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targets/TARGET_Maxim/TARGET_MAX32620/device/system_max32620.c@153:9398a535854b, 2016-12-22 (annotated)

Committer:
fwndz
Date:
Thu Dec 22 05:12:40 2016 +0000
Revision:
153:9398a535854b
Parent:
149:156823d33999 
device target maximize

Who changed what in which revision?

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<> 149:156823d33999 1 /*******************************************************************************
<> 149:156823d33999 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
<> 149:156823d33999 3 *
<> 149:156823d33999 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 149:156823d33999 5 * copy of this software and associated documentation files (the "Software"),
<> 149:156823d33999 6 * to deal in the Software without restriction, including without limitation
<> 149:156823d33999 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 149:156823d33999 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 149:156823d33999 9 * Software is furnished to do so, subject to the following conditions:
<> 149:156823d33999 10 *
<> 149:156823d33999 11 * The above copyright notice and this permission notice shall be included
<> 149:156823d33999 12 * in all copies or substantial portions of the Software.
<> 149:156823d33999 13 *
<> 149:156823d33999 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 149:156823d33999 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 149:156823d33999 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 149:156823d33999 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 149:156823d33999 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 149:156823d33999 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 149:156823d33999 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 149:156823d33999 21 *
<> 149:156823d33999 22 * Except as contained in this notice, the name of Maxim Integrated
<> 149:156823d33999 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 149:156823d33999 24 * Products, Inc. Branding Policy.
<> 149:156823d33999 25 *
<> 149:156823d33999 26 * The mere transfer of this software does not imply any licenses
<> 149:156823d33999 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 149:156823d33999 28 * trademarks, maskwork rights, or any other form of intellectual
<> 149:156823d33999 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 149:156823d33999 30 * ownership rights.
<> 149:156823d33999 31 *******************************************************************************
<> 149:156823d33999 32 */
<> 149:156823d33999 33
<> 149:156823d33999 34 #include "max32620.h"
<> 149:156823d33999 35 #include "clkman_regs.h"
<> 149:156823d33999 36 #include "icc_regs.h"
<> 149:156823d33999 37 #include "pwrseq_regs.h"
<> 149:156823d33999 38 #include "pwrman_regs.h"
<> 149:156823d33999 39 #include "adc_regs.h"
<> 149:156823d33999 40 #include "flc_regs.h"
<> 149:156823d33999 41 #include "trim_regs.h"
<> 149:156823d33999 42 #include "rtc_regs.h"
<> 149:156823d33999 43
<> 149:156823d33999 44 /* SCB CPACR Register Definitions */
<> 149:156823d33999 45 /* Note: Added by Maxim Integrated, as these are missing from CMSIS/Core/Include/core_cm4.h */
<> 149:156823d33999 46 #define SCB_CPACR_CP10_Pos 20 /* SCB CPACR: Coprocessor 10 Position */
<> 149:156823d33999 47 #define SCB_CPACR_CP10_Msk (0x3UL << SCB_CPACR_CP10_Pos) /* SCB CPACR: Coprocessor 10 Mask */
<> 149:156823d33999 48 #define SCB_CPACR_CP11_Pos 22 /* SCB CPACR: Coprocessor 11 Position */
<> 149:156823d33999 49 #define SCB_CPACR_CP11_Msk (0x3UL << SCB_CPACR_CP11_Pos) /* SCB CPACR: Coprocessor 11 Mask */
<> 149:156823d33999 50
<> 149:156823d33999 51 static uint8_t running;
<> 149:156823d33999 52
<> 149:156823d33999 53 // NOTE: Setting the CMSIS SystemCoreClock value to the actual value it will
<> 149:156823d33999 54 // be AFTER SystemInit() runs. This is required so the hal drivers will have
<> 149:156823d33999 55 // the correct value when the DATA sections are initialized.
<> 149:156823d33999 56 uint32_t SystemCoreClock = RO_FREQ / 2;
<> 149:156823d33999 57
<> 149:156823d33999 58 void SystemCoreClockUpdate(void)
<> 149:156823d33999 59 {
<> 149:156823d33999 60 switch ((MXC_CLKMAN->clk_ctrl & MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT) >> MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS) {
<> 149:156823d33999 61
<> 149:156823d33999 62 case MXC_V_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO_DIV_2:
<> 149:156823d33999 63 default:
<> 149:156823d33999 64 SystemCoreClock = RO_FREQ / 2;
<> 149:156823d33999 65 break;
<> 149:156823d33999 66 case MXC_V_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO:
<> 149:156823d33999 67 SystemCoreClock = RO_FREQ;
<> 149:156823d33999 68 break;
<> 149:156823d33999 69 }
<> 149:156823d33999 70 }
<> 149:156823d33999 71
<> 149:156823d33999 72 void Trim_ROAtomic(void)
<> 149:156823d33999 73 {
<> 149:156823d33999 74 uint32_t trim;
<> 149:156823d33999 75
<> 149:156823d33999 76 // Step 1: enable 32KHz RTC
<> 149:156823d33999 77 running = MXC_PWRSEQ->reg0 & MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN;
<> 149:156823d33999 78 MXC_PWRSEQ->reg0 |= MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN;
<> 149:156823d33999 79
<> 149:156823d33999 80 // Step 2: enable RO calibration complete interrupt
<> 149:156823d33999 81 MXC_ADC->intr = (MXC_ADC->intr & 0xFFFF) | MXC_F_ADC_INTR_RO_CAL_DONE_IE;
<> 149:156823d33999 82
<> 149:156823d33999 83 // Step 3: clear RO calibration complete interrupt
<> 149:156823d33999 84 MXC_ADC->intr = (MXC_ADC->intr & 0xFFFF) | MXC_F_ADC_INTR_RO_CAL_DONE_IF;
<> 149:156823d33999 85
<> 149:156823d33999 86 /* Step 4: -- NO LONGER NEEDED / HANDLED BY STARTUP CODE -- */
<> 149:156823d33999 87
<> 149:156823d33999 88 /* Step 5: write initial trim to frequency calibration initial condition register */
<> 149:156823d33999 89 trim = (MXC_PWRSEQ->reg6 & MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF) >> MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF_POS;
<> 149:156823d33999 90 MXC_ADC->ro_cal1 = (MXC_ADC->ro_cal1 & ~MXC_F_ADC_RO_CAL1_TRM_INIT) |
<> 149:156823d33999 91 ((trim << MXC_F_ADC_RO_CAL1_TRM_INIT_POS) & MXC_F_ADC_RO_CAL1_TRM_INIT);
<> 149:156823d33999 92
<> 149:156823d33999 93 // Step 6: load initial trim to active frequency trim register
<> 149:156823d33999 94 MXC_ADC->ro_cal0 |= MXC_F_ADC_RO_CAL0_RO_CAL_LOAD;
<> 149:156823d33999 95
<> 149:156823d33999 96 // Step 7: enable frequency loop to control RO trim
<> 149:156823d33999 97 MXC_ADC->ro_cal0 |= MXC_F_ADC_RO_CAL0_RO_CAL_EN;
<> 149:156823d33999 98
<> 149:156823d33999 99 // Step 8: run frequency calibration in atomic mode
<> 149:156823d33999 100 MXC_ADC->ro_cal0 |= MXC_F_ADC_RO_CAL0_RO_CAL_ATOMIC;
<> 149:156823d33999 101
<> 149:156823d33999 102 // Step 9: waiting for ro_cal_done flag
<> 149:156823d33999 103 while (!(MXC_ADC->intr & MXC_F_ADC_INTR_RO_CAL_DONE_IF));
<> 149:156823d33999 104
<> 149:156823d33999 105 // Step 10: stop frequency calibration
<> 149:156823d33999 106 MXC_ADC->ro_cal0 &= ~MXC_F_ADC_RO_CAL0_RO_CAL_RUN;
<> 149:156823d33999 107
<> 149:156823d33999 108 // Step 11: disable RO calibration complete interrupt
<> 149:156823d33999 109 MXC_ADC->intr = (MXC_ADC->intr & 0xFFFF) & ~MXC_F_ADC_INTR_RO_CAL_DONE_IE;
<> 149:156823d33999 110
<> 149:156823d33999 111 // Step 12: read final frequency trim value
<> 149:156823d33999 112 trim = (MXC_ADC->ro_cal0 & MXC_F_ADC_RO_CAL0_RO_TRM) >> MXC_F_ADC_RO_CAL0_RO_TRM_POS;
<> 149:156823d33999 113
<> 149:156823d33999 114 /* Step 13: write final trim to RO flash trim shadow register */
<> 149:156823d33999 115 MXC_PWRSEQ->reg6 = (MXC_PWRSEQ->reg6 & ~MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF) |
<> 149:156823d33999 116 ((trim << MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF_POS) & MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF);
<> 149:156823d33999 117
<> 149:156823d33999 118 // Step 14: restore RTC status
<> 149:156823d33999 119 if (!running) {
<> 149:156823d33999 120 MXC_PWRSEQ->reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN;
<> 149:156823d33999 121 }
<> 149:156823d33999 122
<> 149:156823d33999 123 // Step 15: disable frequency loop to control RO trim
<> 149:156823d33999 124 MXC_ADC->ro_cal0 &= ~MXC_F_ADC_RO_CAL0_RO_CAL_EN;
<> 149:156823d33999 125 }
<> 149:156823d33999 126
<> 149:156823d33999 127 static void ICC_Enable(void)
<> 149:156823d33999 128 {
<> 149:156823d33999 129 /* Invalidate cache and wait until ready */
<> 149:156823d33999 130 MXC_ICC->invdt_all = 1;
<> 149:156823d33999 131 while (!(MXC_ICC->ctrl_stat & MXC_F_ICC_CTRL_STAT_READY));
<> 149:156823d33999 132
<> 149:156823d33999 133 /* Enable cache */
<> 149:156823d33999 134 MXC_ICC->ctrl_stat |= MXC_F_ICC_CTRL_STAT_ENABLE;
<> 149:156823d33999 135
<> 149:156823d33999 136 /* Must invalidate a second time for proper use */
<> 149:156823d33999 137 MXC_ICC->invdt_all = 1;
<> 149:156823d33999 138 }
<> 149:156823d33999 139
<> 149:156823d33999 140 // This function to be implemented by the hal
<> 149:156823d33999 141 extern void low_level_init(void);
<> 149:156823d33999 142
<> 149:156823d33999 143 // Note: This is called before C run-time initialization. Do not use any initialized variables.
<> 149:156823d33999 144 void SystemInit(void)
<> 149:156823d33999 145 {
<> 149:156823d33999 146 ICC_Enable();
<> 149:156823d33999 147
<> 149:156823d33999 148 low_level_init();
<> 149:156823d33999 149
<> 149:156823d33999 150 // Select 48MHz ring oscillator as clock source
<> 149:156823d33999 151 uint32_t reg = MXC_CLKMAN->clk_ctrl;
<> 149:156823d33999 152 reg &= ~MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT;
<> 149:156823d33999 153 MXC_CLKMAN->clk_ctrl = reg;
<> 149:156823d33999 154
<> 149:156823d33999 155 // Copy trim information from shadow registers into power manager registers
<> 149:156823d33999 156 // NOTE: Checks have been added to prevent bad/missing trim values from being loaded
<> 149:156823d33999 157 if ((MXC_FLC->ctrl & MXC_F_FLC_CTRL_INFO_BLOCK_VALID) &&
<> 149:156823d33999 158 (MXC_TRIM->for_pwr_reg5 != 0xffffffff) &&
<> 149:156823d33999 159 (MXC_TRIM->for_pwr_reg6 != 0xffffffff)) {
<> 149:156823d33999 160 MXC_PWRSEQ->reg5 = MXC_TRIM->for_pwr_reg5;
<> 149:156823d33999 161 MXC_PWRSEQ->reg6 = MXC_TRIM->for_pwr_reg6;
<> 149:156823d33999 162 } else {
<> 149:156823d33999 163 /* No valid info block, use some reasonable defaults */
<> 149:156823d33999 164 MXC_PWRSEQ->reg6 &= ~MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF;
<> 149:156823d33999 165 MXC_PWRSEQ->reg6 |= (0x1e0 << MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF_POS);
<> 149:156823d33999 166 }
<> 149:156823d33999 167
<> 149:156823d33999 168 // Use ASYNC flags, and ASYNC Reset of flags to improve synchronization speed
<> 149:156823d33999 169 // between RTC and ARM core. Also avoid delayed RTC interrupts after lp wake.
<> 149:156823d33999 170 MXC_RTCTMR->ctrl |= (MXC_F_RTC_CTRL_USE_ASYNC_FLAGS | MXC_F_RTC_CTRL_AGGRESSIVE_RST);
<> 149:156823d33999 171
<> 149:156823d33999 172 /* Clear the GPIO WUD event if not waking up from LP0 */
<> 149:156823d33999 173 /* this is necessary because WUD flops come up in undetermined state out of POR or SRST*/
<> 149:156823d33999 174 if (MXC_PWRSEQ->reg0 & MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT || !(MXC_PWRMAN->pwr_rst_ctrl & MXC_F_PWRMAN_PWR_RST_CTRL_POR)) {
<> 149:156823d33999 175 /* Clear GPIO WUD event and configuration registers, globally */
<> 149:156823d33999 176 MXC_PWRSEQ->reg1 |= (MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH | MXC_F_PWRSEQ_REG1_PWR_CLR_IO_CFG_LATCH);
<> 149:156823d33999 177 MXC_PWRSEQ->reg1 &= ~(MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH | MXC_F_PWRSEQ_REG1_PWR_CLR_IO_CFG_LATCH);
<> 149:156823d33999 178 } else {
<> 149:156823d33999 179 /* Unfreeze the GPIO by clearing MBUS_GATE, when returning from LP0 */
<> 149:156823d33999 180 MXC_PWRSEQ->reg1 &= ~(MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE);
<> 149:156823d33999 181 }
<> 149:156823d33999 182
<> 149:156823d33999 183 // Turn on retention regulator
<> 149:156823d33999 184 MXC_PWRSEQ->reg0 |= (MXC_F_PWRSEQ_REG0_PWR_RETREGEN_RUN | MXC_F_PWRSEQ_REG0_PWR_RETREGEN_SLP);
<> 149:156823d33999 185
<> 149:156823d33999 186 // Clear all unused wakeup sources
<> 149:156823d33999 187 // Beware! Do not change any flag not mentioned here, as they will gate important power sequencer signals
<> 149:156823d33999 188 MXC_PWRSEQ->msk_flags &= ~(MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP |
<> 149:156823d33999 189 MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP);
<> 149:156823d33999 190
<> 149:156823d33999 191 // RTC sources are inverted, so a 1 will disable them
<> 149:156823d33999 192 MXC_PWRSEQ->msk_flags |= (MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1 |
<> 149:156823d33999 193 MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP);
<> 149:156823d33999 194
<> 149:156823d33999 195 /* Enable RTOS Mode: Enable 32kHz clock synchronizer to SysTick external clock input */
<> 149:156823d33999 196 MXC_CLKMAN->clk_ctrl |= MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE;
<> 149:156823d33999 197
<> 149:156823d33999 198 // Enable real-time clock during sleep mode
<> 149:156823d33999 199 MXC_PWRSEQ->reg0 |= (MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN | MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP);
<> 149:156823d33999 200
<> 149:156823d33999 201 #if (__FPU_PRESENT == 1)
<> 149:156823d33999 202 /* Enable FPU on Cortex-M4, which occupies coprocessor slots 10 & 11 */
<> 149:156823d33999 203 /* Grant full access, per "Table B3-24 CPACR bit assignments". */
<> 149:156823d33999 204 /* DDI0403D "ARMv7-M Architecture Reference Manual" */
<> 149:156823d33999 205 SCB->CPACR |= SCB_CPACR_CP10_Msk | SCB_CPACR_CP11_Msk;
<> 149:156823d33999 206 __DSB();
<> 149:156823d33999 207 __ISB();
<> 149:156823d33999 208 #endif
<> 149:156823d33999 209
<> 149:156823d33999 210 // Trim ring oscillator
<> 149:156823d33999 211 Trim_ROAtomic();
<> 149:156823d33999 212 }