Fawwaz Nadzmy / mbed-STM

mbed library sources. Supersedes mbed-src.

Fork of mbed-dev by mbed official

targets/TARGET_Freescale/TARGET_K20XX/sleep.c@153:9398a535854b, 2016-12-22 (annotated)

Committer:
fwndz
Date:
Thu Dec 22 05:12:40 2016 +0000
Revision:
153:9398a535854b
Parent:
149:156823d33999 
device target maximize

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* mbed Microcontroller Library
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2006-2015 ARM Limited
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Licensed under the Apache License, Version 2.0 (the "License");
<> 144:ef7eb2e8f9f7 5 * you may not use this file except in compliance with the License.
<> 144:ef7eb2e8f9f7 6 * You may obtain a copy of the License at
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * http://www.apache.org/licenses/LICENSE-2.0
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Unless required by applicable law or agreed to in writing, software
<> 144:ef7eb2e8f9f7 11 * distributed under the License is distributed on an "AS IS" BASIS,
<> 144:ef7eb2e8f9f7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 144:ef7eb2e8f9f7 13 * See the License for the specific language governing permissions and
<> 144:ef7eb2e8f9f7 14 * limitations under the License.
<> 144:ef7eb2e8f9f7 15 */
<> 144:ef7eb2e8f9f7 16 #include "sleep_api.h"
<> 144:ef7eb2e8f9f7 17 #include "cmsis.h"
<> 144:ef7eb2e8f9f7 18
<> 144:ef7eb2e8f9f7 19 //Normal wait mode
<> 144:ef7eb2e8f9f7 20 void sleep(void)
<> 144:ef7eb2e8f9f7 21 {
<> 144:ef7eb2e8f9f7 22 SMC->PMPROT = SMC_PMPROT_AVLLS_MASK | SMC_PMPROT_ALLS_MASK | SMC_PMPROT_AVLP_MASK;
<> 144:ef7eb2e8f9f7 23
<> 144:ef7eb2e8f9f7 24 //Normal sleep mode for ARM core:
<> 144:ef7eb2e8f9f7 25 SCB->SCR = 0;
<> 144:ef7eb2e8f9f7 26 __WFI();
<> 144:ef7eb2e8f9f7 27 }
<> 144:ef7eb2e8f9f7 28
<> 144:ef7eb2e8f9f7 29 //Very low-power stop mode
<> 144:ef7eb2e8f9f7 30 void deepsleep(void)
<> 144:ef7eb2e8f9f7 31 {
<> 144:ef7eb2e8f9f7 32 //Check if ADC is enabled and HS mode is set, if yes disable it (lowers power consumption by 60uA)
<> 144:ef7eb2e8f9f7 33 uint8_t ADC_HSC = 0;
<> 144:ef7eb2e8f9f7 34 if (SIM->SCGC6 & SIM_SCGC6_ADC0_MASK) {
<> 144:ef7eb2e8f9f7 35 if (ADC0->CFG2 & ADC_CFG2_ADHSC_MASK) {
<> 144:ef7eb2e8f9f7 36 ADC_HSC = 1;
<> 144:ef7eb2e8f9f7 37 ADC0->CFG2 &= ~(ADC_CFG2_ADHSC_MASK);
<> 144:ef7eb2e8f9f7 38 }
<> 144:ef7eb2e8f9f7 39 }
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 //Check if PLL/FLL is enabled:
<> 144:ef7eb2e8f9f7 42 uint32_t PLL_FLL_en = (MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(0);
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 SMC->PMPROT = SMC_PMPROT_AVLLS_MASK | SMC_PMPROT_ALLS_MASK | SMC_PMPROT_AVLP_MASK;
<> 144:ef7eb2e8f9f7 45 SMC->PMCTRL = SMC_PMCTRL_STOPM(2);
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 //Deep sleep for ARM core:
<> 144:ef7eb2e8f9f7 48 SCB->SCR = 1<<SCB_SCR_SLEEPDEEP_Pos;
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 __WFI();
<> 144:ef7eb2e8f9f7 51 //Switch back to PLL as clock source if needed
<> 144:ef7eb2e8f9f7 52 //The interrupt that woke up the device will run at reduced speed
<> 144:ef7eb2e8f9f7 53 if (PLL_FLL_en) {
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 #if defined (TARGET_K20D50M)
<> 144:ef7eb2e8f9f7 56 if (MCG->C6 & (1<<MCG_C6_PLLS_SHIFT) != 0) /* If PLL */
<> 144:ef7eb2e8f9f7 57 while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U); /* Wait until locked */
<> 144:ef7eb2e8f9f7 58 MCG->C1 &= ~MCG_C1_CLKS_MASK;
<> 144:ef7eb2e8f9f7 59 #else
<> 144:ef7eb2e8f9f7 60 // MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0
<> 144:ef7eb2e8f9f7 61 MCG->C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3) | MCG_C1_IRCLKEN_MASK;
<> 144:ef7eb2e8f9f7 62 // MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0
<> 144:ef7eb2e8f9f7 63 MCG->C6 = MCG_C6_VDIV0(0);
<> 144:ef7eb2e8f9f7 64 while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { } // Check that the oscillator is running
<> 144:ef7eb2e8f9f7 65 while((MCG->S & 0x0Cu) != 0x08u) { } // Wait until external reference clock is selected as MCG output
<> 144:ef7eb2e8f9f7 66 // MCG->C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=3
<> 144:ef7eb2e8f9f7 67 MCG->C5 = MCG_C5_PRDIV0(5);
<> 144:ef7eb2e8f9f7 68 // MCG->C6: LOLIE=0,PLLS=1,CME=0,VDIV0=3
<> 144:ef7eb2e8f9f7 69 MCG->C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV0(3);
<> 144:ef7eb2e8f9f7 70 while((MCG->S & 0x0Cu) != 0x08u) { } // Wait until external reference clock is selected as MCG output
<> 144:ef7eb2e8f9f7 71 while((MCG->S & MCG_S_PLLST_MASK) == 0u) { } // Wait until the source of the PLLS clock has switched to the PLL
<> 144:ef7eb2e8f9f7 72 while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } // Wait until locked
<> 144:ef7eb2e8f9f7 73 // MCG->C1: CLKS=0,FRDIV=2,IREFS=0,IRCLKEN=1,IREFSTEN=0
<> 144:ef7eb2e8f9f7 74 MCG->C1 = MCG_C1_FRDIV(2) | MCG_C1_IRCLKEN_MASK;;
<> 144:ef7eb2e8f9f7 75 while((MCG->S & 0x0Cu) != 0x0Cu) { } // Wait until output of the PLL is selected
<> 144:ef7eb2e8f9f7 76 while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } // Wait until locked
<> 144:ef7eb2e8f9f7 77 #endif
<> 144:ef7eb2e8f9f7 78 }
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80 if (ADC_HSC) {
<> 144:ef7eb2e8f9f7 81 ADC0->CFG2 |= (ADC_CFG2_ADHSC_MASK);
<> 144:ef7eb2e8f9f7 82 }
<> 144:ef7eb2e8f9f7 83 }