Fawwaz Nadzmy / mbed-STM

mbed library sources. Supersedes mbed-src.

Fork of mbed-dev by mbed official

targets/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/PeripheralNames.h@153:9398a535854b, 2016-12-22 (annotated)

Committer:
fwndz
Date:
Thu Dec 22 05:12:40 2016 +0000
Revision:
153:9398a535854b
Parent:
149:156823d33999 
device target maximize

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* mbed Microcontroller Library
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2006-2015 ARM Limited
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Licensed under the Apache License, Version 2.0 (the "License");
<> 144:ef7eb2e8f9f7 5 * you may not use this file except in compliance with the License.
<> 144:ef7eb2e8f9f7 6 * You may obtain a copy of the License at
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * http://www.apache.org/licenses/LICENSE-2.0
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Unless required by applicable law or agreed to in writing, software
<> 144:ef7eb2e8f9f7 11 * distributed under the License is distributed on an "AS IS" BASIS,
<> 144:ef7eb2e8f9f7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 144:ef7eb2e8f9f7 13 * See the License for the specific language governing permissions and
<> 144:ef7eb2e8f9f7 14 * limitations under the License.
<> 144:ef7eb2e8f9f7 15 */
<> 144:ef7eb2e8f9f7 16 #ifndef MBED_PERIPHERALNAMES_H
<> 144:ef7eb2e8f9f7 17 #define MBED_PERIPHERALNAMES_H
<> 144:ef7eb2e8f9f7 18
<> 144:ef7eb2e8f9f7 19 #include "cmsis.h"
<> 144:ef7eb2e8f9f7 20
<> 144:ef7eb2e8f9f7 21 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 22 extern "C" {
<> 144:ef7eb2e8f9f7 23 #endif
<> 144:ef7eb2e8f9f7 24
<> 144:ef7eb2e8f9f7 25 typedef enum {
<> 144:ef7eb2e8f9f7 26 UART_0 = (int)UART0_BASE,
<> 144:ef7eb2e8f9f7 27 UART_1 = (int)UART1_BASE,
<> 144:ef7eb2e8f9f7 28 UART_2 = (int)UART2_BASE
<> 144:ef7eb2e8f9f7 29 } UARTName;
<> 144:ef7eb2e8f9f7 30 #define STDIO_UART_TX USBTX
<> 144:ef7eb2e8f9f7 31 #define STDIO_UART_RX USBRX
<> 144:ef7eb2e8f9f7 32 #define STDIO_UART UART_0
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 typedef enum {
<> 144:ef7eb2e8f9f7 35 I2C_0 = (int)I2C0_BASE,
<> 144:ef7eb2e8f9f7 36 I2C_1 = (int)I2C1_BASE,
<> 144:ef7eb2e8f9f7 37 } I2CName;
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39 #define TPM_SHIFT 8
<> 144:ef7eb2e8f9f7 40 typedef enum {
<> 144:ef7eb2e8f9f7 41 PWM_1 = (0 << TPM_SHIFT) | (0), // FTM0 CH0
<> 144:ef7eb2e8f9f7 42 PWM_2 = (0 << TPM_SHIFT) | (1), // FTM0 CH1
<> 144:ef7eb2e8f9f7 43 PWM_3 = (0 << TPM_SHIFT) | (2), // FTM0 CH2
<> 144:ef7eb2e8f9f7 44 PWM_4 = (0 << TPM_SHIFT) | (3), // FTM0 CH3
<> 144:ef7eb2e8f9f7 45 PWM_5 = (0 << TPM_SHIFT) | (4), // FTM0 CH4
<> 144:ef7eb2e8f9f7 46 PWM_6 = (0 << TPM_SHIFT) | (5), // FTM0 CH5
<> 144:ef7eb2e8f9f7 47 PWM_7 = (0 << TPM_SHIFT) | (6), // FTM0 CH6
<> 144:ef7eb2e8f9f7 48 PWM_8 = (0 << TPM_SHIFT) | (7), // FTM0 CH7
<> 144:ef7eb2e8f9f7 49 PWM_9 = (1 << TPM_SHIFT) | (0), // FTM1 CH0
<> 144:ef7eb2e8f9f7 50 PWM_10 = (1 << TPM_SHIFT) | (1), // FTM1 CH1
<> 144:ef7eb2e8f9f7 51 } PWMName;
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 typedef enum {
<> 144:ef7eb2e8f9f7 54 ADC0_SE4b = 4,
<> 144:ef7eb2e8f9f7 55 ADC0_SE5b = 5,
<> 144:ef7eb2e8f9f7 56 ADC0_SE6b = 6,
<> 144:ef7eb2e8f9f7 57 ADC0_SE7b = 7,
<> 144:ef7eb2e8f9f7 58 ADC0_SE8 = 8,
<> 144:ef7eb2e8f9f7 59 ADC0_SE9 = 9,
<> 144:ef7eb2e8f9f7 60 ADC0_SE12 = 12,
<> 144:ef7eb2e8f9f7 61 ADC0_SE13 = 13,
<> 144:ef7eb2e8f9f7 62 ADC0_SE14 = 14,
<> 144:ef7eb2e8f9f7 63 ADC0_SE15 = 15,
<> 144:ef7eb2e8f9f7 64 ADC1_SE4b = 16,
<> 144:ef7eb2e8f9f7 65 ADC1_SE5b = 17,
<> 144:ef7eb2e8f9f7 66 ADC1_SE6b = 18,
<> 144:ef7eb2e8f9f7 67 ADC1_SE7b = 19,
<> 144:ef7eb2e8f9f7 68 } ADCName;
<> 144:ef7eb2e8f9f7 69
<> 144:ef7eb2e8f9f7 70 typedef enum {
<> 144:ef7eb2e8f9f7 71 DAC_0 = 0
<> 144:ef7eb2e8f9f7 72 } DACName;
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74 typedef enum {
<> 144:ef7eb2e8f9f7 75 SPI_0 = (int)SPI0_BASE,
<> 144:ef7eb2e8f9f7 76 SPI_1 = (int)SPI0_BASE,
<> 144:ef7eb2e8f9f7 77 SPI_2 = (int)SPI0_BASE,
<> 144:ef7eb2e8f9f7 78 SPI_3 = (int)SPI0_BASE,
<> 144:ef7eb2e8f9f7 79 SPI_4 = (int)SPI0_BASE,
<> 144:ef7eb2e8f9f7 80 } SPIName;
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 83 }
<> 144:ef7eb2e8f9f7 84 #endif
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 #endif