Fawwaz Nadzmy / mbed-STM

mbed library sources. Supersedes mbed-src.

Fork of mbed-dev by mbed official

cmsis/TOOLCHAIN_IAR/TARGET_CORTEX_A/cache.s@153:9398a535854b, 2016-12-22 (annotated)

Committer:
fwndz
Date:
Thu Dec 22 05:12:40 2016 +0000
Revision:
153:9398a535854b
Parent:
149:156823d33999 
device target maximize

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 66:fdb3f9f9a72f 1 /* Copyright (c) 2009 - 2012 ARM LIMITED
mbed_official 66:fdb3f9f9a72f 2
mbed_official 66:fdb3f9f9a72f 3 All rights reserved.
mbed_official 66:fdb3f9f9a72f 4 Redistribution and use in source and binary forms, with or without
mbed_official 66:fdb3f9f9a72f 5 modification, are permitted provided that the following conditions are met:
mbed_official 66:fdb3f9f9a72f 6 - Redistributions of source code must retain the above copyright
mbed_official 66:fdb3f9f9a72f 7 notice, this list of conditions and the following disclaimer.
mbed_official 66:fdb3f9f9a72f 8 - Redistributions in binary form must reproduce the above copyright
mbed_official 66:fdb3f9f9a72f 9 notice, this list of conditions and the following disclaimer in the
mbed_official 66:fdb3f9f9a72f 10 documentation and/or other materials provided with the distribution.
mbed_official 66:fdb3f9f9a72f 11 - Neither the name of ARM nor the names of its contributors may be used
mbed_official 66:fdb3f9f9a72f 12 to endorse or promote products derived from this software without
mbed_official 66:fdb3f9f9a72f 13 specific prior written permission.
mbed_official 66:fdb3f9f9a72f 14 *
mbed_official 66:fdb3f9f9a72f 15 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 66:fdb3f9f9a72f 16 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 66:fdb3f9f9a72f 17 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
mbed_official 66:fdb3f9f9a72f 18 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
mbed_official 66:fdb3f9f9a72f 19 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
mbed_official 66:fdb3f9f9a72f 20 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
mbed_official 66:fdb3f9f9a72f 21 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mbed_official 66:fdb3f9f9a72f 22 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mbed_official 66:fdb3f9f9a72f 23 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
mbed_official 66:fdb3f9f9a72f 24 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
mbed_official 66:fdb3f9f9a72f 25 POSSIBILITY OF SUCH DAMAGE.
mbed_official 66:fdb3f9f9a72f 26 ---------------------------------------------------------------------------*/
mbed_official 66:fdb3f9f9a72f 27
mbed_official 66:fdb3f9f9a72f 28 /*----------------------------------------------------------------------------
mbed_official 66:fdb3f9f9a72f 29 * Functions
mbed_official 66:fdb3f9f9a72f 30 *---------------------------------------------------------------------------*/
mbed_official 66:fdb3f9f9a72f 31 SECTION `.text`:CODE:NOROOT(2)
mbed_official 66:fdb3f9f9a72f 32 arm
mbed_official 66:fdb3f9f9a72f 33 PUBLIC __v7_all_cache
mbed_official 66:fdb3f9f9a72f 34 /*
mbed_official 66:fdb3f9f9a72f 35 * __STATIC_ASM void __v7_all_cache(uint32_t op) {
mbed_official 66:fdb3f9f9a72f 36 */
mbed_official 66:fdb3f9f9a72f 37
mbed_official 66:fdb3f9f9a72f 38 __v7_all_cache:
mbed_official 66:fdb3f9f9a72f 39
mbed_official 66:fdb3f9f9a72f 40
mbed_official 66:fdb3f9f9a72f 41 PUSH {R4-R11}
mbed_official 66:fdb3f9f9a72f 42
mbed_official 66:fdb3f9f9a72f 43 MRC p15, 1, R6, c0, c0, 1 /* Read CLIDR */
mbed_official 66:fdb3f9f9a72f 44 ANDS R3, R6, #0x07000000 /* Extract coherency level */
mbed_official 66:fdb3f9f9a72f 45 MOV R3, R3, LSR #23 /* Total cache levels << 1 */
mbed_official 66:fdb3f9f9a72f 46 BEQ Finished /* If 0, no need to clean */
mbed_official 66:fdb3f9f9a72f 47
mbed_official 66:fdb3f9f9a72f 48 MOV R10, #0 /* R10 holds current cache level << 1 */
mbed_official 66:fdb3f9f9a72f 49 Loop1: ADD R2, R10, R10, LSR #1 /* R2 holds cache "Set" position */
mbed_official 66:fdb3f9f9a72f 50 MOV R1, R6, LSR R2 /* Bottom 3 bits are the Cache-type for this level */
mbed_official 66:fdb3f9f9a72f 51 AND R1, R1, #7 /* Isolate those lower 3 bits */
mbed_official 66:fdb3f9f9a72f 52 CMP R1, #2
mbed_official 66:fdb3f9f9a72f 53 BLT Skip /* No cache or only instruction cache at this level */
mbed_official 66:fdb3f9f9a72f 54
mbed_official 66:fdb3f9f9a72f 55 MCR p15, 2, R10, c0, c0, 0 /* Write the Cache Size selection register */
mbed_official 66:fdb3f9f9a72f 56 ISB /* ISB to sync the change to the CacheSizeID reg */
mbed_official 66:fdb3f9f9a72f 57 MRC p15, 1, R1, c0, c0, 0 /* Reads current Cache Size ID register */
mbed_official 66:fdb3f9f9a72f 58 AND R2, R1, #7 /* Extract the line length field */
mbed_official 66:fdb3f9f9a72f 59 ADD R2, R2, #4 /* Add 4 for the line length offset (log2 16 bytes) */
mbed_official 66:fdb3f9f9a72f 60 LDR R4, =0x3FF
mbed_official 66:fdb3f9f9a72f 61 ANDS R4, R4, R1, LSR #3 /* R4 is the max number on the way size (right aligned) */
mbed_official 66:fdb3f9f9a72f 62 CLZ R5, R4 /* R5 is the bit position of the way size increment */
mbed_official 66:fdb3f9f9a72f 63 LDR R7, =0x7FFF
mbed_official 66:fdb3f9f9a72f 64 ANDS R7, R7, R1, LSR #13 /* R7 is the max number of the index size (right aligned) */
mbed_official 66:fdb3f9f9a72f 65
mbed_official 66:fdb3f9f9a72f 66 Loop2: MOV R9, R4 /* R9 working copy of the max way size (right aligned) */
mbed_official 66:fdb3f9f9a72f 67
mbed_official 66:fdb3f9f9a72f 68 Loop3: ORR R11, R10, R9, LSL R5 /* Factor in the Way number and cache number into R11 */
mbed_official 66:fdb3f9f9a72f 69 ORR R11, R11, R7, LSL R2 /* Factor in the Set number */
mbed_official 66:fdb3f9f9a72f 70 CMP R0, #0
mbed_official 66:fdb3f9f9a72f 71 BNE Dccsw
mbed_official 66:fdb3f9f9a72f 72 MCR p15, 0, R11, c7, c6, 2 /* DCISW. Invalidate by Set/Way */
mbed_official 66:fdb3f9f9a72f 73 B cont
mbed_official 66:fdb3f9f9a72f 74 Dccsw: CMP R0, #1
mbed_official 66:fdb3f9f9a72f 75 BNE Dccisw
mbed_official 66:fdb3f9f9a72f 76 MCR p15, 0, R11, c7, c10, 2 /* DCCSW. Clean by Set/Way */
mbed_official 66:fdb3f9f9a72f 77 B cont
mbed_official 66:fdb3f9f9a72f 78 Dccisw: MCR p15, 0, R11, c7, c14, 2 /* DCCISW, Clean and Invalidate by Set/Way */
mbed_official 66:fdb3f9f9a72f 79 cont: SUBS R9, R9, #1 /* Decrement the Way number */
mbed_official 66:fdb3f9f9a72f 80 BGE Loop3
mbed_official 66:fdb3f9f9a72f 81 SUBS R7, R7, #1 /* Decrement the Set number */
mbed_official 66:fdb3f9f9a72f 82 BGE Loop2
mbed_official 66:fdb3f9f9a72f 83 Skip: ADD R10, R10, #2 /* increment the cache number */
mbed_official 66:fdb3f9f9a72f 84 CMP R3, R10
mbed_official 66:fdb3f9f9a72f 85 BGT Loop1
mbed_official 66:fdb3f9f9a72f 86
mbed_official 66:fdb3f9f9a72f 87 Finished:
mbed_official 66:fdb3f9f9a72f 88 DSB
mbed_official 66:fdb3f9f9a72f 89 POP {R4-R11}
mbed_official 66:fdb3f9f9a72f 90 BX lr
mbed_official 66:fdb3f9f9a72f 91
mbed_official 66:fdb3f9f9a72f 92
mbed_official 66:fdb3f9f9a72f 93 END
mbed_official 66:fdb3f9f9a72f 94 /*----------------------------------------------------------------------------
mbed_official 66:fdb3f9f9a72f 95 * end of file
mbed_official 66:fdb3f9f9a72f 96 *---------------------------------------------------------------------------*/
mbed_official 66:fdb3f9f9a72f 97