Fawwaz Nadzmy / mbed-STM

mbed library sources. Supersedes mbed-src.

Fork of mbed-dev by mbed official

targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_rcc.c@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /**
<> 149:156823d33999 2 ******************************************************************************
<> 149:156823d33999 3 * @file stm32l1xx_ll_rcc.c
<> 149:156823d33999 4 * @author MCD Application Team
<> 149:156823d33999 5 * @version V1.2.0
<> 149:156823d33999 6 * @date 01-July-2016
<> 149:156823d33999 7 * @brief RCC LL module driver.
<> 149:156823d33999 8 ******************************************************************************
<> 149:156823d33999 9 * @attention
<> 149:156823d33999 10 *
<> 149:156823d33999 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 149:156823d33999 12 *
<> 149:156823d33999 13 * Redistribution and use in source and binary forms, with or without modification,
<> 149:156823d33999 14 * are permitted provided that the following conditions are met:
<> 149:156823d33999 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 149:156823d33999 16 * this list of conditions and the following disclaimer.
<> 149:156823d33999 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 149:156823d33999 18 * this list of conditions and the following disclaimer in the documentation
<> 149:156823d33999 19 * and/or other materials provided with the distribution.
<> 149:156823d33999 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 149:156823d33999 21 * may be used to endorse or promote products derived from this software
<> 149:156823d33999 22 * without specific prior written permission.
<> 149:156823d33999 23 *
<> 149:156823d33999 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 149:156823d33999 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 149:156823d33999 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 149:156823d33999 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 149:156823d33999 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 149:156823d33999 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 149:156823d33999 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 149:156823d33999 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 149:156823d33999 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 149:156823d33999 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 149:156823d33999 34 *
<> 149:156823d33999 35 ******************************************************************************
<> 149:156823d33999 36 */
<> 149:156823d33999 37 #if defined(USE_FULL_LL_DRIVER)
<> 149:156823d33999 38
<> 149:156823d33999 39 /* Includes ------------------------------------------------------------------*/
<> 149:156823d33999 40 #include "stm32l1xx_ll_rcc.h"
<> 149:156823d33999 41 /** @addtogroup STM32L1xx_LL_Driver
<> 149:156823d33999 42 * @{
<> 149:156823d33999 43 */
<> 149:156823d33999 44
<> 149:156823d33999 45 #if defined(RCC)
<> 149:156823d33999 46
<> 149:156823d33999 47 /** @defgroup RCC_LL RCC
<> 149:156823d33999 48 * @{
<> 149:156823d33999 49 */
<> 149:156823d33999 50
<> 149:156823d33999 51 /* Private types -------------------------------------------------------------*/
<> 149:156823d33999 52 /* Private variables ---------------------------------------------------------*/
<> 149:156823d33999 53
<> 149:156823d33999 54 /* Private constants ---------------------------------------------------------*/
<> 149:156823d33999 55 /* Private macros ------------------------------------------------------------*/
<> 149:156823d33999 56 /* Private function prototypes -----------------------------------------------*/
<> 149:156823d33999 57 /** @defgroup RCC_LL_Private_Functions RCC Private functions
<> 149:156823d33999 58 * @{
<> 149:156823d33999 59 */
<> 149:156823d33999 60 uint32_t RCC_GetSystemClockFreq(void);
<> 149:156823d33999 61 uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
<> 149:156823d33999 62 uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
<> 149:156823d33999 63 uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
<> 149:156823d33999 64 uint32_t RCC_PLL_GetFreqDomain_SYS(void);
<> 149:156823d33999 65 /**
<> 149:156823d33999 66 * @}
<> 149:156823d33999 67 */
<> 149:156823d33999 68
<> 149:156823d33999 69
<> 149:156823d33999 70 /* Exported functions --------------------------------------------------------*/
<> 149:156823d33999 71 /** @addtogroup RCC_LL_Exported_Functions
<> 149:156823d33999 72 * @{
<> 149:156823d33999 73 */
<> 149:156823d33999 74
<> 149:156823d33999 75 /** @addtogroup RCC_LL_EF_Init
<> 149:156823d33999 76 * @{
<> 149:156823d33999 77 */
<> 149:156823d33999 78
<> 149:156823d33999 79 /**
<> 149:156823d33999 80 * @brief Reset the RCC clock configuration to the default reset state.
<> 149:156823d33999 81 * @note The default reset state of the clock configuration is given below:
<> 149:156823d33999 82 * - MSI ON and used as system clock source
<> 149:156823d33999 83 * - HSE, HSI and PLL OFF
<> 149:156823d33999 84 * - AHB, APB1 and APB2 prescaler set to 1.
<> 149:156823d33999 85 * - CSS, MCO OFF
<> 149:156823d33999 86 * - All interrupts disabled
<> 149:156823d33999 87 * @note This function doesn't modify the configuration of the
<> 149:156823d33999 88 * - Peripheral clocks
<> 149:156823d33999 89 * - LSI, LSE and RTC clocks
<> 149:156823d33999 90 * @retval An ErrorStatus enumeration value:
<> 149:156823d33999 91 * - SUCCESS: RCC registers are de-initialized
<> 149:156823d33999 92 * - ERROR: not applicable
<> 149:156823d33999 93 */
<> 149:156823d33999 94 ErrorStatus LL_RCC_DeInit(void)
<> 149:156823d33999 95 {
<> 149:156823d33999 96 uint32_t vl_mask = 0U;
<> 149:156823d33999 97
<> 149:156823d33999 98 /* Set MSION bit */
<> 149:156823d33999 99 LL_RCC_MSI_Enable();
<> 149:156823d33999 100
<> 149:156823d33999 101 /* Insure MSIRDY bit is set before writing default MSIRANGE value */
<> 149:156823d33999 102 while (LL_RCC_MSI_IsReady() == 0U)
<> 149:156823d33999 103 {
<> 149:156823d33999 104 __NOP();
<> 149:156823d33999 105 }
<> 149:156823d33999 106
<> 149:156823d33999 107 /* Set MSIRANGE default value */
<> 149:156823d33999 108 LL_RCC_MSI_SetRange(LL_RCC_MSIRANGE_5);
<> 149:156823d33999 109 /* Set MSITRIM bits to the reset value*/
<> 149:156823d33999 110 LL_RCC_MSI_SetCalibTrimming(0U);
<> 149:156823d33999 111
<> 149:156823d33999 112 /* Set HSITRIM bits to the reset value*/
<> 149:156823d33999 113 LL_RCC_HSI_SetCalibTrimming(0x10U);
<> 149:156823d33999 114
<> 149:156823d33999 115 /* Reset SW, HPRE, PPRE and MCOSEL bits */
<> 149:156823d33999 116 vl_mask = 0xFFFFFFFFU;
<> 149:156823d33999 117 CLEAR_BIT(vl_mask, (RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE1 | RCC_CFGR_PPRE2 | RCC_CFGR_MCOSEL));
<> 149:156823d33999 118 LL_RCC_WriteReg(CFGR, vl_mask);
<> 149:156823d33999 119
<> 149:156823d33999 120 /* Reset HSION, HSEON, CSSON, PLLON bits */
<> 149:156823d33999 121 vl_mask = 0xFFFFFFFFU;
<> 149:156823d33999 122 CLEAR_BIT(vl_mask, (RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_HSEON | RCC_CR_HSION));
<> 149:156823d33999 123 LL_RCC_WriteReg(CR, vl_mask);
<> 149:156823d33999 124
<> 149:156823d33999 125 /* Reset HSEBYP bit */
<> 149:156823d33999 126 LL_RCC_HSE_DisableBypass();
<> 149:156823d33999 127
<> 149:156823d33999 128 /* Reset CFGR register */
<> 149:156823d33999 129 LL_RCC_WriteReg(CFGR, 0x00000000U);
<> 149:156823d33999 130
<> 149:156823d33999 131
<> 149:156823d33999 132 /* Clear pending flags */
<> 149:156823d33999 133 #if defined(RCC_LSECSS_SUPPORT)
<> 149:156823d33999 134 vl_mask = (LL_RCC_CIR_LSIRDYC | LL_RCC_CIR_LSERDYC | LL_RCC_CIR_HSIRDYC | LL_RCC_CIR_HSERDYC | LL_RCC_CIR_PLLRDYC | LL_RCC_CIR_MSIRDYC | LL_RCC_CIR_LSECSSC | LL_RCC_CIR_CSSC);
<> 149:156823d33999 135 #else
<> 149:156823d33999 136 vl_mask = (LL_RCC_CIR_LSIRDYC | LL_RCC_CIR_LSERDYC | LL_RCC_CIR_HSIRDYC | LL_RCC_CIR_HSERDYC | LL_RCC_CIR_PLLRDYC | LL_RCC_CIR_MSIRDYC | LL_RCC_CIR_CSSC);
<> 149:156823d33999 137 #endif /* RCC_LSECSS_SUPPORT */
<> 149:156823d33999 138 SET_BIT(RCC->CIR, vl_mask);
<> 149:156823d33999 139
<> 149:156823d33999 140 /* Disable all interrupts */
<> 149:156823d33999 141 LL_RCC_WriteReg(CIR, 0x00000000U);
<> 149:156823d33999 142
<> 149:156823d33999 143 return SUCCESS;
<> 149:156823d33999 144 }
<> 149:156823d33999 145
<> 149:156823d33999 146 /**
<> 149:156823d33999 147 * @}
<> 149:156823d33999 148 */
<> 149:156823d33999 149
<> 149:156823d33999 150 /** @addtogroup RCC_LL_EF_Get_Freq
<> 149:156823d33999 151 * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
<> 149:156823d33999 152 * and different peripheral clocks available on the device.
<> 149:156823d33999 153 * @note If SYSCLK source is MSI, function returns values based on MSI clock(*)
<> 149:156823d33999 154 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
<> 149:156823d33999 155 * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
<> 149:156823d33999 156 * @note If SYSCLK source is PLL, function returns values based on
<> 149:156823d33999 157 * HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
<> 149:156823d33999 158 * @note (*) MSI clock depends on the selected MSI range but the real value
<> 149:156823d33999 159 * may vary depending on the variations in voltage and temperature.
<> 149:156823d33999 160 * @note (**) HSI_VALUE is a defined constant but the real value may vary
<> 149:156823d33999 161 * depending on the variations in voltage and temperature.
<> 149:156823d33999 162 * @note (***) HSE_VALUE is a defined constant, user has to ensure that
<> 149:156823d33999 163 * HSE_VALUE is same as the real frequency of the crystal used.
<> 149:156823d33999 164 * Otherwise, this function may have wrong result.
<> 149:156823d33999 165 * @note The result of this function could be incorrect when using fractional
<> 149:156823d33999 166 * value for HSE crystal.
<> 149:156823d33999 167 * @note This function can be used by the user application to compute the
<> 149:156823d33999 168 * baud-rate for the communication peripherals or configure other parameters.
<> 149:156823d33999 169 * @{
<> 149:156823d33999 170 */
<> 149:156823d33999 171
<> 149:156823d33999 172 /**
<> 149:156823d33999 173 * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
<> 149:156823d33999 174 * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
<> 149:156823d33999 175 * must be called to update structure fields. Otherwise, any
<> 149:156823d33999 176 * configuration based on this function will be incorrect.
<> 149:156823d33999 177 * @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
<> 149:156823d33999 178 * @retval None
<> 149:156823d33999 179 */
<> 149:156823d33999 180 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
<> 149:156823d33999 181 {
<> 149:156823d33999 182 /* Get SYSCLK frequency */
<> 149:156823d33999 183 RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();
<> 149:156823d33999 184
<> 149:156823d33999 185 /* HCLK clock frequency */
<> 149:156823d33999 186 RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);
<> 149:156823d33999 187
<> 149:156823d33999 188 /* PCLK1 clock frequency */
<> 149:156823d33999 189 RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);
<> 149:156823d33999 190
<> 149:156823d33999 191 /* PCLK2 clock frequency */
<> 149:156823d33999 192 RCC_Clocks->PCLK2_Frequency = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency);
<> 149:156823d33999 193 }
<> 149:156823d33999 194
<> 149:156823d33999 195 /**
<> 149:156823d33999 196 * @}
<> 149:156823d33999 197 */
<> 149:156823d33999 198
<> 149:156823d33999 199 /**
<> 149:156823d33999 200 * @}
<> 149:156823d33999 201 */
<> 149:156823d33999 202
<> 149:156823d33999 203 /** @addtogroup RCC_LL_Private_Functions
<> 149:156823d33999 204 * @{
<> 149:156823d33999 205 */
<> 149:156823d33999 206
<> 149:156823d33999 207 /**
<> 149:156823d33999 208 * @brief Return SYSTEM clock frequency
<> 149:156823d33999 209 * @retval SYSTEM clock frequency (in Hz)
<> 149:156823d33999 210 */
<> 149:156823d33999 211 uint32_t RCC_GetSystemClockFreq(void)
<> 149:156823d33999 212 {
<> 149:156823d33999 213 uint32_t frequency = 0U;
<> 149:156823d33999 214
<> 149:156823d33999 215 /* Get SYSCLK source -------------------------------------------------------*/
<> 149:156823d33999 216 switch (LL_RCC_GetSysClkSource())
<> 149:156823d33999 217 {
<> 149:156823d33999 218 case LL_RCC_SYS_CLKSOURCE_STATUS_MSI: /* MSI used as system clock source */
<> 149:156823d33999 219 frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange());
<> 149:156823d33999 220 break;
<> 149:156823d33999 221
<> 149:156823d33999 222 case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
<> 149:156823d33999 223 frequency = HSI_VALUE;
<> 149:156823d33999 224 break;
<> 149:156823d33999 225
<> 149:156823d33999 226 case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
<> 149:156823d33999 227 frequency = HSE_VALUE;
<> 149:156823d33999 228 break;
<> 149:156823d33999 229
<> 149:156823d33999 230 case LL_RCC_SYS_CLKSOURCE_STATUS_PLL: /* PLL used as system clock source */
<> 149:156823d33999 231 frequency = RCC_PLL_GetFreqDomain_SYS();
<> 149:156823d33999 232 break;
<> 149:156823d33999 233
<> 149:156823d33999 234 default:
<> 149:156823d33999 235 frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange());
<> 149:156823d33999 236 break;
<> 149:156823d33999 237 }
<> 149:156823d33999 238
<> 149:156823d33999 239 return frequency;
<> 149:156823d33999 240 }
<> 149:156823d33999 241
<> 149:156823d33999 242 /**
<> 149:156823d33999 243 * @brief Return HCLK clock frequency
<> 149:156823d33999 244 * @param SYSCLK_Frequency SYSCLK clock frequency
<> 149:156823d33999 245 * @retval HCLK clock frequency (in Hz)
<> 149:156823d33999 246 */
<> 149:156823d33999 247 uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
<> 149:156823d33999 248 {
<> 149:156823d33999 249 /* HCLK clock frequency */
<> 149:156823d33999 250 return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
<> 149:156823d33999 251 }
<> 149:156823d33999 252
<> 149:156823d33999 253 /**
<> 149:156823d33999 254 * @brief Return PCLK1 clock frequency
<> 149:156823d33999 255 * @param HCLK_Frequency HCLK clock frequency
<> 149:156823d33999 256 * @retval PCLK1 clock frequency (in Hz)
<> 149:156823d33999 257 */
<> 149:156823d33999 258 uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
<> 149:156823d33999 259 {
<> 149:156823d33999 260 /* PCLK1 clock frequency */
<> 149:156823d33999 261 return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
<> 149:156823d33999 262 }
<> 149:156823d33999 263
<> 149:156823d33999 264 /**
<> 149:156823d33999 265 * @brief Return PCLK2 clock frequency
<> 149:156823d33999 266 * @param HCLK_Frequency HCLK clock frequency
<> 149:156823d33999 267 * @retval PCLK2 clock frequency (in Hz)
<> 149:156823d33999 268 */
<> 149:156823d33999 269 uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
<> 149:156823d33999 270 {
<> 149:156823d33999 271 /* PCLK2 clock frequency */
<> 149:156823d33999 272 return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
<> 149:156823d33999 273 }
<> 149:156823d33999 274
<> 149:156823d33999 275 /**
<> 149:156823d33999 276 * @brief Return PLL clock frequency used for system domain
<> 149:156823d33999 277 * @retval PLL clock frequency (in Hz)
<> 149:156823d33999 278 */
<> 149:156823d33999 279 uint32_t RCC_PLL_GetFreqDomain_SYS(void)
<> 149:156823d33999 280 {
<> 149:156823d33999 281 uint32_t pllinputfreq = 0U, pllsource = 0U;
<> 149:156823d33999 282
<> 149:156823d33999 283 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL divider) * PLL Multiplicator */
<> 149:156823d33999 284
<> 149:156823d33999 285 /* Get PLL source */
<> 149:156823d33999 286 pllsource = LL_RCC_PLL_GetMainSource();
<> 149:156823d33999 287
<> 149:156823d33999 288 switch (pllsource)
<> 149:156823d33999 289 {
<> 149:156823d33999 290 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
<> 149:156823d33999 291 pllinputfreq = HSI_VALUE;
<> 149:156823d33999 292 break;
<> 149:156823d33999 293
<> 149:156823d33999 294 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
<> 149:156823d33999 295 pllinputfreq = HSE_VALUE;
<> 149:156823d33999 296 break;
<> 149:156823d33999 297
<> 149:156823d33999 298 default:
<> 149:156823d33999 299 pllinputfreq = HSI_VALUE;
<> 149:156823d33999 300 break;
<> 149:156823d33999 301 }
<> 149:156823d33999 302 return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetMultiplicator(), LL_RCC_PLL_GetDivider());
<> 149:156823d33999 303 }
<> 149:156823d33999 304 /**
<> 149:156823d33999 305 * @}
<> 149:156823d33999 306 */
<> 149:156823d33999 307
<> 149:156823d33999 308 /**
<> 149:156823d33999 309 * @}
<> 149:156823d33999 310 */
<> 149:156823d33999 311
<> 149:156823d33999 312 #endif /* defined(RCC) */
<> 149:156823d33999 313
<> 149:156823d33999 314 /**
<> 149:156823d33999 315 * @}
<> 149:156823d33999 316 */
<> 149:156823d33999 317
<> 149:156823d33999 318 #endif /* USE_FULL_LL_DRIVER */
<> 149:156823d33999 319
<> 149:156823d33999 320 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/