Fawwaz Nadzmy / mbed-STM

mbed library sources. Supersedes mbed-src.

Fork of mbed-dev by mbed official

targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_dac.h@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /**
<> 149:156823d33999 2 ******************************************************************************
<> 149:156823d33999 3 * @file stm32l1xx_ll_dac.h
<> 149:156823d33999 4 * @author MCD Application Team
<> 149:156823d33999 5 * @version V1.2.0
<> 149:156823d33999 6 * @date 01-July-2016
<> 149:156823d33999 7 * @brief Header file of DAC LL module.
<> 149:156823d33999 8 ******************************************************************************
<> 149:156823d33999 9 * @attention
<> 149:156823d33999 10 *
<> 149:156823d33999 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 149:156823d33999 12 *
<> 149:156823d33999 13 * Redistribution and use in source and binary forms, with or without modification,
<> 149:156823d33999 14 * are permitted provided that the following conditions are met:
<> 149:156823d33999 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 149:156823d33999 16 * this list of conditions and the following disclaimer.
<> 149:156823d33999 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 149:156823d33999 18 * this list of conditions and the following disclaimer in the documentation
<> 149:156823d33999 19 * and/or other materials provided with the distribution.
<> 149:156823d33999 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 149:156823d33999 21 * may be used to endorse or promote products derived from this software
<> 149:156823d33999 22 * without specific prior written permission.
<> 149:156823d33999 23 *
<> 149:156823d33999 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 149:156823d33999 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 149:156823d33999 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 149:156823d33999 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 149:156823d33999 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 149:156823d33999 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 149:156823d33999 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 149:156823d33999 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 149:156823d33999 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 149:156823d33999 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 149:156823d33999 34 *
<> 149:156823d33999 35 ******************************************************************************
<> 149:156823d33999 36 */
<> 149:156823d33999 37
<> 149:156823d33999 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 149:156823d33999 39 #ifndef __STM32L1xx_LL_DAC_H
<> 149:156823d33999 40 #define __STM32L1xx_LL_DAC_H
<> 149:156823d33999 41
<> 149:156823d33999 42 #ifdef __cplusplus
<> 149:156823d33999 43 extern "C" {
<> 149:156823d33999 44 #endif
<> 149:156823d33999 45
<> 149:156823d33999 46 /* Includes ------------------------------------------------------------------*/
<> 149:156823d33999 47 #include "stm32l1xx.h"
<> 149:156823d33999 48
<> 149:156823d33999 49 /** @addtogroup STM32L1xx_LL_Driver
<> 149:156823d33999 50 * @{
<> 149:156823d33999 51 */
<> 149:156823d33999 52
<> 149:156823d33999 53 #if defined (DAC1)
<> 149:156823d33999 54
<> 149:156823d33999 55 /** @defgroup DAC_LL DAC
<> 149:156823d33999 56 * @{
<> 149:156823d33999 57 */
<> 149:156823d33999 58
<> 149:156823d33999 59 /* Private types -------------------------------------------------------------*/
<> 149:156823d33999 60 /* Private variables ---------------------------------------------------------*/
<> 149:156823d33999 61
<> 149:156823d33999 62 /* Private constants ---------------------------------------------------------*/
<> 149:156823d33999 63 /** @defgroup DAC_LL_Private_Constants DAC Private Constants
<> 149:156823d33999 64 * @{
<> 149:156823d33999 65 */
<> 149:156823d33999 66
<> 149:156823d33999 67 /* Internal masks for DAC channels definition */
<> 149:156823d33999 68 /* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */
<> 149:156823d33999 69 /* - channel bits position into register CR */
<> 149:156823d33999 70 /* - channel bits position into register SWTRIG */
<> 149:156823d33999 71 /* - channel register offset of data holding register DHRx */
<> 149:156823d33999 72 /* - channel register offset of data output register DORx */
<> 149:156823d33999 73 #define DAC_CR_CH1_BITOFFSET ((uint32_t) 0U) /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */
<> 149:156823d33999 74 #define DAC_CR_CH2_BITOFFSET ((uint32_t)16U) /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */
<> 149:156823d33999 75 #define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
<> 149:156823d33999 76
<> 149:156823d33999 77 #define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
<> 149:156823d33999 78 #define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
<> 149:156823d33999 79 #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2)
<> 149:156823d33999 80
<> 149:156823d33999 81 #define DAC_REG_DHR12R1_REGOFFSET ((uint32_t)0x00000000U) /* Register DHR12Rx channel 1 taken as reference */
<> 149:156823d33999 82 #define DAC_REG_DHR12L1_REGOFFSET ((uint32_t)0x00100000U) /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */
<> 149:156823d33999 83 #define DAC_REG_DHR8R1_REGOFFSET ((uint32_t)0x02000000U) /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */
<> 149:156823d33999 84 #define DAC_REG_DHR12R2_REGOFFSET ((uint32_t)0x00030000U) /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */
<> 149:156823d33999 85 #define DAC_REG_DHR12L2_REGOFFSET ((uint32_t)0x00400000U) /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
<> 149:156823d33999 86 #define DAC_REG_DHR8R2_REGOFFSET ((uint32_t)0x05000000U) /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
<> 149:156823d33999 87 #define DAC_REG_DHR12RX_REGOFFSET_MASK ((uint32_t)0x000F0000U)
<> 149:156823d33999 88 #define DAC_REG_DHR12LX_REGOFFSET_MASK ((uint32_t)0x00F00000U)
<> 149:156823d33999 89 #define DAC_REG_DHR8RX_REGOFFSET_MASK ((uint32_t)0x0F000000U)
<> 149:156823d33999 90 #define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
<> 149:156823d33999 91
<> 149:156823d33999 92 #define DAC_REG_DOR1_REGOFFSET ((uint32_t)0x00000000U) /* Register DORx channel 1 taken as reference */
<> 149:156823d33999 93 #define DAC_REG_DOR2_REGOFFSET ((uint32_t)0x10000000U)/* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 28 bits) */
<> 149:156823d33999 94 #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
<> 149:156823d33999 95
<> 149:156823d33999 96 /* DAC registers bits positions */
<> 149:156823d33999 97 #define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS ((uint32_t)16U) /* Value equivalent to POSITION_VAL(DAC_DHR12RD_DACC2DHR) */
<> 149:156823d33999 98 #define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS ((uint32_t)20U) /* Value equivalent to POSITION_VAL(DAC_DHR12LD_DACC2DHR) */
<> 149:156823d33999 99 #define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS ((uint32_t) 8U) /* Value equivalent to POSITION_VAL(DAC_DHR8RD_DACC2DHR) */
<> 149:156823d33999 100
<> 149:156823d33999 101 /* Miscellaneous data */
<> 149:156823d33999 102 #define DAC_DIGITAL_SCALE_12BITS ((uint32_t)4095U) /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */
<> 149:156823d33999 103
<> 149:156823d33999 104 /**
<> 149:156823d33999 105 * @}
<> 149:156823d33999 106 */
<> 149:156823d33999 107
<> 149:156823d33999 108
<> 149:156823d33999 109 /* Private macros ------------------------------------------------------------*/
<> 149:156823d33999 110 /** @defgroup DAC_LL_Private_Macros DAC Private Macros
<> 149:156823d33999 111 * @{
<> 149:156823d33999 112 */
<> 149:156823d33999 113
<> 149:156823d33999 114 /**
<> 149:156823d33999 115 * @brief Driver macro reserved for internal use: isolate bits with the
<> 149:156823d33999 116 * selected mask and shift them to the register LSB
<> 149:156823d33999 117 * (shift mask on register position bit 0).
<> 149:156823d33999 118 * @param __BITS__ Bits in register 32 bits
<> 149:156823d33999 119 * @param __MASK__ Mask in register 32 bits
<> 149:156823d33999 120 * @retval Bits in register 32 bits
<> 149:156823d33999 121 */
<> 149:156823d33999 122 #define __DAC_MASK_SHIFT(__BITS__, __MASK__) \
<> 149:156823d33999 123 (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
<> 149:156823d33999 124
<> 149:156823d33999 125 /**
<> 149:156823d33999 126 * @brief Driver macro reserved for internal use: set a pointer to
<> 149:156823d33999 127 * a register from a register basis from which an offset
<> 149:156823d33999 128 * is applied.
<> 149:156823d33999 129 * @param __REG__ Register basis from which the offset is applied.
<> 149:156823d33999 130 * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
<> 149:156823d33999 131 * @retval Pointer to register address
<> 149:156823d33999 132 */
<> 149:156823d33999 133 #define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
<> 149:156823d33999 134 ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
<> 149:156823d33999 135
<> 149:156823d33999 136 /**
<> 149:156823d33999 137 * @}
<> 149:156823d33999 138 */
<> 149:156823d33999 139
<> 149:156823d33999 140
<> 149:156823d33999 141 /* Exported types ------------------------------------------------------------*/
<> 149:156823d33999 142 #if defined(USE_FULL_LL_DRIVER)
<> 149:156823d33999 143 /** @defgroup DAC_LL_ES_INIT DAC Exported Init structure
<> 149:156823d33999 144 * @{
<> 149:156823d33999 145 */
<> 149:156823d33999 146
<> 149:156823d33999 147 /**
<> 149:156823d33999 148 * @brief Structure definition of some features of DAC instance.
<> 149:156823d33999 149 */
<> 149:156823d33999 150 typedef struct
<> 149:156823d33999 151 {
<> 149:156823d33999 152 uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external IP (timer event, external interrupt line).
<> 149:156823d33999 153 This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
<> 149:156823d33999 154
<> 149:156823d33999 155 This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource(). */
<> 149:156823d33999 156
<> 149:156823d33999 157 uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel.
<> 149:156823d33999 158 This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
<> 149:156823d33999 159
<> 149:156823d33999 160 This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveAutoGeneration(). */
<> 149:156823d33999 161
<> 149:156823d33999 162 uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel.
<> 149:156823d33999 163 If waveform automatic generation mode is set to noise, this parameter can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
<> 149:156823d33999 164 If waveform automatic generation mode is set to triangle, this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
<> 149:156823d33999 165 @note If waveform automatic generation mode is disabled, this parameter is discarded.
<> 149:156823d33999 166
<> 149:156823d33999 167 This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveNoiseLFSR() or @ref LL_DAC_SetWaveTriangleAmplitude(), depending on the wave automatic generation selected. */
<> 149:156823d33999 168
<> 149:156823d33999 169 uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel.
<> 149:156823d33999 170 This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
<> 149:156823d33999 171
<> 149:156823d33999 172 This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputBuffer(). */
<> 149:156823d33999 173
<> 149:156823d33999 174 } LL_DAC_InitTypeDef;
<> 149:156823d33999 175
<> 149:156823d33999 176 /**
<> 149:156823d33999 177 * @}
<> 149:156823d33999 178 */
<> 149:156823d33999 179 #endif /* USE_FULL_LL_DRIVER */
<> 149:156823d33999 180
<> 149:156823d33999 181 /* Exported constants --------------------------------------------------------*/
<> 149:156823d33999 182 /** @defgroup DAC_LL_Exported_Constants DAC Exported Constants
<> 149:156823d33999 183 * @{
<> 149:156823d33999 184 */
<> 149:156823d33999 185
<> 149:156823d33999 186 /** @defgroup DAC_LL_EC_GET_FLAG DAC flags
<> 149:156823d33999 187 * @brief Flags defines which can be used with LL_DAC_ReadReg function
<> 149:156823d33999 188 * @{
<> 149:156823d33999 189 */
<> 149:156823d33999 190 /* DAC channel 1 flags */
<> 149:156823d33999 191 #define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /*!< DAC channel 1 flag DMA underrun */
<> 149:156823d33999 192
<> 149:156823d33999 193 /* DAC channel 2 flags */
<> 149:156823d33999 194 #define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /*!< DAC channel 2 flag DMA underrun */
<> 149:156823d33999 195 /**
<> 149:156823d33999 196 * @}
<> 149:156823d33999 197 */
<> 149:156823d33999 198
<> 149:156823d33999 199 /** @defgroup DAC_LL_EC_IT DAC interruptions
<> 149:156823d33999 200 * @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions
<> 149:156823d33999 201 * @{
<> 149:156823d33999 202 */
<> 149:156823d33999 203 #define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */
<> 149:156823d33999 204 #define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */
<> 149:156823d33999 205 /**
<> 149:156823d33999 206 * @}
<> 149:156823d33999 207 */
<> 149:156823d33999 208
<> 149:156823d33999 209 /** @defgroup DAC_LL_EC_CHANNEL DAC channels
<> 149:156823d33999 210 * @{
<> 149:156823d33999 211 */
<> 149:156823d33999 212 #define LL_DAC_CHANNEL_1 (DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */
<> 149:156823d33999 213 #define LL_DAC_CHANNEL_2 (DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */
<> 149:156823d33999 214 /**
<> 149:156823d33999 215 * @}
<> 149:156823d33999 216 */
<> 149:156823d33999 217
<> 149:156823d33999 218 /** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source
<> 149:156823d33999 219 * @{
<> 149:156823d33999 220 */
<> 149:156823d33999 221 #define LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger internal (SW start) */
<> 149:156823d33999 222 #define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
<> 149:156823d33999 223 #define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */
<> 149:156823d33999 224 #define LL_DAC_TRIG_EXT_TIM6_TRGO ((uint32_t)0x00000000U) /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
<> 149:156823d33999 225 #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */
<> 149:156823d33999 226 #define LL_DAC_TRIG_EXT_TIM9_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM15 TRGO. */
<> 149:156823d33999 227 #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
<> 149:156823d33999 228 /**
<> 149:156823d33999 229 * @}
<> 149:156823d33999 230 */
<> 149:156823d33999 231
<> 149:156823d33999 232 /** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
<> 149:156823d33999 233 * @{
<> 149:156823d33999 234 */
<> 149:156823d33999 235 #define LL_DAC_WAVE_AUTO_GENERATION_NONE ((uint32_t)0x00000000U) /*!< DAC channel wave auto generation mode disabled. */
<> 149:156823d33999 236 #define LL_DAC_WAVE_AUTO_GENERATION_NOISE (DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */
<> 149:156823d33999 237 #define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */
<> 149:156823d33999 238 /**
<> 149:156823d33999 239 * @}
<> 149:156823d33999 240 */
<> 149:156823d33999 241
<> 149:156823d33999 242 /** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
<> 149:156823d33999 243 * @{
<> 149:156823d33999 244 */
<> 149:156823d33999 245 #define LL_DAC_NOISE_LFSR_UNMASK_BIT0 ((uint32_t)0x00000000U) /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */
<> 149:156823d33999 246 #define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */
<> 149:156823d33999 247 #define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */
<> 149:156823d33999 248 #define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */
<> 149:156823d33999 249 #define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */
<> 149:156823d33999 250 #define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */
<> 149:156823d33999 251 #define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */
<> 149:156823d33999 252 #define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */
<> 149:156823d33999 253 #define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */
<> 149:156823d33999 254 #define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */
<> 149:156823d33999 255 #define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */
<> 149:156823d33999 256 #define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */
<> 149:156823d33999 257 /**
<> 149:156823d33999 258 * @}
<> 149:156823d33999 259 */
<> 149:156823d33999 260
<> 149:156823d33999 261 /** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
<> 149:156823d33999 262 * @{
<> 149:156823d33999 263 */
<> 149:156823d33999 264 #define LL_DAC_TRIANGLE_AMPLITUDE_1 ((uint32_t)0x00000000U) /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */
<> 149:156823d33999 265 #define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */
<> 149:156823d33999 266 #define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */
<> 149:156823d33999 267 #define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */
<> 149:156823d33999 268 #define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */
<> 149:156823d33999 269 #define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */
<> 149:156823d33999 270 #define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */
<> 149:156823d33999 271 #define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */
<> 149:156823d33999 272 #define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */
<> 149:156823d33999 273 #define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */
<> 149:156823d33999 274 #define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */
<> 149:156823d33999 275 #define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */
<> 149:156823d33999 276 /**
<> 149:156823d33999 277 * @}
<> 149:156823d33999 278 */
<> 149:156823d33999 279
<> 149:156823d33999 280 /** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
<> 149:156823d33999 281 * @{
<> 149:156823d33999 282 */
<> 149:156823d33999 283 #define LL_DAC_OUTPUT_BUFFER_ENABLE ((uint32_t)0x00000000U) /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */
<> 149:156823d33999 284 #define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_CR_BOFF1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */
<> 149:156823d33999 285 /**
<> 149:156823d33999 286 * @}
<> 149:156823d33999 287 */
<> 149:156823d33999 288
<> 149:156823d33999 289
<> 149:156823d33999 290 /** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution
<> 149:156823d33999 291 * @{
<> 149:156823d33999 292 */
<> 149:156823d33999 293 #define LL_DAC_RESOLUTION_12B ((uint32_t)0x00000000U) /*!< DAC channel resolution 12 bits */
<> 149:156823d33999 294 #define LL_DAC_RESOLUTION_8B ((uint32_t)0x00000002U) /*!< DAC channel resolution 8 bits */
<> 149:156823d33999 295 /**
<> 149:156823d33999 296 * @}
<> 149:156823d33999 297 */
<> 149:156823d33999 298
<> 149:156823d33999 299 /** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose
<> 149:156823d33999 300 * @{
<> 149:156823d33999 301 */
<> 149:156823d33999 302 /* List of DAC registers intended to be used (most commonly) with */
<> 149:156823d33999 303 /* DMA transfer. */
<> 149:156823d33999 304 /* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */
<> 149:156823d33999 305 #define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_MASK /*!< DAC channel data holding register 12 bits right aligned */
<> 149:156823d33999 306 #define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_MASK /*!< DAC channel data holding register 12 bits left aligned */
<> 149:156823d33999 307 #define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_MASK /*!< DAC channel data holding register 8 bits right aligned */
<> 149:156823d33999 308 /**
<> 149:156823d33999 309 * @}
<> 149:156823d33999 310 */
<> 149:156823d33999 311
<> 149:156823d33999 312 /** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays
<> 149:156823d33999 313 * @note Only DAC IP HW delays are defined in DAC LL driver driver,
<> 149:156823d33999 314 * not timeout values.
<> 149:156823d33999 315 * For details on delays values, refer to descriptions in source code
<> 149:156823d33999 316 * above each literal definition.
<> 149:156823d33999 317 * @{
<> 149:156823d33999 318 */
<> 149:156823d33999 319
<> 149:156823d33999 320 /* Delay for DAC channel voltage settling time from DAC channel startup */
<> 149:156823d33999 321 /* (transition from disable to enable). */
<> 149:156823d33999 322 /* Note: DAC channel startup time depends on board application environment: */
<> 149:156823d33999 323 /* impedance connected to DAC channel output. */
<> 149:156823d33999 324 /* The delay below is specified under conditions: */
<> 149:156823d33999 325 /* - voltage maximum transition (lowest to highest value) */
<> 149:156823d33999 326 /* - until voltage reaches final value +-1LSB */
<> 149:156823d33999 327 /* - DAC channel output buffer enabled */
<> 149:156823d33999 328 /* - load impedance of 5kOhm (min), 50pF (max) */
<> 149:156823d33999 329 /* Literal set to maximum value (refer to device datasheet, */
<> 149:156823d33999 330 /* parameter "tWAKEUP"). */
<> 149:156823d33999 331 /* Unit: us */
<> 149:156823d33999 332 #define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US ((uint32_t) 15U) /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
<> 149:156823d33999 333
<> 149:156823d33999 334 /* Delay for DAC channel voltage settling time. */
<> 149:156823d33999 335 /* Note: DAC channel startup time depends on board application environment: */
<> 149:156823d33999 336 /* impedance connected to DAC channel output. */
<> 149:156823d33999 337 /* The delay below is specified under conditions: */
<> 149:156823d33999 338 /* - voltage maximum transition (lowest to highest value) */
<> 149:156823d33999 339 /* - until voltage reaches final value +-1LSB */
<> 149:156823d33999 340 /* - DAC channel output buffer enabled */
<> 149:156823d33999 341 /* - load impedance of 5kOhm min, 50pF max */
<> 149:156823d33999 342 /* Literal set to maximum value (refer to device datasheet, */
<> 149:156823d33999 343 /* parameter "tSETTLING"). */
<> 149:156823d33999 344 /* Unit: us */
<> 149:156823d33999 345 #define LL_DAC_DELAY_VOLTAGE_SETTLING_US ((uint32_t) 12U) /*!< Delay for DAC channel voltage settling time */
<> 149:156823d33999 346 /**
<> 149:156823d33999 347 * @}
<> 149:156823d33999 348 */
<> 149:156823d33999 349
<> 149:156823d33999 350 /**
<> 149:156823d33999 351 * @}
<> 149:156823d33999 352 */
<> 149:156823d33999 353
<> 149:156823d33999 354 /* Exported macro ------------------------------------------------------------*/
<> 149:156823d33999 355 /** @defgroup DAC_LL_Exported_Macros DAC Exported Macros
<> 149:156823d33999 356 * @{
<> 149:156823d33999 357 */
<> 149:156823d33999 358
<> 149:156823d33999 359 /** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros
<> 149:156823d33999 360 * @{
<> 149:156823d33999 361 */
<> 149:156823d33999 362
<> 149:156823d33999 363 /**
<> 149:156823d33999 364 * @brief Write a value in DAC register
<> 149:156823d33999 365 * @param __INSTANCE__ DAC Instance
<> 149:156823d33999 366 * @param __REG__ Register to be written
<> 149:156823d33999 367 * @param __VALUE__ Value to be written in the register
<> 149:156823d33999 368 * @retval None
<> 149:156823d33999 369 */
<> 149:156823d33999 370 #define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
<> 149:156823d33999 371
<> 149:156823d33999 372 /**
<> 149:156823d33999 373 * @brief Read a value in DAC register
<> 149:156823d33999 374 * @param __INSTANCE__ DAC Instance
<> 149:156823d33999 375 * @param __REG__ Register to be read
<> 149:156823d33999 376 * @retval Register value
<> 149:156823d33999 377 */
<> 149:156823d33999 378 #define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
<> 149:156823d33999 379
<> 149:156823d33999 380 /**
<> 149:156823d33999 381 * @}
<> 149:156823d33999 382 */
<> 149:156823d33999 383
<> 149:156823d33999 384 /** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro
<> 149:156823d33999 385 * @{
<> 149:156823d33999 386 */
<> 149:156823d33999 387
<> 149:156823d33999 388 /**
<> 149:156823d33999 389 * @brief Helper macro to get DAC channel number in decimal format
<> 149:156823d33999 390 * from literals LL_DAC_CHANNEL_x.
<> 149:156823d33999 391 * Example:
<> 149:156823d33999 392 * __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1)
<> 149:156823d33999 393 * will return decimal number "1".
<> 149:156823d33999 394 * @note The input can be a value from functions where a channel
<> 149:156823d33999 395 * number is returned.
<> 149:156823d33999 396 * @param __CHANNEL__ This parameter can be one of the following values:
<> 149:156823d33999 397 * @arg @ref LL_DAC_CHANNEL_1
<> 149:156823d33999 398 * @arg @ref LL_DAC_CHANNEL_2
<> 149:156823d33999 399 * @retval 1...2
<> 149:156823d33999 400 */
<> 149:156823d33999 401 #define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
<> 149:156823d33999 402 ((__CHANNEL__) & DAC_SWTR_CHX_MASK)
<> 149:156823d33999 403
<> 149:156823d33999 404 /**
<> 149:156823d33999 405 * @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x
<> 149:156823d33999 406 * from number in decimal format.
<> 149:156823d33999 407 * Example:
<> 149:156823d33999 408 * __LL_DAC_DECIMAL_NB_TO_CHANNEL(1)
<> 149:156823d33999 409 * will return a data equivalent to "LL_DAC_CHANNEL_1".
<> 149:156823d33999 410 * @note If the input parameter does not correspond to a DAC channel,
<> 149:156823d33999 411 * this macro returns value '0'.
<> 149:156823d33999 412 * @param __DECIMAL_NB__ 1...2
<> 149:156823d33999 413 * @retval Returned value can be one of the following values:
<> 149:156823d33999 414 * @arg @ref LL_DAC_CHANNEL_1
<> 149:156823d33999 415 * @arg @ref LL_DAC_CHANNEL_2
<> 149:156823d33999 416 */
<> 149:156823d33999 417 #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
<> 149:156823d33999 418 (((__DECIMAL_NB__) == 1U) \
<> 149:156823d33999 419 ? ( \
<> 149:156823d33999 420 LL_DAC_CHANNEL_1 \
<> 149:156823d33999 421 ) \
<> 149:156823d33999 422 : \
<> 149:156823d33999 423 (((__DECIMAL_NB__) == 2U) \
<> 149:156823d33999 424 ? ( \
<> 149:156823d33999 425 LL_DAC_CHANNEL_2 \
<> 149:156823d33999 426 ) \
<> 149:156823d33999 427 : \
<> 149:156823d33999 428 ( \
<> 149:156823d33999 429 0 \
<> 149:156823d33999 430 ) \
<> 149:156823d33999 431 ) \
<> 149:156823d33999 432 )
<> 149:156823d33999 433
<> 149:156823d33999 434 /**
<> 149:156823d33999 435 * @brief Helper macro to define the DAC conversion data full-scale digital
<> 149:156823d33999 436 * value corresponding to the selected DAC resolution.
<> 149:156823d33999 437 * @note DAC conversion data full-scale corresponds to voltage range
<> 149:156823d33999 438 * determined by analog voltage references Vref+ and Vref-
<> 149:156823d33999 439 * (refer to reference manual).
<> 149:156823d33999 440 * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
<> 149:156823d33999 441 * @arg @ref LL_DAC_RESOLUTION_12B
<> 149:156823d33999 442 * @arg @ref LL_DAC_RESOLUTION_8B
<> 149:156823d33999 443 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
<> 149:156823d33999 444 */
<> 149:156823d33999 445 #define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
<> 149:156823d33999 446 (((uint32_t)0xFFFU) >> ((__DAC_RESOLUTION__) << 1U))
<> 149:156823d33999 447
<> 149:156823d33999 448 /**
<> 149:156823d33999 449 * @brief Helper macro to calculate the DAC conversion data (unit: digital
<> 149:156823d33999 450 * value) corresponding to a voltage (unit: mVolt).
<> 149:156823d33999 451 * @note This helper macro is intended to provide input data in voltage
<> 149:156823d33999 452 * rather than digital value,
<> 149:156823d33999 453 * to be used with LL DAC functions such as
<> 149:156823d33999 454 * @ref LL_DAC_ConvertData12RightAligned().
<> 149:156823d33999 455 * @note Analog reference voltage (Vref+) must be either known from
<> 149:156823d33999 456 * user board environment or can be calculated using ADC measurement
<> 149:156823d33999 457 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
<> 149:156823d33999 458 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
<> 149:156823d33999 459 * @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel
<> 149:156823d33999 460 * (unit: mVolt).
<> 149:156823d33999 461 * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
<> 149:156823d33999 462 * @arg @ref LL_DAC_RESOLUTION_12B
<> 149:156823d33999 463 * @arg @ref LL_DAC_RESOLUTION_8B
<> 149:156823d33999 464 * @retval DAC conversion data (unit: digital value)
<> 149:156823d33999 465 */
<> 149:156823d33999 466 #define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\
<> 149:156823d33999 467 __DAC_VOLTAGE__,\
<> 149:156823d33999 468 __DAC_RESOLUTION__) \
<> 149:156823d33999 469 ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
<> 149:156823d33999 470 / (__VREFANALOG_VOLTAGE__) \
<> 149:156823d33999 471 )
<> 149:156823d33999 472
<> 149:156823d33999 473 /**
<> 149:156823d33999 474 * @}
<> 149:156823d33999 475 */
<> 149:156823d33999 476
<> 149:156823d33999 477 /**
<> 149:156823d33999 478 * @}
<> 149:156823d33999 479 */
<> 149:156823d33999 480
<> 149:156823d33999 481
<> 149:156823d33999 482 /* Exported functions --------------------------------------------------------*/
<> 149:156823d33999 483 /** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
<> 149:156823d33999 484 * @{
<> 149:156823d33999 485 */
<> 149:156823d33999 486 /** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels
<> 149:156823d33999 487 * @{
<> 149:156823d33999 488 */
<> 149:156823d33999 489
<> 149:156823d33999 490 /**
<> 149:156823d33999 491 * @brief Set the conversion trigger source for the selected DAC channel.
<> 149:156823d33999 492 * @note For conversion trigger source to be effective, DAC trigger
<> 149:156823d33999 493 * must be enabled using function @ref LL_DAC_EnableTrigger().
<> 149:156823d33999 494 * @note To set conversion trigger source, DAC channel must be disabled.
<> 149:156823d33999 495 * Otherwise, the setting is discarded.
<> 149:156823d33999 496 * @note Availability of parameters of trigger sources from timer
<> 149:156823d33999 497 * depends on timers availability on the selected device.
<> 149:156823d33999 498 * @rmtoll CR TSEL1 LL_DAC_SetTriggerSource\n
<> 149:156823d33999 499 * CR TSEL2 LL_DAC_SetTriggerSource
<> 149:156823d33999 500 * @param DACx DAC instance
<> 149:156823d33999 501 * @param DAC_Channel This parameter can be one of the following values:
<> 149:156823d33999 502 * @arg @ref LL_DAC_CHANNEL_1
<> 149:156823d33999 503 * @arg @ref LL_DAC_CHANNEL_2
<> 149:156823d33999 504 * @param TriggerSource This parameter can be one of the following values:
<> 149:156823d33999 505 * @arg @ref LL_DAC_TRIG_SOFTWARE
<> 149:156823d33999 506 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
<> 149:156823d33999 507 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
<> 149:156823d33999 508 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
<> 149:156823d33999 509 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
<> 149:156823d33999 510 * @arg @ref LL_DAC_TRIG_EXT_TIM9_TRGO
<> 149:156823d33999 511 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
<> 149:156823d33999 512 * @retval None
<> 149:156823d33999 513 */
<> 149:156823d33999 514 __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
<> 149:156823d33999 515 {
<> 149:156823d33999 516 MODIFY_REG(DACx->CR,
<> 149:156823d33999 517 DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
<> 149:156823d33999 518 TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
<> 149:156823d33999 519 }
<> 149:156823d33999 520
<> 149:156823d33999 521 /**
<> 149:156823d33999 522 * @brief Get the conversion trigger source for the selected DAC channel.
<> 149:156823d33999 523 * @note For conversion trigger source to be effective, DAC trigger
<> 149:156823d33999 524 * must be enabled using function @ref LL_DAC_EnableTrigger().
<> 149:156823d33999 525 * @note Availability of parameters of trigger sources from timer
<> 149:156823d33999 526 * depends on timers availability on the selected device.
<> 149:156823d33999 527 * @rmtoll CR TSEL1 LL_DAC_GetTriggerSource\n
<> 149:156823d33999 528 * CR TSEL2 LL_DAC_GetTriggerSource
<> 149:156823d33999 529 * @param DACx DAC instance
<> 149:156823d33999 530 * @param DAC_Channel This parameter can be one of the following values:
<> 149:156823d33999 531 * @arg @ref LL_DAC_CHANNEL_1
<> 149:156823d33999 532 * @arg @ref LL_DAC_CHANNEL_2
<> 149:156823d33999 533 * @retval Returned value can be one of the following values:
<> 149:156823d33999 534 * @arg @ref LL_DAC_TRIG_SOFTWARE
<> 149:156823d33999 535 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
<> 149:156823d33999 536 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
<> 149:156823d33999 537 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
<> 149:156823d33999 538 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
<> 149:156823d33999 539 * @arg @ref LL_DAC_TRIG_EXT_TIM9_TRGO
<> 149:156823d33999 540 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
<> 149:156823d33999 541 */
<> 149:156823d33999 542 __STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<> 149:156823d33999 543 {
<> 149:156823d33999 544 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
<> 149:156823d33999 545 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
<> 149:156823d33999 546 );
<> 149:156823d33999 547 }
<> 149:156823d33999 548
<> 149:156823d33999 549 /**
<> 149:156823d33999 550 * @brief Set the waveform automatic generation mode
<> 149:156823d33999 551 * for the selected DAC channel.
<> 149:156823d33999 552 * @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration\n
<> 149:156823d33999 553 * CR WAVE2 LL_DAC_SetWaveAutoGeneration
<> 149:156823d33999 554 * @param DACx DAC instance
<> 149:156823d33999 555 * @param DAC_Channel This parameter can be one of the following values:
<> 149:156823d33999 556 * @arg @ref LL_DAC_CHANNEL_1
<> 149:156823d33999 557 * @arg @ref LL_DAC_CHANNEL_2
<> 149:156823d33999 558 * @param WaveAutoGeneration This parameter can be one of the following values:
<> 149:156823d33999 559 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
<> 149:156823d33999 560 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
<> 149:156823d33999 561 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
<> 149:156823d33999 562 * @retval None
<> 149:156823d33999 563 */
<> 149:156823d33999 564 __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
<> 149:156823d33999 565 {
<> 149:156823d33999 566 MODIFY_REG(DACx->CR,
<> 149:156823d33999 567 DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
<> 149:156823d33999 568 WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
<> 149:156823d33999 569 }
<> 149:156823d33999 570
<> 149:156823d33999 571 /**
<> 149:156823d33999 572 * @brief Get the waveform automatic generation mode
<> 149:156823d33999 573 * for the selected DAC channel.
<> 149:156823d33999 574 * @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration\n
<> 149:156823d33999 575 * CR WAVE2 LL_DAC_GetWaveAutoGeneration
<> 149:156823d33999 576 * @param DACx DAC instance
<> 149:156823d33999 577 * @param DAC_Channel This parameter can be one of the following values:
<> 149:156823d33999 578 * @arg @ref LL_DAC_CHANNEL_1
<> 149:156823d33999 579 * @arg @ref LL_DAC_CHANNEL_2
<> 149:156823d33999 580 * @retval Returned value can be one of the following values:
<> 149:156823d33999 581 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
<> 149:156823d33999 582 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
<> 149:156823d33999 583 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
<> 149:156823d33999 584 */
<> 149:156823d33999 585 __STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<> 149:156823d33999 586 {
<> 149:156823d33999 587 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
<> 149:156823d33999 588 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
<> 149:156823d33999 589 );
<> 149:156823d33999 590 }
<> 149:156823d33999 591
<> 149:156823d33999 592 /**
<> 149:156823d33999 593 * @brief Set the noise waveform generation for the selected DAC channel:
<> 149:156823d33999 594 * Noise mode and parameters LFSR (linear feedback shift register).
<> 149:156823d33999 595 * @note For wave generation to be effective, DAC channel
<> 149:156823d33999 596 * wave generation mode must be enabled using
<> 149:156823d33999 597 * function @ref LL_DAC_SetWaveAutoGeneration().
<> 149:156823d33999 598 * @note This setting can be set when the selected DAC channel is disabled
<> 149:156823d33999 599 * (otherwise, the setting operation is ignored).
<> 149:156823d33999 600 * @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR\n
<> 149:156823d33999 601 * CR MAMP2 LL_DAC_SetWaveNoiseLFSR
<> 149:156823d33999 602 * @param DACx DAC instance
<> 149:156823d33999 603 * @param DAC_Channel This parameter can be one of the following values:
<> 149:156823d33999 604 * @arg @ref LL_DAC_CHANNEL_1
<> 149:156823d33999 605 * @arg @ref LL_DAC_CHANNEL_2
<> 149:156823d33999 606 * @param NoiseLFSRMask This parameter can be one of the following values:
<> 149:156823d33999 607 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
<> 149:156823d33999 608 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
<> 149:156823d33999 609 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
<> 149:156823d33999 610 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
<> 149:156823d33999 611 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
<> 149:156823d33999 612 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
<> 149:156823d33999 613 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
<> 149:156823d33999 614 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
<> 149:156823d33999 615 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
<> 149:156823d33999 616 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
<> 149:156823d33999 617 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
<> 149:156823d33999 618 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
<> 149:156823d33999 619 * @retval None
<> 149:156823d33999 620 */
<> 149:156823d33999 621 __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
<> 149:156823d33999 622 {
<> 149:156823d33999 623 MODIFY_REG(DACx->CR,
<> 149:156823d33999 624 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
<> 149:156823d33999 625 NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
<> 149:156823d33999 626 }
<> 149:156823d33999 627
<> 149:156823d33999 628 /**
<> 149:156823d33999 629 * @brief Set the noise waveform generation for the selected DAC channel:
<> 149:156823d33999 630 * Noise mode and parameters LFSR (linear feedback shift register).
<> 149:156823d33999 631 * @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n
<> 149:156823d33999 632 * CR MAMP2 LL_DAC_GetWaveNoiseLFSR
<> 149:156823d33999 633 * @param DACx DAC instance
<> 149:156823d33999 634 * @param DAC_Channel This parameter can be one of the following values:
<> 149:156823d33999 635 * @arg @ref LL_DAC_CHANNEL_1
<> 149:156823d33999 636 * @arg @ref LL_DAC_CHANNEL_2
<> 149:156823d33999 637 * @retval Returned value can be one of the following values:
<> 149:156823d33999 638 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
<> 149:156823d33999 639 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
<> 149:156823d33999 640 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
<> 149:156823d33999 641 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
<> 149:156823d33999 642 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
<> 149:156823d33999 643 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
<> 149:156823d33999 644 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
<> 149:156823d33999 645 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
<> 149:156823d33999 646 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
<> 149:156823d33999 647 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
<> 149:156823d33999 648 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
<> 149:156823d33999 649 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
<> 149:156823d33999 650 */
<> 149:156823d33999 651 __STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<> 149:156823d33999 652 {
<> 149:156823d33999 653 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
<> 149:156823d33999 654 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
<> 149:156823d33999 655 );
<> 149:156823d33999 656 }
<> 149:156823d33999 657
<> 149:156823d33999 658 /**
<> 149:156823d33999 659 * @brief Set the triangle waveform generation for the selected DAC channel:
<> 149:156823d33999 660 * triangle mode and amplitude.
<> 149:156823d33999 661 * @note For wave generation to be effective, DAC channel
<> 149:156823d33999 662 * wave generation mode must be enabled using
<> 149:156823d33999 663 * function @ref LL_DAC_SetWaveAutoGeneration().
<> 149:156823d33999 664 * @note This setting can be set when the selected DAC channel is disabled
<> 149:156823d33999 665 * (otherwise, the setting operation is ignored).
<> 149:156823d33999 666 * @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude\n
<> 149:156823d33999 667 * CR MAMP2 LL_DAC_SetWaveTriangleAmplitude
<> 149:156823d33999 668 * @param DACx DAC instance
<> 149:156823d33999 669 * @param DAC_Channel This parameter can be one of the following values:
<> 149:156823d33999 670 * @arg @ref LL_DAC_CHANNEL_1
<> 149:156823d33999 671 * @arg @ref LL_DAC_CHANNEL_2
<> 149:156823d33999 672 * @param TriangleAmplitude This parameter can be one of the following values:
<> 149:156823d33999 673 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
<> 149:156823d33999 674 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
<> 149:156823d33999 675 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
<> 149:156823d33999 676 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
<> 149:156823d33999 677 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
<> 149:156823d33999 678 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
<> 149:156823d33999 679 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
<> 149:156823d33999 680 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
<> 149:156823d33999 681 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
<> 149:156823d33999 682 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
<> 149:156823d33999 683 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
<> 149:156823d33999 684 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
<> 149:156823d33999 685 * @retval None
<> 149:156823d33999 686 */
<> 149:156823d33999 687 __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriangleAmplitude)
<> 149:156823d33999 688 {
<> 149:156823d33999 689 MODIFY_REG(DACx->CR,
<> 149:156823d33999 690 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
<> 149:156823d33999 691 TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
<> 149:156823d33999 692 }
<> 149:156823d33999 693
<> 149:156823d33999 694 /**
<> 149:156823d33999 695 * @brief Set the triangle waveform generation for the selected DAC channel:
<> 149:156823d33999 696 * triangle mode and amplitude.
<> 149:156823d33999 697 * @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n
<> 149:156823d33999 698 * CR MAMP2 LL_DAC_GetWaveTriangleAmplitude
<> 149:156823d33999 699 * @param DACx DAC instance
<> 149:156823d33999 700 * @param DAC_Channel This parameter can be one of the following values:
<> 149:156823d33999 701 * @arg @ref LL_DAC_CHANNEL_1
<> 149:156823d33999 702 * @arg @ref LL_DAC_CHANNEL_2
<> 149:156823d33999 703 * @retval Returned value can be one of the following values:
<> 149:156823d33999 704 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
<> 149:156823d33999 705 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
<> 149:156823d33999 706 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
<> 149:156823d33999 707 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
<> 149:156823d33999 708 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
<> 149:156823d33999 709 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
<> 149:156823d33999 710 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
<> 149:156823d33999 711 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
<> 149:156823d33999 712 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
<> 149:156823d33999 713 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
<> 149:156823d33999 714 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
<> 149:156823d33999 715 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
<> 149:156823d33999 716 */
<> 149:156823d33999 717 __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<> 149:156823d33999 718 {
<> 149:156823d33999 719 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
<> 149:156823d33999 720 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
<> 149:156823d33999 721 );
<> 149:156823d33999 722 }
<> 149:156823d33999 723
<> 149:156823d33999 724 /**
<> 149:156823d33999 725 * @brief Set the output buffer for the selected DAC channel.
<> 149:156823d33999 726 * @rmtoll CR BOFF1 LL_DAC_SetOutputBuffer\n
<> 149:156823d33999 727 * CR BOFF2 LL_DAC_SetOutputBuffer
<> 149:156823d33999 728 * @param DACx DAC instance
<> 149:156823d33999 729 * @param DAC_Channel This parameter can be one of the following values:
<> 149:156823d33999 730 * @arg @ref LL_DAC_CHANNEL_1
<> 149:156823d33999 731 * @arg @ref LL_DAC_CHANNEL_2
<> 149:156823d33999 732 * @param OutputBuffer This parameter can be one of the following values:
<> 149:156823d33999 733 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
<> 149:156823d33999 734 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
<> 149:156823d33999 735 * @retval None
<> 149:156823d33999 736 */
<> 149:156823d33999 737 __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
<> 149:156823d33999 738 {
<> 149:156823d33999 739 MODIFY_REG(DACx->CR,
<> 149:156823d33999 740 DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
<> 149:156823d33999 741 OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
<> 149:156823d33999 742 }
<> 149:156823d33999 743
<> 149:156823d33999 744 /**
<> 149:156823d33999 745 * @brief Get the output buffer state for the selected DAC channel.
<> 149:156823d33999 746 * @rmtoll CR BOFF1 LL_DAC_GetOutputBuffer\n
<> 149:156823d33999 747 * CR BOFF2 LL_DAC_GetOutputBuffer
<> 149:156823d33999 748 * @param DACx DAC instance
<> 149:156823d33999 749 * @param DAC_Channel This parameter can be one of the following values:
<> 149:156823d33999 750 * @arg @ref LL_DAC_CHANNEL_1
<> 149:156823d33999 751 * @arg @ref LL_DAC_CHANNEL_2
<> 149:156823d33999 752 * @retval Returned value can be one of the following values:
<> 149:156823d33999 753 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
<> 149:156823d33999 754 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
<> 149:156823d33999 755 */
<> 149:156823d33999 756 __STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<> 149:156823d33999 757 {
<> 149:156823d33999 758 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
<> 149:156823d33999 759 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
<> 149:156823d33999 760 );
<> 149:156823d33999 761 }
<> 149:156823d33999 762
<> 149:156823d33999 763 /**
<> 149:156823d33999 764 * @}
<> 149:156823d33999 765 */
<> 149:156823d33999 766
<> 149:156823d33999 767 /** @defgroup DAC_LL_EF_DMA_Management DMA Management
<> 149:156823d33999 768 * @{
<> 149:156823d33999 769 */
<> 149:156823d33999 770
<> 149:156823d33999 771 /**
<> 149:156823d33999 772 * @brief Enable DAC DMA transfer request of the selected channel.
<> 149:156823d33999 773 * @note To configure DMA source address (peripheral address),
<> 149:156823d33999 774 * use function @ref LL_DAC_DMA_GetRegAddr().
<> 149:156823d33999 775 * @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq\n
<> 149:156823d33999 776 * CR DMAEN2 LL_DAC_EnableDMAReq
<> 149:156823d33999 777 * @param DACx DAC instance
<> 149:156823d33999 778 * @param DAC_Channel This parameter can be one of the following values:
<> 149:156823d33999 779 * @arg @ref LL_DAC_CHANNEL_1
<> 149:156823d33999 780 * @arg @ref LL_DAC_CHANNEL_2
<> 149:156823d33999 781 * @retval None
<> 149:156823d33999 782 */
<> 149:156823d33999 783 __STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<> 149:156823d33999 784 {
<> 149:156823d33999 785 SET_BIT(DACx->CR,
<> 149:156823d33999 786 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
<> 149:156823d33999 787 }
<> 149:156823d33999 788
<> 149:156823d33999 789 /**
<> 149:156823d33999 790 * @brief Disable DAC DMA transfer request of the selected channel.
<> 149:156823d33999 791 * @note To configure DMA source address (peripheral address),
<> 149:156823d33999 792 * use function @ref LL_DAC_DMA_GetRegAddr().
<> 149:156823d33999 793 * @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq\n
<> 149:156823d33999 794 * CR DMAEN2 LL_DAC_DisableDMAReq
<> 149:156823d33999 795 * @param DACx DAC instance
<> 149:156823d33999 796 * @param DAC_Channel This parameter can be one of the following values:
<> 149:156823d33999 797 * @arg @ref LL_DAC_CHANNEL_1
<> 149:156823d33999 798 * @arg @ref LL_DAC_CHANNEL_2
<> 149:156823d33999 799 * @retval None
<> 149:156823d33999 800 */
<> 149:156823d33999 801 __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<> 149:156823d33999 802 {
<> 149:156823d33999 803 CLEAR_BIT(DACx->CR,
<> 149:156823d33999 804 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
<> 149:156823d33999 805 }
<> 149:156823d33999 806
<> 149:156823d33999 807 /**
<> 149:156823d33999 808 * @brief Get DAC DMA transfer request state of the selected channel.
<> 149:156823d33999 809 * (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled)
<> 149:156823d33999 810 * @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled\n
<> 149:156823d33999 811 * CR DMAEN2 LL_DAC_IsDMAReqEnabled
<> 149:156823d33999 812 * @param DACx DAC instance
<> 149:156823d33999 813 * @param DAC_Channel This parameter can be one of the following values:
<> 149:156823d33999 814 * @arg @ref LL_DAC_CHANNEL_1
<> 149:156823d33999 815 * @arg @ref LL_DAC_CHANNEL_2
<> 149:156823d33999 816 * @retval State of bit (1 or 0).
<> 149:156823d33999 817 */
<> 149:156823d33999 818 __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<> 149:156823d33999 819 {
<> 149:156823d33999 820 return (READ_BIT(DACx->CR,
<> 149:156823d33999 821 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
<> 149:156823d33999 822 == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
<> 149:156823d33999 823 }
<> 149:156823d33999 824
<> 149:156823d33999 825 /**
<> 149:156823d33999 826 * @brief Function to help to configure DMA transfer to DAC: retrieve the
<> 149:156823d33999 827 * DAC register address from DAC instance and a list of DAC registers
<> 149:156823d33999 828 * intended to be used (most commonly) with DMA transfer.
<> 149:156823d33999 829 * @note These DAC registers are data holding registers:
<> 149:156823d33999 830 * when DAC conversion is requested, DAC generates a DMA transfer
<> 149:156823d33999 831 * request to have data available in DAC data holding registers.
<> 149:156823d33999 832 * @note This macro is intended to be used with LL DMA driver, refer to
<> 149:156823d33999 833 * function "LL_DMA_ConfigAddresses()".
<> 149:156823d33999 834 * Example:
<> 149:156823d33999 835 * LL_DMA_ConfigAddresses(DMA1,
<> 149:156823d33999 836 * LL_DMA_CHANNEL_1,
<> 149:156823d33999 837 * (uint32_t)&< array or variable >,
<> 149:156823d33999 838 * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
<> 149:156823d33999 839 * LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
<> 149:156823d33999 840 * @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
<> 149:156823d33999 841 * DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
<> 149:156823d33999 842 * DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
<> 149:156823d33999 843 * DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
<> 149:156823d33999 844 * DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
<> 149:156823d33999 845 * DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr
<> 149:156823d33999 846 * @param DACx DAC instance
<> 149:156823d33999 847 * @param DAC_Channel This parameter can be one of the following values:
<> 149:156823d33999 848 * @arg @ref LL_DAC_CHANNEL_1
<> 149:156823d33999 849 * @arg @ref LL_DAC_CHANNEL_2
<> 149:156823d33999 850 * @param Register This parameter can be one of the following values:
<> 149:156823d33999 851 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
<> 149:156823d33999 852 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED
<> 149:156823d33999 853 * @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
<> 149:156823d33999 854 * @retval DAC register address
<> 149:156823d33999 855 */
<> 149:156823d33999 856 __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
<> 149:156823d33999 857 {
<> 149:156823d33999 858 /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */
<> 149:156823d33999 859 /* DAC channel selected. */
<> 149:156823d33999 860 return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, Register))));
<> 149:156823d33999 861 }
<> 149:156823d33999 862 /**
<> 149:156823d33999 863 * @}
<> 149:156823d33999 864 */
<> 149:156823d33999 865
<> 149:156823d33999 866 /** @defgroup DAC_LL_EF_Operation Operation on DAC channels
<> 149:156823d33999 867 * @{
<> 149:156823d33999 868 */
<> 149:156823d33999 869
<> 149:156823d33999 870 /**
<> 149:156823d33999 871 * @brief Enable DAC selected channel.
<> 149:156823d33999 872 * @rmtoll CR EN1 LL_DAC_Enable\n
<> 149:156823d33999 873 * CR EN2 LL_DAC_Enable
<> 149:156823d33999 874 * @note After enable from off state, DAC channel requires a delay
<> 149:156823d33999 875 * for output voltage to reach accuracy +/- 1 LSB.
<> 149:156823d33999 876 * Refer to device datasheet, parameter "tWAKEUP".
<> 149:156823d33999 877 * @param DACx DAC instance
<> 149:156823d33999 878 * @param DAC_Channel This parameter can be one of the following values:
<> 149:156823d33999 879 * @arg @ref LL_DAC_CHANNEL_1
<> 149:156823d33999 880 * @arg @ref LL_DAC_CHANNEL_2
<> 149:156823d33999 881 * @retval None
<> 149:156823d33999 882 */
<> 149:156823d33999 883 __STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<> 149:156823d33999 884 {
<> 149:156823d33999 885 SET_BIT(DACx->CR,
<> 149:156823d33999 886 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
<> 149:156823d33999 887 }
<> 149:156823d33999 888
<> 149:156823d33999 889 /**
<> 149:156823d33999 890 * @brief Disable DAC selected channel.
<> 149:156823d33999 891 * @rmtoll CR EN1 LL_DAC_Disable\n
<> 149:156823d33999 892 * CR EN2 LL_DAC_Disable
<> 149:156823d33999 893 * @param DACx DAC instance
<> 149:156823d33999 894 * @param DAC_Channel This parameter can be one of the following values:
<> 149:156823d33999 895 * @arg @ref LL_DAC_CHANNEL_1
<> 149:156823d33999 896 * @arg @ref LL_DAC_CHANNEL_2
<> 149:156823d33999 897 * @retval None
<> 149:156823d33999 898 */
<> 149:156823d33999 899 __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<> 149:156823d33999 900 {
<> 149:156823d33999 901 CLEAR_BIT(DACx->CR,
<> 149:156823d33999 902 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
<> 149:156823d33999 903 }
<> 149:156823d33999 904
<> 149:156823d33999 905 /**
<> 149:156823d33999 906 * @brief Get DAC enable state of the selected channel.
<> 149:156823d33999 907 * (0: DAC channel is disabled, 1: DAC channel is enabled)
<> 149:156823d33999 908 * @rmtoll CR EN1 LL_DAC_IsEnabled\n
<> 149:156823d33999 909 * CR EN2 LL_DAC_IsEnabled
<> 149:156823d33999 910 * @param DACx DAC instance
<> 149:156823d33999 911 * @param DAC_Channel This parameter can be one of the following values:
<> 149:156823d33999 912 * @arg @ref LL_DAC_CHANNEL_1
<> 149:156823d33999 913 * @arg @ref LL_DAC_CHANNEL_2
<> 149:156823d33999 914 * @retval State of bit (1 or 0).
<> 149:156823d33999 915 */
<> 149:156823d33999 916 __STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<> 149:156823d33999 917 {
<> 149:156823d33999 918 return (READ_BIT(DACx->CR,
<> 149:156823d33999 919 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
<> 149:156823d33999 920 == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
<> 149:156823d33999 921 }
<> 149:156823d33999 922
<> 149:156823d33999 923 /**
<> 149:156823d33999 924 * @brief Enable DAC trigger of the selected channel.
<> 149:156823d33999 925 * @note - If DAC trigger is disabled, DAC conversion is performed
<> 149:156823d33999 926 * automatically once the data holding register is updated,
<> 149:156823d33999 927 * using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
<> 149:156823d33999 928 * @ref LL_DAC_ConvertData12RightAligned(), ...
<> 149:156823d33999 929 * - If DAC trigger is enabled, DAC conversion is performed
<> 149:156823d33999 930 * only when a hardware of software trigger event is occurring.
<> 149:156823d33999 931 * Select trigger source using
<> 149:156823d33999 932 * function @ref LL_DAC_SetTriggerSource().
<> 149:156823d33999 933 * @rmtoll CR TEN1 LL_DAC_EnableTrigger\n
<> 149:156823d33999 934 * CR TEN2 LL_DAC_EnableTrigger
<> 149:156823d33999 935 * @param DACx DAC instance
<> 149:156823d33999 936 * @param DAC_Channel This parameter can be one of the following values:
<> 149:156823d33999 937 * @arg @ref LL_DAC_CHANNEL_1
<> 149:156823d33999 938 * @arg @ref LL_DAC_CHANNEL_2
<> 149:156823d33999 939 * @retval None
<> 149:156823d33999 940 */
<> 149:156823d33999 941 __STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<> 149:156823d33999 942 {
<> 149:156823d33999 943 SET_BIT(DACx->CR,
<> 149:156823d33999 944 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
<> 149:156823d33999 945 }
<> 149:156823d33999 946
<> 149:156823d33999 947 /**
<> 149:156823d33999 948 * @brief Disable DAC trigger of the selected channel.
<> 149:156823d33999 949 * @rmtoll CR TEN1 LL_DAC_DisableTrigger\n
<> 149:156823d33999 950 * CR TEN2 LL_DAC_DisableTrigger
<> 149:156823d33999 951 * @param DACx DAC instance
<> 149:156823d33999 952 * @param DAC_Channel This parameter can be one of the following values:
<> 149:156823d33999 953 * @arg @ref LL_DAC_CHANNEL_1
<> 149:156823d33999 954 * @arg @ref LL_DAC_CHANNEL_2
<> 149:156823d33999 955 * @retval None
<> 149:156823d33999 956 */
<> 149:156823d33999 957 __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<> 149:156823d33999 958 {
<> 149:156823d33999 959 CLEAR_BIT(DACx->CR,
<> 149:156823d33999 960 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
<> 149:156823d33999 961 }
<> 149:156823d33999 962
<> 149:156823d33999 963 /**
<> 149:156823d33999 964 * @brief Get DAC trigger state of the selected channel.
<> 149:156823d33999 965 * (0: DAC trigger is disabled, 1: DAC trigger is enabled)
<> 149:156823d33999 966 * @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled\n
<> 149:156823d33999 967 * CR TEN2 LL_DAC_IsTriggerEnabled
<> 149:156823d33999 968 * @param DACx DAC instance
<> 149:156823d33999 969 * @param DAC_Channel This parameter can be one of the following values:
<> 149:156823d33999 970 * @arg @ref LL_DAC_CHANNEL_1
<> 149:156823d33999 971 * @arg @ref LL_DAC_CHANNEL_2
<> 149:156823d33999 972 * @retval State of bit (1 or 0).
<> 149:156823d33999 973 */
<> 149:156823d33999 974 __STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<> 149:156823d33999 975 {
<> 149:156823d33999 976 return (READ_BIT(DACx->CR,
<> 149:156823d33999 977 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
<> 149:156823d33999 978 == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
<> 149:156823d33999 979 }
<> 149:156823d33999 980
<> 149:156823d33999 981 /**
<> 149:156823d33999 982 * @brief Trig DAC conversion by software for the selected DAC channel.
<> 149:156823d33999 983 * @note Preliminarily, DAC trigger must be set to software trigger
<> 149:156823d33999 984 * using function @ref LL_DAC_SetTriggerSource()
<> 149:156823d33999 985 * with parameter "LL_DAC_TRIGGER_SOFTWARE".
<> 149:156823d33999 986 * and DAC trigger must be enabled using
<> 149:156823d33999 987 * function @ref LL_DAC_EnableTrigger().
<> 149:156823d33999 988 * @note For devices featuring DAC with 2 channels: this function
<> 149:156823d33999 989 * can perform a SW start of both DAC channels simultaneously.
<> 149:156823d33999 990 * Two channels can be selected as parameter.
<> 149:156823d33999 991 * Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2)
<> 149:156823d33999 992 * @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion\n
<> 149:156823d33999 993 * SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion
<> 149:156823d33999 994 * @param DACx DAC instance
<> 149:156823d33999 995 * @param DAC_Channel This parameter can a combination of the following values:
<> 149:156823d33999 996 * @arg @ref LL_DAC_CHANNEL_1
<> 149:156823d33999 997 * @arg @ref LL_DAC_CHANNEL_2
<> 149:156823d33999 998 * @retval None
<> 149:156823d33999 999 */
<> 149:156823d33999 1000 __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<> 149:156823d33999 1001 {
<> 149:156823d33999 1002 SET_BIT(DACx->SWTRIGR,
<> 149:156823d33999 1003 (DAC_Channel & DAC_SWTR_CHX_MASK));
<> 149:156823d33999 1004 }
<> 149:156823d33999 1005
<> 149:156823d33999 1006 /**
<> 149:156823d33999 1007 * @brief Set the data to be loaded in the data holding register
<> 149:156823d33999 1008 * in format 12 bits left alignment (LSB aligned on bit 0),
<> 149:156823d33999 1009 * for the selected DAC channel.
<> 149:156823d33999 1010 * @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned\n
<> 149:156823d33999 1011 * DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned
<> 149:156823d33999 1012 * @param DACx DAC instance
<> 149:156823d33999 1013 * @param DAC_Channel This parameter can be one of the following values:
<> 149:156823d33999 1014 * @arg @ref LL_DAC_CHANNEL_1
<> 149:156823d33999 1015 * @arg @ref LL_DAC_CHANNEL_2
<> 149:156823d33999 1016 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
<> 149:156823d33999 1017 * @retval None
<> 149:156823d33999 1018 */
<> 149:156823d33999 1019 __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
<> 149:156823d33999 1020 {
<> 149:156823d33999 1021 register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12RX_REGOFFSET_MASK));
<> 149:156823d33999 1022
<> 149:156823d33999 1023 MODIFY_REG(*preg,
<> 149:156823d33999 1024 DAC_DHR12R1_DACC1DHR,
<> 149:156823d33999 1025 Data);
<> 149:156823d33999 1026 }
<> 149:156823d33999 1027
<> 149:156823d33999 1028 /**
<> 149:156823d33999 1029 * @brief Set the data to be loaded in the data holding register
<> 149:156823d33999 1030 * in format 12 bits left alignment (MSB aligned on bit 15),
<> 149:156823d33999 1031 * for the selected DAC channel.
<> 149:156823d33999 1032 * @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned\n
<> 149:156823d33999 1033 * DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned
<> 149:156823d33999 1034 * @param DACx DAC instance
<> 149:156823d33999 1035 * @param DAC_Channel This parameter can be one of the following values:
<> 149:156823d33999 1036 * @arg @ref LL_DAC_CHANNEL_1
<> 149:156823d33999 1037 * @arg @ref LL_DAC_CHANNEL_2
<> 149:156823d33999 1038 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
<> 149:156823d33999 1039 * @retval None
<> 149:156823d33999 1040 */
<> 149:156823d33999 1041 __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
<> 149:156823d33999 1042 {
<> 149:156823d33999 1043 register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12LX_REGOFFSET_MASK));
<> 149:156823d33999 1044
<> 149:156823d33999 1045 MODIFY_REG(*preg,
<> 149:156823d33999 1046 DAC_DHR12L1_DACC1DHR,
<> 149:156823d33999 1047 Data);
<> 149:156823d33999 1048 }
<> 149:156823d33999 1049
<> 149:156823d33999 1050 /**
<> 149:156823d33999 1051 * @brief Set the data to be loaded in the data holding register
<> 149:156823d33999 1052 * in format 8 bits left alignment (LSB aligned on bit 0),
<> 149:156823d33999 1053 * for the selected DAC channel.
<> 149:156823d33999 1054 * @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned\n
<> 149:156823d33999 1055 * DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned
<> 149:156823d33999 1056 * @param DACx DAC instance
<> 149:156823d33999 1057 * @param DAC_Channel This parameter can be one of the following values:
<> 149:156823d33999 1058 * @arg @ref LL_DAC_CHANNEL_1
<> 149:156823d33999 1059 * @arg @ref LL_DAC_CHANNEL_2
<> 149:156823d33999 1060 * @param Data Value between Min_Data=0x00 and Max_Data=0xFF
<> 149:156823d33999 1061 * @retval None
<> 149:156823d33999 1062 */
<> 149:156823d33999 1063 __STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
<> 149:156823d33999 1064 {
<> 149:156823d33999 1065 register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR8RX_REGOFFSET_MASK));
<> 149:156823d33999 1066
<> 149:156823d33999 1067 MODIFY_REG(*preg,
<> 149:156823d33999 1068 DAC_DHR8R1_DACC1DHR,
<> 149:156823d33999 1069 Data);
<> 149:156823d33999 1070 }
<> 149:156823d33999 1071
<> 149:156823d33999 1072 /**
<> 149:156823d33999 1073 * @brief Set the data to be loaded in the data holding register
<> 149:156823d33999 1074 * in format 12 bits left alignment (LSB aligned on bit 0),
<> 149:156823d33999 1075 * for both DAC channels.
<> 149:156823d33999 1076 * @rmtoll DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned\n
<> 149:156823d33999 1077 * DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned
<> 149:156823d33999 1078 * @param DACx DAC instance
<> 149:156823d33999 1079 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
<> 149:156823d33999 1080 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
<> 149:156823d33999 1081 * @retval None
<> 149:156823d33999 1082 */
<> 149:156823d33999 1083 __STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
<> 149:156823d33999 1084 {
<> 149:156823d33999 1085 MODIFY_REG(DACx->DHR12RD,
<> 149:156823d33999 1086 (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR),
<> 149:156823d33999 1087 ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
<> 149:156823d33999 1088 }
<> 149:156823d33999 1089
<> 149:156823d33999 1090 /**
<> 149:156823d33999 1091 * @brief Set the data to be loaded in the data holding register
<> 149:156823d33999 1092 * in format 12 bits left alignment (MSB aligned on bit 15),
<> 149:156823d33999 1093 * for both DAC channels.
<> 149:156823d33999 1094 * @rmtoll DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned\n
<> 149:156823d33999 1095 * DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned
<> 149:156823d33999 1096 * @param DACx DAC instance
<> 149:156823d33999 1097 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
<> 149:156823d33999 1098 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
<> 149:156823d33999 1099 * @retval None
<> 149:156823d33999 1100 */
<> 149:156823d33999 1101 __STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
<> 149:156823d33999 1102 {
<> 149:156823d33999 1103 /* Note: Data of DAC channel 2 shift value subtracted of 4 because */
<> 149:156823d33999 1104 /* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */
<> 149:156823d33999 1105 /* the 4 LSB must be taken into account for the shift value. */
<> 149:156823d33999 1106 MODIFY_REG(DACx->DHR12LD,
<> 149:156823d33999 1107 (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR),
<> 149:156823d33999 1108 ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1));
<> 149:156823d33999 1109 }
<> 149:156823d33999 1110
<> 149:156823d33999 1111 /**
<> 149:156823d33999 1112 * @brief Set the data to be loaded in the data holding register
<> 149:156823d33999 1113 * in format 8 bits left alignment (LSB aligned on bit 0),
<> 149:156823d33999 1114 * for both DAC channels.
<> 149:156823d33999 1115 * @rmtoll DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned\n
<> 149:156823d33999 1116 * DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned
<> 149:156823d33999 1117 * @param DACx DAC instance
<> 149:156823d33999 1118 * @param DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF
<> 149:156823d33999 1119 * @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF
<> 149:156823d33999 1120 * @retval None
<> 149:156823d33999 1121 */
<> 149:156823d33999 1122 __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
<> 149:156823d33999 1123 {
<> 149:156823d33999 1124 MODIFY_REG(DACx->DHR8RD,
<> 149:156823d33999 1125 (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR),
<> 149:156823d33999 1126 ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
<> 149:156823d33999 1127 }
<> 149:156823d33999 1128
<> 149:156823d33999 1129 /**
<> 149:156823d33999 1130 * @brief Retrieve output data currently generated for the selected DAC channel.
<> 149:156823d33999 1131 * @note Whatever alignment and resolution settings
<> 149:156823d33999 1132 * (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
<> 149:156823d33999 1133 * @ref LL_DAC_ConvertData12RightAligned(), ...),
<> 149:156823d33999 1134 * output data format is 12 bits right aligned (LSB aligned on bit 0).
<> 149:156823d33999 1135 * @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData\n
<> 149:156823d33999 1136 * DOR2 DACC2DOR LL_DAC_RetrieveOutputData
<> 149:156823d33999 1137 * @param DACx DAC instance
<> 149:156823d33999 1138 * @param DAC_Channel This parameter can be one of the following values:
<> 149:156823d33999 1139 * @arg @ref LL_DAC_CHANNEL_1
<> 149:156823d33999 1140 * @arg @ref LL_DAC_CHANNEL_2
<> 149:156823d33999 1141 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
<> 149:156823d33999 1142 */
<> 149:156823d33999 1143 __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<> 149:156823d33999 1144 {
<> 149:156823d33999 1145 register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DORX_REGOFFSET_MASK));
<> 149:156823d33999 1146
<> 149:156823d33999 1147 return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
<> 149:156823d33999 1148 }
<> 149:156823d33999 1149
<> 149:156823d33999 1150 /**
<> 149:156823d33999 1151 * @}
<> 149:156823d33999 1152 */
<> 149:156823d33999 1153
<> 149:156823d33999 1154 /** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
<> 149:156823d33999 1155 * @{
<> 149:156823d33999 1156 */
<> 149:156823d33999 1157 /**
<> 149:156823d33999 1158 * @brief Get DAC underrun flag for DAC channel 1
<> 149:156823d33999 1159 * @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1
<> 149:156823d33999 1160 * @param DACx DAC instance
<> 149:156823d33999 1161 * @retval State of bit (1 or 0).
<> 149:156823d33999 1162 */
<> 149:156823d33999 1163 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx)
<> 149:156823d33999 1164 {
<> 149:156823d33999 1165 return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1));
<> 149:156823d33999 1166 }
<> 149:156823d33999 1167
<> 149:156823d33999 1168 /**
<> 149:156823d33999 1169 * @brief Get DAC underrun flag for DAC channel 2
<> 149:156823d33999 1170 * @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2
<> 149:156823d33999 1171 * @param DACx DAC instance
<> 149:156823d33999 1172 * @retval State of bit (1 or 0).
<> 149:156823d33999 1173 */
<> 149:156823d33999 1174 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx)
<> 149:156823d33999 1175 {
<> 149:156823d33999 1176 return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2));
<> 149:156823d33999 1177 }
<> 149:156823d33999 1178
<> 149:156823d33999 1179 /**
<> 149:156823d33999 1180 * @brief Clear DAC underrun flag for DAC channel 1
<> 149:156823d33999 1181 * @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1
<> 149:156823d33999 1182 * @param DACx DAC instance
<> 149:156823d33999 1183 * @retval None
<> 149:156823d33999 1184 */
<> 149:156823d33999 1185 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx)
<> 149:156823d33999 1186 {
<> 149:156823d33999 1187 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1);
<> 149:156823d33999 1188 }
<> 149:156823d33999 1189
<> 149:156823d33999 1190 /**
<> 149:156823d33999 1191 * @brief Clear DAC underrun flag for DAC channel 2
<> 149:156823d33999 1192 * @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2
<> 149:156823d33999 1193 * @param DACx DAC instance
<> 149:156823d33999 1194 * @retval None
<> 149:156823d33999 1195 */
<> 149:156823d33999 1196 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx)
<> 149:156823d33999 1197 {
<> 149:156823d33999 1198 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2);
<> 149:156823d33999 1199 }
<> 149:156823d33999 1200
<> 149:156823d33999 1201 /**
<> 149:156823d33999 1202 * @}
<> 149:156823d33999 1203 */
<> 149:156823d33999 1204
<> 149:156823d33999 1205 /** @defgroup DAC_LL_EF_IT_Management IT management
<> 149:156823d33999 1206 * @{
<> 149:156823d33999 1207 */
<> 149:156823d33999 1208
<> 149:156823d33999 1209 /**
<> 149:156823d33999 1210 * @brief Enable DMA underrun interrupt for DAC channel 1
<> 149:156823d33999 1211 * @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1
<> 149:156823d33999 1212 * @param DACx DAC instance
<> 149:156823d33999 1213 * @retval None
<> 149:156823d33999 1214 */
<> 149:156823d33999 1215 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx)
<> 149:156823d33999 1216 {
<> 149:156823d33999 1217 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
<> 149:156823d33999 1218 }
<> 149:156823d33999 1219
<> 149:156823d33999 1220 /**
<> 149:156823d33999 1221 * @brief Enable DMA underrun interrupt for DAC channel 2
<> 149:156823d33999 1222 * @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2
<> 149:156823d33999 1223 * @param DACx DAC instance
<> 149:156823d33999 1224 * @retval None
<> 149:156823d33999 1225 */
<> 149:156823d33999 1226 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx)
<> 149:156823d33999 1227 {
<> 149:156823d33999 1228 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
<> 149:156823d33999 1229 }
<> 149:156823d33999 1230
<> 149:156823d33999 1231 /**
<> 149:156823d33999 1232 * @brief Disable DMA underrun interrupt for DAC channel 1
<> 149:156823d33999 1233 * @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1
<> 149:156823d33999 1234 * @param DACx DAC instance
<> 149:156823d33999 1235 * @retval None
<> 149:156823d33999 1236 */
<> 149:156823d33999 1237 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx)
<> 149:156823d33999 1238 {
<> 149:156823d33999 1239 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
<> 149:156823d33999 1240 }
<> 149:156823d33999 1241
<> 149:156823d33999 1242 /**
<> 149:156823d33999 1243 * @brief Disable DMA underrun interrupt for DAC channel 2
<> 149:156823d33999 1244 * @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2
<> 149:156823d33999 1245 * @param DACx DAC instance
<> 149:156823d33999 1246 * @retval None
<> 149:156823d33999 1247 */
<> 149:156823d33999 1248 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
<> 149:156823d33999 1249 {
<> 149:156823d33999 1250 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
<> 149:156823d33999 1251 }
<> 149:156823d33999 1252
<> 149:156823d33999 1253 /**
<> 149:156823d33999 1254 * @brief Get DMA underrun interrupt for DAC channel 1
<> 149:156823d33999 1255 * @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1
<> 149:156823d33999 1256 * @param DACx DAC instance
<> 149:156823d33999 1257 * @retval State of bit (1 or 0).
<> 149:156823d33999 1258 */
<> 149:156823d33999 1259 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx)
<> 149:156823d33999 1260 {
<> 149:156823d33999 1261 return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1));
<> 149:156823d33999 1262 }
<> 149:156823d33999 1263
<> 149:156823d33999 1264 /**
<> 149:156823d33999 1265 * @brief Get DMA underrun interrupt for DAC channel 2
<> 149:156823d33999 1266 * @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2
<> 149:156823d33999 1267 * @param DACx DAC instance
<> 149:156823d33999 1268 * @retval State of bit (1 or 0).
<> 149:156823d33999 1269 */
<> 149:156823d33999 1270 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx)
<> 149:156823d33999 1271 {
<> 149:156823d33999 1272 return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2));
<> 149:156823d33999 1273 }
<> 149:156823d33999 1274
<> 149:156823d33999 1275 /**
<> 149:156823d33999 1276 * @}
<> 149:156823d33999 1277 */
<> 149:156823d33999 1278
<> 149:156823d33999 1279 #if defined(USE_FULL_LL_DRIVER)
<> 149:156823d33999 1280 /** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions
<> 149:156823d33999 1281 * @{
<> 149:156823d33999 1282 */
<> 149:156823d33999 1283
<> 149:156823d33999 1284 ErrorStatus LL_DAC_DeInit(DAC_TypeDef* DACx);
<> 149:156823d33999 1285 ErrorStatus LL_DAC_Init(DAC_TypeDef* DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef* DAC_InitStruct);
<> 149:156823d33999 1286 void LL_DAC_StructInit(LL_DAC_InitTypeDef* DAC_InitStruct);
<> 149:156823d33999 1287
<> 149:156823d33999 1288 /**
<> 149:156823d33999 1289 * @}
<> 149:156823d33999 1290 */
<> 149:156823d33999 1291 #endif /* USE_FULL_LL_DRIVER */
<> 149:156823d33999 1292
<> 149:156823d33999 1293 /**
<> 149:156823d33999 1294 * @}
<> 149:156823d33999 1295 */
<> 149:156823d33999 1296
<> 149:156823d33999 1297 /**
<> 149:156823d33999 1298 * @}
<> 149:156823d33999 1299 */
<> 149:156823d33999 1300
<> 149:156823d33999 1301 #endif /* DAC1 */
<> 149:156823d33999 1302
<> 149:156823d33999 1303 /**
<> 149:156823d33999 1304 * @}
<> 149:156823d33999 1305 */
<> 149:156823d33999 1306
<> 149:156823d33999 1307 #ifdef __cplusplus
<> 149:156823d33999 1308 }
<> 149:156823d33999 1309 #endif
<> 149:156823d33999 1310
<> 149:156823d33999 1311 #endif /* __STM32L1xx_LL_DAC_H */
<> 149:156823d33999 1312
<> 149:156823d33999 1313 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/