mbed-STM - mbed library sources. Supersedes mbed-src.

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Fawwaz Nadzmy / mbed-STM

mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_tim.c@149:156823d33999, 2016-10-28 (annotated)

Committer:: <>
Date:: Fri Oct 28 11:17:30 2016 +0100
Revision:: 149:156823d33999

This updates the lib to the mbed lib v128

NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	149:156823d33999	1	/**
<>	149:156823d33999	2	******************************************************************************
<>	149:156823d33999	3	* @file stm32l1xx_hal_tim.c
<>	149:156823d33999	4	* @author MCD Application Team
<>	149:156823d33999	5	* @version V1.2.0
<>	149:156823d33999	6	* @date 01-July-2016
<>	149:156823d33999	7	* @brief TIM HAL module driver
<>	149:156823d33999	8	* This file provides firmware functions to manage the following
<>	149:156823d33999	9	* functionalities of the Timer (TIM) peripheral:
<>	149:156823d33999	10	* + Time Base Initialization
<>	149:156823d33999	11	* + Time Base Start
<>	149:156823d33999	12	* + Time Base Start Interruption
<>	149:156823d33999	13	* + Time Base Start DMA
<>	149:156823d33999	14	* + Time Output Compare/PWM Initialization
<>	149:156823d33999	15	* + Time Output Compare/PWM Channel Configuration
<>	149:156823d33999	16	* + Time Output Compare/PWM Start
<>	149:156823d33999	17	* + Time Output Compare/PWM Start Interruption
<>	149:156823d33999	18	* + Time Output Compare/PWM Start DMA
<>	149:156823d33999	19	* + Time Input Capture Initialization
<>	149:156823d33999	20	* + Time Input Capture Channel Configuration
<>	149:156823d33999	21	* + Time Input Capture Start
<>	149:156823d33999	22	* + Time Input Capture Start Interruption
<>	149:156823d33999	23	* + Time Input Capture Start DMA
<>	149:156823d33999	24	* + Time One Pulse Initialization
<>	149:156823d33999	25	* + Time One Pulse Channel Configuration
<>	149:156823d33999	26	* + Time One Pulse Start
<>	149:156823d33999	27	* + Time Encoder Interface Initialization
<>	149:156823d33999	28	* + Time Encoder Interface Start
<>	149:156823d33999	29	* + Time Encoder Interface Start Interruption
<>	149:156823d33999	30	* + Time Encoder Interface Start DMA
<>	149:156823d33999	31	* + Commutation Event configuration with Interruption and DMA
<>	149:156823d33999	32	* + Time OCRef clear configuration
<>	149:156823d33999	33	* + Time External Clock configuration
<>	149:156823d33999	34	* + Time Master and Slave synchronization configuration
<>	149:156823d33999	35	@verbatim
<>	149:156823d33999	36	==============================================================================
<>	149:156823d33999	37	##### TIMER Generic features #####
<>	149:156823d33999	38	==============================================================================
<>	149:156823d33999	39	[..] The Timer features include:
<>	149:156823d33999	40	(#) 16-bit up, down, up/down auto-reload counter.
<>	149:156823d33999	41	(#) 16-bit programmable prescaler allowing dividing (also on the fly) the
<>	149:156823d33999	42	counter clock frequency either by any factor between 1 and 65536.
<>	149:156823d33999	43	(#) Up to 4 independent channels for:
<>	149:156823d33999	44	(++) Input Capture
<>	149:156823d33999	45	(++) Output Compare
<>	149:156823d33999	46	(++) PWM generation (Edge and Center-aligned Mode)
<>	149:156823d33999	47	(++) One-pulse mode output
<>	149:156823d33999	48	(#) Synchronization circuit to control the timer with external signals and to interconnect
<>	149:156823d33999	49	several timers together.
<>	149:156823d33999	50	(#) Supports incremental (quadrature) encoder
<>	149:156823d33999	51
<>	149:156823d33999	52	##### How to use this driver #####
<>	149:156823d33999	53	================================================================================
<>	149:156823d33999	54	[..]
<>	149:156823d33999	55	(#) Initialize the TIM low level resources by implementing the following functions
<>	149:156823d33999	56	depending from feature used :
<>	149:156823d33999	57	(++) Time Base : HAL_TIM_Base_MspInit()
<>	149:156823d33999	58	(++) Input Capture : HAL_TIM_IC_MspInit()
<>	149:156823d33999	59	(++) Output Compare : HAL_TIM_OC_MspInit()
<>	149:156823d33999	60	(++) PWM generation : HAL_TIM_PWM_MspInit()
<>	149:156823d33999	61	(++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
<>	149:156823d33999	62	(++) Encoder mode output : HAL_TIM_Encoder_MspInit()
<>	149:156823d33999	63
<>	149:156823d33999	64	(#) Initialize the TIM low level resources :
<>	149:156823d33999	65	(##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
<>	149:156823d33999	66	(##) TIM pins configuration
<>	149:156823d33999	67	(+++) Enable the clock for the TIM GPIOs using the following function:
<>	149:156823d33999	68	__HAL_RCC_GPIOx_CLK_ENABLE();
<>	149:156823d33999	69	(+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
<>	149:156823d33999	70
<>	149:156823d33999	71	(#) The external Clock can be configured, if needed (the default clock is the
<>	149:156823d33999	72	internal clock from the APBx), using the following function:
<>	149:156823d33999	73	HAL_TIM_ConfigClockSource, the clock configuration should be done before
<>	149:156823d33999	74	any start function.
<>	149:156823d33999	75
<>	149:156823d33999	76	(#) Configure the TIM in the desired functioning mode using one of the
<>	149:156823d33999	77	Initialization function of this driver:
<>	149:156823d33999	78	(++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
<>	149:156823d33999	79	(++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
<>	149:156823d33999	80	Output Compare signal.
<>	149:156823d33999	81	(++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
<>	149:156823d33999	82	PWM signal.
<>	149:156823d33999	83	(++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
<>	149:156823d33999	84	external signal.
<>	149:156823d33999	85	(++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
<>	149:156823d33999	86	in One Pulse Mode.
<>	149:156823d33999	87	(++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
<>	149:156823d33999	88
<>	149:156823d33999	89	(#) Activate the TIM peripheral using one of the start functions depending from the feature used:
<>	149:156823d33999	90	(++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
<>	149:156823d33999	91	(++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
<>	149:156823d33999	92	(++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
<>	149:156823d33999	93	(++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
<>	149:156823d33999	94	(++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
<>	149:156823d33999	95	(++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
<>	149:156823d33999	96
<>	149:156823d33999	97	(#) The DMA Burst is managed with the two following functions:
<>	149:156823d33999	98	HAL_TIM_DMABurst_WriteStart()
<>	149:156823d33999	99	HAL_TIM_DMABurst_ReadStart()
<>	149:156823d33999	100
<>	149:156823d33999	101	@endverbatim
<>	149:156823d33999	102	******************************************************************************
<>	149:156823d33999	103	* @attention
<>	149:156823d33999	104	*
<>	149:156823d33999	105	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	149:156823d33999	106	*
<>	149:156823d33999	107	* Redistribution and use in source and binary forms, with or without modification,
<>	149:156823d33999	108	* are permitted provided that the following conditions are met:
<>	149:156823d33999	109	* 1. Redistributions of source code must retain the above copyright notice,
<>	149:156823d33999	110	* this list of conditions and the following disclaimer.
<>	149:156823d33999	111	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	149:156823d33999	112	* this list of conditions and the following disclaimer in the documentation
<>	149:156823d33999	113	* and/or other materials provided with the distribution.
<>	149:156823d33999	114	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	149:156823d33999	115	* may be used to endorse or promote products derived from this software
<>	149:156823d33999	116	* without specific prior written permission.
<>	149:156823d33999	117	*
<>	149:156823d33999	118	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	149:156823d33999	119	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	149:156823d33999	120	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	149:156823d33999	121	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	149:156823d33999	122	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	149:156823d33999	123	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	149:156823d33999	124	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	149:156823d33999	125	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	149:156823d33999	126	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	149:156823d33999	127	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	149:156823d33999	128	*
<>	149:156823d33999	129	******************************************************************************
<>	149:156823d33999	130	*/
<>	149:156823d33999	131
<>	149:156823d33999	132	/* Includes ------------------------------------------------------------------*/
<>	149:156823d33999	133	#include "stm32l1xx_hal.h"
<>	149:156823d33999	134
<>	149:156823d33999	135	/** @addtogroup STM32L1xx_HAL_Driver
<>	149:156823d33999	136	* @{
<>	149:156823d33999	137	*/
<>	149:156823d33999	138
<>	149:156823d33999	139	/** @defgroup TIM TIM
<>	149:156823d33999	140	* @brief TIM HAL module driver
<>	149:156823d33999	141	* @{
<>	149:156823d33999	142	*/
<>	149:156823d33999	143
<>	149:156823d33999	144	#ifdef HAL_TIM_MODULE_ENABLED
<>	149:156823d33999	145
<>	149:156823d33999	146	/* Private typedef -----------------------------------------------------------*/
<>	149:156823d33999	147	/* Private define ------------------------------------------------------------*/
<>	149:156823d33999	148	/* Private macro -------------------------------------------------------------*/
<>	149:156823d33999	149	/* Private variables ---------------------------------------------------------*/
<>	149:156823d33999	150	/* Private function prototypes -----------------------------------------------*/
<>	149:156823d33999	151	/** @defgroup TIM_Private_Functions TIM Private Functions
<>	149:156823d33999	152	* @{
<>	149:156823d33999	153	*/
<>	149:156823d33999	154	static void TIM_Base_SetConfig(TIM_TypeDef TIMx, TIM_Base_InitTypeDef Structure);
<>	149:156823d33999	155	static void TIM_OC1_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
<>	149:156823d33999	156	static void TIM_OC2_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
<>	149:156823d33999	157	static void TIM_OC3_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
<>	149:156823d33999	158	static void TIM_OC4_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
<>	149:156823d33999	159	static void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
<>	149:156823d33999	160	static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
<>	149:156823d33999	161	static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
<>	149:156823d33999	162	static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
<>	149:156823d33999	163	static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
<>	149:156823d33999	164	static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
<>	149:156823d33999	165	static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
<>	149:156823d33999	166	static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t InputTriggerSource);
<>	149:156823d33999	167	static void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
<>	149:156823d33999	168	static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
<>	149:156823d33999	169	static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
<>	149:156823d33999	170	static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig);
<>	149:156823d33999	171
<>	149:156823d33999	172	/**
<>	149:156823d33999	173	* @}
<>	149:156823d33999	174	*/
<>	149:156823d33999	175
<>	149:156823d33999	176	/* Exported functions ---------------------------------------------------------*/
<>	149:156823d33999	177
<>	149:156823d33999	178	/** @defgroup TIM_Exported_Functions TIM Exported Functions
<>	149:156823d33999	179	* @{
<>	149:156823d33999	180	*/
<>	149:156823d33999	181
<>	149:156823d33999	182	/** @defgroup TIM_Exported_Functions_Group1 Time Base functions
<>	149:156823d33999	183	* @brief Time Base functions
<>	149:156823d33999	184	*
<>	149:156823d33999	185	@verbatim
<>	149:156823d33999	186	==============================================================================
<>	149:156823d33999	187	##### Time Base functions #####
<>	149:156823d33999	188	==============================================================================
<>	149:156823d33999	189	[..]
<>	149:156823d33999	190	This section provides functions allowing to:
<>	149:156823d33999	191	(+) Initialize and configure the TIM base.
<>	149:156823d33999	192	(+) De-initialize the TIM base.
<>	149:156823d33999	193	(+) Start the Time Base.
<>	149:156823d33999	194	(+) Stop the Time Base.
<>	149:156823d33999	195	(+) Start the Time Base and enable interrupt.
<>	149:156823d33999	196	(+) Stop the Time Base and disable interrupt.
<>	149:156823d33999	197	(+) Start the Time Base and enable DMA transfer.
<>	149:156823d33999	198	(+) Stop the Time Base and disable DMA transfer.
<>	149:156823d33999	199
<>	149:156823d33999	200	@endverbatim
<>	149:156823d33999	201	* @{
<>	149:156823d33999	202	*/
<>	149:156823d33999	203	/**
<>	149:156823d33999	204	* @brief Initializes the TIM Time base Unit according to the specified
<>	149:156823d33999	205	* parameters in the TIM_HandleTypeDef and create the associated handle.
<>	149:156823d33999	206	* @param htim: TIM Base handle
<>	149:156823d33999	207	* @retval HAL status
<>	149:156823d33999	208	*/
<>	149:156823d33999	209	HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
<>	149:156823d33999	210	{
<>	149:156823d33999	211	/* Check the TIM handle allocation */
<>	149:156823d33999	212	if(htim == NULL)
<>	149:156823d33999	213	{
<>	149:156823d33999	214	return HAL_ERROR;
<>	149:156823d33999	215	}
<>	149:156823d33999	216
<>	149:156823d33999	217	/* Check the parameters */
<>	149:156823d33999	218	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	149:156823d33999	219	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
<>	149:156823d33999	220	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
<>	149:156823d33999	221
<>	149:156823d33999	222	if(htim->State == HAL_TIM_STATE_RESET)
<>	149:156823d33999	223	{
<>	149:156823d33999	224	/* Allocate lock resource and initialize it */
<>	149:156823d33999	225	htim->Lock = HAL_UNLOCKED;
<>	149:156823d33999	226
<>	149:156823d33999	227	/* Init the low level hardware : GPIO, CLOCK, NVIC */
<>	149:156823d33999	228	HAL_TIM_Base_MspInit(htim);
<>	149:156823d33999	229	}
<>	149:156823d33999	230
<>	149:156823d33999	231	/* Set the TIM state */
<>	149:156823d33999	232	htim->State= HAL_TIM_STATE_BUSY;
<>	149:156823d33999	233
<>	149:156823d33999	234	/* Set the Time Base configuration */
<>	149:156823d33999	235	TIM_Base_SetConfig(htim->Instance, &htim->Init);
<>	149:156823d33999	236
<>	149:156823d33999	237	/* Initialize the TIM state*/
<>	149:156823d33999	238	htim->State= HAL_TIM_STATE_READY;
<>	149:156823d33999	239
<>	149:156823d33999	240	return HAL_OK;
<>	149:156823d33999	241	}
<>	149:156823d33999	242
<>	149:156823d33999	243	/**
<>	149:156823d33999	244	* @brief DeInitializes the TIM Base peripheral
<>	149:156823d33999	245	* @param htim: TIM Base handle
<>	149:156823d33999	246	* @retval HAL status
<>	149:156823d33999	247	*/
<>	149:156823d33999	248	HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
<>	149:156823d33999	249	{
<>	149:156823d33999	250	/* Check the parameters */
<>	149:156823d33999	251	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	149:156823d33999	252
<>	149:156823d33999	253	htim->State = HAL_TIM_STATE_BUSY;
<>	149:156823d33999	254
<>	149:156823d33999	255	/* Disable the TIM Peripheral Clock */
<>	149:156823d33999	256	__HAL_TIM_DISABLE(htim);
<>	149:156823d33999	257
<>	149:156823d33999	258	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
<>	149:156823d33999	259	HAL_TIM_Base_MspDeInit(htim);
<>	149:156823d33999	260
<>	149:156823d33999	261	/* Change TIM state */
<>	149:156823d33999	262	htim->State = HAL_TIM_STATE_RESET;
<>	149:156823d33999	263
<>	149:156823d33999	264	/* Release Lock */
<>	149:156823d33999	265	__HAL_UNLOCK(htim);
<>	149:156823d33999	266
<>	149:156823d33999	267	return HAL_OK;
<>	149:156823d33999	268	}
<>	149:156823d33999	269
<>	149:156823d33999	270	/**
<>	149:156823d33999	271	* @brief Initializes the TIM Base MSP.
<>	149:156823d33999	272	* @param htim: TIM handle
<>	149:156823d33999	273	* @retval None
<>	149:156823d33999	274	*/
<>	149:156823d33999	275	__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
<>	149:156823d33999	276	{
<>	149:156823d33999	277	/* Prevent unused argument(s) compilation warning */
<>	149:156823d33999	278	UNUSED(htim);
<>	149:156823d33999	279
<>	149:156823d33999	280	/* NOTE : This function Should not be modified, when the callback is needed,
<>	149:156823d33999	281	the HAL_TIM_Base_MspInit could be implemented in the user file
<>	149:156823d33999	282	*/
<>	149:156823d33999	283	}
<>	149:156823d33999	284
<>	149:156823d33999	285	/**
<>	149:156823d33999	286	* @brief DeInitializes TIM Base MSP.
<>	149:156823d33999	287	* @param htim: TIM handle
<>	149:156823d33999	288	* @retval None
<>	149:156823d33999	289	*/
<>	149:156823d33999	290	__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
<>	149:156823d33999	291	{
<>	149:156823d33999	292	/* Prevent unused argument(s) compilation warning */
<>	149:156823d33999	293	UNUSED(htim);
<>	149:156823d33999	294
<>	149:156823d33999	295	/* NOTE : This function Should not be modified, when the callback is needed,
<>	149:156823d33999	296	the HAL_TIM_Base_MspDeInit could be implemented in the user file
<>	149:156823d33999	297	*/
<>	149:156823d33999	298	}
<>	149:156823d33999	299
<>	149:156823d33999	300
<>	149:156823d33999	301	/**
<>	149:156823d33999	302	* @brief Starts the TIM Base generation.
<>	149:156823d33999	303	* @param htim : TIM handle
<>	149:156823d33999	304	* @retval HAL status
<>	149:156823d33999	305	*/
<>	149:156823d33999	306	HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
<>	149:156823d33999	307	{
<>	149:156823d33999	308	/* Check the parameters */
<>	149:156823d33999	309	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	149:156823d33999	310
<>	149:156823d33999	311	/* Set the TIM state */
<>	149:156823d33999	312	htim->State= HAL_TIM_STATE_BUSY;
<>	149:156823d33999	313
<>	149:156823d33999	314	/* Enable the Peripheral */
<>	149:156823d33999	315	__HAL_TIM_ENABLE(htim);
<>	149:156823d33999	316
<>	149:156823d33999	317	/* Change the TIM state*/
<>	149:156823d33999	318	htim->State= HAL_TIM_STATE_READY;
<>	149:156823d33999	319
<>	149:156823d33999	320	/* Return function status */
<>	149:156823d33999	321	return HAL_OK;
<>	149:156823d33999	322	}
<>	149:156823d33999	323
<>	149:156823d33999	324	/**
<>	149:156823d33999	325	* @brief Stops the TIM Base generation.
<>	149:156823d33999	326	* @param htim : TIM handle
<>	149:156823d33999	327	* @retval HAL status
<>	149:156823d33999	328	*/
<>	149:156823d33999	329	HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
<>	149:156823d33999	330	{
<>	149:156823d33999	331	/* Check the parameters */
<>	149:156823d33999	332	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	149:156823d33999	333
<>	149:156823d33999	334	/* Set the TIM state */
<>	149:156823d33999	335	htim->State= HAL_TIM_STATE_BUSY;
<>	149:156823d33999	336
<>	149:156823d33999	337	/* Disable the Peripheral */
<>	149:156823d33999	338	__HAL_TIM_DISABLE(htim);
<>	149:156823d33999	339
<>	149:156823d33999	340	/* Change the TIM state*/
<>	149:156823d33999	341	htim->State= HAL_TIM_STATE_READY;
<>	149:156823d33999	342
<>	149:156823d33999	343	/* Return function status */
<>	149:156823d33999	344	return HAL_OK;
<>	149:156823d33999	345	}
<>	149:156823d33999	346
<>	149:156823d33999	347	/**
<>	149:156823d33999	348	* @brief Starts the TIM Base generation in interrupt mode.
<>	149:156823d33999	349	* @param htim : TIM handle
<>	149:156823d33999	350	* @retval HAL status
<>	149:156823d33999	351	*/
<>	149:156823d33999	352	HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
<>	149:156823d33999	353	{
<>	149:156823d33999	354	/* Check the parameters */
<>	149:156823d33999	355	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	149:156823d33999	356
<>	149:156823d33999	357	/* Enable the TIM Update interrupt */
<>	149:156823d33999	358	__HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
<>	149:156823d33999	359
<>	149:156823d33999	360	/* Enable the Peripheral */
<>	149:156823d33999	361	__HAL_TIM_ENABLE(htim);
<>	149:156823d33999	362
<>	149:156823d33999	363	/* Return function status */
<>	149:156823d33999	364	return HAL_OK;
<>	149:156823d33999	365	}
<>	149:156823d33999	366
<>	149:156823d33999	367	/**
<>	149:156823d33999	368	* @brief Stops the TIM Base generation in interrupt mode.
<>	149:156823d33999	369	* @param htim : TIM handle
<>	149:156823d33999	370	* @retval HAL status
<>	149:156823d33999	371	*/
<>	149:156823d33999	372	HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
<>	149:156823d33999	373	{
<>	149:156823d33999	374	/* Check the parameters */
<>	149:156823d33999	375	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	149:156823d33999	376	/* Disable the TIM Update interrupt */
<>	149:156823d33999	377	__HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
<>	149:156823d33999	378
<>	149:156823d33999	379	/* Disable the Peripheral */
<>	149:156823d33999	380	__HAL_TIM_DISABLE(htim);
<>	149:156823d33999	381
<>	149:156823d33999	382	/* Return function status */
<>	149:156823d33999	383	return HAL_OK;
<>	149:156823d33999	384	}
<>	149:156823d33999	385
<>	149:156823d33999	386	/**
<>	149:156823d33999	387	* @brief Starts the TIM Base generation in DMA mode.
<>	149:156823d33999	388	* @param htim : TIM handle
<>	149:156823d33999	389	* @param pData: The source Buffer address.
<>	149:156823d33999	390	* @param Length: The length of data to be transferred from memory to peripheral.
<>	149:156823d33999	391	* @retval HAL status
<>	149:156823d33999	392	*/
<>	149:156823d33999	393	HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef htim, uint32_t pData, uint16_t Length)
<>	149:156823d33999	394	{
<>	149:156823d33999	395	/* Check the parameters */
<>	149:156823d33999	396	assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
<>	149:156823d33999	397
<>	149:156823d33999	398	if((htim->State == HAL_TIM_STATE_BUSY))
<>	149:156823d33999	399	{
<>	149:156823d33999	400	return HAL_BUSY;
<>	149:156823d33999	401	}
<>	149:156823d33999	402	else if((htim->State == HAL_TIM_STATE_READY))
<>	149:156823d33999	403	{
<>	149:156823d33999	404	if((pData == 0 ) && (Length > 0))
<>	149:156823d33999	405	{
<>	149:156823d33999	406	return HAL_ERROR;
<>	149:156823d33999	407	}
<>	149:156823d33999	408	else
<>	149:156823d33999	409	{
<>	149:156823d33999	410	htim->State = HAL_TIM_STATE_BUSY;
<>	149:156823d33999	411	}
<>	149:156823d33999	412	}
<>	149:156823d33999	413	else
<>	149:156823d33999	414	{
<>	149:156823d33999	415	return HAL_ERROR;
<>	149:156823d33999	416	}
<>	149:156823d33999	417
<>	149:156823d33999	418	/* Set the DMA Period elapsed callback */
<>	149:156823d33999	419	htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
<>	149:156823d33999	420
<>	149:156823d33999	421	/* Set the DMA error callback */
<>	149:156823d33999	422	htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
<>	149:156823d33999	423
<>	149:156823d33999	424	/* Enable the DMA channel */
<>	149:156823d33999	425	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
<>	149:156823d33999	426
<>	149:156823d33999	427	/* Enable the TIM Update DMA request */
<>	149:156823d33999	428	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
<>	149:156823d33999	429
<>	149:156823d33999	430	/* Enable the Peripheral */
<>	149:156823d33999	431	__HAL_TIM_ENABLE(htim);
<>	149:156823d33999	432
<>	149:156823d33999	433	/* Return function status */
<>	149:156823d33999	434	return HAL_OK;
<>	149:156823d33999	435	}
<>	149:156823d33999	436
<>	149:156823d33999	437	/**
<>	149:156823d33999	438	* @brief Stops the TIM Base generation in DMA mode.
<>	149:156823d33999	439	* @param htim : TIM handle
<>	149:156823d33999	440	* @retval HAL status
<>	149:156823d33999	441	*/
<>	149:156823d33999	442	HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
<>	149:156823d33999	443	{
<>	149:156823d33999	444	/* Check the parameters */
<>	149:156823d33999	445	assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
<>	149:156823d33999	446
<>	149:156823d33999	447	/* Disable the TIM Update DMA request */
<>	149:156823d33999	448	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
<>	149:156823d33999	449
<>	149:156823d33999	450	/* Disable the Peripheral */
<>	149:156823d33999	451	__HAL_TIM_DISABLE(htim);
<>	149:156823d33999	452
<>	149:156823d33999	453	/* Change the htim state */
<>	149:156823d33999	454	htim->State = HAL_TIM_STATE_READY;
<>	149:156823d33999	455
<>	149:156823d33999	456	/* Return function status */
<>	149:156823d33999	457	return HAL_OK;
<>	149:156823d33999	458	}
<>	149:156823d33999	459
<>	149:156823d33999	460	/**
<>	149:156823d33999	461	* @}
<>	149:156823d33999	462	*/
<>	149:156823d33999	463
<>	149:156823d33999	464	/** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions
<>	149:156823d33999	465	* @brief Time Output Compare functions
<>	149:156823d33999	466	*
<>	149:156823d33999	467	@verbatim
<>	149:156823d33999	468	==============================================================================
<>	149:156823d33999	469	##### Time Output Compare functions #####
<>	149:156823d33999	470	==============================================================================
<>	149:156823d33999	471	[..]
<>	149:156823d33999	472	This section provides functions allowing to:
<>	149:156823d33999	473	(+) Initialize and configure the TIM Output Compare.
<>	149:156823d33999	474	(+) De-initialize the TIM Output Compare.
<>	149:156823d33999	475	(+) Start the Time Output Compare.
<>	149:156823d33999	476	(+) Stop the Time Output Compare.
<>	149:156823d33999	477	(+) Start the Time Output Compare and enable interrupt.
<>	149:156823d33999	478	(+) Stop the Time Output Compare and disable interrupt.
<>	149:156823d33999	479	(+) Start the Time Output Compare and enable DMA transfer.
<>	149:156823d33999	480	(+) Stop the Time Output Compare and disable DMA transfer.
<>	149:156823d33999	481
<>	149:156823d33999	482	@endverbatim
<>	149:156823d33999	483	* @{
<>	149:156823d33999	484	*/
<>	149:156823d33999	485	/**
<>	149:156823d33999	486	* @brief Initializes the TIM Output Compare according to the specified
<>	149:156823d33999	487	* parameters in the TIM_HandleTypeDef and create the associated handle.
<>	149:156823d33999	488	* @param htim: TIM Output Compare handle
<>	149:156823d33999	489	* @retval HAL status
<>	149:156823d33999	490	*/
<>	149:156823d33999	491	HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
<>	149:156823d33999	492	{
<>	149:156823d33999	493	/* Check the TIM handle allocation */
<>	149:156823d33999	494	if(htim == NULL)
<>	149:156823d33999	495	{
<>	149:156823d33999	496	return HAL_ERROR;
<>	149:156823d33999	497	}
<>	149:156823d33999	498
<>	149:156823d33999	499	/* Check the parameters */
<>	149:156823d33999	500	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	149:156823d33999	501	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
<>	149:156823d33999	502	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
<>	149:156823d33999	503
<>	149:156823d33999	504	if(htim->State == HAL_TIM_STATE_RESET)
<>	149:156823d33999	505	{
<>	149:156823d33999	506	/* Allocate lock resource and initialize it */
<>	149:156823d33999	507	htim->Lock = HAL_UNLOCKED;
<>	149:156823d33999	508
<>	149:156823d33999	509	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
<>	149:156823d33999	510	HAL_TIM_OC_MspInit(htim);
<>	149:156823d33999	511	}
<>	149:156823d33999	512
<>	149:156823d33999	513	/* Set the TIM state */
<>	149:156823d33999	514	htim->State= HAL_TIM_STATE_BUSY;
<>	149:156823d33999	515
<>	149:156823d33999	516	/* Init the base time for the Output Compare */
<>	149:156823d33999	517	TIM_Base_SetConfig(htim->Instance, &htim->Init);
<>	149:156823d33999	518
<>	149:156823d33999	519	/* Initialize the TIM state*/
<>	149:156823d33999	520	htim->State= HAL_TIM_STATE_READY;
<>	149:156823d33999	521
<>	149:156823d33999	522	return HAL_OK;
<>	149:156823d33999	523	}
<>	149:156823d33999	524
<>	149:156823d33999	525	/**
<>	149:156823d33999	526	* @brief DeInitializes the TIM peripheral
<>	149:156823d33999	527	* @param htim: TIM Output Compare handle
<>	149:156823d33999	528	* @retval HAL status
<>	149:156823d33999	529	*/
<>	149:156823d33999	530	HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
<>	149:156823d33999	531	{
<>	149:156823d33999	532	/* Check the parameters */
<>	149:156823d33999	533	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	149:156823d33999	534
<>	149:156823d33999	535	htim->State = HAL_TIM_STATE_BUSY;
<>	149:156823d33999	536
<>	149:156823d33999	537	/* Disable the TIM Peripheral Clock */
<>	149:156823d33999	538	__HAL_TIM_DISABLE(htim);
<>	149:156823d33999	539
<>	149:156823d33999	540	/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
<>	149:156823d33999	541	HAL_TIM_OC_MspDeInit(htim);
<>	149:156823d33999	542
<>	149:156823d33999	543	/* Change TIM state */
<>	149:156823d33999	544	htim->State = HAL_TIM_STATE_RESET;
<>	149:156823d33999	545
<>	149:156823d33999	546	/* Release Lock */
<>	149:156823d33999	547	__HAL_UNLOCK(htim);
<>	149:156823d33999	548
<>	149:156823d33999	549	return HAL_OK;
<>	149:156823d33999	550	}
<>	149:156823d33999	551
<>	149:156823d33999	552	/**
<>	149:156823d33999	553	* @brief Initializes the TIM Output Compare MSP.
<>	149:156823d33999	554	* @param htim: TIM handle
<>	149:156823d33999	555	* @retval None
<>	149:156823d33999	556	*/
<>	149:156823d33999	557	__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
<>	149:156823d33999	558	{
<>	149:156823d33999	559	/* Prevent unused argument(s) compilation warning */
<>	149:156823d33999	560	UNUSED(htim);
<>	149:156823d33999	561
<>	149:156823d33999	562	/* NOTE : This function Should not be modified, when the callback is needed,
<>	149:156823d33999	563	the HAL_TIM_OC_MspInit could be implemented in the user file
<>	149:156823d33999	564	*/
<>	149:156823d33999	565	}
<>	149:156823d33999	566
<>	149:156823d33999	567	/**
<>	149:156823d33999	568	* @brief DeInitializes TIM Output Compare MSP.
<>	149:156823d33999	569	* @param htim: TIM handle
<>	149:156823d33999	570	* @retval None
<>	149:156823d33999	571	*/
<>	149:156823d33999	572	__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
<>	149:156823d33999	573	{
<>	149:156823d33999	574	/* Prevent unused argument(s) compilation warning */
<>	149:156823d33999	575	UNUSED(htim);
<>	149:156823d33999	576
<>	149:156823d33999	577	/* NOTE : This function Should not be modified, when the callback is needed,
<>	149:156823d33999	578	the HAL_TIM_OC_MspDeInit could be implemented in the user file
<>	149:156823d33999	579	*/
<>	149:156823d33999	580	}
<>	149:156823d33999	581
<>	149:156823d33999	582	/**
<>	149:156823d33999	583	* @brief Starts the TIM Output Compare signal generation.
<>	149:156823d33999	584	* @param htim : TIM Output Compare handle
<>	149:156823d33999	585	* @param Channel : TIM Channel to be enabled
<>	149:156823d33999	586	* This parameter can be one of the following values:
<>	149:156823d33999	587	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	149:156823d33999	588	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	149:156823d33999	589	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	149:156823d33999	590	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	149:156823d33999	591	* @retval HAL status
<>	149:156823d33999	592	*/
<>	149:156823d33999	593	HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	149:156823d33999	594	{
<>	149:156823d33999	595	/* Check the parameters */
<>	149:156823d33999	596	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	149:156823d33999	597
<>	149:156823d33999	598	/* Enable the Output compare channel */
<>	149:156823d33999	599	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<>	149:156823d33999	600
<>	149:156823d33999	601	/* Enable the Peripheral */
<>	149:156823d33999	602	__HAL_TIM_ENABLE(htim);
<>	149:156823d33999	603
<>	149:156823d33999	604	/* Return function status */
<>	149:156823d33999	605	return HAL_OK;
<>	149:156823d33999	606	}
<>	149:156823d33999	607
<>	149:156823d33999	608	/**
<>	149:156823d33999	609	* @brief Stops the TIM Output Compare signal generation.
<>	149:156823d33999	610	* @param htim : TIM handle
<>	149:156823d33999	611	* @param Channel : TIM Channel to be disabled
<>	149:156823d33999	612	* This parameter can be one of the following values:
<>	149:156823d33999	613	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	149:156823d33999	614	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	149:156823d33999	615	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	149:156823d33999	616	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	149:156823d33999	617	* @retval HAL status
<>	149:156823d33999	618	*/
<>	149:156823d33999	619	HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	149:156823d33999	620	{
<>	149:156823d33999	621	/* Check the parameters */
<>	149:156823d33999	622	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	149:156823d33999	623
<>	149:156823d33999	624	/* Disable the Output compare channel */
<>	149:156823d33999	625	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<>	149:156823d33999	626
<>	149:156823d33999	627	/* Disable the Peripheral */
<>	149:156823d33999	628	__HAL_TIM_DISABLE(htim);
<>	149:156823d33999	629
<>	149:156823d33999	630	/* Return function status */
<>	149:156823d33999	631	return HAL_OK;
<>	149:156823d33999	632	}
<>	149:156823d33999	633
<>	149:156823d33999	634	/**
<>	149:156823d33999	635	* @brief Starts the TIM Output Compare signal generation in interrupt mode.
<>	149:156823d33999	636	* @param htim : TIM OC handle
<>	149:156823d33999	637	* @param Channel : TIM Channel to be enabled
<>	149:156823d33999	638	* This parameter can be one of the following values:
<>	149:156823d33999	639	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	149:156823d33999	640	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	149:156823d33999	641	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	149:156823d33999	642	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	149:156823d33999	643	* @retval HAL status
<>	149:156823d33999	644	*/
<>	149:156823d33999	645	HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	149:156823d33999	646	{
<>	149:156823d33999	647	/* Check the parameters */
<>	149:156823d33999	648	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	149:156823d33999	649
<>	149:156823d33999	650	switch (Channel)
<>	149:156823d33999	651	{
<>	149:156823d33999	652	case TIM_CHANNEL_1:
<>	149:156823d33999	653	{
<>	149:156823d33999	654	/* Enable the TIM Capture/Compare 1 interrupt */
<>	149:156823d33999	655	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<>	149:156823d33999	656	}
<>	149:156823d33999	657	break;
<>	149:156823d33999	658
<>	149:156823d33999	659	case TIM_CHANNEL_2:
<>	149:156823d33999	660	{
<>	149:156823d33999	661	/* Enable the TIM Capture/Compare 2 interrupt */
<>	149:156823d33999	662	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<>	149:156823d33999	663	}
<>	149:156823d33999	664	break;
<>	149:156823d33999	665
<>	149:156823d33999	666	case TIM_CHANNEL_3:
<>	149:156823d33999	667	{
<>	149:156823d33999	668	/* Enable the TIM Capture/Compare 3 interrupt */
<>	149:156823d33999	669	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
<>	149:156823d33999	670	}
<>	149:156823d33999	671	break;
<>	149:156823d33999	672
<>	149:156823d33999	673	case TIM_CHANNEL_4:
<>	149:156823d33999	674	{
<>	149:156823d33999	675	/* Enable the TIM Capture/Compare 4 interrupt */
<>	149:156823d33999	676	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
<>	149:156823d33999	677	}
<>	149:156823d33999	678	break;
<>	149:156823d33999	679
<>	149:156823d33999	680	default:
<>	149:156823d33999	681	break;
<>	149:156823d33999	682	}
<>	149:156823d33999	683
<>	149:156823d33999	684	/* Enable the Output compare channel */
<>	149:156823d33999	685	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<>	149:156823d33999	686
<>	149:156823d33999	687	/* Enable the Peripheral */
<>	149:156823d33999	688	__HAL_TIM_ENABLE(htim);
<>	149:156823d33999	689
<>	149:156823d33999	690	/* Return function status */
<>	149:156823d33999	691	return HAL_OK;
<>	149:156823d33999	692	}
<>	149:156823d33999	693
<>	149:156823d33999	694	/**
<>	149:156823d33999	695	* @brief Stops the TIM Output Compare signal generation in interrupt mode.
<>	149:156823d33999	696	* @param htim : TIM Output Compare handle
<>	149:156823d33999	697	* @param Channel : TIM Channel to be disabled
<>	149:156823d33999	698	* This parameter can be one of the following values:
<>	149:156823d33999	699	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	149:156823d33999	700	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	149:156823d33999	701	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	149:156823d33999	702	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	149:156823d33999	703	* @retval HAL status
<>	149:156823d33999	704	*/
<>	149:156823d33999	705	HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	149:156823d33999	706	{
<>	149:156823d33999	707	/* Check the parameters */
<>	149:156823d33999	708	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	149:156823d33999	709
<>	149:156823d33999	710	switch (Channel)
<>	149:156823d33999	711	{
<>	149:156823d33999	712	case TIM_CHANNEL_1:
<>	149:156823d33999	713	{
<>	149:156823d33999	714	/* Disable the TIM Capture/Compare 1 interrupt */
<>	149:156823d33999	715	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<>	149:156823d33999	716	}
<>	149:156823d33999	717	break;
<>	149:156823d33999	718
<>	149:156823d33999	719	case TIM_CHANNEL_2:
<>	149:156823d33999	720	{
<>	149:156823d33999	721	/* Disable the TIM Capture/Compare 2 interrupt */
<>	149:156823d33999	722	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<>	149:156823d33999	723	}
<>	149:156823d33999	724	break;
<>	149:156823d33999	725
<>	149:156823d33999	726	case TIM_CHANNEL_3:
<>	149:156823d33999	727	{
<>	149:156823d33999	728	/* Disable the TIM Capture/Compare 3 interrupt */
<>	149:156823d33999	729	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
<>	149:156823d33999	730	}
<>	149:156823d33999	731	break;
<>	149:156823d33999	732
<>	149:156823d33999	733	case TIM_CHANNEL_4:
<>	149:156823d33999	734	{
<>	149:156823d33999	735	/* Disable the TIM Capture/Compare 4 interrupt */
<>	149:156823d33999	736	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
<>	149:156823d33999	737	}
<>	149:156823d33999	738	break;
<>	149:156823d33999	739
<>	149:156823d33999	740	default:
<>	149:156823d33999	741	break;
<>	149:156823d33999	742	}
<>	149:156823d33999	743
<>	149:156823d33999	744	/* Disable the Output compare channel */
<>	149:156823d33999	745	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<>	149:156823d33999	746
<>	149:156823d33999	747	/* Disable the Peripheral */
<>	149:156823d33999	748	__HAL_TIM_DISABLE(htim);
<>	149:156823d33999	749
<>	149:156823d33999	750	/* Return function status */
<>	149:156823d33999	751	return HAL_OK;
<>	149:156823d33999	752	}
<>	149:156823d33999	753
<>	149:156823d33999	754	/**
<>	149:156823d33999	755	* @brief Starts the TIM Output Compare signal generation in DMA mode.
<>	149:156823d33999	756	* @param htim : TIM Output Compare handle
<>	149:156823d33999	757	* @param Channel : TIM Channel to be enabled
<>	149:156823d33999	758	* This parameter can be one of the following values:
<>	149:156823d33999	759	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	149:156823d33999	760	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	149:156823d33999	761	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	149:156823d33999	762	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	149:156823d33999	763	* @param pData: The source Buffer address.
<>	149:156823d33999	764	* @param Length: The length of data to be transferred from memory to TIM peripheral
<>	149:156823d33999	765	* @retval HAL status
<>	149:156823d33999	766	*/
<>	149:156823d33999	767	HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length)
<>	149:156823d33999	768	{
<>	149:156823d33999	769	/* Check the parameters */
<>	149:156823d33999	770	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	149:156823d33999	771
<>	149:156823d33999	772	if((htim->State == HAL_TIM_STATE_BUSY))
<>	149:156823d33999	773	{
<>	149:156823d33999	774	return HAL_BUSY;
<>	149:156823d33999	775	}
<>	149:156823d33999	776	else if((htim->State == HAL_TIM_STATE_READY))
<>	149:156823d33999	777	{
<>	149:156823d33999	778	if(((uint32_t)pData == 0 ) && (Length > 0))
<>	149:156823d33999	779	{
<>	149:156823d33999	780	return HAL_ERROR;
<>	149:156823d33999	781	}
<>	149:156823d33999	782	else
<>	149:156823d33999	783	{
<>	149:156823d33999	784	htim->State = HAL_TIM_STATE_BUSY;
<>	149:156823d33999	785	}
<>	149:156823d33999	786	}
<>	149:156823d33999	787	else
<>	149:156823d33999	788	{
<>	149:156823d33999	789	return HAL_ERROR;
<>	149:156823d33999	790	}
<>	149:156823d33999	791
<>	149:156823d33999	792	switch (Channel)
<>	149:156823d33999	793	{
<>	149:156823d33999	794	case TIM_CHANNEL_1:
<>	149:156823d33999	795	{
<>	149:156823d33999	796	/* Set the DMA Period elapsed callback */
<>	149:156823d33999	797	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
<>	149:156823d33999	798
<>	149:156823d33999	799	/* Set the DMA error callback */
<>	149:156823d33999	800	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<>	149:156823d33999	801
<>	149:156823d33999	802	/* Enable the DMA channel */
<>	149:156823d33999	803	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
<>	149:156823d33999	804
<>	149:156823d33999	805	/* Enable the TIM Capture/Compare 1 DMA request */
<>	149:156823d33999	806	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<>	149:156823d33999	807	}
<>	149:156823d33999	808	break;
<>	149:156823d33999	809
<>	149:156823d33999	810	case TIM_CHANNEL_2:
<>	149:156823d33999	811	{
<>	149:156823d33999	812	/* Set the DMA Period elapsed callback */
<>	149:156823d33999	813	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
<>	149:156823d33999	814
<>	149:156823d33999	815	/* Set the DMA error callback */
<>	149:156823d33999	816	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<>	149:156823d33999	817
<>	149:156823d33999	818	/* Enable the DMA channel */
<>	149:156823d33999	819	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
<>	149:156823d33999	820
<>	149:156823d33999	821	/* Enable the TIM Capture/Compare 2 DMA request */
<>	149:156823d33999	822	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<>	149:156823d33999	823	}
<>	149:156823d33999	824	break;
<>	149:156823d33999	825
<>	149:156823d33999	826	case TIM_CHANNEL_3:
<>	149:156823d33999	827	{
<>	149:156823d33999	828	/* Set the DMA Period elapsed callback */
<>	149:156823d33999	829	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
<>	149:156823d33999	830
<>	149:156823d33999	831	/* Set the DMA error callback */
<>	149:156823d33999	832	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
<>	149:156823d33999	833
<>	149:156823d33999	834	/* Enable the DMA channel */
<>	149:156823d33999	835	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
<>	149:156823d33999	836
<>	149:156823d33999	837	/* Enable the TIM Capture/Compare 3 DMA request */
<>	149:156823d33999	838	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
<>	149:156823d33999	839	}
<>	149:156823d33999	840	break;
<>	149:156823d33999	841
<>	149:156823d33999	842	case TIM_CHANNEL_4:
<>	149:156823d33999	843	{
<>	149:156823d33999	844	/* Set the DMA Period elapsed callback */
<>	149:156823d33999	845	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
<>	149:156823d33999	846
<>	149:156823d33999	847	/* Set the DMA error callback */
<>	149:156823d33999	848	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
<>	149:156823d33999	849
<>	149:156823d33999	850	/* Enable the DMA channel */
<>	149:156823d33999	851	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
<>	149:156823d33999	852
<>	149:156823d33999	853	/* Enable the TIM Capture/Compare 4 DMA request */
<>	149:156823d33999	854	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
<>	149:156823d33999	855	}
<>	149:156823d33999	856	break;
<>	149:156823d33999	857
<>	149:156823d33999	858	default:
<>	149:156823d33999	859	break;
<>	149:156823d33999	860	}
<>	149:156823d33999	861
<>	149:156823d33999	862	/* Enable the Output compare channel */
<>	149:156823d33999	863	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<>	149:156823d33999	864
<>	149:156823d33999	865	/* Enable the Peripheral */
<>	149:156823d33999	866	__HAL_TIM_ENABLE(htim);
<>	149:156823d33999	867
<>	149:156823d33999	868	/* Return function status */
<>	149:156823d33999	869	return HAL_OK;
<>	149:156823d33999	870	}
<>	149:156823d33999	871
<>	149:156823d33999	872	/**
<>	149:156823d33999	873	* @brief Stops the TIM Output Compare signal generation in DMA mode.
<>	149:156823d33999	874	* @param htim : TIM Output Compare handle
<>	149:156823d33999	875	* @param Channel : TIM Channel to be disabled
<>	149:156823d33999	876	* This parameter can be one of the following values:
<>	149:156823d33999	877	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	149:156823d33999	878	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	149:156823d33999	879	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	149:156823d33999	880	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	149:156823d33999	881	* @retval HAL status
<>	149:156823d33999	882	*/
<>	149:156823d33999	883	HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	149:156823d33999	884	{
<>	149:156823d33999	885	/* Check the parameters */
<>	149:156823d33999	886	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	149:156823d33999	887
<>	149:156823d33999	888	switch (Channel)
<>	149:156823d33999	889	{
<>	149:156823d33999	890	case TIM_CHANNEL_1:
<>	149:156823d33999	891	{
<>	149:156823d33999	892	/* Disable the TIM Capture/Compare 1 DMA request */
<>	149:156823d33999	893	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<>	149:156823d33999	894	}
<>	149:156823d33999	895	break;
<>	149:156823d33999	896
<>	149:156823d33999	897	case TIM_CHANNEL_2:
<>	149:156823d33999	898	{
<>	149:156823d33999	899	/* Disable the TIM Capture/Compare 2 DMA request */
<>	149:156823d33999	900	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<>	149:156823d33999	901	}
<>	149:156823d33999	902	break;
<>	149:156823d33999	903
<>	149:156823d33999	904	case TIM_CHANNEL_3:
<>	149:156823d33999	905	{
<>	149:156823d33999	906	/* Disable the TIM Capture/Compare 3 DMA request */
<>	149:156823d33999	907	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
<>	149:156823d33999	908	}
<>	149:156823d33999	909	break;
<>	149:156823d33999	910
<>	149:156823d33999	911	case TIM_CHANNEL_4:
<>	149:156823d33999	912	{
<>	149:156823d33999	913	/* Disable the TIM Capture/Compare 4 interrupt */
<>	149:156823d33999	914	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
<>	149:156823d33999	915	}
<>	149:156823d33999	916	break;
<>	149:156823d33999	917
<>	149:156823d33999	918	default:
<>	149:156823d33999	919	break;
<>	149:156823d33999	920	}
<>	149:156823d33999	921
<>	149:156823d33999	922	/* Disable the Output compare channel */
<>	149:156823d33999	923	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<>	149:156823d33999	924
<>	149:156823d33999	925	/* Disable the Peripheral */
<>	149:156823d33999	926	__HAL_TIM_DISABLE(htim);
<>	149:156823d33999	927
<>	149:156823d33999	928	/* Change the htim state */
<>	149:156823d33999	929	htim->State = HAL_TIM_STATE_READY;
<>	149:156823d33999	930
<>	149:156823d33999	931	/* Return function status */
<>	149:156823d33999	932	return HAL_OK;
<>	149:156823d33999	933	}
<>	149:156823d33999	934
<>	149:156823d33999	935	/**
<>	149:156823d33999	936	* @}
<>	149:156823d33999	937	*/
<>	149:156823d33999	938
<>	149:156823d33999	939	/** @defgroup TIM_Exported_Functions_Group3 Time PWM functions
<>	149:156823d33999	940	* @brief Time PWM functions
<>	149:156823d33999	941	*
<>	149:156823d33999	942	@verbatim
<>	149:156823d33999	943	==============================================================================
<>	149:156823d33999	944	##### Time PWM functions #####
<>	149:156823d33999	945	==============================================================================
<>	149:156823d33999	946	[..]
<>	149:156823d33999	947	This section provides functions allowing to:
<>	149:156823d33999	948	(+) Initialize and configure the TIM PWM.
<>	149:156823d33999	949	(+) De-initialize the TIM PWM.
<>	149:156823d33999	950	(+) Start the Time PWM.
<>	149:156823d33999	951	(+) Stop the Time PWM.
<>	149:156823d33999	952	(+) Start the Time PWM and enable interrupt.
<>	149:156823d33999	953	(+) Stop the Time PWM and disable interrupt.
<>	149:156823d33999	954	(+) Start the Time PWM and enable DMA transfer.
<>	149:156823d33999	955	(+) Stop the Time PWM and disable DMA transfer.
<>	149:156823d33999	956
<>	149:156823d33999	957	@endverbatim
<>	149:156823d33999	958	* @{
<>	149:156823d33999	959	*/
<>	149:156823d33999	960	/**
<>	149:156823d33999	961	* @brief Initializes the TIM PWM Time Base according to the specified
<>	149:156823d33999	962	* parameters in the TIM_HandleTypeDef and create the associated handle.
<>	149:156823d33999	963	* @param htim: TIM handle
<>	149:156823d33999	964	* @retval HAL status
<>	149:156823d33999	965	*/
<>	149:156823d33999	966	HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
<>	149:156823d33999	967	{
<>	149:156823d33999	968	/* Check the TIM handle allocation */
<>	149:156823d33999	969	if(htim == NULL)
<>	149:156823d33999	970	{
<>	149:156823d33999	971	return HAL_ERROR;
<>	149:156823d33999	972	}
<>	149:156823d33999	973
<>	149:156823d33999	974	/* Check the parameters */
<>	149:156823d33999	975	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	149:156823d33999	976	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
<>	149:156823d33999	977	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
<>	149:156823d33999	978
<>	149:156823d33999	979	if(htim->State == HAL_TIM_STATE_RESET)
<>	149:156823d33999	980	{
<>	149:156823d33999	981	/* Allocate lock resource and initialize it */
<>	149:156823d33999	982	htim->Lock = HAL_UNLOCKED;
<>	149:156823d33999	983
<>	149:156823d33999	984	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
<>	149:156823d33999	985	HAL_TIM_PWM_MspInit(htim);
<>	149:156823d33999	986	}
<>	149:156823d33999	987
<>	149:156823d33999	988	/* Set the TIM state */
<>	149:156823d33999	989	htim->State= HAL_TIM_STATE_BUSY;
<>	149:156823d33999	990
<>	149:156823d33999	991	/* Init the base time for the PWM */
<>	149:156823d33999	992	TIM_Base_SetConfig(htim->Instance, &htim->Init);
<>	149:156823d33999	993
<>	149:156823d33999	994	/* Initialize the TIM state*/
<>	149:156823d33999	995	htim->State= HAL_TIM_STATE_READY;
<>	149:156823d33999	996
<>	149:156823d33999	997	return HAL_OK;
<>	149:156823d33999	998	}
<>	149:156823d33999	999
<>	149:156823d33999	1000	/**
<>	149:156823d33999	1001	* @brief DeInitializes the TIM peripheral
<>	149:156823d33999	1002	* @param htim: TIM handle
<>	149:156823d33999	1003	* @retval HAL status
<>	149:156823d33999	1004	*/
<>	149:156823d33999	1005	HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
<>	149:156823d33999	1006	{
<>	149:156823d33999	1007	/* Check the parameters */
<>	149:156823d33999	1008	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	149:156823d33999	1009
<>	149:156823d33999	1010	htim->State = HAL_TIM_STATE_BUSY;
<>	149:156823d33999	1011
<>	149:156823d33999	1012	/* Disable the TIM Peripheral Clock */
<>	149:156823d33999	1013	__HAL_TIM_DISABLE(htim);
<>	149:156823d33999	1014
<>	149:156823d33999	1015	/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
<>	149:156823d33999	1016	HAL_TIM_PWM_MspDeInit(htim);
<>	149:156823d33999	1017
<>	149:156823d33999	1018	/* Change TIM state */
<>	149:156823d33999	1019	htim->State = HAL_TIM_STATE_RESET;
<>	149:156823d33999	1020
<>	149:156823d33999	1021	/* Release Lock */
<>	149:156823d33999	1022	__HAL_UNLOCK(htim);
<>	149:156823d33999	1023
<>	149:156823d33999	1024	return HAL_OK;
<>	149:156823d33999	1025	}
<>	149:156823d33999	1026
<>	149:156823d33999	1027	/**
<>	149:156823d33999	1028	* @brief Initializes the TIM PWM MSP.
<>	149:156823d33999	1029	* @param htim: TIM handle
<>	149:156823d33999	1030	* @retval None
<>	149:156823d33999	1031	*/
<>	149:156823d33999	1032	__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
<>	149:156823d33999	1033	{
<>	149:156823d33999	1034	/* Prevent unused argument(s) compilation warning */
<>	149:156823d33999	1035	UNUSED(htim);
<>	149:156823d33999	1036
<>	149:156823d33999	1037	/* NOTE : This function Should not be modified, when the callback is needed,
<>	149:156823d33999	1038	the HAL_TIM_PWM_MspInit could be implemented in the user file
<>	149:156823d33999	1039	*/
<>	149:156823d33999	1040	}
<>	149:156823d33999	1041
<>	149:156823d33999	1042	/**
<>	149:156823d33999	1043	* @brief DeInitializes TIM PWM MSP.
<>	149:156823d33999	1044	* @param htim: TIM handle
<>	149:156823d33999	1045	* @retval None
<>	149:156823d33999	1046	*/
<>	149:156823d33999	1047	__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
<>	149:156823d33999	1048	{
<>	149:156823d33999	1049	/* Prevent unused argument(s) compilation warning */
<>	149:156823d33999	1050	UNUSED(htim);
<>	149:156823d33999	1051
<>	149:156823d33999	1052	/* NOTE : This function Should not be modified, when the callback is needed,
<>	149:156823d33999	1053	the HAL_TIM_PWM_MspDeInit could be implemented in the user file
<>	149:156823d33999	1054	*/
<>	149:156823d33999	1055	}
<>	149:156823d33999	1056
<>	149:156823d33999	1057	/**
<>	149:156823d33999	1058	* @brief Starts the PWM signal generation.
<>	149:156823d33999	1059	* @param htim : TIM handle
<>	149:156823d33999	1060	* @param Channel : TIM Channels to be enabled
<>	149:156823d33999	1061	* This parameter can be one of the following values:
<>	149:156823d33999	1062	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	149:156823d33999	1063	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	149:156823d33999	1064	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	149:156823d33999	1065	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	149:156823d33999	1066	* @retval HAL status
<>	149:156823d33999	1067	*/
<>	149:156823d33999	1068	HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	149:156823d33999	1069	{
<>	149:156823d33999	1070	/* Check the parameters */
<>	149:156823d33999	1071	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	149:156823d33999	1072
<>	149:156823d33999	1073	/* Enable the Capture compare channel */
<>	149:156823d33999	1074	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<>	149:156823d33999	1075
<>	149:156823d33999	1076	/* Enable the Peripheral */
<>	149:156823d33999	1077	__HAL_TIM_ENABLE(htim);
<>	149:156823d33999	1078
<>	149:156823d33999	1079	/* Return function status */
<>	149:156823d33999	1080	return HAL_OK;
<>	149:156823d33999	1081	}
<>	149:156823d33999	1082
<>	149:156823d33999	1083	/**
<>	149:156823d33999	1084	* @brief Stops the PWM signal generation.
<>	149:156823d33999	1085	* @param htim : TIM handle
<>	149:156823d33999	1086	* @param Channel : TIM Channels to be disabled
<>	149:156823d33999	1087	* This parameter can be one of the following values:
<>	149:156823d33999	1088	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	149:156823d33999	1089	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	149:156823d33999	1090	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	149:156823d33999	1091	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	149:156823d33999	1092	* @retval HAL status
<>	149:156823d33999	1093	*/
<>	149:156823d33999	1094	HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	149:156823d33999	1095	{
<>	149:156823d33999	1096	/* Check the parameters */
<>	149:156823d33999	1097	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	149:156823d33999	1098
<>	149:156823d33999	1099	/* Disable the Capture compare channel */
<>	149:156823d33999	1100	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<>	149:156823d33999	1101
<>	149:156823d33999	1102	/* Disable the Peripheral */
<>	149:156823d33999	1103	__HAL_TIM_DISABLE(htim);
<>	149:156823d33999	1104
<>	149:156823d33999	1105	/* Change the htim state */
<>	149:156823d33999	1106	htim->State = HAL_TIM_STATE_READY;
<>	149:156823d33999	1107
<>	149:156823d33999	1108	/* Return function status */
<>	149:156823d33999	1109	return HAL_OK;
<>	149:156823d33999	1110	}
<>	149:156823d33999	1111
<>	149:156823d33999	1112	/**
<>	149:156823d33999	1113	* @brief Starts the PWM signal generation in interrupt mode.
<>	149:156823d33999	1114	* @param htim : TIM handle
<>	149:156823d33999	1115	* @param Channel : TIM Channel to be enabled
<>	149:156823d33999	1116	* This parameter can be one of the following values:
<>	149:156823d33999	1117	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	149:156823d33999	1118	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	149:156823d33999	1119	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	149:156823d33999	1120	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	149:156823d33999	1121	* @retval HAL status
<>	149:156823d33999	1122	*/
<>	149:156823d33999	1123	HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	149:156823d33999	1124	{
<>	149:156823d33999	1125	/* Check the parameters */
<>	149:156823d33999	1126	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	149:156823d33999	1127
<>	149:156823d33999	1128	switch (Channel)
<>	149:156823d33999	1129	{
<>	149:156823d33999	1130	case TIM_CHANNEL_1:
<>	149:156823d33999	1131	{
<>	149:156823d33999	1132	/* Enable the TIM Capture/Compare 1 interrupt */
<>	149:156823d33999	1133	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<>	149:156823d33999	1134	}
<>	149:156823d33999	1135	break;
<>	149:156823d33999	1136
<>	149:156823d33999	1137	case TIM_CHANNEL_2:
<>	149:156823d33999	1138	{
<>	149:156823d33999	1139	/* Enable the TIM Capture/Compare 2 interrupt */
<>	149:156823d33999	1140	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<>	149:156823d33999	1141	}
<>	149:156823d33999	1142	break;
<>	149:156823d33999	1143
<>	149:156823d33999	1144	case TIM_CHANNEL_3:
<>	149:156823d33999	1145	{
<>	149:156823d33999	1146	/* Enable the TIM Capture/Compare 3 interrupt */
<>	149:156823d33999	1147	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
<>	149:156823d33999	1148	}
<>	149:156823d33999	1149	break;
<>	149:156823d33999	1150
<>	149:156823d33999	1151	case TIM_CHANNEL_4:
<>	149:156823d33999	1152	{
<>	149:156823d33999	1153	/* Enable the TIM Capture/Compare 4 interrupt */
<>	149:156823d33999	1154	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
<>	149:156823d33999	1155	}
<>	149:156823d33999	1156	break;
<>	149:156823d33999	1157
<>	149:156823d33999	1158	default:
<>	149:156823d33999	1159	break;
<>	149:156823d33999	1160	}
<>	149:156823d33999	1161
<>	149:156823d33999	1162	/* Enable the Capture compare channel */
<>	149:156823d33999	1163	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<>	149:156823d33999	1164
<>	149:156823d33999	1165	/* Enable the Peripheral */
<>	149:156823d33999	1166	__HAL_TIM_ENABLE(htim);
<>	149:156823d33999	1167
<>	149:156823d33999	1168	/* Return function status */
<>	149:156823d33999	1169	return HAL_OK;
<>	149:156823d33999	1170	}
<>	149:156823d33999	1171
<>	149:156823d33999	1172	/**
<>	149:156823d33999	1173	* @brief Stops the PWM signal generation in interrupt mode.
<>	149:156823d33999	1174	* @param htim : TIM handle
<>	149:156823d33999	1175	* @param Channel : TIM Channels to be disabled
<>	149:156823d33999	1176	* This parameter can be one of the following values:
<>	149:156823d33999	1177	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	149:156823d33999	1178	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	149:156823d33999	1179	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	149:156823d33999	1180	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	149:156823d33999	1181	* @retval HAL status
<>	149:156823d33999	1182	*/
<>	149:156823d33999	1183	HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
<>	149:156823d33999	1184	{
<>	149:156823d33999	1185	/* Check the parameters */
<>	149:156823d33999	1186	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	149:156823d33999	1187
<>	149:156823d33999	1188	switch (Channel)
<>	149:156823d33999	1189	{
<>	149:156823d33999	1190	case TIM_CHANNEL_1:
<>	149:156823d33999	1191	{
<>	149:156823d33999	1192	/* Disable the TIM Capture/Compare 1 interrupt */
<>	149:156823d33999	1193	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<>	149:156823d33999	1194	}
<>	149:156823d33999	1195	break;
<>	149:156823d33999	1196
<>	149:156823d33999	1197	case TIM_CHANNEL_2:
<>	149:156823d33999	1198	{
<>	149:156823d33999	1199	/* Disable the TIM Capture/Compare 2 interrupt */
<>	149:156823d33999	1200	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<>	149:156823d33999	1201	}
<>	149:156823d33999	1202	break;
<>	149:156823d33999	1203
<>	149:156823d33999	1204	case TIM_CHANNEL_3:
<>	149:156823d33999	1205	{
<>	149:156823d33999	1206	/* Disable the TIM Capture/Compare 3 interrupt */
<>	149:156823d33999	1207	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
<>	149:156823d33999	1208	}
<>	149:156823d33999	1209	break;
<>	149:156823d33999	1210
<>	149:156823d33999	1211	case TIM_CHANNEL_4:
<>	149:156823d33999	1212	{
<>	149:156823d33999	1213	/* Disable the TIM Capture/Compare 4 interrupt */
<>	149:156823d33999	1214	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
<>	149:156823d33999	1215	}
<>	149:156823d33999	1216	break;
<>	149:156823d33999	1217
<>	149:156823d33999	1218	default:
<>	149:156823d33999	1219	break;
<>	149:156823d33999	1220	}
<>	149:156823d33999	1221
<>	149:156823d33999	1222	/* Disable the Capture compare channel */
<>	149:156823d33999	1223	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<>	149:156823d33999	1224
<>	149:156823d33999	1225
<>	149:156823d33999	1226	/* Disable the Peripheral */
<>	149:156823d33999	1227	__HAL_TIM_DISABLE(htim);
<>	149:156823d33999	1228
<>	149:156823d33999	1229	/* Return function status */
<>	149:156823d33999	1230	return HAL_OK;
<>	149:156823d33999	1231	}
<>	149:156823d33999	1232
<>	149:156823d33999	1233	/**
<>	149:156823d33999	1234	* @brief Starts the TIM PWM signal generation in DMA mode.
<>	149:156823d33999	1235	* @param htim : TIM handle
<>	149:156823d33999	1236	* @param Channel : TIM Channels to be enabled
<>	149:156823d33999	1237	* This parameter can be one of the following values:
<>	149:156823d33999	1238	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	149:156823d33999	1239	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	149:156823d33999	1240	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	149:156823d33999	1241	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	149:156823d33999	1242	* @param pData: The source Buffer address.
<>	149:156823d33999	1243	* @param Length: The length of data to be transferred from memory to TIM peripheral
<>	149:156823d33999	1244	* @retval HAL status
<>	149:156823d33999	1245	*/
<>	149:156823d33999	1246	HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length)
<>	149:156823d33999	1247	{
<>	149:156823d33999	1248	/* Check the parameters */
<>	149:156823d33999	1249	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	149:156823d33999	1250
<>	149:156823d33999	1251	if((htim->State == HAL_TIM_STATE_BUSY))
<>	149:156823d33999	1252	{
<>	149:156823d33999	1253	return HAL_BUSY;
<>	149:156823d33999	1254	}
<>	149:156823d33999	1255	else if((htim->State == HAL_TIM_STATE_READY))
<>	149:156823d33999	1256	{
<>	149:156823d33999	1257	if(((uint32_t)pData == 0 ) && (Length > 0))
<>	149:156823d33999	1258	{
<>	149:156823d33999	1259	return HAL_ERROR;
<>	149:156823d33999	1260	}
<>	149:156823d33999	1261	else
<>	149:156823d33999	1262	{
<>	149:156823d33999	1263	htim->State = HAL_TIM_STATE_BUSY;
<>	149:156823d33999	1264	}
<>	149:156823d33999	1265	}
<>	149:156823d33999	1266	else
<>	149:156823d33999	1267	{
<>	149:156823d33999	1268	return HAL_ERROR;
<>	149:156823d33999	1269	}
<>	149:156823d33999	1270
<>	149:156823d33999	1271	switch (Channel)
<>	149:156823d33999	1272	{
<>	149:156823d33999	1273	case TIM_CHANNEL_1:
<>	149:156823d33999	1274	{
<>	149:156823d33999	1275	/* Set the DMA Period elapsed callback */
<>	149:156823d33999	1276	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
<>	149:156823d33999	1277
<>	149:156823d33999	1278	/* Set the DMA error callback */
<>	149:156823d33999	1279	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<>	149:156823d33999	1280
<>	149:156823d33999	1281	/* Enable the DMA channel */
<>	149:156823d33999	1282	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
<>	149:156823d33999	1283
<>	149:156823d33999	1284	/* Enable the TIM Capture/Compare 1 DMA request */
<>	149:156823d33999	1285	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<>	149:156823d33999	1286	}
<>	149:156823d33999	1287	break;
<>	149:156823d33999	1288
<>	149:156823d33999	1289	case TIM_CHANNEL_2:
<>	149:156823d33999	1290	{
<>	149:156823d33999	1291	/* Set the DMA Period elapsed callback */
<>	149:156823d33999	1292	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
<>	149:156823d33999	1293
<>	149:156823d33999	1294	/* Set the DMA error callback */
<>	149:156823d33999	1295	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<>	149:156823d33999	1296
<>	149:156823d33999	1297	/* Enable the DMA channel */
<>	149:156823d33999	1298	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
<>	149:156823d33999	1299
<>	149:156823d33999	1300	/* Enable the TIM Capture/Compare 2 DMA request */
<>	149:156823d33999	1301	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<>	149:156823d33999	1302	}
<>	149:156823d33999	1303	break;
<>	149:156823d33999	1304
<>	149:156823d33999	1305	case TIM_CHANNEL_3:
<>	149:156823d33999	1306	{
<>	149:156823d33999	1307	/* Set the DMA Period elapsed callback */
<>	149:156823d33999	1308	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
<>	149:156823d33999	1309
<>	149:156823d33999	1310	/* Set the DMA error callback */
<>	149:156823d33999	1311	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
<>	149:156823d33999	1312
<>	149:156823d33999	1313	/* Enable the DMA channel */
<>	149:156823d33999	1314	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
<>	149:156823d33999	1315
<>	149:156823d33999	1316	/* Enable the TIM Output Capture/Compare 3 request */
<>	149:156823d33999	1317	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
<>	149:156823d33999	1318	}
<>	149:156823d33999	1319	break;
<>	149:156823d33999	1320
<>	149:156823d33999	1321	case TIM_CHANNEL_4:
<>	149:156823d33999	1322	{
<>	149:156823d33999	1323	/* Set the DMA Period elapsed callback */
<>	149:156823d33999	1324	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
<>	149:156823d33999	1325
<>	149:156823d33999	1326	/* Set the DMA error callback */
<>	149:156823d33999	1327	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
<>	149:156823d33999	1328
<>	149:156823d33999	1329	/* Enable the DMA channel */
<>	149:156823d33999	1330	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
<>	149:156823d33999	1331
<>	149:156823d33999	1332	/* Enable the TIM Capture/Compare 4 DMA request */
<>	149:156823d33999	1333	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
<>	149:156823d33999	1334	}
<>	149:156823d33999	1335	break;
<>	149:156823d33999	1336
<>	149:156823d33999	1337	default:
<>	149:156823d33999	1338	break;
<>	149:156823d33999	1339	}
<>	149:156823d33999	1340
<>	149:156823d33999	1341	/* Enable the Capture compare channel */
<>	149:156823d33999	1342	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<>	149:156823d33999	1343
<>	149:156823d33999	1344	/* Enable the Peripheral */
<>	149:156823d33999	1345	__HAL_TIM_ENABLE(htim);
<>	149:156823d33999	1346
<>	149:156823d33999	1347	/* Return function status */
<>	149:156823d33999	1348	return HAL_OK;
<>	149:156823d33999	1349	}
<>	149:156823d33999	1350
<>	149:156823d33999	1351	/**
<>	149:156823d33999	1352	* @brief Stops the TIM PWM signal generation in DMA mode.
<>	149:156823d33999	1353	* @param htim : TIM handle
<>	149:156823d33999	1354	* @param Channel : TIM Channels to be disabled
<>	149:156823d33999	1355	* This parameter can be one of the following values:
<>	149:156823d33999	1356	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	149:156823d33999	1357	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	149:156823d33999	1358	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	149:156823d33999	1359	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	149:156823d33999	1360	* @retval HAL status
<>	149:156823d33999	1361	*/
<>	149:156823d33999	1362	HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	149:156823d33999	1363	{
<>	149:156823d33999	1364	/* Check the parameters */
<>	149:156823d33999	1365	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	149:156823d33999	1366
<>	149:156823d33999	1367	switch (Channel)
<>	149:156823d33999	1368	{
<>	149:156823d33999	1369	case TIM_CHANNEL_1:
<>	149:156823d33999	1370	{
<>	149:156823d33999	1371	/* Disable the TIM Capture/Compare 1 DMA request */
<>	149:156823d33999	1372	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<>	149:156823d33999	1373	}
<>	149:156823d33999	1374	break;
<>	149:156823d33999	1375
<>	149:156823d33999	1376	case TIM_CHANNEL_2:
<>	149:156823d33999	1377	{
<>	149:156823d33999	1378	/* Disable the TIM Capture/Compare 2 DMA request */
<>	149:156823d33999	1379	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<>	149:156823d33999	1380	}
<>	149:156823d33999	1381	break;
<>	149:156823d33999	1382
<>	149:156823d33999	1383	case TIM_CHANNEL_3:
<>	149:156823d33999	1384	{
<>	149:156823d33999	1385	/* Disable the TIM Capture/Compare 3 DMA request */
<>	149:156823d33999	1386	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
<>	149:156823d33999	1387	}
<>	149:156823d33999	1388	break;
<>	149:156823d33999	1389
<>	149:156823d33999	1390	case TIM_CHANNEL_4:
<>	149:156823d33999	1391	{
<>	149:156823d33999	1392	/* Disable the TIM Capture/Compare 4 interrupt */
<>	149:156823d33999	1393	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
<>	149:156823d33999	1394	}
<>	149:156823d33999	1395	break;
<>	149:156823d33999	1396
<>	149:156823d33999	1397	default:
<>	149:156823d33999	1398	break;
<>	149:156823d33999	1399	}
<>	149:156823d33999	1400
<>	149:156823d33999	1401	/* Disable the Capture compare channel */
<>	149:156823d33999	1402	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<>	149:156823d33999	1403
<>	149:156823d33999	1404	/* Disable the Peripheral */
<>	149:156823d33999	1405	__HAL_TIM_DISABLE(htim);
<>	149:156823d33999	1406
<>	149:156823d33999	1407	/* Change the htim state */
<>	149:156823d33999	1408	htim->State = HAL_TIM_STATE_READY;
<>	149:156823d33999	1409
<>	149:156823d33999	1410	/* Return function status */
<>	149:156823d33999	1411	return HAL_OK;
<>	149:156823d33999	1412	}
<>	149:156823d33999	1413
<>	149:156823d33999	1414	/**
<>	149:156823d33999	1415	* @}
<>	149:156823d33999	1416	*/
<>	149:156823d33999	1417
<>	149:156823d33999	1418	/** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions
<>	149:156823d33999	1419	* @brief Time Input Capture functions
<>	149:156823d33999	1420	*
<>	149:156823d33999	1421	@verbatim
<>	149:156823d33999	1422	==============================================================================
<>	149:156823d33999	1423	##### Time Input Capture functions #####
<>	149:156823d33999	1424	==============================================================================
<>	149:156823d33999	1425	[..]
<>	149:156823d33999	1426	This section provides functions allowing to:
<>	149:156823d33999	1427	(+) Initialize and configure the TIM Input Capture.
<>	149:156823d33999	1428	(+) De-initialize the TIM Input Capture.
<>	149:156823d33999	1429	(+) Start the Time Input Capture.
<>	149:156823d33999	1430	(+) Stop the Time Input Capture.
<>	149:156823d33999	1431	(+) Start the Time Input Capture and enable interrupt.
<>	149:156823d33999	1432	(+) Stop the Time Input Capture and disable interrupt.
<>	149:156823d33999	1433	(+) Start the Time Input Capture and enable DMA transfer.
<>	149:156823d33999	1434	(+) Stop the Time Input Capture and disable DMA transfer.
<>	149:156823d33999	1435
<>	149:156823d33999	1436	@endverbatim
<>	149:156823d33999	1437	* @{
<>	149:156823d33999	1438	*/
<>	149:156823d33999	1439	/**
<>	149:156823d33999	1440	* @brief Initializes the TIM Input Capture Time base according to the specified
<>	149:156823d33999	1441	* parameters in the TIM_HandleTypeDef and create the associated handle.
<>	149:156823d33999	1442	* @param htim: TIM Input Capture handle
<>	149:156823d33999	1443	* @retval HAL status
<>	149:156823d33999	1444	*/
<>	149:156823d33999	1445	HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
<>	149:156823d33999	1446	{
<>	149:156823d33999	1447	/* Check the TIM handle allocation */
<>	149:156823d33999	1448	if(htim == NULL)
<>	149:156823d33999	1449	{
<>	149:156823d33999	1450	return HAL_ERROR;
<>	149:156823d33999	1451	}
<>	149:156823d33999	1452
<>	149:156823d33999	1453	/* Check the parameters */
<>	149:156823d33999	1454	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	149:156823d33999	1455	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
<>	149:156823d33999	1456	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
<>	149:156823d33999	1457
<>	149:156823d33999	1458	if(htim->State == HAL_TIM_STATE_RESET)
<>	149:156823d33999	1459	{
<>	149:156823d33999	1460	/* Allocate lock resource and initialize it */
<>	149:156823d33999	1461	htim->Lock = HAL_UNLOCKED;
<>	149:156823d33999	1462
<>	149:156823d33999	1463	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
<>	149:156823d33999	1464	HAL_TIM_IC_MspInit(htim);
<>	149:156823d33999	1465	}
<>	149:156823d33999	1466
<>	149:156823d33999	1467	/* Set the TIM state */
<>	149:156823d33999	1468	htim->State= HAL_TIM_STATE_BUSY;
<>	149:156823d33999	1469
<>	149:156823d33999	1470	/* Init the base time for the input capture */
<>	149:156823d33999	1471	TIM_Base_SetConfig(htim->Instance, &htim->Init);
<>	149:156823d33999	1472
<>	149:156823d33999	1473	/* Initialize the TIM state*/
<>	149:156823d33999	1474	htim->State= HAL_TIM_STATE_READY;
<>	149:156823d33999	1475
<>	149:156823d33999	1476	return HAL_OK;
<>	149:156823d33999	1477	}
<>	149:156823d33999	1478
<>	149:156823d33999	1479	/**
<>	149:156823d33999	1480	* @brief DeInitializes the TIM peripheral
<>	149:156823d33999	1481	* @param htim: TIM Input Capture handle
<>	149:156823d33999	1482	* @retval HAL status
<>	149:156823d33999	1483	*/
<>	149:156823d33999	1484	HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
<>	149:156823d33999	1485	{
<>	149:156823d33999	1486	/* Check the parameters */
<>	149:156823d33999	1487	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	149:156823d33999	1488
<>	149:156823d33999	1489	htim->State = HAL_TIM_STATE_BUSY;
<>	149:156823d33999	1490
<>	149:156823d33999	1491	/* Disable the TIM Peripheral Clock */
<>	149:156823d33999	1492	__HAL_TIM_DISABLE(htim);
<>	149:156823d33999	1493
<>	149:156823d33999	1494	/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
<>	149:156823d33999	1495	HAL_TIM_IC_MspDeInit(htim);
<>	149:156823d33999	1496
<>	149:156823d33999	1497	/* Change TIM state */
<>	149:156823d33999	1498	htim->State = HAL_TIM_STATE_RESET;
<>	149:156823d33999	1499
<>	149:156823d33999	1500	/* Release Lock */
<>	149:156823d33999	1501	__HAL_UNLOCK(htim);
<>	149:156823d33999	1502
<>	149:156823d33999	1503	return HAL_OK;
<>	149:156823d33999	1504	}
<>	149:156823d33999	1505
<>	149:156823d33999	1506	/**
<>	149:156823d33999	1507	* @brief Initializes the TIM Input Capture MSP.
<>	149:156823d33999	1508	* @param htim: TIM handle
<>	149:156823d33999	1509	* @retval None
<>	149:156823d33999	1510	*/
<>	149:156823d33999	1511	__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
<>	149:156823d33999	1512	{
<>	149:156823d33999	1513	/* Prevent unused argument(s) compilation warning */
<>	149:156823d33999	1514	UNUSED(htim);
<>	149:156823d33999	1515
<>	149:156823d33999	1516	/* NOTE : This function Should not be modified, when the callback is needed,
<>	149:156823d33999	1517	the HAL_TIM_IC_MspInit could be implemented in the user file
<>	149:156823d33999	1518	*/
<>	149:156823d33999	1519	}
<>	149:156823d33999	1520
<>	149:156823d33999	1521	/**
<>	149:156823d33999	1522	* @brief DeInitializes TIM Input Capture MSP.
<>	149:156823d33999	1523	* @param htim: TIM handle
<>	149:156823d33999	1524	* @retval None
<>	149:156823d33999	1525	*/
<>	149:156823d33999	1526	__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
<>	149:156823d33999	1527	{
<>	149:156823d33999	1528	/* Prevent unused argument(s) compilation warning */
<>	149:156823d33999	1529	UNUSED(htim);
<>	149:156823d33999	1530
<>	149:156823d33999	1531	/* NOTE : This function Should not be modified, when the callback is needed,
<>	149:156823d33999	1532	the HAL_TIM_IC_MspDeInit could be implemented in the user file
<>	149:156823d33999	1533	*/
<>	149:156823d33999	1534	}
<>	149:156823d33999	1535
<>	149:156823d33999	1536	/**
<>	149:156823d33999	1537	* @brief Starts the TIM Input Capture measurement.
<>	149:156823d33999	1538	* @param htim : TIM Input Capture handle
<>	149:156823d33999	1539	* @param Channel : TIM Channels to be enabled
<>	149:156823d33999	1540	* This parameter can be one of the following values:
<>	149:156823d33999	1541	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	149:156823d33999	1542	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	149:156823d33999	1543	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	149:156823d33999	1544	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	149:156823d33999	1545	* @retval HAL status
<>	149:156823d33999	1546	*/
<>	149:156823d33999	1547	HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
<>	149:156823d33999	1548	{
<>	149:156823d33999	1549	/* Check the parameters */
<>	149:156823d33999	1550	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	149:156823d33999	1551
<>	149:156823d33999	1552	/* Enable the Input Capture channel */
<>	149:156823d33999	1553	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<>	149:156823d33999	1554
<>	149:156823d33999	1555	/* Enable the Peripheral */
<>	149:156823d33999	1556	__HAL_TIM_ENABLE(htim);
<>	149:156823d33999	1557
<>	149:156823d33999	1558	/* Return function status */
<>	149:156823d33999	1559	return HAL_OK;
<>	149:156823d33999	1560	}
<>	149:156823d33999	1561
<>	149:156823d33999	1562	/**
<>	149:156823d33999	1563	* @brief Stops the TIM Input Capture measurement.
<>	149:156823d33999	1564	* @param htim : TIM handle
<>	149:156823d33999	1565	* @param Channel : TIM Channels to be disabled
<>	149:156823d33999	1566	* This parameter can be one of the following values:
<>	149:156823d33999	1567	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	149:156823d33999	1568	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	149:156823d33999	1569	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	149:156823d33999	1570	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	149:156823d33999	1571	* @retval HAL status
<>	149:156823d33999	1572	*/
<>	149:156823d33999	1573	HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	149:156823d33999	1574	{
<>	149:156823d33999	1575	/* Check the parameters */
<>	149:156823d33999	1576	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	149:156823d33999	1577
<>	149:156823d33999	1578	/* Disable the Input Capture channel */
<>	149:156823d33999	1579	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<>	149:156823d33999	1580
<>	149:156823d33999	1581	/* Disable the Peripheral */
<>	149:156823d33999	1582	__HAL_TIM_DISABLE(htim);
<>	149:156823d33999	1583
<>	149:156823d33999	1584	/* Return function status */
<>	149:156823d33999	1585	return HAL_OK;
<>	149:156823d33999	1586	}
<>	149:156823d33999	1587
<>	149:156823d33999	1588	/**
<>	149:156823d33999	1589	* @brief Starts the TIM Input Capture measurement in interrupt mode.
<>	149:156823d33999	1590	* @param htim : TIM Input Capture handle
<>	149:156823d33999	1591	* @param Channel : TIM Channels to be enabled
<>	149:156823d33999	1592	* This parameter can be one of the following values:
<>	149:156823d33999	1593	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	149:156823d33999	1594	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	149:156823d33999	1595	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	149:156823d33999	1596	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	149:156823d33999	1597	* @retval HAL status
<>	149:156823d33999	1598	*/
<>	149:156823d33999	1599	HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
<>	149:156823d33999	1600	{
<>	149:156823d33999	1601	/* Check the parameters */
<>	149:156823d33999	1602	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	149:156823d33999	1603
<>	149:156823d33999	1604	switch (Channel)
<>	149:156823d33999	1605	{
<>	149:156823d33999	1606	case TIM_CHANNEL_1:
<>	149:156823d33999	1607	{
<>	149:156823d33999	1608	/* Enable the TIM Capture/Compare 1 interrupt */
<>	149:156823d33999	1609	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<>	149:156823d33999	1610	}
<>	149:156823d33999	1611	break;
<>	149:156823d33999	1612
<>	149:156823d33999	1613	case TIM_CHANNEL_2:
<>	149:156823d33999	1614	{
<>	149:156823d33999	1615	/* Enable the TIM Capture/Compare 2 interrupt */
<>	149:156823d33999	1616	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<>	149:156823d33999	1617	}
<>	149:156823d33999	1618	break;
<>	149:156823d33999	1619
<>	149:156823d33999	1620	case TIM_CHANNEL_3:
<>	149:156823d33999	1621	{
<>	149:156823d33999	1622	/* Enable the TIM Capture/Compare 3 interrupt */
<>	149:156823d33999	1623	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
<>	149:156823d33999	1624	}
<>	149:156823d33999	1625	break;
<>	149:156823d33999	1626
<>	149:156823d33999	1627	case TIM_CHANNEL_4:
<>	149:156823d33999	1628	{
<>	149:156823d33999	1629	/* Enable the TIM Capture/Compare 4 interrupt */
<>	149:156823d33999	1630	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
<>	149:156823d33999	1631	}
<>	149:156823d33999	1632	break;
<>	149:156823d33999	1633
<>	149:156823d33999	1634	default:
<>	149:156823d33999	1635	break;
<>	149:156823d33999	1636	}
<>	149:156823d33999	1637	/* Enable the Input Capture channel */
<>	149:156823d33999	1638	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<>	149:156823d33999	1639
<>	149:156823d33999	1640	/* Enable the Peripheral */
<>	149:156823d33999	1641	__HAL_TIM_ENABLE(htim);
<>	149:156823d33999	1642
<>	149:156823d33999	1643	/* Return function status */
<>	149:156823d33999	1644	return HAL_OK;
<>	149:156823d33999	1645	}
<>	149:156823d33999	1646
<>	149:156823d33999	1647	/**
<>	149:156823d33999	1648	* @brief Stops the TIM Input Capture measurement in interrupt mode.
<>	149:156823d33999	1649	* @param htim : TIM handle
<>	149:156823d33999	1650	* @param Channel : TIM Channels to be disabled
<>	149:156823d33999	1651	* This parameter can be one of the following values:
<>	149:156823d33999	1652	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	149:156823d33999	1653	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	149:156823d33999	1654	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	149:156823d33999	1655	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	149:156823d33999	1656	* @retval HAL status
<>	149:156823d33999	1657	*/
<>	149:156823d33999	1658	HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	149:156823d33999	1659	{
<>	149:156823d33999	1660	/* Check the parameters */
<>	149:156823d33999	1661	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	149:156823d33999	1662
<>	149:156823d33999	1663	switch (Channel)
<>	149:156823d33999	1664	{
<>	149:156823d33999	1665	case TIM_CHANNEL_1:
<>	149:156823d33999	1666	{
<>	149:156823d33999	1667	/* Disable the TIM Capture/Compare 1 interrupt */
<>	149:156823d33999	1668	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<>	149:156823d33999	1669	}
<>	149:156823d33999	1670	break;
<>	149:156823d33999	1671
<>	149:156823d33999	1672	case TIM_CHANNEL_2:
<>	149:156823d33999	1673	{
<>	149:156823d33999	1674	/* Disable the TIM Capture/Compare 2 interrupt */
<>	149:156823d33999	1675	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<>	149:156823d33999	1676	}
<>	149:156823d33999	1677	break;
<>	149:156823d33999	1678
<>	149:156823d33999	1679	case TIM_CHANNEL_3:
<>	149:156823d33999	1680	{
<>	149:156823d33999	1681	/* Disable the TIM Capture/Compare 3 interrupt */
<>	149:156823d33999	1682	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
<>	149:156823d33999	1683	}
<>	149:156823d33999	1684	break;
<>	149:156823d33999	1685
<>	149:156823d33999	1686	case TIM_CHANNEL_4:
<>	149:156823d33999	1687	{
<>	149:156823d33999	1688	/* Disable the TIM Capture/Compare 4 interrupt */
<>	149:156823d33999	1689	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
<>	149:156823d33999	1690	}
<>	149:156823d33999	1691	break;
<>	149:156823d33999	1692
<>	149:156823d33999	1693	default:
<>	149:156823d33999	1694	break;
<>	149:156823d33999	1695	}
<>	149:156823d33999	1696
<>	149:156823d33999	1697	/* Disable the Input Capture channel */
<>	149:156823d33999	1698	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<>	149:156823d33999	1699
<>	149:156823d33999	1700	/* Disable the Peripheral */
<>	149:156823d33999	1701	__HAL_TIM_DISABLE(htim);
<>	149:156823d33999	1702
<>	149:156823d33999	1703	/* Return function status */
<>	149:156823d33999	1704	return HAL_OK;
<>	149:156823d33999	1705	}
<>	149:156823d33999	1706
<>	149:156823d33999	1707	/**
<>	149:156823d33999	1708	* @brief Starts the TIM Input Capture measurement in DMA mode.
<>	149:156823d33999	1709	* @param htim : TIM Input Capture handle
<>	149:156823d33999	1710	* @param Channel : TIM Channels to be enabled
<>	149:156823d33999	1711	* This parameter can be one of the following values:
<>	149:156823d33999	1712	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	149:156823d33999	1713	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	149:156823d33999	1714	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	149:156823d33999	1715	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	149:156823d33999	1716	* @param pData: The destination Buffer address.
<>	149:156823d33999	1717	* @param Length: The length of data to be transferred from TIM peripheral to memory.
<>	149:156823d33999	1718	* @retval HAL status
<>	149:156823d33999	1719	*/
<>	149:156823d33999	1720	HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length)
<>	149:156823d33999	1721	{
<>	149:156823d33999	1722	/* Check the parameters */
<>	149:156823d33999	1723	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	149:156823d33999	1724	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
<>	149:156823d33999	1725
<>	149:156823d33999	1726	if((htim->State == HAL_TIM_STATE_BUSY))
<>	149:156823d33999	1727	{
<>	149:156823d33999	1728	return HAL_BUSY;
<>	149:156823d33999	1729	}
<>	149:156823d33999	1730	else if((htim->State == HAL_TIM_STATE_READY))
<>	149:156823d33999	1731	{
<>	149:156823d33999	1732	if((pData == 0 ) && (Length > 0))
<>	149:156823d33999	1733	{
<>	149:156823d33999	1734	return HAL_ERROR;
<>	149:156823d33999	1735	}
<>	149:156823d33999	1736	else
<>	149:156823d33999	1737	{
<>	149:156823d33999	1738	htim->State = HAL_TIM_STATE_BUSY;
<>	149:156823d33999	1739	}
<>	149:156823d33999	1740	}
<>	149:156823d33999	1741	else
<>	149:156823d33999	1742	{
<>	149:156823d33999	1743	return HAL_ERROR;
<>	149:156823d33999	1744	}
<>	149:156823d33999	1745
<>	149:156823d33999	1746	switch (Channel)
<>	149:156823d33999	1747	{
<>	149:156823d33999	1748	case TIM_CHANNEL_1:
<>	149:156823d33999	1749	{
<>	149:156823d33999	1750	/* Set the DMA Period elapsed callback */
<>	149:156823d33999	1751	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
<>	149:156823d33999	1752
<>	149:156823d33999	1753	/* Set the DMA error callback */
<>	149:156823d33999	1754	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<>	149:156823d33999	1755
<>	149:156823d33999	1756	/* Enable the DMA channel */
<>	149:156823d33999	1757	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
<>	149:156823d33999	1758
<>	149:156823d33999	1759	/* Enable the TIM Capture/Compare 1 DMA request */
<>	149:156823d33999	1760	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<>	149:156823d33999	1761	}
<>	149:156823d33999	1762	break;
<>	149:156823d33999	1763
<>	149:156823d33999	1764	case TIM_CHANNEL_2:
<>	149:156823d33999	1765	{
<>	149:156823d33999	1766	/* Set the DMA Period elapsed callback */
<>	149:156823d33999	1767	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
<>	149:156823d33999	1768
<>	149:156823d33999	1769	/* Set the DMA error callback */
<>	149:156823d33999	1770	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<>	149:156823d33999	1771
<>	149:156823d33999	1772	/* Enable the DMA channel */
<>	149:156823d33999	1773	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
<>	149:156823d33999	1774
<>	149:156823d33999	1775	/* Enable the TIM Capture/Compare 2 DMA request */
<>	149:156823d33999	1776	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<>	149:156823d33999	1777	}
<>	149:156823d33999	1778	break;
<>	149:156823d33999	1779
<>	149:156823d33999	1780	case TIM_CHANNEL_3:
<>	149:156823d33999	1781	{
<>	149:156823d33999	1782	/* Set the DMA Period elapsed callback */
<>	149:156823d33999	1783	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
<>	149:156823d33999	1784
<>	149:156823d33999	1785	/* Set the DMA error callback */
<>	149:156823d33999	1786	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
<>	149:156823d33999	1787
<>	149:156823d33999	1788	/* Enable the DMA channel */
<>	149:156823d33999	1789	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
<>	149:156823d33999	1790
<>	149:156823d33999	1791	/* Enable the TIM Capture/Compare 3 DMA request */
<>	149:156823d33999	1792	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
<>	149:156823d33999	1793	}
<>	149:156823d33999	1794	break;
<>	149:156823d33999	1795
<>	149:156823d33999	1796	case TIM_CHANNEL_4:
<>	149:156823d33999	1797	{
<>	149:156823d33999	1798	/* Set the DMA Period elapsed callback */
<>	149:156823d33999	1799	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
<>	149:156823d33999	1800
<>	149:156823d33999	1801	/* Set the DMA error callback */
<>	149:156823d33999	1802	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
<>	149:156823d33999	1803
<>	149:156823d33999	1804	/* Enable the DMA channel */
<>	149:156823d33999	1805	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
<>	149:156823d33999	1806
<>	149:156823d33999	1807	/* Enable the TIM Capture/Compare 4 DMA request */
<>	149:156823d33999	1808	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
<>	149:156823d33999	1809	}
<>	149:156823d33999	1810	break;
<>	149:156823d33999	1811
<>	149:156823d33999	1812	default:
<>	149:156823d33999	1813	break;
<>	149:156823d33999	1814	}
<>	149:156823d33999	1815
<>	149:156823d33999	1816	/* Enable the Input Capture channel */
<>	149:156823d33999	1817	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<>	149:156823d33999	1818
<>	149:156823d33999	1819	/* Enable the Peripheral */
<>	149:156823d33999	1820	__HAL_TIM_ENABLE(htim);
<>	149:156823d33999	1821
<>	149:156823d33999	1822	/* Return function status */
<>	149:156823d33999	1823	return HAL_OK;
<>	149:156823d33999	1824	}
<>	149:156823d33999	1825
<>	149:156823d33999	1826	/**
<>	149:156823d33999	1827	* @brief Stops the TIM Input Capture measurement in DMA mode.
<>	149:156823d33999	1828	* @param htim : TIM Input Capture handle
<>	149:156823d33999	1829	* @param Channel : TIM Channels to be disabled
<>	149:156823d33999	1830	* This parameter can be one of the following values:
<>	149:156823d33999	1831	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	149:156823d33999	1832	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	149:156823d33999	1833	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	149:156823d33999	1834	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	149:156823d33999	1835	* @retval HAL status
<>	149:156823d33999	1836	*/
<>	149:156823d33999	1837	HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	149:156823d33999	1838	{
<>	149:156823d33999	1839	/* Check the parameters */
<>	149:156823d33999	1840	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	149:156823d33999	1841	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
<>	149:156823d33999	1842
<>	149:156823d33999	1843	switch (Channel)
<>	149:156823d33999	1844	{
<>	149:156823d33999	1845	case TIM_CHANNEL_1:
<>	149:156823d33999	1846	{
<>	149:156823d33999	1847	/* Disable the TIM Capture/Compare 1 DMA request */
<>	149:156823d33999	1848	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<>	149:156823d33999	1849	}
<>	149:156823d33999	1850	break;
<>	149:156823d33999	1851
<>	149:156823d33999	1852	case TIM_CHANNEL_2:
<>	149:156823d33999	1853	{
<>	149:156823d33999	1854	/* Disable the TIM Capture/Compare 2 DMA request */
<>	149:156823d33999	1855	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<>	149:156823d33999	1856	}
<>	149:156823d33999	1857	break;
<>	149:156823d33999	1858
<>	149:156823d33999	1859	case TIM_CHANNEL_3:
<>	149:156823d33999	1860	{
<>	149:156823d33999	1861	/* Disable the TIM Capture/Compare 3 DMA request */
<>	149:156823d33999	1862	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
<>	149:156823d33999	1863	}
<>	149:156823d33999	1864	break;
<>	149:156823d33999	1865
<>	149:156823d33999	1866	case TIM_CHANNEL_4:
<>	149:156823d33999	1867	{
<>	149:156823d33999	1868	/* Disable the TIM Capture/Compare 4 DMA request */
<>	149:156823d33999	1869	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
<>	149:156823d33999	1870	}
<>	149:156823d33999	1871	break;
<>	149:156823d33999	1872
<>	149:156823d33999	1873	default:
<>	149:156823d33999	1874	break;
<>	149:156823d33999	1875	}
<>	149:156823d33999	1876
<>	149:156823d33999	1877	/* Disable the Input Capture channel */
<>	149:156823d33999	1878	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<>	149:156823d33999	1879
<>	149:156823d33999	1880	/* Disable the Peripheral */
<>	149:156823d33999	1881	__HAL_TIM_DISABLE(htim);
<>	149:156823d33999	1882
<>	149:156823d33999	1883	/* Change the htim state */
<>	149:156823d33999	1884	htim->State = HAL_TIM_STATE_READY;
<>	149:156823d33999	1885
<>	149:156823d33999	1886	/* Return function status */
<>	149:156823d33999	1887	return HAL_OK;
<>	149:156823d33999	1888	}
<>	149:156823d33999	1889	/**
<>	149:156823d33999	1890	* @}
<>	149:156823d33999	1891	*/
<>	149:156823d33999	1892
<>	149:156823d33999	1893	/** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions
<>	149:156823d33999	1894	* @brief Time One Pulse functions
<>	149:156823d33999	1895	*
<>	149:156823d33999	1896	@verbatim
<>	149:156823d33999	1897	==============================================================================
<>	149:156823d33999	1898	##### Time One Pulse functions #####
<>	149:156823d33999	1899	==============================================================================
<>	149:156823d33999	1900	[..]
<>	149:156823d33999	1901	This section provides functions allowing to:
<>	149:156823d33999	1902	(+) Initialize and configure the TIM One Pulse.
<>	149:156823d33999	1903	(+) De-initialize the TIM One Pulse.
<>	149:156823d33999	1904	(+) Start the Time One Pulse.
<>	149:156823d33999	1905	(+) Stop the Time One Pulse.
<>	149:156823d33999	1906	(+) Start the Time One Pulse and enable interrupt.
<>	149:156823d33999	1907	(+) Stop the Time One Pulse and disable interrupt.
<>	149:156823d33999	1908	(+) Start the Time One Pulse and enable DMA transfer.
<>	149:156823d33999	1909	(+) Stop the Time One Pulse and disable DMA transfer.
<>	149:156823d33999	1910
<>	149:156823d33999	1911	@endverbatim
<>	149:156823d33999	1912	* @{
<>	149:156823d33999	1913	*/
<>	149:156823d33999	1914	/**
<>	149:156823d33999	1915	* @brief Initializes the TIM One Pulse Time Base according to the specified
<>	149:156823d33999	1916	* parameters in the TIM_HandleTypeDef and create the associated handle.
<>	149:156823d33999	1917	* @param htim: TIM OnePulse handle
<>	149:156823d33999	1918	* @param OnePulseMode: Select the One pulse mode.
<>	149:156823d33999	1919	* This parameter can be one of the following values:
<>	149:156823d33999	1920	* @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
<>	149:156823d33999	1921	* @arg TIM_OPMODE_REPETITIVE: Repetitive pulses wil be generated.
<>	149:156823d33999	1922	* @retval HAL status
<>	149:156823d33999	1923	*/
<>	149:156823d33999	1924	HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
<>	149:156823d33999	1925	{
<>	149:156823d33999	1926	/* Check the TIM handle allocation */
<>	149:156823d33999	1927	if(htim == NULL)
<>	149:156823d33999	1928	{
<>	149:156823d33999	1929	return HAL_ERROR;
<>	149:156823d33999	1930	}
<>	149:156823d33999	1931
<>	149:156823d33999	1932	/* Check the parameters */
<>	149:156823d33999	1933	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	149:156823d33999	1934	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
<>	149:156823d33999	1935	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
<>	149:156823d33999	1936	assert_param(IS_TIM_OPM_MODE(OnePulseMode));
<>	149:156823d33999	1937
<>	149:156823d33999	1938	if(htim->State == HAL_TIM_STATE_RESET)
<>	149:156823d33999	1939	{
<>	149:156823d33999	1940	/* Allocate lock resource and initialize it */
<>	149:156823d33999	1941	htim->Lock = HAL_UNLOCKED;
<>	149:156823d33999	1942
<>	149:156823d33999	1943	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
<>	149:156823d33999	1944	HAL_TIM_OnePulse_MspInit(htim);
<>	149:156823d33999	1945	}
<>	149:156823d33999	1946
<>	149:156823d33999	1947	/* Set the TIM state */
<>	149:156823d33999	1948	htim->State= HAL_TIM_STATE_BUSY;
<>	149:156823d33999	1949
<>	149:156823d33999	1950	/* Configure the Time base in the One Pulse Mode */
<>	149:156823d33999	1951	TIM_Base_SetConfig(htim->Instance, &htim->Init);
<>	149:156823d33999	1952
<>	149:156823d33999	1953	/* Reset the OPM Bit */
<>	149:156823d33999	1954	htim->Instance->CR1 &= ~TIM_CR1_OPM;
<>	149:156823d33999	1955
<>	149:156823d33999	1956	/* Configure the OPM Mode */
<>	149:156823d33999	1957	htim->Instance->CR1 \|= OnePulseMode;
<>	149:156823d33999	1958
<>	149:156823d33999	1959	/* Initialize the TIM state*/
<>	149:156823d33999	1960	htim->State= HAL_TIM_STATE_READY;
<>	149:156823d33999	1961
<>	149:156823d33999	1962	return HAL_OK;
<>	149:156823d33999	1963	}
<>	149:156823d33999	1964
<>	149:156823d33999	1965	/**
<>	149:156823d33999	1966	* @brief DeInitializes the TIM One Pulse
<>	149:156823d33999	1967	* @param htim: TIM One Pulse handle
<>	149:156823d33999	1968	* @retval HAL status
<>	149:156823d33999	1969	*/
<>	149:156823d33999	1970	HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
<>	149:156823d33999	1971	{
<>	149:156823d33999	1972	/* Check the parameters */
<>	149:156823d33999	1973	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	149:156823d33999	1974
<>	149:156823d33999	1975	htim->State = HAL_TIM_STATE_BUSY;
<>	149:156823d33999	1976
<>	149:156823d33999	1977	/* Disable the TIM Peripheral Clock */
<>	149:156823d33999	1978	__HAL_TIM_DISABLE(htim);
<>	149:156823d33999	1979
<>	149:156823d33999	1980	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
<>	149:156823d33999	1981	HAL_TIM_OnePulse_MspDeInit(htim);
<>	149:156823d33999	1982
<>	149:156823d33999	1983	/* Change TIM state */
<>	149:156823d33999	1984	htim->State = HAL_TIM_STATE_RESET;
<>	149:156823d33999	1985
<>	149:156823d33999	1986	/* Release Lock */
<>	149:156823d33999	1987	__HAL_UNLOCK(htim);
<>	149:156823d33999	1988
<>	149:156823d33999	1989	return HAL_OK;
<>	149:156823d33999	1990	}
<>	149:156823d33999	1991
<>	149:156823d33999	1992	/**
<>	149:156823d33999	1993	* @brief Initializes the TIM One Pulse MSP.
<>	149:156823d33999	1994	* @param htim: TIM handle
<>	149:156823d33999	1995	* @retval None
<>	149:156823d33999	1996	*/
<>	149:156823d33999	1997	__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
<>	149:156823d33999	1998	{
<>	149:156823d33999	1999	/* Prevent unused argument(s) compilation warning */
<>	149:156823d33999	2000	UNUSED(htim);
<>	149:156823d33999	2001
<>	149:156823d33999	2002	/* NOTE : This function Should not be modified, when the callback is needed,
<>	149:156823d33999	2003	the HAL_TIM_OnePulse_MspInit could be implemented in the user file
<>	149:156823d33999	2004	*/
<>	149:156823d33999	2005	}
<>	149:156823d33999	2006
<>	149:156823d33999	2007	/**
<>	149:156823d33999	2008	* @brief DeInitializes TIM One Pulse MSP.
<>	149:156823d33999	2009	* @param htim: TIM handle
<>	149:156823d33999	2010	* @retval None
<>	149:156823d33999	2011	*/
<>	149:156823d33999	2012	__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
<>	149:156823d33999	2013	{
<>	149:156823d33999	2014	/* Prevent unused argument(s) compilation warning */
<>	149:156823d33999	2015	UNUSED(htim);
<>	149:156823d33999	2016
<>	149:156823d33999	2017	/* NOTE : This function Should not be modified, when the callback is needed,
<>	149:156823d33999	2018	the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
<>	149:156823d33999	2019	*/
<>	149:156823d33999	2020	}
<>	149:156823d33999	2021
<>	149:156823d33999	2022	/**
<>	149:156823d33999	2023	* @brief Starts the TIM One Pulse signal generation.
<>	149:156823d33999	2024	* @param htim : TIM One Pulse handle
<>	149:156823d33999	2025	* @param OutputChannel : TIM Channels to be enabled
<>	149:156823d33999	2026	* This parameter can be one of the following values:
<>	149:156823d33999	2027	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	149:156823d33999	2028	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	149:156823d33999	2029	* @retval HAL status
<>	149:156823d33999	2030	*/
<>	149:156823d33999	2031	HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<>	149:156823d33999	2032	{
<>	149:156823d33999	2033	/* Enable the Capture compare and the Input Capture channels
<>	149:156823d33999	2034	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
<>	149:156823d33999	2035	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
<>	149:156823d33999	2036	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
<>	149:156823d33999	2037	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
<>	149:156823d33999	2038
<>	149:156823d33999	2039	No need to enable the counter, it's enabled automatically by hardware
<>	149:156823d33999	2040	(the counter starts in response to a stimulus and generate a pulse */
<>	149:156823d33999	2041
<>	149:156823d33999	2042	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<>	149:156823d33999	2043	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<>	149:156823d33999	2044
<>	149:156823d33999	2045	/* Return function status */
<>	149:156823d33999	2046	return HAL_OK;
<>	149:156823d33999	2047	}
<>	149:156823d33999	2048
<>	149:156823d33999	2049	/**
<>	149:156823d33999	2050	* @brief Stops the TIM One Pulse signal generation.
<>	149:156823d33999	2051	* @param htim : TIM One Pulse handle
<>	149:156823d33999	2052	* @param OutputChannel : TIM Channels to be disable
<>	149:156823d33999	2053	* This parameter can be one of the following values:
<>	149:156823d33999	2054	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	149:156823d33999	2055	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	149:156823d33999	2056	* @retval HAL status
<>	149:156823d33999	2057	*/
<>	149:156823d33999	2058	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<>	149:156823d33999	2059	{
<>	149:156823d33999	2060	/* Disable the Capture compare and the Input Capture channels
<>	149:156823d33999	2061	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
<>	149:156823d33999	2062	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
<>	149:156823d33999	2063	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
<>	149:156823d33999	2064	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
<>	149:156823d33999	2065
<>	149:156823d33999	2066	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<>	149:156823d33999	2067	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<>	149:156823d33999	2068
<>	149:156823d33999	2069	/* Disable the Peripheral */
<>	149:156823d33999	2070	__HAL_TIM_DISABLE(htim);
<>	149:156823d33999	2071
<>	149:156823d33999	2072	/* Return function status */
<>	149:156823d33999	2073	return HAL_OK;
<>	149:156823d33999	2074	}
<>	149:156823d33999	2075
<>	149:156823d33999	2076	/**
<>	149:156823d33999	2077	* @brief Starts the TIM One Pulse signal generation in interrupt mode.
<>	149:156823d33999	2078	* @param htim : TIM One Pulse handle
<>	149:156823d33999	2079	* @param OutputChannel : TIM Channels to be enabled
<>	149:156823d33999	2080	* This parameter can be one of the following values:
<>	149:156823d33999	2081	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	149:156823d33999	2082	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	149:156823d33999	2083	* @retval HAL status
<>	149:156823d33999	2084	*/
<>	149:156823d33999	2085	HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<>	149:156823d33999	2086	{
<>	149:156823d33999	2087	/* Enable the Capture compare and the Input Capture channels
<>	149:156823d33999	2088	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
<>	149:156823d33999	2089	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
<>	149:156823d33999	2090	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
<>	149:156823d33999	2091	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
<>	149:156823d33999	2092
<>	149:156823d33999	2093	No need to enable the counter, it's enabled automatically by hardware
<>	149:156823d33999	2094	(the counter starts in response to a stimulus and generate a pulse */
<>	149:156823d33999	2095
<>	149:156823d33999	2096	/* Enable the TIM Capture/Compare 1 interrupt */
<>	149:156823d33999	2097	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<>	149:156823d33999	2098
<>	149:156823d33999	2099	/* Enable the TIM Capture/Compare 2 interrupt */
<>	149:156823d33999	2100	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<>	149:156823d33999	2101
<>	149:156823d33999	2102	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<>	149:156823d33999	2103	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<>	149:156823d33999	2104
<>	149:156823d33999	2105	/* Return function status */
<>	149:156823d33999	2106	return HAL_OK;
<>	149:156823d33999	2107	}
<>	149:156823d33999	2108
<>	149:156823d33999	2109	/**
<>	149:156823d33999	2110	* @brief Stops the TIM One Pulse signal generation in interrupt mode.
<>	149:156823d33999	2111	* @param htim : TIM One Pulse handle
<>	149:156823d33999	2112	* @param OutputChannel : TIM Channels to be enabled
<>	149:156823d33999	2113	* This parameter can be one of the following values:
<>	149:156823d33999	2114	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	149:156823d33999	2115	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	149:156823d33999	2116	* @retval HAL status
<>	149:156823d33999	2117	*/
<>	149:156823d33999	2118	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<>	149:156823d33999	2119	{
<>	149:156823d33999	2120	/* Disable the TIM Capture/Compare 1 interrupt */
<>	149:156823d33999	2121	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<>	149:156823d33999	2122
<>	149:156823d33999	2123	/* Disable the TIM Capture/Compare 2 interrupt */
<>	149:156823d33999	2124	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<>	149:156823d33999	2125
<>	149:156823d33999	2126	/* Disable the Capture compare and the Input Capture channels
<>	149:156823d33999	2127	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
<>	149:156823d33999	2128	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
<>	149:156823d33999	2129	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
<>	149:156823d33999	2130	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
<>	149:156823d33999	2131	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<>	149:156823d33999	2132	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<>	149:156823d33999	2133
<>	149:156823d33999	2134	/* Disable the Peripheral */
<>	149:156823d33999	2135	__HAL_TIM_DISABLE(htim);
<>	149:156823d33999	2136
<>	149:156823d33999	2137	/* Return function status */
<>	149:156823d33999	2138	return HAL_OK;
<>	149:156823d33999	2139	}
<>	149:156823d33999	2140
<>	149:156823d33999	2141	/**
<>	149:156823d33999	2142	* @}
<>	149:156823d33999	2143	*/
<>	149:156823d33999	2144
<>	149:156823d33999	2145	/** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions
<>	149:156823d33999	2146	* @brief Time Encoder functions
<>	149:156823d33999	2147	*
<>	149:156823d33999	2148	@verbatim
<>	149:156823d33999	2149	==============================================================================
<>	149:156823d33999	2150	##### Time Encoder functions #####
<>	149:156823d33999	2151	==============================================================================
<>	149:156823d33999	2152	[..]
<>	149:156823d33999	2153	This section provides functions allowing to:
<>	149:156823d33999	2154	(+) Initialize and configure the TIM Encoder.
<>	149:156823d33999	2155	(+) De-initialize the TIM Encoder.
<>	149:156823d33999	2156	(+) Start the Time Encoder.
<>	149:156823d33999	2157	(+) Stop the Time Encoder.
<>	149:156823d33999	2158	(+) Start the Time Encoder and enable interrupt.
<>	149:156823d33999	2159	(+) Stop the Time Encoder and disable interrupt.
<>	149:156823d33999	2160	(+) Start the Time Encoder and enable DMA transfer.
<>	149:156823d33999	2161	(+) Stop the Time Encoder and disable DMA transfer.
<>	149:156823d33999	2162
<>	149:156823d33999	2163	@endverbatim
<>	149:156823d33999	2164	* @{
<>	149:156823d33999	2165	*/
<>	149:156823d33999	2166	/**
<>	149:156823d33999	2167	* @brief Initializes the TIM Encoder Interface and create the associated handle.
<>	149:156823d33999	2168	* @param htim: TIM Encoder Interface handle
<>	149:156823d33999	2169	* @param sConfig: TIM Encoder Interface configuration structure
<>	149:156823d33999	2170	* @retval HAL status
<>	149:156823d33999	2171	*/
<>	149:156823d33999	2172	HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef htim, TIM_Encoder_InitTypeDef sConfig)
<>	149:156823d33999	2173	{
<>	149:156823d33999	2174	uint32_t tmpsmcr = 0;
<>	149:156823d33999	2175	uint32_t tmpccmr1 = 0;
<>	149:156823d33999	2176	uint32_t tmpccer = 0;
<>	149:156823d33999	2177
<>	149:156823d33999	2178	/* Check the TIM handle allocation */
<>	149:156823d33999	2179	if(htim == NULL)
<>	149:156823d33999	2180	{
<>	149:156823d33999	2181	return HAL_ERROR;
<>	149:156823d33999	2182	}
<>	149:156823d33999	2183
<>	149:156823d33999	2184	/* Check the parameters */
<>	149:156823d33999	2185	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	149:156823d33999	2186	assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
<>	149:156823d33999	2187	assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
<>	149:156823d33999	2188	assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
<>	149:156823d33999	2189	assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
<>	149:156823d33999	2190	assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
<>	149:156823d33999	2191	assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
<>	149:156823d33999	2192	assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
<>	149:156823d33999	2193	assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
<>	149:156823d33999	2194	assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
<>	149:156823d33999	2195
<>	149:156823d33999	2196	if(htim->State == HAL_TIM_STATE_RESET)
<>	149:156823d33999	2197	{
<>	149:156823d33999	2198	/* Allocate lock resource and initialize it */
<>	149:156823d33999	2199	htim->Lock = HAL_UNLOCKED;
<>	149:156823d33999	2200
<>	149:156823d33999	2201	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
<>	149:156823d33999	2202	HAL_TIM_Encoder_MspInit(htim);
<>	149:156823d33999	2203	}
<>	149:156823d33999	2204
<>	149:156823d33999	2205	/* Set the TIM state */
<>	149:156823d33999	2206	htim->State= HAL_TIM_STATE_BUSY;
<>	149:156823d33999	2207
<>	149:156823d33999	2208	/* Reset the SMS bits */
<>	149:156823d33999	2209	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
<>	149:156823d33999	2210
<>	149:156823d33999	2211	/* Configure the Time base in the Encoder Mode */
<>	149:156823d33999	2212	TIM_Base_SetConfig(htim->Instance, &htim->Init);
<>	149:156823d33999	2213
<>	149:156823d33999	2214	/* Get the TIMx SMCR register value */
<>	149:156823d33999	2215	tmpsmcr = htim->Instance->SMCR;
<>	149:156823d33999	2216
<>	149:156823d33999	2217	/* Get the TIMx CCMR1 register value */
<>	149:156823d33999	2218	tmpccmr1 = htim->Instance->CCMR1;
<>	149:156823d33999	2219
<>	149:156823d33999	2220	/* Get the TIMx CCER register value */
<>	149:156823d33999	2221	tmpccer = htim->Instance->CCER;
<>	149:156823d33999	2222
<>	149:156823d33999	2223	/* Set the encoder Mode */
<>	149:156823d33999	2224	tmpsmcr \|= sConfig->EncoderMode;
<>	149:156823d33999	2225
<>	149:156823d33999	2226	/* Select the Capture Compare 1 and the Capture Compare 2 as input */
<>	149:156823d33999	2227	tmpccmr1 &= ~(TIM_CCMR1_CC1S \| TIM_CCMR1_CC2S);
<>	149:156823d33999	2228	tmpccmr1 \|= (sConfig->IC1Selection \| (sConfig->IC2Selection << 8));
<>	149:156823d33999	2229
<>	149:156823d33999	2230	/* Set the the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
<>	149:156823d33999	2231	tmpccmr1 &= ~(TIM_CCMR1_IC1PSC \| TIM_CCMR1_IC2PSC);
<>	149:156823d33999	2232	tmpccmr1 &= ~(TIM_CCMR1_IC1F \| TIM_CCMR1_IC2F);
<>	149:156823d33999	2233	tmpccmr1 \|= sConfig->IC1Prescaler \| (sConfig->IC2Prescaler << 8);
<>	149:156823d33999	2234	tmpccmr1 \|= (sConfig->IC1Filter << 4) \| (sConfig->IC2Filter << 12);
<>	149:156823d33999	2235
<>	149:156823d33999	2236	/* Set the TI1 and the TI2 Polarities */
<>	149:156823d33999	2237	tmpccer &= ~(TIM_CCER_CC1P \| TIM_CCER_CC2P);
<>	149:156823d33999	2238	tmpccer &= ~(TIM_CCER_CC1NP \| TIM_CCER_CC2NP);
<>	149:156823d33999	2239	tmpccer \|= sConfig->IC1Polarity \| (sConfig->IC2Polarity << 4);
<>	149:156823d33999	2240
<>	149:156823d33999	2241	/* Write to TIMx SMCR */
<>	149:156823d33999	2242	htim->Instance->SMCR = tmpsmcr;
<>	149:156823d33999	2243
<>	149:156823d33999	2244	/* Write to TIMx CCMR1 */
<>	149:156823d33999	2245	htim->Instance->CCMR1 = tmpccmr1;
<>	149:156823d33999	2246
<>	149:156823d33999	2247	/* Write to TIMx CCER */
<>	149:156823d33999	2248	htim->Instance->CCER = tmpccer;
<>	149:156823d33999	2249
<>	149:156823d33999	2250	/* Initialize the TIM state*/
<>	149:156823d33999	2251	htim->State= HAL_TIM_STATE_READY;
<>	149:156823d33999	2252
<>	149:156823d33999	2253	return HAL_OK;
<>	149:156823d33999	2254	}
<>	149:156823d33999	2255
<>	149:156823d33999	2256
<>	149:156823d33999	2257	/**
<>	149:156823d33999	2258	* @brief DeInitializes the TIM Encoder interface
<>	149:156823d33999	2259	* @param htim: TIM Encoder handle
<>	149:156823d33999	2260	* @retval HAL status
<>	149:156823d33999	2261	*/
<>	149:156823d33999	2262	HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
<>	149:156823d33999	2263	{
<>	149:156823d33999	2264	/* Check the parameters */
<>	149:156823d33999	2265	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	149:156823d33999	2266
<>	149:156823d33999	2267	htim->State = HAL_TIM_STATE_BUSY;
<>	149:156823d33999	2268
<>	149:156823d33999	2269	/* Disable the TIM Peripheral Clock */
<>	149:156823d33999	2270	__HAL_TIM_DISABLE(htim);
<>	149:156823d33999	2271
<>	149:156823d33999	2272	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
<>	149:156823d33999	2273	HAL_TIM_Encoder_MspDeInit(htim);
<>	149:156823d33999	2274
<>	149:156823d33999	2275	/* Change TIM state */
<>	149:156823d33999	2276	htim->State = HAL_TIM_STATE_RESET;
<>	149:156823d33999	2277
<>	149:156823d33999	2278	/* Release Lock */
<>	149:156823d33999	2279	__HAL_UNLOCK(htim);
<>	149:156823d33999	2280
<>	149:156823d33999	2281	return HAL_OK;
<>	149:156823d33999	2282	}
<>	149:156823d33999	2283
<>	149:156823d33999	2284	/**
<>	149:156823d33999	2285	* @brief Initializes the TIM Encoder Interface MSP.
<>	149:156823d33999	2286	* @param htim: TIM handle
<>	149:156823d33999	2287	* @retval None
<>	149:156823d33999	2288	*/
<>	149:156823d33999	2289	__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
<>	149:156823d33999	2290	{
<>	149:156823d33999	2291	/* Prevent unused argument(s) compilation warning */
<>	149:156823d33999	2292	UNUSED(htim);
<>	149:156823d33999	2293
<>	149:156823d33999	2294	/* NOTE : This function Should not be modified, when the callback is needed,
<>	149:156823d33999	2295	the HAL_TIM_Encoder_MspInit could be implemented in the user file
<>	149:156823d33999	2296	*/
<>	149:156823d33999	2297	}
<>	149:156823d33999	2298
<>	149:156823d33999	2299	/**
<>	149:156823d33999	2300	* @brief DeInitializes TIM Encoder Interface MSP.
<>	149:156823d33999	2301	* @param htim: TIM handle
<>	149:156823d33999	2302	* @retval None
<>	149:156823d33999	2303	*/
<>	149:156823d33999	2304	__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
<>	149:156823d33999	2305	{
<>	149:156823d33999	2306	/* Prevent unused argument(s) compilation warning */
<>	149:156823d33999	2307	UNUSED(htim);
<>	149:156823d33999	2308
<>	149:156823d33999	2309	/* NOTE : This function Should not be modified, when the callback is needed,
<>	149:156823d33999	2310	the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
<>	149:156823d33999	2311	*/
<>	149:156823d33999	2312	}
<>	149:156823d33999	2313
<>	149:156823d33999	2314	/**
<>	149:156823d33999	2315	* @brief Starts the TIM Encoder Interface.
<>	149:156823d33999	2316	* @param htim : TIM Encoder Interface handle
<>	149:156823d33999	2317	* @param Channel : TIM Channels to be enabled
<>	149:156823d33999	2318	* This parameter can be one of the following values:
<>	149:156823d33999	2319	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	149:156823d33999	2320	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	149:156823d33999	2321	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
<>	149:156823d33999	2322	* @retval HAL status
<>	149:156823d33999	2323	*/
<>	149:156823d33999	2324	HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	149:156823d33999	2325	{
<>	149:156823d33999	2326	/* Check the parameters */
<>	149:156823d33999	2327	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	149:156823d33999	2328
<>	149:156823d33999	2329	/* Enable the encoder interface channels */
<>	149:156823d33999	2330	switch (Channel)
<>	149:156823d33999	2331	{
<>	149:156823d33999	2332	case TIM_CHANNEL_1:
<>	149:156823d33999	2333	{
<>	149:156823d33999	2334	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<>	149:156823d33999	2335	break;
<>	149:156823d33999	2336	}
<>	149:156823d33999	2337	case TIM_CHANNEL_2:
<>	149:156823d33999	2338	{
<>	149:156823d33999	2339	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<>	149:156823d33999	2340	break;
<>	149:156823d33999	2341	}
<>	149:156823d33999	2342	default :
<>	149:156823d33999	2343	{
<>	149:156823d33999	2344	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<>	149:156823d33999	2345	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<>	149:156823d33999	2346	break;
<>	149:156823d33999	2347	}
<>	149:156823d33999	2348	}
<>	149:156823d33999	2349	/* Enable the Peripheral */
<>	149:156823d33999	2350	__HAL_TIM_ENABLE(htim);
<>	149:156823d33999	2351
<>	149:156823d33999	2352	/* Return function status */
<>	149:156823d33999	2353	return HAL_OK;
<>	149:156823d33999	2354	}
<>	149:156823d33999	2355
<>	149:156823d33999	2356	/**
<>	149:156823d33999	2357	* @brief Stops the TIM Encoder Interface.
<>	149:156823d33999	2358	* @param htim : TIM Encoder Interface handle
<>	149:156823d33999	2359	* @param Channel : TIM Channels to be disabled
<>	149:156823d33999	2360	* This parameter can be one of the following values:
<>	149:156823d33999	2361	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	149:156823d33999	2362	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	149:156823d33999	2363	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
<>	149:156823d33999	2364	* @retval HAL status
<>	149:156823d33999	2365	*/
<>	149:156823d33999	2366	HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	149:156823d33999	2367	{
<>	149:156823d33999	2368	/* Check the parameters */
<>	149:156823d33999	2369	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	149:156823d33999	2370
<>	149:156823d33999	2371	/* Disable the Input Capture channels 1 and 2
<>	149:156823d33999	2372	(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
<>	149:156823d33999	2373	switch (Channel)
<>	149:156823d33999	2374	{
<>	149:156823d33999	2375	case TIM_CHANNEL_1:
<>	149:156823d33999	2376	{
<>	149:156823d33999	2377	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<>	149:156823d33999	2378	break;
<>	149:156823d33999	2379	}
<>	149:156823d33999	2380	case TIM_CHANNEL_2:
<>	149:156823d33999	2381	{
<>	149:156823d33999	2382	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<>	149:156823d33999	2383	break;
<>	149:156823d33999	2384	}
<>	149:156823d33999	2385	default :
<>	149:156823d33999	2386	{
<>	149:156823d33999	2387	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<>	149:156823d33999	2388	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<>	149:156823d33999	2389	break;
<>	149:156823d33999	2390	}
<>	149:156823d33999	2391	}
<>	149:156823d33999	2392
<>	149:156823d33999	2393	/* Disable the Peripheral */
<>	149:156823d33999	2394	__HAL_TIM_DISABLE(htim);
<>	149:156823d33999	2395
<>	149:156823d33999	2396	/* Return function status */
<>	149:156823d33999	2397	return HAL_OK;
<>	149:156823d33999	2398	}
<>	149:156823d33999	2399
<>	149:156823d33999	2400	/**
<>	149:156823d33999	2401	* @brief Starts the TIM Encoder Interface in interrupt mode.
<>	149:156823d33999	2402	* @param htim : TIM Encoder Interface handle
<>	149:156823d33999	2403	* @param Channel : TIM Channels to be enabled
<>	149:156823d33999	2404	* This parameter can be one of the following values:
<>	149:156823d33999	2405	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	149:156823d33999	2406	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	149:156823d33999	2407	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
<>	149:156823d33999	2408	* @retval HAL status
<>	149:156823d33999	2409	*/
<>	149:156823d33999	2410	HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	149:156823d33999	2411	{
<>	149:156823d33999	2412	/* Check the parameters */
<>	149:156823d33999	2413	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	149:156823d33999	2414
<>	149:156823d33999	2415	/* Enable the encoder interface channels */
<>	149:156823d33999	2416	/* Enable the capture compare Interrupts 1 and/or 2 */
<>	149:156823d33999	2417	switch (Channel)
<>	149:156823d33999	2418	{
<>	149:156823d33999	2419	case TIM_CHANNEL_1:
<>	149:156823d33999	2420	{
<>	149:156823d33999	2421	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<>	149:156823d33999	2422	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<>	149:156823d33999	2423	break;
<>	149:156823d33999	2424	}
<>	149:156823d33999	2425	case TIM_CHANNEL_2:
<>	149:156823d33999	2426	{
<>	149:156823d33999	2427	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<>	149:156823d33999	2428	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<>	149:156823d33999	2429	break;
<>	149:156823d33999	2430	}
<>	149:156823d33999	2431	default :
<>	149:156823d33999	2432	{
<>	149:156823d33999	2433	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<>	149:156823d33999	2434	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<>	149:156823d33999	2435	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<>	149:156823d33999	2436	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<>	149:156823d33999	2437	break;
<>	149:156823d33999	2438	}
<>	149:156823d33999	2439	}
<>	149:156823d33999	2440
<>	149:156823d33999	2441	/* Enable the Peripheral */
<>	149:156823d33999	2442	__HAL_TIM_ENABLE(htim);
<>	149:156823d33999	2443
<>	149:156823d33999	2444	/* Return function status */
<>	149:156823d33999	2445	return HAL_OK;
<>	149:156823d33999	2446	}
<>	149:156823d33999	2447
<>	149:156823d33999	2448	/**
<>	149:156823d33999	2449	* @brief Stops the TIM Encoder Interface in interrupt mode.
<>	149:156823d33999	2450	* @param htim : TIM Encoder Interface handle
<>	149:156823d33999	2451	* @param Channel : TIM Channels to be disabled
<>	149:156823d33999	2452	* This parameter can be one of the following values:
<>	149:156823d33999	2453	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	149:156823d33999	2454	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	149:156823d33999	2455	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
<>	149:156823d33999	2456	* @retval HAL status
<>	149:156823d33999	2457	*/
<>	149:156823d33999	2458	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	149:156823d33999	2459	{
<>	149:156823d33999	2460	/* Check the parameters */
<>	149:156823d33999	2461	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	149:156823d33999	2462
<>	149:156823d33999	2463	/* Disable the Input Capture channels 1 and 2
<>	149:156823d33999	2464	(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
<>	149:156823d33999	2465	if(Channel == TIM_CHANNEL_1)
<>	149:156823d33999	2466	{
<>	149:156823d33999	2467	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<>	149:156823d33999	2468
<>	149:156823d33999	2469	/* Disable the capture compare Interrupts 1 */
<>	149:156823d33999	2470	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<>	149:156823d33999	2471	}
<>	149:156823d33999	2472	else if(Channel == TIM_CHANNEL_2)
<>	149:156823d33999	2473	{
<>	149:156823d33999	2474	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<>	149:156823d33999	2475
<>	149:156823d33999	2476	/* Disable the capture compare Interrupts 2 */
<>	149:156823d33999	2477	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<>	149:156823d33999	2478	}
<>	149:156823d33999	2479	else
<>	149:156823d33999	2480	{
<>	149:156823d33999	2481	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<>	149:156823d33999	2482	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<>	149:156823d33999	2483
<>	149:156823d33999	2484	/* Disable the capture compare Interrupts 1 and 2 */
<>	149:156823d33999	2485	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<>	149:156823d33999	2486	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<>	149:156823d33999	2487	}
<>	149:156823d33999	2488
<>	149:156823d33999	2489	/* Disable the Peripheral */
<>	149:156823d33999	2490	__HAL_TIM_DISABLE(htim);
<>	149:156823d33999	2491
<>	149:156823d33999	2492	/* Change the htim state */
<>	149:156823d33999	2493	htim->State = HAL_TIM_STATE_READY;
<>	149:156823d33999	2494
<>	149:156823d33999	2495	/* Return function status */
<>	149:156823d33999	2496	return HAL_OK;
<>	149:156823d33999	2497	}
<>	149:156823d33999	2498
<>	149:156823d33999	2499	/**
<>	149:156823d33999	2500	* @brief Starts the TIM Encoder Interface in DMA mode.
<>	149:156823d33999	2501	* @param htim : TIM Encoder Interface handle
<>	149:156823d33999	2502	* @param Channel : TIM Channels to be enabled
<>	149:156823d33999	2503	* This parameter can be one of the following values:
<>	149:156823d33999	2504	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	149:156823d33999	2505	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	149:156823d33999	2506	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
<>	149:156823d33999	2507	* @param pData1: The destination Buffer address for IC1.
<>	149:156823d33999	2508	* @param pData2: The destination Buffer address for IC2.
<>	149:156823d33999	2509	* @param Length: The length of data to be transferred from TIM peripheral to memory.
<>	149:156823d33999	2510	* @retval HAL status
<>	149:156823d33999	2511	*/
<>	149:156823d33999	2512	HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData1, uint32_t *pData2, uint16_t Length)
<>	149:156823d33999	2513	{
<>	149:156823d33999	2514	/* Check the parameters */
<>	149:156823d33999	2515	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
<>	149:156823d33999	2516
<>	149:156823d33999	2517	if((htim->State == HAL_TIM_STATE_BUSY))
<>	149:156823d33999	2518	{
<>	149:156823d33999	2519	return HAL_BUSY;
<>	149:156823d33999	2520	}
<>	149:156823d33999	2521	else if((htim->State == HAL_TIM_STATE_READY))
<>	149:156823d33999	2522	{
<>	149:156823d33999	2523	if((((pData1 == 0) \|\| (pData2 == 0) )) && (Length > 0))
<>	149:156823d33999	2524	{
<>	149:156823d33999	2525	return HAL_ERROR;
<>	149:156823d33999	2526	}
<>	149:156823d33999	2527	else
<>	149:156823d33999	2528	{
<>	149:156823d33999	2529	htim->State = HAL_TIM_STATE_BUSY;
<>	149:156823d33999	2530	}
<>	149:156823d33999	2531	}
<>	149:156823d33999	2532	else
<>	149:156823d33999	2533	{
<>	149:156823d33999	2534	return HAL_ERROR;
<>	149:156823d33999	2535	}
<>	149:156823d33999	2536
<>	149:156823d33999	2537	switch (Channel)
<>	149:156823d33999	2538	{
<>	149:156823d33999	2539	case TIM_CHANNEL_1:
<>	149:156823d33999	2540	{
<>	149:156823d33999	2541	/* Set the DMA Period elapsed callback */
<>	149:156823d33999	2542	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
<>	149:156823d33999	2543
<>	149:156823d33999	2544	/* Set the DMA error callback */
<>	149:156823d33999	2545	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<>	149:156823d33999	2546
<>	149:156823d33999	2547	/* Enable the DMA channel */
<>	149:156823d33999	2548	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
<>	149:156823d33999	2549
<>	149:156823d33999	2550	/* Enable the TIM Input Capture DMA request */
<>	149:156823d33999	2551	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<>	149:156823d33999	2552
<>	149:156823d33999	2553	/* Enable the Peripheral */
<>	149:156823d33999	2554	__HAL_TIM_ENABLE(htim);
<>	149:156823d33999	2555
<>	149:156823d33999	2556	/* Enable the Capture compare channel */
<>	149:156823d33999	2557	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<>	149:156823d33999	2558	}
<>	149:156823d33999	2559	break;
<>	149:156823d33999	2560
<>	149:156823d33999	2561	case TIM_CHANNEL_2:
<>	149:156823d33999	2562	{
<>	149:156823d33999	2563	/* Set the DMA Period elapsed callback */
<>	149:156823d33999	2564	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
<>	149:156823d33999	2565
<>	149:156823d33999	2566	/* Set the DMA error callback */
<>	149:156823d33999	2567	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
<>	149:156823d33999	2568	/* Enable the DMA channel */
<>	149:156823d33999	2569	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
<>	149:156823d33999	2570
<>	149:156823d33999	2571	/* Enable the TIM Input Capture DMA request */
<>	149:156823d33999	2572	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<>	149:156823d33999	2573
<>	149:156823d33999	2574	/* Enable the Peripheral */
<>	149:156823d33999	2575	__HAL_TIM_ENABLE(htim);
<>	149:156823d33999	2576
<>	149:156823d33999	2577	/* Enable the Capture compare channel */
<>	149:156823d33999	2578	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<>	149:156823d33999	2579	}
<>	149:156823d33999	2580	break;
<>	149:156823d33999	2581
<>	149:156823d33999	2582	case TIM_CHANNEL_ALL:
<>	149:156823d33999	2583	{
<>	149:156823d33999	2584	/* Set the DMA Period elapsed callback */
<>	149:156823d33999	2585	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
<>	149:156823d33999	2586
<>	149:156823d33999	2587	/* Set the DMA error callback */
<>	149:156823d33999	2588	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<>	149:156823d33999	2589
<>	149:156823d33999	2590	/* Enable the DMA channel */
<>	149:156823d33999	2591	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
<>	149:156823d33999	2592
<>	149:156823d33999	2593	/* Set the DMA Period elapsed callback */
<>	149:156823d33999	2594	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
<>	149:156823d33999	2595
<>	149:156823d33999	2596	/* Set the DMA error callback */
<>	149:156823d33999	2597	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<>	149:156823d33999	2598
<>	149:156823d33999	2599	/* Enable the DMA channel */
<>	149:156823d33999	2600	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
<>	149:156823d33999	2601
<>	149:156823d33999	2602	/* Enable the Peripheral */
<>	149:156823d33999	2603	__HAL_TIM_ENABLE(htim);
<>	149:156823d33999	2604
<>	149:156823d33999	2605	/* Enable the Capture compare channel */
<>	149:156823d33999	2606	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<>	149:156823d33999	2607	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<>	149:156823d33999	2608
<>	149:156823d33999	2609	/* Enable the TIM Input Capture DMA request */
<>	149:156823d33999	2610	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<>	149:156823d33999	2611	/* Enable the TIM Input Capture DMA request */
<>	149:156823d33999	2612	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<>	149:156823d33999	2613	}
<>	149:156823d33999	2614	break;
<>	149:156823d33999	2615
<>	149:156823d33999	2616	default:
<>	149:156823d33999	2617	break;
<>	149:156823d33999	2618	}
<>	149:156823d33999	2619	/* Return function status */
<>	149:156823d33999	2620	return HAL_OK;
<>	149:156823d33999	2621	}
<>	149:156823d33999	2622
<>	149:156823d33999	2623	/**
<>	149:156823d33999	2624	* @brief Stops the TIM Encoder Interface in DMA mode.
<>	149:156823d33999	2625	* @param htim : TIM Encoder Interface handle
<>	149:156823d33999	2626	* @param Channel : TIM Channels to be enabled
<>	149:156823d33999	2627	* This parameter can be one of the following values:
<>	149:156823d33999	2628	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	149:156823d33999	2629	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	149:156823d33999	2630	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
<>	149:156823d33999	2631	* @retval HAL status
<>	149:156823d33999	2632	*/
<>	149:156823d33999	2633	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	149:156823d33999	2634	{
<>	149:156823d33999	2635	/* Check the parameters */
<>	149:156823d33999	2636	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
<>	149:156823d33999	2637
<>	149:156823d33999	2638	/* Disable the Input Capture channels 1 and 2
<>	149:156823d33999	2639	(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
<>	149:156823d33999	2640	if(Channel == TIM_CHANNEL_1)
<>	149:156823d33999	2641	{
<>	149:156823d33999	2642	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<>	149:156823d33999	2643
<>	149:156823d33999	2644	/* Disable the capture compare DMA Request 1 */
<>	149:156823d33999	2645	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<>	149:156823d33999	2646	}
<>	149:156823d33999	2647	else if(Channel == TIM_CHANNEL_2)
<>	149:156823d33999	2648	{
<>	149:156823d33999	2649	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<>	149:156823d33999	2650
<>	149:156823d33999	2651	/* Disable the capture compare DMA Request 2 */
<>	149:156823d33999	2652	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<>	149:156823d33999	2653	}
<>	149:156823d33999	2654	else
<>	149:156823d33999	2655	{
<>	149:156823d33999	2656	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<>	149:156823d33999	2657	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<>	149:156823d33999	2658
<>	149:156823d33999	2659	/* Disable the capture compare DMA Request 1 and 2 */
<>	149:156823d33999	2660	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<>	149:156823d33999	2661	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<>	149:156823d33999	2662	}
<>	149:156823d33999	2663
<>	149:156823d33999	2664	/* Disable the Peripheral */
<>	149:156823d33999	2665	__HAL_TIM_DISABLE(htim);
<>	149:156823d33999	2666
<>	149:156823d33999	2667	/* Change the htim state */
<>	149:156823d33999	2668	htim->State = HAL_TIM_STATE_READY;
<>	149:156823d33999	2669
<>	149:156823d33999	2670	/* Return function status */
<>	149:156823d33999	2671	return HAL_OK;
<>	149:156823d33999	2672	}
<>	149:156823d33999	2673
<>	149:156823d33999	2674	/**
<>	149:156823d33999	2675	* @}
<>	149:156823d33999	2676	*/
<>	149:156823d33999	2677	/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
<>	149:156823d33999	2678	* @brief IRQ handler management
<>	149:156823d33999	2679	*
<>	149:156823d33999	2680	@verbatim
<>	149:156823d33999	2681	==============================================================================
<>	149:156823d33999	2682	##### IRQ handler management #####
<>	149:156823d33999	2683	==============================================================================
<>	149:156823d33999	2684	[..]
<>	149:156823d33999	2685	This section provides Timer IRQ handler function.
<>	149:156823d33999	2686
<>	149:156823d33999	2687	@endverbatim
<>	149:156823d33999	2688	* @{
<>	149:156823d33999	2689	*/
<>	149:156823d33999	2690	/**
<>	149:156823d33999	2691	* @brief This function handles TIM interrupts requests.
<>	149:156823d33999	2692	* @param htim: TIM handle
<>	149:156823d33999	2693	* @retval None
<>	149:156823d33999	2694	*/
<>	149:156823d33999	2695	void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
<>	149:156823d33999	2696	{
<>	149:156823d33999	2697	/* Capture compare 1 event */
<>	149:156823d33999	2698	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
<>	149:156823d33999	2699	{
<>	149:156823d33999	2700	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET)
<>	149:156823d33999	2701	{
<>	149:156823d33999	2702	{
<>	149:156823d33999	2703	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
<>	149:156823d33999	2704	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
<>	149:156823d33999	2705
<>	149:156823d33999	2706	/* Input capture event */
<>	149:156823d33999	2707	if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00)
<>	149:156823d33999	2708	{
<>	149:156823d33999	2709	HAL_TIM_IC_CaptureCallback(htim);
<>	149:156823d33999	2710	}
<>	149:156823d33999	2711	/* Output compare event */
<>	149:156823d33999	2712	else
<>	149:156823d33999	2713	{
<>	149:156823d33999	2714	HAL_TIM_OC_DelayElapsedCallback(htim);
<>	149:156823d33999	2715	HAL_TIM_PWM_PulseFinishedCallback(htim);
<>	149:156823d33999	2716	}
<>	149:156823d33999	2717	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
<>	149:156823d33999	2718	}
<>	149:156823d33999	2719	}
<>	149:156823d33999	2720	}
<>	149:156823d33999	2721	/* Capture compare 2 event */
<>	149:156823d33999	2722	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
<>	149:156823d33999	2723	{
<>	149:156823d33999	2724	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET)
<>	149:156823d33999	2725	{
<>	149:156823d33999	2726	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
<>	149:156823d33999	2727	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
<>	149:156823d33999	2728	/* Input capture event */
<>	149:156823d33999	2729	if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00)
<>	149:156823d33999	2730	{
<>	149:156823d33999	2731	HAL_TIM_IC_CaptureCallback(htim);
<>	149:156823d33999	2732	}
<>	149:156823d33999	2733	/* Output compare event */
<>	149:156823d33999	2734	else
<>	149:156823d33999	2735	{
<>	149:156823d33999	2736	HAL_TIM_OC_DelayElapsedCallback(htim);
<>	149:156823d33999	2737	HAL_TIM_PWM_PulseFinishedCallback(htim);
<>	149:156823d33999	2738	}
<>	149:156823d33999	2739	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
<>	149:156823d33999	2740	}
<>	149:156823d33999	2741	}
<>	149:156823d33999	2742	/* Capture compare 3 event */
<>	149:156823d33999	2743	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
<>	149:156823d33999	2744	{
<>	149:156823d33999	2745	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET)
<>	149:156823d33999	2746	{
<>	149:156823d33999	2747	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
<>	149:156823d33999	2748	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
<>	149:156823d33999	2749	/* Input capture event */
<>	149:156823d33999	2750	if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00)
<>	149:156823d33999	2751	{
<>	149:156823d33999	2752	HAL_TIM_IC_CaptureCallback(htim);
<>	149:156823d33999	2753	}
<>	149:156823d33999	2754	/* Output compare event */
<>	149:156823d33999	2755	else
<>	149:156823d33999	2756	{
<>	149:156823d33999	2757	HAL_TIM_OC_DelayElapsedCallback(htim);
<>	149:156823d33999	2758	HAL_TIM_PWM_PulseFinishedCallback(htim);
<>	149:156823d33999	2759	}
<>	149:156823d33999	2760	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
<>	149:156823d33999	2761	}
<>	149:156823d33999	2762	}
<>	149:156823d33999	2763	/* Capture compare 4 event */
<>	149:156823d33999	2764	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
<>	149:156823d33999	2765	{
<>	149:156823d33999	2766	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET)
<>	149:156823d33999	2767	{
<>	149:156823d33999	2768	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
<>	149:156823d33999	2769	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
<>	149:156823d33999	2770	/* Input capture event */
<>	149:156823d33999	2771	if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00)
<>	149:156823d33999	2772	{
<>	149:156823d33999	2773	HAL_TIM_IC_CaptureCallback(htim);
<>	149:156823d33999	2774	}
<>	149:156823d33999	2775	/* Output compare event */
<>	149:156823d33999	2776	else
<>	149:156823d33999	2777	{
<>	149:156823d33999	2778	HAL_TIM_OC_DelayElapsedCallback(htim);
<>	149:156823d33999	2779	HAL_TIM_PWM_PulseFinishedCallback(htim);
<>	149:156823d33999	2780	}
<>	149:156823d33999	2781	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
<>	149:156823d33999	2782	}
<>	149:156823d33999	2783	}
<>	149:156823d33999	2784	/* TIM Update event */
<>	149:156823d33999	2785	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
<>	149:156823d33999	2786	{
<>	149:156823d33999	2787	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET)
<>	149:156823d33999	2788	{
<>	149:156823d33999	2789	__HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
<>	149:156823d33999	2790	HAL_TIM_PeriodElapsedCallback(htim);
<>	149:156823d33999	2791	}
<>	149:156823d33999	2792	}
<>	149:156823d33999	2793	/* TIM Trigger detection event */
<>	149:156823d33999	2794	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
<>	149:156823d33999	2795	{
<>	149:156823d33999	2796	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET)
<>	149:156823d33999	2797	{
<>	149:156823d33999	2798	__HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
<>	149:156823d33999	2799	HAL_TIM_TriggerCallback(htim);
<>	149:156823d33999	2800	}
<>	149:156823d33999	2801	}
<>	149:156823d33999	2802	}
<>	149:156823d33999	2803
<>	149:156823d33999	2804	/**
<>	149:156823d33999	2805	* @}
<>	149:156823d33999	2806	*/
<>	149:156823d33999	2807
<>	149:156823d33999	2808	/** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
<>	149:156823d33999	2809	* @brief Peripheral Control functions
<>	149:156823d33999	2810	*
<>	149:156823d33999	2811	@verbatim
<>	149:156823d33999	2812	==============================================================================
<>	149:156823d33999	2813	##### Peripheral Control functions #####
<>	149:156823d33999	2814	==============================================================================
<>	149:156823d33999	2815	[..]
<>	149:156823d33999	2816	This section provides functions allowing to:
<>	149:156823d33999	2817	(+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
<>	149:156823d33999	2818	(+) Configure External Clock source.
<>	149:156823d33999	2819	(+) Configure Complementary channels, break features and dead time.
<>	149:156823d33999	2820	(+) Configure Master and the Slave synchronization.
<>	149:156823d33999	2821	(+) Configure the DMA Burst Mode.
<>	149:156823d33999	2822
<>	149:156823d33999	2823	@endverbatim
<>	149:156823d33999	2824	* @{
<>	149:156823d33999	2825	*/
<>	149:156823d33999	2826
<>	149:156823d33999	2827	/**
<>	149:156823d33999	2828	* @brief Initializes the TIM Output Compare Channels according to the specified
<>	149:156823d33999	2829	* parameters in the TIM_OC_InitTypeDef.
<>	149:156823d33999	2830	* @param htim: TIM Output Compare handle
<>	149:156823d33999	2831	* @param sConfig: TIM Output Compare configuration structure
<>	149:156823d33999	2832	* @param Channel : TIM Channels to configure
<>	149:156823d33999	2833	* This parameter can be one of the following values:
<>	149:156823d33999	2834	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	149:156823d33999	2835	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	149:156823d33999	2836	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	149:156823d33999	2837	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	149:156823d33999	2838	* @retval HAL status
<>	149:156823d33999	2839	*/
<>	149:156823d33999	2840	HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel)
<>	149:156823d33999	2841	{
<>	149:156823d33999	2842	/* Check the parameters */
<>	149:156823d33999	2843	assert_param(IS_TIM_CHANNELS(Channel));
<>	149:156823d33999	2844	assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
<>	149:156823d33999	2845	assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
<>	149:156823d33999	2846
<>	149:156823d33999	2847	/* Check input state */
<>	149:156823d33999	2848	__HAL_LOCK(htim);
<>	149:156823d33999	2849
<>	149:156823d33999	2850	htim->State = HAL_TIM_STATE_BUSY;
<>	149:156823d33999	2851
<>	149:156823d33999	2852	switch (Channel)
<>	149:156823d33999	2853	{
<>	149:156823d33999	2854	case TIM_CHANNEL_1:
<>	149:156823d33999	2855	{
<>	149:156823d33999	2856	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<>	149:156823d33999	2857	/* Configure the TIM Channel 1 in Output Compare */
<>	149:156823d33999	2858	TIM_OC1_SetConfig(htim->Instance, sConfig);
<>	149:156823d33999	2859	}
<>	149:156823d33999	2860	break;
<>	149:156823d33999	2861
<>	149:156823d33999	2862	case TIM_CHANNEL_2:
<>	149:156823d33999	2863	{
<>	149:156823d33999	2864	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	149:156823d33999	2865	/* Configure the TIM Channel 2 in Output Compare */
<>	149:156823d33999	2866	TIM_OC2_SetConfig(htim->Instance, sConfig);
<>	149:156823d33999	2867	}
<>	149:156823d33999	2868	break;
<>	149:156823d33999	2869
<>	149:156823d33999	2870	case TIM_CHANNEL_3:
<>	149:156823d33999	2871	{
<>	149:156823d33999	2872	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
<>	149:156823d33999	2873	/* Configure the TIM Channel 3 in Output Compare */
<>	149:156823d33999	2874	TIM_OC3_SetConfig(htim->Instance, sConfig);
<>	149:156823d33999	2875	}
<>	149:156823d33999	2876	break;
<>	149:156823d33999	2877
<>	149:156823d33999	2878	case TIM_CHANNEL_4:
<>	149:156823d33999	2879	{
<>	149:156823d33999	2880	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
<>	149:156823d33999	2881	/* Configure the TIM Channel 4 in Output Compare */
<>	149:156823d33999	2882	TIM_OC4_SetConfig(htim->Instance, sConfig);
<>	149:156823d33999	2883	}
<>	149:156823d33999	2884	break;
<>	149:156823d33999	2885
<>	149:156823d33999	2886	default:
<>	149:156823d33999	2887	break;
<>	149:156823d33999	2888	}
<>	149:156823d33999	2889	htim->State = HAL_TIM_STATE_READY;
<>	149:156823d33999	2890
<>	149:156823d33999	2891	__HAL_UNLOCK(htim);
<>	149:156823d33999	2892
<>	149:156823d33999	2893	return HAL_OK;
<>	149:156823d33999	2894	}
<>	149:156823d33999	2895
<>	149:156823d33999	2896	/**
<>	149:156823d33999	2897	* @brief Initializes the TIM Input Capture Channels according to the specified
<>	149:156823d33999	2898	* parameters in the TIM_IC_InitTypeDef.
<>	149:156823d33999	2899	* @param htim: TIM IC handle
<>	149:156823d33999	2900	* @param sConfig: TIM Input Capture configuration structure
<>	149:156823d33999	2901	* @param Channel : TIM Channels to be enabled
<>	149:156823d33999	2902	* This parameter can be one of the following values:
<>	149:156823d33999	2903	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	149:156823d33999	2904	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	149:156823d33999	2905	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	149:156823d33999	2906	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	149:156823d33999	2907	* @retval HAL status
<>	149:156823d33999	2908	*/
<>	149:156823d33999	2909	HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef htim, TIM_IC_InitTypeDef sConfig, uint32_t Channel)
<>	149:156823d33999	2910	{
<>	149:156823d33999	2911	/* Check the parameters */
<>	149:156823d33999	2912	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<>	149:156823d33999	2913	assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
<>	149:156823d33999	2914	assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
<>	149:156823d33999	2915	assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
<>	149:156823d33999	2916	assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
<>	149:156823d33999	2917
<>	149:156823d33999	2918	__HAL_LOCK(htim);
<>	149:156823d33999	2919
<>	149:156823d33999	2920	htim->State = HAL_TIM_STATE_BUSY;
<>	149:156823d33999	2921
<>	149:156823d33999	2922	if (Channel == TIM_CHANNEL_1)
<>	149:156823d33999	2923	{
<>	149:156823d33999	2924	/* TI1 Configuration */
<>	149:156823d33999	2925	TIM_TI1_SetConfig(htim->Instance,
<>	149:156823d33999	2926	sConfig->ICPolarity,
<>	149:156823d33999	2927	sConfig->ICSelection,
<>	149:156823d33999	2928	sConfig->ICFilter);
<>	149:156823d33999	2929
<>	149:156823d33999	2930	/* Reset the IC1PSC Bits */
<>	149:156823d33999	2931	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
<>	149:156823d33999	2932
<>	149:156823d33999	2933	/* Set the IC1PSC value */
<>	149:156823d33999	2934	htim->Instance->CCMR1 \|= sConfig->ICPrescaler;
<>	149:156823d33999	2935	}
<>	149:156823d33999	2936	else if (Channel == TIM_CHANNEL_2)
<>	149:156823d33999	2937	{
<>	149:156823d33999	2938	/* TI2 Configuration */
<>	149:156823d33999	2939	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	149:156823d33999	2940
<>	149:156823d33999	2941	TIM_TI2_SetConfig(htim->Instance,
<>	149:156823d33999	2942	sConfig->ICPolarity,
<>	149:156823d33999	2943	sConfig->ICSelection,
<>	149:156823d33999	2944	sConfig->ICFilter);
<>	149:156823d33999	2945
<>	149:156823d33999	2946	/* Reset the IC2PSC Bits */
<>	149:156823d33999	2947	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
<>	149:156823d33999	2948
<>	149:156823d33999	2949	/* Set the IC2PSC value */
<>	149:156823d33999	2950	htim->Instance->CCMR1 \|= (sConfig->ICPrescaler << 8);
<>	149:156823d33999	2951	}
<>	149:156823d33999	2952	else if (Channel == TIM_CHANNEL_3)
<>	149:156823d33999	2953	{
<>	149:156823d33999	2954	/* TI3 Configuration */
<>	149:156823d33999	2955	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
<>	149:156823d33999	2956
<>	149:156823d33999	2957	TIM_TI3_SetConfig(htim->Instance,
<>	149:156823d33999	2958	sConfig->ICPolarity,
<>	149:156823d33999	2959	sConfig->ICSelection,
<>	149:156823d33999	2960	sConfig->ICFilter);
<>	149:156823d33999	2961
<>	149:156823d33999	2962	/* Reset the IC3PSC Bits */
<>	149:156823d33999	2963	htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
<>	149:156823d33999	2964
<>	149:156823d33999	2965	/* Set the IC3PSC value */
<>	149:156823d33999	2966	htim->Instance->CCMR2 \|= sConfig->ICPrescaler;
<>	149:156823d33999	2967	}
<>	149:156823d33999	2968	else
<>	149:156823d33999	2969	{
<>	149:156823d33999	2970	/* TI4 Configuration */
<>	149:156823d33999	2971	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
<>	149:156823d33999	2972
<>	149:156823d33999	2973	TIM_TI4_SetConfig(htim->Instance,
<>	149:156823d33999	2974	sConfig->ICPolarity,
<>	149:156823d33999	2975	sConfig->ICSelection,
<>	149:156823d33999	2976	sConfig->ICFilter);
<>	149:156823d33999	2977
<>	149:156823d33999	2978	/* Reset the IC4PSC Bits */
<>	149:156823d33999	2979	htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
<>	149:156823d33999	2980
<>	149:156823d33999	2981	/* Set the IC4PSC value */
<>	149:156823d33999	2982	htim->Instance->CCMR2 \|= (sConfig->ICPrescaler << 8);
<>	149:156823d33999	2983	}
<>	149:156823d33999	2984
<>	149:156823d33999	2985	htim->State = HAL_TIM_STATE_READY;
<>	149:156823d33999	2986
<>	149:156823d33999	2987	__HAL_UNLOCK(htim);
<>	149:156823d33999	2988
<>	149:156823d33999	2989	return HAL_OK;
<>	149:156823d33999	2990	}
<>	149:156823d33999	2991
<>	149:156823d33999	2992	/**
<>	149:156823d33999	2993	* @brief Initializes the TIM PWM channels according to the specified
<>	149:156823d33999	2994	* parameters in the TIM_OC_InitTypeDef.
<>	149:156823d33999	2995	* @param htim: TIM PWM handle
<>	149:156823d33999	2996	* @param sConfig: TIM PWM configuration structure
<>	149:156823d33999	2997	* @param Channel : TIM Channels to be configured
<>	149:156823d33999	2998	* This parameter can be one of the following values:
<>	149:156823d33999	2999	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	149:156823d33999	3000	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	149:156823d33999	3001	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	149:156823d33999	3002	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	149:156823d33999	3003	* @retval HAL status
<>	149:156823d33999	3004	*/
<>	149:156823d33999	3005	HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel)
<>	149:156823d33999	3006	{
<>	149:156823d33999	3007	__HAL_LOCK(htim);
<>	149:156823d33999	3008
<>	149:156823d33999	3009	/* Check the parameters */
<>	149:156823d33999	3010	assert_param(IS_TIM_CHANNELS(Channel));
<>	149:156823d33999	3011	assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
<>	149:156823d33999	3012	assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
<>	149:156823d33999	3013	assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
<>	149:156823d33999	3014
<>	149:156823d33999	3015	htim->State = HAL_TIM_STATE_BUSY;
<>	149:156823d33999	3016
<>	149:156823d33999	3017	switch (Channel)
<>	149:156823d33999	3018	{
<>	149:156823d33999	3019	case TIM_CHANNEL_1:
<>	149:156823d33999	3020	{
<>	149:156823d33999	3021	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<>	149:156823d33999	3022	/* Configure the Channel 1 in PWM mode */
<>	149:156823d33999	3023	TIM_OC1_SetConfig(htim->Instance, sConfig);
<>	149:156823d33999	3024
<>	149:156823d33999	3025	/* Set the Preload enable bit for channel1 */
<>	149:156823d33999	3026	htim->Instance->CCMR1 \|= TIM_CCMR1_OC1PE;
<>	149:156823d33999	3027
<>	149:156823d33999	3028	/* Configure the Output Fast mode */
<>	149:156823d33999	3029	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
<>	149:156823d33999	3030	htim->Instance->CCMR1 \|= sConfig->OCFastMode;
<>	149:156823d33999	3031	}
<>	149:156823d33999	3032	break;
<>	149:156823d33999	3033
<>	149:156823d33999	3034	case TIM_CHANNEL_2:
<>	149:156823d33999	3035	{
<>	149:156823d33999	3036	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	149:156823d33999	3037	/* Configure the Channel 2 in PWM mode */
<>	149:156823d33999	3038	TIM_OC2_SetConfig(htim->Instance, sConfig);
<>	149:156823d33999	3039
<>	149:156823d33999	3040	/* Set the Preload enable bit for channel2 */
<>	149:156823d33999	3041	htim->Instance->CCMR1 \|= TIM_CCMR1_OC2PE;
<>	149:156823d33999	3042
<>	149:156823d33999	3043	/* Configure the Output Fast mode */
<>	149:156823d33999	3044	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
<>	149:156823d33999	3045	htim->Instance->CCMR1 \|= sConfig->OCFastMode << 8;
<>	149:156823d33999	3046	}
<>	149:156823d33999	3047	break;
<>	149:156823d33999	3048
<>	149:156823d33999	3049	case TIM_CHANNEL_3:
<>	149:156823d33999	3050	{
<>	149:156823d33999	3051	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
<>	149:156823d33999	3052	/* Configure the Channel 3 in PWM mode */
<>	149:156823d33999	3053	TIM_OC3_SetConfig(htim->Instance, sConfig);
<>	149:156823d33999	3054
<>	149:156823d33999	3055	/* Set the Preload enable bit for channel3 */
<>	149:156823d33999	3056	htim->Instance->CCMR2 \|= TIM_CCMR2_OC3PE;
<>	149:156823d33999	3057
<>	149:156823d33999	3058	/* Configure the Output Fast mode */
<>	149:156823d33999	3059	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
<>	149:156823d33999	3060	htim->Instance->CCMR2 \|= sConfig->OCFastMode;
<>	149:156823d33999	3061	}
<>	149:156823d33999	3062	break;
<>	149:156823d33999	3063
<>	149:156823d33999	3064	case TIM_CHANNEL_4:
<>	149:156823d33999	3065	{
<>	149:156823d33999	3066	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
<>	149:156823d33999	3067	/* Configure the Channel 4 in PWM mode */
<>	149:156823d33999	3068	TIM_OC4_SetConfig(htim->Instance, sConfig);
<>	149:156823d33999	3069
<>	149:156823d33999	3070	/* Set the Preload enable bit for channel4 */
<>	149:156823d33999	3071	htim->Instance->CCMR2 \|= TIM_CCMR2_OC4PE;
<>	149:156823d33999	3072
<>	149:156823d33999	3073	/* Configure the Output Fast mode */
<>	149:156823d33999	3074	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
<>	149:156823d33999	3075	htim->Instance->CCMR2 \|= sConfig->OCFastMode << 8;
<>	149:156823d33999	3076	}
<>	149:156823d33999	3077	break;
<>	149:156823d33999	3078
<>	149:156823d33999	3079	default:
<>	149:156823d33999	3080	break;
<>	149:156823d33999	3081	}
<>	149:156823d33999	3082
<>	149:156823d33999	3083	htim->State = HAL_TIM_STATE_READY;
<>	149:156823d33999	3084
<>	149:156823d33999	3085	__HAL_UNLOCK(htim);
<>	149:156823d33999	3086
<>	149:156823d33999	3087	return HAL_OK;
<>	149:156823d33999	3088	}
<>	149:156823d33999	3089
<>	149:156823d33999	3090	/**
<>	149:156823d33999	3091	* @brief Initializes the TIM One Pulse Channels according to the specified
<>	149:156823d33999	3092	* parameters in the TIM_OnePulse_InitTypeDef.
<>	149:156823d33999	3093	* @param htim: TIM One Pulse handle
<>	149:156823d33999	3094	* @param sConfig: TIM One Pulse configuration structure
<>	149:156823d33999	3095	* @param OutputChannel : TIM Channels to be enabled
<>	149:156823d33999	3096	* This parameter can be one of the following values:
<>	149:156823d33999	3097	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	149:156823d33999	3098	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	149:156823d33999	3099	* @param InputChannel : TIM Channels to be enabled
<>	149:156823d33999	3100	* This parameter can be one of the following values:
<>	149:156823d33999	3101	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	149:156823d33999	3102	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	149:156823d33999	3103	* @retval HAL status
<>	149:156823d33999	3104	*/
<>	149:156823d33999	3105	HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef htim, TIM_OnePulse_InitTypeDef sConfig, uint32_t OutputChannel, uint32_t InputChannel)
<>	149:156823d33999	3106	{
<>	149:156823d33999	3107	TIM_OC_InitTypeDef temp1;
<>	149:156823d33999	3108
<>	149:156823d33999	3109	/* Check the parameters */
<>	149:156823d33999	3110	assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
<>	149:156823d33999	3111	assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
<>	149:156823d33999	3112
<>	149:156823d33999	3113	if(OutputChannel != InputChannel)
<>	149:156823d33999	3114	{
<>	149:156823d33999	3115	__HAL_LOCK(htim);
<>	149:156823d33999	3116
<>	149:156823d33999	3117	htim->State = HAL_TIM_STATE_BUSY;
<>	149:156823d33999	3118
<>	149:156823d33999	3119	/* Extract the Ouput compare configuration from sConfig structure */
<>	149:156823d33999	3120	temp1.OCMode = sConfig->OCMode;
<>	149:156823d33999	3121	temp1.Pulse = sConfig->Pulse;
<>	149:156823d33999	3122	temp1.OCPolarity = sConfig->OCPolarity;
<>	149:156823d33999	3123	temp1.OCIdleState = sConfig->OCIdleState;
<>	149:156823d33999	3124
<>	149:156823d33999	3125	switch (OutputChannel)
<>	149:156823d33999	3126	{
<>	149:156823d33999	3127	case TIM_CHANNEL_1:
<>	149:156823d33999	3128	{
<>	149:156823d33999	3129	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<>	149:156823d33999	3130
<>	149:156823d33999	3131	TIM_OC1_SetConfig(htim->Instance, &temp1);
<>	149:156823d33999	3132	}
<>	149:156823d33999	3133	break;
<>	149:156823d33999	3134	case TIM_CHANNEL_2:
<>	149:156823d33999	3135	{
<>	149:156823d33999	3136	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	149:156823d33999	3137
<>	149:156823d33999	3138	TIM_OC2_SetConfig(htim->Instance, &temp1);
<>	149:156823d33999	3139	}
<>	149:156823d33999	3140	break;
<>	149:156823d33999	3141	default:
<>	149:156823d33999	3142	break;
<>	149:156823d33999	3143	}
<>	149:156823d33999	3144	switch (InputChannel)
<>	149:156823d33999	3145	{
<>	149:156823d33999	3146	case TIM_CHANNEL_1:
<>	149:156823d33999	3147	{
<>	149:156823d33999	3148	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<>	149:156823d33999	3149
<>	149:156823d33999	3150	TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
<>	149:156823d33999	3151	sConfig->ICSelection, sConfig->ICFilter);
<>	149:156823d33999	3152
<>	149:156823d33999	3153	/* Reset the IC1PSC Bits */
<>	149:156823d33999	3154	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
<>	149:156823d33999	3155
<>	149:156823d33999	3156	/* Select the Trigger source */
<>	149:156823d33999	3157	htim->Instance->SMCR &= ~TIM_SMCR_TS;
<>	149:156823d33999	3158	htim->Instance->SMCR \|= TIM_TS_TI1FP1;
<>	149:156823d33999	3159
<>	149:156823d33999	3160	/* Select the Slave Mode */
<>	149:156823d33999	3161	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
<>	149:156823d33999	3162	htim->Instance->SMCR \|= TIM_SLAVEMODE_TRIGGER;
<>	149:156823d33999	3163	}
<>	149:156823d33999	3164	break;
<>	149:156823d33999	3165	case TIM_CHANNEL_2:
<>	149:156823d33999	3166	{
<>	149:156823d33999	3167	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	149:156823d33999	3168
<>	149:156823d33999	3169	TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
<>	149:156823d33999	3170	sConfig->ICSelection, sConfig->ICFilter);
<>	149:156823d33999	3171
<>	149:156823d33999	3172	/* Reset the IC2PSC Bits */
<>	149:156823d33999	3173	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
<>	149:156823d33999	3174
<>	149:156823d33999	3175	/* Select the Trigger source */
<>	149:156823d33999	3176	htim->Instance->SMCR &= ~TIM_SMCR_TS;
<>	149:156823d33999	3177	htim->Instance->SMCR \|= TIM_TS_TI2FP2;
<>	149:156823d33999	3178
<>	149:156823d33999	3179	/* Select the Slave Mode */
<>	149:156823d33999	3180	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
<>	149:156823d33999	3181	htim->Instance->SMCR \|= TIM_SLAVEMODE_TRIGGER;
<>	149:156823d33999	3182	}
<>	149:156823d33999	3183	break;
<>	149:156823d33999	3184
<>	149:156823d33999	3185	default:
<>	149:156823d33999	3186	break;
<>	149:156823d33999	3187	}
<>	149:156823d33999	3188
<>	149:156823d33999	3189	htim->State = HAL_TIM_STATE_READY;
<>	149:156823d33999	3190
<>	149:156823d33999	3191	__HAL_UNLOCK(htim);
<>	149:156823d33999	3192
<>	149:156823d33999	3193	return HAL_OK;
<>	149:156823d33999	3194	}
<>	149:156823d33999	3195	else
<>	149:156823d33999	3196	{
<>	149:156823d33999	3197	return HAL_ERROR;
<>	149:156823d33999	3198	}
<>	149:156823d33999	3199	}
<>	149:156823d33999	3200
<>	149:156823d33999	3201	/**
<>	149:156823d33999	3202	* @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
<>	149:156823d33999	3203	* @param htim: TIM handle
<>	149:156823d33999	3204	* @param BurstBaseAddress : TIM Base address from where the DMA will start the Data write
<>	149:156823d33999	3205	* This parameter can be one of the following values:
<>	149:156823d33999	3206	* @arg TIM_DMABASE_CR1
<>	149:156823d33999	3207	* @arg TIM_DMABASE_CR2
<>	149:156823d33999	3208	* @arg TIM_DMABASE_SMCR
<>	149:156823d33999	3209	* @arg TIM_DMABASE_DIER
<>	149:156823d33999	3210	* @arg TIM_DMABASE_SR
<>	149:156823d33999	3211	* @arg TIM_DMABASE_EGR
<>	149:156823d33999	3212	* @arg TIM_DMABASE_CCMR1
<>	149:156823d33999	3213	* @arg TIM_DMABASE_CCMR2
<>	149:156823d33999	3214	* @arg TIM_DMABASE_CCER
<>	149:156823d33999	3215	* @arg TIM_DMABASE_CNT
<>	149:156823d33999	3216	* @arg TIM_DMABASE_PSC
<>	149:156823d33999	3217	* @arg TIM_DMABASE_ARR
<>	149:156823d33999	3218	* @arg TIM_DMABASE_CCR1
<>	149:156823d33999	3219	* @arg TIM_DMABASE_CCR2
<>	149:156823d33999	3220	* @arg TIM_DMABASE_CCR3
<>	149:156823d33999	3221	* @arg TIM_DMABASE_CCR4
<>	149:156823d33999	3222	* @arg TIM_DMABASE_DCR
<>	149:156823d33999	3223	* @param BurstRequestSrc: TIM DMA Request sources
<>	149:156823d33999	3224	* This parameter can be one of the following values:
<>	149:156823d33999	3225	* @arg TIM_DMA_UPDATE: TIM update Interrupt source
<>	149:156823d33999	3226	* @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
<>	149:156823d33999	3227	* @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
<>	149:156823d33999	3228	* @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
<>	149:156823d33999	3229	* @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
<>	149:156823d33999	3230	* @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
<>	149:156823d33999	3231	* @param BurstBuffer: The Buffer address.
<>	149:156823d33999	3232	* @param BurstLength: DMA Burst length. This parameter can be one value
<>	149:156823d33999	3233	* between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
<>	149:156823d33999	3234	* @retval HAL status
<>	149:156823d33999	3235	*/
<>	149:156823d33999	3236	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
<>	149:156823d33999	3237	uint32_t* BurstBuffer, uint32_t BurstLength)
<>	149:156823d33999	3238	{
<>	149:156823d33999	3239	/* Check the parameters */
<>	149:156823d33999	3240	assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
<>	149:156823d33999	3241	assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
<>	149:156823d33999	3242	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
<>	149:156823d33999	3243	assert_param(IS_TIM_DMA_LENGTH(BurstLength));
<>	149:156823d33999	3244
<>	149:156823d33999	3245	if((htim->State == HAL_TIM_STATE_BUSY))
<>	149:156823d33999	3246	{
<>	149:156823d33999	3247	return HAL_BUSY;
<>	149:156823d33999	3248	}
<>	149:156823d33999	3249	else if((htim->State == HAL_TIM_STATE_READY))
<>	149:156823d33999	3250	{
<>	149:156823d33999	3251	if((BurstBuffer == 0 ) && (BurstLength > 0))
<>	149:156823d33999	3252	{
<>	149:156823d33999	3253	return HAL_ERROR;
<>	149:156823d33999	3254	}
<>	149:156823d33999	3255	else
<>	149:156823d33999	3256	{
<>	149:156823d33999	3257	htim->State = HAL_TIM_STATE_BUSY;
<>	149:156823d33999	3258	}
<>	149:156823d33999	3259	}
<>	149:156823d33999	3260	else
<>	149:156823d33999	3261	{
<>	149:156823d33999	3262	return HAL_ERROR;
<>	149:156823d33999	3263	}
<>	149:156823d33999	3264
<>	149:156823d33999	3265	switch(BurstRequestSrc)
<>	149:156823d33999	3266	{
<>	149:156823d33999	3267	case TIM_DMA_UPDATE:
<>	149:156823d33999	3268	{
<>	149:156823d33999	3269	/* Set the DMA Period elapsed callback */
<>	149:156823d33999	3270	htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
<>	149:156823d33999	3271
<>	149:156823d33999	3272	/* Set the DMA error callback */
<>	149:156823d33999	3273	htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
<>	149:156823d33999	3274
<>	149:156823d33999	3275	/* Enable the DMA channel */
<>	149:156823d33999	3276	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
<>	149:156823d33999	3277	}
<>	149:156823d33999	3278	break;
<>	149:156823d33999	3279	case TIM_DMA_CC1:
<>	149:156823d33999	3280	{
<>	149:156823d33999	3281	/* Set the DMA Period elapsed callback */
<>	149:156823d33999	3282	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
<>	149:156823d33999	3283
<>	149:156823d33999	3284	/* Set the DMA error callback */
<>	149:156823d33999	3285	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<>	149:156823d33999	3286
<>	149:156823d33999	3287	/* Enable the DMA channel */
<>	149:156823d33999	3288	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
<>	149:156823d33999	3289	}
<>	149:156823d33999	3290	break;
<>	149:156823d33999	3291	case TIM_DMA_CC2:
<>	149:156823d33999	3292	{
<>	149:156823d33999	3293	/* Set the DMA Period elapsed callback */
<>	149:156823d33999	3294	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
<>	149:156823d33999	3295
<>	149:156823d33999	3296	/* Set the DMA error callback */
<>	149:156823d33999	3297	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<>	149:156823d33999	3298
<>	149:156823d33999	3299	/* Enable the DMA channel */
<>	149:156823d33999	3300	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
<>	149:156823d33999	3301	}
<>	149:156823d33999	3302	break;
<>	149:156823d33999	3303	case TIM_DMA_CC3:
<>	149:156823d33999	3304	{
<>	149:156823d33999	3305	/* Set the DMA Period elapsed callback */
<>	149:156823d33999	3306	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
<>	149:156823d33999	3307
<>	149:156823d33999	3308	/* Set the DMA error callback */
<>	149:156823d33999	3309	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
<>	149:156823d33999	3310
<>	149:156823d33999	3311	/* Enable the DMA channel */
<>	149:156823d33999	3312	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
<>	149:156823d33999	3313	}
<>	149:156823d33999	3314	break;
<>	149:156823d33999	3315	case TIM_DMA_CC4:
<>	149:156823d33999	3316	{
<>	149:156823d33999	3317	/* Set the DMA Period elapsed callback */
<>	149:156823d33999	3318	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
<>	149:156823d33999	3319
<>	149:156823d33999	3320	/* Set the DMA error callback */
<>	149:156823d33999	3321	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
<>	149:156823d33999	3322
<>	149:156823d33999	3323	/* Enable the DMA channel */
<>	149:156823d33999	3324	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
<>	149:156823d33999	3325	}
<>	149:156823d33999	3326	break;
<>	149:156823d33999	3327	case TIM_DMA_TRIGGER:
<>	149:156823d33999	3328	{
<>	149:156823d33999	3329	/* Set the DMA Period elapsed callback */
<>	149:156823d33999	3330	htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
<>	149:156823d33999	3331
<>	149:156823d33999	3332	/* Set the DMA error callback */
<>	149:156823d33999	3333	htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
<>	149:156823d33999	3334
<>	149:156823d33999	3335	/* Enable the DMA channel */
<>	149:156823d33999	3336	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
<>	149:156823d33999	3337	}
<>	149:156823d33999	3338	break;
<>	149:156823d33999	3339	default:
<>	149:156823d33999	3340	break;
<>	149:156823d33999	3341	}
<>	149:156823d33999	3342	/* configure the DMA Burst Mode */
<>	149:156823d33999	3343	htim->Instance->DCR = BurstBaseAddress \| BurstLength;
<>	149:156823d33999	3344
<>	149:156823d33999	3345	/* Enable the TIM DMA Request */
<>	149:156823d33999	3346	__HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
<>	149:156823d33999	3347
<>	149:156823d33999	3348	htim->State = HAL_TIM_STATE_READY;
<>	149:156823d33999	3349
<>	149:156823d33999	3350	/* Return function status */
<>	149:156823d33999	3351	return HAL_OK;
<>	149:156823d33999	3352	}
<>	149:156823d33999	3353
<>	149:156823d33999	3354	/**
<>	149:156823d33999	3355	* @brief Stops the TIM DMA Burst mode
<>	149:156823d33999	3356	* @param htim: TIM handle
<>	149:156823d33999	3357	* @param BurstRequestSrc: TIM DMA Request sources to disable
<>	149:156823d33999	3358	* @retval HAL status
<>	149:156823d33999	3359	*/
<>	149:156823d33999	3360	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
<>	149:156823d33999	3361	{
<>	149:156823d33999	3362	/* Check the parameters */
<>	149:156823d33999	3363	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
<>	149:156823d33999	3364
<>	149:156823d33999	3365	/* Abort the DMA transfer (at least disable the DMA channel) */
<>	149:156823d33999	3366	switch(BurstRequestSrc)
<>	149:156823d33999	3367	{
<>	149:156823d33999	3368	case TIM_DMA_UPDATE:
<>	149:156823d33999	3369	{
<>	149:156823d33999	3370	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
<>	149:156823d33999	3371	}
<>	149:156823d33999	3372	break;
<>	149:156823d33999	3373	case TIM_DMA_CC1:
<>	149:156823d33999	3374	{
<>	149:156823d33999	3375	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
<>	149:156823d33999	3376	}
<>	149:156823d33999	3377	break;
<>	149:156823d33999	3378	case TIM_DMA_CC2:
<>	149:156823d33999	3379	{
<>	149:156823d33999	3380	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
<>	149:156823d33999	3381	}
<>	149:156823d33999	3382	break;
<>	149:156823d33999	3383	case TIM_DMA_CC3:
<>	149:156823d33999	3384	{
<>	149:156823d33999	3385	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
<>	149:156823d33999	3386	}
<>	149:156823d33999	3387	break;
<>	149:156823d33999	3388	case TIM_DMA_CC4:
<>	149:156823d33999	3389	{
<>	149:156823d33999	3390	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
<>	149:156823d33999	3391	}
<>	149:156823d33999	3392	break;
<>	149:156823d33999	3393	case TIM_DMA_TRIGGER:
<>	149:156823d33999	3394	{
<>	149:156823d33999	3395	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
<>	149:156823d33999	3396	}
<>	149:156823d33999	3397	break;
<>	149:156823d33999	3398	default:
<>	149:156823d33999	3399	break;
<>	149:156823d33999	3400	}
<>	149:156823d33999	3401
<>	149:156823d33999	3402	/* Disable the TIM Update DMA request */
<>	149:156823d33999	3403	__HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
<>	149:156823d33999	3404
<>	149:156823d33999	3405	/* Return function status */
<>	149:156823d33999	3406	return HAL_OK;
<>	149:156823d33999	3407	}
<>	149:156823d33999	3408
<>	149:156823d33999	3409	/**
<>	149:156823d33999	3410	* @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
<>	149:156823d33999	3411	* @param htim: TIM handle
<>	149:156823d33999	3412	* @param BurstBaseAddress : TIM Base address from where the DMA will starts the Data read
<>	149:156823d33999	3413	* This parameter can be one of the following values:
<>	149:156823d33999	3414	* @arg TIM_DMABASE_CR1
<>	149:156823d33999	3415	* @arg TIM_DMABASE_CR2
<>	149:156823d33999	3416	* @arg TIM_DMABASE_SMCR
<>	149:156823d33999	3417	* @arg TIM_DMABASE_DIER
<>	149:156823d33999	3418	* @arg TIM_DMABASE_SR
<>	149:156823d33999	3419	* @arg TIM_DMABASE_EGR
<>	149:156823d33999	3420	* @arg TIM_DMABASE_CCMR1
<>	149:156823d33999	3421	* @arg TIM_DMABASE_CCMR2
<>	149:156823d33999	3422	* @arg TIM_DMABASE_CCER
<>	149:156823d33999	3423	* @arg TIM_DMABASE_CNT
<>	149:156823d33999	3424	* @arg TIM_DMABASE_PSC
<>	149:156823d33999	3425	* @arg TIM_DMABASE_ARR
<>	149:156823d33999	3426	* @arg TIM_DMABASE_CCR1
<>	149:156823d33999	3427	* @arg TIM_DMABASE_CCR2
<>	149:156823d33999	3428	* @arg TIM_DMABASE_CCR3
<>	149:156823d33999	3429	* @arg TIM_DMABASE_CCR4
<>	149:156823d33999	3430	* @arg TIM_DMABASE_DCR
<>	149:156823d33999	3431	* @param BurstRequestSrc: TIM DMA Request sources
<>	149:156823d33999	3432	* This parameter can be one of the following values:
<>	149:156823d33999	3433	* @arg TIM_DMA_UPDATE: TIM update Interrupt source
<>	149:156823d33999	3434	* @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
<>	149:156823d33999	3435	* @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
<>	149:156823d33999	3436	* @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
<>	149:156823d33999	3437	* @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
<>	149:156823d33999	3438	* @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
<>	149:156823d33999	3439	* @param BurstBuffer: The Buffer address.
<>	149:156823d33999	3440	* @param BurstLength: DMA Burst length. This parameter can be one value
<>	149:156823d33999	3441	* between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
<>	149:156823d33999	3442	* @retval HAL status
<>	149:156823d33999	3443	*/
<>	149:156823d33999	3444	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
<>	149:156823d33999	3445	uint32_t *BurstBuffer, uint32_t BurstLength)
<>	149:156823d33999	3446	{
<>	149:156823d33999	3447	/* Check the parameters */
<>	149:156823d33999	3448	assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
<>	149:156823d33999	3449	assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
<>	149:156823d33999	3450	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
<>	149:156823d33999	3451	assert_param(IS_TIM_DMA_LENGTH(BurstLength));
<>	149:156823d33999	3452
<>	149:156823d33999	3453	if((htim->State == HAL_TIM_STATE_BUSY))
<>	149:156823d33999	3454	{
<>	149:156823d33999	3455	return HAL_BUSY;
<>	149:156823d33999	3456	}
<>	149:156823d33999	3457	else if((htim->State == HAL_TIM_STATE_READY))
<>	149:156823d33999	3458	{
<>	149:156823d33999	3459	if((BurstBuffer == 0 ) && (BurstLength > 0))
<>	149:156823d33999	3460	{
<>	149:156823d33999	3461	return HAL_ERROR;
<>	149:156823d33999	3462	}
<>	149:156823d33999	3463	else
<>	149:156823d33999	3464	{
<>	149:156823d33999	3465	htim->State = HAL_TIM_STATE_BUSY;
<>	149:156823d33999	3466	}
<>	149:156823d33999	3467	}
<>	149:156823d33999	3468	else
<>	149:156823d33999	3469	{
<>	149:156823d33999	3470	return HAL_ERROR;
<>	149:156823d33999	3471	}
<>	149:156823d33999	3472
<>	149:156823d33999	3473	switch(BurstRequestSrc)
<>	149:156823d33999	3474	{
<>	149:156823d33999	3475	case TIM_DMA_UPDATE:
<>	149:156823d33999	3476	{
<>	149:156823d33999	3477	/* Set the DMA Period elapsed callback */
<>	149:156823d33999	3478	htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
<>	149:156823d33999	3479
<>	149:156823d33999	3480	/* Set the DMA error callback */
<>	149:156823d33999	3481	htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
<>	149:156823d33999	3482
<>	149:156823d33999	3483	/* Enable the DMA channel */
<>	149:156823d33999	3484	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
<>	149:156823d33999	3485	}
<>	149:156823d33999	3486	break;
<>	149:156823d33999	3487	case TIM_DMA_CC1:
<>	149:156823d33999	3488	{
<>	149:156823d33999	3489	/* Set the DMA Period elapsed callback */
<>	149:156823d33999	3490	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
<>	149:156823d33999	3491
<>	149:156823d33999	3492	/* Set the DMA error callback */
<>	149:156823d33999	3493	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<>	149:156823d33999	3494
<>	149:156823d33999	3495	/* Enable the DMA channel */
<>	149:156823d33999	3496	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
<>	149:156823d33999	3497	}
<>	149:156823d33999	3498	break;
<>	149:156823d33999	3499	case TIM_DMA_CC2:
<>	149:156823d33999	3500	{
<>	149:156823d33999	3501	/* Set the DMA Period elapsed callback */
<>	149:156823d33999	3502	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
<>	149:156823d33999	3503
<>	149:156823d33999	3504	/* Set the DMA error callback */
<>	149:156823d33999	3505	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<>	149:156823d33999	3506
<>	149:156823d33999	3507	/* Enable the DMA channel */
<>	149:156823d33999	3508	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
<>	149:156823d33999	3509	}
<>	149:156823d33999	3510	break;
<>	149:156823d33999	3511	case TIM_DMA_CC3:
<>	149:156823d33999	3512	{
<>	149:156823d33999	3513	/* Set the DMA Period elapsed callback */
<>	149:156823d33999	3514	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
<>	149:156823d33999	3515
<>	149:156823d33999	3516	/* Set the DMA error callback */
<>	149:156823d33999	3517	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
<>	149:156823d33999	3518
<>	149:156823d33999	3519	/* Enable the DMA channel */
<>	149:156823d33999	3520	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
<>	149:156823d33999	3521	}
<>	149:156823d33999	3522	break;
<>	149:156823d33999	3523	case TIM_DMA_CC4:
<>	149:156823d33999	3524	{
<>	149:156823d33999	3525	/* Set the DMA Period elapsed callback */
<>	149:156823d33999	3526	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
<>	149:156823d33999	3527
<>	149:156823d33999	3528	/* Set the DMA error callback */
<>	149:156823d33999	3529	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
<>	149:156823d33999	3530
<>	149:156823d33999	3531	/* Enable the DMA channel */
<>	149:156823d33999	3532	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
<>	149:156823d33999	3533	}
<>	149:156823d33999	3534	break;
<>	149:156823d33999	3535	case TIM_DMA_TRIGGER:
<>	149:156823d33999	3536	{
<>	149:156823d33999	3537	/* Set the DMA Period elapsed callback */
<>	149:156823d33999	3538	htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
<>	149:156823d33999	3539
<>	149:156823d33999	3540	/* Set the DMA error callback */
<>	149:156823d33999	3541	htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
<>	149:156823d33999	3542
<>	149:156823d33999	3543	/* Enable the DMA channel */
<>	149:156823d33999	3544	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
<>	149:156823d33999	3545	}
<>	149:156823d33999	3546	break;
<>	149:156823d33999	3547	default:
<>	149:156823d33999	3548	break;
<>	149:156823d33999	3549	}
<>	149:156823d33999	3550
<>	149:156823d33999	3551	/* configure the DMA Burst Mode */
<>	149:156823d33999	3552	htim->Instance->DCR = BurstBaseAddress \| BurstLength;
<>	149:156823d33999	3553
<>	149:156823d33999	3554	/* Enable the TIM DMA Request */
<>	149:156823d33999	3555	__HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
<>	149:156823d33999	3556
<>	149:156823d33999	3557	htim->State = HAL_TIM_STATE_READY;
<>	149:156823d33999	3558
<>	149:156823d33999	3559	/* Return function status */
<>	149:156823d33999	3560	return HAL_OK;
<>	149:156823d33999	3561	}
<>	149:156823d33999	3562
<>	149:156823d33999	3563	/**
<>	149:156823d33999	3564	* @brief Stop the DMA burst reading
<>	149:156823d33999	3565	* @param htim: TIM handle
<>	149:156823d33999	3566	* @param BurstRequestSrc: TIM DMA Request sources to disable.
<>	149:156823d33999	3567	* @retval HAL status
<>	149:156823d33999	3568	*/
<>	149:156823d33999	3569	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
<>	149:156823d33999	3570	{
<>	149:156823d33999	3571	/* Check the parameters */
<>	149:156823d33999	3572	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
<>	149:156823d33999	3573
<>	149:156823d33999	3574	/* Abort the DMA transfer (at least disable the DMA channel) */
<>	149:156823d33999	3575	switch(BurstRequestSrc)
<>	149:156823d33999	3576	{
<>	149:156823d33999	3577	case TIM_DMA_UPDATE:
<>	149:156823d33999	3578	{
<>	149:156823d33999	3579	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
<>	149:156823d33999	3580	}
<>	149:156823d33999	3581	break;
<>	149:156823d33999	3582	case TIM_DMA_CC1:
<>	149:156823d33999	3583	{
<>	149:156823d33999	3584	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
<>	149:156823d33999	3585	}
<>	149:156823d33999	3586	break;
<>	149:156823d33999	3587	case TIM_DMA_CC2:
<>	149:156823d33999	3588	{
<>	149:156823d33999	3589	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
<>	149:156823d33999	3590	}
<>	149:156823d33999	3591	break;
<>	149:156823d33999	3592	case TIM_DMA_CC3:
<>	149:156823d33999	3593	{
<>	149:156823d33999	3594	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
<>	149:156823d33999	3595	}
<>	149:156823d33999	3596	break;
<>	149:156823d33999	3597	case TIM_DMA_CC4:
<>	149:156823d33999	3598	{
<>	149:156823d33999	3599	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
<>	149:156823d33999	3600	}
<>	149:156823d33999	3601	break;
<>	149:156823d33999	3602	case TIM_DMA_TRIGGER:
<>	149:156823d33999	3603	{
<>	149:156823d33999	3604	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
<>	149:156823d33999	3605	}
<>	149:156823d33999	3606	break;
<>	149:156823d33999	3607	default:
<>	149:156823d33999	3608	break;
<>	149:156823d33999	3609	}
<>	149:156823d33999	3610
<>	149:156823d33999	3611	/* Disable the TIM Update DMA request */
<>	149:156823d33999	3612	__HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
<>	149:156823d33999	3613
<>	149:156823d33999	3614	/* Return function status */
<>	149:156823d33999	3615	return HAL_OK;
<>	149:156823d33999	3616	}
<>	149:156823d33999	3617
<>	149:156823d33999	3618	/**
<>	149:156823d33999	3619	* @brief Generate a software event
<>	149:156823d33999	3620	* @param htim: TIM handle
<>	149:156823d33999	3621	* @param EventSource: specifies the event source.
<>	149:156823d33999	3622	* This parameter can be one of the following values:
<>	149:156823d33999	3623	* @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
<>	149:156823d33999	3624	* @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
<>	149:156823d33999	3625	* @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
<>	149:156823d33999	3626	* @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
<>	149:156823d33999	3627	* @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
<>	149:156823d33999	3628	* @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
<>	149:156823d33999	3629	* @note TIM6 and TIM7 can only generate an update event.
<>	149:156823d33999	3630	* @retval HAL status
<>	149:156823d33999	3631	*/
<>	149:156823d33999	3632
<>	149:156823d33999	3633	HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
<>	149:156823d33999	3634	{
<>	149:156823d33999	3635	/* Check the parameters */
<>	149:156823d33999	3636	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	149:156823d33999	3637	assert_param(IS_TIM_EVENT_SOURCE(EventSource));
<>	149:156823d33999	3638
<>	149:156823d33999	3639	/* Process Locked */
<>	149:156823d33999	3640	__HAL_LOCK(htim);
<>	149:156823d33999	3641
<>	149:156823d33999	3642	/* Change the TIM state */
<>	149:156823d33999	3643	htim->State = HAL_TIM_STATE_BUSY;
<>	149:156823d33999	3644
<>	149:156823d33999	3645	/* Set the event sources */
<>	149:156823d33999	3646	htim->Instance->EGR = EventSource;
<>	149:156823d33999	3647
<>	149:156823d33999	3648	/* Change the TIM state */
<>	149:156823d33999	3649	htim->State = HAL_TIM_STATE_READY;
<>	149:156823d33999	3650
<>	149:156823d33999	3651	__HAL_UNLOCK(htim);
<>	149:156823d33999	3652
<>	149:156823d33999	3653	/* Return function status */
<>	149:156823d33999	3654	return HAL_OK;
<>	149:156823d33999	3655	}
<>	149:156823d33999	3656
<>	149:156823d33999	3657	/**
<>	149:156823d33999	3658	* @brief Configures the OCRef clear feature
<>	149:156823d33999	3659	* @param htim: TIM handle
<>	149:156823d33999	3660	* @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that
<>	149:156823d33999	3661	* contains the OCREF clear feature and parameters for the TIM peripheral.
<>	149:156823d33999	3662	* @param Channel: specifies the TIM Channel
<>	149:156823d33999	3663	* This parameter can be one of the following values:
<>	149:156823d33999	3664	* @arg TIM_CHANNEL_1: TIM Channel 1
<>	149:156823d33999	3665	* @arg TIM_CHANNEL_2: TIM Channel 2
<>	149:156823d33999	3666	* @arg TIM_CHANNEL_3: TIM Channel 3
<>	149:156823d33999	3667	* @arg TIM_CHANNEL_4: TIM Channel 4
<>	149:156823d33999	3668	* @retval HAL status
<>	149:156823d33999	3669	*/
<>	149:156823d33999	3670	HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef htim, TIM_ClearInputConfigTypeDef sClearInputConfig, uint32_t Channel)
<>	149:156823d33999	3671	{
<>	149:156823d33999	3672
<>	149:156823d33999	3673	/* Check the parameters */
<>	149:156823d33999	3674	assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
<>	149:156823d33999	3675	assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
<>	149:156823d33999	3676	assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
<>	149:156823d33999	3677	assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
<>	149:156823d33999	3678	assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
<>	149:156823d33999	3679
<>	149:156823d33999	3680	/* Process Locked */
<>	149:156823d33999	3681	__HAL_LOCK(htim);
<>	149:156823d33999	3682
<>	149:156823d33999	3683	htim->State = HAL_TIM_STATE_BUSY;
<>	149:156823d33999	3684
<>	149:156823d33999	3685	switch (sClearInputConfig->ClearInputSource)
<>	149:156823d33999	3686	{
<>	149:156823d33999	3687	case TIM_CLEARINPUTSOURCE_NONE:
<>	149:156823d33999	3688	{
<>	149:156823d33999	3689	/* Clear the OCREF clear selection bit */
<>	149:156823d33999	3690	CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);
<>	149:156823d33999	3691
<>	149:156823d33999	3692	/* Clear the ETR Bits */
<>	149:156823d33999	3693	CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF \| TIM_SMCR_ETPS \| TIM_SMCR_ECE \| TIM_SMCR_ETP));
<>	149:156823d33999	3694
<>	149:156823d33999	3695	}
<>	149:156823d33999	3696	break;
<>	149:156823d33999	3697
<>	149:156823d33999	3698	case TIM_CLEARINPUTSOURCE_OCREFCLR:
<>	149:156823d33999	3699	{
<>	149:156823d33999	3700	/* Clear the OCREF clear selection bit */
<>	149:156823d33999	3701	CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);
<>	149:156823d33999	3702	}
<>	149:156823d33999	3703	break;
<>	149:156823d33999	3704
<>	149:156823d33999	3705	case TIM_CLEARINPUTSOURCE_ETR:
<>	149:156823d33999	3706	{
<>	149:156823d33999	3707	TIM_ETR_SetConfig(htim->Instance,
<>	149:156823d33999	3708	sClearInputConfig->ClearInputPrescaler,
<>	149:156823d33999	3709	sClearInputConfig->ClearInputPolarity,
<>	149:156823d33999	3710	sClearInputConfig->ClearInputFilter);
<>	149:156823d33999	3711
<>	149:156823d33999	3712	/* Set the OCREF clear selection bit */
<>	149:156823d33999	3713	SET_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);
<>	149:156823d33999	3714	}
<>	149:156823d33999	3715	break;
<>	149:156823d33999	3716
<>	149:156823d33999	3717	default:
<>	149:156823d33999	3718	break;
<>	149:156823d33999	3719
<>	149:156823d33999	3720	}
<>	149:156823d33999	3721
<>	149:156823d33999	3722	switch (Channel)
<>	149:156823d33999	3723	{
<>	149:156823d33999	3724	case TIM_CHANNEL_1:
<>	149:156823d33999	3725	{
<>	149:156823d33999	3726	if(sClearInputConfig->ClearInputState != RESET)
<>	149:156823d33999	3727	{
<>	149:156823d33999	3728	/* Enable the Ocref clear feature for Channel 1 */
<>	149:156823d33999	3729	htim->Instance->CCMR1 \|= TIM_CCMR1_OC1CE;
<>	149:156823d33999	3730	}
<>	149:156823d33999	3731	else
<>	149:156823d33999	3732	{
<>	149:156823d33999	3733	/* Disable the Ocref clear feature for Channel 1 */
<>	149:156823d33999	3734	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
<>	149:156823d33999	3735	}
<>	149:156823d33999	3736	}
<>	149:156823d33999	3737	break;
<>	149:156823d33999	3738	case TIM_CHANNEL_2:
<>	149:156823d33999	3739	{
<>	149:156823d33999	3740	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	149:156823d33999	3741	if(sClearInputConfig->ClearInputState != RESET)
<>	149:156823d33999	3742	{
<>	149:156823d33999	3743	/* Enable the Ocref clear feature for Channel 2 */
<>	149:156823d33999	3744	htim->Instance->CCMR1 \|= TIM_CCMR1_OC2CE;
<>	149:156823d33999	3745	}
<>	149:156823d33999	3746	else
<>	149:156823d33999	3747	{
<>	149:156823d33999	3748	/* Disable the Ocref clear feature for Channel 2 */
<>	149:156823d33999	3749	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
<>	149:156823d33999	3750	}
<>	149:156823d33999	3751	}
<>	149:156823d33999	3752	break;
<>	149:156823d33999	3753	case TIM_CHANNEL_3:
<>	149:156823d33999	3754	{
<>	149:156823d33999	3755	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
<>	149:156823d33999	3756	if(sClearInputConfig->ClearInputState != RESET)
<>	149:156823d33999	3757	{
<>	149:156823d33999	3758	/* Enable the Ocref clear feature for Channel 3 */
<>	149:156823d33999	3759	htim->Instance->CCMR2 \|= TIM_CCMR2_OC3CE;
<>	149:156823d33999	3760	}
<>	149:156823d33999	3761	else
<>	149:156823d33999	3762	{
<>	149:156823d33999	3763	/* Disable the Ocref clear feature for Channel 3 */
<>	149:156823d33999	3764	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
<>	149:156823d33999	3765	}
<>	149:156823d33999	3766	}
<>	149:156823d33999	3767	break;
<>	149:156823d33999	3768	case TIM_CHANNEL_4:
<>	149:156823d33999	3769	{
<>	149:156823d33999	3770	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
<>	149:156823d33999	3771	if(sClearInputConfig->ClearInputState != RESET)
<>	149:156823d33999	3772	{
<>	149:156823d33999	3773	/* Enable the Ocref clear feature for Channel 4 */
<>	149:156823d33999	3774	htim->Instance->CCMR2 \|= TIM_CCMR2_OC4CE;
<>	149:156823d33999	3775	}
<>	149:156823d33999	3776	else
<>	149:156823d33999	3777	{
<>	149:156823d33999	3778	/* Disable the Ocref clear feature for Channel 4 */
<>	149:156823d33999	3779	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
<>	149:156823d33999	3780	}
<>	149:156823d33999	3781	}
<>	149:156823d33999	3782	break;
<>	149:156823d33999	3783	default:
<>	149:156823d33999	3784	break;
<>	149:156823d33999	3785	}
<>	149:156823d33999	3786
<>	149:156823d33999	3787	htim->State = HAL_TIM_STATE_READY;
<>	149:156823d33999	3788
<>	149:156823d33999	3789	__HAL_UNLOCK(htim);
<>	149:156823d33999	3790
<>	149:156823d33999	3791	return HAL_OK;
<>	149:156823d33999	3792	}
<>	149:156823d33999	3793
<>	149:156823d33999	3794	/**
<>	149:156823d33999	3795	* @brief Configures the clock source to be used
<>	149:156823d33999	3796	* @param htim: TIM handle
<>	149:156823d33999	3797	* @param sClockSourceConfig: pointer to a TIM_ClockConfigTypeDef structure that
<>	149:156823d33999	3798	* contains the clock source information for the TIM peripheral.
<>	149:156823d33999	3799	* @retval HAL status
<>	149:156823d33999	3800	*/
<>	149:156823d33999	3801	HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef htim, TIM_ClockConfigTypeDef sClockSourceConfig)
<>	149:156823d33999	3802	{
<>	149:156823d33999	3803	uint32_t tmpsmcr = 0;
<>	149:156823d33999	3804
<>	149:156823d33999	3805	/* Process Locked */
<>	149:156823d33999	3806	__HAL_LOCK(htim);
<>	149:156823d33999	3807
<>	149:156823d33999	3808	htim->State = HAL_TIM_STATE_BUSY;
<>	149:156823d33999	3809
<>	149:156823d33999	3810	/* Check the parameters */
<>	149:156823d33999	3811	assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
<>	149:156823d33999	3812
<>	149:156823d33999	3813	/* Reset the SMS, TS, ECE, ETPS and ETRF bits */
<>	149:156823d33999	3814	tmpsmcr = htim->Instance->SMCR;
<>	149:156823d33999	3815	tmpsmcr &= ~(TIM_SMCR_SMS \| TIM_SMCR_TS);
<>	149:156823d33999	3816	tmpsmcr &= ~(TIM_SMCR_ETF \| TIM_SMCR_ETPS \| TIM_SMCR_ECE \| TIM_SMCR_ETP);
<>	149:156823d33999	3817	htim->Instance->SMCR = tmpsmcr;
<>	149:156823d33999	3818
<>	149:156823d33999	3819	switch (sClockSourceConfig->ClockSource)
<>	149:156823d33999	3820	{
<>	149:156823d33999	3821	case TIM_CLOCKSOURCE_INTERNAL:
<>	149:156823d33999	3822	{
<>	149:156823d33999	3823	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	149:156823d33999	3824	/* Disable slave mode to clock the prescaler directly with the internal clock */
<>	149:156823d33999	3825	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
<>	149:156823d33999	3826	}
<>	149:156823d33999	3827	break;
<>	149:156823d33999	3828
<>	149:156823d33999	3829	case TIM_CLOCKSOURCE_ETRMODE1:
<>	149:156823d33999	3830	{
<>	149:156823d33999	3831	/* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
<>	149:156823d33999	3832	assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
<>	149:156823d33999	3833
<>	149:156823d33999	3834	/* Check ETR input conditioning related parameters */
<>	149:156823d33999	3835	assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
<>	149:156823d33999	3836	assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
<>	149:156823d33999	3837	assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
<>	149:156823d33999	3838
<>	149:156823d33999	3839	/* Configure the ETR Clock source */
<>	149:156823d33999	3840	TIM_ETR_SetConfig(htim->Instance,
<>	149:156823d33999	3841	sClockSourceConfig->ClockPrescaler,
<>	149:156823d33999	3842	sClockSourceConfig->ClockPolarity,
<>	149:156823d33999	3843	sClockSourceConfig->ClockFilter);
<>	149:156823d33999	3844	/* Get the TIMx SMCR register value */
<>	149:156823d33999	3845	tmpsmcr = htim->Instance->SMCR;
<>	149:156823d33999	3846	/* Reset the SMS and TS Bits */
<>	149:156823d33999	3847	tmpsmcr &= ~(TIM_SMCR_SMS \| TIM_SMCR_TS);
<>	149:156823d33999	3848	/* Select the External clock mode1 and the ETRF trigger */
<>	149:156823d33999	3849	tmpsmcr \|= (TIM_SLAVEMODE_EXTERNAL1 \| TIM_CLOCKSOURCE_ETRMODE1);
<>	149:156823d33999	3850	/* Write to TIMx SMCR */
<>	149:156823d33999	3851	htim->Instance->SMCR = tmpsmcr;
<>	149:156823d33999	3852	}
<>	149:156823d33999	3853	break;
<>	149:156823d33999	3854
<>	149:156823d33999	3855	case TIM_CLOCKSOURCE_ETRMODE2:
<>	149:156823d33999	3856	{
<>	149:156823d33999	3857	/* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
<>	149:156823d33999	3858	assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
<>	149:156823d33999	3859
<>	149:156823d33999	3860	/* Check ETR input conditioning related parameters */
<>	149:156823d33999	3861	assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
<>	149:156823d33999	3862	assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
<>	149:156823d33999	3863	assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
<>	149:156823d33999	3864
<>	149:156823d33999	3865	/* Configure the ETR Clock source */
<>	149:156823d33999	3866	TIM_ETR_SetConfig(htim->Instance,
<>	149:156823d33999	3867	sClockSourceConfig->ClockPrescaler,
<>	149:156823d33999	3868	sClockSourceConfig->ClockPolarity,
<>	149:156823d33999	3869	sClockSourceConfig->ClockFilter);
<>	149:156823d33999	3870	/* Enable the External clock mode2 */
<>	149:156823d33999	3871	htim->Instance->SMCR \|= TIM_SMCR_ECE;
<>	149:156823d33999	3872	}
<>	149:156823d33999	3873	break;
<>	149:156823d33999	3874
<>	149:156823d33999	3875	case TIM_CLOCKSOURCE_TI1:
<>	149:156823d33999	3876	{
<>	149:156823d33999	3877	/* Check whether or not the timer instance supports external clock mode 1 */
<>	149:156823d33999	3878	assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
<>	149:156823d33999	3879
<>	149:156823d33999	3880	/* Check TI1 input conditioning related parameters */
<>	149:156823d33999	3881	assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
<>	149:156823d33999	3882	assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
<>	149:156823d33999	3883
<>	149:156823d33999	3884	TIM_TI1_ConfigInputStage(htim->Instance,
<>	149:156823d33999	3885	sClockSourceConfig->ClockPolarity,
<>	149:156823d33999	3886	sClockSourceConfig->ClockFilter);
<>	149:156823d33999	3887	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
<>	149:156823d33999	3888	}
<>	149:156823d33999	3889	break;
<>	149:156823d33999	3890	case TIM_CLOCKSOURCE_TI2:
<>	149:156823d33999	3891	{
<>	149:156823d33999	3892	/* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
<>	149:156823d33999	3893	assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
<>	149:156823d33999	3894
<>	149:156823d33999	3895	/* Check TI2 input conditioning related parameters */
<>	149:156823d33999	3896	assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
<>	149:156823d33999	3897	assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
<>	149:156823d33999	3898
<>	149:156823d33999	3899	TIM_TI2_ConfigInputStage(htim->Instance,
<>	149:156823d33999	3900	sClockSourceConfig->ClockPolarity,
<>	149:156823d33999	3901	sClockSourceConfig->ClockFilter);
<>	149:156823d33999	3902	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
<>	149:156823d33999	3903	}
<>	149:156823d33999	3904	break;
<>	149:156823d33999	3905	case TIM_CLOCKSOURCE_TI1ED:
<>	149:156823d33999	3906	{
<>	149:156823d33999	3907	/* Check whether or not the timer instance supports external clock mode 1 */
<>	149:156823d33999	3908	assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
<>	149:156823d33999	3909
<>	149:156823d33999	3910	/* Check TI1 input conditioning related parameters */
<>	149:156823d33999	3911	assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
<>	149:156823d33999	3912	assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
<>	149:156823d33999	3913
<>	149:156823d33999	3914	TIM_TI1_ConfigInputStage(htim->Instance,
<>	149:156823d33999	3915	sClockSourceConfig->ClockPolarity,
<>	149:156823d33999	3916	sClockSourceConfig->ClockFilter);
<>	149:156823d33999	3917	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
<>	149:156823d33999	3918	}
<>	149:156823d33999	3919	break;
<>	149:156823d33999	3920	case TIM_CLOCKSOURCE_ITR0:
<>	149:156823d33999	3921	{
<>	149:156823d33999	3922	/* Check whether or not the timer instance supports external clock mode 1 */
<>	149:156823d33999	3923	assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
<>	149:156823d33999	3924
<>	149:156823d33999	3925	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
<>	149:156823d33999	3926	}
<>	149:156823d33999	3927	break;
<>	149:156823d33999	3928	case TIM_CLOCKSOURCE_ITR1:
<>	149:156823d33999	3929	{
<>	149:156823d33999	3930	/* Check whether or not the timer instance supports external clock mode 1 */
<>	149:156823d33999	3931	assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
<>	149:156823d33999	3932
<>	149:156823d33999	3933	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
<>	149:156823d33999	3934	}
<>	149:156823d33999	3935	break;
<>	149:156823d33999	3936	case TIM_CLOCKSOURCE_ITR2:
<>	149:156823d33999	3937	{
<>	149:156823d33999	3938	/* Check whether or not the timer instance supports external clock mode 1 */
<>	149:156823d33999	3939	assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
<>	149:156823d33999	3940
<>	149:156823d33999	3941	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
<>	149:156823d33999	3942	}
<>	149:156823d33999	3943	break;
<>	149:156823d33999	3944	case TIM_CLOCKSOURCE_ITR3:
<>	149:156823d33999	3945	{
<>	149:156823d33999	3946	/* Check whether or not the timer instance supports external clock mode 1 */
<>	149:156823d33999	3947	assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
<>	149:156823d33999	3948
<>	149:156823d33999	3949	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
<>	149:156823d33999	3950	}
<>	149:156823d33999	3951	break;
<>	149:156823d33999	3952
<>	149:156823d33999	3953	default:
<>	149:156823d33999	3954	break;
<>	149:156823d33999	3955	}
<>	149:156823d33999	3956	htim->State = HAL_TIM_STATE_READY;
<>	149:156823d33999	3957
<>	149:156823d33999	3958	__HAL_UNLOCK(htim);
<>	149:156823d33999	3959
<>	149:156823d33999	3960	return HAL_OK;
<>	149:156823d33999	3961	}
<>	149:156823d33999	3962
<>	149:156823d33999	3963	/**
<>	149:156823d33999	3964	* @brief Selects the signal connected to the TI1 input: direct from CH1_input
<>	149:156823d33999	3965	* or a XOR combination between CH1_input, CH2_input & CH3_input
<>	149:156823d33999	3966	* @param htim: TIM handle.
<>	149:156823d33999	3967	* @param TI1_Selection: Indicate whether or not channel 1 is connected to the
<>	149:156823d33999	3968	* output of a XOR gate.
<>	149:156823d33999	3969	* This parameter can be one of the following values:
<>	149:156823d33999	3970	* @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
<>	149:156823d33999	3971	* @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
<>	149:156823d33999	3972	* pins are connected to the TI1 input (XOR combination)
<>	149:156823d33999	3973	* @retval HAL status
<>	149:156823d33999	3974	*/
<>	149:156823d33999	3975	HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
<>	149:156823d33999	3976	{
<>	149:156823d33999	3977	uint32_t tmpcr2 = 0;
<>	149:156823d33999	3978
<>	149:156823d33999	3979	/* Check the parameters */
<>	149:156823d33999	3980	assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
<>	149:156823d33999	3981	assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
<>	149:156823d33999	3982
<>	149:156823d33999	3983	/* Get the TIMx CR2 register value */
<>	149:156823d33999	3984	tmpcr2 = htim->Instance->CR2;
<>	149:156823d33999	3985
<>	149:156823d33999	3986	/* Reset the TI1 selection */
<>	149:156823d33999	3987	tmpcr2 &= ~TIM_CR2_TI1S;
<>	149:156823d33999	3988
<>	149:156823d33999	3989	/* Set the the TI1 selection */
<>	149:156823d33999	3990	tmpcr2 \|= TI1_Selection;
<>	149:156823d33999	3991
<>	149:156823d33999	3992	/* Write to TIMxCR2 */
<>	149:156823d33999	3993	htim->Instance->CR2 = tmpcr2;
<>	149:156823d33999	3994
<>	149:156823d33999	3995	return HAL_OK;
<>	149:156823d33999	3996	}
<>	149:156823d33999	3997
<>	149:156823d33999	3998	/**
<>	149:156823d33999	3999	* @brief Configures the TIM in Slave mode
<>	149:156823d33999	4000	* @param htim : TIM handle.
<>	149:156823d33999	4001	* @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
<>	149:156823d33999	4002	* contains the selected trigger (internal trigger input, filtered
<>	149:156823d33999	4003	* timer input or external trigger input) and the ) and the Slave
<>	149:156823d33999	4004	* mode (Disable, Reset, Gated, Trigger, External clock mode 1).
<>	149:156823d33999	4005	* @retval HAL status
<>	149:156823d33999	4006	*/
<>	149:156823d33999	4007	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig)
<>	149:156823d33999	4008	{
<>	149:156823d33999	4009	/* Check the parameters */
<>	149:156823d33999	4010	assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
<>	149:156823d33999	4011	assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
<>	149:156823d33999	4012	assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
<>	149:156823d33999	4013
<>	149:156823d33999	4014	__HAL_LOCK(htim);
<>	149:156823d33999	4015
<>	149:156823d33999	4016	htim->State = HAL_TIM_STATE_BUSY;
<>	149:156823d33999	4017
<>	149:156823d33999	4018	TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
<>	149:156823d33999	4019
<>	149:156823d33999	4020	/* Disable Trigger Interrupt */
<>	149:156823d33999	4021	__HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
<>	149:156823d33999	4022
<>	149:156823d33999	4023	/* Disable Trigger DMA request */
<>	149:156823d33999	4024	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
<>	149:156823d33999	4025
<>	149:156823d33999	4026	htim->State = HAL_TIM_STATE_READY;
<>	149:156823d33999	4027
<>	149:156823d33999	4028	__HAL_UNLOCK(htim);
<>	149:156823d33999	4029
<>	149:156823d33999	4030	return HAL_OK;
<>	149:156823d33999	4031	}
<>	149:156823d33999	4032
<>	149:156823d33999	4033	/**
<>	149:156823d33999	4034	* @brief Configures the TIM in Slave mode in interrupt mode
<>	149:156823d33999	4035	* @param htim: TIM handle.
<>	149:156823d33999	4036	* @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
<>	149:156823d33999	4037	* contains the selected trigger (internal trigger input, filtered
<>	149:156823d33999	4038	* timer input or external trigger input) and the ) and the Slave
<>	149:156823d33999	4039	* mode (Disable, Reset, Gated, Trigger, External clock mode 1).
<>	149:156823d33999	4040	* @retval HAL status
<>	149:156823d33999	4041	*/
<>	149:156823d33999	4042	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim,
<>	149:156823d33999	4043	TIM_SlaveConfigTypeDef * sSlaveConfig)
<>	149:156823d33999	4044	{
<>	149:156823d33999	4045	/* Check the parameters */
<>	149:156823d33999	4046	assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
<>	149:156823d33999	4047	assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
<>	149:156823d33999	4048	assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
<>	149:156823d33999	4049
<>	149:156823d33999	4050	__HAL_LOCK(htim);
<>	149:156823d33999	4051
<>	149:156823d33999	4052	htim->State = HAL_TIM_STATE_BUSY;
<>	149:156823d33999	4053
<>	149:156823d33999	4054	TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
<>	149:156823d33999	4055
<>	149:156823d33999	4056	/* Enable Trigger Interrupt */
<>	149:156823d33999	4057	__HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
<>	149:156823d33999	4058
<>	149:156823d33999	4059	/* Disable Trigger DMA request */
<>	149:156823d33999	4060	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
<>	149:156823d33999	4061
<>	149:156823d33999	4062	htim->State = HAL_TIM_STATE_READY;
<>	149:156823d33999	4063
<>	149:156823d33999	4064	__HAL_UNLOCK(htim);
<>	149:156823d33999	4065
<>	149:156823d33999	4066	return HAL_OK;
<>	149:156823d33999	4067	}
<>	149:156823d33999	4068
<>	149:156823d33999	4069	/**
<>	149:156823d33999	4070	* @brief Read the captured value from Capture Compare unit
<>	149:156823d33999	4071	* @param htim: TIM handle.
<>	149:156823d33999	4072	* @param Channel : TIM Channels to be enabled
<>	149:156823d33999	4073	* This parameter can be one of the following values:
<>	149:156823d33999	4074	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	149:156823d33999	4075	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	149:156823d33999	4076	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	149:156823d33999	4077	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	149:156823d33999	4078	* @retval Captured value
<>	149:156823d33999	4079	*/
<>	149:156823d33999	4080	uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	149:156823d33999	4081	{
<>	149:156823d33999	4082	uint32_t tmpreg = 0;
<>	149:156823d33999	4083
<>	149:156823d33999	4084	__HAL_LOCK(htim);
<>	149:156823d33999	4085
<>	149:156823d33999	4086	switch (Channel)
<>	149:156823d33999	4087	{
<>	149:156823d33999	4088	case TIM_CHANNEL_1:
<>	149:156823d33999	4089	{
<>	149:156823d33999	4090	/* Check the parameters */
<>	149:156823d33999	4091	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<>	149:156823d33999	4092
<>	149:156823d33999	4093	/* Return the capture 1 value */
<>	149:156823d33999	4094	tmpreg = htim->Instance->CCR1;
<>	149:156823d33999	4095
<>	149:156823d33999	4096	break;
<>	149:156823d33999	4097	}
<>	149:156823d33999	4098	case TIM_CHANNEL_2:
<>	149:156823d33999	4099	{
<>	149:156823d33999	4100	/* Check the parameters */
<>	149:156823d33999	4101	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	149:156823d33999	4102
<>	149:156823d33999	4103	/* Return the capture 2 value */
<>	149:156823d33999	4104	tmpreg = htim->Instance->CCR2;
<>	149:156823d33999	4105
<>	149:156823d33999	4106	break;
<>	149:156823d33999	4107	}
<>	149:156823d33999	4108
<>	149:156823d33999	4109	case TIM_CHANNEL_3:
<>	149:156823d33999	4110	{
<>	149:156823d33999	4111	/* Check the parameters */
<>	149:156823d33999	4112	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
<>	149:156823d33999	4113
<>	149:156823d33999	4114	/* Return the capture 3 value */
<>	149:156823d33999	4115	tmpreg = htim->Instance->CCR3;
<>	149:156823d33999	4116
<>	149:156823d33999	4117	break;
<>	149:156823d33999	4118	}
<>	149:156823d33999	4119
<>	149:156823d33999	4120	case TIM_CHANNEL_4:
<>	149:156823d33999	4121	{
<>	149:156823d33999	4122	/* Check the parameters */
<>	149:156823d33999	4123	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
<>	149:156823d33999	4124
<>	149:156823d33999	4125	/* Return the capture 4 value */
<>	149:156823d33999	4126	tmpreg = htim->Instance->CCR4;
<>	149:156823d33999	4127
<>	149:156823d33999	4128	break;
<>	149:156823d33999	4129	}
<>	149:156823d33999	4130
<>	149:156823d33999	4131	default:
<>	149:156823d33999	4132	break;
<>	149:156823d33999	4133	}
<>	149:156823d33999	4134
<>	149:156823d33999	4135	__HAL_UNLOCK(htim);
<>	149:156823d33999	4136	return tmpreg;
<>	149:156823d33999	4137	}
<>	149:156823d33999	4138
<>	149:156823d33999	4139	/**
<>	149:156823d33999	4140	* @}
<>	149:156823d33999	4141	*/
<>	149:156823d33999	4142
<>	149:156823d33999	4143	/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
<>	149:156823d33999	4144	* @brief TIM Callbacks functions
<>	149:156823d33999	4145	*
<>	149:156823d33999	4146	@verbatim
<>	149:156823d33999	4147	==============================================================================
<>	149:156823d33999	4148	##### TIM Callbacks functions #####
<>	149:156823d33999	4149	==============================================================================
<>	149:156823d33999	4150	[..]
<>	149:156823d33999	4151	This section provides TIM callback functions:
<>	149:156823d33999	4152	(+) Timer Period elapsed callback
<>	149:156823d33999	4153	(+) Timer Output Compare callback
<>	149:156823d33999	4154	(+) Timer Input capture callback
<>	149:156823d33999	4155	(+) Timer Trigger callback
<>	149:156823d33999	4156	(+) Timer Error callback
<>	149:156823d33999	4157
<>	149:156823d33999	4158	@endverbatim
<>	149:156823d33999	4159	* @{
<>	149:156823d33999	4160	*/
<>	149:156823d33999	4161
<>	149:156823d33999	4162	/**
<>	149:156823d33999	4163	* @brief Period elapsed callback in non blocking mode
<>	149:156823d33999	4164	* @param htim : TIM handle
<>	149:156823d33999	4165	* @retval None
<>	149:156823d33999	4166	*/
<>	149:156823d33999	4167	__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
<>	149:156823d33999	4168	{
<>	149:156823d33999	4169	/* Prevent unused argument(s) compilation warning */
<>	149:156823d33999	4170	UNUSED(htim);
<>	149:156823d33999	4171
<>	149:156823d33999	4172	/* NOTE : This function Should not be modified, when the callback is needed,
<>	149:156823d33999	4173	the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
<>	149:156823d33999	4174	*/
<>	149:156823d33999	4175
<>	149:156823d33999	4176	}
<>	149:156823d33999	4177	/**
<>	149:156823d33999	4178	* @brief Output Compare callback in non blocking mode
<>	149:156823d33999	4179	* @param htim : TIM OC handle
<>	149:156823d33999	4180	* @retval None
<>	149:156823d33999	4181	*/
<>	149:156823d33999	4182	__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
<>	149:156823d33999	4183	{
<>	149:156823d33999	4184	/* Prevent unused argument(s) compilation warning */
<>	149:156823d33999	4185	UNUSED(htim);
<>	149:156823d33999	4186
<>	149:156823d33999	4187	/* NOTE : This function Should not be modified, when the callback is needed,
<>	149:156823d33999	4188	the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
<>	149:156823d33999	4189	*/
<>	149:156823d33999	4190	}
<>	149:156823d33999	4191	/**
<>	149:156823d33999	4192	* @brief Input Capture callback in non blocking mode
<>	149:156823d33999	4193	* @param htim : TIM IC handle
<>	149:156823d33999	4194	* @retval None
<>	149:156823d33999	4195	*/
<>	149:156823d33999	4196	__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
<>	149:156823d33999	4197	{
<>	149:156823d33999	4198	/* Prevent unused argument(s) compilation warning */
<>	149:156823d33999	4199	UNUSED(htim);
<>	149:156823d33999	4200
<>	149:156823d33999	4201	/* NOTE : This function Should not be modified, when the callback is needed,
<>	149:156823d33999	4202	the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
<>	149:156823d33999	4203	*/
<>	149:156823d33999	4204	}
<>	149:156823d33999	4205
<>	149:156823d33999	4206	/**
<>	149:156823d33999	4207	* @brief PWM Pulse finished callback in non blocking mode
<>	149:156823d33999	4208	* @param htim : TIM handle
<>	149:156823d33999	4209	* @retval None
<>	149:156823d33999	4210	*/
<>	149:156823d33999	4211	__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
<>	149:156823d33999	4212	{
<>	149:156823d33999	4213	/* Prevent unused argument(s) compilation warning */
<>	149:156823d33999	4214	UNUSED(htim);
<>	149:156823d33999	4215
<>	149:156823d33999	4216	/* NOTE : This function Should not be modified, when the callback is needed,
<>	149:156823d33999	4217	the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
<>	149:156823d33999	4218	*/
<>	149:156823d33999	4219	}
<>	149:156823d33999	4220
<>	149:156823d33999	4221	/**
<>	149:156823d33999	4222	* @brief Hall Trigger detection callback in non blocking mode
<>	149:156823d33999	4223	* @param htim : TIM handle
<>	149:156823d33999	4224	* @retval None
<>	149:156823d33999	4225	*/
<>	149:156823d33999	4226	__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
<>	149:156823d33999	4227	{
<>	149:156823d33999	4228	/* Prevent unused argument(s) compilation warning */
<>	149:156823d33999	4229	UNUSED(htim);
<>	149:156823d33999	4230
<>	149:156823d33999	4231	/* NOTE : This function Should not be modified, when the callback is needed,
<>	149:156823d33999	4232	the HAL_TIM_TriggerCallback could be implemented in the user file
<>	149:156823d33999	4233	*/
<>	149:156823d33999	4234	}
<>	149:156823d33999	4235
<>	149:156823d33999	4236	/**
<>	149:156823d33999	4237	* @brief Timer error callback in non blocking mode
<>	149:156823d33999	4238	* @param htim : TIM handle
<>	149:156823d33999	4239	* @retval None
<>	149:156823d33999	4240	*/
<>	149:156823d33999	4241	__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
<>	149:156823d33999	4242	{
<>	149:156823d33999	4243	/* Prevent unused argument(s) compilation warning */
<>	149:156823d33999	4244	UNUSED(htim);
<>	149:156823d33999	4245
<>	149:156823d33999	4246	/* NOTE : This function Should not be modified, when the callback is needed,
<>	149:156823d33999	4247	the HAL_TIM_ErrorCallback could be implemented in the user file
<>	149:156823d33999	4248	*/
<>	149:156823d33999	4249	}
<>	149:156823d33999	4250
<>	149:156823d33999	4251	/**
<>	149:156823d33999	4252	* @}
<>	149:156823d33999	4253	*/
<>	149:156823d33999	4254
<>	149:156823d33999	4255	/** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
<>	149:156823d33999	4256	* @brief Peripheral State functions
<>	149:156823d33999	4257	*
<>	149:156823d33999	4258	@verbatim
<>	149:156823d33999	4259	==============================================================================
<>	149:156823d33999	4260	##### Peripheral State functions #####
<>	149:156823d33999	4261	==============================================================================
<>	149:156823d33999	4262	[..]
<>	149:156823d33999	4263	This subsection permit to get in run-time the status of the peripheral
<>	149:156823d33999	4264	and the data flow.
<>	149:156823d33999	4265
<>	149:156823d33999	4266	@endverbatim
<>	149:156823d33999	4267	* @{
<>	149:156823d33999	4268	*/
<>	149:156823d33999	4269
<>	149:156823d33999	4270	/**
<>	149:156823d33999	4271	* @brief Return the TIM Base state
<>	149:156823d33999	4272	* @param htim: TIM Base handle
<>	149:156823d33999	4273	* @retval HAL state
<>	149:156823d33999	4274	*/
<>	149:156823d33999	4275	HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
<>	149:156823d33999	4276	{
<>	149:156823d33999	4277	return htim->State;
<>	149:156823d33999	4278	}
<>	149:156823d33999	4279
<>	149:156823d33999	4280	/**
<>	149:156823d33999	4281	* @brief Return the TIM OC state
<>	149:156823d33999	4282	* @param htim: TIM Ouput Compare handle
<>	149:156823d33999	4283	* @retval HAL state
<>	149:156823d33999	4284	*/
<>	149:156823d33999	4285	HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
<>	149:156823d33999	4286	{
<>	149:156823d33999	4287	return htim->State;
<>	149:156823d33999	4288	}
<>	149:156823d33999	4289
<>	149:156823d33999	4290	/**
<>	149:156823d33999	4291	* @brief Return the TIM PWM state
<>	149:156823d33999	4292	* @param htim: TIM handle
<>	149:156823d33999	4293	* @retval HAL state
<>	149:156823d33999	4294	*/
<>	149:156823d33999	4295	HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
<>	149:156823d33999	4296	{
<>	149:156823d33999	4297	return htim->State;
<>	149:156823d33999	4298	}
<>	149:156823d33999	4299
<>	149:156823d33999	4300	/**
<>	149:156823d33999	4301	* @brief Return the TIM Input Capture state
<>	149:156823d33999	4302	* @param htim: TIM IC handle
<>	149:156823d33999	4303	* @retval HAL state
<>	149:156823d33999	4304	*/
<>	149:156823d33999	4305	HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
<>	149:156823d33999	4306	{
<>	149:156823d33999	4307	return htim->State;
<>	149:156823d33999	4308	}
<>	149:156823d33999	4309
<>	149:156823d33999	4310	/**
<>	149:156823d33999	4311	* @brief Return the TIM One Pulse Mode state
<>	149:156823d33999	4312	* @param htim: TIM OPM handle
<>	149:156823d33999	4313	* @retval HAL state
<>	149:156823d33999	4314	*/
<>	149:156823d33999	4315	HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
<>	149:156823d33999	4316	{
<>	149:156823d33999	4317	return htim->State;
<>	149:156823d33999	4318	}
<>	149:156823d33999	4319
<>	149:156823d33999	4320	/**
<>	149:156823d33999	4321	* @brief Return the TIM Encoder Mode state
<>	149:156823d33999	4322	* @param htim: TIM Encoder handle
<>	149:156823d33999	4323	* @retval HAL state
<>	149:156823d33999	4324	*/
<>	149:156823d33999	4325	HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
<>	149:156823d33999	4326	{
<>	149:156823d33999	4327	return htim->State;
<>	149:156823d33999	4328	}
<>	149:156823d33999	4329
<>	149:156823d33999	4330	/**
<>	149:156823d33999	4331	* @brief TIM DMA error callback
<>	149:156823d33999	4332	* @param hdma : pointer to DMA handle.
<>	149:156823d33999	4333	* @retval None
<>	149:156823d33999	4334	*/
<>	149:156823d33999	4335	void TIM_DMAError(DMA_HandleTypeDef *hdma)
<>	149:156823d33999	4336	{
<>	149:156823d33999	4337	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	149:156823d33999	4338
<>	149:156823d33999	4339	htim->State= HAL_TIM_STATE_READY;
<>	149:156823d33999	4340
<>	149:156823d33999	4341	HAL_TIM_ErrorCallback(htim);
<>	149:156823d33999	4342	}
<>	149:156823d33999	4343
<>	149:156823d33999	4344	/**
<>	149:156823d33999	4345	* @brief TIM DMA Delay Pulse complete callback.
<>	149:156823d33999	4346	* @param hdma : pointer to DMA handle.
<>	149:156823d33999	4347	* @retval None
<>	149:156823d33999	4348	*/
<>	149:156823d33999	4349	void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
<>	149:156823d33999	4350	{
<>	149:156823d33999	4351	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	149:156823d33999	4352
<>	149:156823d33999	4353	htim->State= HAL_TIM_STATE_READY;
<>	149:156823d33999	4354
<>	149:156823d33999	4355	if (hdma == htim->hdma[TIM_DMA_ID_CC1])
<>	149:156823d33999	4356	{
<>	149:156823d33999	4357	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
<>	149:156823d33999	4358	}
<>	149:156823d33999	4359	else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
<>	149:156823d33999	4360	{
<>	149:156823d33999	4361	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
<>	149:156823d33999	4362	}
<>	149:156823d33999	4363	else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
<>	149:156823d33999	4364	{
<>	149:156823d33999	4365	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
<>	149:156823d33999	4366	}
<>	149:156823d33999	4367	else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
<>	149:156823d33999	4368	{
<>	149:156823d33999	4369	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
<>	149:156823d33999	4370	}
<>	149:156823d33999	4371
<>	149:156823d33999	4372	HAL_TIM_PWM_PulseFinishedCallback(htim);
<>	149:156823d33999	4373
<>	149:156823d33999	4374	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
<>	149:156823d33999	4375	}
<>	149:156823d33999	4376
<>	149:156823d33999	4377	/**
<>	149:156823d33999	4378	* @brief TIM DMA Capture complete callback.
<>	149:156823d33999	4379	* @param hdma : pointer to DMA handle.
<>	149:156823d33999	4380	* @retval None
<>	149:156823d33999	4381	*/
<>	149:156823d33999	4382	void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
<>	149:156823d33999	4383	{
<>	149:156823d33999	4384	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	149:156823d33999	4385
<>	149:156823d33999	4386	htim->State= HAL_TIM_STATE_READY;
<>	149:156823d33999	4387
<>	149:156823d33999	4388	if (hdma == htim->hdma[TIM_DMA_ID_CC1])
<>	149:156823d33999	4389	{
<>	149:156823d33999	4390	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
<>	149:156823d33999	4391	}
<>	149:156823d33999	4392	else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
<>	149:156823d33999	4393	{
<>	149:156823d33999	4394	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
<>	149:156823d33999	4395	}
<>	149:156823d33999	4396	else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
<>	149:156823d33999	4397	{
<>	149:156823d33999	4398	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
<>	149:156823d33999	4399	}
<>	149:156823d33999	4400	else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
<>	149:156823d33999	4401	{
<>	149:156823d33999	4402	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
<>	149:156823d33999	4403	}
<>	149:156823d33999	4404
<>	149:156823d33999	4405	HAL_TIM_IC_CaptureCallback(htim);
<>	149:156823d33999	4406
<>	149:156823d33999	4407	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
<>	149:156823d33999	4408	}
<>	149:156823d33999	4409
<>	149:156823d33999	4410	/**
<>	149:156823d33999	4411	* @}
<>	149:156823d33999	4412	*/
<>	149:156823d33999	4413
<>	149:156823d33999	4414	/**
<>	149:156823d33999	4415	* @}
<>	149:156823d33999	4416	*/
<>	149:156823d33999	4417
<>	149:156823d33999	4418
<>	149:156823d33999	4419	/** @addtogroup TIM_Private_Functions
<>	149:156823d33999	4420	* @{
<>	149:156823d33999	4421	*/
<>	149:156823d33999	4422
<>	149:156823d33999	4423	/**
<>	149:156823d33999	4424	* @brief TIM DMA Period Elapse complete callback.
<>	149:156823d33999	4425	* @param hdma : pointer to DMA handle.
<>	149:156823d33999	4426	* @retval None
<>	149:156823d33999	4427	*/
<>	149:156823d33999	4428	static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
<>	149:156823d33999	4429	{
<>	149:156823d33999	4430	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	149:156823d33999	4431
<>	149:156823d33999	4432	htim->State= HAL_TIM_STATE_READY;
<>	149:156823d33999	4433
<>	149:156823d33999	4434	HAL_TIM_PeriodElapsedCallback(htim);
<>	149:156823d33999	4435	}
<>	149:156823d33999	4436
<>	149:156823d33999	4437	/**
<>	149:156823d33999	4438	* @brief TIM DMA Trigger callback.
<>	149:156823d33999	4439	* @param hdma : pointer to DMA handle.
<>	149:156823d33999	4440	* @retval None
<>	149:156823d33999	4441	*/
<>	149:156823d33999	4442	static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
<>	149:156823d33999	4443	{
<>	149:156823d33999	4444	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	149:156823d33999	4445
<>	149:156823d33999	4446	htim->State= HAL_TIM_STATE_READY;
<>	149:156823d33999	4447
<>	149:156823d33999	4448	HAL_TIM_TriggerCallback(htim);
<>	149:156823d33999	4449	}
<>	149:156823d33999	4450
<>	149:156823d33999	4451	/**
<>	149:156823d33999	4452	* @brief Time Base configuration
<>	149:156823d33999	4453	* @param TIMx: TIM periheral
<>	149:156823d33999	4454	* @param Structure: TIM Base configuration structure
<>	149:156823d33999	4455	* @retval None
<>	149:156823d33999	4456	*/
<>	149:156823d33999	4457	static void TIM_Base_SetConfig(TIM_TypeDef TIMx, TIM_Base_InitTypeDef Structure)
<>	149:156823d33999	4458	{
<>	149:156823d33999	4459	uint32_t tmpcr1 = 0;
<>	149:156823d33999	4460	tmpcr1 = TIMx->CR1;
<>	149:156823d33999	4461
<>	149:156823d33999	4462	/* Set TIM Time Base Unit parameters ---------------------------------------*/
<>	149:156823d33999	4463	if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
<>	149:156823d33999	4464	{
<>	149:156823d33999	4465	/* Select the Counter Mode */
<>	149:156823d33999	4466	tmpcr1 &= ~(TIM_CR1_DIR \| TIM_CR1_CMS);
<>	149:156823d33999	4467	tmpcr1 \|= Structure->CounterMode;
<>	149:156823d33999	4468	}
<>	149:156823d33999	4469
<>	149:156823d33999	4470	if(IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
<>	149:156823d33999	4471	{
<>	149:156823d33999	4472	/* Set the clock division */
<>	149:156823d33999	4473	tmpcr1 &= ~TIM_CR1_CKD;
<>	149:156823d33999	4474	tmpcr1 \|= (uint32_t)Structure->ClockDivision;
<>	149:156823d33999	4475	}
<>	149:156823d33999	4476
<>	149:156823d33999	4477	TIMx->CR1 = tmpcr1;
<>	149:156823d33999	4478
<>	149:156823d33999	4479	/* Set the Autoreload value */
<>	149:156823d33999	4480	TIMx->ARR = (uint32_t)Structure->Period ;
<>	149:156823d33999	4481
<>	149:156823d33999	4482	/* Set the Prescaler value */
<>	149:156823d33999	4483	TIMx->PSC = (uint32_t)Structure->Prescaler;
<>	149:156823d33999	4484
<>	149:156823d33999	4485	/* Generate an update event to reload the Prescaler */
<>	149:156823d33999	4486	TIMx->EGR = TIM_EGR_UG;
<>	149:156823d33999	4487	}
<>	149:156823d33999	4488
<>	149:156823d33999	4489	/**
<>	149:156823d33999	4490	* @brief Time Ouput Compare 1 configuration
<>	149:156823d33999	4491	* @param TIMx to select the TIM peripheral
<>	149:156823d33999	4492	* @param OC_Config: The ouput configuration structure
<>	149:156823d33999	4493	* @retval None
<>	149:156823d33999	4494	*/
<>	149:156823d33999	4495	static void TIM_OC1_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
<>	149:156823d33999	4496	{
<>	149:156823d33999	4497	uint32_t tmpccmrx = 0;
<>	149:156823d33999	4498	uint32_t tmpccer = 0;
<>	149:156823d33999	4499	uint32_t tmpcr2 = 0;
<>	149:156823d33999	4500
<>	149:156823d33999	4501	/* Disable the Channel 1: Reset the CC1E Bit */
<>	149:156823d33999	4502	TIMx->CCER &= ~TIM_CCER_CC1E;
<>	149:156823d33999	4503
<>	149:156823d33999	4504	/* Get the TIMx CCER register value */
<>	149:156823d33999	4505	tmpccer = TIMx->CCER;
<>	149:156823d33999	4506	/* Get the TIMx CR2 register value */
<>	149:156823d33999	4507	tmpcr2 = TIMx->CR2;
<>	149:156823d33999	4508
<>	149:156823d33999	4509	/* Get the TIMx CCMR1 register value */
<>	149:156823d33999	4510	tmpccmrx = TIMx->CCMR1;
<>	149:156823d33999	4511
<>	149:156823d33999	4512	/* Reset the Output Compare Mode Bits */
<>	149:156823d33999	4513	tmpccmrx &= ~TIM_CCMR1_OC1M;
<>	149:156823d33999	4514	tmpccmrx &= ~TIM_CCMR1_CC1S;
<>	149:156823d33999	4515	/* Select the Output Compare Mode */
<>	149:156823d33999	4516	tmpccmrx \|= OC_Config->OCMode;
<>	149:156823d33999	4517
<>	149:156823d33999	4518	/* Reset the Output Polarity level */
<>	149:156823d33999	4519	tmpccer &= ~TIM_CCER_CC1P;
<>	149:156823d33999	4520	/* Set the Output Compare Polarity */
<>	149:156823d33999	4521	tmpccer \|= OC_Config->OCPolarity;
<>	149:156823d33999	4522
<>	149:156823d33999	4523	/* Write to TIMx CR2 */
<>	149:156823d33999	4524	TIMx->CR2 = tmpcr2;
<>	149:156823d33999	4525
<>	149:156823d33999	4526	/* Write to TIMx CCMR1 */
<>	149:156823d33999	4527	TIMx->CCMR1 = tmpccmrx;
<>	149:156823d33999	4528
<>	149:156823d33999	4529	/* Set the Capture Compare Register value */
<>	149:156823d33999	4530	TIMx->CCR1 = OC_Config->Pulse;
<>	149:156823d33999	4531
<>	149:156823d33999	4532	/* Write to TIMx CCER */
<>	149:156823d33999	4533	TIMx->CCER = tmpccer;
<>	149:156823d33999	4534	}
<>	149:156823d33999	4535
<>	149:156823d33999	4536	/**
<>	149:156823d33999	4537	* @brief Time Ouput Compare 2 configuration
<>	149:156823d33999	4538	* @param TIMx to select the TIM peripheral
<>	149:156823d33999	4539	* @param OC_Config: The ouput configuration structure
<>	149:156823d33999	4540	* @retval None
<>	149:156823d33999	4541	*/
<>	149:156823d33999	4542	static void TIM_OC2_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
<>	149:156823d33999	4543	{
<>	149:156823d33999	4544	uint32_t tmpccmrx = 0;
<>	149:156823d33999	4545	uint32_t tmpccer = 0;
<>	149:156823d33999	4546	uint32_t tmpcr2 = 0;
<>	149:156823d33999	4547
<>	149:156823d33999	4548	/* Disable the Channel 2: Reset the CC2E Bit */
<>	149:156823d33999	4549	TIMx->CCER &= ~TIM_CCER_CC2E;
<>	149:156823d33999	4550
<>	149:156823d33999	4551	/* Get the TIMx CCER register value */
<>	149:156823d33999	4552	tmpccer = TIMx->CCER;
<>	149:156823d33999	4553	/* Get the TIMx CR2 register value */
<>	149:156823d33999	4554	tmpcr2 = TIMx->CR2;
<>	149:156823d33999	4555
<>	149:156823d33999	4556	/* Get the TIMx CCMR1 register value */
<>	149:156823d33999	4557	tmpccmrx = TIMx->CCMR1;
<>	149:156823d33999	4558
<>	149:156823d33999	4559	/* Reset the Output Compare mode and Capture/Compare selection Bits */
<>	149:156823d33999	4560	tmpccmrx &= ~TIM_CCMR1_OC2M;
<>	149:156823d33999	4561	tmpccmrx &= ~TIM_CCMR1_CC2S;
<>	149:156823d33999	4562
<>	149:156823d33999	4563	/* Select the Output Compare Mode */
<>	149:156823d33999	4564	tmpccmrx \|= (OC_Config->OCMode << 8);
<>	149:156823d33999	4565
<>	149:156823d33999	4566	/* Reset the Output Polarity level */
<>	149:156823d33999	4567	tmpccer &= ~TIM_CCER_CC2P;
<>	149:156823d33999	4568	/* Set the Output Compare Polarity */
<>	149:156823d33999	4569	tmpccer \|= (OC_Config->OCPolarity << 4);
<>	149:156823d33999	4570
<>	149:156823d33999	4571	/* Write to TIMx CR2 */
<>	149:156823d33999	4572	TIMx->CR2 = tmpcr2;
<>	149:156823d33999	4573
<>	149:156823d33999	4574	/* Write to TIMx CCMR1 */
<>	149:156823d33999	4575	TIMx->CCMR1 = tmpccmrx;
<>	149:156823d33999	4576
<>	149:156823d33999	4577	/* Set the Capture Compare Register value */
<>	149:156823d33999	4578	TIMx->CCR2 = OC_Config->Pulse;
<>	149:156823d33999	4579
<>	149:156823d33999	4580	/* Write to TIMx CCER */
<>	149:156823d33999	4581	TIMx->CCER = tmpccer;
<>	149:156823d33999	4582	}
<>	149:156823d33999	4583
<>	149:156823d33999	4584	/**
<>	149:156823d33999	4585	* @brief Time Ouput Compare 3 configuration
<>	149:156823d33999	4586	* @param TIMx to select the TIM peripheral
<>	149:156823d33999	4587	* @param OC_Config: The ouput configuration structure
<>	149:156823d33999	4588	* @retval None
<>	149:156823d33999	4589	*/
<>	149:156823d33999	4590	static void TIM_OC3_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
<>	149:156823d33999	4591	{
<>	149:156823d33999	4592	uint32_t tmpccmrx = 0;
<>	149:156823d33999	4593	uint32_t tmpccer = 0;
<>	149:156823d33999	4594	uint32_t tmpcr2 = 0;
<>	149:156823d33999	4595
<>	149:156823d33999	4596	/* Disable the Channel 3: Reset the CC2E Bit */
<>	149:156823d33999	4597	TIMx->CCER &= ~TIM_CCER_CC3E;
<>	149:156823d33999	4598
<>	149:156823d33999	4599	/* Get the TIMx CCER register value */
<>	149:156823d33999	4600	tmpccer = TIMx->CCER;
<>	149:156823d33999	4601	/* Get the TIMx CR2 register value */
<>	149:156823d33999	4602	tmpcr2 = TIMx->CR2;
<>	149:156823d33999	4603
<>	149:156823d33999	4604	/* Get the TIMx CCMR2 register value */
<>	149:156823d33999	4605	tmpccmrx = TIMx->CCMR2;
<>	149:156823d33999	4606
<>	149:156823d33999	4607	/* Reset the Output Compare mode and Capture/Compare selection Bits */
<>	149:156823d33999	4608	tmpccmrx &= ~TIM_CCMR2_OC3M;
<>	149:156823d33999	4609	tmpccmrx &= ~TIM_CCMR2_CC3S;
<>	149:156823d33999	4610	/* Select the Output Compare Mode */
<>	149:156823d33999	4611	tmpccmrx \|= OC_Config->OCMode;
<>	149:156823d33999	4612
<>	149:156823d33999	4613	/* Reset the Output Polarity level */
<>	149:156823d33999	4614	tmpccer &= ~TIM_CCER_CC3P;
<>	149:156823d33999	4615	/* Set the Output Compare Polarity */
<>	149:156823d33999	4616	tmpccer \|= (OC_Config->OCPolarity << 8);
<>	149:156823d33999	4617
<>	149:156823d33999	4618	/* Write to TIMx CR2 */
<>	149:156823d33999	4619	TIMx->CR2 = tmpcr2;
<>	149:156823d33999	4620
<>	149:156823d33999	4621	/* Write to TIMx CCMR2 */
<>	149:156823d33999	4622	TIMx->CCMR2 = tmpccmrx;
<>	149:156823d33999	4623
<>	149:156823d33999	4624	/* Set the Capture Compare Register value */
<>	149:156823d33999	4625	TIMx->CCR3 = OC_Config->Pulse;
<>	149:156823d33999	4626
<>	149:156823d33999	4627	/* Write to TIMx CCER */
<>	149:156823d33999	4628	TIMx->CCER = tmpccer;
<>	149:156823d33999	4629	}
<>	149:156823d33999	4630
<>	149:156823d33999	4631	/**
<>	149:156823d33999	4632	* @brief Time Ouput Compare 4 configuration
<>	149:156823d33999	4633	* @param TIMx to select the TIM peripheral
<>	149:156823d33999	4634	* @param OC_Config: The ouput configuration structure
<>	149:156823d33999	4635	* @retval None
<>	149:156823d33999	4636	*/
<>	149:156823d33999	4637	static void TIM_OC4_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
<>	149:156823d33999	4638	{
<>	149:156823d33999	4639	uint32_t tmpccmrx = 0;
<>	149:156823d33999	4640	uint32_t tmpccer = 0;
<>	149:156823d33999	4641	uint32_t tmpcr2 = 0;
<>	149:156823d33999	4642
<>	149:156823d33999	4643	/* Disable the Channel 4: Reset the CC4E Bit */
<>	149:156823d33999	4644	TIMx->CCER &= ~TIM_CCER_CC4E;
<>	149:156823d33999	4645
<>	149:156823d33999	4646	/* Get the TIMx CCER register value */
<>	149:156823d33999	4647	tmpccer = TIMx->CCER;
<>	149:156823d33999	4648	/* Get the TIMx CR2 register value */
<>	149:156823d33999	4649	tmpcr2 = TIMx->CR2;
<>	149:156823d33999	4650
<>	149:156823d33999	4651	/* Get the TIMx CCMR2 register value */
<>	149:156823d33999	4652	tmpccmrx = TIMx->CCMR2;
<>	149:156823d33999	4653
<>	149:156823d33999	4654	/* Reset the Output Compare mode and Capture/Compare selection Bits */
<>	149:156823d33999	4655	tmpccmrx &= ~TIM_CCMR2_OC4M;
<>	149:156823d33999	4656	tmpccmrx &= ~TIM_CCMR2_CC4S;
<>	149:156823d33999	4657
<>	149:156823d33999	4658	/* Select the Output Compare Mode */
<>	149:156823d33999	4659	tmpccmrx \|= (OC_Config->OCMode << 8);
<>	149:156823d33999	4660
<>	149:156823d33999	4661	/* Reset the Output Polarity level */
<>	149:156823d33999	4662	tmpccer &= ~TIM_CCER_CC4P;
<>	149:156823d33999	4663	/* Set the Output Compare Polarity */
<>	149:156823d33999	4664	tmpccer \|= (OC_Config->OCPolarity << 12);
<>	149:156823d33999	4665
<>	149:156823d33999	4666	/* Write to TIMx CR2 */
<>	149:156823d33999	4667	TIMx->CR2 = tmpcr2;
<>	149:156823d33999	4668
<>	149:156823d33999	4669	/* Write to TIMx CCMR2 */
<>	149:156823d33999	4670	TIMx->CCMR2 = tmpccmrx;
<>	149:156823d33999	4671
<>	149:156823d33999	4672	/* Set the Capture Compare Register value */
<>	149:156823d33999	4673	TIMx->CCR4 = OC_Config->Pulse;
<>	149:156823d33999	4674
<>	149:156823d33999	4675	/* Write to TIMx CCER */
<>	149:156823d33999	4676	TIMx->CCER = tmpccer;
<>	149:156823d33999	4677	}
<>	149:156823d33999	4678
<>	149:156823d33999	4679
<>	149:156823d33999	4680	/**
<>	149:156823d33999	4681	* @brief Time Slave configuration
<>	149:156823d33999	4682	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	149:156823d33999	4683	* the configuration information for TIM module.
<>	149:156823d33999	4684	* @param sSlaveConfig: The slave configuration structure
<>	149:156823d33999	4685	* @retval None
<>	149:156823d33999	4686	*/
<>	149:156823d33999	4687	static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
<>	149:156823d33999	4688	TIM_SlaveConfigTypeDef * sSlaveConfig)
<>	149:156823d33999	4689	{
<>	149:156823d33999	4690	uint32_t tmpsmcr = 0;
<>	149:156823d33999	4691	uint32_t tmpccmr1 = 0;
<>	149:156823d33999	4692	uint32_t tmpccer = 0;
<>	149:156823d33999	4693
<>	149:156823d33999	4694	/* Get the TIMx SMCR register value */
<>	149:156823d33999	4695	tmpsmcr = htim->Instance->SMCR;
<>	149:156823d33999	4696
<>	149:156823d33999	4697	/* Reset the Trigger Selection Bits */
<>	149:156823d33999	4698	tmpsmcr &= ~TIM_SMCR_TS;
<>	149:156823d33999	4699	/* Set the Input Trigger source */
<>	149:156823d33999	4700	tmpsmcr \|= sSlaveConfig->InputTrigger;
<>	149:156823d33999	4701
<>	149:156823d33999	4702	/* Reset the slave mode Bits */
<>	149:156823d33999	4703	tmpsmcr &= ~TIM_SMCR_SMS;
<>	149:156823d33999	4704	/* Set the slave mode */
<>	149:156823d33999	4705	tmpsmcr \|= sSlaveConfig->SlaveMode;
<>	149:156823d33999	4706
<>	149:156823d33999	4707	/* Write to TIMx SMCR */
<>	149:156823d33999	4708	htim->Instance->SMCR = tmpsmcr;
<>	149:156823d33999	4709
<>	149:156823d33999	4710	/* Configure the trigger prescaler, filter, and polarity */
<>	149:156823d33999	4711	switch (sSlaveConfig->InputTrigger)
<>	149:156823d33999	4712	{
<>	149:156823d33999	4713	case TIM_TS_ETRF:
<>	149:156823d33999	4714	{
<>	149:156823d33999	4715	/* Check the parameters */
<>	149:156823d33999	4716	assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
<>	149:156823d33999	4717	assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
<>	149:156823d33999	4718	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
<>	149:156823d33999	4719	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
<>	149:156823d33999	4720	/* Configure the ETR Trigger source */
<>	149:156823d33999	4721	TIM_ETR_SetConfig(htim->Instance,
<>	149:156823d33999	4722	sSlaveConfig->TriggerPrescaler,
<>	149:156823d33999	4723	sSlaveConfig->TriggerPolarity,
<>	149:156823d33999	4724	sSlaveConfig->TriggerFilter);
<>	149:156823d33999	4725	}
<>	149:156823d33999	4726	break;
<>	149:156823d33999	4727
<>	149:156823d33999	4728	case TIM_TS_TI1F_ED:
<>	149:156823d33999	4729	{
<>	149:156823d33999	4730	/* Check the parameters */
<>	149:156823d33999	4731	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<>	149:156823d33999	4732	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
<>	149:156823d33999	4733
<>	149:156823d33999	4734	/* Disable the Channel 1: Reset the CC1E Bit */
<>	149:156823d33999	4735	tmpccer = htim->Instance->CCER;
<>	149:156823d33999	4736	htim->Instance->CCER &= ~TIM_CCER_CC1E;
<>	149:156823d33999	4737	tmpccmr1 = htim->Instance->CCMR1;
<>	149:156823d33999	4738
<>	149:156823d33999	4739	/* Set the filter */
<>	149:156823d33999	4740	tmpccmr1 &= ~TIM_CCMR1_IC1F;
<>	149:156823d33999	4741	tmpccmr1 \|= ((sSlaveConfig->TriggerFilter) << 4);
<>	149:156823d33999	4742
<>	149:156823d33999	4743	/* Write to TIMx CCMR1 and CCER registers */
<>	149:156823d33999	4744	htim->Instance->CCMR1 = tmpccmr1;
<>	149:156823d33999	4745	htim->Instance->CCER = tmpccer;
<>	149:156823d33999	4746
<>	149:156823d33999	4747	}
<>	149:156823d33999	4748	break;
<>	149:156823d33999	4749
<>	149:156823d33999	4750	case TIM_TS_TI1FP1:
<>	149:156823d33999	4751	{
<>	149:156823d33999	4752	/* Check the parameters */
<>	149:156823d33999	4753	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<>	149:156823d33999	4754	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
<>	149:156823d33999	4755	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
<>	149:156823d33999	4756
<>	149:156823d33999	4757	/* Configure TI1 Filter and Polarity */
<>	149:156823d33999	4758	TIM_TI1_ConfigInputStage(htim->Instance,
<>	149:156823d33999	4759	sSlaveConfig->TriggerPolarity,
<>	149:156823d33999	4760	sSlaveConfig->TriggerFilter);
<>	149:156823d33999	4761	}
<>	149:156823d33999	4762	break;
<>	149:156823d33999	4763
<>	149:156823d33999	4764	case TIM_TS_TI2FP2:
<>	149:156823d33999	4765	{
<>	149:156823d33999	4766	/* Check the parameters */
<>	149:156823d33999	4767	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	149:156823d33999	4768	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
<>	149:156823d33999	4769	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
<>	149:156823d33999	4770
<>	149:156823d33999	4771	/* Configure TI2 Filter and Polarity */
<>	149:156823d33999	4772	TIM_TI2_ConfigInputStage(htim->Instance,
<>	149:156823d33999	4773	sSlaveConfig->TriggerPolarity,
<>	149:156823d33999	4774	sSlaveConfig->TriggerFilter);
<>	149:156823d33999	4775	}
<>	149:156823d33999	4776	break;
<>	149:156823d33999	4777
<>	149:156823d33999	4778	case TIM_TS_ITR0:
<>	149:156823d33999	4779	{
<>	149:156823d33999	4780	/* Check the parameter */
<>	149:156823d33999	4781	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	149:156823d33999	4782	}
<>	149:156823d33999	4783	break;
<>	149:156823d33999	4784
<>	149:156823d33999	4785	case TIM_TS_ITR1:
<>	149:156823d33999	4786	{
<>	149:156823d33999	4787	/* Check the parameter */
<>	149:156823d33999	4788	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	149:156823d33999	4789	}
<>	149:156823d33999	4790	break;
<>	149:156823d33999	4791
<>	149:156823d33999	4792	case TIM_TS_ITR2:
<>	149:156823d33999	4793	{
<>	149:156823d33999	4794	/* Check the parameter */
<>	149:156823d33999	4795	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	149:156823d33999	4796	}
<>	149:156823d33999	4797	break;
<>	149:156823d33999	4798
<>	149:156823d33999	4799	case TIM_TS_ITR3:
<>	149:156823d33999	4800	{
<>	149:156823d33999	4801	/* Check the parameter */
<>	149:156823d33999	4802	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	149:156823d33999	4803	}
<>	149:156823d33999	4804	break;
<>	149:156823d33999	4805
<>	149:156823d33999	4806	default:
<>	149:156823d33999	4807	break;
<>	149:156823d33999	4808	}
<>	149:156823d33999	4809	}
<>	149:156823d33999	4810
<>	149:156823d33999	4811	/**
<>	149:156823d33999	4812	* @brief Configure the TI1 as Input.
<>	149:156823d33999	4813	* @param TIMx to select the TIM peripheral.
<>	149:156823d33999	4814	* @param TIM_ICPolarity : The Input Polarity.
<>	149:156823d33999	4815	* This parameter can be one of the following values:
<>	149:156823d33999	4816	* @arg TIM_ICPOLARITY_RISING
<>	149:156823d33999	4817	* @arg TIM_ICPOLARITY_FALLING
<>	149:156823d33999	4818	* @arg TIM_ICPOLARITY_BOTHEDGE
<>	149:156823d33999	4819	* @param TIM_ICSelection: specifies the input to be used.
<>	149:156823d33999	4820	* This parameter can be one of the following values:
<>	149:156823d33999	4821	* @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
<>	149:156823d33999	4822	* @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
<>	149:156823d33999	4823	* @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
<>	149:156823d33999	4824	* @param TIM_ICFilter: Specifies the Input Capture Filter.
<>	149:156823d33999	4825	* This parameter must be a value between 0x00 and 0x0F.
<>	149:156823d33999	4826	* @retval None
<>	149:156823d33999	4827	* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
<>	149:156823d33999	4828	* (on channel2 path) is used as the input signal. Therefore CCMR1 must be
<>	149:156823d33999	4829	* protected against un-initialized filter and polarity values.
<>	149:156823d33999	4830	*/
<>	149:156823d33999	4831	static void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
<>	149:156823d33999	4832	uint32_t TIM_ICFilter)
<>	149:156823d33999	4833	{
<>	149:156823d33999	4834	uint32_t tmpccmr1 = 0;
<>	149:156823d33999	4835	uint32_t tmpccer = 0;
<>	149:156823d33999	4836
<>	149:156823d33999	4837	/* Disable the Channel 1: Reset the CC1E Bit */
<>	149:156823d33999	4838	TIMx->CCER &= ~TIM_CCER_CC1E;
<>	149:156823d33999	4839	tmpccmr1 = TIMx->CCMR1;
<>	149:156823d33999	4840	tmpccer = TIMx->CCER;
<>	149:156823d33999	4841
<>	149:156823d33999	4842	/* Select the Input */
<>	149:156823d33999	4843	if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
<>	149:156823d33999	4844	{
<>	149:156823d33999	4845	tmpccmr1 &= ~TIM_CCMR1_CC1S;
<>	149:156823d33999	4846	tmpccmr1 \|= TIM_ICSelection;
<>	149:156823d33999	4847	}
<>	149:156823d33999	4848	else
<>	149:156823d33999	4849	{
<>	149:156823d33999	4850	tmpccmr1 \|= TIM_CCMR1_CC1S_0;
<>	149:156823d33999	4851	}
<>	149:156823d33999	4852
<>	149:156823d33999	4853	/* Set the filter */
<>	149:156823d33999	4854	tmpccmr1 &= ~TIM_CCMR1_IC1F;
<>	149:156823d33999	4855	tmpccmr1 \|= ((TIM_ICFilter << 4) & TIM_CCMR1_IC1F);
<>	149:156823d33999	4856
<>	149:156823d33999	4857	/* Select the Polarity and set the CC1E Bit */
<>	149:156823d33999	4858	tmpccer &= ~(TIM_CCER_CC1P \| TIM_CCER_CC1NP);
<>	149:156823d33999	4859	tmpccer \|= (TIM_ICPolarity & (TIM_CCER_CC1P \| TIM_CCER_CC1NP));
<>	149:156823d33999	4860
<>	149:156823d33999	4861	/* Write to TIMx CCMR1 and CCER registers */
<>	149:156823d33999	4862	TIMx->CCMR1 = tmpccmr1;
<>	149:156823d33999	4863	TIMx->CCER = tmpccer;
<>	149:156823d33999	4864	}
<>	149:156823d33999	4865
<>	149:156823d33999	4866	/**
<>	149:156823d33999	4867	* @brief Configure the Polarity and Filter for TI1.
<>	149:156823d33999	4868	* @param TIMx to select the TIM peripheral.
<>	149:156823d33999	4869	* @param TIM_ICPolarity : The Input Polarity.
<>	149:156823d33999	4870	* This parameter can be one of the following values:
<>	149:156823d33999	4871	* @arg TIM_ICPOLARITY_RISING
<>	149:156823d33999	4872	* @arg TIM_ICPOLARITY_FALLING
<>	149:156823d33999	4873	* @arg TIM_ICPOLARITY_BOTHEDGE
<>	149:156823d33999	4874	* @param TIM_ICFilter: Specifies the Input Capture Filter.
<>	149:156823d33999	4875	* This parameter must be a value between 0x00 and 0x0F.
<>	149:156823d33999	4876	* @retval None
<>	149:156823d33999	4877	*/
<>	149:156823d33999	4878	static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
<>	149:156823d33999	4879	{
<>	149:156823d33999	4880	uint32_t tmpccmr1 = 0;
<>	149:156823d33999	4881	uint32_t tmpccer = 0;
<>	149:156823d33999	4882
<>	149:156823d33999	4883	/* Disable the Channel 1: Reset the CC1E Bit */
<>	149:156823d33999	4884	tmpccer = TIMx->CCER;
<>	149:156823d33999	4885	TIMx->CCER &= ~TIM_CCER_CC1E;
<>	149:156823d33999	4886	tmpccmr1 = TIMx->CCMR1;
<>	149:156823d33999	4887
<>	149:156823d33999	4888	/* Set the filter */
<>	149:156823d33999	4889	tmpccmr1 &= ~TIM_CCMR1_IC1F;
<>	149:156823d33999	4890	tmpccmr1 \|= (TIM_ICFilter << 4);
<>	149:156823d33999	4891
<>	149:156823d33999	4892	/* Select the Polarity and set the CC1E Bit */
<>	149:156823d33999	4893	tmpccer &= ~(TIM_CCER_CC1P \| TIM_CCER_CC1NP);
<>	149:156823d33999	4894	tmpccer \|= TIM_ICPolarity;
<>	149:156823d33999	4895
<>	149:156823d33999	4896	/* Write to TIMx CCMR1 and CCER registers */
<>	149:156823d33999	4897	TIMx->CCMR1 = tmpccmr1;
<>	149:156823d33999	4898	TIMx->CCER = tmpccer;
<>	149:156823d33999	4899	}
<>	149:156823d33999	4900
<>	149:156823d33999	4901	/**
<>	149:156823d33999	4902	* @brief Configure the TI2 as Input.
<>	149:156823d33999	4903	* @param TIMx to select the TIM peripheral
<>	149:156823d33999	4904	* @param TIM_ICPolarity : The Input Polarity.
<>	149:156823d33999	4905	* This parameter can be one of the following values:
<>	149:156823d33999	4906	* @arg TIM_ICPOLARITY_RISING
<>	149:156823d33999	4907	* @arg TIM_ICPOLARITY_FALLING
<>	149:156823d33999	4908	* @arg TIM_ICPOLARITY_BOTHEDGE
<>	149:156823d33999	4909	* @param TIM_ICSelection: specifies the input to be used.
<>	149:156823d33999	4910	* This parameter can be one of the following values:
<>	149:156823d33999	4911	* @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
<>	149:156823d33999	4912	* @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
<>	149:156823d33999	4913	* @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
<>	149:156823d33999	4914	* @param TIM_ICFilter: Specifies the Input Capture Filter.
<>	149:156823d33999	4915	* This parameter must be a value between 0x00 and 0x0F.
<>	149:156823d33999	4916	* @retval None
<>	149:156823d33999	4917	* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
<>	149:156823d33999	4918	* (on channel1 path) is used as the input signal. Therefore CCMR1 must be
<>	149:156823d33999	4919	* protected against un-initialized filter and polarity values.
<>	149:156823d33999	4920	*/
<>	149:156823d33999	4921	static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
<>	149:156823d33999	4922	uint32_t TIM_ICFilter)
<>	149:156823d33999	4923	{
<>	149:156823d33999	4924	uint32_t tmpccmr1 = 0;
<>	149:156823d33999	4925	uint32_t tmpccer = 0;
<>	149:156823d33999	4926
<>	149:156823d33999	4927	/* Disable the Channel 2: Reset the CC2E Bit */
<>	149:156823d33999	4928	TIMx->CCER &= ~TIM_CCER_CC2E;
<>	149:156823d33999	4929	tmpccmr1 = TIMx->CCMR1;
<>	149:156823d33999	4930	tmpccer = TIMx->CCER;
<>	149:156823d33999	4931
<>	149:156823d33999	4932	/* Select the Input */
<>	149:156823d33999	4933	tmpccmr1 &= ~TIM_CCMR1_CC2S;
<>	149:156823d33999	4934	tmpccmr1 \|= (TIM_ICSelection << 8);
<>	149:156823d33999	4935
<>	149:156823d33999	4936	/* Set the filter */
<>	149:156823d33999	4937	tmpccmr1 &= ~TIM_CCMR1_IC2F;
<>	149:156823d33999	4938	tmpccmr1 \|= ((TIM_ICFilter << 12) & TIM_CCMR1_IC2F);
<>	149:156823d33999	4939
<>	149:156823d33999	4940	/* Select the Polarity and set the CC2E Bit */
<>	149:156823d33999	4941	tmpccer &= ~(TIM_CCER_CC2P \| TIM_CCER_CC2NP);
<>	149:156823d33999	4942	tmpccer \|= ((TIM_ICPolarity << 4) & (TIM_CCER_CC2P \| TIM_CCER_CC2NP));
<>	149:156823d33999	4943
<>	149:156823d33999	4944	/* Write to TIMx CCMR1 and CCER registers */
<>	149:156823d33999	4945	TIMx->CCMR1 = tmpccmr1 ;
<>	149:156823d33999	4946	TIMx->CCER = tmpccer;
<>	149:156823d33999	4947	}
<>	149:156823d33999	4948
<>	149:156823d33999	4949	/**
<>	149:156823d33999	4950	* @brief Configure the Polarity and Filter for TI2.
<>	149:156823d33999	4951	* @param TIMx to select the TIM peripheral.
<>	149:156823d33999	4952	* @param TIM_ICPolarity : The Input Polarity.
<>	149:156823d33999	4953	* This parameter can be one of the following values:
<>	149:156823d33999	4954	* @arg TIM_ICPOLARITY_RISING
<>	149:156823d33999	4955	* @arg TIM_ICPOLARITY_FALLING
<>	149:156823d33999	4956	* @arg TIM_ICPOLARITY_BOTHEDGE
<>	149:156823d33999	4957	* @param TIM_ICFilter: Specifies the Input Capture Filter.
<>	149:156823d33999	4958	* This parameter must be a value between 0x00 and 0x0F.
<>	149:156823d33999	4959	* @retval None
<>	149:156823d33999	4960	*/
<>	149:156823d33999	4961	static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
<>	149:156823d33999	4962	{
<>	149:156823d33999	4963	uint32_t tmpccmr1 = 0;
<>	149:156823d33999	4964	uint32_t tmpccer = 0;
<>	149:156823d33999	4965
<>	149:156823d33999	4966	/* Disable the Channel 2: Reset the CC2E Bit */
<>	149:156823d33999	4967	TIMx->CCER &= ~TIM_CCER_CC2E;
<>	149:156823d33999	4968	tmpccmr1 = TIMx->CCMR1;
<>	149:156823d33999	4969	tmpccer = TIMx->CCER;
<>	149:156823d33999	4970
<>	149:156823d33999	4971	/* Set the filter */
<>	149:156823d33999	4972	tmpccmr1 &= ~TIM_CCMR1_IC2F;
<>	149:156823d33999	4973	tmpccmr1 \|= (TIM_ICFilter << 12);
<>	149:156823d33999	4974
<>	149:156823d33999	4975	/* Select the Polarity and set the CC2E Bit */
<>	149:156823d33999	4976	tmpccer &= ~(TIM_CCER_CC2P \| TIM_CCER_CC2NP);
<>	149:156823d33999	4977	tmpccer \|= (TIM_ICPolarity << 4);
<>	149:156823d33999	4978
<>	149:156823d33999	4979	/* Write to TIMx CCMR1 and CCER registers */
<>	149:156823d33999	4980	TIMx->CCMR1 = tmpccmr1 ;
<>	149:156823d33999	4981	TIMx->CCER = tmpccer;
<>	149:156823d33999	4982	}
<>	149:156823d33999	4983
<>	149:156823d33999	4984	/**
<>	149:156823d33999	4985	* @brief Configure the TI3 as Input.
<>	149:156823d33999	4986	* @param TIMx to select the TIM peripheral
<>	149:156823d33999	4987	* @param TIM_ICPolarity : The Input Polarity.
<>	149:156823d33999	4988	* This parameter can be one of the following values:
<>	149:156823d33999	4989	* @arg TIM_ICPOLARITY_RISING
<>	149:156823d33999	4990	* @arg TIM_ICPOLARITY_FALLING
<>	149:156823d33999	4991	* @arg TIM_ICPOLARITY_BOTHEDGE
<>	149:156823d33999	4992	* @param TIM_ICSelection: specifies the input to be used.
<>	149:156823d33999	4993	* This parameter can be one of the following values:
<>	149:156823d33999	4994	* @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
<>	149:156823d33999	4995	* @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
<>	149:156823d33999	4996	* @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
<>	149:156823d33999	4997	* @param TIM_ICFilter: Specifies the Input Capture Filter.
<>	149:156823d33999	4998	* This parameter must be a value between 0x00 and 0x0F.
<>	149:156823d33999	4999	* @retval None
<>	149:156823d33999	5000	* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
<>	149:156823d33999	5001	* (on channel1 path) is used as the input signal. Therefore CCMR2 must be
<>	149:156823d33999	5002	* protected against un-initialized filter and polarity values.
<>	149:156823d33999	5003	*/
<>	149:156823d33999	5004	static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
<>	149:156823d33999	5005	uint32_t TIM_ICFilter)
<>	149:156823d33999	5006	{
<>	149:156823d33999	5007	uint32_t tmpccmr2 = 0;
<>	149:156823d33999	5008	uint32_t tmpccer = 0;
<>	149:156823d33999	5009
<>	149:156823d33999	5010	/* Disable the Channel 3: Reset the CC3E Bit */
<>	149:156823d33999	5011	TIMx->CCER &= ~TIM_CCER_CC3E;
<>	149:156823d33999	5012	tmpccmr2 = TIMx->CCMR2;
<>	149:156823d33999	5013	tmpccer = TIMx->CCER;
<>	149:156823d33999	5014
<>	149:156823d33999	5015	/* Select the Input */
<>	149:156823d33999	5016	tmpccmr2 &= ~TIM_CCMR2_CC3S;
<>	149:156823d33999	5017	tmpccmr2 \|= TIM_ICSelection;
<>	149:156823d33999	5018
<>	149:156823d33999	5019	/* Set the filter */
<>	149:156823d33999	5020	tmpccmr2 &= ~TIM_CCMR2_IC3F;
<>	149:156823d33999	5021	tmpccmr2 \|= ((TIM_ICFilter << 4) & TIM_CCMR2_IC3F);
<>	149:156823d33999	5022
<>	149:156823d33999	5023	/* Select the Polarity and set the CC3E Bit */
<>	149:156823d33999	5024	tmpccer &= ~(TIM_CCER_CC3P \| TIM_CCER_CC3NP);
<>	149:156823d33999	5025	tmpccer \|= ((TIM_ICPolarity << 8) & (TIM_CCER_CC3P \| TIM_CCER_CC3NP));
<>	149:156823d33999	5026
<>	149:156823d33999	5027	/* Write to TIMx CCMR2 and CCER registers */
<>	149:156823d33999	5028	TIMx->CCMR2 = tmpccmr2;
<>	149:156823d33999	5029	TIMx->CCER = tmpccer;
<>	149:156823d33999	5030	}
<>	149:156823d33999	5031
<>	149:156823d33999	5032	/**
<>	149:156823d33999	5033	* @brief Configure the TI4 as Input.
<>	149:156823d33999	5034	* @param TIMx to select the TIM peripheral
<>	149:156823d33999	5035	* @param TIM_ICPolarity : The Input Polarity.
<>	149:156823d33999	5036	* This parameter can be one of the following values:
<>	149:156823d33999	5037	* @arg TIM_ICPOLARITY_RISING
<>	149:156823d33999	5038	* @arg TIM_ICPOLARITY_FALLING
<>	149:156823d33999	5039	* @arg TIM_ICPOLARITY_BOTHEDGE
<>	149:156823d33999	5040	* @param TIM_ICSelection: specifies the input to be used.
<>	149:156823d33999	5041	* This parameter can be one of the following values:
<>	149:156823d33999	5042	* @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
<>	149:156823d33999	5043	* @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
<>	149:156823d33999	5044	* @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
<>	149:156823d33999	5045	* @param TIM_ICFilter: Specifies the Input Capture Filter.
<>	149:156823d33999	5046	* This parameter must be a value between 0x00 and 0x0F.
<>	149:156823d33999	5047	* @retval None
<>	149:156823d33999	5048	* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
<>	149:156823d33999	5049	* (on channel1 path) is used as the input signal. Therefore CCMR2 must be
<>	149:156823d33999	5050	* protected against un-initialized filter and polarity values.
<>	149:156823d33999	5051	*/
<>	149:156823d33999	5052	static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
<>	149:156823d33999	5053	uint32_t TIM_ICFilter)
<>	149:156823d33999	5054	{
<>	149:156823d33999	5055	uint32_t tmpccmr2 = 0;
<>	149:156823d33999	5056	uint32_t tmpccer = 0;
<>	149:156823d33999	5057
<>	149:156823d33999	5058	/* Disable the Channel 4: Reset the CC4E Bit */
<>	149:156823d33999	5059	TIMx->CCER &= ~TIM_CCER_CC4E;
<>	149:156823d33999	5060	tmpccmr2 = TIMx->CCMR2;
<>	149:156823d33999	5061	tmpccer = TIMx->CCER;
<>	149:156823d33999	5062
<>	149:156823d33999	5063	/* Select the Input */
<>	149:156823d33999	5064	tmpccmr2 &= ~TIM_CCMR2_CC4S;
<>	149:156823d33999	5065	tmpccmr2 \|= (TIM_ICSelection << 8);
<>	149:156823d33999	5066
<>	149:156823d33999	5067	/* Set the filter */
<>	149:156823d33999	5068	tmpccmr2 &= ~TIM_CCMR2_IC4F;
<>	149:156823d33999	5069	tmpccmr2 \|= ((TIM_ICFilter << 12) & TIM_CCMR2_IC4F);
<>	149:156823d33999	5070
<>	149:156823d33999	5071	/* Select the Polarity and set the CC4E Bit */
<>	149:156823d33999	5072	tmpccer &= ~(TIM_CCER_CC4P \| TIM_CCER_CC4NP);
<>	149:156823d33999	5073	tmpccer \|= ((TIM_ICPolarity << 12) & (TIM_CCER_CC4P \| TIM_CCER_CC4NP));
<>	149:156823d33999	5074
<>	149:156823d33999	5075	/* Write to TIMx CCMR2 and CCER registers */
<>	149:156823d33999	5076	TIMx->CCMR2 = tmpccmr2;
<>	149:156823d33999	5077	TIMx->CCER = tmpccer ;
<>	149:156823d33999	5078	}
<>	149:156823d33999	5079
<>	149:156823d33999	5080	/**
<>	149:156823d33999	5081	* @brief Selects the Input Trigger source
<>	149:156823d33999	5082	* @param TIMx to select the TIM peripheral
<>	149:156823d33999	5083	* @param InputTriggerSource: The Input Trigger source.
<>	149:156823d33999	5084	* This parameter can be one of the following values:
<>	149:156823d33999	5085	* @arg TIM_TS_ITR0: Internal Trigger 0
<>	149:156823d33999	5086	* @arg TIM_TS_ITR1: Internal Trigger 1
<>	149:156823d33999	5087	* @arg TIM_TS_ITR2: Internal Trigger 2
<>	149:156823d33999	5088	* @arg TIM_TS_ITR3: Internal Trigger 3
<>	149:156823d33999	5089	* @arg TIM_TS_TI1F_ED: TI1 Edge Detector
<>	149:156823d33999	5090	* @arg TIM_TS_TI1FP1: Filtered Timer Input 1
<>	149:156823d33999	5091	* @arg TIM_TS_TI2FP2: Filtered Timer Input 2
<>	149:156823d33999	5092	* @arg TIM_TS_ETRF: External Trigger input
<>	149:156823d33999	5093	* @retval None
<>	149:156823d33999	5094	*/
<>	149:156823d33999	5095	static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource)
<>	149:156823d33999	5096	{
<>	149:156823d33999	5097	uint32_t tmpsmcr = 0;
<>	149:156823d33999	5098
<>	149:156823d33999	5099	/* Get the TIMx SMCR register value */
<>	149:156823d33999	5100	tmpsmcr = TIMx->SMCR;
<>	149:156823d33999	5101	/* Reset the TS Bits */
<>	149:156823d33999	5102	tmpsmcr &= ~TIM_SMCR_TS;
<>	149:156823d33999	5103	/* Set the Input Trigger source and the slave mode*/
<>	149:156823d33999	5104	tmpsmcr \|= InputTriggerSource \| TIM_SLAVEMODE_EXTERNAL1;
<>	149:156823d33999	5105	/* Write to TIMx SMCR */
<>	149:156823d33999	5106	TIMx->SMCR = tmpsmcr;
<>	149:156823d33999	5107	}
<>	149:156823d33999	5108	/**
<>	149:156823d33999	5109	* @brief Configures the TIMx External Trigger (ETR).
<>	149:156823d33999	5110	* @param TIMx to select the TIM peripheral
<>	149:156823d33999	5111	* @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
<>	149:156823d33999	5112	* This parameter can be one of the following values:
<>	149:156823d33999	5113	* @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
<>	149:156823d33999	5114	* @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
<>	149:156823d33999	5115	* @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
<>	149:156823d33999	5116	* @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
<>	149:156823d33999	5117	* @param TIM_ExtTRGPolarity: The external Trigger Polarity.
<>	149:156823d33999	5118	* This parameter can be one of the following values:
<>	149:156823d33999	5119	* @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
<>	149:156823d33999	5120	* @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
<>	149:156823d33999	5121	* @param ExtTRGFilter: External Trigger Filter.
<>	149:156823d33999	5122	* This parameter must be a value between 0x00 and 0x0F
<>	149:156823d33999	5123	* @retval None
<>	149:156823d33999	5124	*/
<>	149:156823d33999	5125	static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
<>	149:156823d33999	5126	uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
<>	149:156823d33999	5127	{
<>	149:156823d33999	5128	uint32_t tmpsmcr = 0;
<>	149:156823d33999	5129
<>	149:156823d33999	5130	tmpsmcr = TIMx->SMCR;
<>	149:156823d33999	5131
<>	149:156823d33999	5132	/* Reset the ETR Bits */
<>	149:156823d33999	5133	tmpsmcr &= (uint32_t)(~(TIM_SMCR_ETF \| TIM_SMCR_ETPS \| TIM_SMCR_ECE \| TIM_SMCR_ETP));
<>	149:156823d33999	5134
<>	149:156823d33999	5135	/* Set the Prescaler, the Filter value and the Polarity */
<>	149:156823d33999	5136	tmpsmcr \|= (uint32_t)(TIM_ExtTRGPrescaler \| (TIM_ExtTRGPolarity \| (ExtTRGFilter << 8)));
<>	149:156823d33999	5137
<>	149:156823d33999	5138	/* Write to TIMx SMCR */
<>	149:156823d33999	5139	TIMx->SMCR = tmpsmcr;
<>	149:156823d33999	5140	}
<>	149:156823d33999	5141
<>	149:156823d33999	5142	/**
<>	149:156823d33999	5143	* @brief Enables or disables the TIM Capture Compare Channel x.
<>	149:156823d33999	5144	* @param TIMx to select the TIM peripheral
<>	149:156823d33999	5145	* @param Channel: specifies the TIM Channel
<>	149:156823d33999	5146	* This parameter can be one of the following values:
<>	149:156823d33999	5147	* @arg TIM_CHANNEL_1: TIM Channel 1
<>	149:156823d33999	5148	* @arg TIM_CHANNEL_2: TIM Channel 2
<>	149:156823d33999	5149	* @arg TIM_CHANNEL_3: TIM Channel 3
<>	149:156823d33999	5150	* @arg TIM_CHANNEL_4: TIM Channel 4
<>	149:156823d33999	5151	* @param ChannelState: specifies the TIM Channel CCxE bit new state.
<>	149:156823d33999	5152	* This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
<>	149:156823d33999	5153	* @retval None
<>	149:156823d33999	5154	*/
<>	149:156823d33999	5155	static void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
<>	149:156823d33999	5156	{
<>	149:156823d33999	5157	uint32_t tmp = 0;
<>	149:156823d33999	5158
<>	149:156823d33999	5159	/* Check the parameters */
<>	149:156823d33999	5160	assert_param(IS_TIM_CC1_INSTANCE(TIMx));
<>	149:156823d33999	5161	assert_param(IS_TIM_CHANNELS(Channel));
<>	149:156823d33999	5162
<>	149:156823d33999	5163	tmp = TIM_CCER_CC1E << Channel;
<>	149:156823d33999	5164
<>	149:156823d33999	5165	/* Reset the CCxE Bit */
<>	149:156823d33999	5166	TIMx->CCER &= ~tmp;
<>	149:156823d33999	5167
<>	149:156823d33999	5168	/* Set or reset the CCxE Bit */
<>	149:156823d33999	5169	TIMx->CCER \|= (uint32_t)(ChannelState << Channel);
<>	149:156823d33999	5170	}
<>	149:156823d33999	5171
<>	149:156823d33999	5172	/**
<>	149:156823d33999	5173	* @}
<>	149:156823d33999	5174	*/
<>	149:156823d33999	5175
<>	149:156823d33999	5176	#endif /* HAL_TIM_MODULE_ENABLED */
<>	149:156823d33999	5177	/**
<>	149:156823d33999	5178	* @}
<>	149:156823d33999	5179	*/
<>	149:156823d33999	5180
<>	149:156823d33999	5181	/**
<>	149:156823d33999	5182	* @}
<>	149:156823d33999	5183	*/
<>	149:156823d33999	5184	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	22 Dec 2016
Imports:	1
Forks:	0
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targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_tim.c@149:156823d33999, 2016-10-28 (annotated)

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