mbed-STM - mbed library sources. Supersedes mbed-src.

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Fawwaz Nadzmy / mbed-STM

mbed library sources. Supersedes mbed-src.

Fork of mbed-dev by mbed official

targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_spi.c@149:156823d33999, 2016-10-28 (annotated)

Committer:: <>
Date:: Fri Oct 28 11:17:30 2016 +0100
Revision:: 149:156823d33999

This updates the lib to the mbed lib v128

NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	149:156823d33999	1	/**
<>	149:156823d33999	2	******************************************************************************
<>	149:156823d33999	3	* @file stm32l1xx_hal_spi.c
<>	149:156823d33999	4	* @author MCD Application Team
<>	149:156823d33999	5	* @version V1.2.0
<>	149:156823d33999	6	* @date 01-July-2016
<>	149:156823d33999	7	* @brief SPI HAL module driver.
<>	149:156823d33999	8	*
<>	149:156823d33999	9	* This file provides firmware functions to manage the following
<>	149:156823d33999	10	* functionalities of the Serial Peripheral Interface (SPI) peripheral:
<>	149:156823d33999	11	* + Initialization and de-initialization functions
<>	149:156823d33999	12	* + IO operation functions
<>	149:156823d33999	13	* + Peripheral Control functions
<>	149:156823d33999	14	* + Peripheral State functions
<>	149:156823d33999	15	@verbatim
<>	149:156823d33999	16	==============================================================================
<>	149:156823d33999	17	##### How to use this driver #####
<>	149:156823d33999	18	==============================================================================
<>	149:156823d33999	19	[..]
<>	149:156823d33999	20	The SPI HAL driver can be used as follows:
<>	149:156823d33999	21
<>	149:156823d33999	22	(#) Declare a SPI_HandleTypeDef handle structure, for example:
<>	149:156823d33999	23	SPI_HandleTypeDef hspi;
<>	149:156823d33999	24
<>	149:156823d33999	25	(#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit ()API:
<>	149:156823d33999	26	(##) Enable the SPIx interface clock
<>	149:156823d33999	27	(##) SPI pins configuration
<>	149:156823d33999	28	(+++) Enable the clock for the SPI GPIOs
<>	149:156823d33999	29	(+++) Configure these SPI pins as alternate function push-pull
<>	149:156823d33999	30	(##) NVIC configuration if you need to use interrupt process
<>	149:156823d33999	31	(+++) Configure the SPIx interrupt priority
<>	149:156823d33999	32	(+++) Enable the NVIC SPI IRQ handle
<>	149:156823d33999	33	(##) DMA Configuration if you need to use DMA process
<>	149:156823d33999	34	(+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Channel
<>	149:156823d33999	35	(+++) Enable the DMAx clock
<>	149:156823d33999	36	(+++) Configure the DMA handle parameters
<>	149:156823d33999	37	(+++) Configure the DMA Tx or Rx Channel
<>	149:156823d33999	38	(+++) Associate the initilalized hdma_tx(or _rx) handle to the hspi DMA Tx (or Rx) handle
<>	149:156823d33999	39	(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Channel
<>	149:156823d33999	40
<>	149:156823d33999	41	(#) Program the Mode, Direction , Data size, Baudrate Prescaler, NSS
<>	149:156823d33999	42	management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
<>	149:156823d33999	43
<>	149:156823d33999	44	(#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
<>	149:156823d33999	45	(++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
<>	149:156823d33999	46	by calling the customed HAL_SPI_MspInit() API.
<>	149:156823d33999	47	[..]
<>	149:156823d33999	48	Circular mode restriction:
<>	149:156823d33999	49	(#) The DMA circular mode cannot be used when the SPI is configured in these modes:
<>	149:156823d33999	50	(##) Master 2Lines RxOnly
<>	149:156823d33999	51	(##) Master 1Line Rx
<>	149:156823d33999	52	(#) The CRC feature is not managed when the DMA circular mode is enabled
<>	149:156823d33999	53	(#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
<>	149:156823d33999	54	the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
<>	149:156823d33999	55
<>	149:156823d33999	56
<>	149:156823d33999	57
<>	149:156823d33999	58	@endverbatim
<>	149:156823d33999	59	******************************************************************************
<>	149:156823d33999	60	* @attention
<>	149:156823d33999	61	*
<>	149:156823d33999	62	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	149:156823d33999	63	*
<>	149:156823d33999	64	* Redistribution and use in source and binary forms, with or without modification,
<>	149:156823d33999	65	* are permitted provided that the following conditions are met:
<>	149:156823d33999	66	* 1. Redistributions of source code must retain the above copyright notice,
<>	149:156823d33999	67	* this list of conditions and the following disclaimer.
<>	149:156823d33999	68	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	149:156823d33999	69	* this list of conditions and the following disclaimer in the documentation
<>	149:156823d33999	70	* and/or other materials provided with the distribution.
<>	149:156823d33999	71	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	149:156823d33999	72	* may be used to endorse or promote products derived from this software
<>	149:156823d33999	73	* without specific prior written permission.
<>	149:156823d33999	74	*
<>	149:156823d33999	75	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	149:156823d33999	76	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	149:156823d33999	77	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	149:156823d33999	78	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	149:156823d33999	79	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	149:156823d33999	80	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	149:156823d33999	81	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	149:156823d33999	82	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	149:156823d33999	83	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	149:156823d33999	84	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	149:156823d33999	85	*
<>	149:156823d33999	86	******************************************************************************
<>	149:156823d33999	87	*/
<>	149:156823d33999	88
<>	149:156823d33999	89	/* Includes ------------------------------------------------------------------*/
<>	149:156823d33999	90	#include "stm32l1xx_hal.h"
<>	149:156823d33999	91
<>	149:156823d33999	92	/** @addtogroup STM32L1xx_HAL_Driver
<>	149:156823d33999	93	* @{
<>	149:156823d33999	94	*/
<>	149:156823d33999	95
<>	149:156823d33999	96	/** @defgroup SPI SPI
<>	149:156823d33999	97	* @brief SPI HAL module driver
<>	149:156823d33999	98	* @{
<>	149:156823d33999	99	*/
<>	149:156823d33999	100
<>	149:156823d33999	101	#ifdef HAL_SPI_MODULE_ENABLED
<>	149:156823d33999	102
<>	149:156823d33999	103	/* Private typedef -----------------------------------------------------------*/
<>	149:156823d33999	104	/* Private define ------------------------------------------------------------*/
<>	149:156823d33999	105	/** @defgroup SPI_Private_Constants SPI Private Constants
<>	149:156823d33999	106	* @{
<>	149:156823d33999	107	*/
<>	149:156823d33999	108	#define SPI_TIMEOUT_VALUE 10
<>	149:156823d33999	109	/**
<>	149:156823d33999	110	* @}
<>	149:156823d33999	111	*/
<>	149:156823d33999	112
<>	149:156823d33999	113	/* Private macro -------------------------------------------------------------*/
<>	149:156823d33999	114	/* Private variables ---------------------------------------------------------*/
<>	149:156823d33999	115	/* Private function prototypes -----------------------------------------------*/
<>	149:156823d33999	116	/** @defgroup SPI_Private_Functions SPI Private Functions
<>	149:156823d33999	117	* @{
<>	149:156823d33999	118	*/
<>	149:156823d33999	119
<>	149:156823d33999	120	static void SPI_TxCloseIRQHandler(struct __SPI_HandleTypeDef *hspi);
<>	149:156823d33999	121	static void SPI_TxISR(struct __SPI_HandleTypeDef *hspi);
<>	149:156823d33999	122	static void SPI_RxCloseIRQHandler(struct __SPI_HandleTypeDef *hspi);
<>	149:156823d33999	123	static void SPI_2LinesRxISR(struct __SPI_HandleTypeDef *hspi);
<>	149:156823d33999	124	static void SPI_RxISR(struct __SPI_HandleTypeDef *hspi);
<>	149:156823d33999	125	static void SPI_DMATransmitCplt(struct __DMA_HandleTypeDef *hdma);
<>	149:156823d33999	126	static void SPI_DMAReceiveCplt(struct __DMA_HandleTypeDef *hdma);
<>	149:156823d33999	127	static void SPI_DMATransmitReceiveCplt(struct __DMA_HandleTypeDef *hdma);
<>	149:156823d33999	128	static void SPI_DMAHalfTransmitCplt(struct __DMA_HandleTypeDef *hdma);
<>	149:156823d33999	129	static void SPI_DMAHalfReceiveCplt(struct __DMA_HandleTypeDef *hdma);
<>	149:156823d33999	130	static void SPI_DMAHalfTransmitReceiveCplt(struct __DMA_HandleTypeDef *hdma);
<>	149:156823d33999	131	static void SPI_DMAError(struct __DMA_HandleTypeDef *hdma);
<>	149:156823d33999	132	static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(struct __SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
<>	149:156823d33999	133	/**
<>	149:156823d33999	134	* @}
<>	149:156823d33999	135	*/
<>	149:156823d33999	136
<>	149:156823d33999	137	/* Exported functions ---------------------------------------------------------*/
<>	149:156823d33999	138
<>	149:156823d33999	139	/** @defgroup SPI_Exported_Functions SPI Exported Functions
<>	149:156823d33999	140	* @{
<>	149:156823d33999	141	*/
<>	149:156823d33999	142
<>	149:156823d33999	143	/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
<>	149:156823d33999	144	* @brief Initialization and Configuration functions
<>	149:156823d33999	145	*
<>	149:156823d33999	146	@verbatim
<>	149:156823d33999	147	===============================================================================
<>	149:156823d33999	148	##### Initialization and de-initialization functions #####
<>	149:156823d33999	149	===============================================================================
<>	149:156823d33999	150	[..] This subsection provides a set of functions allowing to initialize and
<>	149:156823d33999	151	de-initialiaze the SPIx peripheral:
<>	149:156823d33999	152
<>	149:156823d33999	153	(+) User must implement HAL_SPI_MspInit() function in which he configures
<>	149:156823d33999	154	all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
<>	149:156823d33999	155
<>	149:156823d33999	156	(+) Call the function HAL_SPI_Init() to configure the selected device with
<>	149:156823d33999	157	the selected configuration:
<>	149:156823d33999	158	(++) Mode
<>	149:156823d33999	159	(++) Direction
<>	149:156823d33999	160	(++) Data Size
<>	149:156823d33999	161	(++) Clock Polarity and Phase
<>	149:156823d33999	162	(++) NSS Management
<>	149:156823d33999	163	(++) BaudRate Prescaler
<>	149:156823d33999	164	(++) FirstBit
<>	149:156823d33999	165	(++) TIMode
<>	149:156823d33999	166	(++) CRC Calculation
<>	149:156823d33999	167	(++) CRC Polynomial if CRC enabled
<>	149:156823d33999	168
<>	149:156823d33999	169	(+) Call the function HAL_SPI_DeInit() to restore the default configuration
<>	149:156823d33999	170	of the selected SPIx periperal.
<>	149:156823d33999	171
<>	149:156823d33999	172	@endverbatim
<>	149:156823d33999	173	* @{
<>	149:156823d33999	174	*/
<>	149:156823d33999	175
<>	149:156823d33999	176	/**
<>	149:156823d33999	177	* @brief Initializes the SPI according to the specified parameters
<>	149:156823d33999	178	* in the SPI_InitTypeDef and create the associated handle.
<>	149:156823d33999	179	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	180	* the configuration information for SPI module.
<>	149:156823d33999	181	* @retval HAL status
<>	149:156823d33999	182	*/
<>	149:156823d33999	183	__weak HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
<>	149:156823d33999	184	{
<>	149:156823d33999	185	/* Prevent unused argument(s) compilation warning */
<>	149:156823d33999	186	UNUSED(hspi);
<>	149:156823d33999	187
<>	149:156823d33999	188	return HAL_ERROR;
<>	149:156823d33999	189	}
<>	149:156823d33999	190
<>	149:156823d33999	191	/**
<>	149:156823d33999	192	* @brief DeInitializes the SPI peripheral
<>	149:156823d33999	193	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	194	* the configuration information for SPI module.
<>	149:156823d33999	195	* @retval HAL status
<>	149:156823d33999	196	*/
<>	149:156823d33999	197	HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
<>	149:156823d33999	198	{
<>	149:156823d33999	199	/* Check the SPI handle allocation */
<>	149:156823d33999	200	if(hspi == NULL)
<>	149:156823d33999	201	{
<>	149:156823d33999	202	return HAL_ERROR;
<>	149:156823d33999	203	}
<>	149:156823d33999	204
<>	149:156823d33999	205	/* Disable the SPI Peripheral Clock */
<>	149:156823d33999	206	__HAL_SPI_DISABLE(hspi);
<>	149:156823d33999	207
<>	149:156823d33999	208	/* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
<>	149:156823d33999	209	HAL_SPI_MspDeInit(hspi);
<>	149:156823d33999	210
<>	149:156823d33999	211	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<>	149:156823d33999	212	hspi->State = HAL_SPI_STATE_RESET;
<>	149:156823d33999	213
<>	149:156823d33999	214	/* Release Lock */
<>	149:156823d33999	215	__HAL_UNLOCK(hspi);
<>	149:156823d33999	216
<>	149:156823d33999	217	return HAL_OK;
<>	149:156823d33999	218	}
<>	149:156823d33999	219
<>	149:156823d33999	220	/**
<>	149:156823d33999	221	* @brief SPI MSP Init
<>	149:156823d33999	222	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	223	* the configuration information for SPI module.
<>	149:156823d33999	224	* @retval None
<>	149:156823d33999	225	*/
<>	149:156823d33999	226	__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
<>	149:156823d33999	227	{
<>	149:156823d33999	228	/* Prevent unused argument(s) compilation warning */
<>	149:156823d33999	229	UNUSED(hspi);
<>	149:156823d33999	230
<>	149:156823d33999	231	/* NOTE : This function Should not be modified, when the callback is needed,
<>	149:156823d33999	232	the HAL_SPI_MspInit could be implenetd in the user file
<>	149:156823d33999	233	*/
<>	149:156823d33999	234	}
<>	149:156823d33999	235
<>	149:156823d33999	236	/**
<>	149:156823d33999	237	* @brief SPI MSP DeInit
<>	149:156823d33999	238	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	239	* the configuration information for SPI module.
<>	149:156823d33999	240	* @retval None
<>	149:156823d33999	241	*/
<>	149:156823d33999	242	__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
<>	149:156823d33999	243	{
<>	149:156823d33999	244	/* Prevent unused argument(s) compilation warning */
<>	149:156823d33999	245	UNUSED(hspi);
<>	149:156823d33999	246
<>	149:156823d33999	247	/* NOTE : This function Should not be modified, when the callback is needed,
<>	149:156823d33999	248	the HAL_SPI_MspDeInit could be implenetd in the user file
<>	149:156823d33999	249	*/
<>	149:156823d33999	250	}
<>	149:156823d33999	251
<>	149:156823d33999	252	/**
<>	149:156823d33999	253	* @}
<>	149:156823d33999	254	*/
<>	149:156823d33999	255
<>	149:156823d33999	256	/** @defgroup SPI_Exported_Functions_Group2 IO operation functions
<>	149:156823d33999	257	* @brief Data transfers functions
<>	149:156823d33999	258	*
<>	149:156823d33999	259	@verbatim
<>	149:156823d33999	260	==============================================================================
<>	149:156823d33999	261	##### IO operation functions #####
<>	149:156823d33999	262	===============================================================================
<>	149:156823d33999	263	This subsection provides a set of functions allowing to manage the SPI
<>	149:156823d33999	264	data transfers.
<>	149:156823d33999	265
<>	149:156823d33999	266	[..] The SPI supports master and slave mode :
<>	149:156823d33999	267
<>	149:156823d33999	268	(#) There are two modes of transfer:
<>	149:156823d33999	269	(++) Blocking mode: The communication is performed in polling mode.
<>	149:156823d33999	270	The HAL status of all data processing is returned by the same function
<>	149:156823d33999	271	after finishing transfer.
<>	149:156823d33999	272	(++) No-Blocking mode: The communication is performed using Interrupts
<>	149:156823d33999	273	or DMA, These APIs return the HAL status.
<>	149:156823d33999	274	The end of the data processing will be indicated through the
<>	149:156823d33999	275	dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
<>	149:156823d33999	276	using DMA mode.
<>	149:156823d33999	277	The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
<>	149:156823d33999	278	will be executed respectivelly at the end of the transmit or Receive process
<>	149:156823d33999	279	The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
<>	149:156823d33999	280
<>	149:156823d33999	281	(#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
<>	149:156823d33999	282	exist for 1Line (simplex) and 2Lines (full duplex) modes.
<>	149:156823d33999	283
<>	149:156823d33999	284	@endverbatim
<>	149:156823d33999	285	* @{
<>	149:156823d33999	286	*/
<>	149:156823d33999	287
<>	149:156823d33999	288	/**
<>	149:156823d33999	289	* @brief Transmit an amount of data in blocking mode
<>	149:156823d33999	290	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	291	* the configuration information for SPI module.
<>	149:156823d33999	292	* @param pData: pointer to data buffer
<>	149:156823d33999	293	* @param Size: amount of data to be sent
<>	149:156823d33999	294	* @param Timeout: Timeout duration
<>	149:156823d33999	295	* @retval HAL status
<>	149:156823d33999	296	*/
<>	149:156823d33999	297	HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size, uint32_t Timeout)
<>	149:156823d33999	298	{
<>	149:156823d33999	299
<>	149:156823d33999	300	if(hspi->State == HAL_SPI_STATE_READY)
<>	149:156823d33999	301	{
<>	149:156823d33999	302	if((pData == NULL ) \|\| (Size == 0))
<>	149:156823d33999	303	{
<>	149:156823d33999	304	return HAL_ERROR;
<>	149:156823d33999	305	}
<>	149:156823d33999	306
<>	149:156823d33999	307	/* Check the parameters */
<>	149:156823d33999	308	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
<>	149:156823d33999	309
<>	149:156823d33999	310	/* Process Locked */
<>	149:156823d33999	311	__HAL_LOCK(hspi);
<>	149:156823d33999	312
<>	149:156823d33999	313	/* Configure communication */
<>	149:156823d33999	314	hspi->State = HAL_SPI_STATE_BUSY_TX;
<>	149:156823d33999	315	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<>	149:156823d33999	316
<>	149:156823d33999	317	hspi->pTxBuffPtr = pData;
<>	149:156823d33999	318	hspi->TxXferSize = Size;
<>	149:156823d33999	319	hspi->TxXferCount = Size;
<>	149:156823d33999	320
<>	149:156823d33999	321	/Init field not used in handle to zero /
<>	149:156823d33999	322	hspi->TxISR = 0;
<>	149:156823d33999	323	hspi->RxISR = 0;
<>	149:156823d33999	324	hspi->pRxBuffPtr = NULL;
<>	149:156823d33999	325	hspi->RxXferSize = 0;
<>	149:156823d33999	326	hspi->RxXferCount = 0;
<>	149:156823d33999	327
<>	149:156823d33999	328	/* Reset CRC Calculation */
<>	149:156823d33999	329	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	149:156823d33999	330	{
<>	149:156823d33999	331	SPI_RESET_CRC(hspi);
<>	149:156823d33999	332	}
<>	149:156823d33999	333
<>	149:156823d33999	334	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
<>	149:156823d33999	335	{
<>	149:156823d33999	336	/* Configure communication direction : 1Line */
<>	149:156823d33999	337	SPI_1LINE_TX(hspi);
<>	149:156823d33999	338	}
<>	149:156823d33999	339
<>	149:156823d33999	340	/* Check if the SPI is already enabled */
<>	149:156823d33999	341	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
<>	149:156823d33999	342	{
<>	149:156823d33999	343	/* Enable SPI peripheral */
<>	149:156823d33999	344	__HAL_SPI_ENABLE(hspi);
<>	149:156823d33999	345	}
<>	149:156823d33999	346
<>	149:156823d33999	347	/* Transmit data in 8 Bit mode */
<>	149:156823d33999	348	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
<>	149:156823d33999	349	{
<>	149:156823d33999	350	if((hspi->Init.Mode == SPI_MODE_SLAVE)\|\| (hspi->TxXferCount == 0x01))
<>	149:156823d33999	351	{
<>	149:156823d33999	352	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
<>	149:156823d33999	353	hspi->TxXferCount--;
<>	149:156823d33999	354	}
<>	149:156823d33999	355	while(hspi->TxXferCount > 0)
<>	149:156823d33999	356	{
<>	149:156823d33999	357	/* Wait until TXE flag is set to send data */
<>	149:156823d33999	358	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
<>	149:156823d33999	359	{
<>	149:156823d33999	360	return HAL_TIMEOUT;
<>	149:156823d33999	361	}
<>	149:156823d33999	362	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
<>	149:156823d33999	363	hspi->TxXferCount--;
<>	149:156823d33999	364	}
<>	149:156823d33999	365	/* Enable CRC Transmission */
<>	149:156823d33999	366	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	149:156823d33999	367	{
<>	149:156823d33999	368	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<>	149:156823d33999	369	}
<>	149:156823d33999	370	}
<>	149:156823d33999	371	/* Transmit data in 16 Bit mode */
<>	149:156823d33999	372	else
<>	149:156823d33999	373	{
<>	149:156823d33999	374	if((hspi->Init.Mode == SPI_MODE_SLAVE) \|\| (hspi->TxXferCount == 0x01))
<>	149:156823d33999	375	{
<>	149:156823d33999	376	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
<>	149:156823d33999	377	hspi->pTxBuffPtr+=2;
<>	149:156823d33999	378	hspi->TxXferCount--;
<>	149:156823d33999	379	}
<>	149:156823d33999	380	while(hspi->TxXferCount > 0)
<>	149:156823d33999	381	{
<>	149:156823d33999	382	/* Wait until TXE flag is set to send data */
<>	149:156823d33999	383	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
<>	149:156823d33999	384	{
<>	149:156823d33999	385	return HAL_TIMEOUT;
<>	149:156823d33999	386	}
<>	149:156823d33999	387	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
<>	149:156823d33999	388	hspi->pTxBuffPtr+=2;
<>	149:156823d33999	389	hspi->TxXferCount--;
<>	149:156823d33999	390	}
<>	149:156823d33999	391	/* Enable CRC Transmission */
<>	149:156823d33999	392	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	149:156823d33999	393	{
<>	149:156823d33999	394	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<>	149:156823d33999	395	}
<>	149:156823d33999	396	}
<>	149:156823d33999	397
<>	149:156823d33999	398	/* Wait until TXE flag is set to send data */
<>	149:156823d33999	399	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
<>	149:156823d33999	400	{
<>	149:156823d33999	401	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<>	149:156823d33999	402	return HAL_TIMEOUT;
<>	149:156823d33999	403	}
<>	149:156823d33999	404
<>	149:156823d33999	405	/* Wait until Busy flag is reset before disabling SPI */
<>	149:156823d33999	406	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, Timeout) != HAL_OK)
<>	149:156823d33999	407	{
<>	149:156823d33999	408	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<>	149:156823d33999	409	return HAL_TIMEOUT;
<>	149:156823d33999	410	}
<>	149:156823d33999	411
<>	149:156823d33999	412	/* Clear OVERUN flag in 2 Lines communication mode because received is not read */
<>	149:156823d33999	413	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
<>	149:156823d33999	414	{
<>	149:156823d33999	415	__HAL_SPI_CLEAR_OVRFLAG(hspi);
<>	149:156823d33999	416	}
<>	149:156823d33999	417
<>	149:156823d33999	418	hspi->State = HAL_SPI_STATE_READY;
<>	149:156823d33999	419
<>	149:156823d33999	420	/* Process Unlocked */
<>	149:156823d33999	421	__HAL_UNLOCK(hspi);
<>	149:156823d33999	422
<>	149:156823d33999	423	return HAL_OK;
<>	149:156823d33999	424	}
<>	149:156823d33999	425	else
<>	149:156823d33999	426	{
<>	149:156823d33999	427	return HAL_BUSY;
<>	149:156823d33999	428	}
<>	149:156823d33999	429	}
<>	149:156823d33999	430
<>	149:156823d33999	431	/**
<>	149:156823d33999	432	* @brief Receive an amount of data in blocking mode
<>	149:156823d33999	433	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	434	* the configuration information for SPI module.
<>	149:156823d33999	435	* @param pData: pointer to data buffer
<>	149:156823d33999	436	* @param Size: amount of data to be sent
<>	149:156823d33999	437	* @param Timeout: Timeout duration
<>	149:156823d33999	438	* @retval HAL status
<>	149:156823d33999	439	*/
<>	149:156823d33999	440	HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size, uint32_t Timeout)
<>	149:156823d33999	441	{
<>	149:156823d33999	442	__IO uint16_t tmpreg = 0;
<>	149:156823d33999	443
<>	149:156823d33999	444	if(hspi->State == HAL_SPI_STATE_READY)
<>	149:156823d33999	445	{
<>	149:156823d33999	446	if((pData == NULL ) \|\| (Size == 0))
<>	149:156823d33999	447	{
<>	149:156823d33999	448	return HAL_ERROR;
<>	149:156823d33999	449	}
<>	149:156823d33999	450
<>	149:156823d33999	451	/* Process Locked */
<>	149:156823d33999	452	__HAL_LOCK(hspi);
<>	149:156823d33999	453
<>	149:156823d33999	454	/* Configure communication */
<>	149:156823d33999	455	hspi->State = HAL_SPI_STATE_BUSY_RX;
<>	149:156823d33999	456	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<>	149:156823d33999	457
<>	149:156823d33999	458	hspi->pRxBuffPtr = pData;
<>	149:156823d33999	459	hspi->RxXferSize = Size;
<>	149:156823d33999	460	hspi->RxXferCount = Size;
<>	149:156823d33999	461
<>	149:156823d33999	462	/Init field not used in handle to zero /
<>	149:156823d33999	463	hspi->RxISR = 0;
<>	149:156823d33999	464	hspi->TxISR = 0;
<>	149:156823d33999	465	hspi->pTxBuffPtr = NULL;
<>	149:156823d33999	466	hspi->TxXferSize = 0;
<>	149:156823d33999	467	hspi->TxXferCount = 0;
<>	149:156823d33999	468
<>	149:156823d33999	469	/* Configure communication direction : 1Line */
<>	149:156823d33999	470	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
<>	149:156823d33999	471	{
<>	149:156823d33999	472	SPI_1LINE_RX(hspi);
<>	149:156823d33999	473	}
<>	149:156823d33999	474
<>	149:156823d33999	475	/* Reset CRC Calculation */
<>	149:156823d33999	476	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	149:156823d33999	477	{
<>	149:156823d33999	478	SPI_RESET_CRC(hspi);
<>	149:156823d33999	479	}
<>	149:156823d33999	480
<>	149:156823d33999	481	if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
<>	149:156823d33999	482	{
<>	149:156823d33999	483	/* Process Unlocked */
<>	149:156823d33999	484	__HAL_UNLOCK(hspi);
<>	149:156823d33999	485
<>	149:156823d33999	486	/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
<>	149:156823d33999	487	return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
<>	149:156823d33999	488	}
<>	149:156823d33999	489
<>	149:156823d33999	490	/* Check if the SPI is already enabled */
<>	149:156823d33999	491	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
<>	149:156823d33999	492	{
<>	149:156823d33999	493	/* Enable SPI peripheral */
<>	149:156823d33999	494	__HAL_SPI_ENABLE(hspi);
<>	149:156823d33999	495	}
<>	149:156823d33999	496
<>	149:156823d33999	497	/* Receive data in 8 Bit mode */
<>	149:156823d33999	498	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
<>	149:156823d33999	499	{
<>	149:156823d33999	500	while(hspi->RxXferCount > 1)
<>	149:156823d33999	501	{
<>	149:156823d33999	502	/* Wait until RXNE flag is set */
<>	149:156823d33999	503	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
<>	149:156823d33999	504	{
<>	149:156823d33999	505	return HAL_TIMEOUT;
<>	149:156823d33999	506	}
<>	149:156823d33999	507
<>	149:156823d33999	508	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
<>	149:156823d33999	509	hspi->RxXferCount--;
<>	149:156823d33999	510	}
<>	149:156823d33999	511	/* Enable CRC Transmission */
<>	149:156823d33999	512	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	149:156823d33999	513	{
<>	149:156823d33999	514	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<>	149:156823d33999	515	}
<>	149:156823d33999	516	}
<>	149:156823d33999	517	/* Receive data in 16 Bit mode */
<>	149:156823d33999	518	else
<>	149:156823d33999	519	{
<>	149:156823d33999	520	while(hspi->RxXferCount > 1)
<>	149:156823d33999	521	{
<>	149:156823d33999	522	/* Wait until RXNE flag is set to read data */
<>	149:156823d33999	523	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
<>	149:156823d33999	524	{
<>	149:156823d33999	525	return HAL_TIMEOUT;
<>	149:156823d33999	526	}
<>	149:156823d33999	527
<>	149:156823d33999	528	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
<>	149:156823d33999	529	hspi->pRxBuffPtr+=2;
<>	149:156823d33999	530	hspi->RxXferCount--;
<>	149:156823d33999	531	}
<>	149:156823d33999	532	/* Enable CRC Transmission */
<>	149:156823d33999	533	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	149:156823d33999	534	{
<>	149:156823d33999	535	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<>	149:156823d33999	536	}
<>	149:156823d33999	537	}
<>	149:156823d33999	538
<>	149:156823d33999	539	/* Wait until RXNE flag is set */
<>	149:156823d33999	540	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
<>	149:156823d33999	541	{
<>	149:156823d33999	542	return HAL_TIMEOUT;
<>	149:156823d33999	543	}
<>	149:156823d33999	544
<>	149:156823d33999	545	/* Receive last data in 8 Bit mode */
<>	149:156823d33999	546	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
<>	149:156823d33999	547	{
<>	149:156823d33999	548	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
<>	149:156823d33999	549	}
<>	149:156823d33999	550	/* Receive last data in 16 Bit mode */
<>	149:156823d33999	551	else
<>	149:156823d33999	552	{
<>	149:156823d33999	553	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
<>	149:156823d33999	554	hspi->pRxBuffPtr+=2;
<>	149:156823d33999	555	}
<>	149:156823d33999	556	hspi->RxXferCount--;
<>	149:156823d33999	557
<>	149:156823d33999	558	/* Wait until RXNE flag is set: CRC Received */
<>	149:156823d33999	559	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	149:156823d33999	560	{
<>	149:156823d33999	561	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
<>	149:156823d33999	562	{
<>	149:156823d33999	563	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<>	149:156823d33999	564	return HAL_TIMEOUT;
<>	149:156823d33999	565	}
<>	149:156823d33999	566
<>	149:156823d33999	567	/* Read CRC to Flush RXNE flag */
<>	149:156823d33999	568	tmpreg = hspi->Instance->DR;
<>	149:156823d33999	569	UNUSED(tmpreg);
<>	149:156823d33999	570	}
<>	149:156823d33999	571
<>	149:156823d33999	572	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
<>	149:156823d33999	573	{
<>	149:156823d33999	574	/* Disable SPI peripheral */
<>	149:156823d33999	575	__HAL_SPI_DISABLE(hspi);
<>	149:156823d33999	576	}
<>	149:156823d33999	577
<>	149:156823d33999	578	hspi->State = HAL_SPI_STATE_READY;
<>	149:156823d33999	579
<>	149:156823d33999	580	/* Check if CRC error occurred */
<>	149:156823d33999	581	if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET))
<>	149:156823d33999	582	{
<>	149:156823d33999	583	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<>	149:156823d33999	584
<>	149:156823d33999	585	/* Reset CRC Calculation */
<>	149:156823d33999	586	SPI_RESET_CRC(hspi);
<>	149:156823d33999	587
<>	149:156823d33999	588	/* Process Unlocked */
<>	149:156823d33999	589	__HAL_UNLOCK(hspi);
<>	149:156823d33999	590
<>	149:156823d33999	591	return HAL_ERROR;
<>	149:156823d33999	592	}
<>	149:156823d33999	593
<>	149:156823d33999	594	/* Process Unlocked */
<>	149:156823d33999	595	__HAL_UNLOCK(hspi);
<>	149:156823d33999	596
<>	149:156823d33999	597	return HAL_OK;
<>	149:156823d33999	598	}
<>	149:156823d33999	599	else
<>	149:156823d33999	600	{
<>	149:156823d33999	601	return HAL_BUSY;
<>	149:156823d33999	602	}
<>	149:156823d33999	603	}
<>	149:156823d33999	604
<>	149:156823d33999	605	/**
<>	149:156823d33999	606	* @brief Transmit and Receive an amount of data in blocking mode
<>	149:156823d33999	607	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	608	* the configuration information for SPI module.
<>	149:156823d33999	609	* @param pTxData: pointer to transmission data buffer
<>	149:156823d33999	610	* @param pRxData: pointer to reception data buffer to be
<>	149:156823d33999	611	* @param Size: amount of data to be sent
<>	149:156823d33999	612	* @param Timeout: Timeout duration
<>	149:156823d33999	613	* @retval HAL status
<>	149:156823d33999	614	*/
<>	149:156823d33999	615	HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
<>	149:156823d33999	616	{
<>	149:156823d33999	617	__IO uint16_t tmpreg = 0;
<>	149:156823d33999	618
<>	149:156823d33999	619	if((hspi->State == HAL_SPI_STATE_READY) \|\| (hspi->State == HAL_SPI_STATE_BUSY_RX))
<>	149:156823d33999	620	{
<>	149:156823d33999	621	if((pTxData == NULL ) \|\| (pRxData == NULL ) \|\| (Size == 0))
<>	149:156823d33999	622	{
<>	149:156823d33999	623	return HAL_ERROR;
<>	149:156823d33999	624	}
<>	149:156823d33999	625
<>	149:156823d33999	626	/* Check the parameters */
<>	149:156823d33999	627	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
<>	149:156823d33999	628
<>	149:156823d33999	629	/* Process Locked */
<>	149:156823d33999	630	__HAL_LOCK(hspi);
<>	149:156823d33999	631
<>	149:156823d33999	632	/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
<>	149:156823d33999	633	if(hspi->State == HAL_SPI_STATE_READY)
<>	149:156823d33999	634	{
<>	149:156823d33999	635	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
<>	149:156823d33999	636	}
<>	149:156823d33999	637
<>	149:156823d33999	638	/* Configure communication */
<>	149:156823d33999	639	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<>	149:156823d33999	640
<>	149:156823d33999	641	hspi->pRxBuffPtr = pRxData;
<>	149:156823d33999	642	hspi->RxXferSize = Size;
<>	149:156823d33999	643	hspi->RxXferCount = Size;
<>	149:156823d33999	644
<>	149:156823d33999	645	hspi->pTxBuffPtr = pTxData;
<>	149:156823d33999	646	hspi->TxXferSize = Size;
<>	149:156823d33999	647	hspi->TxXferCount = Size;
<>	149:156823d33999	648
<>	149:156823d33999	649	/Init field not used in handle to zero /
<>	149:156823d33999	650	hspi->RxISR = 0;
<>	149:156823d33999	651	hspi->TxISR = 0;
<>	149:156823d33999	652
<>	149:156823d33999	653	/* Reset CRC Calculation */
<>	149:156823d33999	654	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	149:156823d33999	655	{
<>	149:156823d33999	656	SPI_RESET_CRC(hspi);
<>	149:156823d33999	657	}
<>	149:156823d33999	658
<>	149:156823d33999	659	/* Check if the SPI is already enabled */
<>	149:156823d33999	660	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
<>	149:156823d33999	661	{
<>	149:156823d33999	662	/* Enable SPI peripheral */
<>	149:156823d33999	663	__HAL_SPI_ENABLE(hspi);
<>	149:156823d33999	664	}
<>	149:156823d33999	665
<>	149:156823d33999	666	/* Transmit and Receive data in 16 Bit mode */
<>	149:156823d33999	667	if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
<>	149:156823d33999	668	{
<>	149:156823d33999	669	if((hspi->Init.Mode == SPI_MODE_SLAVE) \|\| ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->TxXferCount == 0x01)))
<>	149:156823d33999	670	{
<>	149:156823d33999	671	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
<>	149:156823d33999	672	hspi->pTxBuffPtr+=2;
<>	149:156823d33999	673	hspi->TxXferCount--;
<>	149:156823d33999	674	}
<>	149:156823d33999	675	if(hspi->TxXferCount == 0)
<>	149:156823d33999	676	{
<>	149:156823d33999	677	/* Enable CRC Transmission */
<>	149:156823d33999	678	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	149:156823d33999	679	{
<>	149:156823d33999	680	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<>	149:156823d33999	681	}
<>	149:156823d33999	682
<>	149:156823d33999	683	/* Wait until RXNE flag is set */
<>	149:156823d33999	684	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
<>	149:156823d33999	685	{
<>	149:156823d33999	686	return HAL_TIMEOUT;
<>	149:156823d33999	687	}
<>	149:156823d33999	688
<>	149:156823d33999	689	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
<>	149:156823d33999	690	hspi->pRxBuffPtr+=2;
<>	149:156823d33999	691	hspi->RxXferCount--;
<>	149:156823d33999	692	}
<>	149:156823d33999	693	else
<>	149:156823d33999	694	{
<>	149:156823d33999	695	while(hspi->TxXferCount > 0)
<>	149:156823d33999	696	{
<>	149:156823d33999	697	/* Wait until TXE flag is set to send data */
<>	149:156823d33999	698	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
<>	149:156823d33999	699	{
<>	149:156823d33999	700	return HAL_TIMEOUT;
<>	149:156823d33999	701	}
<>	149:156823d33999	702
<>	149:156823d33999	703	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
<>	149:156823d33999	704	hspi->pTxBuffPtr+=2;
<>	149:156823d33999	705	hspi->TxXferCount--;
<>	149:156823d33999	706
<>	149:156823d33999	707	/* Enable CRC Transmission */
<>	149:156823d33999	708	if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
<>	149:156823d33999	709	{
<>	149:156823d33999	710	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<>	149:156823d33999	711	}
<>	149:156823d33999	712
<>	149:156823d33999	713	/* Wait until RXNE flag is set */
<>	149:156823d33999	714	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
<>	149:156823d33999	715	{
<>	149:156823d33999	716	return HAL_TIMEOUT;
<>	149:156823d33999	717	}
<>	149:156823d33999	718
<>	149:156823d33999	719	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
<>	149:156823d33999	720	hspi->pRxBuffPtr+=2;
<>	149:156823d33999	721	hspi->RxXferCount--;
<>	149:156823d33999	722	}
<>	149:156823d33999	723	/* Receive the last byte */
<>	149:156823d33999	724	if(hspi->Init.Mode == SPI_MODE_SLAVE)
<>	149:156823d33999	725	{
<>	149:156823d33999	726	/* Wait until RXNE flag is set */
<>	149:156823d33999	727	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
<>	149:156823d33999	728	{
<>	149:156823d33999	729	return HAL_TIMEOUT;
<>	149:156823d33999	730	}
<>	149:156823d33999	731
<>	149:156823d33999	732	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
<>	149:156823d33999	733	hspi->pRxBuffPtr+=2;
<>	149:156823d33999	734	hspi->RxXferCount--;
<>	149:156823d33999	735	}
<>	149:156823d33999	736	}
<>	149:156823d33999	737	}
<>	149:156823d33999	738	/* Transmit and Receive data in 8 Bit mode */
<>	149:156823d33999	739	else
<>	149:156823d33999	740	{
<>	149:156823d33999	741	if((hspi->Init.Mode == SPI_MODE_SLAVE) \|\| ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->TxXferCount == 0x01)))
<>	149:156823d33999	742	{
<>	149:156823d33999	743	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
<>	149:156823d33999	744	hspi->TxXferCount--;
<>	149:156823d33999	745	}
<>	149:156823d33999	746	if(hspi->TxXferCount == 0)
<>	149:156823d33999	747	{
<>	149:156823d33999	748	/* Enable CRC Transmission */
<>	149:156823d33999	749	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	149:156823d33999	750	{
<>	149:156823d33999	751	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<>	149:156823d33999	752	}
<>	149:156823d33999	753
<>	149:156823d33999	754	/* Wait until RXNE flag is set */
<>	149:156823d33999	755	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
<>	149:156823d33999	756	{
<>	149:156823d33999	757	return HAL_TIMEOUT;
<>	149:156823d33999	758	}
<>	149:156823d33999	759
<>	149:156823d33999	760	(*hspi->pRxBuffPtr) = hspi->Instance->DR;
<>	149:156823d33999	761	hspi->RxXferCount--;
<>	149:156823d33999	762	}
<>	149:156823d33999	763	else
<>	149:156823d33999	764	{
<>	149:156823d33999	765	while(hspi->TxXferCount > 0)
<>	149:156823d33999	766	{
<>	149:156823d33999	767	/* Wait until TXE flag is set to send data */
<>	149:156823d33999	768	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
<>	149:156823d33999	769	{
<>	149:156823d33999	770	return HAL_TIMEOUT;
<>	149:156823d33999	771	}
<>	149:156823d33999	772
<>	149:156823d33999	773	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
<>	149:156823d33999	774	hspi->TxXferCount--;
<>	149:156823d33999	775
<>	149:156823d33999	776	/* Enable CRC Transmission */
<>	149:156823d33999	777	if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
<>	149:156823d33999	778	{
<>	149:156823d33999	779	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<>	149:156823d33999	780	}
<>	149:156823d33999	781
<>	149:156823d33999	782	/* Wait until RXNE flag is set */
<>	149:156823d33999	783	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
<>	149:156823d33999	784	{
<>	149:156823d33999	785	return HAL_TIMEOUT;
<>	149:156823d33999	786	}
<>	149:156823d33999	787
<>	149:156823d33999	788	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
<>	149:156823d33999	789	hspi->RxXferCount--;
<>	149:156823d33999	790	}
<>	149:156823d33999	791	if(hspi->Init.Mode == SPI_MODE_SLAVE)
<>	149:156823d33999	792	{
<>	149:156823d33999	793	/* Wait until RXNE flag is set */
<>	149:156823d33999	794	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
<>	149:156823d33999	795	{
<>	149:156823d33999	796	return HAL_TIMEOUT;
<>	149:156823d33999	797	}
<>	149:156823d33999	798
<>	149:156823d33999	799	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
<>	149:156823d33999	800	hspi->RxXferCount--;
<>	149:156823d33999	801	}
<>	149:156823d33999	802	}
<>	149:156823d33999	803	}
<>	149:156823d33999	804
<>	149:156823d33999	805	/* Read CRC from DR to close CRC calculation process */
<>	149:156823d33999	806	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	149:156823d33999	807	{
<>	149:156823d33999	808	/* Wait until RXNE flag is set */
<>	149:156823d33999	809	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
<>	149:156823d33999	810	{
<>	149:156823d33999	811	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<>	149:156823d33999	812	return HAL_TIMEOUT;
<>	149:156823d33999	813	}
<>	149:156823d33999	814	/* Read CRC */
<>	149:156823d33999	815	tmpreg = hspi->Instance->DR;
<>	149:156823d33999	816	UNUSED(tmpreg);
<>	149:156823d33999	817	}
<>	149:156823d33999	818
<>	149:156823d33999	819	/* Wait until Busy flag is reset before disabling SPI */
<>	149:156823d33999	820	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, Timeout) != HAL_OK)
<>	149:156823d33999	821	{
<>	149:156823d33999	822	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<>	149:156823d33999	823	return HAL_TIMEOUT;
<>	149:156823d33999	824	}
<>	149:156823d33999	825
<>	149:156823d33999	826	hspi->State = HAL_SPI_STATE_READY;
<>	149:156823d33999	827
<>	149:156823d33999	828	/* Check if CRC error occurred */
<>	149:156823d33999	829	if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET))
<>	149:156823d33999	830	{
<>	149:156823d33999	831	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<>	149:156823d33999	832
<>	149:156823d33999	833	/* Reset CRC Calculation */
<>	149:156823d33999	834	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	149:156823d33999	835	{
<>	149:156823d33999	836	SPI_RESET_CRC(hspi);
<>	149:156823d33999	837	}
<>	149:156823d33999	838
<>	149:156823d33999	839	/* Process Unlocked */
<>	149:156823d33999	840	__HAL_UNLOCK(hspi);
<>	149:156823d33999	841
<>	149:156823d33999	842	return HAL_ERROR;
<>	149:156823d33999	843	}
<>	149:156823d33999	844
<>	149:156823d33999	845	/* Process Unlocked */
<>	149:156823d33999	846	__HAL_UNLOCK(hspi);
<>	149:156823d33999	847
<>	149:156823d33999	848	return HAL_OK;
<>	149:156823d33999	849	}
<>	149:156823d33999	850	else
<>	149:156823d33999	851	{
<>	149:156823d33999	852	return HAL_BUSY;
<>	149:156823d33999	853	}
<>	149:156823d33999	854	}
<>	149:156823d33999	855
<>	149:156823d33999	856	/**
<>	149:156823d33999	857	* @brief Transmit an amount of data in no-blocking mode with Interrupt
<>	149:156823d33999	858	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	859	* the configuration information for SPI module.
<>	149:156823d33999	860	* @param pData: pointer to data buffer
<>	149:156823d33999	861	* @param Size: amount of data to be sent
<>	149:156823d33999	862	* @retval HAL status
<>	149:156823d33999	863	*/
<>	149:156823d33999	864	HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
<>	149:156823d33999	865	{
<>	149:156823d33999	866	if(hspi->State == HAL_SPI_STATE_READY)
<>	149:156823d33999	867	{
<>	149:156823d33999	868	if((pData == NULL) \|\| (Size == 0))
<>	149:156823d33999	869	{
<>	149:156823d33999	870	return HAL_ERROR;
<>	149:156823d33999	871	}
<>	149:156823d33999	872
<>	149:156823d33999	873	/* Check the parameters */
<>	149:156823d33999	874	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
<>	149:156823d33999	875
<>	149:156823d33999	876	/* Process Locked */
<>	149:156823d33999	877	__HAL_LOCK(hspi);
<>	149:156823d33999	878
<>	149:156823d33999	879	/* Configure communication */
<>	149:156823d33999	880	hspi->State = HAL_SPI_STATE_BUSY_TX;
<>	149:156823d33999	881	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<>	149:156823d33999	882
<>	149:156823d33999	883	hspi->TxISR = &SPI_TxISR;
<>	149:156823d33999	884	hspi->pTxBuffPtr = pData;
<>	149:156823d33999	885	hspi->TxXferSize = Size;
<>	149:156823d33999	886	hspi->TxXferCount = Size;
<>	149:156823d33999	887
<>	149:156823d33999	888	/Init field not used in handle to zero /
<>	149:156823d33999	889	hspi->RxISR = 0;
<>	149:156823d33999	890	hspi->pRxBuffPtr = NULL;
<>	149:156823d33999	891	hspi->RxXferSize = 0;
<>	149:156823d33999	892	hspi->RxXferCount = 0;
<>	149:156823d33999	893
<>	149:156823d33999	894	/* Configure communication direction : 1Line */
<>	149:156823d33999	895	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
<>	149:156823d33999	896	{
<>	149:156823d33999	897	SPI_1LINE_TX(hspi);
<>	149:156823d33999	898	}
<>	149:156823d33999	899
<>	149:156823d33999	900	/* Reset CRC Calculation */
<>	149:156823d33999	901	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	149:156823d33999	902	{
<>	149:156823d33999	903	SPI_RESET_CRC(hspi);
<>	149:156823d33999	904	}
<>	149:156823d33999	905
<>	149:156823d33999	906	if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
<>	149:156823d33999	907	{
<>	149:156823d33999	908	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE));
<>	149:156823d33999	909	}else
<>	149:156823d33999	910	{
<>	149:156823d33999	911	/* Enable TXE and ERR interrupt */
<>	149:156823d33999	912	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_ERR));
<>	149:156823d33999	913	}
<>	149:156823d33999	914	/* Process Unlocked */
<>	149:156823d33999	915	__HAL_UNLOCK(hspi);
<>	149:156823d33999	916
<>	149:156823d33999	917	/* Check if the SPI is already enabled */
<>	149:156823d33999	918	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
<>	149:156823d33999	919	{
<>	149:156823d33999	920	/* Enable SPI peripheral */
<>	149:156823d33999	921	__HAL_SPI_ENABLE(hspi);
<>	149:156823d33999	922	}
<>	149:156823d33999	923
<>	149:156823d33999	924	return HAL_OK;
<>	149:156823d33999	925	}
<>	149:156823d33999	926	else
<>	149:156823d33999	927	{
<>	149:156823d33999	928	return HAL_BUSY;
<>	149:156823d33999	929	}
<>	149:156823d33999	930	}
<>	149:156823d33999	931
<>	149:156823d33999	932	/**
<>	149:156823d33999	933	* @brief Receive an amount of data in no-blocking mode with Interrupt
<>	149:156823d33999	934	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	935	* the configuration information for SPI module.
<>	149:156823d33999	936	* @param pData: pointer to data buffer
<>	149:156823d33999	937	* @param Size: amount of data to be sent
<>	149:156823d33999	938	* @retval HAL status
<>	149:156823d33999	939	*/
<>	149:156823d33999	940	HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
<>	149:156823d33999	941	{
<>	149:156823d33999	942	if(hspi->State == HAL_SPI_STATE_READY)
<>	149:156823d33999	943	{
<>	149:156823d33999	944	if((pData == NULL) \|\| (Size == 0))
<>	149:156823d33999	945	{
<>	149:156823d33999	946	return HAL_ERROR;
<>	149:156823d33999	947	}
<>	149:156823d33999	948
<>	149:156823d33999	949	/* Process Locked */
<>	149:156823d33999	950	__HAL_LOCK(hspi);
<>	149:156823d33999	951
<>	149:156823d33999	952	/* Configure communication */
<>	149:156823d33999	953	hspi->State = HAL_SPI_STATE_BUSY_RX;
<>	149:156823d33999	954	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<>	149:156823d33999	955
<>	149:156823d33999	956	hspi->RxISR = &SPI_RxISR;
<>	149:156823d33999	957	hspi->pRxBuffPtr = pData;
<>	149:156823d33999	958	hspi->RxXferSize = Size;
<>	149:156823d33999	959	hspi->RxXferCount = Size ;
<>	149:156823d33999	960
<>	149:156823d33999	961	/Init field not used in handle to zero /
<>	149:156823d33999	962	hspi->TxISR = 0;
<>	149:156823d33999	963	hspi->pTxBuffPtr = NULL;
<>	149:156823d33999	964	hspi->TxXferSize = 0;
<>	149:156823d33999	965	hspi->TxXferCount = 0;
<>	149:156823d33999	966
<>	149:156823d33999	967	/* Configure communication direction : 1Line */
<>	149:156823d33999	968	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
<>	149:156823d33999	969	{
<>	149:156823d33999	970	SPI_1LINE_RX(hspi);
<>	149:156823d33999	971	}
<>	149:156823d33999	972	else if((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
<>	149:156823d33999	973	{
<>	149:156823d33999	974	/* Process Unlocked */
<>	149:156823d33999	975	__HAL_UNLOCK(hspi);
<>	149:156823d33999	976
<>	149:156823d33999	977	/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
<>	149:156823d33999	978	return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
<>	149:156823d33999	979	}
<>	149:156823d33999	980
<>	149:156823d33999	981	/* Reset CRC Calculation */
<>	149:156823d33999	982	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	149:156823d33999	983	{
<>	149:156823d33999	984	SPI_RESET_CRC(hspi);
<>	149:156823d33999	985	}
<>	149:156823d33999	986
<>	149:156823d33999	987	/* Enable TXE and ERR interrupt */
<>	149:156823d33999	988	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
<>	149:156823d33999	989
<>	149:156823d33999	990	/* Process Unlocked */
<>	149:156823d33999	991	__HAL_UNLOCK(hspi);
<>	149:156823d33999	992
<>	149:156823d33999	993	/* Note : The SPI must be enabled after unlocking current process
<>	149:156823d33999	994	to avoid the risk of SPI interrupt handle execution before current
<>	149:156823d33999	995	process unlock */
<>	149:156823d33999	996
<>	149:156823d33999	997	/* Check if the SPI is already enabled */
<>	149:156823d33999	998	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
<>	149:156823d33999	999	{
<>	149:156823d33999	1000	/* Enable SPI peripheral */
<>	149:156823d33999	1001	__HAL_SPI_ENABLE(hspi);
<>	149:156823d33999	1002	}
<>	149:156823d33999	1003
<>	149:156823d33999	1004	return HAL_OK;
<>	149:156823d33999	1005	}
<>	149:156823d33999	1006	else
<>	149:156823d33999	1007	{
<>	149:156823d33999	1008	return HAL_BUSY;
<>	149:156823d33999	1009	}
<>	149:156823d33999	1010	}
<>	149:156823d33999	1011
<>	149:156823d33999	1012	/**
<>	149:156823d33999	1013	* @brief Transmit and Receive an amount of data in no-blocking mode with Interrupt
<>	149:156823d33999	1014	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	1015	* the configuration information for SPI module.
<>	149:156823d33999	1016	* @param pTxData: pointer to transmission data buffer
<>	149:156823d33999	1017	* @param pRxData: pointer to reception data buffer to be
<>	149:156823d33999	1018	* @param Size: amount of data to be sent
<>	149:156823d33999	1019	* @retval HAL status
<>	149:156823d33999	1020	*/
<>	149:156823d33999	1021	HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size)
<>	149:156823d33999	1022	{
<>	149:156823d33999	1023
<>	149:156823d33999	1024	if((hspi->State == HAL_SPI_STATE_READY) \|\| \
<>	149:156823d33999	1025	((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX)))
<>	149:156823d33999	1026	{
<>	149:156823d33999	1027	if((pTxData == NULL ) \|\| (pRxData == NULL ) \|\| (Size == 0))
<>	149:156823d33999	1028	{
<>	149:156823d33999	1029	return HAL_ERROR;
<>	149:156823d33999	1030	}
<>	149:156823d33999	1031
<>	149:156823d33999	1032	/* Check the parameters */
<>	149:156823d33999	1033	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
<>	149:156823d33999	1034
<>	149:156823d33999	1035	/* Process locked */
<>	149:156823d33999	1036	__HAL_LOCK(hspi);
<>	149:156823d33999	1037
<>	149:156823d33999	1038	/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
<>	149:156823d33999	1039	if(hspi->State != HAL_SPI_STATE_BUSY_RX)
<>	149:156823d33999	1040	{
<>	149:156823d33999	1041	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
<>	149:156823d33999	1042	}
<>	149:156823d33999	1043
<>	149:156823d33999	1044	/* Configure communication */
<>	149:156823d33999	1045	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<>	149:156823d33999	1046
<>	149:156823d33999	1047	hspi->TxISR = &SPI_TxISR;
<>	149:156823d33999	1048	hspi->pTxBuffPtr = pTxData;
<>	149:156823d33999	1049	hspi->TxXferSize = Size;
<>	149:156823d33999	1050	hspi->TxXferCount = Size;
<>	149:156823d33999	1051
<>	149:156823d33999	1052	hspi->RxISR = &SPI_2LinesRxISR;
<>	149:156823d33999	1053	hspi->pRxBuffPtr = pRxData;
<>	149:156823d33999	1054	hspi->RxXferSize = Size;
<>	149:156823d33999	1055	hspi->RxXferCount = Size;
<>	149:156823d33999	1056
<>	149:156823d33999	1057	/* Reset CRC Calculation */
<>	149:156823d33999	1058	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	149:156823d33999	1059	{
<>	149:156823d33999	1060	SPI_RESET_CRC(hspi);
<>	149:156823d33999	1061	}
<>	149:156823d33999	1062
<>	149:156823d33999	1063	/* Enable TXE, RXNE and ERR interrupt */
<>	149:156823d33999	1064	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
<>	149:156823d33999	1065
<>	149:156823d33999	1066	/* Process Unlocked */
<>	149:156823d33999	1067	__HAL_UNLOCK(hspi);
<>	149:156823d33999	1068
<>	149:156823d33999	1069	/* Check if the SPI is already enabled */
<>	149:156823d33999	1070	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
<>	149:156823d33999	1071	{
<>	149:156823d33999	1072	/* Enable SPI peripheral */
<>	149:156823d33999	1073	__HAL_SPI_ENABLE(hspi);
<>	149:156823d33999	1074	}
<>	149:156823d33999	1075
<>	149:156823d33999	1076	return HAL_OK;
<>	149:156823d33999	1077	}
<>	149:156823d33999	1078	else
<>	149:156823d33999	1079	{
<>	149:156823d33999	1080	return HAL_BUSY;
<>	149:156823d33999	1081	}
<>	149:156823d33999	1082	}
<>	149:156823d33999	1083
<>	149:156823d33999	1084	/**
<>	149:156823d33999	1085	* @brief Transmit an amount of data in no-blocking mode with DMA
<>	149:156823d33999	1086	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	1087	* the configuration information for SPI module.
<>	149:156823d33999	1088	* @param pData: pointer to data buffer
<>	149:156823d33999	1089	* @param Size: amount of data to be sent
<>	149:156823d33999	1090	* @retval HAL status
<>	149:156823d33999	1091	*/
<>	149:156823d33999	1092	HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
<>	149:156823d33999	1093	{
<>	149:156823d33999	1094	if(hspi->State == HAL_SPI_STATE_READY)
<>	149:156823d33999	1095	{
<>	149:156823d33999	1096	if((pData == NULL) \|\| (Size == 0))
<>	149:156823d33999	1097	{
<>	149:156823d33999	1098	return HAL_ERROR;
<>	149:156823d33999	1099	}
<>	149:156823d33999	1100
<>	149:156823d33999	1101	/* Check the parameters */
<>	149:156823d33999	1102	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
<>	149:156823d33999	1103
<>	149:156823d33999	1104	/* Process Locked */
<>	149:156823d33999	1105	__HAL_LOCK(hspi);
<>	149:156823d33999	1106
<>	149:156823d33999	1107	/* Configure communication */
<>	149:156823d33999	1108	hspi->State = HAL_SPI_STATE_BUSY_TX;
<>	149:156823d33999	1109	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<>	149:156823d33999	1110
<>	149:156823d33999	1111	hspi->pTxBuffPtr = pData;
<>	149:156823d33999	1112	hspi->TxXferSize = Size;
<>	149:156823d33999	1113	hspi->TxXferCount = Size;
<>	149:156823d33999	1114
<>	149:156823d33999	1115	/Init field not used in handle to zero /
<>	149:156823d33999	1116	hspi->TxISR = 0;
<>	149:156823d33999	1117	hspi->RxISR = 0;
<>	149:156823d33999	1118	hspi->pRxBuffPtr = NULL;
<>	149:156823d33999	1119	hspi->RxXferSize = 0;
<>	149:156823d33999	1120	hspi->RxXferCount = 0;
<>	149:156823d33999	1121
<>	149:156823d33999	1122	/* Configure communication direction : 1Line */
<>	149:156823d33999	1123	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
<>	149:156823d33999	1124	{
<>	149:156823d33999	1125	SPI_1LINE_TX(hspi);
<>	149:156823d33999	1126	}
<>	149:156823d33999	1127
<>	149:156823d33999	1128	/* Reset CRC Calculation */
<>	149:156823d33999	1129	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	149:156823d33999	1130	{
<>	149:156823d33999	1131	SPI_RESET_CRC(hspi);
<>	149:156823d33999	1132	}
<>	149:156823d33999	1133
<>	149:156823d33999	1134	/* Set the SPI TxDMA Half transfer complete callback */
<>	149:156823d33999	1135	hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
<>	149:156823d33999	1136
<>	149:156823d33999	1137	/* Set the SPI TxDMA transfer complete callback */
<>	149:156823d33999	1138	hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
<>	149:156823d33999	1139
<>	149:156823d33999	1140	/* Set the DMA error callback */
<>	149:156823d33999	1141	hspi->hdmatx->XferErrorCallback = SPI_DMAError;
<>	149:156823d33999	1142
<>	149:156823d33999	1143	/* Enable the Tx DMA Channel */
<>	149:156823d33999	1144	HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
<>	149:156823d33999	1145
<>	149:156823d33999	1146	/* Enable Tx DMA Request */
<>	149:156823d33999	1147	SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
<>	149:156823d33999	1148
<>	149:156823d33999	1149	/* Process Unlocked */
<>	149:156823d33999	1150	__HAL_UNLOCK(hspi);
<>	149:156823d33999	1151
<>	149:156823d33999	1152	/* Check if the SPI is already enabled */
<>	149:156823d33999	1153	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
<>	149:156823d33999	1154	{
<>	149:156823d33999	1155	/* Enable SPI peripheral */
<>	149:156823d33999	1156	__HAL_SPI_ENABLE(hspi);
<>	149:156823d33999	1157	}
<>	149:156823d33999	1158
<>	149:156823d33999	1159	return HAL_OK;
<>	149:156823d33999	1160	}
<>	149:156823d33999	1161	else
<>	149:156823d33999	1162	{
<>	149:156823d33999	1163	return HAL_BUSY;
<>	149:156823d33999	1164	}
<>	149:156823d33999	1165	}
<>	149:156823d33999	1166
<>	149:156823d33999	1167	/**
<>	149:156823d33999	1168	* @brief Receive an amount of data in no-blocking mode with DMA
<>	149:156823d33999	1169	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	1170	* the configuration information for SPI module.
<>	149:156823d33999	1171	* @param pData: pointer to data buffer
<>	149:156823d33999	1172	* @note When the CRC feature is enabled the pData Length must be Size + 1.
<>	149:156823d33999	1173	* @param Size: amount of data to be sent
<>	149:156823d33999	1174	* @retval HAL status
<>	149:156823d33999	1175	*/
<>	149:156823d33999	1176	HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
<>	149:156823d33999	1177	{
<>	149:156823d33999	1178	if(hspi->State == HAL_SPI_STATE_READY)
<>	149:156823d33999	1179	{
<>	149:156823d33999	1180	if((pData == NULL) \|\| (Size == 0))
<>	149:156823d33999	1181	{
<>	149:156823d33999	1182	return HAL_ERROR;
<>	149:156823d33999	1183	}
<>	149:156823d33999	1184
<>	149:156823d33999	1185	/* Process Locked */
<>	149:156823d33999	1186	__HAL_LOCK(hspi);
<>	149:156823d33999	1187
<>	149:156823d33999	1188	/* Configure communication */
<>	149:156823d33999	1189	hspi->State = HAL_SPI_STATE_BUSY_RX;
<>	149:156823d33999	1190	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<>	149:156823d33999	1191
<>	149:156823d33999	1192	hspi->pRxBuffPtr = pData;
<>	149:156823d33999	1193	hspi->RxXferSize = Size;
<>	149:156823d33999	1194	hspi->RxXferCount = Size;
<>	149:156823d33999	1195
<>	149:156823d33999	1196	/Init field not used in handle to zero /
<>	149:156823d33999	1197	hspi->RxISR = 0;
<>	149:156823d33999	1198	hspi->TxISR = 0;
<>	149:156823d33999	1199	hspi->pTxBuffPtr = NULL;
<>	149:156823d33999	1200	hspi->TxXferSize = 0;
<>	149:156823d33999	1201	hspi->TxXferCount = 0;
<>	149:156823d33999	1202
<>	149:156823d33999	1203	/* Configure communication direction : 1Line */
<>	149:156823d33999	1204	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
<>	149:156823d33999	1205	{
<>	149:156823d33999	1206	SPI_1LINE_RX(hspi);
<>	149:156823d33999	1207	}
<>	149:156823d33999	1208	else if((hspi->Init.Direction == SPI_DIRECTION_2LINES)&&(hspi->Init.Mode == SPI_MODE_MASTER))
<>	149:156823d33999	1209	{
<>	149:156823d33999	1210	/* Process Unlocked */
<>	149:156823d33999	1211	__HAL_UNLOCK(hspi);
<>	149:156823d33999	1212
<>	149:156823d33999	1213	/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
<>	149:156823d33999	1214	return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
<>	149:156823d33999	1215	}
<>	149:156823d33999	1216
<>	149:156823d33999	1217	/* Reset CRC Calculation */
<>	149:156823d33999	1218	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	149:156823d33999	1219	{
<>	149:156823d33999	1220	SPI_RESET_CRC(hspi);
<>	149:156823d33999	1221	}
<>	149:156823d33999	1222
<>	149:156823d33999	1223	/* Set the SPI RxDMA Half transfer complete callback */
<>	149:156823d33999	1224	hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
<>	149:156823d33999	1225
<>	149:156823d33999	1226	/* Set the SPI Rx DMA transfer complete callback */
<>	149:156823d33999	1227	hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
<>	149:156823d33999	1228
<>	149:156823d33999	1229	/* Set the DMA error callback */
<>	149:156823d33999	1230	hspi->hdmarx->XferErrorCallback = SPI_DMAError;
<>	149:156823d33999	1231
<>	149:156823d33999	1232	/* Enable the Rx DMA Channel */
<>	149:156823d33999	1233	HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
<>	149:156823d33999	1234
<>	149:156823d33999	1235	/* Enable Rx DMA Request */
<>	149:156823d33999	1236	SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
<>	149:156823d33999	1237
<>	149:156823d33999	1238	/* Process Unlocked */
<>	149:156823d33999	1239	__HAL_UNLOCK(hspi);
<>	149:156823d33999	1240
<>	149:156823d33999	1241	/* Check if the SPI is already enabled */
<>	149:156823d33999	1242	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
<>	149:156823d33999	1243	{
<>	149:156823d33999	1244	/* Enable SPI peripheral */
<>	149:156823d33999	1245	__HAL_SPI_ENABLE(hspi);
<>	149:156823d33999	1246	}
<>	149:156823d33999	1247
<>	149:156823d33999	1248	return HAL_OK;
<>	149:156823d33999	1249	}
<>	149:156823d33999	1250	else
<>	149:156823d33999	1251	{
<>	149:156823d33999	1252	return HAL_BUSY;
<>	149:156823d33999	1253	}
<>	149:156823d33999	1254	}
<>	149:156823d33999	1255
<>	149:156823d33999	1256	/**
<>	149:156823d33999	1257	* @brief Transmit and Receive an amount of data in no-blocking mode with DMA
<>	149:156823d33999	1258	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	1259	* the configuration information for SPI module.
<>	149:156823d33999	1260	* @param pTxData: pointer to transmission data buffer
<>	149:156823d33999	1261	* @param pRxData: pointer to reception data buffer
<>	149:156823d33999	1262	* @note When the CRC feature is enabled the pRxData Length must be Size + 1
<>	149:156823d33999	1263	* @param Size: amount of data to be sent
<>	149:156823d33999	1264	* @retval HAL status
<>	149:156823d33999	1265	*/
<>	149:156823d33999	1266	HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size)
<>	149:156823d33999	1267	{
<>	149:156823d33999	1268	if((hspi->State == HAL_SPI_STATE_READY) \|\| \
<>	149:156823d33999	1269	((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX)))
<>	149:156823d33999	1270	{
<>	149:156823d33999	1271	if((pTxData == NULL ) \|\| (pRxData == NULL ) \|\| (Size == 0))
<>	149:156823d33999	1272	{
<>	149:156823d33999	1273	return HAL_ERROR;
<>	149:156823d33999	1274	}
<>	149:156823d33999	1275
<>	149:156823d33999	1276	/* Check the parameters */
<>	149:156823d33999	1277	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
<>	149:156823d33999	1278
<>	149:156823d33999	1279	/* Process locked */
<>	149:156823d33999	1280	__HAL_LOCK(hspi);
<>	149:156823d33999	1281
<>	149:156823d33999	1282	/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
<>	149:156823d33999	1283	if(hspi->State != HAL_SPI_STATE_BUSY_RX)
<>	149:156823d33999	1284	{
<>	149:156823d33999	1285	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
<>	149:156823d33999	1286	}
<>	149:156823d33999	1287
<>	149:156823d33999	1288	/* Configure communication */
<>	149:156823d33999	1289	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<>	149:156823d33999	1290
<>	149:156823d33999	1291	hspi->pTxBuffPtr = (uint8_t*)pTxData;
<>	149:156823d33999	1292	hspi->TxXferSize = Size;
<>	149:156823d33999	1293	hspi->TxXferCount = Size;
<>	149:156823d33999	1294
<>	149:156823d33999	1295	hspi->pRxBuffPtr = (uint8_t*)pRxData;
<>	149:156823d33999	1296	hspi->RxXferSize = Size;
<>	149:156823d33999	1297	hspi->RxXferCount = Size;
<>	149:156823d33999	1298
<>	149:156823d33999	1299	/Init field not used in handle to zero /
<>	149:156823d33999	1300	hspi->RxISR = 0;
<>	149:156823d33999	1301	hspi->TxISR = 0;
<>	149:156823d33999	1302
<>	149:156823d33999	1303	/* Reset CRC Calculation */
<>	149:156823d33999	1304	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	149:156823d33999	1305	{
<>	149:156823d33999	1306	SPI_RESET_CRC(hspi);
<>	149:156823d33999	1307	}
<>	149:156823d33999	1308
<>	149:156823d33999	1309	/* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
<>	149:156823d33999	1310	if(hspi->State == HAL_SPI_STATE_BUSY_RX)
<>	149:156823d33999	1311	{
<>	149:156823d33999	1312	/* Set the SPI Rx DMA Half transfer complete callback */
<>	149:156823d33999	1313	hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
<>	149:156823d33999	1314
<>	149:156823d33999	1315	hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
<>	149:156823d33999	1316	}
<>	149:156823d33999	1317	else
<>	149:156823d33999	1318	{
<>	149:156823d33999	1319	/* Set the SPI Tx/Rx DMA Half transfer complete callback */
<>	149:156823d33999	1320	hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
<>	149:156823d33999	1321
<>	149:156823d33999	1322	hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
<>	149:156823d33999	1323	}
<>	149:156823d33999	1324
<>	149:156823d33999	1325	/* Set the DMA error callback */
<>	149:156823d33999	1326	hspi->hdmarx->XferErrorCallback = SPI_DMAError;
<>	149:156823d33999	1327
<>	149:156823d33999	1328	/* Enable the Rx DMA Channel */
<>	149:156823d33999	1329	HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
<>	149:156823d33999	1330
<>	149:156823d33999	1331	/* Enable Rx DMA Request */
<>	149:156823d33999	1332	SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
<>	149:156823d33999	1333
<>	149:156823d33999	1334	/* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
<>	149:156823d33999	1335	is performed in DMA reception complete callback */
<>	149:156823d33999	1336	if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX)
<>	149:156823d33999	1337	{
<>	149:156823d33999	1338	/* Set the DMA error callback */
<>	149:156823d33999	1339	hspi->hdmatx->XferErrorCallback = SPI_DMAError;
<>	149:156823d33999	1340	}
<>	149:156823d33999	1341	else
<>	149:156823d33999	1342	{
<>	149:156823d33999	1343	hspi->hdmatx->XferErrorCallback = NULL;
<>	149:156823d33999	1344	}
<>	149:156823d33999	1345
<>	149:156823d33999	1346	/* Enable the Tx DMA Channel */
<>	149:156823d33999	1347	HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
<>	149:156823d33999	1348
<>	149:156823d33999	1349	/* Check if the SPI is already enabled */
<>	149:156823d33999	1350	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
<>	149:156823d33999	1351	{
<>	149:156823d33999	1352	/* Enable SPI peripheral */
<>	149:156823d33999	1353	__HAL_SPI_ENABLE(hspi);
<>	149:156823d33999	1354	}
<>	149:156823d33999	1355
<>	149:156823d33999	1356	/* Enable Tx DMA Request */
<>	149:156823d33999	1357	SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
<>	149:156823d33999	1358
<>	149:156823d33999	1359	/* Process Unlocked */
<>	149:156823d33999	1360	__HAL_UNLOCK(hspi);
<>	149:156823d33999	1361
<>	149:156823d33999	1362	return HAL_OK;
<>	149:156823d33999	1363	}
<>	149:156823d33999	1364	else
<>	149:156823d33999	1365	{
<>	149:156823d33999	1366	return HAL_BUSY;
<>	149:156823d33999	1367	}
<>	149:156823d33999	1368	}
<>	149:156823d33999	1369
<>	149:156823d33999	1370
<>	149:156823d33999	1371	/**
<>	149:156823d33999	1372	* @brief Pauses the DMA Transfer.
<>	149:156823d33999	1373	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	1374	* the configuration information for the specified SPI module.
<>	149:156823d33999	1375	* @retval HAL status
<>	149:156823d33999	1376	*/
<>	149:156823d33999	1377	HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
<>	149:156823d33999	1378	{
<>	149:156823d33999	1379	/* Process Locked */
<>	149:156823d33999	1380	__HAL_LOCK(hspi);
<>	149:156823d33999	1381
<>	149:156823d33999	1382	/* Disable the SPI DMA Tx & Rx requests */
<>	149:156823d33999	1383	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
<>	149:156823d33999	1384	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
<>	149:156823d33999	1385
<>	149:156823d33999	1386	/* Process Unlocked */
<>	149:156823d33999	1387	__HAL_UNLOCK(hspi);
<>	149:156823d33999	1388
<>	149:156823d33999	1389	return HAL_OK;
<>	149:156823d33999	1390	}
<>	149:156823d33999	1391
<>	149:156823d33999	1392	/**
<>	149:156823d33999	1393	* @brief Resumes the DMA Transfer.
<>	149:156823d33999	1394	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	1395	* the configuration information for the specified SPI module.
<>	149:156823d33999	1396	* @retval HAL status
<>	149:156823d33999	1397	*/
<>	149:156823d33999	1398	HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
<>	149:156823d33999	1399	{
<>	149:156823d33999	1400	/* Process Locked */
<>	149:156823d33999	1401	__HAL_LOCK(hspi);
<>	149:156823d33999	1402
<>	149:156823d33999	1403	/* Enable the SPI DMA Tx & Rx requests */
<>	149:156823d33999	1404	SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
<>	149:156823d33999	1405	SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
<>	149:156823d33999	1406
<>	149:156823d33999	1407	/* Process Unlocked */
<>	149:156823d33999	1408	__HAL_UNLOCK(hspi);
<>	149:156823d33999	1409
<>	149:156823d33999	1410	return HAL_OK;
<>	149:156823d33999	1411	}
<>	149:156823d33999	1412
<>	149:156823d33999	1413	/**
<>	149:156823d33999	1414	* @brief Stops the DMA Transfer.
<>	149:156823d33999	1415	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	1416	* the configuration information for the specified UART module.
<>	149:156823d33999	1417	* @retval HAL status
<>	149:156823d33999	1418	*/
<>	149:156823d33999	1419	HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
<>	149:156823d33999	1420	{
<>	149:156823d33999	1421	/* The Lock is not implemented on this API to allow the user application
<>	149:156823d33999	1422	to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
<>	149:156823d33999	1423	when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
<>	149:156823d33999	1424	and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
<>	149:156823d33999	1425	*/
<>	149:156823d33999	1426
<>	149:156823d33999	1427	/* Abort the SPI DMA tx Channel */
<>	149:156823d33999	1428	if(hspi->hdmatx != NULL)
<>	149:156823d33999	1429	{
<>	149:156823d33999	1430	HAL_DMA_Abort(hspi->hdmatx);
<>	149:156823d33999	1431	}
<>	149:156823d33999	1432	/* Abort the SPI DMA rx Channel */
<>	149:156823d33999	1433	if(hspi->hdmarx != NULL)
<>	149:156823d33999	1434	{
<>	149:156823d33999	1435	HAL_DMA_Abort(hspi->hdmarx);
<>	149:156823d33999	1436	}
<>	149:156823d33999	1437
<>	149:156823d33999	1438	/* Disable the SPI DMA Tx & Rx requests */
<>	149:156823d33999	1439	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
<>	149:156823d33999	1440	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
<>	149:156823d33999	1441
<>	149:156823d33999	1442	hspi->State = HAL_SPI_STATE_READY;
<>	149:156823d33999	1443
<>	149:156823d33999	1444	return HAL_OK;
<>	149:156823d33999	1445	}
<>	149:156823d33999	1446
<>	149:156823d33999	1447	/**
<>	149:156823d33999	1448	* @brief This function handles SPI interrupt request.
<>	149:156823d33999	1449	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	1450	* the configuration information for SPI module.
<>	149:156823d33999	1451	* @retval HAL status
<>	149:156823d33999	1452	*/
<>	149:156823d33999	1453	void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
<>	149:156823d33999	1454	{
<>	149:156823d33999	1455	/* SPI in mode Receiver and Overrun not occurred ---------------------------*/
<>	149:156823d33999	1456	if((__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) == RESET))
<>	149:156823d33999	1457	{
<>	149:156823d33999	1458	hspi->RxISR(hspi);
<>	149:156823d33999	1459	return;
<>	149:156823d33999	1460	}
<>	149:156823d33999	1461
<>	149:156823d33999	1462	/* SPI in mode Tramitter ---------------------------------------------------*/
<>	149:156823d33999	1463	if((__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE) != RESET))
<>	149:156823d33999	1464	{
<>	149:156823d33999	1465	hspi->TxISR(hspi);
<>	149:156823d33999	1466	return;
<>	149:156823d33999	1467	}
<>	149:156823d33999	1468
<>	149:156823d33999	1469	if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_ERR) != RESET)
<>	149:156823d33999	1470	{
<>	149:156823d33999	1471	/* SPI CRC error interrupt occurred ---------------------------------------*/
<>	149:156823d33999	1472	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
<>	149:156823d33999	1473	{
<>	149:156823d33999	1474	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<>	149:156823d33999	1475	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
<>	149:156823d33999	1476	}
<>	149:156823d33999	1477	/* SPI Mode Fault error interrupt occurred --------------------------------*/
<>	149:156823d33999	1478	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_MODF) != RESET)
<>	149:156823d33999	1479	{
<>	149:156823d33999	1480	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
<>	149:156823d33999	1481	__HAL_SPI_CLEAR_MODFFLAG(hspi);
<>	149:156823d33999	1482	}
<>	149:156823d33999	1483
<>	149:156823d33999	1484	/* SPI Overrun error interrupt occurred -----------------------------------*/
<>	149:156823d33999	1485	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) != RESET)
<>	149:156823d33999	1486	{
<>	149:156823d33999	1487	if(hspi->State != HAL_SPI_STATE_BUSY_TX)
<>	149:156823d33999	1488	{
<>	149:156823d33999	1489	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
<>	149:156823d33999	1490	__HAL_SPI_CLEAR_OVRFLAG(hspi);
<>	149:156823d33999	1491	}
<>	149:156823d33999	1492	}
<>	149:156823d33999	1493
<>	149:156823d33999	1494	/* SPI Frame error interrupt occurred -------------------------------------*/
<>	149:156823d33999	1495	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_FRE) != RESET)
<>	149:156823d33999	1496	{
<>	149:156823d33999	1497	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
<>	149:156823d33999	1498	__HAL_SPI_CLEAR_FREFLAG(hspi);
<>	149:156823d33999	1499	}
<>	149:156823d33999	1500
<>	149:156823d33999	1501	/* Call the Error call Back in case of Errors */
<>	149:156823d33999	1502	if(hspi->ErrorCode!=HAL_SPI_ERROR_NONE)
<>	149:156823d33999	1503	{
<>	149:156823d33999	1504	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE \| SPI_IT_TXE \| SPI_IT_ERR);
<>	149:156823d33999	1505	hspi->State = HAL_SPI_STATE_READY;
<>	149:156823d33999	1506	HAL_SPI_ErrorCallback(hspi);
<>	149:156823d33999	1507	}
<>	149:156823d33999	1508	}
<>	149:156823d33999	1509	}
<>	149:156823d33999	1510
<>	149:156823d33999	1511	/**
<>	149:156823d33999	1512	* @brief Tx Transfer completed callbacks
<>	149:156823d33999	1513	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	1514	* the configuration information for SPI module.
<>	149:156823d33999	1515	* @retval None
<>	149:156823d33999	1516	*/
<>	149:156823d33999	1517	__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
<>	149:156823d33999	1518	{
<>	149:156823d33999	1519	/* Prevent unused argument(s) compilation warning */
<>	149:156823d33999	1520	UNUSED(hspi);
<>	149:156823d33999	1521
<>	149:156823d33999	1522	/* NOTE : This function Should not be modified, when the callback is needed,
<>	149:156823d33999	1523	the HAL_SPI_TxCpltCallback could be implenetd in the user file
<>	149:156823d33999	1524	*/
<>	149:156823d33999	1525	}
<>	149:156823d33999	1526
<>	149:156823d33999	1527	/**
<>	149:156823d33999	1528	* @brief Rx Transfer completed callbacks
<>	149:156823d33999	1529	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	1530	* the configuration information for SPI module.
<>	149:156823d33999	1531	* @retval None
<>	149:156823d33999	1532	*/
<>	149:156823d33999	1533	__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
<>	149:156823d33999	1534	{
<>	149:156823d33999	1535	/* Prevent unused argument(s) compilation warning */
<>	149:156823d33999	1536	UNUSED(hspi);
<>	149:156823d33999	1537
<>	149:156823d33999	1538	/* NOTE : This function Should not be modified, when the callback is needed,
<>	149:156823d33999	1539	the HAL_SPI_RxCpltCallback() could be implenetd in the user file
<>	149:156823d33999	1540	*/
<>	149:156823d33999	1541	}
<>	149:156823d33999	1542
<>	149:156823d33999	1543	/**
<>	149:156823d33999	1544	* @brief Tx and Rx Transfer completed callbacks
<>	149:156823d33999	1545	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	1546	* the configuration information for SPI module.
<>	149:156823d33999	1547	* @retval None
<>	149:156823d33999	1548	*/
<>	149:156823d33999	1549	__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
<>	149:156823d33999	1550	{
<>	149:156823d33999	1551	/* Prevent unused argument(s) compilation warning */
<>	149:156823d33999	1552	UNUSED(hspi);
<>	149:156823d33999	1553
<>	149:156823d33999	1554	/* NOTE : This function Should not be modified, when the callback is needed,
<>	149:156823d33999	1555	the HAL_SPI_TxRxCpltCallback() could be implenetd in the user file
<>	149:156823d33999	1556	*/
<>	149:156823d33999	1557	}
<>	149:156823d33999	1558
<>	149:156823d33999	1559	/**
<>	149:156823d33999	1560	* @brief Tx Half Transfer completed callbacks
<>	149:156823d33999	1561	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	1562	* the configuration information for SPI module.
<>	149:156823d33999	1563	* @retval None
<>	149:156823d33999	1564	*/
<>	149:156823d33999	1565	__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
<>	149:156823d33999	1566	{
<>	149:156823d33999	1567	/* Prevent unused argument(s) compilation warning */
<>	149:156823d33999	1568	UNUSED(hspi);
<>	149:156823d33999	1569
<>	149:156823d33999	1570	/* NOTE : This function Should not be modified, when the callback is needed,
<>	149:156823d33999	1571	the HAL_SPI_TxHalfCpltCallback could be implenetd in the user file
<>	149:156823d33999	1572	*/
<>	149:156823d33999	1573	}
<>	149:156823d33999	1574
<>	149:156823d33999	1575	/**
<>	149:156823d33999	1576	* @brief Rx Half Transfer completed callbacks
<>	149:156823d33999	1577	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	1578	* the configuration information for SPI module.
<>	149:156823d33999	1579	* @retval None
<>	149:156823d33999	1580	*/
<>	149:156823d33999	1581	__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
<>	149:156823d33999	1582	{
<>	149:156823d33999	1583	/* Prevent unused argument(s) compilation warning */
<>	149:156823d33999	1584	UNUSED(hspi);
<>	149:156823d33999	1585
<>	149:156823d33999	1586	/* NOTE : This function Should not be modified, when the callback is needed,
<>	149:156823d33999	1587	the HAL_SPI_RxHalfCpltCallback() could be implenetd in the user file
<>	149:156823d33999	1588	*/
<>	149:156823d33999	1589	}
<>	149:156823d33999	1590
<>	149:156823d33999	1591	/**
<>	149:156823d33999	1592	* @brief Tx and Rx Transfer completed callbacks
<>	149:156823d33999	1593	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	1594	* the configuration information for SPI module.
<>	149:156823d33999	1595	* @retval None
<>	149:156823d33999	1596	*/
<>	149:156823d33999	1597	__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
<>	149:156823d33999	1598	{
<>	149:156823d33999	1599	/* Prevent unused argument(s) compilation warning */
<>	149:156823d33999	1600	UNUSED(hspi);
<>	149:156823d33999	1601
<>	149:156823d33999	1602	/* NOTE : This function Should not be modified, when the callback is needed,
<>	149:156823d33999	1603	the HAL_SPI_TxRxHalfCpltCallback() could be implenetd in the user file
<>	149:156823d33999	1604	*/
<>	149:156823d33999	1605	}
<>	149:156823d33999	1606
<>	149:156823d33999	1607	/**
<>	149:156823d33999	1608	* @brief SPI error callbacks
<>	149:156823d33999	1609	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	1610	* the configuration information for SPI module.
<>	149:156823d33999	1611	* @retval None
<>	149:156823d33999	1612	*/
<>	149:156823d33999	1613	__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
<>	149:156823d33999	1614	{
<>	149:156823d33999	1615	/* Prevent unused argument(s) compilation warning */
<>	149:156823d33999	1616	UNUSED(hspi);
<>	149:156823d33999	1617
<>	149:156823d33999	1618	/* NOTE : - This function Should not be modified, when the callback is needed,
<>	149:156823d33999	1619	the HAL_SPI_ErrorCallback() could be implenetd in the user file.
<>	149:156823d33999	1620	- The ErrorCode parameter in the hspi handle is updated by the SPI processes
<>	149:156823d33999	1621	and user can use HAL_SPI_GetError() API to check the latest error occurred.
<>	149:156823d33999	1622	*/
<>	149:156823d33999	1623	}
<>	149:156823d33999	1624
<>	149:156823d33999	1625	/**
<>	149:156823d33999	1626	* @}
<>	149:156823d33999	1627	*/
<>	149:156823d33999	1628
<>	149:156823d33999	1629	/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
<>	149:156823d33999	1630	* @brief SPI control functions
<>	149:156823d33999	1631	*
<>	149:156823d33999	1632	@verbatim
<>	149:156823d33999	1633	===============================================================================
<>	149:156823d33999	1634	##### Peripheral State and Errors functions #####
<>	149:156823d33999	1635	===============================================================================
<>	149:156823d33999	1636	[..]
<>	149:156823d33999	1637	This subsection provides a set of functions allowing to control the SPI.
<>	149:156823d33999	1638	(+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
<>	149:156823d33999	1639	(+) HAL_SPI_GetError() check in run-time Errors occurring during communication
<>	149:156823d33999	1640	@endverbatim
<>	149:156823d33999	1641	* @{
<>	149:156823d33999	1642	*/
<>	149:156823d33999	1643
<>	149:156823d33999	1644	/**
<>	149:156823d33999	1645	* @brief Return the SPI state
<>	149:156823d33999	1646	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	1647	* the configuration information for SPI module.
<>	149:156823d33999	1648	* @retval HAL state
<>	149:156823d33999	1649	*/
<>	149:156823d33999	1650	HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
<>	149:156823d33999	1651	{
<>	149:156823d33999	1652	return hspi->State;
<>	149:156823d33999	1653	}
<>	149:156823d33999	1654
<>	149:156823d33999	1655	/**
<>	149:156823d33999	1656	* @brief Return the SPI error code
<>	149:156823d33999	1657	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	1658	* the configuration information for SPI module.
<>	149:156823d33999	1659	* @retval SPI Error Code
<>	149:156823d33999	1660	*/
<>	149:156823d33999	1661	uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
<>	149:156823d33999	1662	{
<>	149:156823d33999	1663	return hspi->ErrorCode;
<>	149:156823d33999	1664	}
<>	149:156823d33999	1665
<>	149:156823d33999	1666	/**
<>	149:156823d33999	1667	* @}
<>	149:156823d33999	1668	*/
<>	149:156823d33999	1669
<>	149:156823d33999	1670	/**
<>	149:156823d33999	1671	* @}
<>	149:156823d33999	1672	*/
<>	149:156823d33999	1673
<>	149:156823d33999	1674
<>	149:156823d33999	1675
<>	149:156823d33999	1676	/** @addtogroup SPI_Private_Functions
<>	149:156823d33999	1677	* @{
<>	149:156823d33999	1678	*/
<>	149:156823d33999	1679
<>	149:156823d33999	1680
<>	149:156823d33999	1681	/**
<>	149:156823d33999	1682	* @brief Interrupt Handler to close Tx transfer
<>	149:156823d33999	1683	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	1684	* the configuration information for SPI module.
<>	149:156823d33999	1685	* @retval void
<>	149:156823d33999	1686	*/
<>	149:156823d33999	1687	static void SPI_TxCloseIRQHandler(struct __SPI_HandleTypeDef *hspi)
<>	149:156823d33999	1688	{
<>	149:156823d33999	1689	/* Wait until TXE flag is set to send data */
<>	149:156823d33999	1690	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
<>	149:156823d33999	1691	{
<>	149:156823d33999	1692	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<>	149:156823d33999	1693	}
<>	149:156823d33999	1694
<>	149:156823d33999	1695	/* Disable TXE interrupt */
<>	149:156823d33999	1696	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE ));
<>	149:156823d33999	1697
<>	149:156823d33999	1698	/* Disable ERR interrupt if Receive process is finished */
<>	149:156823d33999	1699	if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) == RESET)
<>	149:156823d33999	1700	{
<>	149:156823d33999	1701	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_ERR));
<>	149:156823d33999	1702
<>	149:156823d33999	1703	/* Wait until Busy flag is reset before disabling SPI */
<>	149:156823d33999	1704	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
<>	149:156823d33999	1705	{
<>	149:156823d33999	1706	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<>	149:156823d33999	1707	}
<>	149:156823d33999	1708
<>	149:156823d33999	1709	/* Clear OVERUN flag in 2 Lines communication mode because received is not read */
<>	149:156823d33999	1710	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
<>	149:156823d33999	1711	{
<>	149:156823d33999	1712	__HAL_SPI_CLEAR_OVRFLAG(hspi);
<>	149:156823d33999	1713	}
<>	149:156823d33999	1714
<>	149:156823d33999	1715	/* Check if Errors has been detected during transfer */
<>	149:156823d33999	1716	if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
<>	149:156823d33999	1717	{
<>	149:156823d33999	1718	/* Check if we are in Tx or in Rx/Tx Mode */
<>	149:156823d33999	1719	if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX)
<>	149:156823d33999	1720	{
<>	149:156823d33999	1721	/* Set state to READY before run the Callback Complete */
<>	149:156823d33999	1722	hspi->State = HAL_SPI_STATE_READY;
<>	149:156823d33999	1723	HAL_SPI_TxRxCpltCallback(hspi);
<>	149:156823d33999	1724	}
<>	149:156823d33999	1725	else
<>	149:156823d33999	1726	{
<>	149:156823d33999	1727	/* Set state to READY before run the Callback Complete */
<>	149:156823d33999	1728	hspi->State = HAL_SPI_STATE_READY;
<>	149:156823d33999	1729	HAL_SPI_TxCpltCallback(hspi);
<>	149:156823d33999	1730	}
<>	149:156823d33999	1731	}
<>	149:156823d33999	1732	else
<>	149:156823d33999	1733	{
<>	149:156823d33999	1734	/* Set state to READY before run the Callback Complete */
<>	149:156823d33999	1735	hspi->State = HAL_SPI_STATE_READY;
<>	149:156823d33999	1736	/* Call Error call back in case of Error */
<>	149:156823d33999	1737	HAL_SPI_ErrorCallback(hspi);
<>	149:156823d33999	1738	}
<>	149:156823d33999	1739	}
<>	149:156823d33999	1740	}
<>	149:156823d33999	1741
<>	149:156823d33999	1742	/**
<>	149:156823d33999	1743	* @brief Interrupt Handler to transmit amount of data in no-blocking mode
<>	149:156823d33999	1744	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	1745	* the configuration information for SPI module.
<>	149:156823d33999	1746	* @retval void
<>	149:156823d33999	1747	*/
<>	149:156823d33999	1748	static void SPI_TxISR(struct __SPI_HandleTypeDef *hspi)
<>	149:156823d33999	1749	{
<>	149:156823d33999	1750	/* Transmit data in 8 Bit mode */
<>	149:156823d33999	1751	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
<>	149:156823d33999	1752	{
<>	149:156823d33999	1753	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
<>	149:156823d33999	1754	}
<>	149:156823d33999	1755	/* Transmit data in 16 Bit mode */
<>	149:156823d33999	1756	else
<>	149:156823d33999	1757	{
<>	149:156823d33999	1758	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
<>	149:156823d33999	1759	hspi->pTxBuffPtr+=2;
<>	149:156823d33999	1760	}
<>	149:156823d33999	1761	hspi->TxXferCount--;
<>	149:156823d33999	1762
<>	149:156823d33999	1763	if(hspi->TxXferCount == 0)
<>	149:156823d33999	1764	{
<>	149:156823d33999	1765	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	149:156823d33999	1766	{
<>	149:156823d33999	1767	/* calculate and transfer CRC on Tx line */
<>	149:156823d33999	1768	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<>	149:156823d33999	1769	}
<>	149:156823d33999	1770	SPI_TxCloseIRQHandler(hspi);
<>	149:156823d33999	1771	}
<>	149:156823d33999	1772	}
<>	149:156823d33999	1773
<>	149:156823d33999	1774	/**
<>	149:156823d33999	1775	* @brief Interrupt Handler to close Rx transfer
<>	149:156823d33999	1776	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	1777	* the configuration information for SPI module.
<>	149:156823d33999	1778	* @retval void
<>	149:156823d33999	1779	*/
<>	149:156823d33999	1780	static void SPI_RxCloseIRQHandler(struct __SPI_HandleTypeDef *hspi)
<>	149:156823d33999	1781	{
<>	149:156823d33999	1782	__IO uint16_t tmpreg = 0;
<>	149:156823d33999	1783
<>	149:156823d33999	1784	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	149:156823d33999	1785	{
<>	149:156823d33999	1786	/* Wait until RXNE flag is set to send data */
<>	149:156823d33999	1787	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
<>	149:156823d33999	1788	{
<>	149:156823d33999	1789	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<>	149:156823d33999	1790	}
<>	149:156823d33999	1791
<>	149:156823d33999	1792	/* Read CRC to reset RXNE flag */
<>	149:156823d33999	1793	tmpreg = hspi->Instance->DR;
<>	149:156823d33999	1794	UNUSED(tmpreg);
<>	149:156823d33999	1795
<>	149:156823d33999	1796	/* Wait until RXNE flag is set to send data */
<>	149:156823d33999	1797	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
<>	149:156823d33999	1798	{
<>	149:156823d33999	1799	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<>	149:156823d33999	1800	}
<>	149:156823d33999	1801
<>	149:156823d33999	1802	/* Check if CRC error occurred */
<>	149:156823d33999	1803	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
<>	149:156823d33999	1804	{
<>	149:156823d33999	1805	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<>	149:156823d33999	1806
<>	149:156823d33999	1807	/* Reset CRC Calculation */
<>	149:156823d33999	1808	SPI_RESET_CRC(hspi);
<>	149:156823d33999	1809	}
<>	149:156823d33999	1810	}
<>	149:156823d33999	1811
<>	149:156823d33999	1812	/* Disable RXNE interrupt */
<>	149:156823d33999	1813	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE));
<>	149:156823d33999	1814
<>	149:156823d33999	1815	/* if Transmit process is finished */
<>	149:156823d33999	1816	if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) == RESET)
<>	149:156823d33999	1817	{
<>	149:156823d33999	1818	/* Disable ERR interrupt */
<>	149:156823d33999	1819	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_ERR));
<>	149:156823d33999	1820
<>	149:156823d33999	1821	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
<>	149:156823d33999	1822	{
<>	149:156823d33999	1823	/* Disable SPI peripheral */
<>	149:156823d33999	1824	__HAL_SPI_DISABLE(hspi);
<>	149:156823d33999	1825	}
<>	149:156823d33999	1826
<>	149:156823d33999	1827	/* Check if Errors has been detected during transfer */
<>	149:156823d33999	1828	if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
<>	149:156823d33999	1829	{
<>	149:156823d33999	1830	/* Check if we are in Rx or in Rx/Tx Mode */
<>	149:156823d33999	1831	if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX)
<>	149:156823d33999	1832	{
<>	149:156823d33999	1833	/* Set state to READY before run the Callback Complete */
<>	149:156823d33999	1834	hspi->State = HAL_SPI_STATE_READY;
<>	149:156823d33999	1835	HAL_SPI_TxRxCpltCallback(hspi);
<>	149:156823d33999	1836	}
<>	149:156823d33999	1837	else
<>	149:156823d33999	1838	{
<>	149:156823d33999	1839	/* Set state to READY before run the Callback Complete */
<>	149:156823d33999	1840	hspi->State = HAL_SPI_STATE_READY;
<>	149:156823d33999	1841	HAL_SPI_RxCpltCallback(hspi);
<>	149:156823d33999	1842	}
<>	149:156823d33999	1843	}
<>	149:156823d33999	1844	else
<>	149:156823d33999	1845	{
<>	149:156823d33999	1846	/* Set state to READY before run the Callback Complete */
<>	149:156823d33999	1847	hspi->State = HAL_SPI_STATE_READY;
<>	149:156823d33999	1848	/* Call Error call back in case of Error */
<>	149:156823d33999	1849	HAL_SPI_ErrorCallback(hspi);
<>	149:156823d33999	1850	}
<>	149:156823d33999	1851	}
<>	149:156823d33999	1852	}
<>	149:156823d33999	1853
<>	149:156823d33999	1854	/**
<>	149:156823d33999	1855	* @brief Interrupt Handler to receive amount of data in 2Lines mode
<>	149:156823d33999	1856	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	1857	* the configuration information for SPI module.
<>	149:156823d33999	1858	* @retval void
<>	149:156823d33999	1859	*/
<>	149:156823d33999	1860	static void SPI_2LinesRxISR(struct __SPI_HandleTypeDef *hspi)
<>	149:156823d33999	1861	{
<>	149:156823d33999	1862	/* Receive data in 8 Bit mode */
<>	149:156823d33999	1863	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
<>	149:156823d33999	1864	{
<>	149:156823d33999	1865	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
<>	149:156823d33999	1866	}
<>	149:156823d33999	1867	/* Receive data in 16 Bit mode */
<>	149:156823d33999	1868	else
<>	149:156823d33999	1869	{
<>	149:156823d33999	1870	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
<>	149:156823d33999	1871	hspi->pRxBuffPtr+=2;
<>	149:156823d33999	1872	}
<>	149:156823d33999	1873	hspi->RxXferCount--;
<>	149:156823d33999	1874
<>	149:156823d33999	1875	if(hspi->RxXferCount==0)
<>	149:156823d33999	1876	{
<>	149:156823d33999	1877	SPI_RxCloseIRQHandler(hspi);
<>	149:156823d33999	1878	}
<>	149:156823d33999	1879	}
<>	149:156823d33999	1880
<>	149:156823d33999	1881	/**
<>	149:156823d33999	1882	* @brief Interrupt Handler to receive amount of data in no-blocking mode
<>	149:156823d33999	1883	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	1884	* the configuration information for SPI module.
<>	149:156823d33999	1885	* @retval void
<>	149:156823d33999	1886	*/
<>	149:156823d33999	1887	static void SPI_RxISR(struct __SPI_HandleTypeDef *hspi)
<>	149:156823d33999	1888	{
<>	149:156823d33999	1889	/* Receive data in 8 Bit mode */
<>	149:156823d33999	1890	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
<>	149:156823d33999	1891	{
<>	149:156823d33999	1892	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
<>	149:156823d33999	1893	}
<>	149:156823d33999	1894	/* Receive data in 16 Bit mode */
<>	149:156823d33999	1895	else
<>	149:156823d33999	1896	{
<>	149:156823d33999	1897	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
<>	149:156823d33999	1898	hspi->pRxBuffPtr+=2;
<>	149:156823d33999	1899	}
<>	149:156823d33999	1900	hspi->RxXferCount--;
<>	149:156823d33999	1901
<>	149:156823d33999	1902	/* Enable CRC Transmission */
<>	149:156823d33999	1903	if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
<>	149:156823d33999	1904	{
<>	149:156823d33999	1905	/* Set CRC Next to calculate CRC on Rx side */
<>	149:156823d33999	1906	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<>	149:156823d33999	1907	}
<>	149:156823d33999	1908
<>	149:156823d33999	1909	if(hspi->RxXferCount == 0)
<>	149:156823d33999	1910	{
<>	149:156823d33999	1911	SPI_RxCloseIRQHandler(hspi);
<>	149:156823d33999	1912	}
<>	149:156823d33999	1913	}
<>	149:156823d33999	1914
<>	149:156823d33999	1915	/**
<>	149:156823d33999	1916	* @brief DMA SPI transmit process complete callback
<>	149:156823d33999	1917	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<>	149:156823d33999	1918	* the configuration information for the specified DMA module.
<>	149:156823d33999	1919	* @retval None
<>	149:156823d33999	1920	*/
<>	149:156823d33999	1921	static void SPI_DMATransmitCplt(struct __DMA_HandleTypeDef *hdma)
<>	149:156823d33999	1922	{
<>	149:156823d33999	1923	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	149:156823d33999	1924
<>	149:156823d33999	1925	/* DMA Normal Mode */
<>	149:156823d33999	1926	if((hdma->Instance->CCR & DMA_CIRCULAR) == 0)
<>	149:156823d33999	1927	{
<>	149:156823d33999	1928	/* Wait until TXE flag is set to send data */
<>	149:156823d33999	1929	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
<>	149:156823d33999	1930	{
<>	149:156823d33999	1931	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<>	149:156823d33999	1932	}
<>	149:156823d33999	1933
<>	149:156823d33999	1934	/* Disable Tx DMA Request */
<>	149:156823d33999	1935	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
<>	149:156823d33999	1936
<>	149:156823d33999	1937	/* Wait until Busy flag is reset before disabling SPI */
<>	149:156823d33999	1938	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
<>	149:156823d33999	1939	{
<>	149:156823d33999	1940	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<>	149:156823d33999	1941	}
<>	149:156823d33999	1942
<>	149:156823d33999	1943	hspi->TxXferCount = 0;
<>	149:156823d33999	1944	hspi->State = HAL_SPI_STATE_READY;
<>	149:156823d33999	1945	}
<>	149:156823d33999	1946
<>	149:156823d33999	1947	/* Clear OVERUN flag in 2 Lines communication mode because received is not read */
<>	149:156823d33999	1948	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
<>	149:156823d33999	1949	{
<>	149:156823d33999	1950	__HAL_SPI_CLEAR_OVRFLAG(hspi);
<>	149:156823d33999	1951	}
<>	149:156823d33999	1952
<>	149:156823d33999	1953	/* Check if Errors has been detected during transfer */
<>	149:156823d33999	1954	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
<>	149:156823d33999	1955	{
<>	149:156823d33999	1956	HAL_SPI_ErrorCallback(hspi);
<>	149:156823d33999	1957	}
<>	149:156823d33999	1958	else
<>	149:156823d33999	1959	{
<>	149:156823d33999	1960	HAL_SPI_TxCpltCallback(hspi);
<>	149:156823d33999	1961	}
<>	149:156823d33999	1962	}
<>	149:156823d33999	1963
<>	149:156823d33999	1964	/**
<>	149:156823d33999	1965	* @brief DMA SPI receive process complete callback
<>	149:156823d33999	1966	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<>	149:156823d33999	1967	* the configuration information for the specified DMA module.
<>	149:156823d33999	1968	* @retval None
<>	149:156823d33999	1969	*/
<>	149:156823d33999	1970	static void SPI_DMAReceiveCplt(struct __DMA_HandleTypeDef *hdma)
<>	149:156823d33999	1971	{
<>	149:156823d33999	1972	__IO uint16_t tmpreg = 0;
<>	149:156823d33999	1973
<>	149:156823d33999	1974	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	149:156823d33999	1975
<>	149:156823d33999	1976	/* DMA Normal mode */
<>	149:156823d33999	1977	if((hdma->Instance->CCR & DMA_CIRCULAR) == 0)
<>	149:156823d33999	1978	{
<>	149:156823d33999	1979	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
<>	149:156823d33999	1980	{
<>	149:156823d33999	1981	/* Disable SPI peripheral */
<>	149:156823d33999	1982	__HAL_SPI_DISABLE(hspi);
<>	149:156823d33999	1983	}
<>	149:156823d33999	1984
<>	149:156823d33999	1985	/* Disable Rx DMA Request */
<>	149:156823d33999	1986	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
<>	149:156823d33999	1987
<>	149:156823d33999	1988	/* Disable Tx DMA Request (done by default to handle the case Master RX direction 2 lines) */
<>	149:156823d33999	1989	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
<>	149:156823d33999	1990
<>	149:156823d33999	1991	/* Reset CRC Calculation */
<>	149:156823d33999	1992	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	149:156823d33999	1993	{
<>	149:156823d33999	1994	/* Wait until RXNE flag is set to send data */
<>	149:156823d33999	1995	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
<>	149:156823d33999	1996	{
<>	149:156823d33999	1997	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<>	149:156823d33999	1998	}
<>	149:156823d33999	1999
<>	149:156823d33999	2000	/* Read CRC */
<>	149:156823d33999	2001	tmpreg = hspi->Instance->DR;
<>	149:156823d33999	2002	UNUSED(tmpreg);
<>	149:156823d33999	2003
<>	149:156823d33999	2004	/* Wait until RXNE flag is set */
<>	149:156823d33999	2005	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
<>	149:156823d33999	2006	{
<>	149:156823d33999	2007	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<>	149:156823d33999	2008	}
<>	149:156823d33999	2009
<>	149:156823d33999	2010	/* Check if CRC error occurred */
<>	149:156823d33999	2011	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
<>	149:156823d33999	2012	{
<>	149:156823d33999	2013	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<>	149:156823d33999	2014	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
<>	149:156823d33999	2015	}
<>	149:156823d33999	2016	}
<>	149:156823d33999	2017
<>	149:156823d33999	2018	hspi->RxXferCount = 0;
<>	149:156823d33999	2019	hspi->State = HAL_SPI_STATE_READY;
<>	149:156823d33999	2020
<>	149:156823d33999	2021	/* Check if Errors has been detected during transfer */
<>	149:156823d33999	2022	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
<>	149:156823d33999	2023	{
<>	149:156823d33999	2024	HAL_SPI_ErrorCallback(hspi);
<>	149:156823d33999	2025	}
<>	149:156823d33999	2026	else
<>	149:156823d33999	2027	{
<>	149:156823d33999	2028	HAL_SPI_RxCpltCallback(hspi);
<>	149:156823d33999	2029	}
<>	149:156823d33999	2030	}
<>	149:156823d33999	2031	else
<>	149:156823d33999	2032	{
<>	149:156823d33999	2033	HAL_SPI_RxCpltCallback(hspi);
<>	149:156823d33999	2034	}
<>	149:156823d33999	2035	}
<>	149:156823d33999	2036
<>	149:156823d33999	2037	/**
<>	149:156823d33999	2038	* @brief DMA SPI transmit receive process complete callback
<>	149:156823d33999	2039	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<>	149:156823d33999	2040	* the configuration information for the specified DMA module.
<>	149:156823d33999	2041	* @retval None
<>	149:156823d33999	2042	*/
<>	149:156823d33999	2043	static void SPI_DMATransmitReceiveCplt(struct __DMA_HandleTypeDef *hdma)
<>	149:156823d33999	2044	{
<>	149:156823d33999	2045	__IO uint16_t tmpreg = 0;
<>	149:156823d33999	2046
<>	149:156823d33999	2047	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	149:156823d33999	2048
<>	149:156823d33999	2049	if((hdma->Instance->CCR & DMA_CIRCULAR) == 0)
<>	149:156823d33999	2050	{
<>	149:156823d33999	2051	/* Reset CRC Calculation */
<>	149:156823d33999	2052	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	149:156823d33999	2053	{
<>	149:156823d33999	2054	/* Check if CRC is done on going (RXNE flag set) */
<>	149:156823d33999	2055	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) == HAL_OK)
<>	149:156823d33999	2056	{
<>	149:156823d33999	2057	/* Wait until RXNE flag is set to send data */
<>	149:156823d33999	2058	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
<>	149:156823d33999	2059	{
<>	149:156823d33999	2060	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<>	149:156823d33999	2061	}
<>	149:156823d33999	2062	}
<>	149:156823d33999	2063	/* Read CRC */
<>	149:156823d33999	2064	tmpreg = hspi->Instance->DR;
<>	149:156823d33999	2065	UNUSED(tmpreg);
<>	149:156823d33999	2066
<>	149:156823d33999	2067	/* Check if CRC error occurred */
<>	149:156823d33999	2068	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
<>	149:156823d33999	2069	{
<>	149:156823d33999	2070	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<>	149:156823d33999	2071	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
<>	149:156823d33999	2072	}
<>	149:156823d33999	2073	}
<>	149:156823d33999	2074
<>	149:156823d33999	2075	/* Wait until TXE flag is set to send data */
<>	149:156823d33999	2076	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
<>	149:156823d33999	2077	{
<>	149:156823d33999	2078	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<>	149:156823d33999	2079	}
<>	149:156823d33999	2080
<>	149:156823d33999	2081	/* Disable Tx DMA Request */
<>	149:156823d33999	2082	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
<>	149:156823d33999	2083
<>	149:156823d33999	2084	/* Wait until Busy flag is reset before disabling SPI */
<>	149:156823d33999	2085	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
<>	149:156823d33999	2086	{
<>	149:156823d33999	2087	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<>	149:156823d33999	2088	}
<>	149:156823d33999	2089
<>	149:156823d33999	2090	/* Disable Rx DMA Request */
<>	149:156823d33999	2091	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
<>	149:156823d33999	2092
<>	149:156823d33999	2093	hspi->TxXferCount = 0;
<>	149:156823d33999	2094	hspi->RxXferCount = 0;
<>	149:156823d33999	2095
<>	149:156823d33999	2096	hspi->State = HAL_SPI_STATE_READY;
<>	149:156823d33999	2097
<>	149:156823d33999	2098	/* Check if Errors has been detected during transfer */
<>	149:156823d33999	2099	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
<>	149:156823d33999	2100	{
<>	149:156823d33999	2101	HAL_SPI_ErrorCallback(hspi);
<>	149:156823d33999	2102	}
<>	149:156823d33999	2103	else
<>	149:156823d33999	2104	{
<>	149:156823d33999	2105	HAL_SPI_TxRxCpltCallback(hspi);
<>	149:156823d33999	2106	}
<>	149:156823d33999	2107	}
<>	149:156823d33999	2108	else
<>	149:156823d33999	2109	{
<>	149:156823d33999	2110	HAL_SPI_TxRxCpltCallback(hspi);
<>	149:156823d33999	2111	}
<>	149:156823d33999	2112	}
<>	149:156823d33999	2113
<>	149:156823d33999	2114	/**
<>	149:156823d33999	2115	* @brief DMA SPI half transmit process complete callback
<>	149:156823d33999	2116	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<>	149:156823d33999	2117	* the configuration information for the specified DMA module.
<>	149:156823d33999	2118	* @retval None
<>	149:156823d33999	2119	*/
<>	149:156823d33999	2120	static void SPI_DMAHalfTransmitCplt(struct __DMA_HandleTypeDef *hdma)
<>	149:156823d33999	2121	{
<>	149:156823d33999	2122	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	149:156823d33999	2123
<>	149:156823d33999	2124	HAL_SPI_TxHalfCpltCallback(hspi);
<>	149:156823d33999	2125	}
<>	149:156823d33999	2126
<>	149:156823d33999	2127	/**
<>	149:156823d33999	2128	* @brief DMA SPI half receive process complete callback
<>	149:156823d33999	2129	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<>	149:156823d33999	2130	* the configuration information for the specified DMA module.
<>	149:156823d33999	2131	* @retval None
<>	149:156823d33999	2132	*/
<>	149:156823d33999	2133	static void SPI_DMAHalfReceiveCplt(struct __DMA_HandleTypeDef *hdma)
<>	149:156823d33999	2134	{
<>	149:156823d33999	2135	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	149:156823d33999	2136
<>	149:156823d33999	2137	HAL_SPI_RxHalfCpltCallback(hspi);
<>	149:156823d33999	2138	}
<>	149:156823d33999	2139
<>	149:156823d33999	2140	/**
<>	149:156823d33999	2141	* @brief DMA SPI Half transmit receive process complete callback
<>	149:156823d33999	2142	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<>	149:156823d33999	2143	* the configuration information for the specified DMA module.
<>	149:156823d33999	2144	* @retval None
<>	149:156823d33999	2145	*/
<>	149:156823d33999	2146	static void SPI_DMAHalfTransmitReceiveCplt(struct __DMA_HandleTypeDef *hdma)
<>	149:156823d33999	2147	{
<>	149:156823d33999	2148	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	149:156823d33999	2149
<>	149:156823d33999	2150	HAL_SPI_TxRxHalfCpltCallback(hspi);
<>	149:156823d33999	2151	}
<>	149:156823d33999	2152
<>	149:156823d33999	2153	/**
<>	149:156823d33999	2154	* @brief DMA SPI communication error callback
<>	149:156823d33999	2155	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<>	149:156823d33999	2156	* the configuration information for the specified DMA module.
<>	149:156823d33999	2157	* @retval None
<>	149:156823d33999	2158	*/
<>	149:156823d33999	2159	static void SPI_DMAError(struct __DMA_HandleTypeDef *hdma)
<>	149:156823d33999	2160	{
<>	149:156823d33999	2161	SPI_HandleTypeDef* hspi = (SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	149:156823d33999	2162	hspi->TxXferCount = 0;
<>	149:156823d33999	2163	hspi->RxXferCount = 0;
<>	149:156823d33999	2164	hspi->State= HAL_SPI_STATE_READY;
<>	149:156823d33999	2165	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
<>	149:156823d33999	2166	HAL_SPI_ErrorCallback(hspi);
<>	149:156823d33999	2167	}
<>	149:156823d33999	2168
<>	149:156823d33999	2169	/**
<>	149:156823d33999	2170	* @brief This function handles SPI Communication Timeout.
<>	149:156823d33999	2171	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	2172	* the configuration information for SPI module.
<>	149:156823d33999	2173	* @param Flag: SPI flag to check
<>	149:156823d33999	2174	* @param Status: Flag status to check: RESET or set
<>	149:156823d33999	2175	* @param Timeout: Timeout duration
<>	149:156823d33999	2176	* @retval HAL status
<>	149:156823d33999	2177	*/
<>	149:156823d33999	2178	static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(struct __SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
<>	149:156823d33999	2179	{
<>	149:156823d33999	2180	uint32_t tickstart = 0;
<>	149:156823d33999	2181
<>	149:156823d33999	2182	/* Get tick */
<>	149:156823d33999	2183	tickstart = HAL_GetTick();
<>	149:156823d33999	2184
<>	149:156823d33999	2185	/* Wait until flag is set */
<>	149:156823d33999	2186	if(Status == RESET)
<>	149:156823d33999	2187	{
<>	149:156823d33999	2188	while(__HAL_SPI_GET_FLAG(hspi, Flag) == RESET)
<>	149:156823d33999	2189	{
<>	149:156823d33999	2190	if(Timeout != HAL_MAX_DELAY)
<>	149:156823d33999	2191	{
<>	149:156823d33999	2192	if((Timeout == 0) \|\| ((HAL_GetTick() - tickstart ) > Timeout))
<>	149:156823d33999	2193	{
<>	149:156823d33999	2194	/* Disable the SPI and reset the CRC: the CRC value should be cleared
<>	149:156823d33999	2195	on both master and slave sides in order to resynchronize the master
<>	149:156823d33999	2196	and slave for their respective CRC calculation */
<>	149:156823d33999	2197
<>	149:156823d33999	2198	/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
<>	149:156823d33999	2199	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
<>	149:156823d33999	2200
<>	149:156823d33999	2201	/* Disable SPI peripheral */
<>	149:156823d33999	2202	__HAL_SPI_DISABLE(hspi);
<>	149:156823d33999	2203
<>	149:156823d33999	2204	/* Reset CRC Calculation */
<>	149:156823d33999	2205	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	149:156823d33999	2206	{
<>	149:156823d33999	2207	SPI_RESET_CRC(hspi);
<>	149:156823d33999	2208	}
<>	149:156823d33999	2209
<>	149:156823d33999	2210	hspi->State= HAL_SPI_STATE_READY;
<>	149:156823d33999	2211
<>	149:156823d33999	2212	/* Process Unlocked */
<>	149:156823d33999	2213	__HAL_UNLOCK(hspi);
<>	149:156823d33999	2214
<>	149:156823d33999	2215	return HAL_TIMEOUT;
<>	149:156823d33999	2216	}
<>	149:156823d33999	2217	}
<>	149:156823d33999	2218	}
<>	149:156823d33999	2219	}
<>	149:156823d33999	2220	else
<>	149:156823d33999	2221	{
<>	149:156823d33999	2222	while(__HAL_SPI_GET_FLAG(hspi, Flag) != RESET)
<>	149:156823d33999	2223	{
<>	149:156823d33999	2224	if(Timeout != HAL_MAX_DELAY)
<>	149:156823d33999	2225	{
<>	149:156823d33999	2226	if((Timeout == 0) \|\| ((HAL_GetTick() - tickstart ) > Timeout))
<>	149:156823d33999	2227	{
<>	149:156823d33999	2228	/* Disable the SPI and reset the CRC: the CRC value should be cleared
<>	149:156823d33999	2229	on both master and slave sides in order to resynchronize the master
<>	149:156823d33999	2230	and slave for their respective CRC calculation */
<>	149:156823d33999	2231
<>	149:156823d33999	2232	/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
<>	149:156823d33999	2233	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
<>	149:156823d33999	2234
<>	149:156823d33999	2235	/* Disable SPI peripheral */
<>	149:156823d33999	2236	__HAL_SPI_DISABLE(hspi);
<>	149:156823d33999	2237
<>	149:156823d33999	2238	/* Reset CRC Calculation */
<>	149:156823d33999	2239	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	149:156823d33999	2240	{
<>	149:156823d33999	2241	SPI_RESET_CRC(hspi);
<>	149:156823d33999	2242	}
<>	149:156823d33999	2243
<>	149:156823d33999	2244	hspi->State= HAL_SPI_STATE_READY;
<>	149:156823d33999	2245
<>	149:156823d33999	2246	/* Process Unlocked */
<>	149:156823d33999	2247	__HAL_UNLOCK(hspi);
<>	149:156823d33999	2248
<>	149:156823d33999	2249	return HAL_TIMEOUT;
<>	149:156823d33999	2250	}
<>	149:156823d33999	2251	}
<>	149:156823d33999	2252	}
<>	149:156823d33999	2253	}
<>	149:156823d33999	2254	return HAL_OK;
<>	149:156823d33999	2255	}
<>	149:156823d33999	2256	/**
<>	149:156823d33999	2257	* @}
<>	149:156823d33999	2258	*/
<>	149:156823d33999	2259
<>	149:156823d33999	2260	#endif /* HAL_SPI_MODULE_ENABLED */
<>	149:156823d33999	2261	/**
<>	149:156823d33999	2262	* @}
<>	149:156823d33999	2263	*/
<>	149:156823d33999	2264
<>	149:156823d33999	2265	/**
<>	149:156823d33999	2266	* @}
<>	149:156823d33999	2267	*/
<>	149:156823d33999	2268
<>	149:156823d33999	2269	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	22 Dec 2016
Imports:	1
Forks:	0
Commits:	154
Dependents:	0
Dependencies:	0
Followers:	1

targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_spi.c@149:156823d33999, 2016-10-28 (annotated)

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