Fawwaz Nadzmy / mbed-STM

mbed library sources. Supersedes mbed-src.

Fork of mbed-dev by mbed official

targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal.h@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /**
<> 149:156823d33999 2 ******************************************************************************
<> 149:156823d33999 3 * @file stm32l1xx_hal.h
<> 149:156823d33999 4 * @author MCD Application Team
<> 149:156823d33999 5 * @version V1.2.0
<> 149:156823d33999 6 * @date 01-July-2016
<> 149:156823d33999 7 * @brief This file contains all the functions prototypes for the HAL
<> 149:156823d33999 8 * module driver.
<> 149:156823d33999 9 ******************************************************************************
<> 149:156823d33999 10 * @attention
<> 149:156823d33999 11 *
<> 149:156823d33999 12 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 149:156823d33999 13 *
<> 149:156823d33999 14 * Redistribution and use in source and binary forms, with or without modification,
<> 149:156823d33999 15 * are permitted provided that the following conditions are met:
<> 149:156823d33999 16 * 1. Redistributions of source code must retain the above copyright notice,
<> 149:156823d33999 17 * this list of conditions and the following disclaimer.
<> 149:156823d33999 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 149:156823d33999 19 * this list of conditions and the following disclaimer in the documentation
<> 149:156823d33999 20 * and/or other materials provided with the distribution.
<> 149:156823d33999 21 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 149:156823d33999 22 * may be used to endorse or promote products derived from this software
<> 149:156823d33999 23 * without specific prior written permission.
<> 149:156823d33999 24 *
<> 149:156823d33999 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 149:156823d33999 26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 149:156823d33999 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 149:156823d33999 28 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 149:156823d33999 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 149:156823d33999 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 149:156823d33999 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 149:156823d33999 32 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 149:156823d33999 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 149:156823d33999 34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 149:156823d33999 35 *
<> 149:156823d33999 36 ******************************************************************************
<> 149:156823d33999 37 */
<> 149:156823d33999 38
<> 149:156823d33999 39 /* Define to prevent recursive inclusion -------------------------------------*/
<> 149:156823d33999 40 #ifndef __STM32L1xx_HAL_H
<> 149:156823d33999 41 #define __STM32L1xx_HAL_H
<> 149:156823d33999 42
<> 149:156823d33999 43 #ifdef __cplusplus
<> 149:156823d33999 44 extern "C" {
<> 149:156823d33999 45 #endif
<> 149:156823d33999 46
<> 149:156823d33999 47 /* Includes ------------------------------------------------------------------*/
<> 149:156823d33999 48 #include "stm32l1xx_hal_conf.h"
<> 149:156823d33999 49
<> 149:156823d33999 50 /** @addtogroup STM32L1xx_HAL_Driver
<> 149:156823d33999 51 * @{
<> 149:156823d33999 52 */
<> 149:156823d33999 53
<> 149:156823d33999 54 /** @addtogroup HAL
<> 149:156823d33999 55 * @{
<> 149:156823d33999 56 */
<> 149:156823d33999 57
<> 149:156823d33999 58 /* Exported types ------------------------------------------------------------*/
<> 149:156823d33999 59 /* Exported constants --------------------------------------------------------*/
<> 149:156823d33999 60 /** @defgroup HAL_Exported_Constants HAL Exported Constants
<> 149:156823d33999 61 * @{
<> 149:156823d33999 62 */
<> 149:156823d33999 63
<> 149:156823d33999 64 /** @defgroup SYSCFG_Constants SYSCFG: SYStem ConFiG
<> 149:156823d33999 65 * @{
<> 149:156823d33999 66 */
<> 149:156823d33999 67
<> 149:156823d33999 68 /** @defgroup SYSCFG_BootMode Boot Mode
<> 149:156823d33999 69 * @{
<> 149:156823d33999 70 */
<> 149:156823d33999 71
<> 149:156823d33999 72 #define SYSCFG_BOOT_MAINFLASH (0x00000000U)
<> 149:156823d33999 73 #define SYSCFG_BOOT_SYSTEMFLASH ((uint32_t)SYSCFG_MEMRMP_BOOT_MODE_0)
<> 149:156823d33999 74 #if defined(FSMC_R_BASE)
<> 149:156823d33999 75 #define SYSCFG_BOOT_FSMC ((uint32_t)SYSCFG_MEMRMP_BOOT_MODE_1)
<> 149:156823d33999 76 #endif /* FSMC_R_BASE */
<> 149:156823d33999 77 #define SYSCFG_BOOT_SRAM ((uint32_t)SYSCFG_MEMRMP_BOOT_MODE)
<> 149:156823d33999 78
<> 149:156823d33999 79 /**
<> 149:156823d33999 80 * @}
<> 149:156823d33999 81 */
<> 149:156823d33999 82
<> 149:156823d33999 83 /**
<> 149:156823d33999 84 * @}
<> 149:156823d33999 85 */
<> 149:156823d33999 86
<> 149:156823d33999 87 /** @defgroup RI_Constants RI: Routing Interface
<> 149:156823d33999 88 * @{
<> 149:156823d33999 89 */
<> 149:156823d33999 90
<> 149:156823d33999 91 /** @defgroup RI_InputCapture Input Capture
<> 149:156823d33999 92 * @{
<> 149:156823d33999 93 */
<> 149:156823d33999 94
<> 149:156823d33999 95 #define RI_INPUTCAPTURE_IC1 RI_ICR_IC1 /*!< Input Capture 1 */
<> 149:156823d33999 96 #define RI_INPUTCAPTURE_IC2 RI_ICR_IC2 /*!< Input Capture 2 */
<> 149:156823d33999 97 #define RI_INPUTCAPTURE_IC3 RI_ICR_IC3 /*!< Input Capture 3 */
<> 149:156823d33999 98 #define RI_INPUTCAPTURE_IC4 RI_ICR_IC4 /*!< Input Capture 4 */
<> 149:156823d33999 99
<> 149:156823d33999 100 /**
<> 149:156823d33999 101 * @}
<> 149:156823d33999 102 */
<> 149:156823d33999 103
<> 149:156823d33999 104 /** @defgroup TIM_Select TIM Select
<> 149:156823d33999 105 * @{
<> 149:156823d33999 106 */
<> 149:156823d33999 107
<> 149:156823d33999 108 #define TIM_SELECT_NONE (0x00000000U) /*!< None selected */
<> 149:156823d33999 109 #define TIM_SELECT_TIM2 ((uint32_t)RI_ICR_TIM_0) /*!< Timer 2 selected */
<> 149:156823d33999 110 #define TIM_SELECT_TIM3 ((uint32_t)RI_ICR_TIM_1) /*!< Timer 3 selected */
<> 149:156823d33999 111 #define TIM_SELECT_TIM4 ((uint32_t)RI_ICR_TIM) /*!< Timer 4 selected */
<> 149:156823d33999 112
<> 149:156823d33999 113 #define IS_RI_TIM(__TIM__) (((__TIM__) == TIM_SELECT_NONE) || \
<> 149:156823d33999 114 ((__TIM__) == TIM_SELECT_TIM2) || \
<> 149:156823d33999 115 ((__TIM__) == TIM_SELECT_TIM3) || \
<> 149:156823d33999 116 ((__TIM__) == TIM_SELECT_TIM4))
<> 149:156823d33999 117
<> 149:156823d33999 118 /**
<> 149:156823d33999 119 * @}
<> 149:156823d33999 120 */
<> 149:156823d33999 121
<> 149:156823d33999 122 /** @defgroup RI_InputCaptureRouting Input Capture Routing
<> 149:156823d33999 123 * @{
<> 149:156823d33999 124 */
<> 149:156823d33999 125 /* TIMx_IC1 TIMx_IC2 TIMx_IC3 TIMx_IC4 */
<> 149:156823d33999 126 #define RI_INPUTCAPTUREROUTING_0 (0x00000000U) /* PA0 PA1 PA2 PA3 */
<> 149:156823d33999 127 #define RI_INPUTCAPTUREROUTING_1 (0x00000001U) /* PA4 PA5 PA6 PA7 */
<> 149:156823d33999 128 #define RI_INPUTCAPTUREROUTING_2 (0x00000002U) /* PA8 PA9 PA10 PA11 */
<> 149:156823d33999 129 #define RI_INPUTCAPTUREROUTING_3 (0x00000003U) /* PA12 PA13 PA14 PA15 */
<> 149:156823d33999 130 #define RI_INPUTCAPTUREROUTING_4 (0x00000004U) /* PC0 PC1 PC2 PC3 */
<> 149:156823d33999 131 #define RI_INPUTCAPTUREROUTING_5 (0x00000005U) /* PC4 PC5 PC6 PC7 */
<> 149:156823d33999 132 #define RI_INPUTCAPTUREROUTING_6 (0x00000006U) /* PC8 PC9 PC10 PC11 */
<> 149:156823d33999 133 #define RI_INPUTCAPTUREROUTING_7 (0x00000007U) /* PC12 PC13 PC14 PC15 */
<> 149:156823d33999 134 #define RI_INPUTCAPTUREROUTING_8 (0x00000008U) /* PD0 PD1 PD2 PD3 */
<> 149:156823d33999 135 #define RI_INPUTCAPTUREROUTING_9 (0x00000009U) /* PD4 PD5 PD6 PD7 */
<> 149:156823d33999 136 #define RI_INPUTCAPTUREROUTING_10 (0x0000000AU) /* PD8 PD9 PD10 PD11 */
<> 149:156823d33999 137 #define RI_INPUTCAPTUREROUTING_11 (0x0000000BU) /* PD12 PD13 PD14 PD15 */
<> 149:156823d33999 138 #define RI_INPUTCAPTUREROUTING_12 (0x0000000CU) /* PE0 PE1 PE2 PE3 */
<> 149:156823d33999 139 #define RI_INPUTCAPTUREROUTING_13 (0x0000000DU) /* PE4 PE5 PE6 PE7 */
<> 149:156823d33999 140 #define RI_INPUTCAPTUREROUTING_14 (0x0000000EU) /* PE8 PE9 PE10 PE11 */
<> 149:156823d33999 141 #define RI_INPUTCAPTUREROUTING_15 (0x0000000FU) /* PE12 PE13 PE14 PE15 */
<> 149:156823d33999 142
<> 149:156823d33999 143 #define IS_RI_INPUTCAPTURE_ROUTING(__ROUTING__) (((__ROUTING__) == RI_INPUTCAPTUREROUTING_0) || \
<> 149:156823d33999 144 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_1) || \
<> 149:156823d33999 145 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_2) || \
<> 149:156823d33999 146 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_3) || \
<> 149:156823d33999 147 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_4) || \
<> 149:156823d33999 148 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_5) || \
<> 149:156823d33999 149 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_6) || \
<> 149:156823d33999 150 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_7) || \
<> 149:156823d33999 151 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_8) || \
<> 149:156823d33999 152 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_9) || \
<> 149:156823d33999 153 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_10) || \
<> 149:156823d33999 154 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_11) || \
<> 149:156823d33999 155 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_12) || \
<> 149:156823d33999 156 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_13) || \
<> 149:156823d33999 157 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_14) || \
<> 149:156823d33999 158 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_15))
<> 149:156823d33999 159
<> 149:156823d33999 160 /**
<> 149:156823d33999 161 * @}
<> 149:156823d33999 162 */
<> 149:156823d33999 163
<> 149:156823d33999 164 /** @defgroup RI_IOSwitch IO Switch
<> 149:156823d33999 165 * @{
<> 149:156823d33999 166 */
<> 149:156823d33999 167 #define RI_ASCR1_REGISTER (0x80000000U)
<> 149:156823d33999 168 /* ASCR1 I/O switch: bit 31 is set to '1' to indicate that the mask is in ASCR1 register */
<> 149:156823d33999 169 #define RI_IOSWITCH_CH0 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_0)
<> 149:156823d33999 170 #define RI_IOSWITCH_CH1 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_1)
<> 149:156823d33999 171 #define RI_IOSWITCH_CH2 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_2)
<> 149:156823d33999 172 #define RI_IOSWITCH_CH3 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_3)
<> 149:156823d33999 173 #define RI_IOSWITCH_CH4 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_4)
<> 149:156823d33999 174 #define RI_IOSWITCH_CH5 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_5)
<> 149:156823d33999 175 #define RI_IOSWITCH_CH6 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_6)
<> 149:156823d33999 176 #define RI_IOSWITCH_CH7 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_7)
<> 149:156823d33999 177 #define RI_IOSWITCH_CH8 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_8)
<> 149:156823d33999 178 #define RI_IOSWITCH_CH9 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_9)
<> 149:156823d33999 179 #define RI_IOSWITCH_CH10 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_10)
<> 149:156823d33999 180 #define RI_IOSWITCH_CH11 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_11)
<> 149:156823d33999 181 #define RI_IOSWITCH_CH12 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_12)
<> 149:156823d33999 182 #define RI_IOSWITCH_CH13 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_13)
<> 149:156823d33999 183 #define RI_IOSWITCH_CH14 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_14)
<> 149:156823d33999 184 #define RI_IOSWITCH_CH15 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_15)
<> 149:156823d33999 185 #define RI_IOSWITCH_CH18 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_18)
<> 149:156823d33999 186 #define RI_IOSWITCH_CH19 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_19)
<> 149:156823d33999 187 #define RI_IOSWITCH_CH20 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_20)
<> 149:156823d33999 188 #define RI_IOSWITCH_CH21 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_21)
<> 149:156823d33999 189 #define RI_IOSWITCH_CH22 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_22)
<> 149:156823d33999 190 #define RI_IOSWITCH_CH23 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_23)
<> 149:156823d33999 191 #define RI_IOSWITCH_CH24 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_24)
<> 149:156823d33999 192 #define RI_IOSWITCH_CH25 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_25)
<> 149:156823d33999 193 #define RI_IOSWITCH_VCOMP ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_VCOMP) /* VCOMP (ADC channel 26) is an internal switch used to connect selected channel to COMP1 non inverting input */
<> 149:156823d33999 194 #if defined (RI_ASCR2_CH1b) /* STM32L1 devices category Cat.4 and Cat.5 */
<> 149:156823d33999 195 #define RI_IOSWITCH_CH27 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_27)
<> 149:156823d33999 196 #define RI_IOSWITCH_CH28 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_28)
<> 149:156823d33999 197 #define RI_IOSWITCH_CH29 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_29)
<> 149:156823d33999 198 #define RI_IOSWITCH_CH30 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_30)
<> 149:156823d33999 199 #define RI_IOSWITCH_CH31 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_31)
<> 149:156823d33999 200 #endif /* RI_ASCR2_CH1b */
<> 149:156823d33999 201
<> 149:156823d33999 202 /* ASCR2 IO switch: bit 31 is set to '0' to indicate that the mask is in ASCR2 register */
<> 149:156823d33999 203 #define RI_IOSWITCH_GR10_1 ((uint32_t)RI_ASCR2_GR10_1)
<> 149:156823d33999 204 #define RI_IOSWITCH_GR10_2 ((uint32_t)RI_ASCR2_GR10_2)
<> 149:156823d33999 205 #define RI_IOSWITCH_GR10_3 ((uint32_t)RI_ASCR2_GR10_3)
<> 149:156823d33999 206 #define RI_IOSWITCH_GR10_4 ((uint32_t)RI_ASCR2_GR10_4)
<> 149:156823d33999 207 #define RI_IOSWITCH_GR6_1 ((uint32_t)RI_ASCR2_GR6_1)
<> 149:156823d33999 208 #define RI_IOSWITCH_GR6_2 ((uint32_t)RI_ASCR2_GR6_2)
<> 149:156823d33999 209 #define RI_IOSWITCH_GR5_1 ((uint32_t)RI_ASCR2_GR5_1)
<> 149:156823d33999 210 #define RI_IOSWITCH_GR5_2 ((uint32_t)RI_ASCR2_GR5_2)
<> 149:156823d33999 211 #define RI_IOSWITCH_GR5_3 ((uint32_t)RI_ASCR2_GR5_3)
<> 149:156823d33999 212 #define RI_IOSWITCH_GR4_1 ((uint32_t)RI_ASCR2_GR4_1)
<> 149:156823d33999 213 #define RI_IOSWITCH_GR4_2 ((uint32_t)RI_ASCR2_GR4_2)
<> 149:156823d33999 214 #define RI_IOSWITCH_GR4_3 ((uint32_t)RI_ASCR2_GR4_3)
<> 149:156823d33999 215 #if defined (RI_ASCR2_CH0b) /* STM32L1 devices category Cat.3, Cat.4 and Cat.5 */
<> 149:156823d33999 216 #define RI_IOSWITCH_CH0b ((uint32_t)RI_ASCR2_CH0b)
<> 149:156823d33999 217 #if defined (RI_ASCR2_CH1b) /* STM32L1 devices category Cat.4 and Cat.5 */
<> 149:156823d33999 218 #define RI_IOSWITCH_CH1b ((uint32_t)RI_ASCR2_CH1b)
<> 149:156823d33999 219 #define RI_IOSWITCH_CH2b ((uint32_t)RI_ASCR2_CH2b)
<> 149:156823d33999 220 #define RI_IOSWITCH_CH3b ((uint32_t)RI_ASCR2_CH3b)
<> 149:156823d33999 221 #define RI_IOSWITCH_CH6b ((uint32_t)RI_ASCR2_CH6b)
<> 149:156823d33999 222 #define RI_IOSWITCH_CH7b ((uint32_t)RI_ASCR2_CH7b)
<> 149:156823d33999 223 #define RI_IOSWITCH_CH8b ((uint32_t)RI_ASCR2_CH8b)
<> 149:156823d33999 224 #define RI_IOSWITCH_CH9b ((uint32_t)RI_ASCR2_CH9b)
<> 149:156823d33999 225 #define RI_IOSWITCH_CH10b ((uint32_t)RI_ASCR2_CH10b)
<> 149:156823d33999 226 #define RI_IOSWITCH_CH11b ((uint32_t)RI_ASCR2_CH11b)
<> 149:156823d33999 227 #define RI_IOSWITCH_CH12b ((uint32_t)RI_ASCR2_CH12b)
<> 149:156823d33999 228 #endif /* RI_ASCR2_CH1b */
<> 149:156823d33999 229 #define RI_IOSWITCH_GR6_3 ((uint32_t)RI_ASCR2_GR6_3)
<> 149:156823d33999 230 #define RI_IOSWITCH_GR6_4 ((uint32_t)RI_ASCR2_GR6_4)
<> 149:156823d33999 231 #endif /* RI_ASCR2_CH0b */
<> 149:156823d33999 232
<> 149:156823d33999 233
<> 149:156823d33999 234 #if defined (RI_ASCR2_CH1b) /* STM32L1 devices category Cat.4 and Cat.5 */
<> 149:156823d33999 235
<> 149:156823d33999 236 #define IS_RI_IOSWITCH(__IOSWITCH__) (((__IOSWITCH__) == RI_IOSWITCH_CH0) || ((__IOSWITCH__) == RI_IOSWITCH_CH1) || \
<> 149:156823d33999 237 ((__IOSWITCH__) == RI_IOSWITCH_CH2) || ((__IOSWITCH__) == RI_IOSWITCH_CH3) || \
<> 149:156823d33999 238 ((__IOSWITCH__) == RI_IOSWITCH_CH4) || ((__IOSWITCH__) == RI_IOSWITCH_CH5) || \
<> 149:156823d33999 239 ((__IOSWITCH__) == RI_IOSWITCH_CH6) || ((__IOSWITCH__) == RI_IOSWITCH_CH7) || \
<> 149:156823d33999 240 ((__IOSWITCH__) == RI_IOSWITCH_CH8) || ((__IOSWITCH__) == RI_IOSWITCH_CH9) || \
<> 149:156823d33999 241 ((__IOSWITCH__) == RI_IOSWITCH_CH10) || ((__IOSWITCH__) == RI_IOSWITCH_CH11) || \
<> 149:156823d33999 242 ((__IOSWITCH__) == RI_IOSWITCH_CH12) || ((__IOSWITCH__) == RI_IOSWITCH_CH13) || \
<> 149:156823d33999 243 ((__IOSWITCH__) == RI_IOSWITCH_CH14) || ((__IOSWITCH__) == RI_IOSWITCH_CH15) || \
<> 149:156823d33999 244 ((__IOSWITCH__) == RI_IOSWITCH_CH18) || ((__IOSWITCH__) == RI_IOSWITCH_CH19) || \
<> 149:156823d33999 245 ((__IOSWITCH__) == RI_IOSWITCH_CH20) || ((__IOSWITCH__) == RI_IOSWITCH_CH21) || \
<> 149:156823d33999 246 ((__IOSWITCH__) == RI_IOSWITCH_CH22) || ((__IOSWITCH__) == RI_IOSWITCH_CH23) || \
<> 149:156823d33999 247 ((__IOSWITCH__) == RI_IOSWITCH_CH24) || ((__IOSWITCH__) == RI_IOSWITCH_CH25) || \
<> 149:156823d33999 248 ((__IOSWITCH__) == RI_IOSWITCH_VCOMP) || ((__IOSWITCH__) == RI_IOSWITCH_CH27) || \
<> 149:156823d33999 249 ((__IOSWITCH__) == RI_IOSWITCH_CH28) || ((__IOSWITCH__) == RI_IOSWITCH_CH29) || \
<> 149:156823d33999 250 ((__IOSWITCH__) == RI_IOSWITCH_CH30) || ((__IOSWITCH__) == RI_IOSWITCH_CH31) || \
<> 149:156823d33999 251 ((__IOSWITCH__) == RI_IOSWITCH_GR10_1) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_2) || \
<> 149:156823d33999 252 ((__IOSWITCH__) == RI_IOSWITCH_GR10_3) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_4) || \
<> 149:156823d33999 253 ((__IOSWITCH__) == RI_IOSWITCH_GR6_1) || ((__IOSWITCH__) == RI_IOSWITCH_GR6_2) || \
<> 149:156823d33999 254 ((__IOSWITCH__) == RI_IOSWITCH_GR6_3) || ((__IOSWITCH__) == RI_IOSWITCH_GR6_4) || \
<> 149:156823d33999 255 ((__IOSWITCH__) == RI_IOSWITCH_GR5_1) || ((__IOSWITCH__) == RI_IOSWITCH_GR5_2) || \
<> 149:156823d33999 256 ((__IOSWITCH__) == RI_IOSWITCH_GR5_3) || ((__IOSWITCH__) == RI_IOSWITCH_GR4_1) || \
<> 149:156823d33999 257 ((__IOSWITCH__) == RI_IOSWITCH_GR4_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR4_3) || \
<> 149:156823d33999 258 ((__IOSWITCH__) == RI_IOSWITCH_CH0b) || ((__IOSWITCH__) == RI_IOSWITCH_CH1b) || \
<> 149:156823d33999 259 ((__IOSWITCH__) == RI_IOSWITCH_CH2b) || ((__IOSWITCH__) == RI_IOSWITCH_CH3b) || \
<> 149:156823d33999 260 ((__IOSWITCH__) == RI_IOSWITCH_CH6b) || ((__IOSWITCH__) == RI_IOSWITCH_CH7b) || \
<> 149:156823d33999 261 ((__IOSWITCH__) == RI_IOSWITCH_CH8b) || ((__IOSWITCH__) == RI_IOSWITCH_CH9b) || \
<> 149:156823d33999 262 ((__IOSWITCH__) == RI_IOSWITCH_CH10b) || ((__IOSWITCH__) == RI_IOSWITCH_CH11b) || \
<> 149:156823d33999 263 ((__IOSWITCH__) == RI_IOSWITCH_CH12b))
<> 149:156823d33999 264
<> 149:156823d33999 265 #else /* !RI_ASCR2_CH1b */
<> 149:156823d33999 266
<> 149:156823d33999 267 #if defined (RI_ASCR2_CH0b) /* STM32L1 devices category Cat.3 */
<> 149:156823d33999 268
<> 149:156823d33999 269 #define IS_RI_IOSWITCH(__IOSWITCH__) (((__IOSWITCH__) == RI_IOSWITCH_CH0) || ((__IOSWITCH__) == RI_IOSWITCH_CH1) || \
<> 149:156823d33999 270 ((__IOSWITCH__) == RI_IOSWITCH_CH2) || ((__IOSWITCH__) == RI_IOSWITCH_CH3) || \
<> 149:156823d33999 271 ((__IOSWITCH__) == RI_IOSWITCH_CH4) || ((__IOSWITCH__) == RI_IOSWITCH_CH5) || \
<> 149:156823d33999 272 ((__IOSWITCH__) == RI_IOSWITCH_CH6) || ((__IOSWITCH__) == RI_IOSWITCH_CH7) || \
<> 149:156823d33999 273 ((__IOSWITCH__) == RI_IOSWITCH_CH8) || ((__IOSWITCH__) == RI_IOSWITCH_CH9) || \
<> 149:156823d33999 274 ((__IOSWITCH__) == RI_IOSWITCH_CH10) || ((__IOSWITCH__) == RI_IOSWITCH_CH11) || \
<> 149:156823d33999 275 ((__IOSWITCH__) == RI_IOSWITCH_CH12) || ((__IOSWITCH__) == RI_IOSWITCH_CH13) || \
<> 149:156823d33999 276 ((__IOSWITCH__) == RI_IOSWITCH_CH14) || ((__IOSWITCH__) == RI_IOSWITCH_CH15) || \
<> 149:156823d33999 277 ((__IOSWITCH__) == RI_IOSWITCH_CH18) || ((__IOSWITCH__) == RI_IOSWITCH_CH19) || \
<> 149:156823d33999 278 ((__IOSWITCH__) == RI_IOSWITCH_CH20) || ((__IOSWITCH__) == RI_IOSWITCH_CH21) || \
<> 149:156823d33999 279 ((__IOSWITCH__) == RI_IOSWITCH_CH22) || ((__IOSWITCH__) == RI_IOSWITCH_CH23) || \
<> 149:156823d33999 280 ((__IOSWITCH__) == RI_IOSWITCH_CH24) || ((__IOSWITCH__) == RI_IOSWITCH_CH25) || \
<> 149:156823d33999 281 ((__IOSWITCH__) == RI_IOSWITCH_VCOMP) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_1) || \
<> 149:156823d33999 282 ((__IOSWITCH__) == RI_IOSWITCH_GR10_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_3) || \
<> 149:156823d33999 283 ((__IOSWITCH__) == RI_IOSWITCH_GR10_4) || ((__IOSWITCH__) == RI_IOSWITCH_GR6_1) || \
<> 149:156823d33999 284 ((__IOSWITCH__) == RI_IOSWITCH_GR6_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR5_1) || \
<> 149:156823d33999 285 ((__IOSWITCH__) == RI_IOSWITCH_GR5_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR5_3) || \
<> 149:156823d33999 286 ((__IOSWITCH__) == RI_IOSWITCH_GR4_1) || ((__IOSWITCH__) == RI_IOSWITCH_GR4_2) || \
<> 149:156823d33999 287 ((__IOSWITCH__) == RI_IOSWITCH_GR4_3) || ((__IOSWITCH__) == RI_IOSWITCH_CH0b))
<> 149:156823d33999 288
<> 149:156823d33999 289 #else /* !RI_ASCR2_CH0b */ /* STM32L1 devices category Cat.1 and Cat.2 */
<> 149:156823d33999 290
<> 149:156823d33999 291 #define IS_RI_IOSWITCH(__IOSWITCH__) (((__IOSWITCH__) == RI_IOSWITCH_CH0) || ((__IOSWITCH__) == RI_IOSWITCH_CH1) || \
<> 149:156823d33999 292 ((__IOSWITCH__) == RI_IOSWITCH_CH2) || ((__IOSWITCH__) == RI_IOSWITCH_CH3) || \
<> 149:156823d33999 293 ((__IOSWITCH__) == RI_IOSWITCH_CH4) || ((__IOSWITCH__) == RI_IOSWITCH_CH5) || \
<> 149:156823d33999 294 ((__IOSWITCH__) == RI_IOSWITCH_CH6) || ((__IOSWITCH__) == RI_IOSWITCH_CH7) || \
<> 149:156823d33999 295 ((__IOSWITCH__) == RI_IOSWITCH_CH8) || ((__IOSWITCH__) == RI_IOSWITCH_CH9) || \
<> 149:156823d33999 296 ((__IOSWITCH__) == RI_IOSWITCH_CH10) || ((__IOSWITCH__) == RI_IOSWITCH_CH11) || \
<> 149:156823d33999 297 ((__IOSWITCH__) == RI_IOSWITCH_CH12) || ((__IOSWITCH__) == RI_IOSWITCH_CH13) || \
<> 149:156823d33999 298 ((__IOSWITCH__) == RI_IOSWITCH_CH14) || ((__IOSWITCH__) == RI_IOSWITCH_CH15) || \
<> 149:156823d33999 299 ((__IOSWITCH__) == RI_IOSWITCH_CH18) || ((__IOSWITCH__) == RI_IOSWITCH_CH19) || \
<> 149:156823d33999 300 ((__IOSWITCH__) == RI_IOSWITCH_CH20) || ((__IOSWITCH__) == RI_IOSWITCH_CH21) || \
<> 149:156823d33999 301 ((__IOSWITCH__) == RI_IOSWITCH_CH22) || ((__IOSWITCH__) == RI_IOSWITCH_CH23) || \
<> 149:156823d33999 302 ((__IOSWITCH__) == RI_IOSWITCH_CH24) || ((__IOSWITCH__) == RI_IOSWITCH_CH25) || \
<> 149:156823d33999 303 ((__IOSWITCH__) == RI_IOSWITCH_VCOMP) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_1) || \
<> 149:156823d33999 304 ((__IOSWITCH__) == RI_IOSWITCH_GR10_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_3) || \
<> 149:156823d33999 305 ((__IOSWITCH__) == RI_IOSWITCH_GR10_4) || ((__IOSWITCH__) == RI_IOSWITCH_GR6_1) || \
<> 149:156823d33999 306 ((__IOSWITCH__) == RI_IOSWITCH_GR6_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR5_1) || \
<> 149:156823d33999 307 ((__IOSWITCH__) == RI_IOSWITCH_GR5_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR5_3) || \
<> 149:156823d33999 308 ((__IOSWITCH__) == RI_IOSWITCH_GR4_1) || ((__IOSWITCH__) == RI_IOSWITCH_GR4_2) || \
<> 149:156823d33999 309 ((__IOSWITCH__) == RI_IOSWITCH_GR4_3))
<> 149:156823d33999 310
<> 149:156823d33999 311 #endif /* RI_ASCR2_CH0b */
<> 149:156823d33999 312 #endif /* RI_ASCR2_CH1b */
<> 149:156823d33999 313
<> 149:156823d33999 314 /**
<> 149:156823d33999 315 * @}
<> 149:156823d33999 316 */
<> 149:156823d33999 317
<> 149:156823d33999 318 /** @defgroup RI_Pin PIN define
<> 149:156823d33999 319 * @{
<> 149:156823d33999 320 */
<> 149:156823d33999 321 #define RI_PIN_0 ((uint16_t)0x0001) /*!< Pin 0 selected */
<> 149:156823d33999 322 #define RI_PIN_1 ((uint16_t)0x0002) /*!< Pin 1 selected */
<> 149:156823d33999 323 #define RI_PIN_2 ((uint16_t)0x0004) /*!< Pin 2 selected */
<> 149:156823d33999 324 #define RI_PIN_3 ((uint16_t)0x0008) /*!< Pin 3 selected */
<> 149:156823d33999 325 #define RI_PIN_4 ((uint16_t)0x0010) /*!< Pin 4 selected */
<> 149:156823d33999 326 #define RI_PIN_5 ((uint16_t)0x0020) /*!< Pin 5 selected */
<> 149:156823d33999 327 #define RI_PIN_6 ((uint16_t)0x0040) /*!< Pin 6 selected */
<> 149:156823d33999 328 #define RI_PIN_7 ((uint16_t)0x0080) /*!< Pin 7 selected */
<> 149:156823d33999 329 #define RI_PIN_8 ((uint16_t)0x0100) /*!< Pin 8 selected */
<> 149:156823d33999 330 #define RI_PIN_9 ((uint16_t)0x0200) /*!< Pin 9 selected */
<> 149:156823d33999 331 #define RI_PIN_10 ((uint16_t)0x0400) /*!< Pin 10 selected */
<> 149:156823d33999 332 #define RI_PIN_11 ((uint16_t)0x0800) /*!< Pin 11 selected */
<> 149:156823d33999 333 #define RI_PIN_12 ((uint16_t)0x1000) /*!< Pin 12 selected */
<> 149:156823d33999 334 #define RI_PIN_13 ((uint16_t)0x2000) /*!< Pin 13 selected */
<> 149:156823d33999 335 #define RI_PIN_14 ((uint16_t)0x4000) /*!< Pin 14 selected */
<> 149:156823d33999 336 #define RI_PIN_15 ((uint16_t)0x8000) /*!< Pin 15 selected */
<> 149:156823d33999 337 #define RI_PIN_ALL ((uint16_t)0xFFFF) /*!< All pins selected */
<> 149:156823d33999 338
<> 149:156823d33999 339 #define IS_RI_PIN(__PIN__) ((__PIN__) != (uint16_t)0x00)
<> 149:156823d33999 340
<> 149:156823d33999 341 /**
<> 149:156823d33999 342 * @}
<> 149:156823d33999 343 */
<> 149:156823d33999 344
<> 149:156823d33999 345 /**
<> 149:156823d33999 346 * @}
<> 149:156823d33999 347 */
<> 149:156823d33999 348
<> 149:156823d33999 349 /**
<> 149:156823d33999 350 * @}
<> 149:156823d33999 351 */
<> 149:156823d33999 352
<> 149:156823d33999 353 /* Exported macro ------------------------------------------------------------*/
<> 149:156823d33999 354
<> 149:156823d33999 355 /** @defgroup HAL_Exported_Macros HAL Exported Macros
<> 149:156823d33999 356 * @{
<> 149:156823d33999 357 */
<> 149:156823d33999 358
<> 149:156823d33999 359 /** @defgroup DBGMCU_Macros DBGMCU: Debug MCU
<> 149:156823d33999 360 * @{
<> 149:156823d33999 361 */
<> 149:156823d33999 362
<> 149:156823d33999 363 /** @defgroup DBGMCU_Freeze_Unfreeze Freeze Unfreeze Peripherals in Debug mode
<> 149:156823d33999 364 * @brief Freeze/Unfreeze Peripherals in Debug mode
<> 149:156823d33999 365 * @{
<> 149:156823d33999 366 */
<> 149:156823d33999 367
<> 149:156823d33999 368 /**
<> 149:156823d33999 369 * @brief TIM2 Peripherals Debug mode
<> 149:156823d33999 370 */
<> 149:156823d33999 371 #if defined (DBGMCU_APB1_FZ_DBG_TIM2_STOP)
<> 149:156823d33999 372 #define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM2_STOP)
<> 149:156823d33999 373 #define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM2_STOP)
<> 149:156823d33999 374 #endif
<> 149:156823d33999 375
<> 149:156823d33999 376 /**
<> 149:156823d33999 377 * @brief TIM3 Peripherals Debug mode
<> 149:156823d33999 378 */
<> 149:156823d33999 379 #if defined (DBGMCU_APB1_FZ_DBG_TIM3_STOP)
<> 149:156823d33999 380 #define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM3_STOP)
<> 149:156823d33999 381 #define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM3_STOP)
<> 149:156823d33999 382 #endif
<> 149:156823d33999 383
<> 149:156823d33999 384 /**
<> 149:156823d33999 385 * @brief TIM4 Peripherals Debug mode
<> 149:156823d33999 386 */
<> 149:156823d33999 387 #if defined (DBGMCU_APB1_FZ_DBG_TIM4_STOP)
<> 149:156823d33999 388 #define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM4_STOP)
<> 149:156823d33999 389 #define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM4_STOP)
<> 149:156823d33999 390 #endif
<> 149:156823d33999 391
<> 149:156823d33999 392 /**
<> 149:156823d33999 393 * @brief TIM5 Peripherals Debug mode
<> 149:156823d33999 394 */
<> 149:156823d33999 395 #if defined (DBGMCU_APB1_FZ_DBG_TIM5_STOP)
<> 149:156823d33999 396 #define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM5_STOP)
<> 149:156823d33999 397 #define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM5_STOP)
<> 149:156823d33999 398 #endif
<> 149:156823d33999 399
<> 149:156823d33999 400 /**
<> 149:156823d33999 401 * @brief TIM6 Peripherals Debug mode
<> 149:156823d33999 402 */
<> 149:156823d33999 403 #if defined (DBGMCU_APB1_FZ_DBG_TIM6_STOP)
<> 149:156823d33999 404 #define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM6_STOP)
<> 149:156823d33999 405 #define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM6_STOP)
<> 149:156823d33999 406 #endif
<> 149:156823d33999 407
<> 149:156823d33999 408 /**
<> 149:156823d33999 409 * @brief TIM7 Peripherals Debug mode
<> 149:156823d33999 410 */
<> 149:156823d33999 411 #if defined (DBGMCU_APB1_FZ_DBG_TIM7_STOP)
<> 149:156823d33999 412 #define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM7_STOP)
<> 149:156823d33999 413 #define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM7_STOP)
<> 149:156823d33999 414 #endif
<> 149:156823d33999 415
<> 149:156823d33999 416 /**
<> 149:156823d33999 417 * @brief RTC Peripherals Debug mode
<> 149:156823d33999 418 */
<> 149:156823d33999 419 #if defined (DBGMCU_APB1_FZ_DBG_RTC_STOP)
<> 149:156823d33999 420 #define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_RTC_STOP)
<> 149:156823d33999 421 #define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_RTC_STOP)
<> 149:156823d33999 422 #endif
<> 149:156823d33999 423
<> 149:156823d33999 424 /**
<> 149:156823d33999 425 * @brief WWDG Peripherals Debug mode
<> 149:156823d33999 426 */
<> 149:156823d33999 427 #if defined (DBGMCU_APB1_FZ_DBG_WWDG_STOP)
<> 149:156823d33999 428 #define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_WWDG_STOP)
<> 149:156823d33999 429 #define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_WWDG_STOP)
<> 149:156823d33999 430 #endif
<> 149:156823d33999 431
<> 149:156823d33999 432 /**
<> 149:156823d33999 433 * @brief IWDG Peripherals Debug mode
<> 149:156823d33999 434 */
<> 149:156823d33999 435 #if defined (DBGMCU_APB1_FZ_DBG_IWDG_STOP)
<> 149:156823d33999 436 #define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_IWDG_STOP)
<> 149:156823d33999 437 #define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_IWDG_STOP)
<> 149:156823d33999 438 #endif
<> 149:156823d33999 439
<> 149:156823d33999 440 /**
<> 149:156823d33999 441 * @brief I2C1 Peripherals Debug mode
<> 149:156823d33999 442 */
<> 149:156823d33999 443 #if defined (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)
<> 149:156823d33999 444 #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)
<> 149:156823d33999 445 #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)
<> 149:156823d33999 446 #endif
<> 149:156823d33999 447
<> 149:156823d33999 448 /**
<> 149:156823d33999 449 * @brief I2C2 Peripherals Debug mode
<> 149:156823d33999 450 */
<> 149:156823d33999 451 #if defined (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)
<> 149:156823d33999 452 #define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)
<> 149:156823d33999 453 #define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)
<> 149:156823d33999 454 #endif
<> 149:156823d33999 455
<> 149:156823d33999 456 /**
<> 149:156823d33999 457 * @brief TIM9 Peripherals Debug mode
<> 149:156823d33999 458 */
<> 149:156823d33999 459 #if defined (DBGMCU_APB2_FZ_DBG_TIM9_STOP)
<> 149:156823d33999 460 #define __HAL_DBGMCU_FREEZE_TIM9() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM9_STOP)
<> 149:156823d33999 461 #define __HAL_DBGMCU_UNFREEZE_TIM9() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM9_STOP)
<> 149:156823d33999 462 #endif
<> 149:156823d33999 463
<> 149:156823d33999 464 /**
<> 149:156823d33999 465 * @brief TIM10 Peripherals Debug mode
<> 149:156823d33999 466 */
<> 149:156823d33999 467 #if defined (DBGMCU_APB2_FZ_DBG_TIM10_STOP)
<> 149:156823d33999 468 #define __HAL_DBGMCU_FREEZE_TIM10() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM10_STOP)
<> 149:156823d33999 469 #define __HAL_DBGMCU_UNFREEZE_TIM10() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM10_STOP)
<> 149:156823d33999 470 #endif
<> 149:156823d33999 471
<> 149:156823d33999 472 /**
<> 149:156823d33999 473 * @brief TIM11 Peripherals Debug mode
<> 149:156823d33999 474 */
<> 149:156823d33999 475 #if defined (DBGMCU_APB2_FZ_DBG_TIM11_STOP)
<> 149:156823d33999 476 #define __HAL_DBGMCU_FREEZE_TIM11() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM11_STOP)
<> 149:156823d33999 477 #define __HAL_DBGMCU_UNFREEZE_TIM11() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM11_STOP)
<> 149:156823d33999 478 #endif
<> 149:156823d33999 479
<> 149:156823d33999 480
<> 149:156823d33999 481 /**
<> 149:156823d33999 482 * @}
<> 149:156823d33999 483 */
<> 149:156823d33999 484
<> 149:156823d33999 485 /**
<> 149:156823d33999 486 * @}
<> 149:156823d33999 487 */
<> 149:156823d33999 488
<> 149:156823d33999 489 /** @defgroup SYSCFG_Macros SYSCFG: SYStem ConFiG
<> 149:156823d33999 490 * @{
<> 149:156823d33999 491 */
<> 149:156823d33999 492
<> 149:156823d33999 493 /** @defgroup SYSCFG_VrefInt VREFINT configuration
<> 149:156823d33999 494 * @{
<> 149:156823d33999 495 */
<> 149:156823d33999 496
<> 149:156823d33999 497 /**
<> 149:156823d33999 498 * @brief Enables or disables the output of internal reference voltage
<> 149:156823d33999 499 * (VREFINT) on I/O pin.
<> 149:156823d33999 500 * The VREFINT output can be routed to any I/O in group 3:
<> 149:156823d33999 501 * - For Cat.1 and Cat.2 devices: CH8 (PB0) or CH9 (PB1).
<> 149:156823d33999 502 * - For Cat.3 devices: CH8 (PB0), CH9 (PB1) or CH0b (PB2).
<> 149:156823d33999 503 * - For Cat.4 and Cat.5 devices: CH8 (PB0), CH9 (PB1), CH0b (PB2),
<> 149:156823d33999 504 * CH1b (PF11) or CH2b (PF12).
<> 149:156823d33999 505 * Note: Comparator peripheral clock must be preliminarility enabled,
<> 149:156823d33999 506 * either in COMP user function "HAL_COMP_MspInit()" (should be
<> 149:156823d33999 507 * done if comparators are used) or by direct clock enable:
<> 149:156823d33999 508 * Refer to macro "__HAL_RCC_COMP_CLK_ENABLE()".
<> 149:156823d33999 509 * Note: In addition with this macro, Vrefint output buffer must be
<> 149:156823d33999 510 * connected to the selected I/O pin. Refer to macro
<> 149:156823d33999 511 * "__HAL_RI_IOSWITCH_CLOSE()".
<> 149:156823d33999 512 * @note ENABLE: Internal reference voltage connected to I/O group 3
<> 149:156823d33999 513 * @note DISABLE: Internal reference voltage disconnected from I/O group 3
<> 149:156823d33999 514 * @retval None
<> 149:156823d33999 515 */
<> 149:156823d33999 516 #define __HAL_SYSCFG_VREFINT_OUT_ENABLE() SET_BIT(COMP->CSR, COMP_CSR_VREFOUTEN)
<> 149:156823d33999 517 #define __HAL_SYSCFG_VREFINT_OUT_DISABLE() CLEAR_BIT(COMP->CSR, COMP_CSR_VREFOUTEN)
<> 149:156823d33999 518
<> 149:156823d33999 519 /**
<> 149:156823d33999 520 * @}
<> 149:156823d33999 521 */
<> 149:156823d33999 522
<> 149:156823d33999 523 /** @defgroup SYSCFG_BootModeConfig Boot Mode Configuration
<> 149:156823d33999 524 * @{
<> 149:156823d33999 525 */
<> 149:156823d33999 526
<> 149:156823d33999 527 /**
<> 149:156823d33999 528 * @brief Main Flash memory mapped at 0x00000000
<> 149:156823d33999 529 */
<> 149:156823d33999 530 #define __HAL_SYSCFG_REMAPMEMORY_FLASH() CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)
<> 149:156823d33999 531
<> 149:156823d33999 532 /** @brief System Flash memory mapped at 0x00000000
<> 149:156823d33999 533 */
<> 149:156823d33999 534 #define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0)
<> 149:156823d33999 535
<> 149:156823d33999 536 /** @brief Embedded SRAM mapped at 0x00000000
<> 149:156823d33999 537 */
<> 149:156823d33999 538 #define __HAL_SYSCFG_REMAPMEMORY_SRAM() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0 | SYSCFG_MEMRMP_MEM_MODE_1)
<> 149:156823d33999 539
<> 149:156823d33999 540 #if defined(FSMC_R_BASE)
<> 149:156823d33999 541 /** @brief FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000
<> 149:156823d33999 542 */
<> 149:156823d33999 543 #define __HAL_SYSCFG_REMAPMEMORY_FSMC() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_1)
<> 149:156823d33999 544
<> 149:156823d33999 545 #endif /* FSMC_R_BASE */
<> 149:156823d33999 546
<> 149:156823d33999 547 /**
<> 149:156823d33999 548 * @brief Returns the boot mode as configured by user.
<> 149:156823d33999 549 * @retval The boot mode as configured by user. The returned value can be one
<> 149:156823d33999 550 * of the following values:
<> 149:156823d33999 551 * @arg SYSCFG_BOOT_MAINFLASH
<> 149:156823d33999 552 * @arg SYSCFG_BOOT_SYSTEMFLASH
<> 149:156823d33999 553 * @arg SYSCFG_BOOT_FSMC (available only for STM32L151xD, STM32L152xD & STM32L162xD)
<> 149:156823d33999 554 * @arg SYSCFG_BOOT_SRAM
<> 149:156823d33999 555 */
<> 149:156823d33999 556 #define __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BOOT_MODE)
<> 149:156823d33999 557
<> 149:156823d33999 558 /**
<> 149:156823d33999 559 * @}
<> 149:156823d33999 560 */
<> 149:156823d33999 561
<> 149:156823d33999 562 /** @defgroup SYSCFG_USBConfig USB DP line Configuration
<> 149:156823d33999 563 * @{
<> 149:156823d33999 564 */
<> 149:156823d33999 565
<> 149:156823d33999 566 /**
<> 149:156823d33999 567 * @brief Control the internal pull-up on USB DP line.
<> 149:156823d33999 568 */
<> 149:156823d33999 569 #define __HAL_SYSCFG_USBPULLUP_ENABLE() SET_BIT(SYSCFG->PMC, SYSCFG_PMC_USB_PU)
<> 149:156823d33999 570
<> 149:156823d33999 571 #define __HAL_SYSCFG_USBPULLUP_DISABLE() CLEAR_BIT(SYSCFG->PMC, SYSCFG_PMC_USB_PU)
<> 149:156823d33999 572
<> 149:156823d33999 573 /**
<> 149:156823d33999 574 * @}
<> 149:156823d33999 575 */
<> 149:156823d33999 576
<> 149:156823d33999 577 /**
<> 149:156823d33999 578 * @}
<> 149:156823d33999 579 */
<> 149:156823d33999 580
<> 149:156823d33999 581 /** @defgroup RI_Macris RI: Routing Interface
<> 149:156823d33999 582 * @{
<> 149:156823d33999 583 */
<> 149:156823d33999 584
<> 149:156823d33999 585 /** @defgroup RI_InputCaputureConfig Input Capture configuration
<> 149:156823d33999 586 * @{
<> 149:156823d33999 587 */
<> 149:156823d33999 588
<> 149:156823d33999 589 /**
<> 149:156823d33999 590 * @brief Configures the routing interface to map Input Capture 1 of TIMx to a selected I/O pin.
<> 149:156823d33999 591 * @param __TIMSELECT__: Timer select.
<> 149:156823d33999 592 * This parameter can be one of the following values:
<> 149:156823d33999 593 * @arg TIM_SELECT_NONE: No timer selected and default Timer mapping is enabled.
<> 149:156823d33999 594 * @arg TIM_SELECT_TIM2: Timer 2 Input Captures to be routed.
<> 149:156823d33999 595 * @arg TIM_SELECT_TIM3: Timer 3 Input Captures to be routed.
<> 149:156823d33999 596 * @arg TIM_SELECT_TIM4: Timer 4 Input Captures to be routed.
<> 149:156823d33999 597 * @param __INPUT__: selects which pin to be routed to Input Capture.
<> 149:156823d33999 598 * This parameter must be a value of @ref RI_InputCaptureRouting
<> 149:156823d33999 599 * e.g.
<> 149:156823d33999 600 * __HAL_RI_REMAP_INPUTCAPTURE1(TIM_SELECT_TIM2, RI_INPUTCAPTUREROUTING_1)
<> 149:156823d33999 601 * allows routing of Input capture IC1 of TIM2 to PA4.
<> 149:156823d33999 602 * For details about correspondence between RI_INPUTCAPTUREROUTING_x
<> 149:156823d33999 603 * and I/O pins refer to the parameters' description in the header file
<> 149:156823d33999 604 * or refer to the product reference manual.
<> 149:156823d33999 605 * @note Input capture selection bits are not reset by this function.
<> 149:156823d33999 606 * To reset input capture selection bits, use SYSCFG_RIDeInit() function.
<> 149:156823d33999 607 * @note The I/O should be configured in alternate function mode (AF14) using
<> 149:156823d33999 608 * GPIO_PinAFConfig() function.
<> 149:156823d33999 609 * @retval None.
<> 149:156823d33999 610 */
<> 149:156823d33999 611 #define __HAL_RI_REMAP_INPUTCAPTURE1(__TIMSELECT__, __INPUT__) \
<> 149:156823d33999 612 do {assert_param(IS_RI_TIM(__TIMSELECT__)); \
<> 149:156823d33999 613 assert_param(IS_RI_INPUTCAPTURE_ROUTING(__INPUT__)); \
<> 149:156823d33999 614 MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \
<> 149:156823d33999 615 SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC1); \
<> 149:156823d33999 616 MODIFY_REG(RI->ICR, RI_ICR_IC1OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC1OS)); \
<> 149:156823d33999 617 }while(0)
<> 149:156823d33999 618
<> 149:156823d33999 619 /**
<> 149:156823d33999 620 * @brief Configures the routing interface to map Input Capture 2 of TIMx to a selected I/O pin.
<> 149:156823d33999 621 * @param __TIMSELECT__: Timer select.
<> 149:156823d33999 622 * This parameter can be one of the following values:
<> 149:156823d33999 623 * @arg TIM_SELECT_NONE: No timer selected and default Timer mapping is enabled.
<> 149:156823d33999 624 * @arg TIM_SELECT_TIM2: Timer 2 Input Captures to be routed.
<> 149:156823d33999 625 * @arg TIM_SELECT_TIM3: Timer 3 Input Captures to be routed.
<> 149:156823d33999 626 * @arg TIM_SELECT_TIM4: Timer 4 Input Captures to be routed.
<> 149:156823d33999 627 * @param __INPUT__: selects which pin to be routed to Input Capture.
<> 149:156823d33999 628 * This parameter must be a value of @ref RI_InputCaptureRouting
<> 149:156823d33999 629 * @retval None.
<> 149:156823d33999 630 */
<> 149:156823d33999 631 #define __HAL_RI_REMAP_INPUTCAPTURE2(__TIMSELECT__, __INPUT__) \
<> 149:156823d33999 632 do {assert_param(IS_RI_TIM(__TIMSELECT__)); \
<> 149:156823d33999 633 assert_param(IS_RI_INPUTCAPTURE_ROUTING(__INPUT__)); \
<> 149:156823d33999 634 MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \
<> 149:156823d33999 635 SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC2); \
<> 149:156823d33999 636 MODIFY_REG(RI->ICR, RI_ICR_IC2OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC2OS)); \
<> 149:156823d33999 637 }while(0)
<> 149:156823d33999 638
<> 149:156823d33999 639 /**
<> 149:156823d33999 640 * @brief Configures the routing interface to map Input Capture 3 of TIMx to a selected I/O pin.
<> 149:156823d33999 641 * @param __TIMSELECT__: Timer select.
<> 149:156823d33999 642 * This parameter can be one of the following values:
<> 149:156823d33999 643 * @arg TIM_SELECT_NONE: No timer selected and default Timer mapping is enabled.
<> 149:156823d33999 644 * @arg TIM_SELECT_TIM2: Timer 2 Input Captures to be routed.
<> 149:156823d33999 645 * @arg TIM_SELECT_TIM3: Timer 3 Input Captures to be routed.
<> 149:156823d33999 646 * @arg TIM_SELECT_TIM4: Timer 4 Input Captures to be routed.
<> 149:156823d33999 647 * @param __INPUT__: selects which pin to be routed to Input Capture.
<> 149:156823d33999 648 * This parameter must be a value of @ref RI_InputCaptureRouting
<> 149:156823d33999 649 * @retval None.
<> 149:156823d33999 650 */
<> 149:156823d33999 651 #define __HAL_RI_REMAP_INPUTCAPTURE3(__TIMSELECT__, __INPUT__) \
<> 149:156823d33999 652 do {assert_param(IS_RI_TIM(__TIMSELECT__)); \
<> 149:156823d33999 653 assert_param(IS_RI_INPUTCAPTURE_ROUTING(__INPUT__)); \
<> 149:156823d33999 654 MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \
<> 149:156823d33999 655 SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC3); \
<> 149:156823d33999 656 MODIFY_REG(RI->ICR, RI_ICR_IC3OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC3OS)); \
<> 149:156823d33999 657 }while(0)
<> 149:156823d33999 658
<> 149:156823d33999 659 /**
<> 149:156823d33999 660 * @brief Configures the routing interface to map Input Capture 4 of TIMx to a selected I/O pin.
<> 149:156823d33999 661 * @param __TIMSELECT__: Timer select.
<> 149:156823d33999 662 * This parameter can be one of the following values:
<> 149:156823d33999 663 * @arg TIM_SELECT_NONE: No timer selected and default Timer mapping is enabled.
<> 149:156823d33999 664 * @arg TIM_SELECT_TIM2: Timer 2 Input Captures to be routed.
<> 149:156823d33999 665 * @arg TIM_SELECT_TIM3: Timer 3 Input Captures to be routed.
<> 149:156823d33999 666 * @arg TIM_SELECT_TIM4: Timer 4 Input Captures to be routed.
<> 149:156823d33999 667 * @param __INPUT__: selects which pin to be routed to Input Capture.
<> 149:156823d33999 668 * This parameter must be a value of @ref RI_InputCaptureRouting
<> 149:156823d33999 669 * @retval None.
<> 149:156823d33999 670 */
<> 149:156823d33999 671 #define __HAL_RI_REMAP_INPUTCAPTURE4(__TIMSELECT__, __INPUT__) \
<> 149:156823d33999 672 do {assert_param(IS_RI_TIM(__TIMSELECT__)); \
<> 149:156823d33999 673 assert_param(IS_RI_INPUTCAPTURE_ROUTING(__INPUT__)); \
<> 149:156823d33999 674 MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \
<> 149:156823d33999 675 SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC4); \
<> 149:156823d33999 676 MODIFY_REG(RI->ICR, RI_ICR_IC4OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC4OS)); \
<> 149:156823d33999 677 }while(0)
<> 149:156823d33999 678
<> 149:156823d33999 679 /**
<> 149:156823d33999 680 * @}
<> 149:156823d33999 681 */
<> 149:156823d33999 682
<> 149:156823d33999 683 /** @defgroup RI_SwitchControlConfig Switch Control configuration
<> 149:156823d33999 684 * @{
<> 149:156823d33999 685 */
<> 149:156823d33999 686
<> 149:156823d33999 687 /**
<> 149:156823d33999 688 * @brief Enable or disable the switch control mode.
<> 149:156823d33999 689 * @note ENABLE: ADC analog switches closed if the corresponding
<> 149:156823d33999 690 * I/O switch is also closed.
<> 149:156823d33999 691 * When using COMP1, switch control mode must be enabled.
<> 149:156823d33999 692 * @note DISABLE: ADC analog switches open or controlled by the ADC interface.
<> 149:156823d33999 693 * When using the ADC for acquisition, switch control mode
<> 149:156823d33999 694 * must be disabled.
<> 149:156823d33999 695 * @note COMP1 comparator and ADC cannot be used at the same time since
<> 149:156823d33999 696 * they share the ADC switch matrix.
<> 149:156823d33999 697 * @retval None
<> 149:156823d33999 698 */
<> 149:156823d33999 699 #define __HAL_RI_SWITCHCONTROLMODE_ENABLE() SET_BIT(RI->ASCR1, RI_ASCR1_SCM)
<> 149:156823d33999 700
<> 149:156823d33999 701 #define __HAL_RI_SWITCHCONTROLMODE_DISABLE() CLEAR_BIT(RI->ASCR1, RI_ASCR1_SCM)
<> 149:156823d33999 702
<> 149:156823d33999 703 /*
<> 149:156823d33999 704 * @brief Close or Open the routing interface Input Output switches.
<> 149:156823d33999 705 * @param __IOSWITCH__: selects the I/O analog switch number.
<> 149:156823d33999 706 * This parameter must be a value of @ref RI_IOSwitch
<> 149:156823d33999 707 * @retval None
<> 149:156823d33999 708 */
<> 149:156823d33999 709 #define __HAL_RI_IOSWITCH_CLOSE(__IOSWITCH__) do { assert_param(IS_RI_IOSWITCH(__IOSWITCH__)); \
<> 149:156823d33999 710 if ((__IOSWITCH__) >> 31 != 0 ) \
<> 149:156823d33999 711 { \
<> 149:156823d33999 712 SET_BIT(RI->ASCR1, (__IOSWITCH__) & 0x7FFFFFFF); \
<> 149:156823d33999 713 } \
<> 149:156823d33999 714 else \
<> 149:156823d33999 715 { \
<> 149:156823d33999 716 SET_BIT(RI->ASCR2, (__IOSWITCH__)); \
<> 149:156823d33999 717 } \
<> 149:156823d33999 718 }while(0)
<> 149:156823d33999 719
<> 149:156823d33999 720 #define __HAL_RI_IOSWITCH_OPEN(__IOSWITCH__) do { assert_param(IS_RI_IOSWITCH(__IOSWITCH__)); \
<> 149:156823d33999 721 if ((__IOSWITCH__) >> 31 != 0 ) \
<> 149:156823d33999 722 { \
<> 149:156823d33999 723 CLEAR_BIT(RI->ASCR1, (__IOSWITCH__) & 0x7FFFFFFF); \
<> 149:156823d33999 724 } \
<> 149:156823d33999 725 else \
<> 149:156823d33999 726 { \
<> 149:156823d33999 727 CLEAR_BIT(RI->ASCR2, (__IOSWITCH__)); \
<> 149:156823d33999 728 } \
<> 149:156823d33999 729 }while(0)
<> 149:156823d33999 730
<> 149:156823d33999 731 #if defined (COMP_CSR_SW1)
<> 149:156823d33999 732 /**
<> 149:156823d33999 733 * @brief Close or open the internal switch COMP1_SW1.
<> 149:156823d33999 734 * This switch connects I/O pin PC3 (can be used as ADC channel 13)
<> 149:156823d33999 735 * and OPAMP3 ouput to ADC switch matrix (ADC channel VCOMP, channel
<> 149:156823d33999 736 * 26) and COMP1 non-inverting input.
<> 149:156823d33999 737 * Pin PC3 connection depends on another switch setting, refer to
<> 149:156823d33999 738 * macro "__HAL_ADC_CHANNEL_SPEED_FAST()".
<> 149:156823d33999 739 * @retval None.
<> 149:156823d33999 740 */
<> 149:156823d33999 741 #define __HAL_RI_SWITCH_COMP1_SW1_CLOSE() SET_BIT(COMP->CSR, COMP_CSR_SW1)
<> 149:156823d33999 742
<> 149:156823d33999 743 #define __HAL_RI_SWITCH_COMP1_SW1_OPEN() CLEAR_BIT(COMP->CSR, COMP_CSR_SW1)
<> 149:156823d33999 744 #endif /* COMP_CSR_SW1 */
<> 149:156823d33999 745
<> 149:156823d33999 746 /**
<> 149:156823d33999 747 * @}
<> 149:156823d33999 748 */
<> 149:156823d33999 749
<> 149:156823d33999 750 /** @defgroup RI_HystConfig Hysteresis Activation and Deactivation
<> 149:156823d33999 751 * @{
<> 149:156823d33999 752 */
<> 149:156823d33999 753
<> 149:156823d33999 754 /**
<> 149:156823d33999 755 * @brief Enable or disable Hysteresis of the input schmitt triger of Ports A
<> 149:156823d33999 756 * When the I/Os are programmed in input mode by standard I/O port
<> 149:156823d33999 757 * registers, the Schmitt trigger and the hysteresis are enabled by default.
<> 149:156823d33999 758 * When hysteresis is disabled, it is possible to read the
<> 149:156823d33999 759 * corresponding port with a trigger level of VDDIO/2.
<> 149:156823d33999 760 * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.
<> 149:156823d33999 761 * This parameter must be a value of @ref RI_Pin
<> 149:156823d33999 762 * @retval None
<> 149:156823d33999 763 */
<> 149:156823d33999 764 #define __HAL_RI_HYSTERIS_PORTA_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
<> 149:156823d33999 765 CLEAR_BIT(RI->HYSCR1, (__IOPIN__)); \
<> 149:156823d33999 766 } while(0)
<> 149:156823d33999 767
<> 149:156823d33999 768 #define __HAL_RI_HYSTERIS_PORTA_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
<> 149:156823d33999 769 SET_BIT(RI->HYSCR1, (__IOPIN__)); \
<> 149:156823d33999 770 } while(0)
<> 149:156823d33999 771
<> 149:156823d33999 772 /**
<> 149:156823d33999 773 * @brief Enable or disable Hysteresis of the input schmitt triger of Ports B
<> 149:156823d33999 774 * When the I/Os are programmed in input mode by standard I/O port
<> 149:156823d33999 775 * registers, the Schmitt trigger and the hysteresis are enabled by default.
<> 149:156823d33999 776 * When hysteresis is disabled, it is possible to read the
<> 149:156823d33999 777 * corresponding port with a trigger level of VDDIO/2.
<> 149:156823d33999 778 * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.
<> 149:156823d33999 779 * This parameter must be a value of @ref RI_Pin
<> 149:156823d33999 780 * @retval None
<> 149:156823d33999 781 */
<> 149:156823d33999 782 #define __HAL_RI_HYSTERIS_PORTB_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
<> 149:156823d33999 783 CLEAR_BIT(RI->HYSCR1, (__IOPIN__) << 16 ); \
<> 149:156823d33999 784 } while(0)
<> 149:156823d33999 785
<> 149:156823d33999 786 #define __HAL_RI_HYSTERIS_PORTB_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
<> 149:156823d33999 787 SET_BIT(RI->HYSCR1, (__IOPIN__) << 16 ); \
<> 149:156823d33999 788 } while(0)
<> 149:156823d33999 789
<> 149:156823d33999 790 /**
<> 149:156823d33999 791 * @brief Enable or disable Hysteresis of the input schmitt triger of Ports C
<> 149:156823d33999 792 * When the I/Os are programmed in input mode by standard I/O port
<> 149:156823d33999 793 * registers, the Schmitt trigger and the hysteresis are enabled by default.
<> 149:156823d33999 794 * When hysteresis is disabled, it is possible to read the
<> 149:156823d33999 795 * corresponding port with a trigger level of VDDIO/2.
<> 149:156823d33999 796 * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.
<> 149:156823d33999 797 * This parameter must be a value of @ref RI_Pin
<> 149:156823d33999 798 * @retval None
<> 149:156823d33999 799 */
<> 149:156823d33999 800 #define __HAL_RI_HYSTERIS_PORTC_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
<> 149:156823d33999 801 CLEAR_BIT(RI->HYSCR2, (__IOPIN__)); \
<> 149:156823d33999 802 } while(0)
<> 149:156823d33999 803
<> 149:156823d33999 804 #define __HAL_RI_HYSTERIS_PORTC_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
<> 149:156823d33999 805 SET_BIT(RI->HYSCR2, (__IOPIN__)); \
<> 149:156823d33999 806 } while(0)
<> 149:156823d33999 807
<> 149:156823d33999 808 /**
<> 149:156823d33999 809 * @brief Enable or disable Hysteresis of the input schmitt triger of Ports D
<> 149:156823d33999 810 * When the I/Os are programmed in input mode by standard I/O port
<> 149:156823d33999 811 * registers, the Schmitt trigger and the hysteresis are enabled by default.
<> 149:156823d33999 812 * When hysteresis is disabled, it is possible to read the
<> 149:156823d33999 813 * corresponding port with a trigger level of VDDIO/2.
<> 149:156823d33999 814 * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.
<> 149:156823d33999 815 * This parameter must be a value of @ref RI_Pin
<> 149:156823d33999 816 * @retval None
<> 149:156823d33999 817 */
<> 149:156823d33999 818 #define __HAL_RI_HYSTERIS_PORTD_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
<> 149:156823d33999 819 CLEAR_BIT(RI->HYSCR2, (__IOPIN__) << 16 ); \
<> 149:156823d33999 820 } while(0)
<> 149:156823d33999 821
<> 149:156823d33999 822 #define __HAL_RI_HYSTERIS_PORTD_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
<> 149:156823d33999 823 SET_BIT(RI->HYSCR2, (__IOPIN__) << 16 ); \
<> 149:156823d33999 824 } while(0)
<> 149:156823d33999 825
<> 149:156823d33999 826 #if defined (GPIOE_BASE)
<> 149:156823d33999 827
<> 149:156823d33999 828 /**
<> 149:156823d33999 829 * @brief Enable or disable Hysteresis of the input schmitt triger of Ports E
<> 149:156823d33999 830 * When the I/Os are programmed in input mode by standard I/O port
<> 149:156823d33999 831 * registers, the Schmitt trigger and the hysteresis are enabled by default.
<> 149:156823d33999 832 * When hysteresis is disabled, it is possible to read the
<> 149:156823d33999 833 * corresponding port with a trigger level of VDDIO/2.
<> 149:156823d33999 834 * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.
<> 149:156823d33999 835 * This parameter must be a value of @ref RI_Pin
<> 149:156823d33999 836 * @retval None
<> 149:156823d33999 837 */
<> 149:156823d33999 838 #define __HAL_RI_HYSTERIS_PORTE_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
<> 149:156823d33999 839 CLEAR_BIT(RI->HYSCR3, (__IOPIN__)); \
<> 149:156823d33999 840 } while(0)
<> 149:156823d33999 841
<> 149:156823d33999 842 #define __HAL_RI_HYSTERIS_PORTE_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
<> 149:156823d33999 843 SET_BIT(RI->HYSCR3, (__IOPIN__)); \
<> 149:156823d33999 844 } while(0)
<> 149:156823d33999 845
<> 149:156823d33999 846 #endif /* GPIOE_BASE */
<> 149:156823d33999 847
<> 149:156823d33999 848 #if defined(GPIOF_BASE) || defined(GPIOG_BASE)
<> 149:156823d33999 849
<> 149:156823d33999 850 /**
<> 149:156823d33999 851 * @brief Enable or disable Hysteresis of the input schmitt triger of Ports F
<> 149:156823d33999 852 * When the I/Os are programmed in input mode by standard I/O port
<> 149:156823d33999 853 * registers, the Schmitt trigger and the hysteresis are enabled by default.
<> 149:156823d33999 854 * When hysteresis is disabled, it is possible to read the
<> 149:156823d33999 855 * corresponding port with a trigger level of VDDIO/2.
<> 149:156823d33999 856 * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.
<> 149:156823d33999 857 * This parameter must be a value of @ref RI_Pin
<> 149:156823d33999 858 * @retval None
<> 149:156823d33999 859 */
<> 149:156823d33999 860 #define __HAL_RI_HYSTERIS_PORTF_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
<> 149:156823d33999 861 CLEAR_BIT(RI->HYSCR3, (__IOPIN__) << 16 ); \
<> 149:156823d33999 862 } while(0)
<> 149:156823d33999 863
<> 149:156823d33999 864 #define __HAL_RI_HYSTERIS_PORTF_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
<> 149:156823d33999 865 SET_BIT(RI->HYSCR3, (__IOPIN__) << 16 ); \
<> 149:156823d33999 866 } while(0)
<> 149:156823d33999 867
<> 149:156823d33999 868 /**
<> 149:156823d33999 869 * @brief Enable or disable Hysteresis of the input schmitt triger of Ports G
<> 149:156823d33999 870 * When the I/Os are programmed in input mode by standard I/O port
<> 149:156823d33999 871 * registers, the Schmitt trigger and the hysteresis are enabled by default.
<> 149:156823d33999 872 * When hysteresis is disabled, it is possible to read the
<> 149:156823d33999 873 * corresponding port with a trigger level of VDDIO/2.
<> 149:156823d33999 874 * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.
<> 149:156823d33999 875 * This parameter must be a value of @ref RI_Pin
<> 149:156823d33999 876 * @retval None
<> 149:156823d33999 877 */
<> 149:156823d33999 878 #define __HAL_RI_HYSTERIS_PORTG_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
<> 149:156823d33999 879 CLEAR_BIT(RI->HYSCR4, (__IOPIN__)); \
<> 149:156823d33999 880 } while(0)
<> 149:156823d33999 881
<> 149:156823d33999 882 #define __HAL_RI_HYSTERIS_PORTG_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
<> 149:156823d33999 883 SET_BIT(RI->HYSCR4, (__IOPIN__)); \
<> 149:156823d33999 884 } while(0)
<> 149:156823d33999 885
<> 149:156823d33999 886 #endif /* GPIOF_BASE || GPIOG_BASE */
<> 149:156823d33999 887
<> 149:156823d33999 888 /**
<> 149:156823d33999 889 * @}
<> 149:156823d33999 890 */
<> 149:156823d33999 891
<> 149:156823d33999 892 /**
<> 149:156823d33999 893 * @}
<> 149:156823d33999 894 */
<> 149:156823d33999 895
<> 149:156823d33999 896 /**
<> 149:156823d33999 897 * @}
<> 149:156823d33999 898 */
<> 149:156823d33999 899
<> 149:156823d33999 900 /* Exported functions --------------------------------------------------------*/
<> 149:156823d33999 901
<> 149:156823d33999 902 /** @addtogroup HAL_Exported_Functions
<> 149:156823d33999 903 * @{
<> 149:156823d33999 904 */
<> 149:156823d33999 905
<> 149:156823d33999 906 /** @addtogroup HAL_Exported_Functions_Group1
<> 149:156823d33999 907 * @{
<> 149:156823d33999 908 */
<> 149:156823d33999 909
<> 149:156823d33999 910 /* Initialization and de-initialization functions ******************************/
<> 149:156823d33999 911 HAL_StatusTypeDef HAL_Init(void);
<> 149:156823d33999 912 HAL_StatusTypeDef HAL_DeInit(void);
<> 149:156823d33999 913 void HAL_MspInit(void);
<> 149:156823d33999 914 void HAL_MspDeInit(void);
<> 149:156823d33999 915 HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
<> 149:156823d33999 916
<> 149:156823d33999 917 /**
<> 149:156823d33999 918 * @}
<> 149:156823d33999 919 */
<> 149:156823d33999 920
<> 149:156823d33999 921 /** @addtogroup HAL_Exported_Functions_Group2
<> 149:156823d33999 922 * @{
<> 149:156823d33999 923 */
<> 149:156823d33999 924
<> 149:156823d33999 925 /* Peripheral Control functions ************************************************/
<> 149:156823d33999 926 void HAL_IncTick(void);
<> 149:156823d33999 927 void HAL_Delay(__IO uint32_t Delay);
<> 149:156823d33999 928 uint32_t HAL_GetTick(void);
<> 149:156823d33999 929 void HAL_SuspendTick(void);
<> 149:156823d33999 930 void HAL_ResumeTick(void);
<> 149:156823d33999 931 uint32_t HAL_GetHalVersion(void);
<> 149:156823d33999 932 uint32_t HAL_GetREVID(void);
<> 149:156823d33999 933 uint32_t HAL_GetDEVID(void);
<> 149:156823d33999 934 void HAL_DBGMCU_EnableDBGSleepMode(void);
<> 149:156823d33999 935 void HAL_DBGMCU_DisableDBGSleepMode(void);
<> 149:156823d33999 936 void HAL_DBGMCU_EnableDBGStopMode(void);
<> 149:156823d33999 937 void HAL_DBGMCU_DisableDBGStopMode(void);
<> 149:156823d33999 938 void HAL_DBGMCU_EnableDBGStandbyMode(void);
<> 149:156823d33999 939 void HAL_DBGMCU_DisableDBGStandbyMode(void);
<> 149:156823d33999 940
<> 149:156823d33999 941 /**
<> 149:156823d33999 942 * @}
<> 149:156823d33999 943 */
<> 149:156823d33999 944
<> 149:156823d33999 945 /**
<> 149:156823d33999 946 * @}
<> 149:156823d33999 947 */
<> 149:156823d33999 948
<> 149:156823d33999 949
<> 149:156823d33999 950 /**
<> 149:156823d33999 951 * @}
<> 149:156823d33999 952 */
<> 149:156823d33999 953
<> 149:156823d33999 954 /**
<> 149:156823d33999 955 * @}
<> 149:156823d33999 956 */
<> 149:156823d33999 957
<> 149:156823d33999 958 #ifdef __cplusplus
<> 149:156823d33999 959 }
<> 149:156823d33999 960 #endif
<> 149:156823d33999 961
<> 149:156823d33999 962 #endif /* __STM32L1xx_HAL_H */
<> 149:156823d33999 963
<> 149:156823d33999 964 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/