mbed library sources. Supersedes mbed-src.
Fork of mbed-dev by
targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_wdog.h@150:02e0a0aed4ec, 2016-11-08 (annotated)
- Committer:
- <>
- Date:
- Tue Nov 08 17:45:16 2016 +0000
- Revision:
- 150:02e0a0aed4ec
This updates the lib to the mbed lib v129
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 150:02e0a0aed4ec | 1 | /**************************************************************************//** |
<> | 150:02e0a0aed4ec | 2 | * @file efm32wg_wdog.h |
<> | 150:02e0a0aed4ec | 3 | * @brief EFM32WG_WDOG register and bit field definitions |
<> | 150:02e0a0aed4ec | 4 | * @version 5.0.0 |
<> | 150:02e0a0aed4ec | 5 | ****************************************************************************** |
<> | 150:02e0a0aed4ec | 6 | * @section License |
<> | 150:02e0a0aed4ec | 7 | * <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b> |
<> | 150:02e0a0aed4ec | 8 | ****************************************************************************** |
<> | 150:02e0a0aed4ec | 9 | * |
<> | 150:02e0a0aed4ec | 10 | * Permission is granted to anyone to use this software for any purpose, |
<> | 150:02e0a0aed4ec | 11 | * including commercial applications, and to alter it and redistribute it |
<> | 150:02e0a0aed4ec | 12 | * freely, subject to the following restrictions: |
<> | 150:02e0a0aed4ec | 13 | * |
<> | 150:02e0a0aed4ec | 14 | * 1. The origin of this software must not be misrepresented; you must not |
<> | 150:02e0a0aed4ec | 15 | * claim that you wrote the original software.@n |
<> | 150:02e0a0aed4ec | 16 | * 2. Altered source versions must be plainly marked as such, and must not be |
<> | 150:02e0a0aed4ec | 17 | * misrepresented as being the original software.@n |
<> | 150:02e0a0aed4ec | 18 | * 3. This notice may not be removed or altered from any source distribution. |
<> | 150:02e0a0aed4ec | 19 | * |
<> | 150:02e0a0aed4ec | 20 | * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. |
<> | 150:02e0a0aed4ec | 21 | * has no obligation to support this Software. Silicon Laboratories, Inc. is |
<> | 150:02e0a0aed4ec | 22 | * providing the Software "AS IS", with no express or implied warranties of any |
<> | 150:02e0a0aed4ec | 23 | * kind, including, but not limited to, any implied warranties of |
<> | 150:02e0a0aed4ec | 24 | * merchantability or fitness for any particular purpose or warranties against |
<> | 150:02e0a0aed4ec | 25 | * infringement of any proprietary rights of a third party. |
<> | 150:02e0a0aed4ec | 26 | * |
<> | 150:02e0a0aed4ec | 27 | * Silicon Laboratories, Inc. will not be liable for any consequential, |
<> | 150:02e0a0aed4ec | 28 | * incidental, or special damages, or any other relief, or for any claim by |
<> | 150:02e0a0aed4ec | 29 | * any third party, arising from your use of this Software. |
<> | 150:02e0a0aed4ec | 30 | * |
<> | 150:02e0a0aed4ec | 31 | *****************************************************************************/ |
<> | 150:02e0a0aed4ec | 32 | /**************************************************************************//** |
<> | 150:02e0a0aed4ec | 33 | * @addtogroup Parts |
<> | 150:02e0a0aed4ec | 34 | * @{ |
<> | 150:02e0a0aed4ec | 35 | ******************************************************************************/ |
<> | 150:02e0a0aed4ec | 36 | /**************************************************************************//** |
<> | 150:02e0a0aed4ec | 37 | * @defgroup EFM32WG_WDOG |
<> | 150:02e0a0aed4ec | 38 | * @{ |
<> | 150:02e0a0aed4ec | 39 | * @brief EFM32WG_WDOG Register Declaration |
<> | 150:02e0a0aed4ec | 40 | *****************************************************************************/ |
<> | 150:02e0a0aed4ec | 41 | typedef struct |
<> | 150:02e0a0aed4ec | 42 | { |
<> | 150:02e0a0aed4ec | 43 | __IOM uint32_t CTRL; /**< Control Register */ |
<> | 150:02e0a0aed4ec | 44 | __IOM uint32_t CMD; /**< Command Register */ |
<> | 150:02e0a0aed4ec | 45 | |
<> | 150:02e0a0aed4ec | 46 | __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ |
<> | 150:02e0a0aed4ec | 47 | } WDOG_TypeDef; /** @} */ |
<> | 150:02e0a0aed4ec | 48 | |
<> | 150:02e0a0aed4ec | 49 | /**************************************************************************//** |
<> | 150:02e0a0aed4ec | 50 | * @defgroup EFM32WG_WDOG_BitFields |
<> | 150:02e0a0aed4ec | 51 | * @{ |
<> | 150:02e0a0aed4ec | 52 | *****************************************************************************/ |
<> | 150:02e0a0aed4ec | 53 | |
<> | 150:02e0a0aed4ec | 54 | /* Bit fields for WDOG CTRL */ |
<> | 150:02e0a0aed4ec | 55 | #define _WDOG_CTRL_RESETVALUE 0x00000F00UL /**< Default value for WDOG_CTRL */ |
<> | 150:02e0a0aed4ec | 56 | #define _WDOG_CTRL_MASK 0x00003F7FUL /**< Mask for WDOG_CTRL */ |
<> | 150:02e0a0aed4ec | 57 | #define WDOG_CTRL_EN (0x1UL << 0) /**< Watchdog Timer Enable */ |
<> | 150:02e0a0aed4ec | 58 | #define _WDOG_CTRL_EN_SHIFT 0 /**< Shift value for WDOG_EN */ |
<> | 150:02e0a0aed4ec | 59 | #define _WDOG_CTRL_EN_MASK 0x1UL /**< Bit mask for WDOG_EN */ |
<> | 150:02e0a0aed4ec | 60 | #define _WDOG_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ |
<> | 150:02e0a0aed4ec | 61 | #define WDOG_CTRL_EN_DEFAULT (_WDOG_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_CTRL */ |
<> | 150:02e0a0aed4ec | 62 | #define WDOG_CTRL_DEBUGRUN (0x1UL << 1) /**< Debug Mode Run Enable */ |
<> | 150:02e0a0aed4ec | 63 | #define _WDOG_CTRL_DEBUGRUN_SHIFT 1 /**< Shift value for WDOG_DEBUGRUN */ |
<> | 150:02e0a0aed4ec | 64 | #define _WDOG_CTRL_DEBUGRUN_MASK 0x2UL /**< Bit mask for WDOG_DEBUGRUN */ |
<> | 150:02e0a0aed4ec | 65 | #define _WDOG_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ |
<> | 150:02e0a0aed4ec | 66 | #define WDOG_CTRL_DEBUGRUN_DEFAULT (_WDOG_CTRL_DEBUGRUN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_CTRL */ |
<> | 150:02e0a0aed4ec | 67 | #define WDOG_CTRL_EM2RUN (0x1UL << 2) /**< Energy Mode 2 Run Enable */ |
<> | 150:02e0a0aed4ec | 68 | #define _WDOG_CTRL_EM2RUN_SHIFT 2 /**< Shift value for WDOG_EM2RUN */ |
<> | 150:02e0a0aed4ec | 69 | #define _WDOG_CTRL_EM2RUN_MASK 0x4UL /**< Bit mask for WDOG_EM2RUN */ |
<> | 150:02e0a0aed4ec | 70 | #define _WDOG_CTRL_EM2RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ |
<> | 150:02e0a0aed4ec | 71 | #define WDOG_CTRL_EM2RUN_DEFAULT (_WDOG_CTRL_EM2RUN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_CTRL */ |
<> | 150:02e0a0aed4ec | 72 | #define WDOG_CTRL_EM3RUN (0x1UL << 3) /**< Energy Mode 3 Run Enable */ |
<> | 150:02e0a0aed4ec | 73 | #define _WDOG_CTRL_EM3RUN_SHIFT 3 /**< Shift value for WDOG_EM3RUN */ |
<> | 150:02e0a0aed4ec | 74 | #define _WDOG_CTRL_EM3RUN_MASK 0x8UL /**< Bit mask for WDOG_EM3RUN */ |
<> | 150:02e0a0aed4ec | 75 | #define _WDOG_CTRL_EM3RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ |
<> | 150:02e0a0aed4ec | 76 | #define WDOG_CTRL_EM3RUN_DEFAULT (_WDOG_CTRL_EM3RUN_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_CTRL */ |
<> | 150:02e0a0aed4ec | 77 | #define WDOG_CTRL_LOCK (0x1UL << 4) /**< Configuration lock */ |
<> | 150:02e0a0aed4ec | 78 | #define _WDOG_CTRL_LOCK_SHIFT 4 /**< Shift value for WDOG_LOCK */ |
<> | 150:02e0a0aed4ec | 79 | #define _WDOG_CTRL_LOCK_MASK 0x10UL /**< Bit mask for WDOG_LOCK */ |
<> | 150:02e0a0aed4ec | 80 | #define _WDOG_CTRL_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ |
<> | 150:02e0a0aed4ec | 81 | #define WDOG_CTRL_LOCK_DEFAULT (_WDOG_CTRL_LOCK_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_CTRL */ |
<> | 150:02e0a0aed4ec | 82 | #define WDOG_CTRL_EM4BLOCK (0x1UL << 5) /**< Energy Mode 4 Block */ |
<> | 150:02e0a0aed4ec | 83 | #define _WDOG_CTRL_EM4BLOCK_SHIFT 5 /**< Shift value for WDOG_EM4BLOCK */ |
<> | 150:02e0a0aed4ec | 84 | #define _WDOG_CTRL_EM4BLOCK_MASK 0x20UL /**< Bit mask for WDOG_EM4BLOCK */ |
<> | 150:02e0a0aed4ec | 85 | #define _WDOG_CTRL_EM4BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ |
<> | 150:02e0a0aed4ec | 86 | #define WDOG_CTRL_EM4BLOCK_DEFAULT (_WDOG_CTRL_EM4BLOCK_DEFAULT << 5) /**< Shifted mode DEFAULT for WDOG_CTRL */ |
<> | 150:02e0a0aed4ec | 87 | #define WDOG_CTRL_SWOSCBLOCK (0x1UL << 6) /**< Software Oscillator Disable Block */ |
<> | 150:02e0a0aed4ec | 88 | #define _WDOG_CTRL_SWOSCBLOCK_SHIFT 6 /**< Shift value for WDOG_SWOSCBLOCK */ |
<> | 150:02e0a0aed4ec | 89 | #define _WDOG_CTRL_SWOSCBLOCK_MASK 0x40UL /**< Bit mask for WDOG_SWOSCBLOCK */ |
<> | 150:02e0a0aed4ec | 90 | #define _WDOG_CTRL_SWOSCBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ |
<> | 150:02e0a0aed4ec | 91 | #define WDOG_CTRL_SWOSCBLOCK_DEFAULT (_WDOG_CTRL_SWOSCBLOCK_DEFAULT << 6) /**< Shifted mode DEFAULT for WDOG_CTRL */ |
<> | 150:02e0a0aed4ec | 92 | #define _WDOG_CTRL_PERSEL_SHIFT 8 /**< Shift value for WDOG_PERSEL */ |
<> | 150:02e0a0aed4ec | 93 | #define _WDOG_CTRL_PERSEL_MASK 0xF00UL /**< Bit mask for WDOG_PERSEL */ |
<> | 150:02e0a0aed4ec | 94 | #define _WDOG_CTRL_PERSEL_DEFAULT 0x0000000FUL /**< Mode DEFAULT for WDOG_CTRL */ |
<> | 150:02e0a0aed4ec | 95 | #define WDOG_CTRL_PERSEL_DEFAULT (_WDOG_CTRL_PERSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WDOG_CTRL */ |
<> | 150:02e0a0aed4ec | 96 | #define _WDOG_CTRL_CLKSEL_SHIFT 12 /**< Shift value for WDOG_CLKSEL */ |
<> | 150:02e0a0aed4ec | 97 | #define _WDOG_CTRL_CLKSEL_MASK 0x3000UL /**< Bit mask for WDOG_CLKSEL */ |
<> | 150:02e0a0aed4ec | 98 | #define _WDOG_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ |
<> | 150:02e0a0aed4ec | 99 | #define _WDOG_CTRL_CLKSEL_ULFRCO 0x00000000UL /**< Mode ULFRCO for WDOG_CTRL */ |
<> | 150:02e0a0aed4ec | 100 | #define _WDOG_CTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for WDOG_CTRL */ |
<> | 150:02e0a0aed4ec | 101 | #define _WDOG_CTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for WDOG_CTRL */ |
<> | 150:02e0a0aed4ec | 102 | #define WDOG_CTRL_CLKSEL_DEFAULT (_WDOG_CTRL_CLKSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for WDOG_CTRL */ |
<> | 150:02e0a0aed4ec | 103 | #define WDOG_CTRL_CLKSEL_ULFRCO (_WDOG_CTRL_CLKSEL_ULFRCO << 12) /**< Shifted mode ULFRCO for WDOG_CTRL */ |
<> | 150:02e0a0aed4ec | 104 | #define WDOG_CTRL_CLKSEL_LFRCO (_WDOG_CTRL_CLKSEL_LFRCO << 12) /**< Shifted mode LFRCO for WDOG_CTRL */ |
<> | 150:02e0a0aed4ec | 105 | #define WDOG_CTRL_CLKSEL_LFXO (_WDOG_CTRL_CLKSEL_LFXO << 12) /**< Shifted mode LFXO for WDOG_CTRL */ |
<> | 150:02e0a0aed4ec | 106 | |
<> | 150:02e0a0aed4ec | 107 | /* Bit fields for WDOG CMD */ |
<> | 150:02e0a0aed4ec | 108 | #define _WDOG_CMD_RESETVALUE 0x00000000UL /**< Default value for WDOG_CMD */ |
<> | 150:02e0a0aed4ec | 109 | #define _WDOG_CMD_MASK 0x00000001UL /**< Mask for WDOG_CMD */ |
<> | 150:02e0a0aed4ec | 110 | #define WDOG_CMD_CLEAR (0x1UL << 0) /**< Watchdog Timer Clear */ |
<> | 150:02e0a0aed4ec | 111 | #define _WDOG_CMD_CLEAR_SHIFT 0 /**< Shift value for WDOG_CLEAR */ |
<> | 150:02e0a0aed4ec | 112 | #define _WDOG_CMD_CLEAR_MASK 0x1UL /**< Bit mask for WDOG_CLEAR */ |
<> | 150:02e0a0aed4ec | 113 | #define _WDOG_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CMD */ |
<> | 150:02e0a0aed4ec | 114 | #define _WDOG_CMD_CLEAR_UNCHANGED 0x00000000UL /**< Mode UNCHANGED for WDOG_CMD */ |
<> | 150:02e0a0aed4ec | 115 | #define _WDOG_CMD_CLEAR_CLEARED 0x00000001UL /**< Mode CLEARED for WDOG_CMD */ |
<> | 150:02e0a0aed4ec | 116 | #define WDOG_CMD_CLEAR_DEFAULT (_WDOG_CMD_CLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_CMD */ |
<> | 150:02e0a0aed4ec | 117 | #define WDOG_CMD_CLEAR_UNCHANGED (_WDOG_CMD_CLEAR_UNCHANGED << 0) /**< Shifted mode UNCHANGED for WDOG_CMD */ |
<> | 150:02e0a0aed4ec | 118 | #define WDOG_CMD_CLEAR_CLEARED (_WDOG_CMD_CLEAR_CLEARED << 0) /**< Shifted mode CLEARED for WDOG_CMD */ |
<> | 150:02e0a0aed4ec | 119 | |
<> | 150:02e0a0aed4ec | 120 | /* Bit fields for WDOG SYNCBUSY */ |
<> | 150:02e0a0aed4ec | 121 | #define _WDOG_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for WDOG_SYNCBUSY */ |
<> | 150:02e0a0aed4ec | 122 | #define _WDOG_SYNCBUSY_MASK 0x00000003UL /**< Mask for WDOG_SYNCBUSY */ |
<> | 150:02e0a0aed4ec | 123 | #define WDOG_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Register Busy */ |
<> | 150:02e0a0aed4ec | 124 | #define _WDOG_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for WDOG_CTRL */ |
<> | 150:02e0a0aed4ec | 125 | #define _WDOG_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for WDOG_CTRL */ |
<> | 150:02e0a0aed4ec | 126 | #define _WDOG_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */ |
<> | 150:02e0a0aed4ec | 127 | #define WDOG_SYNCBUSY_CTRL_DEFAULT (_WDOG_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */ |
<> | 150:02e0a0aed4ec | 128 | #define WDOG_SYNCBUSY_CMD (0x1UL << 1) /**< CMD Register Busy */ |
<> | 150:02e0a0aed4ec | 129 | #define _WDOG_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for WDOG_CMD */ |
<> | 150:02e0a0aed4ec | 130 | #define _WDOG_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for WDOG_CMD */ |
<> | 150:02e0a0aed4ec | 131 | #define _WDOG_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */ |
<> | 150:02e0a0aed4ec | 132 | #define WDOG_SYNCBUSY_CMD_DEFAULT (_WDOG_SYNCBUSY_CMD_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */ |
<> | 150:02e0a0aed4ec | 133 | |
<> | 150:02e0a0aed4ec | 134 | /** @} End of group EFM32WG_WDOG */ |
<> | 150:02e0a0aed4ec | 135 | /** @} End of group Parts */ |
<> | 150:02e0a0aed4ec | 136 |