Seungchan Lee
/
210714_ads1299_ex3_multi_reg_control
ADS1299 multi register control test
Embed:
(wiki syntax)
Show/hide line numbers
main.cpp
00001 #include "mbed.h" 00002 // Programed by Seungchan Lee, futuremax7@gmail.com 00003 // 2021.07.15 00004 00005 //Serial pc(USBTX, USBRX); 00006 static UARTSerial pc(USBTX, USBRX, 115200); 00007 00008 InterruptIn drdy(D10); 00009 SPI ads1299(D11, D12, D13); // mosi, miso, sclk 00010 DigitalOut cs(D9); 00011 DigitalOut reset(A1); 00012 DigitalOut pwdn(A2); 00013 DigitalOut start(A0); 00014 00015 //SPI Command Definition Byte Assignments (Datasheet, p35) 00016 #define _WAKEUP 0x02 // Wake-up from standby mode 00017 #define _STANDBY 0x04 // Enter Standby mode 00018 #define _RESET 0x06 // Reset the device 00019 #define _START 0x08 // Start and restart (synchronize) conversions 00020 #define _STOP 0x0A // Stop conversion 00021 #define _RDATAC 0x10 // Enable Read Data Continuous mode (default mode at power-up) 00022 #define _SDATAC 0x11 // Stop Read Data Continuous mode 00023 #define _RDATA 0x12 // Read data by command; supports multiple read back 00024 00025 //Register Addresses 00026 #define ID 0x00 00027 #define CONFIG1 0x01 00028 #define CONFIG2 0x02 00029 #define CONFIG3 0x03 00030 #define LOFF 0x04 00031 #define CH1SET 0x05 00032 #define CH2SET 0x06 00033 #define CH3SET 0x07 00034 #define CH4SET 0x08 00035 #define CH5SET 0x09 00036 #define CH6SET 0x0A 00037 #define CH7SET 0x0B 00038 #define CH8SET 0x0C 00039 #define BIAS_SENSP 0x0D 00040 #define BIAS_SENSN 0x0E 00041 #define LOFF_SENSP 0x0F 00042 #define LOFF_SENSN 0x10 00043 #define LOFF_FLIP 0x11 00044 #define LOFF_STATP 0x12 00045 #define LOFF_STATN 0x13 00046 #define GPIO 0x14 00047 #define MISC1 0x15 00048 #define MISC2 0x16 00049 #define CONFIG4 0x17 00050 00051 #define REG_LENGTH 0x18 00052 #define REG_UPPER_START 0x01 00053 #define REG_UPPER_LENGTH 0x11 00054 #define REG_LOWER_START 0x14 00055 #define REG_LOWER_LENGTH 0x04 00056 00057 #define BYTE_DATA 28 00058 #define BYTE_HEADER 2 00059 #define BYTE_INFO 1 00060 #define DATA_LENGTH (BYTE_DATA+BYTE_HEADER+BYTE_INFO) 00061 00062 char ads1299_reg_data0[REG_LENGTH] = {0x3C, 0x96, 0xC0, 0x60, 0x00, 0x61, 0x61, 0x61, 0x61, 0x00, 0x00, 0x00, 0x00, 00063 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00}; 00064 char ads1299_reg_data1[REG_LENGTH] = {0x3C, 0x96, 0xD0, 0xFC, 0x00, 0x65, 0x65, 0x61, 0x60, 0x00, 0x00, 0x00, 0x00, 00065 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; 00066 char ads1299_reg_buf[REG_LENGTH] = {0}; 00067 00068 void ads1299_command(char command) 00069 { 00070 cs = 0; 00071 ads1299.write(command); 00072 cs = 1; 00073 wait(0.01); // 100 ms 00074 } 00075 00076 char ads1299_rreg(char address) 00077 { 00078 char opcode1 = address + 0x20; // RREG expects 001rrrrr where rrrrr = _address 00079 cs = 0; // open SPI 00080 ads1299.write(opcode1); // opcode1 00081 ads1299.write(0x00); // opcode2 00082 ads1299_reg_buf[address] = ads1299.write(0x00); // update mirror location with returned byte 00083 cs = 1; // close SPI 00084 printf("RREG 0x%0X = 0x%0X\n", address, ads1299_reg_buf[address]); 00085 00086 return ads1299_reg_buf[address]; // return requested register value 00087 } 00088 00089 void ads1299_rregs() 00090 { 00091 const char tx_buf[REG_LENGTH]={0}; 00092 00093 cs = 0; // open SPI 00094 ads1299.write(0x20); // opcode1 00095 ads1299.write(REG_LENGTH-1); // opcode2 00096 ads1299.write(tx_buf, REG_LENGTH, ads1299_reg_buf, REG_LENGTH); 00097 cs = 1; // close SPI 00098 for (char n = 0; n<REG_LENGTH; n++) 00099 { 00100 printf("RREG 0x%0X = 0x%0X\n", n, ads1299_reg_buf[n]); 00101 } 00102 } 00103 00104 void ads1299_wreg(char address, char data) 00105 { 00106 char opcode1 = address + 0x40; // RREG expects 001rrrrr where rrrrr = _address 00107 cs = 0; // open SPI 00108 ads1299.write(opcode1); // opcode1 00109 ads1299.write(0x00); // opcode2 00110 ads1299.write(data); // update mirror location with returned byte 00111 cs = 1; // close SPI 00112 00113 // char check = ads1299_rreg(address); 00114 // printf("WREG 0x%X = 0x%X\n", address, check); 00115 } 00116 00117 void ads1299_wregs_upper(char* data) 00118 { 00119 char rx_buf[REG_UPPER_LENGTH]={0}; 00120 00121 cs = 0; // open SPI 00122 ads1299.write(0x40+REG_UPPER_START); // opcode1 00123 ads1299.write(REG_UPPER_LENGTH-1); // opcode2 00124 ads1299.write(data+REG_UPPER_START, REG_UPPER_LENGTH, rx_buf, REG_UPPER_LENGTH); 00125 cs = 1; // close SPI 00126 00127 // printf("WREG ALL check!\n"); 00128 // ads1299_rregs(); 00129 } 00130 00131 void ads1299_wregs_lower(char* data) 00132 { 00133 char rx_buf[REG_LOWER_LENGTH]={0}; 00134 00135 cs = 0; // open SPI 00136 ads1299.write(0x40+REG_LOWER_START); // opcode1 00137 ads1299.write(REG_LOWER_LENGTH-1); // opcode2 00138 ads1299.write(data+REG_LOWER_START, REG_LOWER_LENGTH, rx_buf, REG_LOWER_LENGTH); 00139 cs = 1; // close SPI 00140 00141 // printf("WREG ALL check!\n"); 00142 // ads1299_rregs(); 00143 } 00144 00145 //------------------------------------------------------------------------------------------------------- 00146 00147 int main() { 00148 // pc.baud(115200); 00149 00150 // GPIO setting 00151 reset = 1; 00152 pwdn = 1; 00153 start = 0; 00154 cs = 1; 00155 00156 // Setup the ads1299 for 8 bit data, high steady state clock, 00157 // second edge capture, with a 1MHz clock rate 00158 ads1299.format(8,1); 00159 ads1299.frequency(10000000); 00160 wait(0.1); 00161 00162 cs = 0; 00163 ads1299.write(0x06); //RESET 00164 cs = 1; 00165 wait(0.5); // 100 ms 00166 00167 cs = 0; 00168 ads1299.write(0x11); //SDATAC 00169 cs = 1; 00170 wait(0.1); // 100 ms 00171 00172 while(1) 00173 { 00174 printf("REG SET0 WREGS\n"); 00175 ads1299_wregs_upper(ads1299_reg_data0); 00176 ads1299_wregs_lower(ads1299_reg_data0); 00177 ads1299_rregs(); 00178 wait(0.5); 00179 00180 printf("REG SET1 WREGS\n"); 00181 ads1299_wregs_upper(ads1299_reg_data1); 00182 ads1299_wregs_lower(ads1299_reg_data1); 00183 ads1299_rregs(); 00184 wait(0.5); 00185 } 00186 }
Generated on Sat Jul 16 2022 11:04:19 by 1.7.2