Revision 50:a417edff4437, committed 2016-01-15

Comitter:

mbed_official

Date:

Fri Jan 15 07:45:16 2016 +0000

Parent:

49:57ac6e3cdfd3

Child:

51:2dcb841baa4f

Commit message:

Synchronized with git revision 6010f32619bfcbb01cc73747d4ff9040863482d9

Full URL: https://github.com/mbedmicro/mbed/commit/6010f32619bfcbb01cc73747d4ff9040863482d9/

Remove doubling of buffer size in realiseEndpoint()

Changed in this revision

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/TOOLCHAIN_ARM_MICRO/efm32gg.sct	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/TOOLCHAIN_ARM_MICRO/efm32gg.sct	Fri Jan 15 07:45:16 2016 +0000
@@ -8,7 +8,7 @@
    *(InRoot$$Sections)
    .ANY (+RO)
   }
-  RW_IRAM1 0x200000E0 0x0001FF20  {  ; RW data
+  RW_IRAM1 0x200000DC 0x0001FF24  {  ; RW data
    .ANY (+RW +ZI)
   }
 }

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/TOOLCHAIN_ARM_MICRO/startup_efm32gg.S	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/TOOLCHAIN_ARM_MICRO/startup_efm32gg.S	Fri Jan 15 07:45:16 2016 +0000
@@ -2,7 +2,7 @@
 ; * @file startup_efm32gg.s
 ; * @brief    CMSIS Core Device Startup File for
 ; *           Silicon Labs EFM32GG Device Series
-; * @version 3.20.6
+; * @version 4.2.1
 ; * @date     03. February 2012
 ; *
 ; * @note
@@ -262,10 +262,7 @@
 AES_IRQHandler
 EBI_IRQHandler
 EMU_IRQHandler
-
-
                 B       .
-
                 ENDP
 
                 ALIGN

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/TOOLCHAIN_ARM_STD/efm32gg.sct	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/TOOLCHAIN_ARM_STD/efm32gg.sct	Fri Jan 15 07:45:16 2016 +0000
@@ -8,7 +8,7 @@
    *(InRoot$$Sections)
    .ANY (+RO)
   }
-  RW_IRAM1 0x200000E0 0x0001FF20  {  ; RW data
+  RW_IRAM1 0x200000DC 0x0001FF24  {  ; RW data
    .ANY (+RW +ZI)
   }
 }

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/TOOLCHAIN_ARM_STD/startup_efm32gg.S	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/TOOLCHAIN_ARM_STD/startup_efm32gg.S	Fri Jan 15 07:45:16 2016 +0000
@@ -2,7 +2,7 @@
 ; * @file startup_efm32gg.s
 ; * @brief    CMSIS Core Device Startup File for
 ; *           Silicon Labs EFM32GG Device Series
-; * @version 3.20.6
+; * @version 4.2.1
 ; * @date     03. February 2012
 ; *
 ; * @note
@@ -262,10 +262,7 @@
 AES_IRQHandler
 EBI_IRQHandler
 EMU_IRQHandler
-
-
                 B       .
-
                 ENDP
 
                 ALIGN

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/TOOLCHAIN_GCC_ARM/efm32gg.ld	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/TOOLCHAIN_GCC_ARM/efm32gg.ld	Fri Jan 15 07:45:16 2016 +0000
@@ -4,7 +4,11 @@
 /* CMSIS END USER LICENSE AGREEMENT.pdf, governing the use of       */
 /* Example Code.                                                    */
 /*                                                                  */
-/* Silicon Laboratories, Inc. 2014                                  */
+/* Silicon Laboratories, Inc. 2015                                  */
+/*                                                                  */
+/* Version 4.2.0 */
+/*                                                                  */
+
 MEMORY
 {
   FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 1048576
@@ -13,16 +17,20 @@
 /* MBED: mbed needs to be able to dynamically set the interrupt vector table.
  * We make room for the table at the very beginning of RAM, i.e. at
  * 0x20000000. We need (16+39) * sizeof(uint32_t) = 220 bytes for EFM32GG */
-__vector_size = 0xE0;
+__vector_size = 0xDC;
 
 /* Linker script to place sections and symbol values. Should be used together
  * with other linker script that defines memory regions FLASH and RAM.
  * It references following symbols, which must be defined in code:
  *   Reset_Handler : Entry of reset handler
- * 
+ *
  * It defines following symbols, which code can use without definition:
  *   __exidx_start
  *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
  *   __etext
  *   __data_start__
  *   __preinit_array_start
@@ -40,6 +48,8 @@
  *   __StackLimit
  *   __StackTop
  *   __stack
+ *   __Vectors_End
+ *   __Vectors_Size
  */
 ENTRY(Reset_Handler)
 
@@ -47,7 +57,11 @@
 {
   .text :
   {
-    KEEP(*(.isr_vector))
+    KEEP(*(.vectors))
+    __Vectors_End = .;
+    __Vectors_Size = __Vectors_End - __Vectors;
+    __end__ = .;
+
     *(.text*)
 
     KEEP(*(.init))
@@ -72,7 +86,7 @@
     KEEP(*(.eh_frame*))
   } > FLASH
 
-  .ARM.extab : 
+  .ARM.extab :
   {
     *(.ARM.extab* .gnu.linkonce.armextab.*)
   } > FLASH
@@ -84,15 +98,49 @@
   } > FLASH
   __exidx_end = .;
 
+  /* To copy multiple ROM to RAM sections,
+   * uncomment .copy.table section and,
+   * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+  /*
+  .copy.table :
+  {
+    . = ALIGN(4);
+    __copy_table_start__ = .;
+    LONG (__etext)
+    LONG (__data_start__)
+    LONG (__data_end__ - __data_start__)
+    LONG (__etext2)
+    LONG (__data2_start__)
+    LONG (__data2_end__ - __data2_start__)
+    __copy_table_end__ = .;
+  } > FLASH
+  */
+
+  /* To clear multiple BSS sections,
+   * uncomment .zero.table section and,
+   * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+  /*
+  .zero.table :
+  {
+    . = ALIGN(4);
+    __zero_table_start__ = .;
+    LONG (__bss_start__)
+    LONG (__bss_end__ - __bss_start__)
+    LONG (__bss2_start__)
+    LONG (__bss2_end__ - __bss2_start__)
+    __zero_table_end__ = .;
+  } > FLASH
+  */
+
   __etext = .;
-  
+
   .data : AT (__etext)
   {
     __data_start__ = .;
     *("dma")
     PROVIDE( __start_vector_table__ = .);
-  	. += __vector_size;
-  	PROVIDE( __end_vector_table__ = .);
+    . += __vector_size;
+    PROVIDE( __end_vector_table__ = .);
     *(vtable)
     *(.data*)
     . = ALIGN (4);
@@ -118,6 +166,7 @@
     KEEP(*(.fini_array))
     PROVIDE_HIDDEN (__fini_array_end = .);
 
+    KEEP(*(.jcr*))
     . = ALIGN(4);
     /* All data end */
     __data_end__ = .;
@@ -126,27 +175,30 @@
 
   .bss :
   {
+    . = ALIGN(4);
     __bss_start__ = .;
     *(.bss*)
     *(COMMON)
+    . = ALIGN(4);
     __bss_end__ = .;
   } > RAM
 
-  .heap :
+  .heap (COPY):
   {
+    __HeapBase = .;
     __end__ = .;
     end = __end__;
     _end = __end__;
-    *(.heap*)
+    KEEP(*(.heap*))
     __HeapLimit = .;
   } > RAM
 
   /* .stack_dummy section doesn't contains any symbols. It is only
    * used for linker to calculate size of stack sections, and assign
    * values to stack symbols later */
-  .stack_dummy :
+  .stack_dummy (COPY):
   {
-    *(.stack)
+    KEEP(*(.stack*))
   } > RAM
 
   /* Set stack top to end of RAM, and stack limit move down by
@@ -157,4 +209,7 @@
 
   /* Check if data + heap + stack exceeds RAM limit */
   ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+
+  /* Check if FLASH usage exceeds FLASH size */
+  ASSERT( LENGTH(FLASH) >= (__etext + SIZEOF(.data)), "FLASH memory overflowed !")
 }

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/TOOLCHAIN_GCC_ARM/startup_efm32gg.S	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/TOOLCHAIN_GCC_ARM/startup_efm32gg.S	Fri Jan 15 07:45:16 2016 +0000
@@ -1,233 +1,338 @@
 /* @file startup_efm32gg.S
  * @brief startup file for Silicon Labs EFM32GG devices.
  *        For use with GCC for ARM Embedded Processors
- * @version 3.20.6
- * Date: 08 Feb 2012
- *
- * Copyright (c) 2012, ARM Limited
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
-    * Redistributions of source code must retain the above copyright
-      notice, this list of conditions and the following disclaimer.
-    * Redistributions in binary form must reproduce the above copyright
-      notice, this list of conditions and the following disclaimer in the
-      documentation and/or other materials provided with the distribution.
-    * Neither the name of the ARM Limited nor the
-      names of its contributors may be used to endorse or promote products
-      derived from this software without specific prior written permission.
+ * @version 4.2.1
+ * Date:    12 June 2014
  *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
-    .syntax unified
-    .arch armv7-m
+/* Copyright (c) 2011 - 2014 ARM LIMITED
 
-    .section .stack
-    .align 3
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+    .syntax     unified
+    .arch       armv7-m
+    .section    .stack
+    .align      3
 #ifdef __STACK_SIZE
-    .equ    Stack_Size, __STACK_SIZE
+    .equ        Stack_Size, __STACK_SIZE
 #else
-    .equ    Stack_Size, 0x400
+    .equ        Stack_Size, 0x00000400
 #endif
-    .globl    __StackTop
-    .globl    __StackLimit
+    .globl      __StackTop
+    .globl      __StackLimit
 __StackLimit:
-    .space    Stack_Size
-    .size __StackLimit, . - __StackLimit
+    .space      Stack_Size
+    .size       __StackLimit, . - __StackLimit
 __StackTop:
-    .size __StackTop, . - __StackTop
+    .size       __StackTop, . - __StackTop
 
-    .section .heap
-    .align 3
+    .section    .heap
+    .align      3
 #ifdef __HEAP_SIZE
-    .equ    Heap_Size, __HEAP_SIZE
+    .equ        Heap_Size, __HEAP_SIZE
 #else
-    .equ    Heap_Size, 0xC00
+    .equ        Heap_Size, 0x00000C00
 #endif
-    .globl    __HeapBase
-    .globl    __HeapLimit
+    .globl      __HeapBase
+    .globl      __HeapLimit
 __HeapBase:
-    .if    Heap_Size
-    .space    Heap_Size
+    .if Heap_Size
+    .space      Heap_Size
     .endif
-    .size __HeapBase, . - __HeapBase
+    .size       __HeapBase, . - __HeapBase
 __HeapLimit:
-    .size __HeapLimit, . - __HeapLimit
+    .size       __HeapLimit, . - __HeapLimit
 
-    .section .isr_vector
-    .align 8
-    .globl __isr_vector
-__isr_vector:
-    .long    __StackTop            /* Top of Stack */
-    .long    Reset_Handler         /* Reset Handler */
-    .long    NMI_Handler           /* NMI Handler */
-    .long    HardFault_Handler     /* Hard Fault Handler */
-    .long    MemManage_Handler     /* MPU Fault Handler */
-    .long    BusFault_Handler      /* Bus Fault Handler */
-    .long    UsageFault_Handler    /* Usage Fault Handler */
-    .long    Default_Handler       /* Reserved */
-    .long    Default_Handler       /* Reserved */
-    .long    Default_Handler       /* Reserved */
-    .long    Default_Handler       /* Reserved */
-    .long    SVC_Handler           /* SVCall Handler */
-    .long    DebugMon_Handler      /* Debug Monitor Handler */
-    .long    Default_Handler       /* Reserved */
-    .long    PendSV_Handler        /* PendSV Handler */
-    .long    SysTick_Handler       /* SysTick Handler */
+    .section    .vectors
+    .align      2
+    .globl      __Vectors
+__Vectors:
+    .long       __StackTop            /* Top of Stack */
+    .long       Reset_Handler         /* Reset Handler */
+    .long       NMI_Handler           /* NMI Handler */
+    .long       HardFault_Handler     /* Hard Fault Handler */
+    .long       MemManage_Handler     /* MPU Fault Handler */
+    .long       BusFault_Handler      /* Bus Fault Handler */
+    .long       UsageFault_Handler    /* Usage Fault Handler */
+    .long       Default_Handler       /* Reserved */
+    .long       Default_Handler       /* Reserved */
+    .long       Default_Handler       /* Reserved */
+    .long       Default_Handler       /* Reserved */
+    .long       SVC_Handler           /* SVCall Handler */
+    .long       DebugMon_Handler      /* Debug Monitor Handler */
+    .long       Default_Handler       /* Reserved */
+    .long       PendSV_Handler        /* PendSV Handler */
+    .long       SysTick_Handler       /* SysTick Handler */
 
     /* External interrupts */
-    .long    DMA_IRQHandler    /* 0 - DMA */
-    .long    GPIO_EVEN_IRQHandler    /* 1 - GPIO_EVEN */
-    .long    TIMER0_IRQHandler    /* 2 - TIMER0 */
-    .long    USART0_RX_IRQHandler    /* 3 - USART0_RX */
-    .long    USART0_TX_IRQHandler    /* 4 - USART0_TX */
-    .long    USB_IRQHandler    /* 5 - USB */
-    .long    ACMP0_IRQHandler    /* 6 - ACMP0 */
-    .long    ADC0_IRQHandler    /* 7 - ADC0 */
-    .long    DAC0_IRQHandler    /* 8 - DAC0 */
-    .long    I2C0_IRQHandler    /* 9 - I2C0 */
-    .long    I2C1_IRQHandler    /* 10 - I2C1 */
-    .long    GPIO_ODD_IRQHandler    /* 11 - GPIO_ODD */
-    .long    TIMER1_IRQHandler    /* 12 - TIMER1 */
-    .long    TIMER2_IRQHandler    /* 13 - TIMER2 */
-    .long    TIMER3_IRQHandler    /* 14 - TIMER3 */
-    .long    USART1_RX_IRQHandler    /* 15 - USART1_RX */
-    .long    USART1_TX_IRQHandler    /* 16 - USART1_TX */
-    .long    LESENSE_IRQHandler    /* 17 - LESENSE */
-    .long    USART2_RX_IRQHandler    /* 18 - USART2_RX */
-    .long    USART2_TX_IRQHandler    /* 19 - USART2_TX */
-    .long    UART0_RX_IRQHandler    /* 20 - UART0_RX */
-    .long    UART0_TX_IRQHandler    /* 21 - UART0_TX */
-    .long    UART1_RX_IRQHandler    /* 22 - UART1_RX */
-    .long    UART1_TX_IRQHandler    /* 23 - UART1_TX */
-    .long    LEUART0_IRQHandler    /* 24 - LEUART0 */
-    .long    LEUART1_IRQHandler    /* 25 - LEUART1 */
-    .long    LETIMER0_IRQHandler    /* 26 - LETIMER0 */
-    .long    PCNT0_IRQHandler    /* 27 - PCNT0 */
-    .long    PCNT1_IRQHandler    /* 28 - PCNT1 */
-    .long    PCNT2_IRQHandler    /* 29 - PCNT2 */
-    .long    RTC_IRQHandler    /* 30 - RTC */
-    .long    BURTC_IRQHandler    /* 31 - BURTC */
-    .long    CMU_IRQHandler    /* 32 - CMU */
-    .long    VCMP_IRQHandler    /* 33 - VCMP */
-    .long    LCD_IRQHandler    /* 34 - LCD */
-    .long    MSC_IRQHandler    /* 35 - MSC */
-    .long    AES_IRQHandler    /* 36 - AES */
-    .long    EBI_IRQHandler    /* 37 - EBI */
-    .long    EMU_IRQHandler    /* 38 - EMU */
+
+    .long       DMA_IRQHandler    /* 0 - DMA */
+    .long       GPIO_EVEN_IRQHandler    /* 1 - GPIO_EVEN */
+    .long       TIMER0_IRQHandler    /* 2 - TIMER0 */
+    .long       USART0_RX_IRQHandler    /* 3 - USART0_RX */
+    .long       USART0_TX_IRQHandler    /* 4 - USART0_TX */
+    .long       USB_IRQHandler    /* 5 - USB */
+    .long       ACMP0_IRQHandler    /* 6 - ACMP0 */
+    .long       ADC0_IRQHandler    /* 7 - ADC0 */
+    .long       DAC0_IRQHandler    /* 8 - DAC0 */
+    .long       I2C0_IRQHandler    /* 9 - I2C0 */
+    .long       I2C1_IRQHandler    /* 10 - I2C1 */
+    .long       GPIO_ODD_IRQHandler    /* 11 - GPIO_ODD */
+    .long       TIMER1_IRQHandler    /* 12 - TIMER1 */
+    .long       TIMER2_IRQHandler    /* 13 - TIMER2 */
+    .long       TIMER3_IRQHandler    /* 14 - TIMER3 */
+    .long       USART1_RX_IRQHandler    /* 15 - USART1_RX */
+    .long       USART1_TX_IRQHandler    /* 16 - USART1_TX */
+    .long       LESENSE_IRQHandler    /* 17 - LESENSE */
+    .long       USART2_RX_IRQHandler    /* 18 - USART2_RX */
+    .long       USART2_TX_IRQHandler    /* 19 - USART2_TX */
+    .long       UART0_RX_IRQHandler    /* 20 - UART0_RX */
+    .long       UART0_TX_IRQHandler    /* 21 - UART0_TX */
+    .long       UART1_RX_IRQHandler    /* 22 - UART1_RX */
+    .long       UART1_TX_IRQHandler    /* 23 - UART1_TX */
+    .long       LEUART0_IRQHandler    /* 24 - LEUART0 */
+    .long       LEUART1_IRQHandler    /* 25 - LEUART1 */
+    .long       LETIMER0_IRQHandler    /* 26 - LETIMER0 */
+    .long       PCNT0_IRQHandler    /* 27 - PCNT0 */
+    .long       PCNT1_IRQHandler    /* 28 - PCNT1 */
+    .long       PCNT2_IRQHandler    /* 29 - PCNT2 */
+    .long       RTC_IRQHandler    /* 30 - RTC */
+    .long       BURTC_IRQHandler    /* 31 - BURTC */
+    .long       CMU_IRQHandler    /* 32 - CMU */
+    .long       VCMP_IRQHandler    /* 33 - VCMP */
+    .long       LCD_IRQHandler    /* 34 - LCD */
+    .long       MSC_IRQHandler    /* 35 - MSC */
+    .long       AES_IRQHandler    /* 36 - AES */
+    .long       EBI_IRQHandler    /* 37 - EBI */
+    .long       EMU_IRQHandler    /* 38 - EMU */
 
 
-    .size    __isr_vector, . - __isr_vector
+    .size       __Vectors, . - __Vectors
 
     .text
     .thumb
     .thumb_func
-    .align 2
-    .globl    Reset_Handler
-    .type    Reset_Handler, %function
+    .align      2
+    .globl      Reset_Handler
+    .type       Reset_Handler, %function
 Reset_Handler:
-/*     Loop to copy data from read only memory to RAM. The ranges
- *      of copy from/to are specified by following symbols evaluated in
- *      linker script.
- *      __etext: End of code section, i.e., begin of data sections to copy from.
- *      __data_start__/__data_end__: RAM address range that data should be
- *      copied to. Both must be aligned to 4 bytes boundary.  */
 #ifndef __NO_SYSTEM_INIT
-    ldr    r0, =SystemInit
-    blx    r0
+    ldr     r0, =SystemInit
+    blx     r0
 #endif
-    ldr    r1, =__etext
-    ldr    r2, =__data_start__
-    ldr    r3, =__data_end__
+
+/*  Firstly it copies data from read only memory to RAM. There are two schemes
+ *  to copy. One can copy more than one sections. Another can only copy
+ *  one section.  The former scheme needs more instructions and read-only
+ *  data to implement than the latter.
+ *  Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.  */
+
+#ifdef __STARTUP_COPY_MULTIPLE
+/*  Multiple sections scheme.
+ *
+ *  Between symbol address __copy_table_start__ and __copy_table_end__,
+ *  there are array of triplets, each of which specify:
+ *    offset 0: LMA of start of a section to copy from
+ *    offset 4: VMA of start of a section to copy to
+ *    offset 8: size of the section to copy. Must be multiply of 4
+ *
+ *  All addresses must be aligned to 4 bytes boundary.
+ */
+    ldr     r4, =__copy_table_start__
+    ldr     r5, =__copy_table_end__
+
+.L_loop0:
+    cmp     r4, r5
+    bge     .L_loop0_done
+    ldr     r1, [r4]
+    ldr     r2, [r4, #4]
+    ldr     r3, [r4, #8]
+
+.L_loop0_0:
+    subs    r3, #4
+    ittt    ge
+    ldrge   r0, [r1, r3]
+    strge   r0, [r2, r3]
+    bge     .L_loop0_0
+
+    adds    r4, #12
+    b       .L_loop0
+
+.L_loop0_done:
+#else
+/*  Single section scheme.
+ *
+ *  The ranges of copy from/to are specified by following symbols
+ *    __etext: LMA of start of the section to copy from. Usually end of text
+ *    __data_start__: VMA of start of the section to copy to
+ *    __data_end__: VMA of end of the section to copy to
+ *
+ *  All addresses must be aligned to 4 bytes boundary.
+ */
+    ldr     r1, =__etext
+    ldr     r2, =__data_start__
+    ldr     r3, =__data_end__
+
+.L_loop1:
+    cmp     r2, r3
+    ittt    lt
+    ldrlt   r0, [r1], #4
+    strlt   r0, [r2], #4
+    blt     .L_loop1
+#endif /*__STARTUP_COPY_MULTIPLE */
 
-    subs   r3, r2
-    ble    .flash_to_ram_loop_end
-.flash_to_ram_loop:
-    subs   r3, #4
-    ldr    r0, [r1, r3]
-    str    r0, [r2, r3]
-    bgt    .flash_to_ram_loop
-.flash_to_ram_loop_end:
+/*  This part of work usually is done in C library startup code. Otherwise,
+ *  define this macro to enable it in this startup.
+ *
+ *  There are two schemes too. One can clear multiple BSS sections. Another
+ *  can only clear one section. The former is more size expensive than the
+ *  latter.
+ *
+ *  Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ *  Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ */
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
+/*  Multiple sections scheme.
+ *
+ *  Between symbol address __copy_table_start__ and __copy_table_end__,
+ *  there are array of tuples specifying:
+ *    offset 0: Start of a BSS section
+ *    offset 4: Size of this BSS section. Must be multiply of 4
+ */
+    ldr     r3, =__zero_table_start__
+    ldr     r4, =__zero_table_end__
+
+.L_loop2:
+    cmp     r3, r4
+    bge     .L_loop2_done
+    ldr     r1, [r3]
+    ldr     r2, [r3, #4]
+    movs    r0, 0
 
-    ldr    r0, =_start
-    bx     r0
+.L_loop2_0:
+    subs    r2, #4
+    itt     ge
+    strge   r0, [r1, r2]
+    bge     .L_loop2_0
+    adds    r3, #8
+    b       .L_loop2
+.L_loop2_done:
+#elif defined (__STARTUP_CLEAR_BSS)
+/*  Single BSS section scheme.
+ *
+ *  The BSS section is specified by following symbols
+ *    __bss_start__: start of the BSS section.
+ *    __bss_end__: end of the BSS section.
+ *
+ *  Both addresses must be aligned to 4 bytes boundary.
+ */
+    ldr     r1, =__bss_start__
+    ldr     r2, =__bss_end__
+
+    movs    r0, 0
+.L_loop3:
+    cmp     r1, r2
+    itt     lt
+    strlt   r0, [r1], #4
+    blt     .L_loop3
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
+
+#ifndef __START
+#define __START _start
+#endif
+    bl      __START
+
     .pool
-    .size Reset_Handler, . - Reset_Handler
+    .size   Reset_Handler, . - Reset_Handler
+
+    .align  1
+    .thumb_func
+    .weak   Default_Handler
+    .type   Default_Handler, %function
+Default_Handler:
+    b       .
+    .size   Default_Handler, . - Default_Handler
 
 /*    Macro to define default handlers. Default handler
  *    will be weak symbol and just dead loops. They can be
  *    overwritten by other handlers */
-    .macro    def_irq_handler    handler_name
-    .align 1
-    .thumb_func
-    .weak    \handler_name
-    .type    \handler_name, %function
-\handler_name:
-    b    .
-    .size    \handler_name, . - \handler_name
+    .macro  def_irq_handler	handler_name
+    .weak   \handler_name
+    .set    \handler_name, Default_Handler
     .endm
 
-    def_irq_handler    Default_Handler
-
-    def_irq_handler    NMI_Handler
-    def_irq_handler    HardFault_Handler
-    def_irq_handler    MemManage_Handler
-    def_irq_handler    BusFault_Handler
-    def_irq_handler    UsageFault_Handler
-    def_irq_handler    SVC_Handler
-    def_irq_handler    DebugMon_Handler
-    def_irq_handler    PendSV_Handler
-    def_irq_handler    SysTick_Handler
+    def_irq_handler     NMI_Handler
+    def_irq_handler     HardFault_Handler
+    def_irq_handler     MemManage_Handler
+    def_irq_handler     BusFault_Handler
+    def_irq_handler     UsageFault_Handler
+    def_irq_handler     SVC_Handler
+    def_irq_handler     DebugMon_Handler
+    def_irq_handler     PendSV_Handler
+    def_irq_handler     SysTick_Handler
 
-    def_irq_handler    DMA_IRQHandler
-    def_irq_handler    GPIO_EVEN_IRQHandler
-    def_irq_handler    TIMER0_IRQHandler
-    def_irq_handler    USART0_RX_IRQHandler
-    def_irq_handler    USART0_TX_IRQHandler
-    def_irq_handler    USB_IRQHandler
-    def_irq_handler    ACMP0_IRQHandler
-    def_irq_handler    ADC0_IRQHandler
-    def_irq_handler    DAC0_IRQHandler
-    def_irq_handler    I2C0_IRQHandler
-    def_irq_handler    I2C1_IRQHandler
-    def_irq_handler    GPIO_ODD_IRQHandler
-    def_irq_handler    TIMER1_IRQHandler
-    def_irq_handler    TIMER2_IRQHandler
-    def_irq_handler    TIMER3_IRQHandler
-    def_irq_handler    USART1_RX_IRQHandler
-    def_irq_handler    USART1_TX_IRQHandler
-    def_irq_handler    LESENSE_IRQHandler
-    def_irq_handler    USART2_RX_IRQHandler
-    def_irq_handler    USART2_TX_IRQHandler
-    def_irq_handler    UART0_RX_IRQHandler
-    def_irq_handler    UART0_TX_IRQHandler
-    def_irq_handler    UART1_RX_IRQHandler
-    def_irq_handler    UART1_TX_IRQHandler
-    def_irq_handler    LEUART0_IRQHandler
-    def_irq_handler    LEUART1_IRQHandler
-    def_irq_handler    LETIMER0_IRQHandler
-    def_irq_handler    PCNT0_IRQHandler
-    def_irq_handler    PCNT1_IRQHandler
-    def_irq_handler    PCNT2_IRQHandler
-    def_irq_handler    RTC_IRQHandler
-    def_irq_handler    BURTC_IRQHandler
-    def_irq_handler    CMU_IRQHandler
-    def_irq_handler    VCMP_IRQHandler
-    def_irq_handler    LCD_IRQHandler
-    def_irq_handler    MSC_IRQHandler
-    def_irq_handler    AES_IRQHandler
-    def_irq_handler    EBI_IRQHandler
-    def_irq_handler    EMU_IRQHandler
+    def_irq_handler     DMA_IRQHandler
+    def_irq_handler     GPIO_EVEN_IRQHandler
+    def_irq_handler     TIMER0_IRQHandler
+    def_irq_handler     USART0_RX_IRQHandler
+    def_irq_handler     USART0_TX_IRQHandler
+    def_irq_handler     USB_IRQHandler
+    def_irq_handler     ACMP0_IRQHandler
+    def_irq_handler     ADC0_IRQHandler
+    def_irq_handler     DAC0_IRQHandler
+    def_irq_handler     I2C0_IRQHandler
+    def_irq_handler     I2C1_IRQHandler
+    def_irq_handler     GPIO_ODD_IRQHandler
+    def_irq_handler     TIMER1_IRQHandler
+    def_irq_handler     TIMER2_IRQHandler
+    def_irq_handler     TIMER3_IRQHandler
+    def_irq_handler     USART1_RX_IRQHandler
+    def_irq_handler     USART1_TX_IRQHandler
+    def_irq_handler     LESENSE_IRQHandler
+    def_irq_handler     USART2_RX_IRQHandler
+    def_irq_handler     USART2_TX_IRQHandler
+    def_irq_handler     UART0_RX_IRQHandler
+    def_irq_handler     UART0_TX_IRQHandler
+    def_irq_handler     UART1_RX_IRQHandler
+    def_irq_handler     UART1_TX_IRQHandler
+    def_irq_handler     LEUART0_IRQHandler
+    def_irq_handler     LEUART1_IRQHandler
+    def_irq_handler     LETIMER0_IRQHandler
+    def_irq_handler     PCNT0_IRQHandler
+    def_irq_handler     PCNT1_IRQHandler
+    def_irq_handler     PCNT2_IRQHandler
+    def_irq_handler     RTC_IRQHandler
+    def_irq_handler     BURTC_IRQHandler
+    def_irq_handler     CMU_IRQHandler
+    def_irq_handler     VCMP_IRQHandler
+    def_irq_handler     LCD_IRQHandler
+    def_irq_handler     MSC_IRQHandler
+    def_irq_handler     AES_IRQHandler
+    def_irq_handler     EBI_IRQHandler
+    def_irq_handler     EMU_IRQHandler
 
 
     .end

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg990f1024.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg990f1024.h	Fri Jan 15 07:45:16 2016 +0000
@@ -2,10 +2,10 @@
  * @file efm32gg990f1024.h
  * @brief CMSIS Cortex-M Peripheral Access Layer Header File
  *        for EFM32GG990F1024
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -31,8 +31,8 @@
  *
  *****************************************************************************/
 
-#ifndef __EFM32GG990F1024_H
-#define __EFM32GG990F1024_H
+#ifndef EFM32GG990F1024_H
+#define EFM32GG990F1024_H
 
 #ifdef __cplusplus
 extern "C" {
@@ -52,7 +52,7 @@
 typedef enum IRQn
 {
 /******  Cortex-M3 Processor Exceptions Numbers *******************************************/
-  NonMaskableInt_IRQn   = -14,              /*!< 2 Non Maskable Interrupt                 */
+  NonMaskableInt_IRQn   = -14,              /*!< 2 Cortex-M3 Non Maskable Interrupt       */
   HardFault_IRQn        = -13,              /*!< 3 Cortex-M3 Hard Fault Interrupt         */
   MemoryManagement_IRQn = -12,              /*!< 4 Cortex-M3 Memory Management Interrupt  */
   BusFault_IRQn         = -11,              /*!< 5 Cortex-M3 Bus Fault Interrupt          */
@@ -121,8 +121,10 @@
 ******************************************************************************/
 
 /** Part family */
-#define _EFM32_GIANT_FAMILY    1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */
-#define _EFM_DEVICE              /**< Silicon Labs EFM-type microcontroller */
+#define _EFM32_GIANT_FAMILY             1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */
+#define _EFM_DEVICE                       /**< Silicon Labs EFM-type microcontroller */
+#define _SILICON_LABS_32B_PLATFORM_1      /**< Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM      1 /**< Silicon Labs platform name */
 
 /* If part number is not defined as compiler option, define it */
 #if !defined(EFM32GG990F1024)
@@ -474,4 +476,4 @@
 #ifdef __cplusplus
 }
 #endif
-#endif /* __EFM32GG990F1024_H */
+#endif /* EFM32GG990F1024_H */

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_acmp.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_acmp.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32gg_acmp.h
  * @brief EFM32GG_ACMP register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32GG_ACMP
  * @{
  * @brief EFM32GG_ACMP Register Declaration
@@ -327,5 +331,5 @@
 #define ACMP_ROUTE_LOCATION_LOC2           (_ACMP_ROUTE_LOCATION_LOC2 << 8)    /**< Shifted mode LOC2 for ACMP_ROUTE */
 
 /** @} End of group EFM32GG_ACMP */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_adc.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_adc.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32gg_adc.h
  * @brief EFM32GG_ADC register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32GG_ADC
  * @{
  * @brief EFM32GG_ADC Register Declaration
@@ -666,5 +670,5 @@
 #define ADC_BIASPROG_COMPBIAS_DEFAULT           (_ADC_BIASPROG_COMPBIAS_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_BIASPROG */
 
 /** @} End of group EFM32GG_ADC */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_aes.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_aes.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32gg_aes.h
  * @brief EFM32GG_AES register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32GG_AES
  * @{
  * @brief EFM32GG_AES Register Declaration
@@ -235,5 +239,5 @@
 #define AES_KEYHD_KEYHD_DEFAULT         (_AES_KEYHD_KEYHD_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYHD */
 
 /** @} End of group EFM32GG_AES */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_af_pins.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_af_pins.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32gg_af_pins.h
  * @brief EFM32GG_AF_PINS register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32GG_AF_Pins
  * @{
  *****************************************************************************/
@@ -200,5 +204,5 @@
 #define AF_ETM_TD3_PIN(i)           ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 5 :  -1)
 
 /** @} End of group EFM32GG_AF_Pins */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_af_ports.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_af_ports.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32gg_af_ports.h
  * @brief EFM32GG_AF_PORTS register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32GG_AF_Ports
  * @{
  *****************************************************************************/
@@ -200,5 +204,5 @@
 #define AF_ETM_TD3_PORT(i)           ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 0 :  -1)
 
 /** @} End of group EFM32GG_AF_Ports */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_burtc.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_burtc.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32gg_burtc.h
  * @brief EFM32GG_BURTC register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32GG_BURTC
  * @{
  * @brief EFM32GG_BURTC Register Declaration
@@ -55,7 +59,6 @@
   __I uint32_t      SYNCBUSY;      /**< Synchronization Busy Register  */
 
   uint32_t          RESERVED0[48]; /**< Reserved registers */
-
   BURTC_RET_TypeDef RET[128];      /**< RetentionReg */
 } BURTC_TypeDef;                   /** @} */
 
@@ -373,5 +376,5 @@
 #define BURTC_RET_REG_REG_DEFAULT             (_BURTC_RET_REG_REG_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_RET_REG */
 
 /** @} End of group EFM32GG_BURTC */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_burtc_ret.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_burtc_ret.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32gg_burtc_ret.h
  * @brief EFM32GG_BURTC_RET register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @brief BURTC_RET EFM32GG BURTC RET
  *****************************************************************************/
 typedef struct
@@ -37,3 +41,6 @@
   __IO uint32_t REG; /**< Retention Register  */
 } BURTC_RET_TypeDef;
 
+/** @} End of group Parts */
+
+

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_calibrate.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_calibrate.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32gg_calibrate.h
  * @brief EFM32GG_CALIBRATE register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32GG_CALIBRATE
  * @{
  *****************************************************************************/
@@ -41,3 +45,6 @@
   __I uint32_t VALUE;   /**< Default value for calibration register */
 } CALIBRATE_TypeDef;    /** @} */
 
+/** @} End of group Parts */
+
+

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_cmu.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_cmu.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32gg_cmu.h
  * @brief EFM32GG_CMU register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32GG_CMU
  * @{
  * @brief EFM32GG_CMU Register Declaration
@@ -60,6 +64,7 @@
   __IO uint32_t LFACLKEN0;    /**< Low Frequency A Clock Enable Register 0  (Async Reg)  */
   uint32_t      RESERVED1[1]; /**< Reserved for future use **/
   __IO uint32_t LFBCLKEN0;    /**< Low Frequency B Clock Enable Register 0 (Async Reg)  */
+
   uint32_t      RESERVED2[1]; /**< Reserved for future use **/
   __IO uint32_t LFAPRESC0;    /**< Low Frequency A Prescaler Register 0 (Async Reg)  */
   uint32_t      RESERVED3[1]; /**< Reserved for future use **/
@@ -78,7 +83,7 @@
 
 /* Bit fields for CMU CTRL */
 #define _CMU_CTRL_RESETVALUE                        0x000C062CUL                                /**< Default value for CMU_CTRL */
-#define _CMU_CTRL_MASK                              0x53FFFEEFUL                                /**< Mask for CMU_CTRL */
+#define _CMU_CTRL_MASK                              0x57FFFEEFUL                                /**< Mask for CMU_CTRL */
 #define _CMU_CTRL_HFXOMODE_SHIFT                    0                                           /**< Shift value for CMU_HFXOMODE */
 #define _CMU_CTRL_HFXOMODE_MASK                     0x3UL                                       /**< Bit mask for CMU_HFXOMODE */
 #define _CMU_CTRL_HFXOMODE_DEFAULT                  0x00000000UL                                /**< Mode DEFAULT for CMU_CTRL */
@@ -187,7 +192,7 @@
 #define CMU_CTRL_CLKOUTSEL0_ULFRCO                  (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20)         /**< Shifted mode ULFRCO for CMU_CTRL */
 #define CMU_CTRL_CLKOUTSEL0_AUXHFRCO                (_CMU_CTRL_CLKOUTSEL0_AUXHFRCO << 20)       /**< Shifted mode AUXHFRCO for CMU_CTRL */
 #define _CMU_CTRL_CLKOUTSEL1_SHIFT                  23                                          /**< Shift value for CMU_CLKOUTSEL1 */
-#define _CMU_CTRL_CLKOUTSEL1_MASK                   0x3800000UL                                 /**< Bit mask for CMU_CLKOUTSEL1 */
+#define _CMU_CTRL_CLKOUTSEL1_MASK                   0x7800000UL                                 /**< Bit mask for CMU_CLKOUTSEL1 */
 #define _CMU_CTRL_CLKOUTSEL1_DEFAULT                0x00000000UL                                /**< Mode DEFAULT for CMU_CTRL */
 #define _CMU_CTRL_CLKOUTSEL1_LFRCO                  0x00000000UL                                /**< Mode LFRCO for CMU_CTRL */
 #define _CMU_CTRL_CLKOUTSEL1_LFXO                   0x00000001UL                                /**< Mode LFXO for CMU_CTRL */
@@ -454,7 +459,7 @@
 
 /* Bit fields for CMU CMD */
 #define _CMU_CMD_RESETVALUE                         0x00000000UL                          /**< Default value for CMU_CMD */
-#define _CMU_CMD_MASK                               0x0000007FUL                          /**< Mask for CMU_CMD */
+#define _CMU_CMD_MASK                               0x000000FFUL                          /**< Mask for CMU_CMD */
 #define _CMU_CMD_HFCLKSEL_SHIFT                     0                                     /**< Shift value for CMU_HFCLKSEL */
 #define _CMU_CMD_HFCLKSEL_MASK                      0x7UL                                 /**< Bit mask for CMU_HFCLKSEL */
 #define _CMU_CMD_HFCLKSEL_DEFAULT                   0x00000000UL                          /**< Mode DEFAULT for CMU_CMD */
@@ -478,7 +483,7 @@
 #define _CMU_CMD_CALSTOP_DEFAULT                    0x00000000UL                          /**< Mode DEFAULT for CMU_CMD */
 #define CMU_CMD_CALSTOP_DEFAULT                     (_CMU_CMD_CALSTOP_DEFAULT << 4)       /**< Shifted mode DEFAULT for CMU_CMD */
 #define _CMU_CMD_USBCCLKSEL_SHIFT                   5                                     /**< Shift value for CMU_USBCCLKSEL */
-#define _CMU_CMD_USBCCLKSEL_MASK                    0x60UL                                /**< Bit mask for CMU_USBCCLKSEL */
+#define _CMU_CMD_USBCCLKSEL_MASK                    0xE0UL                                /**< Bit mask for CMU_USBCCLKSEL */
 #define _CMU_CMD_USBCCLKSEL_DEFAULT                 0x00000000UL                          /**< Mode DEFAULT for CMU_CMD */
 #define _CMU_CMD_USBCCLKSEL_HFCLKNODIV              0x00000001UL                          /**< Mode HFCLKNODIV for CMU_CMD */
 #define _CMU_CMD_USBCCLKSEL_LFXO                    0x00000002UL                          /**< Mode LFXO for CMU_CMD */
@@ -1243,5 +1248,5 @@
 #define CMU_LOCK_LOCKKEY_UNLOCK                     (_CMU_LOCK_LOCKKEY_UNLOCK << 0)   /**< Shifted mode UNLOCK for CMU_LOCK */
 
 /** @} End of group EFM32GG_CMU */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_dac.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_dac.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32gg_dac.h
  * @brief EFM32GG_DAC register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32GG_DAC
  * @{
  * @brief EFM32GG_DAC Register Declaration
@@ -788,5 +792,5 @@
 #define DAC_OPA2MUX_RESSEL_RES7               (_DAC_OPA2MUX_RESSEL_RES7 << 28)     /**< Shifted mode RES7 for DAC_OPA2MUX */
 
 /** @} End of group EFM32GG_DAC */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_devinfo.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_devinfo.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32gg_devinfo.h
  * @brief EFM32GG_DEVINFO register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32GG_DEVINFO
  * @{
  *****************************************************************************/
@@ -140,15 +144,28 @@
 #define _DEVINFO_PART_PROD_REV_SHIFT               24           /**< Bit position for production revision */
 #define _DEVINFO_PART_DEVICE_FAMILY_MASK           0x00FF0000UL /**< Device Family, 0x47 for Gecko */
 #define _DEVINFO_PART_DEVICE_FAMILY_SHIFT          16           /**< Bit position for device family */
+/* Legacy family #defines */
 #define _DEVINFO_PART_DEVICE_FAMILY_G              71           /**< Gecko Device Family */
 #define _DEVINFO_PART_DEVICE_FAMILY_GG             72           /**< Giant Gecko Device Family */
 #define _DEVINFO_PART_DEVICE_FAMILY_TG             73           /**< Tiny Gecko Device Family */
 #define _DEVINFO_PART_DEVICE_FAMILY_LG             74           /**< Leopard Gecko Device Family */
 #define _DEVINFO_PART_DEVICE_FAMILY_WG             75           /**< Wonder Gecko Device Family */
 #define _DEVINFO_PART_DEVICE_FAMILY_ZG             76           /**< Zero Gecko Device Family */
+#define _DEVINFO_PART_DEVICE_FAMILY_HG             77           /**< Happy Gecko Device Family */
+/* New style family #defines */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFM32G         71           /**< Gecko Device Family */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFM32GG        72           /**< Giant Gecko Device Family */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFM32TG        73           /**< Tiny Gecko Device Family */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFM32LG        74           /**< Leopard Gecko Device Family */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFM32WG        75           /**< Wonder Gecko Device Family */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFM32ZG        76           /**< Zero Gecko Device Family */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFM32HG        77           /**< Happy Gecko Device Family */
+#define _DEVINFO_PART_DEVICE_FAMILY_EZR32WG        120          /**< EZR Wonder Gecko Device Family */
+#define _DEVINFO_PART_DEVICE_FAMILY_EZR32LG        121          /**< EZR Leopard Gecko Device Family */
+#define _DEVINFO_PART_DEVICE_FAMILY_EZR32HG        122          /**< EZR Happy Gecko Device Family */
 #define _DEVINFO_PART_DEVICE_NUMBER_MASK           0x0000FFFFUL /**< Device number */
 #define _DEVINFO_PART_DEVICE_NUMBER_SHIFT          0            /**< Bit position for device number */
 
 /** @} End of group EFM32GG_DEVINFO */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_dma.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_dma.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32gg_dma.h
  * @brief EFM32GG_DMA register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32GG_DMA
  * @{
  * @brief EFM32GG_DMA Register Declaration
@@ -75,7 +79,6 @@
   __IO uint32_t  RECT0;          /**< Channel 0 Rectangle Register  */
 
   uint32_t       RESERVED6[39];  /**< Reserved registers */
-
   DMA_CH_TypeDef CH[12];         /**< Channel registers */
 } DMA_TypeDef;                   /** @} */
 
@@ -1625,5 +1628,5 @@
 #define DMA_CH_CTRL_SOURCESEL_EBI                       (_DMA_CH_CTRL_SOURCESEL_EBI << 16)            /**< Shifted mode EBI for DMA_CH_CTRL */
 
 /** @} End of group EFM32GG_DMA */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_dma_ch.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_dma_ch.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32gg_dma_ch.h
  * @brief EFM32GG_DMA_CH register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @brief DMA_CH EFM32GG DMA CH
  *****************************************************************************/
 typedef struct
@@ -37,3 +41,6 @@
   __IO uint32_t CTRL; /**< Channel Control Register  */
 } DMA_CH_TypeDef;
 
+/** @} End of group Parts */
+
+

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_dma_descriptor.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_dma_descriptor.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32gg_dma_descriptor.h
  * @brief EFM32GG_DMA_DESCRIPTOR register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32GG_DMA_DESCRIPTOR
  * @{
  *****************************************************************************/
@@ -43,3 +47,6 @@
   __IO uint32_t    USER;       /**< DMA padding register, available for user */
 } DMA_DESCRIPTOR_TypeDef;      /** @} */
 
+/** @} End of group Parts */
+
+

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_dmactrl.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_dmactrl.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32gg_dmactrl.h
  * @brief EFM32GG_DMACTRL register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -29,6 +29,10 @@
  * any third party, arising from your use of this Software.
  *
  *****************************************************************************/
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
 
 /**************************************************************************//**
  * @defgroup EFM32GG_DMACTRL_BitFields
@@ -132,5 +136,5 @@
 #define DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER_ALT     0x000000007UL /**< Peripheral scatter gather cycle type using alternate structure */
 
 /** @} End of group EFM32GG_DMA */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_dmareq.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_dmareq.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32gg_dmareq.h
  * @brief EFM32GG_DMAREQ register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -29,6 +29,10 @@
  * any third party, arising from your use of this Software.
  *
  *****************************************************************************/
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
 
 /**************************************************************************//**
  * @defgroup EFM32GG_DMAREQ_BitFields
@@ -95,5 +99,5 @@
 #define DMAREQ_EBI_DDEMPTY            ((51 << 16) + 3) /**< DMA channel select for EBI_DDEMPTY */
 
 /** @} End of group EFM32GG_DMAREQ */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_ebi.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_ebi.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32gg_ebi.h
  * @brief EFM32GG_EBI register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32GG_EBI
  * @{
  * @brief EFM32GG_EBI Register Declaration
@@ -1456,5 +1460,5 @@
 #define EBI_IEN_DDJIT_DEFAULT                     (_EBI_IEN_DDJIT_DEFAULT << 5)   /**< Shifted mode DEFAULT for EBI_IEN */
 
 /** @} End of group EFM32GG_EBI */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_emu.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_emu.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32gg_emu.h
  * @brief EFM32GG_EMU register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32GG_EMU
  * @{
  * @brief EFM32GG_EMU Register Declaration
@@ -353,5 +357,5 @@
 #define EMU_BUBODUNREGCAL_RANGE_DEFAULT      (_EMU_BUBODUNREGCAL_RANGE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_BUBODUNREGCAL */
 
 /** @} End of group EFM32GG_EMU */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_etm.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_etm.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32gg_etm.h
  * @brief EFM32GG_ETM register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32GG_ETM
  * @{
  * @brief EFM32GG_ETM Register Declaration
@@ -778,5 +782,5 @@
 #define ETM_ETMCIDR3_PREAMB_DEFAULT                   (_ETM_ETMCIDR3_PREAMB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCIDR3 */
 
 /** @} End of group EFM32GG_ETM */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_gpio.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_gpio.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32gg_gpio.h
  * @brief EFM32GG_GPIO register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32GG_GPIO
  * @{
  * @brief EFM32GG_GPIO Register Declaration
@@ -1200,5 +1204,5 @@
 #define GPIO_EM4WUCAUSE_EM4WUCAUSE_E13                    (_GPIO_EM4WUCAUSE_EM4WUCAUSE_E13 << 0)     /**< Shifted mode E13 for GPIO_EM4WUCAUSE */
 
 /** @} End of group EFM32GG_GPIO */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_gpio_p.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_gpio_p.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32gg_gpio_p.h
  * @brief EFM32GG_GPIO_P register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @brief GPIO_P EFM32GG GPIO P
  *****************************************************************************/
 typedef struct
@@ -45,3 +49,6 @@
   __IO uint32_t PINLOCKN; /**< Port Unlocked Pins Register  */
 } GPIO_P_TypeDef;
 
+/** @} End of group Parts */
+
+

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_i2c.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_i2c.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32gg_i2c.h
  * @brief EFM32GG_I2C register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32GG_I2C
  * @{
  * @brief EFM32GG_I2C Register Declaration
@@ -697,5 +701,5 @@
 #define I2C_ROUTE_LOCATION_LOC6           (_I2C_ROUTE_LOCATION_LOC6 << 8)    /**< Shifted mode LOC6 for I2C_ROUTE */
 
 /** @} End of group EFM32GG_I2C */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_lcd.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_lcd.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32gg_lcd.h
  * @brief EFM32GG_LCD register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32GG_LCD
  * @{
  * @brief EFM32GG_LCD Register Declaration
@@ -591,5 +595,5 @@
 #define LCD_SEGD7L_SEGD7L_DEFAULT          (_LCD_SEGD7L_SEGD7L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD7L */
 
 /** @} End of group EFM32GG_LCD */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_lesense.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_lesense.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32gg_lesense.h
  * @brief EFM32GG_LESENSE register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32GG_LESENSE
  * @{
  * @brief EFM32GG_LESENSE Register Declaration
@@ -61,9 +65,10 @@
   __IO uint32_t       POWERDOWN;      /**< LESENSE RAM power-down register  */
 
   uint32_t            RESERVED0[105]; /**< Reserved registers */
+  LESENSE_ST_TypeDef  ST[16];         /**< Decoding states */
 
-  LESENSE_ST_TypeDef  ST[16];         /**< Decoding states */
   LESENSE_BUF_TypeDef BUF[16];        /**< Scanresult */
+
   LESENSE_CH_TypeDef  CH[16];         /**< Scanconfig */
 } LESENSE_TypeDef;                    /** @} */
 
@@ -1921,5 +1926,5 @@
 #define LESENSE_CH_EVAL_SCANRESINV_DEFAULT             (_LESENSE_CH_EVAL_SCANRESINV_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_CH_EVAL */
 
 /** @} End of group EFM32GG_LESENSE */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_lesense_buf.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_lesense_buf.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32gg_lesense_buf.h
  * @brief EFM32GG_LESENSE_BUF register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @brief LESENSE_BUF EFM32GG LESENSE BUF
  *****************************************************************************/
 typedef struct
@@ -37,3 +41,6 @@
   __IO uint32_t DATA; /**< Scan results  */
 } LESENSE_BUF_TypeDef;
 
+/** @} End of group Parts */
+
+

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_lesense_ch.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_lesense_ch.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32gg_lesense_ch.h
  * @brief EFM32GG_LESENSE_CH register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @brief LESENSE_CH EFM32GG LESENSE CH
  *****************************************************************************/
 typedef struct
@@ -37,7 +41,9 @@
   __IO uint32_t TIMING;       /**< Scan configuration  */
   __IO uint32_t INTERACT;     /**< Scan configuration  */
   __IO uint32_t EVAL;         /**< Scan configuration  */
-
   uint32_t      RESERVED0[1]; /**< Reserved future */
 } LESENSE_CH_TypeDef;
 
+/** @} End of group Parts */
+
+

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_lesense_st.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_lesense_st.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32gg_lesense_st.h
  * @brief EFM32GG_LESENSE_ST register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @brief LESENSE_ST EFM32GG LESENSE ST
  *****************************************************************************/
 typedef struct
@@ -38,3 +42,6 @@
   __IO uint32_t TCONFB; /**< State transition configuration B  */
 } LESENSE_ST_TypeDef;
 
+/** @} End of group Parts */
+
+

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_letimer.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_letimer.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32gg_letimer.h
  * @brief EFM32GG_LETIMER register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32GG_LETIMER
  * @{
  * @brief EFM32GG_LETIMER Register Declaration
@@ -404,5 +408,5 @@
 #define LETIMER_ROUTE_LOCATION_LOC3          (_LETIMER_ROUTE_LOCATION_LOC3 << 8)    /**< Shifted mode LOC3 for LETIMER_ROUTE */
 
 /** @} End of group EFM32GG_LETIMER */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_leuart.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_leuart.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32gg_leuart.h
  * @brief EFM32GG_LEUART register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32GG_LEUART
  * @{
  * @brief EFM32GG_LEUART Register Declaration
@@ -695,5 +699,5 @@
 #define LEUART_INPUT_RXPRS_DEFAULT               (_LEUART_INPUT_RXPRS_DEFAULT << 4)    /**< Shifted mode DEFAULT for LEUART_INPUT */
 
 /** @} End of group EFM32GG_LEUART */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_msc.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_msc.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32gg_msc.h
  * @brief EFM32GG_MSC register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32GG_MSC
  * @{
  * @brief EFM32GG_MSC Register Declaration
@@ -459,5 +463,5 @@
 #define MSC_MASSLOCK_LOCKKEY_UNLOCK             (_MSC_MASSLOCK_LOCKKEY_UNLOCK << 0)   /**< Shifted mode UNLOCK for MSC_MASSLOCK */
 
 /** @} End of group EFM32GG_MSC */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_pcnt.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_pcnt.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32gg_pcnt.h
  * @brief EFM32GG_PCNT register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32GG_PCNT
  * @{
  * @brief EFM32GG_PCNT Register Declaration
@@ -413,5 +417,5 @@
 #define PCNT_INPUT_S1PRSEN_DEFAULT        (_PCNT_INPUT_S1PRSEN_DEFAULT << 10) /**< Shifted mode DEFAULT for PCNT_INPUT */
 
 /** @} End of group EFM32GG_PCNT */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_prs.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_prs.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32gg_prs.h
  * @brief EFM32GG_PRS register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32GG_PRS
  * @{
  * @brief EFM32GG_PRS Register Declaration
@@ -41,7 +45,6 @@
   __IO uint32_t  ROUTE;        /**< I/O Routing Register  */
 
   uint32_t       RESERVED0[1]; /**< Reserved registers */
-
   PRS_CH_TypeDef CH[12];       /**< Channel registers */
 } PRS_TypeDef;                 /** @} */
 
@@ -448,5 +451,5 @@
 #define PRS_CH_CTRL_ASYNC_DEFAULT               (_PRS_CH_CTRL_ASYNC_DEFAULT << 28)          /**< Shifted mode DEFAULT for PRS_CH_CTRL */
 
 /** @} End of group EFM32GG_PRS */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_prs_ch.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_prs_ch.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32gg_prs_ch.h
  * @brief EFM32GG_PRS_CH register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @brief PRS_CH EFM32GG PRS CH
  *****************************************************************************/
 typedef struct
@@ -37,3 +41,6 @@
   __IO uint32_t CTRL; /**< Channel Control Register  */
 } PRS_CH_TypeDef;
 
+/** @} End of group Parts */
+
+

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_prs_signals.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_prs_signals.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32gg_prs_signals.h
  * @brief EFM32GG_PRS_SIGNALS register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,11 +30,14 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @addtogroup EFM32GG_PRS_Signals
  * @{
  * @brief PRS Signal names
  *****************************************************************************/
-
 #define PRS_VCMP_OUT             ((1 << 16) + 0)  /**< PRS Voltage comparator output */
 #define PRS_ACMP0_OUT            ((2 << 16) + 0)  /**< PRS Analog comparator output */
 #define PRS_ACMP1_OUT            ((3 << 16) + 0)  /**< PRS Analog comparator output */
@@ -119,5 +122,5 @@
 #define PRS_LESENSE_DEC2         ((59 << 16) + 2) /**< PRS LESENSE Decoder PRS out 2 */
 
 /** @} End of group EFM32GG_PRS */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_rmu.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_rmu.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32gg_rmu.h
  * @brief EFM32GG_RMU register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32GG_RMU
  * @{
  * @brief EFM32GG_RMU Register Declaration
@@ -154,5 +158,5 @@
 #define RMU_CMD_RCCLR_DEFAULT                 (_RMU_CMD_RCCLR_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_CMD */
 
 /** @} End of group EFM32GG_RMU */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_romtable.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_romtable.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32gg_romtable.h
  * @brief EFM32GG_ROMTABLE register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32GG_ROMTABLE
  * @{
  * @brief Chip Information, Revision numbers
@@ -64,5 +68,5 @@
 #define _ROMTABLE_PID3_REVMINORLSB_SHIFT    4            /**< Least Significant Bits [3:0] of CHIP MINOR revision, shift */
 
 /** @} End of group EFM32GG_ROMTABLE */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_rtc.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_rtc.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32gg_rtc.h
  * @brief EFM32GG_RTC register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32GG_RTC
  * @{
  * @brief EFM32GG_RTC Register Declaration
@@ -210,5 +214,5 @@
 #define RTC_SYNCBUSY_COMP1_DEFAULT       (_RTC_SYNCBUSY_COMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_SYNCBUSY */
 
 /** @} End of group EFM32GG_RTC */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_timer.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_timer.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32gg_timer.h
  * @brief EFM32GG_TIMER register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32GG_TIMER
  * @{
  * @brief EFM32GG_TIMER Register Declaration
@@ -49,7 +53,6 @@
   __IO uint32_t    ROUTE;        /**< I/O Routing Register  */
 
   uint32_t         RESERVED0[1]; /**< Reserved registers */
-
   TIMER_CC_TypeDef CC[3];        /**< Compare/Capture Channel */
 
   uint32_t         RESERVED1[4]; /**< Reserved for future use **/
@@ -181,7 +184,7 @@
 #define _TIMER_CTRL_ATI_MASK                       0x10000000UL                             /**< Bit mask for TIMER_ATI */
 #define _TIMER_CTRL_ATI_DEFAULT                    0x00000000UL                             /**< Mode DEFAULT for TIMER_CTRL */
 #define TIMER_CTRL_ATI_DEFAULT                     (_TIMER_CTRL_ATI_DEFAULT << 28)          /**< Shifted mode DEFAULT for TIMER_CTRL */
-#define TIMER_CTRL_RSSCOIST                        (0x1UL << 29)                            /**< Reload-Start Sets Compare Ouptut initial State */
+#define TIMER_CTRL_RSSCOIST                        (0x1UL << 29)                            /**< Reload-Start Sets Compare Output initial State */
 #define _TIMER_CTRL_RSSCOIST_SHIFT                 29                                       /**< Shift value for TIMER_RSSCOIST */
 #define _TIMER_CTRL_RSSCOIST_MASK                  0x20000000UL                             /**< Bit mask for TIMER_RSSCOIST */
 #define _TIMER_CTRL_RSSCOIST_DEFAULT               0x00000000UL                             /**< Mode DEFAULT for TIMER_CTRL */
@@ -516,15 +519,15 @@
 #define TIMER_ROUTE_CDTI2PEN_DEFAULT               (_TIMER_ROUTE_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_ROUTE */
 #define _TIMER_ROUTE_LOCATION_SHIFT                16                                    /**< Shift value for TIMER_LOCATION */
 #define _TIMER_ROUTE_LOCATION_MASK                 0x70000UL                             /**< Bit mask for TIMER_LOCATION */
+#define _TIMER_ROUTE_LOCATION_LOC0                 0x00000000UL                          /**< Mode LOC0 for TIMER_ROUTE */
 #define _TIMER_ROUTE_LOCATION_DEFAULT              0x00000000UL                          /**< Mode DEFAULT for TIMER_ROUTE */
-#define _TIMER_ROUTE_LOCATION_LOC0                 0x00000000UL                          /**< Mode LOC0 for TIMER_ROUTE */
 #define _TIMER_ROUTE_LOCATION_LOC1                 0x00000001UL                          /**< Mode LOC1 for TIMER_ROUTE */
 #define _TIMER_ROUTE_LOCATION_LOC2                 0x00000002UL                          /**< Mode LOC2 for TIMER_ROUTE */
 #define _TIMER_ROUTE_LOCATION_LOC3                 0x00000003UL                          /**< Mode LOC3 for TIMER_ROUTE */
 #define _TIMER_ROUTE_LOCATION_LOC4                 0x00000004UL                          /**< Mode LOC4 for TIMER_ROUTE */
 #define _TIMER_ROUTE_LOCATION_LOC5                 0x00000005UL                          /**< Mode LOC5 for TIMER_ROUTE */
+#define TIMER_ROUTE_LOCATION_LOC0                  (_TIMER_ROUTE_LOCATION_LOC0 << 16)    /**< Shifted mode LOC0 for TIMER_ROUTE */
 #define TIMER_ROUTE_LOCATION_DEFAULT               (_TIMER_ROUTE_LOCATION_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_ROUTE */
-#define TIMER_ROUTE_LOCATION_LOC0                  (_TIMER_ROUTE_LOCATION_LOC0 << 16)    /**< Shifted mode LOC0 for TIMER_ROUTE */
 #define TIMER_ROUTE_LOCATION_LOC1                  (_TIMER_ROUTE_LOCATION_LOC1 << 16)    /**< Shifted mode LOC1 for TIMER_ROUTE */
 #define TIMER_ROUTE_LOCATION_LOC2                  (_TIMER_ROUTE_LOCATION_LOC2 << 16)    /**< Shifted mode LOC2 for TIMER_ROUTE */
 #define TIMER_ROUTE_LOCATION_LOC3                  (_TIMER_ROUTE_LOCATION_LOC3 << 16)    /**< Shifted mode LOC3 for TIMER_ROUTE */
@@ -961,5 +964,5 @@
 #define TIMER_DTLOCK_LOCKKEY_UNLOCK                (_TIMER_DTLOCK_LOCKKEY_UNLOCK << 0)   /**< Shifted mode UNLOCK for TIMER_DTLOCK */
 
 /** @} End of group EFM32GG_TIMER */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_timer_cc.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_timer_cc.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32gg_timer_cc.h
  * @brief EFM32GG_TIMER_CC register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @brief TIMER_CC EFM32GG TIMER CC
  *****************************************************************************/
 typedef struct
@@ -40,3 +44,6 @@
   __IO uint32_t CCVB; /**< CC Channel Buffer Register  */
 } TIMER_CC_TypeDef;
 
+/** @} End of group Parts */
+
+

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_uart.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_uart.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32gg_uart.h
  * @brief EFM32GG_UART register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -29,6 +29,10 @@
  * any third party, arising from your use of this Software.
  *
  *****************************************************************************/
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
 
 /**************************************************************************//**
  * @defgroup EFM32GG_UART_BitFields
@@ -1113,5 +1117,5 @@
 #define UART_I2SCTRL_FORMAT_W8D8             (_UART_I2SCTRL_FORMAT_W8D8 << 8)      /**< Shifted mode W8D8 for UART_I2SCTRL */
 
 /** @} End of group EFM32GG_UART */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_usart.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_usart.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32gg_usart.h
  * @brief EFM32GG_USART register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32GG_USART
  * @{
  * @brief EFM32GG_USART Register Declaration
@@ -1145,5 +1149,5 @@
 #define USART_I2SCTRL_FORMAT_W8D8             (_USART_I2SCTRL_FORMAT_W8D8 << 8)      /**< Shifted mode W8D8 for USART_I2SCTRL */
 
 /** @} End of group EFM32GG_USART */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_usb.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_usb.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32gg_usb.h
  * @brief EFM32GG_USB register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32GG_USB
  * @{
  * @brief EFM32GG_USB Register Declaration
@@ -81,7 +85,6 @@
   __IO uint32_t    HPRT;              /**< Host Port Control and Status Register  */
 
   uint32_t         RESERVED6[47];     /**< Reserved registers */
-
   USB_HC_TypeDef   HC[14];            /**< Host Channel Registers */
 
   uint32_t         RESERVED7[80];     /**< Reserved for future use **/
@@ -110,7 +113,6 @@
   __I uint32_t     DIEP0TXFSTS;       /**< Device IN Endpoint 0 Transmit FIFO Status Register  */
 
   uint32_t         RESERVED14[1];     /**< Reserved registers */
-
   USB_DIEP_TypeDef DIEP[6];           /**< Device IN Endpoint x+1 Registers */
 
   uint32_t         RESERVED15[72];    /**< Reserved for future use **/
@@ -122,70 +124,54 @@
   __IO uint32_t    DOEP0DMAADDR;      /**< Device OUT Endpoint 0 DMA Address Register  */
 
   uint32_t         RESERVED18[2];     /**< Reserved registers */
-
   USB_DOEP_TypeDef DOEP[6];           /**< Device OUT Endpoint x+1 Registers */
 
   uint32_t         RESERVED19[136];   /**< Reserved for future use **/
   __IO uint32_t    PCGCCTL;           /**< Power and Clock Gating Control Register  */
 
   uint32_t         RESERVED20[127];   /**< Reserved registers */
-
   __IO uint32_t    FIFO0D[512];       /**< Device EP 0/Host Channel 0 FIFO  */
 
   uint32_t         RESERVED21[512];   /**< Reserved registers */
-
   __IO uint32_t    FIFO1D[512];       /**< Device EP 1/Host Channel 1 FIFO  */
 
   uint32_t         RESERVED22[512];   /**< Reserved registers */
-
   __IO uint32_t    FIFO2D[512];       /**< Device EP 2/Host Channel 2 FIFO  */
 
   uint32_t         RESERVED23[512];   /**< Reserved registers */
-
   __IO uint32_t    FIFO3D[512];       /**< Device EP 3/Host Channel 3 FIFO  */
 
   uint32_t         RESERVED24[512];   /**< Reserved registers */
-
   __IO uint32_t    FIFO4D[512];       /**< Device EP 4/Host Channel 4 FIFO  */
 
   uint32_t         RESERVED25[512];   /**< Reserved registers */
-
   __IO uint32_t    FIFO5D[512];       /**< Device EP 5/Host Channel 5 FIFO  */
 
   uint32_t         RESERVED26[512];   /**< Reserved registers */
-
   __IO uint32_t    FIFO6D[512];       /**< Device EP 6/Host Channel 6 FIFO  */
 
   uint32_t         RESERVED27[512];   /**< Reserved registers */
-
   __IO uint32_t    FIFO7D[512];       /**< Host Channel 7 FIFO  */
 
   uint32_t         RESERVED28[512];   /**< Reserved registers */
-
   __IO uint32_t    FIFO8D[512];       /**< Host Channel 8 FIFO  */
 
   uint32_t         RESERVED29[512];   /**< Reserved registers */
-
   __IO uint32_t    FIFO9D[512];       /**< Host Channel 9 FIFO  */
 
   uint32_t         RESERVED30[512];   /**< Reserved registers */
-
   __IO uint32_t    FIFO10D[512];      /**< Host Channel 10 FIFO  */
 
   uint32_t         RESERVED31[512];   /**< Reserved registers */
-
   __IO uint32_t    FIFO11D[512];      /**< Host Channel 11 FIFO  */
 
   uint32_t         RESERVED32[512];   /**< Reserved registers */
-
   __IO uint32_t    FIFO12D[512];      /**< Host Channel 12 FIFO  */
 
   uint32_t         RESERVED33[512];   /**< Reserved registers */
-
   __IO uint32_t    FIFO13D[512];      /**< Host Channel 13 FIFO  */
 
   uint32_t         RESERVED34[17920]; /**< Reserved registers */
-
   __IO uint32_t    FIFORAM[512];      /**< Direct Access to Data FIFO RAM for Debugging (2 KB)  */
 } USB_TypeDef;                        /** @} */
 
@@ -321,12 +307,12 @@
 /* Bit fields for USB GOTGCTL */
 #define _USB_GOTGCTL_RESETVALUE                    0x00010000UL                             /**< Default value for USB_GOTGCTL */
 #define _USB_GOTGCTL_MASK                          0x001F0FFFUL                             /**< Mask for USB_GOTGCTL */
-#define USB_GOTGCTL_SESREQSCS                      (0x1UL << 0)                             /**< Session Request Success (device only) */
+#define USB_GOTGCTL_SESREQSCS                      (0x1UL << 0)                             /**< Session Request Success device only */
 #define _USB_GOTGCTL_SESREQSCS_SHIFT               0                                        /**< Shift value for USB_SESREQSCS */
 #define _USB_GOTGCTL_SESREQSCS_MASK                0x1UL                                    /**< Bit mask for USB_SESREQSCS */
 #define _USB_GOTGCTL_SESREQSCS_DEFAULT             0x00000000UL                             /**< Mode DEFAULT for USB_GOTGCTL */
 #define USB_GOTGCTL_SESREQSCS_DEFAULT              (_USB_GOTGCTL_SESREQSCS_DEFAULT << 0)    /**< Shifted mode DEFAULT for USB_GOTGCTL */
-#define USB_GOTGCTL_SESREQ                         (0x1UL << 1)                             /**< Session Request (device only) */
+#define USB_GOTGCTL_SESREQ                         (0x1UL << 1)                             /**< Session Request device only */
 #define _USB_GOTGCTL_SESREQ_SHIFT                  1                                        /**< Shift value for USB_SESREQ */
 #define _USB_GOTGCTL_SESREQ_MASK                   0x2UL                                    /**< Bit mask for USB_SESREQ */
 #define _USB_GOTGCTL_SESREQ_DEFAULT                0x00000000UL                             /**< Mode DEFAULT for USB_GOTGCTL */
@@ -361,27 +347,27 @@
 #define _USB_GOTGCTL_AVALIDOVVAL_MASK              0x80UL                                   /**< Bit mask for USB_AVALIDOVVAL */
 #define _USB_GOTGCTL_AVALIDOVVAL_DEFAULT           0x00000000UL                             /**< Mode DEFAULT for USB_GOTGCTL */
 #define USB_GOTGCTL_AVALIDOVVAL_DEFAULT            (_USB_GOTGCTL_AVALIDOVVAL_DEFAULT << 7)  /**< Shifted mode DEFAULT for USB_GOTGCTL */
-#define USB_GOTGCTL_HSTNEGSCS                      (0x1UL << 8)                             /**< Host Negotiation Success (device only) */
+#define USB_GOTGCTL_HSTNEGSCS                      (0x1UL << 8)                             /**< Host Negotiation Success device only */
 #define _USB_GOTGCTL_HSTNEGSCS_SHIFT               8                                        /**< Shift value for USB_HSTNEGSCS */
 #define _USB_GOTGCTL_HSTNEGSCS_MASK                0x100UL                                  /**< Bit mask for USB_HSTNEGSCS */
 #define _USB_GOTGCTL_HSTNEGSCS_DEFAULT             0x00000000UL                             /**< Mode DEFAULT for USB_GOTGCTL */
 #define USB_GOTGCTL_HSTNEGSCS_DEFAULT              (_USB_GOTGCTL_HSTNEGSCS_DEFAULT << 8)    /**< Shifted mode DEFAULT for USB_GOTGCTL */
-#define USB_GOTGCTL_HNPREQ                         (0x1UL << 9)                             /**< HNP Request (device only) */
+#define USB_GOTGCTL_HNPREQ                         (0x1UL << 9)                             /**< HNP Request device only */
 #define _USB_GOTGCTL_HNPREQ_SHIFT                  9                                        /**< Shift value for USB_HNPREQ */
 #define _USB_GOTGCTL_HNPREQ_MASK                   0x200UL                                  /**< Bit mask for USB_HNPREQ */
 #define _USB_GOTGCTL_HNPREQ_DEFAULT                0x00000000UL                             /**< Mode DEFAULT for USB_GOTGCTL */
 #define USB_GOTGCTL_HNPREQ_DEFAULT                 (_USB_GOTGCTL_HNPREQ_DEFAULT << 9)       /**< Shifted mode DEFAULT for USB_GOTGCTL */
-#define USB_GOTGCTL_HSTSETHNPEN                    (0x1UL << 10)                            /**< Host Set HNP Enable (host only) */
+#define USB_GOTGCTL_HSTSETHNPEN                    (0x1UL << 10)                            /**< Host Set HNP Enable host only */
 #define _USB_GOTGCTL_HSTSETHNPEN_SHIFT             10                                       /**< Shift value for USB_HSTSETHNPEN */
 #define _USB_GOTGCTL_HSTSETHNPEN_MASK              0x400UL                                  /**< Bit mask for USB_HSTSETHNPEN */
 #define _USB_GOTGCTL_HSTSETHNPEN_DEFAULT           0x00000000UL                             /**< Mode DEFAULT for USB_GOTGCTL */
 #define USB_GOTGCTL_HSTSETHNPEN_DEFAULT            (_USB_GOTGCTL_HSTSETHNPEN_DEFAULT << 10) /**< Shifted mode DEFAULT for USB_GOTGCTL */
-#define USB_GOTGCTL_DEVHNPEN                       (0x1UL << 11)                            /**< Device HNP Enabled (device only) */
+#define USB_GOTGCTL_DEVHNPEN                       (0x1UL << 11)                            /**< Device HNP Enabled device only */
 #define _USB_GOTGCTL_DEVHNPEN_SHIFT                11                                       /**< Shift value for USB_DEVHNPEN */
 #define _USB_GOTGCTL_DEVHNPEN_MASK                 0x800UL                                  /**< Bit mask for USB_DEVHNPEN */
 #define _USB_GOTGCTL_DEVHNPEN_DEFAULT              0x00000000UL                             /**< Mode DEFAULT for USB_GOTGCTL */
 #define USB_GOTGCTL_DEVHNPEN_DEFAULT               (_USB_GOTGCTL_DEVHNPEN_DEFAULT << 11)    /**< Shifted mode DEFAULT for USB_GOTGCTL */
-#define USB_GOTGCTL_CONIDSTS                       (0x1UL << 16)                            /**< Connector ID Status (host and device) */
+#define USB_GOTGCTL_CONIDSTS                       (0x1UL << 16)                            /**< Connector ID Status host and device */
 #define _USB_GOTGCTL_CONIDSTS_SHIFT                16                                       /**< Shift value for USB_CONIDSTS */
 #define _USB_GOTGCTL_CONIDSTS_MASK                 0x10000UL                                /**< Bit mask for USB_CONIDSTS */
 #define _USB_GOTGCTL_CONIDSTS_A                    0x00000000UL                             /**< Mode A for USB_GOTGCTL */
@@ -390,7 +376,7 @@
 #define USB_GOTGCTL_CONIDSTS_A                     (_USB_GOTGCTL_CONIDSTS_A << 16)          /**< Shifted mode A for USB_GOTGCTL */
 #define USB_GOTGCTL_CONIDSTS_DEFAULT               (_USB_GOTGCTL_CONIDSTS_DEFAULT << 16)    /**< Shifted mode DEFAULT for USB_GOTGCTL */
 #define USB_GOTGCTL_CONIDSTS_B                     (_USB_GOTGCTL_CONIDSTS_B << 16)          /**< Shifted mode B for USB_GOTGCTL */
-#define USB_GOTGCTL_DBNCTIME                       (0x1UL << 17)                            /**< Long/Short Debounce Time (host only) */
+#define USB_GOTGCTL_DBNCTIME                       (0x1UL << 17)                            /**< Long/Short Debounce Time host only */
 #define _USB_GOTGCTL_DBNCTIME_SHIFT                17                                       /**< Shift value for USB_DBNCTIME */
 #define _USB_GOTGCTL_DBNCTIME_MASK                 0x20000UL                                /**< Bit mask for USB_DBNCTIME */
 #define _USB_GOTGCTL_DBNCTIME_DEFAULT              0x00000000UL                             /**< Mode DEFAULT for USB_GOTGCTL */
@@ -399,12 +385,12 @@
 #define USB_GOTGCTL_DBNCTIME_DEFAULT               (_USB_GOTGCTL_DBNCTIME_DEFAULT << 17)    /**< Shifted mode DEFAULT for USB_GOTGCTL */
 #define USB_GOTGCTL_DBNCTIME_LONG                  (_USB_GOTGCTL_DBNCTIME_LONG << 17)       /**< Shifted mode LONG for USB_GOTGCTL */
 #define USB_GOTGCTL_DBNCTIME_SHORT                 (_USB_GOTGCTL_DBNCTIME_SHORT << 17)      /**< Shifted mode SHORT for USB_GOTGCTL */
-#define USB_GOTGCTL_ASESVLD                        (0x1UL << 18)                            /**< A-Session Valid (host only) */
+#define USB_GOTGCTL_ASESVLD                        (0x1UL << 18)                            /**< A-Session Valid host only */
 #define _USB_GOTGCTL_ASESVLD_SHIFT                 18                                       /**< Shift value for USB_ASESVLD */
 #define _USB_GOTGCTL_ASESVLD_MASK                  0x40000UL                                /**< Bit mask for USB_ASESVLD */
 #define _USB_GOTGCTL_ASESVLD_DEFAULT               0x00000000UL                             /**< Mode DEFAULT for USB_GOTGCTL */
 #define USB_GOTGCTL_ASESVLD_DEFAULT                (_USB_GOTGCTL_ASESVLD_DEFAULT << 18)     /**< Shifted mode DEFAULT for USB_GOTGCTL */
-#define USB_GOTGCTL_BSESVLD                        (0x1UL << 19)                            /**< B-Session Valid (device only) */
+#define USB_GOTGCTL_BSESVLD                        (0x1UL << 19)                            /**< B-Session Valid device only */
 #define _USB_GOTGCTL_BSESVLD_SHIFT                 19                                       /**< Shift value for USB_BSESVLD */
 #define _USB_GOTGCTL_BSESVLD_MASK                  0x80000UL                                /**< Bit mask for USB_BSESVLD */
 #define _USB_GOTGCTL_BSESVLD_DEFAULT               0x00000000UL                             /**< Mode DEFAULT for USB_GOTGCTL */
@@ -422,32 +408,32 @@
 /* Bit fields for USB GOTGINT */
 #define _USB_GOTGINT_RESETVALUE                    0x00000000UL                                 /**< Default value for USB_GOTGINT */
 #define _USB_GOTGINT_MASK                          0x000E0304UL                                 /**< Mask for USB_GOTGINT */
-#define USB_GOTGINT_SESENDDET                      (0x1UL << 2)                                 /**< Session End Detected (host and device) */
+#define USB_GOTGINT_SESENDDET                      (0x1UL << 2)                                 /**< Session End Detected host and device */
 #define _USB_GOTGINT_SESENDDET_SHIFT               2                                            /**< Shift value for USB_SESENDDET */
 #define _USB_GOTGINT_SESENDDET_MASK                0x4UL                                        /**< Bit mask for USB_SESENDDET */
 #define _USB_GOTGINT_SESENDDET_DEFAULT             0x00000000UL                                 /**< Mode DEFAULT for USB_GOTGINT */
 #define USB_GOTGINT_SESENDDET_DEFAULT              (_USB_GOTGINT_SESENDDET_DEFAULT << 2)        /**< Shifted mode DEFAULT for USB_GOTGINT */
-#define USB_GOTGINT_SESREQSUCSTSCHNG               (0x1UL << 8)                                 /**< Session Request Success Status Change (host and device) */
+#define USB_GOTGINT_SESREQSUCSTSCHNG               (0x1UL << 8)                                 /**< Session Request Success Status Change host and device */
 #define _USB_GOTGINT_SESREQSUCSTSCHNG_SHIFT        8                                            /**< Shift value for USB_SESREQSUCSTSCHNG */
 #define _USB_GOTGINT_SESREQSUCSTSCHNG_MASK         0x100UL                                      /**< Bit mask for USB_SESREQSUCSTSCHNG */
 #define _USB_GOTGINT_SESREQSUCSTSCHNG_DEFAULT      0x00000000UL                                 /**< Mode DEFAULT for USB_GOTGINT */
 #define USB_GOTGINT_SESREQSUCSTSCHNG_DEFAULT       (_USB_GOTGINT_SESREQSUCSTSCHNG_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_GOTGINT */
-#define USB_GOTGINT_HSTNEGSUCSTSCHNG               (0x1UL << 9)                                 /**< Host Negotiation Success Status Change (host and device) */
+#define USB_GOTGINT_HSTNEGSUCSTSCHNG               (0x1UL << 9)                                 /**< Host Negotiation Success Status Change host and device */
 #define _USB_GOTGINT_HSTNEGSUCSTSCHNG_SHIFT        9                                            /**< Shift value for USB_HSTNEGSUCSTSCHNG */
 #define _USB_GOTGINT_HSTNEGSUCSTSCHNG_MASK         0x200UL                                      /**< Bit mask for USB_HSTNEGSUCSTSCHNG */
 #define _USB_GOTGINT_HSTNEGSUCSTSCHNG_DEFAULT      0x00000000UL                                 /**< Mode DEFAULT for USB_GOTGINT */
 #define USB_GOTGINT_HSTNEGSUCSTSCHNG_DEFAULT       (_USB_GOTGINT_HSTNEGSUCSTSCHNG_DEFAULT << 9) /**< Shifted mode DEFAULT for USB_GOTGINT */
-#define USB_GOTGINT_HSTNEGDET                      (0x1UL << 17)                                /**< Host Negotiation Detected (host and device) */
+#define USB_GOTGINT_HSTNEGDET                      (0x1UL << 17)                                /**< Host Negotiation Detected host and device */
 #define _USB_GOTGINT_HSTNEGDET_SHIFT               17                                           /**< Shift value for USB_HSTNEGDET */
 #define _USB_GOTGINT_HSTNEGDET_MASK                0x20000UL                                    /**< Bit mask for USB_HSTNEGDET */
 #define _USB_GOTGINT_HSTNEGDET_DEFAULT             0x00000000UL                                 /**< Mode DEFAULT for USB_GOTGINT */
 #define USB_GOTGINT_HSTNEGDET_DEFAULT              (_USB_GOTGINT_HSTNEGDET_DEFAULT << 17)       /**< Shifted mode DEFAULT for USB_GOTGINT */
-#define USB_GOTGINT_ADEVTOUTCHG                    (0x1UL << 18)                                /**< A-Device Timeout Change (host and device) */
+#define USB_GOTGINT_ADEVTOUTCHG                    (0x1UL << 18)                                /**< A-Device Timeout Change host and device */
 #define _USB_GOTGINT_ADEVTOUTCHG_SHIFT             18                                           /**< Shift value for USB_ADEVTOUTCHG */
 #define _USB_GOTGINT_ADEVTOUTCHG_MASK              0x40000UL                                    /**< Bit mask for USB_ADEVTOUTCHG */
 #define _USB_GOTGINT_ADEVTOUTCHG_DEFAULT           0x00000000UL                                 /**< Mode DEFAULT for USB_GOTGINT */
 #define USB_GOTGINT_ADEVTOUTCHG_DEFAULT            (_USB_GOTGINT_ADEVTOUTCHG_DEFAULT << 18)     /**< Shifted mode DEFAULT for USB_GOTGINT */
-#define USB_GOTGINT_DBNCEDONE                      (0x1UL << 19)                                /**< Debounce Done (host only) */
+#define USB_GOTGINT_DBNCEDONE                      (0x1UL << 19)                                /**< Debounce Done host only */
 #define _USB_GOTGINT_DBNCEDONE_SHIFT               19                                           /**< Shift value for USB_DBNCEDONE */
 #define _USB_GOTGINT_DBNCEDONE_MASK                0x80000UL                                    /**< Bit mask for USB_DBNCEDONE */
 #define _USB_GOTGINT_DBNCEDONE_DEFAULT             0x00000000UL                                 /**< Mode DEFAULT for USB_GOTGINT */
@@ -456,7 +442,7 @@
 /* Bit fields for USB GAHBCFG */
 #define _USB_GAHBCFG_RESETVALUE                    0x00000000UL                                /**< Default value for USB_GAHBCFG */
 #define _USB_GAHBCFG_MASK                          0x006001BFUL                                /**< Mask for USB_GAHBCFG */
-#define USB_GAHBCFG_GLBLINTRMSK                    (0x1UL << 0)                                /**< Global Interrupt Mask (host and device) */
+#define USB_GAHBCFG_GLBLINTRMSK                    (0x1UL << 0)                                /**< Global Interrupt Mask host and device */
 #define _USB_GAHBCFG_GLBLINTRMSK_SHIFT             0                                           /**< Shift value for USB_GLBLINTRMSK */
 #define _USB_GAHBCFG_GLBLINTRMSK_MASK              0x1UL                                       /**< Bit mask for USB_GLBLINTRMSK */
 #define _USB_GAHBCFG_GLBLINTRMSK_DEFAULT           0x00000000UL                                /**< Mode DEFAULT for USB_GAHBCFG */
@@ -475,12 +461,12 @@
 #define USB_GAHBCFG_HBSTLEN_INCR4                  (_USB_GAHBCFG_HBSTLEN_INCR4 << 1)           /**< Shifted mode INCR4 for USB_GAHBCFG */
 #define USB_GAHBCFG_HBSTLEN_INCR8                  (_USB_GAHBCFG_HBSTLEN_INCR8 << 1)           /**< Shifted mode INCR8 for USB_GAHBCFG */
 #define USB_GAHBCFG_HBSTLEN_INCR16                 (_USB_GAHBCFG_HBSTLEN_INCR16 << 1)          /**< Shifted mode INCR16 for USB_GAHBCFG */
-#define USB_GAHBCFG_DMAEN                          (0x1UL << 5)                                /**< DMA Enable (host and device) */
+#define USB_GAHBCFG_DMAEN                          (0x1UL << 5)                                /**< DMA Enable host and device */
 #define _USB_GAHBCFG_DMAEN_SHIFT                   5                                           /**< Shift value for USB_DMAEN */
 #define _USB_GAHBCFG_DMAEN_MASK                    0x20UL                                      /**< Bit mask for USB_DMAEN */
 #define _USB_GAHBCFG_DMAEN_DEFAULT                 0x00000000UL                                /**< Mode DEFAULT for USB_GAHBCFG */
 #define USB_GAHBCFG_DMAEN_DEFAULT                  (_USB_GAHBCFG_DMAEN_DEFAULT << 5)           /**< Shifted mode DEFAULT for USB_GAHBCFG */
-#define USB_GAHBCFG_NPTXFEMPLVL                    (0x1UL << 7)                                /**< Non-Periodic TxFIFO Empty Level (host and device) */
+#define USB_GAHBCFG_NPTXFEMPLVL                    (0x1UL << 7)                                /**< Non-Periodic TxFIFO Empty Level host and device */
 #define _USB_GAHBCFG_NPTXFEMPLVL_SHIFT             7                                           /**< Shift value for USB_NPTXFEMPLVL */
 #define _USB_GAHBCFG_NPTXFEMPLVL_MASK              0x80UL                                      /**< Bit mask for USB_NPTXFEMPLVL */
 #define _USB_GAHBCFG_NPTXFEMPLVL_DEFAULT           0x00000000UL                                /**< Mode DEFAULT for USB_GAHBCFG */
@@ -489,7 +475,7 @@
 #define USB_GAHBCFG_NPTXFEMPLVL_DEFAULT            (_USB_GAHBCFG_NPTXFEMPLVL_DEFAULT << 7)     /**< Shifted mode DEFAULT for USB_GAHBCFG */
 #define USB_GAHBCFG_NPTXFEMPLVL_HALFEMPTY          (_USB_GAHBCFG_NPTXFEMPLVL_HALFEMPTY << 7)   /**< Shifted mode HALFEMPTY for USB_GAHBCFG */
 #define USB_GAHBCFG_NPTXFEMPLVL_EMPTY              (_USB_GAHBCFG_NPTXFEMPLVL_EMPTY << 7)       /**< Shifted mode EMPTY for USB_GAHBCFG */
-#define USB_GAHBCFG_PTXFEMPLVL                     (0x1UL << 8)                                /**< Periodic TxFIFO Empty Level (host only) */
+#define USB_GAHBCFG_PTXFEMPLVL                     (0x1UL << 8)                                /**< Periodic TxFIFO Empty Level host only */
 #define _USB_GAHBCFG_PTXFEMPLVL_SHIFT              8                                           /**< Shift value for USB_PTXFEMPLVL */
 #define _USB_GAHBCFG_PTXFEMPLVL_MASK               0x100UL                                     /**< Bit mask for USB_PTXFEMPLVL */
 #define _USB_GAHBCFG_PTXFEMPLVL_DEFAULT            0x00000000UL                                /**< Mode DEFAULT for USB_GAHBCFG */
@@ -516,17 +502,17 @@
 #define _USB_GUSBCFG_TOUTCAL_MASK                  0x7UL                                       /**< Bit mask for USB_TOUTCAL */
 #define _USB_GUSBCFG_TOUTCAL_DEFAULT               0x00000000UL                                /**< Mode DEFAULT for USB_GUSBCFG */
 #define USB_GUSBCFG_TOUTCAL_DEFAULT                (_USB_GUSBCFG_TOUTCAL_DEFAULT << 0)         /**< Shifted mode DEFAULT for USB_GUSBCFG */
-#define USB_GUSBCFG_FSINTF                         (0x1UL << 5)                                /**< Full-Speed Serial Interface Select (host and device) */
+#define USB_GUSBCFG_FSINTF                         (0x1UL << 5)                                /**< Full-Speed Serial Interface Select host and device */
 #define _USB_GUSBCFG_FSINTF_SHIFT                  5                                           /**< Shift value for USB_FSINTF */
 #define _USB_GUSBCFG_FSINTF_MASK                   0x20UL                                      /**< Bit mask for USB_FSINTF */
 #define _USB_GUSBCFG_FSINTF_DEFAULT                0x00000000UL                                /**< Mode DEFAULT for USB_GUSBCFG */
 #define USB_GUSBCFG_FSINTF_DEFAULT                 (_USB_GUSBCFG_FSINTF_DEFAULT << 5)          /**< Shifted mode DEFAULT for USB_GUSBCFG */
-#define USB_GUSBCFG_SRPCAP                         (0x1UL << 8)                                /**< SRP-Capable (host and device) */
+#define USB_GUSBCFG_SRPCAP                         (0x1UL << 8)                                /**< SRP-Capable host and device */
 #define _USB_GUSBCFG_SRPCAP_SHIFT                  8                                           /**< Shift value for USB_SRPCAP */
 #define _USB_GUSBCFG_SRPCAP_MASK                   0x100UL                                     /**< Bit mask for USB_SRPCAP */
 #define _USB_GUSBCFG_SRPCAP_DEFAULT                0x00000000UL                                /**< Mode DEFAULT for USB_GUSBCFG */
 #define USB_GUSBCFG_SRPCAP_DEFAULT                 (_USB_GUSBCFG_SRPCAP_DEFAULT << 8)          /**< Shifted mode DEFAULT for USB_GUSBCFG */
-#define USB_GUSBCFG_HNPCAP                         (0x1UL << 9)                                /**< HNP-Capable (host and device) */
+#define USB_GUSBCFG_HNPCAP                         (0x1UL << 9)                                /**< HNP-Capable host and device */
 #define _USB_GUSBCFG_HNPCAP_SHIFT                  9                                           /**< Shift value for USB_HNPCAP */
 #define _USB_GUSBCFG_HNPCAP_MASK                   0x200UL                                     /**< Bit mask for USB_HNPCAP */
 #define _USB_GUSBCFG_HNPCAP_DEFAULT                0x00000000UL                                /**< Mode DEFAULT for USB_GUSBCFG */
@@ -535,7 +521,7 @@
 #define _USB_GUSBCFG_USBTRDTIM_MASK                0x3C00UL                                    /**< Bit mask for USB_USBTRDTIM */
 #define _USB_GUSBCFG_USBTRDTIM_DEFAULT             0x00000005UL                                /**< Mode DEFAULT for USB_GUSBCFG */
 #define USB_GUSBCFG_USBTRDTIM_DEFAULT              (_USB_GUSBCFG_USBTRDTIM_DEFAULT << 10)      /**< Shifted mode DEFAULT for USB_GUSBCFG */
-#define USB_GUSBCFG_TERMSELDLPULSE                 (0x1UL << 22)                               /**< TermSel DLine Pulsing Selection (device only) */
+#define USB_GUSBCFG_TERMSELDLPULSE                 (0x1UL << 22)                               /**< TermSel DLine Pulsing Selection device only */
 #define _USB_GUSBCFG_TERMSELDLPULSE_SHIFT          22                                          /**< Shift value for USB_TERMSELDLPULSE */
 #define _USB_GUSBCFG_TERMSELDLPULSE_MASK           0x400000UL                                  /**< Bit mask for USB_TERMSELDLPULSE */
 #define _USB_GUSBCFG_TERMSELDLPULSE_DEFAULT        0x00000000UL                                /**< Mode DEFAULT for USB_GUSBCFG */
@@ -544,22 +530,22 @@
 #define USB_GUSBCFG_TERMSELDLPULSE_DEFAULT         (_USB_GUSBCFG_TERMSELDLPULSE_DEFAULT << 22) /**< Shifted mode DEFAULT for USB_GUSBCFG */
 #define USB_GUSBCFG_TERMSELDLPULSE_TXVALID         (_USB_GUSBCFG_TERMSELDLPULSE_TXVALID << 22) /**< Shifted mode TXVALID for USB_GUSBCFG */
 #define USB_GUSBCFG_TERMSELDLPULSE_TERMSEL         (_USB_GUSBCFG_TERMSELDLPULSE_TERMSEL << 22) /**< Shifted mode TERMSEL for USB_GUSBCFG */
-#define USB_GUSBCFG_TXENDDELAY                     (0x1UL << 28)                               /**< Tx End Delay (device only) */
+#define USB_GUSBCFG_TXENDDELAY                     (0x1UL << 28)                               /**< Tx End Delay device only */
 #define _USB_GUSBCFG_TXENDDELAY_SHIFT              28                                          /**< Shift value for USB_TXENDDELAY */
 #define _USB_GUSBCFG_TXENDDELAY_MASK               0x10000000UL                                /**< Bit mask for USB_TXENDDELAY */
 #define _USB_GUSBCFG_TXENDDELAY_DEFAULT            0x00000000UL                                /**< Mode DEFAULT for USB_GUSBCFG */
 #define USB_GUSBCFG_TXENDDELAY_DEFAULT             (_USB_GUSBCFG_TXENDDELAY_DEFAULT << 28)     /**< Shifted mode DEFAULT for USB_GUSBCFG */
-#define USB_GUSBCFG_FORCEHSTMODE                   (0x1UL << 29)                               /**< Force Host Mode (host and device) */
+#define USB_GUSBCFG_FORCEHSTMODE                   (0x1UL << 29)                               /**< Force Host Mode host and device */
 #define _USB_GUSBCFG_FORCEHSTMODE_SHIFT            29                                          /**< Shift value for USB_FORCEHSTMODE */
 #define _USB_GUSBCFG_FORCEHSTMODE_MASK             0x20000000UL                                /**< Bit mask for USB_FORCEHSTMODE */
 #define _USB_GUSBCFG_FORCEHSTMODE_DEFAULT          0x00000000UL                                /**< Mode DEFAULT for USB_GUSBCFG */
 #define USB_GUSBCFG_FORCEHSTMODE_DEFAULT           (_USB_GUSBCFG_FORCEHSTMODE_DEFAULT << 29)   /**< Shifted mode DEFAULT for USB_GUSBCFG */
-#define USB_GUSBCFG_FORCEDEVMODE                   (0x1UL << 30)                               /**< Force Device Mode (host and device) */
+#define USB_GUSBCFG_FORCEDEVMODE                   (0x1UL << 30)                               /**< Force Device Mode host and device */
 #define _USB_GUSBCFG_FORCEDEVMODE_SHIFT            30                                          /**< Shift value for USB_FORCEDEVMODE */
 #define _USB_GUSBCFG_FORCEDEVMODE_MASK             0x40000000UL                                /**< Bit mask for USB_FORCEDEVMODE */
 #define _USB_GUSBCFG_FORCEDEVMODE_DEFAULT          0x00000000UL                                /**< Mode DEFAULT for USB_GUSBCFG */
 #define USB_GUSBCFG_FORCEDEVMODE_DEFAULT           (_USB_GUSBCFG_FORCEDEVMODE_DEFAULT << 30)   /**< Shifted mode DEFAULT for USB_GUSBCFG */
-#define USB_GUSBCFG_CORRUPTTXPKT                   (0x1UL << 31)                               /**< Corrupt Tx packet (host and device) */
+#define USB_GUSBCFG_CORRUPTTXPKT                   (0x1UL << 31)                               /**< Corrupt Tx packet host and device */
 #define _USB_GUSBCFG_CORRUPTTXPKT_SHIFT            31                                          /**< Shift value for USB_CORRUPTTXPKT */
 #define _USB_GUSBCFG_CORRUPTTXPKT_MASK             0x80000000UL                                /**< Bit mask for USB_CORRUPTTXPKT */
 #define _USB_GUSBCFG_CORRUPTTXPKT_DEFAULT          0x00000000UL                                /**< Mode DEFAULT for USB_GUSBCFG */
@@ -568,22 +554,22 @@
 /* Bit fields for USB GRSTCTL */
 #define _USB_GRSTCTL_RESETVALUE                    0x80000000UL                           /**< Default value for USB_GRSTCTL */
 #define _USB_GRSTCTL_MASK                          0xC00007F5UL                           /**< Mask for USB_GRSTCTL */
-#define USB_GRSTCTL_CSFTRST                        (0x1UL << 0)                           /**< Core Soft Reset (host and device) */
+#define USB_GRSTCTL_CSFTRST                        (0x1UL << 0)                           /**< Core Soft Reset host and device */
 #define _USB_GRSTCTL_CSFTRST_SHIFT                 0                                      /**< Shift value for USB_CSFTRST */
 #define _USB_GRSTCTL_CSFTRST_MASK                  0x1UL                                  /**< Bit mask for USB_CSFTRST */
 #define _USB_GRSTCTL_CSFTRST_DEFAULT               0x00000000UL                           /**< Mode DEFAULT for USB_GRSTCTL */
 #define USB_GRSTCTL_CSFTRST_DEFAULT                (_USB_GRSTCTL_CSFTRST_DEFAULT << 0)    /**< Shifted mode DEFAULT for USB_GRSTCTL */
-#define USB_GRSTCTL_FRMCNTRRST                     (0x1UL << 2)                           /**< Host Frame Counter Reset (host only) */
+#define USB_GRSTCTL_FRMCNTRRST                     (0x1UL << 2)                           /**< Host Frame Counter Reset host only */
 #define _USB_GRSTCTL_FRMCNTRRST_SHIFT              2                                      /**< Shift value for USB_FRMCNTRRST */
 #define _USB_GRSTCTL_FRMCNTRRST_MASK               0x4UL                                  /**< Bit mask for USB_FRMCNTRRST */
 #define _USB_GRSTCTL_FRMCNTRRST_DEFAULT            0x00000000UL                           /**< Mode DEFAULT for USB_GRSTCTL */
 #define USB_GRSTCTL_FRMCNTRRST_DEFAULT             (_USB_GRSTCTL_FRMCNTRRST_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_GRSTCTL */
-#define USB_GRSTCTL_RXFFLSH                        (0x1UL << 4)                           /**< RxFIFO Flush (host and device) */
+#define USB_GRSTCTL_RXFFLSH                        (0x1UL << 4)                           /**< RxFIFO Flush host and device */
 #define _USB_GRSTCTL_RXFFLSH_SHIFT                 4                                      /**< Shift value for USB_RXFFLSH */
 #define _USB_GRSTCTL_RXFFLSH_MASK                  0x10UL                                 /**< Bit mask for USB_RXFFLSH */
 #define _USB_GRSTCTL_RXFFLSH_DEFAULT               0x00000000UL                           /**< Mode DEFAULT for USB_GRSTCTL */
 #define USB_GRSTCTL_RXFFLSH_DEFAULT                (_USB_GRSTCTL_RXFFLSH_DEFAULT << 4)    /**< Shifted mode DEFAULT for USB_GRSTCTL */
-#define USB_GRSTCTL_TXFFLSH                        (0x1UL << 5)                           /**< TxFIFO Flush (host and device) */
+#define USB_GRSTCTL_TXFFLSH                        (0x1UL << 5)                           /**< TxFIFO Flush host and device */
 #define _USB_GRSTCTL_TXFFLSH_SHIFT                 5                                      /**< Shift value for USB_TXFFLSH */
 #define _USB_GRSTCTL_TXFFLSH_MASK                  0x20UL                                 /**< Bit mask for USB_TXFFLSH */
 #define _USB_GRSTCTL_TXFFLSH_DEFAULT               0x00000000UL                           /**< Mode DEFAULT for USB_GRSTCTL */
@@ -608,12 +594,12 @@
 #define USB_GRSTCTL_TXFNUM_F5                      (_USB_GRSTCTL_TXFNUM_F5 << 6)          /**< Shifted mode F5 for USB_GRSTCTL */
 #define USB_GRSTCTL_TXFNUM_F6                      (_USB_GRSTCTL_TXFNUM_F6 << 6)          /**< Shifted mode F6 for USB_GRSTCTL */
 #define USB_GRSTCTL_TXFNUM_FALL                    (_USB_GRSTCTL_TXFNUM_FALL << 6)        /**< Shifted mode FALL for USB_GRSTCTL */
-#define USB_GRSTCTL_DMAREQ                         (0x1UL << 30)                          /**< DMA Request Signal (host and device) */
+#define USB_GRSTCTL_DMAREQ                         (0x1UL << 30)                          /**< DMA Request Signal host and device */
 #define _USB_GRSTCTL_DMAREQ_SHIFT                  30                                     /**< Shift value for USB_DMAREQ */
 #define _USB_GRSTCTL_DMAREQ_MASK                   0x40000000UL                           /**< Bit mask for USB_DMAREQ */
 #define _USB_GRSTCTL_DMAREQ_DEFAULT                0x00000000UL                           /**< Mode DEFAULT for USB_GRSTCTL */
 #define USB_GRSTCTL_DMAREQ_DEFAULT                 (_USB_GRSTCTL_DMAREQ_DEFAULT << 30)    /**< Shifted mode DEFAULT for USB_GRSTCTL */
-#define USB_GRSTCTL_AHBIDLE                        (0x1UL << 31)                          /**< AHB Master Idle (host and device) */
+#define USB_GRSTCTL_AHBIDLE                        (0x1UL << 31)                          /**< AHB Master Idle host and device */
 #define _USB_GRSTCTL_AHBIDLE_SHIFT                 31                                     /**< Shift value for USB_AHBIDLE */
 #define _USB_GRSTCTL_AHBIDLE_MASK                  0x80000000UL                           /**< Bit mask for USB_AHBIDLE */
 #define _USB_GRSTCTL_AHBIDLE_DEFAULT               0x00000001UL                           /**< Mode DEFAULT for USB_GRSTCTL */
@@ -621,8 +607,8 @@
 
 /* Bit fields for USB GINTSTS */
 #define _USB_GINTSTS_RESETVALUE                    0x14000020UL                              /**< Default value for USB_GINTSTS */
-#define _USB_GINTSTS_MASK                          0xF7FC7CFFUL                              /**< Mask for USB_GINTSTS */
-#define USB_GINTSTS_CURMOD                         (0x1UL << 0)                              /**< Current Mode of Operation (host and device) */
+#define _USB_GINTSTS_MASK                          0xF7FCFCFFUL                              /**< Mask for USB_GINTSTS */
+#define USB_GINTSTS_CURMOD                         (0x1UL << 0)                              /**< Current Mode of Operation host and device */
 #define _USB_GINTSTS_CURMOD_SHIFT                  0                                         /**< Shift value for USB_CURMOD */
 #define _USB_GINTSTS_CURMOD_MASK                   0x1UL                                     /**< Bit mask for USB_CURMOD */
 #define _USB_GINTSTS_CURMOD_DEFAULT                0x00000000UL                              /**< Mode DEFAULT for USB_GINTSTS */
@@ -631,127 +617,132 @@
 #define USB_GINTSTS_CURMOD_DEFAULT                 (_USB_GINTSTS_CURMOD_DEFAULT << 0)        /**< Shifted mode DEFAULT for USB_GINTSTS */
 #define USB_GINTSTS_CURMOD_DEVICE                  (_USB_GINTSTS_CURMOD_DEVICE << 0)         /**< Shifted mode DEVICE for USB_GINTSTS */
 #define USB_GINTSTS_CURMOD_HOST                    (_USB_GINTSTS_CURMOD_HOST << 0)           /**< Shifted mode HOST for USB_GINTSTS */
-#define USB_GINTSTS_MODEMIS                        (0x1UL << 1)                              /**< Mode Mismatch Interrupt (host and device) */
+#define USB_GINTSTS_MODEMIS                        (0x1UL << 1)                              /**< Mode Mismatch Interrupt host and device */
 #define _USB_GINTSTS_MODEMIS_SHIFT                 1                                         /**< Shift value for USB_MODEMIS */
 #define _USB_GINTSTS_MODEMIS_MASK                  0x2UL                                     /**< Bit mask for USB_MODEMIS */
 #define _USB_GINTSTS_MODEMIS_DEFAULT               0x00000000UL                              /**< Mode DEFAULT for USB_GINTSTS */
 #define USB_GINTSTS_MODEMIS_DEFAULT                (_USB_GINTSTS_MODEMIS_DEFAULT << 1)       /**< Shifted mode DEFAULT for USB_GINTSTS */
-#define USB_GINTSTS_OTGINT                         (0x1UL << 2)                              /**< OTG Interrupt (host and device) */
+#define USB_GINTSTS_OTGINT                         (0x1UL << 2)                              /**< OTG Interrupt host and device */
 #define _USB_GINTSTS_OTGINT_SHIFT                  2                                         /**< Shift value for USB_OTGINT */
 #define _USB_GINTSTS_OTGINT_MASK                   0x4UL                                     /**< Bit mask for USB_OTGINT */
 #define _USB_GINTSTS_OTGINT_DEFAULT                0x00000000UL                              /**< Mode DEFAULT for USB_GINTSTS */
 #define USB_GINTSTS_OTGINT_DEFAULT                 (_USB_GINTSTS_OTGINT_DEFAULT << 2)        /**< Shifted mode DEFAULT for USB_GINTSTS */
-#define USB_GINTSTS_SOF                            (0x1UL << 3)                              /**< Start of Frame (host and device) */
+#define USB_GINTSTS_SOF                            (0x1UL << 3)                              /**< Start of Frame host and device */
 #define _USB_GINTSTS_SOF_SHIFT                     3                                         /**< Shift value for USB_SOF */
 #define _USB_GINTSTS_SOF_MASK                      0x8UL                                     /**< Bit mask for USB_SOF */
 #define _USB_GINTSTS_SOF_DEFAULT                   0x00000000UL                              /**< Mode DEFAULT for USB_GINTSTS */
 #define USB_GINTSTS_SOF_DEFAULT                    (_USB_GINTSTS_SOF_DEFAULT << 3)           /**< Shifted mode DEFAULT for USB_GINTSTS */
-#define USB_GINTSTS_RXFLVL                         (0x1UL << 4)                              /**< RxFIFO Non-Empty (host and device) */
+#define USB_GINTSTS_RXFLVL                         (0x1UL << 4)                              /**< RxFIFO Non-Empty host and device */
 #define _USB_GINTSTS_RXFLVL_SHIFT                  4                                         /**< Shift value for USB_RXFLVL */
 #define _USB_GINTSTS_RXFLVL_MASK                   0x10UL                                    /**< Bit mask for USB_RXFLVL */
 #define _USB_GINTSTS_RXFLVL_DEFAULT                0x00000000UL                              /**< Mode DEFAULT for USB_GINTSTS */
 #define USB_GINTSTS_RXFLVL_DEFAULT                 (_USB_GINTSTS_RXFLVL_DEFAULT << 4)        /**< Shifted mode DEFAULT for USB_GINTSTS */
-#define USB_GINTSTS_NPTXFEMP                       (0x1UL << 5)                              /**< Non-Periodic TxFIFO Empty (host only) */
+#define USB_GINTSTS_NPTXFEMP                       (0x1UL << 5)                              /**< Non-Periodic TxFIFO Empty host only */
 #define _USB_GINTSTS_NPTXFEMP_SHIFT                5                                         /**< Shift value for USB_NPTXFEMP */
 #define _USB_GINTSTS_NPTXFEMP_MASK                 0x20UL                                    /**< Bit mask for USB_NPTXFEMP */
 #define _USB_GINTSTS_NPTXFEMP_DEFAULT              0x00000001UL                              /**< Mode DEFAULT for USB_GINTSTS */
 #define USB_GINTSTS_NPTXFEMP_DEFAULT               (_USB_GINTSTS_NPTXFEMP_DEFAULT << 5)      /**< Shifted mode DEFAULT for USB_GINTSTS */
-#define USB_GINTSTS_GINNAKEFF                      (0x1UL << 6)                              /**< Global IN Non-periodic NAK Effective (device only) */
+#define USB_GINTSTS_GINNAKEFF                      (0x1UL << 6)                              /**< Global IN Non-periodic NAK Effective device only */
 #define _USB_GINTSTS_GINNAKEFF_SHIFT               6                                         /**< Shift value for USB_GINNAKEFF */
 #define _USB_GINTSTS_GINNAKEFF_MASK                0x40UL                                    /**< Bit mask for USB_GINNAKEFF */
 #define _USB_GINTSTS_GINNAKEFF_DEFAULT             0x00000000UL                              /**< Mode DEFAULT for USB_GINTSTS */
 #define USB_GINTSTS_GINNAKEFF_DEFAULT              (_USB_GINTSTS_GINNAKEFF_DEFAULT << 6)     /**< Shifted mode DEFAULT for USB_GINTSTS */
-#define USB_GINTSTS_GOUTNAKEFF                     (0x1UL << 7)                              /**< Global OUT NAK Effective (device only) */
+#define USB_GINTSTS_GOUTNAKEFF                     (0x1UL << 7)                              /**< Global OUT NAK Effective device only */
 #define _USB_GINTSTS_GOUTNAKEFF_SHIFT              7                                         /**< Shift value for USB_GOUTNAKEFF */
 #define _USB_GINTSTS_GOUTNAKEFF_MASK               0x80UL                                    /**< Bit mask for USB_GOUTNAKEFF */
 #define _USB_GINTSTS_GOUTNAKEFF_DEFAULT            0x00000000UL                              /**< Mode DEFAULT for USB_GINTSTS */
 #define USB_GINTSTS_GOUTNAKEFF_DEFAULT             (_USB_GINTSTS_GOUTNAKEFF_DEFAULT << 7)    /**< Shifted mode DEFAULT for USB_GINTSTS */
-#define USB_GINTSTS_ERLYSUSP                       (0x1UL << 10)                             /**< Early Suspend (device only) */
+#define USB_GINTSTS_ERLYSUSP                       (0x1UL << 10)                             /**< Early Suspend device only */
 #define _USB_GINTSTS_ERLYSUSP_SHIFT                10                                        /**< Shift value for USB_ERLYSUSP */
 #define _USB_GINTSTS_ERLYSUSP_MASK                 0x400UL                                   /**< Bit mask for USB_ERLYSUSP */
 #define _USB_GINTSTS_ERLYSUSP_DEFAULT              0x00000000UL                              /**< Mode DEFAULT for USB_GINTSTS */
 #define USB_GINTSTS_ERLYSUSP_DEFAULT               (_USB_GINTSTS_ERLYSUSP_DEFAULT << 10)     /**< Shifted mode DEFAULT for USB_GINTSTS */
-#define USB_GINTSTS_USBSUSP                        (0x1UL << 11)                             /**< USB Suspend (device only) */
+#define USB_GINTSTS_USBSUSP                        (0x1UL << 11)                             /**< USB Suspend device only */
 #define _USB_GINTSTS_USBSUSP_SHIFT                 11                                        /**< Shift value for USB_USBSUSP */
 #define _USB_GINTSTS_USBSUSP_MASK                  0x800UL                                   /**< Bit mask for USB_USBSUSP */
 #define _USB_GINTSTS_USBSUSP_DEFAULT               0x00000000UL                              /**< Mode DEFAULT for USB_GINTSTS */
 #define USB_GINTSTS_USBSUSP_DEFAULT                (_USB_GINTSTS_USBSUSP_DEFAULT << 11)      /**< Shifted mode DEFAULT for USB_GINTSTS */
-#define USB_GINTSTS_USBRST                         (0x1UL << 12)                             /**< USB Reset (device only) */
+#define USB_GINTSTS_USBRST                         (0x1UL << 12)                             /**< USB Reset device only */
 #define _USB_GINTSTS_USBRST_SHIFT                  12                                        /**< Shift value for USB_USBRST */
 #define _USB_GINTSTS_USBRST_MASK                   0x1000UL                                  /**< Bit mask for USB_USBRST */
 #define _USB_GINTSTS_USBRST_DEFAULT                0x00000000UL                              /**< Mode DEFAULT for USB_GINTSTS */
 #define USB_GINTSTS_USBRST_DEFAULT                 (_USB_GINTSTS_USBRST_DEFAULT << 12)       /**< Shifted mode DEFAULT for USB_GINTSTS */
-#define USB_GINTSTS_ENUMDONE                       (0x1UL << 13)                             /**< Enumeration Done (device only) */
+#define USB_GINTSTS_ENUMDONE                       (0x1UL << 13)                             /**< Enumeration Done device only */
 #define _USB_GINTSTS_ENUMDONE_SHIFT                13                                        /**< Shift value for USB_ENUMDONE */
 #define _USB_GINTSTS_ENUMDONE_MASK                 0x2000UL                                  /**< Bit mask for USB_ENUMDONE */
 #define _USB_GINTSTS_ENUMDONE_DEFAULT              0x00000000UL                              /**< Mode DEFAULT for USB_GINTSTS */
 #define USB_GINTSTS_ENUMDONE_DEFAULT               (_USB_GINTSTS_ENUMDONE_DEFAULT << 13)     /**< Shifted mode DEFAULT for USB_GINTSTS */
-#define USB_GINTSTS_ISOOUTDROP                     (0x1UL << 14)                             /**< Isochronous OUT Packet Dropped Interrupt (device only) */
+#define USB_GINTSTS_ISOOUTDROP                     (0x1UL << 14)                             /**< Isochronous OUT Packet Dropped Interrupt device only */
 #define _USB_GINTSTS_ISOOUTDROP_SHIFT              14                                        /**< Shift value for USB_ISOOUTDROP */
 #define _USB_GINTSTS_ISOOUTDROP_MASK               0x4000UL                                  /**< Bit mask for USB_ISOOUTDROP */
 #define _USB_GINTSTS_ISOOUTDROP_DEFAULT            0x00000000UL                              /**< Mode DEFAULT for USB_GINTSTS */
 #define USB_GINTSTS_ISOOUTDROP_DEFAULT             (_USB_GINTSTS_ISOOUTDROP_DEFAULT << 14)   /**< Shifted mode DEFAULT for USB_GINTSTS */
-#define USB_GINTSTS_IEPINT                         (0x1UL << 18)                             /**< IN Endpoints Interrupt (device only) */
+#define USB_GINTSTS_EOPF                           (0x1UL << 15)                             /**< End of Periodic Frame Interrupt */
+#define _USB_GINTSTS_EOPF_SHIFT                    15                                        /**< Shift value for USB_EOPF */
+#define _USB_GINTSTS_EOPF_MASK                     0x8000UL                                  /**< Bit mask for USB_EOPF */
+#define _USB_GINTSTS_EOPF_DEFAULT                  0x00000000UL                              /**< Mode DEFAULT for USB_GINTSTS */
+#define USB_GINTSTS_EOPF_DEFAULT                   (_USB_GINTSTS_EOPF_DEFAULT << 15)         /**< Shifted mode DEFAULT for USB_GINTSTS */
+#define USB_GINTSTS_IEPINT                         (0x1UL << 18)                             /**< IN Endpoints Interrupt device only */
 #define _USB_GINTSTS_IEPINT_SHIFT                  18                                        /**< Shift value for USB_IEPINT */
 #define _USB_GINTSTS_IEPINT_MASK                   0x40000UL                                 /**< Bit mask for USB_IEPINT */
 #define _USB_GINTSTS_IEPINT_DEFAULT                0x00000000UL                              /**< Mode DEFAULT for USB_GINTSTS */
 #define USB_GINTSTS_IEPINT_DEFAULT                 (_USB_GINTSTS_IEPINT_DEFAULT << 18)       /**< Shifted mode DEFAULT for USB_GINTSTS */
-#define USB_GINTSTS_OEPINT                         (0x1UL << 19)                             /**< OUT Endpoints Interrupt (device only) */
+#define USB_GINTSTS_OEPINT                         (0x1UL << 19)                             /**< OUT Endpoints Interrupt device only */
 #define _USB_GINTSTS_OEPINT_SHIFT                  19                                        /**< Shift value for USB_OEPINT */
 #define _USB_GINTSTS_OEPINT_MASK                   0x80000UL                                 /**< Bit mask for USB_OEPINT */
 #define _USB_GINTSTS_OEPINT_DEFAULT                0x00000000UL                              /**< Mode DEFAULT for USB_GINTSTS */
 #define USB_GINTSTS_OEPINT_DEFAULT                 (_USB_GINTSTS_OEPINT_DEFAULT << 19)       /**< Shifted mode DEFAULT for USB_GINTSTS */
-#define USB_GINTSTS_INCOMPISOIN                    (0x1UL << 20)                             /**< Incomplete Isochronous IN Transfer (device only) */
+#define USB_GINTSTS_INCOMPISOIN                    (0x1UL << 20)                             /**< Incomplete Isochronous IN Transfer device only */
 #define _USB_GINTSTS_INCOMPISOIN_SHIFT             20                                        /**< Shift value for USB_INCOMPISOIN */
 #define _USB_GINTSTS_INCOMPISOIN_MASK              0x100000UL                                /**< Bit mask for USB_INCOMPISOIN */
 #define _USB_GINTSTS_INCOMPISOIN_DEFAULT           0x00000000UL                              /**< Mode DEFAULT for USB_GINTSTS */
 #define USB_GINTSTS_INCOMPISOIN_DEFAULT            (_USB_GINTSTS_INCOMPISOIN_DEFAULT << 20)  /**< Shifted mode DEFAULT for USB_GINTSTS */
-#define USB_GINTSTS_INCOMPLP                       (0x1UL << 21)                             /**< Incomplete Periodic Transfer (device only) */
+#define USB_GINTSTS_INCOMPLP                       (0x1UL << 21)                             /**< Incomplete Periodic Transfer host and device */
 #define _USB_GINTSTS_INCOMPLP_SHIFT                21                                        /**< Shift value for USB_INCOMPLP */
 #define _USB_GINTSTS_INCOMPLP_MASK                 0x200000UL                                /**< Bit mask for USB_INCOMPLP */
 #define _USB_GINTSTS_INCOMPLP_DEFAULT              0x00000000UL                              /**< Mode DEFAULT for USB_GINTSTS */
 #define USB_GINTSTS_INCOMPLP_DEFAULT               (_USB_GINTSTS_INCOMPLP_DEFAULT << 21)     /**< Shifted mode DEFAULT for USB_GINTSTS */
-#define USB_GINTSTS_FETSUSP                        (0x1UL << 22)                             /**< Data Fetch Suspended (device only) */
+#define USB_GINTSTS_FETSUSP                        (0x1UL << 22)                             /**< Data Fetch Suspended device only */
 #define _USB_GINTSTS_FETSUSP_SHIFT                 22                                        /**< Shift value for USB_FETSUSP */
 #define _USB_GINTSTS_FETSUSP_MASK                  0x400000UL                                /**< Bit mask for USB_FETSUSP */
 #define _USB_GINTSTS_FETSUSP_DEFAULT               0x00000000UL                              /**< Mode DEFAULT for USB_GINTSTS */
 #define USB_GINTSTS_FETSUSP_DEFAULT                (_USB_GINTSTS_FETSUSP_DEFAULT << 22)      /**< Shifted mode DEFAULT for USB_GINTSTS */
-#define USB_GINTSTS_RESETDET                       (0x1UL << 23)                             /**< Reset detected Interrupt (device only) */
+#define USB_GINTSTS_RESETDET                       (0x1UL << 23)                             /**< Reset detected Interrupt device only */
 #define _USB_GINTSTS_RESETDET_SHIFT                23                                        /**< Shift value for USB_RESETDET */
 #define _USB_GINTSTS_RESETDET_MASK                 0x800000UL                                /**< Bit mask for USB_RESETDET */
 #define _USB_GINTSTS_RESETDET_DEFAULT              0x00000000UL                              /**< Mode DEFAULT for USB_GINTSTS */
 #define USB_GINTSTS_RESETDET_DEFAULT               (_USB_GINTSTS_RESETDET_DEFAULT << 23)     /**< Shifted mode DEFAULT for USB_GINTSTS */
-#define USB_GINTSTS_PRTINT                         (0x1UL << 24)                             /**< Host Port Interrupt (host only) */
+#define USB_GINTSTS_PRTINT                         (0x1UL << 24)                             /**< Host Port Interrupt host only */
 #define _USB_GINTSTS_PRTINT_SHIFT                  24                                        /**< Shift value for USB_PRTINT */
 #define _USB_GINTSTS_PRTINT_MASK                   0x1000000UL                               /**< Bit mask for USB_PRTINT */
 #define _USB_GINTSTS_PRTINT_DEFAULT                0x00000000UL                              /**< Mode DEFAULT for USB_GINTSTS */
 #define USB_GINTSTS_PRTINT_DEFAULT                 (_USB_GINTSTS_PRTINT_DEFAULT << 24)       /**< Shifted mode DEFAULT for USB_GINTSTS */
-#define USB_GINTSTS_HCHINT                         (0x1UL << 25)                             /**< Host Channels Interrupt (host only) */
+#define USB_GINTSTS_HCHINT                         (0x1UL << 25)                             /**< Host Channels Interrupt host only */
 #define _USB_GINTSTS_HCHINT_SHIFT                  25                                        /**< Shift value for USB_HCHINT */
 #define _USB_GINTSTS_HCHINT_MASK                   0x2000000UL                               /**< Bit mask for USB_HCHINT */
 #define _USB_GINTSTS_HCHINT_DEFAULT                0x00000000UL                              /**< Mode DEFAULT for USB_GINTSTS */
 #define USB_GINTSTS_HCHINT_DEFAULT                 (_USB_GINTSTS_HCHINT_DEFAULT << 25)       /**< Shifted mode DEFAULT for USB_GINTSTS */
-#define USB_GINTSTS_PTXFEMP                        (0x1UL << 26)                             /**< Periodic TxFIFO Empty (host only) */
+#define USB_GINTSTS_PTXFEMP                        (0x1UL << 26)                             /**< Periodic TxFIFO Empty host only */
 #define _USB_GINTSTS_PTXFEMP_SHIFT                 26                                        /**< Shift value for USB_PTXFEMP */
 #define _USB_GINTSTS_PTXFEMP_MASK                  0x4000000UL                               /**< Bit mask for USB_PTXFEMP */
 #define _USB_GINTSTS_PTXFEMP_DEFAULT               0x00000001UL                              /**< Mode DEFAULT for USB_GINTSTS */
 #define USB_GINTSTS_PTXFEMP_DEFAULT                (_USB_GINTSTS_PTXFEMP_DEFAULT << 26)      /**< Shifted mode DEFAULT for USB_GINTSTS */
-#define USB_GINTSTS_CONIDSTSCHNG                   (0x1UL << 28)                             /**< Connector ID Status Change (host and device) */
+#define USB_GINTSTS_CONIDSTSCHNG                   (0x1UL << 28)                             /**< Connector ID Status Change host and device */
 #define _USB_GINTSTS_CONIDSTSCHNG_SHIFT            28                                        /**< Shift value for USB_CONIDSTSCHNG */
 #define _USB_GINTSTS_CONIDSTSCHNG_MASK             0x10000000UL                              /**< Bit mask for USB_CONIDSTSCHNG */
 #define _USB_GINTSTS_CONIDSTSCHNG_DEFAULT          0x00000001UL                              /**< Mode DEFAULT for USB_GINTSTS */
 #define USB_GINTSTS_CONIDSTSCHNG_DEFAULT           (_USB_GINTSTS_CONIDSTSCHNG_DEFAULT << 28) /**< Shifted mode DEFAULT for USB_GINTSTS */
-#define USB_GINTSTS_DISCONNINT                     (0x1UL << 29)                             /**< Disconnect Detected Interrupt (host only) */
+#define USB_GINTSTS_DISCONNINT                     (0x1UL << 29)                             /**< Disconnect Detected Interrupt host only */
 #define _USB_GINTSTS_DISCONNINT_SHIFT              29                                        /**< Shift value for USB_DISCONNINT */
 #define _USB_GINTSTS_DISCONNINT_MASK               0x20000000UL                              /**< Bit mask for USB_DISCONNINT */
 #define _USB_GINTSTS_DISCONNINT_DEFAULT            0x00000000UL                              /**< Mode DEFAULT for USB_GINTSTS */
 #define USB_GINTSTS_DISCONNINT_DEFAULT             (_USB_GINTSTS_DISCONNINT_DEFAULT << 29)   /**< Shifted mode DEFAULT for USB_GINTSTS */
-#define USB_GINTSTS_SESSREQINT                     (0x1UL << 30)                             /**< Session Request/New Session Detected Interrupt (host and device) */
+#define USB_GINTSTS_SESSREQINT                     (0x1UL << 30)                             /**< Session Request/New Session Detected Interrupt host and device */
 #define _USB_GINTSTS_SESSREQINT_SHIFT              30                                        /**< Shift value for USB_SESSREQINT */
 #define _USB_GINTSTS_SESSREQINT_MASK               0x40000000UL                              /**< Bit mask for USB_SESSREQINT */
 #define _USB_GINTSTS_SESSREQINT_DEFAULT            0x00000000UL                              /**< Mode DEFAULT for USB_GINTSTS */
 #define USB_GINTSTS_SESSREQINT_DEFAULT             (_USB_GINTSTS_SESSREQINT_DEFAULT << 30)   /**< Shifted mode DEFAULT for USB_GINTSTS */
-#define USB_GINTSTS_WKUPINT                        (0x1UL << 31)                             /**< Resume/Remote Wakeup Detected Interrupt (host and device) */
+#define USB_GINTSTS_WKUPINT                        (0x1UL << 31)                             /**< Resume/Remote Wakeup Detected Interrupt host and device */
 #define _USB_GINTSTS_WKUPINT_SHIFT                 31                                        /**< Shift value for USB_WKUPINT */
 #define _USB_GINTSTS_WKUPINT_MASK                  0x80000000UL                              /**< Bit mask for USB_WKUPINT */
 #define _USB_GINTSTS_WKUPINT_DEFAULT               0x00000000UL                              /**< Mode DEFAULT for USB_GINTSTS */
@@ -759,128 +750,133 @@
 
 /* Bit fields for USB GINTMSK */
 #define _USB_GINTMSK_RESETVALUE                    0x00000000UL                                 /**< Default value for USB_GINTMSK */
-#define _USB_GINTMSK_MASK                          0xF7FC7CFEUL                                 /**< Mask for USB_GINTMSK */
-#define USB_GINTMSK_MODEMISMSK                     (0x1UL << 1)                                 /**< Mode Mismatch Interrupt Mask (host and device) */
+#define _USB_GINTMSK_MASK                          0xF7FCFCFEUL                                 /**< Mask for USB_GINTMSK */
+#define USB_GINTMSK_MODEMISMSK                     (0x1UL << 1)                                 /**< Mode Mismatch Interrupt Mask host and device */
 #define _USB_GINTMSK_MODEMISMSK_SHIFT              1                                            /**< Shift value for USB_MODEMISMSK */
 #define _USB_GINTMSK_MODEMISMSK_MASK               0x2UL                                        /**< Bit mask for USB_MODEMISMSK */
 #define _USB_GINTMSK_MODEMISMSK_DEFAULT            0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
 #define USB_GINTMSK_MODEMISMSK_DEFAULT             (_USB_GINTMSK_MODEMISMSK_DEFAULT << 1)       /**< Shifted mode DEFAULT for USB_GINTMSK */
-#define USB_GINTMSK_OTGINTMSK                      (0x1UL << 2)                                 /**< OTG Interrupt Mask (host and device) */
+#define USB_GINTMSK_OTGINTMSK                      (0x1UL << 2)                                 /**< OTG Interrupt Mask host and device */
 #define _USB_GINTMSK_OTGINTMSK_SHIFT               2                                            /**< Shift value for USB_OTGINTMSK */
 #define _USB_GINTMSK_OTGINTMSK_MASK                0x4UL                                        /**< Bit mask for USB_OTGINTMSK */
 #define _USB_GINTMSK_OTGINTMSK_DEFAULT             0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
 #define USB_GINTMSK_OTGINTMSK_DEFAULT              (_USB_GINTMSK_OTGINTMSK_DEFAULT << 2)        /**< Shifted mode DEFAULT for USB_GINTMSK */
-#define USB_GINTMSK_SOFMSK                         (0x1UL << 3)                                 /**< Start of Frame Mask (host and device) */
+#define USB_GINTMSK_SOFMSK                         (0x1UL << 3)                                 /**< Start of Frame Mask host and device */
 #define _USB_GINTMSK_SOFMSK_SHIFT                  3                                            /**< Shift value for USB_SOFMSK */
 #define _USB_GINTMSK_SOFMSK_MASK                   0x8UL                                        /**< Bit mask for USB_SOFMSK */
 #define _USB_GINTMSK_SOFMSK_DEFAULT                0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
 #define USB_GINTMSK_SOFMSK_DEFAULT                 (_USB_GINTMSK_SOFMSK_DEFAULT << 3)           /**< Shifted mode DEFAULT for USB_GINTMSK */
-#define USB_GINTMSK_RXFLVLMSK                      (0x1UL << 4)                                 /**< Receive FIFO Non-Empty Mask (host and device) */
+#define USB_GINTMSK_RXFLVLMSK                      (0x1UL << 4)                                 /**< Receive FIFO Non-Empty Mask host and device */
 #define _USB_GINTMSK_RXFLVLMSK_SHIFT               4                                            /**< Shift value for USB_RXFLVLMSK */
 #define _USB_GINTMSK_RXFLVLMSK_MASK                0x10UL                                       /**< Bit mask for USB_RXFLVLMSK */
 #define _USB_GINTMSK_RXFLVLMSK_DEFAULT             0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
 #define USB_GINTMSK_RXFLVLMSK_DEFAULT              (_USB_GINTMSK_RXFLVLMSK_DEFAULT << 4)        /**< Shifted mode DEFAULT for USB_GINTMSK */
-#define USB_GINTMSK_NPTXFEMPMSK                    (0x1UL << 5)                                 /**< Non-Periodic TxFIFO Empty Mask (host only) */
+#define USB_GINTMSK_NPTXFEMPMSK                    (0x1UL << 5)                                 /**< Non-Periodic TxFIFO Empty Mask host only */
 #define _USB_GINTMSK_NPTXFEMPMSK_SHIFT             5                                            /**< Shift value for USB_NPTXFEMPMSK */
 #define _USB_GINTMSK_NPTXFEMPMSK_MASK              0x20UL                                       /**< Bit mask for USB_NPTXFEMPMSK */
 #define _USB_GINTMSK_NPTXFEMPMSK_DEFAULT           0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
 #define USB_GINTMSK_NPTXFEMPMSK_DEFAULT            (_USB_GINTMSK_NPTXFEMPMSK_DEFAULT << 5)      /**< Shifted mode DEFAULT for USB_GINTMSK */
-#define USB_GINTMSK_GINNAKEFFMSK                   (0x1UL << 6)                                 /**< Global Non-periodic IN NAK Effective Mask (device only) */
+#define USB_GINTMSK_GINNAKEFFMSK                   (0x1UL << 6)                                 /**< Global Non-periodic IN NAK Effective Mask device only */
 #define _USB_GINTMSK_GINNAKEFFMSK_SHIFT            6                                            /**< Shift value for USB_GINNAKEFFMSK */
 #define _USB_GINTMSK_GINNAKEFFMSK_MASK             0x40UL                                       /**< Bit mask for USB_GINNAKEFFMSK */
 #define _USB_GINTMSK_GINNAKEFFMSK_DEFAULT          0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
 #define USB_GINTMSK_GINNAKEFFMSK_DEFAULT           (_USB_GINTMSK_GINNAKEFFMSK_DEFAULT << 6)     /**< Shifted mode DEFAULT for USB_GINTMSK */
-#define USB_GINTMSK_GOUTNAKEFFMSK                  (0x1UL << 7)                                 /**< Global OUT NAK Effective Mask (device only) */
+#define USB_GINTMSK_GOUTNAKEFFMSK                  (0x1UL << 7)                                 /**< Global OUT NAK Effective Mask device only */
 #define _USB_GINTMSK_GOUTNAKEFFMSK_SHIFT           7                                            /**< Shift value for USB_GOUTNAKEFFMSK */
 #define _USB_GINTMSK_GOUTNAKEFFMSK_MASK            0x80UL                                       /**< Bit mask for USB_GOUTNAKEFFMSK */
 #define _USB_GINTMSK_GOUTNAKEFFMSK_DEFAULT         0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
 #define USB_GINTMSK_GOUTNAKEFFMSK_DEFAULT          (_USB_GINTMSK_GOUTNAKEFFMSK_DEFAULT << 7)    /**< Shifted mode DEFAULT for USB_GINTMSK */
-#define USB_GINTMSK_ERLYSUSPMSK                    (0x1UL << 10)                                /**< Early Suspend Mask (device only) */
+#define USB_GINTMSK_ERLYSUSPMSK                    (0x1UL << 10)                                /**< Early Suspend Mask device only */
 #define _USB_GINTMSK_ERLYSUSPMSK_SHIFT             10                                           /**< Shift value for USB_ERLYSUSPMSK */
 #define _USB_GINTMSK_ERLYSUSPMSK_MASK              0x400UL                                      /**< Bit mask for USB_ERLYSUSPMSK */
 #define _USB_GINTMSK_ERLYSUSPMSK_DEFAULT           0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
 #define USB_GINTMSK_ERLYSUSPMSK_DEFAULT            (_USB_GINTMSK_ERLYSUSPMSK_DEFAULT << 10)     /**< Shifted mode DEFAULT for USB_GINTMSK */
-#define USB_GINTMSK_USBSUSPMSK                     (0x1UL << 11)                                /**< USB Suspend Mask (device only) */
+#define USB_GINTMSK_USBSUSPMSK                     (0x1UL << 11)                                /**< USB Suspend Mask device only */
 #define _USB_GINTMSK_USBSUSPMSK_SHIFT              11                                           /**< Shift value for USB_USBSUSPMSK */
 #define _USB_GINTMSK_USBSUSPMSK_MASK               0x800UL                                      /**< Bit mask for USB_USBSUSPMSK */
 #define _USB_GINTMSK_USBSUSPMSK_DEFAULT            0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
 #define USB_GINTMSK_USBSUSPMSK_DEFAULT             (_USB_GINTMSK_USBSUSPMSK_DEFAULT << 11)      /**< Shifted mode DEFAULT for USB_GINTMSK */
-#define USB_GINTMSK_USBRSTMSK                      (0x1UL << 12)                                /**< USB Reset Mask (device only) */
+#define USB_GINTMSK_USBRSTMSK                      (0x1UL << 12)                                /**< USB Reset Mask device only */
 #define _USB_GINTMSK_USBRSTMSK_SHIFT               12                                           /**< Shift value for USB_USBRSTMSK */
 #define _USB_GINTMSK_USBRSTMSK_MASK                0x1000UL                                     /**< Bit mask for USB_USBRSTMSK */
 #define _USB_GINTMSK_USBRSTMSK_DEFAULT             0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
 #define USB_GINTMSK_USBRSTMSK_DEFAULT              (_USB_GINTMSK_USBRSTMSK_DEFAULT << 12)       /**< Shifted mode DEFAULT for USB_GINTMSK */
-#define USB_GINTMSK_ENUMDONEMSK                    (0x1UL << 13)                                /**< Enumeration Done Mask (device only) */
+#define USB_GINTMSK_ENUMDONEMSK                    (0x1UL << 13)                                /**< Enumeration Done Mask device only */
 #define _USB_GINTMSK_ENUMDONEMSK_SHIFT             13                                           /**< Shift value for USB_ENUMDONEMSK */
 #define _USB_GINTMSK_ENUMDONEMSK_MASK              0x2000UL                                     /**< Bit mask for USB_ENUMDONEMSK */
 #define _USB_GINTMSK_ENUMDONEMSK_DEFAULT           0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
 #define USB_GINTMSK_ENUMDONEMSK_DEFAULT            (_USB_GINTMSK_ENUMDONEMSK_DEFAULT << 13)     /**< Shifted mode DEFAULT for USB_GINTMSK */
-#define USB_GINTMSK_ISOOUTDROPMSK                  (0x1UL << 14)                                /**< Isochronous OUT Packet Dropped Interrupt Mask (device only) */
+#define USB_GINTMSK_ISOOUTDROPMSK                  (0x1UL << 14)                                /**< Isochronous OUT Packet Dropped Interrupt Mask device only */
 #define _USB_GINTMSK_ISOOUTDROPMSK_SHIFT           14                                           /**< Shift value for USB_ISOOUTDROPMSK */
 #define _USB_GINTMSK_ISOOUTDROPMSK_MASK            0x4000UL                                     /**< Bit mask for USB_ISOOUTDROPMSK */
 #define _USB_GINTMSK_ISOOUTDROPMSK_DEFAULT         0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
 #define USB_GINTMSK_ISOOUTDROPMSK_DEFAULT          (_USB_GINTMSK_ISOOUTDROPMSK_DEFAULT << 14)   /**< Shifted mode DEFAULT for USB_GINTMSK */
-#define USB_GINTMSK_IEPINTMSK                      (0x1UL << 18)                                /**< IN Endpoints Interrupt Mask (device only) */
+#define USB_GINTMSK_EOPFMSK                        (0x1UL << 15)                                /**< End of Periodic Frame Interrupt Mask device only */
+#define _USB_GINTMSK_EOPFMSK_SHIFT                 15                                           /**< Shift value for USB_EOPFMSK */
+#define _USB_GINTMSK_EOPFMSK_MASK                  0x8000UL                                     /**< Bit mask for USB_EOPFMSK */
+#define _USB_GINTMSK_EOPFMSK_DEFAULT               0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
+#define USB_GINTMSK_EOPFMSK_DEFAULT                (_USB_GINTMSK_EOPFMSK_DEFAULT << 15)         /**< Shifted mode DEFAULT for USB_GINTMSK */
+#define USB_GINTMSK_IEPINTMSK                      (0x1UL << 18)                                /**< IN Endpoints Interrupt Mask device only */
 #define _USB_GINTMSK_IEPINTMSK_SHIFT               18                                           /**< Shift value for USB_IEPINTMSK */
 #define _USB_GINTMSK_IEPINTMSK_MASK                0x40000UL                                    /**< Bit mask for USB_IEPINTMSK */
 #define _USB_GINTMSK_IEPINTMSK_DEFAULT             0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
 #define USB_GINTMSK_IEPINTMSK_DEFAULT              (_USB_GINTMSK_IEPINTMSK_DEFAULT << 18)       /**< Shifted mode DEFAULT for USB_GINTMSK */
-#define USB_GINTMSK_OEPINTMSK                      (0x1UL << 19)                                /**< OUT Endpoints Interrupt Mask (device only) */
+#define USB_GINTMSK_OEPINTMSK                      (0x1UL << 19)                                /**< OUT Endpoints Interrupt Mask device only */
 #define _USB_GINTMSK_OEPINTMSK_SHIFT               19                                           /**< Shift value for USB_OEPINTMSK */
 #define _USB_GINTMSK_OEPINTMSK_MASK                0x80000UL                                    /**< Bit mask for USB_OEPINTMSK */
 #define _USB_GINTMSK_OEPINTMSK_DEFAULT             0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
 #define USB_GINTMSK_OEPINTMSK_DEFAULT              (_USB_GINTMSK_OEPINTMSK_DEFAULT << 19)       /**< Shifted mode DEFAULT for USB_GINTMSK */
-#define USB_GINTMSK_INCOMPISOINMSK                 (0x1UL << 20)                                /**< Incomplete Isochronous IN Transfer Mask (device only) */
+#define USB_GINTMSK_INCOMPISOINMSK                 (0x1UL << 20)                                /**< Incomplete Isochronous IN Transfer Mask device only */
 #define _USB_GINTMSK_INCOMPISOINMSK_SHIFT          20                                           /**< Shift value for USB_INCOMPISOINMSK */
 #define _USB_GINTMSK_INCOMPISOINMSK_MASK           0x100000UL                                   /**< Bit mask for USB_INCOMPISOINMSK */
 #define _USB_GINTMSK_INCOMPISOINMSK_DEFAULT        0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
 #define USB_GINTMSK_INCOMPISOINMSK_DEFAULT         (_USB_GINTMSK_INCOMPISOINMSK_DEFAULT << 20)  /**< Shifted mode DEFAULT for USB_GINTMSK */
-#define USB_GINTMSK_INCOMPLPMSK                    (0x1UL << 21)                                /**< Incomplete Periodic Transfer Mask (host only) */
+#define USB_GINTMSK_INCOMPLPMSK                    (0x1UL << 21)                                /**< Incomplete Periodic Transfer Mask host and device */
 #define _USB_GINTMSK_INCOMPLPMSK_SHIFT             21                                           /**< Shift value for USB_INCOMPLPMSK */
 #define _USB_GINTMSK_INCOMPLPMSK_MASK              0x200000UL                                   /**< Bit mask for USB_INCOMPLPMSK */
 #define _USB_GINTMSK_INCOMPLPMSK_DEFAULT           0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
 #define USB_GINTMSK_INCOMPLPMSK_DEFAULT            (_USB_GINTMSK_INCOMPLPMSK_DEFAULT << 21)     /**< Shifted mode DEFAULT for USB_GINTMSK */
-#define USB_GINTMSK_FETSUSPMSK                     (0x1UL << 22)                                /**< Data Fetch Suspended Mask (device only) */
+#define USB_GINTMSK_FETSUSPMSK                     (0x1UL << 22)                                /**< Data Fetch Suspended Mask device only */
 #define _USB_GINTMSK_FETSUSPMSK_SHIFT              22                                           /**< Shift value for USB_FETSUSPMSK */
 #define _USB_GINTMSK_FETSUSPMSK_MASK               0x400000UL                                   /**< Bit mask for USB_FETSUSPMSK */
 #define _USB_GINTMSK_FETSUSPMSK_DEFAULT            0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
 #define USB_GINTMSK_FETSUSPMSK_DEFAULT             (_USB_GINTMSK_FETSUSPMSK_DEFAULT << 22)      /**< Shifted mode DEFAULT for USB_GINTMSK */
-#define USB_GINTMSK_RESETDETMSK                    (0x1UL << 23)                                /**< Reset detected Interrupt Mask (device only) */
+#define USB_GINTMSK_RESETDETMSK                    (0x1UL << 23)                                /**< Reset detected Interrupt Mask device only */
 #define _USB_GINTMSK_RESETDETMSK_SHIFT             23                                           /**< Shift value for USB_RESETDETMSK */
 #define _USB_GINTMSK_RESETDETMSK_MASK              0x800000UL                                   /**< Bit mask for USB_RESETDETMSK */
 #define _USB_GINTMSK_RESETDETMSK_DEFAULT           0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
 #define USB_GINTMSK_RESETDETMSK_DEFAULT            (_USB_GINTMSK_RESETDETMSK_DEFAULT << 23)     /**< Shifted mode DEFAULT for USB_GINTMSK */
-#define USB_GINTMSK_PRTINTMSK                      (0x1UL << 24)                                /**< Host Port Interrupt Mask (host only) */
+#define USB_GINTMSK_PRTINTMSK                      (0x1UL << 24)                                /**< Host Port Interrupt Mask host only */
 #define _USB_GINTMSK_PRTINTMSK_SHIFT               24                                           /**< Shift value for USB_PRTINTMSK */
 #define _USB_GINTMSK_PRTINTMSK_MASK                0x1000000UL                                  /**< Bit mask for USB_PRTINTMSK */
 #define _USB_GINTMSK_PRTINTMSK_DEFAULT             0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
 #define USB_GINTMSK_PRTINTMSK_DEFAULT              (_USB_GINTMSK_PRTINTMSK_DEFAULT << 24)       /**< Shifted mode DEFAULT for USB_GINTMSK */
-#define USB_GINTMSK_HCHINTMSK                      (0x1UL << 25)                                /**< Host Channels Interrupt Mask (host only) */
+#define USB_GINTMSK_HCHINTMSK                      (0x1UL << 25)                                /**< Host Channels Interrupt Mask host only */
 #define _USB_GINTMSK_HCHINTMSK_SHIFT               25                                           /**< Shift value for USB_HCHINTMSK */
 #define _USB_GINTMSK_HCHINTMSK_MASK                0x2000000UL                                  /**< Bit mask for USB_HCHINTMSK */
 #define _USB_GINTMSK_HCHINTMSK_DEFAULT             0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
 #define USB_GINTMSK_HCHINTMSK_DEFAULT              (_USB_GINTMSK_HCHINTMSK_DEFAULT << 25)       /**< Shifted mode DEFAULT for USB_GINTMSK */
-#define USB_GINTMSK_PTXFEMPMSK                     (0x1UL << 26)                                /**< Periodic TxFIFO Empty Mask (host only) */
+#define USB_GINTMSK_PTXFEMPMSK                     (0x1UL << 26)                                /**< Periodic TxFIFO Empty Mask host only */
 #define _USB_GINTMSK_PTXFEMPMSK_SHIFT              26                                           /**< Shift value for USB_PTXFEMPMSK */
 #define _USB_GINTMSK_PTXFEMPMSK_MASK               0x4000000UL                                  /**< Bit mask for USB_PTXFEMPMSK */
 #define _USB_GINTMSK_PTXFEMPMSK_DEFAULT            0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
 #define USB_GINTMSK_PTXFEMPMSK_DEFAULT             (_USB_GINTMSK_PTXFEMPMSK_DEFAULT << 26)      /**< Shifted mode DEFAULT for USB_GINTMSK */
-#define USB_GINTMSK_CONIDSTSCHNGMSK                (0x1UL << 28)                                /**< Connector ID Status Change Mask (host and device) */
+#define USB_GINTMSK_CONIDSTSCHNGMSK                (0x1UL << 28)                                /**< Connector ID Status Change Mask host and device */
 #define _USB_GINTMSK_CONIDSTSCHNGMSK_SHIFT         28                                           /**< Shift value for USB_CONIDSTSCHNGMSK */
 #define _USB_GINTMSK_CONIDSTSCHNGMSK_MASK          0x10000000UL                                 /**< Bit mask for USB_CONIDSTSCHNGMSK */
 #define _USB_GINTMSK_CONIDSTSCHNGMSK_DEFAULT       0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
 #define USB_GINTMSK_CONIDSTSCHNGMSK_DEFAULT        (_USB_GINTMSK_CONIDSTSCHNGMSK_DEFAULT << 28) /**< Shifted mode DEFAULT for USB_GINTMSK */
-#define USB_GINTMSK_DISCONNINTMSK                  (0x1UL << 29)                                /**< Disconnect Detected Interrupt Mask (host and device) */
+#define USB_GINTMSK_DISCONNINTMSK                  (0x1UL << 29)                                /**< Disconnect Detected Interrupt Mask host and device */
 #define _USB_GINTMSK_DISCONNINTMSK_SHIFT           29                                           /**< Shift value for USB_DISCONNINTMSK */
 #define _USB_GINTMSK_DISCONNINTMSK_MASK            0x20000000UL                                 /**< Bit mask for USB_DISCONNINTMSK */
 #define _USB_GINTMSK_DISCONNINTMSK_DEFAULT         0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
 #define USB_GINTMSK_DISCONNINTMSK_DEFAULT          (_USB_GINTMSK_DISCONNINTMSK_DEFAULT << 29)   /**< Shifted mode DEFAULT for USB_GINTMSK */
-#define USB_GINTMSK_SESSREQINTMSK                  (0x1UL << 30)                                /**< Session Request/New Session Detected Interrupt Mask (host and device) */
+#define USB_GINTMSK_SESSREQINTMSK                  (0x1UL << 30)                                /**< Session Request/New Session Detected Interrupt Mask host and device */
 #define _USB_GINTMSK_SESSREQINTMSK_SHIFT           30                                           /**< Shift value for USB_SESSREQINTMSK */
 #define _USB_GINTMSK_SESSREQINTMSK_MASK            0x40000000UL                                 /**< Bit mask for USB_SESSREQINTMSK */
 #define _USB_GINTMSK_SESSREQINTMSK_DEFAULT         0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
 #define USB_GINTMSK_SESSREQINTMSK_DEFAULT          (_USB_GINTMSK_SESSREQINTMSK_DEFAULT << 30)   /**< Shifted mode DEFAULT for USB_GINTMSK */
-#define USB_GINTMSK_WKUPINTMSK                     (0x1UL << 31)                                /**< Resume/Remote Wakeup Detected Interrupt Mask (host and device) */
+#define USB_GINTMSK_WKUPINTMSK                     (0x1UL << 31)                                /**< Resume/Remote Wakeup Detected Interrupt Mask host and device */
 #define _USB_GINTMSK_WKUPINTMSK_SHIFT              31                                           /**< Shift value for USB_WKUPINTMSK */
 #define _USB_GINTMSK_WKUPINTMSK_MASK               0x80000000UL                                 /**< Bit mask for USB_WKUPINTMSK */
 #define _USB_GINTMSK_WKUPINTMSK_DEFAULT            0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
@@ -2657,5 +2653,5 @@
 #define USB_FIFORAM_FIFORAM_DEFAULT                (_USB_FIFORAM_FIFORAM_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_FIFORAM */
 
 /** @} End of group EFM32GG_USB */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_usb_diep.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_usb_diep.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32gg_usb_diep.h
  * @brief EFM32GG_USB_DIEP register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @brief USB_DIEP EFM32GG USB DIEP
  *****************************************************************************/
 typedef struct
@@ -41,7 +45,9 @@
   __IO uint32_t TSIZ;         /**< Device IN Endpoint x+1 Transfer Size Register  */
   __IO uint32_t DMAADDR;      /**< Device IN Endpoint x+1 DMA Address Register  */
   __I uint32_t  TXFSTS;       /**< Device IN Endpoint x+1 Transmit FIFO Status Register  */
-
   uint32_t      RESERVED2[1]; /**< Reserved future */
 } USB_DIEP_TypeDef;
 
+/** @} End of group Parts */
+
+

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_usb_doep.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_usb_doep.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32gg_usb_doep.h
  * @brief EFM32GG_USB_DOEP register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @brief USB_DOEP EFM32GG USB DOEP
  *****************************************************************************/
 typedef struct
@@ -40,7 +44,9 @@
   uint32_t      RESERVED1[1]; /**< Reserved for future use **/
   __IO uint32_t TSIZ;         /**< Device OUT Endpoint x+1 Transfer Size Register  */
   __IO uint32_t DMAADDR;      /**< Device OUT Endpoint x+1 DMA Address Register  */
-
   uint32_t      RESERVED2[2]; /**< Reserved future */
 } USB_DOEP_TypeDef;
 
+/** @} End of group Parts */
+
+

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_usb_hc.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_usb_hc.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32gg_usb_hc.h
  * @brief EFM32GG_USB_HC register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @brief USB_HC EFM32GG USB HC
  *****************************************************************************/
 typedef struct
@@ -40,7 +44,9 @@
   __IO uint32_t INTMSK;       /**< Host Channel x Interrupt Mask Register  */
   __IO uint32_t TSIZ;         /**< Host Channel x Transfer Size Register  */
   __IO uint32_t DMAADDR;      /**< Host Channel x DMA Address Register  */
-
   uint32_t      RESERVED1[2]; /**< Reserved future */
 } USB_HC_TypeDef;
 
+/** @} End of group Parts */
+
+

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_vcmp.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_vcmp.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32gg_vcmp.h
  * @brief EFM32GG_VCMP register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32GG_VCMP
  * @{
  * @brief EFM32GG_VCMP Register Declaration
@@ -192,5 +196,5 @@
 #define VCMP_IFC_WARMUP_DEFAULT             (_VCMP_IFC_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for VCMP_IFC */
 
 /** @} End of group EFM32GG_VCMP */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_wdog.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_wdog.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32gg_wdog.h
  * @brief EFM32GG_WDOG register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32GG_WDOG
  * @{
  * @brief EFM32GG_WDOG Register Declaration
@@ -128,5 +132,5 @@
 #define WDOG_SYNCBUSY_CMD_DEFAULT        (_WDOG_SYNCBUSY_CMD_DEFAULT << 1)  /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */
 
 /** @} End of group EFM32GG_WDOG */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/em_device.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/em_device.h	Fri Jan 15 07:45:16 2016 +0000
@@ -9,11 +9,13 @@
  * @verbatim
  * Example: Add "-DEFM32G890F128" to your build options, to define part
  *          Add "#include "em_device.h" to your source files
+ *
+ *
  * @endverbatim
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -29,19 +31,18 @@
  * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
  * has no obligation to support this Software. Silicon Laboratories, Inc. is
  * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of 
+ * kind, including, but not limited to, any implied warranties of
  * merchantability or fitness for any particular purpose or warranties against
  * infringement of any proprietary rights of a third party.
  *
- * Silicon Laboratories, Inc. will not be liable for any consequential, 
- * incidental, or special damages, or any other relief, or for any claim by 
+ * Silicon Laboratories, Inc. will not be liable for any consequential,
+ * incidental, or special damages, or any other relief, or for any claim by
  * any third party, arising from your use of this Software.
  *
  *****************************************************************************/
 
-#ifndef __EM_DEVICE_H
-#define __EM_DEVICE_H
-
+#ifndef EM_DEVICE_H
+#define EM_DEVICE_H
 
 #if defined(EFM32GG230F1024)
 #include "efm32gg230f1024.h"
@@ -133,6 +134,12 @@
 #elif defined(EFM32GG895F512)
 #include "efm32gg895f512.h"
 
+#elif defined(EFM32GG900F1024)
+#include "efm32gg900f1024.h"
+
+#elif defined(EFM32GG900F512)
+#include "efm32gg900f512.h"
+
 #elif defined(EFM32GG940F1024)
 #include "efm32gg940f1024.h"
 
@@ -163,9 +170,7 @@
 #elif defined(EFM32GG995F512)
 #include "efm32gg995f512.h"
 
-
 #else
 #error "em_device.h: PART NUMBER undefined"
 #endif
-
-#endif
+#endif /* EM_DEVICE_H */

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/system_efm32gg.c	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/system_efm32gg.c	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /***************************************************************************//**
  * @file system_efm32gg.c
  * @brief CMSIS Cortex-M3 System Layer for EFM32GG devices.
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -20,12 +20,12 @@
  * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
  * has no obligation to support this Software. Silicon Laboratories, Inc. is
  * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of 
+ * kind, including, but not limited to, any implied warranties of
  * merchantability or fitness for any particular purpose or warranties against
  * infringement of any proprietary rights of a third party.
  *
- * Silicon Laboratories, Inc. will not be liable for any consequential, 
- * incidental, or special damages, or any other relief, or for any claim by 
+ * Silicon Laboratories, Inc. will not be liable for any consequential,
+ * incidental, or special damages, or any other relief, or for any claim by
  * any third party, arising from your use of this Software.
  *
  *****************************************************************************/
@@ -54,27 +54,27 @@
 /* SW footprint. */
 
 #ifndef EFM32_HFXO_FREQ
-#ifdef _EFM32_GIANT_FAMILY
 #define EFM32_HFXO_FREQ (48000000UL)
-#else
-#define EFM32_HFXO_FREQ (32000000UL)
 #endif
-#endif
+
+#define EFM32_HFRCO_MAX_FREQ (28000000UL)
+
 /* Do not define variable if HF crystal oscillator not present */
 #if (EFM32_HFXO_FREQ > 0)
 /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
-/** System HFXO clock. */ 
+/** System HFXO clock. */
 static uint32_t SystemHFXOClock = EFM32_HFXO_FREQ;
 /** @endcond (DO_NOT_INCLUDE_WITH_DOXYGEN) */
 #endif
 
-#ifndef EFM32_LFXO_FREQ 
+#ifndef EFM32_LFXO_FREQ
 #define EFM32_LFXO_FREQ (EFM32_LFRCO_FREQ)
 #endif
+
 /* Do not define variable if LF crystal oscillator not present */
 #if (EFM32_LFXO_FREQ > 0)
 /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
-/** System LFXO clock. */ 
+/** System LFXO clock. */
 static uint32_t SystemLFXOClock = EFM32_LFXO_FREQ;
 /** @endcond (DO_NOT_INCLUDE_WITH_DOXYGEN) */
 #endif
@@ -123,13 +123,11 @@
 uint32_t SystemCoreClockGet(void)
 {
   uint32_t ret;
-  
+
   ret = SystemHFClockGet();
-#if defined (_EFM32_GIANT_FAMILY)
   /* Leopard/Giant Gecko has an additional divider */
   ret =  ret / (1 + ((CMU->CTRL & _CMU_CTRL_HFCLKDIV_MASK)>>_CMU_CTRL_HFCLKDIV_SHIFT));
-#endif
-  ret >>= (CMU->HFCORECLKDIV & _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK) >> 
+  ret >>= (CMU->HFCORECLKDIV & _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK) >>
           _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT;
 
   /* Keep CMSIS variable up-to-date just in case */
@@ -141,6 +139,23 @@
 
 /***************************************************************************//**
  * @brief
+ *   Get the maximum core clock frequency.
+ *
+ * @note
+ *   This is an EFR32 proprietary function, not part of the CMSIS definition.
+ *
+ * @return
+ *   The maximum core clock frequency in Hz.
+ ******************************************************************************/
+uint32_t SystemMaxCoreClockGet(void)
+{
+  return (EFM32_HFRCO_MAX_FREQ > EFM32_HFXO_FREQ ? \
+          EFM32_HFRCO_MAX_FREQ : EFM32_HFXO_FREQ);
+}
+
+
+/***************************************************************************//**
+ * @brief
  *   Get the current HFCLK frequency.
  *
  * @note
@@ -152,7 +167,7 @@
 uint32_t SystemHFClockGet(void)
 {
   uint32_t ret;
-  
+
   switch (CMU->STATUS & (CMU_STATUS_HFRCOSEL | CMU_STATUS_HFXOSEL |
                          CMU_STATUS_LFRCOSEL | CMU_STATUS_LFXOSEL))
   {
@@ -165,11 +180,11 @@
       ret = 0;
 #endif
       break;
-      
+
     case CMU_STATUS_LFRCOSEL:
       ret = EFM32_LFRCO_FREQ;
       break;
-      
+
     case CMU_STATUS_HFXOSEL:
 #if (EFM32_HFXO_FREQ > 0)
       ret = SystemHFXOClock;
@@ -179,7 +194,7 @@
       ret = 0;
 #endif
       break;
-      
+
     default: /* CMU_STATUS_HFRCOSEL */
       switch (CMU->HFRCOCTRL & _CMU_HFRCOCTRL_BAND_MASK)
       {

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/system_efm32gg.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/system_efm32gg.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /***************************************************************************//**
  * @file system_efm32gg.h
  * @brief CMSIS Cortex-M3 System Layer for EFM32GG devices.
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,8 +30,8 @@
  *
  *****************************************************************************/
 
-#ifndef __SYSTEM_EFM32GG_H
-#define __SYSTEM_EFM32GG_H
+#ifndef SYSTEM_EFM32GG_H
+#define SYSTEM_EFM32GG_H
 
 #ifdef __cplusplus
 extern "C" {
@@ -50,7 +50,6 @@
  ******************************************************************************/
 
 /* Interrupt routines - prototypes */
-#if defined(_EFM32_GIANT_FAMILY)
 void Reset_Handler(void);
 void NMI_Handler(void);
 void HardFault_Handler(void);
@@ -61,6 +60,7 @@
 void DebugMon_Handler(void);
 void PendSV_Handler(void);
 void SysTick_Handler(void);
+
 void DMA_IRQHandler(void);
 void GPIO_EVEN_IRQHandler(void);
 void TIMER0_IRQHandler(void);
@@ -100,9 +100,9 @@
 void AES_IRQHandler(void);
 void EBI_IRQHandler(void);
 void EMU_IRQHandler(void);
-#endif
 
 uint32_t SystemCoreClockGet(void);
+uint32_t SystemMaxCoreClockGet(void);
 
 /**************************************************************************//**
  * @brief
@@ -135,4 +135,4 @@
 #ifdef __cplusplus
 }
 #endif
-#endif /* __SYSTEM_EFM32GG_H */
+#endif /* SYSTEM_EFM32GG_H */

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/TOOLCHAIN_ARM_MICRO/efm32hg.sct	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/TOOLCHAIN_ARM_MICRO/efm32hg.sct	Fri Jan 15 07:45:16 2016 +0000
@@ -8,7 +8,7 @@
    *(InRoot$$Sections)
    .ANY (+RO)
   }
-  RW_IRAM1 0x20000098 0x00001F68  {  ; RW data
+  RW_IRAM1 0x20000094 0x00001F6C  {  ; RW data
    .ANY (+RW +ZI)
   }
 }

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/TOOLCHAIN_ARM_MICRO/startup_efm32hg.S	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/TOOLCHAIN_ARM_MICRO/startup_efm32hg.S	Fri Jan 15 07:45:16 2016 +0000
@@ -2,7 +2,7 @@
 ; * @file startup_efm32hg.s
 ; * @brief    CMSIS Core Device Startup File for
 ; *           Silicon Labs EFM32HG Device Series
-; * @version 3.20.12
+; * @version 4.2.1
 ; * @date     03. February 2012
 ; *
 ; * @note

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/TOOLCHAIN_GCC_ARM/efm32hg.ld	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/TOOLCHAIN_GCC_ARM/efm32hg.ld	Fri Jan 15 07:45:16 2016 +0000
@@ -6,8 +6,9 @@
 /*                                                                  */
 /* Silicon Laboratories, Inc. 2015                                  */
 /*                                                                  */
-/* Version 3.20.12 */
+/* Version 4.2.0 */
 /*                                                                  */
+
 MEMORY
 {
   FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 65536
@@ -16,17 +17,21 @@
 
 /* MBED: mbed needs to be able to dynamically set the interrupt vector table.
  * We make room for the table at the very beginning of RAM, i.e. at
- * 0x20000000. We need (16+21) * sizeof(uint32_t) = 144 bytes for EFM32HG */
+ * 0x20000000. We need (16+21) * sizeof(uint32_t) = 148 bytes for EFM32HG */
 __vector_size = 0x94;
 
 /* Linker script to place sections and symbol values. Should be used together
  * with other linker script that defines memory regions FLASH and RAM.
  * It references following symbols, which must be defined in code:
  *   Reset_Handler : Entry of reset handler
- * 
+ *
  * It defines following symbols, which code can use without definition:
  *   __exidx_start
  *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
  *   __etext
  *   __data_start__
  *   __preinit_array_start
@@ -44,6 +49,8 @@
  *   __StackLimit
  *   __StackTop
  *   __stack
+ *   __Vectors_End
+ *   __Vectors_Size
  */
 ENTRY(Reset_Handler)
 
@@ -51,7 +58,11 @@
 {
   .text :
   {
-    KEEP(*(.isr_vector))
+    KEEP(*(.vectors))
+    __Vectors_End = .;
+    __Vectors_Size = __Vectors_End - __Vectors;
+    __end__ = .;
+
     *(.text*)
 
     KEEP(*(.init))
@@ -76,7 +87,7 @@
     KEEP(*(.eh_frame*))
   } > FLASH
 
-  .ARM.extab : 
+  .ARM.extab :
   {
     *(.ARM.extab* .gnu.linkonce.armextab.*)
   } > FLASH
@@ -88,15 +99,49 @@
   } > FLASH
   __exidx_end = .;
 
+  /* To copy multiple ROM to RAM sections,
+   * uncomment .copy.table section and,
+   * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+  /*
+  .copy.table :
+  {
+    . = ALIGN(4);
+    __copy_table_start__ = .;
+    LONG (__etext)
+    LONG (__data_start__)
+    LONG (__data_end__ - __data_start__)
+    LONG (__etext2)
+    LONG (__data2_start__)
+    LONG (__data2_end__ - __data2_start__)
+    __copy_table_end__ = .;
+  } > FLASH
+  */
+
+  /* To clear multiple BSS sections,
+   * uncomment .zero.table section and,
+   * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+  /*
+  .zero.table :
+  {
+    . = ALIGN(4);
+    __zero_table_start__ = .;
+    LONG (__bss_start__)
+    LONG (__bss_end__ - __bss_start__)
+    LONG (__bss2_start__)
+    LONG (__bss2_end__ - __bss2_start__)
+    __zero_table_end__ = .;
+  } > FLASH
+  */
+
   __etext = .;
-  
+
   .data : AT (__etext)
   {
     __data_start__ = .;
     *("dma")
     PROVIDE( __start_vector_table__ = .);
-  	. += __vector_size;
-  	PROVIDE( __end_vector_table__ = .);
+    . += __vector_size;
+    PROVIDE( __end_vector_table__ = .);
     *(vtable)
     *(.data*)
     . = ALIGN (4);
@@ -122,6 +167,7 @@
     KEEP(*(.fini_array))
     PROVIDE_HIDDEN (__fini_array_end = .);
 
+    KEEP(*(.jcr*))
     . = ALIGN(4);
     /* All data end */
     __data_end__ = .;
@@ -130,27 +176,30 @@
 
   .bss :
   {
+    . = ALIGN(4);
     __bss_start__ = .;
     *(.bss*)
     *(COMMON)
+    . = ALIGN(4);
     __bss_end__ = .;
   } > RAM
 
-  .heap :
+  .heap (COPY):
   {
+    __HeapBase = .;
     __end__ = .;
     end = __end__;
     _end = __end__;
-    *(.heap*)
+    KEEP(*(.heap*))
     __HeapLimit = .;
   } > RAM
 
   /* .stack_dummy section doesn't contains any symbols. It is only
    * used for linker to calculate size of stack sections, and assign
    * values to stack symbols later */
-  .stack_dummy :
+  .stack_dummy (COPY):
   {
-    *(.stack)
+    KEEP(*(.stack*))
   } > RAM
 
   /* Set stack top to end of RAM, and stack limit move down by

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/TOOLCHAIN_GCC_ARM/startup_efm32hg.S	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/TOOLCHAIN_GCC_ARM/startup_efm32hg.S	Fri Jan 15 07:45:16 2016 +0000
@@ -1,194 +1,309 @@
 /* @file startup_efm32hg.S
  * @brief startup file for Silicon Labs EFM32HG devices.
  *        For use with GCC for ARM Embedded Processors
- * @version 3.20.12
- * Date: 08 Feb 2012
- *
- * Copyright (c) 2012, ARM Limited
- * All rights reserved.
+ * @version 4.2.1
+ * Date:    12 June 2014
  *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
-    * Redistributions of source code must retain the above copyright
-      notice, this list of conditions and the following disclaimer.
-    * Redistributions in binary form must reproduce the above copyright
-      notice, this list of conditions and the following disclaimer in the
-      documentation and/or other materials provided with the distribution.
-    * Neither the name of the ARM Limited nor the
-      names of its contributors may be used to endorse or promote products
-      derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
-    .syntax unified
-    .arch armv6-m
+/* Copyright (c) 2011 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+    .syntax     unified
+    .arch       armv6-m
+
+    .section    .stack
+    .align      3
+#ifdef __STACK_SIZE
+    .equ        Stack_Size, __STACK_SIZE
+#else
+    .equ        Stack_Size, 0x00000400
+#endif
+    .globl      __StackTop
+    .globl      __StackLimit
+__StackLimit:
+    .space      Stack_Size
+    .size       __StackLimit, . - __StackLimit
+__StackTop:
+    .size       __StackTop, . - __StackTop
+
+    .section    .heap
+    .align      3
+#ifdef __HEAP_SIZE
+    .equ        Heap_Size, __HEAP_SIZE
+#else
+    .equ        Heap_Size, 0x00000400
+#endif
+    .globl      __HeapBase
+    .globl      __HeapLimit
+__HeapBase:
+    .if Heap_Size
+    .space      Heap_Size
+    .endif
+    .size       __HeapBase, . - __HeapBase
+__HeapLimit:
+    .size       __HeapLimit, . - __HeapLimit
+
+    .section    .vectors
+    .align      2
+    .globl      __Vectors
+__Vectors:
+    .long       __StackTop            /* Top of Stack */
+    .long       Reset_Handler         /* Reset Handler */
+    .long       NMI_Handler           /* NMI Handler */
+    .long       HardFault_Handler     /* Hard Fault Handler */
+    .long       Default_Handler       /* Reserved */
+    .long       Default_Handler       /* Reserved */
+    .long       Default_Handler       /* Reserved */
+    .long       Default_Handler       /* Reserved */
+    .long       Default_Handler       /* Reserved */
+    .long       Default_Handler       /* Reserved */
+    .long       Default_Handler       /* Reserved */
+    .long       SVC_Handler           /* SVCall Handler */
+    .long       Default_Handler       /* Reserved */
+    .long       Default_Handler       /* Reserved */
+    .long       PendSV_Handler        /* PendSV Handler */
+    .long       SysTick_Handler       /* SysTick Handler */
+
+    /* External interrupts */
+
+    .long       DMA_IRQHandler    /* 0 - DMA */
+    .long       GPIO_EVEN_IRQHandler    /* 1 - GPIO_EVEN */
+    .long       TIMER0_IRQHandler    /* 2 - TIMER0 */
+    .long       ACMP0_IRQHandler    /* 3 - ACMP0 */
+    .long       ADC0_IRQHandler    /* 4 - ADC0 */
+    .long       I2C0_IRQHandler    /* 5 - I2C0 */
+    .long       GPIO_ODD_IRQHandler    /* 6 - GPIO_ODD */
+    .long       TIMER1_IRQHandler    /* 7 - TIMER1 */
+    .long       USART1_RX_IRQHandler    /* 8 - USART1_RX */
+    .long       USART1_TX_IRQHandler    /* 9 - USART1_TX */
+    .long       LEUART0_IRQHandler    /* 10 - LEUART0 */
+    .long       PCNT0_IRQHandler    /* 11 - PCNT0 */
+    .long       RTC_IRQHandler    /* 12 - RTC */
+    .long       CMU_IRQHandler    /* 13 - CMU */
+    .long       VCMP_IRQHandler    /* 14 - VCMP */
+    .long       MSC_IRQHandler    /* 15 - MSC */
+    .long       AES_IRQHandler    /* 16 - AES */
+    .long       USART0_RX_IRQHandler    /* 17 - USART0_RX */
+    .long       USART0_TX_IRQHandler    /* 18 - USART0_TX */
+    .long       USB_IRQHandler    /* 19 - USB */
+    .long       TIMER2_IRQHandler    /* 20 - TIMER2 */
 
 
-    .section .stack
-    .align 3
-#ifdef __STACK_SIZE
-    .equ    Stack_Size, __STACK_SIZE
-#else
-    .equ    Stack_Size, 0x400
-#endif
-    .globl    __StackTop
-    .globl    __StackLimit
-__StackLimit:
-    .space    Stack_Size
-    .size __StackLimit, . - __StackLimit
-__StackTop:
-    .size __StackTop, . - __StackTop
-
-    .section .heap
-    .align 3
-#ifdef __HEAP_SIZE
-    .equ    Heap_Size, __HEAP_SIZE
-#else
-    .equ    Heap_Size, 0x0
-#endif
-    .globl    __HeapBase
-    .globl    __HeapLimit
-__HeapBase:
-    .if    Heap_Size
-    .space    Heap_Size
-    .endif
-    .size __HeapBase, . - __HeapBase
-__HeapLimit:
-    .size __HeapLimit, . - __HeapLimit
-
-    .section .isr_vector
-    .align 8
-    .globl __isr_vector
-__isr_vector:
-    .long    __StackTop            /* Top of Stack */
-    .long    Reset_Handler         /* Reset Handler */
-    .long    NMI_Handler           /* NMI Handler */
-    .long    HardFault_Handler     /* Hard Fault Handler */
-    .long    Default_Handler       /* Reserved */
-    .long    Default_Handler       /* Reserved */
-    .long    Default_Handler       /* Reserved */
-    .long    Default_Handler       /* Reserved */
-    .long    Default_Handler       /* Reserved */
-    .long    Default_Handler       /* Reserved */
-    .long    Default_Handler       /* Reserved */
-    .long    SVC_Handler           /* SVCall Handler */
-    .long    Default_Handler       /* Reserved */
-    .long    Default_Handler       /* Reserved */
-    .long    PendSV_Handler        /* PendSV Handler */
-    .long    SysTick_Handler       /* SysTick Handler */
-
-    /* External interrupts */
-    .long    DMA_IRQHandler    /* 0 - DMA */
-    .long    GPIO_EVEN_IRQHandler    /* 1 - GPIO_EVEN */
-    .long    TIMER0_IRQHandler    /* 2 - TIMER0 */
-    .long    ACMP0_IRQHandler    /* 3 - ACMP0 */
-    .long    ADC0_IRQHandler    /* 4 - ADC0 */
-    .long    I2C0_IRQHandler    /* 5 - I2C0 */
-    .long    GPIO_ODD_IRQHandler    /* 6 - GPIO_ODD */
-    .long    TIMER1_IRQHandler    /* 7 - TIMER1 */
-    .long    USART1_RX_IRQHandler    /* 8 - USART1_RX */
-    .long    USART1_TX_IRQHandler    /* 9 - USART1_TX */
-    .long    LEUART0_IRQHandler    /* 10 - LEUART0 */
-    .long    PCNT0_IRQHandler    /* 11 - PCNT0 */
-    .long    RTC_IRQHandler    /* 12 - RTC */
-    .long    CMU_IRQHandler    /* 13 - CMU */
-    .long    VCMP_IRQHandler    /* 14 - VCMP */
-    .long    MSC_IRQHandler    /* 15 - MSC */
-    .long    AES_IRQHandler    /* 16 - AES */
-    .long    USART0_RX_IRQHandler    /* 17 - USART0_RX */
-    .long    USART0_TX_IRQHandler    /* 18 - USART0_TX */
-    .long    USB_IRQHandler    /* 19 - USB */
-    .long    TIMER2_IRQHandler    /* 20 - TIMER2 */
-
-
-    .size    __isr_vector, . - __isr_vector
+    .size       __Vectors, . - __Vectors
 
     .text
     .thumb
     .thumb_func
-    .align 2
-    .globl    Reset_Handler
-    .type    Reset_Handler, %function
+    .align      2
+    .globl      Reset_Handler
+    .type       Reset_Handler, %function
 Reset_Handler:
-/*     Loop to copy data from read only memory to RAM. The ranges
- *      of copy from/to are specified by following symbols evaluated in
- *      linker script.
- *      __etext: End of code section, i.e., begin of data sections to copy from.
- *      __data_start__/__data_end__: RAM address range that data should be
- *      copied to. Both must be aligned to 4 bytes boundary.  */
 #ifndef __NO_SYSTEM_INIT
-    ldr    r0, =SystemInit
-    blx    r0
+    ldr     r0, =SystemInit
+    blx     r0
 #endif
-    ldr    r1, =__etext
-    ldr    r2, =__data_start__
-    ldr    r3, =__data_end__
+
+/*  Firstly it copies data from read only memory to RAM. There are two schemes
+ *  to copy. One can copy more than one sections. Another can only copy
+ *  one section.  The former scheme needs more instructions and read-only
+ *  data to implement than the latter.
+ *  Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.  */
+
+#ifdef __STARTUP_COPY_MULTIPLE
+/*  Multiple sections scheme.
+ *
+ *  Between symbol address __copy_table_start__ and __copy_table_end__,
+ *  there are array of triplets, each of which specify:
+ *    offset 0: LMA of start of a section to copy from
+ *    offset 4: VMA of start of a section to copy to
+ *    offset 8: size of the section to copy. Must be multiply of 4
+ *
+ *  All addresses must be aligned to 4 bytes boundary.
+ */
+    ldr     r4, =__copy_table_start__
+    ldr     r5, =__copy_table_end__
+
+.L_loop0:
+    cmp     r4, r5
+    bge     .L_loop0_done
+    ldr     r1, [r4]
+    ldr     r2, [r4, #4]
+    ldr     r3, [r4, #8]
+
+.L_loop0_0:
+    subs    r3, #4
+    blt     .L_loop0_0_done
+    ldr     r0, [r1, r3]
+    str     r0, [r2, r3]
+    b       .L_loop0_0
+
+.L_loop0_0_done:
+    adds    r4, #12
+    b       .L_loop0
+
+.L_loop0_done:
+#else
+/*  Single section scheme.
+ *
+ *  The ranges of copy from/to are specified by following symbols
+ *    __etext: LMA of start of the section to copy from. Usually end of text
+ *    __data_start__: VMA of start of the section to copy to
+ *    __data_end__: VMA of end of the section to copy to
+ *
+ *  All addresses must be aligned to 4 bytes boundary.
+ */
+    ldr     r1, =__etext
+    ldr     r2, =__data_start__
+    ldr     r3, =__data_end__
+
+    subs    r3, r2
+    ble     .L_loop1_done
+
+.L_loop1:
+    subs    r3, #4
+    ldr     r0, [r1,r3]
+    str     r0, [r2,r3]
+    bgt     .L_loop1
+
+.L_loop1_done:
+#endif /*__STARTUP_COPY_MULTIPLE */
 
-    subs   r3, r2
-    ble    .flash_to_ram_loop_end
-.flash_to_ram_loop:
-    subs   r3, #4
-    ldr    r0, [r1, r3]
-    str    r0, [r2, r3]
-    bgt    .flash_to_ram_loop
-.flash_to_ram_loop_end:
+/*  This part of work usually is done in C library startup code. Otherwise,
+ *  define this macro to enable it in this startup.
+ *
+ *  There are two schemes too. One can clear multiple BSS sections. Another
+ *  can only clear one section. The former is more size expensive than the
+ *  latter.
+ *
+ *  Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ *  Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ */
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
+/*  Multiple sections scheme.
+ *
+ *  Between symbol address __copy_table_start__ and __copy_table_end__,
+ *  there are array of tuples specifying:
+ *    offset 0: Start of a BSS section
+ *    offset 4: Size of this BSS section. Must be multiply of 4
+ */
+    ldr     r3, =__zero_table_start__
+    ldr     r4, =__zero_table_end__
+
+.L_loop2:
+    cmp     r3, r4
+    bge     .L_loop2_done
+    ldr     r1, [r3]
+    ldr     r2, [r3, #4]
+    movs    r0, 0
+
+.L_loop2_0:
+    subs    r2, #4
+    blt     .L_loop2_0_done
+    str     r0, [r1, r2]
+    b       .L_loop2_0
+.L_loop2_0_done:
 
-    ldr    r0, =_start
-    bx     r0
+    adds    r3, #8
+    b       .L_loop2
+.L_loop2_done:
+#elif defined (__STARTUP_CLEAR_BSS)
+/*  Single BSS section scheme.
+ *
+ *  The BSS section is specified by following symbols
+ *    __bss_start__: start of the BSS section.
+ *    __bss_end__: end of the BSS section.
+ *
+ *  Both addresses must be aligned to 4 bytes boundary.
+ */
+    ldr     r1, =__bss_start__
+    ldr     r2, =__bss_end__
+
+    movs    r0, 0
+    subs    r2, r1
+    ble     .L_loop3_done
+
+.L_loop3:
+    subs    r2, #4
+    str     r0, [r1, r2]
+    bgt     .L_loop3
+.L_loop3_done:
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
+
+#ifndef __START
+#define __START _start
+#endif
+    bl      __START
+
     .pool
-    .size Reset_Handler, . - Reset_Handler
+    .size   Reset_Handler, . - Reset_Handler
+
+    .align  1
+    .thumb_func
+    .weak   Default_Handler
+    .type   Default_Handler, %function
+Default_Handler:
+    b       .
+    .size   Default_Handler, . - Default_Handler
 
 /*    Macro to define default handlers. Default handler
  *    will be weak symbol and just dead loops. They can be
  *    overwritten by other handlers */
-    .macro    def_irq_handler    handler_name
-    .align 1
-    .thumb_func
-    .weak    \handler_name
-    .type    \handler_name, %function
-\handler_name:
-    b    .
-    .size    \handler_name, . - \handler_name
+    .macro  def_irq_handler	handler_name
+    .weak   \handler_name
+    .set    \handler_name, Default_Handler
     .endm
 
-    def_irq_handler    Default_Handler
-
-    def_irq_handler    NMI_Handler
-    def_irq_handler    HardFault_Handler
-    def_irq_handler    SVC_Handler
-    def_irq_handler    PendSV_Handler
-    def_irq_handler    SysTick_Handler
+    def_irq_handler     NMI_Handler
+    def_irq_handler     HardFault_Handler
+    def_irq_handler     SVC_Handler
+    def_irq_handler     PendSV_Handler
+    def_irq_handler     SysTick_Handler
 
-    def_irq_handler    DMA_IRQHandler
-    def_irq_handler    GPIO_EVEN_IRQHandler
-    def_irq_handler    TIMER0_IRQHandler
-    def_irq_handler    ACMP0_IRQHandler
-    def_irq_handler    ADC0_IRQHandler
-    def_irq_handler    I2C0_IRQHandler
-    def_irq_handler    GPIO_ODD_IRQHandler
-    def_irq_handler    TIMER1_IRQHandler
-    def_irq_handler    USART1_RX_IRQHandler
-    def_irq_handler    USART1_TX_IRQHandler
-    def_irq_handler    LEUART0_IRQHandler
-    def_irq_handler    PCNT0_IRQHandler
-    def_irq_handler    RTC_IRQHandler
-    def_irq_handler    CMU_IRQHandler
-    def_irq_handler    VCMP_IRQHandler
-    def_irq_handler    MSC_IRQHandler
-    def_irq_handler    AES_IRQHandler
-    def_irq_handler    USART0_RX_IRQHandler
-    def_irq_handler    USART0_TX_IRQHandler
-    def_irq_handler    USB_IRQHandler
-    def_irq_handler    TIMER2_IRQHandler
+    def_irq_handler     DMA_IRQHandler
+    def_irq_handler     GPIO_EVEN_IRQHandler
+    def_irq_handler     TIMER0_IRQHandler
+    def_irq_handler     ACMP0_IRQHandler
+    def_irq_handler     ADC0_IRQHandler
+    def_irq_handler     I2C0_IRQHandler
+    def_irq_handler     GPIO_ODD_IRQHandler
+    def_irq_handler     TIMER1_IRQHandler
+    def_irq_handler     USART1_RX_IRQHandler
+    def_irq_handler     USART1_TX_IRQHandler
+    def_irq_handler     LEUART0_IRQHandler
+    def_irq_handler     PCNT0_IRQHandler
+    def_irq_handler     RTC_IRQHandler
+    def_irq_handler     CMU_IRQHandler
+    def_irq_handler     VCMP_IRQHandler
+    def_irq_handler     MSC_IRQHandler
+    def_irq_handler     AES_IRQHandler
+    def_irq_handler     USART0_RX_IRQHandler
+    def_irq_handler     USART0_TX_IRQHandler
+    def_irq_handler     USB_IRQHandler
+    def_irq_handler     TIMER2_IRQHandler
 
 
     .end

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg322f64.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg322f64.h	Fri Jan 15 07:45:16 2016 +0000
@@ -2,10 +2,10 @@
  * @file efm32hg322f64.h
  * @brief CMSIS Cortex-M Peripheral Access Layer Header File
  *        for EFM32HG322F64
- * @version 3.20.12
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -31,8 +31,8 @@
  *
  *****************************************************************************/
 
-#ifndef __SILICON_LABS_EFM32HG322F64_H__
-#define __SILICON_LABS_EFM32HG322F64_H__
+#ifndef EFM32HG322F64_H
+#define EFM32HG322F64_H
 
 #ifdef __cplusplus
 extern "C" {
@@ -224,6 +224,9 @@
 
 /** @} End of group EFM32HG322F64_Part */
 
+#ifndef ARM_MATH_CM0PLUS
+#define ARM_MATH_CM0PLUS
+#endif
 #include "arm_math.h"       /* To get __CLZ definitions etc. */
 #include "core_cm0plus.h"   /* Cortex-M0+ processor and core peripherals */
 #include "system_efm32hg.h" /* System Header */
@@ -396,4 +399,4 @@
 #ifdef __cplusplus
 }
 #endif
-#endif /* __SILICON_LABS_EFM32HG322F64_H__ */
+#endif /* EFM32HG322F64_H */

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_acmp.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_acmp.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32hg_acmp.h
  * @brief EFM32HG_ACMP register and bit field definitions
- * @version 3.20.12
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32HG_ACMP
  * @{
  * @brief EFM32HG_ACMP Register Declaration
@@ -325,5 +329,5 @@
 #define ACMP_ROUTE_LOCATION_LOC3           (_ACMP_ROUTE_LOCATION_LOC3 << 8)    /**< Shifted mode LOC3 for ACMP_ROUTE */
 
 /** @} End of group EFM32HG_ACMP */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_adc.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_adc.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32hg_adc.h
  * @brief EFM32HG_ADC register and bit field definitions
- * @version 3.20.12
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32HG_ADC
  * @{
  * @brief EFM32HG_ADC Register Declaration
@@ -651,5 +655,5 @@
 #define ADC_BIASPROG_COMPBIAS_DEFAULT           (_ADC_BIASPROG_COMPBIAS_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_BIASPROG */
 
 /** @} End of group EFM32HG_ADC */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_aes.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_aes.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32hg_aes.h
  * @brief EFM32HG_AES register and bit field definitions
- * @version 3.20.12
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32HG_AES
  * @{
  * @brief EFM32HG_AES Register Declaration
@@ -189,5 +193,5 @@
 #define AES_KEYLD_KEYLD_DEFAULT         (_AES_KEYLD_KEYLD_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYLD */
 
 /** @} End of group EFM32HG_AES */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_af_pins.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_af_pins.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32hg_af_pins.h
  * @brief EFM32HG_AF_PINS register and bit field definitions
- * @version 3.20.12
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32HG_AF_Pins
  * @{
  *****************************************************************************/
@@ -79,5 +83,5 @@
 #define AF_DBG_SWCLK_PIN(i)       ((i) == 0 ? 0 :  -1)
 
 /** @} End of group EFM32HG_AF_Pins */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_af_ports.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_af_ports.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32hg_af_ports.h
  * @brief EFM32HG_AF_PORTS register and bit field definitions
- * @version 3.20.12
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32HG_AF_Ports
  * @{
  *****************************************************************************/
@@ -79,5 +83,5 @@
 #define AF_DBG_SWCLK_PORT(i)       ((i) == 0 ? 5 :  -1)
 
 /** @} End of group EFM32HG_AF_Ports */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_calibrate.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_calibrate.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32hg_calibrate.h
  * @brief EFM32HG_CALIBRATE register and bit field definitions
- * @version 3.20.12
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32HG_CALIBRATE
  * @{
  *****************************************************************************/
@@ -41,3 +45,6 @@
   __I uint32_t VALUE;   /**< Default value for calibration register */
 } CALIBRATE_TypeDef;    /** @} */
 
+/** @} End of group Parts */
+
+

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_cmu.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_cmu.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32hg_cmu.h
  * @brief EFM32HG_CMU register and bit field definitions
- * @version 3.20.12
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32HG_CMU
  * @{
  * @brief EFM32HG_CMU Register Declaration
@@ -84,7 +88,7 @@
  *****************************************************************************/
 
 /* Bit fields for CMU CTRL */
-#define _CMU_CTRL_RESETVALUE                        0x000C062CUL                             /**< Default value for CMU_CTRL */
+#define _CMU_CTRL_RESETVALUE                        0x000C262CUL                             /**< Default value for CMU_CTRL */
 #define _CMU_CTRL_MASK                              0x07FFFEEFUL                             /**< Mask for CMU_CTRL */
 #define _CMU_CTRL_HFXOMODE_SHIFT                    0                                        /**< Shift value for CMU_HFXOMODE */
 #define _CMU_CTRL_HFXOMODE_MASK                     0x3UL                                    /**< Bit mask for CMU_HFXOMODE */
@@ -1198,5 +1202,5 @@
 #define CMU_USHFRCOCONF_USHFRCODIV2DIS_DEFAULT      (_CMU_USHFRCOCONF_USHFRCODIV2DIS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_USHFRCOCONF */
 
 /** @} End of group EFM32HG_CMU */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_devinfo.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_devinfo.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32hg_devinfo.h
  * @brief EFM32HG_DEVINFO register and bit field definitions
- * @version 3.20.12
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32HG_DEVINFO
  * @{
  *****************************************************************************/
@@ -152,9 +156,10 @@
 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32HG             77           /**< Happy Gecko Device Family */
 #define _DEVINFO_PART_DEVICE_FAMILY_EZR32WG             120          /**< EZR Wonder Gecko Device Family */
 #define _DEVINFO_PART_DEVICE_FAMILY_EZR32LG             121          /**< EZR Leopard Gecko Device Family */
+#define _DEVINFO_PART_DEVICE_FAMILY_EZR32HG             122          /**< EZR Happy Gecko Device Family */
 #define _DEVINFO_PART_DEVICE_NUMBER_MASK                0x0000FFFFUL /**< Device number */
 #define _DEVINFO_PART_DEVICE_NUMBER_SHIFT               0            /**< Bit position for device number */
 
 /** @} End of group EFM32HG_DEVINFO */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_dma.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_dma.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32hg_dma.h
  * @brief EFM32HG_DMA register and bit field definitions
- * @version 3.20.12
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32HG_DMA
  * @{
  * @brief EFM32HG_DMA Register Declaration
@@ -884,5 +888,5 @@
 #define DMA_CH_CTRL_SOURCESEL_AES                       (_DMA_CH_CTRL_SOURCESEL_AES << 16)            /**< Shifted mode AES for DMA_CH_CTRL */
 
 /** @} End of group EFM32HG_DMA */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_dma_ch.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_dma_ch.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32hg_dma_ch.h
  * @brief EFM32HG_DMA_CH register and bit field definitions
- * @version 3.20.12
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @brief DMA_CH EFM32HG DMA CH
  *****************************************************************************/
 typedef struct
@@ -37,3 +41,6 @@
   __IO uint32_t CTRL; /**< Channel Control Register  */
 } DMA_CH_TypeDef;
 
+/** @} End of group Parts */
+
+

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_dma_descriptor.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_dma_descriptor.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32hg_dma_descriptor.h
  * @brief EFM32HG_DMA_DESCRIPTOR register and bit field definitions
- * @version 3.20.12
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32HG_DMA_DESCRIPTOR
  * @{
  *****************************************************************************/
@@ -43,3 +47,6 @@
   __IO uint32_t    USER;       /**< DMA padding register, available for user */
 } DMA_DESCRIPTOR_TypeDef;      /** @} */
 
+/** @} End of group Parts */
+
+

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_dmactrl.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_dmactrl.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32hg_dmactrl.h
  * @brief EFM32HG_DMACTRL register and bit field definitions
- * @version 3.20.12
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -29,6 +29,10 @@
  * any third party, arising from your use of this Software.
  *
  *****************************************************************************/
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
 
 /**************************************************************************//**
  * @defgroup EFM32HG_DMACTRL_BitFields
@@ -132,5 +136,5 @@
 #define DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER_ALT     0x000000007UL /**< Peripheral scatter gather cycle type using alternate structure */
 
 /** @} End of group EFM32HG_DMA */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_dmareq.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_dmareq.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32hg_dmareq.h
  * @brief EFM32HG_DMAREQ register and bit field definitions
- * @version 3.20.12
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -29,6 +29,10 @@
  * any third party, arising from your use of this Software.
  *
  *****************************************************************************/
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
 
 /**************************************************************************//**
  * @defgroup EFM32HG_DMAREQ_BitFields
@@ -68,5 +72,5 @@
 #define DMAREQ_AES_KEYWR              ((49 << 16) + 3) /**< DMA channel select for AES_KEYWR */
 
 /** @} End of group EFM32HG_DMAREQ */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_emu.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_emu.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32hg_emu.h
  * @brief EFM32HG_EMU register and bit field definitions
- * @version 3.20.12
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32HG_EMU
  * @{
  * @brief EFM32HG_EMU Register Declaration
@@ -98,5 +102,5 @@
 #define EMU_AUXCTRL_HRCCLR_DEFAULT     (_EMU_AUXCTRL_HRCCLR_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_AUXCTRL */
 
 /** @} End of group EFM32HG_EMU */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_gpio.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_gpio.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32hg_gpio.h
  * @brief EFM32HG_GPIO register and bit field definitions
- * @version 3.20.12
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32HG_GPIO
  * @{
  * @brief EFM32HG_GPIO Register Declaration
@@ -1146,5 +1150,5 @@
 #define GPIO_EM4WUCAUSE_EM4WUCAUSE_C4                     (_GPIO_EM4WUCAUSE_EM4WUCAUSE_C4 << 0)      /**< Shifted mode C4 for GPIO_EM4WUCAUSE */
 
 /** @} End of group EFM32HG_GPIO */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_gpio_p.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_gpio_p.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32hg_gpio_p.h
  * @brief EFM32HG_GPIO_P register and bit field definitions
- * @version 3.20.12
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @brief GPIO_P EFM32HG GPIO P
  *****************************************************************************/
 typedef struct
@@ -45,3 +49,6 @@
   __IO uint32_t PINLOCKN; /**< Port Unlocked Pins Register  */
 } GPIO_P_TypeDef;
 
+/** @} End of group Parts */
+
+

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_i2c.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_i2c.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32hg_i2c.h
  * @brief EFM32HG_I2C register and bit field definitions
- * @version 3.20.12
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32HG_I2C
  * @{
  * @brief EFM32HG_I2C Register Declaration
@@ -697,5 +701,5 @@
 #define I2C_ROUTE_LOCATION_LOC6           (_I2C_ROUTE_LOCATION_LOC6 << 8)    /**< Shifted mode LOC6 for I2C_ROUTE */
 
 /** @} End of group EFM32HG_I2C */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_idac.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_idac.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32hg_idac.h
  * @brief EFM32HG_IDAC register and bit field definitions
- * @version 3.20.12
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32HG_IDAC
  * @{
  * @brief EFM32HG_IDAC Register Declaration
@@ -144,5 +148,5 @@
 #define IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_DEFAULT     (_IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_DUTYCONFIG */
 
 /** @} End of group EFM32HG_IDAC */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_leuart.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_leuart.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32hg_leuart.h
  * @brief EFM32HG_LEUART register and bit field definitions
- * @version 3.20.12
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32HG_LEUART
  * @{
  * @brief EFM32HG_LEUART Register Declaration
@@ -685,5 +689,5 @@
 #define LEUART_INPUT_RXPRS_DEFAULT               (_LEUART_INPUT_RXPRS_DEFAULT << 4)    /**< Shifted mode DEFAULT for LEUART_INPUT */
 
 /** @} End of group EFM32HG_LEUART */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_msc.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_msc.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32hg_msc.h
  * @brief EFM32HG_MSC register and bit field definitions
- * @version 3.20.12
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32HG_MSC
  * @{
  * @brief EFM32HG_MSC Register Declaration
@@ -408,5 +412,5 @@
 #define MSC_IRQLATENCY_IRQLATENCY_DEFAULT       (_MSC_IRQLATENCY_IRQLATENCY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IRQLATENCY */
 
 /** @} End of group EFM32HG_MSC */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_mtb.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_mtb.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32hg_mtb.h
  * @brief EFM32HG_MTB register and bit field definitions
- * @version 3.20.12
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32HG_MTB
  * @{
  * @brief EFM32HG_MTB Register Declaration
@@ -115,5 +119,5 @@
 #define MTB_BASE_BASE_DEFAULT            (_MTB_BASE_BASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MTB_BASE */
 
 /** @} End of group EFM32HG_MTB */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_pcnt.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_pcnt.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32hg_pcnt.h
  * @brief EFM32HG_PCNT register and bit field definitions
- * @version 3.20.12
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32HG_PCNT
  * @{
  * @brief EFM32HG_PCNT Register Declaration
@@ -478,5 +482,5 @@
 #define PCNT_INPUT_S1PRSEN_DEFAULT        (_PCNT_INPUT_S1PRSEN_DEFAULT << 10) /**< Shifted mode DEFAULT for PCNT_INPUT */
 
 /** @} End of group EFM32HG_PCNT */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_prs.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_prs.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32hg_prs.h
  * @brief EFM32HG_PRS register and bit field definitions
- * @version 3.20.12
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32HG_PRS
  * @{
  * @brief EFM32HG_PRS Register Declaration
@@ -350,5 +354,5 @@
 #define PRS_TRACECTRL_TSTOP_PRSCH5           (_PRS_TRACECTRL_TSTOP_PRSCH5 << 9)     /**< Shifted mode PRSCH5 for PRS_TRACECTRL */
 
 /** @} End of group EFM32HG_PRS */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_prs_ch.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_prs_ch.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32hg_prs_ch.h
  * @brief EFM32HG_PRS_CH register and bit field definitions
- * @version 3.20.12
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @brief PRS_CH EFM32HG PRS CH
  *****************************************************************************/
 typedef struct
@@ -37,3 +41,6 @@
   __IO uint32_t CTRL; /**< Channel Control Register  */
 } PRS_CH_TypeDef;
 
+/** @} End of group Parts */
+
+

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_prs_signals.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_prs_signals.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32hg_prs_signals.h
  * @brief EFM32HG_PRS_SIGNALS register and bit field definitions
- * @version 3.20.12
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @addtogroup EFM32HG_PRS_Signals
  * @{
  * @brief PRS Signal names
@@ -83,5 +87,5 @@
 #define PRS_PCNT0_TCC         ((54 << 16) + 0) /**< PRS Triggered compare match */
 
 /** @} End of group EFM32HG_PRS */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_rmu.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_rmu.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32hg_rmu.h
  * @brief EFM32HG_RMU register and bit field definitions
- * @version 3.20.12
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32HG_RMU
  * @{
  * @brief EFM32HG_RMU Register Declaration
@@ -124,5 +128,5 @@
 #define RMU_CMD_RCCLR_DEFAULT                (_RMU_CMD_RCCLR_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_CMD */
 
 /** @} End of group EFM32HG_RMU */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_romtable.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_romtable.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32hg_romtable.h
  * @brief EFM32HG_ROMTABLE register and bit field definitions
- * @version 3.20.12
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32HG_ROMTABLE
  * @{
  * @brief Chip Information, Revision numbers
@@ -64,5 +68,5 @@
 #define _ROMTABLE_PID3_REVMINORLSB_SHIFT    4            /**< Least Significant Bits [3:0] of CHIP MINOR revision, shift */
 
 /** @} End of group EFM32HG_ROMTABLE */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_rtc.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_rtc.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32hg_rtc.h
  * @brief EFM32HG_RTC register and bit field definitions
- * @version 3.20.12
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32HG_RTC
  * @{
  * @brief EFM32HG_RTC Register Declaration
@@ -210,5 +214,5 @@
 #define RTC_SYNCBUSY_COMP1_DEFAULT       (_RTC_SYNCBUSY_COMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_SYNCBUSY */
 
 /** @} End of group EFM32HG_RTC */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_timer.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_timer.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32hg_timer.h
  * @brief EFM32HG_TIMER register and bit field definitions
- * @version 3.20.12
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32HG_TIMER
  * @{
  * @brief EFM32HG_TIMER Register Declaration
@@ -947,5 +951,5 @@
 #define TIMER_DTLOCK_LOCKKEY_UNLOCK                (_TIMER_DTLOCK_LOCKKEY_UNLOCK << 0)   /**< Shifted mode UNLOCK for TIMER_DTLOCK */
 
 /** @} End of group EFM32HG_TIMER */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_timer_cc.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_timer_cc.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32hg_timer_cc.h
  * @brief EFM32HG_TIMER_CC register and bit field definitions
- * @version 3.20.12
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @brief TIMER_CC EFM32HG TIMER CC
  *****************************************************************************/
 typedef struct
@@ -40,3 +44,6 @@
   __IO uint32_t CCVB; /**< CC Channel Buffer Register  */
 } TIMER_CC_TypeDef;
 
+/** @} End of group Parts */
+
+

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_usart.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_usart.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32hg_usart.h
  * @brief EFM32HG_USART register and bit field definitions
- * @version 3.20.12
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32HG_USART
  * @{
  * @brief EFM32HG_USART Register Declaration
@@ -1141,5 +1145,5 @@
 #define USART_I2SCTRL_FORMAT_W8D8             (_USART_I2SCTRL_FORMAT_W8D8 << 8)      /**< Shifted mode W8D8 for USART_I2SCTRL */
 
 /** @} End of group EFM32HG_USART */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_usb.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_usb.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32hg_usb.h
  * @brief EFM32HG_USB register and bit field definitions
- * @version 3.20.12
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32HG_USB
  * @{
  * @brief EFM32HG_USB Register Declaration
@@ -802,7 +806,7 @@
 #define USB_DCFG_RESVALID_DEFAULT                  (_USB_DCFG_RESVALID_DEFAULT << 26)      /**< Shifted mode DEFAULT for USB_DCFG */
 
 /* Bit fields for USB DCTL */
-#define _USB_DCTL_RESETVALUE                       0x00000000UL                           /**< Default value for USB_DCTL */
+#define _USB_DCTL_RESETVALUE                       0x00000002UL                           /**< Default value for USB_DCTL */
 #define _USB_DCTL_MASK                             0x00018FFFUL                           /**< Mask for USB_DCTL */
 #define USB_DCTL_RMTWKUPSIG                        (0x1UL << 0)                           /**< Remote Wakeup Signaling */
 #define _USB_DCTL_RMTWKUPSIG_SHIFT                 0                                      /**< Shift value for USB_RMTWKUPSIG */
@@ -1789,5 +1793,5 @@
 #define USB_FIFORAM_FIFORAM_DEFAULT                (_USB_FIFORAM_FIFORAM_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_FIFORAM */
 
 /** @} End of group EFM32HG_USB */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_usb_diep.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_usb_diep.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32hg_usb_diep.h
  * @brief EFM32HG_USB_DIEP register and bit field definitions
- * @version 3.20.12
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @brief USB_DIEP EFM32HG USB DIEP
  *****************************************************************************/
 typedef struct
@@ -44,3 +48,6 @@
   uint32_t      RESERVED2[1]; /**< Reserved future */
 } USB_DIEP_TypeDef;
 
+/** @} End of group Parts */
+
+

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_usb_doep.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_usb_doep.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32hg_usb_doep.h
  * @brief EFM32HG_USB_DOEP register and bit field definitions
- * @version 3.20.12
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @brief USB_DOEP EFM32HG USB DOEP
  *****************************************************************************/
 typedef struct
@@ -43,3 +47,6 @@
   uint32_t      RESERVED2[2]; /**< Reserved future */
 } USB_DOEP_TypeDef;
 
+/** @} End of group Parts */
+
+

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_vcmp.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_vcmp.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32hg_vcmp.h
  * @brief EFM32HG_VCMP register and bit field definitions
- * @version 3.20.12
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32HG_VCMP
  * @{
  * @brief EFM32HG_VCMP Register Declaration
@@ -192,5 +196,5 @@
 #define VCMP_IFC_WARMUP_DEFAULT             (_VCMP_IFC_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for VCMP_IFC */
 
 /** @} End of group EFM32HG_VCMP */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_wdog.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_wdog.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32hg_wdog.h
  * @brief EFM32HG_WDOG register and bit field definitions
- * @version 3.20.12
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32HG_WDOG
  * @{
  * @brief EFM32HG_WDOG Register Declaration
@@ -128,5 +132,5 @@
 #define WDOG_SYNCBUSY_CMD_DEFAULT        (_WDOG_SYNCBUSY_CMD_DEFAULT << 1)  /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */
 
 /** @} End of group EFM32HG_WDOG */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/em_device.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/em_device.h	Fri Jan 15 07:45:16 2016 +0000
@@ -9,11 +9,13 @@
  * @verbatim
  * Example: Add "-DEFM32G890F128" to your build options, to define part
  *          Add "#include "em_device.h" to your source files
+ *
+ *
  * @endverbatim
- * @version 3.20.12
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -39,9 +41,8 @@
  *
  *****************************************************************************/
 
-#ifndef __SILICON_LABS_EM_DEVICE_H__
-#define __SILICON_LABS_EM_DEVICE_H__
-
+#ifndef EM_DEVICE_H
+#define EM_DEVICE_H
 
 #if defined(EFM32HG108F32)
 #include "efm32hg108f32.h"
@@ -103,9 +104,7 @@
 #elif defined(EFM32HG350F64)
 #include "efm32hg350f64.h"
 
-
 #else
 #error "em_device.h: PART NUMBER undefined"
 #endif
-
-#endif /* __SILICON_LABS_EM_DEVICE_H__ */
+#endif /* EM_DEVICE_H */

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/system_efm32hg.c	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/system_efm32hg.c	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /***************************************************************************//**
  * @file system_efm32hg.c
  * @brief CMSIS Cortex-M0+ System Layer for EFM32HG devices.
- * @version 3.20.12
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -54,9 +54,11 @@
 /* SW footprint. */
 
 #ifndef EFM32_HFXO_FREQ
-#define EFM32_HFXO_FREQ         (24000000UL)
-#define EFM32_HFRCO_MAX_FREQ    (21000000UL)
+#define EFM32_HFXO_FREQ (24000000UL)
 #endif
+
+#define EFM32_HFRCO_MAX_FREQ (21000000UL)
+
 /* Do not define variable if HF crystal oscillator not present */
 #if (EFM32_HFXO_FREQ > 0)
 /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
@@ -68,6 +70,7 @@
 #ifndef EFM32_LFXO_FREQ
 #define EFM32_LFXO_FREQ (EFM32_LFRCO_FREQ)
 #endif
+
 /* Do not define variable if LF crystal oscillator not present */
 #if (EFM32_LFXO_FREQ > 0)
 /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
@@ -156,9 +159,12 @@
 {
   uint32_t ret;
 
-  switch (CMU->STATUS & (CMU_STATUS_HFRCOSEL | CMU_STATUS_HFXOSEL |
-                         CMU_STATUS_LFRCOSEL | CMU_STATUS_LFXOSEL |
-                         CMU_STATUS_USHFRCODIV2SEL))
+  switch (CMU->STATUS & (CMU_STATUS_HFRCOSEL | CMU_STATUS_HFXOSEL
+                         | CMU_STATUS_LFRCOSEL | CMU_STATUS_LFXOSEL
+#if defined(CMU_STATUS_USHFRCODIV2SEL)
+                         | CMU_STATUS_USHFRCODIV2SEL
+#endif
+                        ))
   {
     case CMU_STATUS_LFXOSEL:
 #if (EFM32_LFXO_FREQ > 0)
@@ -184,9 +190,11 @@
 #endif
       break;
 
+#if defined(CMU_STATUS_USHFRCODIV2SEL)
     case CMU_STATUS_USHFRCODIV2SEL:
       ret = 24000000;
       break;
+#endif
 
     default: /* CMU_STATUS_HFRCOSEL */
       switch (CMU->HFRCOCTRL & _CMU_HFRCOCTRL_BAND_MASK)

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/system_efm32hg.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/system_efm32hg.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file system_efm32hg.h
  * @brief CMSIS Cortex-M System Layer for EFM32 devices.
- * @version 3.20.12
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,8 +30,8 @@
  *
  *****************************************************************************/
 
-#ifndef __SILICON_LABS_SYSTEM_EFM32HG_H__
-#define __SILICON_LABS_SYSTEM_EFM32HG_H__
+#ifndef SYSTEM_EFM32HG_H
+#define SYSTEM_EFM32HG_H
 
 #ifdef __cplusplus
 extern "C" {
@@ -113,4 +113,4 @@
 #ifdef __cplusplus
 }
 #endif
-#endif /* __SILICON_LABS_SYSTEM_EFM32HG_H__ */
+#endif /* SYSTEM_EFM32HG_H */

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/TOOLCHAIN_ARM_MICRO/startup_efm32lg.S	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/TOOLCHAIN_ARM_MICRO/startup_efm32lg.S	Fri Jan 15 07:45:16 2016 +0000
@@ -2,7 +2,7 @@
 ; * @file startup_efm32lg.s
 ; * @brief    CMSIS Core Device Startup File for
 ; *           Silicon Labs EFM32LG Device Series
-; * @version 3.20.6
+; * @version 4.2.1
 ; * @date     03. February 2012
 ; *
 ; * @note
@@ -117,6 +117,7 @@
                 DCD     AES_IRQHandler        ; 36: AES Interrupt
                 DCD     EBI_IRQHandler        ; 37: EBI Interrupt
                 DCD     EMU_IRQHandler        ; 38: EMU Interrupt
+                DCD     0                         ; 39: Reserved
 
 __Vectors_End
 __Vectors_Size  EQU     __Vectors_End - __Vectors
@@ -262,10 +263,7 @@
 AES_IRQHandler
 EBI_IRQHandler
 EMU_IRQHandler
-
-
                 B       .
-
                 ENDP
 
                 ALIGN

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/TOOLCHAIN_ARM_STD/startup_efm32lg.S	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/TOOLCHAIN_ARM_STD/startup_efm32lg.S	Fri Jan 15 07:45:16 2016 +0000
@@ -2,7 +2,7 @@
 ; * @file startup_efm32lg.s
 ; * @brief    CMSIS Core Device Startup File for
 ; *           Silicon Labs EFM32LG Device Series
-; * @version 3.20.6
+; * @version 4.2.1
 ; * @date     03. February 2012
 ; *
 ; * @note
@@ -117,6 +117,7 @@
                 DCD     AES_IRQHandler        ; 36: AES Interrupt
                 DCD     EBI_IRQHandler        ; 37: EBI Interrupt
                 DCD     EMU_IRQHandler        ; 38: EMU Interrupt
+                DCD     0                         ; 39: Reserved
 
 __Vectors_End
 __Vectors_Size  EQU     __Vectors_End - __Vectors
@@ -262,24 +263,13 @@
 AES_IRQHandler
 EBI_IRQHandler
 EMU_IRQHandler
-
-
                 B       .
-
                 ENDP
 
                 ALIGN
 
 ; User Initial Stack & Heap
 
-                IF      :DEF:__MICROLIB
-
-                EXPORT  __initial_sp
-                EXPORT  __heap_base
-                EXPORT  __heap_limit
-
-                ELSE
-
                 IMPORT  __use_two_region_memory
                 EXPORT  __user_initial_stackheap
 
@@ -293,6 +283,4 @@
 
                 ALIGN
 
-                ENDIF
-
                 END

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/TOOLCHAIN_GCC_ARM/efm32lg.ld	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/TOOLCHAIN_GCC_ARM/efm32lg.ld	Fri Jan 15 07:45:16 2016 +0000
@@ -4,7 +4,11 @@
 /* CMSIS END USER LICENSE AGREEMENT.pdf, governing the use of       */
 /* Example Code.                                                    */
 /*                                                                  */
-/* Silicon Laboratories, Inc. 2014                                  */
+/* Silicon Laboratories, Inc. 2015                                  */
+/*                                                                  */
+/* Version 4.2.0 */
+/*                                                                  */
+
 MEMORY
 {
   FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 262144
@@ -12,17 +16,21 @@
 }
 /* MBED: mbed needs to be able to dynamically set the interrupt vector table.
  * We make room for the table at the very beginning of RAM, i.e. at
- * 0x20000000. We need (16+39) * sizeof(uint32_t) = 220 bytes for EFM32LG */
+ * 0x20000000. We need (16+40) * sizeof(uint32_t) = 224 bytes for EFM32LG */
 __vector_size = 0xE0;
 
 /* Linker script to place sections and symbol values. Should be used together
  * with other linker script that defines memory regions FLASH and RAM.
  * It references following symbols, which must be defined in code:
  *   Reset_Handler : Entry of reset handler
- * 
+ *
  * It defines following symbols, which code can use without definition:
  *   __exidx_start
  *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
  *   __etext
  *   __data_start__
  *   __preinit_array_start
@@ -40,6 +48,8 @@
  *   __StackLimit
  *   __StackTop
  *   __stack
+ *   __Vectors_End
+ *   __Vectors_Size
  */
 ENTRY(Reset_Handler)
 
@@ -47,7 +57,11 @@
 {
   .text :
   {
-    KEEP(*(.isr_vector))
+    KEEP(*(.vectors))
+    __Vectors_End = .;
+    __Vectors_Size = __Vectors_End - __Vectors;
+    __end__ = .;
+
     *(.text*)
 
     KEEP(*(.init))
@@ -72,7 +86,7 @@
     KEEP(*(.eh_frame*))
   } > FLASH
 
-  .ARM.extab : 
+  .ARM.extab :
   {
     *(.ARM.extab* .gnu.linkonce.armextab.*)
   } > FLASH
@@ -84,15 +98,49 @@
   } > FLASH
   __exidx_end = .;
 
+  /* To copy multiple ROM to RAM sections,
+   * uncomment .copy.table section and,
+   * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+  /*
+  .copy.table :
+  {
+    . = ALIGN(4);
+    __copy_table_start__ = .;
+    LONG (__etext)
+    LONG (__data_start__)
+    LONG (__data_end__ - __data_start__)
+    LONG (__etext2)
+    LONG (__data2_start__)
+    LONG (__data2_end__ - __data2_start__)
+    __copy_table_end__ = .;
+  } > FLASH
+  */
+
+  /* To clear multiple BSS sections,
+   * uncomment .zero.table section and,
+   * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+  /*
+  .zero.table :
+  {
+    . = ALIGN(4);
+    __zero_table_start__ = .;
+    LONG (__bss_start__)
+    LONG (__bss_end__ - __bss_start__)
+    LONG (__bss2_start__)
+    LONG (__bss2_end__ - __bss2_start__)
+    __zero_table_end__ = .;
+  } > FLASH
+  */
+
   __etext = .;
-  
+
   .data : AT (__etext)
   {
     __data_start__ = .;
     *("dma")
     PROVIDE( __start_vector_table__ = .);
-  	. += __vector_size;
-  	PROVIDE( __end_vector_table__ = .);
+    . += __vector_size;
+    PROVIDE( __end_vector_table__ = .);
     *(vtable)
     *(.data*)
     . = ALIGN (4);
@@ -118,6 +166,7 @@
     KEEP(*(.fini_array))
     PROVIDE_HIDDEN (__fini_array_end = .);
 
+    KEEP(*(.jcr*))
     . = ALIGN(4);
     /* All data end */
     __data_end__ = .;
@@ -126,27 +175,30 @@
 
   .bss :
   {
+    . = ALIGN(4);
     __bss_start__ = .;
     *(.bss*)
     *(COMMON)
+    . = ALIGN(4);
     __bss_end__ = .;
   } > RAM
 
-  .heap :
+  .heap (COPY):
   {
+    __HeapBase = .;
     __end__ = .;
     end = __end__;
     _end = __end__;
-    *(.heap*)
+    KEEP(*(.heap*))
     __HeapLimit = .;
   } > RAM
 
   /* .stack_dummy section doesn't contains any symbols. It is only
    * used for linker to calculate size of stack sections, and assign
    * values to stack symbols later */
-  .stack_dummy :
+  .stack_dummy (COPY):
   {
-    *(.stack)
+    KEEP(*(.stack*))
   } > RAM
 
   /* Set stack top to end of RAM, and stack limit move down by
@@ -157,4 +209,7 @@
 
   /* Check if data + heap + stack exceeds RAM limit */
   ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+
+  /* Check if FLASH usage exceeds FLASH size */
+  ASSERT( LENGTH(FLASH) >= (__etext + SIZEOF(.data)), "FLASH memory overflowed !")
 }

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/TOOLCHAIN_GCC_ARM/startup_efm32lg.S	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/TOOLCHAIN_GCC_ARM/startup_efm32lg.S	Fri Jan 15 07:45:16 2016 +0000
@@ -1,233 +1,339 @@
 /* @file startup_efm32lg.S
  * @brief startup file for Silicon Labs EFM32LG devices.
  *        For use with GCC for ARM Embedded Processors
- * @version 3.20.6
- * Date: 08 Feb 2012
- *
- * Copyright (c) 2012, ARM Limited
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
-    * Redistributions of source code must retain the above copyright
-      notice, this list of conditions and the following disclaimer.
-    * Redistributions in binary form must reproduce the above copyright
-      notice, this list of conditions and the following disclaimer in the
-      documentation and/or other materials provided with the distribution.
-    * Neither the name of the ARM Limited nor the
-      names of its contributors may be used to endorse or promote products
-      derived from this software without specific prior written permission.
+ * @version 4.2.1
+ * Date:    12 June 2014
  *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
-    .syntax unified
-    .arch armv7-m
+/* Copyright (c) 2011 - 2014 ARM LIMITED
 
-    .section .stack
-    .align 3
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+    .syntax     unified
+    .arch       armv7-m
+    .section    .stack
+    .align      3
 #ifdef __STACK_SIZE
-    .equ    Stack_Size, __STACK_SIZE
+    .equ        Stack_Size, __STACK_SIZE
 #else
-    .equ    Stack_Size, 0x400
+    .equ        Stack_Size, 0x00000400
 #endif
-    .globl    __StackTop
-    .globl    __StackLimit
+    .globl      __StackTop
+    .globl      __StackLimit
 __StackLimit:
-    .space    Stack_Size
-    .size __StackLimit, . - __StackLimit
+    .space      Stack_Size
+    .size       __StackLimit, . - __StackLimit
 __StackTop:
-    .size __StackTop, . - __StackTop
+    .size       __StackTop, . - __StackTop
 
-    .section .heap
-    .align 3
+    .section    .heap
+    .align      3
 #ifdef __HEAP_SIZE
-    .equ    Heap_Size, __HEAP_SIZE
+    .equ        Heap_Size, __HEAP_SIZE
 #else
-    .equ    Heap_Size, 0xC00
+    .equ        Heap_Size, 0x00000C00
 #endif
-    .globl    __HeapBase
-    .globl    __HeapLimit
+    .globl      __HeapBase
+    .globl      __HeapLimit
 __HeapBase:
-    .if    Heap_Size
-    .space    Heap_Size
+    .if Heap_Size
+    .space      Heap_Size
     .endif
-    .size __HeapBase, . - __HeapBase
+    .size       __HeapBase, . - __HeapBase
 __HeapLimit:
-    .size __HeapLimit, . - __HeapLimit
+    .size       __HeapLimit, . - __HeapLimit
 
-    .section .isr_vector
-    .align 8
-    .globl __isr_vector
-__isr_vector:
-    .long    __StackTop            /* Top of Stack */
-    .long    Reset_Handler         /* Reset Handler */
-    .long    NMI_Handler           /* NMI Handler */
-    .long    HardFault_Handler     /* Hard Fault Handler */
-    .long    MemManage_Handler     /* MPU Fault Handler */
-    .long    BusFault_Handler      /* Bus Fault Handler */
-    .long    UsageFault_Handler    /* Usage Fault Handler */
-    .long    Default_Handler       /* Reserved */
-    .long    Default_Handler       /* Reserved */
-    .long    Default_Handler       /* Reserved */
-    .long    Default_Handler       /* Reserved */
-    .long    SVC_Handler           /* SVCall Handler */
-    .long    DebugMon_Handler      /* Debug Monitor Handler */
-    .long    Default_Handler       /* Reserved */
-    .long    PendSV_Handler        /* PendSV Handler */
-    .long    SysTick_Handler       /* SysTick Handler */
+    .section    .vectors
+    .align      2
+    .globl      __Vectors
+__Vectors:
+    .long       __StackTop            /* Top of Stack */
+    .long       Reset_Handler         /* Reset Handler */
+    .long       NMI_Handler           /* NMI Handler */
+    .long       HardFault_Handler     /* Hard Fault Handler */
+    .long       MemManage_Handler     /* MPU Fault Handler */
+    .long       BusFault_Handler      /* Bus Fault Handler */
+    .long       UsageFault_Handler    /* Usage Fault Handler */
+    .long       Default_Handler       /* Reserved */
+    .long       Default_Handler       /* Reserved */
+    .long       Default_Handler       /* Reserved */
+    .long       Default_Handler       /* Reserved */
+    .long       SVC_Handler           /* SVCall Handler */
+    .long       DebugMon_Handler      /* Debug Monitor Handler */
+    .long       Default_Handler       /* Reserved */
+    .long       PendSV_Handler        /* PendSV Handler */
+    .long       SysTick_Handler       /* SysTick Handler */
 
     /* External interrupts */
-    .long    DMA_IRQHandler    /* 0 - DMA */
-    .long    GPIO_EVEN_IRQHandler    /* 1 - GPIO_EVEN */
-    .long    TIMER0_IRQHandler    /* 2 - TIMER0 */
-    .long    USART0_RX_IRQHandler    /* 3 - USART0_RX */
-    .long    USART0_TX_IRQHandler    /* 4 - USART0_TX */
-    .long    USB_IRQHandler    /* 5 - USB */
-    .long    ACMP0_IRQHandler    /* 6 - ACMP0 */
-    .long    ADC0_IRQHandler    /* 7 - ADC0 */
-    .long    DAC0_IRQHandler    /* 8 - DAC0 */
-    .long    I2C0_IRQHandler    /* 9 - I2C0 */
-    .long    I2C1_IRQHandler    /* 10 - I2C1 */
-    .long    GPIO_ODD_IRQHandler    /* 11 - GPIO_ODD */
-    .long    TIMER1_IRQHandler    /* 12 - TIMER1 */
-    .long    TIMER2_IRQHandler    /* 13 - TIMER2 */
-    .long    TIMER3_IRQHandler    /* 14 - TIMER3 */
-    .long    USART1_RX_IRQHandler    /* 15 - USART1_RX */
-    .long    USART1_TX_IRQHandler    /* 16 - USART1_TX */
-    .long    LESENSE_IRQHandler    /* 17 - LESENSE */
-    .long    USART2_RX_IRQHandler    /* 18 - USART2_RX */
-    .long    USART2_TX_IRQHandler    /* 19 - USART2_TX */
-    .long    UART0_RX_IRQHandler    /* 20 - UART0_RX */
-    .long    UART0_TX_IRQHandler    /* 21 - UART0_TX */
-    .long    UART1_RX_IRQHandler    /* 22 - UART1_RX */
-    .long    UART1_TX_IRQHandler    /* 23 - UART1_TX */
-    .long    LEUART0_IRQHandler    /* 24 - LEUART0 */
-    .long    LEUART1_IRQHandler    /* 25 - LEUART1 */
-    .long    LETIMER0_IRQHandler    /* 26 - LETIMER0 */
-    .long    PCNT0_IRQHandler    /* 27 - PCNT0 */
-    .long    PCNT1_IRQHandler    /* 28 - PCNT1 */
-    .long    PCNT2_IRQHandler    /* 29 - PCNT2 */
-    .long    RTC_IRQHandler    /* 30 - RTC */
-    .long    BURTC_IRQHandler    /* 31 - BURTC */
-    .long    CMU_IRQHandler    /* 32 - CMU */
-    .long    VCMP_IRQHandler    /* 33 - VCMP */
-    .long    LCD_IRQHandler    /* 34 - LCD */
-    .long    MSC_IRQHandler    /* 35 - MSC */
-    .long    AES_IRQHandler    /* 36 - AES */
-    .long    EBI_IRQHandler    /* 37 - EBI */
-    .long    EMU_IRQHandler    /* 38 - EMU */
+
+    .long       DMA_IRQHandler    /* 0 - DMA */
+    .long       GPIO_EVEN_IRQHandler    /* 1 - GPIO_EVEN */
+    .long       TIMER0_IRQHandler    /* 2 - TIMER0 */
+    .long       USART0_RX_IRQHandler    /* 3 - USART0_RX */
+    .long       USART0_TX_IRQHandler    /* 4 - USART0_TX */
+    .long       USB_IRQHandler    /* 5 - USB */
+    .long       ACMP0_IRQHandler    /* 6 - ACMP0 */
+    .long       ADC0_IRQHandler    /* 7 - ADC0 */
+    .long       DAC0_IRQHandler    /* 8 - DAC0 */
+    .long       I2C0_IRQHandler    /* 9 - I2C0 */
+    .long       I2C1_IRQHandler    /* 10 - I2C1 */
+    .long       GPIO_ODD_IRQHandler    /* 11 - GPIO_ODD */
+    .long       TIMER1_IRQHandler    /* 12 - TIMER1 */
+    .long       TIMER2_IRQHandler    /* 13 - TIMER2 */
+    .long       TIMER3_IRQHandler    /* 14 - TIMER3 */
+    .long       USART1_RX_IRQHandler    /* 15 - USART1_RX */
+    .long       USART1_TX_IRQHandler    /* 16 - USART1_TX */
+    .long       LESENSE_IRQHandler    /* 17 - LESENSE */
+    .long       USART2_RX_IRQHandler    /* 18 - USART2_RX */
+    .long       USART2_TX_IRQHandler    /* 19 - USART2_TX */
+    .long       UART0_RX_IRQHandler    /* 20 - UART0_RX */
+    .long       UART0_TX_IRQHandler    /* 21 - UART0_TX */
+    .long       UART1_RX_IRQHandler    /* 22 - UART1_RX */
+    .long       UART1_TX_IRQHandler    /* 23 - UART1_TX */
+    .long       LEUART0_IRQHandler    /* 24 - LEUART0 */
+    .long       LEUART1_IRQHandler    /* 25 - LEUART1 */
+    .long       LETIMER0_IRQHandler    /* 26 - LETIMER0 */
+    .long       PCNT0_IRQHandler    /* 27 - PCNT0 */
+    .long       PCNT1_IRQHandler    /* 28 - PCNT1 */
+    .long       PCNT2_IRQHandler    /* 29 - PCNT2 */
+    .long       RTC_IRQHandler    /* 30 - RTC */
+    .long       BURTC_IRQHandler    /* 31 - BURTC */
+    .long       CMU_IRQHandler    /* 32 - CMU */
+    .long       VCMP_IRQHandler    /* 33 - VCMP */
+    .long       LCD_IRQHandler    /* 34 - LCD */
+    .long       MSC_IRQHandler    /* 35 - MSC */
+    .long       AES_IRQHandler    /* 36 - AES */
+    .long       EBI_IRQHandler    /* 37 - EBI */
+    .long       EMU_IRQHandler    /* 38 - EMU */
+    .long       Default_Handler    /* 39 - Reserved */
 
 
-    .size    __isr_vector, . - __isr_vector
+    .size       __Vectors, . - __Vectors
 
     .text
     .thumb
     .thumb_func
-    .align 2
-    .globl    Reset_Handler
-    .type    Reset_Handler, %function
+    .align      2
+    .globl      Reset_Handler
+    .type       Reset_Handler, %function
 Reset_Handler:
-/*     Loop to copy data from read only memory to RAM. The ranges
- *      of copy from/to are specified by following symbols evaluated in
- *      linker script.
- *      __etext: End of code section, i.e., begin of data sections to copy from.
- *      __data_start__/__data_end__: RAM address range that data should be
- *      copied to. Both must be aligned to 4 bytes boundary.  */
 #ifndef __NO_SYSTEM_INIT
-    ldr    r0, =SystemInit
-    blx    r0
+    ldr     r0, =SystemInit
+    blx     r0
 #endif
-    ldr    r1, =__etext
-    ldr    r2, =__data_start__
-    ldr    r3, =__data_end__
+
+/*  Firstly it copies data from read only memory to RAM. There are two schemes
+ *  to copy. One can copy more than one sections. Another can only copy
+ *  one section.  The former scheme needs more instructions and read-only
+ *  data to implement than the latter.
+ *  Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.  */
+
+#ifdef __STARTUP_COPY_MULTIPLE
+/*  Multiple sections scheme.
+ *
+ *  Between symbol address __copy_table_start__ and __copy_table_end__,
+ *  there are array of triplets, each of which specify:
+ *    offset 0: LMA of start of a section to copy from
+ *    offset 4: VMA of start of a section to copy to
+ *    offset 8: size of the section to copy. Must be multiply of 4
+ *
+ *  All addresses must be aligned to 4 bytes boundary.
+ */
+    ldr     r4, =__copy_table_start__
+    ldr     r5, =__copy_table_end__
+
+.L_loop0:
+    cmp     r4, r5
+    bge     .L_loop0_done
+    ldr     r1, [r4]
+    ldr     r2, [r4, #4]
+    ldr     r3, [r4, #8]
+
+.L_loop0_0:
+    subs    r3, #4
+    ittt    ge
+    ldrge   r0, [r1, r3]
+    strge   r0, [r2, r3]
+    bge     .L_loop0_0
+
+    adds    r4, #12
+    b       .L_loop0
+
+.L_loop0_done:
+#else
+/*  Single section scheme.
+ *
+ *  The ranges of copy from/to are specified by following symbols
+ *    __etext: LMA of start of the section to copy from. Usually end of text
+ *    __data_start__: VMA of start of the section to copy to
+ *    __data_end__: VMA of end of the section to copy to
+ *
+ *  All addresses must be aligned to 4 bytes boundary.
+ */
+    ldr     r1, =__etext
+    ldr     r2, =__data_start__
+    ldr     r3, =__data_end__
+
+.L_loop1:
+    cmp     r2, r3
+    ittt    lt
+    ldrlt   r0, [r1], #4
+    strlt   r0, [r2], #4
+    blt     .L_loop1
+#endif /*__STARTUP_COPY_MULTIPLE */
 
-    subs   r3, r2
-    ble    .flash_to_ram_loop_end
-.flash_to_ram_loop:
-    subs   r3, #4
-    ldr    r0, [r1, r3]
-    str    r0, [r2, r3]
-    bgt    .flash_to_ram_loop
-.flash_to_ram_loop_end:
+/*  This part of work usually is done in C library startup code. Otherwise,
+ *  define this macro to enable it in this startup.
+ *
+ *  There are two schemes too. One can clear multiple BSS sections. Another
+ *  can only clear one section. The former is more size expensive than the
+ *  latter.
+ *
+ *  Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ *  Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ */
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
+/*  Multiple sections scheme.
+ *
+ *  Between symbol address __copy_table_start__ and __copy_table_end__,
+ *  there are array of tuples specifying:
+ *    offset 0: Start of a BSS section
+ *    offset 4: Size of this BSS section. Must be multiply of 4
+ */
+    ldr     r3, =__zero_table_start__
+    ldr     r4, =__zero_table_end__
+
+.L_loop2:
+    cmp     r3, r4
+    bge     .L_loop2_done
+    ldr     r1, [r3]
+    ldr     r2, [r3, #4]
+    movs    r0, 0
 
-    ldr    r0, =_start
-    bx     r0
+.L_loop2_0:
+    subs    r2, #4
+    itt     ge
+    strge   r0, [r1, r2]
+    bge     .L_loop2_0
+    adds    r3, #8
+    b       .L_loop2
+.L_loop2_done:
+#elif defined (__STARTUP_CLEAR_BSS)
+/*  Single BSS section scheme.
+ *
+ *  The BSS section is specified by following symbols
+ *    __bss_start__: start of the BSS section.
+ *    __bss_end__: end of the BSS section.
+ *
+ *  Both addresses must be aligned to 4 bytes boundary.
+ */
+    ldr     r1, =__bss_start__
+    ldr     r2, =__bss_end__
+
+    movs    r0, 0
+.L_loop3:
+    cmp     r1, r2
+    itt     lt
+    strlt   r0, [r1], #4
+    blt     .L_loop3
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
+
+#ifndef __START
+#define __START _start
+#endif
+    bl      __START
+
     .pool
-    .size Reset_Handler, . - Reset_Handler
+    .size   Reset_Handler, . - Reset_Handler
+
+    .align  1
+    .thumb_func
+    .weak   Default_Handler
+    .type   Default_Handler, %function
+Default_Handler:
+    b       .
+    .size   Default_Handler, . - Default_Handler
 
 /*    Macro to define default handlers. Default handler
  *    will be weak symbol and just dead loops. They can be
  *    overwritten by other handlers */
-    .macro    def_irq_handler    handler_name
-    .align 1
-    .thumb_func
-    .weak    \handler_name
-    .type    \handler_name, %function
-\handler_name:
-    b    .
-    .size    \handler_name, . - \handler_name
+    .macro  def_irq_handler	handler_name
+    .weak   \handler_name
+    .set    \handler_name, Default_Handler
     .endm
 
-    def_irq_handler    Default_Handler
-
-    def_irq_handler    NMI_Handler
-    def_irq_handler    HardFault_Handler
-    def_irq_handler    MemManage_Handler
-    def_irq_handler    BusFault_Handler
-    def_irq_handler    UsageFault_Handler
-    def_irq_handler    SVC_Handler
-    def_irq_handler    DebugMon_Handler
-    def_irq_handler    PendSV_Handler
-    def_irq_handler    SysTick_Handler
+    def_irq_handler     NMI_Handler
+    def_irq_handler     HardFault_Handler
+    def_irq_handler     MemManage_Handler
+    def_irq_handler     BusFault_Handler
+    def_irq_handler     UsageFault_Handler
+    def_irq_handler     SVC_Handler
+    def_irq_handler     DebugMon_Handler
+    def_irq_handler     PendSV_Handler
+    def_irq_handler     SysTick_Handler
 
-    def_irq_handler    DMA_IRQHandler
-    def_irq_handler    GPIO_EVEN_IRQHandler
-    def_irq_handler    TIMER0_IRQHandler
-    def_irq_handler    USART0_RX_IRQHandler
-    def_irq_handler    USART0_TX_IRQHandler
-    def_irq_handler    USB_IRQHandler
-    def_irq_handler    ACMP0_IRQHandler
-    def_irq_handler    ADC0_IRQHandler
-    def_irq_handler    DAC0_IRQHandler
-    def_irq_handler    I2C0_IRQHandler
-    def_irq_handler    I2C1_IRQHandler
-    def_irq_handler    GPIO_ODD_IRQHandler
-    def_irq_handler    TIMER1_IRQHandler
-    def_irq_handler    TIMER2_IRQHandler
-    def_irq_handler    TIMER3_IRQHandler
-    def_irq_handler    USART1_RX_IRQHandler
-    def_irq_handler    USART1_TX_IRQHandler
-    def_irq_handler    LESENSE_IRQHandler
-    def_irq_handler    USART2_RX_IRQHandler
-    def_irq_handler    USART2_TX_IRQHandler
-    def_irq_handler    UART0_RX_IRQHandler
-    def_irq_handler    UART0_TX_IRQHandler
-    def_irq_handler    UART1_RX_IRQHandler
-    def_irq_handler    UART1_TX_IRQHandler
-    def_irq_handler    LEUART0_IRQHandler
-    def_irq_handler    LEUART1_IRQHandler
-    def_irq_handler    LETIMER0_IRQHandler
-    def_irq_handler    PCNT0_IRQHandler
-    def_irq_handler    PCNT1_IRQHandler
-    def_irq_handler    PCNT2_IRQHandler
-    def_irq_handler    RTC_IRQHandler
-    def_irq_handler    BURTC_IRQHandler
-    def_irq_handler    CMU_IRQHandler
-    def_irq_handler    VCMP_IRQHandler
-    def_irq_handler    LCD_IRQHandler
-    def_irq_handler    MSC_IRQHandler
-    def_irq_handler    AES_IRQHandler
-    def_irq_handler    EBI_IRQHandler
-    def_irq_handler    EMU_IRQHandler
+    def_irq_handler     DMA_IRQHandler
+    def_irq_handler     GPIO_EVEN_IRQHandler
+    def_irq_handler     TIMER0_IRQHandler
+    def_irq_handler     USART0_RX_IRQHandler
+    def_irq_handler     USART0_TX_IRQHandler
+    def_irq_handler     USB_IRQHandler
+    def_irq_handler     ACMP0_IRQHandler
+    def_irq_handler     ADC0_IRQHandler
+    def_irq_handler     DAC0_IRQHandler
+    def_irq_handler     I2C0_IRQHandler
+    def_irq_handler     I2C1_IRQHandler
+    def_irq_handler     GPIO_ODD_IRQHandler
+    def_irq_handler     TIMER1_IRQHandler
+    def_irq_handler     TIMER2_IRQHandler
+    def_irq_handler     TIMER3_IRQHandler
+    def_irq_handler     USART1_RX_IRQHandler
+    def_irq_handler     USART1_TX_IRQHandler
+    def_irq_handler     LESENSE_IRQHandler
+    def_irq_handler     USART2_RX_IRQHandler
+    def_irq_handler     USART2_TX_IRQHandler
+    def_irq_handler     UART0_RX_IRQHandler
+    def_irq_handler     UART0_TX_IRQHandler
+    def_irq_handler     UART1_RX_IRQHandler
+    def_irq_handler     UART1_TX_IRQHandler
+    def_irq_handler     LEUART0_IRQHandler
+    def_irq_handler     LEUART1_IRQHandler
+    def_irq_handler     LETIMER0_IRQHandler
+    def_irq_handler     PCNT0_IRQHandler
+    def_irq_handler     PCNT1_IRQHandler
+    def_irq_handler     PCNT2_IRQHandler
+    def_irq_handler     RTC_IRQHandler
+    def_irq_handler     BURTC_IRQHandler
+    def_irq_handler     CMU_IRQHandler
+    def_irq_handler     VCMP_IRQHandler
+    def_irq_handler     LCD_IRQHandler
+    def_irq_handler     MSC_IRQHandler
+    def_irq_handler     AES_IRQHandler
+    def_irq_handler     EBI_IRQHandler
+    def_irq_handler     EMU_IRQHandler
 
 
     .end

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/cmsis_nvic.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/cmsis_nvic.h	Fri Jan 15 07:45:16 2016 +0000
@@ -2,14 +2,14 @@
  * Copyright (c) 2009-2011 ARM Limited. All rights reserved.
  *
  * CMSIS-style functionality to support dynamic vectors
- */ 
+ */
 
 #ifndef MBED_CMSIS_NVIC_H
 #define MBED_CMSIS_NVIC_H
 
 #include "cmsis.h"
 
-#define NVIC_NUM_VECTORS      (16 + 39)   // CORE + MCU Peripherals
+#define NVIC_NUM_VECTORS      (16 + 40)   // CORE + MCU Peripherals
 #define NVIC_USER_IRQ_OFFSET  16
 
 #ifdef __cplusplus

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg990f256.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg990f256.h	Fri Jan 15 07:45:16 2016 +0000
@@ -2,10 +2,10 @@
  * @file efm32lg990f256.h
  * @brief CMSIS Cortex-M Peripheral Access Layer Header File
  *        for EFM32LG990F256
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -31,8 +31,8 @@
  *
  *****************************************************************************/
 
-#ifndef __EFM32LG990F256_H
-#define __EFM32LG990F256_H
+#ifndef EFM32LG990F256_H
+#define EFM32LG990F256_H
 
 #ifdef __cplusplus
 extern "C" {
@@ -52,7 +52,7 @@
 typedef enum IRQn
 {
 /******  Cortex-M3 Processor Exceptions Numbers *******************************************/
-  NonMaskableInt_IRQn   = -14,              /*!< 2 Non Maskable Interrupt                 */
+  NonMaskableInt_IRQn   = -14,              /*!< 2 Cortex-M3 Non Maskable Interrupt       */
   HardFault_IRQn        = -13,              /*!< 3 Cortex-M3 Hard Fault Interrupt         */
   MemoryManagement_IRQn = -12,              /*!< 4 Cortex-M3 Memory Management Interrupt  */
   BusFault_IRQn         = -11,              /*!< 5 Cortex-M3 Bus Fault Interrupt          */
@@ -63,6 +63,7 @@
   SysTick_IRQn          = -1,               /*!< 15 Cortex-M3 System Tick Interrupt       */
 
 /******  EFM32LG Peripheral Interrupt Numbers *********************************************/
+
   DMA_IRQn              = 0,  /*!< 16+0 EFM32 DMA Interrupt */
   GPIO_EVEN_IRQn        = 1,  /*!< 16+1 EFM32 GPIO_EVEN Interrupt */
   TIMER0_IRQn           = 2,  /*!< 16+2 EFM32 TIMER0 Interrupt */
@@ -121,8 +122,10 @@
 ******************************************************************************/
 
 /** Part family */
-#define _EFM32_GIANT_FAMILY    1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */
-#define _EFM_DEVICE              /**< Silicon Labs EFM-type microcontroller */
+#define _EFM32_GIANT_FAMILY             1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */
+#define _EFM_DEVICE                       /**< Silicon Labs EFM-type microcontroller */
+#define _SILICON_LABS_32B_PLATFORM_1      /**< Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM      1 /**< Silicon Labs platform name */
 
 /* If part number is not defined as compiler option, define it */
 #if !defined(EFM32LG990F256)
@@ -282,49 +285,7 @@
 #include "efm32lg_msc.h"
 #include "efm32lg_emu.h"
 #include "efm32lg_rmu.h"
-
-/**************************************************************************//**
- * @defgroup EFM32LG990F256_CMU EFM32LG990F256 CMU
- * @{
- * @brief EFM32LG990F256_CMU Register Declaration
- *****************************************************************************/
-typedef struct
-{
-  __IO uint32_t CTRL;         /**< CMU Control Register  */
-  __IO uint32_t HFCORECLKDIV; /**< High Frequency Core Clock Division Register  */
-  __IO uint32_t HFPERCLKDIV;  /**< High Frequency Peripheral Clock Division Register  */
-  __IO uint32_t HFRCOCTRL;    /**< HFRCO Control Register  */
-  __IO uint32_t LFRCOCTRL;    /**< LFRCO Control Register  */
-  __IO uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register  */
-  __IO uint32_t CALCTRL;      /**< Calibration Control Register  */
-  __IO uint32_t CALCNT;       /**< Calibration Counter Register  */
-  __IO uint32_t OSCENCMD;     /**< Oscillator Enable/Disable Command Register  */
-  __IO uint32_t CMD;          /**< Command Register  */
-  __IO uint32_t LFCLKSEL;     /**< Low Frequency Clock Select Register  */
-  __I uint32_t  STATUS;       /**< Status Register  */
-  __I uint32_t  IF;           /**< Interrupt Flag Register  */
-  __IO uint32_t IFS;          /**< Interrupt Flag Set Register  */
-  __IO uint32_t IFC;          /**< Interrupt Flag Clear Register  */
-  __IO uint32_t IEN;          /**< Interrupt Enable Register  */
-  __IO uint32_t HFCORECLKEN0; /**< High Frequency Core Clock Enable Register 0  */
-  __IO uint32_t HFPERCLKEN0;  /**< High Frequency Peripheral Clock Enable Register 0  */
-  uint32_t      RESERVED0[2]; /**< Reserved for future use **/
-  __I uint32_t  SYNCBUSY;     /**< Synchronization Busy Register  */
-  __IO uint32_t FREEZE;       /**< Freeze Register  */
-  __IO uint32_t LFACLKEN0;    /**< Low Frequency A Clock Enable Register 0  (Async Reg)  */
-  uint32_t      RESERVED1[1]; /**< Reserved for future use **/
-  __IO uint32_t LFBCLKEN0;    /**< Low Frequency B Clock Enable Register 0 (Async Reg)  */
-  uint32_t      RESERVED2[1]; /**< Reserved for future use **/
-  __IO uint32_t LFAPRESC0;    /**< Low Frequency A Prescaler Register 0 (Async Reg)  */
-  uint32_t      RESERVED3[1]; /**< Reserved for future use **/
-  __IO uint32_t LFBPRESC0;    /**< Low Frequency B Prescaler Register 0  (Async Reg)  */
-  uint32_t      RESERVED4[1]; /**< Reserved for future use **/
-  __IO uint32_t PCNTCTRL;     /**< PCNT Control Register  */
-  __IO uint32_t LCDCTRL;      /**< LCD Control Register  */
-  __IO uint32_t ROUTE;        /**< I/O Routing Register  */
-  __IO uint32_t LOCK;         /**< Configuration Lock Register  */
-} CMU_TypeDef;                /** @} */
-
+#include "efm32lg_cmu.h"
 #include "efm32lg_lesense_st.h"
 #include "efm32lg_lesense_buf.h"
 #include "efm32lg_lesense_ch.h"
@@ -469,1181 +430,6 @@
 #include "efm32lg_uart.h"
 
 /**************************************************************************//**
- * @defgroup EFM32LG990F256_CMU_BitFields  EFM32LG990F256_CMU Bit Fields
- * @{
- *****************************************************************************/
-
-/* Bit fields for CMU CTRL */
-#define _CMU_CTRL_RESETVALUE                        0x000C062CUL                                /**< Default value for CMU_CTRL */
-#define _CMU_CTRL_MASK                              0x53FFFEEFUL                                /**< Mask for CMU_CTRL */
-#define _CMU_CTRL_HFXOMODE_SHIFT                    0                                           /**< Shift value for CMU_HFXOMODE */
-#define _CMU_CTRL_HFXOMODE_MASK                     0x3UL                                       /**< Bit mask for CMU_HFXOMODE */
-#define _CMU_CTRL_HFXOMODE_DEFAULT                  0x00000000UL                                /**< Mode DEFAULT for CMU_CTRL */
-#define _CMU_CTRL_HFXOMODE_XTAL                     0x00000000UL                                /**< Mode XTAL for CMU_CTRL */
-#define _CMU_CTRL_HFXOMODE_BUFEXTCLK                0x00000001UL                                /**< Mode BUFEXTCLK for CMU_CTRL */
-#define _CMU_CTRL_HFXOMODE_DIGEXTCLK                0x00000002UL                                /**< Mode DIGEXTCLK for CMU_CTRL */
-#define CMU_CTRL_HFXOMODE_DEFAULT                   (_CMU_CTRL_HFXOMODE_DEFAULT << 0)           /**< Shifted mode DEFAULT for CMU_CTRL */
-#define CMU_CTRL_HFXOMODE_XTAL                      (_CMU_CTRL_HFXOMODE_XTAL << 0)              /**< Shifted mode XTAL for CMU_CTRL */
-#define CMU_CTRL_HFXOMODE_BUFEXTCLK                 (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0)         /**< Shifted mode BUFEXTCLK for CMU_CTRL */
-#define CMU_CTRL_HFXOMODE_DIGEXTCLK                 (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0)         /**< Shifted mode DIGEXTCLK for CMU_CTRL */
-#define _CMU_CTRL_HFXOBOOST_SHIFT                   2                                           /**< Shift value for CMU_HFXOBOOST */
-#define _CMU_CTRL_HFXOBOOST_MASK                    0xCUL                                       /**< Bit mask for CMU_HFXOBOOST */
-#define _CMU_CTRL_HFXOBOOST_50PCENT                 0x00000000UL                                /**< Mode 50PCENT for CMU_CTRL */
-#define _CMU_CTRL_HFXOBOOST_70PCENT                 0x00000001UL                                /**< Mode 70PCENT for CMU_CTRL */
-#define _CMU_CTRL_HFXOBOOST_80PCENT                 0x00000002UL                                /**< Mode 80PCENT for CMU_CTRL */
-#define _CMU_CTRL_HFXOBOOST_DEFAULT                 0x00000003UL                                /**< Mode DEFAULT for CMU_CTRL */
-#define _CMU_CTRL_HFXOBOOST_100PCENT                0x00000003UL                                /**< Mode 100PCENT for CMU_CTRL */
-#define CMU_CTRL_HFXOBOOST_50PCENT                  (_CMU_CTRL_HFXOBOOST_50PCENT << 2)          /**< Shifted mode 50PCENT for CMU_CTRL */
-#define CMU_CTRL_HFXOBOOST_70PCENT                  (_CMU_CTRL_HFXOBOOST_70PCENT << 2)          /**< Shifted mode 70PCENT for CMU_CTRL */
-#define CMU_CTRL_HFXOBOOST_80PCENT                  (_CMU_CTRL_HFXOBOOST_80PCENT << 2)          /**< Shifted mode 80PCENT for CMU_CTRL */
-#define CMU_CTRL_HFXOBOOST_DEFAULT                  (_CMU_CTRL_HFXOBOOST_DEFAULT << 2)          /**< Shifted mode DEFAULT for CMU_CTRL */
-#define CMU_CTRL_HFXOBOOST_100PCENT                 (_CMU_CTRL_HFXOBOOST_100PCENT << 2)         /**< Shifted mode 100PCENT for CMU_CTRL */
-#define _CMU_CTRL_HFXOBUFCUR_SHIFT                  5                                           /**< Shift value for CMU_HFXOBUFCUR */
-#define _CMU_CTRL_HFXOBUFCUR_MASK                   0x60UL                                      /**< Bit mask for CMU_HFXOBUFCUR */
-#define _CMU_CTRL_HFXOBUFCUR_DEFAULT                0x00000001UL                                /**< Mode DEFAULT for CMU_CTRL */
-#define _CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ         0x00000001UL                                /**< Mode BOOSTUPTO32MHZ for CMU_CTRL */
-#define _CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ        0x00000003UL                                /**< Mode BOOSTABOVE32MHZ for CMU_CTRL */
-#define CMU_CTRL_HFXOBUFCUR_DEFAULT                 (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5)         /**< Shifted mode DEFAULT for CMU_CTRL */
-#define CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ          (_CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ << 5)  /**< Shifted mode BOOSTUPTO32MHZ for CMU_CTRL */
-#define CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ         (_CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ << 5) /**< Shifted mode BOOSTABOVE32MHZ for CMU_CTRL */
-#define CMU_CTRL_HFXOGLITCHDETEN                    (0x1UL << 7)                                /**< HFXO Glitch Detector Enable */
-#define _CMU_CTRL_HFXOGLITCHDETEN_SHIFT             7                                           /**< Shift value for CMU_HFXOGLITCHDETEN */
-#define _CMU_CTRL_HFXOGLITCHDETEN_MASK              0x80UL                                      /**< Bit mask for CMU_HFXOGLITCHDETEN */
-#define _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT           0x00000000UL                                /**< Mode DEFAULT for CMU_CTRL */
-#define CMU_CTRL_HFXOGLITCHDETEN_DEFAULT            (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7)    /**< Shifted mode DEFAULT for CMU_CTRL */
-#define _CMU_CTRL_HFXOTIMEOUT_SHIFT                 9                                           /**< Shift value for CMU_HFXOTIMEOUT */
-#define _CMU_CTRL_HFXOTIMEOUT_MASK                  0x600UL                                     /**< Bit mask for CMU_HFXOTIMEOUT */
-#define _CMU_CTRL_HFXOTIMEOUT_8CYCLES               0x00000000UL                                /**< Mode 8CYCLES for CMU_CTRL */
-#define _CMU_CTRL_HFXOTIMEOUT_256CYCLES             0x00000001UL                                /**< Mode 256CYCLES for CMU_CTRL */
-#define _CMU_CTRL_HFXOTIMEOUT_1KCYCLES              0x00000002UL                                /**< Mode 1KCYCLES for CMU_CTRL */
-#define _CMU_CTRL_HFXOTIMEOUT_DEFAULT               0x00000003UL                                /**< Mode DEFAULT for CMU_CTRL */
-#define _CMU_CTRL_HFXOTIMEOUT_16KCYCLES             0x00000003UL                                /**< Mode 16KCYCLES for CMU_CTRL */
-#define CMU_CTRL_HFXOTIMEOUT_8CYCLES                (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9)        /**< Shifted mode 8CYCLES for CMU_CTRL */
-#define CMU_CTRL_HFXOTIMEOUT_256CYCLES              (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9)      /**< Shifted mode 256CYCLES for CMU_CTRL */
-#define CMU_CTRL_HFXOTIMEOUT_1KCYCLES               (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9)       /**< Shifted mode 1KCYCLES for CMU_CTRL */
-#define CMU_CTRL_HFXOTIMEOUT_DEFAULT                (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9)        /**< Shifted mode DEFAULT for CMU_CTRL */
-#define CMU_CTRL_HFXOTIMEOUT_16KCYCLES              (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9)      /**< Shifted mode 16KCYCLES for CMU_CTRL */
-#define _CMU_CTRL_LFXOMODE_SHIFT                    11                                          /**< Shift value for CMU_LFXOMODE */
-#define _CMU_CTRL_LFXOMODE_MASK                     0x1800UL                                    /**< Bit mask for CMU_LFXOMODE */
-#define _CMU_CTRL_LFXOMODE_DEFAULT                  0x00000000UL                                /**< Mode DEFAULT for CMU_CTRL */
-#define _CMU_CTRL_LFXOMODE_XTAL                     0x00000000UL                                /**< Mode XTAL for CMU_CTRL */
-#define _CMU_CTRL_LFXOMODE_BUFEXTCLK                0x00000001UL                                /**< Mode BUFEXTCLK for CMU_CTRL */
-#define _CMU_CTRL_LFXOMODE_DIGEXTCLK                0x00000002UL                                /**< Mode DIGEXTCLK for CMU_CTRL */
-#define CMU_CTRL_LFXOMODE_DEFAULT                   (_CMU_CTRL_LFXOMODE_DEFAULT << 11)          /**< Shifted mode DEFAULT for CMU_CTRL */
-#define CMU_CTRL_LFXOMODE_XTAL                      (_CMU_CTRL_LFXOMODE_XTAL << 11)             /**< Shifted mode XTAL for CMU_CTRL */
-#define CMU_CTRL_LFXOMODE_BUFEXTCLK                 (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11)        /**< Shifted mode BUFEXTCLK for CMU_CTRL */
-#define CMU_CTRL_LFXOMODE_DIGEXTCLK                 (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11)        /**< Shifted mode DIGEXTCLK for CMU_CTRL */
-#define CMU_CTRL_LFXOBOOST                          (0x1UL << 13)                               /**< LFXO Start-up Boost Current */
-#define _CMU_CTRL_LFXOBOOST_SHIFT                   13                                          /**< Shift value for CMU_LFXOBOOST */
-#define _CMU_CTRL_LFXOBOOST_MASK                    0x2000UL                                    /**< Bit mask for CMU_LFXOBOOST */
-#define _CMU_CTRL_LFXOBOOST_70PCENT                 0x00000000UL                                /**< Mode 70PCENT for CMU_CTRL */
-#define _CMU_CTRL_LFXOBOOST_DEFAULT                 0x00000001UL                                /**< Mode DEFAULT for CMU_CTRL */
-#define _CMU_CTRL_LFXOBOOST_100PCENT                0x00000001UL                                /**< Mode 100PCENT for CMU_CTRL */
-#define CMU_CTRL_LFXOBOOST_70PCENT                  (_CMU_CTRL_LFXOBOOST_70PCENT << 13)         /**< Shifted mode 70PCENT for CMU_CTRL */
-#define CMU_CTRL_LFXOBOOST_DEFAULT                  (_CMU_CTRL_LFXOBOOST_DEFAULT << 13)         /**< Shifted mode DEFAULT for CMU_CTRL */
-#define CMU_CTRL_LFXOBOOST_100PCENT                 (_CMU_CTRL_LFXOBOOST_100PCENT << 13)        /**< Shifted mode 100PCENT for CMU_CTRL */
-#define _CMU_CTRL_HFCLKDIV_SHIFT                    14                                          /**< Shift value for CMU_HFCLKDIV */
-#define _CMU_CTRL_HFCLKDIV_MASK                     0x1C000UL                                   /**< Bit mask for CMU_HFCLKDIV */
-#define _CMU_CTRL_HFCLKDIV_DEFAULT                  0x00000000UL                                /**< Mode DEFAULT for CMU_CTRL */
-#define CMU_CTRL_HFCLKDIV_DEFAULT                   (_CMU_CTRL_HFCLKDIV_DEFAULT << 14)          /**< Shifted mode DEFAULT for CMU_CTRL */
-#define CMU_CTRL_LFXOBUFCUR                         (0x1UL << 17)                               /**< LFXO Boost Buffer Current */
-#define _CMU_CTRL_LFXOBUFCUR_SHIFT                  17                                          /**< Shift value for CMU_LFXOBUFCUR */
-#define _CMU_CTRL_LFXOBUFCUR_MASK                   0x20000UL                                   /**< Bit mask for CMU_LFXOBUFCUR */
-#define _CMU_CTRL_LFXOBUFCUR_DEFAULT                0x00000000UL                                /**< Mode DEFAULT for CMU_CTRL */
-#define CMU_CTRL_LFXOBUFCUR_DEFAULT                 (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17)        /**< Shifted mode DEFAULT for CMU_CTRL */
-#define _CMU_CTRL_LFXOTIMEOUT_SHIFT                 18                                          /**< Shift value for CMU_LFXOTIMEOUT */
-#define _CMU_CTRL_LFXOTIMEOUT_MASK                  0xC0000UL                                   /**< Bit mask for CMU_LFXOTIMEOUT */
-#define _CMU_CTRL_LFXOTIMEOUT_8CYCLES               0x00000000UL                                /**< Mode 8CYCLES for CMU_CTRL */
-#define _CMU_CTRL_LFXOTIMEOUT_1KCYCLES              0x00000001UL                                /**< Mode 1KCYCLES for CMU_CTRL */
-#define _CMU_CTRL_LFXOTIMEOUT_16KCYCLES             0x00000002UL                                /**< Mode 16KCYCLES for CMU_CTRL */
-#define _CMU_CTRL_LFXOTIMEOUT_DEFAULT               0x00000003UL                                /**< Mode DEFAULT for CMU_CTRL */
-#define _CMU_CTRL_LFXOTIMEOUT_32KCYCLES             0x00000003UL                                /**< Mode 32KCYCLES for CMU_CTRL */
-#define CMU_CTRL_LFXOTIMEOUT_8CYCLES                (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18)       /**< Shifted mode 8CYCLES for CMU_CTRL */
-#define CMU_CTRL_LFXOTIMEOUT_1KCYCLES               (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18)      /**< Shifted mode 1KCYCLES for CMU_CTRL */
-#define CMU_CTRL_LFXOTIMEOUT_16KCYCLES              (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18)     /**< Shifted mode 16KCYCLES for CMU_CTRL */
-#define CMU_CTRL_LFXOTIMEOUT_DEFAULT                (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18)       /**< Shifted mode DEFAULT for CMU_CTRL */
-#define CMU_CTRL_LFXOTIMEOUT_32KCYCLES              (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18)     /**< Shifted mode 32KCYCLES for CMU_CTRL */
-#define _CMU_CTRL_CLKOUTSEL0_SHIFT                  20                                          /**< Shift value for CMU_CLKOUTSEL0 */
-#define _CMU_CTRL_CLKOUTSEL0_MASK                   0x700000UL                                  /**< Bit mask for CMU_CLKOUTSEL0 */
-#define _CMU_CTRL_CLKOUTSEL0_DEFAULT                0x00000000UL                                /**< Mode DEFAULT for CMU_CTRL */
-#define _CMU_CTRL_CLKOUTSEL0_HFRCO                  0x00000000UL                                /**< Mode HFRCO for CMU_CTRL */
-#define _CMU_CTRL_CLKOUTSEL0_HFXO                   0x00000001UL                                /**< Mode HFXO for CMU_CTRL */
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK2                 0x00000002UL                                /**< Mode HFCLK2 for CMU_CTRL */
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK4                 0x00000003UL                                /**< Mode HFCLK4 for CMU_CTRL */
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK8                 0x00000004UL                                /**< Mode HFCLK8 for CMU_CTRL */
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK16                0x00000005UL                                /**< Mode HFCLK16 for CMU_CTRL */
-#define _CMU_CTRL_CLKOUTSEL0_ULFRCO                 0x00000006UL                                /**< Mode ULFRCO for CMU_CTRL */
-#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCO               0x00000007UL                                /**< Mode AUXHFRCO for CMU_CTRL */
-#define CMU_CTRL_CLKOUTSEL0_DEFAULT                 (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20)        /**< Shifted mode DEFAULT for CMU_CTRL */
-#define CMU_CTRL_CLKOUTSEL0_HFRCO                   (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20)          /**< Shifted mode HFRCO for CMU_CTRL */
-#define CMU_CTRL_CLKOUTSEL0_HFXO                    (_CMU_CTRL_CLKOUTSEL0_HFXO << 20)           /**< Shifted mode HFXO for CMU_CTRL */
-#define CMU_CTRL_CLKOUTSEL0_HFCLK2                  (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20)         /**< Shifted mode HFCLK2 for CMU_CTRL */
-#define CMU_CTRL_CLKOUTSEL0_HFCLK4                  (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20)         /**< Shifted mode HFCLK4 for CMU_CTRL */
-#define CMU_CTRL_CLKOUTSEL0_HFCLK8                  (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20)         /**< Shifted mode HFCLK8 for CMU_CTRL */
-#define CMU_CTRL_CLKOUTSEL0_HFCLK16                 (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20)        /**< Shifted mode HFCLK16 for CMU_CTRL */
-#define CMU_CTRL_CLKOUTSEL0_ULFRCO                  (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20)         /**< Shifted mode ULFRCO for CMU_CTRL */
-#define CMU_CTRL_CLKOUTSEL0_AUXHFRCO                (_CMU_CTRL_CLKOUTSEL0_AUXHFRCO << 20)       /**< Shifted mode AUXHFRCO for CMU_CTRL */
-#define _CMU_CTRL_CLKOUTSEL1_SHIFT                  23                                          /**< Shift value for CMU_CLKOUTSEL1 */
-#define _CMU_CTRL_CLKOUTSEL1_MASK                   0x3800000UL                                 /**< Bit mask for CMU_CLKOUTSEL1 */
-#define _CMU_CTRL_CLKOUTSEL1_DEFAULT                0x00000000UL                                /**< Mode DEFAULT for CMU_CTRL */
-#define _CMU_CTRL_CLKOUTSEL1_LFRCO                  0x00000000UL                                /**< Mode LFRCO for CMU_CTRL */
-#define _CMU_CTRL_CLKOUTSEL1_LFXO                   0x00000001UL                                /**< Mode LFXO for CMU_CTRL */
-#define _CMU_CTRL_CLKOUTSEL1_HFCLK                  0x00000002UL                                /**< Mode HFCLK for CMU_CTRL */
-#define _CMU_CTRL_CLKOUTSEL1_LFXOQ                  0x00000003UL                                /**< Mode LFXOQ for CMU_CTRL */
-#define _CMU_CTRL_CLKOUTSEL1_HFXOQ                  0x00000004UL                                /**< Mode HFXOQ for CMU_CTRL */
-#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ                 0x00000005UL                                /**< Mode LFRCOQ for CMU_CTRL */
-#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ                 0x00000006UL                                /**< Mode HFRCOQ for CMU_CTRL */
-#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ              0x00000007UL                                /**< Mode AUXHFRCOQ for CMU_CTRL */
-#define CMU_CTRL_CLKOUTSEL1_DEFAULT                 (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23)        /**< Shifted mode DEFAULT for CMU_CTRL */
-#define CMU_CTRL_CLKOUTSEL1_LFRCO                   (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23)          /**< Shifted mode LFRCO for CMU_CTRL */
-#define CMU_CTRL_CLKOUTSEL1_LFXO                    (_CMU_CTRL_CLKOUTSEL1_LFXO << 23)           /**< Shifted mode LFXO for CMU_CTRL */
-#define CMU_CTRL_CLKOUTSEL1_HFCLK                   (_CMU_CTRL_CLKOUTSEL1_HFCLK << 23)          /**< Shifted mode HFCLK for CMU_CTRL */
-#define CMU_CTRL_CLKOUTSEL1_LFXOQ                   (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 23)          /**< Shifted mode LFXOQ for CMU_CTRL */
-#define CMU_CTRL_CLKOUTSEL1_HFXOQ                   (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 23)          /**< Shifted mode HFXOQ for CMU_CTRL */
-#define CMU_CTRL_CLKOUTSEL1_LFRCOQ                  (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 23)         /**< Shifted mode LFRCOQ for CMU_CTRL */
-#define CMU_CTRL_CLKOUTSEL1_HFRCOQ                  (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 23)         /**< Shifted mode HFRCOQ for CMU_CTRL */
-#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ               (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 23)      /**< Shifted mode AUXHFRCOQ for CMU_CTRL */
-#define CMU_CTRL_DBGCLK                             (0x1UL << 28)                               /**< Debug Clock */
-#define _CMU_CTRL_DBGCLK_SHIFT                      28                                          /**< Shift value for CMU_DBGCLK */
-#define _CMU_CTRL_DBGCLK_MASK                       0x10000000UL                                /**< Bit mask for CMU_DBGCLK */
-#define _CMU_CTRL_DBGCLK_DEFAULT                    0x00000000UL                                /**< Mode DEFAULT for CMU_CTRL */
-#define _CMU_CTRL_DBGCLK_AUXHFRCO                   0x00000000UL                                /**< Mode AUXHFRCO for CMU_CTRL */
-#define _CMU_CTRL_DBGCLK_HFCLK                      0x00000001UL                                /**< Mode HFCLK for CMU_CTRL */
-#define CMU_CTRL_DBGCLK_DEFAULT                     (_CMU_CTRL_DBGCLK_DEFAULT << 28)            /**< Shifted mode DEFAULT for CMU_CTRL */
-#define CMU_CTRL_DBGCLK_AUXHFRCO                    (_CMU_CTRL_DBGCLK_AUXHFRCO << 28)           /**< Shifted mode AUXHFRCO for CMU_CTRL */
-#define CMU_CTRL_DBGCLK_HFCLK                       (_CMU_CTRL_DBGCLK_HFCLK << 28)              /**< Shifted mode HFCLK for CMU_CTRL */
-#define CMU_CTRL_HFLE                               (0x1UL << 30)                               /**< High-Frequency LE Interface */
-#define _CMU_CTRL_HFLE_SHIFT                        30                                          /**< Shift value for CMU_HFLE */
-#define _CMU_CTRL_HFLE_MASK                         0x40000000UL                                /**< Bit mask for CMU_HFLE */
-#define _CMU_CTRL_HFLE_DEFAULT                      0x00000000UL                                /**< Mode DEFAULT for CMU_CTRL */
-#define CMU_CTRL_HFLE_DEFAULT                       (_CMU_CTRL_HFLE_DEFAULT << 30)              /**< Shifted mode DEFAULT for CMU_CTRL */
-
-/* Bit fields for CMU HFCORECLKDIV */
-#define _CMU_HFCORECLKDIV_RESETVALUE                0x00000000UL                                    /**< Default value for CMU_HFCORECLKDIV */
-#define _CMU_HFCORECLKDIV_MASK                      0x0000010FUL                                    /**< Mask for CMU_HFCORECLKDIV */
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT        0                                               /**< Shift value for CMU_HFCORECLKDIV */
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK         0xFUL                                           /**< Bit mask for CMU_HFCORECLKDIV */
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT      0x00000000UL                                    /**< Mode DEFAULT for CMU_HFCORECLKDIV */
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK        0x00000000UL                                    /**< Mode HFCLK for CMU_HFCORECLKDIV */
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2       0x00000001UL                                    /**< Mode HFCLK2 for CMU_HFCORECLKDIV */
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4       0x00000002UL                                    /**< Mode HFCLK4 for CMU_HFCORECLKDIV */
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8       0x00000003UL                                    /**< Mode HFCLK8 for CMU_HFCORECLKDIV */
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16      0x00000004UL                                    /**< Mode HFCLK16 for CMU_HFCORECLKDIV */
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32      0x00000005UL                                    /**< Mode HFCLK32 for CMU_HFCORECLKDIV */
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64      0x00000006UL                                    /**< Mode HFCLK64 for CMU_HFCORECLKDIV */
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128     0x00000007UL                                    /**< Mode HFCLK128 for CMU_HFCORECLKDIV */
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256     0x00000008UL                                    /**< Mode HFCLK256 for CMU_HFCORECLKDIV */
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512     0x00000009UL                                    /**< Mode HFCLK512 for CMU_HFCORECLKDIV */
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT       (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0)   /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK         (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0)     /**< Shifted mode HFCLK for CMU_HFCORECLKDIV */
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2        (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0)    /**< Shifted mode HFCLK2 for CMU_HFCORECLKDIV */
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4        (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0)    /**< Shifted mode HFCLK4 for CMU_HFCORECLKDIV */
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8        (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0)    /**< Shifted mode HFCLK8 for CMU_HFCORECLKDIV */
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16       (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0)   /**< Shifted mode HFCLK16 for CMU_HFCORECLKDIV */
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32       (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0)   /**< Shifted mode HFCLK32 for CMU_HFCORECLKDIV */
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64       (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0)   /**< Shifted mode HFCLK64 for CMU_HFCORECLKDIV */
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128      (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0)  /**< Shifted mode HFCLK128 for CMU_HFCORECLKDIV */
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256      (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0)  /**< Shifted mode HFCLK256 for CMU_HFCORECLKDIV */
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512      (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0)  /**< Shifted mode HFCLK512 for CMU_HFCORECLKDIV */
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV             (0x1UL << 8)                                    /**< Additional Division Factor For HFCORECLKLE */
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT      8                                               /**< Shift value for CMU_HFCORECLKLEDIV */
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK       0x100UL                                         /**< Bit mask for CMU_HFCORECLKLEDIV */
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT    0x00000000UL                                    /**< Mode DEFAULT for CMU_HFCORECLKDIV */
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2       0x00000000UL                                    /**< Mode DIV2 for CMU_HFCORECLKDIV */
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4       0x00000001UL                                    /**< Mode DIV4 for CMU_HFCORECLKDIV */
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT     (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2        (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 << 8)    /**< Shifted mode DIV2 for CMU_HFCORECLKDIV */
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4        (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 << 8)    /**< Shifted mode DIV4 for CMU_HFCORECLKDIV */
-
-/* Bit fields for CMU HFPERCLKDIV */
-#define _CMU_HFPERCLKDIV_RESETVALUE                 0x00000100UL                                 /**< Default value for CMU_HFPERCLKDIV */
-#define _CMU_HFPERCLKDIV_MASK                       0x0000010FUL                                 /**< Mask for CMU_HFPERCLKDIV */
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT          0                                            /**< Shift value for CMU_HFPERCLKDIV */
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK           0xFUL                                        /**< Bit mask for CMU_HFPERCLKDIV */
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT        0x00000000UL                                 /**< Mode DEFAULT for CMU_HFPERCLKDIV */
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK          0x00000000UL                                 /**< Mode HFCLK for CMU_HFPERCLKDIV */
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2         0x00000001UL                                 /**< Mode HFCLK2 for CMU_HFPERCLKDIV */
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4         0x00000002UL                                 /**< Mode HFCLK4 for CMU_HFPERCLKDIV */
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8         0x00000003UL                                 /**< Mode HFCLK8 for CMU_HFPERCLKDIV */
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16        0x00000004UL                                 /**< Mode HFCLK16 for CMU_HFPERCLKDIV */
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32        0x00000005UL                                 /**< Mode HFCLK32 for CMU_HFPERCLKDIV */
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64        0x00000006UL                                 /**< Mode HFCLK64 for CMU_HFPERCLKDIV */
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128       0x00000007UL                                 /**< Mode HFCLK128 for CMU_HFPERCLKDIV */
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256       0x00000008UL                                 /**< Mode HFCLK256 for CMU_HFPERCLKDIV */
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512       0x00000009UL                                 /**< Mode HFCLK512 for CMU_HFPERCLKDIV */
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT         (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0)  /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK           (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0)    /**< Shifted mode HFCLK for CMU_HFPERCLKDIV */
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2          (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0)   /**< Shifted mode HFCLK2 for CMU_HFPERCLKDIV */
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4          (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0)   /**< Shifted mode HFCLK4 for CMU_HFPERCLKDIV */
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8          (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0)   /**< Shifted mode HFCLK8 for CMU_HFPERCLKDIV */
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16         (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0)  /**< Shifted mode HFCLK16 for CMU_HFPERCLKDIV */
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32         (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0)  /**< Shifted mode HFCLK32 for CMU_HFPERCLKDIV */
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64         (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0)  /**< Shifted mode HFCLK64 for CMU_HFPERCLKDIV */
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128        (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFPERCLKDIV */
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256        (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFPERCLKDIV */
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512        (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFPERCLKDIV */
-#define CMU_HFPERCLKDIV_HFPERCLKEN                  (0x1UL << 8)                                 /**< HFPERCLK Enable */
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT           8                                            /**< Shift value for CMU_HFPERCLKEN */
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_MASK            0x100UL                                      /**< Bit mask for CMU_HFPERCLKEN */
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT         0x00000001UL                                 /**< Mode DEFAULT for CMU_HFPERCLKDIV */
-#define CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT          (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8)   /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */
-
-/* Bit fields for CMU HFRCOCTRL */
-#define _CMU_HFRCOCTRL_RESETVALUE                   0x00000380UL                           /**< Default value for CMU_HFRCOCTRL */
-#define _CMU_HFRCOCTRL_MASK                         0x0001F7FFUL                           /**< Mask for CMU_HFRCOCTRL */
-#define _CMU_HFRCOCTRL_TUNING_SHIFT                 0                                      /**< Shift value for CMU_TUNING */
-#define _CMU_HFRCOCTRL_TUNING_MASK                  0xFFUL                                 /**< Bit mask for CMU_TUNING */
-#define _CMU_HFRCOCTRL_TUNING_DEFAULT               0x00000080UL                           /**< Mode DEFAULT for CMU_HFRCOCTRL */
-#define CMU_HFRCOCTRL_TUNING_DEFAULT                (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0)   /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */
-#define _CMU_HFRCOCTRL_BAND_SHIFT                   8                                      /**< Shift value for CMU_BAND */
-#define _CMU_HFRCOCTRL_BAND_MASK                    0x700UL                                /**< Bit mask for CMU_BAND */
-#define _CMU_HFRCOCTRL_BAND_1MHZ                    0x00000000UL                           /**< Mode 1MHZ for CMU_HFRCOCTRL */
-#define _CMU_HFRCOCTRL_BAND_7MHZ                    0x00000001UL                           /**< Mode 7MHZ for CMU_HFRCOCTRL */
-#define _CMU_HFRCOCTRL_BAND_11MHZ                   0x00000002UL                           /**< Mode 11MHZ for CMU_HFRCOCTRL */
-#define _CMU_HFRCOCTRL_BAND_DEFAULT                 0x00000003UL                           /**< Mode DEFAULT for CMU_HFRCOCTRL */
-#define _CMU_HFRCOCTRL_BAND_14MHZ                   0x00000003UL                           /**< Mode 14MHZ for CMU_HFRCOCTRL */
-#define _CMU_HFRCOCTRL_BAND_21MHZ                   0x00000004UL                           /**< Mode 21MHZ for CMU_HFRCOCTRL */
-#define _CMU_HFRCOCTRL_BAND_28MHZ                   0x00000005UL                           /**< Mode 28MHZ for CMU_HFRCOCTRL */
-#define CMU_HFRCOCTRL_BAND_1MHZ                     (_CMU_HFRCOCTRL_BAND_1MHZ << 8)        /**< Shifted mode 1MHZ for CMU_HFRCOCTRL */
-#define CMU_HFRCOCTRL_BAND_7MHZ                     (_CMU_HFRCOCTRL_BAND_7MHZ << 8)        /**< Shifted mode 7MHZ for CMU_HFRCOCTRL */
-#define CMU_HFRCOCTRL_BAND_11MHZ                    (_CMU_HFRCOCTRL_BAND_11MHZ << 8)       /**< Shifted mode 11MHZ for CMU_HFRCOCTRL */
-#define CMU_HFRCOCTRL_BAND_DEFAULT                  (_CMU_HFRCOCTRL_BAND_DEFAULT << 8)     /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */
-#define CMU_HFRCOCTRL_BAND_14MHZ                    (_CMU_HFRCOCTRL_BAND_14MHZ << 8)       /**< Shifted mode 14MHZ for CMU_HFRCOCTRL */
-#define CMU_HFRCOCTRL_BAND_21MHZ                    (_CMU_HFRCOCTRL_BAND_21MHZ << 8)       /**< Shifted mode 21MHZ for CMU_HFRCOCTRL */
-#define CMU_HFRCOCTRL_BAND_28MHZ                    (_CMU_HFRCOCTRL_BAND_28MHZ << 8)       /**< Shifted mode 28MHZ for CMU_HFRCOCTRL */
-#define _CMU_HFRCOCTRL_SUDELAY_SHIFT                12                                     /**< Shift value for CMU_SUDELAY */
-#define _CMU_HFRCOCTRL_SUDELAY_MASK                 0x1F000UL                              /**< Bit mask for CMU_SUDELAY */
-#define _CMU_HFRCOCTRL_SUDELAY_DEFAULT              0x00000000UL                           /**< Mode DEFAULT for CMU_HFRCOCTRL */
-#define CMU_HFRCOCTRL_SUDELAY_DEFAULT               (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */
-
-/* Bit fields for CMU LFRCOCTRL */
-#define _CMU_LFRCOCTRL_RESETVALUE                   0x00000040UL                         /**< Default value for CMU_LFRCOCTRL */
-#define _CMU_LFRCOCTRL_MASK                         0x0000007FUL                         /**< Mask for CMU_LFRCOCTRL */
-#define _CMU_LFRCOCTRL_TUNING_SHIFT                 0                                    /**< Shift value for CMU_TUNING */
-#define _CMU_LFRCOCTRL_TUNING_MASK                  0x7FUL                               /**< Bit mask for CMU_TUNING */
-#define _CMU_LFRCOCTRL_TUNING_DEFAULT               0x00000040UL                         /**< Mode DEFAULT for CMU_LFRCOCTRL */
-#define CMU_LFRCOCTRL_TUNING_DEFAULT                (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */
-
-/* Bit fields for CMU AUXHFRCOCTRL */
-#define _CMU_AUXHFRCOCTRL_RESETVALUE                0x00000080UL                            /**< Default value for CMU_AUXHFRCOCTRL */
-#define _CMU_AUXHFRCOCTRL_MASK                      0x000007FFUL                            /**< Mask for CMU_AUXHFRCOCTRL */
-#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT              0                                       /**< Shift value for CMU_TUNING */
-#define _CMU_AUXHFRCOCTRL_TUNING_MASK               0xFFUL                                  /**< Bit mask for CMU_TUNING */
-#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT            0x00000080UL                            /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */
-#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT             (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */
-#define _CMU_AUXHFRCOCTRL_BAND_SHIFT                8                                       /**< Shift value for CMU_BAND */
-#define _CMU_AUXHFRCOCTRL_BAND_MASK                 0x700UL                                 /**< Bit mask for CMU_BAND */
-#define _CMU_AUXHFRCOCTRL_BAND_DEFAULT              0x00000000UL                            /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */
-#define _CMU_AUXHFRCOCTRL_BAND_14MHZ                0x00000000UL                            /**< Mode 14MHZ for CMU_AUXHFRCOCTRL */
-#define _CMU_AUXHFRCOCTRL_BAND_11MHZ                0x00000001UL                            /**< Mode 11MHZ for CMU_AUXHFRCOCTRL */
-#define _CMU_AUXHFRCOCTRL_BAND_7MHZ                 0x00000002UL                            /**< Mode 7MHZ for CMU_AUXHFRCOCTRL */
-#define _CMU_AUXHFRCOCTRL_BAND_1MHZ                 0x00000003UL                            /**< Mode 1MHZ for CMU_AUXHFRCOCTRL */
-#define _CMU_AUXHFRCOCTRL_BAND_28MHZ                0x00000006UL                            /**< Mode 28MHZ for CMU_AUXHFRCOCTRL */
-#define _CMU_AUXHFRCOCTRL_BAND_21MHZ                0x00000007UL                            /**< Mode 21MHZ for CMU_AUXHFRCOCTRL */
-#define CMU_AUXHFRCOCTRL_BAND_DEFAULT               (_CMU_AUXHFRCOCTRL_BAND_DEFAULT << 8)   /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */
-#define CMU_AUXHFRCOCTRL_BAND_14MHZ                 (_CMU_AUXHFRCOCTRL_BAND_14MHZ << 8)     /**< Shifted mode 14MHZ for CMU_AUXHFRCOCTRL */
-#define CMU_AUXHFRCOCTRL_BAND_11MHZ                 (_CMU_AUXHFRCOCTRL_BAND_11MHZ << 8)     /**< Shifted mode 11MHZ for CMU_AUXHFRCOCTRL */
-#define CMU_AUXHFRCOCTRL_BAND_7MHZ                  (_CMU_AUXHFRCOCTRL_BAND_7MHZ << 8)      /**< Shifted mode 7MHZ for CMU_AUXHFRCOCTRL */
-#define CMU_AUXHFRCOCTRL_BAND_1MHZ                  (_CMU_AUXHFRCOCTRL_BAND_1MHZ << 8)      /**< Shifted mode 1MHZ for CMU_AUXHFRCOCTRL */
-#define CMU_AUXHFRCOCTRL_BAND_28MHZ                 (_CMU_AUXHFRCOCTRL_BAND_28MHZ << 8)     /**< Shifted mode 28MHZ for CMU_AUXHFRCOCTRL */
-#define CMU_AUXHFRCOCTRL_BAND_21MHZ                 (_CMU_AUXHFRCOCTRL_BAND_21MHZ << 8)     /**< Shifted mode 21MHZ for CMU_AUXHFRCOCTRL */
-
-/* Bit fields for CMU CALCTRL */
-#define _CMU_CALCTRL_RESETVALUE                     0x00000000UL                         /**< Default value for CMU_CALCTRL */
-#define _CMU_CALCTRL_MASK                           0x0000007FUL                         /**< Mask for CMU_CALCTRL */
-#define _CMU_CALCTRL_UPSEL_SHIFT                    0                                    /**< Shift value for CMU_UPSEL */
-#define _CMU_CALCTRL_UPSEL_MASK                     0x7UL                                /**< Bit mask for CMU_UPSEL */
-#define _CMU_CALCTRL_UPSEL_DEFAULT                  0x00000000UL                         /**< Mode DEFAULT for CMU_CALCTRL */
-#define _CMU_CALCTRL_UPSEL_HFXO                     0x00000000UL                         /**< Mode HFXO for CMU_CALCTRL */
-#define _CMU_CALCTRL_UPSEL_LFXO                     0x00000001UL                         /**< Mode LFXO for CMU_CALCTRL */
-#define _CMU_CALCTRL_UPSEL_HFRCO                    0x00000002UL                         /**< Mode HFRCO for CMU_CALCTRL */
-#define _CMU_CALCTRL_UPSEL_LFRCO                    0x00000003UL                         /**< Mode LFRCO for CMU_CALCTRL */
-#define _CMU_CALCTRL_UPSEL_AUXHFRCO                 0x00000004UL                         /**< Mode AUXHFRCO for CMU_CALCTRL */
-#define CMU_CALCTRL_UPSEL_DEFAULT                   (_CMU_CALCTRL_UPSEL_DEFAULT << 0)    /**< Shifted mode DEFAULT for CMU_CALCTRL */
-#define CMU_CALCTRL_UPSEL_HFXO                      (_CMU_CALCTRL_UPSEL_HFXO << 0)       /**< Shifted mode HFXO for CMU_CALCTRL */
-#define CMU_CALCTRL_UPSEL_LFXO                      (_CMU_CALCTRL_UPSEL_LFXO << 0)       /**< Shifted mode LFXO for CMU_CALCTRL */
-#define CMU_CALCTRL_UPSEL_HFRCO                     (_CMU_CALCTRL_UPSEL_HFRCO << 0)      /**< Shifted mode HFRCO for CMU_CALCTRL */
-#define CMU_CALCTRL_UPSEL_LFRCO                     (_CMU_CALCTRL_UPSEL_LFRCO << 0)      /**< Shifted mode LFRCO for CMU_CALCTRL */
-#define CMU_CALCTRL_UPSEL_AUXHFRCO                  (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0)   /**< Shifted mode AUXHFRCO for CMU_CALCTRL */
-#define _CMU_CALCTRL_DOWNSEL_SHIFT                  3                                    /**< Shift value for CMU_DOWNSEL */
-#define _CMU_CALCTRL_DOWNSEL_MASK                   0x38UL                               /**< Bit mask for CMU_DOWNSEL */
-#define _CMU_CALCTRL_DOWNSEL_DEFAULT                0x00000000UL                         /**< Mode DEFAULT for CMU_CALCTRL */
-#define _CMU_CALCTRL_DOWNSEL_HFCLK                  0x00000000UL                         /**< Mode HFCLK for CMU_CALCTRL */
-#define _CMU_CALCTRL_DOWNSEL_HFXO                   0x00000001UL                         /**< Mode HFXO for CMU_CALCTRL */
-#define _CMU_CALCTRL_DOWNSEL_LFXO                   0x00000002UL                         /**< Mode LFXO for CMU_CALCTRL */
-#define _CMU_CALCTRL_DOWNSEL_HFRCO                  0x00000003UL                         /**< Mode HFRCO for CMU_CALCTRL */
-#define _CMU_CALCTRL_DOWNSEL_LFRCO                  0x00000004UL                         /**< Mode LFRCO for CMU_CALCTRL */
-#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO               0x00000005UL                         /**< Mode AUXHFRCO for CMU_CALCTRL */
-#define CMU_CALCTRL_DOWNSEL_DEFAULT                 (_CMU_CALCTRL_DOWNSEL_DEFAULT << 3)  /**< Shifted mode DEFAULT for CMU_CALCTRL */
-#define CMU_CALCTRL_DOWNSEL_HFCLK                   (_CMU_CALCTRL_DOWNSEL_HFCLK << 3)    /**< Shifted mode HFCLK for CMU_CALCTRL */
-#define CMU_CALCTRL_DOWNSEL_HFXO                    (_CMU_CALCTRL_DOWNSEL_HFXO << 3)     /**< Shifted mode HFXO for CMU_CALCTRL */
-#define CMU_CALCTRL_DOWNSEL_LFXO                    (_CMU_CALCTRL_DOWNSEL_LFXO << 3)     /**< Shifted mode LFXO for CMU_CALCTRL */
-#define CMU_CALCTRL_DOWNSEL_HFRCO                   (_CMU_CALCTRL_DOWNSEL_HFRCO << 3)    /**< Shifted mode HFRCO for CMU_CALCTRL */
-#define CMU_CALCTRL_DOWNSEL_LFRCO                   (_CMU_CALCTRL_DOWNSEL_LFRCO << 3)    /**< Shifted mode LFRCO for CMU_CALCTRL */
-#define CMU_CALCTRL_DOWNSEL_AUXHFRCO                (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 3) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */
-#define CMU_CALCTRL_CONT                            (0x1UL << 6)                         /**< Continuous Calibration */
-#define _CMU_CALCTRL_CONT_SHIFT                     6                                    /**< Shift value for CMU_CONT */
-#define _CMU_CALCTRL_CONT_MASK                      0x40UL                               /**< Bit mask for CMU_CONT */
-#define _CMU_CALCTRL_CONT_DEFAULT                   0x00000000UL                         /**< Mode DEFAULT for CMU_CALCTRL */
-#define CMU_CALCTRL_CONT_DEFAULT                    (_CMU_CALCTRL_CONT_DEFAULT << 6)     /**< Shifted mode DEFAULT for CMU_CALCTRL */
-
-/* Bit fields for CMU CALCNT */
-#define _CMU_CALCNT_RESETVALUE                      0x00000000UL                      /**< Default value for CMU_CALCNT */
-#define _CMU_CALCNT_MASK                            0x000FFFFFUL                      /**< Mask for CMU_CALCNT */
-#define _CMU_CALCNT_CALCNT_SHIFT                    0                                 /**< Shift value for CMU_CALCNT */
-#define _CMU_CALCNT_CALCNT_MASK                     0xFFFFFUL                         /**< Bit mask for CMU_CALCNT */
-#define _CMU_CALCNT_CALCNT_DEFAULT                  0x00000000UL                      /**< Mode DEFAULT for CMU_CALCNT */
-#define CMU_CALCNT_CALCNT_DEFAULT                   (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */
-
-/* Bit fields for CMU OSCENCMD */
-#define _CMU_OSCENCMD_RESETVALUE                    0x00000000UL                             /**< Default value for CMU_OSCENCMD */
-#define _CMU_OSCENCMD_MASK                          0x000003FFUL                             /**< Mask for CMU_OSCENCMD */
-#define CMU_OSCENCMD_HFRCOEN                        (0x1UL << 0)                             /**< HFRCO Enable */
-#define _CMU_OSCENCMD_HFRCOEN_SHIFT                 0                                        /**< Shift value for CMU_HFRCOEN */
-#define _CMU_OSCENCMD_HFRCOEN_MASK                  0x1UL                                    /**< Bit mask for CMU_HFRCOEN */
-#define _CMU_OSCENCMD_HFRCOEN_DEFAULT               0x00000000UL                             /**< Mode DEFAULT for CMU_OSCENCMD */
-#define CMU_OSCENCMD_HFRCOEN_DEFAULT                (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0)     /**< Shifted mode DEFAULT for CMU_OSCENCMD */
-#define CMU_OSCENCMD_HFRCODIS                       (0x1UL << 1)                             /**< HFRCO Disable */
-#define _CMU_OSCENCMD_HFRCODIS_SHIFT                1                                        /**< Shift value for CMU_HFRCODIS */
-#define _CMU_OSCENCMD_HFRCODIS_MASK                 0x2UL                                    /**< Bit mask for CMU_HFRCODIS */
-#define _CMU_OSCENCMD_HFRCODIS_DEFAULT              0x00000000UL                             /**< Mode DEFAULT for CMU_OSCENCMD */
-#define CMU_OSCENCMD_HFRCODIS_DEFAULT               (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1)    /**< Shifted mode DEFAULT for CMU_OSCENCMD */
-#define CMU_OSCENCMD_HFXOEN                         (0x1UL << 2)                             /**< HFXO Enable */
-#define _CMU_OSCENCMD_HFXOEN_SHIFT                  2                                        /**< Shift value for CMU_HFXOEN */
-#define _CMU_OSCENCMD_HFXOEN_MASK                   0x4UL                                    /**< Bit mask for CMU_HFXOEN */
-#define _CMU_OSCENCMD_HFXOEN_DEFAULT                0x00000000UL                             /**< Mode DEFAULT for CMU_OSCENCMD */
-#define CMU_OSCENCMD_HFXOEN_DEFAULT                 (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2)      /**< Shifted mode DEFAULT for CMU_OSCENCMD */
-#define CMU_OSCENCMD_HFXODIS                        (0x1UL << 3)                             /**< HFXO Disable */
-#define _CMU_OSCENCMD_HFXODIS_SHIFT                 3                                        /**< Shift value for CMU_HFXODIS */
-#define _CMU_OSCENCMD_HFXODIS_MASK                  0x8UL                                    /**< Bit mask for CMU_HFXODIS */
-#define _CMU_OSCENCMD_HFXODIS_DEFAULT               0x00000000UL                             /**< Mode DEFAULT for CMU_OSCENCMD */
-#define CMU_OSCENCMD_HFXODIS_DEFAULT                (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3)     /**< Shifted mode DEFAULT for CMU_OSCENCMD */
-#define CMU_OSCENCMD_AUXHFRCOEN                     (0x1UL << 4)                             /**< AUXHFRCO Enable */
-#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT              4                                        /**< Shift value for CMU_AUXHFRCOEN */
-#define _CMU_OSCENCMD_AUXHFRCOEN_MASK               0x10UL                                   /**< Bit mask for CMU_AUXHFRCOEN */
-#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT            0x00000000UL                             /**< Mode DEFAULT for CMU_OSCENCMD */
-#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT             (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4)  /**< Shifted mode DEFAULT for CMU_OSCENCMD */
-#define CMU_OSCENCMD_AUXHFRCODIS                    (0x1UL << 5)                             /**< AUXHFRCO Disable */
-#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT             5                                        /**< Shift value for CMU_AUXHFRCODIS */
-#define _CMU_OSCENCMD_AUXHFRCODIS_MASK              0x20UL                                   /**< Bit mask for CMU_AUXHFRCODIS */
-#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT           0x00000000UL                             /**< Mode DEFAULT for CMU_OSCENCMD */
-#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT            (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
-#define CMU_OSCENCMD_LFRCOEN                        (0x1UL << 6)                             /**< LFRCO Enable */
-#define _CMU_OSCENCMD_LFRCOEN_SHIFT                 6                                        /**< Shift value for CMU_LFRCOEN */
-#define _CMU_OSCENCMD_LFRCOEN_MASK                  0x40UL                                   /**< Bit mask for CMU_LFRCOEN */
-#define _CMU_OSCENCMD_LFRCOEN_DEFAULT               0x00000000UL                             /**< Mode DEFAULT for CMU_OSCENCMD */
-#define CMU_OSCENCMD_LFRCOEN_DEFAULT                (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6)     /**< Shifted mode DEFAULT for CMU_OSCENCMD */
-#define CMU_OSCENCMD_LFRCODIS                       (0x1UL << 7)                             /**< LFRCO Disable */
-#define _CMU_OSCENCMD_LFRCODIS_SHIFT                7                                        /**< Shift value for CMU_LFRCODIS */
-#define _CMU_OSCENCMD_LFRCODIS_MASK                 0x80UL                                   /**< Bit mask for CMU_LFRCODIS */
-#define _CMU_OSCENCMD_LFRCODIS_DEFAULT              0x00000000UL                             /**< Mode DEFAULT for CMU_OSCENCMD */
-#define CMU_OSCENCMD_LFRCODIS_DEFAULT               (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7)    /**< Shifted mode DEFAULT for CMU_OSCENCMD */
-#define CMU_OSCENCMD_LFXOEN                         (0x1UL << 8)                             /**< LFXO Enable */
-#define _CMU_OSCENCMD_LFXOEN_SHIFT                  8                                        /**< Shift value for CMU_LFXOEN */
-#define _CMU_OSCENCMD_LFXOEN_MASK                   0x100UL                                  /**< Bit mask for CMU_LFXOEN */
-#define _CMU_OSCENCMD_LFXOEN_DEFAULT                0x00000000UL                             /**< Mode DEFAULT for CMU_OSCENCMD */
-#define CMU_OSCENCMD_LFXOEN_DEFAULT                 (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8)      /**< Shifted mode DEFAULT for CMU_OSCENCMD */
-#define CMU_OSCENCMD_LFXODIS                        (0x1UL << 9)                             /**< LFXO Disable */
-#define _CMU_OSCENCMD_LFXODIS_SHIFT                 9                                        /**< Shift value for CMU_LFXODIS */
-#define _CMU_OSCENCMD_LFXODIS_MASK                  0x200UL                                  /**< Bit mask for CMU_LFXODIS */
-#define _CMU_OSCENCMD_LFXODIS_DEFAULT               0x00000000UL                             /**< Mode DEFAULT for CMU_OSCENCMD */
-#define CMU_OSCENCMD_LFXODIS_DEFAULT                (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9)     /**< Shifted mode DEFAULT for CMU_OSCENCMD */
-
-/* Bit fields for CMU CMD */
-#define _CMU_CMD_RESETVALUE                         0x00000000UL                          /**< Default value for CMU_CMD */
-#define _CMU_CMD_MASK                               0x0000007FUL                          /**< Mask for CMU_CMD */
-#define _CMU_CMD_HFCLKSEL_SHIFT                     0                                     /**< Shift value for CMU_HFCLKSEL */
-#define _CMU_CMD_HFCLKSEL_MASK                      0x7UL                                 /**< Bit mask for CMU_HFCLKSEL */
-#define _CMU_CMD_HFCLKSEL_DEFAULT                   0x00000000UL                          /**< Mode DEFAULT for CMU_CMD */
-#define _CMU_CMD_HFCLKSEL_HFRCO                     0x00000001UL                          /**< Mode HFRCO for CMU_CMD */
-#define _CMU_CMD_HFCLKSEL_HFXO                      0x00000002UL                          /**< Mode HFXO for CMU_CMD */
-#define _CMU_CMD_HFCLKSEL_LFRCO                     0x00000003UL                          /**< Mode LFRCO for CMU_CMD */
-#define _CMU_CMD_HFCLKSEL_LFXO                      0x00000004UL                          /**< Mode LFXO for CMU_CMD */
-#define CMU_CMD_HFCLKSEL_DEFAULT                    (_CMU_CMD_HFCLKSEL_DEFAULT << 0)      /**< Shifted mode DEFAULT for CMU_CMD */
-#define CMU_CMD_HFCLKSEL_HFRCO                      (_CMU_CMD_HFCLKSEL_HFRCO << 0)        /**< Shifted mode HFRCO for CMU_CMD */
-#define CMU_CMD_HFCLKSEL_HFXO                       (_CMU_CMD_HFCLKSEL_HFXO << 0)         /**< Shifted mode HFXO for CMU_CMD */
-#define CMU_CMD_HFCLKSEL_LFRCO                      (_CMU_CMD_HFCLKSEL_LFRCO << 0)        /**< Shifted mode LFRCO for CMU_CMD */
-#define CMU_CMD_HFCLKSEL_LFXO                       (_CMU_CMD_HFCLKSEL_LFXO << 0)         /**< Shifted mode LFXO for CMU_CMD */
-#define CMU_CMD_CALSTART                            (0x1UL << 3)                          /**< Calibration Start */
-#define _CMU_CMD_CALSTART_SHIFT                     3                                     /**< Shift value for CMU_CALSTART */
-#define _CMU_CMD_CALSTART_MASK                      0x8UL                                 /**< Bit mask for CMU_CALSTART */
-#define _CMU_CMD_CALSTART_DEFAULT                   0x00000000UL                          /**< Mode DEFAULT for CMU_CMD */
-#define CMU_CMD_CALSTART_DEFAULT                    (_CMU_CMD_CALSTART_DEFAULT << 3)      /**< Shifted mode DEFAULT for CMU_CMD */
-#define CMU_CMD_CALSTOP                             (0x1UL << 4)                          /**< Calibration Stop */
-#define _CMU_CMD_CALSTOP_SHIFT                      4                                     /**< Shift value for CMU_CALSTOP */
-#define _CMU_CMD_CALSTOP_MASK                       0x10UL                                /**< Bit mask for CMU_CALSTOP */
-#define _CMU_CMD_CALSTOP_DEFAULT                    0x00000000UL                          /**< Mode DEFAULT for CMU_CMD */
-#define CMU_CMD_CALSTOP_DEFAULT                     (_CMU_CMD_CALSTOP_DEFAULT << 4)       /**< Shifted mode DEFAULT for CMU_CMD */
-#define _CMU_CMD_USBCCLKSEL_SHIFT                   5                                     /**< Shift value for CMU_USBCCLKSEL */
-#define _CMU_CMD_USBCCLKSEL_MASK                    0x60UL                                /**< Bit mask for CMU_USBCCLKSEL */
-#define _CMU_CMD_USBCCLKSEL_DEFAULT                 0x00000000UL                          /**< Mode DEFAULT for CMU_CMD */
-#define _CMU_CMD_USBCCLKSEL_HFCLKNODIV              0x00000001UL                          /**< Mode HFCLKNODIV for CMU_CMD */
-#define _CMU_CMD_USBCCLKSEL_LFXO                    0x00000002UL                          /**< Mode LFXO for CMU_CMD */
-#define _CMU_CMD_USBCCLKSEL_LFRCO                   0x00000003UL                          /**< Mode LFRCO for CMU_CMD */
-#define CMU_CMD_USBCCLKSEL_DEFAULT                  (_CMU_CMD_USBCCLKSEL_DEFAULT << 5)    /**< Shifted mode DEFAULT for CMU_CMD */
-#define CMU_CMD_USBCCLKSEL_HFCLKNODIV               (_CMU_CMD_USBCCLKSEL_HFCLKNODIV << 5) /**< Shifted mode HFCLKNODIV for CMU_CMD */
-#define CMU_CMD_USBCCLKSEL_LFXO                     (_CMU_CMD_USBCCLKSEL_LFXO << 5)       /**< Shifted mode LFXO for CMU_CMD */
-#define CMU_CMD_USBCCLKSEL_LFRCO                    (_CMU_CMD_USBCCLKSEL_LFRCO << 5)      /**< Shifted mode LFRCO for CMU_CMD */
-
-/* Bit fields for CMU LFCLKSEL */
-#define _CMU_LFCLKSEL_RESETVALUE                    0x00000005UL                             /**< Default value for CMU_LFCLKSEL */
-#define _CMU_LFCLKSEL_MASK                          0x0011000FUL                             /**< Mask for CMU_LFCLKSEL */
-#define _CMU_LFCLKSEL_LFA_SHIFT                     0                                        /**< Shift value for CMU_LFA */
-#define _CMU_LFCLKSEL_LFA_MASK                      0x3UL                                    /**< Bit mask for CMU_LFA */
-#define _CMU_LFCLKSEL_LFA_DISABLED                  0x00000000UL                             /**< Mode DISABLED for CMU_LFCLKSEL */
-#define _CMU_LFCLKSEL_LFA_DEFAULT                   0x00000001UL                             /**< Mode DEFAULT for CMU_LFCLKSEL */
-#define _CMU_LFCLKSEL_LFA_LFRCO                     0x00000001UL                             /**< Mode LFRCO for CMU_LFCLKSEL */
-#define _CMU_LFCLKSEL_LFA_LFXO                      0x00000002UL                             /**< Mode LFXO for CMU_LFCLKSEL */
-#define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2           0x00000003UL                             /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */
-#define CMU_LFCLKSEL_LFA_DISABLED                   (_CMU_LFCLKSEL_LFA_DISABLED << 0)        /**< Shifted mode DISABLED for CMU_LFCLKSEL */
-#define CMU_LFCLKSEL_LFA_DEFAULT                    (_CMU_LFCLKSEL_LFA_DEFAULT << 0)         /**< Shifted mode DEFAULT for CMU_LFCLKSEL */
-#define CMU_LFCLKSEL_LFA_LFRCO                      (_CMU_LFCLKSEL_LFA_LFRCO << 0)           /**< Shifted mode LFRCO for CMU_LFCLKSEL */
-#define CMU_LFCLKSEL_LFA_LFXO                       (_CMU_LFCLKSEL_LFA_LFXO << 0)            /**< Shifted mode LFXO for CMU_LFCLKSEL */
-#define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2            (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */
-#define _CMU_LFCLKSEL_LFB_SHIFT                     2                                        /**< Shift value for CMU_LFB */
-#define _CMU_LFCLKSEL_LFB_MASK                      0xCUL                                    /**< Bit mask for CMU_LFB */
-#define _CMU_LFCLKSEL_LFB_DISABLED                  0x00000000UL                             /**< Mode DISABLED for CMU_LFCLKSEL */
-#define _CMU_LFCLKSEL_LFB_DEFAULT                   0x00000001UL                             /**< Mode DEFAULT for CMU_LFCLKSEL */
-#define _CMU_LFCLKSEL_LFB_LFRCO                     0x00000001UL                             /**< Mode LFRCO for CMU_LFCLKSEL */
-#define _CMU_LFCLKSEL_LFB_LFXO                      0x00000002UL                             /**< Mode LFXO for CMU_LFCLKSEL */
-#define _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2           0x00000003UL                             /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */
-#define CMU_LFCLKSEL_LFB_DISABLED                   (_CMU_LFCLKSEL_LFB_DISABLED << 2)        /**< Shifted mode DISABLED for CMU_LFCLKSEL */
-#define CMU_LFCLKSEL_LFB_DEFAULT                    (_CMU_LFCLKSEL_LFB_DEFAULT << 2)         /**< Shifted mode DEFAULT for CMU_LFCLKSEL */
-#define CMU_LFCLKSEL_LFB_LFRCO                      (_CMU_LFCLKSEL_LFB_LFRCO << 2)           /**< Shifted mode LFRCO for CMU_LFCLKSEL */
-#define CMU_LFCLKSEL_LFB_LFXO                       (_CMU_LFCLKSEL_LFB_LFXO << 2)            /**< Shifted mode LFXO for CMU_LFCLKSEL */
-#define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2            (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */
-#define CMU_LFCLKSEL_LFAE                           (0x1UL << 16)                            /**< Clock Select for LFA Extended */
-#define _CMU_LFCLKSEL_LFAE_SHIFT                    16                                       /**< Shift value for CMU_LFAE */
-#define _CMU_LFCLKSEL_LFAE_MASK                     0x10000UL                                /**< Bit mask for CMU_LFAE */
-#define _CMU_LFCLKSEL_LFAE_DEFAULT                  0x00000000UL                             /**< Mode DEFAULT for CMU_LFCLKSEL */
-#define _CMU_LFCLKSEL_LFAE_DISABLED                 0x00000000UL                             /**< Mode DISABLED for CMU_LFCLKSEL */
-#define _CMU_LFCLKSEL_LFAE_ULFRCO                   0x00000001UL                             /**< Mode ULFRCO for CMU_LFCLKSEL */
-#define CMU_LFCLKSEL_LFAE_DEFAULT                   (_CMU_LFCLKSEL_LFAE_DEFAULT << 16)       /**< Shifted mode DEFAULT for CMU_LFCLKSEL */
-#define CMU_LFCLKSEL_LFAE_DISABLED                  (_CMU_LFCLKSEL_LFAE_DISABLED << 16)      /**< Shifted mode DISABLED for CMU_LFCLKSEL */
-#define CMU_LFCLKSEL_LFAE_ULFRCO                    (_CMU_LFCLKSEL_LFAE_ULFRCO << 16)        /**< Shifted mode ULFRCO for CMU_LFCLKSEL */
-#define CMU_LFCLKSEL_LFBE                           (0x1UL << 20)                            /**< Clock Select for LFB Extended */
-#define _CMU_LFCLKSEL_LFBE_SHIFT                    20                                       /**< Shift value for CMU_LFBE */
-#define _CMU_LFCLKSEL_LFBE_MASK                     0x100000UL                               /**< Bit mask for CMU_LFBE */
-#define _CMU_LFCLKSEL_LFBE_DEFAULT                  0x00000000UL                             /**< Mode DEFAULT for CMU_LFCLKSEL */
-#define _CMU_LFCLKSEL_LFBE_DISABLED                 0x00000000UL                             /**< Mode DISABLED for CMU_LFCLKSEL */
-#define _CMU_LFCLKSEL_LFBE_ULFRCO                   0x00000001UL                             /**< Mode ULFRCO for CMU_LFCLKSEL */
-#define CMU_LFCLKSEL_LFBE_DEFAULT                   (_CMU_LFCLKSEL_LFBE_DEFAULT << 20)       /**< Shifted mode DEFAULT for CMU_LFCLKSEL */
-#define CMU_LFCLKSEL_LFBE_DISABLED                  (_CMU_LFCLKSEL_LFBE_DISABLED << 20)      /**< Shifted mode DISABLED for CMU_LFCLKSEL */
-#define CMU_LFCLKSEL_LFBE_ULFRCO                    (_CMU_LFCLKSEL_LFBE_ULFRCO << 20)        /**< Shifted mode ULFRCO for CMU_LFCLKSEL */
-
-/* Bit fields for CMU STATUS */
-#define _CMU_STATUS_RESETVALUE                      0x00000403UL                             /**< Default value for CMU_STATUS */
-#define _CMU_STATUS_MASK                            0x0003FFFFUL                             /**< Mask for CMU_STATUS */
-#define CMU_STATUS_HFRCOENS                         (0x1UL << 0)                             /**< HFRCO Enable Status */
-#define _CMU_STATUS_HFRCOENS_SHIFT                  0                                        /**< Shift value for CMU_HFRCOENS */
-#define _CMU_STATUS_HFRCOENS_MASK                   0x1UL                                    /**< Bit mask for CMU_HFRCOENS */
-#define _CMU_STATUS_HFRCOENS_DEFAULT                0x00000001UL                             /**< Mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_HFRCOENS_DEFAULT                 (_CMU_STATUS_HFRCOENS_DEFAULT << 0)      /**< Shifted mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_HFRCORDY                         (0x1UL << 1)                             /**< HFRCO Ready */
-#define _CMU_STATUS_HFRCORDY_SHIFT                  1                                        /**< Shift value for CMU_HFRCORDY */
-#define _CMU_STATUS_HFRCORDY_MASK                   0x2UL                                    /**< Bit mask for CMU_HFRCORDY */
-#define _CMU_STATUS_HFRCORDY_DEFAULT                0x00000001UL                             /**< Mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_HFRCORDY_DEFAULT                 (_CMU_STATUS_HFRCORDY_DEFAULT << 1)      /**< Shifted mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_HFXOENS                          (0x1UL << 2)                             /**< HFXO Enable Status */
-#define _CMU_STATUS_HFXOENS_SHIFT                   2                                        /**< Shift value for CMU_HFXOENS */
-#define _CMU_STATUS_HFXOENS_MASK                    0x4UL                                    /**< Bit mask for CMU_HFXOENS */
-#define _CMU_STATUS_HFXOENS_DEFAULT                 0x00000000UL                             /**< Mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_HFXOENS_DEFAULT                  (_CMU_STATUS_HFXOENS_DEFAULT << 2)       /**< Shifted mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_HFXORDY                          (0x1UL << 3)                             /**< HFXO Ready */
-#define _CMU_STATUS_HFXORDY_SHIFT                   3                                        /**< Shift value for CMU_HFXORDY */
-#define _CMU_STATUS_HFXORDY_MASK                    0x8UL                                    /**< Bit mask for CMU_HFXORDY */
-#define _CMU_STATUS_HFXORDY_DEFAULT                 0x00000000UL                             /**< Mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_HFXORDY_DEFAULT                  (_CMU_STATUS_HFXORDY_DEFAULT << 3)       /**< Shifted mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_AUXHFRCOENS                      (0x1UL << 4)                             /**< AUXHFRCO Enable Status */
-#define _CMU_STATUS_AUXHFRCOENS_SHIFT               4                                        /**< Shift value for CMU_AUXHFRCOENS */
-#define _CMU_STATUS_AUXHFRCOENS_MASK                0x10UL                                   /**< Bit mask for CMU_AUXHFRCOENS */
-#define _CMU_STATUS_AUXHFRCOENS_DEFAULT             0x00000000UL                             /**< Mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_AUXHFRCOENS_DEFAULT              (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4)   /**< Shifted mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_AUXHFRCORDY                      (0x1UL << 5)                             /**< AUXHFRCO Ready */
-#define _CMU_STATUS_AUXHFRCORDY_SHIFT               5                                        /**< Shift value for CMU_AUXHFRCORDY */
-#define _CMU_STATUS_AUXHFRCORDY_MASK                0x20UL                                   /**< Bit mask for CMU_AUXHFRCORDY */
-#define _CMU_STATUS_AUXHFRCORDY_DEFAULT             0x00000000UL                             /**< Mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_AUXHFRCORDY_DEFAULT              (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5)   /**< Shifted mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_LFRCOENS                         (0x1UL << 6)                             /**< LFRCO Enable Status */
-#define _CMU_STATUS_LFRCOENS_SHIFT                  6                                        /**< Shift value for CMU_LFRCOENS */
-#define _CMU_STATUS_LFRCOENS_MASK                   0x40UL                                   /**< Bit mask for CMU_LFRCOENS */
-#define _CMU_STATUS_LFRCOENS_DEFAULT                0x00000000UL                             /**< Mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_LFRCOENS_DEFAULT                 (_CMU_STATUS_LFRCOENS_DEFAULT << 6)      /**< Shifted mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_LFRCORDY                         (0x1UL << 7)                             /**< LFRCO Ready */
-#define _CMU_STATUS_LFRCORDY_SHIFT                  7                                        /**< Shift value for CMU_LFRCORDY */
-#define _CMU_STATUS_LFRCORDY_MASK                   0x80UL                                   /**< Bit mask for CMU_LFRCORDY */
-#define _CMU_STATUS_LFRCORDY_DEFAULT                0x00000000UL                             /**< Mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_LFRCORDY_DEFAULT                 (_CMU_STATUS_LFRCORDY_DEFAULT << 7)      /**< Shifted mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_LFXOENS                          (0x1UL << 8)                             /**< LFXO Enable Status */
-#define _CMU_STATUS_LFXOENS_SHIFT                   8                                        /**< Shift value for CMU_LFXOENS */
-#define _CMU_STATUS_LFXOENS_MASK                    0x100UL                                  /**< Bit mask for CMU_LFXOENS */
-#define _CMU_STATUS_LFXOENS_DEFAULT                 0x00000000UL                             /**< Mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_LFXOENS_DEFAULT                  (_CMU_STATUS_LFXOENS_DEFAULT << 8)       /**< Shifted mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_LFXORDY                          (0x1UL << 9)                             /**< LFXO Ready */
-#define _CMU_STATUS_LFXORDY_SHIFT                   9                                        /**< Shift value for CMU_LFXORDY */
-#define _CMU_STATUS_LFXORDY_MASK                    0x200UL                                  /**< Bit mask for CMU_LFXORDY */
-#define _CMU_STATUS_LFXORDY_DEFAULT                 0x00000000UL                             /**< Mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_LFXORDY_DEFAULT                  (_CMU_STATUS_LFXORDY_DEFAULT << 9)       /**< Shifted mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_HFRCOSEL                         (0x1UL << 10)                            /**< HFRCO Selected */
-#define _CMU_STATUS_HFRCOSEL_SHIFT                  10                                       /**< Shift value for CMU_HFRCOSEL */
-#define _CMU_STATUS_HFRCOSEL_MASK                   0x400UL                                  /**< Bit mask for CMU_HFRCOSEL */
-#define _CMU_STATUS_HFRCOSEL_DEFAULT                0x00000001UL                             /**< Mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_HFRCOSEL_DEFAULT                 (_CMU_STATUS_HFRCOSEL_DEFAULT << 10)     /**< Shifted mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_HFXOSEL                          (0x1UL << 11)                            /**< HFXO Selected */
-#define _CMU_STATUS_HFXOSEL_SHIFT                   11                                       /**< Shift value for CMU_HFXOSEL */
-#define _CMU_STATUS_HFXOSEL_MASK                    0x800UL                                  /**< Bit mask for CMU_HFXOSEL */
-#define _CMU_STATUS_HFXOSEL_DEFAULT                 0x00000000UL                             /**< Mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_HFXOSEL_DEFAULT                  (_CMU_STATUS_HFXOSEL_DEFAULT << 11)      /**< Shifted mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_LFRCOSEL                         (0x1UL << 12)                            /**< LFRCO Selected */
-#define _CMU_STATUS_LFRCOSEL_SHIFT                  12                                       /**< Shift value for CMU_LFRCOSEL */
-#define _CMU_STATUS_LFRCOSEL_MASK                   0x1000UL                                 /**< Bit mask for CMU_LFRCOSEL */
-#define _CMU_STATUS_LFRCOSEL_DEFAULT                0x00000000UL                             /**< Mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_LFRCOSEL_DEFAULT                 (_CMU_STATUS_LFRCOSEL_DEFAULT << 12)     /**< Shifted mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_LFXOSEL                          (0x1UL << 13)                            /**< LFXO Selected */
-#define _CMU_STATUS_LFXOSEL_SHIFT                   13                                       /**< Shift value for CMU_LFXOSEL */
-#define _CMU_STATUS_LFXOSEL_MASK                    0x2000UL                                 /**< Bit mask for CMU_LFXOSEL */
-#define _CMU_STATUS_LFXOSEL_DEFAULT                 0x00000000UL                             /**< Mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_LFXOSEL_DEFAULT                  (_CMU_STATUS_LFXOSEL_DEFAULT << 13)      /**< Shifted mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_CALBSY                           (0x1UL << 14)                            /**< Calibration Busy */
-#define _CMU_STATUS_CALBSY_SHIFT                    14                                       /**< Shift value for CMU_CALBSY */
-#define _CMU_STATUS_CALBSY_MASK                     0x4000UL                                 /**< Bit mask for CMU_CALBSY */
-#define _CMU_STATUS_CALBSY_DEFAULT                  0x00000000UL                             /**< Mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_CALBSY_DEFAULT                   (_CMU_STATUS_CALBSY_DEFAULT << 14)       /**< Shifted mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_USBCHFCLKSEL                     (0x1UL << 15)                            /**< USBC HFCLK Selected */
-#define _CMU_STATUS_USBCHFCLKSEL_SHIFT              15                                       /**< Shift value for CMU_USBCHFCLKSEL */
-#define _CMU_STATUS_USBCHFCLKSEL_MASK               0x8000UL                                 /**< Bit mask for CMU_USBCHFCLKSEL */
-#define _CMU_STATUS_USBCHFCLKSEL_DEFAULT            0x00000000UL                             /**< Mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_USBCHFCLKSEL_DEFAULT             (_CMU_STATUS_USBCHFCLKSEL_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_USBCLFXOSEL                      (0x1UL << 16)                            /**< USBC LFXO Selected */
-#define _CMU_STATUS_USBCLFXOSEL_SHIFT               16                                       /**< Shift value for CMU_USBCLFXOSEL */
-#define _CMU_STATUS_USBCLFXOSEL_MASK                0x10000UL                                /**< Bit mask for CMU_USBCLFXOSEL */
-#define _CMU_STATUS_USBCLFXOSEL_DEFAULT             0x00000000UL                             /**< Mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_USBCLFXOSEL_DEFAULT              (_CMU_STATUS_USBCLFXOSEL_DEFAULT << 16)  /**< Shifted mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_USBCLFRCOSEL                     (0x1UL << 17)                            /**< USBC LFRCO Selected */
-#define _CMU_STATUS_USBCLFRCOSEL_SHIFT              17                                       /**< Shift value for CMU_USBCLFRCOSEL */
-#define _CMU_STATUS_USBCLFRCOSEL_MASK               0x20000UL                                /**< Bit mask for CMU_USBCLFRCOSEL */
-#define _CMU_STATUS_USBCLFRCOSEL_DEFAULT            0x00000000UL                             /**< Mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_USBCLFRCOSEL_DEFAULT             (_CMU_STATUS_USBCLFRCOSEL_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_STATUS */
-
-/* Bit fields for CMU IF */
-#define _CMU_IF_RESETVALUE                          0x00000001UL                        /**< Default value for CMU_IF */
-#define _CMU_IF_MASK                                0x000000FFUL                        /**< Mask for CMU_IF */
-#define CMU_IF_HFRCORDY                             (0x1UL << 0)                        /**< HFRCO Ready Interrupt Flag */
-#define _CMU_IF_HFRCORDY_SHIFT                      0                                   /**< Shift value for CMU_HFRCORDY */
-#define _CMU_IF_HFRCORDY_MASK                       0x1UL                               /**< Bit mask for CMU_HFRCORDY */
-#define _CMU_IF_HFRCORDY_DEFAULT                    0x00000001UL                        /**< Mode DEFAULT for CMU_IF */
-#define CMU_IF_HFRCORDY_DEFAULT                     (_CMU_IF_HFRCORDY_DEFAULT << 0)     /**< Shifted mode DEFAULT for CMU_IF */
-#define CMU_IF_HFXORDY                              (0x1UL << 1)                        /**< HFXO Ready Interrupt Flag */
-#define _CMU_IF_HFXORDY_SHIFT                       1                                   /**< Shift value for CMU_HFXORDY */
-#define _CMU_IF_HFXORDY_MASK                        0x2UL                               /**< Bit mask for CMU_HFXORDY */
-#define _CMU_IF_HFXORDY_DEFAULT                     0x00000000UL                        /**< Mode DEFAULT for CMU_IF */
-#define CMU_IF_HFXORDY_DEFAULT                      (_CMU_IF_HFXORDY_DEFAULT << 1)      /**< Shifted mode DEFAULT for CMU_IF */
-#define CMU_IF_LFRCORDY                             (0x1UL << 2)                        /**< LFRCO Ready Interrupt Flag */
-#define _CMU_IF_LFRCORDY_SHIFT                      2                                   /**< Shift value for CMU_LFRCORDY */
-#define _CMU_IF_LFRCORDY_MASK                       0x4UL                               /**< Bit mask for CMU_LFRCORDY */
-#define _CMU_IF_LFRCORDY_DEFAULT                    0x00000000UL                        /**< Mode DEFAULT for CMU_IF */
-#define CMU_IF_LFRCORDY_DEFAULT                     (_CMU_IF_LFRCORDY_DEFAULT << 2)     /**< Shifted mode DEFAULT for CMU_IF */
-#define CMU_IF_LFXORDY                              (0x1UL << 3)                        /**< LFXO Ready Interrupt Flag */
-#define _CMU_IF_LFXORDY_SHIFT                       3                                   /**< Shift value for CMU_LFXORDY */
-#define _CMU_IF_LFXORDY_MASK                        0x8UL                               /**< Bit mask for CMU_LFXORDY */
-#define _CMU_IF_LFXORDY_DEFAULT                     0x00000000UL                        /**< Mode DEFAULT for CMU_IF */
-#define CMU_IF_LFXORDY_DEFAULT                      (_CMU_IF_LFXORDY_DEFAULT << 3)      /**< Shifted mode DEFAULT for CMU_IF */
-#define CMU_IF_AUXHFRCORDY                          (0x1UL << 4)                        /**< AUXHFRCO Ready Interrupt Flag */
-#define _CMU_IF_AUXHFRCORDY_SHIFT                   4                                   /**< Shift value for CMU_AUXHFRCORDY */
-#define _CMU_IF_AUXHFRCORDY_MASK                    0x10UL                              /**< Bit mask for CMU_AUXHFRCORDY */
-#define _CMU_IF_AUXHFRCORDY_DEFAULT                 0x00000000UL                        /**< Mode DEFAULT for CMU_IF */
-#define CMU_IF_AUXHFRCORDY_DEFAULT                  (_CMU_IF_AUXHFRCORDY_DEFAULT << 4)  /**< Shifted mode DEFAULT for CMU_IF */
-#define CMU_IF_CALRDY                               (0x1UL << 5)                        /**< Calibration Ready Interrupt Flag */
-#define _CMU_IF_CALRDY_SHIFT                        5                                   /**< Shift value for CMU_CALRDY */
-#define _CMU_IF_CALRDY_MASK                         0x20UL                              /**< Bit mask for CMU_CALRDY */
-#define _CMU_IF_CALRDY_DEFAULT                      0x00000000UL                        /**< Mode DEFAULT for CMU_IF */
-#define CMU_IF_CALRDY_DEFAULT                       (_CMU_IF_CALRDY_DEFAULT << 5)       /**< Shifted mode DEFAULT for CMU_IF */
-#define CMU_IF_CALOF                                (0x1UL << 6)                        /**< Calibration Overflow Interrupt Flag */
-#define _CMU_IF_CALOF_SHIFT                         6                                   /**< Shift value for CMU_CALOF */
-#define _CMU_IF_CALOF_MASK                          0x40UL                              /**< Bit mask for CMU_CALOF */
-#define _CMU_IF_CALOF_DEFAULT                       0x00000000UL                        /**< Mode DEFAULT for CMU_IF */
-#define CMU_IF_CALOF_DEFAULT                        (_CMU_IF_CALOF_DEFAULT << 6)        /**< Shifted mode DEFAULT for CMU_IF */
-#define CMU_IF_USBCHFCLKSEL                         (0x1UL << 7)                        /**< USBC HFCLK Selected Interrupt Flag */
-#define _CMU_IF_USBCHFCLKSEL_SHIFT                  7                                   /**< Shift value for CMU_USBCHFCLKSEL */
-#define _CMU_IF_USBCHFCLKSEL_MASK                   0x80UL                              /**< Bit mask for CMU_USBCHFCLKSEL */
-#define _CMU_IF_USBCHFCLKSEL_DEFAULT                0x00000000UL                        /**< Mode DEFAULT for CMU_IF */
-#define CMU_IF_USBCHFCLKSEL_DEFAULT                 (_CMU_IF_USBCHFCLKSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IF */
-
-/* Bit fields for CMU IFS */
-#define _CMU_IFS_RESETVALUE                         0x00000000UL                         /**< Default value for CMU_IFS */
-#define _CMU_IFS_MASK                               0x000000FFUL                         /**< Mask for CMU_IFS */
-#define CMU_IFS_HFRCORDY                            (0x1UL << 0)                         /**< HFRCO Ready Interrupt Flag Set */
-#define _CMU_IFS_HFRCORDY_SHIFT                     0                                    /**< Shift value for CMU_HFRCORDY */
-#define _CMU_IFS_HFRCORDY_MASK                      0x1UL                                /**< Bit mask for CMU_HFRCORDY */
-#define _CMU_IFS_HFRCORDY_DEFAULT                   0x00000000UL                         /**< Mode DEFAULT for CMU_IFS */
-#define CMU_IFS_HFRCORDY_DEFAULT                    (_CMU_IFS_HFRCORDY_DEFAULT << 0)     /**< Shifted mode DEFAULT for CMU_IFS */
-#define CMU_IFS_HFXORDY                             (0x1UL << 1)                         /**< HFXO Ready Interrupt Flag Set */
-#define _CMU_IFS_HFXORDY_SHIFT                      1                                    /**< Shift value for CMU_HFXORDY */
-#define _CMU_IFS_HFXORDY_MASK                       0x2UL                                /**< Bit mask for CMU_HFXORDY */
-#define _CMU_IFS_HFXORDY_DEFAULT                    0x00000000UL                         /**< Mode DEFAULT for CMU_IFS */
-#define CMU_IFS_HFXORDY_DEFAULT                     (_CMU_IFS_HFXORDY_DEFAULT << 1)      /**< Shifted mode DEFAULT for CMU_IFS */
-#define CMU_IFS_LFRCORDY                            (0x1UL << 2)                         /**< LFRCO Ready Interrupt Flag Set */
-#define _CMU_IFS_LFRCORDY_SHIFT                     2                                    /**< Shift value for CMU_LFRCORDY */
-#define _CMU_IFS_LFRCORDY_MASK                      0x4UL                                /**< Bit mask for CMU_LFRCORDY */
-#define _CMU_IFS_LFRCORDY_DEFAULT                   0x00000000UL                         /**< Mode DEFAULT for CMU_IFS */
-#define CMU_IFS_LFRCORDY_DEFAULT                    (_CMU_IFS_LFRCORDY_DEFAULT << 2)     /**< Shifted mode DEFAULT for CMU_IFS */
-#define CMU_IFS_LFXORDY                             (0x1UL << 3)                         /**< LFXO Ready Interrupt Flag Set */
-#define _CMU_IFS_LFXORDY_SHIFT                      3                                    /**< Shift value for CMU_LFXORDY */
-#define _CMU_IFS_LFXORDY_MASK                       0x8UL                                /**< Bit mask for CMU_LFXORDY */
-#define _CMU_IFS_LFXORDY_DEFAULT                    0x00000000UL                         /**< Mode DEFAULT for CMU_IFS */
-#define CMU_IFS_LFXORDY_DEFAULT                     (_CMU_IFS_LFXORDY_DEFAULT << 3)      /**< Shifted mode DEFAULT for CMU_IFS */
-#define CMU_IFS_AUXHFRCORDY                         (0x1UL << 4)                         /**< AUXHFRCO Ready Interrupt Flag Set */
-#define _CMU_IFS_AUXHFRCORDY_SHIFT                  4                                    /**< Shift value for CMU_AUXHFRCORDY */
-#define _CMU_IFS_AUXHFRCORDY_MASK                   0x10UL                               /**< Bit mask for CMU_AUXHFRCORDY */
-#define _CMU_IFS_AUXHFRCORDY_DEFAULT                0x00000000UL                         /**< Mode DEFAULT for CMU_IFS */
-#define CMU_IFS_AUXHFRCORDY_DEFAULT                 (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4)  /**< Shifted mode DEFAULT for CMU_IFS */
-#define CMU_IFS_CALRDY                              (0x1UL << 5)                         /**< Calibration Ready Interrupt Flag Set */
-#define _CMU_IFS_CALRDY_SHIFT                       5                                    /**< Shift value for CMU_CALRDY */
-#define _CMU_IFS_CALRDY_MASK                        0x20UL                               /**< Bit mask for CMU_CALRDY */
-#define _CMU_IFS_CALRDY_DEFAULT                     0x00000000UL                         /**< Mode DEFAULT for CMU_IFS */
-#define CMU_IFS_CALRDY_DEFAULT                      (_CMU_IFS_CALRDY_DEFAULT << 5)       /**< Shifted mode DEFAULT for CMU_IFS */
-#define CMU_IFS_CALOF                               (0x1UL << 6)                         /**< Calibration Overflow Interrupt Flag Set */
-#define _CMU_IFS_CALOF_SHIFT                        6                                    /**< Shift value for CMU_CALOF */
-#define _CMU_IFS_CALOF_MASK                         0x40UL                               /**< Bit mask for CMU_CALOF */
-#define _CMU_IFS_CALOF_DEFAULT                      0x00000000UL                         /**< Mode DEFAULT for CMU_IFS */
-#define CMU_IFS_CALOF_DEFAULT                       (_CMU_IFS_CALOF_DEFAULT << 6)        /**< Shifted mode DEFAULT for CMU_IFS */
-#define CMU_IFS_USBCHFCLKSEL                        (0x1UL << 7)                         /**< USBC HFCLK Selected Interrupt Flag Set */
-#define _CMU_IFS_USBCHFCLKSEL_SHIFT                 7                                    /**< Shift value for CMU_USBCHFCLKSEL */
-#define _CMU_IFS_USBCHFCLKSEL_MASK                  0x80UL                               /**< Bit mask for CMU_USBCHFCLKSEL */
-#define _CMU_IFS_USBCHFCLKSEL_DEFAULT               0x00000000UL                         /**< Mode DEFAULT for CMU_IFS */
-#define CMU_IFS_USBCHFCLKSEL_DEFAULT                (_CMU_IFS_USBCHFCLKSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFS */
-
-/* Bit fields for CMU IFC */
-#define _CMU_IFC_RESETVALUE                         0x00000000UL                         /**< Default value for CMU_IFC */
-#define _CMU_IFC_MASK                               0x000000FFUL                         /**< Mask for CMU_IFC */
-#define CMU_IFC_HFRCORDY                            (0x1UL << 0)                         /**< HFRCO Ready Interrupt Flag Clear */
-#define _CMU_IFC_HFRCORDY_SHIFT                     0                                    /**< Shift value for CMU_HFRCORDY */
-#define _CMU_IFC_HFRCORDY_MASK                      0x1UL                                /**< Bit mask for CMU_HFRCORDY */
-#define _CMU_IFC_HFRCORDY_DEFAULT                   0x00000000UL                         /**< Mode DEFAULT for CMU_IFC */
-#define CMU_IFC_HFRCORDY_DEFAULT                    (_CMU_IFC_HFRCORDY_DEFAULT << 0)     /**< Shifted mode DEFAULT for CMU_IFC */
-#define CMU_IFC_HFXORDY                             (0x1UL << 1)                         /**< HFXO Ready Interrupt Flag Clear */
-#define _CMU_IFC_HFXORDY_SHIFT                      1                                    /**< Shift value for CMU_HFXORDY */
-#define _CMU_IFC_HFXORDY_MASK                       0x2UL                                /**< Bit mask for CMU_HFXORDY */
-#define _CMU_IFC_HFXORDY_DEFAULT                    0x00000000UL                         /**< Mode DEFAULT for CMU_IFC */
-#define CMU_IFC_HFXORDY_DEFAULT                     (_CMU_IFC_HFXORDY_DEFAULT << 1)      /**< Shifted mode DEFAULT for CMU_IFC */
-#define CMU_IFC_LFRCORDY                            (0x1UL << 2)                         /**< LFRCO Ready Interrupt Flag Clear */
-#define _CMU_IFC_LFRCORDY_SHIFT                     2                                    /**< Shift value for CMU_LFRCORDY */
-#define _CMU_IFC_LFRCORDY_MASK                      0x4UL                                /**< Bit mask for CMU_LFRCORDY */
-#define _CMU_IFC_LFRCORDY_DEFAULT                   0x00000000UL                         /**< Mode DEFAULT for CMU_IFC */
-#define CMU_IFC_LFRCORDY_DEFAULT                    (_CMU_IFC_LFRCORDY_DEFAULT << 2)     /**< Shifted mode DEFAULT for CMU_IFC */
-#define CMU_IFC_LFXORDY                             (0x1UL << 3)                         /**< LFXO Ready Interrupt Flag Clear */
-#define _CMU_IFC_LFXORDY_SHIFT                      3                                    /**< Shift value for CMU_LFXORDY */
-#define _CMU_IFC_LFXORDY_MASK                       0x8UL                                /**< Bit mask for CMU_LFXORDY */
-#define _CMU_IFC_LFXORDY_DEFAULT                    0x00000000UL                         /**< Mode DEFAULT for CMU_IFC */
-#define CMU_IFC_LFXORDY_DEFAULT                     (_CMU_IFC_LFXORDY_DEFAULT << 3)      /**< Shifted mode DEFAULT for CMU_IFC */
-#define CMU_IFC_AUXHFRCORDY                         (0x1UL << 4)                         /**< AUXHFRCO Ready Interrupt Flag Clear */
-#define _CMU_IFC_AUXHFRCORDY_SHIFT                  4                                    /**< Shift value for CMU_AUXHFRCORDY */
-#define _CMU_IFC_AUXHFRCORDY_MASK                   0x10UL                               /**< Bit mask for CMU_AUXHFRCORDY */
-#define _CMU_IFC_AUXHFRCORDY_DEFAULT                0x00000000UL                         /**< Mode DEFAULT for CMU_IFC */
-#define CMU_IFC_AUXHFRCORDY_DEFAULT                 (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4)  /**< Shifted mode DEFAULT for CMU_IFC */
-#define CMU_IFC_CALRDY                              (0x1UL << 5)                         /**< Calibration Ready Interrupt Flag Clear */
-#define _CMU_IFC_CALRDY_SHIFT                       5                                    /**< Shift value for CMU_CALRDY */
-#define _CMU_IFC_CALRDY_MASK                        0x20UL                               /**< Bit mask for CMU_CALRDY */
-#define _CMU_IFC_CALRDY_DEFAULT                     0x00000000UL                         /**< Mode DEFAULT for CMU_IFC */
-#define CMU_IFC_CALRDY_DEFAULT                      (_CMU_IFC_CALRDY_DEFAULT << 5)       /**< Shifted mode DEFAULT for CMU_IFC */
-#define CMU_IFC_CALOF                               (0x1UL << 6)                         /**< Calibration Overflow Interrupt Flag Clear */
-#define _CMU_IFC_CALOF_SHIFT                        6                                    /**< Shift value for CMU_CALOF */
-#define _CMU_IFC_CALOF_MASK                         0x40UL                               /**< Bit mask for CMU_CALOF */
-#define _CMU_IFC_CALOF_DEFAULT                      0x00000000UL                         /**< Mode DEFAULT for CMU_IFC */
-#define CMU_IFC_CALOF_DEFAULT                       (_CMU_IFC_CALOF_DEFAULT << 6)        /**< Shifted mode DEFAULT for CMU_IFC */
-#define CMU_IFC_USBCHFCLKSEL                        (0x1UL << 7)                         /**< USBC HFCLK Selected Interrupt Flag Clear */
-#define _CMU_IFC_USBCHFCLKSEL_SHIFT                 7                                    /**< Shift value for CMU_USBCHFCLKSEL */
-#define _CMU_IFC_USBCHFCLKSEL_MASK                  0x80UL                               /**< Bit mask for CMU_USBCHFCLKSEL */
-#define _CMU_IFC_USBCHFCLKSEL_DEFAULT               0x00000000UL                         /**< Mode DEFAULT for CMU_IFC */
-#define CMU_IFC_USBCHFCLKSEL_DEFAULT                (_CMU_IFC_USBCHFCLKSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFC */
-
-/* Bit fields for CMU IEN */
-#define _CMU_IEN_RESETVALUE                         0x00000000UL                         /**< Default value for CMU_IEN */
-#define _CMU_IEN_MASK                               0x000000FFUL                         /**< Mask for CMU_IEN */
-#define CMU_IEN_HFRCORDY                            (0x1UL << 0)                         /**< HFRCO Ready Interrupt Enable */
-#define _CMU_IEN_HFRCORDY_SHIFT                     0                                    /**< Shift value for CMU_HFRCORDY */
-#define _CMU_IEN_HFRCORDY_MASK                      0x1UL                                /**< Bit mask for CMU_HFRCORDY */
-#define _CMU_IEN_HFRCORDY_DEFAULT                   0x00000000UL                         /**< Mode DEFAULT for CMU_IEN */
-#define CMU_IEN_HFRCORDY_DEFAULT                    (_CMU_IEN_HFRCORDY_DEFAULT << 0)     /**< Shifted mode DEFAULT for CMU_IEN */
-#define CMU_IEN_HFXORDY                             (0x1UL << 1)                         /**< HFXO Ready Interrupt Enable */
-#define _CMU_IEN_HFXORDY_SHIFT                      1                                    /**< Shift value for CMU_HFXORDY */
-#define _CMU_IEN_HFXORDY_MASK                       0x2UL                                /**< Bit mask for CMU_HFXORDY */
-#define _CMU_IEN_HFXORDY_DEFAULT                    0x00000000UL                         /**< Mode DEFAULT for CMU_IEN */
-#define CMU_IEN_HFXORDY_DEFAULT                     (_CMU_IEN_HFXORDY_DEFAULT << 1)      /**< Shifted mode DEFAULT for CMU_IEN */
-#define CMU_IEN_LFRCORDY                            (0x1UL << 2)                         /**< LFRCO Ready Interrupt Enable */
-#define _CMU_IEN_LFRCORDY_SHIFT                     2                                    /**< Shift value for CMU_LFRCORDY */
-#define _CMU_IEN_LFRCORDY_MASK                      0x4UL                                /**< Bit mask for CMU_LFRCORDY */
-#define _CMU_IEN_LFRCORDY_DEFAULT                   0x00000000UL                         /**< Mode DEFAULT for CMU_IEN */
-#define CMU_IEN_LFRCORDY_DEFAULT                    (_CMU_IEN_LFRCORDY_DEFAULT << 2)     /**< Shifted mode DEFAULT for CMU_IEN */
-#define CMU_IEN_LFXORDY                             (0x1UL << 3)                         /**< LFXO Ready Interrupt Enable */
-#define _CMU_IEN_LFXORDY_SHIFT                      3                                    /**< Shift value for CMU_LFXORDY */
-#define _CMU_IEN_LFXORDY_MASK                       0x8UL                                /**< Bit mask for CMU_LFXORDY */
-#define _CMU_IEN_LFXORDY_DEFAULT                    0x00000000UL                         /**< Mode DEFAULT for CMU_IEN */
-#define CMU_IEN_LFXORDY_DEFAULT                     (_CMU_IEN_LFXORDY_DEFAULT << 3)      /**< Shifted mode DEFAULT for CMU_IEN */
-#define CMU_IEN_AUXHFRCORDY                         (0x1UL << 4)                         /**< AUXHFRCO Ready Interrupt Enable */
-#define _CMU_IEN_AUXHFRCORDY_SHIFT                  4                                    /**< Shift value for CMU_AUXHFRCORDY */
-#define _CMU_IEN_AUXHFRCORDY_MASK                   0x10UL                               /**< Bit mask for CMU_AUXHFRCORDY */
-#define _CMU_IEN_AUXHFRCORDY_DEFAULT                0x00000000UL                         /**< Mode DEFAULT for CMU_IEN */
-#define CMU_IEN_AUXHFRCORDY_DEFAULT                 (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4)  /**< Shifted mode DEFAULT for CMU_IEN */
-#define CMU_IEN_CALRDY                              (0x1UL << 5)                         /**< Calibration Ready Interrupt Enable */
-#define _CMU_IEN_CALRDY_SHIFT                       5                                    /**< Shift value for CMU_CALRDY */
-#define _CMU_IEN_CALRDY_MASK                        0x20UL                               /**< Bit mask for CMU_CALRDY */
-#define _CMU_IEN_CALRDY_DEFAULT                     0x00000000UL                         /**< Mode DEFAULT for CMU_IEN */
-#define CMU_IEN_CALRDY_DEFAULT                      (_CMU_IEN_CALRDY_DEFAULT << 5)       /**< Shifted mode DEFAULT for CMU_IEN */
-#define CMU_IEN_CALOF                               (0x1UL << 6)                         /**< Calibration Overflow Interrupt Enable */
-#define _CMU_IEN_CALOF_SHIFT                        6                                    /**< Shift value for CMU_CALOF */
-#define _CMU_IEN_CALOF_MASK                         0x40UL                               /**< Bit mask for CMU_CALOF */
-#define _CMU_IEN_CALOF_DEFAULT                      0x00000000UL                         /**< Mode DEFAULT for CMU_IEN */
-#define CMU_IEN_CALOF_DEFAULT                       (_CMU_IEN_CALOF_DEFAULT << 6)        /**< Shifted mode DEFAULT for CMU_IEN */
-#define CMU_IEN_USBCHFCLKSEL                        (0x1UL << 7)                         /**< USBC HFCLK Selected Interrupt Enable */
-#define _CMU_IEN_USBCHFCLKSEL_SHIFT                 7                                    /**< Shift value for CMU_USBCHFCLKSEL */
-#define _CMU_IEN_USBCHFCLKSEL_MASK                  0x80UL                               /**< Bit mask for CMU_USBCHFCLKSEL */
-#define _CMU_IEN_USBCHFCLKSEL_DEFAULT               0x00000000UL                         /**< Mode DEFAULT for CMU_IEN */
-#define CMU_IEN_USBCHFCLKSEL_DEFAULT                (_CMU_IEN_USBCHFCLKSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IEN */
-
-/* Bit fields for CMU HFCORECLKEN0 */
-#define _CMU_HFCORECLKEN0_RESETVALUE                0x00000000UL                          /**< Default value for CMU_HFCORECLKEN0 */
-#define _CMU_HFCORECLKEN0_MASK                      0x0000003FUL                          /**< Mask for CMU_HFCORECLKEN0 */
-#define CMU_HFCORECLKEN0_DMA                        (0x1UL << 0)                          /**< Direct Memory Access Controller Clock Enable */
-#define _CMU_HFCORECLKEN0_DMA_SHIFT                 0                                     /**< Shift value for CMU_DMA */
-#define _CMU_HFCORECLKEN0_DMA_MASK                  0x1UL                                 /**< Bit mask for CMU_DMA */
-#define _CMU_HFCORECLKEN0_DMA_DEFAULT               0x00000000UL                          /**< Mode DEFAULT for CMU_HFCORECLKEN0 */
-#define CMU_HFCORECLKEN0_DMA_DEFAULT                (_CMU_HFCORECLKEN0_DMA_DEFAULT << 0)  /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */
-#define CMU_HFCORECLKEN0_AES                        (0x1UL << 1)                          /**< Advanced Encryption Standard Accelerator Clock Enable */
-#define _CMU_HFCORECLKEN0_AES_SHIFT                 1                                     /**< Shift value for CMU_AES */
-#define _CMU_HFCORECLKEN0_AES_MASK                  0x2UL                                 /**< Bit mask for CMU_AES */
-#define _CMU_HFCORECLKEN0_AES_DEFAULT               0x00000000UL                          /**< Mode DEFAULT for CMU_HFCORECLKEN0 */
-#define CMU_HFCORECLKEN0_AES_DEFAULT                (_CMU_HFCORECLKEN0_AES_DEFAULT << 1)  /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */
-#define CMU_HFCORECLKEN0_USBC                       (0x1UL << 2)                          /**< Universal Serial Bus Interface Core Clock Enable */
-#define _CMU_HFCORECLKEN0_USBC_SHIFT                2                                     /**< Shift value for CMU_USBC */
-#define _CMU_HFCORECLKEN0_USBC_MASK                 0x4UL                                 /**< Bit mask for CMU_USBC */
-#define _CMU_HFCORECLKEN0_USBC_DEFAULT              0x00000000UL                          /**< Mode DEFAULT for CMU_HFCORECLKEN0 */
-#define CMU_HFCORECLKEN0_USBC_DEFAULT               (_CMU_HFCORECLKEN0_USBC_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */
-#define CMU_HFCORECLKEN0_USB                        (0x1UL << 3)                          /**< Universal Serial Bus Interface Clock Enable */
-#define _CMU_HFCORECLKEN0_USB_SHIFT                 3                                     /**< Shift value for CMU_USB */
-#define _CMU_HFCORECLKEN0_USB_MASK                  0x8UL                                 /**< Bit mask for CMU_USB */
-#define _CMU_HFCORECLKEN0_USB_DEFAULT               0x00000000UL                          /**< Mode DEFAULT for CMU_HFCORECLKEN0 */
-#define CMU_HFCORECLKEN0_USB_DEFAULT                (_CMU_HFCORECLKEN0_USB_DEFAULT << 3)  /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */
-#define CMU_HFCORECLKEN0_LE                         (0x1UL << 4)                          /**< Low Energy Peripheral Interface Clock Enable */
-#define _CMU_HFCORECLKEN0_LE_SHIFT                  4                                     /**< Shift value for CMU_LE */
-#define _CMU_HFCORECLKEN0_LE_MASK                   0x10UL                                /**< Bit mask for CMU_LE */
-#define _CMU_HFCORECLKEN0_LE_DEFAULT                0x00000000UL                          /**< Mode DEFAULT for CMU_HFCORECLKEN0 */
-#define CMU_HFCORECLKEN0_LE_DEFAULT                 (_CMU_HFCORECLKEN0_LE_DEFAULT << 4)   /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */
-#define CMU_HFCORECLKEN0_EBI                        (0x1UL << 5)                          /**< External Bus Interface Clock Enable */
-#define _CMU_HFCORECLKEN0_EBI_SHIFT                 5                                     /**< Shift value for CMU_EBI */
-#define _CMU_HFCORECLKEN0_EBI_MASK                  0x20UL                                /**< Bit mask for CMU_EBI */
-#define _CMU_HFCORECLKEN0_EBI_DEFAULT               0x00000000UL                          /**< Mode DEFAULT for CMU_HFCORECLKEN0 */
-#define CMU_HFCORECLKEN0_EBI_DEFAULT                (_CMU_HFCORECLKEN0_EBI_DEFAULT << 5)  /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */
-
-/* Bit fields for CMU HFPERCLKEN0 */
-#define _CMU_HFPERCLKEN0_RESETVALUE                 0x00000000UL                           /**< Default value for CMU_HFPERCLKEN0 */
-#define _CMU_HFPERCLKEN0_MASK                       0x0003FFFFUL                           /**< Mask for CMU_HFPERCLKEN0 */
-#define CMU_HFPERCLKEN0_USART0                      (0x1UL << 0)                           /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */
-#define _CMU_HFPERCLKEN0_USART0_SHIFT               0                                      /**< Shift value for CMU_USART0 */
-#define _CMU_HFPERCLKEN0_USART0_MASK                0x1UL                                  /**< Bit mask for CMU_USART0 */
-#define _CMU_HFPERCLKEN0_USART0_DEFAULT             0x00000000UL                           /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
-#define CMU_HFPERCLKEN0_USART0_DEFAULT              (_CMU_HFPERCLKEN0_USART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
-#define CMU_HFPERCLKEN0_USART1                      (0x1UL << 1)                           /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */
-#define _CMU_HFPERCLKEN0_USART1_SHIFT               1                                      /**< Shift value for CMU_USART1 */
-#define _CMU_HFPERCLKEN0_USART1_MASK                0x2UL                                  /**< Bit mask for CMU_USART1 */
-#define _CMU_HFPERCLKEN0_USART1_DEFAULT             0x00000000UL                           /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
-#define CMU_HFPERCLKEN0_USART1_DEFAULT              (_CMU_HFPERCLKEN0_USART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
-#define CMU_HFPERCLKEN0_USART2                      (0x1UL << 2)                           /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */
-#define _CMU_HFPERCLKEN0_USART2_SHIFT               2                                      /**< Shift value for CMU_USART2 */
-#define _CMU_HFPERCLKEN0_USART2_MASK                0x4UL                                  /**< Bit mask for CMU_USART2 */
-#define _CMU_HFPERCLKEN0_USART2_DEFAULT             0x00000000UL                           /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
-#define CMU_HFPERCLKEN0_USART2_DEFAULT              (_CMU_HFPERCLKEN0_USART2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
-#define CMU_HFPERCLKEN0_UART0                       (0x1UL << 3)                           /**< Universal Asynchronous Receiver/Transmitter 0 Clock Enable */
-#define _CMU_HFPERCLKEN0_UART0_SHIFT                3                                      /**< Shift value for CMU_UART0 */
-#define _CMU_HFPERCLKEN0_UART0_MASK                 0x8UL                                  /**< Bit mask for CMU_UART0 */
-#define _CMU_HFPERCLKEN0_UART0_DEFAULT              0x00000000UL                           /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
-#define CMU_HFPERCLKEN0_UART0_DEFAULT               (_CMU_HFPERCLKEN0_UART0_DEFAULT << 3)  /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
-#define CMU_HFPERCLKEN0_UART1                       (0x1UL << 4)                           /**< Universal Asynchronous Receiver/Transmitter 1 Clock Enable */
-#define _CMU_HFPERCLKEN0_UART1_SHIFT                4                                      /**< Shift value for CMU_UART1 */
-#define _CMU_HFPERCLKEN0_UART1_MASK                 0x10UL                                 /**< Bit mask for CMU_UART1 */
-#define _CMU_HFPERCLKEN0_UART1_DEFAULT              0x00000000UL                           /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
-#define CMU_HFPERCLKEN0_UART1_DEFAULT               (_CMU_HFPERCLKEN0_UART1_DEFAULT << 4)  /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
-#define CMU_HFPERCLKEN0_TIMER0                      (0x1UL << 5)                           /**< Timer 0 Clock Enable */
-#define _CMU_HFPERCLKEN0_TIMER0_SHIFT               5                                      /**< Shift value for CMU_TIMER0 */
-#define _CMU_HFPERCLKEN0_TIMER0_MASK                0x20UL                                 /**< Bit mask for CMU_TIMER0 */
-#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT             0x00000000UL                           /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
-#define CMU_HFPERCLKEN0_TIMER0_DEFAULT              (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
-#define CMU_HFPERCLKEN0_TIMER1                      (0x1UL << 6)                           /**< Timer 1 Clock Enable */
-#define _CMU_HFPERCLKEN0_TIMER1_SHIFT               6                                      /**< Shift value for CMU_TIMER1 */
-#define _CMU_HFPERCLKEN0_TIMER1_MASK                0x40UL                                 /**< Bit mask for CMU_TIMER1 */
-#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT             0x00000000UL                           /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
-#define CMU_HFPERCLKEN0_TIMER1_DEFAULT              (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
-#define CMU_HFPERCLKEN0_TIMER2                      (0x1UL << 7)                           /**< Timer 2 Clock Enable */
-#define _CMU_HFPERCLKEN0_TIMER2_SHIFT               7                                      /**< Shift value for CMU_TIMER2 */
-#define _CMU_HFPERCLKEN0_TIMER2_MASK                0x80UL                                 /**< Bit mask for CMU_TIMER2 */
-#define _CMU_HFPERCLKEN0_TIMER2_DEFAULT             0x00000000UL                           /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
-#define CMU_HFPERCLKEN0_TIMER2_DEFAULT              (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
-#define CMU_HFPERCLKEN0_TIMER3                      (0x1UL << 8)                           /**< Timer 3 Clock Enable */
-#define _CMU_HFPERCLKEN0_TIMER3_SHIFT               8                                      /**< Shift value for CMU_TIMER3 */
-#define _CMU_HFPERCLKEN0_TIMER3_MASK                0x100UL                                /**< Bit mask for CMU_TIMER3 */
-#define _CMU_HFPERCLKEN0_TIMER3_DEFAULT             0x00000000UL                           /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
-#define CMU_HFPERCLKEN0_TIMER3_DEFAULT              (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
-#define CMU_HFPERCLKEN0_ACMP0                       (0x1UL << 9)                           /**< Analog Comparator 0 Clock Enable */
-#define _CMU_HFPERCLKEN0_ACMP0_SHIFT                9                                      /**< Shift value for CMU_ACMP0 */
-#define _CMU_HFPERCLKEN0_ACMP0_MASK                 0x200UL                                /**< Bit mask for CMU_ACMP0 */
-#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT              0x00000000UL                           /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
-#define CMU_HFPERCLKEN0_ACMP0_DEFAULT               (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 9)  /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
-#define CMU_HFPERCLKEN0_ACMP1                       (0x1UL << 10)                          /**< Analog Comparator 1 Clock Enable */
-#define _CMU_HFPERCLKEN0_ACMP1_SHIFT                10                                     /**< Shift value for CMU_ACMP1 */
-#define _CMU_HFPERCLKEN0_ACMP1_MASK                 0x400UL                                /**< Bit mask for CMU_ACMP1 */
-#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT              0x00000000UL                           /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
-#define CMU_HFPERCLKEN0_ACMP1_DEFAULT               (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
-#define CMU_HFPERCLKEN0_I2C0                        (0x1UL << 11)                          /**< I2C 0 Clock Enable */
-#define _CMU_HFPERCLKEN0_I2C0_SHIFT                 11                                     /**< Shift value for CMU_I2C0 */
-#define _CMU_HFPERCLKEN0_I2C0_MASK                  0x800UL                                /**< Bit mask for CMU_I2C0 */
-#define _CMU_HFPERCLKEN0_I2C0_DEFAULT               0x00000000UL                           /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
-#define CMU_HFPERCLKEN0_I2C0_DEFAULT                (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 11)  /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
-#define CMU_HFPERCLKEN0_I2C1                        (0x1UL << 12)                          /**< I2C 1 Clock Enable */
-#define _CMU_HFPERCLKEN0_I2C1_SHIFT                 12                                     /**< Shift value for CMU_I2C1 */
-#define _CMU_HFPERCLKEN0_I2C1_MASK                  0x1000UL                               /**< Bit mask for CMU_I2C1 */
-#define _CMU_HFPERCLKEN0_I2C1_DEFAULT               0x00000000UL                           /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
-#define CMU_HFPERCLKEN0_I2C1_DEFAULT                (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 12)  /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
-#define CMU_HFPERCLKEN0_GPIO                        (0x1UL << 13)                          /**< General purpose Input/Output Clock Enable */
-#define _CMU_HFPERCLKEN0_GPIO_SHIFT                 13                                     /**< Shift value for CMU_GPIO */
-#define _CMU_HFPERCLKEN0_GPIO_MASK                  0x2000UL                               /**< Bit mask for CMU_GPIO */
-#define _CMU_HFPERCLKEN0_GPIO_DEFAULT               0x00000000UL                           /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
-#define CMU_HFPERCLKEN0_GPIO_DEFAULT                (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 13)  /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
-#define CMU_HFPERCLKEN0_VCMP                        (0x1UL << 14)                          /**< Voltage Comparator Clock Enable */
-#define _CMU_HFPERCLKEN0_VCMP_SHIFT                 14                                     /**< Shift value for CMU_VCMP */
-#define _CMU_HFPERCLKEN0_VCMP_MASK                  0x4000UL                               /**< Bit mask for CMU_VCMP */
-#define _CMU_HFPERCLKEN0_VCMP_DEFAULT               0x00000000UL                           /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
-#define CMU_HFPERCLKEN0_VCMP_DEFAULT                (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 14)  /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
-#define CMU_HFPERCLKEN0_PRS                         (0x1UL << 15)                          /**< Peripheral Reflex System Clock Enable */
-#define _CMU_HFPERCLKEN0_PRS_SHIFT                  15                                     /**< Shift value for CMU_PRS */
-#define _CMU_HFPERCLKEN0_PRS_MASK                   0x8000UL                               /**< Bit mask for CMU_PRS */
-#define _CMU_HFPERCLKEN0_PRS_DEFAULT                0x00000000UL                           /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
-#define CMU_HFPERCLKEN0_PRS_DEFAULT                 (_CMU_HFPERCLKEN0_PRS_DEFAULT << 15)   /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
-#define CMU_HFPERCLKEN0_ADC0                        (0x1UL << 16)                          /**< Analog to Digital Converter 0 Clock Enable */
-#define _CMU_HFPERCLKEN0_ADC0_SHIFT                 16                                     /**< Shift value for CMU_ADC0 */
-#define _CMU_HFPERCLKEN0_ADC0_MASK                  0x10000UL                              /**< Bit mask for CMU_ADC0 */
-#define _CMU_HFPERCLKEN0_ADC0_DEFAULT               0x00000000UL                           /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
-#define CMU_HFPERCLKEN0_ADC0_DEFAULT                (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 16)  /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
-#define CMU_HFPERCLKEN0_DAC0                        (0x1UL << 17)                          /**< Digital to Analog Converter 0 Clock Enable */
-#define _CMU_HFPERCLKEN0_DAC0_SHIFT                 17                                     /**< Shift value for CMU_DAC0 */
-#define _CMU_HFPERCLKEN0_DAC0_MASK                  0x20000UL                              /**< Bit mask for CMU_DAC0 */
-#define _CMU_HFPERCLKEN0_DAC0_DEFAULT               0x00000000UL                           /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
-#define CMU_HFPERCLKEN0_DAC0_DEFAULT                (_CMU_HFPERCLKEN0_DAC0_DEFAULT << 17)  /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
-
-/* Bit fields for CMU SYNCBUSY */
-#define _CMU_SYNCBUSY_RESETVALUE                    0x00000000UL                           /**< Default value for CMU_SYNCBUSY */
-#define _CMU_SYNCBUSY_MASK                          0x00000055UL                           /**< Mask for CMU_SYNCBUSY */
-#define CMU_SYNCBUSY_LFACLKEN0                      (0x1UL << 0)                           /**< Low Frequency A Clock Enable 0 Busy */
-#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT               0                                      /**< Shift value for CMU_LFACLKEN0 */
-#define _CMU_SYNCBUSY_LFACLKEN0_MASK                0x1UL                                  /**< Bit mask for CMU_LFACLKEN0 */
-#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT             0x00000000UL                           /**< Mode DEFAULT for CMU_SYNCBUSY */
-#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT              (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
-#define CMU_SYNCBUSY_LFAPRESC0                      (0x1UL << 2)                           /**< Low Frequency A Prescaler 0 Busy */
-#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT               2                                      /**< Shift value for CMU_LFAPRESC0 */
-#define _CMU_SYNCBUSY_LFAPRESC0_MASK                0x4UL                                  /**< Bit mask for CMU_LFAPRESC0 */
-#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT             0x00000000UL                           /**< Mode DEFAULT for CMU_SYNCBUSY */
-#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT              (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
-#define CMU_SYNCBUSY_LFBCLKEN0                      (0x1UL << 4)                           /**< Low Frequency B Clock Enable 0 Busy */
-#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT               4                                      /**< Shift value for CMU_LFBCLKEN0 */
-#define _CMU_SYNCBUSY_LFBCLKEN0_MASK                0x10UL                                 /**< Bit mask for CMU_LFBCLKEN0 */
-#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT             0x00000000UL                           /**< Mode DEFAULT for CMU_SYNCBUSY */
-#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT              (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
-#define CMU_SYNCBUSY_LFBPRESC0                      (0x1UL << 6)                           /**< Low Frequency B Prescaler 0 Busy */
-#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT               6                                      /**< Shift value for CMU_LFBPRESC0 */
-#define _CMU_SYNCBUSY_LFBPRESC0_MASK                0x40UL                                 /**< Bit mask for CMU_LFBPRESC0 */
-#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT             0x00000000UL                           /**< Mode DEFAULT for CMU_SYNCBUSY */
-#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT              (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
-
-/* Bit fields for CMU FREEZE */
-#define _CMU_FREEZE_RESETVALUE                      0x00000000UL                         /**< Default value for CMU_FREEZE */
-#define _CMU_FREEZE_MASK                            0x00000001UL                         /**< Mask for CMU_FREEZE */
-#define CMU_FREEZE_REGFREEZE                        (0x1UL << 0)                         /**< Register Update Freeze */
-#define _CMU_FREEZE_REGFREEZE_SHIFT                 0                                    /**< Shift value for CMU_REGFREEZE */
-#define _CMU_FREEZE_REGFREEZE_MASK                  0x1UL                                /**< Bit mask for CMU_REGFREEZE */
-#define _CMU_FREEZE_REGFREEZE_DEFAULT               0x00000000UL                         /**< Mode DEFAULT for CMU_FREEZE */
-#define _CMU_FREEZE_REGFREEZE_UPDATE                0x00000000UL                         /**< Mode UPDATE for CMU_FREEZE */
-#define _CMU_FREEZE_REGFREEZE_FREEZE                0x00000001UL                         /**< Mode FREEZE for CMU_FREEZE */
-#define CMU_FREEZE_REGFREEZE_DEFAULT                (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */
-#define CMU_FREEZE_REGFREEZE_UPDATE                 (_CMU_FREEZE_REGFREEZE_UPDATE << 0)  /**< Shifted mode UPDATE for CMU_FREEZE */
-#define CMU_FREEZE_REGFREEZE_FREEZE                 (_CMU_FREEZE_REGFREEZE_FREEZE << 0)  /**< Shifted mode FREEZE for CMU_FREEZE */
-
-/* Bit fields for CMU LFACLKEN0 */
-#define _CMU_LFACLKEN0_RESETVALUE                   0x00000000UL                           /**< Default value for CMU_LFACLKEN0 */
-#define _CMU_LFACLKEN0_MASK                         0x0000000FUL                           /**< Mask for CMU_LFACLKEN0 */
-#define CMU_LFACLKEN0_LESENSE                       (0x1UL << 0)                           /**< Low Energy Sensor Interface Clock Enable */
-#define _CMU_LFACLKEN0_LESENSE_SHIFT                0                                      /**< Shift value for CMU_LESENSE */
-#define _CMU_LFACLKEN0_LESENSE_MASK                 0x1UL                                  /**< Bit mask for CMU_LESENSE */
-#define _CMU_LFACLKEN0_LESENSE_DEFAULT              0x00000000UL                           /**< Mode DEFAULT for CMU_LFACLKEN0 */
-#define CMU_LFACLKEN0_LESENSE_DEFAULT               (_CMU_LFACLKEN0_LESENSE_DEFAULT << 0)  /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */
-#define CMU_LFACLKEN0_RTC                           (0x1UL << 1)                           /**< Real-Time Counter Clock Enable */
-#define _CMU_LFACLKEN0_RTC_SHIFT                    1                                      /**< Shift value for CMU_RTC */
-#define _CMU_LFACLKEN0_RTC_MASK                     0x2UL                                  /**< Bit mask for CMU_RTC */
-#define _CMU_LFACLKEN0_RTC_DEFAULT                  0x00000000UL                           /**< Mode DEFAULT for CMU_LFACLKEN0 */
-#define CMU_LFACLKEN0_RTC_DEFAULT                   (_CMU_LFACLKEN0_RTC_DEFAULT << 1)      /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */
-#define CMU_LFACLKEN0_LETIMER0                      (0x1UL << 2)                           /**< Low Energy Timer 0 Clock Enable */
-#define _CMU_LFACLKEN0_LETIMER0_SHIFT               2                                      /**< Shift value for CMU_LETIMER0 */
-#define _CMU_LFACLKEN0_LETIMER0_MASK                0x4UL                                  /**< Bit mask for CMU_LETIMER0 */
-#define _CMU_LFACLKEN0_LETIMER0_DEFAULT             0x00000000UL                           /**< Mode DEFAULT for CMU_LFACLKEN0 */
-#define CMU_LFACLKEN0_LETIMER0_DEFAULT              (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */
-#define CMU_LFACLKEN0_LCD                           (0x1UL << 3)                           /**< Liquid Crystal Display Controller Clock Enable */
-#define _CMU_LFACLKEN0_LCD_SHIFT                    3                                      /**< Shift value for CMU_LCD */
-#define _CMU_LFACLKEN0_LCD_MASK                     0x8UL                                  /**< Bit mask for CMU_LCD */
-#define _CMU_LFACLKEN0_LCD_DEFAULT                  0x00000000UL                           /**< Mode DEFAULT for CMU_LFACLKEN0 */
-#define CMU_LFACLKEN0_LCD_DEFAULT                   (_CMU_LFACLKEN0_LCD_DEFAULT << 3)      /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */
-
-/* Bit fields for CMU LFBCLKEN0 */
-#define _CMU_LFBCLKEN0_RESETVALUE                   0x00000000UL                          /**< Default value for CMU_LFBCLKEN0 */
-#define _CMU_LFBCLKEN0_MASK                         0x00000003UL                          /**< Mask for CMU_LFBCLKEN0 */
-#define CMU_LFBCLKEN0_LEUART0                       (0x1UL << 0)                          /**< Low Energy UART 0 Clock Enable */
-#define _CMU_LFBCLKEN0_LEUART0_SHIFT                0                                     /**< Shift value for CMU_LEUART0 */
-#define _CMU_LFBCLKEN0_LEUART0_MASK                 0x1UL                                 /**< Bit mask for CMU_LEUART0 */
-#define _CMU_LFBCLKEN0_LEUART0_DEFAULT              0x00000000UL                          /**< Mode DEFAULT for CMU_LFBCLKEN0 */
-#define CMU_LFBCLKEN0_LEUART0_DEFAULT               (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */
-#define CMU_LFBCLKEN0_LEUART1                       (0x1UL << 1)                          /**< Low Energy UART 1 Clock Enable */
-#define _CMU_LFBCLKEN0_LEUART1_SHIFT                1                                     /**< Shift value for CMU_LEUART1 */
-#define _CMU_LFBCLKEN0_LEUART1_MASK                 0x2UL                                 /**< Bit mask for CMU_LEUART1 */
-#define _CMU_LFBCLKEN0_LEUART1_DEFAULT              0x00000000UL                          /**< Mode DEFAULT for CMU_LFBCLKEN0 */
-#define CMU_LFBCLKEN0_LEUART1_DEFAULT               (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */
-
-/* Bit fields for CMU LFAPRESC0 */
-#define _CMU_LFAPRESC0_RESETVALUE                   0x00000000UL                            /**< Default value for CMU_LFAPRESC0 */
-#define _CMU_LFAPRESC0_MASK                         0x00003FF3UL                            /**< Mask for CMU_LFAPRESC0 */
-#define _CMU_LFAPRESC0_LESENSE_SHIFT                0                                       /**< Shift value for CMU_LESENSE */
-#define _CMU_LFAPRESC0_LESENSE_MASK                 0x3UL                                   /**< Bit mask for CMU_LESENSE */
-#define _CMU_LFAPRESC0_LESENSE_DIV1                 0x00000000UL                            /**< Mode DIV1 for CMU_LFAPRESC0 */
-#define _CMU_LFAPRESC0_LESENSE_DIV2                 0x00000001UL                            /**< Mode DIV2 for CMU_LFAPRESC0 */
-#define _CMU_LFAPRESC0_LESENSE_DIV4                 0x00000002UL                            /**< Mode DIV4 for CMU_LFAPRESC0 */
-#define _CMU_LFAPRESC0_LESENSE_DIV8                 0x00000003UL                            /**< Mode DIV8 for CMU_LFAPRESC0 */
-#define CMU_LFAPRESC0_LESENSE_DIV1                  (_CMU_LFAPRESC0_LESENSE_DIV1 << 0)      /**< Shifted mode DIV1 for CMU_LFAPRESC0 */
-#define CMU_LFAPRESC0_LESENSE_DIV2                  (_CMU_LFAPRESC0_LESENSE_DIV2 << 0)      /**< Shifted mode DIV2 for CMU_LFAPRESC0 */
-#define CMU_LFAPRESC0_LESENSE_DIV4                  (_CMU_LFAPRESC0_LESENSE_DIV4 << 0)      /**< Shifted mode DIV4 for CMU_LFAPRESC0 */
-#define CMU_LFAPRESC0_LESENSE_DIV8                  (_CMU_LFAPRESC0_LESENSE_DIV8 << 0)      /**< Shifted mode DIV8 for CMU_LFAPRESC0 */
-#define _CMU_LFAPRESC0_RTC_SHIFT                    4                                       /**< Shift value for CMU_RTC */
-#define _CMU_LFAPRESC0_RTC_MASK                     0xF0UL                                  /**< Bit mask for CMU_RTC */
-#define _CMU_LFAPRESC0_RTC_DIV1                     0x00000000UL                            /**< Mode DIV1 for CMU_LFAPRESC0 */
-#define _CMU_LFAPRESC0_RTC_DIV2                     0x00000001UL                            /**< Mode DIV2 for CMU_LFAPRESC0 */
-#define _CMU_LFAPRESC0_RTC_DIV4                     0x00000002UL                            /**< Mode DIV4 for CMU_LFAPRESC0 */
-#define _CMU_LFAPRESC0_RTC_DIV8                     0x00000003UL                            /**< Mode DIV8 for CMU_LFAPRESC0 */
-#define _CMU_LFAPRESC0_RTC_DIV16                    0x00000004UL                            /**< Mode DIV16 for CMU_LFAPRESC0 */
-#define _CMU_LFAPRESC0_RTC_DIV32                    0x00000005UL                            /**< Mode DIV32 for CMU_LFAPRESC0 */
-#define _CMU_LFAPRESC0_RTC_DIV64                    0x00000006UL                            /**< Mode DIV64 for CMU_LFAPRESC0 */
-#define _CMU_LFAPRESC0_RTC_DIV128                   0x00000007UL                            /**< Mode DIV128 for CMU_LFAPRESC0 */
-#define _CMU_LFAPRESC0_RTC_DIV256                   0x00000008UL                            /**< Mode DIV256 for CMU_LFAPRESC0 */
-#define _CMU_LFAPRESC0_RTC_DIV512                   0x00000009UL                            /**< Mode DIV512 for CMU_LFAPRESC0 */
-#define _CMU_LFAPRESC0_RTC_DIV1024                  0x0000000AUL                            /**< Mode DIV1024 for CMU_LFAPRESC0 */
-#define _CMU_LFAPRESC0_RTC_DIV2048                  0x0000000BUL                            /**< Mode DIV2048 for CMU_LFAPRESC0 */
-#define _CMU_LFAPRESC0_RTC_DIV4096                  0x0000000CUL                            /**< Mode DIV4096 for CMU_LFAPRESC0 */
-#define _CMU_LFAPRESC0_RTC_DIV8192                  0x0000000DUL                            /**< Mode DIV8192 for CMU_LFAPRESC0 */
-#define _CMU_LFAPRESC0_RTC_DIV16384                 0x0000000EUL                            /**< Mode DIV16384 for CMU_LFAPRESC0 */
-#define _CMU_LFAPRESC0_RTC_DIV32768                 0x0000000FUL                            /**< Mode DIV32768 for CMU_LFAPRESC0 */
-#define CMU_LFAPRESC0_RTC_DIV1                      (_CMU_LFAPRESC0_RTC_DIV1 << 4)          /**< Shifted mode DIV1 for CMU_LFAPRESC0 */
-#define CMU_LFAPRESC0_RTC_DIV2                      (_CMU_LFAPRESC0_RTC_DIV2 << 4)          /**< Shifted mode DIV2 for CMU_LFAPRESC0 */
-#define CMU_LFAPRESC0_RTC_DIV4                      (_CMU_LFAPRESC0_RTC_DIV4 << 4)          /**< Shifted mode DIV4 for CMU_LFAPRESC0 */
-#define CMU_LFAPRESC0_RTC_DIV8                      (_CMU_LFAPRESC0_RTC_DIV8 << 4)          /**< Shifted mode DIV8 for CMU_LFAPRESC0 */
-#define CMU_LFAPRESC0_RTC_DIV16                     (_CMU_LFAPRESC0_RTC_DIV16 << 4)         /**< Shifted mode DIV16 for CMU_LFAPRESC0 */
-#define CMU_LFAPRESC0_RTC_DIV32                     (_CMU_LFAPRESC0_RTC_DIV32 << 4)         /**< Shifted mode DIV32 for CMU_LFAPRESC0 */
-#define CMU_LFAPRESC0_RTC_DIV64                     (_CMU_LFAPRESC0_RTC_DIV64 << 4)         /**< Shifted mode DIV64 for CMU_LFAPRESC0 */
-#define CMU_LFAPRESC0_RTC_DIV128                    (_CMU_LFAPRESC0_RTC_DIV128 << 4)        /**< Shifted mode DIV128 for CMU_LFAPRESC0 */
-#define CMU_LFAPRESC0_RTC_DIV256                    (_CMU_LFAPRESC0_RTC_DIV256 << 4)        /**< Shifted mode DIV256 for CMU_LFAPRESC0 */
-#define CMU_LFAPRESC0_RTC_DIV512                    (_CMU_LFAPRESC0_RTC_DIV512 << 4)        /**< Shifted mode DIV512 for CMU_LFAPRESC0 */
-#define CMU_LFAPRESC0_RTC_DIV1024                   (_CMU_LFAPRESC0_RTC_DIV1024 << 4)       /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */
-#define CMU_LFAPRESC0_RTC_DIV2048                   (_CMU_LFAPRESC0_RTC_DIV2048 << 4)       /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */
-#define CMU_LFAPRESC0_RTC_DIV4096                   (_CMU_LFAPRESC0_RTC_DIV4096 << 4)       /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */
-#define CMU_LFAPRESC0_RTC_DIV8192                   (_CMU_LFAPRESC0_RTC_DIV8192 << 4)       /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */
-#define CMU_LFAPRESC0_RTC_DIV16384                  (_CMU_LFAPRESC0_RTC_DIV16384 << 4)      /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */
-#define CMU_LFAPRESC0_RTC_DIV32768                  (_CMU_LFAPRESC0_RTC_DIV32768 << 4)      /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */
-#define _CMU_LFAPRESC0_LETIMER0_SHIFT               8                                       /**< Shift value for CMU_LETIMER0 */
-#define _CMU_LFAPRESC0_LETIMER0_MASK                0xF00UL                                 /**< Bit mask for CMU_LETIMER0 */
-#define _CMU_LFAPRESC0_LETIMER0_DIV1                0x00000000UL                            /**< Mode DIV1 for CMU_LFAPRESC0 */
-#define _CMU_LFAPRESC0_LETIMER0_DIV2                0x00000001UL                            /**< Mode DIV2 for CMU_LFAPRESC0 */
-#define _CMU_LFAPRESC0_LETIMER0_DIV4                0x00000002UL                            /**< Mode DIV4 for CMU_LFAPRESC0 */
-#define _CMU_LFAPRESC0_LETIMER0_DIV8                0x00000003UL                            /**< Mode DIV8 for CMU_LFAPRESC0 */
-#define _CMU_LFAPRESC0_LETIMER0_DIV16               0x00000004UL                            /**< Mode DIV16 for CMU_LFAPRESC0 */
-#define _CMU_LFAPRESC0_LETIMER0_DIV32               0x00000005UL                            /**< Mode DIV32 for CMU_LFAPRESC0 */
-#define _CMU_LFAPRESC0_LETIMER0_DIV64               0x00000006UL                            /**< Mode DIV64 for CMU_LFAPRESC0 */
-#define _CMU_LFAPRESC0_LETIMER0_DIV128              0x00000007UL                            /**< Mode DIV128 for CMU_LFAPRESC0 */
-#define _CMU_LFAPRESC0_LETIMER0_DIV256              0x00000008UL                            /**< Mode DIV256 for CMU_LFAPRESC0 */
-#define _CMU_LFAPRESC0_LETIMER0_DIV512              0x00000009UL                            /**< Mode DIV512 for CMU_LFAPRESC0 */
-#define _CMU_LFAPRESC0_LETIMER0_DIV1024             0x0000000AUL                            /**< Mode DIV1024 for CMU_LFAPRESC0 */
-#define _CMU_LFAPRESC0_LETIMER0_DIV2048             0x0000000BUL                            /**< Mode DIV2048 for CMU_LFAPRESC0 */
-#define _CMU_LFAPRESC0_LETIMER0_DIV4096             0x0000000CUL                            /**< Mode DIV4096 for CMU_LFAPRESC0 */
-#define _CMU_LFAPRESC0_LETIMER0_DIV8192             0x0000000DUL                            /**< Mode DIV8192 for CMU_LFAPRESC0 */
-#define _CMU_LFAPRESC0_LETIMER0_DIV16384            0x0000000EUL                            /**< Mode DIV16384 for CMU_LFAPRESC0 */
-#define _CMU_LFAPRESC0_LETIMER0_DIV32768            0x0000000FUL                            /**< Mode DIV32768 for CMU_LFAPRESC0 */
-#define CMU_LFAPRESC0_LETIMER0_DIV1                 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 8)     /**< Shifted mode DIV1 for CMU_LFAPRESC0 */
-#define CMU_LFAPRESC0_LETIMER0_DIV2                 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 8)     /**< Shifted mode DIV2 for CMU_LFAPRESC0 */
-#define CMU_LFAPRESC0_LETIMER0_DIV4                 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 8)     /**< Shifted mode DIV4 for CMU_LFAPRESC0 */
-#define CMU_LFAPRESC0_LETIMER0_DIV8                 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 8)     /**< Shifted mode DIV8 for CMU_LFAPRESC0 */
-#define CMU_LFAPRESC0_LETIMER0_DIV16                (_CMU_LFAPRESC0_LETIMER0_DIV16 << 8)    /**< Shifted mode DIV16 for CMU_LFAPRESC0 */
-#define CMU_LFAPRESC0_LETIMER0_DIV32                (_CMU_LFAPRESC0_LETIMER0_DIV32 << 8)    /**< Shifted mode DIV32 for CMU_LFAPRESC0 */
-#define CMU_LFAPRESC0_LETIMER0_DIV64                (_CMU_LFAPRESC0_LETIMER0_DIV64 << 8)    /**< Shifted mode DIV64 for CMU_LFAPRESC0 */
-#define CMU_LFAPRESC0_LETIMER0_DIV128               (_CMU_LFAPRESC0_LETIMER0_DIV128 << 8)   /**< Shifted mode DIV128 for CMU_LFAPRESC0 */
-#define CMU_LFAPRESC0_LETIMER0_DIV256               (_CMU_LFAPRESC0_LETIMER0_DIV256 << 8)   /**< Shifted mode DIV256 for CMU_LFAPRESC0 */
-#define CMU_LFAPRESC0_LETIMER0_DIV512               (_CMU_LFAPRESC0_LETIMER0_DIV512 << 8)   /**< Shifted mode DIV512 for CMU_LFAPRESC0 */
-#define CMU_LFAPRESC0_LETIMER0_DIV1024              (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 8)  /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */
-#define CMU_LFAPRESC0_LETIMER0_DIV2048              (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 8)  /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */
-#define CMU_LFAPRESC0_LETIMER0_DIV4096              (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 8)  /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */
-#define CMU_LFAPRESC0_LETIMER0_DIV8192              (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 8)  /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */
-#define CMU_LFAPRESC0_LETIMER0_DIV16384             (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 8) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */
-#define CMU_LFAPRESC0_LETIMER0_DIV32768             (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 8) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */
-#define _CMU_LFAPRESC0_LCD_SHIFT                    12                                      /**< Shift value for CMU_LCD */
-#define _CMU_LFAPRESC0_LCD_MASK                     0x3000UL                                /**< Bit mask for CMU_LCD */
-#define _CMU_LFAPRESC0_LCD_DIV16                    0x00000000UL                            /**< Mode DIV16 for CMU_LFAPRESC0 */
-#define _CMU_LFAPRESC0_LCD_DIV32                    0x00000001UL                            /**< Mode DIV32 for CMU_LFAPRESC0 */
-#define _CMU_LFAPRESC0_LCD_DIV64                    0x00000002UL                            /**< Mode DIV64 for CMU_LFAPRESC0 */
-#define _CMU_LFAPRESC0_LCD_DIV128                   0x00000003UL                            /**< Mode DIV128 for CMU_LFAPRESC0 */
-#define CMU_LFAPRESC0_LCD_DIV16                     (_CMU_LFAPRESC0_LCD_DIV16 << 12)        /**< Shifted mode DIV16 for CMU_LFAPRESC0 */
-#define CMU_LFAPRESC0_LCD_DIV32                     (_CMU_LFAPRESC0_LCD_DIV32 << 12)        /**< Shifted mode DIV32 for CMU_LFAPRESC0 */
-#define CMU_LFAPRESC0_LCD_DIV64                     (_CMU_LFAPRESC0_LCD_DIV64 << 12)        /**< Shifted mode DIV64 for CMU_LFAPRESC0 */
-#define CMU_LFAPRESC0_LCD_DIV128                    (_CMU_LFAPRESC0_LCD_DIV128 << 12)       /**< Shifted mode DIV128 for CMU_LFAPRESC0 */
-
-/* Bit fields for CMU LFBPRESC0 */
-#define _CMU_LFBPRESC0_RESETVALUE                   0x00000000UL                       /**< Default value for CMU_LFBPRESC0 */
-#define _CMU_LFBPRESC0_MASK                         0x00000033UL                       /**< Mask for CMU_LFBPRESC0 */
-#define _CMU_LFBPRESC0_LEUART0_SHIFT                0                                  /**< Shift value for CMU_LEUART0 */
-#define _CMU_LFBPRESC0_LEUART0_MASK                 0x3UL                              /**< Bit mask for CMU_LEUART0 */
-#define _CMU_LFBPRESC0_LEUART0_DIV1                 0x00000000UL                       /**< Mode DIV1 for CMU_LFBPRESC0 */
-#define _CMU_LFBPRESC0_LEUART0_DIV2                 0x00000001UL                       /**< Mode DIV2 for CMU_LFBPRESC0 */
-#define _CMU_LFBPRESC0_LEUART0_DIV4                 0x00000002UL                       /**< Mode DIV4 for CMU_LFBPRESC0 */
-#define _CMU_LFBPRESC0_LEUART0_DIV8                 0x00000003UL                       /**< Mode DIV8 for CMU_LFBPRESC0 */
-#define CMU_LFBPRESC0_LEUART0_DIV1                  (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */
-#define CMU_LFBPRESC0_LEUART0_DIV2                  (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */
-#define CMU_LFBPRESC0_LEUART0_DIV4                  (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */
-#define CMU_LFBPRESC0_LEUART0_DIV8                  (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */
-#define _CMU_LFBPRESC0_LEUART1_SHIFT                4                                  /**< Shift value for CMU_LEUART1 */
-#define _CMU_LFBPRESC0_LEUART1_MASK                 0x30UL                             /**< Bit mask for CMU_LEUART1 */
-#define _CMU_LFBPRESC0_LEUART1_DIV1                 0x00000000UL                       /**< Mode DIV1 for CMU_LFBPRESC0 */
-#define _CMU_LFBPRESC0_LEUART1_DIV2                 0x00000001UL                       /**< Mode DIV2 for CMU_LFBPRESC0 */
-#define _CMU_LFBPRESC0_LEUART1_DIV4                 0x00000002UL                       /**< Mode DIV4 for CMU_LFBPRESC0 */
-#define _CMU_LFBPRESC0_LEUART1_DIV8                 0x00000003UL                       /**< Mode DIV8 for CMU_LFBPRESC0 */
-#define CMU_LFBPRESC0_LEUART1_DIV1                  (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */
-#define CMU_LFBPRESC0_LEUART1_DIV2                  (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */
-#define CMU_LFBPRESC0_LEUART1_DIV4                  (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */
-#define CMU_LFBPRESC0_LEUART1_DIV8                  (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */
-
-/* Bit fields for CMU PCNTCTRL */
-#define _CMU_PCNTCTRL_RESETVALUE                    0x00000000UL                             /**< Default value for CMU_PCNTCTRL */
-#define _CMU_PCNTCTRL_MASK                          0x0000003FUL                             /**< Mask for CMU_PCNTCTRL */
-#define CMU_PCNTCTRL_PCNT0CLKEN                     (0x1UL << 0)                             /**< PCNT0 Clock Enable */
-#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT              0                                        /**< Shift value for CMU_PCNT0CLKEN */
-#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK               0x1UL                                    /**< Bit mask for CMU_PCNT0CLKEN */
-#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT            0x00000000UL                             /**< Mode DEFAULT for CMU_PCNTCTRL */
-#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT             (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0)  /**< Shifted mode DEFAULT for CMU_PCNTCTRL */
-#define CMU_PCNTCTRL_PCNT0CLKSEL                    (0x1UL << 1)                             /**< PCNT0 Clock Select */
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT             1                                        /**< Shift value for CMU_PCNT0CLKSEL */
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK              0x2UL                                    /**< Bit mask for CMU_PCNT0CLKSEL */
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT           0x00000000UL                             /**< Mode DEFAULT for CMU_PCNTCTRL */
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK            0x00000000UL                             /**< Mode LFACLK for CMU_PCNTCTRL */
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0           0x00000001UL                             /**< Mode PCNT0S0 for CMU_PCNTCTRL */
-#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT            (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */
-#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK             (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1)  /**< Shifted mode LFACLK for CMU_PCNTCTRL */
-#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0            (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */
-#define CMU_PCNTCTRL_PCNT1CLKEN                     (0x1UL << 2)                             /**< PCNT1 Clock Enable */
-#define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT              2                                        /**< Shift value for CMU_PCNT1CLKEN */
-#define _CMU_PCNTCTRL_PCNT1CLKEN_MASK               0x4UL                                    /**< Bit mask for CMU_PCNT1CLKEN */
-#define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT            0x00000000UL                             /**< Mode DEFAULT for CMU_PCNTCTRL */
-#define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT             (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2)  /**< Shifted mode DEFAULT for CMU_PCNTCTRL */
-#define CMU_PCNTCTRL_PCNT1CLKSEL                    (0x1UL << 3)                             /**< PCNT1 Clock Select */
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT             3                                        /**< Shift value for CMU_PCNT1CLKSEL */
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK              0x8UL                                    /**< Bit mask for CMU_PCNT1CLKSEL */
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT           0x00000000UL                             /**< Mode DEFAULT for CMU_PCNTCTRL */
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK            0x00000000UL                             /**< Mode LFACLK for CMU_PCNTCTRL */
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0           0x00000001UL                             /**< Mode PCNT1S0 for CMU_PCNTCTRL */
-#define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT            (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */
-#define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK             (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3)  /**< Shifted mode LFACLK for CMU_PCNTCTRL */
-#define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0            (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */
-#define CMU_PCNTCTRL_PCNT2CLKEN                     (0x1UL << 4)                             /**< PCNT2 Clock Enable */
-#define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT              4                                        /**< Shift value for CMU_PCNT2CLKEN */
-#define _CMU_PCNTCTRL_PCNT2CLKEN_MASK               0x10UL                                   /**< Bit mask for CMU_PCNT2CLKEN */
-#define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT            0x00000000UL                             /**< Mode DEFAULT for CMU_PCNTCTRL */
-#define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT             (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4)  /**< Shifted mode DEFAULT for CMU_PCNTCTRL */
-#define CMU_PCNTCTRL_PCNT2CLKSEL                    (0x1UL << 5)                             /**< PCNT2 Clock Select */
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT             5                                        /**< Shift value for CMU_PCNT2CLKSEL */
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK              0x20UL                                   /**< Bit mask for CMU_PCNT2CLKSEL */
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT           0x00000000UL                             /**< Mode DEFAULT for CMU_PCNTCTRL */
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK            0x00000000UL                             /**< Mode LFACLK for CMU_PCNTCTRL */
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0           0x00000001UL                             /**< Mode PCNT2S0 for CMU_PCNTCTRL */
-#define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT            (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */
-#define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK             (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5)  /**< Shifted mode LFACLK for CMU_PCNTCTRL */
-#define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0            (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */
-
-/* Bit fields for CMU LCDCTRL */
-#define _CMU_LCDCTRL_RESETVALUE                     0x00000020UL                         /**< Default value for CMU_LCDCTRL */
-#define _CMU_LCDCTRL_MASK                           0x0000007FUL                         /**< Mask for CMU_LCDCTRL */
-#define _CMU_LCDCTRL_FDIV_SHIFT                     0                                    /**< Shift value for CMU_FDIV */
-#define _CMU_LCDCTRL_FDIV_MASK                      0x7UL                                /**< Bit mask for CMU_FDIV */
-#define _CMU_LCDCTRL_FDIV_DEFAULT                   0x00000000UL                         /**< Mode DEFAULT for CMU_LCDCTRL */
-#define CMU_LCDCTRL_FDIV_DEFAULT                    (_CMU_LCDCTRL_FDIV_DEFAULT << 0)     /**< Shifted mode DEFAULT for CMU_LCDCTRL */
-#define CMU_LCDCTRL_VBOOSTEN                        (0x1UL << 3)                         /**< Voltage Boost Enable */
-#define _CMU_LCDCTRL_VBOOSTEN_SHIFT                 3                                    /**< Shift value for CMU_VBOOSTEN */
-#define _CMU_LCDCTRL_VBOOSTEN_MASK                  0x8UL                                /**< Bit mask for CMU_VBOOSTEN */
-#define _CMU_LCDCTRL_VBOOSTEN_DEFAULT               0x00000000UL                         /**< Mode DEFAULT for CMU_LCDCTRL */
-#define CMU_LCDCTRL_VBOOSTEN_DEFAULT                (_CMU_LCDCTRL_VBOOSTEN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LCDCTRL */
-#define _CMU_LCDCTRL_VBFDIV_SHIFT                   4                                    /**< Shift value for CMU_VBFDIV */
-#define _CMU_LCDCTRL_VBFDIV_MASK                    0x70UL                               /**< Bit mask for CMU_VBFDIV */
-#define _CMU_LCDCTRL_VBFDIV_DIV1                    0x00000000UL                         /**< Mode DIV1 for CMU_LCDCTRL */
-#define _CMU_LCDCTRL_VBFDIV_DIV2                    0x00000001UL                         /**< Mode DIV2 for CMU_LCDCTRL */
-#define _CMU_LCDCTRL_VBFDIV_DEFAULT                 0x00000002UL                         /**< Mode DEFAULT for CMU_LCDCTRL */
-#define _CMU_LCDCTRL_VBFDIV_DIV4                    0x00000002UL                         /**< Mode DIV4 for CMU_LCDCTRL */
-#define _CMU_LCDCTRL_VBFDIV_DIV8                    0x00000003UL                         /**< Mode DIV8 for CMU_LCDCTRL */
-#define _CMU_LCDCTRL_VBFDIV_DIV16                   0x00000004UL                         /**< Mode DIV16 for CMU_LCDCTRL */
-#define _CMU_LCDCTRL_VBFDIV_DIV32                   0x00000005UL                         /**< Mode DIV32 for CMU_LCDCTRL */
-#define _CMU_LCDCTRL_VBFDIV_DIV64                   0x00000006UL                         /**< Mode DIV64 for CMU_LCDCTRL */
-#define _CMU_LCDCTRL_VBFDIV_DIV128                  0x00000007UL                         /**< Mode DIV128 for CMU_LCDCTRL */
-#define CMU_LCDCTRL_VBFDIV_DIV1                     (_CMU_LCDCTRL_VBFDIV_DIV1 << 4)      /**< Shifted mode DIV1 for CMU_LCDCTRL */
-#define CMU_LCDCTRL_VBFDIV_DIV2                     (_CMU_LCDCTRL_VBFDIV_DIV2 << 4)      /**< Shifted mode DIV2 for CMU_LCDCTRL */
-#define CMU_LCDCTRL_VBFDIV_DEFAULT                  (_CMU_LCDCTRL_VBFDIV_DEFAULT << 4)   /**< Shifted mode DEFAULT for CMU_LCDCTRL */
-#define CMU_LCDCTRL_VBFDIV_DIV4                     (_CMU_LCDCTRL_VBFDIV_DIV4 << 4)      /**< Shifted mode DIV4 for CMU_LCDCTRL */
-#define CMU_LCDCTRL_VBFDIV_DIV8                     (_CMU_LCDCTRL_VBFDIV_DIV8 << 4)      /**< Shifted mode DIV8 for CMU_LCDCTRL */
-#define CMU_LCDCTRL_VBFDIV_DIV16                    (_CMU_LCDCTRL_VBFDIV_DIV16 << 4)     /**< Shifted mode DIV16 for CMU_LCDCTRL */
-#define CMU_LCDCTRL_VBFDIV_DIV32                    (_CMU_LCDCTRL_VBFDIV_DIV32 << 4)     /**< Shifted mode DIV32 for CMU_LCDCTRL */
-#define CMU_LCDCTRL_VBFDIV_DIV64                    (_CMU_LCDCTRL_VBFDIV_DIV64 << 4)     /**< Shifted mode DIV64 for CMU_LCDCTRL */
-#define CMU_LCDCTRL_VBFDIV_DIV128                   (_CMU_LCDCTRL_VBFDIV_DIV128 << 4)    /**< Shifted mode DIV128 for CMU_LCDCTRL */
-
-/* Bit fields for CMU ROUTE */
-#define _CMU_ROUTE_RESETVALUE                       0x00000000UL                         /**< Default value for CMU_ROUTE */
-#define _CMU_ROUTE_MASK                             0x0000001FUL                         /**< Mask for CMU_ROUTE */
-#define CMU_ROUTE_CLKOUT0PEN                        (0x1UL << 0)                         /**< CLKOUT0 Pin Enable */
-#define _CMU_ROUTE_CLKOUT0PEN_SHIFT                 0                                    /**< Shift value for CMU_CLKOUT0PEN */
-#define _CMU_ROUTE_CLKOUT0PEN_MASK                  0x1UL                                /**< Bit mask for CMU_CLKOUT0PEN */
-#define _CMU_ROUTE_CLKOUT0PEN_DEFAULT               0x00000000UL                         /**< Mode DEFAULT for CMU_ROUTE */
-#define CMU_ROUTE_CLKOUT0PEN_DEFAULT                (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTE */
-#define CMU_ROUTE_CLKOUT1PEN                        (0x1UL << 1)                         /**< CLKOUT1 Pin Enable */
-#define _CMU_ROUTE_CLKOUT1PEN_SHIFT                 1                                    /**< Shift value for CMU_CLKOUT1PEN */
-#define _CMU_ROUTE_CLKOUT1PEN_MASK                  0x2UL                                /**< Bit mask for CMU_CLKOUT1PEN */
-#define _CMU_ROUTE_CLKOUT1PEN_DEFAULT               0x00000000UL                         /**< Mode DEFAULT for CMU_ROUTE */
-#define CMU_ROUTE_CLKOUT1PEN_DEFAULT                (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTE */
-#define _CMU_ROUTE_LOCATION_SHIFT                   2                                    /**< Shift value for CMU_LOCATION */
-#define _CMU_ROUTE_LOCATION_MASK                    0x1CUL                               /**< Bit mask for CMU_LOCATION */
-#define _CMU_ROUTE_LOCATION_LOC0                    0x00000000UL                         /**< Mode LOC0 for CMU_ROUTE */
-#define _CMU_ROUTE_LOCATION_DEFAULT                 0x00000000UL                         /**< Mode DEFAULT for CMU_ROUTE */
-#define _CMU_ROUTE_LOCATION_LOC1                    0x00000001UL                         /**< Mode LOC1 for CMU_ROUTE */
-#define _CMU_ROUTE_LOCATION_LOC2                    0x00000002UL                         /**< Mode LOC2 for CMU_ROUTE */
-#define CMU_ROUTE_LOCATION_LOC0                     (_CMU_ROUTE_LOCATION_LOC0 << 2)      /**< Shifted mode LOC0 for CMU_ROUTE */
-#define CMU_ROUTE_LOCATION_DEFAULT                  (_CMU_ROUTE_LOCATION_DEFAULT << 2)   /**< Shifted mode DEFAULT for CMU_ROUTE */
-#define CMU_ROUTE_LOCATION_LOC1                     (_CMU_ROUTE_LOCATION_LOC1 << 2)      /**< Shifted mode LOC1 for CMU_ROUTE */
-#define CMU_ROUTE_LOCATION_LOC2                     (_CMU_ROUTE_LOCATION_LOC2 << 2)      /**< Shifted mode LOC2 for CMU_ROUTE */
-
-/* Bit fields for CMU LOCK */
-#define _CMU_LOCK_RESETVALUE                        0x00000000UL                      /**< Default value for CMU_LOCK */
-#define _CMU_LOCK_MASK                              0x0000FFFFUL                      /**< Mask for CMU_LOCK */
-#define _CMU_LOCK_LOCKKEY_SHIFT                     0                                 /**< Shift value for CMU_LOCKKEY */
-#define _CMU_LOCK_LOCKKEY_MASK                      0xFFFFUL                          /**< Bit mask for CMU_LOCKKEY */
-#define _CMU_LOCK_LOCKKEY_DEFAULT                   0x00000000UL                      /**< Mode DEFAULT for CMU_LOCK */
-#define _CMU_LOCK_LOCKKEY_LOCK                      0x00000000UL                      /**< Mode LOCK for CMU_LOCK */
-#define _CMU_LOCK_LOCKKEY_UNLOCKED                  0x00000000UL                      /**< Mode UNLOCKED for CMU_LOCK */
-#define _CMU_LOCK_LOCKKEY_LOCKED                    0x00000001UL                      /**< Mode LOCKED for CMU_LOCK */
-#define _CMU_LOCK_LOCKKEY_UNLOCK                    0x0000580EUL                      /**< Mode UNLOCK for CMU_LOCK */
-#define CMU_LOCK_LOCKKEY_DEFAULT                    (_CMU_LOCK_LOCKKEY_DEFAULT << 0)  /**< Shifted mode DEFAULT for CMU_LOCK */
-#define CMU_LOCK_LOCKKEY_LOCK                       (_CMU_LOCK_LOCKKEY_LOCK << 0)     /**< Shifted mode LOCK for CMU_LOCK */
-#define CMU_LOCK_LOCKKEY_UNLOCKED                   (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */
-#define CMU_LOCK_LOCKKEY_LOCKED                     (_CMU_LOCK_LOCKKEY_LOCKED << 0)   /**< Shifted mode LOCKED for CMU_LOCK */
-#define CMU_LOCK_LOCKKEY_UNLOCK                     (_CMU_LOCK_LOCKKEY_UNLOCK << 0)   /**< Shifted mode UNLOCK for CMU_LOCK */
-
-/** @} End of group EFM32LG990F256_CMU */
-
-
-
-/**************************************************************************//**
  * @defgroup EFM32LG990F256_UNLOCK EFM32LG990F256 Unlock Codes
  * @{
  *****************************************************************************/
@@ -1691,4 +477,4 @@
 #ifdef __cplusplus
 }
 #endif
-#endif /* __EFM32LG990F256_H */
+#endif /* EFM32LG990F256_H */

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_acmp.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_acmp.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32lg_acmp.h
  * @brief EFM32LG_ACMP register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32LG_ACMP
  * @{
  * @brief EFM32LG_ACMP Register Declaration
@@ -327,5 +331,5 @@
 #define ACMP_ROUTE_LOCATION_LOC2           (_ACMP_ROUTE_LOCATION_LOC2 << 8)    /**< Shifted mode LOC2 for ACMP_ROUTE */
 
 /** @} End of group EFM32LG_ACMP */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_adc.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_adc.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32lg_adc.h
  * @brief EFM32LG_ADC register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32LG_ADC
  * @{
  * @brief EFM32LG_ADC Register Declaration
@@ -666,5 +670,5 @@
 #define ADC_BIASPROG_COMPBIAS_DEFAULT           (_ADC_BIASPROG_COMPBIAS_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_BIASPROG */
 
 /** @} End of group EFM32LG_ADC */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_aes.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_aes.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32lg_aes.h
  * @brief EFM32LG_AES register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32LG_AES
  * @{
  * @brief EFM32LG_AES Register Declaration
@@ -235,5 +239,5 @@
 #define AES_KEYHD_KEYHD_DEFAULT         (_AES_KEYHD_KEYHD_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYHD */
 
 /** @} End of group EFM32LG_AES */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_af_pins.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_af_pins.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32lg_af_pins.h
  * @brief EFM32LG_AF_PINS register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32LG_AF_Pins
  * @{
  *****************************************************************************/
@@ -200,5 +204,5 @@
 #define AF_ETM_TD3_PIN(i)           ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 5 :  -1)
 
 /** @} End of group EFM32LG_AF_Pins */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_af_ports.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_af_ports.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32lg_af_ports.h
  * @brief EFM32LG_AF_PORTS register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32LG_AF_Ports
  * @{
  *****************************************************************************/
@@ -200,5 +204,5 @@
 #define AF_ETM_TD3_PORT(i)           ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 0 :  -1)
 
 /** @} End of group EFM32LG_AF_Ports */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_burtc.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_burtc.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32lg_burtc.h
  * @brief EFM32LG_BURTC register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32LG_BURTC
  * @{
  * @brief EFM32LG_BURTC Register Declaration
@@ -55,7 +59,6 @@
   __I uint32_t      SYNCBUSY;      /**< Synchronization Busy Register  */
 
   uint32_t          RESERVED0[48]; /**< Reserved registers */
-
   BURTC_RET_TypeDef RET[128];      /**< RetentionReg */
 } BURTC_TypeDef;                   /** @} */
 
@@ -373,5 +376,5 @@
 #define BURTC_RET_REG_REG_DEFAULT             (_BURTC_RET_REG_REG_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_RET_REG */
 
 /** @} End of group EFM32LG_BURTC */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_burtc_ret.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_burtc_ret.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32lg_burtc_ret.h
  * @brief EFM32LG_BURTC_RET register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @brief BURTC_RET EFM32LG BURTC RET
  *****************************************************************************/
 typedef struct
@@ -37,3 +41,6 @@
   __IO uint32_t REG; /**< Retention Register  */
 } BURTC_RET_TypeDef;
 
+/** @} End of group Parts */
+
+

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_calibrate.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_calibrate.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32lg_calibrate.h
  * @brief EFM32LG_CALIBRATE register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32LG_CALIBRATE
  * @{
  *****************************************************************************/
@@ -41,3 +45,6 @@
   __I uint32_t VALUE;   /**< Default value for calibration register */
 } CALIBRATE_TypeDef;    /** @} */
 
+/** @} End of group Parts */
+
+

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_cmu.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_cmu.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32lg_cmu.h
  * @brief EFM32LG_CMU register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32LG_CMU
  * @{
  * @brief EFM32LG_CMU Register Declaration
@@ -60,6 +64,7 @@
   __IO uint32_t LFACLKEN0;    /**< Low Frequency A Clock Enable Register 0  (Async Reg)  */
   uint32_t      RESERVED1[1]; /**< Reserved for future use **/
   __IO uint32_t LFBCLKEN0;    /**< Low Frequency B Clock Enable Register 0 (Async Reg)  */
+
   uint32_t      RESERVED2[1]; /**< Reserved for future use **/
   __IO uint32_t LFAPRESC0;    /**< Low Frequency A Prescaler Register 0 (Async Reg)  */
   uint32_t      RESERVED3[1]; /**< Reserved for future use **/
@@ -78,7 +83,7 @@
 
 /* Bit fields for CMU CTRL */
 #define _CMU_CTRL_RESETVALUE                        0x000C262CUL                                /**< Default value for CMU_CTRL */
-#define _CMU_CTRL_MASK                              0x53FFFEEFUL                                /**< Mask for CMU_CTRL */
+#define _CMU_CTRL_MASK                              0x57FFFEEFUL                                /**< Mask for CMU_CTRL */
 #define _CMU_CTRL_HFXOMODE_SHIFT                    0                                           /**< Shift value for CMU_HFXOMODE */
 #define _CMU_CTRL_HFXOMODE_MASK                     0x3UL                                       /**< Bit mask for CMU_HFXOMODE */
 #define _CMU_CTRL_HFXOMODE_DEFAULT                  0x00000000UL                                /**< Mode DEFAULT for CMU_CTRL */
@@ -187,7 +192,7 @@
 #define CMU_CTRL_CLKOUTSEL0_ULFRCO                  (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20)         /**< Shifted mode ULFRCO for CMU_CTRL */
 #define CMU_CTRL_CLKOUTSEL0_AUXHFRCO                (_CMU_CTRL_CLKOUTSEL0_AUXHFRCO << 20)       /**< Shifted mode AUXHFRCO for CMU_CTRL */
 #define _CMU_CTRL_CLKOUTSEL1_SHIFT                  23                                          /**< Shift value for CMU_CLKOUTSEL1 */
-#define _CMU_CTRL_CLKOUTSEL1_MASK                   0x3800000UL                                 /**< Bit mask for CMU_CLKOUTSEL1 */
+#define _CMU_CTRL_CLKOUTSEL1_MASK                   0x7800000UL                                 /**< Bit mask for CMU_CLKOUTSEL1 */
 #define _CMU_CTRL_CLKOUTSEL1_DEFAULT                0x00000000UL                                /**< Mode DEFAULT for CMU_CTRL */
 #define _CMU_CTRL_CLKOUTSEL1_LFRCO                  0x00000000UL                                /**< Mode LFRCO for CMU_CTRL */
 #define _CMU_CTRL_CLKOUTSEL1_LFXO                   0x00000001UL                                /**< Mode LFXO for CMU_CTRL */
@@ -454,7 +459,7 @@
 
 /* Bit fields for CMU CMD */
 #define _CMU_CMD_RESETVALUE                         0x00000000UL                          /**< Default value for CMU_CMD */
-#define _CMU_CMD_MASK                               0x0000007FUL                          /**< Mask for CMU_CMD */
+#define _CMU_CMD_MASK                               0x000000FFUL                          /**< Mask for CMU_CMD */
 #define _CMU_CMD_HFCLKSEL_SHIFT                     0                                     /**< Shift value for CMU_HFCLKSEL */
 #define _CMU_CMD_HFCLKSEL_MASK                      0x7UL                                 /**< Bit mask for CMU_HFCLKSEL */
 #define _CMU_CMD_HFCLKSEL_DEFAULT                   0x00000000UL                          /**< Mode DEFAULT for CMU_CMD */
@@ -478,7 +483,7 @@
 #define _CMU_CMD_CALSTOP_DEFAULT                    0x00000000UL                          /**< Mode DEFAULT for CMU_CMD */
 #define CMU_CMD_CALSTOP_DEFAULT                     (_CMU_CMD_CALSTOP_DEFAULT << 4)       /**< Shifted mode DEFAULT for CMU_CMD */
 #define _CMU_CMD_USBCCLKSEL_SHIFT                   5                                     /**< Shift value for CMU_USBCCLKSEL */
-#define _CMU_CMD_USBCCLKSEL_MASK                    0x60UL                                /**< Bit mask for CMU_USBCCLKSEL */
+#define _CMU_CMD_USBCCLKSEL_MASK                    0xE0UL                                /**< Bit mask for CMU_USBCCLKSEL */
 #define _CMU_CMD_USBCCLKSEL_DEFAULT                 0x00000000UL                          /**< Mode DEFAULT for CMU_CMD */
 #define _CMU_CMD_USBCCLKSEL_HFCLKNODIV              0x00000001UL                          /**< Mode HFCLKNODIV for CMU_CMD */
 #define _CMU_CMD_USBCCLKSEL_LFXO                    0x00000002UL                          /**< Mode LFXO for CMU_CMD */
@@ -1243,5 +1248,5 @@
 #define CMU_LOCK_LOCKKEY_UNLOCK                     (_CMU_LOCK_LOCKKEY_UNLOCK << 0)   /**< Shifted mode UNLOCK for CMU_LOCK */
 
 /** @} End of group EFM32LG_CMU */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_dac.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_dac.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32lg_dac.h
  * @brief EFM32LG_DAC register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32LG_DAC
  * @{
  * @brief EFM32LG_DAC Register Declaration
@@ -788,5 +792,5 @@
 #define DAC_OPA2MUX_RESSEL_RES7               (_DAC_OPA2MUX_RESSEL_RES7 << 28)     /**< Shifted mode RES7 for DAC_OPA2MUX */
 
 /** @} End of group EFM32LG_DAC */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_devinfo.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_devinfo.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32lg_devinfo.h
  * @brief EFM32LG_DEVINFO register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32LG_DEVINFO
  * @{
  *****************************************************************************/
@@ -140,15 +144,28 @@
 #define _DEVINFO_PART_PROD_REV_SHIFT               24           /**< Bit position for production revision */
 #define _DEVINFO_PART_DEVICE_FAMILY_MASK           0x00FF0000UL /**< Device Family, 0x47 for Gecko */
 #define _DEVINFO_PART_DEVICE_FAMILY_SHIFT          16           /**< Bit position for device family */
+/* Legacy family #defines */
 #define _DEVINFO_PART_DEVICE_FAMILY_G              71           /**< Gecko Device Family */
 #define _DEVINFO_PART_DEVICE_FAMILY_GG             72           /**< Giant Gecko Device Family */
 #define _DEVINFO_PART_DEVICE_FAMILY_TG             73           /**< Tiny Gecko Device Family */
 #define _DEVINFO_PART_DEVICE_FAMILY_LG             74           /**< Leopard Gecko Device Family */
 #define _DEVINFO_PART_DEVICE_FAMILY_WG             75           /**< Wonder Gecko Device Family */
 #define _DEVINFO_PART_DEVICE_FAMILY_ZG             76           /**< Zero Gecko Device Family */
+#define _DEVINFO_PART_DEVICE_FAMILY_HG             77           /**< Happy Gecko Device Family */
+/* New style family #defines */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFM32G         71           /**< Gecko Device Family */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFM32GG        72           /**< Giant Gecko Device Family */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFM32TG        73           /**< Tiny Gecko Device Family */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFM32LG        74           /**< Leopard Gecko Device Family */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFM32WG        75           /**< Wonder Gecko Device Family */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFM32ZG        76           /**< Zero Gecko Device Family */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFM32HG        77           /**< Happy Gecko Device Family */
+#define _DEVINFO_PART_DEVICE_FAMILY_EZR32WG        120          /**< EZR Wonder Gecko Device Family */
+#define _DEVINFO_PART_DEVICE_FAMILY_EZR32LG        121          /**< EZR Leopard Gecko Device Family */
+#define _DEVINFO_PART_DEVICE_FAMILY_EZR32HG        122          /**< EZR Happy Gecko Device Family */
 #define _DEVINFO_PART_DEVICE_NUMBER_MASK           0x0000FFFFUL /**< Device number */
 #define _DEVINFO_PART_DEVICE_NUMBER_SHIFT          0            /**< Bit position for device number */
 
 /** @} End of group EFM32LG_DEVINFO */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_dma.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_dma.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32lg_dma.h
  * @brief EFM32LG_DMA register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32LG_DMA
  * @{
  * @brief EFM32LG_DMA Register Declaration
@@ -75,7 +79,6 @@
   __IO uint32_t  RECT0;          /**< Channel 0 Rectangle Register  */
 
   uint32_t       RESERVED6[39];  /**< Reserved registers */
-
   DMA_CH_TypeDef CH[12];         /**< Channel registers */
 } DMA_TypeDef;                   /** @} */
 
@@ -1625,5 +1628,5 @@
 #define DMA_CH_CTRL_SOURCESEL_EBI                       (_DMA_CH_CTRL_SOURCESEL_EBI << 16)            /**< Shifted mode EBI for DMA_CH_CTRL */
 
 /** @} End of group EFM32LG_DMA */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_dma_ch.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_dma_ch.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32lg_dma_ch.h
  * @brief EFM32LG_DMA_CH register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @brief DMA_CH EFM32LG DMA CH
  *****************************************************************************/
 typedef struct
@@ -37,3 +41,6 @@
   __IO uint32_t CTRL; /**< Channel Control Register  */
 } DMA_CH_TypeDef;
 
+/** @} End of group Parts */
+
+

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_dma_descriptor.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_dma_descriptor.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32lg_dma_descriptor.h
  * @brief EFM32LG_DMA_DESCRIPTOR register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32LG_DMA_DESCRIPTOR
  * @{
  *****************************************************************************/
@@ -43,3 +47,6 @@
   __IO uint32_t    USER;       /**< DMA padding register, available for user */
 } DMA_DESCRIPTOR_TypeDef;      /** @} */
 
+/** @} End of group Parts */
+
+

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_dmactrl.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_dmactrl.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32lg_dmactrl.h
  * @brief EFM32LG_DMACTRL register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -29,6 +29,10 @@
  * any third party, arising from your use of this Software.
  *
  *****************************************************************************/
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
 
 /**************************************************************************//**
  * @defgroup EFM32LG_DMACTRL_BitFields
@@ -77,11 +81,11 @@
 #define _DMA_CTRL_DST_PROT_CTRL_MASK                   0x00E00000UL  /**< Protection flag for destination, bit mask */
 #define _DMA_CTRL_DST_PROT_CTRL_SHIFT                  21            /**< Protection flag for destination, shift value */
 #define DMA_CTRL_DST_PROT_PRIVILEGED                   0x00200000UL  /**< Privileged mode for destination */
-#define DMA_CTRL_DST_PROT_NON_PRIVILEGED               0x00000000UL  /**< Non-privileged mode for estination */
+#define DMA_CTRL_DST_PROT_NON_PRIVILEGED               0x00000000UL  /**< Non-privileged mode for destination */
 #define _DMA_CTRL_SRC_PROT_CTRL_MASK                   0x001C0000UL  /**< Protection flag for source, bit mask */
 #define _DMA_CTRL_SRC_PROT_CTRL_SHIFT                  18            /**< Protection flag for source, shift value */
 #define DMA_CTRL_SRC_PROT_PRIVILEGED                   0x00040000UL  /**< Privileged mode for destination */
-#define DMA_CTRL_SRC_PROT_NON_PRIVILEGED               0x00000000UL  /**< Non-privileged mode for estination */
+#define DMA_CTRL_SRC_PROT_NON_PRIVILEGED               0x00000000UL  /**< Non-privileged mode for destination */
 #define _DMA_CTRL_PROT_NON_PRIVILEGED                  0x00          /**< Protection bits to indicate non-privileged access */
 #define _DMA_CTRL_PROT_PRIVILEGED                      0x01          /**< Protection bits to indicate privileged access */
 #define _DMA_CTRL_R_POWER_MASK                         0x0003C000UL  /**< DMA arbitration mask */
@@ -132,5 +136,5 @@
 #define DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER_ALT     0x000000007UL /**< Peripheral scatter gather cycle type using alternate structure */
 
 /** @} End of group EFM32LG_DMA */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_dmareq.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_dmareq.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32lg_dmareq.h
  * @brief EFM32LG_DMAREQ register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -29,6 +29,10 @@
  * any third party, arising from your use of this Software.
  *
  *****************************************************************************/
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
 
 /**************************************************************************//**
  * @defgroup EFM32LG_DMAREQ_BitFields
@@ -95,5 +99,5 @@
 #define DMAREQ_EBI_DDEMPTY            ((51 << 16) + 3) /**< DMA channel select for EBI_DDEMPTY */
 
 /** @} End of group EFM32LG_DMAREQ */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_ebi.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_ebi.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32lg_ebi.h
  * @brief EFM32LG_EBI register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32LG_EBI
  * @{
  * @brief EFM32LG_EBI Register Declaration
@@ -1456,5 +1460,5 @@
 #define EBI_IEN_DDJIT_DEFAULT                     (_EBI_IEN_DDJIT_DEFAULT << 5)   /**< Shifted mode DEFAULT for EBI_IEN */
 
 /** @} End of group EFM32LG_EBI */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_emu.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_emu.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32lg_emu.h
  * @brief EFM32LG_EMU register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32LG_EMU
  * @{
  * @brief EFM32LG_EMU Register Declaration
@@ -66,279 +70,279 @@
  *****************************************************************************/
 
 /* Bit fields for EMU CTRL */
-#define _EMU_CTRL_RESETVALUE                 0x00000000UL                      /**< Default value for EMU_CTRL */
-#define _EMU_CTRL_MASK                       0x0000000FUL                      /**< Mask for EMU_CTRL */
-#define EMU_CTRL_EMVREG                      (0x1UL << 0)                      /**< Energy Mode Voltage Regulator Control */
-#define _EMU_CTRL_EMVREG_SHIFT               0                                 /**< Shift value for EMU_EMVREG */
-#define _EMU_CTRL_EMVREG_MASK                0x1UL                             /**< Bit mask for EMU_EMVREG */
-#define _EMU_CTRL_EMVREG_DEFAULT             0x00000000UL                      /**< Mode DEFAULT for EMU_CTRL */
-#define _EMU_CTRL_EMVREG_REDUCED             0x00000000UL                      /**< Mode REDUCED for EMU_CTRL */
-#define _EMU_CTRL_EMVREG_FULL                0x00000001UL                      /**< Mode FULL for EMU_CTRL */
-#define EMU_CTRL_EMVREG_DEFAULT              (_EMU_CTRL_EMVREG_DEFAULT << 0)   /**< Shifted mode DEFAULT for EMU_CTRL */
-#define EMU_CTRL_EMVREG_REDUCED              (_EMU_CTRL_EMVREG_REDUCED << 0)   /**< Shifted mode REDUCED for EMU_CTRL */
-#define EMU_CTRL_EMVREG_FULL                 (_EMU_CTRL_EMVREG_FULL << 0)      /**< Shifted mode FULL for EMU_CTRL */
-#define EMU_CTRL_EM2BLOCK                    (0x1UL << 1)                      /**< Energy Mode 2 Block */
-#define _EMU_CTRL_EM2BLOCK_SHIFT             1                                 /**< Shift value for EMU_EM2BLOCK */
-#define _EMU_CTRL_EM2BLOCK_MASK              0x2UL                             /**< Bit mask for EMU_EM2BLOCK */
-#define _EMU_CTRL_EM2BLOCK_DEFAULT           0x00000000UL                      /**< Mode DEFAULT for EMU_CTRL */
-#define EMU_CTRL_EM2BLOCK_DEFAULT            (_EMU_CTRL_EM2BLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_CTRL */
-#define _EMU_CTRL_EM4CTRL_SHIFT              2                                 /**< Shift value for EMU_EM4CTRL */
-#define _EMU_CTRL_EM4CTRL_MASK               0xCUL                             /**< Bit mask for EMU_EM4CTRL */
-#define _EMU_CTRL_EM4CTRL_DEFAULT            0x00000000UL                      /**< Mode DEFAULT for EMU_CTRL */
-#define EMU_CTRL_EM4CTRL_DEFAULT             (_EMU_CTRL_EM4CTRL_DEFAULT << 2)  /**< Shifted mode DEFAULT for EMU_CTRL */
+#define _EMU_CTRL_RESETVALUE                0x00000000UL                      /**< Default value for EMU_CTRL */
+#define _EMU_CTRL_MASK                      0x0000000FUL                      /**< Mask for EMU_CTRL */
+#define EMU_CTRL_EMVREG                     (0x1UL << 0)                      /**< Energy Mode Voltage Regulator Control */
+#define _EMU_CTRL_EMVREG_SHIFT              0                                 /**< Shift value for EMU_EMVREG */
+#define _EMU_CTRL_EMVREG_MASK               0x1UL                             /**< Bit mask for EMU_EMVREG */
+#define _EMU_CTRL_EMVREG_DEFAULT            0x00000000UL                      /**< Mode DEFAULT for EMU_CTRL */
+#define _EMU_CTRL_EMVREG_REDUCED            0x00000000UL                      /**< Mode REDUCED for EMU_CTRL */
+#define _EMU_CTRL_EMVREG_FULL               0x00000001UL                      /**< Mode FULL for EMU_CTRL */
+#define EMU_CTRL_EMVREG_DEFAULT             (_EMU_CTRL_EMVREG_DEFAULT << 0)   /**< Shifted mode DEFAULT for EMU_CTRL */
+#define EMU_CTRL_EMVREG_REDUCED             (_EMU_CTRL_EMVREG_REDUCED << 0)   /**< Shifted mode REDUCED for EMU_CTRL */
+#define EMU_CTRL_EMVREG_FULL                (_EMU_CTRL_EMVREG_FULL << 0)      /**< Shifted mode FULL for EMU_CTRL */
+#define EMU_CTRL_EM2BLOCK                   (0x1UL << 1)                      /**< Energy Mode 2 Block */
+#define _EMU_CTRL_EM2BLOCK_SHIFT            1                                 /**< Shift value for EMU_EM2BLOCK */
+#define _EMU_CTRL_EM2BLOCK_MASK             0x2UL                             /**< Bit mask for EMU_EM2BLOCK */
+#define _EMU_CTRL_EM2BLOCK_DEFAULT          0x00000000UL                      /**< Mode DEFAULT for EMU_CTRL */
+#define EMU_CTRL_EM2BLOCK_DEFAULT           (_EMU_CTRL_EM2BLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_CTRL */
+#define _EMU_CTRL_EM4CTRL_SHIFT             2                                 /**< Shift value for EMU_EM4CTRL */
+#define _EMU_CTRL_EM4CTRL_MASK              0xCUL                             /**< Bit mask for EMU_EM4CTRL */
+#define _EMU_CTRL_EM4CTRL_DEFAULT           0x00000000UL                      /**< Mode DEFAULT for EMU_CTRL */
+#define EMU_CTRL_EM4CTRL_DEFAULT            (_EMU_CTRL_EM4CTRL_DEFAULT << 2)  /**< Shifted mode DEFAULT for EMU_CTRL */
 
 /* Bit fields for EMU LOCK */
-#define _EMU_LOCK_RESETVALUE                 0x00000000UL                      /**< Default value for EMU_LOCK */
-#define _EMU_LOCK_MASK                       0x0000FFFFUL                      /**< Mask for EMU_LOCK */
-#define _EMU_LOCK_LOCKKEY_SHIFT              0                                 /**< Shift value for EMU_LOCKKEY */
-#define _EMU_LOCK_LOCKKEY_MASK               0xFFFFUL                          /**< Bit mask for EMU_LOCKKEY */
-#define _EMU_LOCK_LOCKKEY_DEFAULT            0x00000000UL                      /**< Mode DEFAULT for EMU_LOCK */
-#define _EMU_LOCK_LOCKKEY_LOCK               0x00000000UL                      /**< Mode LOCK for EMU_LOCK */
-#define _EMU_LOCK_LOCKKEY_UNLOCKED           0x00000000UL                      /**< Mode UNLOCKED for EMU_LOCK */
-#define _EMU_LOCK_LOCKKEY_LOCKED             0x00000001UL                      /**< Mode LOCKED for EMU_LOCK */
-#define _EMU_LOCK_LOCKKEY_UNLOCK             0x0000ADE8UL                      /**< Mode UNLOCK for EMU_LOCK */
-#define EMU_LOCK_LOCKKEY_DEFAULT             (_EMU_LOCK_LOCKKEY_DEFAULT << 0)  /**< Shifted mode DEFAULT for EMU_LOCK */
-#define EMU_LOCK_LOCKKEY_LOCK                (_EMU_LOCK_LOCKKEY_LOCK << 0)     /**< Shifted mode LOCK for EMU_LOCK */
-#define EMU_LOCK_LOCKKEY_UNLOCKED            (_EMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_LOCK */
-#define EMU_LOCK_LOCKKEY_LOCKED              (_EMU_LOCK_LOCKKEY_LOCKED << 0)   /**< Shifted mode LOCKED for EMU_LOCK */
-#define EMU_LOCK_LOCKKEY_UNLOCK              (_EMU_LOCK_LOCKKEY_UNLOCK << 0)   /**< Shifted mode UNLOCK for EMU_LOCK */
+#define _EMU_LOCK_RESETVALUE                0x00000000UL                      /**< Default value for EMU_LOCK */
+#define _EMU_LOCK_MASK                      0x0000FFFFUL                      /**< Mask for EMU_LOCK */
+#define _EMU_LOCK_LOCKKEY_SHIFT             0                                 /**< Shift value for EMU_LOCKKEY */
+#define _EMU_LOCK_LOCKKEY_MASK              0xFFFFUL                          /**< Bit mask for EMU_LOCKKEY */
+#define _EMU_LOCK_LOCKKEY_DEFAULT           0x00000000UL                      /**< Mode DEFAULT for EMU_LOCK */
+#define _EMU_LOCK_LOCKKEY_LOCK              0x00000000UL                      /**< Mode LOCK for EMU_LOCK */
+#define _EMU_LOCK_LOCKKEY_UNLOCKED          0x00000000UL                      /**< Mode UNLOCKED for EMU_LOCK */
+#define _EMU_LOCK_LOCKKEY_LOCKED            0x00000001UL                      /**< Mode LOCKED for EMU_LOCK */
+#define _EMU_LOCK_LOCKKEY_UNLOCK            0x0000ADE8UL                      /**< Mode UNLOCK for EMU_LOCK */
+#define EMU_LOCK_LOCKKEY_DEFAULT            (_EMU_LOCK_LOCKKEY_DEFAULT << 0)  /**< Shifted mode DEFAULT for EMU_LOCK */
+#define EMU_LOCK_LOCKKEY_LOCK               (_EMU_LOCK_LOCKKEY_LOCK << 0)     /**< Shifted mode LOCK for EMU_LOCK */
+#define EMU_LOCK_LOCKKEY_UNLOCKED           (_EMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_LOCK */
+#define EMU_LOCK_LOCKKEY_LOCKED             (_EMU_LOCK_LOCKKEY_LOCKED << 0)   /**< Shifted mode LOCKED for EMU_LOCK */
+#define EMU_LOCK_LOCKKEY_UNLOCK             (_EMU_LOCK_LOCKKEY_UNLOCK << 0)   /**< Shifted mode UNLOCK for EMU_LOCK */
 
 /* Bit fields for EMU AUXCTRL */
-#define _EMU_AUXCTRL_RESETVALUE              0x00000000UL                             /**< Default value for EMU_AUXCTRL */
-#define _EMU_AUXCTRL_MASK                    0x00000101UL                             /**< Mask for EMU_AUXCTRL */
-#define EMU_AUXCTRL_HRCCLR                   (0x1UL << 0)                             /**< Hard Reset Cause Clear */
-#define _EMU_AUXCTRL_HRCCLR_SHIFT            0                                        /**< Shift value for EMU_HRCCLR */
-#define _EMU_AUXCTRL_HRCCLR_MASK             0x1UL                                    /**< Bit mask for EMU_HRCCLR */
-#define _EMU_AUXCTRL_HRCCLR_DEFAULT          0x00000000UL                             /**< Mode DEFAULT for EMU_AUXCTRL */
-#define EMU_AUXCTRL_HRCCLR_DEFAULT           (_EMU_AUXCTRL_HRCCLR_DEFAULT << 0)       /**< Shifted mode DEFAULT for EMU_AUXCTRL */
-#define EMU_AUXCTRL_REDLFXOBOOST             (0x1UL << 8)                             /**< Reduce LFXO Start-up Boost Current */
-#define _EMU_AUXCTRL_REDLFXOBOOST_SHIFT      8                                        /**< Shift value for EMU_REDLFXOBOOST */
-#define _EMU_AUXCTRL_REDLFXOBOOST_MASK       0x100UL                                  /**< Bit mask for EMU_REDLFXOBOOST */
-#define _EMU_AUXCTRL_REDLFXOBOOST_DEFAULT    0x00000000UL                             /**< Mode DEFAULT for EMU_AUXCTRL */
-#define EMU_AUXCTRL_REDLFXOBOOST_DEFAULT     (_EMU_AUXCTRL_REDLFXOBOOST_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_AUXCTRL */
+#define _EMU_AUXCTRL_RESETVALUE             0x00000000UL                       /**< Default value for EMU_AUXCTRL */
+#define _EMU_AUXCTRL_MASK                   0x00000001UL                       /**< Mask for EMU_AUXCTRL */
+#define EMU_AUXCTRL_HRCCLR                  (0x1UL << 0)                       /**< Hard Reset Cause Clear */
+#define _EMU_AUXCTRL_HRCCLR_SHIFT           0                                  /**< Shift value for EMU_HRCCLR */
+#define _EMU_AUXCTRL_HRCCLR_MASK            0x1UL                              /**< Bit mask for EMU_HRCCLR */
+#define _EMU_AUXCTRL_HRCCLR_DEFAULT         0x00000000UL                       /**< Mode DEFAULT for EMU_AUXCTRL */
+#define EMU_AUXCTRL_HRCCLR_DEFAULT          (_EMU_AUXCTRL_HRCCLR_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_AUXCTRL */
 
 /* Bit fields for EMU EM4CONF */
-#define _EMU_EM4CONF_RESETVALUE              0x00000000UL                            /**< Default value for EMU_EM4CONF */
-#define _EMU_EM4CONF_MASK                    0x0001001FUL                            /**< Mask for EMU_EM4CONF */
-#define EMU_EM4CONF_VREGEN                   (0x1UL << 0)                            /**< EM4 voltage regulator enable */
-#define _EMU_EM4CONF_VREGEN_SHIFT            0                                       /**< Shift value for EMU_VREGEN */
-#define _EMU_EM4CONF_VREGEN_MASK             0x1UL                                   /**< Bit mask for EMU_VREGEN */
-#define _EMU_EM4CONF_VREGEN_DEFAULT          0x00000000UL                            /**< Mode DEFAULT for EMU_EM4CONF */
-#define EMU_EM4CONF_VREGEN_DEFAULT           (_EMU_EM4CONF_VREGEN_DEFAULT << 0)      /**< Shifted mode DEFAULT for EMU_EM4CONF */
-#define EMU_EM4CONF_BURTCWU                  (0x1UL << 1)                            /**< Backup RTC EM4 wakeup enable */
-#define _EMU_EM4CONF_BURTCWU_SHIFT           1                                       /**< Shift value for EMU_BURTCWU */
-#define _EMU_EM4CONF_BURTCWU_MASK            0x2UL                                   /**< Bit mask for EMU_BURTCWU */
-#define _EMU_EM4CONF_BURTCWU_DEFAULT         0x00000000UL                            /**< Mode DEFAULT for EMU_EM4CONF */
-#define EMU_EM4CONF_BURTCWU_DEFAULT          (_EMU_EM4CONF_BURTCWU_DEFAULT << 1)     /**< Shifted mode DEFAULT for EMU_EM4CONF */
-#define _EMU_EM4CONF_OSC_SHIFT               2                                       /**< Shift value for EMU_OSC */
-#define _EMU_EM4CONF_OSC_MASK                0xCUL                                   /**< Bit mask for EMU_OSC */
-#define _EMU_EM4CONF_OSC_DEFAULT             0x00000000UL                            /**< Mode DEFAULT for EMU_EM4CONF */
-#define _EMU_EM4CONF_OSC_ULFRCO              0x00000000UL                            /**< Mode ULFRCO for EMU_EM4CONF */
-#define _EMU_EM4CONF_OSC_LFRCO               0x00000001UL                            /**< Mode LFRCO for EMU_EM4CONF */
-#define _EMU_EM4CONF_OSC_LFXO                0x00000002UL                            /**< Mode LFXO for EMU_EM4CONF */
-#define EMU_EM4CONF_OSC_DEFAULT              (_EMU_EM4CONF_OSC_DEFAULT << 2)         /**< Shifted mode DEFAULT for EMU_EM4CONF */
-#define EMU_EM4CONF_OSC_ULFRCO               (_EMU_EM4CONF_OSC_ULFRCO << 2)          /**< Shifted mode ULFRCO for EMU_EM4CONF */
-#define EMU_EM4CONF_OSC_LFRCO                (_EMU_EM4CONF_OSC_LFRCO << 2)           /**< Shifted mode LFRCO for EMU_EM4CONF */
-#define EMU_EM4CONF_OSC_LFXO                 (_EMU_EM4CONF_OSC_LFXO << 2)            /**< Shifted mode LFXO for EMU_EM4CONF */
-#define EMU_EM4CONF_BUBODRSTDIS              (0x1UL << 4)                            /**< Disable reset from Backup BOD in EM4 */
-#define _EMU_EM4CONF_BUBODRSTDIS_SHIFT       4                                       /**< Shift value for EMU_BUBODRSTDIS */
-#define _EMU_EM4CONF_BUBODRSTDIS_MASK        0x10UL                                  /**< Bit mask for EMU_BUBODRSTDIS */
-#define _EMU_EM4CONF_BUBODRSTDIS_DEFAULT     0x00000000UL                            /**< Mode DEFAULT for EMU_EM4CONF */
-#define EMU_EM4CONF_BUBODRSTDIS_DEFAULT      (_EMU_EM4CONF_BUBODRSTDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM4CONF */
-#define EMU_EM4CONF_LOCKCONF                 (0x1UL << 16)                           /**< EM4 configuration lock enable */
-#define _EMU_EM4CONF_LOCKCONF_SHIFT          16                                      /**< Shift value for EMU_LOCKCONF */
-#define _EMU_EM4CONF_LOCKCONF_MASK           0x10000UL                               /**< Bit mask for EMU_LOCKCONF */
-#define _EMU_EM4CONF_LOCKCONF_DEFAULT        0x00000000UL                            /**< Mode DEFAULT for EMU_EM4CONF */
-#define EMU_EM4CONF_LOCKCONF_DEFAULT         (_EMU_EM4CONF_LOCKCONF_DEFAULT << 16)   /**< Shifted mode DEFAULT for EMU_EM4CONF */
+#define _EMU_EM4CONF_RESETVALUE             0x00000000UL                            /**< Default value for EMU_EM4CONF */
+#define _EMU_EM4CONF_MASK                   0x0001001FUL                            /**< Mask for EMU_EM4CONF */
+#define EMU_EM4CONF_VREGEN                  (0x1UL << 0)                            /**< EM4 voltage regulator enable */
+#define _EMU_EM4CONF_VREGEN_SHIFT           0                                       /**< Shift value for EMU_VREGEN */
+#define _EMU_EM4CONF_VREGEN_MASK            0x1UL                                   /**< Bit mask for EMU_VREGEN */
+#define _EMU_EM4CONF_VREGEN_DEFAULT         0x00000000UL                            /**< Mode DEFAULT for EMU_EM4CONF */
+#define EMU_EM4CONF_VREGEN_DEFAULT          (_EMU_EM4CONF_VREGEN_DEFAULT << 0)      /**< Shifted mode DEFAULT for EMU_EM4CONF */
+#define EMU_EM4CONF_BURTCWU                 (0x1UL << 1)                            /**< Backup RTC EM4 wakeup enable */
+#define _EMU_EM4CONF_BURTCWU_SHIFT          1                                       /**< Shift value for EMU_BURTCWU */
+#define _EMU_EM4CONF_BURTCWU_MASK           0x2UL                                   /**< Bit mask for EMU_BURTCWU */
+#define _EMU_EM4CONF_BURTCWU_DEFAULT        0x00000000UL                            /**< Mode DEFAULT for EMU_EM4CONF */
+#define EMU_EM4CONF_BURTCWU_DEFAULT         (_EMU_EM4CONF_BURTCWU_DEFAULT << 1)     /**< Shifted mode DEFAULT for EMU_EM4CONF */
+#define _EMU_EM4CONF_OSC_SHIFT              2                                       /**< Shift value for EMU_OSC */
+#define _EMU_EM4CONF_OSC_MASK               0xCUL                                   /**< Bit mask for EMU_OSC */
+#define _EMU_EM4CONF_OSC_DEFAULT            0x00000000UL                            /**< Mode DEFAULT for EMU_EM4CONF */
+#define _EMU_EM4CONF_OSC_ULFRCO             0x00000000UL                            /**< Mode ULFRCO for EMU_EM4CONF */
+#define _EMU_EM4CONF_OSC_LFRCO              0x00000001UL                            /**< Mode LFRCO for EMU_EM4CONF */
+#define _EMU_EM4CONF_OSC_LFXO               0x00000002UL                            /**< Mode LFXO for EMU_EM4CONF */
+#define EMU_EM4CONF_OSC_DEFAULT             (_EMU_EM4CONF_OSC_DEFAULT << 2)         /**< Shifted mode DEFAULT for EMU_EM4CONF */
+#define EMU_EM4CONF_OSC_ULFRCO              (_EMU_EM4CONF_OSC_ULFRCO << 2)          /**< Shifted mode ULFRCO for EMU_EM4CONF */
+#define EMU_EM4CONF_OSC_LFRCO               (_EMU_EM4CONF_OSC_LFRCO << 2)           /**< Shifted mode LFRCO for EMU_EM4CONF */
+#define EMU_EM4CONF_OSC_LFXO                (_EMU_EM4CONF_OSC_LFXO << 2)            /**< Shifted mode LFXO for EMU_EM4CONF */
+#define EMU_EM4CONF_BUBODRSTDIS             (0x1UL << 4)                            /**< Disable reset from Backup BOD in EM4 */
+#define _EMU_EM4CONF_BUBODRSTDIS_SHIFT      4                                       /**< Shift value for EMU_BUBODRSTDIS */
+#define _EMU_EM4CONF_BUBODRSTDIS_MASK       0x10UL                                  /**< Bit mask for EMU_BUBODRSTDIS */
+#define _EMU_EM4CONF_BUBODRSTDIS_DEFAULT    0x00000000UL                            /**< Mode DEFAULT for EMU_EM4CONF */
+#define EMU_EM4CONF_BUBODRSTDIS_DEFAULT     (_EMU_EM4CONF_BUBODRSTDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM4CONF */
+#define EMU_EM4CONF_LOCKCONF                (0x1UL << 16)                           /**< EM4 configuration lock enable */
+#define _EMU_EM4CONF_LOCKCONF_SHIFT         16                                      /**< Shift value for EMU_LOCKCONF */
+#define _EMU_EM4CONF_LOCKCONF_MASK          0x10000UL                               /**< Bit mask for EMU_LOCKCONF */
+#define _EMU_EM4CONF_LOCKCONF_DEFAULT       0x00000000UL                            /**< Mode DEFAULT for EMU_EM4CONF */
+#define EMU_EM4CONF_LOCKCONF_DEFAULT        (_EMU_EM4CONF_LOCKCONF_DEFAULT << 16)   /**< Shifted mode DEFAULT for EMU_EM4CONF */
 
 /* Bit fields for EMU BUCTRL */
-#define _EMU_BUCTRL_RESETVALUE               0x00000000UL                      /**< Default value for EMU_BUCTRL */
-#define _EMU_BUCTRL_MASK                     0x00000067UL                      /**< Mask for EMU_BUCTRL */
-#define EMU_BUCTRL_EN                        (0x1UL << 0)                      /**< Enable backup mode */
-#define _EMU_BUCTRL_EN_SHIFT                 0                                 /**< Shift value for EMU_EN */
-#define _EMU_BUCTRL_EN_MASK                  0x1UL                             /**< Bit mask for EMU_EN */
-#define _EMU_BUCTRL_EN_DEFAULT               0x00000000UL                      /**< Mode DEFAULT for EMU_BUCTRL */
-#define EMU_BUCTRL_EN_DEFAULT                (_EMU_BUCTRL_EN_DEFAULT << 0)     /**< Shifted mode DEFAULT for EMU_BUCTRL */
-#define EMU_BUCTRL_STATEN                    (0x1UL << 1)                      /**< Enable backup mode status export */
-#define _EMU_BUCTRL_STATEN_SHIFT             1                                 /**< Shift value for EMU_STATEN */
-#define _EMU_BUCTRL_STATEN_MASK              0x2UL                             /**< Bit mask for EMU_STATEN */
-#define _EMU_BUCTRL_STATEN_DEFAULT           0x00000000UL                      /**< Mode DEFAULT for EMU_BUCTRL */
-#define EMU_BUCTRL_STATEN_DEFAULT            (_EMU_BUCTRL_STATEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_BUCTRL */
-#define EMU_BUCTRL_BODCAL                    (0x1UL << 2)                      /**< Enable BOD calibration mode */
-#define _EMU_BUCTRL_BODCAL_SHIFT             2                                 /**< Shift value for EMU_BODCAL */
-#define _EMU_BUCTRL_BODCAL_MASK              0x4UL                             /**< Bit mask for EMU_BODCAL */
-#define _EMU_BUCTRL_BODCAL_DEFAULT           0x00000000UL                      /**< Mode DEFAULT for EMU_BUCTRL */
-#define EMU_BUCTRL_BODCAL_DEFAULT            (_EMU_BUCTRL_BODCAL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_BUCTRL */
-#define _EMU_BUCTRL_PROBE_SHIFT              5                                 /**< Shift value for EMU_PROBE */
-#define _EMU_BUCTRL_PROBE_MASK               0x60UL                            /**< Bit mask for EMU_PROBE */
-#define _EMU_BUCTRL_PROBE_DEFAULT            0x00000000UL                      /**< Mode DEFAULT for EMU_BUCTRL */
-#define _EMU_BUCTRL_PROBE_DISABLE            0x00000000UL                      /**< Mode DISABLE for EMU_BUCTRL */
-#define _EMU_BUCTRL_PROBE_VDDDREG            0x00000001UL                      /**< Mode VDDDREG for EMU_BUCTRL */
-#define _EMU_BUCTRL_PROBE_BUIN               0x00000002UL                      /**< Mode BUIN for EMU_BUCTRL */
-#define _EMU_BUCTRL_PROBE_BUOUT              0x00000003UL                      /**< Mode BUOUT for EMU_BUCTRL */
-#define EMU_BUCTRL_PROBE_DEFAULT             (_EMU_BUCTRL_PROBE_DEFAULT << 5)  /**< Shifted mode DEFAULT for EMU_BUCTRL */
-#define EMU_BUCTRL_PROBE_DISABLE             (_EMU_BUCTRL_PROBE_DISABLE << 5)  /**< Shifted mode DISABLE for EMU_BUCTRL */
-#define EMU_BUCTRL_PROBE_VDDDREG             (_EMU_BUCTRL_PROBE_VDDDREG << 5)  /**< Shifted mode VDDDREG for EMU_BUCTRL */
-#define EMU_BUCTRL_PROBE_BUIN                (_EMU_BUCTRL_PROBE_BUIN << 5)     /**< Shifted mode BUIN for EMU_BUCTRL */
-#define EMU_BUCTRL_PROBE_BUOUT               (_EMU_BUCTRL_PROBE_BUOUT << 5)    /**< Shifted mode BUOUT for EMU_BUCTRL */
+#define _EMU_BUCTRL_RESETVALUE              0x00000000UL                           /**< Default value for EMU_BUCTRL */
+#define _EMU_BUCTRL_MASK                    0x0000006FUL                           /**< Mask for EMU_BUCTRL */
+#define EMU_BUCTRL_EN                       (0x1UL << 0)                           /**< Enable backup mode */
+#define _EMU_BUCTRL_EN_SHIFT                0                                      /**< Shift value for EMU_EN */
+#define _EMU_BUCTRL_EN_MASK                 0x1UL                                  /**< Bit mask for EMU_EN */
+#define _EMU_BUCTRL_EN_DEFAULT              0x00000000UL                           /**< Mode DEFAULT for EMU_BUCTRL */
+#define EMU_BUCTRL_EN_DEFAULT               (_EMU_BUCTRL_EN_DEFAULT << 0)          /**< Shifted mode DEFAULT for EMU_BUCTRL */
+#define EMU_BUCTRL_STATEN                   (0x1UL << 1)                           /**< Enable backup mode status export */
+#define _EMU_BUCTRL_STATEN_SHIFT            1                                      /**< Shift value for EMU_STATEN */
+#define _EMU_BUCTRL_STATEN_MASK             0x2UL                                  /**< Bit mask for EMU_STATEN */
+#define _EMU_BUCTRL_STATEN_DEFAULT          0x00000000UL                           /**< Mode DEFAULT for EMU_BUCTRL */
+#define EMU_BUCTRL_STATEN_DEFAULT           (_EMU_BUCTRL_STATEN_DEFAULT << 1)      /**< Shifted mode DEFAULT for EMU_BUCTRL */
+#define EMU_BUCTRL_BODCAL                   (0x1UL << 2)                           /**< Enable BOD calibration mode */
+#define _EMU_BUCTRL_BODCAL_SHIFT            2                                      /**< Shift value for EMU_BODCAL */
+#define _EMU_BUCTRL_BODCAL_MASK             0x4UL                                  /**< Bit mask for EMU_BODCAL */
+#define _EMU_BUCTRL_BODCAL_DEFAULT          0x00000000UL                           /**< Mode DEFAULT for EMU_BUCTRL */
+#define EMU_BUCTRL_BODCAL_DEFAULT           (_EMU_BUCTRL_BODCAL_DEFAULT << 2)      /**< Shifted mode DEFAULT for EMU_BUCTRL */
+#define EMU_BUCTRL_BUMODEBODEN              (0x1UL << 3)                           /**< Enable brown out detection on BU_VIN when in backup mode */
+#define _EMU_BUCTRL_BUMODEBODEN_SHIFT       3                                      /**< Shift value for EMU_BUMODEBODEN */
+#define _EMU_BUCTRL_BUMODEBODEN_MASK        0x8UL                                  /**< Bit mask for EMU_BUMODEBODEN */
+#define _EMU_BUCTRL_BUMODEBODEN_DEFAULT     0x00000000UL                           /**< Mode DEFAULT for EMU_BUCTRL */
+#define EMU_BUCTRL_BUMODEBODEN_DEFAULT      (_EMU_BUCTRL_BUMODEBODEN_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_BUCTRL */
+#define _EMU_BUCTRL_PROBE_SHIFT             5                                      /**< Shift value for EMU_PROBE */
+#define _EMU_BUCTRL_PROBE_MASK              0x60UL                                 /**< Bit mask for EMU_PROBE */
+#define _EMU_BUCTRL_PROBE_DEFAULT           0x00000000UL                           /**< Mode DEFAULT for EMU_BUCTRL */
+#define _EMU_BUCTRL_PROBE_DISABLE           0x00000000UL                           /**< Mode DISABLE for EMU_BUCTRL */
+#define _EMU_BUCTRL_PROBE_VDDDREG           0x00000001UL                           /**< Mode VDDDREG for EMU_BUCTRL */
+#define _EMU_BUCTRL_PROBE_BUIN              0x00000002UL                           /**< Mode BUIN for EMU_BUCTRL */
+#define _EMU_BUCTRL_PROBE_BUOUT             0x00000003UL                           /**< Mode BUOUT for EMU_BUCTRL */
+#define EMU_BUCTRL_PROBE_DEFAULT            (_EMU_BUCTRL_PROBE_DEFAULT << 5)       /**< Shifted mode DEFAULT for EMU_BUCTRL */
+#define EMU_BUCTRL_PROBE_DISABLE            (_EMU_BUCTRL_PROBE_DISABLE << 5)       /**< Shifted mode DISABLE for EMU_BUCTRL */
+#define EMU_BUCTRL_PROBE_VDDDREG            (_EMU_BUCTRL_PROBE_VDDDREG << 5)       /**< Shifted mode VDDDREG for EMU_BUCTRL */
+#define EMU_BUCTRL_PROBE_BUIN               (_EMU_BUCTRL_PROBE_BUIN << 5)          /**< Shifted mode BUIN for EMU_BUCTRL */
+#define EMU_BUCTRL_PROBE_BUOUT              (_EMU_BUCTRL_PROBE_BUOUT << 5)         /**< Shifted mode BUOUT for EMU_BUCTRL */
 
 /* Bit fields for EMU PWRCONF */
-#define _EMU_PWRCONF_RESETVALUE              0x00000000UL                           /**< Default value for EMU_PWRCONF */
-#define _EMU_PWRCONF_MASK                    0x0000001FUL                           /**< Mask for EMU_PWRCONF */
-#define EMU_PWRCONF_VOUTWEAK                 (0x1UL << 0)                           /**< BU_VOUT weak enable */
-#define _EMU_PWRCONF_VOUTWEAK_SHIFT          0                                      /**< Shift value for EMU_VOUTWEAK */
-#define _EMU_PWRCONF_VOUTWEAK_MASK           0x1UL                                  /**< Bit mask for EMU_VOUTWEAK */
-#define _EMU_PWRCONF_VOUTWEAK_DEFAULT        0x00000000UL                           /**< Mode DEFAULT for EMU_PWRCONF */
-#define EMU_PWRCONF_VOUTWEAK_DEFAULT         (_EMU_PWRCONF_VOUTWEAK_DEFAULT << 0)   /**< Shifted mode DEFAULT for EMU_PWRCONF */
-#define EMU_PWRCONF_VOUTMED                  (0x1UL << 1)                           /**< BU_VOUT medium enable */
-#define _EMU_PWRCONF_VOUTMED_SHIFT           1                                      /**< Shift value for EMU_VOUTMED */
-#define _EMU_PWRCONF_VOUTMED_MASK            0x2UL                                  /**< Bit mask for EMU_VOUTMED */
-#define _EMU_PWRCONF_VOUTMED_DEFAULT         0x00000000UL                           /**< Mode DEFAULT for EMU_PWRCONF */
-#define EMU_PWRCONF_VOUTMED_DEFAULT          (_EMU_PWRCONF_VOUTMED_DEFAULT << 1)    /**< Shifted mode DEFAULT for EMU_PWRCONF */
-#define EMU_PWRCONF_VOUTSTRONG               (0x1UL << 2)                           /**< BU_VOUT strong enable */
-#define _EMU_PWRCONF_VOUTSTRONG_SHIFT        2                                      /**< Shift value for EMU_VOUTSTRONG */
-#define _EMU_PWRCONF_VOUTSTRONG_MASK         0x4UL                                  /**< Bit mask for EMU_VOUTSTRONG */
-#define _EMU_PWRCONF_VOUTSTRONG_DEFAULT      0x00000000UL                           /**< Mode DEFAULT for EMU_PWRCONF */
-#define EMU_PWRCONF_VOUTSTRONG_DEFAULT       (_EMU_PWRCONF_VOUTSTRONG_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_PWRCONF */
-#define _EMU_PWRCONF_PWRRES_SHIFT            3                                      /**< Shift value for EMU_PWRRES */
-#define _EMU_PWRCONF_PWRRES_MASK             0x18UL                                 /**< Bit mask for EMU_PWRRES */
-#define _EMU_PWRCONF_PWRRES_DEFAULT          0x00000000UL                           /**< Mode DEFAULT for EMU_PWRCONF */
-#define _EMU_PWRCONF_PWRRES_RES0             0x00000000UL                           /**< Mode RES0 for EMU_PWRCONF */
-#define _EMU_PWRCONF_PWRRES_RES1             0x00000001UL                           /**< Mode RES1 for EMU_PWRCONF */
-#define _EMU_PWRCONF_PWRRES_RES2             0x00000002UL                           /**< Mode RES2 for EMU_PWRCONF */
-#define _EMU_PWRCONF_PWRRES_RES3             0x00000003UL                           /**< Mode RES3 for EMU_PWRCONF */
-#define EMU_PWRCONF_PWRRES_DEFAULT           (_EMU_PWRCONF_PWRRES_DEFAULT << 3)     /**< Shifted mode DEFAULT for EMU_PWRCONF */
-#define EMU_PWRCONF_PWRRES_RES0              (_EMU_PWRCONF_PWRRES_RES0 << 3)        /**< Shifted mode RES0 for EMU_PWRCONF */
-#define EMU_PWRCONF_PWRRES_RES1              (_EMU_PWRCONF_PWRRES_RES1 << 3)        /**< Shifted mode RES1 for EMU_PWRCONF */
-#define EMU_PWRCONF_PWRRES_RES2              (_EMU_PWRCONF_PWRRES_RES2 << 3)        /**< Shifted mode RES2 for EMU_PWRCONF */
-#define EMU_PWRCONF_PWRRES_RES3              (_EMU_PWRCONF_PWRRES_RES3 << 3)        /**< Shifted mode RES3 for EMU_PWRCONF */
+#define _EMU_PWRCONF_RESETVALUE             0x00000000UL                           /**< Default value for EMU_PWRCONF */
+#define _EMU_PWRCONF_MASK                   0x0000001FUL                           /**< Mask for EMU_PWRCONF */
+#define EMU_PWRCONF_VOUTWEAK                (0x1UL << 0)                           /**< BU_VOUT weak enable */
+#define _EMU_PWRCONF_VOUTWEAK_SHIFT         0                                      /**< Shift value for EMU_VOUTWEAK */
+#define _EMU_PWRCONF_VOUTWEAK_MASK          0x1UL                                  /**< Bit mask for EMU_VOUTWEAK */
+#define _EMU_PWRCONF_VOUTWEAK_DEFAULT       0x00000000UL                           /**< Mode DEFAULT for EMU_PWRCONF */
+#define EMU_PWRCONF_VOUTWEAK_DEFAULT        (_EMU_PWRCONF_VOUTWEAK_DEFAULT << 0)   /**< Shifted mode DEFAULT for EMU_PWRCONF */
+#define EMU_PWRCONF_VOUTMED                 (0x1UL << 1)                           /**< BU_VOUT medium enable */
+#define _EMU_PWRCONF_VOUTMED_SHIFT          1                                      /**< Shift value for EMU_VOUTMED */
+#define _EMU_PWRCONF_VOUTMED_MASK           0x2UL                                  /**< Bit mask for EMU_VOUTMED */
+#define _EMU_PWRCONF_VOUTMED_DEFAULT        0x00000000UL                           /**< Mode DEFAULT for EMU_PWRCONF */
+#define EMU_PWRCONF_VOUTMED_DEFAULT         (_EMU_PWRCONF_VOUTMED_DEFAULT << 1)    /**< Shifted mode DEFAULT for EMU_PWRCONF */
+#define EMU_PWRCONF_VOUTSTRONG              (0x1UL << 2)                           /**< BU_VOUT strong enable */
+#define _EMU_PWRCONF_VOUTSTRONG_SHIFT       2                                      /**< Shift value for EMU_VOUTSTRONG */
+#define _EMU_PWRCONF_VOUTSTRONG_MASK        0x4UL                                  /**< Bit mask for EMU_VOUTSTRONG */
+#define _EMU_PWRCONF_VOUTSTRONG_DEFAULT     0x00000000UL                           /**< Mode DEFAULT for EMU_PWRCONF */
+#define EMU_PWRCONF_VOUTSTRONG_DEFAULT      (_EMU_PWRCONF_VOUTSTRONG_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_PWRCONF */
+#define _EMU_PWRCONF_PWRRES_SHIFT           3                                      /**< Shift value for EMU_PWRRES */
+#define _EMU_PWRCONF_PWRRES_MASK            0x18UL                                 /**< Bit mask for EMU_PWRRES */
+#define _EMU_PWRCONF_PWRRES_DEFAULT         0x00000000UL                           /**< Mode DEFAULT for EMU_PWRCONF */
+#define _EMU_PWRCONF_PWRRES_RES0            0x00000000UL                           /**< Mode RES0 for EMU_PWRCONF */
+#define _EMU_PWRCONF_PWRRES_RES1            0x00000001UL                           /**< Mode RES1 for EMU_PWRCONF */
+#define _EMU_PWRCONF_PWRRES_RES2            0x00000002UL                           /**< Mode RES2 for EMU_PWRCONF */
+#define _EMU_PWRCONF_PWRRES_RES3            0x00000003UL                           /**< Mode RES3 for EMU_PWRCONF */
+#define EMU_PWRCONF_PWRRES_DEFAULT          (_EMU_PWRCONF_PWRRES_DEFAULT << 3)     /**< Shifted mode DEFAULT for EMU_PWRCONF */
+#define EMU_PWRCONF_PWRRES_RES0             (_EMU_PWRCONF_PWRRES_RES0 << 3)        /**< Shifted mode RES0 for EMU_PWRCONF */
+#define EMU_PWRCONF_PWRRES_RES1             (_EMU_PWRCONF_PWRRES_RES1 << 3)        /**< Shifted mode RES1 for EMU_PWRCONF */
+#define EMU_PWRCONF_PWRRES_RES2             (_EMU_PWRCONF_PWRRES_RES2 << 3)        /**< Shifted mode RES2 for EMU_PWRCONF */
+#define EMU_PWRCONF_PWRRES_RES3             (_EMU_PWRCONF_PWRRES_RES3 << 3)        /**< Shifted mode RES3 for EMU_PWRCONF */
 
 /* Bit fields for EMU BUINACT */
-#define _EMU_BUINACT_RESETVALUE              0x0000000BUL                          /**< Default value for EMU_BUINACT */
-#define _EMU_BUINACT_MASK                    0x0000007FUL                          /**< Mask for EMU_BUINACT */
-#define _EMU_BUINACT_BUENTHRES_SHIFT         0                                     /**< Shift value for EMU_BUENTHRES */
-#define _EMU_BUINACT_BUENTHRES_MASK          0x7UL                                 /**< Bit mask for EMU_BUENTHRES */
-#define _EMU_BUINACT_BUENTHRES_DEFAULT       0x00000003UL                          /**< Mode DEFAULT for EMU_BUINACT */
-#define EMU_BUINACT_BUENTHRES_DEFAULT        (_EMU_BUINACT_BUENTHRES_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_BUINACT */
-#define _EMU_BUINACT_BUENRANGE_SHIFT         3                                     /**< Shift value for EMU_BUENRANGE */
-#define _EMU_BUINACT_BUENRANGE_MASK          0x18UL                                /**< Bit mask for EMU_BUENRANGE */
-#define _EMU_BUINACT_BUENRANGE_DEFAULT       0x00000001UL                          /**< Mode DEFAULT for EMU_BUINACT */
-#define EMU_BUINACT_BUENRANGE_DEFAULT        (_EMU_BUINACT_BUENRANGE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_BUINACT */
-#define _EMU_BUINACT_PWRCON_SHIFT            5                                     /**< Shift value for EMU_PWRCON */
-#define _EMU_BUINACT_PWRCON_MASK             0x60UL                                /**< Bit mask for EMU_PWRCON */
-#define _EMU_BUINACT_PWRCON_DEFAULT          0x00000000UL                          /**< Mode DEFAULT for EMU_BUINACT */
-#define _EMU_BUINACT_PWRCON_NONE             0x00000000UL                          /**< Mode NONE for EMU_BUINACT */
-#define _EMU_BUINACT_PWRCON_BUMAIN           0x00000001UL                          /**< Mode BUMAIN for EMU_BUINACT */
-#define _EMU_BUINACT_PWRCON_MAINBU           0x00000002UL                          /**< Mode MAINBU for EMU_BUINACT */
-#define _EMU_BUINACT_PWRCON_NODIODE          0x00000003UL                          /**< Mode NODIODE for EMU_BUINACT */
-#define EMU_BUINACT_PWRCON_DEFAULT           (_EMU_BUINACT_PWRCON_DEFAULT << 5)    /**< Shifted mode DEFAULT for EMU_BUINACT */
-#define EMU_BUINACT_PWRCON_NONE              (_EMU_BUINACT_PWRCON_NONE << 5)       /**< Shifted mode NONE for EMU_BUINACT */
-#define EMU_BUINACT_PWRCON_BUMAIN            (_EMU_BUINACT_PWRCON_BUMAIN << 5)     /**< Shifted mode BUMAIN for EMU_BUINACT */
-#define EMU_BUINACT_PWRCON_MAINBU            (_EMU_BUINACT_PWRCON_MAINBU << 5)     /**< Shifted mode MAINBU for EMU_BUINACT */
-#define EMU_BUINACT_PWRCON_NODIODE           (_EMU_BUINACT_PWRCON_NODIODE << 5)    /**< Shifted mode NODIODE for EMU_BUINACT */
+#define _EMU_BUINACT_RESETVALUE             0x0000000BUL                          /**< Default value for EMU_BUINACT */
+#define _EMU_BUINACT_MASK                   0x0000007FUL                          /**< Mask for EMU_BUINACT */
+#define _EMU_BUINACT_BUENTHRES_SHIFT        0                                     /**< Shift value for EMU_BUENTHRES */
+#define _EMU_BUINACT_BUENTHRES_MASK         0x7UL                                 /**< Bit mask for EMU_BUENTHRES */
+#define _EMU_BUINACT_BUENTHRES_DEFAULT      0x00000003UL                          /**< Mode DEFAULT for EMU_BUINACT */
+#define EMU_BUINACT_BUENTHRES_DEFAULT       (_EMU_BUINACT_BUENTHRES_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_BUINACT */
+#define _EMU_BUINACT_BUENRANGE_SHIFT        3                                     /**< Shift value for EMU_BUENRANGE */
+#define _EMU_BUINACT_BUENRANGE_MASK         0x18UL                                /**< Bit mask for EMU_BUENRANGE */
+#define _EMU_BUINACT_BUENRANGE_DEFAULT      0x00000001UL                          /**< Mode DEFAULT for EMU_BUINACT */
+#define EMU_BUINACT_BUENRANGE_DEFAULT       (_EMU_BUINACT_BUENRANGE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_BUINACT */
+#define _EMU_BUINACT_PWRCON_SHIFT           5                                     /**< Shift value for EMU_PWRCON */
+#define _EMU_BUINACT_PWRCON_MASK            0x60UL                                /**< Bit mask for EMU_PWRCON */
+#define _EMU_BUINACT_PWRCON_DEFAULT         0x00000000UL                          /**< Mode DEFAULT for EMU_BUINACT */
+#define _EMU_BUINACT_PWRCON_NONE            0x00000000UL                          /**< Mode NONE for EMU_BUINACT */
+#define _EMU_BUINACT_PWRCON_BUMAIN          0x00000001UL                          /**< Mode BUMAIN for EMU_BUINACT */
+#define _EMU_BUINACT_PWRCON_MAINBU          0x00000002UL                          /**< Mode MAINBU for EMU_BUINACT */
+#define _EMU_BUINACT_PWRCON_NODIODE         0x00000003UL                          /**< Mode NODIODE for EMU_BUINACT */
+#define EMU_BUINACT_PWRCON_DEFAULT          (_EMU_BUINACT_PWRCON_DEFAULT << 5)    /**< Shifted mode DEFAULT for EMU_BUINACT */
+#define EMU_BUINACT_PWRCON_NONE             (_EMU_BUINACT_PWRCON_NONE << 5)       /**< Shifted mode NONE for EMU_BUINACT */
+#define EMU_BUINACT_PWRCON_BUMAIN           (_EMU_BUINACT_PWRCON_BUMAIN << 5)     /**< Shifted mode BUMAIN for EMU_BUINACT */
+#define EMU_BUINACT_PWRCON_MAINBU           (_EMU_BUINACT_PWRCON_MAINBU << 5)     /**< Shifted mode MAINBU for EMU_BUINACT */
+#define EMU_BUINACT_PWRCON_NODIODE          (_EMU_BUINACT_PWRCON_NODIODE << 5)    /**< Shifted mode NODIODE for EMU_BUINACT */
 
 /* Bit fields for EMU BUACT */
-#define _EMU_BUACT_RESETVALUE                0x0000000BUL                        /**< Default value for EMU_BUACT */
-#define _EMU_BUACT_MASK                      0x0000007FUL                        /**< Mask for EMU_BUACT */
-#define _EMU_BUACT_BUEXTHRES_SHIFT           0                                   /**< Shift value for EMU_BUEXTHRES */
-#define _EMU_BUACT_BUEXTHRES_MASK            0x7UL                               /**< Bit mask for EMU_BUEXTHRES */
-#define _EMU_BUACT_BUEXTHRES_DEFAULT         0x00000003UL                        /**< Mode DEFAULT for EMU_BUACT */
-#define EMU_BUACT_BUEXTHRES_DEFAULT          (_EMU_BUACT_BUEXTHRES_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_BUACT */
-#define _EMU_BUACT_BUEXRANGE_SHIFT           3                                   /**< Shift value for EMU_BUEXRANGE */
-#define _EMU_BUACT_BUEXRANGE_MASK            0x18UL                              /**< Bit mask for EMU_BUEXRANGE */
-#define _EMU_BUACT_BUEXRANGE_DEFAULT         0x00000001UL                        /**< Mode DEFAULT for EMU_BUACT */
-#define EMU_BUACT_BUEXRANGE_DEFAULT          (_EMU_BUACT_BUEXRANGE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_BUACT */
-#define _EMU_BUACT_PWRCON_SHIFT              5                                   /**< Shift value for EMU_PWRCON */
-#define _EMU_BUACT_PWRCON_MASK               0x60UL                              /**< Bit mask for EMU_PWRCON */
-#define _EMU_BUACT_PWRCON_DEFAULT            0x00000000UL                        /**< Mode DEFAULT for EMU_BUACT */
-#define _EMU_BUACT_PWRCON_NONE               0x00000000UL                        /**< Mode NONE for EMU_BUACT */
-#define _EMU_BUACT_PWRCON_BUMAIN             0x00000001UL                        /**< Mode BUMAIN for EMU_BUACT */
-#define _EMU_BUACT_PWRCON_MAINBU             0x00000002UL                        /**< Mode MAINBU for EMU_BUACT */
-#define _EMU_BUACT_PWRCON_NODIODE            0x00000003UL                        /**< Mode NODIODE for EMU_BUACT */
-#define EMU_BUACT_PWRCON_DEFAULT             (_EMU_BUACT_PWRCON_DEFAULT << 5)    /**< Shifted mode DEFAULT for EMU_BUACT */
-#define EMU_BUACT_PWRCON_NONE                (_EMU_BUACT_PWRCON_NONE << 5)       /**< Shifted mode NONE for EMU_BUACT */
-#define EMU_BUACT_PWRCON_BUMAIN              (_EMU_BUACT_PWRCON_BUMAIN << 5)     /**< Shifted mode BUMAIN for EMU_BUACT */
-#define EMU_BUACT_PWRCON_MAINBU              (_EMU_BUACT_PWRCON_MAINBU << 5)     /**< Shifted mode MAINBU for EMU_BUACT */
-#define EMU_BUACT_PWRCON_NODIODE             (_EMU_BUACT_PWRCON_NODIODE << 5)    /**< Shifted mode NODIODE for EMU_BUACT */
+#define _EMU_BUACT_RESETVALUE               0x0000000BUL                        /**< Default value for EMU_BUACT */
+#define _EMU_BUACT_MASK                     0x0000007FUL                        /**< Mask for EMU_BUACT */
+#define _EMU_BUACT_BUEXTHRES_SHIFT          0                                   /**< Shift value for EMU_BUEXTHRES */
+#define _EMU_BUACT_BUEXTHRES_MASK           0x7UL                               /**< Bit mask for EMU_BUEXTHRES */
+#define _EMU_BUACT_BUEXTHRES_DEFAULT        0x00000003UL                        /**< Mode DEFAULT for EMU_BUACT */
+#define EMU_BUACT_BUEXTHRES_DEFAULT         (_EMU_BUACT_BUEXTHRES_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_BUACT */
+#define _EMU_BUACT_BUEXRANGE_SHIFT          3                                   /**< Shift value for EMU_BUEXRANGE */
+#define _EMU_BUACT_BUEXRANGE_MASK           0x18UL                              /**< Bit mask for EMU_BUEXRANGE */
+#define _EMU_BUACT_BUEXRANGE_DEFAULT        0x00000001UL                        /**< Mode DEFAULT for EMU_BUACT */
+#define EMU_BUACT_BUEXRANGE_DEFAULT         (_EMU_BUACT_BUEXRANGE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_BUACT */
+#define _EMU_BUACT_PWRCON_SHIFT             5                                   /**< Shift value for EMU_PWRCON */
+#define _EMU_BUACT_PWRCON_MASK              0x60UL                              /**< Bit mask for EMU_PWRCON */
+#define _EMU_BUACT_PWRCON_DEFAULT           0x00000000UL                        /**< Mode DEFAULT for EMU_BUACT */
+#define _EMU_BUACT_PWRCON_NONE              0x00000000UL                        /**< Mode NONE for EMU_BUACT */
+#define _EMU_BUACT_PWRCON_BUMAIN            0x00000001UL                        /**< Mode BUMAIN for EMU_BUACT */
+#define _EMU_BUACT_PWRCON_MAINBU            0x00000002UL                        /**< Mode MAINBU for EMU_BUACT */
+#define _EMU_BUACT_PWRCON_NODIODE           0x00000003UL                        /**< Mode NODIODE for EMU_BUACT */
+#define EMU_BUACT_PWRCON_DEFAULT            (_EMU_BUACT_PWRCON_DEFAULT << 5)    /**< Shifted mode DEFAULT for EMU_BUACT */
+#define EMU_BUACT_PWRCON_NONE               (_EMU_BUACT_PWRCON_NONE << 5)       /**< Shifted mode NONE for EMU_BUACT */
+#define EMU_BUACT_PWRCON_BUMAIN             (_EMU_BUACT_PWRCON_BUMAIN << 5)     /**< Shifted mode BUMAIN for EMU_BUACT */
+#define EMU_BUACT_PWRCON_MAINBU             (_EMU_BUACT_PWRCON_MAINBU << 5)     /**< Shifted mode MAINBU for EMU_BUACT */
+#define EMU_BUACT_PWRCON_NODIODE            (_EMU_BUACT_PWRCON_NODIODE << 5)    /**< Shifted mode NODIODE for EMU_BUACT */
 
 /* Bit fields for EMU STATUS */
-#define _EMU_STATUS_RESETVALUE               0x00000000UL                     /**< Default value for EMU_STATUS */
-#define _EMU_STATUS_MASK                     0x00000001UL                     /**< Mask for EMU_STATUS */
-#define EMU_STATUS_BURDY                     (0x1UL << 0)                     /**< Backup mode ready */
-#define _EMU_STATUS_BURDY_SHIFT              0                                /**< Shift value for EMU_BURDY */
-#define _EMU_STATUS_BURDY_MASK               0x1UL                            /**< Bit mask for EMU_BURDY */
-#define _EMU_STATUS_BURDY_DEFAULT            0x00000000UL                     /**< Mode DEFAULT for EMU_STATUS */
-#define EMU_STATUS_BURDY_DEFAULT             (_EMU_STATUS_BURDY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_STATUS */
+#define _EMU_STATUS_RESETVALUE              0x00000000UL                     /**< Default value for EMU_STATUS */
+#define _EMU_STATUS_MASK                    0x00000001UL                     /**< Mask for EMU_STATUS */
+#define EMU_STATUS_BURDY                    (0x1UL << 0)                     /**< Backup mode ready */
+#define _EMU_STATUS_BURDY_SHIFT             0                                /**< Shift value for EMU_BURDY */
+#define _EMU_STATUS_BURDY_MASK              0x1UL                            /**< Bit mask for EMU_BURDY */
+#define _EMU_STATUS_BURDY_DEFAULT           0x00000000UL                     /**< Mode DEFAULT for EMU_STATUS */
+#define EMU_STATUS_BURDY_DEFAULT            (_EMU_STATUS_BURDY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_STATUS */
 
 /* Bit fields for EMU ROUTE */
-#define _EMU_ROUTE_RESETVALUE                0x00000001UL                       /**< Default value for EMU_ROUTE */
-#define _EMU_ROUTE_MASK                      0x00000001UL                       /**< Mask for EMU_ROUTE */
-#define EMU_ROUTE_BUVINPEN                   (0x1UL << 0)                       /**< BU_VIN Pin Enable */
-#define _EMU_ROUTE_BUVINPEN_SHIFT            0                                  /**< Shift value for EMU_BUVINPEN */
-#define _EMU_ROUTE_BUVINPEN_MASK             0x1UL                              /**< Bit mask for EMU_BUVINPEN */
-#define _EMU_ROUTE_BUVINPEN_DEFAULT          0x00000001UL                       /**< Mode DEFAULT for EMU_ROUTE */
-#define EMU_ROUTE_BUVINPEN_DEFAULT           (_EMU_ROUTE_BUVINPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_ROUTE */
+#define _EMU_ROUTE_RESETVALUE               0x00000001UL                       /**< Default value for EMU_ROUTE */
+#define _EMU_ROUTE_MASK                     0x00000001UL                       /**< Mask for EMU_ROUTE */
+#define EMU_ROUTE_BUVINPEN                  (0x1UL << 0)                       /**< BU_VIN Pin Enable */
+#define _EMU_ROUTE_BUVINPEN_SHIFT           0                                  /**< Shift value for EMU_BUVINPEN */
+#define _EMU_ROUTE_BUVINPEN_MASK            0x1UL                              /**< Bit mask for EMU_BUVINPEN */
+#define _EMU_ROUTE_BUVINPEN_DEFAULT         0x00000001UL                       /**< Mode DEFAULT for EMU_ROUTE */
+#define EMU_ROUTE_BUVINPEN_DEFAULT          (_EMU_ROUTE_BUVINPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_ROUTE */
 
 /* Bit fields for EMU IF */
-#define _EMU_IF_RESETVALUE                   0x00000000UL                 /**< Default value for EMU_IF */
-#define _EMU_IF_MASK                         0x00000001UL                 /**< Mask for EMU_IF */
-#define EMU_IF_BURDY                         (0x1UL << 0)                 /**< Backup functionality ready Interrupt Flag */
-#define _EMU_IF_BURDY_SHIFT                  0                            /**< Shift value for EMU_BURDY */
-#define _EMU_IF_BURDY_MASK                   0x1UL                        /**< Bit mask for EMU_BURDY */
-#define _EMU_IF_BURDY_DEFAULT                0x00000000UL                 /**< Mode DEFAULT for EMU_IF */
-#define EMU_IF_BURDY_DEFAULT                 (_EMU_IF_BURDY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IF */
+#define _EMU_IF_RESETVALUE                  0x00000000UL                 /**< Default value for EMU_IF */
+#define _EMU_IF_MASK                        0x00000001UL                 /**< Mask for EMU_IF */
+#define EMU_IF_BURDY                        (0x1UL << 0)                 /**< Backup functionality ready Interrupt Flag */
+#define _EMU_IF_BURDY_SHIFT                 0                            /**< Shift value for EMU_BURDY */
+#define _EMU_IF_BURDY_MASK                  0x1UL                        /**< Bit mask for EMU_BURDY */
+#define _EMU_IF_BURDY_DEFAULT               0x00000000UL                 /**< Mode DEFAULT for EMU_IF */
+#define EMU_IF_BURDY_DEFAULT                (_EMU_IF_BURDY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IF */
 
 /* Bit fields for EMU IFS */
-#define _EMU_IFS_RESETVALUE                  0x00000000UL                  /**< Default value for EMU_IFS */
-#define _EMU_IFS_MASK                        0x00000001UL                  /**< Mask for EMU_IFS */
-#define EMU_IFS_BURDY                        (0x1UL << 0)                  /**< Set Backup functionality ready Interrupt Flag */
-#define _EMU_IFS_BURDY_SHIFT                 0                             /**< Shift value for EMU_BURDY */
-#define _EMU_IFS_BURDY_MASK                  0x1UL                         /**< Bit mask for EMU_BURDY */
-#define _EMU_IFS_BURDY_DEFAULT               0x00000000UL                  /**< Mode DEFAULT for EMU_IFS */
-#define EMU_IFS_BURDY_DEFAULT                (_EMU_IFS_BURDY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFS */
+#define _EMU_IFS_RESETVALUE                 0x00000000UL                  /**< Default value for EMU_IFS */
+#define _EMU_IFS_MASK                       0x00000001UL                  /**< Mask for EMU_IFS */
+#define EMU_IFS_BURDY                       (0x1UL << 0)                  /**< Set Backup functionality ready Interrupt Flag */
+#define _EMU_IFS_BURDY_SHIFT                0                             /**< Shift value for EMU_BURDY */
+#define _EMU_IFS_BURDY_MASK                 0x1UL                         /**< Bit mask for EMU_BURDY */
+#define _EMU_IFS_BURDY_DEFAULT              0x00000000UL                  /**< Mode DEFAULT for EMU_IFS */
+#define EMU_IFS_BURDY_DEFAULT               (_EMU_IFS_BURDY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFS */
 
 /* Bit fields for EMU IFC */
-#define _EMU_IFC_RESETVALUE                  0x00000000UL                  /**< Default value for EMU_IFC */
-#define _EMU_IFC_MASK                        0x00000001UL                  /**< Mask for EMU_IFC */
-#define EMU_IFC_BURDY                        (0x1UL << 0)                  /**< Clear Backup functionality ready Interrupt Flag */
-#define _EMU_IFC_BURDY_SHIFT                 0                             /**< Shift value for EMU_BURDY */
-#define _EMU_IFC_BURDY_MASK                  0x1UL                         /**< Bit mask for EMU_BURDY */
-#define _EMU_IFC_BURDY_DEFAULT               0x00000000UL                  /**< Mode DEFAULT for EMU_IFC */
-#define EMU_IFC_BURDY_DEFAULT                (_EMU_IFC_BURDY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFC */
+#define _EMU_IFC_RESETVALUE                 0x00000000UL                  /**< Default value for EMU_IFC */
+#define _EMU_IFC_MASK                       0x00000001UL                  /**< Mask for EMU_IFC */
+#define EMU_IFC_BURDY                       (0x1UL << 0)                  /**< Clear Backup functionality ready Interrupt Flag */
+#define _EMU_IFC_BURDY_SHIFT                0                             /**< Shift value for EMU_BURDY */
+#define _EMU_IFC_BURDY_MASK                 0x1UL                         /**< Bit mask for EMU_BURDY */
+#define _EMU_IFC_BURDY_DEFAULT              0x00000000UL                  /**< Mode DEFAULT for EMU_IFC */
+#define EMU_IFC_BURDY_DEFAULT               (_EMU_IFC_BURDY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFC */
 
 /* Bit fields for EMU IEN */
-#define _EMU_IEN_RESETVALUE                  0x00000000UL                  /**< Default value for EMU_IEN */
-#define _EMU_IEN_MASK                        0x00000001UL                  /**< Mask for EMU_IEN */
-#define EMU_IEN_BURDY                        (0x1UL << 0)                  /**< Backup functionality ready Interrupt Enable */
-#define _EMU_IEN_BURDY_SHIFT                 0                             /**< Shift value for EMU_BURDY */
-#define _EMU_IEN_BURDY_MASK                  0x1UL                         /**< Bit mask for EMU_BURDY */
-#define _EMU_IEN_BURDY_DEFAULT               0x00000000UL                  /**< Mode DEFAULT for EMU_IEN */
-#define EMU_IEN_BURDY_DEFAULT                (_EMU_IEN_BURDY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IEN */
+#define _EMU_IEN_RESETVALUE                 0x00000000UL                  /**< Default value for EMU_IEN */
+#define _EMU_IEN_MASK                       0x00000001UL                  /**< Mask for EMU_IEN */
+#define EMU_IEN_BURDY                       (0x1UL << 0)                  /**< Backup functionality ready Interrupt Enable */
+#define _EMU_IEN_BURDY_SHIFT                0                             /**< Shift value for EMU_BURDY */
+#define _EMU_IEN_BURDY_MASK                 0x1UL                         /**< Bit mask for EMU_BURDY */
+#define _EMU_IEN_BURDY_DEFAULT              0x00000000UL                  /**< Mode DEFAULT for EMU_IEN */
+#define EMU_IEN_BURDY_DEFAULT               (_EMU_IEN_BURDY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IEN */
 
 /* Bit fields for EMU BUBODBUVINCAL */
-#define _EMU_BUBODBUVINCAL_RESETVALUE        0x0000000BUL                            /**< Default value for EMU_BUBODBUVINCAL */
-#define _EMU_BUBODBUVINCAL_MASK              0x0000001FUL                            /**< Mask for EMU_BUBODBUVINCAL */
-#define _EMU_BUBODBUVINCAL_THRES_SHIFT       0                                       /**< Shift value for EMU_THRES */
-#define _EMU_BUBODBUVINCAL_THRES_MASK        0x7UL                                   /**< Bit mask for EMU_THRES */
-#define _EMU_BUBODBUVINCAL_THRES_DEFAULT     0x00000003UL                            /**< Mode DEFAULT for EMU_BUBODBUVINCAL */
-#define EMU_BUBODBUVINCAL_THRES_DEFAULT      (_EMU_BUBODBUVINCAL_THRES_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_BUBODBUVINCAL */
-#define _EMU_BUBODBUVINCAL_RANGE_SHIFT       3                                       /**< Shift value for EMU_RANGE */
-#define _EMU_BUBODBUVINCAL_RANGE_MASK        0x18UL                                  /**< Bit mask for EMU_RANGE */
-#define _EMU_BUBODBUVINCAL_RANGE_DEFAULT     0x00000001UL                            /**< Mode DEFAULT for EMU_BUBODBUVINCAL */
-#define EMU_BUBODBUVINCAL_RANGE_DEFAULT      (_EMU_BUBODBUVINCAL_RANGE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_BUBODBUVINCAL */
+#define _EMU_BUBODBUVINCAL_RESETVALUE       0x0000000BUL                            /**< Default value for EMU_BUBODBUVINCAL */
+#define _EMU_BUBODBUVINCAL_MASK             0x0000001FUL                            /**< Mask for EMU_BUBODBUVINCAL */
+#define _EMU_BUBODBUVINCAL_THRES_SHIFT      0                                       /**< Shift value for EMU_THRES */
+#define _EMU_BUBODBUVINCAL_THRES_MASK       0x7UL                                   /**< Bit mask for EMU_THRES */
+#define _EMU_BUBODBUVINCAL_THRES_DEFAULT    0x00000003UL                            /**< Mode DEFAULT for EMU_BUBODBUVINCAL */
+#define EMU_BUBODBUVINCAL_THRES_DEFAULT     (_EMU_BUBODBUVINCAL_THRES_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_BUBODBUVINCAL */
+#define _EMU_BUBODBUVINCAL_RANGE_SHIFT      3                                       /**< Shift value for EMU_RANGE */
+#define _EMU_BUBODBUVINCAL_RANGE_MASK       0x18UL                                  /**< Bit mask for EMU_RANGE */
+#define _EMU_BUBODBUVINCAL_RANGE_DEFAULT    0x00000001UL                            /**< Mode DEFAULT for EMU_BUBODBUVINCAL */
+#define EMU_BUBODBUVINCAL_RANGE_DEFAULT     (_EMU_BUBODBUVINCAL_RANGE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_BUBODBUVINCAL */
 
 /* Bit fields for EMU BUBODUNREGCAL */
-#define _EMU_BUBODUNREGCAL_RESETVALUE        0x0000000BUL                            /**< Default value for EMU_BUBODUNREGCAL */
-#define _EMU_BUBODUNREGCAL_MASK              0x0000001FUL                            /**< Mask for EMU_BUBODUNREGCAL */
-#define _EMU_BUBODUNREGCAL_THRES_SHIFT       0                                       /**< Shift value for EMU_THRES */
-#define _EMU_BUBODUNREGCAL_THRES_MASK        0x7UL                                   /**< Bit mask for EMU_THRES */
-#define _EMU_BUBODUNREGCAL_THRES_DEFAULT     0x00000003UL                            /**< Mode DEFAULT for EMU_BUBODUNREGCAL */
-#define EMU_BUBODUNREGCAL_THRES_DEFAULT      (_EMU_BUBODUNREGCAL_THRES_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_BUBODUNREGCAL */
-#define _EMU_BUBODUNREGCAL_RANGE_SHIFT       3                                       /**< Shift value for EMU_RANGE */
-#define _EMU_BUBODUNREGCAL_RANGE_MASK        0x18UL                                  /**< Bit mask for EMU_RANGE */
-#define _EMU_BUBODUNREGCAL_RANGE_DEFAULT     0x00000001UL                            /**< Mode DEFAULT for EMU_BUBODUNREGCAL */
-#define EMU_BUBODUNREGCAL_RANGE_DEFAULT      (_EMU_BUBODUNREGCAL_RANGE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_BUBODUNREGCAL */
+#define _EMU_BUBODUNREGCAL_RESETVALUE       0x0000000BUL                            /**< Default value for EMU_BUBODUNREGCAL */
+#define _EMU_BUBODUNREGCAL_MASK             0x0000001FUL                            /**< Mask for EMU_BUBODUNREGCAL */
+#define _EMU_BUBODUNREGCAL_THRES_SHIFT      0                                       /**< Shift value for EMU_THRES */
+#define _EMU_BUBODUNREGCAL_THRES_MASK       0x7UL                                   /**< Bit mask for EMU_THRES */
+#define _EMU_BUBODUNREGCAL_THRES_DEFAULT    0x00000003UL                            /**< Mode DEFAULT for EMU_BUBODUNREGCAL */
+#define EMU_BUBODUNREGCAL_THRES_DEFAULT     (_EMU_BUBODUNREGCAL_THRES_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_BUBODUNREGCAL */
+#define _EMU_BUBODUNREGCAL_RANGE_SHIFT      3                                       /**< Shift value for EMU_RANGE */
+#define _EMU_BUBODUNREGCAL_RANGE_MASK       0x18UL                                  /**< Bit mask for EMU_RANGE */
+#define _EMU_BUBODUNREGCAL_RANGE_DEFAULT    0x00000001UL                            /**< Mode DEFAULT for EMU_BUBODUNREGCAL */
+#define EMU_BUBODUNREGCAL_RANGE_DEFAULT     (_EMU_BUBODUNREGCAL_RANGE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_BUBODUNREGCAL */
 
 /** @} End of group EFM32LG_EMU */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_etm.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_etm.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32lg_etm.h
  * @brief EFM32LG_ETM register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32LG_ETM
  * @{
  * @brief EFM32LG_ETM Register Declaration
@@ -778,5 +782,5 @@
 #define ETM_ETMCIDR3_PREAMB_DEFAULT                   (_ETM_ETMCIDR3_PREAMB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCIDR3 */
 
 /** @} End of group EFM32LG_ETM */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_gpio.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_gpio.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32lg_gpio.h
  * @brief EFM32LG_GPIO register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32LG_GPIO
  * @{
  * @brief EFM32LG_GPIO Register Declaration
@@ -1200,5 +1204,5 @@
 #define GPIO_EM4WUCAUSE_EM4WUCAUSE_E13                    (_GPIO_EM4WUCAUSE_EM4WUCAUSE_E13 << 0)     /**< Shifted mode E13 for GPIO_EM4WUCAUSE */
 
 /** @} End of group EFM32LG_GPIO */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_gpio_p.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_gpio_p.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32lg_gpio_p.h
  * @brief EFM32LG_GPIO_P register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @brief GPIO_P EFM32LG GPIO P
  *****************************************************************************/
 typedef struct
@@ -45,3 +49,6 @@
   __IO uint32_t PINLOCKN; /**< Port Unlocked Pins Register  */
 } GPIO_P_TypeDef;
 
+/** @} End of group Parts */
+
+

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_i2c.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_i2c.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32lg_i2c.h
  * @brief EFM32LG_I2C register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32LG_I2C
  * @{
  * @brief EFM32LG_I2C Register Declaration
@@ -697,5 +701,5 @@
 #define I2C_ROUTE_LOCATION_LOC6           (_I2C_ROUTE_LOCATION_LOC6 << 8)    /**< Shifted mode LOC6 for I2C_ROUTE */
 
 /** @} End of group EFM32LG_I2C */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_lcd.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_lcd.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32lg_lcd.h
  * @brief EFM32LG_LCD register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32LG_LCD
  * @{
  * @brief EFM32LG_LCD Register Declaration
@@ -591,5 +595,5 @@
 #define LCD_SEGD7L_SEGD7L_DEFAULT          (_LCD_SEGD7L_SEGD7L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD7L */
 
 /** @} End of group EFM32LG_LCD */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_lesense.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_lesense.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32lg_lesense.h
  * @brief EFM32LG_LESENSE register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32LG_LESENSE
  * @{
  * @brief EFM32LG_LESENSE Register Declaration
@@ -61,9 +65,10 @@
   __IO uint32_t       POWERDOWN;      /**< LESENSE RAM power-down register  */
 
   uint32_t            RESERVED0[105]; /**< Reserved registers */
+  LESENSE_ST_TypeDef  ST[16];         /**< Decoding states */
 
-  LESENSE_ST_TypeDef  ST[16];         /**< Decoding states */
   LESENSE_BUF_TypeDef BUF[16];        /**< Scanresult */
+
   LESENSE_CH_TypeDef  CH[16];         /**< Scanconfig */
 } LESENSE_TypeDef;                    /** @} */
 
@@ -1921,5 +1926,5 @@
 #define LESENSE_CH_EVAL_SCANRESINV_DEFAULT             (_LESENSE_CH_EVAL_SCANRESINV_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_CH_EVAL */
 
 /** @} End of group EFM32LG_LESENSE */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_lesense_buf.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_lesense_buf.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32lg_lesense_buf.h
  * @brief EFM32LG_LESENSE_BUF register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @brief LESENSE_BUF EFM32LG LESENSE BUF
  *****************************************************************************/
 typedef struct
@@ -37,3 +41,6 @@
   __IO uint32_t DATA; /**< Scan results  */
 } LESENSE_BUF_TypeDef;
 
+/** @} End of group Parts */
+
+

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_lesense_ch.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_lesense_ch.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32lg_lesense_ch.h
  * @brief EFM32LG_LESENSE_CH register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @brief LESENSE_CH EFM32LG LESENSE CH
  *****************************************************************************/
 typedef struct
@@ -37,7 +41,9 @@
   __IO uint32_t TIMING;       /**< Scan configuration  */
   __IO uint32_t INTERACT;     /**< Scan configuration  */
   __IO uint32_t EVAL;         /**< Scan configuration  */
-
   uint32_t      RESERVED0[1]; /**< Reserved future */
 } LESENSE_CH_TypeDef;
 
+/** @} End of group Parts */
+
+

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_lesense_st.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_lesense_st.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32lg_lesense_st.h
  * @brief EFM32LG_LESENSE_ST register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @brief LESENSE_ST EFM32LG LESENSE ST
  *****************************************************************************/
 typedef struct
@@ -38,3 +42,6 @@
   __IO uint32_t TCONFB; /**< State transition configuration B  */
 } LESENSE_ST_TypeDef;
 
+/** @} End of group Parts */
+
+

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_letimer.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_letimer.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32lg_letimer.h
  * @brief EFM32LG_LETIMER register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32LG_LETIMER
  * @{
  * @brief EFM32LG_LETIMER Register Declaration
@@ -404,5 +408,5 @@
 #define LETIMER_ROUTE_LOCATION_LOC3          (_LETIMER_ROUTE_LOCATION_LOC3 << 8)    /**< Shifted mode LOC3 for LETIMER_ROUTE */
 
 /** @} End of group EFM32LG_LETIMER */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_leuart.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_leuart.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32lg_leuart.h
  * @brief EFM32LG_LEUART register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32LG_LEUART
  * @{
  * @brief EFM32LG_LEUART Register Declaration
@@ -695,5 +699,5 @@
 #define LEUART_INPUT_RXPRS_DEFAULT               (_LEUART_INPUT_RXPRS_DEFAULT << 4)    /**< Shifted mode DEFAULT for LEUART_INPUT */
 
 /** @} End of group EFM32LG_LEUART */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_msc.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_msc.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32lg_msc.h
  * @brief EFM32LG_MSC register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32LG_MSC
  * @{
  * @brief EFM32LG_MSC Register Declaration
@@ -429,5 +433,5 @@
 #define MSC_MASSLOCK_LOCKKEY_UNLOCK             (_MSC_MASSLOCK_LOCKKEY_UNLOCK << 0)   /**< Shifted mode UNLOCK for MSC_MASSLOCK */
 
 /** @} End of group EFM32LG_MSC */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_pcnt.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_pcnt.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32lg_pcnt.h
  * @brief EFM32LG_PCNT register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32LG_PCNT
  * @{
  * @brief EFM32LG_PCNT Register Declaration
@@ -413,5 +417,5 @@
 #define PCNT_INPUT_S1PRSEN_DEFAULT        (_PCNT_INPUT_S1PRSEN_DEFAULT << 10) /**< Shifted mode DEFAULT for PCNT_INPUT */
 
 /** @} End of group EFM32LG_PCNT */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_prs.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_prs.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32lg_prs.h
  * @brief EFM32LG_PRS register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32LG_PRS
  * @{
  * @brief EFM32LG_PRS Register Declaration
@@ -41,7 +45,6 @@
   __IO uint32_t  ROUTE;        /**< I/O Routing Register  */
 
   uint32_t       RESERVED0[1]; /**< Reserved registers */
-
   PRS_CH_TypeDef CH[12];       /**< Channel registers */
 } PRS_TypeDef;                 /** @} */
 
@@ -448,5 +451,5 @@
 #define PRS_CH_CTRL_ASYNC_DEFAULT               (_PRS_CH_CTRL_ASYNC_DEFAULT << 28)          /**< Shifted mode DEFAULT for PRS_CH_CTRL */
 
 /** @} End of group EFM32LG_PRS */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_prs_ch.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_prs_ch.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32lg_prs_ch.h
  * @brief EFM32LG_PRS_CH register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @brief PRS_CH EFM32LG PRS CH
  *****************************************************************************/
 typedef struct
@@ -37,3 +41,6 @@
   __IO uint32_t CTRL; /**< Channel Control Register  */
 } PRS_CH_TypeDef;
 
+/** @} End of group Parts */
+
+

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_prs_signals.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_prs_signals.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32lg_prs_signals.h
  * @brief EFM32LG_PRS_SIGNALS register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,11 +30,14 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @addtogroup EFM32LG_PRS_Signals
  * @{
  * @brief PRS Signal names
  *****************************************************************************/
-
 #define PRS_VCMP_OUT             ((1 << 16) + 0)  /**< PRS Voltage comparator output */
 #define PRS_ACMP0_OUT            ((2 << 16) + 0)  /**< PRS Analog comparator output */
 #define PRS_ACMP1_OUT            ((3 << 16) + 0)  /**< PRS Analog comparator output */
@@ -119,5 +122,5 @@
 #define PRS_LESENSE_DEC2         ((59 << 16) + 2) /**< PRS LESENSE Decoder PRS out 2 */
 
 /** @} End of group EFM32LG_PRS */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_rmu.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_rmu.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32lg_rmu.h
  * @brief EFM32LG_RMU register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32LG_RMU
  * @{
  * @brief EFM32LG_RMU Register Declaration
@@ -154,5 +158,5 @@
 #define RMU_CMD_RCCLR_DEFAULT                 (_RMU_CMD_RCCLR_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_CMD */
 
 /** @} End of group EFM32LG_RMU */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_romtable.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_romtable.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32lg_romtable.h
  * @brief EFM32LG_ROMTABLE register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32LG_ROMTABLE
  * @{
  * @brief Chip Information, Revision numbers
@@ -64,5 +68,5 @@
 #define _ROMTABLE_PID3_REVMINORLSB_SHIFT    4            /**< Least Significant Bits [3:0] of CHIP MINOR revision, shift */
 
 /** @} End of group EFM32LG_ROMTABLE */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_rtc.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_rtc.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32lg_rtc.h
  * @brief EFM32LG_RTC register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32LG_RTC
  * @{
  * @brief EFM32LG_RTC Register Declaration
@@ -210,5 +214,5 @@
 #define RTC_SYNCBUSY_COMP1_DEFAULT       (_RTC_SYNCBUSY_COMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_SYNCBUSY */
 
 /** @} End of group EFM32LG_RTC */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_timer.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_timer.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32lg_timer.h
  * @brief EFM32LG_TIMER register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32LG_TIMER
  * @{
  * @brief EFM32LG_TIMER Register Declaration
@@ -49,7 +53,6 @@
   __IO uint32_t    ROUTE;        /**< I/O Routing Register  */
 
   uint32_t         RESERVED0[1]; /**< Reserved registers */
-
   TIMER_CC_TypeDef CC[3];        /**< Compare/Capture Channel */
 
   uint32_t         RESERVED1[4]; /**< Reserved for future use **/
@@ -181,7 +184,7 @@
 #define _TIMER_CTRL_ATI_MASK                       0x10000000UL                             /**< Bit mask for TIMER_ATI */
 #define _TIMER_CTRL_ATI_DEFAULT                    0x00000000UL                             /**< Mode DEFAULT for TIMER_CTRL */
 #define TIMER_CTRL_ATI_DEFAULT                     (_TIMER_CTRL_ATI_DEFAULT << 28)          /**< Shifted mode DEFAULT for TIMER_CTRL */
-#define TIMER_CTRL_RSSCOIST                        (0x1UL << 29)                            /**< Reload-Start Sets Compare Ouptut initial State */
+#define TIMER_CTRL_RSSCOIST                        (0x1UL << 29)                            /**< Reload-Start Sets Compare Output initial State */
 #define _TIMER_CTRL_RSSCOIST_SHIFT                 29                                       /**< Shift value for TIMER_RSSCOIST */
 #define _TIMER_CTRL_RSSCOIST_MASK                  0x20000000UL                             /**< Bit mask for TIMER_RSSCOIST */
 #define _TIMER_CTRL_RSSCOIST_DEFAULT               0x00000000UL                             /**< Mode DEFAULT for TIMER_CTRL */
@@ -516,15 +519,15 @@
 #define TIMER_ROUTE_CDTI2PEN_DEFAULT               (_TIMER_ROUTE_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_ROUTE */
 #define _TIMER_ROUTE_LOCATION_SHIFT                16                                    /**< Shift value for TIMER_LOCATION */
 #define _TIMER_ROUTE_LOCATION_MASK                 0x70000UL                             /**< Bit mask for TIMER_LOCATION */
+#define _TIMER_ROUTE_LOCATION_LOC0                 0x00000000UL                          /**< Mode LOC0 for TIMER_ROUTE */
 #define _TIMER_ROUTE_LOCATION_DEFAULT              0x00000000UL                          /**< Mode DEFAULT for TIMER_ROUTE */
-#define _TIMER_ROUTE_LOCATION_LOC0                 0x00000000UL                          /**< Mode LOC0 for TIMER_ROUTE */
 #define _TIMER_ROUTE_LOCATION_LOC1                 0x00000001UL                          /**< Mode LOC1 for TIMER_ROUTE */
 #define _TIMER_ROUTE_LOCATION_LOC2                 0x00000002UL                          /**< Mode LOC2 for TIMER_ROUTE */
 #define _TIMER_ROUTE_LOCATION_LOC3                 0x00000003UL                          /**< Mode LOC3 for TIMER_ROUTE */
 #define _TIMER_ROUTE_LOCATION_LOC4                 0x00000004UL                          /**< Mode LOC4 for TIMER_ROUTE */
 #define _TIMER_ROUTE_LOCATION_LOC5                 0x00000005UL                          /**< Mode LOC5 for TIMER_ROUTE */
+#define TIMER_ROUTE_LOCATION_LOC0                  (_TIMER_ROUTE_LOCATION_LOC0 << 16)    /**< Shifted mode LOC0 for TIMER_ROUTE */
 #define TIMER_ROUTE_LOCATION_DEFAULT               (_TIMER_ROUTE_LOCATION_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_ROUTE */
-#define TIMER_ROUTE_LOCATION_LOC0                  (_TIMER_ROUTE_LOCATION_LOC0 << 16)    /**< Shifted mode LOC0 for TIMER_ROUTE */
 #define TIMER_ROUTE_LOCATION_LOC1                  (_TIMER_ROUTE_LOCATION_LOC1 << 16)    /**< Shifted mode LOC1 for TIMER_ROUTE */
 #define TIMER_ROUTE_LOCATION_LOC2                  (_TIMER_ROUTE_LOCATION_LOC2 << 16)    /**< Shifted mode LOC2 for TIMER_ROUTE */
 #define TIMER_ROUTE_LOCATION_LOC3                  (_TIMER_ROUTE_LOCATION_LOC3 << 16)    /**< Shifted mode LOC3 for TIMER_ROUTE */
@@ -961,5 +964,5 @@
 #define TIMER_DTLOCK_LOCKKEY_UNLOCK                (_TIMER_DTLOCK_LOCKKEY_UNLOCK << 0)   /**< Shifted mode UNLOCK for TIMER_DTLOCK */
 
 /** @} End of group EFM32LG_TIMER */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_timer_cc.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_timer_cc.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32lg_timer_cc.h
  * @brief EFM32LG_TIMER_CC register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @brief TIMER_CC EFM32LG TIMER CC
  *****************************************************************************/
 typedef struct
@@ -40,3 +44,6 @@
   __IO uint32_t CCVB; /**< CC Channel Buffer Register  */
 } TIMER_CC_TypeDef;
 
+/** @} End of group Parts */
+
+

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_uart.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_uart.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32lg_uart.h
  * @brief EFM32LG_UART register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -29,6 +29,10 @@
  * any third party, arising from your use of this Software.
  *
  *****************************************************************************/
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
 
 /**************************************************************************//**
  * @defgroup EFM32LG_UART_BitFields
@@ -37,7 +41,7 @@
 
 /* Bit fields for UART CTRL */
 #define _UART_CTRL_RESETVALUE                0x00000000UL                            /**< Default value for UART_CTRL */
-#define _UART_CTRL_MASK                      0x7DFFFF7FUL                            /**< Mask for UART_CTRL */
+#define _UART_CTRL_MASK                      0xFFFFFF7FUL                            /**< Mask for UART_CTRL */
 #define UART_CTRL_SYNC                       (0x1UL << 0)                            /**< USART Synchronous Mode */
 #define _UART_CTRL_SYNC_SHIFT                0                                       /**< Shift value for USART_SYNC */
 #define _UART_CTRL_SYNC_MASK                 0x1UL                                   /**< Bit mask for USART_SYNC */
@@ -176,6 +180,11 @@
 #define _UART_CTRL_ERRSTX_MASK               0x1000000UL                             /**< Bit mask for USART_ERRSTX */
 #define _UART_CTRL_ERRSTX_DEFAULT            0x00000000UL                            /**< Mode DEFAULT for UART_CTRL */
 #define UART_CTRL_ERRSTX_DEFAULT             (_UART_CTRL_ERRSTX_DEFAULT << 24)       /**< Shifted mode DEFAULT for UART_CTRL */
+#define UART_CTRL_SSSEARLY                   (0x1UL << 25)                           /**< Synchronous Slave Setup Early */
+#define _UART_CTRL_SSSEARLY_SHIFT            25                                      /**< Shift value for USART_SSSEARLY */
+#define _UART_CTRL_SSSEARLY_MASK             0x2000000UL                             /**< Bit mask for USART_SSSEARLY */
+#define _UART_CTRL_SSSEARLY_DEFAULT          0x00000000UL                            /**< Mode DEFAULT for UART_CTRL */
+#define UART_CTRL_SSSEARLY_DEFAULT           (_UART_CTRL_SSSEARLY_DEFAULT << 25)     /**< Shifted mode DEFAULT for UART_CTRL */
 #define _UART_CTRL_TXDELAY_SHIFT             26                                      /**< Shift value for USART_TXDELAY */
 #define _UART_CTRL_TXDELAY_MASK              0xC000000UL                             /**< Bit mask for USART_TXDELAY */
 #define _UART_CTRL_TXDELAY_DEFAULT           0x00000000UL                            /**< Mode DEFAULT for UART_CTRL */
@@ -203,6 +212,11 @@
 #define _UART_CTRL_MVDIS_MASK                0x40000000UL                            /**< Bit mask for USART_MVDIS */
 #define _UART_CTRL_MVDIS_DEFAULT             0x00000000UL                            /**< Mode DEFAULT for UART_CTRL */
 #define UART_CTRL_MVDIS_DEFAULT              (_UART_CTRL_MVDIS_DEFAULT << 30)        /**< Shifted mode DEFAULT for UART_CTRL */
+#define UART_CTRL_SMSDELAY                   (0x1UL << 31)                           /**< Synchronous Master Sample Delay */
+#define _UART_CTRL_SMSDELAY_SHIFT            31                                      /**< Shift value for USART_SMSDELAY */
+#define _UART_CTRL_SMSDELAY_MASK             0x80000000UL                            /**< Bit mask for USART_SMSDELAY */
+#define _UART_CTRL_SMSDELAY_DEFAULT          0x00000000UL                            /**< Mode DEFAULT for UART_CTRL */
+#define UART_CTRL_SMSDELAY_DEFAULT           (_UART_CTRL_SMSDELAY_DEFAULT << 31)     /**< Shifted mode DEFAULT for UART_CTRL */
 
 /* Bit fields for UART FRAME */
 #define _UART_FRAME_RESETVALUE               0x00001005UL                             /**< Default value for UART_FRAME */
@@ -1113,5 +1127,5 @@
 #define UART_I2SCTRL_FORMAT_W8D8             (_UART_I2SCTRL_FORMAT_W8D8 << 8)      /**< Shifted mode W8D8 for UART_I2SCTRL */
 
 /** @} End of group EFM32LG_UART */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_usart.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_usart.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32lg_usart.h
  * @brief EFM32LG_USART register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32LG_USART
  * @{
  * @brief EFM32LG_USART Register Declaration
@@ -69,7 +73,7 @@
 
 /* Bit fields for USART CTRL */
 #define _USART_CTRL_RESETVALUE                0x00000000UL                             /**< Default value for USART_CTRL */
-#define _USART_CTRL_MASK                      0x7DFFFF7FUL                             /**< Mask for USART_CTRL */
+#define _USART_CTRL_MASK                      0xFFFFFF7FUL                             /**< Mask for USART_CTRL */
 #define USART_CTRL_SYNC                       (0x1UL << 0)                             /**< USART Synchronous Mode */
 #define _USART_CTRL_SYNC_SHIFT                0                                        /**< Shift value for USART_SYNC */
 #define _USART_CTRL_SYNC_MASK                 0x1UL                                    /**< Bit mask for USART_SYNC */
@@ -208,6 +212,11 @@
 #define _USART_CTRL_ERRSTX_MASK               0x1000000UL                              /**< Bit mask for USART_ERRSTX */
 #define _USART_CTRL_ERRSTX_DEFAULT            0x00000000UL                             /**< Mode DEFAULT for USART_CTRL */
 #define USART_CTRL_ERRSTX_DEFAULT             (_USART_CTRL_ERRSTX_DEFAULT << 24)       /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_SSSEARLY                   (0x1UL << 25)                            /**< Synchronous Slave Setup Early */
+#define _USART_CTRL_SSSEARLY_SHIFT            25                                       /**< Shift value for USART_SSSEARLY */
+#define _USART_CTRL_SSSEARLY_MASK             0x2000000UL                              /**< Bit mask for USART_SSSEARLY */
+#define _USART_CTRL_SSSEARLY_DEFAULT          0x00000000UL                             /**< Mode DEFAULT for USART_CTRL */
+#define USART_CTRL_SSSEARLY_DEFAULT           (_USART_CTRL_SSSEARLY_DEFAULT << 25)     /**< Shifted mode DEFAULT for USART_CTRL */
 #define _USART_CTRL_TXDELAY_SHIFT             26                                       /**< Shift value for USART_TXDELAY */
 #define _USART_CTRL_TXDELAY_MASK              0xC000000UL                              /**< Bit mask for USART_TXDELAY */
 #define _USART_CTRL_TXDELAY_DEFAULT           0x00000000UL                             /**< Mode DEFAULT for USART_CTRL */
@@ -235,6 +244,11 @@
 #define _USART_CTRL_MVDIS_MASK                0x40000000UL                             /**< Bit mask for USART_MVDIS */
 #define _USART_CTRL_MVDIS_DEFAULT             0x00000000UL                             /**< Mode DEFAULT for USART_CTRL */
 #define USART_CTRL_MVDIS_DEFAULT              (_USART_CTRL_MVDIS_DEFAULT << 30)        /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_SMSDELAY                   (0x1UL << 31)                            /**< Synchronous Master Sample Delay */
+#define _USART_CTRL_SMSDELAY_SHIFT            31                                       /**< Shift value for USART_SMSDELAY */
+#define _USART_CTRL_SMSDELAY_MASK             0x80000000UL                             /**< Bit mask for USART_SMSDELAY */
+#define _USART_CTRL_SMSDELAY_DEFAULT          0x00000000UL                             /**< Mode DEFAULT for USART_CTRL */
+#define USART_CTRL_SMSDELAY_DEFAULT           (_USART_CTRL_SMSDELAY_DEFAULT << 31)     /**< Shifted mode DEFAULT for USART_CTRL */
 
 /* Bit fields for USART FRAME */
 #define _USART_FRAME_RESETVALUE               0x00001005UL                              /**< Default value for USART_FRAME */
@@ -1145,5 +1159,5 @@
 #define USART_I2SCTRL_FORMAT_W8D8             (_USART_I2SCTRL_FORMAT_W8D8 << 8)      /**< Shifted mode W8D8 for USART_I2SCTRL */
 
 /** @} End of group EFM32LG_USART */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_usb.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_usb.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32lg_usb.h
  * @brief EFM32LG_USB register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32LG_USB
  * @{
  * @brief EFM32LG_USB Register Declaration
@@ -81,7 +85,6 @@
   __IO uint32_t    HPRT;              /**< Host Port Control and Status Register  */
 
   uint32_t         RESERVED6[47];     /**< Reserved registers */
-
   USB_HC_TypeDef   HC[14];            /**< Host Channel Registers */
 
   uint32_t         RESERVED7[80];     /**< Reserved for future use **/
@@ -110,7 +113,6 @@
   __I uint32_t     DIEP0TXFSTS;       /**< Device IN Endpoint 0 Transmit FIFO Status Register  */
 
   uint32_t         RESERVED14[1];     /**< Reserved registers */
-
   USB_DIEP_TypeDef DIEP[6];           /**< Device IN Endpoint x+1 Registers */
 
   uint32_t         RESERVED15[72];    /**< Reserved for future use **/
@@ -122,70 +124,54 @@
   __IO uint32_t    DOEP0DMAADDR;      /**< Device OUT Endpoint 0 DMA Address Register  */
 
   uint32_t         RESERVED18[2];     /**< Reserved registers */
-
   USB_DOEP_TypeDef DOEP[6];           /**< Device OUT Endpoint x+1 Registers */
 
   uint32_t         RESERVED19[136];   /**< Reserved for future use **/
   __IO uint32_t    PCGCCTL;           /**< Power and Clock Gating Control Register  */
 
   uint32_t         RESERVED20[127];   /**< Reserved registers */
-
   __IO uint32_t    FIFO0D[512];       /**< Device EP 0/Host Channel 0 FIFO  */
 
   uint32_t         RESERVED21[512];   /**< Reserved registers */
-
   __IO uint32_t    FIFO1D[512];       /**< Device EP 1/Host Channel 1 FIFO  */
 
   uint32_t         RESERVED22[512];   /**< Reserved registers */
-
   __IO uint32_t    FIFO2D[512];       /**< Device EP 2/Host Channel 2 FIFO  */
 
   uint32_t         RESERVED23[512];   /**< Reserved registers */
-
   __IO uint32_t    FIFO3D[512];       /**< Device EP 3/Host Channel 3 FIFO  */
 
   uint32_t         RESERVED24[512];   /**< Reserved registers */
-
   __IO uint32_t    FIFO4D[512];       /**< Device EP 4/Host Channel 4 FIFO  */
 
   uint32_t         RESERVED25[512];   /**< Reserved registers */
-
   __IO uint32_t    FIFO5D[512];       /**< Device EP 5/Host Channel 5 FIFO  */
 
   uint32_t         RESERVED26[512];   /**< Reserved registers */
-
   __IO uint32_t    FIFO6D[512];       /**< Device EP 6/Host Channel 6 FIFO  */
 
   uint32_t         RESERVED27[512];   /**< Reserved registers */
-
   __IO uint32_t    FIFO7D[512];       /**< Host Channel 7 FIFO  */
 
   uint32_t         RESERVED28[512];   /**< Reserved registers */
-
   __IO uint32_t    FIFO8D[512];       /**< Host Channel 8 FIFO  */
 
   uint32_t         RESERVED29[512];   /**< Reserved registers */
-
   __IO uint32_t    FIFO9D[512];       /**< Host Channel 9 FIFO  */
 
   uint32_t         RESERVED30[512];   /**< Reserved registers */
-
   __IO uint32_t    FIFO10D[512];      /**< Host Channel 10 FIFO  */
 
   uint32_t         RESERVED31[512];   /**< Reserved registers */
-
   __IO uint32_t    FIFO11D[512];      /**< Host Channel 11 FIFO  */
 
   uint32_t         RESERVED32[512];   /**< Reserved registers */
-
   __IO uint32_t    FIFO12D[512];      /**< Host Channel 12 FIFO  */
 
   uint32_t         RESERVED33[512];   /**< Reserved registers */
-
   __IO uint32_t    FIFO13D[512];      /**< Host Channel 13 FIFO  */
 
   uint32_t         RESERVED34[17920]; /**< Reserved registers */
-
   __IO uint32_t    FIFORAM[512];      /**< Direct Access to Data FIFO RAM for Debugging (2 KB)  */
 } USB_TypeDef;                        /** @} */
 
@@ -321,12 +307,12 @@
 /* Bit fields for USB GOTGCTL */
 #define _USB_GOTGCTL_RESETVALUE                    0x00010000UL                             /**< Default value for USB_GOTGCTL */
 #define _USB_GOTGCTL_MASK                          0x001F0FFFUL                             /**< Mask for USB_GOTGCTL */
-#define USB_GOTGCTL_SESREQSCS                      (0x1UL << 0)                             /**< Session Request Success (device only) */
+#define USB_GOTGCTL_SESREQSCS                      (0x1UL << 0)                             /**< Session Request Success device only */
 #define _USB_GOTGCTL_SESREQSCS_SHIFT               0                                        /**< Shift value for USB_SESREQSCS */
 #define _USB_GOTGCTL_SESREQSCS_MASK                0x1UL                                    /**< Bit mask for USB_SESREQSCS */
 #define _USB_GOTGCTL_SESREQSCS_DEFAULT             0x00000000UL                             /**< Mode DEFAULT for USB_GOTGCTL */
 #define USB_GOTGCTL_SESREQSCS_DEFAULT              (_USB_GOTGCTL_SESREQSCS_DEFAULT << 0)    /**< Shifted mode DEFAULT for USB_GOTGCTL */
-#define USB_GOTGCTL_SESREQ                         (0x1UL << 1)                             /**< Session Request (device only) */
+#define USB_GOTGCTL_SESREQ                         (0x1UL << 1)                             /**< Session Request device only */
 #define _USB_GOTGCTL_SESREQ_SHIFT                  1                                        /**< Shift value for USB_SESREQ */
 #define _USB_GOTGCTL_SESREQ_MASK                   0x2UL                                    /**< Bit mask for USB_SESREQ */
 #define _USB_GOTGCTL_SESREQ_DEFAULT                0x00000000UL                             /**< Mode DEFAULT for USB_GOTGCTL */
@@ -361,27 +347,27 @@
 #define _USB_GOTGCTL_AVALIDOVVAL_MASK              0x80UL                                   /**< Bit mask for USB_AVALIDOVVAL */
 #define _USB_GOTGCTL_AVALIDOVVAL_DEFAULT           0x00000000UL                             /**< Mode DEFAULT for USB_GOTGCTL */
 #define USB_GOTGCTL_AVALIDOVVAL_DEFAULT            (_USB_GOTGCTL_AVALIDOVVAL_DEFAULT << 7)  /**< Shifted mode DEFAULT for USB_GOTGCTL */
-#define USB_GOTGCTL_HSTNEGSCS                      (0x1UL << 8)                             /**< Host Negotiation Success (device only) */
+#define USB_GOTGCTL_HSTNEGSCS                      (0x1UL << 8)                             /**< Host Negotiation Success device only */
 #define _USB_GOTGCTL_HSTNEGSCS_SHIFT               8                                        /**< Shift value for USB_HSTNEGSCS */
 #define _USB_GOTGCTL_HSTNEGSCS_MASK                0x100UL                                  /**< Bit mask for USB_HSTNEGSCS */
 #define _USB_GOTGCTL_HSTNEGSCS_DEFAULT             0x00000000UL                             /**< Mode DEFAULT for USB_GOTGCTL */
 #define USB_GOTGCTL_HSTNEGSCS_DEFAULT              (_USB_GOTGCTL_HSTNEGSCS_DEFAULT << 8)    /**< Shifted mode DEFAULT for USB_GOTGCTL */
-#define USB_GOTGCTL_HNPREQ                         (0x1UL << 9)                             /**< HNP Request (device only) */
+#define USB_GOTGCTL_HNPREQ                         (0x1UL << 9)                             /**< HNP Request device only */
 #define _USB_GOTGCTL_HNPREQ_SHIFT                  9                                        /**< Shift value for USB_HNPREQ */
 #define _USB_GOTGCTL_HNPREQ_MASK                   0x200UL                                  /**< Bit mask for USB_HNPREQ */
 #define _USB_GOTGCTL_HNPREQ_DEFAULT                0x00000000UL                             /**< Mode DEFAULT for USB_GOTGCTL */
 #define USB_GOTGCTL_HNPREQ_DEFAULT                 (_USB_GOTGCTL_HNPREQ_DEFAULT << 9)       /**< Shifted mode DEFAULT for USB_GOTGCTL */
-#define USB_GOTGCTL_HSTSETHNPEN                    (0x1UL << 10)                            /**< Host Set HNP Enable (host only) */
+#define USB_GOTGCTL_HSTSETHNPEN                    (0x1UL << 10)                            /**< Host Set HNP Enable host only */
 #define _USB_GOTGCTL_HSTSETHNPEN_SHIFT             10                                       /**< Shift value for USB_HSTSETHNPEN */
 #define _USB_GOTGCTL_HSTSETHNPEN_MASK              0x400UL                                  /**< Bit mask for USB_HSTSETHNPEN */
 #define _USB_GOTGCTL_HSTSETHNPEN_DEFAULT           0x00000000UL                             /**< Mode DEFAULT for USB_GOTGCTL */
 #define USB_GOTGCTL_HSTSETHNPEN_DEFAULT            (_USB_GOTGCTL_HSTSETHNPEN_DEFAULT << 10) /**< Shifted mode DEFAULT for USB_GOTGCTL */
-#define USB_GOTGCTL_DEVHNPEN                       (0x1UL << 11)                            /**< Device HNP Enabled (device only) */
+#define USB_GOTGCTL_DEVHNPEN                       (0x1UL << 11)                            /**< Device HNP Enabled device only */
 #define _USB_GOTGCTL_DEVHNPEN_SHIFT                11                                       /**< Shift value for USB_DEVHNPEN */
 #define _USB_GOTGCTL_DEVHNPEN_MASK                 0x800UL                                  /**< Bit mask for USB_DEVHNPEN */
 #define _USB_GOTGCTL_DEVHNPEN_DEFAULT              0x00000000UL                             /**< Mode DEFAULT for USB_GOTGCTL */
 #define USB_GOTGCTL_DEVHNPEN_DEFAULT               (_USB_GOTGCTL_DEVHNPEN_DEFAULT << 11)    /**< Shifted mode DEFAULT for USB_GOTGCTL */
-#define USB_GOTGCTL_CONIDSTS                       (0x1UL << 16)                            /**< Connector ID Status (host and device) */
+#define USB_GOTGCTL_CONIDSTS                       (0x1UL << 16)                            /**< Connector ID Status host and device */
 #define _USB_GOTGCTL_CONIDSTS_SHIFT                16                                       /**< Shift value for USB_CONIDSTS */
 #define _USB_GOTGCTL_CONIDSTS_MASK                 0x10000UL                                /**< Bit mask for USB_CONIDSTS */
 #define _USB_GOTGCTL_CONIDSTS_A                    0x00000000UL                             /**< Mode A for USB_GOTGCTL */
@@ -390,7 +376,7 @@
 #define USB_GOTGCTL_CONIDSTS_A                     (_USB_GOTGCTL_CONIDSTS_A << 16)          /**< Shifted mode A for USB_GOTGCTL */
 #define USB_GOTGCTL_CONIDSTS_DEFAULT               (_USB_GOTGCTL_CONIDSTS_DEFAULT << 16)    /**< Shifted mode DEFAULT for USB_GOTGCTL */
 #define USB_GOTGCTL_CONIDSTS_B                     (_USB_GOTGCTL_CONIDSTS_B << 16)          /**< Shifted mode B for USB_GOTGCTL */
-#define USB_GOTGCTL_DBNCTIME                       (0x1UL << 17)                            /**< Long/Short Debounce Time (host only) */
+#define USB_GOTGCTL_DBNCTIME                       (0x1UL << 17)                            /**< Long/Short Debounce Time host only */
 #define _USB_GOTGCTL_DBNCTIME_SHIFT                17                                       /**< Shift value for USB_DBNCTIME */
 #define _USB_GOTGCTL_DBNCTIME_MASK                 0x20000UL                                /**< Bit mask for USB_DBNCTIME */
 #define _USB_GOTGCTL_DBNCTIME_DEFAULT              0x00000000UL                             /**< Mode DEFAULT for USB_GOTGCTL */
@@ -399,12 +385,12 @@
 #define USB_GOTGCTL_DBNCTIME_DEFAULT               (_USB_GOTGCTL_DBNCTIME_DEFAULT << 17)    /**< Shifted mode DEFAULT for USB_GOTGCTL */
 #define USB_GOTGCTL_DBNCTIME_LONG                  (_USB_GOTGCTL_DBNCTIME_LONG << 17)       /**< Shifted mode LONG for USB_GOTGCTL */
 #define USB_GOTGCTL_DBNCTIME_SHORT                 (_USB_GOTGCTL_DBNCTIME_SHORT << 17)      /**< Shifted mode SHORT for USB_GOTGCTL */
-#define USB_GOTGCTL_ASESVLD                        (0x1UL << 18)                            /**< A-Session Valid (host only) */
+#define USB_GOTGCTL_ASESVLD                        (0x1UL << 18)                            /**< A-Session Valid host only */
 #define _USB_GOTGCTL_ASESVLD_SHIFT                 18                                       /**< Shift value for USB_ASESVLD */
 #define _USB_GOTGCTL_ASESVLD_MASK                  0x40000UL                                /**< Bit mask for USB_ASESVLD */
 #define _USB_GOTGCTL_ASESVLD_DEFAULT               0x00000000UL                             /**< Mode DEFAULT for USB_GOTGCTL */
 #define USB_GOTGCTL_ASESVLD_DEFAULT                (_USB_GOTGCTL_ASESVLD_DEFAULT << 18)     /**< Shifted mode DEFAULT for USB_GOTGCTL */
-#define USB_GOTGCTL_BSESVLD                        (0x1UL << 19)                            /**< B-Session Valid (device only) */
+#define USB_GOTGCTL_BSESVLD                        (0x1UL << 19)                            /**< B-Session Valid device only */
 #define _USB_GOTGCTL_BSESVLD_SHIFT                 19                                       /**< Shift value for USB_BSESVLD */
 #define _USB_GOTGCTL_BSESVLD_MASK                  0x80000UL                                /**< Bit mask for USB_BSESVLD */
 #define _USB_GOTGCTL_BSESVLD_DEFAULT               0x00000000UL                             /**< Mode DEFAULT for USB_GOTGCTL */
@@ -422,32 +408,32 @@
 /* Bit fields for USB GOTGINT */
 #define _USB_GOTGINT_RESETVALUE                    0x00000000UL                                 /**< Default value for USB_GOTGINT */
 #define _USB_GOTGINT_MASK                          0x000E0304UL                                 /**< Mask for USB_GOTGINT */
-#define USB_GOTGINT_SESENDDET                      (0x1UL << 2)                                 /**< Session End Detected (host and device) */
+#define USB_GOTGINT_SESENDDET                      (0x1UL << 2)                                 /**< Session End Detected host and device */
 #define _USB_GOTGINT_SESENDDET_SHIFT               2                                            /**< Shift value for USB_SESENDDET */
 #define _USB_GOTGINT_SESENDDET_MASK                0x4UL                                        /**< Bit mask for USB_SESENDDET */
 #define _USB_GOTGINT_SESENDDET_DEFAULT             0x00000000UL                                 /**< Mode DEFAULT for USB_GOTGINT */
 #define USB_GOTGINT_SESENDDET_DEFAULT              (_USB_GOTGINT_SESENDDET_DEFAULT << 2)        /**< Shifted mode DEFAULT for USB_GOTGINT */
-#define USB_GOTGINT_SESREQSUCSTSCHNG               (0x1UL << 8)                                 /**< Session Request Success Status Change (host and device) */
+#define USB_GOTGINT_SESREQSUCSTSCHNG               (0x1UL << 8)                                 /**< Session Request Success Status Change host and device */
 #define _USB_GOTGINT_SESREQSUCSTSCHNG_SHIFT        8                                            /**< Shift value for USB_SESREQSUCSTSCHNG */
 #define _USB_GOTGINT_SESREQSUCSTSCHNG_MASK         0x100UL                                      /**< Bit mask for USB_SESREQSUCSTSCHNG */
 #define _USB_GOTGINT_SESREQSUCSTSCHNG_DEFAULT      0x00000000UL                                 /**< Mode DEFAULT for USB_GOTGINT */
 #define USB_GOTGINT_SESREQSUCSTSCHNG_DEFAULT       (_USB_GOTGINT_SESREQSUCSTSCHNG_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_GOTGINT */
-#define USB_GOTGINT_HSTNEGSUCSTSCHNG               (0x1UL << 9)                                 /**< Host Negotiation Success Status Change (host and device) */
+#define USB_GOTGINT_HSTNEGSUCSTSCHNG               (0x1UL << 9)                                 /**< Host Negotiation Success Status Change host and device */
 #define _USB_GOTGINT_HSTNEGSUCSTSCHNG_SHIFT        9                                            /**< Shift value for USB_HSTNEGSUCSTSCHNG */
 #define _USB_GOTGINT_HSTNEGSUCSTSCHNG_MASK         0x200UL                                      /**< Bit mask for USB_HSTNEGSUCSTSCHNG */
 #define _USB_GOTGINT_HSTNEGSUCSTSCHNG_DEFAULT      0x00000000UL                                 /**< Mode DEFAULT for USB_GOTGINT */
 #define USB_GOTGINT_HSTNEGSUCSTSCHNG_DEFAULT       (_USB_GOTGINT_HSTNEGSUCSTSCHNG_DEFAULT << 9) /**< Shifted mode DEFAULT for USB_GOTGINT */
-#define USB_GOTGINT_HSTNEGDET                      (0x1UL << 17)                                /**< Host Negotiation Detected (host and device) */
+#define USB_GOTGINT_HSTNEGDET                      (0x1UL << 17)                                /**< Host Negotiation Detected host and device */
 #define _USB_GOTGINT_HSTNEGDET_SHIFT               17                                           /**< Shift value for USB_HSTNEGDET */
 #define _USB_GOTGINT_HSTNEGDET_MASK                0x20000UL                                    /**< Bit mask for USB_HSTNEGDET */
 #define _USB_GOTGINT_HSTNEGDET_DEFAULT             0x00000000UL                                 /**< Mode DEFAULT for USB_GOTGINT */
 #define USB_GOTGINT_HSTNEGDET_DEFAULT              (_USB_GOTGINT_HSTNEGDET_DEFAULT << 17)       /**< Shifted mode DEFAULT for USB_GOTGINT */
-#define USB_GOTGINT_ADEVTOUTCHG                    (0x1UL << 18)                                /**< A-Device Timeout Change (host and device) */
+#define USB_GOTGINT_ADEVTOUTCHG                    (0x1UL << 18)                                /**< A-Device Timeout Change host and device */
 #define _USB_GOTGINT_ADEVTOUTCHG_SHIFT             18                                           /**< Shift value for USB_ADEVTOUTCHG */
 #define _USB_GOTGINT_ADEVTOUTCHG_MASK              0x40000UL                                    /**< Bit mask for USB_ADEVTOUTCHG */
 #define _USB_GOTGINT_ADEVTOUTCHG_DEFAULT           0x00000000UL                                 /**< Mode DEFAULT for USB_GOTGINT */
 #define USB_GOTGINT_ADEVTOUTCHG_DEFAULT            (_USB_GOTGINT_ADEVTOUTCHG_DEFAULT << 18)     /**< Shifted mode DEFAULT for USB_GOTGINT */
-#define USB_GOTGINT_DBNCEDONE                      (0x1UL << 19)                                /**< Debounce Done (host only) */
+#define USB_GOTGINT_DBNCEDONE                      (0x1UL << 19)                                /**< Debounce Done host only */
 #define _USB_GOTGINT_DBNCEDONE_SHIFT               19                                           /**< Shift value for USB_DBNCEDONE */
 #define _USB_GOTGINT_DBNCEDONE_MASK                0x80000UL                                    /**< Bit mask for USB_DBNCEDONE */
 #define _USB_GOTGINT_DBNCEDONE_DEFAULT             0x00000000UL                                 /**< Mode DEFAULT for USB_GOTGINT */
@@ -456,7 +442,7 @@
 /* Bit fields for USB GAHBCFG */
 #define _USB_GAHBCFG_RESETVALUE                    0x00000000UL                                /**< Default value for USB_GAHBCFG */
 #define _USB_GAHBCFG_MASK                          0x006001BFUL                                /**< Mask for USB_GAHBCFG */
-#define USB_GAHBCFG_GLBLINTRMSK                    (0x1UL << 0)                                /**< Global Interrupt Mask (host and device) */
+#define USB_GAHBCFG_GLBLINTRMSK                    (0x1UL << 0)                                /**< Global Interrupt Mask host and device */
 #define _USB_GAHBCFG_GLBLINTRMSK_SHIFT             0                                           /**< Shift value for USB_GLBLINTRMSK */
 #define _USB_GAHBCFG_GLBLINTRMSK_MASK              0x1UL                                       /**< Bit mask for USB_GLBLINTRMSK */
 #define _USB_GAHBCFG_GLBLINTRMSK_DEFAULT           0x00000000UL                                /**< Mode DEFAULT for USB_GAHBCFG */
@@ -475,12 +461,12 @@
 #define USB_GAHBCFG_HBSTLEN_INCR4                  (_USB_GAHBCFG_HBSTLEN_INCR4 << 1)           /**< Shifted mode INCR4 for USB_GAHBCFG */
 #define USB_GAHBCFG_HBSTLEN_INCR8                  (_USB_GAHBCFG_HBSTLEN_INCR8 << 1)           /**< Shifted mode INCR8 for USB_GAHBCFG */
 #define USB_GAHBCFG_HBSTLEN_INCR16                 (_USB_GAHBCFG_HBSTLEN_INCR16 << 1)          /**< Shifted mode INCR16 for USB_GAHBCFG */
-#define USB_GAHBCFG_DMAEN                          (0x1UL << 5)                                /**< DMA Enable (host and device) */
+#define USB_GAHBCFG_DMAEN                          (0x1UL << 5)                                /**< DMA Enable host and device */
 #define _USB_GAHBCFG_DMAEN_SHIFT                   5                                           /**< Shift value for USB_DMAEN */
 #define _USB_GAHBCFG_DMAEN_MASK                    0x20UL                                      /**< Bit mask for USB_DMAEN */
 #define _USB_GAHBCFG_DMAEN_DEFAULT                 0x00000000UL                                /**< Mode DEFAULT for USB_GAHBCFG */
 #define USB_GAHBCFG_DMAEN_DEFAULT                  (_USB_GAHBCFG_DMAEN_DEFAULT << 5)           /**< Shifted mode DEFAULT for USB_GAHBCFG */
-#define USB_GAHBCFG_NPTXFEMPLVL                    (0x1UL << 7)                                /**< Non-Periodic TxFIFO Empty Level (host and device) */
+#define USB_GAHBCFG_NPTXFEMPLVL                    (0x1UL << 7)                                /**< Non-Periodic TxFIFO Empty Level host and device */
 #define _USB_GAHBCFG_NPTXFEMPLVL_SHIFT             7                                           /**< Shift value for USB_NPTXFEMPLVL */
 #define _USB_GAHBCFG_NPTXFEMPLVL_MASK              0x80UL                                      /**< Bit mask for USB_NPTXFEMPLVL */
 #define _USB_GAHBCFG_NPTXFEMPLVL_DEFAULT           0x00000000UL                                /**< Mode DEFAULT for USB_GAHBCFG */
@@ -489,7 +475,7 @@
 #define USB_GAHBCFG_NPTXFEMPLVL_DEFAULT            (_USB_GAHBCFG_NPTXFEMPLVL_DEFAULT << 7)     /**< Shifted mode DEFAULT for USB_GAHBCFG */
 #define USB_GAHBCFG_NPTXFEMPLVL_HALFEMPTY          (_USB_GAHBCFG_NPTXFEMPLVL_HALFEMPTY << 7)   /**< Shifted mode HALFEMPTY for USB_GAHBCFG */
 #define USB_GAHBCFG_NPTXFEMPLVL_EMPTY              (_USB_GAHBCFG_NPTXFEMPLVL_EMPTY << 7)       /**< Shifted mode EMPTY for USB_GAHBCFG */
-#define USB_GAHBCFG_PTXFEMPLVL                     (0x1UL << 8)                                /**< Periodic TxFIFO Empty Level (host only) */
+#define USB_GAHBCFG_PTXFEMPLVL                     (0x1UL << 8)                                /**< Periodic TxFIFO Empty Level host only */
 #define _USB_GAHBCFG_PTXFEMPLVL_SHIFT              8                                           /**< Shift value for USB_PTXFEMPLVL */
 #define _USB_GAHBCFG_PTXFEMPLVL_MASK               0x100UL                                     /**< Bit mask for USB_PTXFEMPLVL */
 #define _USB_GAHBCFG_PTXFEMPLVL_DEFAULT            0x00000000UL                                /**< Mode DEFAULT for USB_GAHBCFG */
@@ -516,17 +502,17 @@
 #define _USB_GUSBCFG_TOUTCAL_MASK                  0x7UL                                       /**< Bit mask for USB_TOUTCAL */
 #define _USB_GUSBCFG_TOUTCAL_DEFAULT               0x00000000UL                                /**< Mode DEFAULT for USB_GUSBCFG */
 #define USB_GUSBCFG_TOUTCAL_DEFAULT                (_USB_GUSBCFG_TOUTCAL_DEFAULT << 0)         /**< Shifted mode DEFAULT for USB_GUSBCFG */
-#define USB_GUSBCFG_FSINTF                         (0x1UL << 5)                                /**< Full-Speed Serial Interface Select (host and device) */
+#define USB_GUSBCFG_FSINTF                         (0x1UL << 5)                                /**< Full-Speed Serial Interface Select host and device */
 #define _USB_GUSBCFG_FSINTF_SHIFT                  5                                           /**< Shift value for USB_FSINTF */
 #define _USB_GUSBCFG_FSINTF_MASK                   0x20UL                                      /**< Bit mask for USB_FSINTF */
 #define _USB_GUSBCFG_FSINTF_DEFAULT                0x00000000UL                                /**< Mode DEFAULT for USB_GUSBCFG */
 #define USB_GUSBCFG_FSINTF_DEFAULT                 (_USB_GUSBCFG_FSINTF_DEFAULT << 5)          /**< Shifted mode DEFAULT for USB_GUSBCFG */
-#define USB_GUSBCFG_SRPCAP                         (0x1UL << 8)                                /**< SRP-Capable (host and device) */
+#define USB_GUSBCFG_SRPCAP                         (0x1UL << 8)                                /**< SRP-Capable host and device */
 #define _USB_GUSBCFG_SRPCAP_SHIFT                  8                                           /**< Shift value for USB_SRPCAP */
 #define _USB_GUSBCFG_SRPCAP_MASK                   0x100UL                                     /**< Bit mask for USB_SRPCAP */
 #define _USB_GUSBCFG_SRPCAP_DEFAULT                0x00000000UL                                /**< Mode DEFAULT for USB_GUSBCFG */
 #define USB_GUSBCFG_SRPCAP_DEFAULT                 (_USB_GUSBCFG_SRPCAP_DEFAULT << 8)          /**< Shifted mode DEFAULT for USB_GUSBCFG */
-#define USB_GUSBCFG_HNPCAP                         (0x1UL << 9)                                /**< HNP-Capable (host and device) */
+#define USB_GUSBCFG_HNPCAP                         (0x1UL << 9)                                /**< HNP-Capable host and device */
 #define _USB_GUSBCFG_HNPCAP_SHIFT                  9                                           /**< Shift value for USB_HNPCAP */
 #define _USB_GUSBCFG_HNPCAP_MASK                   0x200UL                                     /**< Bit mask for USB_HNPCAP */
 #define _USB_GUSBCFG_HNPCAP_DEFAULT                0x00000000UL                                /**< Mode DEFAULT for USB_GUSBCFG */
@@ -535,7 +521,7 @@
 #define _USB_GUSBCFG_USBTRDTIM_MASK                0x3C00UL                                    /**< Bit mask for USB_USBTRDTIM */
 #define _USB_GUSBCFG_USBTRDTIM_DEFAULT             0x00000005UL                                /**< Mode DEFAULT for USB_GUSBCFG */
 #define USB_GUSBCFG_USBTRDTIM_DEFAULT              (_USB_GUSBCFG_USBTRDTIM_DEFAULT << 10)      /**< Shifted mode DEFAULT for USB_GUSBCFG */
-#define USB_GUSBCFG_TERMSELDLPULSE                 (0x1UL << 22)                               /**< TermSel DLine Pulsing Selection (device only) */
+#define USB_GUSBCFG_TERMSELDLPULSE                 (0x1UL << 22)                               /**< TermSel DLine Pulsing Selection device only */
 #define _USB_GUSBCFG_TERMSELDLPULSE_SHIFT          22                                          /**< Shift value for USB_TERMSELDLPULSE */
 #define _USB_GUSBCFG_TERMSELDLPULSE_MASK           0x400000UL                                  /**< Bit mask for USB_TERMSELDLPULSE */
 #define _USB_GUSBCFG_TERMSELDLPULSE_DEFAULT        0x00000000UL                                /**< Mode DEFAULT for USB_GUSBCFG */
@@ -544,22 +530,22 @@
 #define USB_GUSBCFG_TERMSELDLPULSE_DEFAULT         (_USB_GUSBCFG_TERMSELDLPULSE_DEFAULT << 22) /**< Shifted mode DEFAULT for USB_GUSBCFG */
 #define USB_GUSBCFG_TERMSELDLPULSE_TXVALID         (_USB_GUSBCFG_TERMSELDLPULSE_TXVALID << 22) /**< Shifted mode TXVALID for USB_GUSBCFG */
 #define USB_GUSBCFG_TERMSELDLPULSE_TERMSEL         (_USB_GUSBCFG_TERMSELDLPULSE_TERMSEL << 22) /**< Shifted mode TERMSEL for USB_GUSBCFG */
-#define USB_GUSBCFG_TXENDDELAY                     (0x1UL << 28)                               /**< Tx End Delay (device only) */
+#define USB_GUSBCFG_TXENDDELAY                     (0x1UL << 28)                               /**< Tx End Delay device only */
 #define _USB_GUSBCFG_TXENDDELAY_SHIFT              28                                          /**< Shift value for USB_TXENDDELAY */
 #define _USB_GUSBCFG_TXENDDELAY_MASK               0x10000000UL                                /**< Bit mask for USB_TXENDDELAY */
 #define _USB_GUSBCFG_TXENDDELAY_DEFAULT            0x00000000UL                                /**< Mode DEFAULT for USB_GUSBCFG */
 #define USB_GUSBCFG_TXENDDELAY_DEFAULT             (_USB_GUSBCFG_TXENDDELAY_DEFAULT << 28)     /**< Shifted mode DEFAULT for USB_GUSBCFG */
-#define USB_GUSBCFG_FORCEHSTMODE                   (0x1UL << 29)                               /**< Force Host Mode (host and device) */
+#define USB_GUSBCFG_FORCEHSTMODE                   (0x1UL << 29)                               /**< Force Host Mode host and device */
 #define _USB_GUSBCFG_FORCEHSTMODE_SHIFT            29                                          /**< Shift value for USB_FORCEHSTMODE */
 #define _USB_GUSBCFG_FORCEHSTMODE_MASK             0x20000000UL                                /**< Bit mask for USB_FORCEHSTMODE */
 #define _USB_GUSBCFG_FORCEHSTMODE_DEFAULT          0x00000000UL                                /**< Mode DEFAULT for USB_GUSBCFG */
 #define USB_GUSBCFG_FORCEHSTMODE_DEFAULT           (_USB_GUSBCFG_FORCEHSTMODE_DEFAULT << 29)   /**< Shifted mode DEFAULT for USB_GUSBCFG */
-#define USB_GUSBCFG_FORCEDEVMODE                   (0x1UL << 30)                               /**< Force Device Mode (host and device) */
+#define USB_GUSBCFG_FORCEDEVMODE                   (0x1UL << 30)                               /**< Force Device Mode host and device */
 #define _USB_GUSBCFG_FORCEDEVMODE_SHIFT            30                                          /**< Shift value for USB_FORCEDEVMODE */
 #define _USB_GUSBCFG_FORCEDEVMODE_MASK             0x40000000UL                                /**< Bit mask for USB_FORCEDEVMODE */
 #define _USB_GUSBCFG_FORCEDEVMODE_DEFAULT          0x00000000UL                                /**< Mode DEFAULT for USB_GUSBCFG */
 #define USB_GUSBCFG_FORCEDEVMODE_DEFAULT           (_USB_GUSBCFG_FORCEDEVMODE_DEFAULT << 30)   /**< Shifted mode DEFAULT for USB_GUSBCFG */
-#define USB_GUSBCFG_CORRUPTTXPKT                   (0x1UL << 31)                               /**< Corrupt Tx packet (host and device) */
+#define USB_GUSBCFG_CORRUPTTXPKT                   (0x1UL << 31)                               /**< Corrupt Tx packet host and device */
 #define _USB_GUSBCFG_CORRUPTTXPKT_SHIFT            31                                          /**< Shift value for USB_CORRUPTTXPKT */
 #define _USB_GUSBCFG_CORRUPTTXPKT_MASK             0x80000000UL                                /**< Bit mask for USB_CORRUPTTXPKT */
 #define _USB_GUSBCFG_CORRUPTTXPKT_DEFAULT          0x00000000UL                                /**< Mode DEFAULT for USB_GUSBCFG */
@@ -568,22 +554,22 @@
 /* Bit fields for USB GRSTCTL */
 #define _USB_GRSTCTL_RESETVALUE                    0x80000000UL                           /**< Default value for USB_GRSTCTL */
 #define _USB_GRSTCTL_MASK                          0xC00007F5UL                           /**< Mask for USB_GRSTCTL */
-#define USB_GRSTCTL_CSFTRST                        (0x1UL << 0)                           /**< Core Soft Reset (host and device) */
+#define USB_GRSTCTL_CSFTRST                        (0x1UL << 0)                           /**< Core Soft Reset host and device */
 #define _USB_GRSTCTL_CSFTRST_SHIFT                 0                                      /**< Shift value for USB_CSFTRST */
 #define _USB_GRSTCTL_CSFTRST_MASK                  0x1UL                                  /**< Bit mask for USB_CSFTRST */
 #define _USB_GRSTCTL_CSFTRST_DEFAULT               0x00000000UL                           /**< Mode DEFAULT for USB_GRSTCTL */
 #define USB_GRSTCTL_CSFTRST_DEFAULT                (_USB_GRSTCTL_CSFTRST_DEFAULT << 0)    /**< Shifted mode DEFAULT for USB_GRSTCTL */
-#define USB_GRSTCTL_FRMCNTRRST                     (0x1UL << 2)                           /**< Host Frame Counter Reset (host only) */
+#define USB_GRSTCTL_FRMCNTRRST                     (0x1UL << 2)                           /**< Host Frame Counter Reset host only */
 #define _USB_GRSTCTL_FRMCNTRRST_SHIFT              2                                      /**< Shift value for USB_FRMCNTRRST */
 #define _USB_GRSTCTL_FRMCNTRRST_MASK               0x4UL                                  /**< Bit mask for USB_FRMCNTRRST */
 #define _USB_GRSTCTL_FRMCNTRRST_DEFAULT            0x00000000UL                           /**< Mode DEFAULT for USB_GRSTCTL */
 #define USB_GRSTCTL_FRMCNTRRST_DEFAULT             (_USB_GRSTCTL_FRMCNTRRST_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_GRSTCTL */
-#define USB_GRSTCTL_RXFFLSH                        (0x1UL << 4)                           /**< RxFIFO Flush (host and device) */
+#define USB_GRSTCTL_RXFFLSH                        (0x1UL << 4)                           /**< RxFIFO Flush host and device */
 #define _USB_GRSTCTL_RXFFLSH_SHIFT                 4                                      /**< Shift value for USB_RXFFLSH */
 #define _USB_GRSTCTL_RXFFLSH_MASK                  0x10UL                                 /**< Bit mask for USB_RXFFLSH */
 #define _USB_GRSTCTL_RXFFLSH_DEFAULT               0x00000000UL                           /**< Mode DEFAULT for USB_GRSTCTL */
 #define USB_GRSTCTL_RXFFLSH_DEFAULT                (_USB_GRSTCTL_RXFFLSH_DEFAULT << 4)    /**< Shifted mode DEFAULT for USB_GRSTCTL */
-#define USB_GRSTCTL_TXFFLSH                        (0x1UL << 5)                           /**< TxFIFO Flush (host and device) */
+#define USB_GRSTCTL_TXFFLSH                        (0x1UL << 5)                           /**< TxFIFO Flush host and device */
 #define _USB_GRSTCTL_TXFFLSH_SHIFT                 5                                      /**< Shift value for USB_TXFFLSH */
 #define _USB_GRSTCTL_TXFFLSH_MASK                  0x20UL                                 /**< Bit mask for USB_TXFFLSH */
 #define _USB_GRSTCTL_TXFFLSH_DEFAULT               0x00000000UL                           /**< Mode DEFAULT for USB_GRSTCTL */
@@ -608,12 +594,12 @@
 #define USB_GRSTCTL_TXFNUM_F5                      (_USB_GRSTCTL_TXFNUM_F5 << 6)          /**< Shifted mode F5 for USB_GRSTCTL */
 #define USB_GRSTCTL_TXFNUM_F6                      (_USB_GRSTCTL_TXFNUM_F6 << 6)          /**< Shifted mode F6 for USB_GRSTCTL */
 #define USB_GRSTCTL_TXFNUM_FALL                    (_USB_GRSTCTL_TXFNUM_FALL << 6)        /**< Shifted mode FALL for USB_GRSTCTL */
-#define USB_GRSTCTL_DMAREQ                         (0x1UL << 30)                          /**< DMA Request Signal (host and device) */
+#define USB_GRSTCTL_DMAREQ                         (0x1UL << 30)                          /**< DMA Request Signal host and device */
 #define _USB_GRSTCTL_DMAREQ_SHIFT                  30                                     /**< Shift value for USB_DMAREQ */
 #define _USB_GRSTCTL_DMAREQ_MASK                   0x40000000UL                           /**< Bit mask for USB_DMAREQ */
 #define _USB_GRSTCTL_DMAREQ_DEFAULT                0x00000000UL                           /**< Mode DEFAULT for USB_GRSTCTL */
 #define USB_GRSTCTL_DMAREQ_DEFAULT                 (_USB_GRSTCTL_DMAREQ_DEFAULT << 30)    /**< Shifted mode DEFAULT for USB_GRSTCTL */
-#define USB_GRSTCTL_AHBIDLE                        (0x1UL << 31)                          /**< AHB Master Idle (host and device) */
+#define USB_GRSTCTL_AHBIDLE                        (0x1UL << 31)                          /**< AHB Master Idle host and device */
 #define _USB_GRSTCTL_AHBIDLE_SHIFT                 31                                     /**< Shift value for USB_AHBIDLE */
 #define _USB_GRSTCTL_AHBIDLE_MASK                  0x80000000UL                           /**< Bit mask for USB_AHBIDLE */
 #define _USB_GRSTCTL_AHBIDLE_DEFAULT               0x00000001UL                           /**< Mode DEFAULT for USB_GRSTCTL */
@@ -621,8 +607,8 @@
 
 /* Bit fields for USB GINTSTS */
 #define _USB_GINTSTS_RESETVALUE                    0x14000020UL                              /**< Default value for USB_GINTSTS */
-#define _USB_GINTSTS_MASK                          0xF7FC7CFFUL                              /**< Mask for USB_GINTSTS */
-#define USB_GINTSTS_CURMOD                         (0x1UL << 0)                              /**< Current Mode of Operation (host and device) */
+#define _USB_GINTSTS_MASK                          0xF7FCFCFFUL                              /**< Mask for USB_GINTSTS */
+#define USB_GINTSTS_CURMOD                         (0x1UL << 0)                              /**< Current Mode of Operation host and device */
 #define _USB_GINTSTS_CURMOD_SHIFT                  0                                         /**< Shift value for USB_CURMOD */
 #define _USB_GINTSTS_CURMOD_MASK                   0x1UL                                     /**< Bit mask for USB_CURMOD */
 #define _USB_GINTSTS_CURMOD_DEFAULT                0x00000000UL                              /**< Mode DEFAULT for USB_GINTSTS */
@@ -631,127 +617,132 @@
 #define USB_GINTSTS_CURMOD_DEFAULT                 (_USB_GINTSTS_CURMOD_DEFAULT << 0)        /**< Shifted mode DEFAULT for USB_GINTSTS */
 #define USB_GINTSTS_CURMOD_DEVICE                  (_USB_GINTSTS_CURMOD_DEVICE << 0)         /**< Shifted mode DEVICE for USB_GINTSTS */
 #define USB_GINTSTS_CURMOD_HOST                    (_USB_GINTSTS_CURMOD_HOST << 0)           /**< Shifted mode HOST for USB_GINTSTS */
-#define USB_GINTSTS_MODEMIS                        (0x1UL << 1)                              /**< Mode Mismatch Interrupt (host and device) */
+#define USB_GINTSTS_MODEMIS                        (0x1UL << 1)                              /**< Mode Mismatch Interrupt host and device */
 #define _USB_GINTSTS_MODEMIS_SHIFT                 1                                         /**< Shift value for USB_MODEMIS */
 #define _USB_GINTSTS_MODEMIS_MASK                  0x2UL                                     /**< Bit mask for USB_MODEMIS */
 #define _USB_GINTSTS_MODEMIS_DEFAULT               0x00000000UL                              /**< Mode DEFAULT for USB_GINTSTS */
 #define USB_GINTSTS_MODEMIS_DEFAULT                (_USB_GINTSTS_MODEMIS_DEFAULT << 1)       /**< Shifted mode DEFAULT for USB_GINTSTS */
-#define USB_GINTSTS_OTGINT                         (0x1UL << 2)                              /**< OTG Interrupt (host and device) */
+#define USB_GINTSTS_OTGINT                         (0x1UL << 2)                              /**< OTG Interrupt host and device */
 #define _USB_GINTSTS_OTGINT_SHIFT                  2                                         /**< Shift value for USB_OTGINT */
 #define _USB_GINTSTS_OTGINT_MASK                   0x4UL                                     /**< Bit mask for USB_OTGINT */
 #define _USB_GINTSTS_OTGINT_DEFAULT                0x00000000UL                              /**< Mode DEFAULT for USB_GINTSTS */
 #define USB_GINTSTS_OTGINT_DEFAULT                 (_USB_GINTSTS_OTGINT_DEFAULT << 2)        /**< Shifted mode DEFAULT for USB_GINTSTS */
-#define USB_GINTSTS_SOF                            (0x1UL << 3)                              /**< Start of Frame (host and device) */
+#define USB_GINTSTS_SOF                            (0x1UL << 3)                              /**< Start of Frame host and device */
 #define _USB_GINTSTS_SOF_SHIFT                     3                                         /**< Shift value for USB_SOF */
 #define _USB_GINTSTS_SOF_MASK                      0x8UL                                     /**< Bit mask for USB_SOF */
 #define _USB_GINTSTS_SOF_DEFAULT                   0x00000000UL                              /**< Mode DEFAULT for USB_GINTSTS */
 #define USB_GINTSTS_SOF_DEFAULT                    (_USB_GINTSTS_SOF_DEFAULT << 3)           /**< Shifted mode DEFAULT for USB_GINTSTS */
-#define USB_GINTSTS_RXFLVL                         (0x1UL << 4)                              /**< RxFIFO Non-Empty (host and device) */
+#define USB_GINTSTS_RXFLVL                         (0x1UL << 4)                              /**< RxFIFO Non-Empty host and device */
 #define _USB_GINTSTS_RXFLVL_SHIFT                  4                                         /**< Shift value for USB_RXFLVL */
 #define _USB_GINTSTS_RXFLVL_MASK                   0x10UL                                    /**< Bit mask for USB_RXFLVL */
 #define _USB_GINTSTS_RXFLVL_DEFAULT                0x00000000UL                              /**< Mode DEFAULT for USB_GINTSTS */
 #define USB_GINTSTS_RXFLVL_DEFAULT                 (_USB_GINTSTS_RXFLVL_DEFAULT << 4)        /**< Shifted mode DEFAULT for USB_GINTSTS */
-#define USB_GINTSTS_NPTXFEMP                       (0x1UL << 5)                              /**< Non-Periodic TxFIFO Empty (host only) */
+#define USB_GINTSTS_NPTXFEMP                       (0x1UL << 5)                              /**< Non-Periodic TxFIFO Empty host only */
 #define _USB_GINTSTS_NPTXFEMP_SHIFT                5                                         /**< Shift value for USB_NPTXFEMP */
 #define _USB_GINTSTS_NPTXFEMP_MASK                 0x20UL                                    /**< Bit mask for USB_NPTXFEMP */
 #define _USB_GINTSTS_NPTXFEMP_DEFAULT              0x00000001UL                              /**< Mode DEFAULT for USB_GINTSTS */
 #define USB_GINTSTS_NPTXFEMP_DEFAULT               (_USB_GINTSTS_NPTXFEMP_DEFAULT << 5)      /**< Shifted mode DEFAULT for USB_GINTSTS */
-#define USB_GINTSTS_GINNAKEFF                      (0x1UL << 6)                              /**< Global IN Non-periodic NAK Effective (device only) */
+#define USB_GINTSTS_GINNAKEFF                      (0x1UL << 6)                              /**< Global IN Non-periodic NAK Effective device only */
 #define _USB_GINTSTS_GINNAKEFF_SHIFT               6                                         /**< Shift value for USB_GINNAKEFF */
 #define _USB_GINTSTS_GINNAKEFF_MASK                0x40UL                                    /**< Bit mask for USB_GINNAKEFF */
 #define _USB_GINTSTS_GINNAKEFF_DEFAULT             0x00000000UL                              /**< Mode DEFAULT for USB_GINTSTS */
 #define USB_GINTSTS_GINNAKEFF_DEFAULT              (_USB_GINTSTS_GINNAKEFF_DEFAULT << 6)     /**< Shifted mode DEFAULT for USB_GINTSTS */
-#define USB_GINTSTS_GOUTNAKEFF                     (0x1UL << 7)                              /**< Global OUT NAK Effective (device only) */
+#define USB_GINTSTS_GOUTNAKEFF                     (0x1UL << 7)                              /**< Global OUT NAK Effective device only */
 #define _USB_GINTSTS_GOUTNAKEFF_SHIFT              7                                         /**< Shift value for USB_GOUTNAKEFF */
 #define _USB_GINTSTS_GOUTNAKEFF_MASK               0x80UL                                    /**< Bit mask for USB_GOUTNAKEFF */
 #define _USB_GINTSTS_GOUTNAKEFF_DEFAULT            0x00000000UL                              /**< Mode DEFAULT for USB_GINTSTS */
 #define USB_GINTSTS_GOUTNAKEFF_DEFAULT             (_USB_GINTSTS_GOUTNAKEFF_DEFAULT << 7)    /**< Shifted mode DEFAULT for USB_GINTSTS */
-#define USB_GINTSTS_ERLYSUSP                       (0x1UL << 10)                             /**< Early Suspend (device only) */
+#define USB_GINTSTS_ERLYSUSP                       (0x1UL << 10)                             /**< Early Suspend device only */
 #define _USB_GINTSTS_ERLYSUSP_SHIFT                10                                        /**< Shift value for USB_ERLYSUSP */
 #define _USB_GINTSTS_ERLYSUSP_MASK                 0x400UL                                   /**< Bit mask for USB_ERLYSUSP */
 #define _USB_GINTSTS_ERLYSUSP_DEFAULT              0x00000000UL                              /**< Mode DEFAULT for USB_GINTSTS */
 #define USB_GINTSTS_ERLYSUSP_DEFAULT               (_USB_GINTSTS_ERLYSUSP_DEFAULT << 10)     /**< Shifted mode DEFAULT for USB_GINTSTS */
-#define USB_GINTSTS_USBSUSP                        (0x1UL << 11)                             /**< USB Suspend (device only) */
+#define USB_GINTSTS_USBSUSP                        (0x1UL << 11)                             /**< USB Suspend device only */
 #define _USB_GINTSTS_USBSUSP_SHIFT                 11                                        /**< Shift value for USB_USBSUSP */
 #define _USB_GINTSTS_USBSUSP_MASK                  0x800UL                                   /**< Bit mask for USB_USBSUSP */
 #define _USB_GINTSTS_USBSUSP_DEFAULT               0x00000000UL                              /**< Mode DEFAULT for USB_GINTSTS */
 #define USB_GINTSTS_USBSUSP_DEFAULT                (_USB_GINTSTS_USBSUSP_DEFAULT << 11)      /**< Shifted mode DEFAULT for USB_GINTSTS */
-#define USB_GINTSTS_USBRST                         (0x1UL << 12)                             /**< USB Reset (device only) */
+#define USB_GINTSTS_USBRST                         (0x1UL << 12)                             /**< USB Reset device only */
 #define _USB_GINTSTS_USBRST_SHIFT                  12                                        /**< Shift value for USB_USBRST */
 #define _USB_GINTSTS_USBRST_MASK                   0x1000UL                                  /**< Bit mask for USB_USBRST */
 #define _USB_GINTSTS_USBRST_DEFAULT                0x00000000UL                              /**< Mode DEFAULT for USB_GINTSTS */
 #define USB_GINTSTS_USBRST_DEFAULT                 (_USB_GINTSTS_USBRST_DEFAULT << 12)       /**< Shifted mode DEFAULT for USB_GINTSTS */
-#define USB_GINTSTS_ENUMDONE                       (0x1UL << 13)                             /**< Enumeration Done (device only) */
+#define USB_GINTSTS_ENUMDONE                       (0x1UL << 13)                             /**< Enumeration Done device only */
 #define _USB_GINTSTS_ENUMDONE_SHIFT                13                                        /**< Shift value for USB_ENUMDONE */
 #define _USB_GINTSTS_ENUMDONE_MASK                 0x2000UL                                  /**< Bit mask for USB_ENUMDONE */
 #define _USB_GINTSTS_ENUMDONE_DEFAULT              0x00000000UL                              /**< Mode DEFAULT for USB_GINTSTS */
 #define USB_GINTSTS_ENUMDONE_DEFAULT               (_USB_GINTSTS_ENUMDONE_DEFAULT << 13)     /**< Shifted mode DEFAULT for USB_GINTSTS */
-#define USB_GINTSTS_ISOOUTDROP                     (0x1UL << 14)                             /**< Isochronous OUT Packet Dropped Interrupt (device only) */
+#define USB_GINTSTS_ISOOUTDROP                     (0x1UL << 14)                             /**< Isochronous OUT Packet Dropped Interrupt device only */
 #define _USB_GINTSTS_ISOOUTDROP_SHIFT              14                                        /**< Shift value for USB_ISOOUTDROP */
 #define _USB_GINTSTS_ISOOUTDROP_MASK               0x4000UL                                  /**< Bit mask for USB_ISOOUTDROP */
 #define _USB_GINTSTS_ISOOUTDROP_DEFAULT            0x00000000UL                              /**< Mode DEFAULT for USB_GINTSTS */
 #define USB_GINTSTS_ISOOUTDROP_DEFAULT             (_USB_GINTSTS_ISOOUTDROP_DEFAULT << 14)   /**< Shifted mode DEFAULT for USB_GINTSTS */
-#define USB_GINTSTS_IEPINT                         (0x1UL << 18)                             /**< IN Endpoints Interrupt (device only) */
+#define USB_GINTSTS_EOPF                           (0x1UL << 15)                             /**< End of Periodic Frame Interrupt */
+#define _USB_GINTSTS_EOPF_SHIFT                    15                                        /**< Shift value for USB_EOPF */
+#define _USB_GINTSTS_EOPF_MASK                     0x8000UL                                  /**< Bit mask for USB_EOPF */
+#define _USB_GINTSTS_EOPF_DEFAULT                  0x00000000UL                              /**< Mode DEFAULT for USB_GINTSTS */
+#define USB_GINTSTS_EOPF_DEFAULT                   (_USB_GINTSTS_EOPF_DEFAULT << 15)         /**< Shifted mode DEFAULT for USB_GINTSTS */
+#define USB_GINTSTS_IEPINT                         (0x1UL << 18)                             /**< IN Endpoints Interrupt device only */
 #define _USB_GINTSTS_IEPINT_SHIFT                  18                                        /**< Shift value for USB_IEPINT */
 #define _USB_GINTSTS_IEPINT_MASK                   0x40000UL                                 /**< Bit mask for USB_IEPINT */
 #define _USB_GINTSTS_IEPINT_DEFAULT                0x00000000UL                              /**< Mode DEFAULT for USB_GINTSTS */
 #define USB_GINTSTS_IEPINT_DEFAULT                 (_USB_GINTSTS_IEPINT_DEFAULT << 18)       /**< Shifted mode DEFAULT for USB_GINTSTS */
-#define USB_GINTSTS_OEPINT                         (0x1UL << 19)                             /**< OUT Endpoints Interrupt (device only) */
+#define USB_GINTSTS_OEPINT                         (0x1UL << 19)                             /**< OUT Endpoints Interrupt device only */
 #define _USB_GINTSTS_OEPINT_SHIFT                  19                                        /**< Shift value for USB_OEPINT */
 #define _USB_GINTSTS_OEPINT_MASK                   0x80000UL                                 /**< Bit mask for USB_OEPINT */
 #define _USB_GINTSTS_OEPINT_DEFAULT                0x00000000UL                              /**< Mode DEFAULT for USB_GINTSTS */
 #define USB_GINTSTS_OEPINT_DEFAULT                 (_USB_GINTSTS_OEPINT_DEFAULT << 19)       /**< Shifted mode DEFAULT for USB_GINTSTS */
-#define USB_GINTSTS_INCOMPISOIN                    (0x1UL << 20)                             /**< Incomplete Isochronous IN Transfer (device only) */
+#define USB_GINTSTS_INCOMPISOIN                    (0x1UL << 20)                             /**< Incomplete Isochronous IN Transfer device only */
 #define _USB_GINTSTS_INCOMPISOIN_SHIFT             20                                        /**< Shift value for USB_INCOMPISOIN */
 #define _USB_GINTSTS_INCOMPISOIN_MASK              0x100000UL                                /**< Bit mask for USB_INCOMPISOIN */
 #define _USB_GINTSTS_INCOMPISOIN_DEFAULT           0x00000000UL                              /**< Mode DEFAULT for USB_GINTSTS */
 #define USB_GINTSTS_INCOMPISOIN_DEFAULT            (_USB_GINTSTS_INCOMPISOIN_DEFAULT << 20)  /**< Shifted mode DEFAULT for USB_GINTSTS */
-#define USB_GINTSTS_INCOMPLP                       (0x1UL << 21)                             /**< Incomplete Periodic Transfer (device only) */
+#define USB_GINTSTS_INCOMPLP                       (0x1UL << 21)                             /**< Incomplete Periodic Transfer host and device */
 #define _USB_GINTSTS_INCOMPLP_SHIFT                21                                        /**< Shift value for USB_INCOMPLP */
 #define _USB_GINTSTS_INCOMPLP_MASK                 0x200000UL                                /**< Bit mask for USB_INCOMPLP */
 #define _USB_GINTSTS_INCOMPLP_DEFAULT              0x00000000UL                              /**< Mode DEFAULT for USB_GINTSTS */
 #define USB_GINTSTS_INCOMPLP_DEFAULT               (_USB_GINTSTS_INCOMPLP_DEFAULT << 21)     /**< Shifted mode DEFAULT for USB_GINTSTS */
-#define USB_GINTSTS_FETSUSP                        (0x1UL << 22)                             /**< Data Fetch Suspended (device only) */
+#define USB_GINTSTS_FETSUSP                        (0x1UL << 22)                             /**< Data Fetch Suspended device only */
 #define _USB_GINTSTS_FETSUSP_SHIFT                 22                                        /**< Shift value for USB_FETSUSP */
 #define _USB_GINTSTS_FETSUSP_MASK                  0x400000UL                                /**< Bit mask for USB_FETSUSP */
 #define _USB_GINTSTS_FETSUSP_DEFAULT               0x00000000UL                              /**< Mode DEFAULT for USB_GINTSTS */
 #define USB_GINTSTS_FETSUSP_DEFAULT                (_USB_GINTSTS_FETSUSP_DEFAULT << 22)      /**< Shifted mode DEFAULT for USB_GINTSTS */
-#define USB_GINTSTS_RESETDET                       (0x1UL << 23)                             /**< Reset detected Interrupt (device only) */
+#define USB_GINTSTS_RESETDET                       (0x1UL << 23)                             /**< Reset detected Interrupt device only */
 #define _USB_GINTSTS_RESETDET_SHIFT                23                                        /**< Shift value for USB_RESETDET */
 #define _USB_GINTSTS_RESETDET_MASK                 0x800000UL                                /**< Bit mask for USB_RESETDET */
 #define _USB_GINTSTS_RESETDET_DEFAULT              0x00000000UL                              /**< Mode DEFAULT for USB_GINTSTS */
 #define USB_GINTSTS_RESETDET_DEFAULT               (_USB_GINTSTS_RESETDET_DEFAULT << 23)     /**< Shifted mode DEFAULT for USB_GINTSTS */
-#define USB_GINTSTS_PRTINT                         (0x1UL << 24)                             /**< Host Port Interrupt (host only) */
+#define USB_GINTSTS_PRTINT                         (0x1UL << 24)                             /**< Host Port Interrupt host only */
 #define _USB_GINTSTS_PRTINT_SHIFT                  24                                        /**< Shift value for USB_PRTINT */
 #define _USB_GINTSTS_PRTINT_MASK                   0x1000000UL                               /**< Bit mask for USB_PRTINT */
 #define _USB_GINTSTS_PRTINT_DEFAULT                0x00000000UL                              /**< Mode DEFAULT for USB_GINTSTS */
 #define USB_GINTSTS_PRTINT_DEFAULT                 (_USB_GINTSTS_PRTINT_DEFAULT << 24)       /**< Shifted mode DEFAULT for USB_GINTSTS */
-#define USB_GINTSTS_HCHINT                         (0x1UL << 25)                             /**< Host Channels Interrupt (host only) */
+#define USB_GINTSTS_HCHINT                         (0x1UL << 25)                             /**< Host Channels Interrupt host only */
 #define _USB_GINTSTS_HCHINT_SHIFT                  25                                        /**< Shift value for USB_HCHINT */
 #define _USB_GINTSTS_HCHINT_MASK                   0x2000000UL                               /**< Bit mask for USB_HCHINT */
 #define _USB_GINTSTS_HCHINT_DEFAULT                0x00000000UL                              /**< Mode DEFAULT for USB_GINTSTS */
 #define USB_GINTSTS_HCHINT_DEFAULT                 (_USB_GINTSTS_HCHINT_DEFAULT << 25)       /**< Shifted mode DEFAULT for USB_GINTSTS */
-#define USB_GINTSTS_PTXFEMP                        (0x1UL << 26)                             /**< Periodic TxFIFO Empty (host only) */
+#define USB_GINTSTS_PTXFEMP                        (0x1UL << 26)                             /**< Periodic TxFIFO Empty host only */
 #define _USB_GINTSTS_PTXFEMP_SHIFT                 26                                        /**< Shift value for USB_PTXFEMP */
 #define _USB_GINTSTS_PTXFEMP_MASK                  0x4000000UL                               /**< Bit mask for USB_PTXFEMP */
 #define _USB_GINTSTS_PTXFEMP_DEFAULT               0x00000001UL                              /**< Mode DEFAULT for USB_GINTSTS */
 #define USB_GINTSTS_PTXFEMP_DEFAULT                (_USB_GINTSTS_PTXFEMP_DEFAULT << 26)      /**< Shifted mode DEFAULT for USB_GINTSTS */
-#define USB_GINTSTS_CONIDSTSCHNG                   (0x1UL << 28)                             /**< Connector ID Status Change (host and device) */
+#define USB_GINTSTS_CONIDSTSCHNG                   (0x1UL << 28)                             /**< Connector ID Status Change host and device */
 #define _USB_GINTSTS_CONIDSTSCHNG_SHIFT            28                                        /**< Shift value for USB_CONIDSTSCHNG */
 #define _USB_GINTSTS_CONIDSTSCHNG_MASK             0x10000000UL                              /**< Bit mask for USB_CONIDSTSCHNG */
 #define _USB_GINTSTS_CONIDSTSCHNG_DEFAULT          0x00000001UL                              /**< Mode DEFAULT for USB_GINTSTS */
 #define USB_GINTSTS_CONIDSTSCHNG_DEFAULT           (_USB_GINTSTS_CONIDSTSCHNG_DEFAULT << 28) /**< Shifted mode DEFAULT for USB_GINTSTS */
-#define USB_GINTSTS_DISCONNINT                     (0x1UL << 29)                             /**< Disconnect Detected Interrupt (host only) */
+#define USB_GINTSTS_DISCONNINT                     (0x1UL << 29)                             /**< Disconnect Detected Interrupt host only */
 #define _USB_GINTSTS_DISCONNINT_SHIFT              29                                        /**< Shift value for USB_DISCONNINT */
 #define _USB_GINTSTS_DISCONNINT_MASK               0x20000000UL                              /**< Bit mask for USB_DISCONNINT */
 #define _USB_GINTSTS_DISCONNINT_DEFAULT            0x00000000UL                              /**< Mode DEFAULT for USB_GINTSTS */
 #define USB_GINTSTS_DISCONNINT_DEFAULT             (_USB_GINTSTS_DISCONNINT_DEFAULT << 29)   /**< Shifted mode DEFAULT for USB_GINTSTS */
-#define USB_GINTSTS_SESSREQINT                     (0x1UL << 30)                             /**< Session Request/New Session Detected Interrupt (host and device) */
+#define USB_GINTSTS_SESSREQINT                     (0x1UL << 30)                             /**< Session Request/New Session Detected Interrupt host and device */
 #define _USB_GINTSTS_SESSREQINT_SHIFT              30                                        /**< Shift value for USB_SESSREQINT */
 #define _USB_GINTSTS_SESSREQINT_MASK               0x40000000UL                              /**< Bit mask for USB_SESSREQINT */
 #define _USB_GINTSTS_SESSREQINT_DEFAULT            0x00000000UL                              /**< Mode DEFAULT for USB_GINTSTS */
 #define USB_GINTSTS_SESSREQINT_DEFAULT             (_USB_GINTSTS_SESSREQINT_DEFAULT << 30)   /**< Shifted mode DEFAULT for USB_GINTSTS */
-#define USB_GINTSTS_WKUPINT                        (0x1UL << 31)                             /**< Resume/Remote Wakeup Detected Interrupt (host and device) */
+#define USB_GINTSTS_WKUPINT                        (0x1UL << 31)                             /**< Resume/Remote Wakeup Detected Interrupt host and device */
 #define _USB_GINTSTS_WKUPINT_SHIFT                 31                                        /**< Shift value for USB_WKUPINT */
 #define _USB_GINTSTS_WKUPINT_MASK                  0x80000000UL                              /**< Bit mask for USB_WKUPINT */
 #define _USB_GINTSTS_WKUPINT_DEFAULT               0x00000000UL                              /**< Mode DEFAULT for USB_GINTSTS */
@@ -759,128 +750,133 @@
 
 /* Bit fields for USB GINTMSK */
 #define _USB_GINTMSK_RESETVALUE                    0x00000000UL                                 /**< Default value for USB_GINTMSK */
-#define _USB_GINTMSK_MASK                          0xF7FC7CFEUL                                 /**< Mask for USB_GINTMSK */
-#define USB_GINTMSK_MODEMISMSK                     (0x1UL << 1)                                 /**< Mode Mismatch Interrupt Mask (host and device) */
+#define _USB_GINTMSK_MASK                          0xF7FCFCFEUL                                 /**< Mask for USB_GINTMSK */
+#define USB_GINTMSK_MODEMISMSK                     (0x1UL << 1)                                 /**< Mode Mismatch Interrupt Mask host and device */
 #define _USB_GINTMSK_MODEMISMSK_SHIFT              1                                            /**< Shift value for USB_MODEMISMSK */
 #define _USB_GINTMSK_MODEMISMSK_MASK               0x2UL                                        /**< Bit mask for USB_MODEMISMSK */
 #define _USB_GINTMSK_MODEMISMSK_DEFAULT            0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
 #define USB_GINTMSK_MODEMISMSK_DEFAULT             (_USB_GINTMSK_MODEMISMSK_DEFAULT << 1)       /**< Shifted mode DEFAULT for USB_GINTMSK */
-#define USB_GINTMSK_OTGINTMSK                      (0x1UL << 2)                                 /**< OTG Interrupt Mask (host and device) */
+#define USB_GINTMSK_OTGINTMSK                      (0x1UL << 2)                                 /**< OTG Interrupt Mask host and device */
 #define _USB_GINTMSK_OTGINTMSK_SHIFT               2                                            /**< Shift value for USB_OTGINTMSK */
 #define _USB_GINTMSK_OTGINTMSK_MASK                0x4UL                                        /**< Bit mask for USB_OTGINTMSK */
 #define _USB_GINTMSK_OTGINTMSK_DEFAULT             0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
 #define USB_GINTMSK_OTGINTMSK_DEFAULT              (_USB_GINTMSK_OTGINTMSK_DEFAULT << 2)        /**< Shifted mode DEFAULT for USB_GINTMSK */
-#define USB_GINTMSK_SOFMSK                         (0x1UL << 3)                                 /**< Start of Frame Mask (host and device) */
+#define USB_GINTMSK_SOFMSK                         (0x1UL << 3)                                 /**< Start of Frame Mask host and device */
 #define _USB_GINTMSK_SOFMSK_SHIFT                  3                                            /**< Shift value for USB_SOFMSK */
 #define _USB_GINTMSK_SOFMSK_MASK                   0x8UL                                        /**< Bit mask for USB_SOFMSK */
 #define _USB_GINTMSK_SOFMSK_DEFAULT                0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
 #define USB_GINTMSK_SOFMSK_DEFAULT                 (_USB_GINTMSK_SOFMSK_DEFAULT << 3)           /**< Shifted mode DEFAULT for USB_GINTMSK */
-#define USB_GINTMSK_RXFLVLMSK                      (0x1UL << 4)                                 /**< Receive FIFO Non-Empty Mask (host and device) */
+#define USB_GINTMSK_RXFLVLMSK                      (0x1UL << 4)                                 /**< Receive FIFO Non-Empty Mask host and device */
 #define _USB_GINTMSK_RXFLVLMSK_SHIFT               4                                            /**< Shift value for USB_RXFLVLMSK */
 #define _USB_GINTMSK_RXFLVLMSK_MASK                0x10UL                                       /**< Bit mask for USB_RXFLVLMSK */
 #define _USB_GINTMSK_RXFLVLMSK_DEFAULT             0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
 #define USB_GINTMSK_RXFLVLMSK_DEFAULT              (_USB_GINTMSK_RXFLVLMSK_DEFAULT << 4)        /**< Shifted mode DEFAULT for USB_GINTMSK */
-#define USB_GINTMSK_NPTXFEMPMSK                    (0x1UL << 5)                                 /**< Non-Periodic TxFIFO Empty Mask (host only) */
+#define USB_GINTMSK_NPTXFEMPMSK                    (0x1UL << 5)                                 /**< Non-Periodic TxFIFO Empty Mask host only */
 #define _USB_GINTMSK_NPTXFEMPMSK_SHIFT             5                                            /**< Shift value for USB_NPTXFEMPMSK */
 #define _USB_GINTMSK_NPTXFEMPMSK_MASK              0x20UL                                       /**< Bit mask for USB_NPTXFEMPMSK */
 #define _USB_GINTMSK_NPTXFEMPMSK_DEFAULT           0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
 #define USB_GINTMSK_NPTXFEMPMSK_DEFAULT            (_USB_GINTMSK_NPTXFEMPMSK_DEFAULT << 5)      /**< Shifted mode DEFAULT for USB_GINTMSK */
-#define USB_GINTMSK_GINNAKEFFMSK                   (0x1UL << 6)                                 /**< Global Non-periodic IN NAK Effective Mask (device only) */
+#define USB_GINTMSK_GINNAKEFFMSK                   (0x1UL << 6)                                 /**< Global Non-periodic IN NAK Effective Mask device only */
 #define _USB_GINTMSK_GINNAKEFFMSK_SHIFT            6                                            /**< Shift value for USB_GINNAKEFFMSK */
 #define _USB_GINTMSK_GINNAKEFFMSK_MASK             0x40UL                                       /**< Bit mask for USB_GINNAKEFFMSK */
 #define _USB_GINTMSK_GINNAKEFFMSK_DEFAULT          0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
 #define USB_GINTMSK_GINNAKEFFMSK_DEFAULT           (_USB_GINTMSK_GINNAKEFFMSK_DEFAULT << 6)     /**< Shifted mode DEFAULT for USB_GINTMSK */
-#define USB_GINTMSK_GOUTNAKEFFMSK                  (0x1UL << 7)                                 /**< Global OUT NAK Effective Mask (device only) */
+#define USB_GINTMSK_GOUTNAKEFFMSK                  (0x1UL << 7)                                 /**< Global OUT NAK Effective Mask device only */
 #define _USB_GINTMSK_GOUTNAKEFFMSK_SHIFT           7                                            /**< Shift value for USB_GOUTNAKEFFMSK */
 #define _USB_GINTMSK_GOUTNAKEFFMSK_MASK            0x80UL                                       /**< Bit mask for USB_GOUTNAKEFFMSK */
 #define _USB_GINTMSK_GOUTNAKEFFMSK_DEFAULT         0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
 #define USB_GINTMSK_GOUTNAKEFFMSK_DEFAULT          (_USB_GINTMSK_GOUTNAKEFFMSK_DEFAULT << 7)    /**< Shifted mode DEFAULT for USB_GINTMSK */
-#define USB_GINTMSK_ERLYSUSPMSK                    (0x1UL << 10)                                /**< Early Suspend Mask (device only) */
+#define USB_GINTMSK_ERLYSUSPMSK                    (0x1UL << 10)                                /**< Early Suspend Mask device only */
 #define _USB_GINTMSK_ERLYSUSPMSK_SHIFT             10                                           /**< Shift value for USB_ERLYSUSPMSK */
 #define _USB_GINTMSK_ERLYSUSPMSK_MASK              0x400UL                                      /**< Bit mask for USB_ERLYSUSPMSK */
 #define _USB_GINTMSK_ERLYSUSPMSK_DEFAULT           0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
 #define USB_GINTMSK_ERLYSUSPMSK_DEFAULT            (_USB_GINTMSK_ERLYSUSPMSK_DEFAULT << 10)     /**< Shifted mode DEFAULT for USB_GINTMSK */
-#define USB_GINTMSK_USBSUSPMSK                     (0x1UL << 11)                                /**< USB Suspend Mask (device only) */
+#define USB_GINTMSK_USBSUSPMSK                     (0x1UL << 11)                                /**< USB Suspend Mask device only */
 #define _USB_GINTMSK_USBSUSPMSK_SHIFT              11                                           /**< Shift value for USB_USBSUSPMSK */
 #define _USB_GINTMSK_USBSUSPMSK_MASK               0x800UL                                      /**< Bit mask for USB_USBSUSPMSK */
 #define _USB_GINTMSK_USBSUSPMSK_DEFAULT            0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
 #define USB_GINTMSK_USBSUSPMSK_DEFAULT             (_USB_GINTMSK_USBSUSPMSK_DEFAULT << 11)      /**< Shifted mode DEFAULT for USB_GINTMSK */
-#define USB_GINTMSK_USBRSTMSK                      (0x1UL << 12)                                /**< USB Reset Mask (device only) */
+#define USB_GINTMSK_USBRSTMSK                      (0x1UL << 12)                                /**< USB Reset Mask device only */
 #define _USB_GINTMSK_USBRSTMSK_SHIFT               12                                           /**< Shift value for USB_USBRSTMSK */
 #define _USB_GINTMSK_USBRSTMSK_MASK                0x1000UL                                     /**< Bit mask for USB_USBRSTMSK */
 #define _USB_GINTMSK_USBRSTMSK_DEFAULT             0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
 #define USB_GINTMSK_USBRSTMSK_DEFAULT              (_USB_GINTMSK_USBRSTMSK_DEFAULT << 12)       /**< Shifted mode DEFAULT for USB_GINTMSK */
-#define USB_GINTMSK_ENUMDONEMSK                    (0x1UL << 13)                                /**< Enumeration Done Mask (device only) */
+#define USB_GINTMSK_ENUMDONEMSK                    (0x1UL << 13)                                /**< Enumeration Done Mask device only */
 #define _USB_GINTMSK_ENUMDONEMSK_SHIFT             13                                           /**< Shift value for USB_ENUMDONEMSK */
 #define _USB_GINTMSK_ENUMDONEMSK_MASK              0x2000UL                                     /**< Bit mask for USB_ENUMDONEMSK */
 #define _USB_GINTMSK_ENUMDONEMSK_DEFAULT           0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
 #define USB_GINTMSK_ENUMDONEMSK_DEFAULT            (_USB_GINTMSK_ENUMDONEMSK_DEFAULT << 13)     /**< Shifted mode DEFAULT for USB_GINTMSK */
-#define USB_GINTMSK_ISOOUTDROPMSK                  (0x1UL << 14)                                /**< Isochronous OUT Packet Dropped Interrupt Mask (device only) */
+#define USB_GINTMSK_ISOOUTDROPMSK                  (0x1UL << 14)                                /**< Isochronous OUT Packet Dropped Interrupt Mask device only */
 #define _USB_GINTMSK_ISOOUTDROPMSK_SHIFT           14                                           /**< Shift value for USB_ISOOUTDROPMSK */
 #define _USB_GINTMSK_ISOOUTDROPMSK_MASK            0x4000UL                                     /**< Bit mask for USB_ISOOUTDROPMSK */
 #define _USB_GINTMSK_ISOOUTDROPMSK_DEFAULT         0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
 #define USB_GINTMSK_ISOOUTDROPMSK_DEFAULT          (_USB_GINTMSK_ISOOUTDROPMSK_DEFAULT << 14)   /**< Shifted mode DEFAULT for USB_GINTMSK */
-#define USB_GINTMSK_IEPINTMSK                      (0x1UL << 18)                                /**< IN Endpoints Interrupt Mask (device only) */
+#define USB_GINTMSK_EOPFMSK                        (0x1UL << 15)                                /**< End of Periodic Frame Interrupt Mask device only */
+#define _USB_GINTMSK_EOPFMSK_SHIFT                 15                                           /**< Shift value for USB_EOPFMSK */
+#define _USB_GINTMSK_EOPFMSK_MASK                  0x8000UL                                     /**< Bit mask for USB_EOPFMSK */
+#define _USB_GINTMSK_EOPFMSK_DEFAULT               0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
+#define USB_GINTMSK_EOPFMSK_DEFAULT                (_USB_GINTMSK_EOPFMSK_DEFAULT << 15)         /**< Shifted mode DEFAULT for USB_GINTMSK */
+#define USB_GINTMSK_IEPINTMSK                      (0x1UL << 18)                                /**< IN Endpoints Interrupt Mask device only */
 #define _USB_GINTMSK_IEPINTMSK_SHIFT               18                                           /**< Shift value for USB_IEPINTMSK */
 #define _USB_GINTMSK_IEPINTMSK_MASK                0x40000UL                                    /**< Bit mask for USB_IEPINTMSK */
 #define _USB_GINTMSK_IEPINTMSK_DEFAULT             0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
 #define USB_GINTMSK_IEPINTMSK_DEFAULT              (_USB_GINTMSK_IEPINTMSK_DEFAULT << 18)       /**< Shifted mode DEFAULT for USB_GINTMSK */
-#define USB_GINTMSK_OEPINTMSK                      (0x1UL << 19)                                /**< OUT Endpoints Interrupt Mask (device only) */
+#define USB_GINTMSK_OEPINTMSK                      (0x1UL << 19)                                /**< OUT Endpoints Interrupt Mask device only */
 #define _USB_GINTMSK_OEPINTMSK_SHIFT               19                                           /**< Shift value for USB_OEPINTMSK */
 #define _USB_GINTMSK_OEPINTMSK_MASK                0x80000UL                                    /**< Bit mask for USB_OEPINTMSK */
 #define _USB_GINTMSK_OEPINTMSK_DEFAULT             0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
 #define USB_GINTMSK_OEPINTMSK_DEFAULT              (_USB_GINTMSK_OEPINTMSK_DEFAULT << 19)       /**< Shifted mode DEFAULT for USB_GINTMSK */
-#define USB_GINTMSK_INCOMPISOINMSK                 (0x1UL << 20)                                /**< Incomplete Isochronous IN Transfer Mask (device only) */
+#define USB_GINTMSK_INCOMPISOINMSK                 (0x1UL << 20)                                /**< Incomplete Isochronous IN Transfer Mask device only */
 #define _USB_GINTMSK_INCOMPISOINMSK_SHIFT          20                                           /**< Shift value for USB_INCOMPISOINMSK */
 #define _USB_GINTMSK_INCOMPISOINMSK_MASK           0x100000UL                                   /**< Bit mask for USB_INCOMPISOINMSK */
 #define _USB_GINTMSK_INCOMPISOINMSK_DEFAULT        0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
 #define USB_GINTMSK_INCOMPISOINMSK_DEFAULT         (_USB_GINTMSK_INCOMPISOINMSK_DEFAULT << 20)  /**< Shifted mode DEFAULT for USB_GINTMSK */
-#define USB_GINTMSK_INCOMPLPMSK                    (0x1UL << 21)                                /**< Incomplete Periodic Transfer Mask (host only) */
+#define USB_GINTMSK_INCOMPLPMSK                    (0x1UL << 21)                                /**< Incomplete Periodic Transfer Mask host and device */
 #define _USB_GINTMSK_INCOMPLPMSK_SHIFT             21                                           /**< Shift value for USB_INCOMPLPMSK */
 #define _USB_GINTMSK_INCOMPLPMSK_MASK              0x200000UL                                   /**< Bit mask for USB_INCOMPLPMSK */
 #define _USB_GINTMSK_INCOMPLPMSK_DEFAULT           0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
 #define USB_GINTMSK_INCOMPLPMSK_DEFAULT            (_USB_GINTMSK_INCOMPLPMSK_DEFAULT << 21)     /**< Shifted mode DEFAULT for USB_GINTMSK */
-#define USB_GINTMSK_FETSUSPMSK                     (0x1UL << 22)                                /**< Data Fetch Suspended Mask (device only) */
+#define USB_GINTMSK_FETSUSPMSK                     (0x1UL << 22)                                /**< Data Fetch Suspended Mask device only */
 #define _USB_GINTMSK_FETSUSPMSK_SHIFT              22                                           /**< Shift value for USB_FETSUSPMSK */
 #define _USB_GINTMSK_FETSUSPMSK_MASK               0x400000UL                                   /**< Bit mask for USB_FETSUSPMSK */
 #define _USB_GINTMSK_FETSUSPMSK_DEFAULT            0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
 #define USB_GINTMSK_FETSUSPMSK_DEFAULT             (_USB_GINTMSK_FETSUSPMSK_DEFAULT << 22)      /**< Shifted mode DEFAULT for USB_GINTMSK */
-#define USB_GINTMSK_RESETDETMSK                    (0x1UL << 23)                                /**< Reset detected Interrupt Mask (device only) */
+#define USB_GINTMSK_RESETDETMSK                    (0x1UL << 23)                                /**< Reset detected Interrupt Mask device only */
 #define _USB_GINTMSK_RESETDETMSK_SHIFT             23                                           /**< Shift value for USB_RESETDETMSK */
 #define _USB_GINTMSK_RESETDETMSK_MASK              0x800000UL                                   /**< Bit mask for USB_RESETDETMSK */
 #define _USB_GINTMSK_RESETDETMSK_DEFAULT           0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
 #define USB_GINTMSK_RESETDETMSK_DEFAULT            (_USB_GINTMSK_RESETDETMSK_DEFAULT << 23)     /**< Shifted mode DEFAULT for USB_GINTMSK */
-#define USB_GINTMSK_PRTINTMSK                      (0x1UL << 24)                                /**< Host Port Interrupt Mask (host only) */
+#define USB_GINTMSK_PRTINTMSK                      (0x1UL << 24)                                /**< Host Port Interrupt Mask host only */
 #define _USB_GINTMSK_PRTINTMSK_SHIFT               24                                           /**< Shift value for USB_PRTINTMSK */
 #define _USB_GINTMSK_PRTINTMSK_MASK                0x1000000UL                                  /**< Bit mask for USB_PRTINTMSK */
 #define _USB_GINTMSK_PRTINTMSK_DEFAULT             0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
 #define USB_GINTMSK_PRTINTMSK_DEFAULT              (_USB_GINTMSK_PRTINTMSK_DEFAULT << 24)       /**< Shifted mode DEFAULT for USB_GINTMSK */
-#define USB_GINTMSK_HCHINTMSK                      (0x1UL << 25)                                /**< Host Channels Interrupt Mask (host only) */
+#define USB_GINTMSK_HCHINTMSK                      (0x1UL << 25)                                /**< Host Channels Interrupt Mask host only */
 #define _USB_GINTMSK_HCHINTMSK_SHIFT               25                                           /**< Shift value for USB_HCHINTMSK */
 #define _USB_GINTMSK_HCHINTMSK_MASK                0x2000000UL                                  /**< Bit mask for USB_HCHINTMSK */
 #define _USB_GINTMSK_HCHINTMSK_DEFAULT             0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
 #define USB_GINTMSK_HCHINTMSK_DEFAULT              (_USB_GINTMSK_HCHINTMSK_DEFAULT << 25)       /**< Shifted mode DEFAULT for USB_GINTMSK */
-#define USB_GINTMSK_PTXFEMPMSK                     (0x1UL << 26)                                /**< Periodic TxFIFO Empty Mask (host only) */
+#define USB_GINTMSK_PTXFEMPMSK                     (0x1UL << 26)                                /**< Periodic TxFIFO Empty Mask host only */
 #define _USB_GINTMSK_PTXFEMPMSK_SHIFT              26                                           /**< Shift value for USB_PTXFEMPMSK */
 #define _USB_GINTMSK_PTXFEMPMSK_MASK               0x4000000UL                                  /**< Bit mask for USB_PTXFEMPMSK */
 #define _USB_GINTMSK_PTXFEMPMSK_DEFAULT            0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
 #define USB_GINTMSK_PTXFEMPMSK_DEFAULT             (_USB_GINTMSK_PTXFEMPMSK_DEFAULT << 26)      /**< Shifted mode DEFAULT for USB_GINTMSK */
-#define USB_GINTMSK_CONIDSTSCHNGMSK                (0x1UL << 28)                                /**< Connector ID Status Change Mask (host and device) */
+#define USB_GINTMSK_CONIDSTSCHNGMSK                (0x1UL << 28)                                /**< Connector ID Status Change Mask host and device */
 #define _USB_GINTMSK_CONIDSTSCHNGMSK_SHIFT         28                                           /**< Shift value for USB_CONIDSTSCHNGMSK */
 #define _USB_GINTMSK_CONIDSTSCHNGMSK_MASK          0x10000000UL                                 /**< Bit mask for USB_CONIDSTSCHNGMSK */
 #define _USB_GINTMSK_CONIDSTSCHNGMSK_DEFAULT       0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
 #define USB_GINTMSK_CONIDSTSCHNGMSK_DEFAULT        (_USB_GINTMSK_CONIDSTSCHNGMSK_DEFAULT << 28) /**< Shifted mode DEFAULT for USB_GINTMSK */
-#define USB_GINTMSK_DISCONNINTMSK                  (0x1UL << 29)                                /**< Disconnect Detected Interrupt Mask (host and device) */
+#define USB_GINTMSK_DISCONNINTMSK                  (0x1UL << 29)                                /**< Disconnect Detected Interrupt Mask host and device */
 #define _USB_GINTMSK_DISCONNINTMSK_SHIFT           29                                           /**< Shift value for USB_DISCONNINTMSK */
 #define _USB_GINTMSK_DISCONNINTMSK_MASK            0x20000000UL                                 /**< Bit mask for USB_DISCONNINTMSK */
 #define _USB_GINTMSK_DISCONNINTMSK_DEFAULT         0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
 #define USB_GINTMSK_DISCONNINTMSK_DEFAULT          (_USB_GINTMSK_DISCONNINTMSK_DEFAULT << 29)   /**< Shifted mode DEFAULT for USB_GINTMSK */
-#define USB_GINTMSK_SESSREQINTMSK                  (0x1UL << 30)                                /**< Session Request/New Session Detected Interrupt Mask (host and device) */
+#define USB_GINTMSK_SESSREQINTMSK                  (0x1UL << 30)                                /**< Session Request/New Session Detected Interrupt Mask host and device */
 #define _USB_GINTMSK_SESSREQINTMSK_SHIFT           30                                           /**< Shift value for USB_SESSREQINTMSK */
 #define _USB_GINTMSK_SESSREQINTMSK_MASK            0x40000000UL                                 /**< Bit mask for USB_SESSREQINTMSK */
 #define _USB_GINTMSK_SESSREQINTMSK_DEFAULT         0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
 #define USB_GINTMSK_SESSREQINTMSK_DEFAULT          (_USB_GINTMSK_SESSREQINTMSK_DEFAULT << 30)   /**< Shifted mode DEFAULT for USB_GINTMSK */
-#define USB_GINTMSK_WKUPINTMSK                     (0x1UL << 31)                                /**< Resume/Remote Wakeup Detected Interrupt Mask (host and device) */
+#define USB_GINTMSK_WKUPINTMSK                     (0x1UL << 31)                                /**< Resume/Remote Wakeup Detected Interrupt Mask host and device */
 #define _USB_GINTMSK_WKUPINTMSK_SHIFT              31                                           /**< Shift value for USB_WKUPINTMSK */
 #define _USB_GINTMSK_WKUPINTMSK_MASK               0x80000000UL                                 /**< Bit mask for USB_WKUPINTMSK */
 #define _USB_GINTMSK_WKUPINTMSK_DEFAULT            0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
@@ -2657,5 +2653,5 @@
 #define USB_FIFORAM_FIFORAM_DEFAULT                (_USB_FIFORAM_FIFORAM_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_FIFORAM */
 
 /** @} End of group EFM32LG_USB */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_usb_diep.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_usb_diep.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32lg_usb_diep.h
  * @brief EFM32LG_USB_DIEP register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @brief USB_DIEP EFM32LG USB DIEP
  *****************************************************************************/
 typedef struct
@@ -41,7 +45,9 @@
   __IO uint32_t TSIZ;         /**< Device IN Endpoint x+1 Transfer Size Register  */
   __IO uint32_t DMAADDR;      /**< Device IN Endpoint x+1 DMA Address Register  */
   __I uint32_t  TXFSTS;       /**< Device IN Endpoint x+1 Transmit FIFO Status Register  */
-
   uint32_t      RESERVED2[1]; /**< Reserved future */
 } USB_DIEP_TypeDef;
 
+/** @} End of group Parts */
+
+

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_usb_doep.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_usb_doep.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32lg_usb_doep.h
  * @brief EFM32LG_USB_DOEP register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @brief USB_DOEP EFM32LG USB DOEP
  *****************************************************************************/
 typedef struct
@@ -40,7 +44,9 @@
   uint32_t      RESERVED1[1]; /**< Reserved for future use **/
   __IO uint32_t TSIZ;         /**< Device OUT Endpoint x+1 Transfer Size Register  */
   __IO uint32_t DMAADDR;      /**< Device OUT Endpoint x+1 DMA Address Register  */
-
   uint32_t      RESERVED2[2]; /**< Reserved future */
 } USB_DOEP_TypeDef;
 
+/** @} End of group Parts */
+
+

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_usb_hc.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_usb_hc.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32lg_usb_hc.h
  * @brief EFM32LG_USB_HC register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @brief USB_HC EFM32LG USB HC
  *****************************************************************************/
 typedef struct
@@ -40,7 +44,9 @@
   __IO uint32_t INTMSK;       /**< Host Channel x Interrupt Mask Register  */
   __IO uint32_t TSIZ;         /**< Host Channel x Transfer Size Register  */
   __IO uint32_t DMAADDR;      /**< Host Channel x DMA Address Register  */
-
   uint32_t      RESERVED1[2]; /**< Reserved future */
 } USB_HC_TypeDef;
 
+/** @} End of group Parts */
+
+

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_vcmp.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_vcmp.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32lg_vcmp.h
  * @brief EFM32LG_VCMP register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32LG_VCMP
  * @{
  * @brief EFM32LG_VCMP Register Declaration
@@ -192,5 +196,5 @@
 #define VCMP_IFC_WARMUP_DEFAULT             (_VCMP_IFC_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for VCMP_IFC */
 
 /** @} End of group EFM32LG_VCMP */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_wdog.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_wdog.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32lg_wdog.h
  * @brief EFM32LG_WDOG register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32LG_WDOG
  * @{
  * @brief EFM32LG_WDOG Register Declaration
@@ -128,5 +132,5 @@
 #define WDOG_SYNCBUSY_CMD_DEFAULT        (_WDOG_SYNCBUSY_CMD_DEFAULT << 1)  /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */
 
 /** @} End of group EFM32LG_WDOG */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/em_device.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/em_device.h	Fri Jan 15 07:45:16 2016 +0000
@@ -9,11 +9,13 @@
  * @verbatim
  * Example: Add "-DEFM32G890F128" to your build options, to define part
  *          Add "#include "em_device.h" to your source files
+ *
+ *
  * @endverbatim
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -29,19 +31,18 @@
  * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
  * has no obligation to support this Software. Silicon Laboratories, Inc. is
  * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of 
+ * kind, including, but not limited to, any implied warranties of
  * merchantability or fitness for any particular purpose or warranties against
  * infringement of any proprietary rights of a third party.
  *
- * Silicon Laboratories, Inc. will not be liable for any consequential, 
- * incidental, or special damages, or any other relief, or for any claim by 
+ * Silicon Laboratories, Inc. will not be liable for any consequential,
+ * incidental, or special damages, or any other relief, or for any claim by
  * any third party, arising from your use of this Software.
  *
  *****************************************************************************/
 
-#ifndef __EM_DEVICE_H
-#define __EM_DEVICE_H
-
+#ifndef EM_DEVICE_H
+#define EM_DEVICE_H
 
 #if defined(EFM32LG230F128)
 #include "efm32lg230f128.h"
@@ -106,6 +107,15 @@
 #elif defined(EFM32LG332F64)
 #include "efm32lg332f64.h"
 
+#elif defined(EFM32LG360F128)
+#include "efm32lg360f128.h"
+
+#elif defined(EFM32LG360F256)
+#include "efm32lg360f256.h"
+
+#elif defined(EFM32LG360F64)
+#include "efm32lg360f64.h"
+
 #elif defined(EFM32LG380F128)
 #include "efm32lg380f128.h"
 
@@ -178,6 +188,9 @@
 #elif defined(EFM32LG895F64)
 #include "efm32lg895f64.h"
 
+#elif defined(EFM32LG900F256)
+#include "efm32lg900f256.h"
+
 #elif defined(EFM32LG940F128)
 #include "efm32lg940f128.h"
 
@@ -223,9 +236,7 @@
 #elif defined(EFM32LG995F64)
 #include "efm32lg995f64.h"
 
-
 #else
 #error "em_device.h: PART NUMBER undefined"
 #endif
-
-#endif
+#endif /* EM_DEVICE_H */

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/system_efm32lg.c	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/system_efm32lg.c	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /***************************************************************************//**
  * @file system_efm32lg.c
  * @brief CMSIS Cortex-M3 System Layer for EFM32LG devices.
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -20,12 +20,12 @@
  * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
  * has no obligation to support this Software. Silicon Laboratories, Inc. is
  * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of 
+ * kind, including, but not limited to, any implied warranties of
  * merchantability or fitness for any particular purpose or warranties against
  * infringement of any proprietary rights of a third party.
  *
- * Silicon Laboratories, Inc. will not be liable for any consequential, 
- * incidental, or special damages, or any other relief, or for any claim by 
+ * Silicon Laboratories, Inc. will not be liable for any consequential,
+ * incidental, or special damages, or any other relief, or for any claim by
  * any third party, arising from your use of this Software.
  *
  *****************************************************************************/
@@ -54,27 +54,27 @@
 /* SW footprint. */
 
 #ifndef EFM32_HFXO_FREQ
-#ifdef _EFM32_GIANT_FAMILY
 #define EFM32_HFXO_FREQ (48000000UL)
-#else
-#define EFM32_HFXO_FREQ (32000000UL)
 #endif
-#endif
+
+#define EFM32_HFRCO_MAX_FREQ (28000000UL)
+
 /* Do not define variable if HF crystal oscillator not present */
 #if (EFM32_HFXO_FREQ > 0)
 /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
-/** System HFXO clock. */ 
+/** System HFXO clock. */
 static uint32_t SystemHFXOClock = EFM32_HFXO_FREQ;
 /** @endcond (DO_NOT_INCLUDE_WITH_DOXYGEN) */
 #endif
 
-#ifndef EFM32_LFXO_FREQ 
+#ifndef EFM32_LFXO_FREQ
 #define EFM32_LFXO_FREQ (EFM32_LFRCO_FREQ)
 #endif
+
 /* Do not define variable if LF crystal oscillator not present */
 #if (EFM32_LFXO_FREQ > 0)
 /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
-/** System LFXO clock. */ 
+/** System LFXO clock. */
 static uint32_t SystemLFXOClock = EFM32_LFXO_FREQ;
 /** @endcond (DO_NOT_INCLUDE_WITH_DOXYGEN) */
 #endif
@@ -123,13 +123,11 @@
 uint32_t SystemCoreClockGet(void)
 {
   uint32_t ret;
-  
+
   ret = SystemHFClockGet();
-#if defined (_EFM32_GIANT_FAMILY)
   /* Leopard/Giant Gecko has an additional divider */
   ret =  ret / (1 + ((CMU->CTRL & _CMU_CTRL_HFCLKDIV_MASK)>>_CMU_CTRL_HFCLKDIV_SHIFT));
-#endif
-  ret >>= (CMU->HFCORECLKDIV & _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK) >> 
+  ret >>= (CMU->HFCORECLKDIV & _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK) >>
           _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT;
 
   /* Keep CMSIS variable up-to-date just in case */
@@ -141,6 +139,23 @@
 
 /***************************************************************************//**
  * @brief
+ *   Get the maximum core clock frequency.
+ *
+ * @note
+ *   This is an EFR32 proprietary function, not part of the CMSIS definition.
+ *
+ * @return
+ *   The maximum core clock frequency in Hz.
+ ******************************************************************************/
+uint32_t SystemMaxCoreClockGet(void)
+{
+  return (EFM32_HFRCO_MAX_FREQ > EFM32_HFXO_FREQ ? \
+          EFM32_HFRCO_MAX_FREQ : EFM32_HFXO_FREQ);
+}
+
+
+/***************************************************************************//**
+ * @brief
  *   Get the current HFCLK frequency.
  *
  * @note
@@ -152,7 +167,7 @@
 uint32_t SystemHFClockGet(void)
 {
   uint32_t ret;
-  
+
   switch (CMU->STATUS & (CMU_STATUS_HFRCOSEL | CMU_STATUS_HFXOSEL |
                          CMU_STATUS_LFRCOSEL | CMU_STATUS_LFXOSEL))
   {
@@ -165,11 +180,11 @@
       ret = 0;
 #endif
       break;
-      
+
     case CMU_STATUS_LFRCOSEL:
       ret = EFM32_LFRCO_FREQ;
       break;
-      
+
     case CMU_STATUS_HFXOSEL:
 #if (EFM32_HFXO_FREQ > 0)
       ret = SystemHFXOClock;
@@ -179,7 +194,7 @@
       ret = 0;
 #endif
       break;
-      
+
     default: /* CMU_STATUS_HFRCOSEL */
       switch (CMU->HFRCOCTRL & _CMU_HFRCOCTRL_BAND_MASK)
       {

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/system_efm32lg.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/system_efm32lg.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /***************************************************************************//**
  * @file system_efm32lg.h
  * @brief CMSIS Cortex-M3 System Layer for EFM32LG devices.
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,8 +30,8 @@
  *
  *****************************************************************************/
 
-#ifndef __SYSTEM_EFM32LG_H
-#define __SYSTEM_EFM32LG_H
+#ifndef SYSTEM_EFM32LG_H
+#define SYSTEM_EFM32LG_H
 
 #ifdef __cplusplus
 extern "C" {
@@ -50,7 +50,6 @@
  ******************************************************************************/
 
 /* Interrupt routines - prototypes */
-#if defined(_EFM32_GIANT_FAMILY)
 void Reset_Handler(void);
 void NMI_Handler(void);
 void HardFault_Handler(void);
@@ -61,6 +60,7 @@
 void DebugMon_Handler(void);
 void PendSV_Handler(void);
 void SysTick_Handler(void);
+
 void DMA_IRQHandler(void);
 void GPIO_EVEN_IRQHandler(void);
 void TIMER0_IRQHandler(void);
@@ -100,9 +100,9 @@
 void AES_IRQHandler(void);
 void EBI_IRQHandler(void);
 void EMU_IRQHandler(void);
-#endif
 
 uint32_t SystemCoreClockGet(void);
+uint32_t SystemMaxCoreClockGet(void);
 
 /**************************************************************************//**
  * @brief
@@ -135,4 +135,4 @@
 #ifdef __cplusplus
 }
 #endif
-#endif /* __SYSTEM_EFM32LG_H */
+#endif /* SYSTEM_EFM32LG_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG_STK3401/TOOLCHAIN_ARM_MICRO/efm32pg1b.sct	Fri Jan 15 07:45:16 2016 +0000
@@ -0,0 +1,15 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x00000000 0x00040000  {    ; load region size_region
+  ER_IROM1 0x00000000 0x00040000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1 0x200000C8 0x00007F38  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG_STK3401/TOOLCHAIN_ARM_MICRO/startup_efm32pg1b.S	Fri Jan 15 07:45:16 2016 +0000
@@ -0,0 +1,242 @@
+;/**************************************************************************//**
+; * @file startup_efm32pg1b.s
+; * @brief    CMSIS Core Device Startup File for
+; *           Silicon Labs EFM32PG1B Device Series
+; * @version 4.2.1
+; * @date     03. February 2012
+; *
+; * @note
+; * Copyright (C) 2012 ARM Limited. All rights reserved.
+; *
+; * @par
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M
+; * processor based microcontrollers.  This file can be freely distributed
+; * within development tools that are supporting such ARM based processors.
+; *
+; * @par
+; * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; ******************************************************************************/
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp    EQU     0x20008000
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000C00
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY, ALIGN=8
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+
+                DCD     EMU_IRQHandler        ; 0: EMU Interrupt
+                DCD     0                         ; 1: Reserved
+                DCD     WDOG0_IRQHandler        ; 2: WDOG0 Interrupt
+                DCD     0                         ; 3: Reserved
+                DCD     0                         ; 4: Reserved
+                DCD     0                         ; 5: Reserved
+                DCD     0                         ; 6: Reserved
+                DCD     0                         ; 7: Reserved
+                DCD     LDMA_IRQHandler        ; 8: LDMA Interrupt
+                DCD     GPIO_EVEN_IRQHandler        ; 9: GPIO_EVEN Interrupt
+                DCD     TIMER0_IRQHandler        ; 10: TIMER0 Interrupt
+                DCD     USART0_RX_IRQHandler        ; 11: USART0_RX Interrupt
+                DCD     USART0_TX_IRQHandler        ; 12: USART0_TX Interrupt
+                DCD     ACMP0_IRQHandler        ; 13: ACMP0 Interrupt
+                DCD     ADC0_IRQHandler        ; 14: ADC0 Interrupt
+                DCD     IDAC0_IRQHandler        ; 15: IDAC0 Interrupt
+                DCD     I2C0_IRQHandler        ; 16: I2C0 Interrupt
+                DCD     GPIO_ODD_IRQHandler        ; 17: GPIO_ODD Interrupt
+                DCD     TIMER1_IRQHandler        ; 18: TIMER1 Interrupt
+                DCD     USART1_RX_IRQHandler        ; 19: USART1_RX Interrupt
+                DCD     USART1_TX_IRQHandler        ; 20: USART1_TX Interrupt
+                DCD     LEUART0_IRQHandler        ; 21: LEUART0 Interrupt
+                DCD     PCNT0_IRQHandler        ; 22: PCNT0 Interrupt
+                DCD     CMU_IRQHandler        ; 23: CMU Interrupt
+                DCD     MSC_IRQHandler        ; 24: MSC Interrupt
+                DCD     CRYPTO_IRQHandler        ; 25: CRYPTO Interrupt
+                DCD     LETIMER0_IRQHandler        ; 26: LETIMER0 Interrupt
+                DCD     0                         ; 27: Reserved
+                DCD     0                         ; 28: Reserved
+                DCD     RTCC_IRQHandler        ; 29: RTCC Interrupt
+                DCD     0                         ; 30: Reserved
+                DCD     CRYOTIMER_IRQHandler        ; 31: CRYOTIMER Interrupt
+                DCD     0                         ; 32: Reserved
+                DCD     FPUEH_IRQHandler        ; 33: FPUEH Interrupt
+
+__Vectors_End
+__Vectors_Size  EQU     __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  EMU_IRQHandler        [WEAK]
+                EXPORT  WDOG0_IRQHandler        [WEAK]
+                EXPORT  LDMA_IRQHandler        [WEAK]
+                EXPORT  GPIO_EVEN_IRQHandler        [WEAK]
+                EXPORT  TIMER0_IRQHandler        [WEAK]
+                EXPORT  USART0_RX_IRQHandler        [WEAK]
+                EXPORT  USART0_TX_IRQHandler        [WEAK]
+                EXPORT  ACMP0_IRQHandler        [WEAK]
+                EXPORT  ADC0_IRQHandler        [WEAK]
+                EXPORT  IDAC0_IRQHandler        [WEAK]
+                EXPORT  I2C0_IRQHandler        [WEAK]
+                EXPORT  GPIO_ODD_IRQHandler        [WEAK]
+                EXPORT  TIMER1_IRQHandler        [WEAK]
+                EXPORT  USART1_RX_IRQHandler        [WEAK]
+                EXPORT  USART1_TX_IRQHandler        [WEAK]
+                EXPORT  LEUART0_IRQHandler        [WEAK]
+                EXPORT  PCNT0_IRQHandler        [WEAK]
+                EXPORT  CMU_IRQHandler        [WEAK]
+                EXPORT  MSC_IRQHandler        [WEAK]
+                EXPORT  CRYPTO_IRQHandler        [WEAK]
+                EXPORT  LETIMER0_IRQHandler        [WEAK]
+                EXPORT  RTCC_IRQHandler        [WEAK]
+                EXPORT  CRYOTIMER_IRQHandler        [WEAK]
+                EXPORT  FPUEH_IRQHandler        [WEAK]
+
+
+EMU_IRQHandler
+WDOG0_IRQHandler
+LDMA_IRQHandler
+GPIO_EVEN_IRQHandler
+TIMER0_IRQHandler
+USART0_RX_IRQHandler
+USART0_TX_IRQHandler
+ACMP0_IRQHandler
+ADC0_IRQHandler
+IDAC0_IRQHandler
+I2C0_IRQHandler
+GPIO_ODD_IRQHandler
+TIMER1_IRQHandler
+USART1_RX_IRQHandler
+USART1_TX_IRQHandler
+LEUART0_IRQHandler
+PCNT0_IRQHandler
+CMU_IRQHandler
+MSC_IRQHandler
+CRYPTO_IRQHandler
+LETIMER0_IRQHandler
+RTCC_IRQHandler
+CRYOTIMER_IRQHandler
+FPUEH_IRQHandler
+                B       .
+                ENDP
+
+                ALIGN
+
+; User Initial Stack & Heap
+
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+
+                END

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG_STK3401/TOOLCHAIN_ARM_STD/efm32pg1b.sct	Fri Jan 15 07:45:16 2016 +0000
@@ -0,0 +1,15 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x00000000 0x00040000  {    ; load region size_region
+  ER_IROM1 0x00000000 0x00040000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1 0x200000C8 0x00007F38  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG_STK3401/TOOLCHAIN_ARM_STD/startup_efm32pg1b.S	Fri Jan 15 07:45:16 2016 +0000
@@ -0,0 +1,251 @@
+;/**************************************************************************//**
+; * @file startup_efm32pg1b.s
+; * @brief    CMSIS Core Device Startup File for
+; *           Silicon Labs EFM32PG1B Device Series
+; * @version 4.2.1
+; * @date     03. February 2012
+; *
+; * @note
+; * Copyright (C) 2012 ARM Limited. All rights reserved.
+; *
+; * @par
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M
+; * processor based microcontrollers.  This file can be freely distributed
+; * within development tools that are supporting such ARM based processors.
+; *
+; * @par
+; * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; ******************************************************************************/
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp    EQU     0x20008000
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000C00
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY, ALIGN=8
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+
+                DCD     EMU_IRQHandler        ; 0: EMU Interrupt
+                DCD     0                         ; 1: Reserved
+                DCD     WDOG0_IRQHandler        ; 2: WDOG0 Interrupt
+                DCD     0                         ; 3: Reserved
+                DCD     0                         ; 4: Reserved
+                DCD     0                         ; 5: Reserved
+                DCD     0                         ; 6: Reserved
+                DCD     0                         ; 7: Reserved
+                DCD     LDMA_IRQHandler        ; 8: LDMA Interrupt
+                DCD     GPIO_EVEN_IRQHandler        ; 9: GPIO_EVEN Interrupt
+                DCD     TIMER0_IRQHandler        ; 10: TIMER0 Interrupt
+                DCD     USART0_RX_IRQHandler        ; 11: USART0_RX Interrupt
+                DCD     USART0_TX_IRQHandler        ; 12: USART0_TX Interrupt
+                DCD     ACMP0_IRQHandler        ; 13: ACMP0 Interrupt
+                DCD     ADC0_IRQHandler        ; 14: ADC0 Interrupt
+                DCD     IDAC0_IRQHandler        ; 15: IDAC0 Interrupt
+                DCD     I2C0_IRQHandler        ; 16: I2C0 Interrupt
+                DCD     GPIO_ODD_IRQHandler        ; 17: GPIO_ODD Interrupt
+                DCD     TIMER1_IRQHandler        ; 18: TIMER1 Interrupt
+                DCD     USART1_RX_IRQHandler        ; 19: USART1_RX Interrupt
+                DCD     USART1_TX_IRQHandler        ; 20: USART1_TX Interrupt
+                DCD     LEUART0_IRQHandler        ; 21: LEUART0 Interrupt
+                DCD     PCNT0_IRQHandler        ; 22: PCNT0 Interrupt
+                DCD     CMU_IRQHandler        ; 23: CMU Interrupt
+                DCD     MSC_IRQHandler        ; 24: MSC Interrupt
+                DCD     CRYPTO_IRQHandler        ; 25: CRYPTO Interrupt
+                DCD     LETIMER0_IRQHandler        ; 26: LETIMER0 Interrupt
+                DCD     0                         ; 27: Reserved
+                DCD     0                         ; 28: Reserved
+                DCD     RTCC_IRQHandler        ; 29: RTCC Interrupt
+                DCD     0                         ; 30: Reserved
+                DCD     CRYOTIMER_IRQHandler        ; 31: CRYOTIMER Interrupt
+                DCD     0                         ; 32: Reserved
+                DCD     FPUEH_IRQHandler        ; 33: FPUEH Interrupt
+
+__Vectors_End
+__Vectors_Size  EQU     __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  EMU_IRQHandler        [WEAK]
+                EXPORT  WDOG0_IRQHandler        [WEAK]
+                EXPORT  LDMA_IRQHandler        [WEAK]
+                EXPORT  GPIO_EVEN_IRQHandler        [WEAK]
+                EXPORT  TIMER0_IRQHandler        [WEAK]
+                EXPORT  USART0_RX_IRQHandler        [WEAK]
+                EXPORT  USART0_TX_IRQHandler        [WEAK]
+                EXPORT  ACMP0_IRQHandler        [WEAK]
+                EXPORT  ADC0_IRQHandler        [WEAK]
+                EXPORT  IDAC0_IRQHandler        [WEAK]
+                EXPORT  I2C0_IRQHandler        [WEAK]
+                EXPORT  GPIO_ODD_IRQHandler        [WEAK]
+                EXPORT  TIMER1_IRQHandler        [WEAK]
+                EXPORT  USART1_RX_IRQHandler        [WEAK]
+                EXPORT  USART1_TX_IRQHandler        [WEAK]
+                EXPORT  LEUART0_IRQHandler        [WEAK]
+                EXPORT  PCNT0_IRQHandler        [WEAK]
+                EXPORT  CMU_IRQHandler        [WEAK]
+                EXPORT  MSC_IRQHandler        [WEAK]
+                EXPORT  CRYPTO_IRQHandler        [WEAK]
+                EXPORT  LETIMER0_IRQHandler        [WEAK]
+                EXPORT  RTCC_IRQHandler        [WEAK]
+                EXPORT  CRYOTIMER_IRQHandler        [WEAK]
+                EXPORT  FPUEH_IRQHandler        [WEAK]
+
+
+EMU_IRQHandler
+WDOG0_IRQHandler
+LDMA_IRQHandler
+GPIO_EVEN_IRQHandler
+TIMER0_IRQHandler
+USART0_RX_IRQHandler
+USART0_TX_IRQHandler
+ACMP0_IRQHandler
+ADC0_IRQHandler
+IDAC0_IRQHandler
+I2C0_IRQHandler
+GPIO_ODD_IRQHandler
+TIMER1_IRQHandler
+USART1_RX_IRQHandler
+USART1_TX_IRQHandler
+LEUART0_IRQHandler
+PCNT0_IRQHandler
+CMU_IRQHandler
+MSC_IRQHandler
+CRYPTO_IRQHandler
+LETIMER0_IRQHandler
+RTCC_IRQHandler
+CRYOTIMER_IRQHandler
+FPUEH_IRQHandler
+                B       .
+                ENDP
+
+                ALIGN
+
+; User Initial Stack & Heap
+
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap PROC
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+                ENDP
+
+                ALIGN
+
+                END

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG_STK3401/TOOLCHAIN_GCC_ARM/efm32pg1b.ld	Fri Jan 15 07:45:16 2016 +0000
@@ -0,0 +1,215 @@
+/* Linker script for Silicon Labs EFM32PG1B devices */
+/*                                                                  */
+/* This file is subject to the license terms as defined in ARM's    */
+/* CMSIS END USER LICENSE AGREEMENT.pdf, governing the use of       */
+/* Example Code.                                                    */
+/*                                                                  */
+/* Silicon Laboratories, Inc. 2015                                  */
+/*                                                                  */
+/* Version 4.2.0 */
+/*                                                                  */
+
+MEMORY
+{
+  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 262144
+  RAM (rwx)  : ORIGIN = 0x20000000, LENGTH = 32768
+}
+
+/* MBED: mbed needs to be able to dynamically set the interrupt vector table.
+ * We make room for the table at the very beginning of RAM, i.e. at
+ * 0x20000000. We need (16+34) * sizeof(uint32_t) = 200 bytes for EFM32PG */
+__vector_size = 0xC8;
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ *   __Vectors_End
+ *   __Vectors_Size
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+  .text :
+  {
+    KEEP(*(.vectors))
+    __Vectors_End = .;
+    __Vectors_Size = __Vectors_End - __Vectors;
+    __end__ = .;
+
+    *(.text*)
+
+    KEEP(*(.init))
+    KEEP(*(.fini))
+
+    /* .ctors */
+    *crtbegin.o(.ctors)
+    *crtbegin?.o(.ctors)
+    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+    *(SORT(.ctors.*))
+    *(.ctors)
+
+    /* .dtors */
+    *crtbegin.o(.dtors)
+    *crtbegin?.o(.dtors)
+    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+    *(SORT(.dtors.*))
+    *(.dtors)
+
+    *(.rodata*)
+
+    KEEP(*(.eh_frame*))
+  } > FLASH
+
+  .ARM.extab :
+  {
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+  } > FLASH
+
+  __exidx_start = .;
+  .ARM.exidx :
+  {
+    *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+  } > FLASH
+  __exidx_end = .;
+
+  /* To copy multiple ROM to RAM sections,
+   * uncomment .copy.table section and,
+   * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+  /*
+  .copy.table :
+  {
+    . = ALIGN(4);
+    __copy_table_start__ = .;
+    LONG (__etext)
+    LONG (__data_start__)
+    LONG (__data_end__ - __data_start__)
+    LONG (__etext2)
+    LONG (__data2_start__)
+    LONG (__data2_end__ - __data2_start__)
+    __copy_table_end__ = .;
+  } > FLASH
+  */
+
+  /* To clear multiple BSS sections,
+   * uncomment .zero.table section and,
+   * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+  /*
+  .zero.table :
+  {
+    . = ALIGN(4);
+    __zero_table_start__ = .;
+    LONG (__bss_start__)
+    LONG (__bss_end__ - __bss_start__)
+    LONG (__bss2_start__)
+    LONG (__bss2_end__ - __bss2_start__)
+    __zero_table_end__ = .;
+  } > FLASH
+  */
+
+  __etext = .;
+
+  .data : AT (__etext)
+  {
+    __data_start__ = .;
+    PROVIDE( __start_vector_table__ = .);
+    . += __vector_size;
+    PROVIDE( __end_vector_table__ = .);
+    *(vtable)
+    *(.data*)
+    . = ALIGN (4);
+    *(.ram)
+
+    . = ALIGN(4);
+    /* preinit data */
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP(*(.preinit_array))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+
+    . = ALIGN(4);
+    /* init data */
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP(*(SORT(.init_array.*)))
+    KEEP(*(.init_array))
+    PROVIDE_HIDDEN (__init_array_end = .);
+
+    . = ALIGN(4);
+    /* finit data */
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP(*(SORT(.fini_array.*)))
+    KEEP(*(.fini_array))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+
+    KEEP(*(.jcr*))
+    . = ALIGN(4);
+    /* All data end */
+    __data_end__ = .;
+
+  } > RAM
+
+  .bss :
+  {
+    . = ALIGN(4);
+    __bss_start__ = .;
+    *(.bss*)
+    *(COMMON)
+    . = ALIGN(4);
+    __bss_end__ = .;
+  } > RAM
+
+  .heap (COPY):
+  {
+    __HeapBase = .;
+    __end__ = .;
+    end = __end__;
+    _end = __end__;
+    KEEP(*(.heap*))
+    __HeapLimit = .;
+  } > RAM
+
+  /* .stack_dummy section doesn't contains any symbols. It is only
+   * used for linker to calculate size of stack sections, and assign
+   * values to stack symbols later */
+  .stack_dummy (COPY):
+  {
+    KEEP(*(.stack*))
+  } > RAM
+
+  /* Set stack top to end of RAM, and stack limit move down by
+   * size of stack_dummy section */
+  __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+  __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+  PROVIDE(__stack = __StackTop);
+
+  /* Check if data + heap + stack exceeds RAM limit */
+  ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+
+  /* Check if FLASH usage exceeds FLASH size */
+  ASSERT( LENGTH(FLASH) >= (__etext + SIZEOF(.data)), "FLASH memory overflowed !")
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG_STK3401/TOOLCHAIN_GCC_ARM/startup_efm32pg1b.S	Fri Jan 15 07:45:16 2016 +0000
@@ -0,0 +1,317 @@
+/* @file startup_efm32pg1b.S
+ * @brief startup file for Silicon Labs EFM32PG1B devices.
+ *        For use with GCC for ARM Embedded Processors
+ * @version 4.2.1
+ * Date:    12 June 2014
+ *
+ */
+/* Copyright (c) 2011 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+    .syntax     unified
+    .arch       armv7-m
+    .section    .stack
+    .align      3
+#ifdef __STACK_SIZE
+    .equ        Stack_Size, __STACK_SIZE
+#else
+    .equ        Stack_Size, 0x00000400
+#endif
+    .globl      __StackTop
+    .globl      __StackLimit
+__StackLimit:
+    .space      Stack_Size
+    .size       __StackLimit, . - __StackLimit
+__StackTop:
+    .size       __StackTop, . - __StackTop
+
+    .section    .heap
+    .align      3
+#ifdef __HEAP_SIZE
+    .equ        Heap_Size, __HEAP_SIZE
+#else
+    .equ        Heap_Size, 0x00000C00
+#endif
+    .globl      __HeapBase
+    .globl      __HeapLimit
+__HeapBase:
+    .if Heap_Size
+    .space      Heap_Size
+    .endif
+    .size       __HeapBase, . - __HeapBase
+__HeapLimit:
+    .size       __HeapLimit, . - __HeapLimit
+
+    .section    .vectors
+    .align      2
+    .globl      __Vectors
+__Vectors:
+    .long       __StackTop            /* Top of Stack */
+    .long       Reset_Handler         /* Reset Handler */
+    .long       NMI_Handler           /* NMI Handler */
+    .long       HardFault_Handler     /* Hard Fault Handler */
+    .long       MemManage_Handler     /* MPU Fault Handler */
+    .long       BusFault_Handler      /* Bus Fault Handler */
+    .long       UsageFault_Handler    /* Usage Fault Handler */
+    .long       Default_Handler       /* Reserved */
+    .long       Default_Handler       /* Reserved */
+    .long       Default_Handler       /* Reserved */
+    .long       Default_Handler       /* Reserved */
+    .long       SVC_Handler           /* SVCall Handler */
+    .long       DebugMon_Handler      /* Debug Monitor Handler */
+    .long       Default_Handler       /* Reserved */
+    .long       PendSV_Handler        /* PendSV Handler */
+    .long       SysTick_Handler       /* SysTick Handler */
+
+    /* External interrupts */
+    .long       EMU_IRQHandler    /* 0 - EMU */
+    .long       Default_Handler    /* 1 - Reserved */
+    .long       WDOG0_IRQHandler    /* 2 - WDOG0 */
+    .long       Default_Handler    /* 3 - Reserved */
+    .long       Default_Handler    /* 4 - Reserved */
+    .long       Default_Handler    /* 5 - Reserved */
+    .long       Default_Handler    /* 6 - Reserved */
+    .long       Default_Handler    /* 7 - Reserved */
+    .long       LDMA_IRQHandler    /* 8 - LDMA */
+    .long       GPIO_EVEN_IRQHandler    /* 9 - GPIO_EVEN */
+    .long       TIMER0_IRQHandler    /* 10 - TIMER0 */
+    .long       USART0_RX_IRQHandler    /* 11 - USART0_RX */
+    .long       USART0_TX_IRQHandler    /* 12 - USART0_TX */
+    .long       ACMP0_IRQHandler    /* 13 - ACMP0 */
+    .long       ADC0_IRQHandler    /* 14 - ADC0 */
+    .long       IDAC0_IRQHandler    /* 15 - IDAC0 */
+    .long       I2C0_IRQHandler    /* 16 - I2C0 */
+    .long       GPIO_ODD_IRQHandler    /* 17 - GPIO_ODD */
+    .long       TIMER1_IRQHandler    /* 18 - TIMER1 */
+    .long       USART1_RX_IRQHandler    /* 19 - USART1_RX */
+    .long       USART1_TX_IRQHandler    /* 20 - USART1_TX */
+    .long       LEUART0_IRQHandler    /* 21 - LEUART0 */
+    .long       PCNT0_IRQHandler    /* 22 - PCNT0 */
+    .long       CMU_IRQHandler    /* 23 - CMU */
+    .long       MSC_IRQHandler    /* 24 - MSC */
+    .long       CRYPTO_IRQHandler    /* 25 - CRYPTO */
+    .long       LETIMER0_IRQHandler    /* 26 - LETIMER0 */
+    .long       Default_Handler    /* 27 - Reserved */
+    .long       Default_Handler    /* 28 - Reserved */
+    .long       RTCC_IRQHandler    /* 29 - RTCC */
+    .long       Default_Handler    /* 30 - Reserved */
+    .long       CRYOTIMER_IRQHandler    /* 31 - CRYOTIMER */
+    .long       Default_Handler    /* 32 - Reserved */
+    .long       FPUEH_IRQHandler    /* 33 - FPUEH */
+
+
+    .size       __Vectors, . - __Vectors
+
+    .text
+    .thumb
+    .thumb_func
+    .align      2
+    .globl      Reset_Handler
+    .type       Reset_Handler, %function
+Reset_Handler:
+#ifndef __NO_SYSTEM_INIT
+    ldr     r0, =SystemInit
+    blx     r0
+#endif
+
+/*  Firstly it copies data from read only memory to RAM. There are two schemes
+ *  to copy. One can copy more than one sections. Another can only copy
+ *  one section.  The former scheme needs more instructions and read-only
+ *  data to implement than the latter.
+ *  Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.  */
+
+#ifdef __STARTUP_COPY_MULTIPLE
+/*  Multiple sections scheme.
+ *
+ *  Between symbol address __copy_table_start__ and __copy_table_end__,
+ *  there are array of triplets, each of which specify:
+ *    offset 0: LMA of start of a section to copy from
+ *    offset 4: VMA of start of a section to copy to
+ *    offset 8: size of the section to copy. Must be multiply of 4
+ *
+ *  All addresses must be aligned to 4 bytes boundary.
+ */
+    ldr     r4, =__copy_table_start__
+    ldr     r5, =__copy_table_end__
+
+.L_loop0:
+    cmp     r4, r5
+    bge     .L_loop0_done
+    ldr     r1, [r4]
+    ldr     r2, [r4, #4]
+    ldr     r3, [r4, #8]
+
+.L_loop0_0:
+    subs    r3, #4
+    ittt    ge
+    ldrge   r0, [r1, r3]
+    strge   r0, [r2, r3]
+    bge     .L_loop0_0
+
+    adds    r4, #12
+    b       .L_loop0
+
+.L_loop0_done:
+#else
+/*  Single section scheme.
+ *
+ *  The ranges of copy from/to are specified by following symbols
+ *    __etext: LMA of start of the section to copy from. Usually end of text
+ *    __data_start__: VMA of start of the section to copy to
+ *    __data_end__: VMA of end of the section to copy to
+ *
+ *  All addresses must be aligned to 4 bytes boundary.
+ */
+    ldr     r1, =__etext
+    ldr     r2, =__data_start__
+    ldr     r3, =__data_end__
+
+.L_loop1:
+    cmp     r2, r3
+    ittt    lt
+    ldrlt   r0, [r1], #4
+    strlt   r0, [r2], #4
+    blt     .L_loop1
+#endif /*__STARTUP_COPY_MULTIPLE */
+
+/*  This part of work usually is done in C library startup code. Otherwise,
+ *  define this macro to enable it in this startup.
+ *
+ *  There are two schemes too. One can clear multiple BSS sections. Another
+ *  can only clear one section. The former is more size expensive than the
+ *  latter.
+ *
+ *  Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ *  Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ */
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
+/*  Multiple sections scheme.
+ *
+ *  Between symbol address __copy_table_start__ and __copy_table_end__,
+ *  there are array of tuples specifying:
+ *    offset 0: Start of a BSS section
+ *    offset 4: Size of this BSS section. Must be multiply of 4
+ */
+    ldr     r3, =__zero_table_start__
+    ldr     r4, =__zero_table_end__
+
+.L_loop2:
+    cmp     r3, r4
+    bge     .L_loop2_done
+    ldr     r1, [r3]
+    ldr     r2, [r3, #4]
+    movs    r0, 0
+
+.L_loop2_0:
+    subs    r2, #4
+    itt     ge
+    strge   r0, [r1, r2]
+    bge     .L_loop2_0
+    adds    r3, #8
+    b       .L_loop2
+.L_loop2_done:
+#elif defined (__STARTUP_CLEAR_BSS)
+/*  Single BSS section scheme.
+ *
+ *  The BSS section is specified by following symbols
+ *    __bss_start__: start of the BSS section.
+ *    __bss_end__: end of the BSS section.
+ *
+ *  Both addresses must be aligned to 4 bytes boundary.
+ */
+    ldr     r1, =__bss_start__
+    ldr     r2, =__bss_end__
+
+    movs    r0, 0
+.L_loop3:
+    cmp     r1, r2
+    itt     lt
+    strlt   r0, [r1], #4
+    blt     .L_loop3
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
+
+#ifndef __START
+#define __START _start
+#endif
+    bl      __START
+
+    .pool
+    .size   Reset_Handler, . - Reset_Handler
+
+    .align  1
+    .thumb_func
+    .weak   Default_Handler
+    .type   Default_Handler, %function
+Default_Handler:
+    b       .
+    .size   Default_Handler, . - Default_Handler
+
+/*    Macro to define default handlers. Default handler
+ *    will be weak symbol and just dead loops. They can be
+ *    overwritten by other handlers */
+    .macro  def_irq_handler	handler_name
+    .weak   \handler_name
+    .set    \handler_name, Default_Handler
+    .endm
+
+    def_irq_handler     NMI_Handler
+    def_irq_handler     HardFault_Handler
+    def_irq_handler     MemManage_Handler
+    def_irq_handler     BusFault_Handler
+    def_irq_handler     UsageFault_Handler
+    def_irq_handler     SVC_Handler
+    def_irq_handler     DebugMon_Handler
+    def_irq_handler     PendSV_Handler
+    def_irq_handler     SysTick_Handler
+
+
+    def_irq_handler     EMU_IRQHandler
+    def_irq_handler     WDOG0_IRQHandler
+    def_irq_handler     LDMA_IRQHandler
+    def_irq_handler     GPIO_EVEN_IRQHandler
+    def_irq_handler     TIMER0_IRQHandler
+    def_irq_handler     USART0_RX_IRQHandler
+    def_irq_handler     USART0_TX_IRQHandler
+    def_irq_handler     ACMP0_IRQHandler
+    def_irq_handler     ADC0_IRQHandler
+    def_irq_handler     IDAC0_IRQHandler
+    def_irq_handler     I2C0_IRQHandler
+    def_irq_handler     GPIO_ODD_IRQHandler
+    def_irq_handler     TIMER1_IRQHandler
+    def_irq_handler     USART1_RX_IRQHandler
+    def_irq_handler     USART1_TX_IRQHandler
+    def_irq_handler     LEUART0_IRQHandler
+    def_irq_handler     PCNT0_IRQHandler
+    def_irq_handler     CMU_IRQHandler
+    def_irq_handler     MSC_IRQHandler
+    def_irq_handler     CRYPTO_IRQHandler
+    def_irq_handler     LETIMER0_IRQHandler
+    def_irq_handler     RTCC_IRQHandler
+    def_irq_handler     CRYOTIMER_IRQHandler
+    def_irq_handler     FPUEH_IRQHandler
+
+    .end

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG_STK3401/TOOLCHAIN_IAR/efm32pg1b200f256.icf	Fri Jan 15 07:45:16 2016 +0000
@@ -0,0 +1,33 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__   = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__     = 0x0003FFFF;
+define symbol __NVIC_start__                 = 0x20000000;
+define symbol __NVIC_end__                   = 0x200000C7;
+define symbol __ICFEDIT_region_RAM_start__   = 0x200000C8;
+define symbol __ICFEDIT_region_RAM_end__     = 0x20007FFF;
+/*-Sizes-*/
+/*Heap 1/4 of ram and stack 1/8*/
+define symbol __ICFEDIT_size_cstack__   = 0x1000;
+define symbol __ICFEDIT_size_heap__     = 0x2000;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+keep { section .intvec };
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite, block CSTACK, block HEAP };
+                        
\ No newline at end of file

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG_STK3401/TOOLCHAIN_IAR/startup_efm32pg1b.S	Fri Jan 15 07:45:16 2016 +0000
@@ -0,0 +1,304 @@
+;/**************************************************************************//**
+; * @file startup_efm32pg1b.s
+; * @brief    CMSIS Core Device Startup File
+; *           Silicon Labs EFM32PG1B Device Series
+; * @version 4.2.1
+; * @date     30. January 2012
+; *
+; * @note
+; * Copyright (C) 2012 ARM Limited. All rights reserved.
+; *
+; * @par
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M
+; * processor based microcontrollers.  This file can be freely distributed
+; * within development tools that are supporting such ARM based processors.
+; *
+; * @par
+; * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; ******************************************************************************/
+
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+;
+; When debugging in RAM, it can be located in RAM with at least a 128 byte
+; alignment, 256 byte alignment is requied if all interrupt vectors are in use.
+;
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(8)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+        PUBLIC  __vector_table_0x1c
+        PUBLIC  __Vectors
+        PUBLIC  __Vectors_End
+        PUBLIC  __Vectors_Size
+
+        DATA
+
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler
+
+        DCD     NMI_Handler
+        DCD     HardFault_Handler
+        DCD     MemManage_Handler
+        DCD     BusFault_Handler
+        DCD     UsageFault_Handler
+__vector_table_0x1c
+        DCD     0
+        DCD     0
+        DCD     0
+        DCD     0
+        DCD     SVC_Handler
+        DCD     DebugMon_Handler
+        DCD     0
+        DCD     PendSV_Handler
+        DCD     SysTick_Handler
+
+        ; External Interrupts
+
+        DCD EMU_IRQHandler  ; 0: EMU Interrupt
+        DCD 0               ; 1: Reserved Interrupt
+        DCD WDOG0_IRQHandler  ; 2: WDOG0 Interrupt
+        DCD 0               ; 3: Reserved Interrupt
+        DCD 0               ; 4: Reserved Interrupt
+        DCD 0               ; 5: Reserved Interrupt
+        DCD 0               ; 6: Reserved Interrupt
+        DCD 0               ; 7: Reserved Interrupt
+        DCD LDMA_IRQHandler  ; 8: LDMA Interrupt
+        DCD GPIO_EVEN_IRQHandler  ; 9: GPIO_EVEN Interrupt
+        DCD TIMER0_IRQHandler  ; 10: TIMER0 Interrupt
+        DCD USART0_RX_IRQHandler  ; 11: USART0_RX Interrupt
+        DCD USART0_TX_IRQHandler  ; 12: USART0_TX Interrupt
+        DCD ACMP0_IRQHandler  ; 13: ACMP0 Interrupt
+        DCD ADC0_IRQHandler  ; 14: ADC0 Interrupt
+        DCD IDAC0_IRQHandler  ; 15: IDAC0 Interrupt
+        DCD I2C0_IRQHandler  ; 16: I2C0 Interrupt
+        DCD GPIO_ODD_IRQHandler  ; 17: GPIO_ODD Interrupt
+        DCD TIMER1_IRQHandler  ; 18: TIMER1 Interrupt
+        DCD USART1_RX_IRQHandler  ; 19: USART1_RX Interrupt
+        DCD USART1_TX_IRQHandler  ; 20: USART1_TX Interrupt
+        DCD LEUART0_IRQHandler  ; 21: LEUART0 Interrupt
+        DCD PCNT0_IRQHandler  ; 22: PCNT0 Interrupt
+        DCD CMU_IRQHandler  ; 23: CMU Interrupt
+        DCD MSC_IRQHandler  ; 24: MSC Interrupt
+        DCD CRYPTO_IRQHandler  ; 25: CRYPTO Interrupt
+        DCD LETIMER0_IRQHandler  ; 26: LETIMER0 Interrupt
+        DCD 0               ; 27: Reserved Interrupt
+        DCD 0               ; 28: Reserved Interrupt
+        DCD RTCC_IRQHandler  ; 29: RTCC Interrupt
+        DCD 0               ; 30: Reserved Interrupt
+        DCD CRYOTIMER_IRQHandler  ; 31: CRYOTIMER Interrupt
+        DCD 0               ; 32: Reserved Interrupt
+        DCD FPUEH_IRQHandler  ; 33: FPUEH Interrupt
+
+__Vectors_End
+__Vectors       EQU   __vector_table
+__Vectors_Size  EQU   __Vectors_End - __Vectors
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        ; Device specific interrupt handlers
+
+        PUBWEAK EMU_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+EMU_IRQHandler
+        B EMU_IRQHandler
+
+        PUBWEAK WDOG0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+WDOG0_IRQHandler
+        B WDOG0_IRQHandler
+
+        PUBWEAK LDMA_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+LDMA_IRQHandler
+        B LDMA_IRQHandler
+
+        PUBWEAK GPIO_EVEN_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+GPIO_EVEN_IRQHandler
+        B GPIO_EVEN_IRQHandler
+
+        PUBWEAK TIMER0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TIMER0_IRQHandler
+        B TIMER0_IRQHandler
+
+        PUBWEAK USART0_RX_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+USART0_RX_IRQHandler
+        B USART0_RX_IRQHandler
+
+        PUBWEAK USART0_TX_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+USART0_TX_IRQHandler
+        B USART0_TX_IRQHandler
+
+        PUBWEAK ACMP0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+ACMP0_IRQHandler
+        B ACMP0_IRQHandler
+
+        PUBWEAK ADC0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+ADC0_IRQHandler
+        B ADC0_IRQHandler
+
+        PUBWEAK IDAC0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+IDAC0_IRQHandler
+        B IDAC0_IRQHandler
+
+        PUBWEAK I2C0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+I2C0_IRQHandler
+        B I2C0_IRQHandler
+
+        PUBWEAK GPIO_ODD_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+GPIO_ODD_IRQHandler
+        B GPIO_ODD_IRQHandler
+
+        PUBWEAK TIMER1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TIMER1_IRQHandler
+        B TIMER1_IRQHandler
+
+        PUBWEAK USART1_RX_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+USART1_RX_IRQHandler
+        B USART1_RX_IRQHandler
+
+        PUBWEAK USART1_TX_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+USART1_TX_IRQHandler
+        B USART1_TX_IRQHandler
+
+        PUBWEAK LEUART0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+LEUART0_IRQHandler
+        B LEUART0_IRQHandler
+
+        PUBWEAK PCNT0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+PCNT0_IRQHandler
+        B PCNT0_IRQHandler
+
+        PUBWEAK CMU_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+CMU_IRQHandler
+        B CMU_IRQHandler
+
+        PUBWEAK MSC_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+MSC_IRQHandler
+        B MSC_IRQHandler
+
+        PUBWEAK CRYPTO_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+CRYPTO_IRQHandler
+        B CRYPTO_IRQHandler
+
+        PUBWEAK LETIMER0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+LETIMER0_IRQHandler
+        B LETIMER0_IRQHandler
+
+        PUBWEAK RTCC_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RTCC_IRQHandler
+        B RTCC_IRQHandler
+
+        PUBWEAK CRYOTIMER_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+CRYOTIMER_IRQHandler
+        B CRYOTIMER_IRQHandler
+
+        PUBWEAK FPUEH_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+FPUEH_IRQHandler
+        B FPUEH_IRQHandler
+
+
+        END

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG_STK3401/cmsis.h	Fri Jan 15 07:45:16 2016 +0000
@@ -0,0 +1,13 @@
+/* mbed Microcontroller Library - CMSIS
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * A generic CMSIS include header, pulling in EFM32 specifics
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "em_device.h"
+#include "cmsis_nvic.h"
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG_STK3401/cmsis_nvic.c	Fri Jan 15 07:45:16 2016 +0000
@@ -0,0 +1,47 @@
+/* mbed Microcontroller Library - cmsis_nvic for EFM32
+ * Copyright (c) 2011 ARM Limited. All rights reserved.
+ *
+ * CMSIS-style functionality to support dynamic vectors
+ */
+#include "cmsis_nvic.h"
+
+#if (defined (__GNUC__) && (!defined(__CC_ARM)))
+extern uint32_t __start_vector_table__;		  // Dynamic vector positioning in GCC
+#endif
+
+#define NVIC_RAM_VECTOR_ADDRESS (0x20000000)  // Vectors positioned at start of RAM
+#define NVIC_FLASH_VECTOR_ADDRESS (0x0)       // Initial vector position in flash
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+    uint32_t *vectors = (uint32_t*)SCB->VTOR;
+    uint32_t i;
+
+    // Copy and switch to dynamic vectors if the first time called
+    // For GCC, use dynamic vector table placement since otherwise we run into an alignment conflict
+#if (defined (__GNUC__) && (!defined(__CC_ARM)))
+    if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
+        uint32_t *old_vectors = vectors;
+        vectors = (uint32_t*)(&__start_vector_table__);
+        for (i=0; i<NVIC_NUM_VECTORS; i++) {
+            vectors[i] = old_vectors[i];
+        }
+        SCB->VTOR = (uint32_t)(&__start_vector_table__);
+    }
+    // Other compilers don't matter as much...
+#else
+    if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
+		uint32_t *old_vectors = vectors;
+		vectors = (uint32_t*)(NVIC_RAM_VECTOR_ADDRESS);
+		for (i=0; i<NVIC_NUM_VECTORS; i++) {
+			vectors[i] = old_vectors[i];
+		}
+		SCB->VTOR = (uint32_t)(NVIC_RAM_VECTOR_ADDRESS);
+	}
+#endif
+    vectors[IRQn + 16] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+    uint32_t *vectors = (uint32_t*)SCB->VTOR;
+    return vectors[IRQn + 16];
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG_STK3401/cmsis_nvic.h	Fri Jan 15 07:45:16 2016 +0000
@@ -0,0 +1,26 @@
+/* mbed Microcontroller Library - cmsis_nvic
+ * Copyright (c) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * CMSIS-style functionality to support dynamic vectors
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#include "cmsis.h"
+
+#define NVIC_NUM_VECTORS      (16 + 34)   // CORE + MCU Peripherals
+#define NVIC_USER_IRQ_OFFSET  16
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG_STK3401/efm32pg1b100f128gm32.h	Fri Jan 15 07:45:16 2016 +0000
@@ -0,0 +1,425 @@
+/**************************************************************************//**
+ * @file efm32pg1b100f128gm32.h
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File
+ *        for EFM32PG1B100F128GM32
+ * @version 4.2.0
+ ******************************************************************************
+ * @section License
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ ******************************************************************************
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software.@n
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.@n
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is
+ * providing the Software "AS IS", with no express or implied warranties of any
+ * kind, including, but not limited to, any implied warranties of
+ * merchantability or fitness for any particular purpose or warranties against
+ * infringement of any proprietary rights of a third party.
+ *
+ * Silicon Laboratories, Inc. will not be liable for any consequential,
+ * incidental, or special damages, or any other relief, or for any claim by
+ * any third party, arising from your use of this Software.
+ *
+ *****************************************************************************/
+
+#ifndef SILICON_LABS_EFM32PG1B100F128GM32_H
+#define SILICON_LABS_EFM32PG1B100F128GM32_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ *****************************************************************************/
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B100F128GM32 EFM32PG1B100F128GM32
+ * @{
+ *****************************************************************************/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M4 Processor Exceptions Numbers *******************************************/
+  NonMaskableInt_IRQn   = -14,              /*!< 2  Cortex-M4 Non Maskable Interrupt      */
+  HardFault_IRQn        = -13,              /*!< 3  Cortex-M4 Hard Fault Interrupt        */
+  MemoryManagement_IRQn = -12,              /*!< 4  Cortex-M4 Memory Management Interrupt */
+  BusFault_IRQn         = -11,              /*!< 5  Cortex-M4 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10,              /*!< 6  Cortex-M4 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,               /*!< 11 Cortex-M4 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,               /*!< 12 Cortex-M4 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,               /*!< 14 Cortex-M4 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,               /*!< 15 Cortex-M4 System Tick Interrupt       */
+
+/******  EFM32PG1B Peripheral Interrupt Numbers *********************************************/
+
+  EMU_IRQn              = 0,  /*!< 16+0 EFM32 EMU Interrupt */
+  WDOG0_IRQn            = 2,  /*!< 16+2 EFM32 WDOG0 Interrupt */
+  LDMA_IRQn             = 8,  /*!< 16+8 EFM32 LDMA Interrupt */
+  GPIO_EVEN_IRQn        = 9,  /*!< 16+9 EFM32 GPIO_EVEN Interrupt */
+  TIMER0_IRQn           = 10, /*!< 16+10 EFM32 TIMER0 Interrupt */
+  USART0_RX_IRQn        = 11, /*!< 16+11 EFM32 USART0_RX Interrupt */
+  USART0_TX_IRQn        = 12, /*!< 16+12 EFM32 USART0_TX Interrupt */
+  ACMP0_IRQn            = 13, /*!< 16+13 EFM32 ACMP0 Interrupt */
+  ADC0_IRQn             = 14, /*!< 16+14 EFM32 ADC0 Interrupt */
+  IDAC0_IRQn            = 15, /*!< 16+15 EFM32 IDAC0 Interrupt */
+  I2C0_IRQn             = 16, /*!< 16+16 EFM32 I2C0 Interrupt */
+  GPIO_ODD_IRQn         = 17, /*!< 16+17 EFM32 GPIO_ODD Interrupt */
+  TIMER1_IRQn           = 18, /*!< 16+18 EFM32 TIMER1 Interrupt */
+  USART1_RX_IRQn        = 19, /*!< 16+19 EFM32 USART1_RX Interrupt */
+  USART1_TX_IRQn        = 20, /*!< 16+20 EFM32 USART1_TX Interrupt */
+  LEUART0_IRQn          = 21, /*!< 16+21 EFM32 LEUART0 Interrupt */
+  PCNT0_IRQn            = 22, /*!< 16+22 EFM32 PCNT0 Interrupt */
+  CMU_IRQn              = 23, /*!< 16+23 EFM32 CMU Interrupt */
+  MSC_IRQn              = 24, /*!< 16+24 EFM32 MSC Interrupt */
+  CRYPTO_IRQn           = 25, /*!< 16+25 EFM32 CRYPTO Interrupt */
+  LETIMER0_IRQn         = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */
+  RTCC_IRQn             = 29, /*!< 16+29 EFM32 RTCC Interrupt */
+  CRYOTIMER_IRQn        = 31, /*!< 16+31 EFM32 CRYOTIMER Interrupt */
+  FPUEH_IRQn            = 33, /*!< 16+33 EFM32 FPUEH Interrupt */
+} IRQn_Type;
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B100F128GM32_Core EFM32PG1B100F128GM32 Core
+ * @{
+ * @brief Processor and Core Peripheral Section
+ *****************************************************************************/
+#define __MPU_PRESENT             1 /**< Presence of MPU  */
+#define __FPU_PRESENT             1 /**< Presence of FPU  */
+#define __NVIC_PRIO_BITS          3 /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig    0 /**< Is 1 if different SysTick counter is used */
+
+/** @} End of group EFM32PG1B100F128GM32_Core */
+
+/**************************************************************************//**
+* @defgroup EFM32PG1B100F128GM32_Part EFM32PG1B100F128GM32 Part
+* @{
+******************************************************************************/
+
+/** Part family */
+#define _EFM32_PEARL_FAMILY             1 /**< PEARL Gecko MCU Family  */
+#define _EFM_DEVICE                       /**< Silicon Labs EFM-type microcontroller */
+#define _SILICON_LABS_32B_PLATFORM_2      /**< Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM      2 /**< Silicon Labs platform name */
+
+/* If part number is not defined as compiler option, define it */
+#if !defined(EFM32PG1B100F128GM32)
+#define EFM32PG1B100F128GM32    1 /**< PEARL Gecko Part */
+#endif
+
+/** Configure part number */
+#define PART_NUMBER               "EFM32PG1B100F128GM32" /**< Part Number */
+
+/** Memory Base addresses and limits */
+#define FLASH_MEM_BASE            ((uint32_t) 0x00000000UL) /**< FLASH base address  */
+#define FLASH_MEM_SIZE            ((uint32_t) 0x10000000UL) /**< FLASH available address space  */
+#define FLASH_MEM_END             ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address  */
+#define FLASH_MEM_BITS            ((uint32_t) 0x28UL)       /**< FLASH used bits  */
+#define RAM_CODE_MEM_BASE         ((uint32_t) 0x10000000UL) /**< RAM_CODE base address  */
+#define RAM_CODE_MEM_SIZE         ((uint32_t) 0x7C00UL)     /**< RAM_CODE available address space  */
+#define RAM_CODE_MEM_END          ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address  */
+#define RAM_CODE_MEM_BITS         ((uint32_t) 0x15UL)       /**< RAM_CODE used bits  */
+#define PER_BITCLR_MEM_BASE       ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address  */
+#define PER_BITCLR_MEM_SIZE       ((uint32_t) 0xE8000UL)    /**< PER_BITCLR available address space  */
+#define PER_BITCLR_MEM_END        ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address  */
+#define PER_BITCLR_MEM_BITS       ((uint32_t) 0x20UL)       /**< PER_BITCLR used bits  */
+#define CRYPTO_BITSET_MEM_BASE    ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address  */
+#define CRYPTO_BITSET_MEM_SIZE    ((uint32_t) 0x400UL)      /**< CRYPTO_BITSET available address space  */
+#define CRYPTO_BITSET_MEM_END     ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address  */
+#define CRYPTO_BITSET_MEM_BITS    ((uint32_t) 0x10UL)       /**< CRYPTO_BITSET used bits  */
+#define CRYPTO_MEM_BASE           ((uint32_t) 0x400F0000UL) /**< CRYPTO base address  */
+#define CRYPTO_MEM_SIZE           ((uint32_t) 0x400UL)      /**< CRYPTO available address space  */
+#define CRYPTO_MEM_END            ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address  */
+#define CRYPTO_MEM_BITS           ((uint32_t) 0x10UL)       /**< CRYPTO used bits  */
+#define CRYPTO_BITCLR_MEM_BASE    ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address  */
+#define CRYPTO_BITCLR_MEM_SIZE    ((uint32_t) 0x400UL)      /**< CRYPTO_BITCLR available address space  */
+#define CRYPTO_BITCLR_MEM_END     ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address  */
+#define CRYPTO_BITCLR_MEM_BITS    ((uint32_t) 0x10UL)       /**< CRYPTO_BITCLR used bits  */
+#define PER_BITSET_MEM_BASE       ((uint32_t) 0x46000000UL) /**< PER_BITSET base address  */
+#define PER_BITSET_MEM_SIZE       ((uint32_t) 0xE8000UL)    /**< PER_BITSET available address space  */
+#define PER_BITSET_MEM_END        ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address  */
+#define PER_BITSET_MEM_BITS       ((uint32_t) 0x20UL)       /**< PER_BITSET used bits  */
+#define PER_MEM_BASE              ((uint32_t) 0x40000000UL) /**< PER base address  */
+#define PER_MEM_SIZE              ((uint32_t) 0xE8000UL)    /**< PER available address space  */
+#define PER_MEM_END               ((uint32_t) 0x400E7FFFUL) /**< PER end address  */
+#define PER_MEM_BITS              ((uint32_t) 0x20UL)       /**< PER used bits  */
+#define RAM_MEM_BASE              ((uint32_t) 0x20000000UL) /**< RAM base address  */
+#define RAM_MEM_SIZE              ((uint32_t) 0x7C00UL)     /**< RAM available address space  */
+#define RAM_MEM_END               ((uint32_t) 0x20007BFFUL) /**< RAM end address  */
+#define RAM_MEM_BITS              ((uint32_t) 0x15UL)       /**< RAM used bits  */
+
+/** Bit banding area */
+#define BITBAND_PER_BASE          ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
+#define BITBAND_RAM_BASE          ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
+
+/** Flash and SRAM limits for EFM32PG1B100F128GM32 */
+#define FLASH_BASE                (0x00000000UL) /**< Flash Base Address */
+#define FLASH_SIZE                (0x00020000UL) /**< Available Flash Memory */
+#define FLASH_PAGE_SIZE           2048           /**< Flash Memory page size */
+#define SRAM_BASE                 (0x20000000UL) /**< SRAM Base Address */
+#define SRAM_SIZE                 (0x00008000UL) /**< Available SRAM Memory */
+#define __CM4_REV                 0x001          /**< Cortex-M4 Core revision r0p1 */
+#define PRS_CHAN_COUNT            12             /**< Number of PRS channels */
+#define DMA_CHAN_COUNT            8              /**< Number of DMA channels */
+
+/** AF channels connect the different on-chip peripherals with the af-mux */
+#define AFCHAN_MAX                72
+#define AFCHANLOC_MAX             32
+/** Analog AF channels */
+#define AFACHAN_MAX               61
+
+/* Part number capabilities */
+
+#define TIMER_PRESENT         /**< TIMER is available in this part */
+#define TIMER_COUNT         2 /**< 2 TIMERs available  */
+#define USART_PRESENT         /**< USART is available in this part */
+#define USART_COUNT         2 /**< 2 USARTs available  */
+#define LEUART_PRESENT        /**< LEUART is available in this part */
+#define LEUART_COUNT        1 /**< 1 LEUARTs available  */
+#define LETIMER_PRESENT       /**< LETIMER is available in this part */
+#define LETIMER_COUNT       1 /**< 1 LETIMERs available  */
+#define PCNT_PRESENT          /**< PCNT is available in this part */
+#define PCNT_COUNT          1 /**< 1 PCNTs available  */
+#define I2C_PRESENT           /**< I2C is available in this part */
+#define I2C_COUNT           1 /**< 1 I2Cs available  */
+#define ADC_PRESENT           /**< ADC is available in this part */
+#define ADC_COUNT           1 /**< 1 ADCs available  */
+#define ACMP_PRESENT          /**< ACMP is available in this part */
+#define ACMP_COUNT          2 /**< 2 ACMPs available  */
+#define IDAC_PRESENT          /**< IDAC is available in this part */
+#define IDAC_COUNT          1 /**< 1 IDACs available  */
+#define WDOG_PRESENT          /**< WDOG is available in this part */
+#define WDOG_COUNT          1 /**< 1 WDOGs available  */
+#define MSC_PRESENT
+#define MSC_COUNT           1
+#define EMU_PRESENT
+#define EMU_COUNT           1
+#define RMU_PRESENT
+#define RMU_COUNT           1
+#define CMU_PRESENT
+#define CMU_COUNT           1
+#define CRYPTO_PRESENT
+#define CRYPTO_COUNT        1
+#define GPIO_PRESENT
+#define GPIO_COUNT          1
+#define PRS_PRESENT
+#define PRS_COUNT           1
+#define LDMA_PRESENT
+#define LDMA_COUNT          1
+#define FPUEH_PRESENT
+#define FPUEH_COUNT         1
+#define GPCRC_PRESENT
+#define GPCRC_COUNT         1
+#define CRYOTIMER_PRESENT
+#define CRYOTIMER_COUNT     1
+#define RTCC_PRESENT
+#define RTCC_COUNT          1
+#define BOOTLOADER_PRESENT
+#define BOOTLOADER_COUNT    1
+
+#include "core_cm4.h"         /* Cortex-M4 processor and core peripherals */
+#include "system_efm32pg1b.h" /* System Header File */
+
+/** @} End of group EFM32PG1B100F128GM32_Part */
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B100F128GM32_Peripheral_TypeDefs EFM32PG1B100F128GM32 Peripheral TypeDefs
+ * @{
+ * @brief Device Specific Peripheral Register Structures
+ *****************************************************************************/
+
+#include "efm32pg1b_msc.h"
+#include "efm32pg1b_emu.h"
+#include "efm32pg1b_rmu.h"
+#include "efm32pg1b_cmu.h"
+#include "efm32pg1b_crypto.h"
+#include "efm32pg1b_gpio_p.h"
+#include "efm32pg1b_gpio.h"
+#include "efm32pg1b_prs_ch.h"
+#include "efm32pg1b_prs.h"
+#include "efm32pg1b_ldma_ch.h"
+#include "efm32pg1b_ldma.h"
+#include "efm32pg1b_fpueh.h"
+#include "efm32pg1b_gpcrc.h"
+#include "efm32pg1b_timer_cc.h"
+#include "efm32pg1b_timer.h"
+#include "efm32pg1b_usart.h"
+#include "efm32pg1b_leuart.h"
+#include "efm32pg1b_letimer.h"
+#include "efm32pg1b_cryotimer.h"
+#include "efm32pg1b_pcnt.h"
+#include "efm32pg1b_i2c.h"
+#include "efm32pg1b_adc.h"
+#include "efm32pg1b_acmp.h"
+#include "efm32pg1b_idac.h"
+#include "efm32pg1b_rtcc_cc.h"
+#include "efm32pg1b_rtcc_ret.h"
+#include "efm32pg1b_rtcc.h"
+#include "efm32pg1b_wdog_pch.h"
+#include "efm32pg1b_wdog.h"
+#include "efm32pg1b_dma_descriptor.h"
+#include "efm32pg1b_devinfo.h"
+#include "efm32pg1b_romtable.h"
+
+/** @} End of group EFM32PG1B100F128GM32_Peripheral_TypeDefs  */
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B100F128GM32_Peripheral_Base EFM32PG1B100F128GM32 Peripheral Memory Map
+ * @{
+ *****************************************************************************/
+
+#define MSC_BASE          (0x400E0000UL) /**< MSC base address  */
+#define EMU_BASE          (0x400E3000UL) /**< EMU base address  */
+#define RMU_BASE          (0x400E5000UL) /**< RMU base address  */
+#define CMU_BASE          (0x400E4000UL) /**< CMU base address  */
+#define CRYPTO_BASE       (0x400F0000UL) /**< CRYPTO base address  */
+#define GPIO_BASE         (0x4000A000UL) /**< GPIO base address  */
+#define PRS_BASE          (0x400E6000UL) /**< PRS base address  */
+#define LDMA_BASE         (0x400E2000UL) /**< LDMA base address  */
+#define FPUEH_BASE        (0x400E1000UL) /**< FPUEH base address  */
+#define GPCRC_BASE        (0x4001C000UL) /**< GPCRC base address  */
+#define TIMER0_BASE       (0x40018000UL) /**< TIMER0 base address  */
+#define TIMER1_BASE       (0x40018400UL) /**< TIMER1 base address  */
+#define USART0_BASE       (0x40010000UL) /**< USART0 base address  */
+#define USART1_BASE       (0x40010400UL) /**< USART1 base address  */
+#define LEUART0_BASE      (0x4004A000UL) /**< LEUART0 base address  */
+#define LETIMER0_BASE     (0x40046000UL) /**< LETIMER0 base address  */
+#define CRYOTIMER_BASE    (0x4001E000UL) /**< CRYOTIMER base address  */
+#define PCNT0_BASE        (0x4004E000UL) /**< PCNT0 base address  */
+#define I2C0_BASE         (0x4000C000UL) /**< I2C0 base address  */
+#define ADC0_BASE         (0x40002000UL) /**< ADC0 base address  */
+#define ACMP0_BASE        (0x40000000UL) /**< ACMP0 base address  */
+#define ACMP1_BASE        (0x40000400UL) /**< ACMP1 base address  */
+#define IDAC0_BASE        (0x40006000UL) /**< IDAC0 base address  */
+#define RTCC_BASE         (0x40042000UL) /**< RTCC base address  */
+#define WDOG0_BASE        (0x40052000UL) /**< WDOG0 base address  */
+#define DEVINFO_BASE      (0x0FE081B0UL) /**< DEVINFO base address */
+#define ROMTABLE_BASE     (0xE00FFFD0UL) /**< ROMTABLE base address */
+#define LOCKBITS_BASE     (0x0FE04000UL) /**< Lock-bits page base address */
+#define USERDATA_BASE     (0x0FE00000UL) /**< User data page base address */
+
+/** @} End of group EFM32PG1B100F128GM32_Peripheral_Base */
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B100F128GM32_Peripheral_Declaration  EFM32PG1B100F128GM32 Peripheral Declarations
+ * @{
+ *****************************************************************************/
+
+#define MSC          ((MSC_TypeDef *) MSC_BASE)             /**< MSC base pointer */
+#define EMU          ((EMU_TypeDef *) EMU_BASE)             /**< EMU base pointer */
+#define RMU          ((RMU_TypeDef *) RMU_BASE)             /**< RMU base pointer */
+#define CMU          ((CMU_TypeDef *) CMU_BASE)             /**< CMU base pointer */
+#define CRYPTO       ((CRYPTO_TypeDef *) CRYPTO_BASE)       /**< CRYPTO base pointer */
+#define GPIO         ((GPIO_TypeDef *) GPIO_BASE)           /**< GPIO base pointer */
+#define PRS          ((PRS_TypeDef *) PRS_BASE)             /**< PRS base pointer */
+#define LDMA         ((LDMA_TypeDef *) LDMA_BASE)           /**< LDMA base pointer */
+#define FPUEH        ((FPUEH_TypeDef *) FPUEH_BASE)         /**< FPUEH base pointer */
+#define GPCRC        ((GPCRC_TypeDef *) GPCRC_BASE)         /**< GPCRC base pointer */
+#define TIMER0       ((TIMER_TypeDef *) TIMER0_BASE)        /**< TIMER0 base pointer */
+#define TIMER1       ((TIMER_TypeDef *) TIMER1_BASE)        /**< TIMER1 base pointer */
+#define USART0       ((USART_TypeDef *) USART0_BASE)        /**< USART0 base pointer */
+#define USART1       ((USART_TypeDef *) USART1_BASE)        /**< USART1 base pointer */
+#define LEUART0      ((LEUART_TypeDef *) LEUART0_BASE)      /**< LEUART0 base pointer */
+#define LETIMER0     ((LETIMER_TypeDef *) LETIMER0_BASE)    /**< LETIMER0 base pointer */
+#define CRYOTIMER    ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */
+#define PCNT0        ((PCNT_TypeDef *) PCNT0_BASE)          /**< PCNT0 base pointer */
+#define I2C0         ((I2C_TypeDef *) I2C0_BASE)            /**< I2C0 base pointer */
+#define ADC0         ((ADC_TypeDef *) ADC0_BASE)            /**< ADC0 base pointer */
+#define ACMP0        ((ACMP_TypeDef *) ACMP0_BASE)          /**< ACMP0 base pointer */
+#define ACMP1        ((ACMP_TypeDef *) ACMP1_BASE)          /**< ACMP1 base pointer */
+#define IDAC0        ((IDAC_TypeDef *) IDAC0_BASE)          /**< IDAC0 base pointer */
+#define RTCC         ((RTCC_TypeDef *) RTCC_BASE)           /**< RTCC base pointer */
+#define WDOG0        ((WDOG_TypeDef *) WDOG0_BASE)          /**< WDOG0 base pointer */
+#define DEVINFO      ((DEVINFO_TypeDef *) DEVINFO_BASE)     /**< DEVINFO base pointer */
+#define ROMTABLE     ((ROMTABLE_TypeDef *) ROMTABLE_BASE)   /**< ROMTABLE base pointer */
+
+/** @} End of group EFM32PG1B100F128GM32_Peripheral_Declaration */
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B100F128GM32_Peripheral_Offsets  EFM32PG1B100F128GM32 Peripheral Offsets
+ * @{
+ *****************************************************************************/
+
+#define TIMER_OFFSET      0x400 /**< Offset in bytes between TIMER instances */
+#define USART_OFFSET      0x400 /**< Offset in bytes between USART instances */
+#define LEUART_OFFSET     0x400 /**< Offset in bytes between LEUART instances */
+#define LETIMER_OFFSET    0x400 /**< Offset in bytes between LETIMER instances */
+#define PCNT_OFFSET       0x400 /**< Offset in bytes between PCNT instances */
+#define I2C_OFFSET        0x400 /**< Offset in bytes between I2C instances */
+#define ADC_OFFSET        0x400 /**< Offset in bytes between ADC instances */
+#define ACMP_OFFSET       0x400 /**< Offset in bytes between ACMP instances */
+#define IDAC_OFFSET       0x400 /**< Offset in bytes between IDAC instances */
+#define WDOG_OFFSET       0x400 /**< Offset in bytes between WDOG instances */
+
+/** @} End of group EFM32PG1B100F128GM32_Peripheral_Offsets */
+
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B100F128GM32_BitFields EFM32PG1B100F128GM32 Bit Fields
+ * @{
+ *****************************************************************************/
+
+#include "efm32pg1b_prs_signals.h"
+#include "efm32pg1b_dmareq.h"
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B100F128GM32_UNLOCK EFM32PG1B100F128GM32 Unlock Codes
+ * @{
+ *****************************************************************************/
+#define MSC_UNLOCK_CODE      0x1B71 /**< MSC unlock code */
+#define EMU_UNLOCK_CODE      0xADE8 /**< EMU unlock code */
+#define RMU_UNLOCK_CODE      0xE084 /**< RMU unlock code */
+#define CMU_UNLOCK_CODE      0x580E /**< CMU unlock code */
+#define GPIO_UNLOCK_CODE     0xA534 /**< GPIO unlock code */
+#define TIMER_UNLOCK_CODE    0xCE80 /**< TIMER unlock code */
+#define RTCC_UNLOCK_CODE     0xAEE8 /**< RTCC unlock code */
+
+/** @} End of group EFM32PG1B100F128GM32_UNLOCK */
+
+/** @} End of group EFM32PG1B100F128GM32_BitFields */
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B100F128GM32_Alternate_Function EFM32PG1B100F128GM32 Alternate Function
+ * @{
+ *****************************************************************************/
+
+#include "efm32pg1b_af_ports.h"
+#include "efm32pg1b_af_pins.h"
+
+/** @} End of group EFM32PG1B100F128GM32_Alternate_Function */
+
+/**************************************************************************//**
+ *  @brief Set the value of a bit field within a register.
+ *
+ *  @param REG
+ *       The register to update
+ *  @param MASK
+ *       The mask for the bit field to update
+ *  @param VALUE
+ *       The value to write to the bit field
+ *  @param OFFSET
+ *       The number of bits that the field is offset within the register.
+ *       0 (zero) means LSB.
+ *****************************************************************************/
+#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
+  REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
+
+/** @} End of group EFM32PG1B100F128GM32 */
+
+/** @} End of group Parts */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* SILICON_LABS_EFM32PG1B100F128GM32_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG_STK3401/efm32pg1b100f256gm32.h	Fri Jan 15 07:45:16 2016 +0000
@@ -0,0 +1,425 @@
+/**************************************************************************//**
+ * @file efm32pg1b100f256gm32.h
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File
+ *        for EFM32PG1B100F256GM32
+ * @version 4.2.0
+ ******************************************************************************
+ * @section License
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ ******************************************************************************
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software.@n
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.@n
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is
+ * providing the Software "AS IS", with no express or implied warranties of any
+ * kind, including, but not limited to, any implied warranties of
+ * merchantability or fitness for any particular purpose or warranties against
+ * infringement of any proprietary rights of a third party.
+ *
+ * Silicon Laboratories, Inc. will not be liable for any consequential,
+ * incidental, or special damages, or any other relief, or for any claim by
+ * any third party, arising from your use of this Software.
+ *
+ *****************************************************************************/
+
+#ifndef SILICON_LABS_EFM32PG1B100F256GM32_H
+#define SILICON_LABS_EFM32PG1B100F256GM32_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ *****************************************************************************/
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B100F256GM32 EFM32PG1B100F256GM32
+ * @{
+ *****************************************************************************/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M4 Processor Exceptions Numbers *******************************************/
+  NonMaskableInt_IRQn   = -14,              /*!< 2  Cortex-M4 Non Maskable Interrupt      */
+  HardFault_IRQn        = -13,              /*!< 3  Cortex-M4 Hard Fault Interrupt        */
+  MemoryManagement_IRQn = -12,              /*!< 4  Cortex-M4 Memory Management Interrupt */
+  BusFault_IRQn         = -11,              /*!< 5  Cortex-M4 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10,              /*!< 6  Cortex-M4 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,               /*!< 11 Cortex-M4 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,               /*!< 12 Cortex-M4 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,               /*!< 14 Cortex-M4 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,               /*!< 15 Cortex-M4 System Tick Interrupt       */
+
+/******  EFM32PG1B Peripheral Interrupt Numbers *********************************************/
+
+  EMU_IRQn              = 0,  /*!< 16+0 EFM32 EMU Interrupt */
+  WDOG0_IRQn            = 2,  /*!< 16+2 EFM32 WDOG0 Interrupt */
+  LDMA_IRQn             = 8,  /*!< 16+8 EFM32 LDMA Interrupt */
+  GPIO_EVEN_IRQn        = 9,  /*!< 16+9 EFM32 GPIO_EVEN Interrupt */
+  TIMER0_IRQn           = 10, /*!< 16+10 EFM32 TIMER0 Interrupt */
+  USART0_RX_IRQn        = 11, /*!< 16+11 EFM32 USART0_RX Interrupt */
+  USART0_TX_IRQn        = 12, /*!< 16+12 EFM32 USART0_TX Interrupt */
+  ACMP0_IRQn            = 13, /*!< 16+13 EFM32 ACMP0 Interrupt */
+  ADC0_IRQn             = 14, /*!< 16+14 EFM32 ADC0 Interrupt */
+  IDAC0_IRQn            = 15, /*!< 16+15 EFM32 IDAC0 Interrupt */
+  I2C0_IRQn             = 16, /*!< 16+16 EFM32 I2C0 Interrupt */
+  GPIO_ODD_IRQn         = 17, /*!< 16+17 EFM32 GPIO_ODD Interrupt */
+  TIMER1_IRQn           = 18, /*!< 16+18 EFM32 TIMER1 Interrupt */
+  USART1_RX_IRQn        = 19, /*!< 16+19 EFM32 USART1_RX Interrupt */
+  USART1_TX_IRQn        = 20, /*!< 16+20 EFM32 USART1_TX Interrupt */
+  LEUART0_IRQn          = 21, /*!< 16+21 EFM32 LEUART0 Interrupt */
+  PCNT0_IRQn            = 22, /*!< 16+22 EFM32 PCNT0 Interrupt */
+  CMU_IRQn              = 23, /*!< 16+23 EFM32 CMU Interrupt */
+  MSC_IRQn              = 24, /*!< 16+24 EFM32 MSC Interrupt */
+  CRYPTO_IRQn           = 25, /*!< 16+25 EFM32 CRYPTO Interrupt */
+  LETIMER0_IRQn         = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */
+  RTCC_IRQn             = 29, /*!< 16+29 EFM32 RTCC Interrupt */
+  CRYOTIMER_IRQn        = 31, /*!< 16+31 EFM32 CRYOTIMER Interrupt */
+  FPUEH_IRQn            = 33, /*!< 16+33 EFM32 FPUEH Interrupt */
+} IRQn_Type;
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B100F256GM32_Core EFM32PG1B100F256GM32 Core
+ * @{
+ * @brief Processor and Core Peripheral Section
+ *****************************************************************************/
+#define __MPU_PRESENT             1 /**< Presence of MPU  */
+#define __FPU_PRESENT             1 /**< Presence of FPU  */
+#define __NVIC_PRIO_BITS          3 /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig    0 /**< Is 1 if different SysTick counter is used */
+
+/** @} End of group EFM32PG1B100F256GM32_Core */
+
+/**************************************************************************//**
+* @defgroup EFM32PG1B100F256GM32_Part EFM32PG1B100F256GM32 Part
+* @{
+******************************************************************************/
+
+/** Part family */
+#define _EFM32_PEARL_FAMILY             1 /**< PEARL Gecko MCU Family  */
+#define _EFM_DEVICE                       /**< Silicon Labs EFM-type microcontroller */
+#define _SILICON_LABS_32B_PLATFORM_2      /**< Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM      2 /**< Silicon Labs platform name */
+
+/* If part number is not defined as compiler option, define it */
+#if !defined(EFM32PG1B100F256GM32)
+#define EFM32PG1B100F256GM32    1 /**< PEARL Gecko Part */
+#endif
+
+/** Configure part number */
+#define PART_NUMBER               "EFM32PG1B100F256GM32" /**< Part Number */
+
+/** Memory Base addresses and limits */
+#define FLASH_MEM_BASE            ((uint32_t) 0x00000000UL) /**< FLASH base address  */
+#define FLASH_MEM_SIZE            ((uint32_t) 0x10000000UL) /**< FLASH available address space  */
+#define FLASH_MEM_END             ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address  */
+#define FLASH_MEM_BITS            ((uint32_t) 0x28UL)       /**< FLASH used bits  */
+#define RAM_CODE_MEM_BASE         ((uint32_t) 0x10000000UL) /**< RAM_CODE base address  */
+#define RAM_CODE_MEM_SIZE         ((uint32_t) 0x7C00UL)     /**< RAM_CODE available address space  */
+#define RAM_CODE_MEM_END          ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address  */
+#define RAM_CODE_MEM_BITS         ((uint32_t) 0x15UL)       /**< RAM_CODE used bits  */
+#define PER_BITCLR_MEM_BASE       ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address  */
+#define PER_BITCLR_MEM_SIZE       ((uint32_t) 0xE8000UL)    /**< PER_BITCLR available address space  */
+#define PER_BITCLR_MEM_END        ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address  */
+#define PER_BITCLR_MEM_BITS       ((uint32_t) 0x20UL)       /**< PER_BITCLR used bits  */
+#define CRYPTO_BITSET_MEM_BASE    ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address  */
+#define CRYPTO_BITSET_MEM_SIZE    ((uint32_t) 0x400UL)      /**< CRYPTO_BITSET available address space  */
+#define CRYPTO_BITSET_MEM_END     ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address  */
+#define CRYPTO_BITSET_MEM_BITS    ((uint32_t) 0x10UL)       /**< CRYPTO_BITSET used bits  */
+#define CRYPTO_MEM_BASE           ((uint32_t) 0x400F0000UL) /**< CRYPTO base address  */
+#define CRYPTO_MEM_SIZE           ((uint32_t) 0x400UL)      /**< CRYPTO available address space  */
+#define CRYPTO_MEM_END            ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address  */
+#define CRYPTO_MEM_BITS           ((uint32_t) 0x10UL)       /**< CRYPTO used bits  */
+#define CRYPTO_BITCLR_MEM_BASE    ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address  */
+#define CRYPTO_BITCLR_MEM_SIZE    ((uint32_t) 0x400UL)      /**< CRYPTO_BITCLR available address space  */
+#define CRYPTO_BITCLR_MEM_END     ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address  */
+#define CRYPTO_BITCLR_MEM_BITS    ((uint32_t) 0x10UL)       /**< CRYPTO_BITCLR used bits  */
+#define PER_BITSET_MEM_BASE       ((uint32_t) 0x46000000UL) /**< PER_BITSET base address  */
+#define PER_BITSET_MEM_SIZE       ((uint32_t) 0xE8000UL)    /**< PER_BITSET available address space  */
+#define PER_BITSET_MEM_END        ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address  */
+#define PER_BITSET_MEM_BITS       ((uint32_t) 0x20UL)       /**< PER_BITSET used bits  */
+#define PER_MEM_BASE              ((uint32_t) 0x40000000UL) /**< PER base address  */
+#define PER_MEM_SIZE              ((uint32_t) 0xE8000UL)    /**< PER available address space  */
+#define PER_MEM_END               ((uint32_t) 0x400E7FFFUL) /**< PER end address  */
+#define PER_MEM_BITS              ((uint32_t) 0x20UL)       /**< PER used bits  */
+#define RAM_MEM_BASE              ((uint32_t) 0x20000000UL) /**< RAM base address  */
+#define RAM_MEM_SIZE              ((uint32_t) 0x7C00UL)     /**< RAM available address space  */
+#define RAM_MEM_END               ((uint32_t) 0x20007BFFUL) /**< RAM end address  */
+#define RAM_MEM_BITS              ((uint32_t) 0x15UL)       /**< RAM used bits  */
+
+/** Bit banding area */
+#define BITBAND_PER_BASE          ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
+#define BITBAND_RAM_BASE          ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
+
+/** Flash and SRAM limits for EFM32PG1B100F256GM32 */
+#define FLASH_BASE                (0x00000000UL) /**< Flash Base Address */
+#define FLASH_SIZE                (0x00040000UL) /**< Available Flash Memory */
+#define FLASH_PAGE_SIZE           2048           /**< Flash Memory page size */
+#define SRAM_BASE                 (0x20000000UL) /**< SRAM Base Address */
+#define SRAM_SIZE                 (0x00008000UL) /**< Available SRAM Memory */
+#define __CM4_REV                 0x001          /**< Cortex-M4 Core revision r0p1 */
+#define PRS_CHAN_COUNT            12             /**< Number of PRS channels */
+#define DMA_CHAN_COUNT            8              /**< Number of DMA channels */
+
+/** AF channels connect the different on-chip peripherals with the af-mux */
+#define AFCHAN_MAX                72
+#define AFCHANLOC_MAX             32
+/** Analog AF channels */
+#define AFACHAN_MAX               61
+
+/* Part number capabilities */
+
+#define TIMER_PRESENT         /**< TIMER is available in this part */
+#define TIMER_COUNT         2 /**< 2 TIMERs available  */
+#define USART_PRESENT         /**< USART is available in this part */
+#define USART_COUNT         2 /**< 2 USARTs available  */
+#define LEUART_PRESENT        /**< LEUART is available in this part */
+#define LEUART_COUNT        1 /**< 1 LEUARTs available  */
+#define LETIMER_PRESENT       /**< LETIMER is available in this part */
+#define LETIMER_COUNT       1 /**< 1 LETIMERs available  */
+#define PCNT_PRESENT          /**< PCNT is available in this part */
+#define PCNT_COUNT          1 /**< 1 PCNTs available  */
+#define I2C_PRESENT           /**< I2C is available in this part */
+#define I2C_COUNT           1 /**< 1 I2Cs available  */
+#define ADC_PRESENT           /**< ADC is available in this part */
+#define ADC_COUNT           1 /**< 1 ADCs available  */
+#define ACMP_PRESENT          /**< ACMP is available in this part */
+#define ACMP_COUNT          2 /**< 2 ACMPs available  */
+#define IDAC_PRESENT          /**< IDAC is available in this part */
+#define IDAC_COUNT          1 /**< 1 IDACs available  */
+#define WDOG_PRESENT          /**< WDOG is available in this part */
+#define WDOG_COUNT          1 /**< 1 WDOGs available  */
+#define MSC_PRESENT
+#define MSC_COUNT           1
+#define EMU_PRESENT
+#define EMU_COUNT           1
+#define RMU_PRESENT
+#define RMU_COUNT           1
+#define CMU_PRESENT
+#define CMU_COUNT           1
+#define CRYPTO_PRESENT
+#define CRYPTO_COUNT        1
+#define GPIO_PRESENT
+#define GPIO_COUNT          1
+#define PRS_PRESENT
+#define PRS_COUNT           1
+#define LDMA_PRESENT
+#define LDMA_COUNT          1
+#define FPUEH_PRESENT
+#define FPUEH_COUNT         1
+#define GPCRC_PRESENT
+#define GPCRC_COUNT         1
+#define CRYOTIMER_PRESENT
+#define CRYOTIMER_COUNT     1
+#define RTCC_PRESENT
+#define RTCC_COUNT          1
+#define BOOTLOADER_PRESENT
+#define BOOTLOADER_COUNT    1
+
+#include "core_cm4.h"         /* Cortex-M4 processor and core peripherals */
+#include "system_efm32pg1b.h" /* System Header File */
+
+/** @} End of group EFM32PG1B100F256GM32_Part */
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B100F256GM32_Peripheral_TypeDefs EFM32PG1B100F256GM32 Peripheral TypeDefs
+ * @{
+ * @brief Device Specific Peripheral Register Structures
+ *****************************************************************************/
+
+#include "efm32pg1b_msc.h"
+#include "efm32pg1b_emu.h"
+#include "efm32pg1b_rmu.h"
+#include "efm32pg1b_cmu.h"
+#include "efm32pg1b_crypto.h"
+#include "efm32pg1b_gpio_p.h"
+#include "efm32pg1b_gpio.h"
+#include "efm32pg1b_prs_ch.h"
+#include "efm32pg1b_prs.h"
+#include "efm32pg1b_ldma_ch.h"
+#include "efm32pg1b_ldma.h"
+#include "efm32pg1b_fpueh.h"
+#include "efm32pg1b_gpcrc.h"
+#include "efm32pg1b_timer_cc.h"
+#include "efm32pg1b_timer.h"
+#include "efm32pg1b_usart.h"
+#include "efm32pg1b_leuart.h"
+#include "efm32pg1b_letimer.h"
+#include "efm32pg1b_cryotimer.h"
+#include "efm32pg1b_pcnt.h"
+#include "efm32pg1b_i2c.h"
+#include "efm32pg1b_adc.h"
+#include "efm32pg1b_acmp.h"
+#include "efm32pg1b_idac.h"
+#include "efm32pg1b_rtcc_cc.h"
+#include "efm32pg1b_rtcc_ret.h"
+#include "efm32pg1b_rtcc.h"
+#include "efm32pg1b_wdog_pch.h"
+#include "efm32pg1b_wdog.h"
+#include "efm32pg1b_dma_descriptor.h"
+#include "efm32pg1b_devinfo.h"
+#include "efm32pg1b_romtable.h"
+
+/** @} End of group EFM32PG1B100F256GM32_Peripheral_TypeDefs  */
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B100F256GM32_Peripheral_Base EFM32PG1B100F256GM32 Peripheral Memory Map
+ * @{
+ *****************************************************************************/
+
+#define MSC_BASE          (0x400E0000UL) /**< MSC base address  */
+#define EMU_BASE          (0x400E3000UL) /**< EMU base address  */
+#define RMU_BASE          (0x400E5000UL) /**< RMU base address  */
+#define CMU_BASE          (0x400E4000UL) /**< CMU base address  */
+#define CRYPTO_BASE       (0x400F0000UL) /**< CRYPTO base address  */
+#define GPIO_BASE         (0x4000A000UL) /**< GPIO base address  */
+#define PRS_BASE          (0x400E6000UL) /**< PRS base address  */
+#define LDMA_BASE         (0x400E2000UL) /**< LDMA base address  */
+#define FPUEH_BASE        (0x400E1000UL) /**< FPUEH base address  */
+#define GPCRC_BASE        (0x4001C000UL) /**< GPCRC base address  */
+#define TIMER0_BASE       (0x40018000UL) /**< TIMER0 base address  */
+#define TIMER1_BASE       (0x40018400UL) /**< TIMER1 base address  */
+#define USART0_BASE       (0x40010000UL) /**< USART0 base address  */
+#define USART1_BASE       (0x40010400UL) /**< USART1 base address  */
+#define LEUART0_BASE      (0x4004A000UL) /**< LEUART0 base address  */
+#define LETIMER0_BASE     (0x40046000UL) /**< LETIMER0 base address  */
+#define CRYOTIMER_BASE    (0x4001E000UL) /**< CRYOTIMER base address  */
+#define PCNT0_BASE        (0x4004E000UL) /**< PCNT0 base address  */
+#define I2C0_BASE         (0x4000C000UL) /**< I2C0 base address  */
+#define ADC0_BASE         (0x40002000UL) /**< ADC0 base address  */
+#define ACMP0_BASE        (0x40000000UL) /**< ACMP0 base address  */
+#define ACMP1_BASE        (0x40000400UL) /**< ACMP1 base address  */
+#define IDAC0_BASE        (0x40006000UL) /**< IDAC0 base address  */
+#define RTCC_BASE         (0x40042000UL) /**< RTCC base address  */
+#define WDOG0_BASE        (0x40052000UL) /**< WDOG0 base address  */
+#define DEVINFO_BASE      (0x0FE081B0UL) /**< DEVINFO base address */
+#define ROMTABLE_BASE     (0xE00FFFD0UL) /**< ROMTABLE base address */
+#define LOCKBITS_BASE     (0x0FE04000UL) /**< Lock-bits page base address */
+#define USERDATA_BASE     (0x0FE00000UL) /**< User data page base address */
+
+/** @} End of group EFM32PG1B100F256GM32_Peripheral_Base */
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B100F256GM32_Peripheral_Declaration  EFM32PG1B100F256GM32 Peripheral Declarations
+ * @{
+ *****************************************************************************/
+
+#define MSC          ((MSC_TypeDef *) MSC_BASE)             /**< MSC base pointer */
+#define EMU          ((EMU_TypeDef *) EMU_BASE)             /**< EMU base pointer */
+#define RMU          ((RMU_TypeDef *) RMU_BASE)             /**< RMU base pointer */
+#define CMU          ((CMU_TypeDef *) CMU_BASE)             /**< CMU base pointer */
+#define CRYPTO       ((CRYPTO_TypeDef *) CRYPTO_BASE)       /**< CRYPTO base pointer */
+#define GPIO         ((GPIO_TypeDef *) GPIO_BASE)           /**< GPIO base pointer */
+#define PRS          ((PRS_TypeDef *) PRS_BASE)             /**< PRS base pointer */
+#define LDMA         ((LDMA_TypeDef *) LDMA_BASE)           /**< LDMA base pointer */
+#define FPUEH        ((FPUEH_TypeDef *) FPUEH_BASE)         /**< FPUEH base pointer */
+#define GPCRC        ((GPCRC_TypeDef *) GPCRC_BASE)         /**< GPCRC base pointer */
+#define TIMER0       ((TIMER_TypeDef *) TIMER0_BASE)        /**< TIMER0 base pointer */
+#define TIMER1       ((TIMER_TypeDef *) TIMER1_BASE)        /**< TIMER1 base pointer */
+#define USART0       ((USART_TypeDef *) USART0_BASE)        /**< USART0 base pointer */
+#define USART1       ((USART_TypeDef *) USART1_BASE)        /**< USART1 base pointer */
+#define LEUART0      ((LEUART_TypeDef *) LEUART0_BASE)      /**< LEUART0 base pointer */
+#define LETIMER0     ((LETIMER_TypeDef *) LETIMER0_BASE)    /**< LETIMER0 base pointer */
+#define CRYOTIMER    ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */
+#define PCNT0        ((PCNT_TypeDef *) PCNT0_BASE)          /**< PCNT0 base pointer */
+#define I2C0         ((I2C_TypeDef *) I2C0_BASE)            /**< I2C0 base pointer */
+#define ADC0         ((ADC_TypeDef *) ADC0_BASE)            /**< ADC0 base pointer */
+#define ACMP0        ((ACMP_TypeDef *) ACMP0_BASE)          /**< ACMP0 base pointer */
+#define ACMP1        ((ACMP_TypeDef *) ACMP1_BASE)          /**< ACMP1 base pointer */
+#define IDAC0        ((IDAC_TypeDef *) IDAC0_BASE)          /**< IDAC0 base pointer */
+#define RTCC         ((RTCC_TypeDef *) RTCC_BASE)           /**< RTCC base pointer */
+#define WDOG0        ((WDOG_TypeDef *) WDOG0_BASE)          /**< WDOG0 base pointer */
+#define DEVINFO      ((DEVINFO_TypeDef *) DEVINFO_BASE)     /**< DEVINFO base pointer */
+#define ROMTABLE     ((ROMTABLE_TypeDef *) ROMTABLE_BASE)   /**< ROMTABLE base pointer */
+
+/** @} End of group EFM32PG1B100F256GM32_Peripheral_Declaration */
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B100F256GM32_Peripheral_Offsets  EFM32PG1B100F256GM32 Peripheral Offsets
+ * @{
+ *****************************************************************************/
+
+#define TIMER_OFFSET      0x400 /**< Offset in bytes between TIMER instances */
+#define USART_OFFSET      0x400 /**< Offset in bytes between USART instances */
+#define LEUART_OFFSET     0x400 /**< Offset in bytes between LEUART instances */
+#define LETIMER_OFFSET    0x400 /**< Offset in bytes between LETIMER instances */
+#define PCNT_OFFSET       0x400 /**< Offset in bytes between PCNT instances */
+#define I2C_OFFSET        0x400 /**< Offset in bytes between I2C instances */
+#define ADC_OFFSET        0x400 /**< Offset in bytes between ADC instances */
+#define ACMP_OFFSET       0x400 /**< Offset in bytes between ACMP instances */
+#define IDAC_OFFSET       0x400 /**< Offset in bytes between IDAC instances */
+#define WDOG_OFFSET       0x400 /**< Offset in bytes between WDOG instances */
+
+/** @} End of group EFM32PG1B100F256GM32_Peripheral_Offsets */
+
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B100F256GM32_BitFields EFM32PG1B100F256GM32 Bit Fields
+ * @{
+ *****************************************************************************/
+
+#include "efm32pg1b_prs_signals.h"
+#include "efm32pg1b_dmareq.h"
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B100F256GM32_UNLOCK EFM32PG1B100F256GM32 Unlock Codes
+ * @{
+ *****************************************************************************/
+#define MSC_UNLOCK_CODE      0x1B71 /**< MSC unlock code */
+#define EMU_UNLOCK_CODE      0xADE8 /**< EMU unlock code */
+#define RMU_UNLOCK_CODE      0xE084 /**< RMU unlock code */
+#define CMU_UNLOCK_CODE      0x580E /**< CMU unlock code */
+#define GPIO_UNLOCK_CODE     0xA534 /**< GPIO unlock code */
+#define TIMER_UNLOCK_CODE    0xCE80 /**< TIMER unlock code */
+#define RTCC_UNLOCK_CODE     0xAEE8 /**< RTCC unlock code */
+
+/** @} End of group EFM32PG1B100F256GM32_UNLOCK */
+
+/** @} End of group EFM32PG1B100F256GM32_BitFields */
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B100F256GM32_Alternate_Function EFM32PG1B100F256GM32 Alternate Function
+ * @{
+ *****************************************************************************/
+
+#include "efm32pg1b_af_ports.h"
+#include "efm32pg1b_af_pins.h"
+
+/** @} End of group EFM32PG1B100F256GM32_Alternate_Function */
+
+/**************************************************************************//**
+ *  @brief Set the value of a bit field within a register.
+ *
+ *  @param REG
+ *       The register to update
+ *  @param MASK
+ *       The mask for the bit field to update
+ *  @param VALUE
+ *       The value to write to the bit field
+ *  @param OFFSET
+ *       The number of bits that the field is offset within the register.
+ *       0 (zero) means LSB.
+ *****************************************************************************/
+#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
+  REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
+
+/** @} End of group EFM32PG1B100F256GM32 */
+
+/** @} End of group Parts */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* SILICON_LABS_EFM32PG1B100F256GM32_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG_STK3401/efm32pg1b200f128gm32.h	Fri Jan 15 07:45:16 2016 +0000
@@ -0,0 +1,425 @@
+/**************************************************************************//**
+ * @file efm32pg1b200f128gm32.h
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File
+ *        for EFM32PG1B200F128GM32
+ * @version 4.2.0
+ ******************************************************************************
+ * @section License
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ ******************************************************************************
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software.@n
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.@n
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is
+ * providing the Software "AS IS", with no express or implied warranties of any
+ * kind, including, but not limited to, any implied warranties of
+ * merchantability or fitness for any particular purpose or warranties against
+ * infringement of any proprietary rights of a third party.
+ *
+ * Silicon Laboratories, Inc. will not be liable for any consequential,
+ * incidental, or special damages, or any other relief, or for any claim by
+ * any third party, arising from your use of this Software.
+ *
+ *****************************************************************************/
+
+#ifndef SILICON_LABS_EFM32PG1B200F128GM32_H
+#define SILICON_LABS_EFM32PG1B200F128GM32_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ *****************************************************************************/
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B200F128GM32 EFM32PG1B200F128GM32
+ * @{
+ *****************************************************************************/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M4 Processor Exceptions Numbers *******************************************/
+  NonMaskableInt_IRQn   = -14,              /*!< 2  Cortex-M4 Non Maskable Interrupt      */
+  HardFault_IRQn        = -13,              /*!< 3  Cortex-M4 Hard Fault Interrupt        */
+  MemoryManagement_IRQn = -12,              /*!< 4  Cortex-M4 Memory Management Interrupt */
+  BusFault_IRQn         = -11,              /*!< 5  Cortex-M4 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10,              /*!< 6  Cortex-M4 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,               /*!< 11 Cortex-M4 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,               /*!< 12 Cortex-M4 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,               /*!< 14 Cortex-M4 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,               /*!< 15 Cortex-M4 System Tick Interrupt       */
+
+/******  EFM32PG1B Peripheral Interrupt Numbers *********************************************/
+
+  EMU_IRQn              = 0,  /*!< 16+0 EFM32 EMU Interrupt */
+  WDOG0_IRQn            = 2,  /*!< 16+2 EFM32 WDOG0 Interrupt */
+  LDMA_IRQn             = 8,  /*!< 16+8 EFM32 LDMA Interrupt */
+  GPIO_EVEN_IRQn        = 9,  /*!< 16+9 EFM32 GPIO_EVEN Interrupt */
+  TIMER0_IRQn           = 10, /*!< 16+10 EFM32 TIMER0 Interrupt */
+  USART0_RX_IRQn        = 11, /*!< 16+11 EFM32 USART0_RX Interrupt */
+  USART0_TX_IRQn        = 12, /*!< 16+12 EFM32 USART0_TX Interrupt */
+  ACMP0_IRQn            = 13, /*!< 16+13 EFM32 ACMP0 Interrupt */
+  ADC0_IRQn             = 14, /*!< 16+14 EFM32 ADC0 Interrupt */
+  IDAC0_IRQn            = 15, /*!< 16+15 EFM32 IDAC0 Interrupt */
+  I2C0_IRQn             = 16, /*!< 16+16 EFM32 I2C0 Interrupt */
+  GPIO_ODD_IRQn         = 17, /*!< 16+17 EFM32 GPIO_ODD Interrupt */
+  TIMER1_IRQn           = 18, /*!< 16+18 EFM32 TIMER1 Interrupt */
+  USART1_RX_IRQn        = 19, /*!< 16+19 EFM32 USART1_RX Interrupt */
+  USART1_TX_IRQn        = 20, /*!< 16+20 EFM32 USART1_TX Interrupt */
+  LEUART0_IRQn          = 21, /*!< 16+21 EFM32 LEUART0 Interrupt */
+  PCNT0_IRQn            = 22, /*!< 16+22 EFM32 PCNT0 Interrupt */
+  CMU_IRQn              = 23, /*!< 16+23 EFM32 CMU Interrupt */
+  MSC_IRQn              = 24, /*!< 16+24 EFM32 MSC Interrupt */
+  CRYPTO_IRQn           = 25, /*!< 16+25 EFM32 CRYPTO Interrupt */
+  LETIMER0_IRQn         = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */
+  RTCC_IRQn             = 29, /*!< 16+29 EFM32 RTCC Interrupt */
+  CRYOTIMER_IRQn        = 31, /*!< 16+31 EFM32 CRYOTIMER Interrupt */
+  FPUEH_IRQn            = 33, /*!< 16+33 EFM32 FPUEH Interrupt */
+} IRQn_Type;
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B200F128GM32_Core EFM32PG1B200F128GM32 Core
+ * @{
+ * @brief Processor and Core Peripheral Section
+ *****************************************************************************/
+#define __MPU_PRESENT             1 /**< Presence of MPU  */
+#define __FPU_PRESENT             1 /**< Presence of FPU  */
+#define __NVIC_PRIO_BITS          3 /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig    0 /**< Is 1 if different SysTick counter is used */
+
+/** @} End of group EFM32PG1B200F128GM32_Core */
+
+/**************************************************************************//**
+* @defgroup EFM32PG1B200F128GM32_Part EFM32PG1B200F128GM32 Part
+* @{
+******************************************************************************/
+
+/** Part family */
+#define _EFM32_PEARL_FAMILY             1 /**< PEARL Gecko MCU Family  */
+#define _EFM_DEVICE                       /**< Silicon Labs EFM-type microcontroller */
+#define _SILICON_LABS_32B_PLATFORM_2      /**< Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM      2 /**< Silicon Labs platform name */
+
+/* If part number is not defined as compiler option, define it */
+#if !defined(EFM32PG1B200F128GM32)
+#define EFM32PG1B200F128GM32    1 /**< PEARL Gecko Part */
+#endif
+
+/** Configure part number */
+#define PART_NUMBER               "EFM32PG1B200F128GM32" /**< Part Number */
+
+/** Memory Base addresses and limits */
+#define FLASH_MEM_BASE            ((uint32_t) 0x00000000UL) /**< FLASH base address  */
+#define FLASH_MEM_SIZE            ((uint32_t) 0x10000000UL) /**< FLASH available address space  */
+#define FLASH_MEM_END             ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address  */
+#define FLASH_MEM_BITS            ((uint32_t) 0x28UL)       /**< FLASH used bits  */
+#define RAM_CODE_MEM_BASE         ((uint32_t) 0x10000000UL) /**< RAM_CODE base address  */
+#define RAM_CODE_MEM_SIZE         ((uint32_t) 0x7C00UL)     /**< RAM_CODE available address space  */
+#define RAM_CODE_MEM_END          ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address  */
+#define RAM_CODE_MEM_BITS         ((uint32_t) 0x15UL)       /**< RAM_CODE used bits  */
+#define PER_BITCLR_MEM_BASE       ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address  */
+#define PER_BITCLR_MEM_SIZE       ((uint32_t) 0xE8000UL)    /**< PER_BITCLR available address space  */
+#define PER_BITCLR_MEM_END        ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address  */
+#define PER_BITCLR_MEM_BITS       ((uint32_t) 0x20UL)       /**< PER_BITCLR used bits  */
+#define CRYPTO_BITSET_MEM_BASE    ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address  */
+#define CRYPTO_BITSET_MEM_SIZE    ((uint32_t) 0x400UL)      /**< CRYPTO_BITSET available address space  */
+#define CRYPTO_BITSET_MEM_END     ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address  */
+#define CRYPTO_BITSET_MEM_BITS    ((uint32_t) 0x10UL)       /**< CRYPTO_BITSET used bits  */
+#define CRYPTO_MEM_BASE           ((uint32_t) 0x400F0000UL) /**< CRYPTO base address  */
+#define CRYPTO_MEM_SIZE           ((uint32_t) 0x400UL)      /**< CRYPTO available address space  */
+#define CRYPTO_MEM_END            ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address  */
+#define CRYPTO_MEM_BITS           ((uint32_t) 0x10UL)       /**< CRYPTO used bits  */
+#define CRYPTO_BITCLR_MEM_BASE    ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address  */
+#define CRYPTO_BITCLR_MEM_SIZE    ((uint32_t) 0x400UL)      /**< CRYPTO_BITCLR available address space  */
+#define CRYPTO_BITCLR_MEM_END     ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address  */
+#define CRYPTO_BITCLR_MEM_BITS    ((uint32_t) 0x10UL)       /**< CRYPTO_BITCLR used bits  */
+#define PER_BITSET_MEM_BASE       ((uint32_t) 0x46000000UL) /**< PER_BITSET base address  */
+#define PER_BITSET_MEM_SIZE       ((uint32_t) 0xE8000UL)    /**< PER_BITSET available address space  */
+#define PER_BITSET_MEM_END        ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address  */
+#define PER_BITSET_MEM_BITS       ((uint32_t) 0x20UL)       /**< PER_BITSET used bits  */
+#define PER_MEM_BASE              ((uint32_t) 0x40000000UL) /**< PER base address  */
+#define PER_MEM_SIZE              ((uint32_t) 0xE8000UL)    /**< PER available address space  */
+#define PER_MEM_END               ((uint32_t) 0x400E7FFFUL) /**< PER end address  */
+#define PER_MEM_BITS              ((uint32_t) 0x20UL)       /**< PER used bits  */
+#define RAM_MEM_BASE              ((uint32_t) 0x20000000UL) /**< RAM base address  */
+#define RAM_MEM_SIZE              ((uint32_t) 0x7C00UL)     /**< RAM available address space  */
+#define RAM_MEM_END               ((uint32_t) 0x20007BFFUL) /**< RAM end address  */
+#define RAM_MEM_BITS              ((uint32_t) 0x15UL)       /**< RAM used bits  */
+
+/** Bit banding area */
+#define BITBAND_PER_BASE          ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
+#define BITBAND_RAM_BASE          ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
+
+/** Flash and SRAM limits for EFM32PG1B200F128GM32 */
+#define FLASH_BASE                (0x00000000UL) /**< Flash Base Address */
+#define FLASH_SIZE                (0x00020000UL) /**< Available Flash Memory */
+#define FLASH_PAGE_SIZE           2048           /**< Flash Memory page size */
+#define SRAM_BASE                 (0x20000000UL) /**< SRAM Base Address */
+#define SRAM_SIZE                 (0x00008000UL) /**< Available SRAM Memory */
+#define __CM4_REV                 0x001          /**< Cortex-M4 Core revision r0p1 */
+#define PRS_CHAN_COUNT            12             /**< Number of PRS channels */
+#define DMA_CHAN_COUNT            8              /**< Number of DMA channels */
+
+/** AF channels connect the different on-chip peripherals with the af-mux */
+#define AFCHAN_MAX                72
+#define AFCHANLOC_MAX             32
+/** Analog AF channels */
+#define AFACHAN_MAX               61
+
+/* Part number capabilities */
+
+#define TIMER_PRESENT         /**< TIMER is available in this part */
+#define TIMER_COUNT         2 /**< 2 TIMERs available  */
+#define USART_PRESENT         /**< USART is available in this part */
+#define USART_COUNT         2 /**< 2 USARTs available  */
+#define LEUART_PRESENT        /**< LEUART is available in this part */
+#define LEUART_COUNT        1 /**< 1 LEUARTs available  */
+#define LETIMER_PRESENT       /**< LETIMER is available in this part */
+#define LETIMER_COUNT       1 /**< 1 LETIMERs available  */
+#define PCNT_PRESENT          /**< PCNT is available in this part */
+#define PCNT_COUNT          1 /**< 1 PCNTs available  */
+#define I2C_PRESENT           /**< I2C is available in this part */
+#define I2C_COUNT           1 /**< 1 I2Cs available  */
+#define ADC_PRESENT           /**< ADC is available in this part */
+#define ADC_COUNT           1 /**< 1 ADCs available  */
+#define ACMP_PRESENT          /**< ACMP is available in this part */
+#define ACMP_COUNT          2 /**< 2 ACMPs available  */
+#define IDAC_PRESENT          /**< IDAC is available in this part */
+#define IDAC_COUNT          1 /**< 1 IDACs available  */
+#define WDOG_PRESENT          /**< WDOG is available in this part */
+#define WDOG_COUNT          1 /**< 1 WDOGs available  */
+#define MSC_PRESENT
+#define MSC_COUNT           1
+#define EMU_PRESENT
+#define EMU_COUNT           1
+#define RMU_PRESENT
+#define RMU_COUNT           1
+#define CMU_PRESENT
+#define CMU_COUNT           1
+#define CRYPTO_PRESENT
+#define CRYPTO_COUNT        1
+#define GPIO_PRESENT
+#define GPIO_COUNT          1
+#define PRS_PRESENT
+#define PRS_COUNT           1
+#define LDMA_PRESENT
+#define LDMA_COUNT          1
+#define FPUEH_PRESENT
+#define FPUEH_COUNT         1
+#define GPCRC_PRESENT
+#define GPCRC_COUNT         1
+#define CRYOTIMER_PRESENT
+#define CRYOTIMER_COUNT     1
+#define RTCC_PRESENT
+#define RTCC_COUNT          1
+#define BOOTLOADER_PRESENT
+#define BOOTLOADER_COUNT    1
+
+#include "core_cm4.h"         /* Cortex-M4 processor and core peripherals */
+#include "system_efm32pg1b.h" /* System Header File */
+
+/** @} End of group EFM32PG1B200F128GM32_Part */
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B200F128GM32_Peripheral_TypeDefs EFM32PG1B200F128GM32 Peripheral TypeDefs
+ * @{
+ * @brief Device Specific Peripheral Register Structures
+ *****************************************************************************/
+
+#include "efm32pg1b_msc.h"
+#include "efm32pg1b_emu.h"
+#include "efm32pg1b_rmu.h"
+#include "efm32pg1b_cmu.h"
+#include "efm32pg1b_crypto.h"
+#include "efm32pg1b_gpio_p.h"
+#include "efm32pg1b_gpio.h"
+#include "efm32pg1b_prs_ch.h"
+#include "efm32pg1b_prs.h"
+#include "efm32pg1b_ldma_ch.h"
+#include "efm32pg1b_ldma.h"
+#include "efm32pg1b_fpueh.h"
+#include "efm32pg1b_gpcrc.h"
+#include "efm32pg1b_timer_cc.h"
+#include "efm32pg1b_timer.h"
+#include "efm32pg1b_usart.h"
+#include "efm32pg1b_leuart.h"
+#include "efm32pg1b_letimer.h"
+#include "efm32pg1b_cryotimer.h"
+#include "efm32pg1b_pcnt.h"
+#include "efm32pg1b_i2c.h"
+#include "efm32pg1b_adc.h"
+#include "efm32pg1b_acmp.h"
+#include "efm32pg1b_idac.h"
+#include "efm32pg1b_rtcc_cc.h"
+#include "efm32pg1b_rtcc_ret.h"
+#include "efm32pg1b_rtcc.h"
+#include "efm32pg1b_wdog_pch.h"
+#include "efm32pg1b_wdog.h"
+#include "efm32pg1b_dma_descriptor.h"
+#include "efm32pg1b_devinfo.h"
+#include "efm32pg1b_romtable.h"
+
+/** @} End of group EFM32PG1B200F128GM32_Peripheral_TypeDefs  */
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B200F128GM32_Peripheral_Base EFM32PG1B200F128GM32 Peripheral Memory Map
+ * @{
+ *****************************************************************************/
+
+#define MSC_BASE          (0x400E0000UL) /**< MSC base address  */
+#define EMU_BASE          (0x400E3000UL) /**< EMU base address  */
+#define RMU_BASE          (0x400E5000UL) /**< RMU base address  */
+#define CMU_BASE          (0x400E4000UL) /**< CMU base address  */
+#define CRYPTO_BASE       (0x400F0000UL) /**< CRYPTO base address  */
+#define GPIO_BASE         (0x4000A000UL) /**< GPIO base address  */
+#define PRS_BASE          (0x400E6000UL) /**< PRS base address  */
+#define LDMA_BASE         (0x400E2000UL) /**< LDMA base address  */
+#define FPUEH_BASE        (0x400E1000UL) /**< FPUEH base address  */
+#define GPCRC_BASE        (0x4001C000UL) /**< GPCRC base address  */
+#define TIMER0_BASE       (0x40018000UL) /**< TIMER0 base address  */
+#define TIMER1_BASE       (0x40018400UL) /**< TIMER1 base address  */
+#define USART0_BASE       (0x40010000UL) /**< USART0 base address  */
+#define USART1_BASE       (0x40010400UL) /**< USART1 base address  */
+#define LEUART0_BASE      (0x4004A000UL) /**< LEUART0 base address  */
+#define LETIMER0_BASE     (0x40046000UL) /**< LETIMER0 base address  */
+#define CRYOTIMER_BASE    (0x4001E000UL) /**< CRYOTIMER base address  */
+#define PCNT0_BASE        (0x4004E000UL) /**< PCNT0 base address  */
+#define I2C0_BASE         (0x4000C000UL) /**< I2C0 base address  */
+#define ADC0_BASE         (0x40002000UL) /**< ADC0 base address  */
+#define ACMP0_BASE        (0x40000000UL) /**< ACMP0 base address  */
+#define ACMP1_BASE        (0x40000400UL) /**< ACMP1 base address  */
+#define IDAC0_BASE        (0x40006000UL) /**< IDAC0 base address  */
+#define RTCC_BASE         (0x40042000UL) /**< RTCC base address  */
+#define WDOG0_BASE        (0x40052000UL) /**< WDOG0 base address  */
+#define DEVINFO_BASE      (0x0FE081B0UL) /**< DEVINFO base address */
+#define ROMTABLE_BASE     (0xE00FFFD0UL) /**< ROMTABLE base address */
+#define LOCKBITS_BASE     (0x0FE04000UL) /**< Lock-bits page base address */
+#define USERDATA_BASE     (0x0FE00000UL) /**< User data page base address */
+
+/** @} End of group EFM32PG1B200F128GM32_Peripheral_Base */
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B200F128GM32_Peripheral_Declaration  EFM32PG1B200F128GM32 Peripheral Declarations
+ * @{
+ *****************************************************************************/
+
+#define MSC          ((MSC_TypeDef *) MSC_BASE)             /**< MSC base pointer */
+#define EMU          ((EMU_TypeDef *) EMU_BASE)             /**< EMU base pointer */
+#define RMU          ((RMU_TypeDef *) RMU_BASE)             /**< RMU base pointer */
+#define CMU          ((CMU_TypeDef *) CMU_BASE)             /**< CMU base pointer */
+#define CRYPTO       ((CRYPTO_TypeDef *) CRYPTO_BASE)       /**< CRYPTO base pointer */
+#define GPIO         ((GPIO_TypeDef *) GPIO_BASE)           /**< GPIO base pointer */
+#define PRS          ((PRS_TypeDef *) PRS_BASE)             /**< PRS base pointer */
+#define LDMA         ((LDMA_TypeDef *) LDMA_BASE)           /**< LDMA base pointer */
+#define FPUEH        ((FPUEH_TypeDef *) FPUEH_BASE)         /**< FPUEH base pointer */
+#define GPCRC        ((GPCRC_TypeDef *) GPCRC_BASE)         /**< GPCRC base pointer */
+#define TIMER0       ((TIMER_TypeDef *) TIMER0_BASE)        /**< TIMER0 base pointer */
+#define TIMER1       ((TIMER_TypeDef *) TIMER1_BASE)        /**< TIMER1 base pointer */
+#define USART0       ((USART_TypeDef *) USART0_BASE)        /**< USART0 base pointer */
+#define USART1       ((USART_TypeDef *) USART1_BASE)        /**< USART1 base pointer */
+#define LEUART0      ((LEUART_TypeDef *) LEUART0_BASE)      /**< LEUART0 base pointer */
+#define LETIMER0     ((LETIMER_TypeDef *) LETIMER0_BASE)    /**< LETIMER0 base pointer */
+#define CRYOTIMER    ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */
+#define PCNT0        ((PCNT_TypeDef *) PCNT0_BASE)          /**< PCNT0 base pointer */
+#define I2C0         ((I2C_TypeDef *) I2C0_BASE)            /**< I2C0 base pointer */
+#define ADC0         ((ADC_TypeDef *) ADC0_BASE)            /**< ADC0 base pointer */
+#define ACMP0        ((ACMP_TypeDef *) ACMP0_BASE)          /**< ACMP0 base pointer */
+#define ACMP1        ((ACMP_TypeDef *) ACMP1_BASE)          /**< ACMP1 base pointer */
+#define IDAC0        ((IDAC_TypeDef *) IDAC0_BASE)          /**< IDAC0 base pointer */
+#define RTCC         ((RTCC_TypeDef *) RTCC_BASE)           /**< RTCC base pointer */
+#define WDOG0        ((WDOG_TypeDef *) WDOG0_BASE)          /**< WDOG0 base pointer */
+#define DEVINFO      ((DEVINFO_TypeDef *) DEVINFO_BASE)     /**< DEVINFO base pointer */
+#define ROMTABLE     ((ROMTABLE_TypeDef *) ROMTABLE_BASE)   /**< ROMTABLE base pointer */
+
+/** @} End of group EFM32PG1B200F128GM32_Peripheral_Declaration */
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B200F128GM32_Peripheral_Offsets  EFM32PG1B200F128GM32 Peripheral Offsets
+ * @{
+ *****************************************************************************/
+
+#define TIMER_OFFSET      0x400 /**< Offset in bytes between TIMER instances */
+#define USART_OFFSET      0x400 /**< Offset in bytes between USART instances */
+#define LEUART_OFFSET     0x400 /**< Offset in bytes between LEUART instances */
+#define LETIMER_OFFSET    0x400 /**< Offset in bytes between LETIMER instances */
+#define PCNT_OFFSET       0x400 /**< Offset in bytes between PCNT instances */
+#define I2C_OFFSET        0x400 /**< Offset in bytes between I2C instances */
+#define ADC_OFFSET        0x400 /**< Offset in bytes between ADC instances */
+#define ACMP_OFFSET       0x400 /**< Offset in bytes between ACMP instances */
+#define IDAC_OFFSET       0x400 /**< Offset in bytes between IDAC instances */
+#define WDOG_OFFSET       0x400 /**< Offset in bytes between WDOG instances */
+
+/** @} End of group EFM32PG1B200F128GM32_Peripheral_Offsets */
+
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B200F128GM32_BitFields EFM32PG1B200F128GM32 Bit Fields
+ * @{
+ *****************************************************************************/
+
+#include "efm32pg1b_prs_signals.h"
+#include "efm32pg1b_dmareq.h"
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B200F128GM32_UNLOCK EFM32PG1B200F128GM32 Unlock Codes
+ * @{
+ *****************************************************************************/
+#define MSC_UNLOCK_CODE      0x1B71 /**< MSC unlock code */
+#define EMU_UNLOCK_CODE      0xADE8 /**< EMU unlock code */
+#define RMU_UNLOCK_CODE      0xE084 /**< RMU unlock code */
+#define CMU_UNLOCK_CODE      0x580E /**< CMU unlock code */
+#define GPIO_UNLOCK_CODE     0xA534 /**< GPIO unlock code */
+#define TIMER_UNLOCK_CODE    0xCE80 /**< TIMER unlock code */
+#define RTCC_UNLOCK_CODE     0xAEE8 /**< RTCC unlock code */
+
+/** @} End of group EFM32PG1B200F128GM32_UNLOCK */
+
+/** @} End of group EFM32PG1B200F128GM32_BitFields */
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B200F128GM32_Alternate_Function EFM32PG1B200F128GM32 Alternate Function
+ * @{
+ *****************************************************************************/
+
+#include "efm32pg1b_af_ports.h"
+#include "efm32pg1b_af_pins.h"
+
+/** @} End of group EFM32PG1B200F128GM32_Alternate_Function */
+
+/**************************************************************************//**
+ *  @brief Set the value of a bit field within a register.
+ *
+ *  @param REG
+ *       The register to update
+ *  @param MASK
+ *       The mask for the bit field to update
+ *  @param VALUE
+ *       The value to write to the bit field
+ *  @param OFFSET
+ *       The number of bits that the field is offset within the register.
+ *       0 (zero) means LSB.
+ *****************************************************************************/
+#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
+  REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
+
+/** @} End of group EFM32PG1B200F128GM32 */
+
+/** @} End of group Parts */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* SILICON_LABS_EFM32PG1B200F128GM32_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG_STK3401/efm32pg1b200f128gm48.h	Fri Jan 15 07:45:16 2016 +0000
@@ -0,0 +1,425 @@
+/**************************************************************************//**
+ * @file efm32pg1b200f128gm48.h
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File
+ *        for EFM32PG1B200F128GM48
+ * @version 4.2.0
+ ******************************************************************************
+ * @section License
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ ******************************************************************************
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software.@n
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.@n
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is
+ * providing the Software "AS IS", with no express or implied warranties of any
+ * kind, including, but not limited to, any implied warranties of
+ * merchantability or fitness for any particular purpose or warranties against
+ * infringement of any proprietary rights of a third party.
+ *
+ * Silicon Laboratories, Inc. will not be liable for any consequential,
+ * incidental, or special damages, or any other relief, or for any claim by
+ * any third party, arising from your use of this Software.
+ *
+ *****************************************************************************/
+
+#ifndef SILICON_LABS_EFM32PG1B200F128GM48_H
+#define SILICON_LABS_EFM32PG1B200F128GM48_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ *****************************************************************************/
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B200F128GM48 EFM32PG1B200F128GM48
+ * @{
+ *****************************************************************************/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M4 Processor Exceptions Numbers *******************************************/
+  NonMaskableInt_IRQn   = -14,              /*!< 2  Cortex-M4 Non Maskable Interrupt      */
+  HardFault_IRQn        = -13,              /*!< 3  Cortex-M4 Hard Fault Interrupt        */
+  MemoryManagement_IRQn = -12,              /*!< 4  Cortex-M4 Memory Management Interrupt */
+  BusFault_IRQn         = -11,              /*!< 5  Cortex-M4 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10,              /*!< 6  Cortex-M4 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,               /*!< 11 Cortex-M4 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,               /*!< 12 Cortex-M4 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,               /*!< 14 Cortex-M4 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,               /*!< 15 Cortex-M4 System Tick Interrupt       */
+
+/******  EFM32PG1B Peripheral Interrupt Numbers *********************************************/
+
+  EMU_IRQn              = 0,  /*!< 16+0 EFM32 EMU Interrupt */
+  WDOG0_IRQn            = 2,  /*!< 16+2 EFM32 WDOG0 Interrupt */
+  LDMA_IRQn             = 8,  /*!< 16+8 EFM32 LDMA Interrupt */
+  GPIO_EVEN_IRQn        = 9,  /*!< 16+9 EFM32 GPIO_EVEN Interrupt */
+  TIMER0_IRQn           = 10, /*!< 16+10 EFM32 TIMER0 Interrupt */
+  USART0_RX_IRQn        = 11, /*!< 16+11 EFM32 USART0_RX Interrupt */
+  USART0_TX_IRQn        = 12, /*!< 16+12 EFM32 USART0_TX Interrupt */
+  ACMP0_IRQn            = 13, /*!< 16+13 EFM32 ACMP0 Interrupt */
+  ADC0_IRQn             = 14, /*!< 16+14 EFM32 ADC0 Interrupt */
+  IDAC0_IRQn            = 15, /*!< 16+15 EFM32 IDAC0 Interrupt */
+  I2C0_IRQn             = 16, /*!< 16+16 EFM32 I2C0 Interrupt */
+  GPIO_ODD_IRQn         = 17, /*!< 16+17 EFM32 GPIO_ODD Interrupt */
+  TIMER1_IRQn           = 18, /*!< 16+18 EFM32 TIMER1 Interrupt */
+  USART1_RX_IRQn        = 19, /*!< 16+19 EFM32 USART1_RX Interrupt */
+  USART1_TX_IRQn        = 20, /*!< 16+20 EFM32 USART1_TX Interrupt */
+  LEUART0_IRQn          = 21, /*!< 16+21 EFM32 LEUART0 Interrupt */
+  PCNT0_IRQn            = 22, /*!< 16+22 EFM32 PCNT0 Interrupt */
+  CMU_IRQn              = 23, /*!< 16+23 EFM32 CMU Interrupt */
+  MSC_IRQn              = 24, /*!< 16+24 EFM32 MSC Interrupt */
+  CRYPTO_IRQn           = 25, /*!< 16+25 EFM32 CRYPTO Interrupt */
+  LETIMER0_IRQn         = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */
+  RTCC_IRQn             = 29, /*!< 16+29 EFM32 RTCC Interrupt */
+  CRYOTIMER_IRQn        = 31, /*!< 16+31 EFM32 CRYOTIMER Interrupt */
+  FPUEH_IRQn            = 33, /*!< 16+33 EFM32 FPUEH Interrupt */
+} IRQn_Type;
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B200F128GM48_Core EFM32PG1B200F128GM48 Core
+ * @{
+ * @brief Processor and Core Peripheral Section
+ *****************************************************************************/
+#define __MPU_PRESENT             1 /**< Presence of MPU  */
+#define __FPU_PRESENT             1 /**< Presence of FPU  */
+#define __NVIC_PRIO_BITS          3 /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig    0 /**< Is 1 if different SysTick counter is used */
+
+/** @} End of group EFM32PG1B200F128GM48_Core */
+
+/**************************************************************************//**
+* @defgroup EFM32PG1B200F128GM48_Part EFM32PG1B200F128GM48 Part
+* @{
+******************************************************************************/
+
+/** Part family */
+#define _EFM32_PEARL_FAMILY             1 /**< PEARL Gecko MCU Family  */
+#define _EFM_DEVICE                       /**< Silicon Labs EFM-type microcontroller */
+#define _SILICON_LABS_32B_PLATFORM_2      /**< Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM      2 /**< Silicon Labs platform name */
+
+/* If part number is not defined as compiler option, define it */
+#if !defined(EFM32PG1B200F128GM48)
+#define EFM32PG1B200F128GM48    1 /**< PEARL Gecko Part */
+#endif
+
+/** Configure part number */
+#define PART_NUMBER               "EFM32PG1B200F128GM48" /**< Part Number */
+
+/** Memory Base addresses and limits */
+#define FLASH_MEM_BASE            ((uint32_t) 0x00000000UL) /**< FLASH base address  */
+#define FLASH_MEM_SIZE            ((uint32_t) 0x10000000UL) /**< FLASH available address space  */
+#define FLASH_MEM_END             ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address  */
+#define FLASH_MEM_BITS            ((uint32_t) 0x28UL)       /**< FLASH used bits  */
+#define RAM_CODE_MEM_BASE         ((uint32_t) 0x10000000UL) /**< RAM_CODE base address  */
+#define RAM_CODE_MEM_SIZE         ((uint32_t) 0x7C00UL)     /**< RAM_CODE available address space  */
+#define RAM_CODE_MEM_END          ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address  */
+#define RAM_CODE_MEM_BITS         ((uint32_t) 0x15UL)       /**< RAM_CODE used bits  */
+#define PER_BITCLR_MEM_BASE       ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address  */
+#define PER_BITCLR_MEM_SIZE       ((uint32_t) 0xE8000UL)    /**< PER_BITCLR available address space  */
+#define PER_BITCLR_MEM_END        ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address  */
+#define PER_BITCLR_MEM_BITS       ((uint32_t) 0x20UL)       /**< PER_BITCLR used bits  */
+#define CRYPTO_BITSET_MEM_BASE    ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address  */
+#define CRYPTO_BITSET_MEM_SIZE    ((uint32_t) 0x400UL)      /**< CRYPTO_BITSET available address space  */
+#define CRYPTO_BITSET_MEM_END     ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address  */
+#define CRYPTO_BITSET_MEM_BITS    ((uint32_t) 0x10UL)       /**< CRYPTO_BITSET used bits  */
+#define CRYPTO_MEM_BASE           ((uint32_t) 0x400F0000UL) /**< CRYPTO base address  */
+#define CRYPTO_MEM_SIZE           ((uint32_t) 0x400UL)      /**< CRYPTO available address space  */
+#define CRYPTO_MEM_END            ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address  */
+#define CRYPTO_MEM_BITS           ((uint32_t) 0x10UL)       /**< CRYPTO used bits  */
+#define CRYPTO_BITCLR_MEM_BASE    ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address  */
+#define CRYPTO_BITCLR_MEM_SIZE    ((uint32_t) 0x400UL)      /**< CRYPTO_BITCLR available address space  */
+#define CRYPTO_BITCLR_MEM_END     ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address  */
+#define CRYPTO_BITCLR_MEM_BITS    ((uint32_t) 0x10UL)       /**< CRYPTO_BITCLR used bits  */
+#define PER_BITSET_MEM_BASE       ((uint32_t) 0x46000000UL) /**< PER_BITSET base address  */
+#define PER_BITSET_MEM_SIZE       ((uint32_t) 0xE8000UL)    /**< PER_BITSET available address space  */
+#define PER_BITSET_MEM_END        ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address  */
+#define PER_BITSET_MEM_BITS       ((uint32_t) 0x20UL)       /**< PER_BITSET used bits  */
+#define PER_MEM_BASE              ((uint32_t) 0x40000000UL) /**< PER base address  */
+#define PER_MEM_SIZE              ((uint32_t) 0xE8000UL)    /**< PER available address space  */
+#define PER_MEM_END               ((uint32_t) 0x400E7FFFUL) /**< PER end address  */
+#define PER_MEM_BITS              ((uint32_t) 0x20UL)       /**< PER used bits  */
+#define RAM_MEM_BASE              ((uint32_t) 0x20000000UL) /**< RAM base address  */
+#define RAM_MEM_SIZE              ((uint32_t) 0x7C00UL)     /**< RAM available address space  */
+#define RAM_MEM_END               ((uint32_t) 0x20007BFFUL) /**< RAM end address  */
+#define RAM_MEM_BITS              ((uint32_t) 0x15UL)       /**< RAM used bits  */
+
+/** Bit banding area */
+#define BITBAND_PER_BASE          ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
+#define BITBAND_RAM_BASE          ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
+
+/** Flash and SRAM limits for EFM32PG1B200F128GM48 */
+#define FLASH_BASE                (0x00000000UL) /**< Flash Base Address */
+#define FLASH_SIZE                (0x00020000UL) /**< Available Flash Memory */
+#define FLASH_PAGE_SIZE           2048           /**< Flash Memory page size */
+#define SRAM_BASE                 (0x20000000UL) /**< SRAM Base Address */
+#define SRAM_SIZE                 (0x00008000UL) /**< Available SRAM Memory */
+#define __CM4_REV                 0x001          /**< Cortex-M4 Core revision r0p1 */
+#define PRS_CHAN_COUNT            12             /**< Number of PRS channels */
+#define DMA_CHAN_COUNT            8              /**< Number of DMA channels */
+
+/** AF channels connect the different on-chip peripherals with the af-mux */
+#define AFCHAN_MAX                72
+#define AFCHANLOC_MAX             32
+/** Analog AF channels */
+#define AFACHAN_MAX               61
+
+/* Part number capabilities */
+
+#define TIMER_PRESENT         /**< TIMER is available in this part */
+#define TIMER_COUNT         2 /**< 2 TIMERs available  */
+#define USART_PRESENT         /**< USART is available in this part */
+#define USART_COUNT         2 /**< 2 USARTs available  */
+#define LEUART_PRESENT        /**< LEUART is available in this part */
+#define LEUART_COUNT        1 /**< 1 LEUARTs available  */
+#define LETIMER_PRESENT       /**< LETIMER is available in this part */
+#define LETIMER_COUNT       1 /**< 1 LETIMERs available  */
+#define PCNT_PRESENT          /**< PCNT is available in this part */
+#define PCNT_COUNT          1 /**< 1 PCNTs available  */
+#define I2C_PRESENT           /**< I2C is available in this part */
+#define I2C_COUNT           1 /**< 1 I2Cs available  */
+#define ADC_PRESENT           /**< ADC is available in this part */
+#define ADC_COUNT           1 /**< 1 ADCs available  */
+#define ACMP_PRESENT          /**< ACMP is available in this part */
+#define ACMP_COUNT          2 /**< 2 ACMPs available  */
+#define IDAC_PRESENT          /**< IDAC is available in this part */
+#define IDAC_COUNT          1 /**< 1 IDACs available  */
+#define WDOG_PRESENT          /**< WDOG is available in this part */
+#define WDOG_COUNT          1 /**< 1 WDOGs available  */
+#define MSC_PRESENT
+#define MSC_COUNT           1
+#define EMU_PRESENT
+#define EMU_COUNT           1
+#define RMU_PRESENT
+#define RMU_COUNT           1
+#define CMU_PRESENT
+#define CMU_COUNT           1
+#define CRYPTO_PRESENT
+#define CRYPTO_COUNT        1
+#define GPIO_PRESENT
+#define GPIO_COUNT          1
+#define PRS_PRESENT
+#define PRS_COUNT           1
+#define LDMA_PRESENT
+#define LDMA_COUNT          1
+#define FPUEH_PRESENT
+#define FPUEH_COUNT         1
+#define GPCRC_PRESENT
+#define GPCRC_COUNT         1
+#define CRYOTIMER_PRESENT
+#define CRYOTIMER_COUNT     1
+#define RTCC_PRESENT
+#define RTCC_COUNT          1
+#define BOOTLOADER_PRESENT
+#define BOOTLOADER_COUNT    1
+
+#include "core_cm4.h"         /* Cortex-M4 processor and core peripherals */
+#include "system_efm32pg1b.h" /* System Header File */
+
+/** @} End of group EFM32PG1B200F128GM48_Part */
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B200F128GM48_Peripheral_TypeDefs EFM32PG1B200F128GM48 Peripheral TypeDefs
+ * @{
+ * @brief Device Specific Peripheral Register Structures
+ *****************************************************************************/
+
+#include "efm32pg1b_msc.h"
+#include "efm32pg1b_emu.h"
+#include "efm32pg1b_rmu.h"
+#include "efm32pg1b_cmu.h"
+#include "efm32pg1b_crypto.h"
+#include "efm32pg1b_gpio_p.h"
+#include "efm32pg1b_gpio.h"
+#include "efm32pg1b_prs_ch.h"
+#include "efm32pg1b_prs.h"
+#include "efm32pg1b_ldma_ch.h"
+#include "efm32pg1b_ldma.h"
+#include "efm32pg1b_fpueh.h"
+#include "efm32pg1b_gpcrc.h"
+#include "efm32pg1b_timer_cc.h"
+#include "efm32pg1b_timer.h"
+#include "efm32pg1b_usart.h"
+#include "efm32pg1b_leuart.h"
+#include "efm32pg1b_letimer.h"
+#include "efm32pg1b_cryotimer.h"
+#include "efm32pg1b_pcnt.h"
+#include "efm32pg1b_i2c.h"
+#include "efm32pg1b_adc.h"
+#include "efm32pg1b_acmp.h"
+#include "efm32pg1b_idac.h"
+#include "efm32pg1b_rtcc_cc.h"
+#include "efm32pg1b_rtcc_ret.h"
+#include "efm32pg1b_rtcc.h"
+#include "efm32pg1b_wdog_pch.h"
+#include "efm32pg1b_wdog.h"
+#include "efm32pg1b_dma_descriptor.h"
+#include "efm32pg1b_devinfo.h"
+#include "efm32pg1b_romtable.h"
+
+/** @} End of group EFM32PG1B200F128GM48_Peripheral_TypeDefs  */
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B200F128GM48_Peripheral_Base EFM32PG1B200F128GM48 Peripheral Memory Map
+ * @{
+ *****************************************************************************/
+
+#define MSC_BASE          (0x400E0000UL) /**< MSC base address  */
+#define EMU_BASE          (0x400E3000UL) /**< EMU base address  */
+#define RMU_BASE          (0x400E5000UL) /**< RMU base address  */
+#define CMU_BASE          (0x400E4000UL) /**< CMU base address  */
+#define CRYPTO_BASE       (0x400F0000UL) /**< CRYPTO base address  */
+#define GPIO_BASE         (0x4000A000UL) /**< GPIO base address  */
+#define PRS_BASE          (0x400E6000UL) /**< PRS base address  */
+#define LDMA_BASE         (0x400E2000UL) /**< LDMA base address  */
+#define FPUEH_BASE        (0x400E1000UL) /**< FPUEH base address  */
+#define GPCRC_BASE        (0x4001C000UL) /**< GPCRC base address  */
+#define TIMER0_BASE       (0x40018000UL) /**< TIMER0 base address  */
+#define TIMER1_BASE       (0x40018400UL) /**< TIMER1 base address  */
+#define USART0_BASE       (0x40010000UL) /**< USART0 base address  */
+#define USART1_BASE       (0x40010400UL) /**< USART1 base address  */
+#define LEUART0_BASE      (0x4004A000UL) /**< LEUART0 base address  */
+#define LETIMER0_BASE     (0x40046000UL) /**< LETIMER0 base address  */
+#define CRYOTIMER_BASE    (0x4001E000UL) /**< CRYOTIMER base address  */
+#define PCNT0_BASE        (0x4004E000UL) /**< PCNT0 base address  */
+#define I2C0_BASE         (0x4000C000UL) /**< I2C0 base address  */
+#define ADC0_BASE         (0x40002000UL) /**< ADC0 base address  */
+#define ACMP0_BASE        (0x40000000UL) /**< ACMP0 base address  */
+#define ACMP1_BASE        (0x40000400UL) /**< ACMP1 base address  */
+#define IDAC0_BASE        (0x40006000UL) /**< IDAC0 base address  */
+#define RTCC_BASE         (0x40042000UL) /**< RTCC base address  */
+#define WDOG0_BASE        (0x40052000UL) /**< WDOG0 base address  */
+#define DEVINFO_BASE      (0x0FE081B0UL) /**< DEVINFO base address */
+#define ROMTABLE_BASE     (0xE00FFFD0UL) /**< ROMTABLE base address */
+#define LOCKBITS_BASE     (0x0FE04000UL) /**< Lock-bits page base address */
+#define USERDATA_BASE     (0x0FE00000UL) /**< User data page base address */
+
+/** @} End of group EFM32PG1B200F128GM48_Peripheral_Base */
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B200F128GM48_Peripheral_Declaration  EFM32PG1B200F128GM48 Peripheral Declarations
+ * @{
+ *****************************************************************************/
+
+#define MSC          ((MSC_TypeDef *) MSC_BASE)             /**< MSC base pointer */
+#define EMU          ((EMU_TypeDef *) EMU_BASE)             /**< EMU base pointer */
+#define RMU          ((RMU_TypeDef *) RMU_BASE)             /**< RMU base pointer */
+#define CMU          ((CMU_TypeDef *) CMU_BASE)             /**< CMU base pointer */
+#define CRYPTO       ((CRYPTO_TypeDef *) CRYPTO_BASE)       /**< CRYPTO base pointer */
+#define GPIO         ((GPIO_TypeDef *) GPIO_BASE)           /**< GPIO base pointer */
+#define PRS          ((PRS_TypeDef *) PRS_BASE)             /**< PRS base pointer */
+#define LDMA         ((LDMA_TypeDef *) LDMA_BASE)           /**< LDMA base pointer */
+#define FPUEH        ((FPUEH_TypeDef *) FPUEH_BASE)         /**< FPUEH base pointer */
+#define GPCRC        ((GPCRC_TypeDef *) GPCRC_BASE)         /**< GPCRC base pointer */
+#define TIMER0       ((TIMER_TypeDef *) TIMER0_BASE)        /**< TIMER0 base pointer */
+#define TIMER1       ((TIMER_TypeDef *) TIMER1_BASE)        /**< TIMER1 base pointer */
+#define USART0       ((USART_TypeDef *) USART0_BASE)        /**< USART0 base pointer */
+#define USART1       ((USART_TypeDef *) USART1_BASE)        /**< USART1 base pointer */
+#define LEUART0      ((LEUART_TypeDef *) LEUART0_BASE)      /**< LEUART0 base pointer */
+#define LETIMER0     ((LETIMER_TypeDef *) LETIMER0_BASE)    /**< LETIMER0 base pointer */
+#define CRYOTIMER    ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */
+#define PCNT0        ((PCNT_TypeDef *) PCNT0_BASE)          /**< PCNT0 base pointer */
+#define I2C0         ((I2C_TypeDef *) I2C0_BASE)            /**< I2C0 base pointer */
+#define ADC0         ((ADC_TypeDef *) ADC0_BASE)            /**< ADC0 base pointer */
+#define ACMP0        ((ACMP_TypeDef *) ACMP0_BASE)          /**< ACMP0 base pointer */
+#define ACMP1        ((ACMP_TypeDef *) ACMP1_BASE)          /**< ACMP1 base pointer */
+#define IDAC0        ((IDAC_TypeDef *) IDAC0_BASE)          /**< IDAC0 base pointer */
+#define RTCC         ((RTCC_TypeDef *) RTCC_BASE)           /**< RTCC base pointer */
+#define WDOG0        ((WDOG_TypeDef *) WDOG0_BASE)          /**< WDOG0 base pointer */
+#define DEVINFO      ((DEVINFO_TypeDef *) DEVINFO_BASE)     /**< DEVINFO base pointer */
+#define ROMTABLE     ((ROMTABLE_TypeDef *) ROMTABLE_BASE)   /**< ROMTABLE base pointer */
+
+/** @} End of group EFM32PG1B200F128GM48_Peripheral_Declaration */
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B200F128GM48_Peripheral_Offsets  EFM32PG1B200F128GM48 Peripheral Offsets
+ * @{
+ *****************************************************************************/
+
+#define TIMER_OFFSET      0x400 /**< Offset in bytes between TIMER instances */
+#define USART_OFFSET      0x400 /**< Offset in bytes between USART instances */
+#define LEUART_OFFSET     0x400 /**< Offset in bytes between LEUART instances */
+#define LETIMER_OFFSET    0x400 /**< Offset in bytes between LETIMER instances */
+#define PCNT_OFFSET       0x400 /**< Offset in bytes between PCNT instances */
+#define I2C_OFFSET        0x400 /**< Offset in bytes between I2C instances */
+#define ADC_OFFSET        0x400 /**< Offset in bytes between ADC instances */
+#define ACMP_OFFSET       0x400 /**< Offset in bytes between ACMP instances */
+#define IDAC_OFFSET       0x400 /**< Offset in bytes between IDAC instances */
+#define WDOG_OFFSET       0x400 /**< Offset in bytes between WDOG instances */
+
+/** @} End of group EFM32PG1B200F128GM48_Peripheral_Offsets */
+
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B200F128GM48_BitFields EFM32PG1B200F128GM48 Bit Fields
+ * @{
+ *****************************************************************************/
+
+#include "efm32pg1b_prs_signals.h"
+#include "efm32pg1b_dmareq.h"
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B200F128GM48_UNLOCK EFM32PG1B200F128GM48 Unlock Codes
+ * @{
+ *****************************************************************************/
+#define MSC_UNLOCK_CODE      0x1B71 /**< MSC unlock code */
+#define EMU_UNLOCK_CODE      0xADE8 /**< EMU unlock code */
+#define RMU_UNLOCK_CODE      0xE084 /**< RMU unlock code */
+#define CMU_UNLOCK_CODE      0x580E /**< CMU unlock code */
+#define GPIO_UNLOCK_CODE     0xA534 /**< GPIO unlock code */
+#define TIMER_UNLOCK_CODE    0xCE80 /**< TIMER unlock code */
+#define RTCC_UNLOCK_CODE     0xAEE8 /**< RTCC unlock code */
+
+/** @} End of group EFM32PG1B200F128GM48_UNLOCK */
+
+/** @} End of group EFM32PG1B200F128GM48_BitFields */
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B200F128GM48_Alternate_Function EFM32PG1B200F128GM48 Alternate Function
+ * @{
+ *****************************************************************************/
+
+#include "efm32pg1b_af_ports.h"
+#include "efm32pg1b_af_pins.h"
+
+/** @} End of group EFM32PG1B200F128GM48_Alternate_Function */
+
+/**************************************************************************//**
+ *  @brief Set the value of a bit field within a register.
+ *
+ *  @param REG
+ *       The register to update
+ *  @param MASK
+ *       The mask for the bit field to update
+ *  @param VALUE
+ *       The value to write to the bit field
+ *  @param OFFSET
+ *       The number of bits that the field is offset within the register.
+ *       0 (zero) means LSB.
+ *****************************************************************************/
+#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
+  REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
+
+/** @} End of group EFM32PG1B200F128GM48 */
+
+/** @} End of group Parts */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* SILICON_LABS_EFM32PG1B200F128GM48_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG_STK3401/efm32pg1b200f256gm32.h	Fri Jan 15 07:45:16 2016 +0000
@@ -0,0 +1,425 @@
+/**************************************************************************//**
+ * @file efm32pg1b200f256gm32.h
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File
+ *        for EFM32PG1B200F256GM32
+ * @version 4.2.0
+ ******************************************************************************
+ * @section License
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ ******************************************************************************
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software.@n
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.@n
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is
+ * providing the Software "AS IS", with no express or implied warranties of any
+ * kind, including, but not limited to, any implied warranties of
+ * merchantability or fitness for any particular purpose or warranties against
+ * infringement of any proprietary rights of a third party.
+ *
+ * Silicon Laboratories, Inc. will not be liable for any consequential,
+ * incidental, or special damages, or any other relief, or for any claim by
+ * any third party, arising from your use of this Software.
+ *
+ *****************************************************************************/
+
+#ifndef SILICON_LABS_EFM32PG1B200F256GM32_H
+#define SILICON_LABS_EFM32PG1B200F256GM32_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ *****************************************************************************/
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B200F256GM32 EFM32PG1B200F256GM32
+ * @{
+ *****************************************************************************/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M4 Processor Exceptions Numbers *******************************************/
+  NonMaskableInt_IRQn   = -14,              /*!< 2  Cortex-M4 Non Maskable Interrupt      */
+  HardFault_IRQn        = -13,              /*!< 3  Cortex-M4 Hard Fault Interrupt        */
+  MemoryManagement_IRQn = -12,              /*!< 4  Cortex-M4 Memory Management Interrupt */
+  BusFault_IRQn         = -11,              /*!< 5  Cortex-M4 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10,              /*!< 6  Cortex-M4 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,               /*!< 11 Cortex-M4 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,               /*!< 12 Cortex-M4 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,               /*!< 14 Cortex-M4 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,               /*!< 15 Cortex-M4 System Tick Interrupt       */
+
+/******  EFM32PG1B Peripheral Interrupt Numbers *********************************************/
+
+  EMU_IRQn              = 0,  /*!< 16+0 EFM32 EMU Interrupt */
+  WDOG0_IRQn            = 2,  /*!< 16+2 EFM32 WDOG0 Interrupt */
+  LDMA_IRQn             = 8,  /*!< 16+8 EFM32 LDMA Interrupt */
+  GPIO_EVEN_IRQn        = 9,  /*!< 16+9 EFM32 GPIO_EVEN Interrupt */
+  TIMER0_IRQn           = 10, /*!< 16+10 EFM32 TIMER0 Interrupt */
+  USART0_RX_IRQn        = 11, /*!< 16+11 EFM32 USART0_RX Interrupt */
+  USART0_TX_IRQn        = 12, /*!< 16+12 EFM32 USART0_TX Interrupt */
+  ACMP0_IRQn            = 13, /*!< 16+13 EFM32 ACMP0 Interrupt */
+  ADC0_IRQn             = 14, /*!< 16+14 EFM32 ADC0 Interrupt */
+  IDAC0_IRQn            = 15, /*!< 16+15 EFM32 IDAC0 Interrupt */
+  I2C0_IRQn             = 16, /*!< 16+16 EFM32 I2C0 Interrupt */
+  GPIO_ODD_IRQn         = 17, /*!< 16+17 EFM32 GPIO_ODD Interrupt */
+  TIMER1_IRQn           = 18, /*!< 16+18 EFM32 TIMER1 Interrupt */
+  USART1_RX_IRQn        = 19, /*!< 16+19 EFM32 USART1_RX Interrupt */
+  USART1_TX_IRQn        = 20, /*!< 16+20 EFM32 USART1_TX Interrupt */
+  LEUART0_IRQn          = 21, /*!< 16+21 EFM32 LEUART0 Interrupt */
+  PCNT0_IRQn            = 22, /*!< 16+22 EFM32 PCNT0 Interrupt */
+  CMU_IRQn              = 23, /*!< 16+23 EFM32 CMU Interrupt */
+  MSC_IRQn              = 24, /*!< 16+24 EFM32 MSC Interrupt */
+  CRYPTO_IRQn           = 25, /*!< 16+25 EFM32 CRYPTO Interrupt */
+  LETIMER0_IRQn         = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */
+  RTCC_IRQn             = 29, /*!< 16+29 EFM32 RTCC Interrupt */
+  CRYOTIMER_IRQn        = 31, /*!< 16+31 EFM32 CRYOTIMER Interrupt */
+  FPUEH_IRQn            = 33, /*!< 16+33 EFM32 FPUEH Interrupt */
+} IRQn_Type;
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B200F256GM32_Core EFM32PG1B200F256GM32 Core
+ * @{
+ * @brief Processor and Core Peripheral Section
+ *****************************************************************************/
+#define __MPU_PRESENT             1 /**< Presence of MPU  */
+#define __FPU_PRESENT             1 /**< Presence of FPU  */
+#define __NVIC_PRIO_BITS          3 /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig    0 /**< Is 1 if different SysTick counter is used */
+
+/** @} End of group EFM32PG1B200F256GM32_Core */
+
+/**************************************************************************//**
+* @defgroup EFM32PG1B200F256GM32_Part EFM32PG1B200F256GM32 Part
+* @{
+******************************************************************************/
+
+/** Part family */
+#define _EFM32_PEARL_FAMILY             1 /**< PEARL Gecko MCU Family  */
+#define _EFM_DEVICE                       /**< Silicon Labs EFM-type microcontroller */
+#define _SILICON_LABS_32B_PLATFORM_2      /**< Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM      2 /**< Silicon Labs platform name */
+
+/* If part number is not defined as compiler option, define it */
+#if !defined(EFM32PG1B200F256GM32)
+#define EFM32PG1B200F256GM32    1 /**< PEARL Gecko Part */
+#endif
+
+/** Configure part number */
+#define PART_NUMBER               "EFM32PG1B200F256GM32" /**< Part Number */
+
+/** Memory Base addresses and limits */
+#define FLASH_MEM_BASE            ((uint32_t) 0x00000000UL) /**< FLASH base address  */
+#define FLASH_MEM_SIZE            ((uint32_t) 0x10000000UL) /**< FLASH available address space  */
+#define FLASH_MEM_END             ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address  */
+#define FLASH_MEM_BITS            ((uint32_t) 0x28UL)       /**< FLASH used bits  */
+#define RAM_CODE_MEM_BASE         ((uint32_t) 0x10000000UL) /**< RAM_CODE base address  */
+#define RAM_CODE_MEM_SIZE         ((uint32_t) 0x7C00UL)     /**< RAM_CODE available address space  */
+#define RAM_CODE_MEM_END          ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address  */
+#define RAM_CODE_MEM_BITS         ((uint32_t) 0x15UL)       /**< RAM_CODE used bits  */
+#define PER_BITCLR_MEM_BASE       ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address  */
+#define PER_BITCLR_MEM_SIZE       ((uint32_t) 0xE8000UL)    /**< PER_BITCLR available address space  */
+#define PER_BITCLR_MEM_END        ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address  */
+#define PER_BITCLR_MEM_BITS       ((uint32_t) 0x20UL)       /**< PER_BITCLR used bits  */
+#define CRYPTO_BITSET_MEM_BASE    ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address  */
+#define CRYPTO_BITSET_MEM_SIZE    ((uint32_t) 0x400UL)      /**< CRYPTO_BITSET available address space  */
+#define CRYPTO_BITSET_MEM_END     ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address  */
+#define CRYPTO_BITSET_MEM_BITS    ((uint32_t) 0x10UL)       /**< CRYPTO_BITSET used bits  */
+#define CRYPTO_MEM_BASE           ((uint32_t) 0x400F0000UL) /**< CRYPTO base address  */
+#define CRYPTO_MEM_SIZE           ((uint32_t) 0x400UL)      /**< CRYPTO available address space  */
+#define CRYPTO_MEM_END            ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address  */
+#define CRYPTO_MEM_BITS           ((uint32_t) 0x10UL)       /**< CRYPTO used bits  */
+#define CRYPTO_BITCLR_MEM_BASE    ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address  */
+#define CRYPTO_BITCLR_MEM_SIZE    ((uint32_t) 0x400UL)      /**< CRYPTO_BITCLR available address space  */
+#define CRYPTO_BITCLR_MEM_END     ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address  */
+#define CRYPTO_BITCLR_MEM_BITS    ((uint32_t) 0x10UL)       /**< CRYPTO_BITCLR used bits  */
+#define PER_BITSET_MEM_BASE       ((uint32_t) 0x46000000UL) /**< PER_BITSET base address  */
+#define PER_BITSET_MEM_SIZE       ((uint32_t) 0xE8000UL)    /**< PER_BITSET available address space  */
+#define PER_BITSET_MEM_END        ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address  */
+#define PER_BITSET_MEM_BITS       ((uint32_t) 0x20UL)       /**< PER_BITSET used bits  */
+#define PER_MEM_BASE              ((uint32_t) 0x40000000UL) /**< PER base address  */
+#define PER_MEM_SIZE              ((uint32_t) 0xE8000UL)    /**< PER available address space  */
+#define PER_MEM_END               ((uint32_t) 0x400E7FFFUL) /**< PER end address  */
+#define PER_MEM_BITS              ((uint32_t) 0x20UL)       /**< PER used bits  */
+#define RAM_MEM_BASE              ((uint32_t) 0x20000000UL) /**< RAM base address  */
+#define RAM_MEM_SIZE              ((uint32_t) 0x7C00UL)     /**< RAM available address space  */
+#define RAM_MEM_END               ((uint32_t) 0x20007BFFUL) /**< RAM end address  */
+#define RAM_MEM_BITS              ((uint32_t) 0x15UL)       /**< RAM used bits  */
+
+/** Bit banding area */
+#define BITBAND_PER_BASE          ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
+#define BITBAND_RAM_BASE          ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
+
+/** Flash and SRAM limits for EFM32PG1B200F256GM32 */
+#define FLASH_BASE                (0x00000000UL) /**< Flash Base Address */
+#define FLASH_SIZE                (0x00040000UL) /**< Available Flash Memory */
+#define FLASH_PAGE_SIZE           2048           /**< Flash Memory page size */
+#define SRAM_BASE                 (0x20000000UL) /**< SRAM Base Address */
+#define SRAM_SIZE                 (0x00008000UL) /**< Available SRAM Memory */
+#define __CM4_REV                 0x001          /**< Cortex-M4 Core revision r0p1 */
+#define PRS_CHAN_COUNT            12             /**< Number of PRS channels */
+#define DMA_CHAN_COUNT            8              /**< Number of DMA channels */
+
+/** AF channels connect the different on-chip peripherals with the af-mux */
+#define AFCHAN_MAX                72
+#define AFCHANLOC_MAX             32
+/** Analog AF channels */
+#define AFACHAN_MAX               61
+
+/* Part number capabilities */
+
+#define TIMER_PRESENT         /**< TIMER is available in this part */
+#define TIMER_COUNT         2 /**< 2 TIMERs available  */
+#define USART_PRESENT         /**< USART is available in this part */
+#define USART_COUNT         2 /**< 2 USARTs available  */
+#define LEUART_PRESENT        /**< LEUART is available in this part */
+#define LEUART_COUNT        1 /**< 1 LEUARTs available  */
+#define LETIMER_PRESENT       /**< LETIMER is available in this part */
+#define LETIMER_COUNT       1 /**< 1 LETIMERs available  */
+#define PCNT_PRESENT          /**< PCNT is available in this part */
+#define PCNT_COUNT          1 /**< 1 PCNTs available  */
+#define I2C_PRESENT           /**< I2C is available in this part */
+#define I2C_COUNT           1 /**< 1 I2Cs available  */
+#define ADC_PRESENT           /**< ADC is available in this part */
+#define ADC_COUNT           1 /**< 1 ADCs available  */
+#define ACMP_PRESENT          /**< ACMP is available in this part */
+#define ACMP_COUNT          2 /**< 2 ACMPs available  */
+#define IDAC_PRESENT          /**< IDAC is available in this part */
+#define IDAC_COUNT          1 /**< 1 IDACs available  */
+#define WDOG_PRESENT          /**< WDOG is available in this part */
+#define WDOG_COUNT          1 /**< 1 WDOGs available  */
+#define MSC_PRESENT
+#define MSC_COUNT           1
+#define EMU_PRESENT
+#define EMU_COUNT           1
+#define RMU_PRESENT
+#define RMU_COUNT           1
+#define CMU_PRESENT
+#define CMU_COUNT           1
+#define CRYPTO_PRESENT
+#define CRYPTO_COUNT        1
+#define GPIO_PRESENT
+#define GPIO_COUNT          1
+#define PRS_PRESENT
+#define PRS_COUNT           1
+#define LDMA_PRESENT
+#define LDMA_COUNT          1
+#define FPUEH_PRESENT
+#define FPUEH_COUNT         1
+#define GPCRC_PRESENT
+#define GPCRC_COUNT         1
+#define CRYOTIMER_PRESENT
+#define CRYOTIMER_COUNT     1
+#define RTCC_PRESENT
+#define RTCC_COUNT          1
+#define BOOTLOADER_PRESENT
+#define BOOTLOADER_COUNT    1
+
+#include "core_cm4.h"         /* Cortex-M4 processor and core peripherals */
+#include "system_efm32pg1b.h" /* System Header File */
+
+/** @} End of group EFM32PG1B200F256GM32_Part */
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B200F256GM32_Peripheral_TypeDefs EFM32PG1B200F256GM32 Peripheral TypeDefs
+ * @{
+ * @brief Device Specific Peripheral Register Structures
+ *****************************************************************************/
+
+#include "efm32pg1b_msc.h"
+#include "efm32pg1b_emu.h"
+#include "efm32pg1b_rmu.h"
+#include "efm32pg1b_cmu.h"
+#include "efm32pg1b_crypto.h"
+#include "efm32pg1b_gpio_p.h"
+#include "efm32pg1b_gpio.h"
+#include "efm32pg1b_prs_ch.h"
+#include "efm32pg1b_prs.h"
+#include "efm32pg1b_ldma_ch.h"
+#include "efm32pg1b_ldma.h"
+#include "efm32pg1b_fpueh.h"
+#include "efm32pg1b_gpcrc.h"
+#include "efm32pg1b_timer_cc.h"
+#include "efm32pg1b_timer.h"
+#include "efm32pg1b_usart.h"
+#include "efm32pg1b_leuart.h"
+#include "efm32pg1b_letimer.h"
+#include "efm32pg1b_cryotimer.h"
+#include "efm32pg1b_pcnt.h"
+#include "efm32pg1b_i2c.h"
+#include "efm32pg1b_adc.h"
+#include "efm32pg1b_acmp.h"
+#include "efm32pg1b_idac.h"
+#include "efm32pg1b_rtcc_cc.h"
+#include "efm32pg1b_rtcc_ret.h"
+#include "efm32pg1b_rtcc.h"
+#include "efm32pg1b_wdog_pch.h"
+#include "efm32pg1b_wdog.h"
+#include "efm32pg1b_dma_descriptor.h"
+#include "efm32pg1b_devinfo.h"
+#include "efm32pg1b_romtable.h"
+
+/** @} End of group EFM32PG1B200F256GM32_Peripheral_TypeDefs  */
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B200F256GM32_Peripheral_Base EFM32PG1B200F256GM32 Peripheral Memory Map
+ * @{
+ *****************************************************************************/
+
+#define MSC_BASE          (0x400E0000UL) /**< MSC base address  */
+#define EMU_BASE          (0x400E3000UL) /**< EMU base address  */
+#define RMU_BASE          (0x400E5000UL) /**< RMU base address  */
+#define CMU_BASE          (0x400E4000UL) /**< CMU base address  */
+#define CRYPTO_BASE       (0x400F0000UL) /**< CRYPTO base address  */
+#define GPIO_BASE         (0x4000A000UL) /**< GPIO base address  */
+#define PRS_BASE          (0x400E6000UL) /**< PRS base address  */
+#define LDMA_BASE         (0x400E2000UL) /**< LDMA base address  */
+#define FPUEH_BASE        (0x400E1000UL) /**< FPUEH base address  */
+#define GPCRC_BASE        (0x4001C000UL) /**< GPCRC base address  */
+#define TIMER0_BASE       (0x40018000UL) /**< TIMER0 base address  */
+#define TIMER1_BASE       (0x40018400UL) /**< TIMER1 base address  */
+#define USART0_BASE       (0x40010000UL) /**< USART0 base address  */
+#define USART1_BASE       (0x40010400UL) /**< USART1 base address  */
+#define LEUART0_BASE      (0x4004A000UL) /**< LEUART0 base address  */
+#define LETIMER0_BASE     (0x40046000UL) /**< LETIMER0 base address  */
+#define CRYOTIMER_BASE    (0x4001E000UL) /**< CRYOTIMER base address  */
+#define PCNT0_BASE        (0x4004E000UL) /**< PCNT0 base address  */
+#define I2C0_BASE         (0x4000C000UL) /**< I2C0 base address  */
+#define ADC0_BASE         (0x40002000UL) /**< ADC0 base address  */
+#define ACMP0_BASE        (0x40000000UL) /**< ACMP0 base address  */
+#define ACMP1_BASE        (0x40000400UL) /**< ACMP1 base address  */
+#define IDAC0_BASE        (0x40006000UL) /**< IDAC0 base address  */
+#define RTCC_BASE         (0x40042000UL) /**< RTCC base address  */
+#define WDOG0_BASE        (0x40052000UL) /**< WDOG0 base address  */
+#define DEVINFO_BASE      (0x0FE081B0UL) /**< DEVINFO base address */
+#define ROMTABLE_BASE     (0xE00FFFD0UL) /**< ROMTABLE base address */
+#define LOCKBITS_BASE     (0x0FE04000UL) /**< Lock-bits page base address */
+#define USERDATA_BASE     (0x0FE00000UL) /**< User data page base address */
+
+/** @} End of group EFM32PG1B200F256GM32_Peripheral_Base */
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B200F256GM32_Peripheral_Declaration  EFM32PG1B200F256GM32 Peripheral Declarations
+ * @{
+ *****************************************************************************/
+
+#define MSC          ((MSC_TypeDef *) MSC_BASE)             /**< MSC base pointer */
+#define EMU          ((EMU_TypeDef *) EMU_BASE)             /**< EMU base pointer */
+#define RMU          ((RMU_TypeDef *) RMU_BASE)             /**< RMU base pointer */
+#define CMU          ((CMU_TypeDef *) CMU_BASE)             /**< CMU base pointer */
+#define CRYPTO       ((CRYPTO_TypeDef *) CRYPTO_BASE)       /**< CRYPTO base pointer */
+#define GPIO         ((GPIO_TypeDef *) GPIO_BASE)           /**< GPIO base pointer */
+#define PRS          ((PRS_TypeDef *) PRS_BASE)             /**< PRS base pointer */
+#define LDMA         ((LDMA_TypeDef *) LDMA_BASE)           /**< LDMA base pointer */
+#define FPUEH        ((FPUEH_TypeDef *) FPUEH_BASE)         /**< FPUEH base pointer */
+#define GPCRC        ((GPCRC_TypeDef *) GPCRC_BASE)         /**< GPCRC base pointer */
+#define TIMER0       ((TIMER_TypeDef *) TIMER0_BASE)        /**< TIMER0 base pointer */
+#define TIMER1       ((TIMER_TypeDef *) TIMER1_BASE)        /**< TIMER1 base pointer */
+#define USART0       ((USART_TypeDef *) USART0_BASE)        /**< USART0 base pointer */
+#define USART1       ((USART_TypeDef *) USART1_BASE)        /**< USART1 base pointer */
+#define LEUART0      ((LEUART_TypeDef *) LEUART0_BASE)      /**< LEUART0 base pointer */
+#define LETIMER0     ((LETIMER_TypeDef *) LETIMER0_BASE)    /**< LETIMER0 base pointer */
+#define CRYOTIMER    ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */
+#define PCNT0        ((PCNT_TypeDef *) PCNT0_BASE)          /**< PCNT0 base pointer */
+#define I2C0         ((I2C_TypeDef *) I2C0_BASE)            /**< I2C0 base pointer */
+#define ADC0         ((ADC_TypeDef *) ADC0_BASE)            /**< ADC0 base pointer */
+#define ACMP0        ((ACMP_TypeDef *) ACMP0_BASE)          /**< ACMP0 base pointer */
+#define ACMP1        ((ACMP_TypeDef *) ACMP1_BASE)          /**< ACMP1 base pointer */
+#define IDAC0        ((IDAC_TypeDef *) IDAC0_BASE)          /**< IDAC0 base pointer */
+#define RTCC         ((RTCC_TypeDef *) RTCC_BASE)           /**< RTCC base pointer */
+#define WDOG0        ((WDOG_TypeDef *) WDOG0_BASE)          /**< WDOG0 base pointer */
+#define DEVINFO      ((DEVINFO_TypeDef *) DEVINFO_BASE)     /**< DEVINFO base pointer */
+#define ROMTABLE     ((ROMTABLE_TypeDef *) ROMTABLE_BASE)   /**< ROMTABLE base pointer */
+
+/** @} End of group EFM32PG1B200F256GM32_Peripheral_Declaration */
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B200F256GM32_Peripheral_Offsets  EFM32PG1B200F256GM32 Peripheral Offsets
+ * @{
+ *****************************************************************************/
+
+#define TIMER_OFFSET      0x400 /**< Offset in bytes between TIMER instances */
+#define USART_OFFSET      0x400 /**< Offset in bytes between USART instances */
+#define LEUART_OFFSET     0x400 /**< Offset in bytes between LEUART instances */
+#define LETIMER_OFFSET    0x400 /**< Offset in bytes between LETIMER instances */
+#define PCNT_OFFSET       0x400 /**< Offset in bytes between PCNT instances */
+#define I2C_OFFSET        0x400 /**< Offset in bytes between I2C instances */
+#define ADC_OFFSET        0x400 /**< Offset in bytes between ADC instances */
+#define ACMP_OFFSET       0x400 /**< Offset in bytes between ACMP instances */
+#define IDAC_OFFSET       0x400 /**< Offset in bytes between IDAC instances */
+#define WDOG_OFFSET       0x400 /**< Offset in bytes between WDOG instances */
+
+/** @} End of group EFM32PG1B200F256GM32_Peripheral_Offsets */
+
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B200F256GM32_BitFields EFM32PG1B200F256GM32 Bit Fields
+ * @{
+ *****************************************************************************/
+
+#include "efm32pg1b_prs_signals.h"
+#include "efm32pg1b_dmareq.h"
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B200F256GM32_UNLOCK EFM32PG1B200F256GM32 Unlock Codes
+ * @{
+ *****************************************************************************/
+#define MSC_UNLOCK_CODE      0x1B71 /**< MSC unlock code */
+#define EMU_UNLOCK_CODE      0xADE8 /**< EMU unlock code */
+#define RMU_UNLOCK_CODE      0xE084 /**< RMU unlock code */
+#define CMU_UNLOCK_CODE      0x580E /**< CMU unlock code */
+#define GPIO_UNLOCK_CODE     0xA534 /**< GPIO unlock code */
+#define TIMER_UNLOCK_CODE    0xCE80 /**< TIMER unlock code */
+#define RTCC_UNLOCK_CODE     0xAEE8 /**< RTCC unlock code */
+
+/** @} End of group EFM32PG1B200F256GM32_UNLOCK */
+
+/** @} End of group EFM32PG1B200F256GM32_BitFields */
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B200F256GM32_Alternate_Function EFM32PG1B200F256GM32 Alternate Function
+ * @{
+ *****************************************************************************/
+
+#include "efm32pg1b_af_ports.h"
+#include "efm32pg1b_af_pins.h"
+
+/** @} End of group EFM32PG1B200F256GM32_Alternate_Function */
+
+/**************************************************************************//**
+ *  @brief Set the value of a bit field within a register.
+ *
+ *  @param REG
+ *       The register to update
+ *  @param MASK
+ *       The mask for the bit field to update
+ *  @param VALUE
+ *       The value to write to the bit field
+ *  @param OFFSET
+ *       The number of bits that the field is offset within the register.
+ *       0 (zero) means LSB.
+ *****************************************************************************/
+#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
+  REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
+
+/** @} End of group EFM32PG1B200F256GM32 */
+
+/** @} End of group Parts */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* SILICON_LABS_EFM32PG1B200F256GM32_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG_STK3401/efm32pg1b200f256gm48.h	Fri Jan 15 07:45:16 2016 +0000
@@ -0,0 +1,425 @@
+/**************************************************************************//**
+ * @file efm32pg1b200f256gm48.h
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File
+ *        for EFM32PG1B200F256GM48
+ * @version 4.2.0
+ ******************************************************************************
+ * @section License
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ ******************************************************************************
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software.@n
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.@n
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is
+ * providing the Software "AS IS", with no express or implied warranties of any
+ * kind, including, but not limited to, any implied warranties of
+ * merchantability or fitness for any particular purpose or warranties against
+ * infringement of any proprietary rights of a third party.
+ *
+ * Silicon Laboratories, Inc. will not be liable for any consequential,
+ * incidental, or special damages, or any other relief, or for any claim by
+ * any third party, arising from your use of this Software.
+ *
+ *****************************************************************************/
+
+#ifndef SILICON_LABS_EFM32PG1B200F256GM48_H
+#define SILICON_LABS_EFM32PG1B200F256GM48_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ *****************************************************************************/
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B200F256GM48 EFM32PG1B200F256GM48
+ * @{
+ *****************************************************************************/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M4 Processor Exceptions Numbers *******************************************/
+  NonMaskableInt_IRQn   = -14,              /*!< 2  Cortex-M4 Non Maskable Interrupt      */
+  HardFault_IRQn        = -13,              /*!< 3  Cortex-M4 Hard Fault Interrupt        */
+  MemoryManagement_IRQn = -12,              /*!< 4  Cortex-M4 Memory Management Interrupt */
+  BusFault_IRQn         = -11,              /*!< 5  Cortex-M4 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10,              /*!< 6  Cortex-M4 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,               /*!< 11 Cortex-M4 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,               /*!< 12 Cortex-M4 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,               /*!< 14 Cortex-M4 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,               /*!< 15 Cortex-M4 System Tick Interrupt       */
+
+/******  EFM32PG1B Peripheral Interrupt Numbers *********************************************/
+
+  EMU_IRQn              = 0,  /*!< 16+0 EFM32 EMU Interrupt */
+  WDOG0_IRQn            = 2,  /*!< 16+2 EFM32 WDOG0 Interrupt */
+  LDMA_IRQn             = 8,  /*!< 16+8 EFM32 LDMA Interrupt */
+  GPIO_EVEN_IRQn        = 9,  /*!< 16+9 EFM32 GPIO_EVEN Interrupt */
+  TIMER0_IRQn           = 10, /*!< 16+10 EFM32 TIMER0 Interrupt */
+  USART0_RX_IRQn        = 11, /*!< 16+11 EFM32 USART0_RX Interrupt */
+  USART0_TX_IRQn        = 12, /*!< 16+12 EFM32 USART0_TX Interrupt */
+  ACMP0_IRQn            = 13, /*!< 16+13 EFM32 ACMP0 Interrupt */
+  ADC0_IRQn             = 14, /*!< 16+14 EFM32 ADC0 Interrupt */
+  IDAC0_IRQn            = 15, /*!< 16+15 EFM32 IDAC0 Interrupt */
+  I2C0_IRQn             = 16, /*!< 16+16 EFM32 I2C0 Interrupt */
+  GPIO_ODD_IRQn         = 17, /*!< 16+17 EFM32 GPIO_ODD Interrupt */
+  TIMER1_IRQn           = 18, /*!< 16+18 EFM32 TIMER1 Interrupt */
+  USART1_RX_IRQn        = 19, /*!< 16+19 EFM32 USART1_RX Interrupt */
+  USART1_TX_IRQn        = 20, /*!< 16+20 EFM32 USART1_TX Interrupt */
+  LEUART0_IRQn          = 21, /*!< 16+21 EFM32 LEUART0 Interrupt */
+  PCNT0_IRQn            = 22, /*!< 16+22 EFM32 PCNT0 Interrupt */
+  CMU_IRQn              = 23, /*!< 16+23 EFM32 CMU Interrupt */
+  MSC_IRQn              = 24, /*!< 16+24 EFM32 MSC Interrupt */
+  CRYPTO_IRQn           = 25, /*!< 16+25 EFM32 CRYPTO Interrupt */
+  LETIMER0_IRQn         = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */
+  RTCC_IRQn             = 29, /*!< 16+29 EFM32 RTCC Interrupt */
+  CRYOTIMER_IRQn        = 31, /*!< 16+31 EFM32 CRYOTIMER Interrupt */
+  FPUEH_IRQn            = 33, /*!< 16+33 EFM32 FPUEH Interrupt */
+} IRQn_Type;
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B200F256GM48_Core EFM32PG1B200F256GM48 Core
+ * @{
+ * @brief Processor and Core Peripheral Section
+ *****************************************************************************/
+#define __MPU_PRESENT             1 /**< Presence of MPU  */
+#define __FPU_PRESENT             1 /**< Presence of FPU  */
+#define __NVIC_PRIO_BITS          3 /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig    0 /**< Is 1 if different SysTick counter is used */
+
+/** @} End of group EFM32PG1B200F256GM48_Core */
+
+/**************************************************************************//**
+* @defgroup EFM32PG1B200F256GM48_Part EFM32PG1B200F256GM48 Part
+* @{
+******************************************************************************/
+
+/** Part family */
+#define _EFM32_PEARL_FAMILY             1 /**< PEARL Gecko MCU Family  */
+#define _EFM_DEVICE                       /**< Silicon Labs EFM-type microcontroller */
+#define _SILICON_LABS_32B_PLATFORM_2      /**< Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM      2 /**< Silicon Labs platform name */
+
+/* If part number is not defined as compiler option, define it */
+#if !defined(EFM32PG1B200F256GM48)
+#define EFM32PG1B200F256GM48    1 /**< PEARL Gecko Part */
+#endif
+
+/** Configure part number */
+#define PART_NUMBER               "EFM32PG1B200F256GM48" /**< Part Number */
+
+/** Memory Base addresses and limits */
+#define FLASH_MEM_BASE            ((uint32_t) 0x00000000UL) /**< FLASH base address  */
+#define FLASH_MEM_SIZE            ((uint32_t) 0x10000000UL) /**< FLASH available address space  */
+#define FLASH_MEM_END             ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address  */
+#define FLASH_MEM_BITS            ((uint32_t) 0x28UL)       /**< FLASH used bits  */
+#define RAM_CODE_MEM_BASE         ((uint32_t) 0x10000000UL) /**< RAM_CODE base address  */
+#define RAM_CODE_MEM_SIZE         ((uint32_t) 0x7C00UL)     /**< RAM_CODE available address space  */
+#define RAM_CODE_MEM_END          ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address  */
+#define RAM_CODE_MEM_BITS         ((uint32_t) 0x15UL)       /**< RAM_CODE used bits  */
+#define PER_BITCLR_MEM_BASE       ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address  */
+#define PER_BITCLR_MEM_SIZE       ((uint32_t) 0xE8000UL)    /**< PER_BITCLR available address space  */
+#define PER_BITCLR_MEM_END        ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address  */
+#define PER_BITCLR_MEM_BITS       ((uint32_t) 0x20UL)       /**< PER_BITCLR used bits  */
+#define CRYPTO_BITSET_MEM_BASE    ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address  */
+#define CRYPTO_BITSET_MEM_SIZE    ((uint32_t) 0x400UL)      /**< CRYPTO_BITSET available address space  */
+#define CRYPTO_BITSET_MEM_END     ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address  */
+#define CRYPTO_BITSET_MEM_BITS    ((uint32_t) 0x10UL)       /**< CRYPTO_BITSET used bits  */
+#define CRYPTO_MEM_BASE           ((uint32_t) 0x400F0000UL) /**< CRYPTO base address  */
+#define CRYPTO_MEM_SIZE           ((uint32_t) 0x400UL)      /**< CRYPTO available address space  */
+#define CRYPTO_MEM_END            ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address  */
+#define CRYPTO_MEM_BITS           ((uint32_t) 0x10UL)       /**< CRYPTO used bits  */
+#define CRYPTO_BITCLR_MEM_BASE    ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address  */
+#define CRYPTO_BITCLR_MEM_SIZE    ((uint32_t) 0x400UL)      /**< CRYPTO_BITCLR available address space  */
+#define CRYPTO_BITCLR_MEM_END     ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address  */
+#define CRYPTO_BITCLR_MEM_BITS    ((uint32_t) 0x10UL)       /**< CRYPTO_BITCLR used bits  */
+#define PER_BITSET_MEM_BASE       ((uint32_t) 0x46000000UL) /**< PER_BITSET base address  */
+#define PER_BITSET_MEM_SIZE       ((uint32_t) 0xE8000UL)    /**< PER_BITSET available address space  */
+#define PER_BITSET_MEM_END        ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address  */
+#define PER_BITSET_MEM_BITS       ((uint32_t) 0x20UL)       /**< PER_BITSET used bits  */
+#define PER_MEM_BASE              ((uint32_t) 0x40000000UL) /**< PER base address  */
+#define PER_MEM_SIZE              ((uint32_t) 0xE8000UL)    /**< PER available address space  */
+#define PER_MEM_END               ((uint32_t) 0x400E7FFFUL) /**< PER end address  */
+#define PER_MEM_BITS              ((uint32_t) 0x20UL)       /**< PER used bits  */
+#define RAM_MEM_BASE              ((uint32_t) 0x20000000UL) /**< RAM base address  */
+#define RAM_MEM_SIZE              ((uint32_t) 0x7C00UL)     /**< RAM available address space  */
+#define RAM_MEM_END               ((uint32_t) 0x20007BFFUL) /**< RAM end address  */
+#define RAM_MEM_BITS              ((uint32_t) 0x15UL)       /**< RAM used bits  */
+
+/** Bit banding area */
+#define BITBAND_PER_BASE          ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
+#define BITBAND_RAM_BASE          ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
+
+/** Flash and SRAM limits for EFM32PG1B200F256GM48 */
+#define FLASH_BASE                (0x00000000UL) /**< Flash Base Address */
+#define FLASH_SIZE                (0x00040000UL) /**< Available Flash Memory */
+#define FLASH_PAGE_SIZE           2048           /**< Flash Memory page size */
+#define SRAM_BASE                 (0x20000000UL) /**< SRAM Base Address */
+#define SRAM_SIZE                 (0x00008000UL) /**< Available SRAM Memory */
+#define __CM4_REV                 0x001          /**< Cortex-M4 Core revision r0p1 */
+#define PRS_CHAN_COUNT            12             /**< Number of PRS channels */
+#define DMA_CHAN_COUNT            8              /**< Number of DMA channels */
+
+/** AF channels connect the different on-chip peripherals with the af-mux */
+#define AFCHAN_MAX                72
+#define AFCHANLOC_MAX             32
+/** Analog AF channels */
+#define AFACHAN_MAX               61
+
+/* Part number capabilities */
+
+#define TIMER_PRESENT         /**< TIMER is available in this part */
+#define TIMER_COUNT         2 /**< 2 TIMERs available  */
+#define USART_PRESENT         /**< USART is available in this part */
+#define USART_COUNT         2 /**< 2 USARTs available  */
+#define LEUART_PRESENT        /**< LEUART is available in this part */
+#define LEUART_COUNT        1 /**< 1 LEUARTs available  */
+#define LETIMER_PRESENT       /**< LETIMER is available in this part */
+#define LETIMER_COUNT       1 /**< 1 LETIMERs available  */
+#define PCNT_PRESENT          /**< PCNT is available in this part */
+#define PCNT_COUNT          1 /**< 1 PCNTs available  */
+#define I2C_PRESENT           /**< I2C is available in this part */
+#define I2C_COUNT           1 /**< 1 I2Cs available  */
+#define ADC_PRESENT           /**< ADC is available in this part */
+#define ADC_COUNT           1 /**< 1 ADCs available  */
+#define ACMP_PRESENT          /**< ACMP is available in this part */
+#define ACMP_COUNT          2 /**< 2 ACMPs available  */
+#define IDAC_PRESENT          /**< IDAC is available in this part */
+#define IDAC_COUNT          1 /**< 1 IDACs available  */
+#define WDOG_PRESENT          /**< WDOG is available in this part */
+#define WDOG_COUNT          1 /**< 1 WDOGs available  */
+#define MSC_PRESENT
+#define MSC_COUNT           1
+#define EMU_PRESENT
+#define EMU_COUNT           1
+#define RMU_PRESENT
+#define RMU_COUNT           1
+#define CMU_PRESENT
+#define CMU_COUNT           1
+#define CRYPTO_PRESENT
+#define CRYPTO_COUNT        1
+#define GPIO_PRESENT
+#define GPIO_COUNT          1
+#define PRS_PRESENT
+#define PRS_COUNT           1
+#define LDMA_PRESENT
+#define LDMA_COUNT          1
+#define FPUEH_PRESENT
+#define FPUEH_COUNT         1
+#define GPCRC_PRESENT
+#define GPCRC_COUNT         1
+#define CRYOTIMER_PRESENT
+#define CRYOTIMER_COUNT     1
+#define RTCC_PRESENT
+#define RTCC_COUNT          1
+#define BOOTLOADER_PRESENT
+#define BOOTLOADER_COUNT    1
+
+#include "core_cm4.h"         /* Cortex-M4 processor and core peripherals */
+#include "system_efm32pg1b.h" /* System Header File */
+
+/** @} End of group EFM32PG1B200F256GM48_Part */
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B200F256GM48_Peripheral_TypeDefs EFM32PG1B200F256GM48 Peripheral TypeDefs
+ * @{
+ * @brief Device Specific Peripheral Register Structures
+ *****************************************************************************/
+
+#include "efm32pg1b_msc.h"
+#include "efm32pg1b_emu.h"
+#include "efm32pg1b_rmu.h"
+#include "efm32pg1b_cmu.h"
+#include "efm32pg1b_crypto.h"
+#include "efm32pg1b_gpio_p.h"
+#include "efm32pg1b_gpio.h"
+#include "efm32pg1b_prs_ch.h"
+#include "efm32pg1b_prs.h"
+#include "efm32pg1b_ldma_ch.h"
+#include "efm32pg1b_ldma.h"
+#include "efm32pg1b_fpueh.h"
+#include "efm32pg1b_gpcrc.h"
+#include "efm32pg1b_timer_cc.h"
+#include "efm32pg1b_timer.h"
+#include "efm32pg1b_usart.h"
+#include "efm32pg1b_leuart.h"
+#include "efm32pg1b_letimer.h"
+#include "efm32pg1b_cryotimer.h"
+#include "efm32pg1b_pcnt.h"
+#include "efm32pg1b_i2c.h"
+#include "efm32pg1b_adc.h"
+#include "efm32pg1b_acmp.h"
+#include "efm32pg1b_idac.h"
+#include "efm32pg1b_rtcc_cc.h"
+#include "efm32pg1b_rtcc_ret.h"
+#include "efm32pg1b_rtcc.h"
+#include "efm32pg1b_wdog_pch.h"
+#include "efm32pg1b_wdog.h"
+#include "efm32pg1b_dma_descriptor.h"
+#include "efm32pg1b_devinfo.h"
+#include "efm32pg1b_romtable.h"
+
+/** @} End of group EFM32PG1B200F256GM48_Peripheral_TypeDefs  */
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B200F256GM48_Peripheral_Base EFM32PG1B200F256GM48 Peripheral Memory Map
+ * @{
+ *****************************************************************************/
+
+#define MSC_BASE          (0x400E0000UL) /**< MSC base address  */
+#define EMU_BASE          (0x400E3000UL) /**< EMU base address  */
+#define RMU_BASE          (0x400E5000UL) /**< RMU base address  */
+#define CMU_BASE          (0x400E4000UL) /**< CMU base address  */
+#define CRYPTO_BASE       (0x400F0000UL) /**< CRYPTO base address  */
+#define GPIO_BASE         (0x4000A000UL) /**< GPIO base address  */
+#define PRS_BASE          (0x400E6000UL) /**< PRS base address  */
+#define LDMA_BASE         (0x400E2000UL) /**< LDMA base address  */
+#define FPUEH_BASE        (0x400E1000UL) /**< FPUEH base address  */
+#define GPCRC_BASE        (0x4001C000UL) /**< GPCRC base address  */
+#define TIMER0_BASE       (0x40018000UL) /**< TIMER0 base address  */
+#define TIMER1_BASE       (0x40018400UL) /**< TIMER1 base address  */
+#define USART0_BASE       (0x40010000UL) /**< USART0 base address  */
+#define USART1_BASE       (0x40010400UL) /**< USART1 base address  */
+#define LEUART0_BASE      (0x4004A000UL) /**< LEUART0 base address  */
+#define LETIMER0_BASE     (0x40046000UL) /**< LETIMER0 base address  */
+#define CRYOTIMER_BASE    (0x4001E000UL) /**< CRYOTIMER base address  */
+#define PCNT0_BASE        (0x4004E000UL) /**< PCNT0 base address  */
+#define I2C0_BASE         (0x4000C000UL) /**< I2C0 base address  */
+#define ADC0_BASE         (0x40002000UL) /**< ADC0 base address  */
+#define ACMP0_BASE        (0x40000000UL) /**< ACMP0 base address  */
+#define ACMP1_BASE        (0x40000400UL) /**< ACMP1 base address  */
+#define IDAC0_BASE        (0x40006000UL) /**< IDAC0 base address  */
+#define RTCC_BASE         (0x40042000UL) /**< RTCC base address  */
+#define WDOG0_BASE        (0x40052000UL) /**< WDOG0 base address  */
+#define DEVINFO_BASE      (0x0FE081B0UL) /**< DEVINFO base address */
+#define ROMTABLE_BASE     (0xE00FFFD0UL) /**< ROMTABLE base address */
+#define LOCKBITS_BASE     (0x0FE04000UL) /**< Lock-bits page base address */
+#define USERDATA_BASE     (0x0FE00000UL) /**< User data page base address */
+
+/** @} End of group EFM32PG1B200F256GM48_Peripheral_Base */
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B200F256GM48_Peripheral_Declaration  EFM32PG1B200F256GM48 Peripheral Declarations
+ * @{
+ *****************************************************************************/
+
+#define MSC          ((MSC_TypeDef *) MSC_BASE)             /**< MSC base pointer */
+#define EMU          ((EMU_TypeDef *) EMU_BASE)             /**< EMU base pointer */
+#define RMU          ((RMU_TypeDef *) RMU_BASE)             /**< RMU base pointer */
+#define CMU          ((CMU_TypeDef *) CMU_BASE)             /**< CMU base pointer */
+#define CRYPTO       ((CRYPTO_TypeDef *) CRYPTO_BASE)       /**< CRYPTO base pointer */
+#define GPIO         ((GPIO_TypeDef *) GPIO_BASE)           /**< GPIO base pointer */
+#define PRS          ((PRS_TypeDef *) PRS_BASE)             /**< PRS base pointer */
+#define LDMA         ((LDMA_TypeDef *) LDMA_BASE)           /**< LDMA base pointer */
+#define FPUEH        ((FPUEH_TypeDef *) FPUEH_BASE)         /**< FPUEH base pointer */
+#define GPCRC        ((GPCRC_TypeDef *) GPCRC_BASE)         /**< GPCRC base pointer */
+#define TIMER0       ((TIMER_TypeDef *) TIMER0_BASE)        /**< TIMER0 base pointer */
+#define TIMER1       ((TIMER_TypeDef *) TIMER1_BASE)        /**< TIMER1 base pointer */
+#define USART0       ((USART_TypeDef *) USART0_BASE)        /**< USART0 base pointer */
+#define USART1       ((USART_TypeDef *) USART1_BASE)        /**< USART1 base pointer */
+#define LEUART0      ((LEUART_TypeDef *) LEUART0_BASE)      /**< LEUART0 base pointer */
+#define LETIMER0     ((LETIMER_TypeDef *) LETIMER0_BASE)    /**< LETIMER0 base pointer */
+#define CRYOTIMER    ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */
+#define PCNT0        ((PCNT_TypeDef *) PCNT0_BASE)          /**< PCNT0 base pointer */
+#define I2C0         ((I2C_TypeDef *) I2C0_BASE)            /**< I2C0 base pointer */
+#define ADC0         ((ADC_TypeDef *) ADC0_BASE)            /**< ADC0 base pointer */
+#define ACMP0        ((ACMP_TypeDef *) ACMP0_BASE)          /**< ACMP0 base pointer */
+#define ACMP1        ((ACMP_TypeDef *) ACMP1_BASE)          /**< ACMP1 base pointer */
+#define IDAC0        ((IDAC_TypeDef *) IDAC0_BASE)          /**< IDAC0 base pointer */
+#define RTCC         ((RTCC_TypeDef *) RTCC_BASE)           /**< RTCC base pointer */
+#define WDOG0        ((WDOG_TypeDef *) WDOG0_BASE)          /**< WDOG0 base pointer */
+#define DEVINFO      ((DEVINFO_TypeDef *) DEVINFO_BASE)     /**< DEVINFO base pointer */
+#define ROMTABLE     ((ROMTABLE_TypeDef *) ROMTABLE_BASE)   /**< ROMTABLE base pointer */
+
+/** @} End of group EFM32PG1B200F256GM48_Peripheral_Declaration */
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B200F256GM48_Peripheral_Offsets  EFM32PG1B200F256GM48 Peripheral Offsets
+ * @{
+ *****************************************************************************/
+
+#define TIMER_OFFSET      0x400 /**< Offset in bytes between TIMER instances */
+#define USART_OFFSET      0x400 /**< Offset in bytes between USART instances */
+#define LEUART_OFFSET     0x400 /**< Offset in bytes between LEUART instances */
+#define LETIMER_OFFSET    0x400 /**< Offset in bytes between LETIMER instances */
+#define PCNT_OFFSET       0x400 /**< Offset in bytes between PCNT instances */
+#define I2C_OFFSET        0x400 /**< Offset in bytes between I2C instances */
+#define ADC_OFFSET        0x400 /**< Offset in bytes between ADC instances */
+#define ACMP_OFFSET       0x400 /**< Offset in bytes between ACMP instances */
+#define IDAC_OFFSET       0x400 /**< Offset in bytes between IDAC instances */
+#define WDOG_OFFSET       0x400 /**< Offset in bytes between WDOG instances */
+
+/** @} End of group EFM32PG1B200F256GM48_Peripheral_Offsets */
+
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B200F256GM48_BitFields EFM32PG1B200F256GM48 Bit Fields
+ * @{
+ *****************************************************************************/
+
+#include "efm32pg1b_prs_signals.h"
+#include "efm32pg1b_dmareq.h"
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B200F256GM48_UNLOCK EFM32PG1B200F256GM48 Unlock Codes
+ * @{
+ *****************************************************************************/
+#define MSC_UNLOCK_CODE      0x1B71 /**< MSC unlock code */
+#define EMU_UNLOCK_CODE      0xADE8 /**< EMU unlock code */
+#define RMU_UNLOCK_CODE      0xE084 /**< RMU unlock code */
+#define CMU_UNLOCK_CODE      0x580E /**< CMU unlock code */
+#define GPIO_UNLOCK_CODE     0xA534 /**< GPIO unlock code */
+#define TIMER_UNLOCK_CODE    0xCE80 /**< TIMER unlock code */
+#define RTCC_UNLOCK_CODE     0xAEE8 /**< RTCC unlock code */
+
+/** @} End of group EFM32PG1B200F256GM48_UNLOCK */
+
+/** @} End of group EFM32PG1B200F256GM48_BitFields */
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B200F256GM48_Alternate_Function EFM32PG1B200F256GM48 Alternate Function
+ * @{
+ *****************************************************************************/
+
+#include "efm32pg1b_af_ports.h"
+#include "efm32pg1b_af_pins.h"
+
+/** @} End of group EFM32PG1B200F256GM48_Alternate_Function */
+
+/**************************************************************************//**
+ *  @brief Set the value of a bit field within a register.
+ *
+ *  @param REG
+ *       The register to update
+ *  @param MASK
+ *       The mask for the bit field to update
+ *  @param VALUE
+ *       The value to write to the bit field
+ *  @param OFFSET
+ *       The number of bits that the field is offset within the register.
+ *       0 (zero) means LSB.
+ *****************************************************************************/
+#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
+  REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
+
+/** @} End of group EFM32PG1B200F256GM48 */
+
+/** @} End of group Parts */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* SILICON_LABS_EFM32PG1B200F256GM48_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG_STK3401/efm32pg1b_acmp.h	Fri Jan 15 07:45:16 2016 +0000
@@ -0,0 +1,1373 @@
+/**************************************************************************//**
+ * @file efm32pg1b_acmp.h
+ * @brief EFM32PG1B_ACMP register and bit field definitions
+ * @version 4.2.0
+ ******************************************************************************
+ * @section License
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ ******************************************************************************
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software.@n
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.@n
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is
+ * providing the Software "AS IS", with no express or implied warranties of any
+ * kind, including, but not limited to, any implied warranties of
+ * merchantability or fitness for any particular purpose or warranties against
+ * infringement of any proprietary rights of a third party.
+ *
+ * Silicon Laboratories, Inc. will not be liable for any consequential,
+ * incidental, or special damages, or any other relief, or for any claim by
+ * any third party, arising from your use of this Software.
+ *
+ *****************************************************************************/
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFM32PG1B_ACMP
+ * @{
+ * @brief EFM32PG1B_ACMP Register Declaration
+ *****************************************************************************/
+typedef struct
+{
+  __IO uint32_t CTRL;          /**< Control Register  */
+  __IO uint32_t INPUTSEL;      /**< Input Selection Register  */
+  __I uint32_t  STATUS;        /**< Status Register  */
+  __I uint32_t  IF;            /**< Interrupt Flag Register  */
+  __IO uint32_t IFS;           /**< Interrupt Flag Set Register  */
+  __IO uint32_t IFC;           /**< Interrupt Flag Clear Register  */
+  __IO uint32_t IEN;           /**< Interrupt Enable Register  */
+  uint32_t      RESERVED0[1];  /**< Reserved for future use **/
+  __I uint32_t  APORTREQ;      /**< APORT Request Status Register  */
+  __I uint32_t  APORTCONFLICT; /**< APORT Request Status Register  */
+  __IO uint32_t HYSTERESIS0;   /**< Hysteresis 0 Register  */
+  __IO uint32_t HYSTERESIS1;   /**< Hysteresis 1 Register  */
+
+  uint32_t      RESERVED1[4];  /**< Reserved for future use **/
+  __IO uint32_t ROUTEPEN;      /**< I/O Routing Pine Enable Register  */
+  __IO uint32_t ROUTELOC0;     /**< I/O Routing Location Register  */
+} ACMP_TypeDef;                /** @} */
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B_ACMP_BitFields
+ * @{
+ *****************************************************************************/
+
+/* Bit fields for ACMP CTRL */
+#define _ACMP_CTRL_RESETVALUE                          0x07000000UL                               /**< Default value for ACMP_CTRL */
+#define _ACMP_CTRL_MASK                                0xBF3CF70DUL                               /**< Mask for ACMP_CTRL */
+#define ACMP_CTRL_EN                                   (0x1UL << 0)                               /**< Analog Comparator Enable */
+#define _ACMP_CTRL_EN_SHIFT                            0                                          /**< Shift value for ACMP_EN */
+#define _ACMP_CTRL_EN_MASK                             0x1UL                                      /**< Bit mask for ACMP_EN */
+#define _ACMP_CTRL_EN_DEFAULT                          0x00000000UL                               /**< Mode DEFAULT for ACMP_CTRL */
+#define ACMP_CTRL_EN_DEFAULT                           (_ACMP_CTRL_EN_DEFAULT << 0)               /**< Shifted mode DEFAULT for ACMP_CTRL */
+#define ACMP_CTRL_INACTVAL                             (0x1UL << 2)                               /**< Inactive Value */
+#define _ACMP_CTRL_INACTVAL_SHIFT                      2                                          /**< Shift value for ACMP_INACTVAL */
+#define _ACMP_CTRL_INACTVAL_MASK                       0x4UL                                      /**< Bit mask for ACMP_INACTVAL */
+#define _ACMP_CTRL_INACTVAL_DEFAULT                    0x00000000UL                               /**< Mode DEFAULT for ACMP_CTRL */
+#define _ACMP_CTRL_INACTVAL_LOW                        0x00000000UL                               /**< Mode LOW for ACMP_CTRL */
+#define _ACMP_CTRL_INACTVAL_HIGH                       0x00000001UL                               /**< Mode HIGH for ACMP_CTRL */
+#define ACMP_CTRL_INACTVAL_DEFAULT                     (_ACMP_CTRL_INACTVAL_DEFAULT << 2)         /**< Shifted mode DEFAULT for ACMP_CTRL */
+#define ACMP_CTRL_INACTVAL_LOW                         (_ACMP_CTRL_INACTVAL_LOW << 2)             /**< Shifted mode LOW for ACMP_CTRL */
+#define ACMP_CTRL_INACTVAL_HIGH                        (_ACMP_CTRL_INACTVAL_HIGH << 2)            /**< Shifted mode HIGH for ACMP_CTRL */
+#define ACMP_CTRL_GPIOINV                              (0x1UL << 3)                               /**< Comparator GPIO Output Invert */
+#define _ACMP_CTRL_GPIOINV_SHIFT                       3                                          /**< Shift value for ACMP_GPIOINV */
+#define _ACMP_CTRL_GPIOINV_MASK                        0x8UL                                      /**< Bit mask for ACMP_GPIOINV */
+#define _ACMP_CTRL_GPIOINV_DEFAULT                     0x00000000UL                               /**< Mode DEFAULT for ACMP_CTRL */
+#define _ACMP_CTRL_GPIOINV_NOTINV                      0x00000000UL                               /**< Mode NOTINV for ACMP_CTRL */
+#define _ACMP_CTRL_GPIOINV_INV                         0x00000001UL                               /**< Mode INV for ACMP_CTRL */
+#define ACMP_CTRL_GPIOINV_DEFAULT                      (_ACMP_CTRL_GPIOINV_DEFAULT << 3)          /**< Shifted mode DEFAULT for ACMP_CTRL */
+#define ACMP_CTRL_GPIOINV_NOTINV                       (_ACMP_CTRL_GPIOINV_NOTINV << 3)           /**< Shifted mode NOTINV for ACMP_CTRL */
+#define ACMP_CTRL_GPIOINV_INV                          (_ACMP_CTRL_GPIOINV_INV << 3)              /**< Shifted mode INV for ACMP_CTRL */
+#define ACMP_CTRL_APORTXMASTERDIS                      (0x1UL << 8)                               /**< APORT Bus X Master Disable */
+#define _ACMP_CTRL_APORTXMASTERDIS_SHIFT               8                                          /**< Shift value for ACMP_APORTXMASTERDIS */
+#define _ACMP_CTRL_APORTXMASTERDIS_MASK                0x100UL                                    /**< Bit mask for ACMP_APORTXMASTERDIS */
+#define _ACMP_CTRL_APORTXMASTERDIS_DEFAULT             0x00000000UL                               /**< Mode DEFAULT for ACMP_CTRL */
+#define ACMP_CTRL_APORTXMASTERDIS_DEFAULT              (_ACMP_CTRL_APORTXMASTERDIS_DEFAULT << 8)  /**< Shifted mode DEFAULT for ACMP_CTRL */
+#define ACMP_CTRL_APORTYMASTERDIS                      (0x1UL << 9)                               /**< APORT Bus Y Master Disable */
+#define _ACMP_CTRL_APORTYMASTERDIS_SHIFT               9                                          /**< Shift value for ACMP_APORTYMASTERDIS */
+#define _ACMP_CTRL_APORTYMASTERDIS_MASK                0x200UL                                    /**< Bit mask for ACMP_APORTYMASTERDIS */
+#define _ACMP_CTRL_APORTYMASTERDIS_DEFAULT             0x00000000UL                               /**< Mode DEFAULT for ACMP_CTRL */
+#define ACMP_CTRL_APORTYMASTERDIS_DEFAULT              (_ACMP_CTRL_APORTYMASTERDIS_DEFAULT << 9)  /**< Shifted mode DEFAULT for ACMP_CTRL */
+#define ACMP_CTRL_APORTVMASTERDIS                      (0x1UL << 10)                              /**< APORT Bus Master Disable for Bus selected by VASEL */
+#define _ACMP_CTRL_APORTVMASTERDIS_SHIFT               10                                         /**< Shift value for ACMP_APORTVMASTERDIS */
+#define _ACMP_CTRL_APORTVMASTERDIS_MASK                0x400UL                                    /**< Bit mask for ACMP_APORTVMASTERDIS */
+#define _ACMP_CTRL_APORTVMASTERDIS_DEFAULT             0x00000000UL                               /**< Mode DEFAULT for ACMP_CTRL */
+#define ACMP_CTRL_APORTVMASTERDIS_DEFAULT              (_ACMP_CTRL_APORTVMASTERDIS_DEFAULT << 10) /**< Shifted mode DEFAULT for ACMP_CTRL */
+#define _ACMP_CTRL_PWRSEL_SHIFT                        12                                         /**< Shift value for ACMP_PWRSEL */
+#define _ACMP_CTRL_PWRSEL_MASK                         0x7000UL                                   /**< Bit mask for ACMP_PWRSEL */
+#define _ACMP_CTRL_PWRSEL_DEFAULT                      0x00000000UL                               /**< Mode DEFAULT for ACMP_CTRL */
+#define _ACMP_CTRL_PWRSEL_AVDD                         0x00000000UL                               /**< Mode AVDD for ACMP_CTRL */
+#define _ACMP_CTRL_PWRSEL_VREGVDD                      0x00000001UL                               /**< Mode VREGVDD for ACMP_CTRL */
+#define _ACMP_CTRL_PWRSEL_IOVDD0                       0x00000002UL                               /**< Mode IOVDD0 for ACMP_CTRL */
+#define _ACMP_CTRL_PWRSEL_IOVDD1                       0x00000004UL                               /**< Mode IOVDD1 for ACMP_CTRL */
+#define ACMP_CTRL_PWRSEL_DEFAULT                       (_ACMP_CTRL_PWRSEL_DEFAULT << 12)          /**< Shifted mode DEFAULT for ACMP_CTRL */
+#define ACMP_CTRL_PWRSEL_AVDD                          (_ACMP_CTRL_PWRSEL_AVDD << 12)             /**< Shifted mode AVDD for ACMP_CTRL */
+#define ACMP_CTRL_PWRSEL_VREGVDD                       (_ACMP_CTRL_PWRSEL_VREGVDD << 12)          /**< Shifted mode VREGVDD for ACMP_CTRL */
+#define ACMP_CTRL_PWRSEL_IOVDD0                        (_ACMP_CTRL_PWRSEL_IOVDD0 << 12)           /**< Shifted mode IOVDD0 for ACMP_CTRL */
+#define ACMP_CTRL_PWRSEL_IOVDD1                        (_ACMP_CTRL_PWRSEL_IOVDD1 << 12)           /**< Shifted mode IOVDD1 for ACMP_CTRL */
+#define ACMP_CTRL_ACCURACY                             (0x1UL << 15)                              /**< ACMP accuracy mode */
+#define _ACMP_CTRL_ACCURACY_SHIFT                      15                                         /**< Shift value for ACMP_ACCURACY */
+#define _ACMP_CTRL_ACCURACY_MASK                       0x8000UL                                   /**< Bit mask for ACMP_ACCURACY */
+#define _ACMP_CTRL_ACCURACY_DEFAULT                    0x00000000UL                               /**< Mode DEFAULT for ACMP_CTRL */
+#define _ACMP_CTRL_ACCURACY_LOW                        0x00000000UL                               /**< Mode LOW for ACMP_CTRL */
+#define _ACMP_CTRL_ACCURACY_HIGH                       0x00000001UL                               /**< Mode HIGH for ACMP_CTRL */
+#define ACMP_CTRL_ACCURACY_DEFAULT                     (_ACMP_CTRL_ACCURACY_DEFAULT << 15)        /**< Shifted mode DEFAULT for ACMP_CTRL */
+#define ACMP_CTRL_ACCURACY_LOW                         (_ACMP_CTRL_ACCURACY_LOW << 15)            /**< Shifted mode LOW for ACMP_CTRL */
+#define ACMP_CTRL_ACCURACY_HIGH                        (_ACMP_CTRL_ACCURACY_HIGH << 15)           /**< Shifted mode HIGH for ACMP_CTRL */
+#define _ACMP_CTRL_INPUTRANGE_SHIFT                    18                                         /**< Shift value for ACMP_INPUTRANGE */
+#define _ACMP_CTRL_INPUTRANGE_MASK                     0xC0000UL                                  /**< Bit mask for ACMP_INPUTRANGE */
+#define _ACMP_CTRL_INPUTRANGE_DEFAULT                  0x00000000UL                               /**< Mode DEFAULT for ACMP_CTRL */
+#define _ACMP_CTRL_INPUTRANGE_FULL                     0x00000000UL                               /**< Mode FULL for ACMP_CTRL */
+#define _ACMP_CTRL_INPUTRANGE_GTVDDDIV2                0x00000001UL                               /**< Mode GTVDDDIV2 for ACMP_CTRL */
+#define _ACMP_CTRL_INPUTRANGE_LTVDDDIV2                0x00000002UL                               /**< Mode LTVDDDIV2 for ACMP_CTRL */
+#define ACMP_CTRL_INPUTRANGE_DEFAULT                   (_ACMP_CTRL_INPUTRANGE_DEFAULT << 18)      /**< Shifted mode DEFAULT for ACMP_CTRL */
+#define ACMP_CTRL_INPUTRANGE_FULL                      (_ACMP_CTRL_INPUTRANGE_FULL << 18)         /**< Shifted mode FULL for ACMP_CTRL */
+#define ACMP_CTRL_INPUTRANGE_GTVDDDIV2                 (_ACMP_CTRL_INPUTRANGE_GTVDDDIV2 << 18)    /**< Shifted mode GTVDDDIV2 for ACMP_CTRL */
+#define ACMP_CTRL_INPUTRANGE_LTVDDDIV2                 (_ACMP_CTRL_INPUTRANGE_LTVDDDIV2 << 18)    /**< Shifted mode LTVDDDIV2 for ACMP_CTRL */
+#define ACMP_CTRL_IRISE                                (0x1UL << 20)                              /**< Rising Edge Interrupt Sense */
+#define _ACMP_CTRL_IRISE_SHIFT                         20                                         /**< Shift value for ACMP_IRISE */
+#define _ACMP_CTRL_IRISE_MASK                          0x100000UL                                 /**< Bit mask for ACMP_IRISE */
+#define _ACMP_CTRL_IRISE_DEFAULT                       0x00000000UL                               /**< Mode DEFAULT for ACMP_CTRL */
+#define _ACMP_CTRL_IRISE_DISABLED                      0x00000000UL                               /**< Mode DISABLED for ACMP_CTRL */
+#define _ACMP_CTRL_IRISE_ENABLED                       0x00000001UL                               /**< Mode ENABLED for ACMP_CTRL */
+#define ACMP_CTRL_IRISE_DEFAULT                        (_ACMP_CTRL_IRISE_DEFAULT << 20)           /**< Shifted mode DEFAULT for ACMP_CTRL */
+#define ACMP_CTRL_IRISE_DISABLED                       (_ACMP_CTRL_IRISE_DISABLED << 20)          /**< Shifted mode DISABLED for ACMP_CTRL */
+#define ACMP_CTRL_IRISE_ENABLED                        (_ACMP_CTRL_IRISE_ENABLED << 20)           /**< Shifted mode ENABLED for ACMP_CTRL */
+#define ACMP_CTRL_IFALL                                (0x1UL << 21)                              /**< Falling Edge Interrupt Sense */
+#define _ACMP_CTRL_IFALL_SHIFT                         21                                         /**< Shift value for ACMP_IFALL */
+#define _ACMP_CTRL_IFALL_MASK                          0x200000UL                                 /**< Bit mask for ACMP_IFALL */
+#define _ACMP_CTRL_IFALL_DEFAULT                       0x00000000UL                               /**< Mode DEFAULT for ACMP_CTRL */
+#define _ACMP_CTRL_IFALL_DISABLED                      0x00000000UL                               /**< Mode DISABLED for ACMP_CTRL */
+#define _ACMP_CTRL_IFALL_ENABLED                       0x00000001UL                               /**< Mode ENABLED for ACMP_CTRL */
+#define ACMP_CTRL_IFALL_DEFAULT                        (_ACMP_CTRL_IFALL_DEFAULT << 21)           /**< Shifted mode DEFAULT for ACMP_CTRL */
+#define ACMP_CTRL_IFALL_DISABLED                       (_ACMP_CTRL_IFALL_DISABLED << 21)          /**< Shifted mode DISABLED for ACMP_CTRL */
+#define ACMP_CTRL_IFALL_ENABLED                        (_ACMP_CTRL_IFALL_ENABLED << 21)           /**< Shifted mode ENABLED for ACMP_CTRL */
+#define _ACMP_CTRL_BIASPROG_SHIFT                      24                                         /**< Shift value for ACMP_BIASPROG */
+#define _ACMP_CTRL_BIASPROG_MASK                       0x3F000000UL                               /**< Bit mask for ACMP_BIASPROG */
+#define _ACMP_CTRL_BIASPROG_DEFAULT                    0x00000007UL                               /**< Mode DEFAULT for ACMP_CTRL */
+#define ACMP_CTRL_BIASPROG_DEFAULT                     (_ACMP_CTRL_BIASPROG_DEFAULT << 24)        /**< Shifted mode DEFAULT for ACMP_CTRL */
+#define ACMP_CTRL_FULLBIAS                             (0x1UL << 31)                              /**< Full Bias Current */
+#define _ACMP_CTRL_FULLBIAS_SHIFT                      31                                         /**< Shift value for ACMP_FULLBIAS */
+#define _ACMP_CTRL_FULLBIAS_MASK                       0x80000000UL                               /**< Bit mask for ACMP_FULLBIAS */
+#define _ACMP_CTRL_FULLBIAS_DEFAULT                    0x00000000UL                               /**< Mode DEFAULT for ACMP_CTRL */
+#define ACMP_CTRL_FULLBIAS_DEFAULT                     (_ACMP_CTRL_FULLBIAS_DEFAULT << 31)        /**< Shifted mode DEFAULT for ACMP_CTRL */
+
+/* Bit fields for ACMP INPUTSEL */
+#define _ACMP_INPUTSEL_RESETVALUE                      0x00000000UL                             /**< Default value for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_MASK                            0x757FFFFFUL                             /**< Mask for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_SHIFT                    0                                        /**< Shift value for ACMP_POSSEL */
+#define _ACMP_INPUTSEL_POSSEL_MASK                     0xFFUL                                   /**< Bit mask for ACMP_POSSEL */
+#define _ACMP_INPUTSEL_POSSEL_DEFAULT                  0x00000000UL                             /**< Mode DEFAULT for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT0XCH0               0x00000000UL                             /**< Mode APORT0XCH0 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT0XCH1               0x00000001UL                             /**< Mode APORT0XCH1 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT0XCH2               0x00000002UL                             /**< Mode APORT0XCH2 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT0XCH3               0x00000003UL                             /**< Mode APORT0XCH3 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT0XCH4               0x00000004UL                             /**< Mode APORT0XCH4 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT0XCH5               0x00000005UL                             /**< Mode APORT0XCH5 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT0XCH6               0x00000006UL                             /**< Mode APORT0XCH6 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT0XCH7               0x00000007UL                             /**< Mode APORT0XCH7 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT0XCH8               0x00000008UL                             /**< Mode APORT0XCH8 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT0XCH9               0x00000009UL                             /**< Mode APORT0XCH9 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT0XCH10              0x0000000AUL                             /**< Mode APORT0XCH10 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT0XCH11              0x0000000BUL                             /**< Mode APORT0XCH11 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT0XCH12              0x0000000CUL                             /**< Mode APORT0XCH12 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT0XCH13              0x0000000DUL                             /**< Mode APORT0XCH13 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT0XCH14              0x0000000EUL                             /**< Mode APORT0XCH14 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT0XCH15              0x0000000FUL                             /**< Mode APORT0XCH15 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT0YCH0               0x00000010UL                             /**< Mode APORT0YCH0 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT0YCH1               0x00000011UL                             /**< Mode APORT0YCH1 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT0YCH2               0x00000012UL                             /**< Mode APORT0YCH2 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT0YCH3               0x00000013UL                             /**< Mode APORT0YCH3 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT0YCH4               0x00000014UL                             /**< Mode APORT0YCH4 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT0YCH5               0x00000015UL                             /**< Mode APORT0YCH5 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT0YCH6               0x00000016UL                             /**< Mode APORT0YCH6 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT0YCH7               0x00000017UL                             /**< Mode APORT0YCH7 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT0YCH8               0x00000018UL                             /**< Mode APORT0YCH8 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT0YCH9               0x00000019UL                             /**< Mode APORT0YCH9 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT0YCH10              0x0000001AUL                             /**< Mode APORT0YCH10 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT0YCH11              0x0000001BUL                             /**< Mode APORT0YCH11 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT0YCH12              0x0000001CUL                             /**< Mode APORT0YCH12 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT0YCH13              0x0000001DUL                             /**< Mode APORT0YCH13 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT0YCH14              0x0000001EUL                             /**< Mode APORT0YCH14 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT0YCH15              0x0000001FUL                             /**< Mode APORT0YCH15 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT1XCH0               0x00000020UL                             /**< Mode APORT1XCH0 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT1YCH1               0x00000021UL                             /**< Mode APORT1YCH1 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT1XCH2               0x00000022UL                             /**< Mode APORT1XCH2 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT1YCH3               0x00000023UL                             /**< Mode APORT1YCH3 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT1XCH4               0x00000024UL                             /**< Mode APORT1XCH4 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT1YCH5               0x00000025UL                             /**< Mode APORT1YCH5 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT1XCH6               0x00000026UL                             /**< Mode APORT1XCH6 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT1YCH7               0x00000027UL                             /**< Mode APORT1YCH7 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT1XCH8               0x00000028UL                             /**< Mode APORT1XCH8 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT1YCH9               0x00000029UL                             /**< Mode APORT1YCH9 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT1XCH10              0x0000002AUL                             /**< Mode APORT1XCH10 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT1YCH11              0x0000002BUL                             /**< Mode APORT1YCH11 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT1XCH12              0x0000002CUL                             /**< Mode APORT1XCH12 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT1YCH13              0x0000002DUL                             /**< Mode APORT1YCH13 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT1XCH14              0x0000002EUL                             /**< Mode APORT1XCH14 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT1YCH15              0x0000002FUL                             /**< Mode APORT1YCH15 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT1XCH16              0x00000030UL                             /**< Mode APORT1XCH16 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT1YCH17              0x00000031UL                             /**< Mode APORT1YCH17 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT1XCH18              0x00000032UL                             /**< Mode APORT1XCH18 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT1YCH19              0x00000033UL                             /**< Mode APORT1YCH19 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT1XCH20              0x00000034UL                             /**< Mode APORT1XCH20 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT1YCH21              0x00000035UL                             /**< Mode APORT1YCH21 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT1XCH22              0x00000036UL                             /**< Mode APORT1XCH22 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT1YCH23              0x00000037UL                             /**< Mode APORT1YCH23 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT1XCH24              0x00000038UL                             /**< Mode APORT1XCH24 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT1YCH25              0x00000039UL                             /**< Mode APORT1YCH25 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT1XCH26              0x0000003AUL                             /**< Mode APORT1XCH26 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT1YCH27              0x0000003BUL                             /**< Mode APORT1YCH27 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT1XCH28              0x0000003CUL                             /**< Mode APORT1XCH28 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT1YCH29              0x0000003DUL                             /**< Mode APORT1YCH29 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT1XCH30              0x0000003EUL                             /**< Mode APORT1XCH30 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT1YCH31              0x0000003FUL                             /**< Mode APORT1YCH31 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT2YCH0               0x00000040UL                             /**< Mode APORT2YCH0 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT2XCH1               0x00000041UL                             /**< Mode APORT2XCH1 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT2YCH2               0x00000042UL                             /**< Mode APORT2YCH2 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT2XCH3               0x00000043UL                             /**< Mode APORT2XCH3 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT2YCH4               0x00000044UL                             /**< Mode APORT2YCH4 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT2XCH5               0x00000045UL                             /**< Mode APORT2XCH5 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT2YCH6               0x00000046UL                             /**< Mode APORT2YCH6 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT2XCH7               0x00000047UL                             /**< Mode APORT2XCH7 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT2YCH8               0x00000048UL                             /**< Mode APORT2YCH8 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT2XCH9               0x00000049UL                             /**< Mode APORT2XCH9 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT2YCH10              0x0000004AUL                             /**< Mode APORT2YCH10 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT2XCH11              0x0000004BUL                             /**< Mode APORT2XCH11 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT2YCH12              0x0000004CUL                             /**< Mode APORT2YCH12 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT2XCH13              0x0000004DUL                             /**< Mode APORT2XCH13 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT2YCH14              0x0000004EUL                             /**< Mode APORT2YCH14 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT2XCH15              0x0000004FUL                             /**< Mode APORT2XCH15 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT2YCH16              0x00000050UL                             /**< Mode APORT2YCH16 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT2XCH17              0x00000051UL                             /**< Mode APORT2XCH17 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT2YCH18              0x00000052UL                             /**< Mode APORT2YCH18 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT2XCH19              0x00000053UL                             /**< Mode APORT2XCH19 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT2YCH20              0x00000054UL                             /**< Mode APORT2YCH20 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT2XCH21              0x00000055UL                             /**< Mode APORT2XCH21 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT2YCH22              0x00000056UL                             /**< Mode APORT2YCH22 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT2XCH23              0x00000057UL                             /**< Mode APORT2XCH23 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT2YCH24              0x00000058UL                             /**< Mode APORT2YCH24 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT2XCH25              0x00000059UL                             /**< Mode APORT2XCH25 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT2YCH26              0x0000005AUL                             /**< Mode APORT2YCH26 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT2XCH27              0x0000005BUL                             /**< Mode APORT2XCH27 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT2YCH28              0x0000005CUL                             /**< Mode APORT2YCH28 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT2XCH29              0x0000005DUL                             /**< Mode APORT2XCH29 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT2YCH30              0x0000005EUL                             /**< Mode APORT2YCH30 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT2XCH31              0x0000005FUL                             /**< Mode APORT2XCH31 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT3XCH0               0x00000060UL                             /**< Mode APORT3XCH0 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT3YCH1               0x00000061UL                             /**< Mode APORT3YCH1 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT3XCH2               0x00000062UL                             /**< Mode APORT3XCH2 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT3YCH3               0x00000063UL                             /**< Mode APORT3YCH3 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT3XCH4               0x00000064UL                             /**< Mode APORT3XCH4 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT3YCH5               0x00000065UL                             /**< Mode APORT3YCH5 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT3XCH6               0x00000066UL                             /**< Mode APORT3XCH6 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT3YCH7               0x00000067UL                             /**< Mode APORT3YCH7 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT3XCH8               0x00000068UL                             /**< Mode APORT3XCH8 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT3YCH9               0x00000069UL                             /**< Mode APORT3YCH9 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT3XCH10              0x0000006AUL                             /**< Mode APORT3XCH10 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT3YCH11              0x0000006BUL                             /**< Mode APORT3YCH11 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT3XCH12              0x0000006CUL                             /**< Mode APORT3XCH12 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT3YCH13              0x0000006DUL                             /**< Mode APORT3YCH13 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT3XCH14              0x0000006EUL                             /**< Mode APORT3XCH14 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT3YCH15              0x0000006FUL                             /**< Mode APORT3YCH15 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT3XCH16              0x00000070UL                             /**< Mode APORT3XCH16 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT3YCH17              0x00000071UL                             /**< Mode APORT3YCH17 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT3XCH18              0x00000072UL                             /**< Mode APORT3XCH18 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT3YCH19              0x00000073UL                             /**< Mode APORT3YCH19 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT3XCH20              0x00000074UL                             /**< Mode APORT3XCH20 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT3YCH21              0x00000075UL                             /**< Mode APORT3YCH21 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT3XCH22              0x00000076UL                             /**< Mode APORT3XCH22 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT3YCH23              0x00000077UL                             /**< Mode APORT3YCH23 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT3XCH24              0x00000078UL                             /**< Mode APORT3XCH24 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT3YCH25              0x00000079UL                             /**< Mode APORT3YCH25 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT3XCH26              0x0000007AUL                             /**< Mode APORT3XCH26 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT3YCH27              0x0000007BUL                             /**< Mode APORT3YCH27 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT3XCH28              0x0000007CUL                             /**< Mode APORT3XCH28 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT3YCH29              0x0000007DUL                             /**< Mode APORT3YCH29 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT3XCH30              0x0000007EUL                             /**< Mode APORT3XCH30 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT3YCH31              0x0000007FUL                             /**< Mode APORT3YCH31 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT4YCH0               0x00000080UL                             /**< Mode APORT4YCH0 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT4XCH1               0x00000081UL                             /**< Mode APORT4XCH1 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT4YCH2               0x00000082UL                             /**< Mode APORT4YCH2 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT4XCH3               0x00000083UL                             /**< Mode APORT4XCH3 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT4YCH4               0x00000084UL                             /**< Mode APORT4YCH4 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT4XCH5               0x00000085UL                             /**< Mode APORT4XCH5 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT4YCH6               0x00000086UL                             /**< Mode APORT4YCH6 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT4XCH7               0x00000087UL                             /**< Mode APORT4XCH7 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT4YCH8               0x00000088UL                             /**< Mode APORT4YCH8 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT4XCH9               0x00000089UL                             /**< Mode APORT4XCH9 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT4YCH10              0x0000008AUL                             /**< Mode APORT4YCH10 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT4XCH11              0x0000008BUL                             /**< Mode APORT4XCH11 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT4YCH12              0x0000008CUL                             /**< Mode APORT4YCH12 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT4XCH13              0x0000008DUL                             /**< Mode APORT4XCH13 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT4YCH16              0x00000090UL                             /**< Mode APORT4YCH16 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT4XCH17              0x00000091UL                             /**< Mode APORT4XCH17 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT4YCH18              0x00000092UL                             /**< Mode APORT4YCH18 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT4XCH19              0x00000093UL                             /**< Mode APORT4XCH19 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT4YCH20              0x00000094UL                             /**< Mode APORT4YCH20 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT4XCH21              0x00000095UL                             /**< Mode APORT4XCH21 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT4YCH22              0x00000096UL                             /**< Mode APORT4YCH22 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT4XCH23              0x00000097UL                             /**< Mode APORT4XCH23 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT4YCH24              0x00000098UL                             /**< Mode APORT4YCH24 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT4XCH25              0x00000099UL                             /**< Mode APORT4XCH25 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT4YCH26              0x0000009AUL                             /**< Mode APORT4YCH26 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT4XCH27              0x0000009BUL                             /**< Mode APORT4XCH27 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT4YCH28              0x0000009CUL                             /**< Mode APORT4YCH28 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT4XCH29              0x0000009DUL                             /**< Mode APORT4XCH29 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT4YCH30              0x0000009EUL                             /**< Mode APORT4YCH30 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT4YCH14              0x0000009EUL                             /**< Mode APORT4YCH14 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT4XCH15              0x0000009FUL                             /**< Mode APORT4XCH15 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT4XCH31              0x0000009FUL                             /**< Mode APORT4XCH31 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_DACOUT0                  0x000000F2UL                             /**< Mode DACOUT0 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_DACOUT1                  0x000000F3UL                             /**< Mode DACOUT1 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_VLP                      0x000000FBUL                             /**< Mode VLP for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_VBDIV                    0x000000FCUL                             /**< Mode VBDIV for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_VADIV                    0x000000FDUL                             /**< Mode VADIV for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_VDD                      0x000000FEUL                             /**< Mode VDD for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_VSS                      0x000000FFUL                             /**< Mode VSS for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_DEFAULT                   (_ACMP_INPUTSEL_POSSEL_DEFAULT << 0)     /**< Shifted mode DEFAULT for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT0XCH0                (_ACMP_INPUTSEL_POSSEL_APORT0XCH0 << 0)  /**< Shifted mode APORT0XCH0 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT0XCH1                (_ACMP_INPUTSEL_POSSEL_APORT0XCH1 << 0)  /**< Shifted mode APORT0XCH1 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT0XCH2                (_ACMP_INPUTSEL_POSSEL_APORT0XCH2 << 0)  /**< Shifted mode APORT0XCH2 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT0XCH3                (_ACMP_INPUTSEL_POSSEL_APORT0XCH3 << 0)  /**< Shifted mode APORT0XCH3 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT0XCH4                (_ACMP_INPUTSEL_POSSEL_APORT0XCH4 << 0)  /**< Shifted mode APORT0XCH4 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT0XCH5                (_ACMP_INPUTSEL_POSSEL_APORT0XCH5 << 0)  /**< Shifted mode APORT0XCH5 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT0XCH6                (_ACMP_INPUTSEL_POSSEL_APORT0XCH6 << 0)  /**< Shifted mode APORT0XCH6 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT0XCH7                (_ACMP_INPUTSEL_POSSEL_APORT0XCH7 << 0)  /**< Shifted mode APORT0XCH7 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT0XCH8                (_ACMP_INPUTSEL_POSSEL_APORT0XCH8 << 0)  /**< Shifted mode APORT0XCH8 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT0XCH9                (_ACMP_INPUTSEL_POSSEL_APORT0XCH9 << 0)  /**< Shifted mode APORT0XCH9 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT0XCH10               (_ACMP_INPUTSEL_POSSEL_APORT0XCH10 << 0) /**< Shifted mode APORT0XCH10 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT0XCH11               (_ACMP_INPUTSEL_POSSEL_APORT0XCH11 << 0) /**< Shifted mode APORT0XCH11 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT0XCH12               (_ACMP_INPUTSEL_POSSEL_APORT0XCH12 << 0) /**< Shifted mode APORT0XCH12 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT0XCH13               (_ACMP_INPUTSEL_POSSEL_APORT0XCH13 << 0) /**< Shifted mode APORT0XCH13 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT0XCH14               (_ACMP_INPUTSEL_POSSEL_APORT0XCH14 << 0) /**< Shifted mode APORT0XCH14 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT0XCH15               (_ACMP_INPUTSEL_POSSEL_APORT0XCH15 << 0) /**< Shifted mode APORT0XCH15 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT0YCH0                (_ACMP_INPUTSEL_POSSEL_APORT0YCH0 << 0)  /**< Shifted mode APORT0YCH0 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT0YCH1                (_ACMP_INPUTSEL_POSSEL_APORT0YCH1 << 0)  /**< Shifted mode APORT0YCH1 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT0YCH2                (_ACMP_INPUTSEL_POSSEL_APORT0YCH2 << 0)  /**< Shifted mode APORT0YCH2 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT0YCH3                (_ACMP_INPUTSEL_POSSEL_APORT0YCH3 << 0)  /**< Shifted mode APORT0YCH3 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT0YCH4                (_ACMP_INPUTSEL_POSSEL_APORT0YCH4 << 0)  /**< Shifted mode APORT0YCH4 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT0YCH5                (_ACMP_INPUTSEL_POSSEL_APORT0YCH5 << 0)  /**< Shifted mode APORT0YCH5 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT0YCH6                (_ACMP_INPUTSEL_POSSEL_APORT0YCH6 << 0)  /**< Shifted mode APORT0YCH6 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT0YCH7                (_ACMP_INPUTSEL_POSSEL_APORT0YCH7 << 0)  /**< Shifted mode APORT0YCH7 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT0YCH8                (_ACMP_INPUTSEL_POSSEL_APORT0YCH8 << 0)  /**< Shifted mode APORT0YCH8 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT0YCH9                (_ACMP_INPUTSEL_POSSEL_APORT0YCH9 << 0)  /**< Shifted mode APORT0YCH9 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT0YCH10               (_ACMP_INPUTSEL_POSSEL_APORT0YCH10 << 0) /**< Shifted mode APORT0YCH10 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT0YCH11               (_ACMP_INPUTSEL_POSSEL_APORT0YCH11 << 0) /**< Shifted mode APORT0YCH11 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT0YCH12               (_ACMP_INPUTSEL_POSSEL_APORT0YCH12 << 0) /**< Shifted mode APORT0YCH12 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT0YCH13               (_ACMP_INPUTSEL_POSSEL_APORT0YCH13 << 0) /**< Shifted mode APORT0YCH13 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT0YCH14               (_ACMP_INPUTSEL_POSSEL_APORT0YCH14 << 0) /**< Shifted mode APORT0YCH14 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT0YCH15               (_ACMP_INPUTSEL_POSSEL_APORT0YCH15 << 0) /**< Shifted mode APORT0YCH15 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT1XCH0                (_ACMP_INPUTSEL_POSSEL_APORT1XCH0 << 0)  /**< Shifted mode APORT1XCH0 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT1YCH1                (_ACMP_INPUTSEL_POSSEL_APORT1YCH1 << 0)  /**< Shifted mode APORT1YCH1 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT1XCH2                (_ACMP_INPUTSEL_POSSEL_APORT1XCH2 << 0)  /**< Shifted mode APORT1XCH2 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT1YCH3                (_ACMP_INPUTSEL_POSSEL_APORT1YCH3 << 0)  /**< Shifted mode APORT1YCH3 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT1XCH4                (_ACMP_INPUTSEL_POSSEL_APORT1XCH4 << 0)  /**< Shifted mode APORT1XCH4 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT1YCH5                (_ACMP_INPUTSEL_POSSEL_APORT1YCH5 << 0)  /**< Shifted mode APORT1YCH5 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT1XCH6                (_ACMP_INPUTSEL_POSSEL_APORT1XCH6 << 0)  /**< Shifted mode APORT1XCH6 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT1YCH7                (_ACMP_INPUTSEL_POSSEL_APORT1YCH7 << 0)  /**< Shifted mode APORT1YCH7 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT1XCH8                (_ACMP_INPUTSEL_POSSEL_APORT1XCH8 << 0)  /**< Shifted mode APORT1XCH8 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT1YCH9                (_ACMP_INPUTSEL_POSSEL_APORT1YCH9 << 0)  /**< Shifted mode APORT1YCH9 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT1XCH10               (_ACMP_INPUTSEL_POSSEL_APORT1XCH10 << 0) /**< Shifted mode APORT1XCH10 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT1YCH11               (_ACMP_INPUTSEL_POSSEL_APORT1YCH11 << 0) /**< Shifted mode APORT1YCH11 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT1XCH12               (_ACMP_INPUTSEL_POSSEL_APORT1XCH12 << 0) /**< Shifted mode APORT1XCH12 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT1YCH13               (_ACMP_INPUTSEL_POSSEL_APORT1YCH13 << 0) /**< Shifted mode APORT1YCH13 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT1XCH14               (_ACMP_INPUTSEL_POSSEL_APORT1XCH14 << 0) /**< Shifted mode APORT1XCH14 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT1YCH15               (_ACMP_INPUTSEL_POSSEL_APORT1YCH15 << 0) /**< Shifted mode APORT1YCH15 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT1XCH16               (_ACMP_INPUTSEL_POSSEL_APORT1XCH16 << 0) /**< Shifted mode APORT1XCH16 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT1YCH17               (_ACMP_INPUTSEL_POSSEL_APORT1YCH17 << 0) /**< Shifted mode APORT1YCH17 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT1XCH18               (_ACMP_INPUTSEL_POSSEL_APORT1XCH18 << 0) /**< Shifted mode APORT1XCH18 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT1YCH19               (_ACMP_INPUTSEL_POSSEL_APORT1YCH19 << 0) /**< Shifted mode APORT1YCH19 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT1XCH20               (_ACMP_INPUTSEL_POSSEL_APORT1XCH20 << 0) /**< Shifted mode APORT1XCH20 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT1YCH21               (_ACMP_INPUTSEL_POSSEL_APORT1YCH21 << 0) /**< Shifted mode APORT1YCH21 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT1XCH22               (_ACMP_INPUTSEL_POSSEL_APORT1XCH22 << 0) /**< Shifted mode APORT1XCH22 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT1YCH23               (_ACMP_INPUTSEL_POSSEL_APORT1YCH23 << 0) /**< Shifted mode APORT1YCH23 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT1XCH24               (_ACMP_INPUTSEL_POSSEL_APORT1XCH24 << 0) /**< Shifted mode APORT1XCH24 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT1YCH25               (_ACMP_INPUTSEL_POSSEL_APORT1YCH25 << 0) /**< Shifted mode APORT1YCH25 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT1XCH26               (_ACMP_INPUTSEL_POSSEL_APORT1XCH26 << 0) /**< Shifted mode APORT1XCH26 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT1YCH27               (_ACMP_INPUTSEL_POSSEL_APORT1YCH27 << 0) /**< Shifted mode APORT1YCH27 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT1XCH28               (_ACMP_INPUTSEL_POSSEL_APORT1XCH28 << 0) /**< Shifted mode APORT1XCH28 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT1YCH29               (_ACMP_INPUTSEL_POSSEL_APORT1YCH29 << 0) /**< Shifted mode APORT1YCH29 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT1XCH30               (_ACMP_INPUTSEL_POSSEL_APORT1XCH30 << 0) /**< Shifted mode APORT1XCH30 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT1YCH31               (_ACMP_INPUTSEL_POSSEL_APORT1YCH31 << 0) /**< Shifted mode APORT1YCH31 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT2YCH0                (_ACMP_INPUTSEL_POSSEL_APORT2YCH0 << 0)  /**< Shifted mode APORT2YCH0 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT2XCH1                (_ACMP_INPUTSEL_POSSEL_APORT2XCH1 << 0)  /**< Shifted mode APORT2XCH1 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT2YCH2                (_ACMP_INPUTSEL_POSSEL_APORT2YCH2 << 0)  /**< Shifted mode APORT2YCH2 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT2XCH3                (_ACMP_INPUTSEL_POSSEL_APORT2XCH3 << 0)  /**< Shifted mode APORT2XCH3 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT2YCH4                (_ACMP_INPUTSEL_POSSEL_APORT2YCH4 << 0)  /**< Shifted mode APORT2YCH4 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT2XCH5                (_ACMP_INPUTSEL_POSSEL_APORT2XCH5 << 0)  /**< Shifted mode APORT2XCH5 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT2YCH6                (_ACMP_INPUTSEL_POSSEL_APORT2YCH6 << 0)  /**< Shifted mode APORT2YCH6 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT2XCH7                (_ACMP_INPUTSEL_POSSEL_APORT2XCH7 << 0)  /**< Shifted mode APORT2XCH7 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT2YCH8                (_ACMP_INPUTSEL_POSSEL_APORT2YCH8 << 0)  /**< Shifted mode APORT2YCH8 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT2XCH9                (_ACMP_INPUTSEL_POSSEL_APORT2XCH9 << 0)  /**< Shifted mode APORT2XCH9 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT2YCH10               (_ACMP_INPUTSEL_POSSEL_APORT2YCH10 << 0) /**< Shifted mode APORT2YCH10 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT2XCH11               (_ACMP_INPUTSEL_POSSEL_APORT2XCH11 << 0) /**< Shifted mode APORT2XCH11 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT2YCH12               (_ACMP_INPUTSEL_POSSEL_APORT2YCH12 << 0) /**< Shifted mode APORT2YCH12 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT2XCH13               (_ACMP_INPUTSEL_POSSEL_APORT2XCH13 << 0) /**< Shifted mode APORT2XCH13 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT2YCH14               (_ACMP_INPUTSEL_POSSEL_APORT2YCH14 << 0) /**< Shifted mode APORT2YCH14 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT2XCH15               (_ACMP_INPUTSEL_POSSEL_APORT2XCH15 << 0) /**< Shifted mode APORT2XCH15 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT2YCH16               (_ACMP_INPUTSEL_POSSEL_APORT2YCH16 << 0) /**< Shifted mode APORT2YCH16 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT2XCH17               (_ACMP_INPUTSEL_POSSEL_APORT2XCH17 << 0) /**< Shifted mode APORT2XCH17 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT2YCH18               (_ACMP_INPUTSEL_POSSEL_APORT2YCH18 << 0) /**< Shifted mode APORT2YCH18 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT2XCH19               (_ACMP_INPUTSEL_POSSEL_APORT2XCH19 << 0) /**< Shifted mode APORT2XCH19 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT2YCH20               (_ACMP_INPUTSEL_POSSEL_APORT2YCH20 << 0) /**< Shifted mode APORT2YCH20 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT2XCH21               (_ACMP_INPUTSEL_POSSEL_APORT2XCH21 << 0) /**< Shifted mode APORT2XCH21 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT2YCH22               (_ACMP_INPUTSEL_POSSEL_APORT2YCH22 << 0) /**< Shifted mode APORT2YCH22 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT2XCH23               (_ACMP_INPUTSEL_POSSEL_APORT2XCH23 << 0) /**< Shifted mode APORT2XCH23 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT2YCH24               (_ACMP_INPUTSEL_POSSEL_APORT2YCH24 << 0) /**< Shifted mode APORT2YCH24 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT2XCH25               (_ACMP_INPUTSEL_POSSEL_APORT2XCH25 << 0) /**< Shifted mode APORT2XCH25 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT2YCH26               (_ACMP_INPUTSEL_POSSEL_APORT2YCH26 << 0) /**< Shifted mode APORT2YCH26 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT2XCH27               (_ACMP_INPUTSEL_POSSEL_APORT2XCH27 << 0) /**< Shifted mode APORT2XCH27 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT2YCH28               (_ACMP_INPUTSEL_POSSEL_APORT2YCH28 << 0) /**< Shifted mode APORT2YCH28 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT2XCH29               (_ACMP_INPUTSEL_POSSEL_APORT2XCH29 << 0) /**< Shifted mode APORT2XCH29 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT2YCH30               (_ACMP_INPUTSEL_POSSEL_APORT2YCH30 << 0) /**< Shifted mode APORT2YCH30 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT2XCH31               (_ACMP_INPUTSEL_POSSEL_APORT2XCH31 << 0) /**< Shifted mode APORT2XCH31 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT3XCH0                (_ACMP_INPUTSEL_POSSEL_APORT3XCH0 << 0)  /**< Shifted mode APORT3XCH0 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT3YCH1                (_ACMP_INPUTSEL_POSSEL_APORT3YCH1 << 0)  /**< Shifted mode APORT3YCH1 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT3XCH2                (_ACMP_INPUTSEL_POSSEL_APORT3XCH2 << 0)  /**< Shifted mode APORT3XCH2 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT3YCH3                (_ACMP_INPUTSEL_POSSEL_APORT3YCH3 << 0)  /**< Shifted mode APORT3YCH3 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT3XCH4                (_ACMP_INPUTSEL_POSSEL_APORT3XCH4 << 0)  /**< Shifted mode APORT3XCH4 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT3YCH5                (_ACMP_INPUTSEL_POSSEL_APORT3YCH5 << 0)  /**< Shifted mode APORT3YCH5 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT3XCH6                (_ACMP_INPUTSEL_POSSEL_APORT3XCH6 << 0)  /**< Shifted mode APORT3XCH6 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT3YCH7                (_ACMP_INPUTSEL_POSSEL_APORT3YCH7 << 0)  /**< Shifted mode APORT3YCH7 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT3XCH8                (_ACMP_INPUTSEL_POSSEL_APORT3XCH8 << 0)  /**< Shifted mode APORT3XCH8 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT3YCH9                (_ACMP_INPUTSEL_POSSEL_APORT3YCH9 << 0)  /**< Shifted mode APORT3YCH9 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT3XCH10               (_ACMP_INPUTSEL_POSSEL_APORT3XCH10 << 0) /**< Shifted mode APORT3XCH10 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT3YCH11               (_ACMP_INPUTSEL_POSSEL_APORT3YCH11 << 0) /**< Shifted mode APORT3YCH11 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT3XCH12               (_ACMP_INPUTSEL_POSSEL_APORT3XCH12 << 0) /**< Shifted mode APORT3XCH12 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT3YCH13               (_ACMP_INPUTSEL_POSSEL_APORT3YCH13 << 0) /**< Shifted mode APORT3YCH13 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT3XCH14               (_ACMP_INPUTSEL_POSSEL_APORT3XCH14 << 0) /**< Shifted mode APORT3XCH14 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT3YCH15               (_ACMP_INPUTSEL_POSSEL_APORT3YCH15 << 0) /**< Shifted mode APORT3YCH15 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT3XCH16               (_ACMP_INPUTSEL_POSSEL_APORT3XCH16 << 0) /**< Shifted mode APORT3XCH16 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT3YCH17               (_ACMP_INPUTSEL_POSSEL_APORT3YCH17 << 0) /**< Shifted mode APORT3YCH17 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT3XCH18               (_ACMP_INPUTSEL_POSSEL_APORT3XCH18 << 0) /**< Shifted mode APORT3XCH18 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT3YCH19               (_ACMP_INPUTSEL_POSSEL_APORT3YCH19 << 0) /**< Shifted mode APORT3YCH19 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT3XCH20               (_ACMP_INPUTSEL_POSSEL_APORT3XCH20 << 0) /**< Shifted mode APORT3XCH20 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT3YCH21               (_ACMP_INPUTSEL_POSSEL_APORT3YCH21 << 0) /**< Shifted mode APORT3YCH21 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT3XCH22               (_ACMP_INPUTSEL_POSSEL_APORT3XCH22 << 0) /**< Shifted mode APORT3XCH22 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT3YCH23               (_ACMP_INPUTSEL_POSSEL_APORT3YCH23 << 0) /**< Shifted mode APORT3YCH23 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT3XCH24               (_ACMP_INPUTSEL_POSSEL_APORT3XCH24 << 0) /**< Shifted mode APORT3XCH24 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT3YCH25               (_ACMP_INPUTSEL_POSSEL_APORT3YCH25 << 0) /**< Shifted mode APORT3YCH25 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT3XCH26               (_ACMP_INPUTSEL_POSSEL_APORT3XCH26 << 0) /**< Shifted mode APORT3XCH26 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT3YCH27               (_ACMP_INPUTSEL_POSSEL_APORT3YCH27 << 0) /**< Shifted mode APORT3YCH27 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT3XCH28               (_ACMP_INPUTSEL_POSSEL_APORT3XCH28 << 0) /**< Shifted mode APORT3XCH28 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT3YCH29               (_ACMP_INPUTSEL_POSSEL_APORT3YCH29 << 0) /**< Shifted mode APORT3YCH29 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT3XCH30               (_ACMP_INPUTSEL_POSSEL_APORT3XCH30 << 0) /**< Shifted mode APORT3XCH30 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT3YCH31               (_ACMP_INPUTSEL_POSSEL_APORT3YCH31 << 0) /**< Shifted mode APORT3YCH31 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT4YCH0                (_ACMP_INPUTSEL_POSSEL_APORT4YCH0 << 0)  /**< Shifted mode APORT4YCH0 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT4XCH1                (_ACMP_INPUTSEL_POSSEL_APORT4XCH1 << 0)  /**< Shifted mode APORT4XCH1 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT4YCH2                (_ACMP_INPUTSEL_POSSEL_APORT4YCH2 << 0)  /**< Shifted mode APORT4YCH2 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT4XCH3                (_ACMP_INPUTSEL_POSSEL_APORT4XCH3 << 0)  /**< Shifted mode APORT4XCH3 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT4YCH4                (_ACMP_INPUTSEL_POSSEL_APORT4YCH4 << 0)  /**< Shifted mode APORT4YCH4 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT4XCH5                (_ACMP_INPUTSEL_POSSEL_APORT4XCH5 << 0)  /**< Shifted mode APORT4XCH5 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT4YCH6                (_ACMP_INPUTSEL_POSSEL_APORT4YCH6 << 0)  /**< Shifted mode APORT4YCH6 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT4XCH7                (_ACMP_INPUTSEL_POSSEL_APORT4XCH7 << 0)  /**< Shifted mode APORT4XCH7 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT4YCH8                (_ACMP_INPUTSEL_POSSEL_APORT4YCH8 << 0)  /**< Shifted mode APORT4YCH8 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT4XCH9                (_ACMP_INPUTSEL_POSSEL_APORT4XCH9 << 0)  /**< Shifted mode APORT4XCH9 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT4YCH10               (_ACMP_INPUTSEL_POSSEL_APORT4YCH10 << 0) /**< Shifted mode APORT4YCH10 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT4XCH11               (_ACMP_INPUTSEL_POSSEL_APORT4XCH11 << 0) /**< Shifted mode APORT4XCH11 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT4YCH12               (_ACMP_INPUTSEL_POSSEL_APORT4YCH12 << 0) /**< Shifted mode APORT4YCH12 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT4XCH13               (_ACMP_INPUTSEL_POSSEL_APORT4XCH13 << 0) /**< Shifted mode APORT4XCH13 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT4YCH16               (_ACMP_INPUTSEL_POSSEL_APORT4YCH16 << 0) /**< Shifted mode APORT4YCH16 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT4XCH17               (_ACMP_INPUTSEL_POSSEL_APORT4XCH17 << 0) /**< Shifted mode APORT4XCH17 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT4YCH18               (_ACMP_INPUTSEL_POSSEL_APORT4YCH18 << 0) /**< Shifted mode APORT4YCH18 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT4XCH19               (_ACMP_INPUTSEL_POSSEL_APORT4XCH19 << 0) /**< Shifted mode APORT4XCH19 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT4YCH20               (_ACMP_INPUTSEL_POSSEL_APORT4YCH20 << 0) /**< Shifted mode APORT4YCH20 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT4XCH21               (_ACMP_INPUTSEL_POSSEL_APORT4XCH21 << 0) /**< Shifted mode APORT4XCH21 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT4YCH22               (_ACMP_INPUTSEL_POSSEL_APORT4YCH22 << 0) /**< Shifted mode APORT4YCH22 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT4XCH23               (_ACMP_INPUTSEL_POSSEL_APORT4XCH23 << 0) /**< Shifted mode APORT4XCH23 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT4YCH24               (_ACMP_INPUTSEL_POSSEL_APORT4YCH24 << 0) /**< Shifted mode APORT4YCH24 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT4XCH25               (_ACMP_INPUTSEL_POSSEL_APORT4XCH25 << 0) /**< Shifted mode APORT4XCH25 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT4YCH26               (_ACMP_INPUTSEL_POSSEL_APORT4YCH26 << 0) /**< Shifted mode APORT4YCH26 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT4XCH27               (_ACMP_INPUTSEL_POSSEL_APORT4XCH27 << 0) /**< Shifted mode APORT4XCH27 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT4YCH28               (_ACMP_INPUTSEL_POSSEL_APORT4YCH28 << 0) /**< Shifted mode APORT4YCH28 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT4XCH29               (_ACMP_INPUTSEL_POSSEL_APORT4XCH29 << 0) /**< Shifted mode APORT4XCH29 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT4YCH30               (_ACMP_INPUTSEL_POSSEL_APORT4YCH30 << 0) /**< Shifted mode APORT4YCH30 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT4YCH14               (_ACMP_INPUTSEL_POSSEL_APORT4YCH14 << 0) /**< Shifted mode APORT4YCH14 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT4XCH15               (_ACMP_INPUTSEL_POSSEL_APORT4XCH15 << 0) /**< Shifted mode APORT4XCH15 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT4XCH31               (_ACMP_INPUTSEL_POSSEL_APORT4XCH31 << 0) /**< Shifted mode APORT4XCH31 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_DACOUT0                   (_ACMP_INPUTSEL_POSSEL_DACOUT0 << 0)     /**< Shifted mode DACOUT0 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_DACOUT1                   (_ACMP_INPUTSEL_POSSEL_DACOUT1 << 0)     /**< Shifted mode DACOUT1 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_VLP                       (_ACMP_INPUTSEL_POSSEL_VLP << 0)         /**< Shifted mode VLP for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_VBDIV                     (_ACMP_INPUTSEL_POSSEL_VBDIV << 0)       /**< Shifted mode VBDIV for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_VADIV                     (_ACMP_INPUTSEL_POSSEL_VADIV << 0)       /**< Shifted mode VADIV for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_VDD                       (_ACMP_INPUTSEL_POSSEL_VDD << 0)         /**< Shifted mode VDD for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_VSS                       (_ACMP_INPUTSEL_POSSEL_VSS << 0)         /**< Shifted mode VSS for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_SHIFT                    8                                        /**< Shift value for ACMP_NEGSEL */
+#define _ACMP_INPUTSEL_NEGSEL_MASK                     0xFF00UL                                 /**< Bit mask for ACMP_NEGSEL */
+#define _ACMP_INPUTSEL_NEGSEL_DEFAULT                  0x00000000UL                             /**< Mode DEFAULT for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH0               0x00000000UL                             /**< Mode APORT0XCH0 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH1               0x00000001UL                             /**< Mode APORT0XCH1 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH2               0x00000002UL                             /**< Mode APORT0XCH2 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH3               0x00000003UL                             /**< Mode APORT0XCH3 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH4               0x00000004UL                             /**< Mode APORT0XCH4 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH5               0x00000005UL                             /**< Mode APORT0XCH5 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH6               0x00000006UL                             /**< Mode APORT0XCH6 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH7               0x00000007UL                             /**< Mode APORT0XCH7 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH8               0x00000008UL                             /**< Mode APORT0XCH8 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH9               0x00000009UL                             /**< Mode APORT0XCH9 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH10              0x0000000AUL                             /**< Mode APORT0XCH10 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH11              0x0000000BUL                             /**< Mode APORT0XCH11 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH12              0x0000000CUL                             /**< Mode APORT0XCH12 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH13              0x0000000DUL                             /**< Mode APORT0XCH13 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH14              0x0000000EUL                             /**< Mode APORT0XCH14 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH15              0x0000000FUL                             /**< Mode APORT0XCH15 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH0               0x00000010UL                             /**< Mode APORT0YCH0 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH1               0x00000011UL                             /**< Mode APORT0YCH1 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH2               0x00000012UL                             /**< Mode APORT0YCH2 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH3               0x00000013UL                             /**< Mode APORT0YCH3 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH4               0x00000014UL                             /**< Mode APORT0YCH4 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH5               0x00000015UL                             /**< Mode APORT0YCH5 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH6               0x00000016UL                             /**< Mode APORT0YCH6 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH7               0x00000017UL                             /**< Mode APORT0YCH7 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH8               0x00000018UL                             /**< Mode APORT0YCH8 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH9               0x00000019UL                             /**< Mode APORT0YCH9 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH10              0x0000001AUL                             /**< Mode APORT0YCH10 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH11              0x0000001BUL                             /**< Mode APORT0YCH11 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH12              0x0000001CUL                             /**< Mode APORT0YCH12 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH13              0x0000001DUL                             /**< Mode APORT0YCH13 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH14              0x0000001EUL                             /**< Mode APORT0YCH14 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH15              0x0000001FUL                             /**< Mode APORT0YCH15 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH0               0x00000020UL                             /**< Mode APORT1XCH0 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH1               0x00000021UL                             /**< Mode APORT1YCH1 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH2               0x00000022UL                             /**< Mode APORT1XCH2 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH3               0x00000023UL                             /**< Mode APORT1YCH3 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH4               0x00000024UL                             /**< Mode APORT1XCH4 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH5               0x00000025UL                             /**< Mode APORT1YCH5 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH6               0x00000026UL                             /**< Mode APORT1XCH6 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH7               0x00000027UL                             /**< Mode APORT1YCH7 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH8               0x00000028UL                             /**< Mode APORT1XCH8 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH9               0x00000029UL                             /**< Mode APORT1YCH9 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH10              0x0000002AUL                             /**< Mode APORT1XCH10 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH11              0x0000002BUL                             /**< Mode APORT1YCH11 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH12              0x0000002CUL                             /**< Mode APORT1XCH12 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH13              0x0000002DUL                             /**< Mode APORT1YCH13 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH14              0x0000002EUL                             /**< Mode APORT1XCH14 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH15              0x0000002FUL                             /**< Mode APORT1YCH15 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH16              0x00000030UL                             /**< Mode APORT1XCH16 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH17              0x00000031UL                             /**< Mode APORT1YCH17 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH18              0x00000032UL                             /**< Mode APORT1XCH18 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH19              0x00000033UL                             /**< Mode APORT1YCH19 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH20              0x00000034UL                             /**< Mode APORT1XCH20 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH21              0x00000035UL                             /**< Mode APORT1YCH21 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH22              0x00000036UL                             /**< Mode APORT1XCH22 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH23              0x00000037UL                             /**< Mode APORT1YCH23 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH24              0x00000038UL                             /**< Mode APORT1XCH24 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH25              0x00000039UL                             /**< Mode APORT1YCH25 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH26              0x0000003AUL                             /**< Mode APORT1XCH26 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH27              0x0000003BUL                             /**< Mode APORT1YCH27 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH28              0x0000003CUL                             /**< Mode APORT1XCH28 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH29              0x0000003DUL                             /**< Mode APORT1YCH29 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH30              0x0000003EUL                             /**< Mode APORT1XCH30 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH31              0x0000003FUL                             /**< Mode APORT1YCH31 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH0               0x00000040UL                             /**< Mode APORT2YCH0 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH1               0x00000041UL                             /**< Mode APORT2XCH1 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH2               0x00000042UL                             /**< Mode APORT2YCH2 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH3               0x00000043UL                             /**< Mode APORT2XCH3 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH4               0x00000044UL                             /**< Mode APORT2YCH4 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH5               0x00000045UL                             /**< Mode APORT2XCH5 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH6               0x00000046UL                             /**< Mode APORT2YCH6 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH7               0x00000047UL                             /**< Mode APORT2XCH7 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH8               0x00000048UL                             /**< Mode APORT2YCH8 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH9               0x00000049UL                             /**< Mode APORT2XCH9 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH10              0x0000004AUL                             /**< Mode APORT2YCH10 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH11              0x0000004BUL                             /**< Mode APORT2XCH11 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH12              0x0000004CUL                             /**< Mode APORT2YCH12 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH13              0x0000004DUL                             /**< Mode APORT2XCH13 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH14              0x0000004EUL                             /**< Mode APORT2YCH14 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH15              0x0000004FUL                             /**< Mode APORT2XCH15 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH16              0x00000050UL                             /**< Mode APORT2YCH16 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH17              0x00000051UL                             /**< Mode APORT2XCH17 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH18              0x00000052UL                             /**< Mode APORT2YCH18 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH19              0x00000053UL                             /**< Mode APORT2XCH19 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH20              0x00000054UL                             /**< Mode APORT2YCH20 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH21              0x00000055UL                             /**< Mode APORT2XCH21 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH22              0x00000056UL                             /**< Mode APORT2YCH22 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH23              0x00000057UL                             /**< Mode APORT2XCH23 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH24              0x00000058UL                             /**< Mode APORT2YCH24 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH25              0x00000059UL                             /**< Mode APORT2XCH25 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH26              0x0000005AUL                             /**< Mode APORT2YCH26 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH27              0x0000005BUL                             /**< Mode APORT2XCH27 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH28              0x0000005CUL                             /**< Mode APORT2YCH28 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH29              0x0000005DUL                             /**< Mode APORT2XCH29 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH30              0x0000005EUL                             /**< Mode APORT2YCH30 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH31              0x0000005FUL                             /**< Mode APORT2XCH31 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH0               0x00000060UL                             /**< Mode APORT3XCH0 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH1               0x00000061UL                             /**< Mode APORT3YCH1 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH2               0x00000062UL                             /**< Mode APORT3XCH2 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH3               0x00000063UL                             /**< Mode APORT3YCH3 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH4               0x00000064UL                             /**< Mode APORT3XCH4 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH5               0x00000065UL                             /**< Mode APORT3YCH5 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH6               0x00000066UL                             /**< Mode APORT3XCH6 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH7               0x00000067UL                             /**< Mode APORT3YCH7 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH8               0x00000068UL                             /**< Mode APORT3XCH8 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH9               0x00000069UL                             /**< Mode APORT3YCH9 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH10              0x0000006AUL                             /**< Mode APORT3XCH10 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH11              0x0000006BUL                             /**< Mode APORT3YCH11 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH12              0x0000006CUL                             /**< Mode APORT3XCH12 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH13              0x0000006DUL                             /**< Mode APORT3YCH13 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH14              0x0000006EUL                             /**< Mode APORT3XCH14 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH15              0x0000006FUL                             /**< Mode APORT3YCH15 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH16              0x00000070UL                             /**< Mode APORT3XCH16 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH17              0x00000071UL                             /**< Mode APORT3YCH17 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH18              0x00000072UL                             /**< Mode APORT3XCH18 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH19              0x00000073UL                             /**< Mode APORT3YCH19 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH20              0x00000074UL                             /**< Mode APORT3XCH20 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH21              0x00000075UL                             /**< Mode APORT3YCH21 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH22              0x00000076UL                             /**< Mode APORT3XCH22 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH23              0x00000077UL                             /**< Mode APORT3YCH23 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH24              0x00000078UL                             /**< Mode APORT3XCH24 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH25              0x00000079UL                             /**< Mode APORT3YCH25 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH26              0x0000007AUL                             /**< Mode APORT3XCH26 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH27              0x0000007BUL                             /**< Mode APORT3YCH27 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH28              0x0000007CUL                             /**< Mode APORT3XCH28 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH29              0x0000007DUL                             /**< Mode APORT3YCH29 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH30              0x0000007EUL                             /**< Mode APORT3XCH30 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH31              0x0000007FUL                             /**< Mode APORT3YCH31 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH0               0x00000080UL                             /**< Mode APORT4YCH0 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH1               0x00000081UL                             /**< Mode APORT4XCH1 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH2               0x00000082UL                             /**< Mode APORT4YCH2 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH3               0x00000083UL                             /**< Mode APORT4XCH3 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH4               0x00000084UL                             /**< Mode APORT4YCH4 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH5               0x00000085UL                             /**< Mode APORT4XCH5 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH6               0x00000086UL                             /**< Mode APORT4YCH6 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH7               0x00000087UL                             /**< Mode APORT4XCH7 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH8               0x00000088UL                             /**< Mode APORT4YCH8 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH9               0x00000089UL                             /**< Mode APORT4XCH9 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH10              0x0000008AUL                             /**< Mode APORT4YCH10 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH11              0x0000008BUL                             /**< Mode APORT4XCH11 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH12              0x0000008CUL                             /**< Mode APORT4YCH12 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH13              0x0000008DUL                             /**< Mode APORT4XCH13 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH16              0x00000090UL                             /**< Mode APORT4YCH16 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH17              0x00000091UL                             /**< Mode APORT4XCH17 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH18              0x00000092UL                             /**< Mode APORT4YCH18 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH19              0x00000093UL                             /**< Mode APORT4XCH19 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH20              0x00000094UL                             /**< Mode APORT4YCH20 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH21              0x00000095UL                             /**< Mode APORT4XCH21 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH22              0x00000096UL                             /**< Mode APORT4YCH22 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH23              0x00000097UL                             /**< Mode APORT4XCH23 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH24              0x00000098UL                             /**< Mode APORT4YCH24 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH25              0x00000099UL                             /**< Mode APORT4XCH25 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH26              0x0000009AUL                             /**< Mode APORT4YCH26 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH27              0x0000009BUL                             /**< Mode APORT4XCH27 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH28              0x0000009CUL                             /**< Mode APORT4YCH28 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH29              0x0000009DUL                             /**< Mode APORT4XCH29 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH30              0x0000009EUL                             /**< Mode APORT4YCH30 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH14              0x0000009EUL                             /**< Mode APORT4YCH14 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH15              0x0000009FUL                             /**< Mode APORT4XCH15 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH31              0x0000009FUL                             /**< Mode APORT4XCH31 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_DACOUT0                  0x000000F2UL                             /**< Mode DACOUT0 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_DACOUT1                  0x000000F3UL                             /**< Mode DACOUT1 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_VLP                      0x000000FBUL                             /**< Mode VLP for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_VBDIV                    0x000000FCUL                             /**< Mode VBDIV for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_VADIV                    0x000000FDUL                             /**< Mode VADIV for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_VDD                      0x000000FEUL                             /**< Mode VDD for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_VSS                      0x000000FFUL                             /**< Mode VSS for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_DEFAULT                   (_ACMP_INPUTSEL_NEGSEL_DEFAULT << 8)     /**< Shifted mode DEFAULT for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT0XCH0                (_ACMP_INPUTSEL_NEGSEL_APORT0XCH0 << 8)  /**< Shifted mode APORT0XCH0 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT0XCH1                (_ACMP_INPUTSEL_NEGSEL_APORT0XCH1 << 8)  /**< Shifted mode APORT0XCH1 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT0XCH2                (_ACMP_INPUTSEL_NEGSEL_APORT0XCH2 << 8)  /**< Shifted mode APORT0XCH2 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT0XCH3                (_ACMP_INPUTSEL_NEGSEL_APORT0XCH3 << 8)  /**< Shifted mode APORT0XCH3 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT0XCH4                (_ACMP_INPUTSEL_NEGSEL_APORT0XCH4 << 8)  /**< Shifted mode APORT0XCH4 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT0XCH5                (_ACMP_INPUTSEL_NEGSEL_APORT0XCH5 << 8)  /**< Shifted mode APORT0XCH5 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT0XCH6                (_ACMP_INPUTSEL_NEGSEL_APORT0XCH6 << 8)  /**< Shifted mode APORT0XCH6 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT0XCH7                (_ACMP_INPUTSEL_NEGSEL_APORT0XCH7 << 8)  /**< Shifted mode APORT0XCH7 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT0XCH8                (_ACMP_INPUTSEL_NEGSEL_APORT0XCH8 << 8)  /**< Shifted mode APORT0XCH8 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT0XCH9                (_ACMP_INPUTSEL_NEGSEL_APORT0XCH9 << 8)  /**< Shifted mode APORT0XCH9 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT0XCH10               (_ACMP_INPUTSEL_NEGSEL_APORT0XCH10 << 8) /**< Shifted mode APORT0XCH10 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT0XCH11               (_ACMP_INPUTSEL_NEGSEL_APORT0XCH11 << 8) /**< Shifted mode APORT0XCH11 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT0XCH12               (_ACMP_INPUTSEL_NEGSEL_APORT0XCH12 << 8) /**< Shifted mode APORT0XCH12 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT0XCH13               (_ACMP_INPUTSEL_NEGSEL_APORT0XCH13 << 8) /**< Shifted mode APORT0XCH13 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT0XCH14               (_ACMP_INPUTSEL_NEGSEL_APORT0XCH14 << 8) /**< Shifted mode APORT0XCH14 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT0XCH15               (_ACMP_INPUTSEL_NEGSEL_APORT0XCH15 << 8) /**< Shifted mode APORT0XCH15 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT0YCH0                (_ACMP_INPUTSEL_NEGSEL_APORT0YCH0 << 8)  /**< Shifted mode APORT0YCH0 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT0YCH1                (_ACMP_INPUTSEL_NEGSEL_APORT0YCH1 << 8)  /**< Shifted mode APORT0YCH1 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT0YCH2                (_ACMP_INPUTSEL_NEGSEL_APORT0YCH2 << 8)  /**< Shifted mode APORT0YCH2 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT0YCH3                (_ACMP_INPUTSEL_NEGSEL_APORT0YCH3 << 8)  /**< Shifted mode APORT0YCH3 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT0YCH4                (_ACMP_INPUTSEL_NEGSEL_APORT0YCH4 << 8)  /**< Shifted mode APORT0YCH4 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT0YCH5                (_ACMP_INPUTSEL_NEGSEL_APORT0YCH5 << 8)  /**< Shifted mode APORT0YCH5 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT0YCH6                (_ACMP_INPUTSEL_NEGSEL_APORT0YCH6 << 8)  /**< Shifted mode APORT0YCH6 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT0YCH7                (_ACMP_INPUTSEL_NEGSEL_APORT0YCH7 << 8)  /**< Shifted mode APORT0YCH7 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT0YCH8                (_ACMP_INPUTSEL_NEGSEL_APORT0YCH8 << 8)  /**< Shifted mode APORT0YCH8 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT0YCH9                (_ACMP_INPUTSEL_NEGSEL_APORT0YCH9 << 8)  /**< Shifted mode APORT0YCH9 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT0YCH10               (_ACMP_INPUTSEL_NEGSEL_APORT0YCH10 << 8) /**< Shifted mode APORT0YCH10 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT0YCH11               (_ACMP_INPUTSEL_NEGSEL_APORT0YCH11 << 8) /**< Shifted mode APORT0YCH11 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT0YCH12               (_ACMP_INPUTSEL_NEGSEL_APORT0YCH12 << 8) /**< Shifted mode APORT0YCH12 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT0YCH13               (_ACMP_INPUTSEL_NEGSEL_APORT0YCH13 << 8) /**< Shifted mode APORT0YCH13 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT0YCH14               (_ACMP_INPUTSEL_NEGSEL_APORT0YCH14 << 8) /**< Shifted mode APORT0YCH14 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT0YCH15               (_ACMP_INPUTSEL_NEGSEL_APORT0YCH15 << 8) /**< Shifted mode APORT0YCH15 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT1XCH0                (_ACMP_INPUTSEL_NEGSEL_APORT1XCH0 << 8)  /**< Shifted mode APORT1XCH0 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT1YCH1                (_ACMP_INPUTSEL_NEGSEL_APORT1YCH1 << 8)  /**< Shifted mode APORT1YCH1 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT1XCH2                (_ACMP_INPUTSEL_NEGSEL_APORT1XCH2 << 8)  /**< Shifted mode APORT1XCH2 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT1YCH3                (_ACMP_INPUTSEL_NEGSEL_APORT1YCH3 << 8)  /**< Shifted mode APORT1YCH3 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT1XCH4                (_ACMP_INPUTSEL_NEGSEL_APORT1XCH4 << 8)  /**< Shifted mode APORT1XCH4 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT1YCH5                (_ACMP_INPUTSEL_NEGSEL_APORT1YCH5 << 8)  /**< Shifted mode APORT1YCH5 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT1XCH6                (_ACMP_INPUTSEL_NEGSEL_APORT1XCH6 << 8)  /**< Shifted mode APORT1XCH6 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT1YCH7                (_ACMP_INPUTSEL_NEGSEL_APORT1YCH7 << 8)  /**< Shifted mode APORT1YCH7 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT1XCH8                (_ACMP_INPUTSEL_NEGSEL_APORT1XCH8 << 8)  /**< Shifted mode APORT1XCH8 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT1YCH9                (_ACMP_INPUTSEL_NEGSEL_APORT1YCH9 << 8)  /**< Shifted mode APORT1YCH9 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT1XCH10               (_ACMP_INPUTSEL_NEGSEL_APORT1XCH10 << 8) /**< Shifted mode APORT1XCH10 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT1YCH11               (_ACMP_INPUTSEL_NEGSEL_APORT1YCH11 << 8) /**< Shifted mode APORT1YCH11 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT1XCH12               (_ACMP_INPUTSEL_NEGSEL_APORT1XCH12 << 8) /**< Shifted mode APORT1XCH12 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT1YCH13               (_ACMP_INPUTSEL_NEGSEL_APORT1YCH13 << 8) /**< Shifted mode APORT1YCH13 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT1XCH14               (_ACMP_INPUTSEL_NEGSEL_APORT1XCH14 << 8) /**< Shifted mode APORT1XCH14 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT1YCH15               (_ACMP_INPUTSEL_NEGSEL_APORT1YCH15 << 8) /**< Shifted mode APORT1YCH15 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT1XCH16               (_ACMP_INPUTSEL_NEGSEL_APORT1XCH16 << 8) /**< Shifted mode APORT1XCH16 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT1YCH17               (_ACMP_INPUTSEL_NEGSEL_APORT1YCH17 << 8) /**< Shifted mode APORT1YCH17 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT1XCH18               (_ACMP_INPUTSEL_NEGSEL_APORT1XCH18 << 8) /**< Shifted mode APORT1XCH18 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT1YCH19               (_ACMP_INPUTSEL_NEGSEL_APORT1YCH19 << 8) /**< Shifted mode APORT1YCH19 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT1XCH20               (_ACMP_INPUTSEL_NEGSEL_APORT1XCH20 << 8) /**< Shifted mode APORT1XCH20 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT1YCH21               (_ACMP_INPUTSEL_NEGSEL_APORT1YCH21 << 8) /**< Shifted mode APORT1YCH21 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT1XCH22               (_ACMP_INPUTSEL_NEGSEL_APORT1XCH22 << 8) /**< Shifted mode APORT1XCH22 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT1YCH23               (_ACMP_INPUTSEL_NEGSEL_APORT1YCH23 << 8) /**< Shifted mode APORT1YCH23 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT1XCH24               (_ACMP_INPUTSEL_NEGSEL_APORT1XCH24 << 8) /**< Shifted mode APORT1XCH24 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT1YCH25               (_ACMP_INPUTSEL_NEGSEL_APORT1YCH25 << 8) /**< Shifted mode APORT1YCH25 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT1XCH26               (_ACMP_INPUTSEL_NEGSEL_APORT1XCH26 << 8) /**< Shifted mode APORT1XCH26 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT1YCH27               (_ACMP_INPUTSEL_NEGSEL_APORT1YCH27 << 8) /**< Shifted mode APORT1YCH27 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT1XCH28               (_ACMP_INPUTSEL_NEGSEL_APORT1XCH28 << 8) /**< Shifted mode APORT1XCH28 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT1YCH29               (_ACMP_INPUTSEL_NEGSEL_APORT1YCH29 << 8) /**< Shifted mode APORT1YCH29 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT1XCH30               (_ACMP_INPUTSEL_NEGSEL_APORT1XCH30 << 8) /**< Shifted mode APORT1XCH30 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT1YCH31               (_ACMP_INPUTSEL_NEGSEL_APORT1YCH31 << 8) /**< Shifted mode APORT1YCH31 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT2YCH0                (_ACMP_INPUTSEL_NEGSEL_APORT2YCH0 << 8)  /**< Shifted mode APORT2YCH0 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT2XCH1                (_ACMP_INPUTSEL_NEGSEL_APORT2XCH1 << 8)  /**< Shifted mode APORT2XCH1 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT2YCH2                (_ACMP_INPUTSEL_NEGSEL_APORT2YCH2 << 8)  /**< Shifted mode APORT2YCH2 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT2XCH3                (_ACMP_INPUTSEL_NEGSEL_APORT2XCH3 << 8)  /**< Shifted mode APORT2XCH3 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT2YCH4                (_ACMP_INPUTSEL_NEGSEL_APORT2YCH4 << 8)  /**< Shifted mode APORT2YCH4 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT2XCH5                (_ACMP_INPUTSEL_NEGSEL_APORT2XCH5 << 8)  /**< Shifted mode APORT2XCH5 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT2YCH6                (_ACMP_INPUTSEL_NEGSEL_APORT2YCH6 << 8)  /**< Shifted mode APORT2YCH6 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT2XCH7                (_ACMP_INPUTSEL_NEGSEL_APORT2XCH7 << 8)  /**< Shifted mode APORT2XCH7 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT2YCH8                (_ACMP_INPUTSEL_NEGSEL_APORT2YCH8 << 8)  /**< Shifted mode APORT2YCH8 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT2XCH9                (_ACMP_INPUTSEL_NEGSEL_APORT2XCH9 << 8)  /**< Shifted mode APORT2XCH9 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT2YCH10               (_ACMP_INPUTSEL_NEGSEL_APORT2YCH10 << 8) /**< Shifted mode APORT2YCH10 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT2XCH11               (_ACMP_INPUTSEL_NEGSEL_APORT2XCH11 << 8) /**< Shifted mode APORT2XCH11 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT2YCH12               (_ACMP_INPUTSEL_NEGSEL_APORT2YCH12 << 8) /**< Shifted mode APORT2YCH12 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT2XCH13               (_ACMP_INPUTSEL_NEGSEL_APORT2XCH13 << 8) /**< Shifted mode APORT2XCH13 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT2YCH14               (_ACMP_INPUTSEL_NEGSEL_APORT2YCH14 << 8) /**< Shifted mode APORT2YCH14 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT2XCH15               (_ACMP_INPUTSEL_NEGSEL_APORT2XCH15 << 8) /**< Shifted mode APORT2XCH15 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT2YCH16               (_ACMP_INPUTSEL_NEGSEL_APORT2YCH16 << 8) /**< Shifted mode APORT2YCH16 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT2XCH17               (_ACMP_INPUTSEL_NEGSEL_APORT2XCH17 << 8) /**< Shifted mode APORT2XCH17 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT2YCH18               (_ACMP_INPUTSEL_NEGSEL_APORT2YCH18 << 8) /**< Shifted mode APORT2YCH18 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT2XCH19               (_ACMP_INPUTSEL_NEGSEL_APORT2XCH19 << 8) /**< Shifted mode APORT2XCH19 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT2YCH20               (_ACMP_INPUTSEL_NEGSEL_APORT2YCH20 << 8) /**< Shifted mode APORT2YCH20 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT2XCH21               (_ACMP_INPUTSEL_NEGSEL_APORT2XCH21 << 8) /**< Shifted mode APORT2XCH21 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT2YCH22               (_ACMP_INPUTSEL_NEGSEL_APORT2YCH22 << 8) /**< Shifted mode APORT2YCH22 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT2XCH23               (_ACMP_INPUTSEL_NEGSEL_APORT2XCH23 << 8) /**< Shifted mode APORT2XCH23 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT2YCH24               (_ACMP_INPUTSEL_NEGSEL_APORT2YCH24 << 8) /**< Shifted mode APORT2YCH24 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT2XCH25               (_ACMP_INPUTSEL_NEGSEL_APORT2XCH25 << 8) /**< Shifted mode APORT2XCH25 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT2YCH26               (_ACMP_INPUTSEL_NEGSEL_APORT2YCH26 << 8) /**< Shifted mode APORT2YCH26 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT2XCH27               (_ACMP_INPUTSEL_NEGSEL_APORT2XCH27 << 8) /**< Shifted mode APORT2XCH27 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT2YCH28               (_ACMP_INPUTSEL_NEGSEL_APORT2YCH28 << 8) /**< Shifted mode APORT2YCH28 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT2XCH29               (_ACMP_INPUTSEL_NEGSEL_APORT2XCH29 << 8) /**< Shifted mode APORT2XCH29 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT2YCH30               (_ACMP_INPUTSEL_NEGSEL_APORT2YCH30 << 8) /**< Shifted mode APORT2YCH30 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT2XCH31               (_ACMP_INPUTSEL_NEGSEL_APORT2XCH31 << 8) /**< Shifted mode APORT2XCH31 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT3XCH0                (_ACMP_INPUTSEL_NEGSEL_APORT3XCH0 << 8)  /**< Shifted mode APORT3XCH0 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT3YCH1                (_ACMP_INPUTSEL_NEGSEL_APORT3YCH1 << 8)  /**< Shifted mode APORT3YCH1 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT3XCH2                (_ACMP_INPUTSEL_NEGSEL_APORT3XCH2 << 8)  /**< Shifted mode APORT3XCH2 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT3YCH3                (_ACMP_INPUTSEL_NEGSEL_APORT3YCH3 << 8)  /**< Shifted mode APORT3YCH3 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT3XCH4                (_ACMP_INPUTSEL_NEGSEL_APORT3XCH4 << 8)  /**< Shifted mode APORT3XCH4 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT3YCH5                (_ACMP_INPUTSEL_NEGSEL_APORT3YCH5 << 8)  /**< Shifted mode APORT3YCH5 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT3XCH6                (_ACMP_INPUTSEL_NEGSEL_APORT3XCH6 << 8)  /**< Shifted mode APORT3XCH6 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT3YCH7                (_ACMP_INPUTSEL_NEGSEL_APORT3YCH7 << 8)  /**< Shifted mode APORT3YCH7 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT3XCH8                (_ACMP_INPUTSEL_NEGSEL_APORT3XCH8 << 8)  /**< Shifted mode APORT3XCH8 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT3YCH9                (_ACMP_INPUTSEL_NEGSEL_APORT3YCH9 << 8)  /**< Shifted mode APORT3YCH9 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT3XCH10               (_ACMP_INPUTSEL_NEGSEL_APORT3XCH10 << 8) /**< Shifted mode APORT3XCH10 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT3YCH11               (_ACMP_INPUTSEL_NEGSEL_APORT3YCH11 << 8) /**< Shifted mode APORT3YCH11 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT3XCH12               (_ACMP_INPUTSEL_NEGSEL_APORT3XCH12 << 8) /**< Shifted mode APORT3XCH12 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT3YCH13               (_ACMP_INPUTSEL_NEGSEL_APORT3YCH13 << 8) /**< Shifted mode APORT3YCH13 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT3XCH14               (_ACMP_INPUTSEL_NEGSEL_APORT3XCH14 << 8) /**< Shifted mode APORT3XCH14 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT3YCH15               (_ACMP_INPUTSEL_NEGSEL_APORT3YCH15 << 8) /**< Shifted mode APORT3YCH15 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT3XCH16               (_ACMP_INPUTSEL_NEGSEL_APORT3XCH16 << 8) /**< Shifted mode APORT3XCH16 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT3YCH17               (_ACMP_INPUTSEL_NEGSEL_APORT3YCH17 << 8) /**< Shifted mode APORT3YCH17 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT3XCH18               (_ACMP_INPUTSEL_NEGSEL_APORT3XCH18 << 8) /**< Shifted mode APORT3XCH18 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT3YCH19               (_ACMP_INPUTSEL_NEGSEL_APORT3YCH19 << 8) /**< Shifted mode APORT3YCH19 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT3XCH20               (_ACMP_INPUTSEL_NEGSEL_APORT3XCH20 << 8) /**< Shifted mode APORT3XCH20 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT3YCH21               (_ACMP_INPUTSEL_NEGSEL_APORT3YCH21 << 8) /**< Shifted mode APORT3YCH21 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT3XCH22               (_ACMP_INPUTSEL_NEGSEL_APORT3XCH22 << 8) /**< Shifted mode APORT3XCH22 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT3YCH23               (_ACMP_INPUTSEL_NEGSEL_APORT3YCH23 << 8) /**< Shifted mode APORT3YCH23 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT3XCH24               (_ACMP_INPUTSEL_NEGSEL_APORT3XCH24 << 8) /**< Shifted mode APORT3XCH24 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT3YCH25               (_ACMP_INPUTSEL_NEGSEL_APORT3YCH25 << 8) /**< Shifted mode APORT3YCH25 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT3XCH26               (_ACMP_INPUTSEL_NEGSEL_APORT3XCH26 << 8) /**< Shifted mode APORT3XCH26 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT3YCH27               (_ACMP_INPUTSEL_NEGSEL_APORT3YCH27 << 8) /**< Shifted mode APORT3YCH27 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT3XCH28               (_ACMP_INPUTSEL_NEGSEL_APORT3XCH28 << 8) /**< Shifted mode APORT3XCH28 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT3YCH29               (_ACMP_INPUTSEL_NEGSEL_APORT3YCH29 << 8) /**< Shifted mode APORT3YCH29 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT3XCH30               (_ACMP_INPUTSEL_NEGSEL_APORT3XCH30 << 8) /**< Shifted mode APORT3XCH30 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT3YCH31               (_ACMP_INPUTSEL_NEGSEL_APORT3YCH31 << 8) /**< Shifted mode APORT3YCH31 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT4YCH0                (_ACMP_INPUTSEL_NEGSEL_APORT4YCH0 << 8)  /**< Shifted mode APORT4YCH0 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT4XCH1                (_ACMP_INPUTSEL_NEGSEL_APORT4XCH1 << 8)  /**< Shifted mode APORT4XCH1 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT4YCH2                (_ACMP_INPUTSEL_NEGSEL_APORT4YCH2 << 8)  /**< Shifted mode APORT4YCH2 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT4XCH3                (_ACMP_INPUTSEL_NEGSEL_APORT4XCH3 << 8)  /**< Shifted mode APORT4XCH3 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT4YCH4                (_ACMP_INPUTSEL_NEGSEL_APORT4YCH4 << 8)  /**< Shifted mode APORT4YCH4 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT4XCH5                (_ACMP_INPUTSEL_NEGSEL_APORT4XCH5 << 8)  /**< Shifted mode APORT4XCH5 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT4YCH6                (_ACMP_INPUTSEL_NEGSEL_APORT4YCH6 << 8)  /**< Shifted mode APORT4YCH6 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT4XCH7                (_ACMP_INPUTSEL_NEGSEL_APORT4XCH7 << 8)  /**< Shifted mode APORT4XCH7 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT4YCH8                (_ACMP_INPUTSEL_NEGSEL_APORT4YCH8 << 8)  /**< Shifted mode APORT4YCH8 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT4XCH9                (_ACMP_INPUTSEL_NEGSEL_APORT4XCH9 << 8)  /**< Shifted mode APORT4XCH9 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT4YCH10               (_ACMP_INPUTSEL_NEGSEL_APORT4YCH10 << 8) /**< Shifted mode APORT4YCH10 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT4XCH11               (_ACMP_INPUTSEL_NEGSEL_APORT4XCH11 << 8) /**< Shifted mode APORT4XCH11 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT4YCH12               (_ACMP_INPUTSEL_NEGSEL_APORT4YCH12 << 8) /**< Shifted mode APORT4YCH12 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT4XCH13               (_ACMP_INPUTSEL_NEGSEL_APORT4XCH13 << 8) /**< Shifted mode APORT4XCH13 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT4YCH16               (_ACMP_INPUTSEL_NEGSEL_APORT4YCH16 << 8) /**< Shifted mode APORT4YCH16 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT4XCH17               (_ACMP_INPUTSEL_NEGSEL_APORT4XCH17 << 8) /**< Shifted mode APORT4XCH17 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT4YCH18               (_ACMP_INPUTSEL_NEGSEL_APORT4YCH18 << 8) /**< Shifted mode APORT4YCH18 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT4XCH19               (_ACMP_INPUTSEL_NEGSEL_APORT4XCH19 << 8) /**< Shifted mode APORT4XCH19 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT4YCH20               (_ACMP_INPUTSEL_NEGSEL_APORT4YCH20 << 8) /**< Shifted mode APORT4YCH20 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT4XCH21               (_ACMP_INPUTSEL_NEGSEL_APORT4XCH21 << 8) /**< Shifted mode APORT4XCH21 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT4YCH22               (_ACMP_INPUTSEL_NEGSEL_APORT4YCH22 << 8) /**< Shifted mode APORT4YCH22 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT4XCH23               (_ACMP_INPUTSEL_NEGSEL_APORT4XCH23 << 8) /**< Shifted mode APORT4XCH23 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT4YCH24               (_ACMP_INPUTSEL_NEGSEL_APORT4YCH24 << 8) /**< Shifted mode APORT4YCH24 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT4XCH25               (_ACMP_INPUTSEL_NEGSEL_APORT4XCH25 << 8) /**< Shifted mode APORT4XCH25 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT4YCH26               (_ACMP_INPUTSEL_NEGSEL_APORT4YCH26 << 8) /**< Shifted mode APORT4YCH26 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT4XCH27               (_ACMP_INPUTSEL_NEGSEL_APORT4XCH27 << 8) /**< Shifted mode APORT4XCH27 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT4YCH28               (_ACMP_INPUTSEL_NEGSEL_APORT4YCH28 << 8) /**< Shifted mode APORT4YCH28 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT4XCH29               (_ACMP_INPUTSEL_NEGSEL_APORT4XCH29 << 8) /**< Shifted mode APORT4XCH29 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT4YCH30               (_ACMP_INPUTSEL_NEGSEL_APORT4YCH30 << 8) /**< Shifted mode APORT4YCH30 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT4YCH14               (_ACMP_INPUTSEL_NEGSEL_APORT4YCH14 << 8) /**< Shifted mode APORT4YCH14 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT4XCH15               (_ACMP_INPUTSEL_NEGSEL_APORT4XCH15 << 8) /**< Shifted mode APORT4XCH15 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT4XCH31               (_ACMP_INPUTSEL_NEGSEL_APORT4XCH31 << 8) /**< Shifted mode APORT4XCH31 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_DACOUT0                   (_ACMP_INPUTSEL_NEGSEL_DACOUT0 << 8)     /**< Shifted mode DACOUT0 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_DACOUT1                   (_ACMP_INPUTSEL_NEGSEL_DACOUT1 << 8)     /**< Shifted mode DACOUT1 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_VLP                       (_ACMP_INPUTSEL_NEGSEL_VLP << 8)         /**< Shifted mode VLP for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_VBDIV                     (_ACMP_INPUTSEL_NEGSEL_VBDIV << 8)       /**< Shifted mode VBDIV for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_VADIV                     (_ACMP_INPUTSEL_NEGSEL_VADIV << 8)       /**< Shifted mode VADIV for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_VDD                       (_ACMP_INPUTSEL_NEGSEL_VDD << 8)         /**< Shifted mode VDD for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_VSS                       (_ACMP_INPUTSEL_NEGSEL_VSS << 8)         /**< Shifted mode VSS for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_SHIFT                     16                                       /**< Shift value for ACMP_VASEL */
+#define _ACMP_INPUTSEL_VASEL_MASK                      0x3F0000UL                               /**< Bit mask for ACMP_VASEL */
+#define _ACMP_INPUTSEL_VASEL_DEFAULT                   0x00000000UL                             /**< Mode DEFAULT for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_VDD                       0x00000000UL                             /**< Mode VDD for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT2YCH0                0x00000001UL                             /**< Mode APORT2YCH0 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT2YCH2                0x00000003UL                             /**< Mode APORT2YCH2 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT2YCH4                0x00000005UL                             /**< Mode APORT2YCH4 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT2YCH6                0x00000007UL                             /**< Mode APORT2YCH6 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT2YCH8                0x00000009UL                             /**< Mode APORT2YCH8 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT2YCH10               0x0000000BUL                             /**< Mode APORT2YCH10 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT2YCH12               0x0000000DUL                             /**< Mode APORT2YCH12 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT2YCH14               0x0000000FUL                             /**< Mode APORT2YCH14 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT2YCH16               0x00000011UL                             /**< Mode APORT2YCH16 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT2YCH18               0x00000013UL                             /**< Mode APORT2YCH18 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT2YCH20               0x00000015UL                             /**< Mode APORT2YCH20 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT2YCH22               0x00000017UL                             /**< Mode APORT2YCH22 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT2YCH24               0x00000019UL                             /**< Mode APORT2YCH24 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT2YCH26               0x0000001BUL                             /**< Mode APORT2YCH26 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT2YCH28               0x0000001DUL                             /**< Mode APORT2YCH28 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT2YCH30               0x0000001FUL                             /**< Mode APORT2YCH30 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT1XCH0                0x00000020UL                             /**< Mode APORT1XCH0 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT1YCH1                0x00000021UL                             /**< Mode APORT1YCH1 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT1XCH2                0x00000022UL                             /**< Mode APORT1XCH2 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT1YCH3                0x00000023UL                             /**< Mode APORT1YCH3 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT1XCH4                0x00000024UL                             /**< Mode APORT1XCH4 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT1YCH5                0x00000025UL                             /**< Mode APORT1YCH5 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT1XCH6                0x00000026UL                             /**< Mode APORT1XCH6 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT1YCH7                0x00000027UL                             /**< Mode APORT1YCH7 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT1XCH8                0x00000028UL                             /**< Mode APORT1XCH8 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT1YCH9                0x00000029UL                             /**< Mode APORT1YCH9 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT1XCH10               0x0000002AUL                             /**< Mode APORT1XCH10 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT1YCH11               0x0000002BUL                             /**< Mode APORT1YCH11 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT1XCH12               0x0000002CUL                             /**< Mode APORT1XCH12 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT1YCH13               0x0000002DUL                             /**< Mode APORT1YCH13 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT1XCH14               0x0000002EUL                             /**< Mode APORT1XCH14 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT1YCH15               0x0000002FUL                             /**< Mode APORT1YCH15 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT1XCH16               0x00000030UL                             /**< Mode APORT1XCH16 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT1YCH17               0x00000031UL                             /**< Mode APORT1YCH17 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT1XCH18               0x00000032UL                             /**< Mode APORT1XCH18 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT1YCH19               0x00000033UL                             /**< Mode APORT1YCH19 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT1XCH20               0x00000034UL                             /**< Mode APORT1XCH20 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT1YCH21               0x00000035UL                             /**< Mode APORT1YCH21 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT1XCH22               0x00000036UL                             /**< Mode APORT1XCH22 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT1YCH23               0x00000037UL                             /**< Mode APORT1YCH23 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT1XCH24               0x00000038UL                             /**< Mode APORT1XCH24 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT1YCH25               0x00000039UL                             /**< Mode APORT1YCH25 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT1XCH26               0x0000003AUL                             /**< Mode APORT1XCH26 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT1YCH27               0x0000003BUL                             /**< Mode APORT1YCH27 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT1XCH28               0x0000003CUL                             /**< Mode APORT1XCH28 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT1YCH29               0x0000003DUL                             /**< Mode APORT1YCH29 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT1XCH30               0x0000003EUL                             /**< Mode APORT1XCH30 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT1YCH31               0x0000003FUL                             /**< Mode APORT1YCH31 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_DEFAULT                    (_ACMP_INPUTSEL_VASEL_DEFAULT << 16)     /**< Shifted mode DEFAULT for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_VDD                        (_ACMP_INPUTSEL_VASEL_VDD << 16)         /**< Shifted mode VDD for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT2YCH0                 (_ACMP_INPUTSEL_VASEL_APORT2YCH0 << 16)  /**< Shifted mode APORT2YCH0 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT2YCH2                 (_ACMP_INPUTSEL_VASEL_APORT2YCH2 << 16)  /**< Shifted mode APORT2YCH2 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT2YCH4                 (_ACMP_INPUTSEL_VASEL_APORT2YCH4 << 16)  /**< Shifted mode APORT2YCH4 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT2YCH6                 (_ACMP_INPUTSEL_VASEL_APORT2YCH6 << 16)  /**< Shifted mode APORT2YCH6 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT2YCH8                 (_ACMP_INPUTSEL_VASEL_APORT2YCH8 << 16)  /**< Shifted mode APORT2YCH8 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT2YCH10                (_ACMP_INPUTSEL_VASEL_APORT2YCH10 << 16) /**< Shifted mode APORT2YCH10 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT2YCH12                (_ACMP_INPUTSEL_VASEL_APORT2YCH12 << 16) /**< Shifted mode APORT2YCH12 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT2YCH14                (_ACMP_INPUTSEL_VASEL_APORT2YCH14 << 16) /**< Shifted mode APORT2YCH14 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT2YCH16                (_ACMP_INPUTSEL_VASEL_APORT2YCH16 << 16) /**< Shifted mode APORT2YCH16 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT2YCH18                (_ACMP_INPUTSEL_VASEL_APORT2YCH18 << 16) /**< Shifted mode APORT2YCH18 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT2YCH20                (_ACMP_INPUTSEL_VASEL_APORT2YCH20 << 16) /**< Shifted mode APORT2YCH20 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT2YCH22                (_ACMP_INPUTSEL_VASEL_APORT2YCH22 << 16) /**< Shifted mode APORT2YCH22 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT2YCH24                (_ACMP_INPUTSEL_VASEL_APORT2YCH24 << 16) /**< Shifted mode APORT2YCH24 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT2YCH26                (_ACMP_INPUTSEL_VASEL_APORT2YCH26 << 16) /**< Shifted mode APORT2YCH26 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT2YCH28                (_ACMP_INPUTSEL_VASEL_APORT2YCH28 << 16) /**< Shifted mode APORT2YCH28 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT2YCH30                (_ACMP_INPUTSEL_VASEL_APORT2YCH30 << 16) /**< Shifted mode APORT2YCH30 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT1XCH0                 (_ACMP_INPUTSEL_VASEL_APORT1XCH0 << 16)  /**< Shifted mode APORT1XCH0 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT1YCH1                 (_ACMP_INPUTSEL_VASEL_APORT1YCH1 << 16)  /**< Shifted mode APORT1YCH1 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT1XCH2                 (_ACMP_INPUTSEL_VASEL_APORT1XCH2 << 16)  /**< Shifted mode APORT1XCH2 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT1YCH3                 (_ACMP_INPUTSEL_VASEL_APORT1YCH3 << 16)  /**< Shifted mode APORT1YCH3 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT1XCH4                 (_ACMP_INPUTSEL_VASEL_APORT1XCH4 << 16)  /**< Shifted mode APORT1XCH4 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT1YCH5                 (_ACMP_INPUTSEL_VASEL_APORT1YCH5 << 16)  /**< Shifted mode APORT1YCH5 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT1XCH6                 (_ACMP_INPUTSEL_VASEL_APORT1XCH6 << 16)  /**< Shifted mode APORT1XCH6 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT1YCH7                 (_ACMP_INPUTSEL_VASEL_APORT1YCH7 << 16)  /**< Shifted mode APORT1YCH7 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT1XCH8                 (_ACMP_INPUTSEL_VASEL_APORT1XCH8 << 16)  /**< Shifted mode APORT1XCH8 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT1YCH9                 (_ACMP_INPUTSEL_VASEL_APORT1YCH9 << 16)  /**< Shifted mode APORT1YCH9 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT1XCH10                (_ACMP_INPUTSEL_VASEL_APORT1XCH10 << 16) /**< Shifted mode APORT1XCH10 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT1YCH11                (_ACMP_INPUTSEL_VASEL_APORT1YCH11 << 16) /**< Shifted mode APORT1YCH11 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT1XCH12                (_ACMP_INPUTSEL_VASEL_APORT1XCH12 << 16) /**< Shifted mode APORT1XCH12 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT1YCH13                (_ACMP_INPUTSEL_VASEL_APORT1YCH13 << 16) /**< Shifted mode APORT1YCH13 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT1XCH14                (_ACMP_INPUTSEL_VASEL_APORT1XCH14 << 16) /**< Shifted mode APORT1XCH14 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT1YCH15                (_ACMP_INPUTSEL_VASEL_APORT1YCH15 << 16) /**< Shifted mode APORT1YCH15 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT1XCH16                (_ACMP_INPUTSEL_VASEL_APORT1XCH16 << 16) /**< Shifted mode APORT1XCH16 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT1YCH17                (_ACMP_INPUTSEL_VASEL_APORT1YCH17 << 16) /**< Shifted mode APORT1YCH17 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT1XCH18                (_ACMP_INPUTSEL_VASEL_APORT1XCH18 << 16) /**< Shifted mode APORT1XCH18 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT1YCH19                (_ACMP_INPUTSEL_VASEL_APORT1YCH19 << 16) /**< Shifted mode APORT1YCH19 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT1XCH20                (_ACMP_INPUTSEL_VASEL_APORT1XCH20 << 16) /**< Shifted mode APORT1XCH20 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT1YCH21                (_ACMP_INPUTSEL_VASEL_APORT1YCH21 << 16) /**< Shifted mode APORT1YCH21 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT1XCH22                (_ACMP_INPUTSEL_VASEL_APORT1XCH22 << 16) /**< Shifted mode APORT1XCH22 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT1YCH23                (_ACMP_INPUTSEL_VASEL_APORT1YCH23 << 16) /**< Shifted mode APORT1YCH23 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT1XCH24                (_ACMP_INPUTSEL_VASEL_APORT1XCH24 << 16) /**< Shifted mode APORT1XCH24 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT1YCH25                (_ACMP_INPUTSEL_VASEL_APORT1YCH25 << 16) /**< Shifted mode APORT1YCH25 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT1XCH26                (_ACMP_INPUTSEL_VASEL_APORT1XCH26 << 16) /**< Shifted mode APORT1XCH26 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT1YCH27                (_ACMP_INPUTSEL_VASEL_APORT1YCH27 << 16) /**< Shifted mode APORT1YCH27 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT1XCH28                (_ACMP_INPUTSEL_VASEL_APORT1XCH28 << 16) /**< Shifted mode APORT1XCH28 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT1YCH29                (_ACMP_INPUTSEL_VASEL_APORT1YCH29 << 16) /**< Shifted mode APORT1YCH29 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT1XCH30                (_ACMP_INPUTSEL_VASEL_APORT1XCH30 << 16) /**< Shifted mode APORT1XCH30 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT1YCH31                (_ACMP_INPUTSEL_VASEL_APORT1YCH31 << 16) /**< Shifted mode APORT1YCH31 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VBSEL                            (0x1UL << 22)                            /**< VB Selection */
+#define _ACMP_INPUTSEL_VBSEL_SHIFT                     22                                       /**< Shift value for ACMP_VBSEL */
+#define _ACMP_INPUTSEL_VBSEL_MASK                      0x400000UL                               /**< Bit mask for ACMP_VBSEL */
+#define _ACMP_INPUTSEL_VBSEL_DEFAULT                   0x00000000UL                             /**< Mode DEFAULT for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VBSEL_1V25                      0x00000000UL                             /**< Mode 1V25 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VBSEL_2V5                       0x00000001UL                             /**< Mode 2V5 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VBSEL_DEFAULT                    (_ACMP_INPUTSEL_VBSEL_DEFAULT << 22)     /**< Shifted mode DEFAULT for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VBSEL_1V25                       (_ACMP_INPUTSEL_VBSEL_1V25 << 22)        /**< Shifted mode 1V25 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VBSEL_2V5                        (_ACMP_INPUTSEL_VBSEL_2V5 << 22)         /**< Shifted mode 2V5 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VLPSEL                           (0x1UL << 24)                            /**< Low-Power Sampled Voltage Selection */
+#define _ACMP_INPUTSEL_VLPSEL_SHIFT                    24                                       /**< Shift value for ACMP_VLPSEL */
+#define _ACMP_INPUTSEL_VLPSEL_MASK                     0x1000000UL                              /**< Bit mask for ACMP_VLPSEL */
+#define _ACMP_INPUTSEL_VLPSEL_DEFAULT                  0x00000000UL                             /**< Mode DEFAULT for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VLPSEL_VADIV                    0x00000000UL                             /**< Mode VADIV for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VLPSEL_VBDIV                    0x00000001UL                             /**< Mode VBDIV for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VLPSEL_DEFAULT                   (_ACMP_INPUTSEL_VLPSEL_DEFAULT << 24)    /**< Shifted mode DEFAULT for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VLPSEL_VADIV                     (_ACMP_INPUTSEL_VLPSEL_VADIV << 24)      /**< Shifted mode VADIV for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VLPSEL_VBDIV                     (_ACMP_INPUTSEL_VLPSEL_VBDIV << 24)      /**< Shifted mode VBDIV for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_CSRESEN                          (0x1UL << 26)                            /**< Capacitive Sense Mode Internal Resistor Enable */
+#define _ACMP_INPUTSEL_CSRESEN_SHIFT                   26                                       /**< Shift value for ACMP_CSRESEN */
+#define _ACMP_INPUTSEL_CSRESEN_MASK                    0x4000000UL                              /**< Bit mask for ACMP_CSRESEN */
+#define _ACMP_INPUTSEL_CSRESEN_DEFAULT                 0x00000000UL                             /**< Mode DEFAULT for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_CSRESEN_DEFAULT                  (_ACMP_INPUTSEL_CSRESEN_DEFAULT << 26)   /**< Shifted mode DEFAULT for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_CSRESSEL_SHIFT                  28                                       /**< Shift value for ACMP_CSRESSEL */
+#define _ACMP_INPUTSEL_CSRESSEL_MASK                   0x70000000UL                             /**< Bit mask for ACMP_CSRESSEL */
+#define _ACMP_INPUTSEL_CSRESSEL_DEFAULT                0x00000000UL                             /**< Mode DEFAULT for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_CSRESSEL_RES0                   0x00000000UL                             /**< Mode RES0 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_CSRESSEL_RES1                   0x00000001UL                             /**< Mode RES1 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_CSRESSEL_RES2                   0x00000002UL                             /**< Mode RES2 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_CSRESSEL_RES3                   0x00000003UL                             /**< Mode RES3 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_CSRESSEL_RES4                   0x00000004UL                             /**< Mode RES4 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_CSRESSEL_RES5                   0x00000005UL                             /**< Mode RES5 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_CSRESSEL_RES6                   0x00000006UL                             /**< Mode RES6 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_CSRESSEL_RES7                   0x00000007UL                             /**< Mode RES7 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_CSRESSEL_DEFAULT                 (_ACMP_INPUTSEL_CSRESSEL_DEFAULT << 28)  /**< Shifted mode DEFAULT for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_CSRESSEL_RES0                    (_ACMP_INPUTSEL_CSRESSEL_RES0 << 28)     /**< Shifted mode RES0 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_CSRESSEL_RES1                    (_ACMP_INPUTSEL_CSRESSEL_RES1 << 28)     /**< Shifted mode RES1 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_CSRESSEL_RES2                    (_ACMP_INPUTSEL_CSRESSEL_RES2 << 28)     /**< Shifted mode RES2 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_CSRESSEL_RES3                    (_ACMP_INPUTSEL_CSRESSEL_RES3 << 28)     /**< Shifted mode RES3 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_CSRESSEL_RES4                    (_ACMP_INPUTSEL_CSRESSEL_RES4 << 28)     /**< Shifted mode RES4 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_CSRESSEL_RES5                    (_ACMP_INPUTSEL_CSRESSEL_RES5 << 28)     /**< Shifted mode RES5 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_CSRESSEL_RES6                    (_ACMP_INPUTSEL_CSRESSEL_RES6 << 28)     /**< Shifted mode RES6 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_CSRESSEL_RES7                    (_ACMP_INPUTSEL_CSRESSEL_RES7 << 28)     /**< Shifted mode RES7 for ACMP_INPUTSEL */
+
+/* Bit fields for ACMP STATUS */
+#define _ACMP_STATUS_RESETVALUE                        0x00000000UL                              /**< Default value for ACMP_STATUS */
+#define _ACMP_STATUS_MASK                              0x00000007UL                              /**< Mask for ACMP_STATUS */
+#define ACMP_STATUS_ACMPACT                            (0x1UL << 0)                              /**< Analog Comparator Active */
+#define _ACMP_STATUS_ACMPACT_SHIFT                     0                                         /**< Shift value for ACMP_ACMPACT */
+#define _ACMP_STATUS_ACMPACT_MASK                      0x1UL                                     /**< Bit mask for ACMP_ACMPACT */
+#define _ACMP_STATUS_ACMPACT_DEFAULT                   0x00000000UL                              /**< Mode DEFAULT for ACMP_STATUS */
+#define ACMP_STATUS_ACMPACT_DEFAULT                    (_ACMP_STATUS_ACMPACT_DEFAULT << 0)       /**< Shifted mode DEFAULT for ACMP_STATUS */
+#define ACMP_STATUS_ACMPOUT                            (0x1UL << 1)                              /**< Analog Comparator Output */
+#define _ACMP_STATUS_ACMPOUT_SHIFT                     1                                         /**< Shift value for ACMP_ACMPOUT */
+#define _ACMP_STATUS_ACMPOUT_MASK                      0x2UL                                     /**< Bit mask for ACMP_ACMPOUT */
+#define _ACMP_STATUS_ACMPOUT_DEFAULT                   0x00000000UL                              /**< Mode DEFAULT for ACMP_STATUS */
+#define ACMP_STATUS_ACMPOUT_DEFAULT                    (_ACMP_STATUS_ACMPOUT_DEFAULT << 1)       /**< Shifted mode DEFAULT for ACMP_STATUS */
+#define ACMP_STATUS_APORTCONFLICT                      (0x1UL << 2)                              /**< APORT Conflict Output */
+#define _ACMP_STATUS_APORTCONFLICT_SHIFT               2                                         /**< Shift value for ACMP_APORTCONFLICT */
+#define _ACMP_STATUS_APORTCONFLICT_MASK                0x4UL                                     /**< Bit mask for ACMP_APORTCONFLICT */
+#define _ACMP_STATUS_APORTCONFLICT_DEFAULT             0x00000000UL                              /**< Mode DEFAULT for ACMP_STATUS */
+#define ACMP_STATUS_APORTCONFLICT_DEFAULT              (_ACMP_STATUS_APORTCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_STATUS */
+
+/* Bit fields for ACMP IF */
+#define _ACMP_IF_RESETVALUE                            0x00000000UL                          /**< Default value for ACMP_IF */
+#define _ACMP_IF_MASK                                  0x00000007UL                          /**< Mask for ACMP_IF */
+#define ACMP_IF_EDGE                                   (0x1UL << 0)                          /**< Edge Triggered Interrupt Flag */
+#define _ACMP_IF_EDGE_SHIFT                            0                                     /**< Shift value for ACMP_EDGE */
+#define _ACMP_IF_EDGE_MASK                             0x1UL                                 /**< Bit mask for ACMP_EDGE */
+#define _ACMP_IF_EDGE_DEFAULT                          0x00000000UL                          /**< Mode DEFAULT for ACMP_IF */
+#define ACMP_IF_EDGE_DEFAULT                           (_ACMP_IF_EDGE_DEFAULT << 0)          /**< Shifted mode DEFAULT for ACMP_IF */
+#define ACMP_IF_WARMUP                                 (0x1UL << 1)                          /**< Warm-up Interrupt Flag */
+#define _ACMP_IF_WARMUP_SHIFT                          1                                     /**< Shift value for ACMP_WARMUP */
+#define _ACMP_IF_WARMUP_MASK                           0x2UL                                 /**< Bit mask for ACMP_WARMUP */
+#define _ACMP_IF_WARMUP_DEFAULT                        0x00000000UL                          /**< Mode DEFAULT for ACMP_IF */
+#define ACMP_IF_WARMUP_DEFAULT                         (_ACMP_IF_WARMUP_DEFAULT << 1)        /**< Shifted mode DEFAULT for ACMP_IF */
+#define ACMP_IF_APORTCONFLICT                          (0x1UL << 2)                          /**< APORT Conflict Interrupt Flag */
+#define _ACMP_IF_APORTCONFLICT_SHIFT                   2                                     /**< Shift value for ACMP_APORTCONFLICT */
+#define _ACMP_IF_APORTCONFLICT_MASK                    0x4UL                                 /**< Bit mask for ACMP_APORTCONFLICT */
+#define _ACMP_IF_APORTCONFLICT_DEFAULT                 0x00000000UL                          /**< Mode DEFAULT for ACMP_IF */
+#define ACMP_IF_APORTCONFLICT_DEFAULT                  (_ACMP_IF_APORTCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_IF */
+
+/* Bit fields for ACMP IFS */
+#define _ACMP_IFS_RESETVALUE                           0x00000000UL                           /**< Default value for ACMP_IFS */
+#define _ACMP_IFS_MASK                                 0x00000007UL                           /**< Mask for ACMP_IFS */
+#define ACMP_IFS_EDGE                                  (0x1UL << 0)                           /**< Set EDGE Interrupt Flag */
+#define _ACMP_IFS_EDGE_SHIFT                           0                                      /**< Shift value for ACMP_EDGE */
+#define _ACMP_IFS_EDGE_MASK                            0x1UL                                  /**< Bit mask for ACMP_EDGE */
+#define _ACMP_IFS_EDGE_DEFAULT                         0x00000000UL                           /**< Mode DEFAULT for ACMP_IFS */
+#define ACMP_IFS_EDGE_DEFAULT                          (_ACMP_IFS_EDGE_DEFAULT << 0)          /**< Shifted mode DEFAULT for ACMP_IFS */
+#define ACMP_IFS_WARMUP                                (0x1UL << 1)                           /**< Set WARMUP Interrupt Flag */
+#define _ACMP_IFS_WARMUP_SHIFT                         1                                      /**< Shift value for ACMP_WARMUP */
+#define _ACMP_IFS_WARMUP_MASK                          0x2UL                                  /**< Bit mask for ACMP_WARMUP */
+#define _ACMP_IFS_WARMUP_DEFAULT                       0x00000000UL                           /**< Mode DEFAULT for ACMP_IFS */
+#define ACMP_IFS_WARMUP_DEFAULT                        (_ACMP_IFS_WARMUP_DEFAULT << 1)        /**< Shifted mode DEFAULT for ACMP_IFS */
+#define ACMP_IFS_APORTCONFLICT                         (0x1UL << 2)                           /**< Set APORTCONFLICT Interrupt Flag */
+#define _ACMP_IFS_APORTCONFLICT_SHIFT                  2                                      /**< Shift value for ACMP_APORTCONFLICT */
+#define _ACMP_IFS_APORTCONFLICT_MASK                   0x4UL                                  /**< Bit mask for ACMP_APORTCONFLICT */
+#define _ACMP_IFS_APORTCONFLICT_DEFAULT                0x00000000UL                           /**< Mode DEFAULT for ACMP_IFS */
+#define ACMP_IFS_APORTCONFLICT_DEFAULT                 (_ACMP_IFS_APORTCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_IFS */
+
+/* Bit fields for ACMP IFC */
+#define _ACMP_IFC_RESETVALUE                           0x00000000UL                           /**< Default value for ACMP_IFC */
+#define _ACMP_IFC_MASK                                 0x00000007UL                           /**< Mask for ACMP_IFC */
+#define ACMP_IFC_EDGE                                  (0x1UL << 0)                           /**< Clear EDGE Interrupt Flag */
+#define _ACMP_IFC_EDGE_SHIFT                           0                                      /**< Shift value for ACMP_EDGE */
+#define _ACMP_IFC_EDGE_MASK                            0x1UL                                  /**< Bit mask for ACMP_EDGE */
+#define _ACMP_IFC_EDGE_DEFAULT                         0x00000000UL                           /**< Mode DEFAULT for ACMP_IFC */
+#define ACMP_IFC_EDGE_DEFAULT                          (_ACMP_IFC_EDGE_DEFAULT << 0)          /**< Shifted mode DEFAULT for ACMP_IFC */
+#define ACMP_IFC_WARMUP                                (0x1UL << 1)                           /**< Clear WARMUP Interrupt Flag */
+#define _ACMP_IFC_WARMUP_SHIFT                         1                                      /**< Shift value for ACMP_WARMUP */
+#define _ACMP_IFC_WARMUP_MASK                          0x2UL                                  /**< Bit mask for ACMP_WARMUP */
+#define _ACMP_IFC_WARMUP_DEFAULT                       0x00000000UL                           /**< Mode DEFAULT for ACMP_IFC */
+#define ACMP_IFC_WARMUP_DEFAULT                        (_ACMP_IFC_WARMUP_DEFAULT << 1)        /**< Shifted mode DEFAULT for ACMP_IFC */
+#define ACMP_IFC_APORTCONFLICT                         (0x1UL << 2)                           /**< Clear APORTCONFLICT Interrupt Flag */
+#define _ACMP_IFC_APORTCONFLICT_SHIFT                  2                                      /**< Shift value for ACMP_APORTCONFLICT */
+#define _ACMP_IFC_APORTCONFLICT_MASK                   0x4UL                                  /**< Bit mask for ACMP_APORTCONFLICT */
+#define _ACMP_IFC_APORTCONFLICT_DEFAULT                0x00000000UL                           /**< Mode DEFAULT for ACMP_IFC */
+#define ACMP_IFC_APORTCONFLICT_DEFAULT                 (_ACMP_IFC_APORTCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_IFC */
+
+/* Bit fields for ACMP IEN */
+#define _ACMP_IEN_RESETVALUE                           0x00000000UL                           /**< Default value for ACMP_IEN */
+#define _ACMP_IEN_MASK                                 0x00000007UL                           /**< Mask for ACMP_IEN */
+#define ACMP_IEN_EDGE                                  (0x1UL << 0)                           /**< EDGE Interrupt Enable */
+#define _ACMP_IEN_EDGE_SHIFT                           0                                      /**< Shift value for ACMP_EDGE */
+#define _ACMP_IEN_EDGE_MASK                            0x1UL                                  /**< Bit mask for ACMP_EDGE */
+#define _ACMP_IEN_EDGE_DEFAULT                         0x00000000UL                           /**< Mode DEFAULT for ACMP_IEN */
+#define ACMP_IEN_EDGE_DEFAULT                          (_ACMP_IEN_EDGE_DEFAULT << 0)          /**< Shifted mode DEFAULT for ACMP_IEN */
+#define ACMP_IEN_WARMUP                                (0x1UL << 1)                           /**< WARMUP Interrupt Enable */
+#define _ACMP_IEN_WARMUP_SHIFT                         1                                      /**< Shift value for ACMP_WARMUP */
+#define _ACMP_IEN_WARMUP_MASK                          0x2UL                                  /**< Bit mask for ACMP_WARMUP */
+#define _ACMP_IEN_WARMUP_DEFAULT                       0x00000000UL                           /**< Mode DEFAULT for ACMP_IEN */
+#define ACMP_IEN_WARMUP_DEFAULT                        (_ACMP_IEN_WARMUP_DEFAULT << 1)        /**< Shifted mode DEFAULT for ACMP_IEN */
+#define ACMP_IEN_APORTCONFLICT                         (0x1UL << 2)                           /**< APORTCONFLICT Interrupt Enable */
+#define _ACMP_IEN_APORTCONFLICT_SHIFT                  2                                      /**< Shift value for ACMP_APORTCONFLICT */
+#define _ACMP_IEN_APORTCONFLICT_MASK                   0x4UL                                  /**< Bit mask for ACMP_APORTCONFLICT */
+#define _ACMP_IEN_APORTCONFLICT_DEFAULT                0x00000000UL                           /**< Mode DEFAULT for ACMP_IEN */
+#define ACMP_IEN_APORTCONFLICT_DEFAULT                 (_ACMP_IEN_APORTCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_IEN */
+
+/* Bit fields for ACMP APORTREQ */
+#define _ACMP_APORTREQ_RESETVALUE                      0x00000000UL                             /**< Default value for ACMP_APORTREQ */
+#define _ACMP_APORTREQ_MASK                            0x000003FFUL                             /**< Mask for ACMP_APORTREQ */
+#define ACMP_APORTREQ_APORT0XREQ                       (0x1UL << 0)                             /**< 1 if the bus connected to APORT0X is requested */
+#define _ACMP_APORTREQ_APORT0XREQ_SHIFT                0                                        /**< Shift value for ACMP_APORT0XREQ */
+#define _ACMP_APORTREQ_APORT0XREQ_MASK                 0x1UL                                    /**< Bit mask for ACMP_APORT0XREQ */
+#define _ACMP_APORTREQ_APORT0XREQ_DEFAULT              0x00000000UL                             /**< Mode DEFAULT for ACMP_APORTREQ */
+#define ACMP_APORTREQ_APORT0XREQ_DEFAULT               (_ACMP_APORTREQ_APORT0XREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_APORTREQ */
+#define ACMP_APORTREQ_APORT0YREQ                       (0x1UL << 1)                             /**< 1 if the bus connected to APORT0Y is requested */
+#define _ACMP_APORTREQ_APORT0YREQ_SHIFT                1                                        /**< Shift value for ACMP_APORT0YREQ */
+#define _ACMP_APORTREQ_APORT0YREQ_MASK                 0x2UL                                    /**< Bit mask for ACMP_APORT0YREQ */
+#define _ACMP_APORTREQ_APORT0YREQ_DEFAULT              0x00000000UL                             /**< Mode DEFAULT for ACMP_APORTREQ */
+#define ACMP_APORTREQ_APORT0YREQ_DEFAULT               (_ACMP_APORTREQ_APORT0YREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_APORTREQ */
+#define ACMP_APORTREQ_APORT1XREQ                       (0x1UL << 2)                             /**< 1 if the bus connected to APORT2X is requested */
+#define _ACMP_APORTREQ_APORT1XREQ_SHIFT                2                                        /**< Shift value for ACMP_APORT1XREQ */
+#define _ACMP_APORTREQ_APORT1XREQ_MASK                 0x4UL                                    /**< Bit mask for ACMP_APORT1XREQ */
+#define _ACMP_APORTREQ_APORT1XREQ_DEFAULT              0x00000000UL                             /**< Mode DEFAULT for ACMP_APORTREQ */
+#define ACMP_APORTREQ_APORT1XREQ_DEFAULT               (_ACMP_APORTREQ_APORT1XREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_APORTREQ */
+#define ACMP_APORTREQ_APORT1YREQ                       (0x1UL << 3)                             /**< 1 if the bus connected to APORT1X is requested */
+#define _ACMP_APORTREQ_APORT1YREQ_SHIFT                3                                        /**< Shift value for ACMP_APORT1YREQ */
+#define _ACMP_APORTREQ_APORT1YREQ_MASK                 0x8UL                                    /**< Bit mask for ACMP_APORT1YREQ */
+#define _ACMP_APORTREQ_APORT1YREQ_DEFAULT              0x00000000UL                             /**< Mode DEFAULT for ACMP_APORTREQ */
+#define ACMP_APORTREQ_APORT1YREQ_DEFAULT               (_ACMP_APORTREQ_APORT1YREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_APORTREQ */
+#define ACMP_APORTREQ_APORT2XREQ                       (0x1UL << 4)                             /**< 1 if the bus connected to APORT2X is requested */
+#define _ACMP_APORTREQ_APORT2XREQ_SHIFT                4                                        /**< Shift value for ACMP_APORT2XREQ */
+#define _ACMP_APORTREQ_APORT2XREQ_MASK                 0x10UL                                   /**< Bit mask for ACMP_APORT2XREQ */
+#define _ACMP_APORTREQ_APORT2XREQ_DEFAULT              0x00000000UL                             /**< Mode DEFAULT for ACMP_APORTREQ */
+#define ACMP_APORTREQ_APORT2XREQ_DEFAULT               (_ACMP_APORTREQ_APORT2XREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_APORTREQ */
+#define ACMP_APORTREQ_APORT2YREQ                       (0x1UL << 5)                             /**< 1 if the bus connected to APORT2Y is requested */
+#define _ACMP_APORTREQ_APORT2YREQ_SHIFT                5                                        /**< Shift value for ACMP_APORT2YREQ */
+#define _ACMP_APORTREQ_APORT2YREQ_MASK                 0x20UL                                   /**< Bit mask for ACMP_APORT2YREQ */
+#define _ACMP_APORTREQ_APORT2YREQ_DEFAULT              0x00000000UL                             /**< Mode DEFAULT for ACMP_APORTREQ */
+#define ACMP_APORTREQ_APORT2YREQ_DEFAULT               (_ACMP_APORTREQ_APORT2YREQ_DEFAULT << 5) /**< Shifted mode DEFAULT for ACMP_APORTREQ */
+#define ACMP_APORTREQ_APORT3XREQ                       (0x1UL << 6)                             /**< 1 if the bus connected to APORT3X is requested */
+#define _ACMP_APORTREQ_APORT3XREQ_SHIFT                6                                        /**< Shift value for ACMP_APORT3XREQ */
+#define _ACMP_APORTREQ_APORT3XREQ_MASK                 0x40UL                                   /**< Bit mask for ACMP_APORT3XREQ */
+#define _ACMP_APORTREQ_APORT3XREQ_DEFAULT              0x00000000UL                             /**< Mode DEFAULT for ACMP_APORTREQ */
+#define ACMP_APORTREQ_APORT3XREQ_DEFAULT               (_ACMP_APORTREQ_APORT3XREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for ACMP_APORTREQ */
+#define ACMP_APORTREQ_APORT3YREQ                       (0x1UL << 7)                             /**< 1 if the bus connected to APORT3Y is requested */
+#define _ACMP_APORTREQ_APORT3YREQ_SHIFT                7                                        /**< Shift value for ACMP_APORT3YREQ */
+#define _ACMP_APORTREQ_APORT3YREQ_MASK                 0x80UL                                   /**< Bit mask for ACMP_APORT3YREQ */
+#define _ACMP_APORTREQ_APORT3YREQ_DEFAULT              0x00000000UL                             /**< Mode DEFAULT for ACMP_APORTREQ */
+#define ACMP_APORTREQ_APORT3YREQ_DEFAULT               (_ACMP_APORTREQ_APORT3YREQ_DEFAULT << 7) /**< Shifted mode DEFAULT for ACMP_APORTREQ */
+#define ACMP_APORTREQ_APORT4XREQ                       (0x1UL << 8)                             /**< 1 if the bus connected to APORT4X is requested */
+#define _ACMP_APORTREQ_APORT4XREQ_SHIFT                8                                        /**< Shift value for ACMP_APORT4XREQ */
+#define _ACMP_APORTREQ_APORT4XREQ_MASK                 0x100UL                                  /**< Bit mask for ACMP_APORT4XREQ */
+#define _ACMP_APORTREQ_APORT4XREQ_DEFAULT              0x00000000UL                             /**< Mode DEFAULT for ACMP_APORTREQ */
+#define ACMP_APORTREQ_APORT4XREQ_DEFAULT               (_ACMP_APORTREQ_APORT4XREQ_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_APORTREQ */
+#define ACMP_APORTREQ_APORT4YREQ                       (0x1UL << 9)                             /**< 1 if the bus connected to APORT4Y is requested */
+#define _ACMP_APORTREQ_APORT4YREQ_SHIFT                9                                        /**< Shift value for ACMP_APORT4YREQ */
+#define _ACMP_APORTREQ_APORT4YREQ_MASK                 0x200UL                                  /**< Bit mask for ACMP_APORT4YREQ */
+#define _ACMP_APORTREQ_APORT4YREQ_DEFAULT              0x00000000UL                             /**< Mode DEFAULT for ACMP_APORTREQ */
+#define ACMP_APORTREQ_APORT4YREQ_DEFAULT               (_ACMP_APORTREQ_APORT4YREQ_DEFAULT << 9) /**< Shifted mode DEFAULT for ACMP_APORTREQ */
+
+/* Bit fields for ACMP APORTCONFLICT */
+#define _ACMP_APORTCONFLICT_RESETVALUE                 0x00000000UL                                       /**< Default value for ACMP_APORTCONFLICT */
+#define _ACMP_APORTCONFLICT_MASK                       0x000003FFUL                                       /**< Mask for ACMP_APORTCONFLICT */
+#define ACMP_APORTCONFLICT_APORT0XCONFLICT             (0x1UL << 0)                                       /**< 1 if the bus connected to APORT0X is in conflict with another peripheral */
+#define _ACMP_APORTCONFLICT_APORT0XCONFLICT_SHIFT      0                                                  /**< Shift value for ACMP_APORT0XCONFLICT */
+#define _ACMP_APORTCONFLICT_APORT0XCONFLICT_MASK       0x1UL                                              /**< Bit mask for ACMP_APORT0XCONFLICT */
+#define _ACMP_APORTCONFLICT_APORT0XCONFLICT_DEFAULT    0x00000000UL                                       /**< Mode DEFAULT for ACMP_APORTCONFLICT */
+#define ACMP_APORTCONFLICT_APORT0XCONFLICT_DEFAULT     (_ACMP_APORTCONFLICT_APORT0XCONFLICT_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */
+#define ACMP_APORTCONFLICT_APORT0YCONFLICT             (0x1UL << 1)                                       /**< 1 if the bus connected to APORT0Y is in conflict with another peripheral */
+#define _ACMP_APORTCONFLICT_APORT0YCONFLICT_SHIFT      1                                                  /**< Shift value for ACMP_APORT0YCONFLICT */
+#define _ACMP_APORTCONFLICT_APORT0YCONFLICT_MASK       0x2UL                                              /**< Bit mask for ACMP_APORT0YCONFLICT */
+#define _ACMP_APORTCONFLICT_APORT0YCONFLICT_DEFAULT    0x00000000UL                                       /**< Mode DEFAULT for ACMP_APORTCONFLICT */
+#define ACMP_APORTCONFLICT_APORT0YCONFLICT_DEFAULT     (_ACMP_APORTCONFLICT_APORT0YCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */
+#define ACMP_APORTCONFLICT_APORT1XCONFLICT             (0x1UL << 2)                                       /**< 1 if the bus connected to APORT1X is in conflict with another peripheral */
+#define _ACMP_APORTCONFLICT_APORT1XCONFLICT_SHIFT      2                                                  /**< Shift value for ACMP_APORT1XCONFLICT */
+#define _ACMP_APORTCONFLICT_APORT1XCONFLICT_MASK       0x4UL                                              /**< Bit mask for ACMP_APORT1XCONFLICT */
+#define _ACMP_APORTCONFLICT_APORT1XCONFLICT_DEFAULT    0x00000000UL                                       /**< Mode DEFAULT for ACMP_APORTCONFLICT */
+#define ACMP_APORTCONFLICT_APORT1XCONFLICT_DEFAULT     (_ACMP_APORTCONFLICT_APORT1XCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */
+#define ACMP_APORTCONFLICT_APORT1YCONFLICT             (0x1UL << 3)                                       /**< 1 if the bus connected to APORT1X is in conflict with another peripheral */
+#define _ACMP_APORTCONFLICT_APORT1YCONFLICT_SHIFT      3                                                  /**< Shift value for ACMP_APORT1YCONFLICT */
+#define _ACMP_APORTCONFLICT_APORT1YCONFLICT_MASK       0x8UL                                              /**< Bit mask for ACMP_APORT1YCONFLICT */
+#define _ACMP_APORTCONFLICT_APORT1YCONFLICT_DEFAULT    0x00000000UL                                       /**< Mode DEFAULT for ACMP_APORTCONFLICT */
+#define ACMP_APORTCONFLICT_APORT1YCONFLICT_DEFAULT     (_ACMP_APORTCONFLICT_APORT1YCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */
+#define ACMP_APORTCONFLICT_APORT2XCONFLICT             (0x1UL << 4)                                       /**< 1 if the bus connected to APORT2X is in conflict with another peripheral */
+#define _ACMP_APORTCONFLICT_APORT2XCONFLICT_SHIFT      4                                                  /**< Shift value for ACMP_APORT2XCONFLICT */
+#define _ACMP_APORTCONFLICT_APORT2XCONFLICT_MASK       0x10UL                                             /**< Bit mask for ACMP_APORT2XCONFLICT */
+#define _ACMP_APORTCONFLICT_APORT2XCONFLICT_DEFAULT    0x00000000UL                                       /**< Mode DEFAULT for ACMP_APORTCONFLICT */
+#define ACMP_APORTCONFLICT_APORT2XCONFLICT_DEFAULT     (_ACMP_APORTCONFLICT_APORT2XCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */
+#define ACMP_APORTCONFLICT_APORT2YCONFLICT             (0x1UL << 5)                                       /**< 1 if the bus connected to APORT2Y is in conflict with another peripheral */
+#define _ACMP_APORTCONFLICT_APORT2YCONFLICT_SHIFT      5                                                  /**< Shift value for ACMP_APORT2YCONFLICT */
+#define _ACMP_APORTCONFLICT_APORT2YCONFLICT_MASK       0x20UL                                             /**< Bit mask for ACMP_APORT2YCONFLICT */
+#define _ACMP_APORTCONFLICT_APORT2YCONFLICT_DEFAULT    0x00000000UL                                       /**< Mode DEFAULT for ACMP_APORTCONFLICT */
+#define ACMP_APORTCONFLICT_APORT2YCONFLICT_DEFAULT     (_ACMP_APORTCONFLICT_APORT2YCONFLICT_DEFAULT << 5) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */
+#define ACMP_APORTCONFLICT_APORT3XCONFLICT             (0x1UL << 6)                                       /**< 1 if the bus connected to APORT3X is in conflict with another peripheral */
+#define _ACMP_APORTCONFLICT_APORT3XCONFLICT_SHIFT      6                                                  /**< Shift value for ACMP_APORT3XCONFLICT */
+#define _ACMP_APORTCONFLICT_APORT3XCONFLICT_MASK       0x40UL                                             /**< Bit mask for ACMP_APORT3XCONFLICT */
+#define _ACMP_APORTCONFLICT_APORT3XCONFLICT_DEFAULT    0x00000000UL                                       /**< Mode DEFAULT for ACMP_APORTCONFLICT */
+#define ACMP_APORTCONFLICT_APORT3XCONFLICT_DEFAULT     (_ACMP_APORTCONFLICT_APORT3XCONFLICT_DEFAULT << 6) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */
+#define ACMP_APORTCONFLICT_APORT3YCONFLICT             (0x1UL << 7)                                       /**< 1 if the bus connected to APORT3Y is in conflict with another peripheral */
+#define _ACMP_APORTCONFLICT_APORT3YCONFLICT_SHIFT      7                                                  /**< Shift value for ACMP_APORT3YCONFLICT */
+#define _ACMP_APORTCONFLICT_APORT3YCONFLICT_MASK       0x80UL                                             /**< Bit mask for ACMP_APORT3YCONFLICT */
+#define _ACMP_APORTCONFLICT_APORT3YCONFLICT_DEFAULT    0x00000000UL                                       /**< Mode DEFAULT for ACMP_APORTCONFLICT */
+#define ACMP_APORTCONFLICT_APORT3YCONFLICT_DEFAULT     (_ACMP_APORTCONFLICT_APORT3YCONFLICT_DEFAULT << 7) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */
+#define ACMP_APORTCONFLICT_APORT4XCONFLICT             (0x1UL << 8)                                       /**< 1 if the bus connected to APORT4X is in conflict with another peripheral */
+#define _ACMP_APORTCONFLICT_APORT4XCONFLICT_SHIFT      8                                                  /**< Shift value for ACMP_APORT4XCONFLICT */
+#define _ACMP_APORTCONFLICT_APORT4XCONFLICT_MASK       0x100UL                                            /**< Bit mask for ACMP_APORT4XCONFLICT */
+#define _ACMP_APORTCONFLICT_APORT4XCONFLICT_DEFAULT    0x00000000UL                                       /**< Mode DEFAULT for ACMP_APORTCONFLICT */
+#define ACMP_APORTCONFLICT_APORT4XCONFLICT_DEFAULT     (_ACMP_APORTCONFLICT_APORT4XCONFLICT_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */
+#define ACMP_APORTCONFLICT_APORT4YCONFLICT             (0x1UL << 9)                                       /**< 1 if the bus connected to APORT4Y is in conflict with another peripheral */
+#define _ACMP_APORTCONFLICT_APORT4YCONFLICT_SHIFT      9                                                  /**< Shift value for ACMP_APORT4YCONFLICT */
+#define _ACMP_APORTCONFLICT_APORT4YCONFLICT_MASK       0x200UL                                            /**< Bit mask for ACMP_APORT4YCONFLICT */
+#define _ACMP_APORTCONFLICT_APORT4YCONFLICT_DEFAULT    0x00000000UL                                       /**< Mode DEFAULT for ACMP_APORTCONFLICT */
+#define ACMP_APORTCONFLICT_APORT4YCONFLICT_DEFAULT     (_ACMP_APORTCONFLICT_APORT4YCONFLICT_DEFAULT << 9) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */
+
+/* Bit fields for ACMP HYSTERESIS0 */
+#define _ACMP_HYSTERESIS0_RESETVALUE                   0x00000000UL                            /**< Default value for ACMP_HYSTERESIS0 */
+#define _ACMP_HYSTERESIS0_MASK                         0x3F3F000FUL                            /**< Mask for ACMP_HYSTERESIS0 */
+#define _ACMP_HYSTERESIS0_HYST_SHIFT                   0                                       /**< Shift value for ACMP_HYST */
+#define _ACMP_HYSTERESIS0_HYST_MASK                    0xFUL                                   /**< Bit mask for ACMP_HYST */
+#define _ACMP_HYSTERESIS0_HYST_DEFAULT                 0x00000000UL                            /**< Mode DEFAULT for ACMP_HYSTERESIS0 */
+#define _ACMP_HYSTERESIS0_HYST_HYST0                   0x00000000UL                            /**< Mode HYST0 for ACMP_HYSTERESIS0 */
+#define _ACMP_HYSTERESIS0_HYST_HYST1                   0x00000001UL                            /**< Mode HYST1 for ACMP_HYSTERESIS0 */
+#define _ACMP_HYSTERESIS0_HYST_HYST2                   0x00000002UL                            /**< Mode HYST2 for ACMP_HYSTERESIS0 */
+#define _ACMP_HYSTERESIS0_HYST_HYST3                   0x00000003UL                            /**< Mode HYST3 for ACMP_HYSTERESIS0 */
+#define _ACMP_HYSTERESIS0_HYST_HYST4                   0x00000004UL                            /**< Mode HYST4 for ACMP_HYSTERESIS0 */
+#define _ACMP_HYSTERESIS0_HYST_HYST5                   0x00000005UL                            /**< Mode HYST5 for ACMP_HYSTERESIS0 */
+#define _ACMP_HYSTERESIS0_HYST_HYST6                   0x00000006UL                            /**< Mode HYST6 for ACMP_HYSTERESIS0 */
+#define _ACMP_HYSTERESIS0_HYST_HYST7                   0x00000007UL                            /**< Mode HYST7 for ACMP_HYSTERESIS0 */
+#define _ACMP_HYSTERESIS0_HYST_HYST8                   0x00000008UL                            /**< Mode HYST8 for ACMP_HYSTERESIS0 */
+#define _ACMP_HYSTERESIS0_HYST_HYST9                   0x00000009UL                            /**< Mode HYST9 for ACMP_HYSTERESIS0 */
+#define _ACMP_HYSTERESIS0_HYST_HYST10                  0x0000000AUL                            /**< Mode HYST10 for ACMP_HYSTERESIS0 */
+#define _ACMP_HYSTERESIS0_HYST_HYST11                  0x0000000BUL                            /**< Mode HYST11 for ACMP_HYSTERESIS0 */
+#define _ACMP_HYSTERESIS0_HYST_HYST12                  0x0000000CUL                            /**< Mode HYST12 for ACMP_HYSTERESIS0 */
+#define _ACMP_HYSTERESIS0_HYST_HYST13                  0x0000000DUL                            /**< Mode HYST13 for ACMP_HYSTERESIS0 */
+#define _ACMP_HYSTERESIS0_HYST_HYST14                  0x0000000EUL                            /**< Mode HYST14 for ACMP_HYSTERESIS0 */
+#define _ACMP_HYSTERESIS0_HYST_HYST15                  0x0000000FUL                            /**< Mode HYST15 for ACMP_HYSTERESIS0 */
+#define ACMP_HYSTERESIS0_HYST_DEFAULT                  (_ACMP_HYSTERESIS0_HYST_DEFAULT << 0)   /**< Shifted mode DEFAULT for ACMP_HYSTERESIS0 */
+#define ACMP_HYSTERESIS0_HYST_HYST0                    (_ACMP_HYSTERESIS0_HYST_HYST0 << 0)     /**< Shifted mode HYST0 for ACMP_HYSTERESIS0 */
+#define ACMP_HYSTERESIS0_HYST_HYST1                    (_ACMP_HYSTERESIS0_HYST_HYST1 << 0)     /**< Shifted mode HYST1 for ACMP_HYSTERESIS0 */
+#define ACMP_HYSTERESIS0_HYST_HYST2                    (_ACMP_HYSTERESIS0_HYST_HYST2 << 0)     /**< Shifted mode HYST2 for ACMP_HYSTERESIS0 */
+#define ACMP_HYSTERESIS0_HYST_HYST3                    (_ACMP_HYSTERESIS0_HYST_HYST3 << 0)     /**< Shifted mode HYST3 for ACMP_HYSTERESIS0 */
+#define ACMP_HYSTERESIS0_HYST_HYST4                    (_ACMP_HYSTERESIS0_HYST_HYST4 << 0)     /**< Shifted mode HYST4 for ACMP_HYSTERESIS0 */
+#define ACMP_HYSTERESIS0_HYST_HYST5                    (_ACMP_HYSTERESIS0_HYST_HYST5 << 0)     /**< Shifted mode HYST5 for ACMP_HYSTERESIS0 */
+#define ACMP_HYSTERESIS0_HYST_HYST6                    (_ACMP_HYSTERESIS0_HYST_HYST6 << 0)     /**< Shifted mode HYST6 for ACMP_HYSTERESIS0 */
+#define ACMP_HYSTERESIS0_HYST_HYST7                    (_ACMP_HYSTERESIS0_HYST_HYST7 << 0)     /**< Shifted mode HYST7 for ACMP_HYSTERESIS0 */
+#define ACMP_HYSTERESIS0_HYST_HYST8                    (_ACMP_HYSTERESIS0_HYST_HYST8 << 0)     /**< Shifted mode HYST8 for ACMP_HYSTERESIS0 */
+#define ACMP_HYSTERESIS0_HYST_HYST9                    (_ACMP_HYSTERESIS0_HYST_HYST9 << 0)     /**< Shifted mode HYST9 for ACMP_HYSTERESIS0 */
+#define ACMP_HYSTERESIS0_HYST_HYST10                   (_ACMP_HYSTERESIS0_HYST_HYST10 << 0)    /**< Shifted mode HYST10 for ACMP_HYSTERESIS0 */
+#define ACMP_HYSTERESIS0_HYST_HYST11                   (_ACMP_HYSTERESIS0_HYST_HYST11 << 0)    /**< Shifted mode HYST11 for ACMP_HYSTERESIS0 */
+#define ACMP_HYSTERESIS0_HYST_HYST12                   (_ACMP_HYSTERESIS0_HYST_HYST12 << 0)    /**< Shifted mode HYST12 for ACMP_HYSTERESIS0 */
+#define ACMP_HYSTERESIS0_HYST_HYST13                   (_ACMP_HYSTERESIS0_HYST_HYST13 << 0)    /**< Shifted mode HYST13 for ACMP_HYSTERESIS0 */
+#define ACMP_HYSTERESIS0_HYST_HYST14                   (_ACMP_HYSTERESIS0_HYST_HYST14 << 0)    /**< Shifted mode HYST14 for ACMP_HYSTERESIS0 */
+#define ACMP_HYSTERESIS0_HYST_HYST15                   (_ACMP_HYSTERESIS0_HYST_HYST15 << 0)    /**< Shifted mode HYST15 for ACMP_HYSTERESIS0 */
+#define _ACMP_HYSTERESIS0_DIVVA_SHIFT                  16                                      /**< Shift value for ACMP_DIVVA */
+#define _ACMP_HYSTERESIS0_DIVVA_MASK                   0x3F0000UL                              /**< Bit mask for ACMP_DIVVA */
+#define _ACMP_HYSTERESIS0_DIVVA_DEFAULT                0x00000000UL                            /**< Mode DEFAULT for ACMP_HYSTERESIS0 */
+#define ACMP_HYSTERESIS0_DIVVA_DEFAULT                 (_ACMP_HYSTERESIS0_DIVVA_DEFAULT << 16) /**< Shifted mode DEFAULT for ACMP_HYSTERESIS0 */
+#define _ACMP_HYSTERESIS0_DIVVB_SHIFT                  24                                      /**< Shift value for ACMP_DIVVB */
+#define _ACMP_HYSTERESIS0_DIVVB_MASK                   0x3F000000UL                            /**< Bit mask for ACMP_DIVVB */
+#define _ACMP_HYSTERESIS0_DIVVB_DEFAULT                0x00000000UL                            /**< Mode DEFAULT for ACMP_HYSTERESIS0 */
+#define ACMP_HYSTERESIS0_DIVVB_DEFAULT                 (_ACMP_HYSTERESIS0_DIVVB_DEFAULT << 24) /**< Shifted mode DEFAULT for ACMP_HYSTERESIS0 */
+
+/* Bit fields for ACMP HYSTERESIS1 */
+#define _ACMP_HYSTERESIS1_RESETVALUE                   0x00000000UL                            /**< Default value for ACMP_HYSTERESIS1 */
+#define _ACMP_HYSTERESIS1_MASK                         0x3F3F000FUL                            /**< Mask for ACMP_HYSTERESIS1 */
+#define _ACMP_HYSTERESIS1_HYST_SHIFT                   0                                       /**< Shift value for ACMP_HYST */
+#define _ACMP_HYSTERESIS1_HYST_MASK                    0xFUL                                   /**< Bit mask for ACMP_HYST */
+#define _ACMP_HYSTERESIS1_HYST_DEFAULT                 0x00000000UL                            /**< Mode DEFAULT for ACMP_HYSTERESIS1 */
+#define _ACMP_HYSTERESIS1_HYST_HYST0                   0x00000000UL                            /**< Mode HYST0 for ACMP_HYSTERESIS1 */
+#define _ACMP_HYSTERESIS1_HYST_HYST1                   0x00000001UL                            /**< Mode HYST1 for ACMP_HYSTERESIS1 */
+#define _ACMP_HYSTERESIS1_HYST_HYST2                   0x00000002UL                            /**< Mode HYST2 for ACMP_HYSTERESIS1 */
+#define _ACMP_HYSTERESIS1_HYST_HYST3                   0x00000003UL                            /**< Mode HYST3 for ACMP_HYSTERESIS1 */
+#define _ACMP_HYSTERESIS1_HYST_HYST4                   0x00000004UL                            /**< Mode HYST4 for ACMP_HYSTERESIS1 */
+#define _ACMP_HYSTERESIS1_HYST_HYST5                   0x00000005UL                            /**< Mode HYST5 for ACMP_HYSTERESIS1 */
+#define _ACMP_HYSTERESIS1_HYST_HYST6                   0x00000006UL                            /**< Mode HYST6 for ACMP_HYSTERESIS1 */
+#define _ACMP_HYSTERESIS1_HYST_HYST7                   0x00000007UL                            /**< Mode HYST7 for ACMP_HYSTERESIS1 */
+#define _ACMP_HYSTERESIS1_HYST_HYST8                   0x00000008UL                            /**< Mode HYST8 for ACMP_HYSTERESIS1 */
+#define _ACMP_HYSTERESIS1_HYST_HYST9                   0x00000009UL                            /**< Mode HYST9 for ACMP_HYSTERESIS1 */
+#define _ACMP_HYSTERESIS1_HYST_HYST10                  0x0000000AUL                            /**< Mode HYST10 for ACMP_HYSTERESIS1 */
+#define _ACMP_HYSTERESIS1_HYST_HYST11                  0x0000000BUL                            /**< Mode HYST11 for ACMP_HYSTERESIS1 */
+#define _ACMP_HYSTERESIS1_HYST_HYST12                  0x0000000CUL                            /**< Mode HYST12 for ACMP_HYSTERESIS1 */
+#define _ACMP_HYSTERESIS1_HYST_HYST13                  0x0000000DUL                            /**< Mode HYST13 for ACMP_HYSTERESIS1 */
+#define _ACMP_HYSTERESIS1_HYST_HYST14                  0x0000000EUL                            /**< Mode HYST14 for ACMP_HYSTERESIS1 */
+#define _ACMP_HYSTERESIS1_HYST_HYST15                  0x0000000FUL                            /**< Mode HYST15 for ACMP_HYSTERESIS1 */
+#define ACMP_HYSTERESIS1_HYST_DEFAULT                  (_ACMP_HYSTERESIS1_HYST_DEFAULT << 0)   /**< Shifted mode DEFAULT for ACMP_HYSTERESIS1 */
+#define ACMP_HYSTERESIS1_HYST_HYST0                    (_ACMP_HYSTERESIS1_HYST_HYST0 << 0)     /**< Shifted mode HYST0 for ACMP_HYSTERESIS1 */
+#define ACMP_HYSTERESIS1_HYST_HYST1                    (_ACMP_HYSTERESIS1_HYST_HYST1 << 0)     /**< Shifted mode HYST1 for ACMP_HYSTERESIS1 */
+#define ACMP_HYSTERESIS1_HYST_HYST2                    (_ACMP_HYSTERESIS1_HYST_HYST2 << 0)     /**< Shifted mode HYST2 for ACMP_HYSTERESIS1 */
+#define ACMP_HYSTERESIS1_HYST_HYST3                    (_ACMP_HYSTERESIS1_HYST_HYST3 << 0)     /**< Shifted mode HYST3 for ACMP_HYSTERESIS1 */
+#define ACMP_HYSTERESIS1_HYST_HYST4                    (_ACMP_HYSTERESIS1_HYST_HYST4 << 0)     /**< Shifted mode HYST4 for ACMP_HYSTERESIS1 */
+#define ACMP_HYSTERESIS1_HYST_HYST5                    (_ACMP_HYSTERESIS1_HYST_HYST5 << 0)     /**< Shifted mode HYST5 for ACMP_HYSTERESIS1 */
+#define ACMP_HYSTERESIS1_HYST_HYST6                    (_ACMP_HYSTERESIS1_HYST_HYST6 << 0)     /**< Shifted mode HYST6 for ACMP_HYSTERESIS1 */
+#define ACMP_HYSTERESIS1_HYST_HYST7                    (_ACMP_HYSTERESIS1_HYST_HYST7 << 0)     /**< Shifted mode HYST7 for ACMP_HYSTERESIS1 */
+#define ACMP_HYSTERESIS1_HYST_HYST8                    (_ACMP_HYSTERESIS1_HYST_HYST8 << 0)     /**< Shifted mode HYST8 for ACMP_HYSTERESIS1 */
+#define ACMP_HYSTERESIS1_HYST_HYST9                    (_ACMP_HYSTERESIS1_HYST_HYST9 << 0)     /**< Shifted mode HYST9 for ACMP_HYSTERESIS1 */
+#define ACMP_HYSTERESIS1_HYST_HYST10                   (_ACMP_HYSTERESIS1_HYST_HYST10 << 0)    /**< Shifted mode HYST10 for ACMP_HYSTERESIS1 */
+#define ACMP_HYSTERESIS1_HYST_HYST11                   (_ACMP_HYSTERESIS1_HYST_HYST11 << 0)    /**< Shifted mode HYST11 for ACMP_HYSTERESIS1 */
+#define ACMP_HYSTERESIS1_HYST_HYST12                   (_ACMP_HYSTERESIS1_HYST_HYST12 << 0)    /**< Shifted mode HYST12 for ACMP_HYSTERESIS1 */
+#define ACMP_HYSTERESIS1_HYST_HYST13                   (_ACMP_HYSTERESIS1_HYST_HYST13 << 0)    /**< Shifted mode HYST13 for ACMP_HYSTERESIS1 */
+#define ACMP_HYSTERESIS1_HYST_HYST14                   (_ACMP_HYSTERESIS1_HYST_HYST14 << 0)    /**< Shifted mode HYST14 for ACMP_HYSTERESIS1 */
+#define ACMP_HYSTERESIS1_HYST_HYST15                   (_ACMP_HYSTERESIS1_HYST_HYST15 << 0)    /**< Shifted mode HYST15 for ACMP_HYSTERESIS1 */
+#define _ACMP_HYSTERESIS1_DIVVA_SHIFT                  16                                      /**< Shift value for ACMP_DIVVA */
+#define _ACMP_HYSTERESIS1_DIVVA_MASK                   0x3F0000UL                              /**< Bit mask for ACMP_DIVVA */
+#define _ACMP_HYSTERESIS1_DIVVA_DEFAULT                0x00000000UL                            /**< Mode DEFAULT for ACMP_HYSTERESIS1 */
+#define ACMP_HYSTERESIS1_DIVVA_DEFAULT                 (_ACMP_HYSTERESIS1_DIVVA_DEFAULT << 16) /**< Shifted mode DEFAULT for ACMP_HYSTERESIS1 */
+#define _ACMP_HYSTERESIS1_DIVVB_SHIFT                  24                                      /**< Shift value for ACMP_DIVVB */
+#define _ACMP_HYSTERESIS1_DIVVB_MASK                   0x3F000000UL                            /**< Bit mask for ACMP_DIVVB */
+#define _ACMP_HYSTERESIS1_DIVVB_DEFAULT                0x00000000UL                            /**< Mode DEFAULT for ACMP_HYSTERESIS1 */
+#define ACMP_HYSTERESIS1_DIVVB_DEFAULT                 (_ACMP_HYSTERESIS1_DIVVB_DEFAULT << 24) /**< Shifted mode DEFAULT for ACMP_HYSTERESIS1 */
+
+/* Bit fields for ACMP ROUTEPEN */
+#define _ACMP_ROUTEPEN_RESETVALUE                      0x00000000UL                         /**< Default value for ACMP_ROUTEPEN */
+#define _ACMP_ROUTEPEN_MASK                            0x00000001UL                         /**< Mask for ACMP_ROUTEPEN */
+#define ACMP_ROUTEPEN_OUTPEN                           (0x1UL << 0)                         /**< ACMP Output Pin Enable */
+#define _ACMP_ROUTEPEN_OUTPEN_SHIFT                    0                                    /**< Shift value for ACMP_OUTPEN */
+#define _ACMP_ROUTEPEN_OUTPEN_MASK                     0x1UL                                /**< Bit mask for ACMP_OUTPEN */
+#define _ACMP_ROUTEPEN_OUTPEN_DEFAULT                  0x00000000UL                         /**< Mode DEFAULT for ACMP_ROUTEPEN */
+#define ACMP_ROUTEPEN_OUTPEN_DEFAULT                   (_ACMP_ROUTEPEN_OUTPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_ROUTEPEN */
+
+/* Bit fields for ACMP ROUTELOC0 */
+#define _ACMP_ROUTELOC0_RESETVALUE                     0x00000000UL                          /**< Default value for ACMP_ROUTELOC0 */
+#define _ACMP_ROUTELOC0_MASK                           0x0000001FUL                          /**< Mask for ACMP_ROUTELOC0 */
+#define _ACMP_ROUTELOC0_OUTLOC_SHIFT                   0                                     /**< Shift value for ACMP_OUTLOC */
+#define _ACMP_ROUTELOC0_OUTLOC_MASK                    0x1FUL                                /**< Bit mask for ACMP_OUTLOC */
+#define _ACMP_ROUTELOC0_OUTLOC_LOC0                    0x00000000UL                          /**< Mode LOC0 for ACMP_ROUTELOC0 */
+#define _ACMP_ROUTELOC0_OUTLOC_DEFAULT                 0x00000000UL                          /**< Mode DEFAULT for ACMP_ROUTELOC0 */
+#define _ACMP_ROUTELOC0_OUTLOC_LOC1                    0x00000001UL                          /**< Mode LOC1 for ACMP_ROUTELOC0 */
+#define _ACMP_ROUTELOC0_OUTLOC_LOC2                    0x00000002UL                          /**< Mode LOC2 for ACMP_ROUTELOC0 */
+#define _ACMP_ROUTELOC0_OUTLOC_LOC3                    0x00000003UL                          /**< Mode LOC3 for ACMP_ROUTELOC0 */
+#define _ACMP_ROUTELOC0_OUTLOC_LOC4                    0x00000004UL                          /**< Mode LOC4 for ACMP_ROUTELOC0 */
+#define _ACMP_ROUTELOC0_OUTLOC_LOC5                    0x00000005UL                          /**< Mode LOC5 for ACMP_ROUTELOC0 */
+#define _ACMP_ROUTELOC0_OUTLOC_LOC6                    0x00000006UL                          /**< Mode LOC6 for ACMP_ROUTELOC0 */
+#define _ACMP_ROUTELOC0_OUTLOC_LOC7                    0x00000007UL                          /**< Mode LOC7 for ACMP_ROUTELOC0 */
+#define _ACMP_ROUTELOC0_OUTLOC_LOC8                    0x00000008UL                          /**< Mode LOC8 for ACMP_ROUTELOC0 */
+#define _ACMP_ROUTELOC0_OUTLOC_LOC9                    0x00000009UL                          /**< Mode LOC9 for ACMP_ROUTELOC0 */
+#define _ACMP_ROUTELOC0_OUTLOC_LOC10                   0x0000000AUL                          /**< Mode LOC10 for ACMP_ROUTELOC0 */
+#define _ACMP_ROUTELOC0_OUTLOC_LOC11                   0x0000000BUL                          /**< Mode LOC11 for ACMP_ROUTELOC0 */
+#define _ACMP_ROUTELOC0_OUTLOC_LOC12                   0x0000000CUL                          /**< Mode LOC12 for ACMP_ROUTELOC0 */
+#define _ACMP_ROUTELOC0_OUTLOC_LOC13                   0x0000000DUL                          /**< Mode LOC13 for ACMP_ROUTELOC0 */
+#define _ACMP_ROUTELOC0_OUTLOC_LOC14                   0x0000000EUL                          /**< Mode LOC14 for ACMP_ROUTELOC0 */
+#define _ACMP_ROUTELOC0_OUTLOC_LOC15                   0x0000000FUL                          /**< Mode LOC15 for ACMP_ROUTELOC0 */
+#define _ACMP_ROUTELOC0_OUTLOC_LOC16                   0x00000010UL                          /**< Mode LOC16 for ACMP_ROUTELOC0 */
+#define _ACMP_ROUTELOC0_OUTLOC_LOC17                   0x00000011UL                          /**< Mode LOC17 for ACMP_ROUTELOC0 */
+#define _ACMP_ROUTELOC0_OUTLOC_LOC18                   0x00000012UL                          /**< Mode LOC18 for ACMP_ROUTELOC0 */
+#define _ACMP_ROUTELOC0_OUTLOC_LOC19                   0x00000013UL                          /**< Mode LOC19 for ACMP_ROUTELOC0 */
+#define _ACMP_ROUTELOC0_OUTLOC_LOC20                   0x00000014UL                          /**< Mode LOC20 for ACMP_ROUTELOC0 */
+#define _ACMP_ROUTELOC0_OUTLOC_LOC21                   0x00000015UL                          /**< Mode LOC21 for ACMP_ROUTELOC0 */
+#define _ACMP_ROUTELOC0_OUTLOC_LOC22                   0x00000016UL                          /**< Mode LOC22 for ACMP_ROUTELOC0 */
+#define _ACMP_ROUTELOC0_OUTLOC_LOC23                   0x00000017UL                          /**< Mode LOC23 for ACMP_ROUTELOC0 */
+#define _ACMP_ROUTELOC0_OUTLOC_LOC24                   0x00000018UL                          /**< Mode LOC24 for ACMP_ROUTELOC0 */
+#define _ACMP_ROUTELOC0_OUTLOC_LOC25                   0x00000019UL                          /**< Mode LOC25 for ACMP_ROUTELOC0 */
+#define _ACMP_ROUTELOC0_OUTLOC_LOC26                   0x0000001AUL                          /**< Mode LOC26 for ACMP_ROUTELOC0 */
+#define _ACMP_ROUTELOC0_OUTLOC_LOC27                   0x0000001BUL                          /**< Mode LOC27 for ACMP_ROUTELOC0 */
+#define _ACMP_ROUTELOC0_OUTLOC_LOC28                   0x0000001CUL                          /**< Mode LOC28 for ACMP_ROUTELOC0 */
+#define _ACMP_ROUTELOC0_OUTLOC_LOC29                   0x0000001DUL                          /**< Mode LOC29 for ACMP_ROUTELOC0 */
+#define _ACMP_ROUTELOC0_OUTLOC_LOC30                   0x0000001EUL                          /**< Mode LOC30 for ACMP_ROUTELOC0 */
+#define _ACMP_ROUTELOC0_OUTLOC_LOC31                   0x0000001FUL                          /**< Mode LOC31 for ACMP_ROUTELOC0 */
+#define ACMP_ROUTELOC0_OUTLOC_LOC0                     (_ACMP_ROUTELOC0_OUTLOC_LOC0 << 0)    /**< Shifted mode LOC0 for ACMP_ROUTELOC0 */
+#define ACMP_ROUTELOC0_OUTLOC_DEFAULT                  (_ACMP_ROUTELOC0_OUTLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_ROUTELOC0 */
+#define ACMP_ROUTELOC0_OUTLOC_LOC1                     (_ACMP_ROUTELOC0_OUTLOC_LOC1 << 0)    /**< Shifted mode LOC1 for ACMP_ROUTELOC0 */
+#define ACMP_ROUTELOC0_OUTLOC_LOC2                     (_ACMP_ROUTELOC0_OUTLOC_LOC2 << 0)    /**< Shifted mode LOC2 for ACMP_ROUTELOC0 */
+#define ACMP_ROUTELOC0_OUTLOC_LOC3                     (_ACMP_ROUTELOC0_OUTLOC_LOC3 << 0)    /**< Shifted mode LOC3 for ACMP_ROUTELOC0 */
+#define ACMP_ROUTELOC0_OUTLOC_LOC4                     (_ACMP_ROUTELOC0_OUTLOC_LOC4 << 0)    /**< Shifted mode LOC4 for ACMP_ROUTELOC0 */
+#define ACMP_ROUTELOC0_OUTLOC_LOC5                     (_ACMP_ROUTELOC0_OUTLOC_LOC5 << 0)    /**< Shifted mode LOC5 for ACMP_ROUTELOC0 */
+#define ACMP_ROUTELOC0_OUTLOC_LOC6                     (_ACMP_ROUTELOC0_OUTLOC_LOC6 << 0)    /**< Shifted mode LOC6 for ACMP_ROUTELOC0 */
+#define ACMP_ROUTELOC0_OUTLOC_LOC7                     (_ACMP_ROUTELOC0_OUTLOC_LOC7 << 0)    /**< Shifted mode LOC7 for ACMP_ROUTELOC0 */
+#define ACMP_ROUTELOC0_OUTLOC_LOC8                     (_ACMP_ROUTELOC0_OUTLOC_LOC8 << 0)    /**< Shifted mode LOC8 for ACMP_ROUTELOC0 */
+#define ACMP_ROUTELOC0_OUTLOC_LOC9                     (_ACMP_ROUTELOC0_OUTLOC_LOC9 << 0)    /**< Shifted mode LOC9 for ACMP_ROUTELOC0 */
+#define ACMP_ROUTELOC0_OUTLOC_LOC10                    (_ACMP_ROUTELOC0_OUTLOC_LOC10 << 0)   /**< Shifted mode LOC10 for ACMP_ROUTELOC0 */
+#define ACMP_ROUTELOC0_OUTLOC_LOC11                    (_ACMP_ROUTELOC0_OUTLOC_LOC11 << 0)   /**< Shifted mode LOC11 for ACMP_ROUTELOC0 */
+#define ACMP_ROUTELOC0_OUTLOC_LOC12                    (_ACMP_ROUTELOC0_OUTLOC_LOC12 << 0)   /**< Shifted mode LOC12 for ACMP_ROUTELOC0 */
+#define ACMP_ROUTELOC0_OUTLOC_LOC13                    (_ACMP_ROUTELOC0_OUTLOC_LOC13 << 0)   /**< Shifted mode LOC13 for ACMP_ROUTELOC0 */
+#define ACMP_ROUTELOC0_OUTLOC_LOC14                    (_ACMP_ROUTELOC0_OUTLOC_LOC14 << 0)   /**< Shifted mode LOC14 for ACMP_ROUTELOC0 */
+#define ACMP_ROUTELOC0_OUTLOC_LOC15                    (_ACMP_ROUTELOC0_OUTLOC_LOC15 << 0)   /**< Shifted mode LOC15 for ACMP_ROUTELOC0 */
+#define ACMP_ROUTELOC0_OUTLOC_LOC16                    (_ACMP_ROUTELOC0_OUTLOC_LOC16 << 0)   /**< Shifted mode LOC16 for ACMP_ROUTELOC0 */
+#define ACMP_ROUTELOC0_OUTLOC_LOC17                    (_ACMP_ROUTELOC0_OUTLOC_LOC17 << 0)   /**< Shifted mode LOC17 for ACMP_ROUTELOC0 */
+#define ACMP_ROUTELOC0_OUTLOC_LOC18                    (_ACMP_ROUTELOC0_OUTLOC_LOC18 << 0)   /**< Shifted mode LOC18 for ACMP_ROUTELOC0 */
+#define ACMP_ROUTELOC0_OUTLOC_LOC19                    (_ACMP_ROUTELOC0_OUTLOC_LOC19 << 0)   /**< Shifted mode LOC19 for ACMP_ROUTELOC0 */
+#define ACMP_ROUTELOC0_OUTLOC_LOC20                    (_ACMP_ROUTELOC0_OUTLOC_LOC20 << 0)   /**< Shifted mode LOC20 for ACMP_ROUTELOC0 */
+#define ACMP_ROUTELOC0_OUTLOC_LOC21                    (_ACMP_ROUTELOC0_OUTLOC_LOC21 << 0)   /**< Shifted mode LOC21 for ACMP_ROUTELOC0 */
+#define ACMP_ROUTELOC0_OUTLOC_LOC22                    (_ACMP_ROUTELOC0_OUTLOC_LOC22 << 0)   /**< Shifted mode LOC22 for ACMP_ROUTELOC0 */
+#define ACMP_ROUTELOC0_OUTLOC_LOC23                    (_ACMP_ROUTELOC0_OUTLOC_LOC23 << 0)   /**< Shifted mode LOC23 for ACMP_ROUTELOC0 */
+#define ACMP_ROUTELOC0_OUTLOC_LOC24                    (_ACMP_ROUTELOC0_OUTLOC_LOC24 << 0)   /**< Shifted mode LOC24 for ACMP_ROUTELOC0 */
+#define ACMP_ROUTELOC0_OUTLOC_LOC25                    (_ACMP_ROUTELOC0_OUTLOC_LOC25 << 0)   /**< Shifted mode LOC25 for ACMP_ROUTELOC0 */
+#define ACMP_ROUTELOC0_OUTLOC_LOC26                    (_ACMP_ROUTELOC0_OUTLOC_LOC26 << 0)   /**< Shifted mode LOC26 for ACMP_ROUTELOC0 */
+#define ACMP_ROUTELOC0_OUTLOC_LOC27                    (_ACMP_ROUTELOC0_OUTLOC_LOC27 << 0)   /**< Shifted mode LOC27 for ACMP_ROUTELOC0 */
+#define ACMP_ROUTELOC0_OUTLOC_LOC28                    (_ACMP_ROUTELOC0_OUTLOC_LOC28 << 0)   /**< Shifted mode LOC28 for ACMP_ROUTELOC0 */
+#define ACMP_ROUTELOC0_OUTLOC_LOC29                    (_ACMP_ROUTELOC0_OUTLOC_LOC29 << 0)   /**< Shifted mode LOC29 for ACMP_ROUTELOC0 */
+#define ACMP_ROUTELOC0_OUTLOC_LOC30                    (_ACMP_ROUTELOC0_OUTLOC_LOC30 << 0)   /**< Shifted mode LOC30 for ACMP_ROUTELOC0 */
+#define ACMP_ROUTELOC0_OUTLOC_LOC31                    (_ACMP_ROUTELOC0_OUTLOC_LOC31 << 0)   /**< Shifted mode LOC31 for ACMP_ROUTELOC0 */
+
+/** @} End of group EFM32PG1B_ACMP */
+/** @} End of group Parts */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG_STK3401/efm32pg1b_adc.h	Fri Jan 15 07:45:16 2016 +0000
@@ -0,0 +1,2222 @@
+/**************************************************************************//**
+ * @file efm32pg1b_adc.h
+ * @brief EFM32PG1B_ADC register and bit field definitions
+ * @version 4.2.0
+ ******************************************************************************
+ * @section License
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ ******************************************************************************
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software.@n
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.@n
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is
+ * providing the Software "AS IS", with no express or implied warranties of any
+ * kind, including, but not limited to, any implied warranties of
+ * merchantability or fitness for any particular purpose or warranties against
+ * infringement of any proprietary rights of a third party.
+ *
+ * Silicon Laboratories, Inc. will not be liable for any consequential,
+ * incidental, or special damages, or any other relief, or for any claim by
+ * any third party, arising from your use of this Software.
+ *
+ *****************************************************************************/
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFM32PG1B_ADC
+ * @{
+ * @brief EFM32PG1B_ADC Register Declaration
+ *****************************************************************************/
+typedef struct
+{
+  __IO uint32_t CTRL;            /**< Control Register  */
+  uint32_t      RESERVED0[1];    /**< Reserved for future use **/
+  __IO uint32_t CMD;             /**< Command Register  */
+  __I uint32_t  STATUS;          /**< Status Register  */
+  __IO uint32_t SINGLECTRL;      /**< Single Channel Control Register  */
+  __IO uint32_t SINGLECTRLX;     /**< Single Channel Control Register continued  */
+  __IO uint32_t SCANCTRL;        /**< Scan Control Register  */
+  __IO uint32_t SCANCTRLX;       /**< Scan Control Register continued  */
+  __IO uint32_t SCANMASK;        /**< Scan Sequence Input Mask Register  */
+  __IO uint32_t SCANINPUTSEL;    /**< Input Selection register for Scan mode  */
+  __IO uint32_t SCANNEGSEL;      /**< Negative Input select register for Scan  */
+  __IO uint32_t CMPTHR;          /**< Compare Threshold Register  */
+  __IO uint32_t BIASPROG;        /**< Bias Programming Register for various analog blocks used in ADC operation  */
+  __IO uint32_t CAL;             /**< Calibration Register  */
+  __I uint32_t  IF;              /**< Interrupt Flag Register  */
+  __IO uint32_t IFS;             /**< Interrupt Flag Set Register  */
+  __IO uint32_t IFC;             /**< Interrupt Flag Clear Register  */
+  __IO uint32_t IEN;             /**< Interrupt Enable Register  */
+  __I uint32_t  SINGLEDATA;      /**< Single Conversion Result Data  */
+  __I uint32_t  SCANDATA;        /**< Scan Conversion Result Data  */
+  __I uint32_t  SINGLEDATAP;     /**< Single Conversion Result Data Peek Register  */
+  __I uint32_t  SCANDATAP;       /**< Scan Sequence Result Data Peek Register  */
+  uint32_t      RESERVED1[4];    /**< Reserved for future use **/
+  __I uint32_t  SCANDATAX;       /**< Scan Sequence Result Data + Data Source Register  */
+  __I uint32_t  SCANDATAXP;      /**< Scan Sequence Result Data + Data Source Peek Register  */
+
+  uint32_t      RESERVED2[3];    /**< Reserved for future use **/
+  __I uint32_t  APORTREQ;        /**< APORT Request Status Register  */
+  __I uint32_t  APORTCONFLICT;   /**< APORT BUS Request Status Register  */
+  __I uint32_t  SINGLEFIFOCOUNT; /**< Single FIFO Count Register  */
+  __I uint32_t  SCANFIFOCOUNT;   /**< Scan FIFO Count Register  */
+  __IO uint32_t SINGLEFIFOCLEAR; /**< Single FIFO Clear Register  */
+  __IO uint32_t SCANFIFOCLEAR;   /**< Scan FIFO Clear Register  */
+  __IO uint32_t APORTMASTERDIS;  /**< APORT Bus Master Disable Register  */
+} ADC_TypeDef;                   /** @} */
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B_ADC_BitFields
+ * @{
+ *****************************************************************************/
+
+/* Bit fields for ADC CTRL */
+#define _ADC_CTRL_RESETVALUE                               0x001F0000UL                              /**< Default value for ADC_CTRL */
+#define _ADC_CTRL_MASK                                     0x2F7F7FDFUL                              /**< Mask for ADC_CTRL */
+#define _ADC_CTRL_WARMUPMODE_SHIFT                         0                                         /**< Shift value for ADC_WARMUPMODE */
+#define _ADC_CTRL_WARMUPMODE_MASK                          0x3UL                                     /**< Bit mask for ADC_WARMUPMODE */
+#define _ADC_CTRL_WARMUPMODE_DEFAULT                       0x00000000UL                              /**< Mode DEFAULT for ADC_CTRL */
+#define _ADC_CTRL_WARMUPMODE_NORMAL                        0x00000000UL                              /**< Mode NORMAL for ADC_CTRL */
+#define _ADC_CTRL_WARMUPMODE_KEEPINSTANDBY                 0x00000001UL                              /**< Mode KEEPINSTANDBY for ADC_CTRL */
+#define _ADC_CTRL_WARMUPMODE_KEEPINSLOWACC                 0x00000002UL                              /**< Mode KEEPINSLOWACC for ADC_CTRL */
+#define _ADC_CTRL_WARMUPMODE_KEEPADCWARM                   0x00000003UL                              /**< Mode KEEPADCWARM for ADC_CTRL */
+#define ADC_CTRL_WARMUPMODE_DEFAULT                        (_ADC_CTRL_WARMUPMODE_DEFAULT << 0)       /**< Shifted mode DEFAULT for ADC_CTRL */
+#define ADC_CTRL_WARMUPMODE_NORMAL                         (_ADC_CTRL_WARMUPMODE_NORMAL << 0)        /**< Shifted mode NORMAL for ADC_CTRL */
+#define ADC_CTRL_WARMUPMODE_KEEPINSTANDBY                  (_ADC_CTRL_WARMUPMODE_KEEPINSTANDBY << 0) /**< Shifted mode KEEPINSTANDBY for ADC_CTRL */
+#define ADC_CTRL_WARMUPMODE_KEEPINSLOWACC                  (_ADC_CTRL_WARMUPMODE_KEEPINSLOWACC << 0) /**< Shifted mode KEEPINSLOWACC for ADC_CTRL */
+#define ADC_CTRL_WARMUPMODE_KEEPADCWARM                    (_ADC_CTRL_WARMUPMODE_KEEPADCWARM << 0)   /**< Shifted mode KEEPADCWARM for ADC_CTRL */
+#define ADC_CTRL_SINGLEDMAWU                               (0x1UL << 2)                              /**< SINGLEFIFO DMA Wakeup */
+#define _ADC_CTRL_SINGLEDMAWU_SHIFT                        2                                         /**< Shift value for ADC_SINGLEDMAWU */
+#define _ADC_CTRL_SINGLEDMAWU_MASK                         0x4UL                                     /**< Bit mask for ADC_SINGLEDMAWU */
+#define _ADC_CTRL_SINGLEDMAWU_DEFAULT                      0x00000000UL                              /**< Mode DEFAULT for ADC_CTRL */
+#define ADC_CTRL_SINGLEDMAWU_DEFAULT                       (_ADC_CTRL_SINGLEDMAWU_DEFAULT << 2)      /**< Shifted mode DEFAULT for ADC_CTRL */
+#define ADC_CTRL_SCANDMAWU                                 (0x1UL << 3)                              /**< SCANFIFO DMA Wakeup */
+#define _ADC_CTRL_SCANDMAWU_SHIFT                          3                                         /**< Shift value for ADC_SCANDMAWU */
+#define _ADC_CTRL_SCANDMAWU_MASK                           0x8UL                                     /**< Bit mask for ADC_SCANDMAWU */
+#define _ADC_CTRL_SCANDMAWU_DEFAULT                        0x00000000UL                              /**< Mode DEFAULT for ADC_CTRL */
+#define ADC_CTRL_SCANDMAWU_DEFAULT                         (_ADC_CTRL_SCANDMAWU_DEFAULT << 3)        /**< Shifted mode DEFAULT for ADC_CTRL */
+#define ADC_CTRL_TAILGATE                                  (0x1UL << 4)                              /**< Conversion Tailgating */
+#define _ADC_CTRL_TAILGATE_SHIFT                           4                                         /**< Shift value for ADC_TAILGATE */
+#define _ADC_CTRL_TAILGATE_MASK                            0x10UL                                    /**< Bit mask for ADC_TAILGATE */
+#define _ADC_CTRL_TAILGATE_DEFAULT                         0x00000000UL                              /**< Mode DEFAULT for ADC_CTRL */
+#define ADC_CTRL_TAILGATE_DEFAULT                          (_ADC_CTRL_TAILGATE_DEFAULT << 4)         /**< Shifted mode DEFAULT for ADC_CTRL */
+#define ADC_CTRL_ASYNCCLKEN                                (0x1UL << 6)                              /**< Selects ASYNC CLK enable mode when ADCCLKMODE=1 */
+#define _ADC_CTRL_ASYNCCLKEN_SHIFT                         6                                         /**< Shift value for ADC_ASYNCCLKEN */
+#define _ADC_CTRL_ASYNCCLKEN_MASK                          0x40UL                                    /**< Bit mask for ADC_ASYNCCLKEN */
+#define _ADC_CTRL_ASYNCCLKEN_DEFAULT                       0x00000000UL                              /**< Mode DEFAULT for ADC_CTRL */
+#define _ADC_CTRL_ASYNCCLKEN_ASNEEDED                      0x00000000UL                              /**< Mode ASNEEDED for ADC_CTRL */
+#define _ADC_CTRL_ASYNCCLKEN_ALWAYSON                      0x00000001UL                              /**< Mode ALWAYSON for ADC_CTRL */
+#define ADC_CTRL_ASYNCCLKEN_DEFAULT                        (_ADC_CTRL_ASYNCCLKEN_DEFAULT << 6)       /**< Shifted mode DEFAULT for ADC_CTRL */
+#define ADC_CTRL_ASYNCCLKEN_ASNEEDED                       (_ADC_CTRL_ASYNCCLKEN_ASNEEDED << 6)      /**< Shifted mode ASNEEDED for ADC_CTRL */
+#define ADC_CTRL_ASYNCCLKEN_ALWAYSON                       (_ADC_CTRL_ASYNCCLKEN_ALWAYSON << 6)      /**< Shifted mode ALWAYSON for ADC_CTRL */
+#define ADC_CTRL_ADCCLKMODE                                (0x1UL << 7)                              /**< ADC Clock Mode */
+#define _ADC_CTRL_ADCCLKMODE_SHIFT                         7                                         /**< Shift value for ADC_ADCCLKMODE */
+#define _ADC_CTRL_ADCCLKMODE_MASK                          0x80UL                                    /**< Bit mask for ADC_ADCCLKMODE */
+#define _ADC_CTRL_ADCCLKMODE_DEFAULT                       0x00000000UL                              /**< Mode DEFAULT for ADC_CTRL */
+#define _ADC_CTRL_ADCCLKMODE_SYNC                          0x00000000UL                              /**< Mode SYNC for ADC_CTRL */
+#define _ADC_CTRL_ADCCLKMODE_ASYNC                         0x00000001UL                              /**< Mode ASYNC for ADC_CTRL */
+#define ADC_CTRL_ADCCLKMODE_DEFAULT                        (_ADC_CTRL_ADCCLKMODE_DEFAULT << 7)       /**< Shifted mode DEFAULT for ADC_CTRL */
+#define ADC_CTRL_ADCCLKMODE_SYNC                           (_ADC_CTRL_ADCCLKMODE_SYNC << 7)          /**< Shifted mode SYNC for ADC_CTRL */
+#define ADC_CTRL_ADCCLKMODE_ASYNC                          (_ADC_CTRL_ADCCLKMODE_ASYNC << 7)         /**< Shifted mode ASYNC for ADC_CTRL */
+#define _ADC_CTRL_PRESC_SHIFT                              8                                         /**< Shift value for ADC_PRESC */
+#define _ADC_CTRL_PRESC_MASK                               0x7F00UL                                  /**< Bit mask for ADC_PRESC */
+#define _ADC_CTRL_PRESC_DEFAULT                            0x00000000UL                              /**< Mode DEFAULT for ADC_CTRL */
+#define _ADC_CTRL_PRESC_NODIVISION                         0x00000000UL                              /**< Mode NODIVISION for ADC_CTRL */
+#define ADC_CTRL_PRESC_DEFAULT                             (_ADC_CTRL_PRESC_DEFAULT << 8)            /**< Shifted mode DEFAULT for ADC_CTRL */
+#define ADC_CTRL_PRESC_NODIVISION                          (_ADC_CTRL_PRESC_NODIVISION << 8)         /**< Shifted mode NODIVISION for ADC_CTRL */
+#define _ADC_CTRL_TIMEBASE_SHIFT                           16                                        /**< Shift value for ADC_TIMEBASE */
+#define _ADC_CTRL_TIMEBASE_MASK                            0x7F0000UL                                /**< Bit mask for ADC_TIMEBASE */
+#define _ADC_CTRL_TIMEBASE_DEFAULT                         0x0000001FUL                              /**< Mode DEFAULT for ADC_CTRL */
+#define ADC_CTRL_TIMEBASE_DEFAULT                          (_ADC_CTRL_TIMEBASE_DEFAULT << 16)        /**< Shifted mode DEFAULT for ADC_CTRL */
+#define _ADC_CTRL_OVSRSEL_SHIFT                            24                                        /**< Shift value for ADC_OVSRSEL */
+#define _ADC_CTRL_OVSRSEL_MASK                             0xF000000UL                               /**< Bit mask for ADC_OVSRSEL */
+#define _ADC_CTRL_OVSRSEL_DEFAULT                          0x00000000UL                              /**< Mode DEFAULT for ADC_CTRL */
+#define _ADC_CTRL_OVSRSEL_X2                               0x00000000UL                              /**< Mode X2 for ADC_CTRL */
+#define _ADC_CTRL_OVSRSEL_X4                               0x00000001UL                              /**< Mode X4 for ADC_CTRL */
+#define _ADC_CTRL_OVSRSEL_X8                               0x00000002UL                              /**< Mode X8 for ADC_CTRL */
+#define _ADC_CTRL_OVSRSEL_X16                              0x00000003UL                              /**< Mode X16 for ADC_CTRL */
+#define _ADC_CTRL_OVSRSEL_X32                              0x00000004UL                              /**< Mode X32 for ADC_CTRL */
+#define _ADC_CTRL_OVSRSEL_X64                              0x00000005UL                              /**< Mode X64 for ADC_CTRL */
+#define _ADC_CTRL_OVSRSEL_X128                             0x00000006UL                              /**< Mode X128 for ADC_CTRL */
+#define _ADC_CTRL_OVSRSEL_X256                             0x00000007UL                              /**< Mode X256 for ADC_CTRL */
+#define _ADC_CTRL_OVSRSEL_X512                             0x00000008UL                              /**< Mode X512 for ADC_CTRL */
+#define _ADC_CTRL_OVSRSEL_X1024                            0x00000009UL                              /**< Mode X1024 for ADC_CTRL */
+#define _ADC_CTRL_OVSRSEL_X2048                            0x0000000AUL                              /**< Mode X2048 for ADC_CTRL */
+#define _ADC_CTRL_OVSRSEL_X4096                            0x0000000BUL                              /**< Mode X4096 for ADC_CTRL */
+#define ADC_CTRL_OVSRSEL_DEFAULT                           (_ADC_CTRL_OVSRSEL_DEFAULT << 24)         /**< Shifted mode DEFAULT for ADC_CTRL */
+#define ADC_CTRL_OVSRSEL_X2                                (_ADC_CTRL_OVSRSEL_X2 << 24)              /**< Shifted mode X2 for ADC_CTRL */
+#define ADC_CTRL_OVSRSEL_X4                                (_ADC_CTRL_OVSRSEL_X4 << 24)              /**< Shifted mode X4 for ADC_CTRL */
+#define ADC_CTRL_OVSRSEL_X8                                (_ADC_CTRL_OVSRSEL_X8 << 24)              /**< Shifted mode X8 for ADC_CTRL */
+#define ADC_CTRL_OVSRSEL_X16                               (_ADC_CTRL_OVSRSEL_X16 << 24)             /**< Shifted mode X16 for ADC_CTRL */
+#define ADC_CTRL_OVSRSEL_X32                               (_ADC_CTRL_OVSRSEL_X32 << 24)             /**< Shifted mode X32 for ADC_CTRL */
+#define ADC_CTRL_OVSRSEL_X64                               (_ADC_CTRL_OVSRSEL_X64 << 24)             /**< Shifted mode X64 for ADC_CTRL */
+#define ADC_CTRL_OVSRSEL_X128                              (_ADC_CTRL_OVSRSEL_X128 << 24)            /**< Shifted mode X128 for ADC_CTRL */
+#define ADC_CTRL_OVSRSEL_X256                              (_ADC_CTRL_OVSRSEL_X256 << 24)            /**< Shifted mode X256 for ADC_CTRL */
+#define ADC_CTRL_OVSRSEL_X512                              (_ADC_CTRL_OVSRSEL_X512 << 24)            /**< Shifted mode X512 for ADC_CTRL */
+#define ADC_CTRL_OVSRSEL_X1024                             (_ADC_CTRL_OVSRSEL_X1024 << 24)           /**< Shifted mode X1024 for ADC_CTRL */
+#define ADC_CTRL_OVSRSEL_X2048                             (_ADC_CTRL_OVSRSEL_X2048 << 24)           /**< Shifted mode X2048 for ADC_CTRL */
+#define ADC_CTRL_OVSRSEL_X4096                             (_ADC_CTRL_OVSRSEL_X4096 << 24)           /**< Shifted mode X4096 for ADC_CTRL */
+#define ADC_CTRL_CHCONMODE                                 (0x1UL << 29)                             /**< Channel Connect */
+#define _ADC_CTRL_CHCONMODE_SHIFT                          29                                        /**< Shift value for ADC_CHCONMODE */
+#define _ADC_CTRL_CHCONMODE_MASK                           0x20000000UL                              /**< Bit mask for ADC_CHCONMODE */
+#define _ADC_CTRL_CHCONMODE_DEFAULT                        0x00000000UL                              /**< Mode DEFAULT for ADC_CTRL */
+#define _ADC_CTRL_CHCONMODE_MAXSETTLE                      0x00000000UL                              /**< Mode MAXSETTLE for ADC_CTRL */
+#define _ADC_CTRL_CHCONMODE_MAXRESP                        0x00000001UL                              /**< Mode MAXRESP for ADC_CTRL */
+#define ADC_CTRL_CHCONMODE_DEFAULT                         (_ADC_CTRL_CHCONMODE_DEFAULT << 29)       /**< Shifted mode DEFAULT for ADC_CTRL */
+#define ADC_CTRL_CHCONMODE_MAXSETTLE                       (_ADC_CTRL_CHCONMODE_MAXSETTLE << 29)     /**< Shifted mode MAXSETTLE for ADC_CTRL */
+#define ADC_CTRL_CHCONMODE_MAXRESP                         (_ADC_CTRL_CHCONMODE_MAXRESP << 29)       /**< Shifted mode MAXRESP for ADC_CTRL */
+
+/* Bit fields for ADC CMD */
+#define _ADC_CMD_RESETVALUE                                0x00000000UL                        /**< Default value for ADC_CMD */
+#define _ADC_CMD_MASK                                      0x0000000FUL                        /**< Mask for ADC_CMD */
+#define ADC_CMD_SINGLESTART                                (0x1UL << 0)                        /**< Single Conversion Start */
+#define _ADC_CMD_SINGLESTART_SHIFT                         0                                   /**< Shift value for ADC_SINGLESTART */
+#define _ADC_CMD_SINGLESTART_MASK                          0x1UL                               /**< Bit mask for ADC_SINGLESTART */
+#define _ADC_CMD_SINGLESTART_DEFAULT                       0x00000000UL                        /**< Mode DEFAULT for ADC_CMD */
+#define ADC_CMD_SINGLESTART_DEFAULT                        (_ADC_CMD_SINGLESTART_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_CMD */
+#define ADC_CMD_SINGLESTOP                                 (0x1UL << 1)                        /**< Single Conversion Stop */
+#define _ADC_CMD_SINGLESTOP_SHIFT                          1                                   /**< Shift value for ADC_SINGLESTOP */
+#define _ADC_CMD_SINGLESTOP_MASK                           0x2UL                               /**< Bit mask for ADC_SINGLESTOP */
+#define _ADC_CMD_SINGLESTOP_DEFAULT                        0x00000000UL                        /**< Mode DEFAULT for ADC_CMD */
+#define ADC_CMD_SINGLESTOP_DEFAULT                         (_ADC_CMD_SINGLESTOP_DEFAULT << 1)  /**< Shifted mode DEFAULT for ADC_CMD */
+#define ADC_CMD_SCANSTART                                  (0x1UL << 2)                        /**< Scan Sequence Start */
+#define _ADC_CMD_SCANSTART_SHIFT                           2                                   /**< Shift value for ADC_SCANSTART */
+#define _ADC_CMD_SCANSTART_MASK                            0x4UL                               /**< Bit mask for ADC_SCANSTART */
+#define _ADC_CMD_SCANSTART_DEFAULT                         0x00000000UL                        /**< Mode DEFAULT for ADC_CMD */
+#define ADC_CMD_SCANSTART_DEFAULT                          (_ADC_CMD_SCANSTART_DEFAULT << 2)   /**< Shifted mode DEFAULT for ADC_CMD */
+#define ADC_CMD_SCANSTOP                                   (0x1UL << 3)                        /**< Scan Sequence Stop */
+#define _ADC_CMD_SCANSTOP_SHIFT                            3                                   /**< Shift value for ADC_SCANSTOP */
+#define _ADC_CMD_SCANSTOP_MASK                             0x8UL                               /**< Bit mask for ADC_SCANSTOP */
+#define _ADC_CMD_SCANSTOP_DEFAULT                          0x00000000UL                        /**< Mode DEFAULT for ADC_CMD */
+#define ADC_CMD_SCANSTOP_DEFAULT                           (_ADC_CMD_SCANSTOP_DEFAULT << 3)    /**< Shifted mode DEFAULT for ADC_CMD */
+
+/* Bit fields for ADC STATUS */
+#define _ADC_STATUS_RESETVALUE                             0x00000000UL                             /**< Default value for ADC_STATUS */
+#define _ADC_STATUS_MASK                                   0x00031F03UL                             /**< Mask for ADC_STATUS */
+#define ADC_STATUS_SINGLEACT                               (0x1UL << 0)                             /**< Single Conversion Active */
+#define _ADC_STATUS_SINGLEACT_SHIFT                        0                                        /**< Shift value for ADC_SINGLEACT */
+#define _ADC_STATUS_SINGLEACT_MASK                         0x1UL                                    /**< Bit mask for ADC_SINGLEACT */
+#define _ADC_STATUS_SINGLEACT_DEFAULT                      0x00000000UL                             /**< Mode DEFAULT for ADC_STATUS */
+#define ADC_STATUS_SINGLEACT_DEFAULT                       (_ADC_STATUS_SINGLEACT_DEFAULT << 0)     /**< Shifted mode DEFAULT for ADC_STATUS */
+#define ADC_STATUS_SCANACT                                 (0x1UL << 1)                             /**< Scan Conversion Active */
+#define _ADC_STATUS_SCANACT_SHIFT                          1                                        /**< Shift value for ADC_SCANACT */
+#define _ADC_STATUS_SCANACT_MASK                           0x2UL                                    /**< Bit mask for ADC_SCANACT */
+#define _ADC_STATUS_SCANACT_DEFAULT                        0x00000000UL                             /**< Mode DEFAULT for ADC_STATUS */
+#define ADC_STATUS_SCANACT_DEFAULT                         (_ADC_STATUS_SCANACT_DEFAULT << 1)       /**< Shifted mode DEFAULT for ADC_STATUS */
+#define ADC_STATUS_SINGLEREFWARM                           (0x1UL << 8)                             /**< Single Reference Warmed Up */
+#define _ADC_STATUS_SINGLEREFWARM_SHIFT                    8                                        /**< Shift value for ADC_SINGLEREFWARM */
+#define _ADC_STATUS_SINGLEREFWARM_MASK                     0x100UL                                  /**< Bit mask for ADC_SINGLEREFWARM */
+#define _ADC_STATUS_SINGLEREFWARM_DEFAULT                  0x00000000UL                             /**< Mode DEFAULT for ADC_STATUS */
+#define ADC_STATUS_SINGLEREFWARM_DEFAULT                   (_ADC_STATUS_SINGLEREFWARM_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_STATUS */
+#define ADC_STATUS_SCANREFWARM                             (0x1UL << 9)                             /**< Scan Reference Warmed Up */
+#define _ADC_STATUS_SCANREFWARM_SHIFT                      9                                        /**< Shift value for ADC_SCANREFWARM */
+#define _ADC_STATUS_SCANREFWARM_MASK                       0x200UL                                  /**< Bit mask for ADC_SCANREFWARM */
+#define _ADC_STATUS_SCANREFWARM_DEFAULT                    0x00000000UL                             /**< Mode DEFAULT for ADC_STATUS */
+#define ADC_STATUS_SCANREFWARM_DEFAULT                     (_ADC_STATUS_SCANREFWARM_DEFAULT << 9)   /**< Shifted mode DEFAULT for ADC_STATUS */
+#define _ADC_STATUS_PROGERR_SHIFT                          10                                       /**< Shift value for ADC_PROGERR */
+#define _ADC_STATUS_PROGERR_MASK                           0xC00UL                                  /**< Bit mask for ADC_PROGERR */
+#define _ADC_STATUS_PROGERR_DEFAULT                        0x00000000UL                             /**< Mode DEFAULT for ADC_STATUS */
+#define _ADC_STATUS_PROGERR_BUSCONF                        0x00000001UL                             /**< Mode BUSCONF for ADC_STATUS */
+#define _ADC_STATUS_PROGERR_NEGSELCONF                     0x00000002UL                             /**< Mode NEGSELCONF for ADC_STATUS */
+#define ADC_STATUS_PROGERR_DEFAULT                         (_ADC_STATUS_PROGERR_DEFAULT << 10)      /**< Shifted mode DEFAULT for ADC_STATUS */
+#define ADC_STATUS_PROGERR_BUSCONF                         (_ADC_STATUS_PROGERR_BUSCONF << 10)      /**< Shifted mode BUSCONF for ADC_STATUS */
+#define ADC_STATUS_PROGERR_NEGSELCONF                      (_ADC_STATUS_PROGERR_NEGSELCONF << 10)   /**< Shifted mode NEGSELCONF for ADC_STATUS */
+#define ADC_STATUS_WARM                                    (0x1UL << 12)                            /**< ADC Warmed Up */
+#define _ADC_STATUS_WARM_SHIFT                             12                                       /**< Shift value for ADC_WARM */
+#define _ADC_STATUS_WARM_MASK                              0x1000UL                                 /**< Bit mask for ADC_WARM */
+#define _ADC_STATUS_WARM_DEFAULT                           0x00000000UL                             /**< Mode DEFAULT for ADC_STATUS */
+#define ADC_STATUS_WARM_DEFAULT                            (_ADC_STATUS_WARM_DEFAULT << 12)         /**< Shifted mode DEFAULT for ADC_STATUS */
+#define ADC_STATUS_SINGLEDV                                (0x1UL << 16)                            /**< Single Channel Data Valid */
+#define _ADC_STATUS_SINGLEDV_SHIFT                         16                                       /**< Shift value for ADC_SINGLEDV */
+#define _ADC_STATUS_SINGLEDV_MASK                          0x10000UL                                /**< Bit mask for ADC_SINGLEDV */
+#define _ADC_STATUS_SINGLEDV_DEFAULT                       0x00000000UL                             /**< Mode DEFAULT for ADC_STATUS */
+#define ADC_STATUS_SINGLEDV_DEFAULT                        (_ADC_STATUS_SINGLEDV_DEFAULT << 16)     /**< Shifted mode DEFAULT for ADC_STATUS */
+#define ADC_STATUS_SCANDV                                  (0x1UL << 17)                            /**< Scan Data Valid */
+#define _ADC_STATUS_SCANDV_SHIFT                           17                                       /**< Shift value for ADC_SCANDV */
+#define _ADC_STATUS_SCANDV_MASK                            0x20000UL                                /**< Bit mask for ADC_SCANDV */
+#define _ADC_STATUS_SCANDV_DEFAULT                         0x00000000UL                             /**< Mode DEFAULT for ADC_STATUS */
+#define ADC_STATUS_SCANDV_DEFAULT                          (_ADC_STATUS_SCANDV_DEFAULT << 17)       /**< Shifted mode DEFAULT for ADC_STATUS */
+
+/* Bit fields for ADC SINGLECTRL */
+#define _ADC_SINGLECTRL_RESETVALUE                         0x00FFFF00UL                               /**< Default value for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_MASK                               0xAFFFFFFFUL                               /**< Mask for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_REP                                 (0x1UL << 0)                               /**< Single Channel Repetitive Mode */
+#define _ADC_SINGLECTRL_REP_SHIFT                          0                                          /**< Shift value for ADC_REP */
+#define _ADC_SINGLECTRL_REP_MASK                           0x1UL                                      /**< Bit mask for ADC_REP */
+#define _ADC_SINGLECTRL_REP_DEFAULT                        0x00000000UL                               /**< Mode DEFAULT for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_REP_DEFAULT                         (_ADC_SINGLECTRL_REP_DEFAULT << 0)         /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_DIFF                                (0x1UL << 1)                               /**< Single Channel Differential Mode */
+#define _ADC_SINGLECTRL_DIFF_SHIFT                         1                                          /**< Shift value for ADC_DIFF */
+#define _ADC_SINGLECTRL_DIFF_MASK                          0x2UL                                      /**< Bit mask for ADC_DIFF */
+#define _ADC_SINGLECTRL_DIFF_DEFAULT                       0x00000000UL                               /**< Mode DEFAULT for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_DIFF_DEFAULT                        (_ADC_SINGLECTRL_DIFF_DEFAULT << 1)        /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_ADJ                                 (0x1UL << 2)                               /**< Single Channel Result Adjustment */
+#define _ADC_SINGLECTRL_ADJ_SHIFT                          2                                          /**< Shift value for ADC_ADJ */
+#define _ADC_SINGLECTRL_ADJ_MASK                           0x4UL                                      /**< Bit mask for ADC_ADJ */
+#define _ADC_SINGLECTRL_ADJ_DEFAULT                        0x00000000UL                               /**< Mode DEFAULT for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_ADJ_RIGHT                          0x00000000UL                               /**< Mode RIGHT for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_ADJ_LEFT                           0x00000001UL                               /**< Mode LEFT for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_ADJ_DEFAULT                         (_ADC_SINGLECTRL_ADJ_DEFAULT << 2)         /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_ADJ_RIGHT                           (_ADC_SINGLECTRL_ADJ_RIGHT << 2)           /**< Shifted mode RIGHT for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_ADJ_LEFT                            (_ADC_SINGLECTRL_ADJ_LEFT << 2)            /**< Shifted mode LEFT for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_RES_SHIFT                          3                                          /**< Shift value for ADC_RES */
+#define _ADC_SINGLECTRL_RES_MASK                           0x18UL                                     /**< Bit mask for ADC_RES */
+#define _ADC_SINGLECTRL_RES_DEFAULT                        0x00000000UL                               /**< Mode DEFAULT for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_RES_12BIT                          0x00000000UL                               /**< Mode 12BIT for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_RES_8BIT                           0x00000001UL                               /**< Mode 8BIT for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_RES_6BIT                           0x00000002UL                               /**< Mode 6BIT for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_RES_OVS                            0x00000003UL                               /**< Mode OVS for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_RES_DEFAULT                         (_ADC_SINGLECTRL_RES_DEFAULT << 3)         /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_RES_12BIT                           (_ADC_SINGLECTRL_RES_12BIT << 3)           /**< Shifted mode 12BIT for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_RES_8BIT                            (_ADC_SINGLECTRL_RES_8BIT << 3)            /**< Shifted mode 8BIT for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_RES_6BIT                            (_ADC_SINGLECTRL_RES_6BIT << 3)            /**< Shifted mode 6BIT for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_RES_OVS                             (_ADC_SINGLECTRL_RES_OVS << 3)             /**< Shifted mode OVS for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_REF_SHIFT                          5                                          /**< Shift value for ADC_REF */
+#define _ADC_SINGLECTRL_REF_MASK                           0xE0UL                                     /**< Bit mask for ADC_REF */
+#define _ADC_SINGLECTRL_REF_DEFAULT                        0x00000000UL                               /**< Mode DEFAULT for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_REF_1V25                           0x00000000UL                               /**< Mode 1V25 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_REF_2V5                            0x00000001UL                               /**< Mode 2V5 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_REF_VDD                            0x00000002UL                               /**< Mode VDD for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_REF_5VDIFF                         0x00000003UL                               /**< Mode 5VDIFF for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_REF_EXTSINGLE                      0x00000004UL                               /**< Mode EXTSINGLE for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_REF_2XEXTDIFF                      0x00000005UL                               /**< Mode 2XEXTDIFF for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_REF_2XVDD                          0x00000006UL                               /**< Mode 2XVDD for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_REF_CONF                           0x00000007UL                               /**< Mode CONF for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_REF_DEFAULT                         (_ADC_SINGLECTRL_REF_DEFAULT << 5)         /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_REF_1V25                            (_ADC_SINGLECTRL_REF_1V25 << 5)            /**< Shifted mode 1V25 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_REF_2V5                             (_ADC_SINGLECTRL_REF_2V5 << 5)             /**< Shifted mode 2V5 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_REF_VDD                             (_ADC_SINGLECTRL_REF_VDD << 5)             /**< Shifted mode VDD for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_REF_5VDIFF                          (_ADC_SINGLECTRL_REF_5VDIFF << 5)          /**< Shifted mode 5VDIFF for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_REF_EXTSINGLE                       (_ADC_SINGLECTRL_REF_EXTSINGLE << 5)       /**< Shifted mode EXTSINGLE for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_REF_2XEXTDIFF                       (_ADC_SINGLECTRL_REF_2XEXTDIFF << 5)       /**< Shifted mode 2XEXTDIFF for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_REF_2XVDD                           (_ADC_SINGLECTRL_REF_2XVDD << 5)           /**< Shifted mode 2XVDD for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_REF_CONF                            (_ADC_SINGLECTRL_REF_CONF << 5)            /**< Shifted mode CONF for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_SHIFT                       8                                          /**< Shift value for ADC_POSSEL */
+#define _ADC_SINGLECTRL_POSSEL_MASK                        0xFF00UL                                   /**< Bit mask for ADC_POSSEL */
+#define _ADC_SINGLECTRL_POSSEL_APORT0XCH0                  0x00000000UL                               /**< Mode APORT0XCH0 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT0XCH1                  0x00000001UL                               /**< Mode APORT0XCH1 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT0XCH2                  0x00000002UL                               /**< Mode APORT0XCH2 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT0XCH3                  0x00000003UL                               /**< Mode APORT0XCH3 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT0XCH4                  0x00000004UL                               /**< Mode APORT0XCH4 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT0XCH5                  0x00000005UL                               /**< Mode APORT0XCH5 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT0XCH6                  0x00000006UL                               /**< Mode APORT0XCH6 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT0XCH7                  0x00000007UL                               /**< Mode APORT0XCH7 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT0XCH8                  0x00000008UL                               /**< Mode APORT0XCH8 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT0XCH9                  0x00000009UL                               /**< Mode APORT0XCH9 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT0XCH10                 0x0000000AUL                               /**< Mode APORT0XCH10 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT0XCH11                 0x0000000BUL                               /**< Mode APORT0XCH11 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT0XCH12                 0x0000000CUL                               /**< Mode APORT0XCH12 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT0XCH13                 0x0000000DUL                               /**< Mode APORT0XCH13 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT0XCH14                 0x0000000EUL                               /**< Mode APORT0XCH14 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT0XCH15                 0x0000000FUL                               /**< Mode APORT0XCH15 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT0YCH0                  0x00000010UL                               /**< Mode APORT0YCH0 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT0YCH1                  0x00000011UL                               /**< Mode APORT0YCH1 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT0YCH2                  0x00000012UL                               /**< Mode APORT0YCH2 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT0YCH3                  0x00000013UL                               /**< Mode APORT0YCH3 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT0YCH4                  0x00000014UL                               /**< Mode APORT0YCH4 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT0YCH5                  0x00000015UL                               /**< Mode APORT0YCH5 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT0YCH6                  0x00000016UL                               /**< Mode APORT0YCH6 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT0YCH7                  0x00000017UL                               /**< Mode APORT0YCH7 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT0YCH8                  0x00000018UL                               /**< Mode APORT0YCH8 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT0YCH9                  0x00000019UL                               /**< Mode APORT0YCH9 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT0YCH10                 0x0000001AUL                               /**< Mode APORT0YCH10 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT0YCH11                 0x0000001BUL                               /**< Mode APORT0YCH11 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT0YCH12                 0x0000001CUL                               /**< Mode APORT0YCH12 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT0YCH13                 0x0000001DUL                               /**< Mode APORT0YCH13 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT0YCH14                 0x0000001EUL                               /**< Mode APORT0YCH14 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT0YCH15                 0x0000001FUL                               /**< Mode APORT0YCH15 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT1XCH0                  0x00000020UL                               /**< Mode APORT1XCH0 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT1YCH1                  0x00000021UL                               /**< Mode APORT1YCH1 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT1XCH2                  0x00000022UL                               /**< Mode APORT1XCH2 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT1YCH3                  0x00000023UL                               /**< Mode APORT1YCH3 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT1XCH4                  0x00000024UL                               /**< Mode APORT1XCH4 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT1YCH5                  0x00000025UL                               /**< Mode APORT1YCH5 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT1XCH6                  0x00000026UL                               /**< Mode APORT1XCH6 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT1YCH7                  0x00000027UL                               /**< Mode APORT1YCH7 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT1XCH8                  0x00000028UL                               /**< Mode APORT1XCH8 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT1YCH9                  0x00000029UL                               /**< Mode APORT1YCH9 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT1XCH10                 0x0000002AUL                               /**< Mode APORT1XCH10 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT1YCH11                 0x0000002BUL                               /**< Mode APORT1YCH11 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT1XCH12                 0x0000002CUL                               /**< Mode APORT1XCH12 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT1YCH13                 0x0000002DUL                               /**< Mode APORT1YCH13 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT1XCH14                 0x0000002EUL                               /**< Mode APORT1XCH14 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT1YCH15                 0x0000002FUL                               /**< Mode APORT1YCH15 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT1XCH16                 0x00000030UL                               /**< Mode APORT1XCH16 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT1YCH17                 0x00000031UL                               /**< Mode APORT1YCH17 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT1XCH18                 0x00000032UL                               /**< Mode APORT1XCH18 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT1YCH19                 0x00000033UL                               /**< Mode APORT1YCH19 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT1XCH20                 0x00000034UL                               /**< Mode APORT1XCH20 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT1YCH21                 0x00000035UL                               /**< Mode APORT1YCH21 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT1XCH22                 0x00000036UL                               /**< Mode APORT1XCH22 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT1YCH23                 0x00000037UL                               /**< Mode APORT1YCH23 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT1XCH24                 0x00000038UL                               /**< Mode APORT1XCH24 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT1YCH25                 0x00000039UL                               /**< Mode APORT1YCH25 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT1XCH26                 0x0000003AUL                               /**< Mode APORT1XCH26 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT1YCH27                 0x0000003BUL                               /**< Mode APORT1YCH27 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT1XCH28                 0x0000003CUL                               /**< Mode APORT1XCH28 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT1YCH29                 0x0000003DUL                               /**< Mode APORT1YCH29 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT1XCH30                 0x0000003EUL                               /**< Mode APORT1XCH30 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT1YCH31                 0x0000003FUL                               /**< Mode APORT1YCH31 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT2YCH0                  0x00000040UL                               /**< Mode APORT2YCH0 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT2XCH1                  0x00000041UL                               /**< Mode APORT2XCH1 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT2YCH2                  0x00000042UL                               /**< Mode APORT2YCH2 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT2XCH3                  0x00000043UL                               /**< Mode APORT2XCH3 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT2YCH4                  0x00000044UL                               /**< Mode APORT2YCH4 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT2XCH5                  0x00000045UL                               /**< Mode APORT2XCH5 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT2YCH6                  0x00000046UL                               /**< Mode APORT2YCH6 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT2XCH7                  0x00000047UL                               /**< Mode APORT2XCH7 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT2YCH8                  0x00000048UL                               /**< Mode APORT2YCH8 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT2XCH9                  0x00000049UL                               /**< Mode APORT2XCH9 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT2YCH10                 0x0000004AUL                               /**< Mode APORT2YCH10 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT2XCH11                 0x0000004BUL                               /**< Mode APORT2XCH11 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT2YCH12                 0x0000004CUL                               /**< Mode APORT2YCH12 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT2XCH13                 0x0000004DUL                               /**< Mode APORT2XCH13 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT2YCH14                 0x0000004EUL                               /**< Mode APORT2YCH14 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT2XCH15                 0x0000004FUL                               /**< Mode APORT2XCH15 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT2YCH16                 0x00000050UL                               /**< Mode APORT2YCH16 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT2XCH17                 0x00000051UL                               /**< Mode APORT2XCH17 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT2YCH18                 0x00000052UL                               /**< Mode APORT2YCH18 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT2XCH19                 0x00000053UL                               /**< Mode APORT2XCH19 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT2YCH20                 0x00000054UL                               /**< Mode APORT2YCH20 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT2XCH21                 0x00000055UL                               /**< Mode APORT2XCH21 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT2YCH22                 0x00000056UL                               /**< Mode APORT2YCH22 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT2XCH23                 0x00000057UL                               /**< Mode APORT2XCH23 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT2YCH24                 0x00000058UL                               /**< Mode APORT2YCH24 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT2XCH25                 0x00000059UL                               /**< Mode APORT2XCH25 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT2YCH26                 0x0000005AUL                               /**< Mode APORT2YCH26 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT2XCH27                 0x0000005BUL                               /**< Mode APORT2XCH27 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT2YCH28                 0x0000005CUL                               /**< Mode APORT2YCH28 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT2XCH29                 0x0000005DUL                               /**< Mode APORT2XCH29 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT2YCH30                 0x0000005EUL                               /**< Mode APORT2YCH30 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT2XCH31                 0x0000005FUL                               /**< Mode APORT2XCH31 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT3XCH0                  0x00000060UL                               /**< Mode APORT3XCH0 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT3YCH1                  0x00000061UL                               /**< Mode APORT3YCH1 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT3XCH2                  0x00000062UL                               /**< Mode APORT3XCH2 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT3YCH3                  0x00000063UL                               /**< Mode APORT3YCH3 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT3XCH4                  0x00000064UL                               /**< Mode APORT3XCH4 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT3YCH5                  0x00000065UL                               /**< Mode APORT3YCH5 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT3XCH6                  0x00000066UL                               /**< Mode APORT3XCH6 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT3YCH7                  0x00000067UL                               /**< Mode APORT3YCH7 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT3XCH8                  0x00000068UL                               /**< Mode APORT3XCH8 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT3YCH9                  0x00000069UL                               /**< Mode APORT3YCH9 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT3XCH10                 0x0000006AUL                               /**< Mode APORT3XCH10 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT3YCH11                 0x0000006BUL                               /**< Mode APORT3YCH11 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT3XCH12                 0x0000006CUL                               /**< Mode APORT3XCH12 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT3YCH13                 0x0000006DUL                               /**< Mode APORT3YCH13 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT3XCH14                 0x0000006EUL                               /**< Mode APORT3XCH14 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT3YCH15                 0x0000006FUL                               /**< Mode APORT3YCH15 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT3XCH16                 0x00000070UL                               /**< Mode APORT3XCH16 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT3YCH17                 0x00000071UL                               /**< Mode APORT3YCH17 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT3XCH18                 0x00000072UL                               /**< Mode APORT3XCH18 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT3YCH19                 0x00000073UL                               /**< Mode APORT3YCH19 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT3XCH20                 0x00000074UL                               /**< Mode APORT3XCH20 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT3YCH21                 0x00000075UL                               /**< Mode APORT3YCH21 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT3XCH22                 0x00000076UL                               /**< Mode APORT3XCH22 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT3YCH23                 0x00000077UL                               /**< Mode APORT3YCH23 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT3XCH24                 0x00000078UL                               /**< Mode APORT3XCH24 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT3YCH25                 0x00000079UL                               /**< Mode APORT3YCH25 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT3XCH26                 0x0000007AUL                               /**< Mode APORT3XCH26 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT3YCH27                 0x0000007BUL                               /**< Mode APORT3YCH27 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT3XCH28                 0x0000007CUL                               /**< Mode APORT3XCH28 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT3YCH29                 0x0000007DUL                               /**< Mode APORT3YCH29 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT3XCH30                 0x0000007EUL                               /**< Mode APORT3XCH30 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT3YCH31                 0x0000007FUL                               /**< Mode APORT3YCH31 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT4YCH0                  0x00000080UL                               /**< Mode APORT4YCH0 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT4XCH1                  0x00000081UL                               /**< Mode APORT4XCH1 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT4YCH2                  0x00000082UL                               /**< Mode APORT4YCH2 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT4XCH3                  0x00000083UL                               /**< Mode APORT4XCH3 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT4YCH4                  0x00000084UL                               /**< Mode APORT4YCH4 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT4XCH5                  0x00000085UL                               /**< Mode APORT4XCH5 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT4YCH6                  0x00000086UL                               /**< Mode APORT4YCH6 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT4XCH7                  0x00000087UL                               /**< Mode APORT4XCH7 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT4YCH8                  0x00000088UL                               /**< Mode APORT4YCH8 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT4XCH9                  0x00000089UL                               /**< Mode APORT4XCH9 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT4YCH10                 0x0000008AUL                               /**< Mode APORT4YCH10 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT4XCH11                 0x0000008BUL                               /**< Mode APORT4XCH11 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT4YCH12                 0x0000008CUL                               /**< Mode APORT4YCH12 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT4XCH13                 0x0000008DUL                               /**< Mode APORT4XCH13 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT4YCH14                 0x0000008EUL                               /**< Mode APORT4YCH14 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT4XCH15                 0x0000008FUL                               /**< Mode APORT4XCH15 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT4YCH16                 0x00000090UL                               /**< Mode APORT4YCH16 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT4XCH17                 0x00000091UL                               /**< Mode APORT4XCH17 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT4YCH18                 0x00000092UL                               /**< Mode APORT4YCH18 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT4XCH19                 0x00000093UL                               /**< Mode APORT4XCH19 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT4YCH20                 0x00000094UL                               /**< Mode APORT4YCH20 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT4XCH21                 0x00000095UL                               /**< Mode APORT4XCH21 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT4YCH22                 0x00000096UL                               /**< Mode APORT4YCH22 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT4XCH23                 0x00000097UL                               /**< Mode APORT4XCH23 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT4YCH24                 0x00000098UL                               /**< Mode APORT4YCH24 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT4XCH25                 0x00000099UL                               /**< Mode APORT4XCH25 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT4YCH26                 0x0000009AUL                               /**< Mode APORT4YCH26 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT4XCH27                 0x0000009BUL                               /**< Mode APORT4XCH27 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT4YCH28                 0x0000009CUL                               /**< Mode APORT4YCH28 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT4XCH29                 0x0000009DUL                               /**< Mode APORT4XCH29 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT4YCH30                 0x0000009EUL                               /**< Mode APORT4YCH30 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT4XCH31                 0x0000009FUL                               /**< Mode APORT4XCH31 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_AVDD                        0x000000E0UL                               /**< Mode AVDD for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_BU                          0x000000E1UL                               /**< Mode BU for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_AREG                        0x000000E2UL                               /**< Mode AREG for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_VREGOUTPA                   0x000000E3UL                               /**< Mode VREGOUTPA for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_PDBU                        0x000000E4UL                               /**< Mode PDBU for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_IO0                         0x000000E5UL                               /**< Mode IO0 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_IO1                         0x000000E6UL                               /**< Mode IO1 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_VSP                         0x000000E7UL                               /**< Mode VSP for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_SP0                         0x000000F2UL                               /**< Mode SP0 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_TEMP                        0x000000F3UL                               /**< Mode TEMP for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_DAC0OUT0                    0x000000F4UL                               /**< Mode DAC0OUT0 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_TESTP                       0x000000F5UL                               /**< Mode TESTP for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_SP1                         0x000000F6UL                               /**< Mode SP1 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_SP2                         0x000000F7UL                               /**< Mode SP2 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_DAC0OUT1                    0x000000F8UL                               /**< Mode DAC0OUT1 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_SUBLSB                      0x000000F9UL                               /**< Mode SUBLSB for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_DEFAULT                     0x000000FFUL                               /**< Mode DEFAULT for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_VSS                         0x000000FFUL                               /**< Mode VSS for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT0XCH0                   (_ADC_SINGLECTRL_POSSEL_APORT0XCH0 << 8)   /**< Shifted mode APORT0XCH0 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT0XCH1                   (_ADC_SINGLECTRL_POSSEL_APORT0XCH1 << 8)   /**< Shifted mode APORT0XCH1 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT0XCH2                   (_ADC_SINGLECTRL_POSSEL_APORT0XCH2 << 8)   /**< Shifted mode APORT0XCH2 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT0XCH3                   (_ADC_SINGLECTRL_POSSEL_APORT0XCH3 << 8)   /**< Shifted mode APORT0XCH3 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT0XCH4                   (_ADC_SINGLECTRL_POSSEL_APORT0XCH4 << 8)   /**< Shifted mode APORT0XCH4 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT0XCH5                   (_ADC_SINGLECTRL_POSSEL_APORT0XCH5 << 8)   /**< Shifted mode APORT0XCH5 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT0XCH6                   (_ADC_SINGLECTRL_POSSEL_APORT0XCH6 << 8)   /**< Shifted mode APORT0XCH6 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT0XCH7                   (_ADC_SINGLECTRL_POSSEL_APORT0XCH7 << 8)   /**< Shifted mode APORT0XCH7 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT0XCH8                   (_ADC_SINGLECTRL_POSSEL_APORT0XCH8 << 8)   /**< Shifted mode APORT0XCH8 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT0XCH9                   (_ADC_SINGLECTRL_POSSEL_APORT0XCH9 << 8)   /**< Shifted mode APORT0XCH9 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT0XCH10                  (_ADC_SINGLECTRL_POSSEL_APORT0XCH10 << 8)  /**< Shifted mode APORT0XCH10 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT0XCH11                  (_ADC_SINGLECTRL_POSSEL_APORT0XCH11 << 8)  /**< Shifted mode APORT0XCH11 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT0XCH12                  (_ADC_SINGLECTRL_POSSEL_APORT0XCH12 << 8)  /**< Shifted mode APORT0XCH12 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT0XCH13                  (_ADC_SINGLECTRL_POSSEL_APORT0XCH13 << 8)  /**< Shifted mode APORT0XCH13 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT0XCH14                  (_ADC_SINGLECTRL_POSSEL_APORT0XCH14 << 8)  /**< Shifted mode APORT0XCH14 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT0XCH15                  (_ADC_SINGLECTRL_POSSEL_APORT0XCH15 << 8)  /**< Shifted mode APORT0XCH15 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT0YCH0                   (_ADC_SINGLECTRL_POSSEL_APORT0YCH0 << 8)   /**< Shifted mode APORT0YCH0 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT0YCH1                   (_ADC_SINGLECTRL_POSSEL_APORT0YCH1 << 8)   /**< Shifted mode APORT0YCH1 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT0YCH2                   (_ADC_SINGLECTRL_POSSEL_APORT0YCH2 << 8)   /**< Shifted mode APORT0YCH2 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT0YCH3                   (_ADC_SINGLECTRL_POSSEL_APORT0YCH3 << 8)   /**< Shifted mode APORT0YCH3 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT0YCH4                   (_ADC_SINGLECTRL_POSSEL_APORT0YCH4 << 8)   /**< Shifted mode APORT0YCH4 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT0YCH5                   (_ADC_SINGLECTRL_POSSEL_APORT0YCH5 << 8)   /**< Shifted mode APORT0YCH5 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT0YCH6                   (_ADC_SINGLECTRL_POSSEL_APORT0YCH6 << 8)   /**< Shifted mode APORT0YCH6 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT0YCH7                   (_ADC_SINGLECTRL_POSSEL_APORT0YCH7 << 8)   /**< Shifted mode APORT0YCH7 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT0YCH8                   (_ADC_SINGLECTRL_POSSEL_APORT0YCH8 << 8)   /**< Shifted mode APORT0YCH8 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT0YCH9                   (_ADC_SINGLECTRL_POSSEL_APORT0YCH9 << 8)   /**< Shifted mode APORT0YCH9 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT0YCH10                  (_ADC_SINGLECTRL_POSSEL_APORT0YCH10 << 8)  /**< Shifted mode APORT0YCH10 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT0YCH11                  (_ADC_SINGLECTRL_POSSEL_APORT0YCH11 << 8)  /**< Shifted mode APORT0YCH11 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT0YCH12                  (_ADC_SINGLECTRL_POSSEL_APORT0YCH12 << 8)  /**< Shifted mode APORT0YCH12 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT0YCH13                  (_ADC_SINGLECTRL_POSSEL_APORT0YCH13 << 8)  /**< Shifted mode APORT0YCH13 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT0YCH14                  (_ADC_SINGLECTRL_POSSEL_APORT0YCH14 << 8)  /**< Shifted mode APORT0YCH14 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT0YCH15                  (_ADC_SINGLECTRL_POSSEL_APORT0YCH15 << 8)  /**< Shifted mode APORT0YCH15 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT1XCH0                   (_ADC_SINGLECTRL_POSSEL_APORT1XCH0 << 8)   /**< Shifted mode APORT1XCH0 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT1YCH1                   (_ADC_SINGLECTRL_POSSEL_APORT1YCH1 << 8)   /**< Shifted mode APORT1YCH1 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT1XCH2                   (_ADC_SINGLECTRL_POSSEL_APORT1XCH2 << 8)   /**< Shifted mode APORT1XCH2 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT1YCH3                   (_ADC_SINGLECTRL_POSSEL_APORT1YCH3 << 8)   /**< Shifted mode APORT1YCH3 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT1XCH4                   (_ADC_SINGLECTRL_POSSEL_APORT1XCH4 << 8)   /**< Shifted mode APORT1XCH4 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT1YCH5                   (_ADC_SINGLECTRL_POSSEL_APORT1YCH5 << 8)   /**< Shifted mode APORT1YCH5 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT1XCH6                   (_ADC_SINGLECTRL_POSSEL_APORT1XCH6 << 8)   /**< Shifted mode APORT1XCH6 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT1YCH7                   (_ADC_SINGLECTRL_POSSEL_APORT1YCH7 << 8)   /**< Shifted mode APORT1YCH7 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT1XCH8                   (_ADC_SINGLECTRL_POSSEL_APORT1XCH8 << 8)   /**< Shifted mode APORT1XCH8 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT1YCH9                   (_ADC_SINGLECTRL_POSSEL_APORT1YCH9 << 8)   /**< Shifted mode APORT1YCH9 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT1XCH10                  (_ADC_SINGLECTRL_POSSEL_APORT1XCH10 << 8)  /**< Shifted mode APORT1XCH10 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT1YCH11                  (_ADC_SINGLECTRL_POSSEL_APORT1YCH11 << 8)  /**< Shifted mode APORT1YCH11 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT1XCH12                  (_ADC_SINGLECTRL_POSSEL_APORT1XCH12 << 8)  /**< Shifted mode APORT1XCH12 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT1YCH13                  (_ADC_SINGLECTRL_POSSEL_APORT1YCH13 << 8)  /**< Shifted mode APORT1YCH13 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT1XCH14                  (_ADC_SINGLECTRL_POSSEL_APORT1XCH14 << 8)  /**< Shifted mode APORT1XCH14 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT1YCH15                  (_ADC_SINGLECTRL_POSSEL_APORT1YCH15 << 8)  /**< Shifted mode APORT1YCH15 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT1XCH16                  (_ADC_SINGLECTRL_POSSEL_APORT1XCH16 << 8)  /**< Shifted mode APORT1XCH16 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT1YCH17                  (_ADC_SINGLECTRL_POSSEL_APORT1YCH17 << 8)  /**< Shifted mode APORT1YCH17 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT1XCH18                  (_ADC_SINGLECTRL_POSSEL_APORT1XCH18 << 8)  /**< Shifted mode APORT1XCH18 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT1YCH19                  (_ADC_SINGLECTRL_POSSEL_APORT1YCH19 << 8)  /**< Shifted mode APORT1YCH19 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT1XCH20                  (_ADC_SINGLECTRL_POSSEL_APORT1XCH20 << 8)  /**< Shifted mode APORT1XCH20 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT1YCH21                  (_ADC_SINGLECTRL_POSSEL_APORT1YCH21 << 8)  /**< Shifted mode APORT1YCH21 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT1XCH22                  (_ADC_SINGLECTRL_POSSEL_APORT1XCH22 << 8)  /**< Shifted mode APORT1XCH22 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT1YCH23                  (_ADC_SINGLECTRL_POSSEL_APORT1YCH23 << 8)  /**< Shifted mode APORT1YCH23 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT1XCH24                  (_ADC_SINGLECTRL_POSSEL_APORT1XCH24 << 8)  /**< Shifted mode APORT1XCH24 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT1YCH25                  (_ADC_SINGLECTRL_POSSEL_APORT1YCH25 << 8)  /**< Shifted mode APORT1YCH25 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT1XCH26                  (_ADC_SINGLECTRL_POSSEL_APORT1XCH26 << 8)  /**< Shifted mode APORT1XCH26 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT1YCH27                  (_ADC_SINGLECTRL_POSSEL_APORT1YCH27 << 8)  /**< Shifted mode APORT1YCH27 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT1XCH28                  (_ADC_SINGLECTRL_POSSEL_APORT1XCH28 << 8)  /**< Shifted mode APORT1XCH28 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT1YCH29                  (_ADC_SINGLECTRL_POSSEL_APORT1YCH29 << 8)  /**< Shifted mode APORT1YCH29 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT1XCH30                  (_ADC_SINGLECTRL_POSSEL_APORT1XCH30 << 8)  /**< Shifted mode APORT1XCH30 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT1YCH31                  (_ADC_SINGLECTRL_POSSEL_APORT1YCH31 << 8)  /**< Shifted mode APORT1YCH31 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT2YCH0                   (_ADC_SINGLECTRL_POSSEL_APORT2YCH0 << 8)   /**< Shifted mode APORT2YCH0 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT2XCH1                   (_ADC_SINGLECTRL_POSSEL_APORT2XCH1 << 8)   /**< Shifted mode APORT2XCH1 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT2YCH2                   (_ADC_SINGLECTRL_POSSEL_APORT2YCH2 << 8)   /**< Shifted mode APORT2YCH2 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT2XCH3                   (_ADC_SINGLECTRL_POSSEL_APORT2XCH3 << 8)   /**< Shifted mode APORT2XCH3 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT2YCH4                   (_ADC_SINGLECTRL_POSSEL_APORT2YCH4 << 8)   /**< Shifted mode APORT2YCH4 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT2XCH5                   (_ADC_SINGLECTRL_POSSEL_APORT2XCH5 << 8)   /**< Shifted mode APORT2XCH5 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT2YCH6                   (_ADC_SINGLECTRL_POSSEL_APORT2YCH6 << 8)   /**< Shifted mode APORT2YCH6 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT2XCH7                   (_ADC_SINGLECTRL_POSSEL_APORT2XCH7 << 8)   /**< Shifted mode APORT2XCH7 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT2YCH8                   (_ADC_SINGLECTRL_POSSEL_APORT2YCH8 << 8)   /**< Shifted mode APORT2YCH8 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT2XCH9                   (_ADC_SINGLECTRL_POSSEL_APORT2XCH9 << 8)   /**< Shifted mode APORT2XCH9 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT2YCH10                  (_ADC_SINGLECTRL_POSSEL_APORT2YCH10 << 8)  /**< Shifted mode APORT2YCH10 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT2XCH11                  (_ADC_SINGLECTRL_POSSEL_APORT2XCH11 << 8)  /**< Shifted mode APORT2XCH11 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT2YCH12                  (_ADC_SINGLECTRL_POSSEL_APORT2YCH12 << 8)  /**< Shifted mode APORT2YCH12 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT2XCH13                  (_ADC_SINGLECTRL_POSSEL_APORT2XCH13 << 8)  /**< Shifted mode APORT2XCH13 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT2YCH14                  (_ADC_SINGLECTRL_POSSEL_APORT2YCH14 << 8)  /**< Shifted mode APORT2YCH14 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT2XCH15                  (_ADC_SINGLECTRL_POSSEL_APORT2XCH15 << 8)  /**< Shifted mode APORT2XCH15 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT2YCH16                  (_ADC_SINGLECTRL_POSSEL_APORT2YCH16 << 8)  /**< Shifted mode APORT2YCH16 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT2XCH17                  (_ADC_SINGLECTRL_POSSEL_APORT2XCH17 << 8)  /**< Shifted mode APORT2XCH17 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT2YCH18                  (_ADC_SINGLECTRL_POSSEL_APORT2YCH18 << 8)  /**< Shifted mode APORT2YCH18 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT2XCH19                  (_ADC_SINGLECTRL_POSSEL_APORT2XCH19 << 8)  /**< Shifted mode APORT2XCH19 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT2YCH20                  (_ADC_SINGLECTRL_POSSEL_APORT2YCH20 << 8)  /**< Shifted mode APORT2YCH20 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT2XCH21                  (_ADC_SINGLECTRL_POSSEL_APORT2XCH21 << 8)  /**< Shifted mode APORT2XCH21 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT2YCH22                  (_ADC_SINGLECTRL_POSSEL_APORT2YCH22 << 8)  /**< Shifted mode APORT2YCH22 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT2XCH23                  (_ADC_SINGLECTRL_POSSEL_APORT2XCH23 << 8)  /**< Shifted mode APORT2XCH23 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT2YCH24                  (_ADC_SINGLECTRL_POSSEL_APORT2YCH24 << 8)  /**< Shifted mode APORT2YCH24 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT2XCH25                  (_ADC_SINGLECTRL_POSSEL_APORT2XCH25 << 8)  /**< Shifted mode APORT2XCH25 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT2YCH26                  (_ADC_SINGLECTRL_POSSEL_APORT2YCH26 << 8)  /**< Shifted mode APORT2YCH26 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT2XCH27                  (_ADC_SINGLECTRL_POSSEL_APORT2XCH27 << 8)  /**< Shifted mode APORT2XCH27 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT2YCH28                  (_ADC_SINGLECTRL_POSSEL_APORT2YCH28 << 8)  /**< Shifted mode APORT2YCH28 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT2XCH29                  (_ADC_SINGLECTRL_POSSEL_APORT2XCH29 << 8)  /**< Shifted mode APORT2XCH29 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT2YCH30                  (_ADC_SINGLECTRL_POSSEL_APORT2YCH30 << 8)  /**< Shifted mode APORT2YCH30 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT2XCH31                  (_ADC_SINGLECTRL_POSSEL_APORT2XCH31 << 8)  /**< Shifted mode APORT2XCH31 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT3XCH0                   (_ADC_SINGLECTRL_POSSEL_APORT3XCH0 << 8)   /**< Shifted mode APORT3XCH0 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT3YCH1                   (_ADC_SINGLECTRL_POSSEL_APORT3YCH1 << 8)   /**< Shifted mode APORT3YCH1 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT3XCH2                   (_ADC_SINGLECTRL_POSSEL_APORT3XCH2 << 8)   /**< Shifted mode APORT3XCH2 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT3YCH3                   (_ADC_SINGLECTRL_POSSEL_APORT3YCH3 << 8)   /**< Shifted mode APORT3YCH3 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT3XCH4                   (_ADC_SINGLECTRL_POSSEL_APORT3XCH4 << 8)   /**< Shifted mode APORT3XCH4 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT3YCH5                   (_ADC_SINGLECTRL_POSSEL_APORT3YCH5 << 8)   /**< Shifted mode APORT3YCH5 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT3XCH6                   (_ADC_SINGLECTRL_POSSEL_APORT3XCH6 << 8)   /**< Shifted mode APORT3XCH6 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT3YCH7                   (_ADC_SINGLECTRL_POSSEL_APORT3YCH7 << 8)   /**< Shifted mode APORT3YCH7 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT3XCH8                   (_ADC_SINGLECTRL_POSSEL_APORT3XCH8 << 8)   /**< Shifted mode APORT3XCH8 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT3YCH9                   (_ADC_SINGLECTRL_POSSEL_APORT3YCH9 << 8)   /**< Shifted mode APORT3YCH9 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT3XCH10                  (_ADC_SINGLECTRL_POSSEL_APORT3XCH10 << 8)  /**< Shifted mode APORT3XCH10 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT3YCH11                  (_ADC_SINGLECTRL_POSSEL_APORT3YCH11 << 8)  /**< Shifted mode APORT3YCH11 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT3XCH12                  (_ADC_SINGLECTRL_POSSEL_APORT3XCH12 << 8)  /**< Shifted mode APORT3XCH12 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT3YCH13                  (_ADC_SINGLECTRL_POSSEL_APORT3YCH13 << 8)  /**< Shifted mode APORT3YCH13 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT3XCH14                  (_ADC_SINGLECTRL_POSSEL_APORT3XCH14 << 8)  /**< Shifted mode APORT3XCH14 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT3YCH15                  (_ADC_SINGLECTRL_POSSEL_APORT3YCH15 << 8)  /**< Shifted mode APORT3YCH15 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT3XCH16                  (_ADC_SINGLECTRL_POSSEL_APORT3XCH16 << 8)  /**< Shifted mode APORT3XCH16 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT3YCH17                  (_ADC_SINGLECTRL_POSSEL_APORT3YCH17 << 8)  /**< Shifted mode APORT3YCH17 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT3XCH18                  (_ADC_SINGLECTRL_POSSEL_APORT3XCH18 << 8)  /**< Shifted mode APORT3XCH18 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT3YCH19                  (_ADC_SINGLECTRL_POSSEL_APORT3YCH19 << 8)  /**< Shifted mode APORT3YCH19 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT3XCH20                  (_ADC_SINGLECTRL_POSSEL_APORT3XCH20 << 8)  /**< Shifted mode APORT3XCH20 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT3YCH21                  (_ADC_SINGLECTRL_POSSEL_APORT3YCH21 << 8)  /**< Shifted mode APORT3YCH21 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT3XCH22                  (_ADC_SINGLECTRL_POSSEL_APORT3XCH22 << 8)  /**< Shifted mode APORT3XCH22 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT3YCH23                  (_ADC_SINGLECTRL_POSSEL_APORT3YCH23 << 8)  /**< Shifted mode APORT3YCH23 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT3XCH24                  (_ADC_SINGLECTRL_POSSEL_APORT3XCH24 << 8)  /**< Shifted mode APORT3XCH24 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT3YCH25                  (_ADC_SINGLECTRL_POSSEL_APORT3YCH25 << 8)  /**< Shifted mode APORT3YCH25 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT3XCH26                  (_ADC_SINGLECTRL_POSSEL_APORT3XCH26 << 8)  /**< Shifted mode APORT3XCH26 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT3YCH27                  (_ADC_SINGLECTRL_POSSEL_APORT3YCH27 << 8)  /**< Shifted mode APORT3YCH27 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT3XCH28                  (_ADC_SINGLECTRL_POSSEL_APORT3XCH28 << 8)  /**< Shifted mode APORT3XCH28 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT3YCH29                  (_ADC_SINGLECTRL_POSSEL_APORT3YCH29 << 8)  /**< Shifted mode APORT3YCH29 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT3XCH30                  (_ADC_SINGLECTRL_POSSEL_APORT3XCH30 << 8)  /**< Shifted mode APORT3XCH30 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT3YCH31                  (_ADC_SINGLECTRL_POSSEL_APORT3YCH31 << 8)  /**< Shifted mode APORT3YCH31 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT4YCH0                   (_ADC_SINGLECTRL_POSSEL_APORT4YCH0 << 8)   /**< Shifted mode APORT4YCH0 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT4XCH1                   (_ADC_SINGLECTRL_POSSEL_APORT4XCH1 << 8)   /**< Shifted mode APORT4XCH1 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT4YCH2                   (_ADC_SINGLECTRL_POSSEL_APORT4YCH2 << 8)   /**< Shifted mode APORT4YCH2 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT4XCH3                   (_ADC_SINGLECTRL_POSSEL_APORT4XCH3 << 8)   /**< Shifted mode APORT4XCH3 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT4YCH4                   (_ADC_SINGLECTRL_POSSEL_APORT4YCH4 << 8)   /**< Shifted mode APORT4YCH4 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT4XCH5                   (_ADC_SINGLECTRL_POSSEL_APORT4XCH5 << 8)   /**< Shifted mode APORT4XCH5 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT4YCH6                   (_ADC_SINGLECTRL_POSSEL_APORT4YCH6 << 8)   /**< Shifted mode APORT4YCH6 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT4XCH7                   (_ADC_SINGLECTRL_POSSEL_APORT4XCH7 << 8)   /**< Shifted mode APORT4XCH7 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT4YCH8                   (_ADC_SINGLECTRL_POSSEL_APORT4YCH8 << 8)   /**< Shifted mode APORT4YCH8 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT4XCH9                   (_ADC_SINGLECTRL_POSSEL_APORT4XCH9 << 8)   /**< Shifted mode APORT4XCH9 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT4YCH10                  (_ADC_SINGLECTRL_POSSEL_APORT4YCH10 << 8)  /**< Shifted mode APORT4YCH10 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT4XCH11                  (_ADC_SINGLECTRL_POSSEL_APORT4XCH11 << 8)  /**< Shifted mode APORT4XCH11 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT4YCH12                  (_ADC_SINGLECTRL_POSSEL_APORT4YCH12 << 8)  /**< Shifted mode APORT4YCH12 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT4XCH13                  (_ADC_SINGLECTRL_POSSEL_APORT4XCH13 << 8)  /**< Shifted mode APORT4XCH13 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT4YCH14                  (_ADC_SINGLECTRL_POSSEL_APORT4YCH14 << 8)  /**< Shifted mode APORT4YCH14 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT4XCH15                  (_ADC_SINGLECTRL_POSSEL_APORT4XCH15 << 8)  /**< Shifted mode APORT4XCH15 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT4YCH16                  (_ADC_SINGLECTRL_POSSEL_APORT4YCH16 << 8)  /**< Shifted mode APORT4YCH16 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT4XCH17                  (_ADC_SINGLECTRL_POSSEL_APORT4XCH17 << 8)  /**< Shifted mode APORT4XCH17 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT4YCH18                  (_ADC_SINGLECTRL_POSSEL_APORT4YCH18 << 8)  /**< Shifted mode APORT4YCH18 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT4XCH19                  (_ADC_SINGLECTRL_POSSEL_APORT4XCH19 << 8)  /**< Shifted mode APORT4XCH19 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT4YCH20                  (_ADC_SINGLECTRL_POSSEL_APORT4YCH20 << 8)  /**< Shifted mode APORT4YCH20 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT4XCH21                  (_ADC_SINGLECTRL_POSSEL_APORT4XCH21 << 8)  /**< Shifted mode APORT4XCH21 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT4YCH22                  (_ADC_SINGLECTRL_POSSEL_APORT4YCH22 << 8)  /**< Shifted mode APORT4YCH22 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT4XCH23                  (_ADC_SINGLECTRL_POSSEL_APORT4XCH23 << 8)  /**< Shifted mode APORT4XCH23 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT4YCH24                  (_ADC_SINGLECTRL_POSSEL_APORT4YCH24 << 8)  /**< Shifted mode APORT4YCH24 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT4XCH25                  (_ADC_SINGLECTRL_POSSEL_APORT4XCH25 << 8)  /**< Shifted mode APORT4XCH25 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT4YCH26                  (_ADC_SINGLECTRL_POSSEL_APORT4YCH26 << 8)  /**< Shifted mode APORT4YCH26 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT4XCH27                  (_ADC_SINGLECTRL_POSSEL_APORT4XCH27 << 8)  /**< Shifted mode APORT4XCH27 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT4YCH28                  (_ADC_SINGLECTRL_POSSEL_APORT4YCH28 << 8)  /**< Shifted mode APORT4YCH28 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT4XCH29                  (_ADC_SINGLECTRL_POSSEL_APORT4XCH29 << 8)  /**< Shifted mode APORT4XCH29 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT4YCH30                  (_ADC_SINGLECTRL_POSSEL_APORT4YCH30 << 8)  /**< Shifted mode APORT4YCH30 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT4XCH31                  (_ADC_SINGLECTRL_POSSEL_APORT4XCH31 << 8)  /**< Shifted mode APORT4XCH31 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_AVDD                         (_ADC_SINGLECTRL_POSSEL_AVDD << 8)         /**< Shifted mode AVDD for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_BU                           (_ADC_SINGLECTRL_POSSEL_BU << 8)           /**< Shifted mode BU for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_AREG                         (_ADC_SINGLECTRL_POSSEL_AREG << 8)         /**< Shifted mode AREG for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_VREGOUTPA                    (_ADC_SINGLECTRL_POSSEL_VREGOUTPA << 8)    /**< Shifted mode VREGOUTPA for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_PDBU                         (_ADC_SINGLECTRL_POSSEL_PDBU << 8)         /**< Shifted mode PDBU for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_IO0                          (_ADC_SINGLECTRL_POSSEL_IO0 << 8)          /**< Shifted mode IO0 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_IO1                          (_ADC_SINGLECTRL_POSSEL_IO1 << 8)          /**< Shifted mode IO1 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_VSP                          (_ADC_SINGLECTRL_POSSEL_VSP << 8)          /**< Shifted mode VSP for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_SP0                          (_ADC_SINGLECTRL_POSSEL_SP0 << 8)          /**< Shifted mode SP0 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_TEMP                         (_ADC_SINGLECTRL_POSSEL_TEMP << 8)         /**< Shifted mode TEMP for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_DAC0OUT0                     (_ADC_SINGLECTRL_POSSEL_DAC0OUT0 << 8)     /**< Shifted mode DAC0OUT0 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_TESTP                        (_ADC_SINGLECTRL_POSSEL_TESTP << 8)        /**< Shifted mode TESTP for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_SP1                          (_ADC_SINGLECTRL_POSSEL_SP1 << 8)          /**< Shifted mode SP1 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_SP2                          (_ADC_SINGLECTRL_POSSEL_SP2 << 8)          /**< Shifted mode SP2 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_DAC0OUT1                     (_ADC_SINGLECTRL_POSSEL_DAC0OUT1 << 8)     /**< Shifted mode DAC0OUT1 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_SUBLSB                       (_ADC_SINGLECTRL_POSSEL_SUBLSB << 8)       /**< Shifted mode SUBLSB for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_DEFAULT                      (_ADC_SINGLECTRL_POSSEL_DEFAULT << 8)      /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_VSS                          (_ADC_SINGLECTRL_POSSEL_VSS << 8)          /**< Shifted mode VSS for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_SHIFT                       16                                         /**< Shift value for ADC_NEGSEL */
+#define _ADC_SINGLECTRL_NEGSEL_MASK                        0xFF0000UL                                 /**< Bit mask for ADC_NEGSEL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH0                  0x00000000UL                               /**< Mode APORT0XCH0 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH1                  0x00000001UL                               /**< Mode APORT0XCH1 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH2                  0x00000002UL                               /**< Mode APORT0XCH2 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH3                  0x00000003UL                               /**< Mode APORT0XCH3 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH4                  0x00000004UL                               /**< Mode APORT0XCH4 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH5                  0x00000005UL                               /**< Mode APORT0XCH5 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH6                  0x00000006UL                               /**< Mode APORT0XCH6 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH7                  0x00000007UL                               /**< Mode APORT0XCH7 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH8                  0x00000008UL                               /**< Mode APORT0XCH8 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH9                  0x00000009UL                               /**< Mode APORT0XCH9 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH10                 0x0000000AUL                               /**< Mode APORT0XCH10 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH11                 0x0000000BUL                               /**< Mode APORT0XCH11 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH12                 0x0000000CUL                               /**< Mode APORT0XCH12 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH13                 0x0000000DUL                               /**< Mode APORT0XCH13 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH14                 0x0000000EUL                               /**< Mode APORT0XCH14 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH15                 0x0000000FUL                               /**< Mode APORT0XCH15 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH0                  0x00000010UL                               /**< Mode APORT0YCH0 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH1                  0x00000011UL                               /**< Mode APORT0YCH1 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH2                  0x00000012UL                               /**< Mode APORT0YCH2 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH3                  0x00000013UL                               /**< Mode APORT0YCH3 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH4                  0x00000014UL                               /**< Mode APORT0YCH4 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH5                  0x00000015UL                               /**< Mode APORT0YCH5 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH6                  0x00000016UL                               /**< Mode APORT0YCH6 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH7                  0x00000017UL                               /**< Mode APORT0YCH7 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH8                  0x00000018UL                               /**< Mode APORT0YCH8 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH9                  0x00000019UL                               /**< Mode APORT0YCH9 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH10                 0x0000001AUL                               /**< Mode APORT0YCH10 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH11                 0x0000001BUL                               /**< Mode APORT0YCH11 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH12                 0x0000001CUL                               /**< Mode APORT0YCH12 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH13                 0x0000001DUL                               /**< Mode APORT0YCH13 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH14                 0x0000001EUL                               /**< Mode APORT0YCH14 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH15                 0x0000001FUL                               /**< Mode APORT0YCH15 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH0                  0x00000020UL                               /**< Mode APORT1XCH0 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH1                  0x00000021UL                               /**< Mode APORT1YCH1 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH2                  0x00000022UL                               /**< Mode APORT1XCH2 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH3                  0x00000023UL                               /**< Mode APORT1YCH3 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH4                  0x00000024UL                               /**< Mode APORT1XCH4 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH5                  0x00000025UL                               /**< Mode APORT1YCH5 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH6                  0x00000026UL                               /**< Mode APORT1XCH6 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH7                  0x00000027UL                               /**< Mode APORT1YCH7 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH8                  0x00000028UL                               /**< Mode APORT1XCH8 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH9                  0x00000029UL                               /**< Mode APORT1YCH9 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH10                 0x0000002AUL                               /**< Mode APORT1XCH10 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH11                 0x0000002BUL                               /**< Mode APORT1YCH11 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH12                 0x0000002CUL                               /**< Mode APORT1XCH12 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH13                 0x0000002DUL                               /**< Mode APORT1YCH13 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH14                 0x0000002EUL                               /**< Mode APORT1XCH14 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH15                 0x0000002FUL                               /**< Mode APORT1YCH15 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH16                 0x00000030UL                               /**< Mode APORT1XCH16 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH17                 0x00000031UL                               /**< Mode APORT1YCH17 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH18                 0x00000032UL                               /**< Mode APORT1XCH18 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH19                 0x00000033UL                               /**< Mode APORT1YCH19 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH20                 0x00000034UL                               /**< Mode APORT1XCH20 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH21                 0x00000035UL                               /**< Mode APORT1YCH21 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH22                 0x00000036UL                               /**< Mode APORT1XCH22 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH23                 0x00000037UL                               /**< Mode APORT1YCH23 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH24                 0x00000038UL                               /**< Mode APORT1XCH24 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH25                 0x00000039UL                               /**< Mode APORT1YCH25 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH26                 0x0000003AUL                               /**< Mode APORT1XCH26 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH27                 0x0000003BUL                               /**< Mode APORT1YCH27 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH28                 0x0000003CUL                               /**< Mode APORT1XCH28 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH29                 0x0000003DUL                               /**< Mode APORT1YCH29 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH30                 0x0000003EUL                               /**< Mode APORT1XCH30 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH31                 0x0000003FUL                               /**< Mode APORT1YCH31 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH0                  0x00000040UL                               /**< Mode APORT2YCH0 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH1                  0x00000041UL                               /**< Mode APORT2XCH1 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH2                  0x00000042UL                               /**< Mode APORT2YCH2 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH3                  0x00000043UL                               /**< Mode APORT2XCH3 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH4                  0x00000044UL                               /**< Mode APORT2YCH4 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH5                  0x00000045UL                               /**< Mode APORT2XCH5 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH6                  0x00000046UL                               /**< Mode APORT2YCH6 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH7                  0x00000047UL                               /**< Mode APORT2XCH7 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH8                  0x00000048UL                               /**< Mode APORT2YCH8 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH9                  0x00000049UL                               /**< Mode APORT2XCH9 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH10                 0x0000004AUL                               /**< Mode APORT2YCH10 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH11                 0x0000004BUL                               /**< Mode APORT2XCH11 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH12                 0x0000004CUL                               /**< Mode APORT2YCH12 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH13                 0x0000004DUL                               /**< Mode APORT2XCH13 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH14                 0x0000004EUL                               /**< Mode APORT2YCH14 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH15                 0x0000004FUL                               /**< Mode APORT2XCH15 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH16                 0x00000050UL                               /**< Mode APORT2YCH16 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH17                 0x00000051UL                               /**< Mode APORT2XCH17 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH18                 0x00000052UL                               /**< Mode APORT2YCH18 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH19                 0x00000053UL                               /**< Mode APORT2XCH19 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH20                 0x00000054UL                               /**< Mode APORT2YCH20 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH21                 0x00000055UL                               /**< Mode APORT2XCH21 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH22                 0x00000056UL                               /**< Mode APORT2YCH22 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH23                 0x00000057UL                               /**< Mode APORT2XCH23 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH24                 0x00000058UL                               /**< Mode APORT2YCH24 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH25                 0x00000059UL                               /**< Mode APORT2XCH25 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH26                 0x0000005AUL                               /**< Mode APORT2YCH26 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH27                 0x0000005BUL                               /**< Mode APORT2XCH27 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH28                 0x0000005CUL                               /**< Mode APORT2YCH28 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH29                 0x0000005DUL                               /**< Mode APORT2XCH29 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH30                 0x0000005EUL                               /**< Mode APORT2YCH30 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH31                 0x0000005FUL                               /**< Mode APORT2XCH31 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH0                  0x00000060UL                               /**< Mode APORT3XCH0 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH1                  0x00000061UL                               /**< Mode APORT3YCH1 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH2                  0x00000062UL                               /**< Mode APORT3XCH2 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH3                  0x00000063UL                               /**< Mode APORT3YCH3 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH4                  0x00000064UL                               /**< Mode APORT3XCH4 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH5                  0x00000065UL                               /**< Mode APORT3YCH5 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH6                  0x00000066UL                               /**< Mode APORT3XCH6 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH7                  0x00000067UL                               /**< Mode APORT3YCH7 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH8                  0x00000068UL                               /**< Mode APORT3XCH8 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH9                  0x00000069UL                               /**< Mode APORT3YCH9 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH10                 0x0000006AUL                               /**< Mode APORT3XCH10 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH11                 0x0000006BUL                               /**< Mode APORT3YCH11 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH12                 0x0000006CUL                               /**< Mode APORT3XCH12 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH13                 0x0000006DUL                               /**< Mode APORT3YCH13 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH14                 0x0000006EUL                               /**< Mode APORT3XCH14 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH15                 0x0000006FUL                               /**< Mode APORT3YCH15 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH16                 0x00000070UL                               /**< Mode APORT3XCH16 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH17                 0x00000071UL                               /**< Mode APORT3YCH17 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH18                 0x00000072UL                               /**< Mode APORT3XCH18 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH19                 0x00000073UL                               /**< Mode APORT3YCH19 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH20                 0x00000074UL                               /**< Mode APORT3XCH20 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH21                 0x00000075UL                               /**< Mode APORT3YCH21 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH22                 0x00000076UL                               /**< Mode APORT3XCH22 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH23                 0x00000077UL                               /**< Mode APORT3YCH23 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH24                 0x00000078UL                               /**< Mode APORT3XCH24 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH25                 0x00000079UL                               /**< Mode APORT3YCH25 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH26                 0x0000007AUL                               /**< Mode APORT3XCH26 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH27                 0x0000007BUL                               /**< Mode APORT3YCH27 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH28                 0x0000007CUL                               /**< Mode APORT3XCH28 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH29                 0x0000007DUL                               /**< Mode APORT3YCH29 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH30                 0x0000007EUL                               /**< Mode APORT3XCH30 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH31                 0x0000007FUL                               /**< Mode APORT3YCH31 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH0                  0x00000080UL                               /**< Mode APORT4YCH0 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH1                  0x00000081UL                               /**< Mode APORT4XCH1 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH2                  0x00000082UL                               /**< Mode APORT4YCH2 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH3                  0x00000083UL                               /**< Mode APORT4XCH3 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH4                  0x00000084UL                               /**< Mode APORT4YCH4 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH5                  0x00000085UL                               /**< Mode APORT4XCH5 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH6                  0x00000086UL                               /**< Mode APORT4YCH6 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH7                  0x00000087UL                               /**< Mode APORT4XCH7 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH8                  0x00000088UL                               /**< Mode APORT4YCH8 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH9                  0x00000089UL                               /**< Mode APORT4XCH9 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH10                 0x0000008AUL                               /**< Mode APORT4YCH10 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH11                 0x0000008BUL                               /**< Mode APORT4XCH11 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH12                 0x0000008CUL                               /**< Mode APORT4YCH12 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH13                 0x0000008DUL                               /**< Mode APORT4XCH13 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH14                 0x0000008EUL                               /**< Mode APORT4YCH14 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH15                 0x0000008FUL                               /**< Mode APORT4XCH15 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH16                 0x00000090UL                               /**< Mode APORT4YCH16 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH17                 0x00000091UL                               /**< Mode APORT4XCH17 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH18                 0x00000092UL                               /**< Mode APORT4YCH18 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH19                 0x00000093UL                               /**< Mode APORT4XCH19 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH20                 0x00000094UL                               /**< Mode APORT4YCH20 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH21                 0x00000095UL                               /**< Mode APORT4XCH21 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH22                 0x00000096UL                               /**< Mode APORT4YCH22 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH23                 0x00000097UL                               /**< Mode APORT4XCH23 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH24                 0x00000098UL                               /**< Mode APORT4YCH24 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH25                 0x00000099UL                               /**< Mode APORT4XCH25 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH26                 0x0000009AUL                               /**< Mode APORT4YCH26 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH27                 0x0000009BUL                               /**< Mode APORT4XCH27 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH28                 0x0000009CUL                               /**< Mode APORT4YCH28 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH29                 0x0000009DUL                               /**< Mode APORT4XCH29 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH30                 0x0000009EUL                               /**< Mode APORT4YCH30 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH31                 0x0000009FUL                               /**< Mode APORT4XCH31 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_TESTN                       0x000000F5UL                               /**< Mode TESTN for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_DEFAULT                     0x000000FFUL                               /**< Mode DEFAULT for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_VSS                         0x000000FFUL                               /**< Mode VSS for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT0XCH0                   (_ADC_SINGLECTRL_NEGSEL_APORT0XCH0 << 16)  /**< Shifted mode APORT0XCH0 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT0XCH1                   (_ADC_SINGLECTRL_NEGSEL_APORT0XCH1 << 16)  /**< Shifted mode APORT0XCH1 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT0XCH2                   (_ADC_SINGLECTRL_NEGSEL_APORT0XCH2 << 16)  /**< Shifted mode APORT0XCH2 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT0XCH3                   (_ADC_SINGLECTRL_NEGSEL_APORT0XCH3 << 16)  /**< Shifted mode APORT0XCH3 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT0XCH4                   (_ADC_SINGLECTRL_NEGSEL_APORT0XCH4 << 16)  /**< Shifted mode APORT0XCH4 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT0XCH5                   (_ADC_SINGLECTRL_NEGSEL_APORT0XCH5 << 16)  /**< Shifted mode APORT0XCH5 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT0XCH6                   (_ADC_SINGLECTRL_NEGSEL_APORT0XCH6 << 16)  /**< Shifted mode APORT0XCH6 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT0XCH7                   (_ADC_SINGLECTRL_NEGSEL_APORT0XCH7 << 16)  /**< Shifted mode APORT0XCH7 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT0XCH8                   (_ADC_SINGLECTRL_NEGSEL_APORT0XCH8 << 16)  /**< Shifted mode APORT0XCH8 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT0XCH9                   (_ADC_SINGLECTRL_NEGSEL_APORT0XCH9 << 16)  /**< Shifted mode APORT0XCH9 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT0XCH10                  (_ADC_SINGLECTRL_NEGSEL_APORT0XCH10 << 16) /**< Shifted mode APORT0XCH10 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT0XCH11                  (_ADC_SINGLECTRL_NEGSEL_APORT0XCH11 << 16) /**< Shifted mode APORT0XCH11 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT0XCH12                  (_ADC_SINGLECTRL_NEGSEL_APORT0XCH12 << 16) /**< Shifted mode APORT0XCH12 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT0XCH13                  (_ADC_SINGLECTRL_NEGSEL_APORT0XCH13 << 16) /**< Shifted mode APORT0XCH13 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT0XCH14                  (_ADC_SINGLECTRL_NEGSEL_APORT0XCH14 << 16) /**< Shifted mode APORT0XCH14 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT0XCH15                  (_ADC_SINGLECTRL_NEGSEL_APORT0XCH15 << 16) /**< Shifted mode APORT0XCH15 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT0YCH0                   (_ADC_SINGLECTRL_NEGSEL_APORT0YCH0 << 16)  /**< Shifted mode APORT0YCH0 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT0YCH1                   (_ADC_SINGLECTRL_NEGSEL_APORT0YCH1 << 16)  /**< Shifted mode APORT0YCH1 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT0YCH2                   (_ADC_SINGLECTRL_NEGSEL_APORT0YCH2 << 16)  /**< Shifted mode APORT0YCH2 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT0YCH3                   (_ADC_SINGLECTRL_NEGSEL_APORT0YCH3 << 16)  /**< Shifted mode APORT0YCH3 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT0YCH4                   (_ADC_SINGLECTRL_NEGSEL_APORT0YCH4 << 16)  /**< Shifted mode APORT0YCH4 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT0YCH5                   (_ADC_SINGLECTRL_NEGSEL_APORT0YCH5 << 16)  /**< Shifted mode APORT0YCH5 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT0YCH6                   (_ADC_SINGLECTRL_NEGSEL_APORT0YCH6 << 16)  /**< Shifted mode APORT0YCH6 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT0YCH7                   (_ADC_SINGLECTRL_NEGSEL_APORT0YCH7 << 16)  /**< Shifted mode APORT0YCH7 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT0YCH8                   (_ADC_SINGLECTRL_NEGSEL_APORT0YCH8 << 16)  /**< Shifted mode APORT0YCH8 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT0YCH9                   (_ADC_SINGLECTRL_NEGSEL_APORT0YCH9 << 16)  /**< Shifted mode APORT0YCH9 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT0YCH10                  (_ADC_SINGLECTRL_NEGSEL_APORT0YCH10 << 16) /**< Shifted mode APORT0YCH10 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT0YCH11                  (_ADC_SINGLECTRL_NEGSEL_APORT0YCH11 << 16) /**< Shifted mode APORT0YCH11 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT0YCH12                  (_ADC_SINGLECTRL_NEGSEL_APORT0YCH12 << 16) /**< Shifted mode APORT0YCH12 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT0YCH13                  (_ADC_SINGLECTRL_NEGSEL_APORT0YCH13 << 16) /**< Shifted mode APORT0YCH13 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT0YCH14                  (_ADC_SINGLECTRL_NEGSEL_APORT0YCH14 << 16) /**< Shifted mode APORT0YCH14 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT0YCH15                  (_ADC_SINGLECTRL_NEGSEL_APORT0YCH15 << 16) /**< Shifted mode APORT0YCH15 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT1XCH0                   (_ADC_SINGLECTRL_NEGSEL_APORT1XCH0 << 16)  /**< Shifted mode APORT1XCH0 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT1YCH1                   (_ADC_SINGLECTRL_NEGSEL_APORT1YCH1 << 16)  /**< Shifted mode APORT1YCH1 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT1XCH2                   (_ADC_SINGLECTRL_NEGSEL_APORT1XCH2 << 16)  /**< Shifted mode APORT1XCH2 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT1YCH3                   (_ADC_SINGLECTRL_NEGSEL_APORT1YCH3 << 16)  /**< Shifted mode APORT1YCH3 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT1XCH4                   (_ADC_SINGLECTRL_NEGSEL_APORT1XCH4 << 16)  /**< Shifted mode APORT1XCH4 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT1YCH5                   (_ADC_SINGLECTRL_NEGSEL_APORT1YCH5 << 16)  /**< Shifted mode APORT1YCH5 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT1XCH6                   (_ADC_SINGLECTRL_NEGSEL_APORT1XCH6 << 16)  /**< Shifted mode APORT1XCH6 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT1YCH7                   (_ADC_SINGLECTRL_NEGSEL_APORT1YCH7 << 16)  /**< Shifted mode APORT1YCH7 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT1XCH8                   (_ADC_SINGLECTRL_NEGSEL_APORT1XCH8 << 16)  /**< Shifted mode APORT1XCH8 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT1YCH9                   (_ADC_SINGLECTRL_NEGSEL_APORT1YCH9 << 16)  /**< Shifted mode APORT1YCH9 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT1XCH10                  (_ADC_SINGLECTRL_NEGSEL_APORT1XCH10 << 16) /**< Shifted mode APORT1XCH10 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT1YCH11                  (_ADC_SINGLECTRL_NEGSEL_APORT1YCH11 << 16) /**< Shifted mode APORT1YCH11 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT1XCH12                  (_ADC_SINGLECTRL_NEGSEL_APORT1XCH12 << 16) /**< Shifted mode APORT1XCH12 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT1YCH13                  (_ADC_SINGLECTRL_NEGSEL_APORT1YCH13 << 16) /**< Shifted mode APORT1YCH13 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT1XCH14                  (_ADC_SINGLECTRL_NEGSEL_APORT1XCH14 << 16) /**< Shifted mode APORT1XCH14 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT1YCH15                  (_ADC_SINGLECTRL_NEGSEL_APORT1YCH15 << 16) /**< Shifted mode APORT1YCH15 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT1XCH16                  (_ADC_SINGLECTRL_NEGSEL_APORT1XCH16 << 16) /**< Shifted mode APORT1XCH16 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT1YCH17                  (_ADC_SINGLECTRL_NEGSEL_APORT1YCH17 << 16) /**< Shifted mode APORT1YCH17 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT1XCH18                  (_ADC_SINGLECTRL_NEGSEL_APORT1XCH18 << 16) /**< Shifted mode APORT1XCH18 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT1YCH19                  (_ADC_SINGLECTRL_NEGSEL_APORT1YCH19 << 16) /**< Shifted mode APORT1YCH19 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT1XCH20                  (_ADC_SINGLECTRL_NEGSEL_APORT1XCH20 << 16) /**< Shifted mode APORT1XCH20 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT1YCH21                  (_ADC_SINGLECTRL_NEGSEL_APORT1YCH21 << 16) /**< Shifted mode APORT1YCH21 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT1XCH22                  (_ADC_SINGLECTRL_NEGSEL_APORT1XCH22 << 16) /**< Shifted mode APORT1XCH22 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT1YCH23                  (_ADC_SINGLECTRL_NEGSEL_APORT1YCH23 << 16) /**< Shifted mode APORT1YCH23 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT1XCH24                  (_ADC_SINGLECTRL_NEGSEL_APORT1XCH24 << 16) /**< Shifted mode APORT1XCH24 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT1YCH25                  (_ADC_SINGLECTRL_NEGSEL_APORT1YCH25 << 16) /**< Shifted mode APORT1YCH25 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT1XCH26                  (_ADC_SINGLECTRL_NEGSEL_APORT1XCH26 << 16) /**< Shifted mode APORT1XCH26 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT1YCH27                  (_ADC_SINGLECTRL_NEGSEL_APORT1YCH27 << 16) /**< Shifted mode APORT1YCH27 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT1XCH28                  (_ADC_SINGLECTRL_NEGSEL_APORT1XCH28 << 16) /**< Shifted mode APORT1XCH28 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT1YCH29                  (_ADC_SINGLECTRL_NEGSEL_APORT1YCH29 << 16) /**< Shifted mode APORT1YCH29 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT1XCH30                  (_ADC_SINGLECTRL_NEGSEL_APORT1XCH30 << 16) /**< Shifted mode APORT1XCH30 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT1YCH31                  (_ADC_SINGLECTRL_NEGSEL_APORT1YCH31 << 16) /**< Shifted mode APORT1YCH31 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT2YCH0                   (_ADC_SINGLECTRL_NEGSEL_APORT2YCH0 << 16)  /**< Shifted mode APORT2YCH0 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT2XCH1                   (_ADC_SINGLECTRL_NEGSEL_APORT2XCH1 << 16)  /**< Shifted mode APORT2XCH1 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT2YCH2                   (_ADC_SINGLECTRL_NEGSEL_APORT2YCH2 << 16)  /**< Shifted mode APORT2YCH2 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT2XCH3                   (_ADC_SINGLECTRL_NEGSEL_APORT2XCH3 << 16)  /**< Shifted mode APORT2XCH3 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT2YCH4                   (_ADC_SINGLECTRL_NEGSEL_APORT2YCH4 << 16)  /**< Shifted mode APORT2YCH4 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT2XCH5                   (_ADC_SINGLECTRL_NEGSEL_APORT2XCH5 << 16)  /**< Shifted mode APORT2XCH5 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT2YCH6                   (_ADC_SINGLECTRL_NEGSEL_APORT2YCH6 << 16)  /**< Shifted mode APORT2YCH6 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT2XCH7                   (_ADC_SINGLECTRL_NEGSEL_APORT2XCH7 << 16)  /**< Shifted mode APORT2XCH7 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT2YCH8                   (_ADC_SINGLECTRL_NEGSEL_APORT2YCH8 << 16)  /**< Shifted mode APORT2YCH8 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT2XCH9                   (_ADC_SINGLECTRL_NEGSEL_APORT2XCH9 << 16)  /**< Shifted mode APORT2XCH9 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT2YCH10                  (_ADC_SINGLECTRL_NEGSEL_APORT2YCH10 << 16) /**< Shifted mode APORT2YCH10 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT2XCH11                  (_ADC_SINGLECTRL_NEGSEL_APORT2XCH11 << 16) /**< Shifted mode APORT2XCH11 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT2YCH12                  (_ADC_SINGLECTRL_NEGSEL_APORT2YCH12 << 16) /**< Shifted mode APORT2YCH12 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT2XCH13                  (_ADC_SINGLECTRL_NEGSEL_APORT2XCH13 << 16) /**< Shifted mode APORT2XCH13 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT2YCH14                  (_ADC_SINGLECTRL_NEGSEL_APORT2YCH14 << 16) /**< Shifted mode APORT2YCH14 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT2XCH15                  (_ADC_SINGLECTRL_NEGSEL_APORT2XCH15 << 16) /**< Shifted mode APORT2XCH15 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT2YCH16                  (_ADC_SINGLECTRL_NEGSEL_APORT2YCH16 << 16) /**< Shifted mode APORT2YCH16 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT2XCH17                  (_ADC_SINGLECTRL_NEGSEL_APORT2XCH17 << 16) /**< Shifted mode APORT2XCH17 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT2YCH18                  (_ADC_SINGLECTRL_NEGSEL_APORT2YCH18 << 16) /**< Shifted mode APORT2YCH18 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT2XCH19                  (_ADC_SINGLECTRL_NEGSEL_APORT2XCH19 << 16) /**< Shifted mode APORT2XCH19 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT2YCH20                  (_ADC_SINGLECTRL_NEGSEL_APORT2YCH20 << 16) /**< Shifted mode APORT2YCH20 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT2XCH21                  (_ADC_SINGLECTRL_NEGSEL_APORT2XCH21 << 16) /**< Shifted mode APORT2XCH21 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT2YCH22                  (_ADC_SINGLECTRL_NEGSEL_APORT2YCH22 << 16) /**< Shifted mode APORT2YCH22 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT2XCH23                  (_ADC_SINGLECTRL_NEGSEL_APORT2XCH23 << 16) /**< Shifted mode APORT2XCH23 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT2YCH24                  (_ADC_SINGLECTRL_NEGSEL_APORT2YCH24 << 16) /**< Shifted mode APORT2YCH24 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT2XCH25                  (_ADC_SINGLECTRL_NEGSEL_APORT2XCH25 << 16) /**< Shifted mode APORT2XCH25 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT2YCH26                  (_ADC_SINGLECTRL_NEGSEL_APORT2YCH26 << 16) /**< Shifted mode APORT2YCH26 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT2XCH27                  (_ADC_SINGLECTRL_NEGSEL_APORT2XCH27 << 16) /**< Shifted mode APORT2XCH27 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT2YCH28                  (_ADC_SINGLECTRL_NEGSEL_APORT2YCH28 << 16) /**< Shifted mode APORT2YCH28 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT2XCH29                  (_ADC_SINGLECTRL_NEGSEL_APORT2XCH29 << 16) /**< Shifted mode APORT2XCH29 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT2YCH30                  (_ADC_SINGLECTRL_NEGSEL_APORT2YCH30 << 16) /**< Shifted mode APORT2YCH30 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT2XCH31                  (_ADC_SINGLECTRL_NEGSEL_APORT2XCH31 << 16) /**< Shifted mode APORT2XCH31 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT3XCH0                   (_ADC_SINGLECTRL_NEGSEL_APORT3XCH0 << 16)  /**< Shifted mode APORT3XCH0 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT3YCH1                   (_ADC_SINGLECTRL_NEGSEL_APORT3YCH1 << 16)  /**< Shifted mode APORT3YCH1 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT3XCH2                   (_ADC_SINGLECTRL_NEGSEL_APORT3XCH2 << 16)  /**< Shifted mode APORT3XCH2 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT3YCH3                   (_ADC_SINGLECTRL_NEGSEL_APORT3YCH3 << 16)  /**< Shifted mode APORT3YCH3 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT3XCH4                   (_ADC_SINGLECTRL_NEGSEL_APORT3XCH4 << 16)  /**< Shifted mode APORT3XCH4 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT3YCH5                   (_ADC_SINGLECTRL_NEGSEL_APORT3YCH5 << 16)  /**< Shifted mode APORT3YCH5 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT3XCH6                   (_ADC_SINGLECTRL_NEGSEL_APORT3XCH6 << 16)  /**< Shifted mode APORT3XCH6 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT3YCH7                   (_ADC_SINGLECTRL_NEGSEL_APORT3YCH7 << 16)  /**< Shifted mode APORT3YCH7 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT3XCH8                   (_ADC_SINGLECTRL_NEGSEL_APORT3XCH8 << 16)  /**< Shifted mode APORT3XCH8 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT3YCH9                   (_ADC_SINGLECTRL_NEGSEL_APORT3YCH9 << 16)  /**< Shifted mode APORT3YCH9 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT3XCH10                  (_ADC_SINGLECTRL_NEGSEL_APORT3XCH10 << 16) /**< Shifted mode APORT3XCH10 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT3YCH11                  (_ADC_SINGLECTRL_NEGSEL_APORT3YCH11 << 16) /**< Shifted mode APORT3YCH11 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT3XCH12                  (_ADC_SINGLECTRL_NEGSEL_APORT3XCH12 << 16) /**< Shifted mode APORT3XCH12 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT3YCH13                  (_ADC_SINGLECTRL_NEGSEL_APORT3YCH13 << 16) /**< Shifted mode APORT3YCH13 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT3XCH14                  (_ADC_SINGLECTRL_NEGSEL_APORT3XCH14 << 16) /**< Shifted mode APORT3XCH14 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT3YCH15                  (_ADC_SINGLECTRL_NEGSEL_APORT3YCH15 << 16) /**< Shifted mode APORT3YCH15 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT3XCH16                  (_ADC_SINGLECTRL_NEGSEL_APORT3XCH16 << 16) /**< Shifted mode APORT3XCH16 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT3YCH17                  (_ADC_SINGLECTRL_NEGSEL_APORT3YCH17 << 16) /**< Shifted mode APORT3YCH17 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT3XCH18                  (_ADC_SINGLECTRL_NEGSEL_APORT3XCH18 << 16) /**< Shifted mode APORT3XCH18 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT3YCH19                  (_ADC_SINGLECTRL_NEGSEL_APORT3YCH19 << 16) /**< Shifted mode APORT3YCH19 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT3XCH20                  (_ADC_SINGLECTRL_NEGSEL_APORT3XCH20 << 16) /**< Shifted mode APORT3XCH20 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT3YCH21                  (_ADC_SINGLECTRL_NEGSEL_APORT3YCH21 << 16) /**< Shifted mode APORT3YCH21 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT3XCH22                  (_ADC_SINGLECTRL_NEGSEL_APORT3XCH22 << 16) /**< Shifted mode APORT3XCH22 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT3YCH23                  (_ADC_SINGLECTRL_NEGSEL_APORT3YCH23 << 16) /**< Shifted mode APORT3YCH23 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT3XCH24                  (_ADC_SINGLECTRL_NEGSEL_APORT3XCH24 << 16) /**< Shifted mode APORT3XCH24 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT3YCH25                  (_ADC_SINGLECTRL_NEGSEL_APORT3YCH25 << 16) /**< Shifted mode APORT3YCH25 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT3XCH26                  (_ADC_SINGLECTRL_NEGSEL_APORT3XCH26 << 16) /**< Shifted mode APORT3XCH26 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT3YCH27                  (_ADC_SINGLECTRL_NEGSEL_APORT3YCH27 << 16) /**< Shifted mode APORT3YCH27 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT3XCH28                  (_ADC_SINGLECTRL_NEGSEL_APORT3XCH28 << 16) /**< Shifted mode APORT3XCH28 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT3YCH29                  (_ADC_SINGLECTRL_NEGSEL_APORT3YCH29 << 16) /**< Shifted mode APORT3YCH29 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT3XCH30                  (_ADC_SINGLECTRL_NEGSEL_APORT3XCH30 << 16) /**< Shifted mode APORT3XCH30 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT3YCH31                  (_ADC_SINGLECTRL_NEGSEL_APORT3YCH31 << 16) /**< Shifted mode APORT3YCH31 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT4YCH0                   (_ADC_SINGLECTRL_NEGSEL_APORT4YCH0 << 16)  /**< Shifted mode APORT4YCH0 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT4XCH1                   (_ADC_SINGLECTRL_NEGSEL_APORT4XCH1 << 16)  /**< Shifted mode APORT4XCH1 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT4YCH2                   (_ADC_SINGLECTRL_NEGSEL_APORT4YCH2 << 16)  /**< Shifted mode APORT4YCH2 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT4XCH3                   (_ADC_SINGLECTRL_NEGSEL_APORT4XCH3 << 16)  /**< Shifted mode APORT4XCH3 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT4YCH4                   (_ADC_SINGLECTRL_NEGSEL_APORT4YCH4 << 16)  /**< Shifted mode APORT4YCH4 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT4XCH5                   (_ADC_SINGLECTRL_NEGSEL_APORT4XCH5 << 16)  /**< Shifted mode APORT4XCH5 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT4YCH6                   (_ADC_SINGLECTRL_NEGSEL_APORT4YCH6 << 16)  /**< Shifted mode APORT4YCH6 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT4XCH7                   (_ADC_SINGLECTRL_NEGSEL_APORT4XCH7 << 16)  /**< Shifted mode APORT4XCH7 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT4YCH8                   (_ADC_SINGLECTRL_NEGSEL_APORT4YCH8 << 16)  /**< Shifted mode APORT4YCH8 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT4XCH9                   (_ADC_SINGLECTRL_NEGSEL_APORT4XCH9 << 16)  /**< Shifted mode APORT4XCH9 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT4YCH10                  (_ADC_SINGLECTRL_NEGSEL_APORT4YCH10 << 16) /**< Shifted mode APORT4YCH10 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT4XCH11                  (_ADC_SINGLECTRL_NEGSEL_APORT4XCH11 << 16) /**< Shifted mode APORT4XCH11 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT4YCH12                  (_ADC_SINGLECTRL_NEGSEL_APORT4YCH12 << 16) /**< Shifted mode APORT4YCH12 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT4XCH13                  (_ADC_SINGLECTRL_NEGSEL_APORT4XCH13 << 16) /**< Shifted mode APORT4XCH13 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT4YCH14                  (_ADC_SINGLECTRL_NEGSEL_APORT4YCH14 << 16) /**< Shifted mode APORT4YCH14 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT4XCH15                  (_ADC_SINGLECTRL_NEGSEL_APORT4XCH15 << 16) /**< Shifted mode APORT4XCH15 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT4YCH16                  (_ADC_SINGLECTRL_NEGSEL_APORT4YCH16 << 16) /**< Shifted mode APORT4YCH16 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT4XCH17                  (_ADC_SINGLECTRL_NEGSEL_APORT4XCH17 << 16) /**< Shifted mode APORT4XCH17 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT4YCH18                  (_ADC_SINGLECTRL_NEGSEL_APORT4YCH18 << 16) /**< Shifted mode APORT4YCH18 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT4XCH19                  (_ADC_SINGLECTRL_NEGSEL_APORT4XCH19 << 16) /**< Shifted mode APORT4XCH19 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT4YCH20                  (_ADC_SINGLECTRL_NEGSEL_APORT4YCH20 << 16) /**< Shifted mode APORT4YCH20 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT4XCH21                  (_ADC_SINGLECTRL_NEGSEL_APORT4XCH21 << 16) /**< Shifted mode APORT4XCH21 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT4YCH22                  (_ADC_SINGLECTRL_NEGSEL_APORT4YCH22 << 16) /**< Shifted mode APORT4YCH22 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT4XCH23                  (_ADC_SINGLECTRL_NEGSEL_APORT4XCH23 << 16) /**< Shifted mode APORT4XCH23 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT4YCH24                  (_ADC_SINGLECTRL_NEGSEL_APORT4YCH24 << 16) /**< Shifted mode APORT4YCH24 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT4XCH25                  (_ADC_SINGLECTRL_NEGSEL_APORT4XCH25 << 16) /**< Shifted mode APORT4XCH25 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT4YCH26                  (_ADC_SINGLECTRL_NEGSEL_APORT4YCH26 << 16) /**< Shifted mode APORT4YCH26 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT4XCH27                  (_ADC_SINGLECTRL_NEGSEL_APORT4XCH27 << 16) /**< Shifted mode APORT4XCH27 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT4YCH28                  (_ADC_SINGLECTRL_NEGSEL_APORT4YCH28 << 16) /**< Shifted mode APORT4YCH28 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT4XCH29                  (_ADC_SINGLECTRL_NEGSEL_APORT4XCH29 << 16) /**< Shifted mode APORT4XCH29 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT4YCH30                  (_ADC_SINGLECTRL_NEGSEL_APORT4YCH30 << 16) /**< Shifted mode APORT4YCH30 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT4XCH31                  (_ADC_SINGLECTRL_NEGSEL_APORT4XCH31 << 16) /**< Shifted mode APORT4XCH31 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_TESTN                        (_ADC_SINGLECTRL_NEGSEL_TESTN << 16)       /**< Shifted mode TESTN for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_DEFAULT                      (_ADC_SINGLECTRL_NEGSEL_DEFAULT << 16)     /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_VSS                          (_ADC_SINGLECTRL_NEGSEL_VSS << 16)         /**< Shifted mode VSS for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_AT_SHIFT                           24                                         /**< Shift value for ADC_AT */
+#define _ADC_SINGLECTRL_AT_MASK                            0xF000000UL                                /**< Bit mask for ADC_AT */
+#define _ADC_SINGLECTRL_AT_DEFAULT                         0x00000000UL                               /**< Mode DEFAULT for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_AT_1CYCLE                          0x00000000UL                               /**< Mode 1CYCLE for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_AT_2CYCLES                         0x00000001UL                               /**< Mode 2CYCLES for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_AT_3CYCLES                         0x00000002UL                               /**< Mode 3CYCLES for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_AT_4CYCLES                         0x00000003UL                               /**< Mode 4CYCLES for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_AT_8CYCLES                         0x00000004UL                               /**< Mode 8CYCLES for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_AT_16CYCLES                        0x00000005UL                               /**< Mode 16CYCLES for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_AT_32CYCLES                        0x00000006UL                               /**< Mode 32CYCLES for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_AT_64CYCLES                        0x00000007UL                               /**< Mode 64CYCLES for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_AT_128CYCLES                       0x00000008UL                               /**< Mode 128CYCLES for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_AT_256CYCLES                       0x00000009UL                               /**< Mode 256CYCLES for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_AT_DEFAULT                          (_ADC_SINGLECTRL_AT_DEFAULT << 24)         /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_AT_1CYCLE                           (_ADC_SINGLECTRL_AT_1CYCLE << 24)          /**< Shifted mode 1CYCLE for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_AT_2CYCLES                          (_ADC_SINGLECTRL_AT_2CYCLES << 24)         /**< Shifted mode 2CYCLES for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_AT_3CYCLES                          (_ADC_SINGLECTRL_AT_3CYCLES << 24)         /**< Shifted mode 3CYCLES for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_AT_4CYCLES                          (_ADC_SINGLECTRL_AT_4CYCLES << 24)         /**< Shifted mode 4CYCLES for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_AT_8CYCLES                          (_ADC_SINGLECTRL_AT_8CYCLES << 24)         /**< Shifted mode 8CYCLES for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_AT_16CYCLES                         (_ADC_SINGLECTRL_AT_16CYCLES << 24)        /**< Shifted mode 16CYCLES for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_AT_32CYCLES                         (_ADC_SINGLECTRL_AT_32CYCLES << 24)        /**< Shifted mode 32CYCLES for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_AT_64CYCLES                         (_ADC_SINGLECTRL_AT_64CYCLES << 24)        /**< Shifted mode 64CYCLES for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_AT_128CYCLES                        (_ADC_SINGLECTRL_AT_128CYCLES << 24)       /**< Shifted mode 128CYCLES for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_AT_256CYCLES                        (_ADC_SINGLECTRL_AT_256CYCLES << 24)       /**< Shifted mode 256CYCLES for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_PRSEN                               (0x1UL << 29)                              /**< Single Channel PRS Trigger Enable */
+#define _ADC_SINGLECTRL_PRSEN_SHIFT                        29                                         /**< Shift value for ADC_PRSEN */
+#define _ADC_SINGLECTRL_PRSEN_MASK                         0x20000000UL                               /**< Bit mask for ADC_PRSEN */
+#define _ADC_SINGLECTRL_PRSEN_DEFAULT                      0x00000000UL                               /**< Mode DEFAULT for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_PRSEN_DEFAULT                       (_ADC_SINGLECTRL_PRSEN_DEFAULT << 29)      /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_CMPEN                               (0x1UL << 31)                              /**< Compare Logic Enable for Single Channel */
+#define _ADC_SINGLECTRL_CMPEN_SHIFT                        31                                         /**< Shift value for ADC_CMPEN */
+#define _ADC_SINGLECTRL_CMPEN_MASK                         0x80000000UL                               /**< Bit mask for ADC_CMPEN */
+#define _ADC_SINGLECTRL_CMPEN_DEFAULT                      0x00000000UL                               /**< Mode DEFAULT for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_CMPEN_DEFAULT                       (_ADC_SINGLECTRL_CMPEN_DEFAULT << 31)      /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
+
+/* Bit fields for ADC SINGLECTRLX */
+#define _ADC_SINGLECTRLX_RESETVALUE                        0x00000000UL                                      /**< Default value for ADC_SINGLECTRLX */
+#define _ADC_SINGLECTRLX_MASK                              0x0F1F7FFFUL                                      /**< Mask for ADC_SINGLECTRLX */
+#define _ADC_SINGLECTRLX_VREFSEL_SHIFT                     0                                                 /**< Shift value for ADC_VREFSEL */
+#define _ADC_SINGLECTRLX_VREFSEL_MASK                      0x7UL                                             /**< Bit mask for ADC_VREFSEL */
+#define _ADC_SINGLECTRLX_VREFSEL_DEFAULT                   0x00000000UL                                      /**< Mode DEFAULT for ADC_SINGLECTRLX */
+#define _ADC_SINGLECTRLX_VREFSEL_VBGR                      0x00000000UL                                      /**< Mode VBGR for ADC_SINGLECTRLX */
+#define _ADC_SINGLECTRLX_VREFSEL_VDDXWATT                  0x00000001UL                                      /**< Mode VDDXWATT for ADC_SINGLECTRLX */
+#define _ADC_SINGLECTRLX_VREFSEL_VREFPWATT                 0x00000002UL                                      /**< Mode VREFPWATT for ADC_SINGLECTRLX */
+#define _ADC_SINGLECTRLX_VREFSEL_VREFP                     0x00000003UL                                      /**< Mode VREFP for ADC_SINGLECTRLX */
+#define _ADC_SINGLECTRLX_VREFSEL_VENTROPY                  0x00000004UL                                      /**< Mode VENTROPY for ADC_SINGLECTRLX */
+#define _ADC_SINGLECTRLX_VREFSEL_VREFPNWATT                0x00000005UL                                      /**< Mode VREFPNWATT for ADC_SINGLECTRLX */
+#define _ADC_SINGLECTRLX_VREFSEL_VREFPN                    0x00000006UL                                      /**< Mode VREFPN for ADC_SINGLECTRLX */
+#define _ADC_SINGLECTRLX_VREFSEL_VBGRLOW                   0x00000007UL                                      /**< Mode VBGRLOW for ADC_SINGLECTRLX */
+#define ADC_SINGLECTRLX_VREFSEL_DEFAULT                    (_ADC_SINGLECTRLX_VREFSEL_DEFAULT << 0)           /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */
+#define ADC_SINGLECTRLX_VREFSEL_VBGR                       (_ADC_SINGLECTRLX_VREFSEL_VBGR << 0)              /**< Shifted mode VBGR for ADC_SINGLECTRLX */
+#define ADC_SINGLECTRLX_VREFSEL_VDDXWATT                   (_ADC_SINGLECTRLX_VREFSEL_VDDXWATT << 0)          /**< Shifted mode VDDXWATT for ADC_SINGLECTRLX */
+#define ADC_SINGLECTRLX_VREFSEL_VREFPWATT                  (_ADC_SINGLECTRLX_VREFSEL_VREFPWATT << 0)         /**< Shifted mode VREFPWATT for ADC_SINGLECTRLX */
+#define ADC_SINGLECTRLX_VREFSEL_VREFP                      (_ADC_SINGLECTRLX_VREFSEL_VREFP << 0)             /**< Shifted mode VREFP for ADC_SINGLECTRLX */
+#define ADC_SINGLECTRLX_VREFSEL_VENTROPY                   (_ADC_SINGLECTRLX_VREFSEL_VENTROPY << 0)          /**< Shifted mode VENTROPY for ADC_SINGLECTRLX */
+#define ADC_SINGLECTRLX_VREFSEL_VREFPNWATT                 (_ADC_SINGLECTRLX_VREFSEL_VREFPNWATT << 0)        /**< Shifted mode VREFPNWATT for ADC_SINGLECTRLX */
+#define ADC_SINGLECTRLX_VREFSEL_VREFPN                     (_ADC_SINGLECTRLX_VREFSEL_VREFPN << 0)            /**< Shifted mode VREFPN for ADC_SINGLECTRLX */
+#define ADC_SINGLECTRLX_VREFSEL_VBGRLOW                    (_ADC_SINGLECTRLX_VREFSEL_VBGRLOW << 0)           /**< Shifted mode VBGRLOW for ADC_SINGLECTRLX */
+#define ADC_SINGLECTRLX_VREFATTFIX                         (0x1UL << 3)                                      /**< Enable 1/3 scaling on VREF */
+#define _ADC_SINGLECTRLX_VREFATTFIX_SHIFT                  3                                                 /**< Shift value for ADC_VREFATTFIX */
+#define _ADC_SINGLECTRLX_VREFATTFIX_MASK                   0x8UL                                             /**< Bit mask for ADC_VREFATTFIX */
+#define _ADC_SINGLECTRLX_VREFATTFIX_DEFAULT                0x00000000UL                                      /**< Mode DEFAULT for ADC_SINGLECTRLX */
+#define ADC_SINGLECTRLX_VREFATTFIX_DEFAULT                 (_ADC_SINGLECTRLX_VREFATTFIX_DEFAULT << 3)        /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */
+#define _ADC_SINGLECTRLX_VREFATT_SHIFT                     4                                                 /**< Shift value for ADC_VREFATT */
+#define _ADC_SINGLECTRLX_VREFATT_MASK                      0xF0UL                                            /**< Bit mask for ADC_VREFATT */
+#define _ADC_SINGLECTRLX_VREFATT_DEFAULT                   0x00000000UL                                      /**< Mode DEFAULT for ADC_SINGLECTRLX */
+#define ADC_SINGLECTRLX_VREFATT_DEFAULT                    (_ADC_SINGLECTRLX_VREFATT_DEFAULT << 4)           /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */
+#define _ADC_SINGLECTRLX_VINATT_SHIFT                      8                                                 /**< Shift value for ADC_VINATT */
+#define _ADC_SINGLECTRLX_VINATT_MASK                       0xF00UL                                           /**< Bit mask for ADC_VINATT */
+#define _ADC_SINGLECTRLX_VINATT_DEFAULT                    0x00000000UL                                      /**< Mode DEFAULT for ADC_SINGLECTRLX */
+#define ADC_SINGLECTRLX_VINATT_DEFAULT                     (_ADC_SINGLECTRLX_VINATT_DEFAULT << 8)            /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */
+#define _ADC_SINGLECTRLX_DVL_SHIFT                         12                                                /**< Shift value for ADC_DVL */
+#define _ADC_SINGLECTRLX_DVL_MASK                          0x3000UL                                          /**< Bit mask for ADC_DVL */
+#define _ADC_SINGLECTRLX_DVL_DEFAULT                       0x00000000UL                                      /**< Mode DEFAULT for ADC_SINGLECTRLX */
+#define ADC_SINGLECTRLX_DVL_DEFAULT                        (_ADC_SINGLECTRLX_DVL_DEFAULT << 12)              /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */
+#define ADC_SINGLECTRLX_FIFOOFACT                          (0x1UL << 14)                                     /**< Single Channel FIFO Overflow Action */
+#define _ADC_SINGLECTRLX_FIFOOFACT_SHIFT                   14                                                /**< Shift value for ADC_FIFOOFACT */
+#define _ADC_SINGLECTRLX_FIFOOFACT_MASK                    0x4000UL                                          /**< Bit mask for ADC_FIFOOFACT */
+#define _ADC_SINGLECTRLX_FIFOOFACT_DEFAULT                 0x00000000UL                                      /**< Mode DEFAULT for ADC_SINGLECTRLX */
+#define _ADC_SINGLECTRLX_FIFOOFACT_DISCARD                 0x00000000UL                                      /**< Mode DISCARD for ADC_SINGLECTRLX */
+#define _ADC_SINGLECTRLX_FIFOOFACT_OVERWRITE               0x00000001UL                                      /**< Mode OVERWRITE for ADC_SINGLECTRLX */
+#define ADC_SINGLECTRLX_FIFOOFACT_DEFAULT                  (_ADC_SINGLECTRLX_FIFOOFACT_DEFAULT << 14)        /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */
+#define ADC_SINGLECTRLX_FIFOOFACT_DISCARD                  (_ADC_SINGLECTRLX_FIFOOFACT_DISCARD << 14)        /**< Shifted mode DISCARD for ADC_SINGLECTRLX */
+#define ADC_SINGLECTRLX_FIFOOFACT_OVERWRITE                (_ADC_SINGLECTRLX_FIFOOFACT_OVERWRITE << 14)      /**< Shifted mode OVERWRITE for ADC_SINGLECTRLX */
+#define ADC_SINGLECTRLX_PRSMODE                            (0x1UL << 16)                                     /**< Single Channel PRS Trigger Mode */
+#define _ADC_SINGLECTRLX_PRSMODE_SHIFT                     16                                                /**< Shift value for ADC_PRSMODE */
+#define _ADC_SINGLECTRLX_PRSMODE_MASK                      0x10000UL                                         /**< Bit mask for ADC_PRSMODE */
+#define _ADC_SINGLECTRLX_PRSMODE_DEFAULT                   0x00000000UL                                      /**< Mode DEFAULT for ADC_SINGLECTRLX */
+#define _ADC_SINGLECTRLX_PRSMODE_PULSED                    0x00000000UL                                      /**< Mode PULSED for ADC_SINGLECTRLX */
+#define _ADC_SINGLECTRLX_PRSMODE_TIMED                     0x00000001UL                                      /**< Mode TIMED for ADC_SINGLECTRLX */
+#define ADC_SINGLECTRLX_PRSMODE_DEFAULT                    (_ADC_SINGLECTRLX_PRSMODE_DEFAULT << 16)          /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */
+#define ADC_SINGLECTRLX_PRSMODE_PULSED                     (_ADC_SINGLECTRLX_PRSMODE_PULSED << 16)           /**< Shifted mode PULSED for ADC_SINGLECTRLX */
+#define ADC_SINGLECTRLX_PRSMODE_TIMED                      (_ADC_SINGLECTRLX_PRSMODE_TIMED << 16)            /**< Shifted mode TIMED for ADC_SINGLECTRLX */
+#define _ADC_SINGLECTRLX_PRSSEL_SHIFT                      17                                                /**< Shift value for ADC_PRSSEL */
+#define _ADC_SINGLECTRLX_PRSSEL_MASK                       0x1E0000UL                                        /**< Bit mask for ADC_PRSSEL */
+#define _ADC_SINGLECTRLX_PRSSEL_DEFAULT                    0x00000000UL                                      /**< Mode DEFAULT for ADC_SINGLECTRLX */
+#define _ADC_SINGLECTRLX_PRSSEL_PRSCH0                     0x00000000UL                                      /**< Mode PRSCH0 for ADC_SINGLECTRLX */
+#define _ADC_SINGLECTRLX_PRSSEL_PRSCH1                     0x00000001UL                                      /**< Mode PRSCH1 for ADC_SINGLECTRLX */
+#define _ADC_SINGLECTRLX_PRSSEL_PRSCH2                     0x00000002UL                                      /**< Mode PRSCH2 for ADC_SINGLECTRLX */
+#define _ADC_SINGLECTRLX_PRSSEL_PRSCH3                     0x00000003UL                                      /**< Mode PRSCH3 for ADC_SINGLECTRLX */
+#define _ADC_SINGLECTRLX_PRSSEL_PRSCH4                     0x00000004UL                                      /**< Mode PRSCH4 for ADC_SINGLECTRLX */
+#define _ADC_SINGLECTRLX_PRSSEL_PRSCH5                     0x00000005UL                                      /**< Mode PRSCH5 for ADC_SINGLECTRLX */
+#define _ADC_SINGLECTRLX_PRSSEL_PRSCH6                     0x00000006UL                                      /**< Mode PRSCH6 for ADC_SINGLECTRLX */
+#define _ADC_SINGLECTRLX_PRSSEL_PRSCH7                     0x00000007UL                                      /**< Mode PRSCH7 for ADC_SINGLECTRLX */
+#define _ADC_SINGLECTRLX_PRSSEL_PRSCH8                     0x00000008UL                                      /**< Mode PRSCH8 for ADC_SINGLECTRLX */
+#define _ADC_SINGLECTRLX_PRSSEL_PRSCH9                     0x00000009UL                                      /**< Mode PRSCH9 for ADC_SINGLECTRLX */
+#define _ADC_SINGLECTRLX_PRSSEL_PRSCH10                    0x0000000AUL                                      /**< Mode PRSCH10 for ADC_SINGLECTRLX */
+#define _ADC_SINGLECTRLX_PRSSEL_PRSCH11                    0x0000000BUL                                      /**< Mode PRSCH11 for ADC_SINGLECTRLX */
+#define ADC_SINGLECTRLX_PRSSEL_DEFAULT                     (_ADC_SINGLECTRLX_PRSSEL_DEFAULT << 17)           /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */
+#define ADC_SINGLECTRLX_PRSSEL_PRSCH0                      (_ADC_SINGLECTRLX_PRSSEL_PRSCH0 << 17)            /**< Shifted mode PRSCH0 for ADC_SINGLECTRLX */
+#define ADC_SINGLECTRLX_PRSSEL_PRSCH1                      (_ADC_SINGLECTRLX_PRSSEL_PRSCH1 << 17)            /**< Shifted mode PRSCH1 for ADC_SINGLECTRLX */
+#define ADC_SINGLECTRLX_PRSSEL_PRSCH2                      (_ADC_SINGLECTRLX_PRSSEL_PRSCH2 << 17)            /**< Shifted mode PRSCH2 for ADC_SINGLECTRLX */
+#define ADC_SINGLECTRLX_PRSSEL_PRSCH3                      (_ADC_SINGLECTRLX_PRSSEL_PRSCH3 << 17)            /**< Shifted mode PRSCH3 for ADC_SINGLECTRLX */
+#define ADC_SINGLECTRLX_PRSSEL_PRSCH4                      (_ADC_SINGLECTRLX_PRSSEL_PRSCH4 << 17)            /**< Shifted mode PRSCH4 for ADC_SINGLECTRLX */
+#define ADC_SINGLECTRLX_PRSSEL_PRSCH5                      (_ADC_SINGLECTRLX_PRSSEL_PRSCH5 << 17)            /**< Shifted mode PRSCH5 for ADC_SINGLECTRLX */
+#define ADC_SINGLECTRLX_PRSSEL_PRSCH6                      (_ADC_SINGLECTRLX_PRSSEL_PRSCH6 << 17)            /**< Shifted mode PRSCH6 for ADC_SINGLECTRLX */
+#define ADC_SINGLECTRLX_PRSSEL_PRSCH7                      (_ADC_SINGLECTRLX_PRSSEL_PRSCH7 << 17)            /**< Shifted mode PRSCH7 for ADC_SINGLECTRLX */
+#define ADC_SINGLECTRLX_PRSSEL_PRSCH8                      (_ADC_SINGLECTRLX_PRSSEL_PRSCH8 << 17)            /**< Shifted mode PRSCH8 for ADC_SINGLECTRLX */
+#define ADC_SINGLECTRLX_PRSSEL_PRSCH9                      (_ADC_SINGLECTRLX_PRSSEL_PRSCH9 << 17)            /**< Shifted mode PRSCH9 for ADC_SINGLECTRLX */
+#define ADC_SINGLECTRLX_PRSSEL_PRSCH10                     (_ADC_SINGLECTRLX_PRSSEL_PRSCH10 << 17)           /**< Shifted mode PRSCH10 for ADC_SINGLECTRLX */
+#define ADC_SINGLECTRLX_PRSSEL_PRSCH11                     (_ADC_SINGLECTRLX_PRSSEL_PRSCH11 << 17)           /**< Shifted mode PRSCH11 for ADC_SINGLECTRLX */
+#define _ADC_SINGLECTRLX_CONVSTARTDELAY_SHIFT              24                                                /**< Shift value for ADC_CONVSTARTDELAY */
+#define _ADC_SINGLECTRLX_CONVSTARTDELAY_MASK               0x7000000UL                                       /**< Bit mask for ADC_CONVSTARTDELAY */
+#define _ADC_SINGLECTRLX_CONVSTARTDELAY_DEFAULT            0x00000000UL                                      /**< Mode DEFAULT for ADC_SINGLECTRLX */
+#define ADC_SINGLECTRLX_CONVSTARTDELAY_DEFAULT             (_ADC_SINGLECTRLX_CONVSTARTDELAY_DEFAULT << 24)   /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */
+#define ADC_SINGLECTRLX_CONVSTARTDELAYEN                   (0x1UL << 27)                                     /**< Enable delaying next conversion start */
+#define _ADC_SINGLECTRLX_CONVSTARTDELAYEN_SHIFT            27                                                /**< Shift value for ADC_CONVSTARTDELAYEN */
+#define _ADC_SINGLECTRLX_CONVSTARTDELAYEN_MASK             0x8000000UL                                       /**< Bit mask for ADC_CONVSTARTDELAYEN */
+#define _ADC_SINGLECTRLX_CONVSTARTDELAYEN_DEFAULT          0x00000000UL                                      /**< Mode DEFAULT for ADC_SINGLECTRLX */
+#define ADC_SINGLECTRLX_CONVSTARTDELAYEN_DEFAULT           (_ADC_SINGLECTRLX_CONVSTARTDELAYEN_DEFAULT << 27) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */
+
+/* Bit fields for ADC SCANCTRL */
+#define _ADC_SCANCTRL_RESETVALUE                           0x00000000UL                        /**< Default value for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_MASK                                 0xAF0000FFUL                        /**< Mask for ADC_SCANCTRL */
+#define ADC_SCANCTRL_REP                                   (0x1UL << 0)                        /**< Scan Sequence Repetitive Mode */
+#define _ADC_SCANCTRL_REP_SHIFT                            0                                   /**< Shift value for ADC_REP */
+#define _ADC_SCANCTRL_REP_MASK                             0x1UL                               /**< Bit mask for ADC_REP */
+#define _ADC_SCANCTRL_REP_DEFAULT                          0x00000000UL                        /**< Mode DEFAULT for ADC_SCANCTRL */
+#define ADC_SCANCTRL_REP_DEFAULT                           (_ADC_SCANCTRL_REP_DEFAULT << 0)    /**< Shifted mode DEFAULT for ADC_SCANCTRL */
+#define ADC_SCANCTRL_DIFF                                  (0x1UL << 1)                        /**< Scan Sequence Differential Mode */
+#define _ADC_SCANCTRL_DIFF_SHIFT                           1                                   /**< Shift value for ADC_DIFF */
+#define _ADC_SCANCTRL_DIFF_MASK                            0x2UL                               /**< Bit mask for ADC_DIFF */
+#define _ADC_SCANCTRL_DIFF_DEFAULT                         0x00000000UL                        /**< Mode DEFAULT for ADC_SCANCTRL */
+#define ADC_SCANCTRL_DIFF_DEFAULT                          (_ADC_SCANCTRL_DIFF_DEFAULT << 1)   /**< Shifted mode DEFAULT for ADC_SCANCTRL */
+#define ADC_SCANCTRL_ADJ                                   (0x1UL << 2)                        /**< Scan Sequence Result Adjustment */
+#define _ADC_SCANCTRL_ADJ_SHIFT                            2                                   /**< Shift value for ADC_ADJ */
+#define _ADC_SCANCTRL_ADJ_MASK                             0x4UL                               /**< Bit mask for ADC_ADJ */
+#define _ADC_SCANCTRL_ADJ_DEFAULT                          0x00000000UL                        /**< Mode DEFAULT for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_ADJ_RIGHT                            0x00000000UL                        /**< Mode RIGHT for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_ADJ_LEFT                             0x00000001UL                        /**< Mode LEFT for ADC_SCANCTRL */
+#define ADC_SCANCTRL_ADJ_DEFAULT                           (_ADC_SCANCTRL_ADJ_DEFAULT << 2)    /**< Shifted mode DEFAULT for ADC_SCANCTRL */
+#define ADC_SCANCTRL_ADJ_RIGHT                             (_ADC_SCANCTRL_ADJ_RIGHT << 2)      /**< Shifted mode RIGHT for ADC_SCANCTRL */
+#define ADC_SCANCTRL_ADJ_LEFT                              (_ADC_SCANCTRL_ADJ_LEFT << 2)       /**< Shifted mode LEFT for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_RES_SHIFT                            3                                   /**< Shift value for ADC_RES */
+#define _ADC_SCANCTRL_RES_MASK                             0x18UL                              /**< Bit mask for ADC_RES */
+#define _ADC_SCANCTRL_RES_DEFAULT                          0x00000000UL                        /**< Mode DEFAULT for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_RES_12BIT                            0x00000000UL                        /**< Mode 12BIT for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_RES_8BIT                             0x00000001UL                        /**< Mode 8BIT for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_RES_6BIT                             0x00000002UL                        /**< Mode 6BIT for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_RES_OVS                              0x00000003UL                        /**< Mode OVS for ADC_SCANCTRL */
+#define ADC_SCANCTRL_RES_DEFAULT                           (_ADC_SCANCTRL_RES_DEFAULT << 3)    /**< Shifted mode DEFAULT for ADC_SCANCTRL */
+#define ADC_SCANCTRL_RES_12BIT                             (_ADC_SCANCTRL_RES_12BIT << 3)      /**< Shifted mode 12BIT for ADC_SCANCTRL */
+#define ADC_SCANCTRL_RES_8BIT                              (_ADC_SCANCTRL_RES_8BIT << 3)       /**< Shifted mode 8BIT for ADC_SCANCTRL */
+#define ADC_SCANCTRL_RES_6BIT                              (_ADC_SCANCTRL_RES_6BIT << 3)       /**< Shifted mode 6BIT for ADC_SCANCTRL */
+#define ADC_SCANCTRL_RES_OVS                               (_ADC_SCANCTRL_RES_OVS << 3)        /**< Shifted mode OVS for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_REF_SHIFT                            5                                   /**< Shift value for ADC_REF */
+#define _ADC_SCANCTRL_REF_MASK                             0xE0UL                              /**< Bit mask for ADC_REF */
+#define _ADC_SCANCTRL_REF_DEFAULT                          0x00000000UL                        /**< Mode DEFAULT for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_REF_1V25                             0x00000000UL                        /**< Mode 1V25 for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_REF_2V5                              0x00000001UL                        /**< Mode 2V5 for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_REF_VDD                              0x00000002UL                        /**< Mode VDD for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_REF_5VDIFF                           0x00000003UL                        /**< Mode 5VDIFF for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_REF_EXTSINGLE                        0x00000004UL                        /**< Mode EXTSINGLE for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_REF_2XEXTDIFF                        0x00000005UL                        /**< Mode 2XEXTDIFF for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_REF_2XVDD                            0x00000006UL                        /**< Mode 2XVDD for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_REF_CONF                             0x00000007UL                        /**< Mode CONF for ADC_SCANCTRL */
+#define ADC_SCANCTRL_REF_DEFAULT                           (_ADC_SCANCTRL_REF_DEFAULT << 5)    /**< Shifted mode DEFAULT for ADC_SCANCTRL */
+#define ADC_SCANCTRL_REF_1V25                              (_ADC_SCANCTRL_REF_1V25 << 5)       /**< Shifted mode 1V25 for ADC_SCANCTRL */
+#define ADC_SCANCTRL_REF_2V5                               (_ADC_SCANCTRL_REF_2V5 << 5)        /**< Shifted mode 2V5 for ADC_SCANCTRL */
+#define ADC_SCANCTRL_REF_VDD                               (_ADC_SCANCTRL_REF_VDD << 5)        /**< Shifted mode VDD for ADC_SCANCTRL */
+#define ADC_SCANCTRL_REF_5VDIFF                            (_ADC_SCANCTRL_REF_5VDIFF << 5)     /**< Shifted mode 5VDIFF for ADC_SCANCTRL */
+#define ADC_SCANCTRL_REF_EXTSINGLE                         (_ADC_SCANCTRL_REF_EXTSINGLE << 5)  /**< Shifted mode EXTSINGLE for ADC_SCANCTRL */
+#define ADC_SCANCTRL_REF_2XEXTDIFF                         (_ADC_SCANCTRL_REF_2XEXTDIFF << 5)  /**< Shifted mode 2XEXTDIFF for ADC_SCANCTRL */
+#define ADC_SCANCTRL_REF_2XVDD                             (_ADC_SCANCTRL_REF_2XVDD << 5)      /**< Shifted mode 2XVDD for ADC_SCANCTRL */
+#define ADC_SCANCTRL_REF_CONF                              (_ADC_SCANCTRL_REF_CONF << 5)       /**< Shifted mode CONF for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_AT_SHIFT                             24                                  /**< Shift value for ADC_AT */
+#define _ADC_SCANCTRL_AT_MASK                              0xF000000UL                         /**< Bit mask for ADC_AT */
+#define _ADC_SCANCTRL_AT_DEFAULT                           0x00000000UL                        /**< Mode DEFAULT for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_AT_1CYCLE                            0x00000000UL                        /**< Mode 1CYCLE for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_AT_2CYCLES                           0x00000001UL                        /**< Mode 2CYCLES for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_AT_3CYCLES                           0x00000002UL                        /**< Mode 3CYCLES for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_AT_4CYCLES                           0x00000003UL                        /**< Mode 4CYCLES for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_AT_8CYCLES                           0x00000004UL                        /**< Mode 8CYCLES for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_AT_16CYCLES                          0x00000005UL                        /**< Mode 16CYCLES for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_AT_32CYCLES                          0x00000006UL                        /**< Mode 32CYCLES for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_AT_64CYCLES                          0x00000007UL                        /**< Mode 64CYCLES for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_AT_128CYCLES                         0x00000008UL                        /**< Mode 128CYCLES for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_AT_256CYCLES                         0x00000009UL                        /**< Mode 256CYCLES for ADC_SCANCTRL */
+#define ADC_SCANCTRL_AT_DEFAULT                            (_ADC_SCANCTRL_AT_DEFAULT << 24)    /**< Shifted mode DEFAULT for ADC_SCANCTRL */
+#define ADC_SCANCTRL_AT_1CYCLE                             (_ADC_SCANCTRL_AT_1CYCLE << 24)     /**< Shifted mode 1CYCLE for ADC_SCANCTRL */
+#define ADC_SCANCTRL_AT_2CYCLES                            (_ADC_SCANCTRL_AT_2CYCLES << 24)    /**< Shifted mode 2CYCLES for ADC_SCANCTRL */
+#define ADC_SCANCTRL_AT_3CYCLES                            (_ADC_SCANCTRL_AT_3CYCLES << 24)    /**< Shifted mode 3CYCLES for ADC_SCANCTRL */
+#define ADC_SCANCTRL_AT_4CYCLES                            (_ADC_SCANCTRL_AT_4CYCLES << 24)    /**< Shifted mode 4CYCLES for ADC_SCANCTRL */
+#define ADC_SCANCTRL_AT_8CYCLES                            (_ADC_SCANCTRL_AT_8CYCLES << 24)    /**< Shifted mode 8CYCLES for ADC_SCANCTRL */
+#define ADC_SCANCTRL_AT_16CYCLES                           (_ADC_SCANCTRL_AT_16CYCLES << 24)   /**< Shifted mode 16CYCLES for ADC_SCANCTRL */
+#define ADC_SCANCTRL_AT_32CYCLES                           (_ADC_SCANCTRL_AT_32CYCLES << 24)   /**< Shifted mode 32CYCLES for ADC_SCANCTRL */
+#define ADC_SCANCTRL_AT_64CYCLES                           (_ADC_SCANCTRL_AT_64CYCLES << 24)   /**< Shifted mode 64CYCLES for ADC_SCANCTRL */
+#define ADC_SCANCTRL_AT_128CYCLES                          (_ADC_SCANCTRL_AT_128CYCLES << 24)  /**< Shifted mode 128CYCLES for ADC_SCANCTRL */
+#define ADC_SCANCTRL_AT_256CYCLES                          (_ADC_SCANCTRL_AT_256CYCLES << 24)  /**< Shifted mode 256CYCLES for ADC_SCANCTRL */
+#define ADC_SCANCTRL_PRSEN                                 (0x1UL << 29)                       /**< Scan Sequence PRS Trigger Enable */
+#define _ADC_SCANCTRL_PRSEN_SHIFT                          29                                  /**< Shift value for ADC_PRSEN */
+#define _ADC_SCANCTRL_PRSEN_MASK                           0x20000000UL                        /**< Bit mask for ADC_PRSEN */
+#define _ADC_SCANCTRL_PRSEN_DEFAULT                        0x00000000UL                        /**< Mode DEFAULT for ADC_SCANCTRL */
+#define ADC_SCANCTRL_PRSEN_DEFAULT                         (_ADC_SCANCTRL_PRSEN_DEFAULT << 29) /**< Shifted mode DEFAULT for ADC_SCANCTRL */
+#define ADC_SCANCTRL_CMPEN                                 (0x1UL << 31)                       /**< Compare Logic Enable for Scan */
+#define _ADC_SCANCTRL_CMPEN_SHIFT                          31                                  /**< Shift value for ADC_CMPEN */
+#define _ADC_SCANCTRL_CMPEN_MASK                           0x80000000UL                        /**< Bit mask for ADC_CMPEN */
+#define _ADC_SCANCTRL_CMPEN_DEFAULT                        0x00000000UL                        /**< Mode DEFAULT for ADC_SCANCTRL */
+#define ADC_SCANCTRL_CMPEN_DEFAULT                         (_ADC_SCANCTRL_CMPEN_DEFAULT << 31) /**< Shifted mode DEFAULT for ADC_SCANCTRL */
+
+/* Bit fields for ADC SCANCTRLX */
+#define _ADC_SCANCTRLX_RESETVALUE                          0x00000000UL                                    /**< Default value for ADC_SCANCTRLX */
+#define _ADC_SCANCTRLX_MASK                                0x0F1F7FFFUL                                    /**< Mask for ADC_SCANCTRLX */
+#define _ADC_SCANCTRLX_VREFSEL_SHIFT                       0                                               /**< Shift value for ADC_VREFSEL */
+#define _ADC_SCANCTRLX_VREFSEL_MASK                        0x7UL                                           /**< Bit mask for ADC_VREFSEL */
+#define _ADC_SCANCTRLX_VREFSEL_DEFAULT                     0x00000000UL                                    /**< Mode DEFAULT for ADC_SCANCTRLX */
+#define _ADC_SCANCTRLX_VREFSEL_VBGR                        0x00000000UL                                    /**< Mode VBGR for ADC_SCANCTRLX */
+#define _ADC_SCANCTRLX_VREFSEL_VDDXWATT                    0x00000001UL                                    /**< Mode VDDXWATT for ADC_SCANCTRLX */
+#define _ADC_SCANCTRLX_VREFSEL_VREFPWATT                   0x00000002UL                                    /**< Mode VREFPWATT for ADC_SCANCTRLX */
+#define _ADC_SCANCTRLX_VREFSEL_VREFP                       0x00000003UL                                    /**< Mode VREFP for ADC_SCANCTRLX */
+#define _ADC_SCANCTRLX_VREFSEL_VENTROPY                    0x00000004UL                                    /**< Mode VENTROPY for ADC_SCANCTRLX */
+#define _ADC_SCANCTRLX_VREFSEL_VREFPNWATT                  0x00000005UL                                    /**< Mode VREFPNWATT for ADC_SCANCTRLX */
+#define _ADC_SCANCTRLX_VREFSEL_VREFPN                      0x00000006UL                                    /**< Mode VREFPN for ADC_SCANCTRLX */
+#define _ADC_SCANCTRLX_VREFSEL_VBGRLOW                     0x00000007UL                                    /**< Mode VBGRLOW for ADC_SCANCTRLX */
+#define ADC_SCANCTRLX_VREFSEL_DEFAULT                      (_ADC_SCANCTRLX_VREFSEL_DEFAULT << 0)           /**< Shifted mode DEFAULT for ADC_SCANCTRLX */
+#define ADC_SCANCTRLX_VREFSEL_VBGR                         (_ADC_SCANCTRLX_VREFSEL_VBGR << 0)              /**< Shifted mode VBGR for ADC_SCANCTRLX */
+#define ADC_SCANCTRLX_VREFSEL_VDDXWATT                     (_ADC_SCANCTRLX_VREFSEL_VDDXWATT << 0)          /**< Shifted mode VDDXWATT for ADC_SCANCTRLX */
+#define ADC_SCANCTRLX_VREFSEL_VREFPWATT                    (_ADC_SCANCTRLX_VREFSEL_VREFPWATT << 0)         /**< Shifted mode VREFPWATT for ADC_SCANCTRLX */
+#define ADC_SCANCTRLX_VREFSEL_VREFP                        (_ADC_SCANCTRLX_VREFSEL_VREFP << 0)             /**< Shifted mode VREFP for ADC_SCANCTRLX */
+#define ADC_SCANCTRLX_VREFSEL_VENTROPY                     (_ADC_SCANCTRLX_VREFSEL_VENTROPY << 0)          /**< Shifted mode VENTROPY for ADC_SCANCTRLX */
+#define ADC_SCANCTRLX_VREFSEL_VREFPNWATT                   (_ADC_SCANCTRLX_VREFSEL_VREFPNWATT << 0)        /**< Shifted mode VREFPNWATT for ADC_SCANCTRLX */
+#define ADC_SCANCTRLX_VREFSEL_VREFPN                       (_ADC_SCANCTRLX_VREFSEL_VREFPN << 0)            /**< Shifted mode VREFPN for ADC_SCANCTRLX */
+#define ADC_SCANCTRLX_VREFSEL_VBGRLOW                      (_ADC_SCANCTRLX_VREFSEL_VBGRLOW << 0)           /**< Shifted mode VBGRLOW for ADC_SCANCTRLX */
+#define ADC_SCANCTRLX_VREFATTFIX                           (0x1UL << 3)                                    /**< Enable fixed 1/3 scaling on VREF */
+#define _ADC_SCANCTRLX_VREFATTFIX_SHIFT                    3                                               /**< Shift value for ADC_VREFATTFIX */
+#define _ADC_SCANCTRLX_VREFATTFIX_MASK                     0x8UL                                           /**< Bit mask for ADC_VREFATTFIX */
+#define _ADC_SCANCTRLX_VREFATTFIX_DEFAULT                  0x00000000UL                                    /**< Mode DEFAULT for ADC_SCANCTRLX */
+#define ADC_SCANCTRLX_VREFATTFIX_DEFAULT                   (_ADC_SCANCTRLX_VREFATTFIX_DEFAULT << 3)        /**< Shifted mode DEFAULT for ADC_SCANCTRLX */
+#define _ADC_SCANCTRLX_VREFATT_SHIFT                       4                                               /**< Shift value for ADC_VREFATT */
+#define _ADC_SCANCTRLX_VREFATT_MASK                        0xF0UL                                          /**< Bit mask for ADC_VREFATT */
+#define _ADC_SCANCTRLX_VREFATT_DEFAULT                     0x00000000UL                                    /**< Mode DEFAULT for ADC_SCANCTRLX */
+#define ADC_SCANCTRLX_VREFATT_DEFAULT                      (_ADC_SCANCTRLX_VREFATT_DEFAULT << 4)           /**< Shifted mode DEFAULT for ADC_SCANCTRLX */
+#define _ADC_SCANCTRLX_VINATT_SHIFT                        8                                               /**< Shift value for ADC_VINATT */
+#define _ADC_SCANCTRLX_VINATT_MASK                         0xF00UL                                         /**< Bit mask for ADC_VINATT */
+#define _ADC_SCANCTRLX_VINATT_DEFAULT                      0x00000000UL                                    /**< Mode DEFAULT for ADC_SCANCTRLX */
+#define ADC_SCANCTRLX_VINATT_DEFAULT                       (_ADC_SCANCTRLX_VINATT_DEFAULT << 8)            /**< Shifted mode DEFAULT for ADC_SCANCTRLX */
+#define _ADC_SCANCTRLX_DVL_SHIFT                           12                                              /**< Shift value for ADC_DVL */
+#define _ADC_SCANCTRLX_DVL_MASK                            0x3000UL                                        /**< Bit mask for ADC_DVL */
+#define _ADC_SCANCTRLX_DVL_DEFAULT                         0x00000000UL                                    /**< Mode DEFAULT for ADC_SCANCTRLX */
+#define ADC_SCANCTRLX_DVL_DEFAULT                          (_ADC_SCANCTRLX_DVL_DEFAULT << 12)              /**< Shifted mode DEFAULT for ADC_SCANCTRLX */
+#define ADC_SCANCTRLX_FIFOOFACT                            (0x1UL << 14)                                   /**< Scan FIFO Overflow Action */
+#define _ADC_SCANCTRLX_FIFOOFACT_SHIFT                     14                                              /**< Shift value for ADC_FIFOOFACT */
+#define _ADC_SCANCTRLX_FIFOOFACT_MASK                      0x4000UL                                        /**< Bit mask for ADC_FIFOOFACT */
+#define _ADC_SCANCTRLX_FIFOOFACT_DEFAULT                   0x00000000UL                                    /**< Mode DEFAULT for ADC_SCANCTRLX */
+#define _ADC_SCANCTRLX_FIFOOFACT_DISCARD                   0x00000000UL                                    /**< Mode DISCARD for ADC_SCANCTRLX */
+#define _ADC_SCANCTRLX_FIFOOFACT_OVERWRITE                 0x00000001UL                                    /**< Mode OVERWRITE for ADC_SCANCTRLX */
+#define ADC_SCANCTRLX_FIFOOFACT_DEFAULT                    (_ADC_SCANCTRLX_FIFOOFACT_DEFAULT << 14)        /**< Shifted mode DEFAULT for ADC_SCANCTRLX */
+#define ADC_SCANCTRLX_FIFOOFACT_DISCARD                    (_ADC_SCANCTRLX_FIFOOFACT_DISCARD << 14)        /**< Shifted mode DISCARD for ADC_SCANCTRLX */
+#define ADC_SCANCTRLX_FIFOOFACT_OVERWRITE                  (_ADC_SCANCTRLX_FIFOOFACT_OVERWRITE << 14)      /**< Shifted mode OVERWRITE for ADC_SCANCTRLX */
+#define ADC_SCANCTRLX_PRSMODE                              (0x1UL << 16)                                   /**< Scan PRS Trigger Mode */
+#define _ADC_SCANCTRLX_PRSMODE_SHIFT                       16                                              /**< Shift value for ADC_PRSMODE */
+#define _ADC_SCANCTRLX_PRSMODE_MASK                        0x10000UL                                       /**< Bit mask for ADC_PRSMODE */
+#define _ADC_SCANCTRLX_PRSMODE_DEFAULT                     0x00000000UL                                    /**< Mode DEFAULT for ADC_SCANCTRLX */
+#define _ADC_SCANCTRLX_PRSMODE_PULSED                      0x00000000UL                                    /**< Mode PULSED for ADC_SCANCTRLX */
+#define _ADC_SCANCTRLX_PRSMODE_TIMED                       0x00000001UL                                    /**< Mode TIMED for ADC_SCANCTRLX */
+#define ADC_SCANCTRLX_PRSMODE_DEFAULT                      (_ADC_SCANCTRLX_PRSMODE_DEFAULT << 16)          /**< Shifted mode DEFAULT for ADC_SCANCTRLX */
+#define ADC_SCANCTRLX_PRSMODE_PULSED                       (_ADC_SCANCTRLX_PRSMODE_PULSED << 16)           /**< Shifted mode PULSED for ADC_SCANCTRLX */
+#define ADC_SCANCTRLX_PRSMODE_TIMED                        (_ADC_SCANCTRLX_PRSMODE_TIMED << 16)            /**< Shifted mode TIMED for ADC_SCANCTRLX */
+#define _ADC_SCANCTRLX_PRSSEL_SHIFT                        17                                              /**< Shift value for ADC_PRSSEL */
+#define _ADC_SCANCTRLX_PRSSEL_MASK                         0x1E0000UL                                      /**< Bit mask for ADC_PRSSEL */
+#define _ADC_SCANCTRLX_PRSSEL_DEFAULT                      0x00000000UL                                    /**< Mode DEFAULT for ADC_SCANCTRLX */
+#define _ADC_SCANCTRLX_PRSSEL_PRSCH0                       0x00000000UL                                    /**< Mode PRSCH0 for ADC_SCANCTRLX */
+#define _ADC_SCANCTRLX_PRSSEL_PRSCH1                       0x00000001UL                                    /**< Mode PRSCH1 for ADC_SCANCTRLX */
+#define _ADC_SCANCTRLX_PRSSEL_PRSCH2                       0x00000002UL                                    /**< Mode PRSCH2 for ADC_SCANCTRLX */
+#define _ADC_SCANCTRLX_PRSSEL_PRSCH3                       0x00000003UL                                    /**< Mode PRSCH3 for ADC_SCANCTRLX */
+#define _ADC_SCANCTRLX_PRSSEL_PRSCH4                       0x00000004UL                                    /**< Mode PRSCH4 for ADC_SCANCTRLX */
+#define _ADC_SCANCTRLX_PRSSEL_PRSCH5                       0x00000005UL                                    /**< Mode PRSCH5 for ADC_SCANCTRLX */
+#define _ADC_SCANCTRLX_PRSSEL_PRSCH6                       0x00000006UL                                    /**< Mode PRSCH6 for ADC_SCANCTRLX */
+#define _ADC_SCANCTRLX_PRSSEL_PRSCH7                       0x00000007UL                                    /**< Mode PRSCH7 for ADC_SCANCTRLX */
+#define _ADC_SCANCTRLX_PRSSEL_PRSCH8                       0x00000008UL                                    /**< Mode PRSCH8 for ADC_SCANCTRLX */
+#define _ADC_SCANCTRLX_PRSSEL_PRSCH9                       0x00000009UL                                    /**< Mode PRSCH9 for ADC_SCANCTRLX */
+#define _ADC_SCANCTRLX_PRSSEL_PRSCH10                      0x0000000AUL                                    /**< Mode PRSCH10 for ADC_SCANCTRLX */
+#define _ADC_SCANCTRLX_PRSSEL_PRSCH11                      0x0000000BUL                                    /**< Mode PRSCH11 for ADC_SCANCTRLX */
+#define ADC_SCANCTRLX_PRSSEL_DEFAULT                       (_ADC_SCANCTRLX_PRSSEL_DEFAULT << 17)           /**< Shifted mode DEFAULT for ADC_SCANCTRLX */
+#define ADC_SCANCTRLX_PRSSEL_PRSCH0                        (_ADC_SCANCTRLX_PRSSEL_PRSCH0 << 17)            /**< Shifted mode PRSCH0 for ADC_SCANCTRLX */
+#define ADC_SCANCTRLX_PRSSEL_PRSCH1                        (_ADC_SCANCTRLX_PRSSEL_PRSCH1 << 17)            /**< Shifted mode PRSCH1 for ADC_SCANCTRLX */
+#define ADC_SCANCTRLX_PRSSEL_PRSCH2                        (_ADC_SCANCTRLX_PRSSEL_PRSCH2 << 17)            /**< Shifted mode PRSCH2 for ADC_SCANCTRLX */
+#define ADC_SCANCTRLX_PRSSEL_PRSCH3                        (_ADC_SCANCTRLX_PRSSEL_PRSCH3 << 17)            /**< Shifted mode PRSCH3 for ADC_SCANCTRLX */
+#define ADC_SCANCTRLX_PRSSEL_PRSCH4                        (_ADC_SCANCTRLX_PRSSEL_PRSCH4 << 17)            /**< Shifted mode PRSCH4 for ADC_SCANCTRLX */
+#define ADC_SCANCTRLX_PRSSEL_PRSCH5                        (_ADC_SCANCTRLX_PRSSEL_PRSCH5 << 17)            /**< Shifted mode PRSCH5 for ADC_SCANCTRLX */
+#define ADC_SCANCTRLX_PRSSEL_PRSCH6                        (_ADC_SCANCTRLX_PRSSEL_PRSCH6 << 17)            /**< Shifted mode PRSCH6 for ADC_SCANCTRLX */
+#define ADC_SCANCTRLX_PRSSEL_PRSCH7                        (_ADC_SCANCTRLX_PRSSEL_PRSCH7 << 17)            /**< Shifted mode PRSCH7 for ADC_SCANCTRLX */
+#define ADC_SCANCTRLX_PRSSEL_PRSCH8                        (_ADC_SCANCTRLX_PRSSEL_PRSCH8 << 17)            /**< Shifted mode PRSCH8 for ADC_SCANCTRLX */
+#define ADC_SCANCTRLX_PRSSEL_PRSCH9                        (_ADC_SCANCTRLX_PRSSEL_PRSCH9 << 17)            /**< Shifted mode PRSCH9 for ADC_SCANCTRLX */
+#define ADC_SCANCTRLX_PRSSEL_PRSCH10                       (_ADC_SCANCTRLX_PRSSEL_PRSCH10 << 17)           /**< Shifted mode PRSCH10 for ADC_SCANCTRLX */
+#define ADC_SCANCTRLX_PRSSEL_PRSCH11                       (_ADC_SCANCTRLX_PRSSEL_PRSCH11 << 17)           /**< Shifted mode PRSCH11 for ADC_SCANCTRLX */
+#define _ADC_SCANCTRLX_CONVSTARTDELAY_SHIFT                24                                              /**< Shift value for ADC_CONVSTARTDELAY */
+#define _ADC_SCANCTRLX_CONVSTARTDELAY_MASK                 0x7000000UL                                     /**< Bit mask for ADC_CONVSTARTDELAY */
+#define _ADC_SCANCTRLX_CONVSTARTDELAY_DEFAULT              0x00000000UL                                    /**< Mode DEFAULT for ADC_SCANCTRLX */
+#define ADC_SCANCTRLX_CONVSTARTDELAY_DEFAULT               (_ADC_SCANCTRLX_CONVSTARTDELAY_DEFAULT << 24)   /**< Shifted mode DEFAULT for ADC_SCANCTRLX */
+#define ADC_SCANCTRLX_CONVSTARTDELAYEN                     (0x1UL << 27)                                   /**< Enable delaying next conversion start */
+#define _ADC_SCANCTRLX_CONVSTARTDELAYEN_SHIFT              27                                              /**< Shift value for ADC_CONVSTARTDELAYEN */
+#define _ADC_SCANCTRLX_CONVSTARTDELAYEN_MASK               0x8000000UL                                     /**< Bit mask for ADC_CONVSTARTDELAYEN */
+#define _ADC_SCANCTRLX_CONVSTARTDELAYEN_DEFAULT            0x00000000UL                                    /**< Mode DEFAULT for ADC_SCANCTRLX */
+#define ADC_SCANCTRLX_CONVSTARTDELAYEN_DEFAULT             (_ADC_SCANCTRLX_CONVSTARTDELAYEN_DEFAULT << 27) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */
+
+/* Bit fields for ADC SCANMASK */
+#define _ADC_SCANMASK_RESETVALUE                           0x00000000UL                                          /**< Default value for ADC_SCANMASK */
+#define _ADC_SCANMASK_MASK                                 0xFFFFFFFFUL                                          /**< Mask for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_SHIFT                    0                                                     /**< Shift value for ADC_SCANINPUTEN */
+#define _ADC_SCANMASK_SCANINPUTEN_MASK                     0xFFFFFFFFUL                                          /**< Bit mask for ADC_SCANINPUTEN */
+#define _ADC_SCANMASK_SCANINPUTEN_DEFAULT                  0x00000000UL                                          /**< Mode DEFAULT for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT0INPUT0NEGSEL       0x00000001UL                                          /**< Mode INPUT0INPUT0NEGSEL for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT0                   0x00000001UL                                          /**< Mode INPUT0 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT1                   0x00000002UL                                          /**< Mode INPUT1 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT1INPUT2             0x00000002UL                                          /**< Mode INPUT1INPUT2 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT2                   0x00000004UL                                          /**< Mode INPUT2 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT2INPUT2NEGSEL       0x00000004UL                                          /**< Mode INPUT2INPUT2NEGSEL for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT3                   0x00000008UL                                          /**< Mode INPUT3 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT3INPUT4             0x00000008UL                                          /**< Mode INPUT3INPUT4 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT4                   0x00000010UL                                          /**< Mode INPUT4 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT4INPUT4NEGSEL       0x00000010UL                                          /**< Mode INPUT4INPUT4NEGSEL for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT5INPUT6             0x00000020UL                                          /**< Mode INPUT5INPUT6 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT5                   0x00000020UL                                          /**< Mode INPUT5 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT6INPUT6NEGSEL       0x00000040UL                                          /**< Mode INPUT6INPUT6NEGSEL for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT6                   0x00000040UL                                          /**< Mode INPUT6 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT7                   0x00000080UL                                          /**< Mode INPUT7 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT7INPUT0             0x00000080UL                                          /**< Mode INPUT7INPUT0 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT8INPUT9             0x00000100UL                                          /**< Mode INPUT8INPUT9 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT8                   0x00000100UL                                          /**< Mode INPUT8 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT9                   0x00000200UL                                          /**< Mode INPUT9 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT9INPUT9NEGSEL       0x00000200UL                                          /**< Mode INPUT9INPUT9NEGSEL for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT10INPUT11           0x00000400UL                                          /**< Mode INPUT10INPUT11 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT10                  0x00000400UL                                          /**< Mode INPUT10 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT11INPUT11NEGSEL     0x00000800UL                                          /**< Mode INPUT11INPUT11NEGSEL for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT11                  0x00000800UL                                          /**< Mode INPUT11 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT12INPUT13           0x00001000UL                                          /**< Mode INPUT12INPUT13 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT12                  0x00001000UL                                          /**< Mode INPUT12 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT13INPUT13NEGSEL     0x00002000UL                                          /**< Mode INPUT13INPUT13NEGSEL for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT13                  0x00002000UL                                          /**< Mode INPUT13 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT14INPUT15           0x00004000UL                                          /**< Mode INPUT14INPUT15 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT14                  0x00004000UL                                          /**< Mode INPUT14 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT15INPUT15NEGSEL     0x00008000UL                                          /**< Mode INPUT15INPUT15NEGSEL for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT15                  0x00008000UL                                          /**< Mode INPUT15 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT16INPUT17           0x00010000UL                                          /**< Mode INPUT16INPUT17 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT16                  0x00010000UL                                          /**< Mode INPUT16 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT17INPUT18           0x00020000UL                                          /**< Mode INPUT17INPUT18 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT17                  0x00020000UL                                          /**< Mode INPUT17 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT18INPUT19           0x00040000UL                                          /**< Mode INPUT18INPUT19 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT18                  0x00040000UL                                          /**< Mode INPUT18 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT19                  0x00080000UL                                          /**< Mode INPUT19 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT19INPUT20           0x00080000UL                                          /**< Mode INPUT19INPUT20 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT20INPUT21           0x00100000UL                                          /**< Mode INPUT20INPUT21 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT20                  0x00100000UL                                          /**< Mode INPUT20 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT21                  0x00200000UL                                          /**< Mode INPUT21 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT21INPUT22           0x00200000UL                                          /**< Mode INPUT21INPUT22 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT22INPUT23           0x00400000UL                                          /**< Mode INPUT22INPUT23 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT22                  0x00400000UL                                          /**< Mode INPUT22 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT23INPUT16           0x00800000UL                                          /**< Mode INPUT23INPUT16 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT23                  0x00800000UL                                          /**< Mode INPUT23 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT24                  0x01000000UL                                          /**< Mode INPUT24 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT24INPUT25           0x01000000UL                                          /**< Mode INPUT24INPUT25 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT25INPUT26           0x02000000UL                                          /**< Mode INPUT25INPUT26 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT25                  0x02000000UL                                          /**< Mode INPUT25 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT26                  0x04000000UL                                          /**< Mode INPUT26 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT26INPUT27           0x04000000UL                                          /**< Mode INPUT26INPUT27 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT27INPUT28           0x08000000UL                                          /**< Mode INPUT27INPUT28 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT27                  0x08000000UL                                          /**< Mode INPUT27 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT28INPUT29           0x10000000UL                                          /**< Mode INPUT28INPUT29 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT28                  0x10000000UL                                          /**< Mode INPUT28 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT29                  0x20000000UL                                          /**< Mode INPUT29 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT29INPUT30           0x20000000UL                                          /**< Mode INPUT29INPUT30 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT30                  0x40000000UL                                          /**< Mode INPUT30 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT30INPUT31           0x40000000UL                                          /**< Mode INPUT30INPUT31 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT31INPUT24           0x80000000UL                                          /**< Mode INPUT31INPUT24 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT31                  0x80000000UL                                          /**< Mode INPUT31 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_DEFAULT                   (_ADC_SCANMASK_SCANINPUTEN_DEFAULT << 0)              /**< Shifted mode DEFAULT for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT0INPUT0NEGSEL        (_ADC_SCANMASK_SCANINPUTEN_INPUT0INPUT0NEGSEL << 0)   /**< Shifted mode INPUT0INPUT0NEGSEL for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT0                    (_ADC_SCANMASK_SCANINPUTEN_INPUT0 << 0)               /**< Shifted mode INPUT0 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT1                    (_ADC_SCANMASK_SCANINPUTEN_INPUT1 << 0)               /**< Shifted mode INPUT1 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT1INPUT2              (_ADC_SCANMASK_SCANINPUTEN_INPUT1INPUT2 << 0)         /**< Shifted mode INPUT1INPUT2 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT2                    (_ADC_SCANMASK_SCANINPUTEN_INPUT2 << 0)               /**< Shifted mode INPUT2 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT2INPUT2NEGSEL        (_ADC_SCANMASK_SCANINPUTEN_INPUT2INPUT2NEGSEL << 0)   /**< Shifted mode INPUT2INPUT2NEGSEL for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT3                    (_ADC_SCANMASK_SCANINPUTEN_INPUT3 << 0)               /**< Shifted mode INPUT3 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT3INPUT4              (_ADC_SCANMASK_SCANINPUTEN_INPUT3INPUT4 << 0)         /**< Shifted mode INPUT3INPUT4 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT4                    (_ADC_SCANMASK_SCANINPUTEN_INPUT4 << 0)               /**< Shifted mode INPUT4 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT4INPUT4NEGSEL        (_ADC_SCANMASK_SCANINPUTEN_INPUT4INPUT4NEGSEL << 0)   /**< Shifted mode INPUT4INPUT4NEGSEL for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT5INPUT6              (_ADC_SCANMASK_SCANINPUTEN_INPUT5INPUT6 << 0)         /**< Shifted mode INPUT5INPUT6 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT5                    (_ADC_SCANMASK_SCANINPUTEN_INPUT5 << 0)               /**< Shifted mode INPUT5 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT6INPUT6NEGSEL        (_ADC_SCANMASK_SCANINPUTEN_INPUT6INPUT6NEGSEL << 0)   /**< Shifted mode INPUT6INPUT6NEGSEL for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT6                    (_ADC_SCANMASK_SCANINPUTEN_INPUT6 << 0)               /**< Shifted mode INPUT6 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT7                    (_ADC_SCANMASK_SCANINPUTEN_INPUT7 << 0)               /**< Shifted mode INPUT7 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT7INPUT0              (_ADC_SCANMASK_SCANINPUTEN_INPUT7INPUT0 << 0)         /**< Shifted mode INPUT7INPUT0 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT8INPUT9              (_ADC_SCANMASK_SCANINPUTEN_INPUT8INPUT9 << 0)         /**< Shifted mode INPUT8INPUT9 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT8                    (_ADC_SCANMASK_SCANINPUTEN_INPUT8 << 0)               /**< Shifted mode INPUT8 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT9                    (_ADC_SCANMASK_SCANINPUTEN_INPUT9 << 0)               /**< Shifted mode INPUT9 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT9INPUT9NEGSEL        (_ADC_SCANMASK_SCANINPUTEN_INPUT9INPUT9NEGSEL << 0)   /**< Shifted mode INPUT9INPUT9NEGSEL for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT10INPUT11            (_ADC_SCANMASK_SCANINPUTEN_INPUT10INPUT11 << 0)       /**< Shifted mode INPUT10INPUT11 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT10                   (_ADC_SCANMASK_SCANINPUTEN_INPUT10 << 0)              /**< Shifted mode INPUT10 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT11INPUT11NEGSEL      (_ADC_SCANMASK_SCANINPUTEN_INPUT11INPUT11NEGSEL << 0) /**< Shifted mode INPUT11INPUT11NEGSEL for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT11                   (_ADC_SCANMASK_SCANINPUTEN_INPUT11 << 0)              /**< Shifted mode INPUT11 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT12INPUT13            (_ADC_SCANMASK_SCANINPUTEN_INPUT12INPUT13 << 0)       /**< Shifted mode INPUT12INPUT13 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT12                   (_ADC_SCANMASK_SCANINPUTEN_INPUT12 << 0)              /**< Shifted mode INPUT12 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT13INPUT13NEGSEL      (_ADC_SCANMASK_SCANINPUTEN_INPUT13INPUT13NEGSEL << 0) /**< Shifted mode INPUT13INPUT13NEGSEL for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT13                   (_ADC_SCANMASK_SCANINPUTEN_INPUT13 << 0)              /**< Shifted mode INPUT13 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT14INPUT15            (_ADC_SCANMASK_SCANINPUTEN_INPUT14INPUT15 << 0)       /**< Shifted mode INPUT14INPUT15 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT14                   (_ADC_SCANMASK_SCANINPUTEN_INPUT14 << 0)              /**< Shifted mode INPUT14 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT15INPUT15NEGSEL      (_ADC_SCANMASK_SCANINPUTEN_INPUT15INPUT15NEGSEL << 0) /**< Shifted mode INPUT15INPUT15NEGSEL for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT15                   (_ADC_SCANMASK_SCANINPUTEN_INPUT15 << 0)              /**< Shifted mode INPUT15 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT16INPUT17            (_ADC_SCANMASK_SCANINPUTEN_INPUT16INPUT17 << 0)       /**< Shifted mode INPUT16INPUT17 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT16                   (_ADC_SCANMASK_SCANINPUTEN_INPUT16 << 0)              /**< Shifted mode INPUT16 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT17INPUT18            (_ADC_SCANMASK_SCANINPUTEN_INPUT17INPUT18 << 0)       /**< Shifted mode INPUT17INPUT18 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT17                   (_ADC_SCANMASK_SCANINPUTEN_INPUT17 << 0)              /**< Shifted mode INPUT17 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT18INPUT19            (_ADC_SCANMASK_SCANINPUTEN_INPUT18INPUT19 << 0)       /**< Shifted mode INPUT18INPUT19 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT18                   (_ADC_SCANMASK_SCANINPUTEN_INPUT18 << 0)              /**< Shifted mode INPUT18 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT19                   (_ADC_SCANMASK_SCANINPUTEN_INPUT19 << 0)              /**< Shifted mode INPUT19 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT19INPUT20            (_ADC_SCANMASK_SCANINPUTEN_INPUT19INPUT20 << 0)       /**< Shifted mode INPUT19INPUT20 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT20INPUT21            (_ADC_SCANMASK_SCANINPUTEN_INPUT20INPUT21 << 0)       /**< Shifted mode INPUT20INPUT21 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT20                   (_ADC_SCANMASK_SCANINPUTEN_INPUT20 << 0)              /**< Shifted mode INPUT20 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT21                   (_ADC_SCANMASK_SCANINPUTEN_INPUT21 << 0)              /**< Shifted mode INPUT21 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT21INPUT22            (_ADC_SCANMASK_SCANINPUTEN_INPUT21INPUT22 << 0)       /**< Shifted mode INPUT21INPUT22 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT22INPUT23            (_ADC_SCANMASK_SCANINPUTEN_INPUT22INPUT23 << 0)       /**< Shifted mode INPUT22INPUT23 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT22                   (_ADC_SCANMASK_SCANINPUTEN_INPUT22 << 0)              /**< Shifted mode INPUT22 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT23INPUT16            (_ADC_SCANMASK_SCANINPUTEN_INPUT23INPUT16 << 0)       /**< Shifted mode INPUT23INPUT16 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT23                   (_ADC_SCANMASK_SCANINPUTEN_INPUT23 << 0)              /**< Shifted mode INPUT23 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT24                   (_ADC_SCANMASK_SCANINPUTEN_INPUT24 << 0)              /**< Shifted mode INPUT24 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT24INPUT25            (_ADC_SCANMASK_SCANINPUTEN_INPUT24INPUT25 << 0)       /**< Shifted mode INPUT24INPUT25 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT25INPUT26            (_ADC_SCANMASK_SCANINPUTEN_INPUT25INPUT26 << 0)       /**< Shifted mode INPUT25INPUT26 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT25                   (_ADC_SCANMASK_SCANINPUTEN_INPUT25 << 0)              /**< Shifted mode INPUT25 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT26                   (_ADC_SCANMASK_SCANINPUTEN_INPUT26 << 0)              /**< Shifted mode INPUT26 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT26INPUT27            (_ADC_SCANMASK_SCANINPUTEN_INPUT26INPUT27 << 0)       /**< Shifted mode INPUT26INPUT27 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT27INPUT28            (_ADC_SCANMASK_SCANINPUTEN_INPUT27INPUT28 << 0)       /**< Shifted mode INPUT27INPUT28 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT27                   (_ADC_SCANMASK_SCANINPUTEN_INPUT27 << 0)              /**< Shifted mode INPUT27 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT28INPUT29            (_ADC_SCANMASK_SCANINPUTEN_INPUT28INPUT29 << 0)       /**< Shifted mode INPUT28INPUT29 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT28                   (_ADC_SCANMASK_SCANINPUTEN_INPUT28 << 0)              /**< Shifted mode INPUT28 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT29                   (_ADC_SCANMASK_SCANINPUTEN_INPUT29 << 0)              /**< Shifted mode INPUT29 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT29INPUT30            (_ADC_SCANMASK_SCANINPUTEN_INPUT29INPUT30 << 0)       /**< Shifted mode INPUT29INPUT30 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT30                   (_ADC_SCANMASK_SCANINPUTEN_INPUT30 << 0)              /**< Shifted mode INPUT30 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT30INPUT31            (_ADC_SCANMASK_SCANINPUTEN_INPUT30INPUT31 << 0)       /**< Shifted mode INPUT30INPUT31 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT31INPUT24            (_ADC_SCANMASK_SCANINPUTEN_INPUT31INPUT24 << 0)       /**< Shifted mode INPUT31INPUT24 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT31                   (_ADC_SCANMASK_SCANINPUTEN_INPUT31 << 0)              /**< Shifted mode INPUT31 for ADC_SCANMASK */
+
+/* Bit fields for ADC SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_RESETVALUE                       0x00000000UL                                            /**< Default value for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_MASK                             0x1F1F1F1FUL                                            /**< Mask for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_SHIFT               0                                                       /**< Shift value for ADC_INPUT0TO7SEL */
+#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_MASK                0x1FUL                                                  /**< Bit mask for ADC_INPUT0TO7SEL */
+#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_DEFAULT             0x00000000UL                                            /**< Mode DEFAULT for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT0CH0TO7        0x00000000UL                                            /**< Mode APORT0CH0TO7 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT0CH8TO15       0x00000001UL                                            /**< Mode APORT0CH8TO15 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH0TO7        0x00000004UL                                            /**< Mode APORT1CH0TO7 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH8TO15       0x00000005UL                                            /**< Mode APORT1CH8TO15 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH16TO23      0x00000006UL                                            /**< Mode APORT1CH16TO23 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH24TO31      0x00000007UL                                            /**< Mode APORT1CH24TO31 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH0TO7        0x00000008UL                                            /**< Mode APORT2CH0TO7 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH8TO15       0x00000009UL                                            /**< Mode APORT2CH8TO15 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH16TO23      0x0000000AUL                                            /**< Mode APORT2CH16TO23 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH24TO31      0x0000000BUL                                            /**< Mode APORT2CH24TO31 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH0TO7        0x0000000CUL                                            /**< Mode APORT3CH0TO7 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH8TO15       0x0000000DUL                                            /**< Mode APORT3CH8TO15 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH16TO23      0x0000000EUL                                            /**< Mode APORT3CH16TO23 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH24TO31      0x0000000FUL                                            /**< Mode APORT3CH24TO31 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH0TO7        0x00000010UL                                            /**< Mode APORT4CH0TO7 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH8TO15       0x00000011UL                                            /**< Mode APORT4CH8TO15 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH16TO23      0x00000012UL                                            /**< Mode APORT4CH16TO23 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH24TO31      0x00000013UL                                            /**< Mode APORT4CH24TO31 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT0TO7SEL_DEFAULT              (_ADC_SCANINPUTSEL_INPUT0TO7SEL_DEFAULT << 0)           /**< Shifted mode DEFAULT for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT0CH0TO7         (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT0CH0TO7 << 0)      /**< Shifted mode APORT0CH0TO7 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT0CH8TO15        (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT0CH8TO15 << 0)     /**< Shifted mode APORT0CH8TO15 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH0TO7         (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH0TO7 << 0)      /**< Shifted mode APORT1CH0TO7 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH8TO15        (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH8TO15 << 0)     /**< Shifted mode APORT1CH8TO15 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH16TO23       (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH16TO23 << 0)    /**< Shifted mode APORT1CH16TO23 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH24TO31       (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH24TO31 << 0)    /**< Shifted mode APORT1CH24TO31 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH0TO7         (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH0TO7 << 0)      /**< Shifted mode APORT2CH0TO7 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH8TO15        (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH8TO15 << 0)     /**< Shifted mode APORT2CH8TO15 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH16TO23       (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH16TO23 << 0)    /**< Shifted mode APORT2CH16TO23 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH24TO31       (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH24TO31 << 0)    /**< Shifted mode APORT2CH24TO31 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH0TO7         (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH0TO7 << 0)      /**< Shifted mode APORT3CH0TO7 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH8TO15        (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH8TO15 << 0)     /**< Shifted mode APORT3CH8TO15 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH16TO23       (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH16TO23 << 0)    /**< Shifted mode APORT3CH16TO23 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH24TO31       (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH24TO31 << 0)    /**< Shifted mode APORT3CH24TO31 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH0TO7         (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH0TO7 << 0)      /**< Shifted mode APORT4CH0TO7 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH8TO15        (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH8TO15 << 0)     /**< Shifted mode APORT4CH8TO15 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH16TO23       (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH16TO23 << 0)    /**< Shifted mode APORT4CH16TO23 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH24TO31       (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH24TO31 << 0)    /**< Shifted mode APORT4CH24TO31 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_SHIFT              8                                                       /**< Shift value for ADC_INPUT8TO15SEL */
+#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_MASK               0x1F00UL                                                /**< Bit mask for ADC_INPUT8TO15SEL */
+#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_DEFAULT            0x00000000UL                                            /**< Mode DEFAULT for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT0CH0TO7       0x00000000UL                                            /**< Mode APORT0CH0TO7 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT0CH8TO15      0x00000001UL                                            /**< Mode APORT0CH8TO15 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH0TO7       0x00000004UL                                            /**< Mode APORT1CH0TO7 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH8TO15      0x00000005UL                                            /**< Mode APORT1CH8TO15 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH16TO23     0x00000006UL                                            /**< Mode APORT1CH16TO23 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH24TO31     0x00000007UL                                            /**< Mode APORT1CH24TO31 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH0TO7       0x00000008UL                                            /**< Mode APORT2CH0TO7 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH8TO15      0x00000009UL                                            /**< Mode APORT2CH8TO15 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH16TO23     0x0000000AUL                                            /**< Mode APORT2CH16TO23 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH24TO31     0x0000000BUL                                            /**< Mode APORT2CH24TO31 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH0TO7       0x0000000CUL                                            /**< Mode APORT3CH0TO7 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH8TO15      0x0000000DUL                                            /**< Mode APORT3CH8TO15 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH16TO23     0x0000000EUL                                            /**< Mode APORT3CH16TO23 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH24TO31     0x0000000FUL                                            /**< Mode APORT3CH24TO31 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH0TO7       0x00000010UL                                            /**< Mode APORT4CH0TO7 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH8TO15      0x00000011UL                                            /**< Mode APORT4CH8TO15 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH16TO23     0x00000012UL                                            /**< Mode APORT4CH16TO23 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH24TO31     0x00000013UL                                            /**< Mode APORT4CH24TO31 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT8TO15SEL_DEFAULT             (_ADC_SCANINPUTSEL_INPUT8TO15SEL_DEFAULT << 8)          /**< Shifted mode DEFAULT for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT0CH0TO7        (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT0CH0TO7 << 8)     /**< Shifted mode APORT0CH0TO7 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT0CH8TO15       (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT0CH8TO15 << 8)    /**< Shifted mode APORT0CH8TO15 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH0TO7        (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH0TO7 << 8)     /**< Shifted mode APORT1CH0TO7 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH8TO15       (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH8TO15 << 8)    /**< Shifted mode APORT1CH8TO15 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH16TO23      (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH16TO23 << 8)   /**< Shifted mode APORT1CH16TO23 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH24TO31      (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH24TO31 << 8)   /**< Shifted mode APORT1CH24TO31 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH0TO7        (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH0TO7 << 8)     /**< Shifted mode APORT2CH0TO7 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH8TO15       (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH8TO15 << 8)    /**< Shifted mode APORT2CH8TO15 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH16TO23      (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH16TO23 << 8)   /**< Shifted mode APORT2CH16TO23 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH24TO31      (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH24TO31 << 8)   /**< Shifted mode APORT2CH24TO31 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH0TO7        (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH0TO7 << 8)     /**< Shifted mode APORT3CH0TO7 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH8TO15       (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH8TO15 << 8)    /**< Shifted mode APORT3CH8TO15 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH16TO23      (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH16TO23 << 8)   /**< Shifted mode APORT3CH16TO23 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH24TO31      (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH24TO31 << 8)   /**< Shifted mode APORT3CH24TO31 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH0TO7        (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH0TO7 << 8)     /**< Shifted mode APORT4CH0TO7 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH8TO15       (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH8TO15 << 8)    /**< Shifted mode APORT4CH8TO15 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH16TO23      (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH16TO23 << 8)   /**< Shifted mode APORT4CH16TO23 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH24TO31      (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH24TO31 << 8)   /**< Shifted mode APORT4CH24TO31 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_SHIFT             16                                                      /**< Shift value for ADC_INPUT16TO23SEL */
+#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_MASK              0x1F0000UL                                              /**< Bit mask for ADC_INPUT16TO23SEL */
+#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_DEFAULT           0x00000000UL                                            /**< Mode DEFAULT for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT0CH0TO7      0x00000000UL                                            /**< Mode APORT0CH0TO7 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT0CH8TO15     0x00000001UL                                            /**< Mode APORT0CH8TO15 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH0TO7      0x00000004UL                                            /**< Mode APORT1CH0TO7 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH8TO15     0x00000005UL                                            /**< Mode APORT1CH8TO15 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH16TO23    0x00000006UL                                            /**< Mode APORT1CH16TO23 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH24TO31    0x00000007UL                                            /**< Mode APORT1CH24TO31 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH0TO7      0x00000008UL                                            /**< Mode APORT2CH0TO7 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH8TO15     0x00000009UL                                            /**< Mode APORT2CH8TO15 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH16TO23    0x0000000AUL                                            /**< Mode APORT2CH16TO23 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH24TO31    0x0000000BUL                                            /**< Mode APORT2CH24TO31 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH0TO7      0x0000000CUL                                            /**< Mode APORT3CH0TO7 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH8TO15     0x0000000DUL                                            /**< Mode APORT3CH8TO15 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH16TO23    0x0000000EUL                                            /**< Mode APORT3CH16TO23 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH24TO31    0x0000000FUL                                            /**< Mode APORT3CH24TO31 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH0TO7      0x00000010UL                                            /**< Mode APORT4CH0TO7 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH8TO15     0x00000011UL                                            /**< Mode APORT4CH8TO15 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH16TO23    0x00000012UL                                            /**< Mode APORT4CH16TO23 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH24TO31    0x00000013UL                                            /**< Mode APORT4CH24TO31 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT16TO23SEL_DEFAULT            (_ADC_SCANINPUTSEL_INPUT16TO23SEL_DEFAULT << 16)        /**< Shifted mode DEFAULT for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT0CH0TO7       (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT0CH0TO7 << 16)   /**< Shifted mode APORT0CH0TO7 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT0CH8TO15      (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT0CH8TO15 << 16)  /**< Shifted mode APORT0CH8TO15 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH0TO7       (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH0TO7 << 16)   /**< Shifted mode APORT1CH0TO7 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH8TO15      (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH8TO15 << 16)  /**< Shifted mode APORT1CH8TO15 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH16TO23     (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH16TO23 << 16) /**< Shifted mode APORT1CH16TO23 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH24TO31     (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH24TO31 << 16) /**< Shifted mode APORT1CH24TO31 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH0TO7       (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH0TO7 << 16)   /**< Shifted mode APORT2CH0TO7 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH8TO15      (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH8TO15 << 16)  /**< Shifted mode APORT2CH8TO15 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH16TO23     (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH16TO23 << 16) /**< Shifted mode APORT2CH16TO23 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH24TO31     (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH24TO31 << 16) /**< Shifted mode APORT2CH24TO31 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH0TO7       (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH0TO7 << 16)   /**< Shifted mode APORT3CH0TO7 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH8TO15      (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH8TO15 << 16)  /**< Shifted mode APORT3CH8TO15 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH16TO23     (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH16TO23 << 16) /**< Shifted mode APORT3CH16TO23 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH24TO31     (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH24TO31 << 16) /**< Shifted mode APORT3CH24TO31 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH0TO7       (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH0TO7 << 16)   /**< Shifted mode APORT4CH0TO7 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH8TO15      (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH8TO15 << 16)  /**< Shifted mode APORT4CH8TO15 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH16TO23     (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH16TO23 << 16) /**< Shifted mode APORT4CH16TO23 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH24TO31     (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH24TO31 << 16) /**< Shifted mode APORT4CH24TO31 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_SHIFT             24                                                      /**< Shift value for ADC_INPUT24TO31SEL */
+#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_MASK              0x1F000000UL                                            /**< Bit mask for ADC_INPUT24TO31SEL */
+#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_DEFAULT           0x00000000UL                                            /**< Mode DEFAULT for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT0CH0TO7      0x00000000UL                                            /**< Mode APORT0CH0TO7 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT0CH8TO15     0x00000001UL                                            /**< Mode APORT0CH8TO15 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH0TO7      0x00000004UL                                            /**< Mode APORT1CH0TO7 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH8TO15     0x00000005UL                                            /**< Mode APORT1CH8TO15 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH16TO23    0x00000006UL                                            /**< Mode APORT1CH16TO23 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH24TO31    0x00000007UL                                            /**< Mode APORT1CH24TO31 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH0TO7      0x00000008UL                                            /**< Mode APORT2CH0TO7 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH8TO15     0x00000009UL                                            /**< Mode APORT2CH8TO15 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH16TO23    0x0000000AUL                                            /**< Mode APORT2CH16TO23 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH24TO31    0x0000000BUL                                            /**< Mode APORT2CH24TO31 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH0TO7      0x0000000CUL                                            /**< Mode APORT3CH0TO7 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH8TO15     0x0000000DUL                                            /**< Mode APORT3CH8TO15 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH16TO23    0x0000000EUL                                            /**< Mode APORT3CH16TO23 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH24TO31    0x0000000FUL                                            /**< Mode APORT3CH24TO31 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH0TO7      0x00000010UL                                            /**< Mode APORT4CH0TO7 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH8TO15     0x00000011UL                                            /**< Mode APORT4CH8TO15 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH16TO23    0x00000012UL                                            /**< Mode APORT4CH16TO23 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH24TO31    0x00000013UL                                            /**< Mode APORT4CH24TO31 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT24TO31SEL_DEFAULT            (_ADC_SCANINPUTSEL_INPUT24TO31SEL_DEFAULT << 24)        /**< Shifted mode DEFAULT for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT0CH0TO7       (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT0CH0TO7 << 24)   /**< Shifted mode APORT0CH0TO7 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT0CH8TO15      (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT0CH8TO15 << 24)  /**< Shifted mode APORT0CH8TO15 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH0TO7       (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH0TO7 << 24)   /**< Shifted mode APORT1CH0TO7 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH8TO15      (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH8TO15 << 24)  /**< Shifted mode APORT1CH8TO15 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH16TO23     (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH16TO23 << 24) /**< Shifted mode APORT1CH16TO23 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH24TO31     (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH24TO31 << 24) /**< Shifted mode APORT1CH24TO31 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH0TO7       (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH0TO7 << 24)   /**< Shifted mode APORT2CH0TO7 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH8TO15      (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH8TO15 << 24)  /**< Shifted mode APORT2CH8TO15 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH16TO23     (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH16TO23 << 24) /**< Shifted mode APORT2CH16TO23 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH24TO31     (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH24TO31 << 24) /**< Shifted mode APORT2CH24TO31 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH0TO7       (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH0TO7 << 24)   /**< Shifted mode APORT3CH0TO7 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH8TO15      (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH8TO15 << 24)  /**< Shifted mode APORT3CH8TO15 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH16TO23     (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH16TO23 << 24) /**< Shifted mode APORT3CH16TO23 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH24TO31     (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH24TO31 << 24) /**< Shifted mode APORT3CH24TO31 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH0TO7       (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH0TO7 << 24)   /**< Shifted mode APORT4CH0TO7 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH8TO15      (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH8TO15 << 24)  /**< Shifted mode APORT4CH8TO15 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH16TO23     (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH16TO23 << 24) /**< Shifted mode APORT4CH16TO23 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH24TO31     (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH24TO31 << 24) /**< Shifted mode APORT4CH24TO31 for ADC_SCANINPUTSEL */
+
+/* Bit fields for ADC SCANNEGSEL */
+#define _ADC_SCANNEGSEL_RESETVALUE                         0x000039E4UL                                  /**< Default value for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_MASK                               0x0000FFFFUL                                  /**< Mask for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT0NEGSEL_SHIFT                 0                                             /**< Shift value for ADC_INPUT0NEGSEL */
+#define _ADC_SCANNEGSEL_INPUT0NEGSEL_MASK                  0x3UL                                         /**< Bit mask for ADC_INPUT0NEGSEL */
+#define _ADC_SCANNEGSEL_INPUT0NEGSEL_DEFAULT               0x00000000UL                                  /**< Mode DEFAULT for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT1                0x00000000UL                                  /**< Mode INPUT1 for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT3                0x00000001UL                                  /**< Mode INPUT3 for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT5                0x00000002UL                                  /**< Mode INPUT5 for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT7                0x00000003UL                                  /**< Mode INPUT7 for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT0NEGSEL_DEFAULT                (_ADC_SCANNEGSEL_INPUT0NEGSEL_DEFAULT << 0)   /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT1                 (_ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT1 << 0)    /**< Shifted mode INPUT1 for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT3                 (_ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT3 << 0)    /**< Shifted mode INPUT3 for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT5                 (_ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT5 << 0)    /**< Shifted mode INPUT5 for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT7                 (_ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT7 << 0)    /**< Shifted mode INPUT7 for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT2NEGSEL_SHIFT                 2                                             /**< Shift value for ADC_INPUT2NEGSEL */
+#define _ADC_SCANNEGSEL_INPUT2NEGSEL_MASK                  0xCUL                                         /**< Bit mask for ADC_INPUT2NEGSEL */
+#define _ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT1                0x00000000UL                                  /**< Mode INPUT1 for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT2NEGSEL_DEFAULT               0x00000001UL                                  /**< Mode DEFAULT for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT3                0x00000001UL                                  /**< Mode INPUT3 for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT5                0x00000002UL                                  /**< Mode INPUT5 for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT7                0x00000003UL                                  /**< Mode INPUT7 for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT1                 (_ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT1 << 2)    /**< Shifted mode INPUT1 for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT2NEGSEL_DEFAULT                (_ADC_SCANNEGSEL_INPUT2NEGSEL_DEFAULT << 2)   /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT3                 (_ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT3 << 2)    /**< Shifted mode INPUT3 for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT5                 (_ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT5 << 2)    /**< Shifted mode INPUT5 for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT7                 (_ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT7 << 2)    /**< Shifted mode INPUT7 for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT4NEGSEL_SHIFT                 4                                             /**< Shift value for ADC_INPUT4NEGSEL */
+#define _ADC_SCANNEGSEL_INPUT4NEGSEL_MASK                  0x30UL                                        /**< Bit mask for ADC_INPUT4NEGSEL */
+#define _ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT1                0x00000000UL                                  /**< Mode INPUT1 for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT3                0x00000001UL                                  /**< Mode INPUT3 for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT4NEGSEL_DEFAULT               0x00000002UL                                  /**< Mode DEFAULT for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT5                0x00000002UL                                  /**< Mode INPUT5 for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT7                0x00000003UL                                  /**< Mode INPUT7 for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT1                 (_ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT1 << 4)    /**< Shifted mode INPUT1 for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT3                 (_ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT3 << 4)    /**< Shifted mode INPUT3 for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT4NEGSEL_DEFAULT                (_ADC_SCANNEGSEL_INPUT4NEGSEL_DEFAULT << 4)   /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT5                 (_ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT5 << 4)    /**< Shifted mode INPUT5 for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT7                 (_ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT7 << 4)    /**< Shifted mode INPUT7 for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT6NEGSEL_SHIFT                 6                                             /**< Shift value for ADC_INPUT6NEGSEL */
+#define _ADC_SCANNEGSEL_INPUT6NEGSEL_MASK                  0xC0UL                                        /**< Bit mask for ADC_INPUT6NEGSEL */
+#define _ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT1                0x00000000UL                                  /**< Mode INPUT1 for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT3                0x00000001UL                                  /**< Mode INPUT3 for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT5                0x00000002UL                                  /**< Mode INPUT5 for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT6NEGSEL_DEFAULT               0x00000003UL                                  /**< Mode DEFAULT for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT7                0x00000003UL                                  /**< Mode INPUT7 for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT1                 (_ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT1 << 6)    /**< Shifted mode INPUT1 for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT3                 (_ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT3 << 6)    /**< Shifted mode INPUT3 for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT5                 (_ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT5 << 6)    /**< Shifted mode INPUT5 for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT6NEGSEL_DEFAULT                (_ADC_SCANNEGSEL_INPUT6NEGSEL_DEFAULT << 6)   /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT7                 (_ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT7 << 6)    /**< Shifted mode INPUT7 for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT9NEGSEL_SHIFT                 8                                             /**< Shift value for ADC_INPUT9NEGSEL */
+#define _ADC_SCANNEGSEL_INPUT9NEGSEL_MASK                  0x300UL                                       /**< Bit mask for ADC_INPUT9NEGSEL */
+#define _ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT8                0x00000000UL                                  /**< Mode INPUT8 for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT9NEGSEL_DEFAULT               0x00000001UL                                  /**< Mode DEFAULT for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT10               0x00000001UL                                  /**< Mode INPUT10 for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT12               0x00000002UL                                  /**< Mode INPUT12 for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT14               0x00000003UL                                  /**< Mode INPUT14 for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT8                 (_ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT8 << 8)    /**< Shifted mode INPUT8 for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT9NEGSEL_DEFAULT                (_ADC_SCANNEGSEL_INPUT9NEGSEL_DEFAULT << 8)   /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT10                (_ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT10 << 8)   /**< Shifted mode INPUT10 for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT12                (_ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT12 << 8)   /**< Shifted mode INPUT12 for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT14                (_ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT14 << 8)   /**< Shifted mode INPUT14 for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT11NEGSEL_SHIFT                10                                            /**< Shift value for ADC_INPUT11NEGSEL */
+#define _ADC_SCANNEGSEL_INPUT11NEGSEL_MASK                 0xC00UL                                       /**< Bit mask for ADC_INPUT11NEGSEL */
+#define _ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT8               0x00000000UL                                  /**< Mode INPUT8 for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT10              0x00000001UL                                  /**< Mode INPUT10 for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT11NEGSEL_DEFAULT              0x00000002UL                                  /**< Mode DEFAULT for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT12              0x00000002UL                                  /**< Mode INPUT12 for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT14              0x00000003UL                                  /**< Mode INPUT14 for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT8                (_ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT8 << 10)  /**< Shifted mode INPUT8 for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT10               (_ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT10 << 10) /**< Shifted mode INPUT10 for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT11NEGSEL_DEFAULT               (_ADC_SCANNEGSEL_INPUT11NEGSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT12               (_ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT12 << 10) /**< Shifted mode INPUT12 for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT14               (_ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT14 << 10) /**< Shifted mode INPUT14 for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT13NEGSEL_SHIFT                12                                            /**< Shift value for ADC_INPUT13NEGSEL */
+#define _ADC_SCANNEGSEL_INPUT13NEGSEL_MASK                 0x3000UL                                      /**< Bit mask for ADC_INPUT13NEGSEL */
+#define _ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT8               0x00000000UL                                  /**< Mode INPUT8 for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT10              0x00000001UL                                  /**< Mode INPUT10 for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT12              0x00000002UL                                  /**< Mode INPUT12 for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT13NEGSEL_DEFAULT              0x00000003UL                                  /**< Mode DEFAULT for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT14              0x00000003UL                                  /**< Mode INPUT14 for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT8                (_ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT8 << 12)  /**< Shifted mode INPUT8 for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT10               (_ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT10 << 12) /**< Shifted mode INPUT10 for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT12               (_ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT12 << 12) /**< Shifted mode INPUT12 for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT13NEGSEL_DEFAULT               (_ADC_SCANNEGSEL_INPUT13NEGSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT14               (_ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT14 << 12) /**< Shifted mode INPUT14 for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT15NEGSEL_SHIFT                14                                            /**< Shift value for ADC_INPUT15NEGSEL */
+#define _ADC_SCANNEGSEL_INPUT15NEGSEL_MASK                 0xC000UL                                      /**< Bit mask for ADC_INPUT15NEGSEL */
+#define _ADC_SCANNEGSEL_INPUT15NEGSEL_DEFAULT              0x00000000UL                                  /**< Mode DEFAULT for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT8               0x00000000UL                                  /**< Mode INPUT8 for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT10              0x00000001UL                                  /**< Mode INPUT10 for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT12              0x00000002UL                                  /**< Mode INPUT12 for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT14              0x00000003UL                                  /**< Mode INPUT14 for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT15NEGSEL_DEFAULT               (_ADC_SCANNEGSEL_INPUT15NEGSEL_DEFAULT << 14) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT8                (_ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT8 << 14)  /**< Shifted mode INPUT8 for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT10               (_ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT10 << 14) /**< Shifted mode INPUT10 for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT12               (_ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT12 << 14) /**< Shifted mode INPUT12 for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT14               (_ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT14 << 14) /**< Shifted mode INPUT14 for ADC_SCANNEGSEL */
+
+/* Bit fields for ADC CMPTHR */
+#define _ADC_CMPTHR_RESETVALUE                             0x00000000UL                     /**< Default value for ADC_CMPTHR */
+#define _ADC_CMPTHR_MASK                                   0xFFFFFFFFUL                     /**< Mask for ADC_CMPTHR */
+#define _ADC_CMPTHR_ADLT_SHIFT                             0                                /**< Shift value for ADC_ADLT */
+#define _ADC_CMPTHR_ADLT_MASK                              0xFFFFUL                         /**< Bit mask for ADC_ADLT */
+#define _ADC_CMPTHR_ADLT_DEFAULT                           0x00000000UL                     /**< Mode DEFAULT for ADC_CMPTHR */
+#define ADC_CMPTHR_ADLT_DEFAULT                            (_ADC_CMPTHR_ADLT_DEFAULT << 0)  /**< Shifted mode DEFAULT for ADC_CMPTHR */
+#define _ADC_CMPTHR_ADGT_SHIFT                             16                               /**< Shift value for ADC_ADGT */
+#define _ADC_CMPTHR_ADGT_MASK                              0xFFFF0000UL                     /**< Bit mask for ADC_ADGT */
+#define _ADC_CMPTHR_ADGT_DEFAULT                           0x00000000UL                     /**< Mode DEFAULT for ADC_CMPTHR */
+#define ADC_CMPTHR_ADGT_DEFAULT                            (_ADC_CMPTHR_ADGT_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_CMPTHR */
+
+/* Bit fields for ADC BIASPROG */
+#define _ADC_BIASPROG_RESETVALUE                           0x00000000UL                             /**< Default value for ADC_BIASPROG */
+#define _ADC_BIASPROG_MASK                                 0x0000100FUL                             /**< Mask for ADC_BIASPROG */
+#define _ADC_BIASPROG_ADCBIASPROG_SHIFT                    0                                        /**< Shift value for ADC_ADCBIASPROG */
+#define _ADC_BIASPROG_ADCBIASPROG_MASK                     0xFUL                                    /**< Bit mask for ADC_ADCBIASPROG */
+#define _ADC_BIASPROG_ADCBIASPROG_DEFAULT                  0x00000000UL                             /**< Mode DEFAULT for ADC_BIASPROG */
+#define _ADC_BIASPROG_ADCBIASPROG_NORMAL                   0x00000000UL                             /**< Mode NORMAL for ADC_BIASPROG */
+#define _ADC_BIASPROG_ADCBIASPROG_SCALE2                   0x00000004UL                             /**< Mode SCALE2 for ADC_BIASPROG */
+#define _ADC_BIASPROG_ADCBIASPROG_SCALE4                   0x00000008UL                             /**< Mode SCALE4 for ADC_BIASPROG */
+#define _ADC_BIASPROG_ADCBIASPROG_SCALE8                   0x0000000CUL                             /**< Mode SCALE8 for ADC_BIASPROG */
+#define _ADC_BIASPROG_ADCBIASPROG_SCALE16                  0x0000000EUL                             /**< Mode SCALE16 for ADC_BIASPROG */
+#define _ADC_BIASPROG_ADCBIASPROG_SCALE32                  0x0000000FUL                             /**< Mode SCALE32 for ADC_BIASPROG */
+#define ADC_BIASPROG_ADCBIASPROG_DEFAULT                   (_ADC_BIASPROG_ADCBIASPROG_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_BIASPROG */
+#define ADC_BIASPROG_ADCBIASPROG_NORMAL                    (_ADC_BIASPROG_ADCBIASPROG_NORMAL << 0)  /**< Shifted mode NORMAL for ADC_BIASPROG */
+#define ADC_BIASPROG_ADCBIASPROG_SCALE2                    (_ADC_BIASPROG_ADCBIASPROG_SCALE2 << 0)  /**< Shifted mode SCALE2 for ADC_BIASPROG */
+#define ADC_BIASPROG_ADCBIASPROG_SCALE4                    (_ADC_BIASPROG_ADCBIASPROG_SCALE4 << 0)  /**< Shifted mode SCALE4 for ADC_BIASPROG */
+#define ADC_BIASPROG_ADCBIASPROG_SCALE8                    (_ADC_BIASPROG_ADCBIASPROG_SCALE8 << 0)  /**< Shifted mode SCALE8 for ADC_BIASPROG */
+#define ADC_BIASPROG_ADCBIASPROG_SCALE16                   (_ADC_BIASPROG_ADCBIASPROG_SCALE16 << 0) /**< Shifted mode SCALE16 for ADC_BIASPROG */
+#define ADC_BIASPROG_ADCBIASPROG_SCALE32                   (_ADC_BIASPROG_ADCBIASPROG_SCALE32 << 0) /**< Shifted mode SCALE32 for ADC_BIASPROG */
+#define ADC_BIASPROG_VFAULTCLR                             (0x1UL << 12)                            /**< Set Vfault_clr flag */
+#define _ADC_BIASPROG_VFAULTCLR_SHIFT                      12                                       /**< Shift value for ADC_VFAULTCLR */
+#define _ADC_BIASPROG_VFAULTCLR_MASK                       0x1000UL                                 /**< Bit mask for ADC_VFAULTCLR */
+#define _ADC_BIASPROG_VFAULTCLR_DEFAULT                    0x00000000UL                             /**< Mode DEFAULT for ADC_BIASPROG */
+#define ADC_BIASPROG_VFAULTCLR_DEFAULT                     (_ADC_BIASPROG_VFAULTCLR_DEFAULT << 12)  /**< Shifted mode DEFAULT for ADC_BIASPROG */
+
+/* Bit fields for ADC CAL */
+#define _ADC_CAL_RESETVALUE                                0x40784078UL                            /**< Default value for ADC_CAL */
+#define _ADC_CAL_MASK                                      0xFFFFFFFFUL                            /**< Mask for ADC_CAL */
+#define _ADC_CAL_SINGLEOFFSET_SHIFT                        0                                       /**< Shift value for ADC_SINGLEOFFSET */
+#define _ADC_CAL_SINGLEOFFSET_MASK                         0xFUL                                   /**< Bit mask for ADC_SINGLEOFFSET */
+#define _ADC_CAL_SINGLEOFFSET_DEFAULT                      0x00000008UL                            /**< Mode DEFAULT for ADC_CAL */
+#define ADC_CAL_SINGLEOFFSET_DEFAULT                       (_ADC_CAL_SINGLEOFFSET_DEFAULT << 0)    /**< Shifted mode DEFAULT for ADC_CAL */
+#define _ADC_CAL_SINGLEOFFSETINV_SHIFT                     4                                       /**< Shift value for ADC_SINGLEOFFSETINV */
+#define _ADC_CAL_SINGLEOFFSETINV_MASK                      0xF0UL                                  /**< Bit mask for ADC_SINGLEOFFSETINV */
+#define _ADC_CAL_SINGLEOFFSETINV_DEFAULT                   0x00000007UL                            /**< Mode DEFAULT for ADC_CAL */
+#define ADC_CAL_SINGLEOFFSETINV_DEFAULT                    (_ADC_CAL_SINGLEOFFSETINV_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_CAL */
+#define _ADC_CAL_SINGLEGAIN_SHIFT                          8                                       /**< Shift value for ADC_SINGLEGAIN */
+#define _ADC_CAL_SINGLEGAIN_MASK                           0x7F00UL                                /**< Bit mask for ADC_SINGLEGAIN */
+#define _ADC_CAL_SINGLEGAIN_DEFAULT                        0x00000040UL                            /**< Mode DEFAULT for ADC_CAL */
+#define ADC_CAL_SINGLEGAIN_DEFAULT                         (_ADC_CAL_SINGLEGAIN_DEFAULT << 8)      /**< Shifted mode DEFAULT for ADC_CAL */
+#define ADC_CAL_OFFSETINVMODE                              (0x1UL << 15)                           /**< Negative single-ended offset calibration is enabled */
+#define _ADC_CAL_OFFSETINVMODE_SHIFT                       15                                      /**< Shift value for ADC_OFFSETINVMODE */
+#define _ADC_CAL_OFFSETINVMODE_MASK                        0x8000UL                                /**< Bit mask for ADC_OFFSETINVMODE */
+#define _ADC_CAL_OFFSETINVMODE_DEFAULT                     0x00000000UL                            /**< Mode DEFAULT for ADC_CAL */
+#define ADC_CAL_OFFSETINVMODE_DEFAULT                      (_ADC_CAL_OFFSETINVMODE_DEFAULT << 15)  /**< Shifted mode DEFAULT for ADC_CAL */
+#define _ADC_CAL_SCANOFFSET_SHIFT                          16                                      /**< Shift value for ADC_SCANOFFSET */
+#define _ADC_CAL_SCANOFFSET_MASK                           0xF0000UL                               /**< Bit mask for ADC_SCANOFFSET */
+#define _ADC_CAL_SCANOFFSET_DEFAULT                        0x00000008UL                            /**< Mode DEFAULT for ADC_CAL */
+#define ADC_CAL_SCANOFFSET_DEFAULT                         (_ADC_CAL_SCANOFFSET_DEFAULT << 16)     /**< Shifted mode DEFAULT for ADC_CAL */
+#define _ADC_CAL_SCANOFFSETINV_SHIFT                       20                                      /**< Shift value for ADC_SCANOFFSETINV */
+#define _ADC_CAL_SCANOFFSETINV_MASK                        0xF00000UL                              /**< Bit mask for ADC_SCANOFFSETINV */
+#define _ADC_CAL_SCANOFFSETINV_DEFAULT                     0x00000007UL                            /**< Mode DEFAULT for ADC_CAL */
+#define ADC_CAL_SCANOFFSETINV_DEFAULT                      (_ADC_CAL_SCANOFFSETINV_DEFAULT << 20)  /**< Shifted mode DEFAULT for ADC_CAL */
+#define _ADC_CAL_SCANGAIN_SHIFT                            24                                      /**< Shift value for ADC_SCANGAIN */
+#define _ADC_CAL_SCANGAIN_MASK                             0x7F000000UL                            /**< Bit mask for ADC_SCANGAIN */
+#define _ADC_CAL_SCANGAIN_DEFAULT                          0x00000040UL                            /**< Mode DEFAULT for ADC_CAL */
+#define ADC_CAL_SCANGAIN_DEFAULT                           (_ADC_CAL_SCANGAIN_DEFAULT << 24)       /**< Shifted mode DEFAULT for ADC_CAL */
+#define ADC_CAL_CALEN                                      (0x1UL << 31)                           /**< Calibration mode is enabled */
+#define _ADC_CAL_CALEN_SHIFT                               31                                      /**< Shift value for ADC_CALEN */
+#define _ADC_CAL_CALEN_MASK                                0x80000000UL                            /**< Bit mask for ADC_CALEN */
+#define _ADC_CAL_CALEN_DEFAULT                             0x00000000UL                            /**< Mode DEFAULT for ADC_CAL */
+#define ADC_CAL_CALEN_DEFAULT                              (_ADC_CAL_CALEN_DEFAULT << 31)          /**< Shifted mode DEFAULT for ADC_CAL */
+
+/* Bit fields for ADC IF */
+#define _ADC_IF_RESETVALUE                                 0x00000000UL                      /**< Default value for ADC_IF */
+#define _ADC_IF_MASK                                       0x03030F03UL                      /**< Mask for ADC_IF */
+#define ADC_IF_SINGLE                                      (0x1UL << 0)                      /**< Single Conversion Complete Interrupt Flag */
+#define _ADC_IF_SINGLE_SHIFT                               0                                 /**< Shift value for ADC_SINGLE */
+#define _ADC_IF_SINGLE_MASK                                0x1UL                             /**< Bit mask for ADC_SINGLE */
+#define _ADC_IF_SINGLE_DEFAULT                             0x00000000UL                      /**< Mode DEFAULT for ADC_IF */
+#define ADC_IF_SINGLE_DEFAULT                              (_ADC_IF_SINGLE_DEFAULT << 0)     /**< Shifted mode DEFAULT for ADC_IF */
+#define ADC_IF_SCAN                                        (0x1UL << 1)                      /**< Scan Conversion Complete Interrupt Flag */
+#define _ADC_IF_SCAN_SHIFT                                 1                                 /**< Shift value for ADC_SCAN */
+#define _ADC_IF_SCAN_MASK                                  0x2UL                             /**< Bit mask for ADC_SCAN */
+#define _ADC_IF_SCAN_DEFAULT                               0x00000000UL                      /**< Mode DEFAULT for ADC_IF */
+#define ADC_IF_SCAN_DEFAULT                                (_ADC_IF_SCAN_DEFAULT << 1)       /**< Shifted mode DEFAULT for ADC_IF */
+#define ADC_IF_SINGLEOF                                    (0x1UL << 8)                      /**< Single Result Overflow Interrupt Flag */
+#define _ADC_IF_SINGLEOF_SHIFT                             8                                 /**< Shift value for ADC_SINGLEOF */
+#define _ADC_IF_SINGLEOF_MASK                              0x100UL                           /**< Bit mask for ADC_SINGLEOF */
+#define _ADC_IF_SINGLEOF_DEFAULT                           0x00000000UL                      /**< Mode DEFAULT for ADC_IF */
+#define ADC_IF_SINGLEOF_DEFAULT                            (_ADC_IF_SINGLEOF_DEFAULT << 8)   /**< Shifted mode DEFAULT for ADC_IF */
+#define ADC_IF_SCANOF                                      (0x1UL << 9)                      /**< Scan Result Overflow Interrupt Flag */
+#define _ADC_IF_SCANOF_SHIFT                               9                                 /**< Shift value for ADC_SCANOF */
+#define _ADC_IF_SCANOF_MASK                                0x200UL                           /**< Bit mask for ADC_SCANOF */
+#define _ADC_IF_SCANOF_DEFAULT                             0x00000000UL                      /**< Mode DEFAULT for ADC_IF */
+#define ADC_IF_SCANOF_DEFAULT                              (_ADC_IF_SCANOF_DEFAULT << 9)     /**< Shifted mode DEFAULT for ADC_IF */
+#define ADC_IF_SINGLEUF                                    (0x1UL << 10)                     /**< Single Result Underflow Interrupt Flag */
+#define _ADC_IF_SINGLEUF_SHIFT                             10                                /**< Shift value for ADC_SINGLEUF */
+#define _ADC_IF_SINGLEUF_MASK                              0x400UL                           /**< Bit mask for ADC_SINGLEUF */
+#define _ADC_IF_SINGLEUF_DEFAULT                           0x00000000UL                      /**< Mode DEFAULT for ADC_IF */
+#define ADC_IF_SINGLEUF_DEFAULT                            (_ADC_IF_SINGLEUF_DEFAULT << 10)  /**< Shifted mode DEFAULT for ADC_IF */
+#define ADC_IF_SCANUF                                      (0x1UL << 11)                     /**< Scan Result Underflow Interrupt Flag */
+#define _ADC_IF_SCANUF_SHIFT                               11                                /**< Shift value for ADC_SCANUF */
+#define _ADC_IF_SCANUF_MASK                                0x800UL                           /**< Bit mask for ADC_SCANUF */
+#define _ADC_IF_SCANUF_DEFAULT                             0x00000000UL                      /**< Mode DEFAULT for ADC_IF */
+#define ADC_IF_SCANUF_DEFAULT                              (_ADC_IF_SCANUF_DEFAULT << 11)    /**< Shifted mode DEFAULT for ADC_IF */
+#define ADC_IF_SINGLECMP                                   (0x1UL << 16)                     /**< Single Result Compare Match Interrupt Flag */
+#define _ADC_IF_SINGLECMP_SHIFT                            16                                /**< Shift value for ADC_SINGLECMP */
+#define _ADC_IF_SINGLECMP_MASK                             0x10000UL                         /**< Bit mask for ADC_SINGLECMP */
+#define _ADC_IF_SINGLECMP_DEFAULT                          0x00000000UL                      /**< Mode DEFAULT for ADC_IF */
+#define ADC_IF_SINGLECMP_DEFAULT                           (_ADC_IF_SINGLECMP_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_IF */
+#define ADC_IF_SCANCMP                                     (0x1UL << 17)                     /**< Scan Result Compare Match Interrupt Flag */
+#define _ADC_IF_SCANCMP_SHIFT                              17                                /**< Shift value for ADC_SCANCMP */
+#define _ADC_IF_SCANCMP_MASK                               0x20000UL                         /**< Bit mask for ADC_SCANCMP */
+#define _ADC_IF_SCANCMP_DEFAULT                            0x00000000UL                      /**< Mode DEFAULT for ADC_IF */
+#define ADC_IF_SCANCMP_DEFAULT                             (_ADC_IF_SCANCMP_DEFAULT << 17)   /**< Shifted mode DEFAULT for ADC_IF */
+#define ADC_IF_VREFOV                                      (0x1UL << 24)                     /**< VREF OverVoltage Interrupt Flag */
+#define _ADC_IF_VREFOV_SHIFT                               24                                /**< Shift value for ADC_VREFOV */
+#define _ADC_IF_VREFOV_MASK                                0x1000000UL                       /**< Bit mask for ADC_VREFOV */
+#define _ADC_IF_VREFOV_DEFAULT                             0x00000000UL                      /**< Mode DEFAULT for ADC_IF */
+#define ADC_IF_VREFOV_DEFAULT                              (_ADC_IF_VREFOV_DEFAULT << 24)    /**< Shifted mode DEFAULT for ADC_IF */
+#define ADC_IF_PROGERR                                     (0x1UL << 25)                     /**< Programming Error Interrupt Flag */
+#define _ADC_IF_PROGERR_SHIFT                              25                                /**< Shift value for ADC_PROGERR */
+#define _ADC_IF_PROGERR_MASK                               0x2000000UL                       /**< Bit mask for ADC_PROGERR */
+#define _ADC_IF_PROGERR_DEFAULT                            0x00000000UL                      /**< Mode DEFAULT for ADC_IF */
+#define ADC_IF_PROGERR_DEFAULT                             (_ADC_IF_PROGERR_DEFAULT << 25)   /**< Shifted mode DEFAULT for ADC_IF */
+
+/* Bit fields for ADC IFS */
+#define _ADC_IFS_RESETVALUE                                0x00000000UL                       /**< Default value for ADC_IFS */
+#define _ADC_IFS_MASK                                      0x03030F00UL                       /**< Mask for ADC_IFS */
+#define ADC_IFS_SINGLEOF                                   (0x1UL << 8)                       /**< Set SINGLEOF Interrupt Flag */
+#define _ADC_IFS_SINGLEOF_SHIFT                            8                                  /**< Shift value for ADC_SINGLEOF */
+#define _ADC_IFS_SINGLEOF_MASK                             0x100UL                            /**< Bit mask for ADC_SINGLEOF */
+#define _ADC_IFS_SINGLEOF_DEFAULT                          0x00000000UL                       /**< Mode DEFAULT for ADC_IFS */
+#define ADC_IFS_SINGLEOF_DEFAULT                           (_ADC_IFS_SINGLEOF_DEFAULT << 8)   /**< Shifted mode DEFAULT for ADC_IFS */
+#define ADC_IFS_SCANOF                                     (0x1UL << 9)                       /**< Set SCANOF Interrupt Flag */
+#define _ADC_IFS_SCANOF_SHIFT                              9                                  /**< Shift value for ADC_SCANOF */
+#define _ADC_IFS_SCANOF_MASK                               0x200UL                            /**< Bit mask for ADC_SCANOF */
+#define _ADC_IFS_SCANOF_DEFAULT                            0x00000000UL                       /**< Mode DEFAULT for ADC_IFS */
+#define ADC_IFS_SCANOF_DEFAULT                             (_ADC_IFS_SCANOF_DEFAULT << 9)     /**< Shifted mode DEFAULT for ADC_IFS */
+#define ADC_IFS_SINGLEUF                                   (0x1UL << 10)                      /**< Set SINGLEUF Interrupt Flag */
+#define _ADC_IFS_SINGLEUF_SHIFT                            10                                 /**< Shift value for ADC_SINGLEUF */
+#define _ADC_IFS_SINGLEUF_MASK                             0x400UL                            /**< Bit mask for ADC_SINGLEUF */
+#define _ADC_IFS_SINGLEUF_DEFAULT                          0x00000000UL                       /**< Mode DEFAULT for ADC_IFS */
+#define ADC_IFS_SINGLEUF_DEFAULT                           (_ADC_IFS_SINGLEUF_DEFAULT << 10)  /**< Shifted mode DEFAULT for ADC_IFS */
+#define ADC_IFS_SCANUF                                     (0x1UL << 11)                      /**< Set SCANUF Interrupt Flag */
+#define _ADC_IFS_SCANUF_SHIFT                              11                                 /**< Shift value for ADC_SCANUF */
+#define _ADC_IFS_SCANUF_MASK                               0x800UL                            /**< Bit mask for ADC_SCANUF */
+#define _ADC_IFS_SCANUF_DEFAULT                            0x00000000UL                       /**< Mode DEFAULT for ADC_IFS */
+#define ADC_IFS_SCANUF_DEFAULT                             (_ADC_IFS_SCANUF_DEFAULT << 11)    /**< Shifted mode DEFAULT for ADC_IFS */
+#define ADC_IFS_SINGLECMP                                  (0x1UL << 16)                      /**< Set SINGLECMP Interrupt Flag */
+#define _ADC_IFS_SINGLECMP_SHIFT                           16                                 /**< Shift value for ADC_SINGLECMP */
+#define _ADC_IFS_SINGLECMP_MASK                            0x10000UL                          /**< Bit mask for ADC_SINGLECMP */
+#define _ADC_IFS_SINGLECMP_DEFAULT                         0x00000000UL                       /**< Mode DEFAULT for ADC_IFS */
+#define ADC_IFS_SINGLECMP_DEFAULT                          (_ADC_IFS_SINGLECMP_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_IFS */
+#define ADC_IFS_SCANCMP                                    (0x1UL << 17)                      /**< Set SCANCMP Interrupt Flag */
+#define _ADC_IFS_SCANCMP_SHIFT                             17                                 /**< Shift value for ADC_SCANCMP */
+#define _ADC_IFS_SCANCMP_MASK                              0x20000UL                          /**< Bit mask for ADC_SCANCMP */
+#define _ADC_IFS_SCANCMP_DEFAULT                           0x00000000UL                       /**< Mode DEFAULT for ADC_IFS */
+#define ADC_IFS_SCANCMP_DEFAULT                            (_ADC_IFS_SCANCMP_DEFAULT << 17)   /**< Shifted mode DEFAULT for ADC_IFS */
+#define ADC_IFS_VREFOV                                     (0x1UL << 24)                      /**< Set VREFOV Interrupt Flag */
+#define _ADC_IFS_VREFOV_SHIFT                              24                                 /**< Shift value for ADC_VREFOV */
+#define _ADC_IFS_VREFOV_MASK                               0x1000000UL                        /**< Bit mask for ADC_VREFOV */
+#define _ADC_IFS_VREFOV_DEFAULT                            0x00000000UL                       /**< Mode DEFAULT for ADC_IFS */
+#define ADC_IFS_VREFOV_DEFAULT                             (_ADC_IFS_VREFOV_DEFAULT << 24)    /**< Shifted mode DEFAULT for ADC_IFS */
+#define ADC_IFS_PROGERR                                    (0x1UL << 25)                      /**< Set PROGERR Interrupt Flag */
+#define _ADC_IFS_PROGERR_SHIFT                             25                                 /**< Shift value for ADC_PROGERR */
+#define _ADC_IFS_PROGERR_MASK                              0x2000000UL                        /**< Bit mask for ADC_PROGERR */
+#define _ADC_IFS_PROGERR_DEFAULT                           0x00000000UL                       /**< Mode DEFAULT for ADC_IFS */
+#define ADC_IFS_PROGERR_DEFAULT                            (_ADC_IFS_PROGERR_DEFAULT << 25)   /**< Shifted mode DEFAULT for ADC_IFS */
+
+/* Bit fields for ADC IFC */
+#define _ADC_IFC_RESETVALUE                                0x00000000UL                       /**< Default value for ADC_IFC */
+#define _ADC_IFC_MASK                                      0x03030F00UL                       /**< Mask for ADC_IFC */
+#define ADC_IFC_SINGLEOF                                   (0x1UL << 8)                       /**< Clear SINGLEOF Interrupt Flag */
+#define _ADC_IFC_SINGLEOF_SHIFT                            8                                  /**< Shift value for ADC_SINGLEOF */
+#define _ADC_IFC_SINGLEOF_MASK                             0x100UL                            /**< Bit mask for ADC_SINGLEOF */
+#define _ADC_IFC_SINGLEOF_DEFAULT                          0x00000000UL                       /**< Mode DEFAULT for ADC_IFC */
+#define ADC_IFC_SINGLEOF_DEFAULT                           (_ADC_IFC_SINGLEOF_DEFAULT << 8)   /**< Shifted mode DEFAULT for ADC_IFC */
+#define ADC_IFC_SCANOF                                     (0x1UL << 9)                       /**< Clear SCANOF Interrupt Flag */
+#define _ADC_IFC_SCANOF_SHIFT                              9                                  /**< Shift value for ADC_SCANOF */
+#define _ADC_IFC_SCANOF_MASK                               0x200UL                            /**< Bit mask for ADC_SCANOF */
+#define _ADC_IFC_SCANOF_DEFAULT                            0x00000000UL                       /**< Mode DEFAULT for ADC_IFC */
+#define ADC_IFC_SCANOF_DEFAULT                             (_ADC_IFC_SCANOF_DEFAULT << 9)     /**< Shifted mode DEFAULT for ADC_IFC */
+#define ADC_IFC_SINGLEUF                                   (0x1UL << 10)                      /**< Clear SINGLEUF Interrupt Flag */
+#define _ADC_IFC_SINGLEUF_SHIFT                            10                                 /**< Shift value for ADC_SINGLEUF */
+#define _ADC_IFC_SINGLEUF_MASK                             0x400UL                            /**< Bit mask for ADC_SINGLEUF */
+#define _ADC_IFC_SINGLEUF_DEFAULT                          0x00000000UL                       /**< Mode DEFAULT for ADC_IFC */
+#define ADC_IFC_SINGLEUF_DEFAULT                           (_ADC_IFC_SINGLEUF_DEFAULT << 10)  /**< Shifted mode DEFAULT for ADC_IFC */
+#define ADC_IFC_SCANUF                                     (0x1UL << 11)                      /**< Clear SCANUF Interrupt Flag */
+#define _ADC_IFC_SCANUF_SHIFT                              11                                 /**< Shift value for ADC_SCANUF */
+#define _ADC_IFC_SCANUF_MASK                               0x800UL                            /**< Bit mask for ADC_SCANUF */
+#define _ADC_IFC_SCANUF_DEFAULT                            0x00000000UL                       /**< Mode DEFAULT for ADC_IFC */
+#define ADC_IFC_SCANUF_DEFAULT                             (_ADC_IFC_SCANUF_DEFAULT << 11)    /**< Shifted mode DEFAULT for ADC_IFC */
+#define ADC_IFC_SINGLECMP                                  (0x1UL << 16)                      /**< Clear SINGLECMP Interrupt Flag */
+#define _ADC_IFC_SINGLECMP_SHIFT                           16                                 /**< Shift value for ADC_SINGLECMP */
+#define _ADC_IFC_SINGLECMP_MASK                            0x10000UL                          /**< Bit mask for ADC_SINGLECMP */
+#define _ADC_IFC_SINGLECMP_DEFAULT                         0x00000000UL                       /**< Mode DEFAULT for ADC_IFC */
+#define ADC_IFC_SINGLECMP_DEFAULT                          (_ADC_IFC_SINGLECMP_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_IFC */
+#define ADC_IFC_SCANCMP                                    (0x1UL << 17)                      /**< Clear SCANCMP Interrupt Flag */
+#define _ADC_IFC_SCANCMP_SHIFT                             17                                 /**< Shift value for ADC_SCANCMP */
+#define _ADC_IFC_SCANCMP_MASK                              0x20000UL                          /**< Bit mask for ADC_SCANCMP */
+#define _ADC_IFC_SCANCMP_DEFAULT                           0x00000000UL                       /**< Mode DEFAULT for ADC_IFC */
+#define ADC_IFC_SCANCMP_DEFAULT                            (_ADC_IFC_SCANCMP_DEFAULT << 17)   /**< Shifted mode DEFAULT for ADC_IFC */
+#define ADC_IFC_VREFOV                                     (0x1UL << 24)                      /**< Clear VREFOV Interrupt Flag */
+#define _ADC_IFC_VREFOV_SHIFT                              24                                 /**< Shift value for ADC_VREFOV */
+#define _ADC_IFC_VREFOV_MASK                               0x1000000UL                        /**< Bit mask for ADC_VREFOV */
+#define _ADC_IFC_VREFOV_DEFAULT                            0x00000000UL                       /**< Mode DEFAULT for ADC_IFC */
+#define ADC_IFC_VREFOV_DEFAULT                             (_ADC_IFC_VREFOV_DEFAULT << 24)    /**< Shifted mode DEFAULT for ADC_IFC */
+#define ADC_IFC_PROGERR                                    (0x1UL << 25)                      /**< Clear PROGERR Interrupt Flag */
+#define _ADC_IFC_PROGERR_SHIFT                             25                                 /**< Shift value for ADC_PROGERR */
+#define _ADC_IFC_PROGERR_MASK                              0x2000000UL                        /**< Bit mask for ADC_PROGERR */
+#define _ADC_IFC_PROGERR_DEFAULT                           0x00000000UL                       /**< Mode DEFAULT for ADC_IFC */
+#define ADC_IFC_PROGERR_DEFAULT                            (_ADC_IFC_PROGERR_DEFAULT << 25)   /**< Shifted mode DEFAULT for ADC_IFC */
+
+/* Bit fields for ADC IEN */
+#define _ADC_IEN_RESETVALUE                                0x00000000UL                       /**< Default value for ADC_IEN */
+#define _ADC_IEN_MASK                                      0x03030F03UL                       /**< Mask for ADC_IEN */
+#define ADC_IEN_SINGLE                                     (0x1UL << 0)                       /**< SINGLE Interrupt Enable */
+#define _ADC_IEN_SINGLE_SHIFT                              0                                  /**< Shift value for ADC_SINGLE */
+#define _ADC_IEN_SINGLE_MASK                               0x1UL                              /**< Bit mask for ADC_SINGLE */
+#define _ADC_IEN_SINGLE_DEFAULT                            0x00000000UL                       /**< Mode DEFAULT for ADC_IEN */
+#define ADC_IEN_SINGLE_DEFAULT                             (_ADC_IEN_SINGLE_DEFAULT << 0)     /**< Shifted mode DEFAULT for ADC_IEN */
+#define ADC_IEN_SCAN                                       (0x1UL << 1)                       /**< SCAN Interrupt Enable */
+#define _ADC_IEN_SCAN_SHIFT                                1                                  /**< Shift value for ADC_SCAN */
+#define _ADC_IEN_SCAN_MASK                                 0x2UL                              /**< Bit mask for ADC_SCAN */
+#define _ADC_IEN_SCAN_DEFAULT                              0x00000000UL                       /**< Mode DEFAULT for ADC_IEN */
+#define ADC_IEN_SCAN_DEFAULT                               (_ADC_IEN_SCAN_DEFAULT << 1)       /**< Shifted mode DEFAULT for ADC_IEN */
+#define ADC_IEN_SINGLEOF                                   (0x1UL << 8)                       /**< SINGLEOF Interrupt Enable */
+#define _ADC_IEN_SINGLEOF_SHIFT                            8                                  /**< Shift value for ADC_SINGLEOF */
+#define _ADC_IEN_SINGLEOF_MASK                             0x100UL                            /**< Bit mask for ADC_SINGLEOF */
+#define _ADC_IEN_SINGLEOF_DEFAULT                          0x00000000UL                       /**< Mode DEFAULT for ADC_IEN */
+#define ADC_IEN_SINGLEOF_DEFAULT                           (_ADC_IEN_SINGLEOF_DEFAULT << 8)   /**< Shifted mode DEFAULT for ADC_IEN */
+#define ADC_IEN_SCANOF                                     (0x1UL << 9)                       /**< SCANOF Interrupt Enable */
+#define _ADC_IEN_SCANOF_SHIFT                              9                                  /**< Shift value for ADC_SCANOF */
+#define _ADC_IEN_SCANOF_MASK                               0x200UL                            /**< Bit mask for ADC_SCANOF */
+#define _ADC_IEN_SCANOF_DEFAULT                            0x00000000UL                       /**< Mode DEFAULT for ADC_IEN */
+#define ADC_IEN_SCANOF_DEFAULT                             (_ADC_IEN_SCANOF_DEFAULT << 9)     /**< Shifted mode DEFAULT for ADC_IEN */
+#define ADC_IEN_SINGLEUF                                   (0x1UL << 10)                      /**< SINGLEUF Interrupt Enable */
+#define _ADC_IEN_SINGLEUF_SHIFT                            10                                 /**< Shift value for ADC_SINGLEUF */
+#define _ADC_IEN_SINGLEUF_MASK                             0x400UL                            /**< Bit mask for ADC_SINGLEUF */
+#define _ADC_IEN_SINGLEUF_DEFAULT                          0x00000000UL                       /**< Mode DEFAULT for ADC_IEN */
+#define ADC_IEN_SINGLEUF_DEFAULT                           (_ADC_IEN_SINGLEUF_DEFAULT << 10)  /**< Shifted mode DEFAULT for ADC_IEN */
+#define ADC_IEN_SCANUF                                     (0x1UL << 11)                      /**< SCANUF Interrupt Enable */
+#define _ADC_IEN_SCANUF_SHIFT                              11                                 /**< Shift value for ADC_SCANUF */
+#define _ADC_IEN_SCANUF_MASK                               0x800UL                            /**< Bit mask for ADC_SCANUF */
+#define _ADC_IEN_SCANUF_DEFAULT                            0x00000000UL                       /**< Mode DEFAULT for ADC_IEN */
+#define ADC_IEN_SCANUF_DEFAULT                             (_ADC_IEN_SCANUF_DEFAULT << 11)    /**< Shifted mode DEFAULT for ADC_IEN */
+#define ADC_IEN_SINGLECMP                                  (0x1UL << 16)                      /**< SINGLECMP Interrupt Enable */
+#define _ADC_IEN_SINGLECMP_SHIFT                           16                                 /**< Shift value for ADC_SINGLECMP */
+#define _ADC_IEN_SINGLECMP_MASK                            0x10000UL                          /**< Bit mask for ADC_SINGLECMP */
+#define _ADC_IEN_SINGLECMP_DEFAULT                         0x00000000UL                       /**< Mode DEFAULT for ADC_IEN */
+#define ADC_IEN_SINGLECMP_DEFAULT                          (_ADC_IEN_SINGLECMP_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_IEN */
+#define ADC_IEN_SCANCMP                                    (0x1UL << 17)                      /**< SCANCMP Interrupt Enable */
+#define _ADC_IEN_SCANCMP_SHIFT                             17                                 /**< Shift value for ADC_SCANCMP */
+#define _ADC_IEN_SCANCMP_MASK                              0x20000UL                          /**< Bit mask for ADC_SCANCMP */
+#define _ADC_IEN_SCANCMP_DEFAULT                           0x00000000UL                       /**< Mode DEFAULT for ADC_IEN */
+#define ADC_IEN_SCANCMP_DEFAULT                            (_ADC_IEN_SCANCMP_DEFAULT << 17)   /**< Shifted mode DEFAULT for ADC_IEN */
+#define ADC_IEN_VREFOV                                     (0x1UL << 24)                      /**< VREFOV Interrupt Enable */
+#define _ADC_IEN_VREFOV_SHIFT                              24                                 /**< Shift value for ADC_VREFOV */
+#define _ADC_IEN_VREFOV_MASK                               0x1000000UL                        /**< Bit mask for ADC_VREFOV */
+#define _ADC_IEN_VREFOV_DEFAULT                            0x00000000UL                       /**< Mode DEFAULT for ADC_IEN */
+#define ADC_IEN_VREFOV_DEFAULT                             (_ADC_IEN_VREFOV_DEFAULT << 24)    /**< Shifted mode DEFAULT for ADC_IEN */
+#define ADC_IEN_PROGERR                                    (0x1UL << 25)                      /**< PROGERR Interrupt Enable */
+#define _ADC_IEN_PROGERR_SHIFT                             25                                 /**< Shift value for ADC_PROGERR */
+#define _ADC_IEN_PROGERR_MASK                              0x2000000UL                        /**< Bit mask for ADC_PROGERR */
+#define _ADC_IEN_PROGERR_DEFAULT                           0x00000000UL                       /**< Mode DEFAULT for ADC_IEN */
+#define ADC_IEN_PROGERR_DEFAULT                            (_ADC_IEN_PROGERR_DEFAULT << 25)   /**< Shifted mode DEFAULT for ADC_IEN */
+
+/* Bit fields for ADC SINGLEDATA */
+#define _ADC_SINGLEDATA_RESETVALUE                         0x00000000UL                        /**< Default value for ADC_SINGLEDATA */
+#define _ADC_SINGLEDATA_MASK                               0xFFFFFFFFUL                        /**< Mask for ADC_SINGLEDATA */
+#define _ADC_SINGLEDATA_DATA_SHIFT                         0                                   /**< Shift value for ADC_DATA */
+#define _ADC_SINGLEDATA_DATA_MASK                          0xFFFFFFFFUL                        /**< Bit mask for ADC_DATA */
+#define _ADC_SINGLEDATA_DATA_DEFAULT                       0x00000000UL                        /**< Mode DEFAULT for ADC_SINGLEDATA */
+#define ADC_SINGLEDATA_DATA_DEFAULT                        (_ADC_SINGLEDATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLEDATA */
+
+/* Bit fields for ADC SCANDATA */
+#define _ADC_SCANDATA_RESETVALUE                           0x00000000UL                      /**< Default value for ADC_SCANDATA */
+#define _ADC_SCANDATA_MASK                                 0xFFFFFFFFUL                      /**< Mask for ADC_SCANDATA */
+#define _ADC_SCANDATA_DATA_SHIFT                           0                                 /**< Shift value for ADC_DATA */
+#define _ADC_SCANDATA_DATA_MASK                            0xFFFFFFFFUL                      /**< Bit mask for ADC_DATA */
+#define _ADC_SCANDATA_DATA_DEFAULT                         0x00000000UL                      /**< Mode DEFAULT for ADC_SCANDATA */
+#define ADC_SCANDATA_DATA_DEFAULT                          (_ADC_SCANDATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANDATA */
+
+/* Bit fields for ADC SINGLEDATAP */
+#define _ADC_SINGLEDATAP_RESETVALUE                        0x00000000UL                          /**< Default value for ADC_SINGLEDATAP */
+#define _ADC_SINGLEDATAP_MASK                              0xFFFFFFFFUL                          /**< Mask for ADC_SINGLEDATAP */
+#define _ADC_SINGLEDATAP_DATAP_SHIFT                       0                                     /**< Shift value for ADC_DATAP */
+#define _ADC_SINGLEDATAP_DATAP_MASK                        0xFFFFFFFFUL                          /**< Bit mask for ADC_DATAP */
+#define _ADC_SINGLEDATAP_DATAP_DEFAULT                     0x00000000UL                          /**< Mode DEFAULT for ADC_SINGLEDATAP */
+#define ADC_SINGLEDATAP_DATAP_DEFAULT                      (_ADC_SINGLEDATAP_DATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLEDATAP */
+
+/* Bit fields for ADC SCANDATAP */
+#define _ADC_SCANDATAP_RESETVALUE                          0x00000000UL                        /**< Default value for ADC_SCANDATAP */
+#define _ADC_SCANDATAP_MASK                                0xFFFFFFFFUL                        /**< Mask for ADC_SCANDATAP */
+#define _ADC_SCANDATAP_DATAP_SHIFT                         0                                   /**< Shift value for ADC_DATAP */
+#define _ADC_SCANDATAP_DATAP_MASK                          0xFFFFFFFFUL                        /**< Bit mask for ADC_DATAP */
+#define _ADC_SCANDATAP_DATAP_DEFAULT                       0x00000000UL                        /**< Mode DEFAULT for ADC_SCANDATAP */
+#define ADC_SCANDATAP_DATAP_DEFAULT                        (_ADC_SCANDATAP_DATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANDATAP */
+
+/* Bit fields for ADC SCANDATAX */
+#define _ADC_SCANDATAX_RESETVALUE                          0x00000000UL                               /**< Default value for ADC_SCANDATAX */
+#define _ADC_SCANDATAX_MASK                                0x001FFFFFUL                               /**< Mask for ADC_SCANDATAX */
+#define _ADC_SCANDATAX_DATA_SHIFT                          0                                          /**< Shift value for ADC_DATA */
+#define _ADC_SCANDATAX_DATA_MASK                           0xFFFFUL                                   /**< Bit mask for ADC_DATA */
+#define _ADC_SCANDATAX_DATA_DEFAULT                        0x00000000UL                               /**< Mode DEFAULT for ADC_SCANDATAX */
+#define ADC_SCANDATAX_DATA_DEFAULT                         (_ADC_SCANDATAX_DATA_DEFAULT << 0)         /**< Shifted mode DEFAULT for ADC_SCANDATAX */
+#define _ADC_SCANDATAX_SCANINPUTID_SHIFT                   16                                         /**< Shift value for ADC_SCANINPUTID */
+#define _ADC_SCANDATAX_SCANINPUTID_MASK                    0x1F0000UL                                 /**< Bit mask for ADC_SCANINPUTID */
+#define _ADC_SCANDATAX_SCANINPUTID_DEFAULT                 0x00000000UL                               /**< Mode DEFAULT for ADC_SCANDATAX */
+#define ADC_SCANDATAX_SCANINPUTID_DEFAULT                  (_ADC_SCANDATAX_SCANINPUTID_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_SCANDATAX */
+
+/* Bit fields for ADC SCANDATAXP */
+#define _ADC_SCANDATAXP_RESETVALUE                         0x00000000UL                                    /**< Default value for ADC_SCANDATAXP */
+#define _ADC_SCANDATAXP_MASK                               0x001FFFFFUL                                    /**< Mask for ADC_SCANDATAXP */
+#define _ADC_SCANDATAXP_DATAP_SHIFT                        0                                               /**< Shift value for ADC_DATAP */
+#define _ADC_SCANDATAXP_DATAP_MASK                         0xFFFFUL                                        /**< Bit mask for ADC_DATAP */
+#define _ADC_SCANDATAXP_DATAP_DEFAULT                      0x00000000UL                                    /**< Mode DEFAULT for ADC_SCANDATAXP */
+#define ADC_SCANDATAXP_DATAP_DEFAULT                       (_ADC_SCANDATAXP_DATAP_DEFAULT << 0)            /**< Shifted mode DEFAULT for ADC_SCANDATAXP */
+#define _ADC_SCANDATAXP_SCANINPUTIDPEEK_SHIFT              16                                              /**< Shift value for ADC_SCANINPUTIDPEEK */
+#define _ADC_SCANDATAXP_SCANINPUTIDPEEK_MASK               0x1F0000UL                                      /**< Bit mask for ADC_SCANINPUTIDPEEK */
+#define _ADC_SCANDATAXP_SCANINPUTIDPEEK_DEFAULT            0x00000000UL                                    /**< Mode DEFAULT for ADC_SCANDATAXP */
+#define ADC_SCANDATAXP_SCANINPUTIDPEEK_DEFAULT             (_ADC_SCANDATAXP_SCANINPUTIDPEEK_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_SCANDATAXP */
+
+/* Bit fields for ADC APORTREQ */
+#define _ADC_APORTREQ_RESETVALUE                           0x00000000UL                            /**< Default value for ADC_APORTREQ */
+#define _ADC_APORTREQ_MASK                                 0x000003FFUL                            /**< Mask for ADC_APORTREQ */
+#define ADC_APORTREQ_APORT0XREQ                            (0x1UL << 0)                            /**< 1 if the bus connected to APORT0X is requested */
+#define _ADC_APORTREQ_APORT0XREQ_SHIFT                     0                                       /**< Shift value for ADC_APORT0XREQ */
+#define _ADC_APORTREQ_APORT0XREQ_MASK                      0x1UL                                   /**< Bit mask for ADC_APORT0XREQ */
+#define _ADC_APORTREQ_APORT0XREQ_DEFAULT                   0x00000000UL                            /**< Mode DEFAULT for ADC_APORTREQ */
+#define ADC_APORTREQ_APORT0XREQ_DEFAULT                    (_ADC_APORTREQ_APORT0XREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_APORTREQ */
+#define ADC_APORTREQ_APORT0YREQ                            (0x1UL << 1)                            /**< 1 if the bus connected to APORT0Y is requested */
+#define _ADC_APORTREQ_APORT0YREQ_SHIFT                     1                                       /**< Shift value for ADC_APORT0YREQ */
+#define _ADC_APORTREQ_APORT0YREQ_MASK                      0x2UL                                   /**< Bit mask for ADC_APORT0YREQ */
+#define _ADC_APORTREQ_APORT0YREQ_DEFAULT                   0x00000000UL                            /**< Mode DEFAULT for ADC_APORTREQ */
+#define ADC_APORTREQ_APORT0YREQ_DEFAULT                    (_ADC_APORTREQ_APORT0YREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_APORTREQ */
+#define ADC_APORTREQ_APORT1XREQ                            (0x1UL << 2)                            /**< 1 if the bus connected to APORT1X is requested */
+#define _ADC_APORTREQ_APORT1XREQ_SHIFT                     2                                       /**< Shift value for ADC_APORT1XREQ */
+#define _ADC_APORTREQ_APORT1XREQ_MASK                      0x4UL                                   /**< Bit mask for ADC_APORT1XREQ */
+#define _ADC_APORTREQ_APORT1XREQ_DEFAULT                   0x00000000UL                            /**< Mode DEFAULT for ADC_APORTREQ */
+#define ADC_APORTREQ_APORT1XREQ_DEFAULT                    (_ADC_APORTREQ_APORT1XREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_APORTREQ */
+#define ADC_APORTREQ_APORT1YREQ                            (0x1UL << 3)                            /**< 1 if the bus connected to APORT1Y is requested */
+#define _ADC_APORTREQ_APORT1YREQ_SHIFT                     3                                       /**< Shift value for ADC_APORT1YREQ */
+#define _ADC_APORTREQ_APORT1YREQ_MASK                      0x8UL                                   /**< Bit mask for ADC_APORT1YREQ */
+#define _ADC_APORTREQ_APORT1YREQ_DEFAULT                   0x00000000UL                            /**< Mode DEFAULT for ADC_APORTREQ */
+#define ADC_APORTREQ_APORT1YREQ_DEFAULT                    (_ADC_APORTREQ_APORT1YREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_APORTREQ */
+#define ADC_APORTREQ_APORT2XREQ                            (0x1UL << 4)                            /**< 1 if the bus connected to APORT2X is requested */
+#define _ADC_APORTREQ_APORT2XREQ_SHIFT                     4                                       /**< Shift value for ADC_APORT2XREQ */
+#define _ADC_APORTREQ_APORT2XREQ_MASK                      0x10UL                                  /**< Bit mask for ADC_APORT2XREQ */
+#define _ADC_APORTREQ_APORT2XREQ_DEFAULT                   0x00000000UL                            /**< Mode DEFAULT for ADC_APORTREQ */
+#define ADC_APORTREQ_APORT2XREQ_DEFAULT                    (_ADC_APORTREQ_APORT2XREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_APORTREQ */
+#define ADC_APORTREQ_APORT2YREQ                            (0x1UL << 5)                            /**< 1 if the bus connected to APORT2Y is requested */
+#define _ADC_APORTREQ_APORT2YREQ_SHIFT                     5                                       /**< Shift value for ADC_APORT2YREQ */
+#define _ADC_APORTREQ_APORT2YREQ_MASK                      0x20UL                                  /**< Bit mask for ADC_APORT2YREQ */
+#define _ADC_APORTREQ_APORT2YREQ_DEFAULT                   0x00000000UL                            /**< Mode DEFAULT for ADC_APORTREQ */
+#define ADC_APORTREQ_APORT2YREQ_DEFAULT                    (_ADC_APORTREQ_APORT2YREQ_DEFAULT << 5) /**< Shifted mode DEFAULT for ADC_APORTREQ */
+#define ADC_APORTREQ_APORT3XREQ                            (0x1UL << 6)                            /**< 1 if the bus connected to APORT3X is requested */
+#define _ADC_APORTREQ_APORT3XREQ_SHIFT                     6                                       /**< Shift value for ADC_APORT3XREQ */
+#define _ADC_APORTREQ_APORT3XREQ_MASK                      0x40UL                                  /**< Bit mask for ADC_APORT3XREQ */
+#define _ADC_APORTREQ_APORT3XREQ_DEFAULT                   0x00000000UL                            /**< Mode DEFAULT for ADC_APORTREQ */
+#define ADC_APORTREQ_APORT3XREQ_DEFAULT                    (_ADC_APORTREQ_APORT3XREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for ADC_APORTREQ */
+#define ADC_APORTREQ_APORT3YREQ                            (0x1UL << 7)                            /**< 1 if the bus connected to APORT3Y is requested */
+#define _ADC_APORTREQ_APORT3YREQ_SHIFT                     7                                       /**< Shift value for ADC_APORT3YREQ */
+#define _ADC_APORTREQ_APORT3YREQ_MASK                      0x80UL                                  /**< Bit mask for ADC_APORT3YREQ */
+#define _ADC_APORTREQ_APORT3YREQ_DEFAULT                   0x00000000UL                            /**< Mode DEFAULT for ADC_APORTREQ */
+#define ADC_APORTREQ_APORT3YREQ_DEFAULT                    (_ADC_APORTREQ_APORT3YREQ_DEFAULT << 7) /**< Shifted mode DEFAULT for ADC_APORTREQ */
+#define ADC_APORTREQ_APORT4XREQ                            (0x1UL << 8)                            /**< 1 if the bus connected to APORT4X is requested */
+#define _ADC_APORTREQ_APORT4XREQ_SHIFT                     8                                       /**< Shift value for ADC_APORT4XREQ */
+#define _ADC_APORTREQ_APORT4XREQ_MASK                      0x100UL                                 /**< Bit mask for ADC_APORT4XREQ */
+#define _ADC_APORTREQ_APORT4XREQ_DEFAULT                   0x00000000UL                            /**< Mode DEFAULT for ADC_APORTREQ */
+#define ADC_APORTREQ_APORT4XREQ_DEFAULT                    (_ADC_APORTREQ_APORT4XREQ_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_APORTREQ */
+#define ADC_APORTREQ_APORT4YREQ                            (0x1UL << 9)                            /**< 1 if the bus connected to APORT4Y is requested */
+#define _ADC_APORTREQ_APORT4YREQ_SHIFT                     9                                       /**< Shift value for ADC_APORT4YREQ */
+#define _ADC_APORTREQ_APORT4YREQ_MASK                      0x200UL                                 /**< Bit mask for ADC_APORT4YREQ */
+#define _ADC_APORTREQ_APORT4YREQ_DEFAULT                   0x00000000UL                            /**< Mode DEFAULT for ADC_APORTREQ */
+#define ADC_APORTREQ_APORT4YREQ_DEFAULT                    (_ADC_APORTREQ_APORT4YREQ_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_APORTREQ */
+
+/* Bit fields for ADC APORTCONFLICT */
+#define _ADC_APORTCONFLICT_RESETVALUE                      0x00000000UL                                      /**< Default value for ADC_APORTCONFLICT */
+#define _ADC_APORTCONFLICT_MASK                            0x000003FFUL                                      /**< Mask for ADC_APORTCONFLICT */
+#define ADC_APORTCONFLICT_APORT0XCONFLICT                  (0x1UL << 0)                                      /**< 1 if the bus connected to APORT0X is in conflict with another peripheral */
+#define _ADC_APORTCONFLICT_APORT0XCONFLICT_SHIFT           0                                                 /**< Shift value for ADC_APORT0XCONFLICT */
+#define _ADC_APORTCONFLICT_APORT0XCONFLICT_MASK            0x1UL                                             /**< Bit mask for ADC_APORT0XCONFLICT */
+#define _ADC_APORTCONFLICT_APORT0XCONFLICT_DEFAULT         0x00000000UL                                      /**< Mode DEFAULT for ADC_APORTCONFLICT */
+#define ADC_APORTCONFLICT_APORT0XCONFLICT_DEFAULT          (_ADC_APORTCONFLICT_APORT0XCONFLICT_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */
+#define ADC_APORTCONFLICT_APORT0YCONFLICT                  (0x1UL << 1)                                      /**< 1 if the bus connected to APORT0Y is in conflict with another peripheral */
+#define _ADC_APORTCONFLICT_APORT0YCONFLICT_SHIFT           1                                                 /**< Shift value for ADC_APORT0YCONFLICT */
+#define _ADC_APORTCONFLICT_APORT0YCONFLICT_MASK            0x2UL                                             /**< Bit mask for ADC_APORT0YCONFLICT */
+#define _ADC_APORTCONFLICT_APORT0YCONFLICT_DEFAULT         0x00000000UL                                      /**< Mode DEFAULT for ADC_APORTCONFLICT */
+#define ADC_APORTCONFLICT_APORT0YCONFLICT_DEFAULT          (_ADC_APORTCONFLICT_APORT0YCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */
+#define ADC_APORTCONFLICT_APORT1XCONFLICT                  (0x1UL << 2)                                      /**< 1 if the bus connected to APORT1X is in conflict with another peripheral */
+#define _ADC_APORTCONFLICT_APORT1XCONFLICT_SHIFT           2                                                 /**< Shift value for ADC_APORT1XCONFLICT */
+#define _ADC_APORTCONFLICT_APORT1XCONFLICT_MASK            0x4UL                                             /**< Bit mask for ADC_APORT1XCONFLICT */
+#define _ADC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT         0x00000000UL                                      /**< Mode DEFAULT for ADC_APORTCONFLICT */
+#define ADC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT          (_ADC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */
+#define ADC_APORTCONFLICT_APORT1YCONFLICT                  (0x1UL << 3)                                      /**< 1 if the bus connected to APORT1Y is in conflict with another peripheral */
+#define _ADC_APORTCONFLICT_APORT1YCONFLICT_SHIFT           3                                                 /**< Shift value for ADC_APORT1YCONFLICT */
+#define _ADC_APORTCONFLICT_APORT1YCONFLICT_MASK            0x8UL                                             /**< Bit mask for ADC_APORT1YCONFLICT */
+#define _ADC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT         0x00000000UL                                      /**< Mode DEFAULT for ADC_APORTCONFLICT */
+#define ADC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT          (_ADC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */
+#define ADC_APORTCONFLICT_APORT2XCONFLICT                  (0x1UL << 4)                                      /**< 1 if the bus connected to APORT2X is in conflict with another peripheral */
+#define _ADC_APORTCONFLICT_APORT2XCONFLICT_SHIFT           4                                                 /**< Shift value for ADC_APORT2XCONFLICT */
+#define _ADC_APORTCONFLICT_APORT2XCONFLICT_MASK            0x10UL                                            /**< Bit mask for ADC_APORT2XCONFLICT */
+#define _ADC_APORTCONFLICT_APORT2XCONFLICT_DEFAULT         0x00000000UL                                      /**< Mode DEFAULT for ADC_APORTCONFLICT */
+#define ADC_APORTCONFLICT_APORT2XCONFLICT_DEFAULT          (_ADC_APORTCONFLICT_APORT2XCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */
+#define ADC_APORTCONFLICT_APORT2YCONFLICT                  (0x1UL << 5)                                      /**< 1 if the bus connected to APORT2Y is in conflict with another peripheral */
+#define _ADC_APORTCONFLICT_APORT2YCONFLICT_SHIFT           5                                                 /**< Shift value for ADC_APORT2YCONFLICT */
+#define _ADC_APORTCONFLICT_APORT2YCONFLICT_MASK            0x20UL                                            /**< Bit mask for ADC_APORT2YCONFLICT */
+#define _ADC_APORTCONFLICT_APORT2YCONFLICT_DEFAULT         0x00000000UL                                      /**< Mode DEFAULT for ADC_APORTCONFLICT */
+#define ADC_APORTCONFLICT_APORT2YCONFLICT_DEFAULT          (_ADC_APORTCONFLICT_APORT2YCONFLICT_DEFAULT << 5) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */
+#define ADC_APORTCONFLICT_APORT3XCONFLICT                  (0x1UL << 6)                                      /**< 1 if the bus connected to APORT3X is in conflict with another peripheral */
+#define _ADC_APORTCONFLICT_APORT3XCONFLICT_SHIFT           6                                                 /**< Shift value for ADC_APORT3XCONFLICT */
+#define _ADC_APORTCONFLICT_APORT3XCONFLICT_MASK            0x40UL                                            /**< Bit mask for ADC_APORT3XCONFLICT */
+#define _ADC_APORTCONFLICT_APORT3XCONFLICT_DEFAULT         0x00000000UL                                      /**< Mode DEFAULT for ADC_APORTCONFLICT */
+#define ADC_APORTCONFLICT_APORT3XCONFLICT_DEFAULT          (_ADC_APORTCONFLICT_APORT3XCONFLICT_DEFAULT << 6) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */
+#define ADC_APORTCONFLICT_APORT3YCONFLICT                  (0x1UL << 7)                                      /**< 1 if the bus connected to APORT3Y is in conflict with another peripheral */
+#define _ADC_APORTCONFLICT_APORT3YCONFLICT_SHIFT           7                                                 /**< Shift value for ADC_APORT3YCONFLICT */
+#define _ADC_APORTCONFLICT_APORT3YCONFLICT_MASK            0x80UL                                            /**< Bit mask for ADC_APORT3YCONFLICT */
+#define _ADC_APORTCONFLICT_APORT3YCONFLICT_DEFAULT         0x00000000UL                                      /**< Mode DEFAULT for ADC_APORTCONFLICT */
+#define ADC_APORTCONFLICT_APORT3YCONFLICT_DEFAULT          (_ADC_APORTCONFLICT_APORT3YCONFLICT_DEFAULT << 7) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */
+#define ADC_APORTCONFLICT_APORT4XCONFLICT                  (0x1UL << 8)                                      /**< 1 if the bus connected to APORT4X is in conflict with another peripheral */
+#define _ADC_APORTCONFLICT_APORT4XCONFLICT_SHIFT           8                                                 /**< Shift value for ADC_APORT4XCONFLICT */
+#define _ADC_APORTCONFLICT_APORT4XCONFLICT_MASK            0x100UL                                           /**< Bit mask for ADC_APORT4XCONFLICT */
+#define _ADC_APORTCONFLICT_APORT4XCONFLICT_DEFAULT         0x00000000UL                                      /**< Mode DEFAULT for ADC_APORTCONFLICT */
+#define ADC_APORTCONFLICT_APORT4XCONFLICT_DEFAULT          (_ADC_APORTCONFLICT_APORT4XCONFLICT_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */
+#define ADC_APORTCONFLICT_APORT4YCONFLICT                  (0x1UL << 9)                                      /**< 1 if the bus connected to APORT4Y is in conflict with another peripheral */
+#define _ADC_APORTCONFLICT_APORT4YCONFLICT_SHIFT           9                                                 /**< Shift value for ADC_APORT4YCONFLICT */
+#define _ADC_APORTCONFLICT_APORT4YCONFLICT_MASK            0x200UL                                           /**< Bit mask for ADC_APORT4YCONFLICT */
+#define _ADC_APORTCONFLICT_APORT4YCONFLICT_DEFAULT         0x00000000UL                                      /**< Mode DEFAULT for ADC_APORTCONFLICT */
+#define ADC_APORTCONFLICT_APORT4YCONFLICT_DEFAULT          (_ADC_APORTCONFLICT_APORT4YCONFLICT_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */
+
+/* Bit fields for ADC SINGLEFIFOCOUNT */
+#define _ADC_SINGLEFIFOCOUNT_RESETVALUE                    0x00000000UL                                 /**< Default value for ADC_SINGLEFIFOCOUNT */
+#define _ADC_SINGLEFIFOCOUNT_MASK                          0x00000007UL                                 /**< Mask for ADC_SINGLEFIFOCOUNT */
+#define _ADC_SINGLEFIFOCOUNT_SINGLEDC_SHIFT                0                                            /**< Shift value for ADC_SINGLEDC */
+#define _ADC_SINGLEFIFOCOUNT_SINGLEDC_MASK                 0x7UL                                        /**< Bit mask for ADC_SINGLEDC */
+#define _ADC_SINGLEFIFOCOUNT_SINGLEDC_DEFAULT              0x00000000UL                                 /**< Mode DEFAULT for ADC_SINGLEFIFOCOUNT */
+#define ADC_SINGLEFIFOCOUNT_SINGLEDC_DEFAULT               (_ADC_SINGLEFIFOCOUNT_SINGLEDC_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLEFIFOCOUNT */
+
+/* Bit fields for ADC SCANFIFOCOUNT */
+#define _ADC_SCANFIFOCOUNT_RESETVALUE                      0x00000000UL                             /**< Default value for ADC_SCANFIFOCOUNT */
+#define _ADC_SCANFIFOCOUNT_MASK                            0x00000007UL                             /**< Mask for ADC_SCANFIFOCOUNT */
+#define _ADC_SCANFIFOCOUNT_SCANDC_SHIFT                    0                                        /**< Shift value for ADC_SCANDC */
+#define _ADC_SCANFIFOCOUNT_SCANDC_MASK                     0x7UL                                    /**< Bit mask for ADC_SCANDC */
+#define _ADC_SCANFIFOCOUNT_SCANDC_DEFAULT                  0x00000000UL                             /**< Mode DEFAULT for ADC_SCANFIFOCOUNT */
+#define ADC_SCANFIFOCOUNT_SCANDC_DEFAULT                   (_ADC_SCANFIFOCOUNT_SCANDC_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANFIFOCOUNT */
+
+/* Bit fields for ADC SINGLEFIFOCLEAR */
+#define _ADC_SINGLEFIFOCLEAR_RESETVALUE                    0x00000000UL                                        /**< Default value for ADC_SINGLEFIFOCLEAR */
+#define _ADC_SINGLEFIFOCLEAR_MASK                          0x00000001UL                                        /**< Mask for ADC_SINGLEFIFOCLEAR */
+#define ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR                (0x1UL << 0)                                        /**< Clear Single FIFO content */
+#define _ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR_SHIFT         0                                                   /**< Shift value for ADC_SINGLEFIFOCLEAR */
+#define _ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR_MASK          0x1UL                                               /**< Bit mask for ADC_SINGLEFIFOCLEAR */
+#define _ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR_DEFAULT       0x00000000UL                                        /**< Mode DEFAULT for ADC_SINGLEFIFOCLEAR */
+#define ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR_DEFAULT        (_ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLEFIFOCLEAR */
+
+/* Bit fields for ADC SCANFIFOCLEAR */
+#define _ADC_SCANFIFOCLEAR_RESETVALUE                      0x00000000UL                                    /**< Default value for ADC_SCANFIFOCLEAR */
+#define _ADC_SCANFIFOCLEAR_MASK                            0x00000001UL                                    /**< Mask for ADC_SCANFIFOCLEAR */
+#define ADC_SCANFIFOCLEAR_SCANFIFOCLEAR                    (0x1UL << 0)                                    /**< Clear Scan FIFO content */
+#define _ADC_SCANFIFOCLEAR_SCANFIFOCLEAR_SHIFT             0                                               /**< Shift value for ADC_SCANFIFOCLEAR */
+#define _ADC_SCANFIFOCLEAR_SCANFIFOCLEAR_MASK              0x1UL                                           /**< Bit mask for ADC_SCANFIFOCLEAR */
+#define _ADC_SCANFIFOCLEAR_SCANFIFOCLEAR_DEFAULT           0x00000000UL                                    /**< Mode DEFAULT for ADC_SCANFIFOCLEAR */
+#define ADC_SCANFIFOCLEAR_SCANFIFOCLEAR_DEFAULT            (_ADC_SCANFIFOCLEAR_SCANFIFOCLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANFIFOCLEAR */
+
+/* Bit fields for ADC APORTMASTERDIS */
+#define _ADC_APORTMASTERDIS_RESETVALUE                     0x00000000UL                                        /**< Default value for ADC_APORTMASTERDIS */
+#define _ADC_APORTMASTERDIS_MASK                           0x000003FCUL                                        /**< Mask for ADC_APORTMASTERDIS */
+#define ADC_APORTMASTERDIS_APORT1XMASTERDIS                (0x1UL << 2)                                        /**< APORT1X Master Disable */
+#define _ADC_APORTMASTERDIS_APORT1XMASTERDIS_SHIFT         2                                                   /**< Shift value for ADC_APORT1XMASTERDIS */
+#define _ADC_APORTMASTERDIS_APORT1XMASTERDIS_MASK          0x4UL                                               /**< Bit mask for ADC_APORT1XMASTERDIS */
+#define _ADC_APORTMASTERDIS_APORT1XMASTERDIS_DEFAULT       0x00000000UL                                        /**< Mode DEFAULT for ADC_APORTMASTERDIS */
+#define ADC_APORTMASTERDIS_APORT1XMASTERDIS_DEFAULT        (_ADC_APORTMASTERDIS_APORT1XMASTERDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */
+#define ADC_APORTMASTERDIS_APORT1YMASTERDIS                (0x1UL << 3)                                        /**< APORT1Y Master Disable */
+#define _ADC_APORTMASTERDIS_APORT1YMASTERDIS_SHIFT         3                                                   /**< Shift value for ADC_APORT1YMASTERDIS */
+#define _ADC_APORTMASTERDIS_APORT1YMASTERDIS_MASK          0x8UL                                               /**< Bit mask for ADC_APORT1YMASTERDIS */
+#define _ADC_APORTMASTERDIS_APORT1YMASTERDIS_DEFAULT       0x00000000UL                                        /**< Mode DEFAULT for ADC_APORTMASTERDIS */
+#define ADC_APORTMASTERDIS_APORT1YMASTERDIS_DEFAULT        (_ADC_APORTMASTERDIS_APORT1YMASTERDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */
+#define ADC_APORTMASTERDIS_APORT2XMASTERDIS                (0x1UL << 4)                                        /**< APORT2X Master Disable */
+#define _ADC_APORTMASTERDIS_APORT2XMASTERDIS_SHIFT         4                                                   /**< Shift value for ADC_APORT2XMASTERDIS */
+#define _ADC_APORTMASTERDIS_APORT2XMASTERDIS_MASK          0x10UL                                              /**< Bit mask for ADC_APORT2XMASTERDIS */
+#define _ADC_APORTMASTERDIS_APORT2XMASTERDIS_DEFAULT       0x00000000UL                                        /**< Mode DEFAULT for ADC_APORTMASTERDIS */
+#define ADC_APORTMASTERDIS_APORT2XMASTERDIS_DEFAULT        (_ADC_APORTMASTERDIS_APORT2XMASTERDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */
+#define ADC_APORTMASTERDIS_APORT2YMASTERDIS                (0x1UL << 5)                                        /**< APORT2Y Master Disable */
+#define _ADC_APORTMASTERDIS_APORT2YMASTERDIS_SHIFT         5                                                   /**< Shift value for ADC_APORT2YMASTERDIS */
+#define _ADC_APORTMASTERDIS_APORT2YMASTERDIS_MASK          0x20UL                                              /**< Bit mask for ADC_APORT2YMASTERDIS */
+#define _ADC_APORTMASTERDIS_APORT2YMASTERDIS_DEFAULT       0x00000000UL                                        /**< Mode DEFAULT for ADC_APORTMASTERDIS */
+#define ADC_APORTMASTERDIS_APORT2YMASTERDIS_DEFAULT        (_ADC_APORTMASTERDIS_APORT2YMASTERDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */
+#define ADC_APORTMASTERDIS_APORT3XMASTERDIS                (0x1UL << 6)                                        /**< APORT3X Master Disable */
+#define _ADC_APORTMASTERDIS_APORT3XMASTERDIS_SHIFT         6                                                   /**< Shift value for ADC_APORT3XMASTERDIS */
+#define _ADC_APORTMASTERDIS_APORT3XMASTERDIS_MASK          0x40UL                                              /**< Bit mask for ADC_APORT3XMASTERDIS */
+#define _ADC_APORTMASTERDIS_APORT3XMASTERDIS_DEFAULT       0x00000000UL                                        /**< Mode DEFAULT for ADC_APORTMASTERDIS */
+#define ADC_APORTMASTERDIS_APORT3XMASTERDIS_DEFAULT        (_ADC_APORTMASTERDIS_APORT3XMASTERDIS_DEFAULT << 6) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */
+#define ADC_APORTMASTERDIS_APORT3YMASTERDIS                (0x1UL << 7)                                        /**< APORT3Y Master Disable */
+#define _ADC_APORTMASTERDIS_APORT3YMASTERDIS_SHIFT         7                                                   /**< Shift value for ADC_APORT3YMASTERDIS */
+#define _ADC_APORTMASTERDIS_APORT3YMASTERDIS_MASK          0x80UL                                              /**< Bit mask for ADC_APORT3YMASTERDIS */
+#define _ADC_APORTMASTERDIS_APORT3YMASTERDIS_DEFAULT       0x00000000UL                                        /**< Mode DEFAULT for ADC_APORTMASTERDIS */
+#define ADC_APORTMASTERDIS_APORT3YMASTERDIS_DEFAULT        (_ADC_APORTMASTERDIS_APORT3YMASTERDIS_DEFAULT << 7) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */
+#define ADC_APORTMASTERDIS_APORT4XMASTERDIS                (0x1UL << 8)                                        /**< APORT4X Master Disable */
+#define _ADC_APORTMASTERDIS_APORT4XMASTERDIS_SHIFT         8                                                   /**< Shift value for ADC_APORT4XMASTERDIS */
+#define _ADC_APORTMASTERDIS_APORT4XMASTERDIS_MASK          0x100UL                                             /**< Bit mask for ADC_APORT4XMASTERDIS */
+#define _ADC_APORTMASTERDIS_APORT4XMASTERDIS_DEFAULT       0x00000000UL                                        /**< Mode DEFAULT for ADC_APORTMASTERDIS */
+#define ADC_APORTMASTERDIS_APORT4XMASTERDIS_DEFAULT        (_ADC_APORTMASTERDIS_APORT4XMASTERDIS_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */
+#define ADC_APORTMASTERDIS_APORT4YMASTERDIS                (0x1UL << 9)                                        /**< APORT4Y Master Disable */
+#define _ADC_APORTMASTERDIS_APORT4YMASTERDIS_SHIFT         9                                                   /**< Shift value for ADC_APORT4YMASTERDIS */
+#define _ADC_APORTMASTERDIS_APORT4YMASTERDIS_MASK          0x200UL                                             /**< Bit mask for ADC_APORT4YMASTERDIS */
+#define _ADC_APORTMASTERDIS_APORT4YMASTERDIS_DEFAULT       0x00000000UL                                        /**< Mode DEFAULT for ADC_APORTMASTERDIS */
+#define ADC_APORTMASTERDIS_APORT4YMASTERDIS_DEFAULT        (_ADC_APORTMASTERDIS_APORT4YMASTERDIS_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */
+
+/** @} End of group EFM32PG1B_ADC */
+/** @} End of group Parts */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG_STK3401/efm32pg1b_af_pins.h	Fri Jan 15 07:45:16 2016 +0000
@@ -0,0 +1,102 @@
+/**************************************************************************//**
+ * @file efm32pg1b_af_pins.h
+ * @brief EFM32PG1B_AF_PINS register and bit field definitions
+ * @version 4.2.0
+ ******************************************************************************
+ * @section License
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ ******************************************************************************
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software.@n
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.@n
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is
+ * providing the Software "AS IS", with no express or implied warranties of any
+ * kind, including, but not limited to, any implied warranties of
+ * merchantability or fitness for any particular purpose or warranties against
+ * infringement of any proprietary rights of a third party.
+ *
+ * Silicon Laboratories, Inc. will not be liable for any consequential,
+ * incidental, or special damages, or any other relief, or for any claim by
+ * any third party, arising from your use of this Software.
+ *
+ *****************************************************************************/
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFM32PG1B_AF_Pins
+ * @{
+ *****************************************************************************/
+
+/** AF pin number for location number i */
+#define AF_CMU_CLK0_PIN(i)         ((i) == 0 ? 1 : (i) == 1 ? 15 : (i) == 2 ? 6 : (i) == 3 ? 11 : (i) == 4 ? 9 : (i) == 5 ? 14 : (i) == 6 ? 2 : (i) == 7 ? 7 :  -1)
+#define AF_CMU_CLK1_PIN(i)         ((i) == 0 ? 0 : (i) == 1 ? 14 : (i) == 2 ? 7 : (i) == 3 ? 10 : (i) == 4 ? 10 : (i) == 5 ? 15 : (i) == 6 ? 3 : (i) == 7 ? 6 :  -1)
+#define AF_PRS_CH0_PIN(i)          ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 :  -1)
+#define AF_PRS_CH1_PIN(i)          ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 7 : (i) == 7 ? 0 :  -1)
+#define AF_PRS_CH2_PIN(i)          ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 6 : (i) == 5 ? 7 : (i) == 6 ? 0 : (i) == 7 ? 1 :  -1)
+#define AF_PRS_CH3_PIN(i)          ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 6 : (i) == 4 ? 7 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 2 : (i) == 8 ? 9 : (i) == 9 ? 10 : (i) == 10 ? 11 : (i) == 11 ? 12 : (i) == 12 ? 13 : (i) == 13 ? 14 : (i) == 14 ? 15 :  -1)
+#define AF_PRS_CH4_PIN(i)          ((i) == 0 ? 9 : (i) == 1 ? 10 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 15 :  -1)
+#define AF_PRS_CH5_PIN(i)          ((i) == 0 ? 10 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 13 : (i) == 4 ? 14 : (i) == 5 ? 15 : (i) == 6 ? 9 :  -1)
+#define AF_PRS_CH6_PIN(i)          ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 12 : (i) == 15 ? 13 : (i) == 16 ? 14 : (i) == 17 ? 15 :  -1)
+#define AF_PRS_CH7_PIN(i)          ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 0 :  -1)
+#define AF_PRS_CH8_PIN(i)          ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 12 : (i) == 6 ? 13 : (i) == 7 ? 14 : (i) == 8 ? 15 : (i) == 9 ? 0 : (i) == 10 ? 1 :  -1)
+#define AF_PRS_CH9_PIN(i)          ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 0 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 :  -1)
+#define AF_PRS_CH10_PIN(i)         ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 9 : (i) == 4 ? 10 : (i) == 5 ? 11 :  -1)
+#define AF_PRS_CH11_PIN(i)         ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 9 : (i) == 3 ? 10 : (i) == 4 ? 11 : (i) == 5 ? 6 :  -1)
+#define AF_TIMER0_CC0_PIN(i)       ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 :  -1)
+#define AF_TIMER0_CC1_PIN(i)       ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 :  -1)
+#define AF_TIMER0_CC2_PIN(i)       ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 12 : (i) == 6 ? 13 : (i) == 7 ? 14 : (i) == 8 ? 15 : (i) == 9 ? 6 : (i) == 10 ? 7 : (i) == 11 ? 8 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 9 : (i) == 16 ? 10 : (i) == 17 ? 11 : (i) == 18 ? 12 : (i) == 19 ? 13 : (i) == 20 ? 14 : (i) == 21 ? 15 : (i) == 22 ? 0 : (i) == 23 ? 1 : (i) == 24 ? 2 : (i) == 25 ? 3 : (i) == 26 ? 4 : (i) == 27 ? 5 : (i) == 28 ? 6 : (i) == 29 ? 7 : (i) == 30 ? 0 : (i) == 31 ? 1 :  -1)
+#define AF_TIMER0_CC3_PIN(i)       (-1)
+#define AF_TIMER0_CDTI0_PIN(i)     ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 12 : (i) == 18 ? 13 : (i) == 19 ? 14 : (i) == 20 ? 15 : (i) == 21 ? 0 : (i) == 22 ? 1 : (i) == 23 ? 2 : (i) == 24 ? 3 : (i) == 25 ? 4 : (i) == 26 ? 5 : (i) == 27 ? 6 : (i) == 28 ? 7 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 :  -1)
+#define AF_TIMER0_CDTI1_PIN(i)     ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 15 : (i) == 7 ? 6 : (i) == 8 ? 7 : (i) == 9 ? 8 : (i) == 10 ? 9 : (i) == 11 ? 10 : (i) == 12 ? 11 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 12 : (i) == 17 ? 13 : (i) == 18 ? 14 : (i) == 19 ? 15 : (i) == 20 ? 0 : (i) == 21 ? 1 : (i) == 22 ? 2 : (i) == 23 ? 3 : (i) == 24 ? 4 : (i) == 25 ? 5 : (i) == 26 ? 6 : (i) == 27 ? 7 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 3 :  -1)
+#define AF_TIMER0_CDTI2_PIN(i)     ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 13 : (i) == 4 ? 14 : (i) == 5 ? 15 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 11 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 12 : (i) == 16 ? 13 : (i) == 17 ? 14 : (i) == 18 ? 15 : (i) == 19 ? 0 : (i) == 20 ? 1 : (i) == 21 ? 2 : (i) == 22 ? 3 : (i) == 23 ? 4 : (i) == 24 ? 5 : (i) == 25 ? 6 : (i) == 26 ? 7 : (i) == 27 ? 0 : (i) == 28 ? 1 : (i) == 29 ? 2 : (i) == 30 ? 3 : (i) == 31 ? 4 :  -1)
+#define AF_TIMER0_CDTI3_PIN(i)     (-1)
+#define AF_TIMER1_CC0_PIN(i)       ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 :  -1)
+#define AF_TIMER1_CC1_PIN(i)       ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 :  -1)
+#define AF_TIMER1_CC2_PIN(i)       ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 12 : (i) == 6 ? 13 : (i) == 7 ? 14 : (i) == 8 ? 15 : (i) == 9 ? 6 : (i) == 10 ? 7 : (i) == 11 ? 8 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 9 : (i) == 16 ? 10 : (i) == 17 ? 11 : (i) == 18 ? 12 : (i) == 19 ? 13 : (i) == 20 ? 14 : (i) == 21 ? 15 : (i) == 22 ? 0 : (i) == 23 ? 1 : (i) == 24 ? 2 : (i) == 25 ? 3 : (i) == 26 ? 4 : (i) == 27 ? 5 : (i) == 28 ? 6 : (i) == 29 ? 7 : (i) == 30 ? 0 : (i) == 31 ? 1 :  -1)
+#define AF_TIMER1_CC3_PIN(i)       ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 12 : (i) == 18 ? 13 : (i) == 19 ? 14 : (i) == 20 ? 15 : (i) == 21 ? 0 : (i) == 22 ? 1 : (i) == 23 ? 2 : (i) == 24 ? 3 : (i) == 25 ? 4 : (i) == 26 ? 5 : (i) == 27 ? 6 : (i) == 28 ? 7 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 :  -1)
+#define AF_TIMER1_CDTI0_PIN(i)     (-1)
+#define AF_TIMER1_CDTI1_PIN(i)     (-1)
+#define AF_TIMER1_CDTI2_PIN(i)     (-1)
+#define AF_TIMER1_CDTI3_PIN(i)     (-1)
+#define AF_USART0_TX_PIN(i)        ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 :  -1)
+#define AF_USART0_RX_PIN(i)        ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 :  -1)
+#define AF_USART0_CLK_PIN(i)       ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 12 : (i) == 6 ? 13 : (i) == 7 ? 14 : (i) == 8 ? 15 : (i) == 9 ? 6 : (i) == 10 ? 7 : (i) == 11 ? 8 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 9 : (i) == 16 ? 10 : (i) == 17 ? 11 : (i) == 18 ? 12 : (i) == 19 ? 13 : (i) == 20 ? 14 : (i) == 21 ? 15 : (i) == 22 ? 0 : (i) == 23 ? 1 : (i) == 24 ? 2 : (i) == 25 ? 3 : (i) == 26 ? 4 : (i) == 27 ? 5 : (i) == 28 ? 6 : (i) == 29 ? 7 : (i) == 30 ? 0 : (i) == 31 ? 1 :  -1)
+#define AF_USART0_CS_PIN(i)        ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 12 : (i) == 18 ? 13 : (i) == 19 ? 14 : (i) == 20 ? 15 : (i) == 21 ? 0 : (i) == 22 ? 1 : (i) == 23 ? 2 : (i) == 24 ? 3 : (i) == 25 ? 4 : (i) == 26 ? 5 : (i) == 27 ? 6 : (i) == 28 ? 7 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 :  -1)
+#define AF_USART0_CTS_PIN(i)       ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 15 : (i) == 7 ? 6 : (i) == 8 ? 7 : (i) == 9 ? 8 : (i) == 10 ? 9 : (i) == 11 ? 10 : (i) == 12 ? 11 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 12 : (i) == 17 ? 13 : (i) == 18 ? 14 : (i) == 19 ? 15 : (i) == 20 ? 0 : (i) == 21 ? 1 : (i) == 22 ? 2 : (i) == 23 ? 3 : (i) == 24 ? 4 : (i) == 25 ? 5 : (i) == 26 ? 6 : (i) == 27 ? 7 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 3 :  -1)
+#define AF_USART0_RTS_PIN(i)       ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 13 : (i) == 4 ? 14 : (i) == 5 ? 15 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 11 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 12 : (i) == 16 ? 13 : (i) == 17 ? 14 : (i) == 18 ? 15 : (i) == 19 ? 0 : (i) == 20 ? 1 : (i) == 21 ? 2 : (i) == 22 ? 3 : (i) == 23 ? 4 : (i) == 24 ? 5 : (i) == 25 ? 6 : (i) == 26 ? 7 : (i) == 27 ? 0 : (i) == 28 ? 1 : (i) == 29 ? 2 : (i) == 30 ? 3 : (i) == 31 ? 4 :  -1)
+#define AF_USART1_TX_PIN(i)        ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 :  -1)
+#define AF_USART1_RX_PIN(i)        ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 :  -1)
+#define AF_USART1_CLK_PIN(i)       ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 12 : (i) == 6 ? 13 : (i) == 7 ? 14 : (i) == 8 ? 15 : (i) == 9 ? 6 : (i) == 10 ? 7 : (i) == 11 ? 8 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 9 : (i) == 16 ? 10 : (i) == 17 ? 11 : (i) == 18 ? 12 : (i) == 19 ? 13 : (i) == 20 ? 14 : (i) == 21 ? 15 : (i) == 22 ? 0 : (i) == 23 ? 1 : (i) == 24 ? 2 : (i) == 25 ? 3 : (i) == 26 ? 4 : (i) == 27 ? 5 : (i) == 28 ? 6 : (i) == 29 ? 7 : (i) == 30 ? 0 : (i) == 31 ? 1 :  -1)
+#define AF_USART1_CS_PIN(i)        ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 12 : (i) == 18 ? 13 : (i) == 19 ? 14 : (i) == 20 ? 15 : (i) == 21 ? 0 : (i) == 22 ? 1 : (i) == 23 ? 2 : (i) == 24 ? 3 : (i) == 25 ? 4 : (i) == 26 ? 5 : (i) == 27 ? 6 : (i) == 28 ? 7 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 :  -1)
+#define AF_USART1_CTS_PIN(i)       ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 15 : (i) == 7 ? 6 : (i) == 8 ? 7 : (i) == 9 ? 8 : (i) == 10 ? 9 : (i) == 11 ? 10 : (i) == 12 ? 11 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 12 : (i) == 17 ? 13 : (i) == 18 ? 14 : (i) == 19 ? 15 : (i) == 20 ? 0 : (i) == 21 ? 1 : (i) == 22 ? 2 : (i) == 23 ? 3 : (i) == 24 ? 4 : (i) == 25 ? 5 : (i) == 26 ? 6 : (i) == 27 ? 7 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 3 :  -1)
+#define AF_USART1_RTS_PIN(i)       ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 13 : (i) == 4 ? 14 : (i) == 5 ? 15 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 11 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 12 : (i) == 16 ? 13 : (i) == 17 ? 14 : (i) == 18 ? 15 : (i) == 19 ? 0 : (i) == 20 ? 1 : (i) == 21 ? 2 : (i) == 22 ? 3 : (i) == 23 ? 4 : (i) == 24 ? 5 : (i) == 25 ? 6 : (i) == 26 ? 7 : (i) == 27 ? 0 : (i) == 28 ? 1 : (i) == 29 ? 2 : (i) == 30 ? 3 : (i) == 31 ? 4 :  -1)
+#define AF_LEUART0_TX_PIN(i)       ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 :  -1)
+#define AF_LEUART0_RX_PIN(i)       ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 :  -1)
+#define AF_LETIMER0_OUT0_PIN(i)    ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 :  -1)
+#define AF_LETIMER0_OUT1_PIN(i)    ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 :  -1)
+#define AF_PCNT0_S0IN_PIN(i)       ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 :  -1)
+#define AF_PCNT0_S1IN_PIN(i)       ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 :  -1)
+#define AF_I2C0_SDA_PIN(i)         ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 :  -1)
+#define AF_I2C0_SCL_PIN(i)         ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 :  -1)
+#define AF_ACMP0_OUT_PIN(i)        ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 :  -1)
+#define AF_ACMP1_OUT_PIN(i)        ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 :  -1)
+#define AF_DBG_TDI_PIN(i)          ((i) == 0 ? 3 :  -1)
+#define AF_DBG_TDO_PIN(i)          ((i) == 0 ? 2 :  -1)
+#define AF_DBG_SWV_PIN(i)          ((i) == 0 ? 2 : (i) == 1 ? 13 : (i) == 2 ? 15 : (i) == 3 ? 11 :  -1)
+#define AF_DBG_SWDIOTMS_PIN(i)     ((i) == 0 ? 1 :  -1)
+#define AF_DBG_SWCLKTCK_PIN(i)     ((i) == 0 ? 0 :  -1)
+
+/** @} End of group EFM32PG1B_AF_Pins */
+/** @} End of group Parts */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG_STK3401/efm32pg1b_af_ports.h	Fri Jan 15 07:45:16 2016 +0000
@@ -0,0 +1,102 @@
+/**************************************************************************//**
+ * @file efm32pg1b_af_ports.h
+ * @brief EFM32PG1B_AF_PORTS register and bit field definitions
+ * @version 4.2.0
+ ******************************************************************************
+ * @section License
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ ******************************************************************************
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software.@n
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.@n
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is
+ * providing the Software "AS IS", with no express or implied warranties of any
+ * kind, including, but not limited to, any implied warranties of
+ * merchantability or fitness for any particular purpose or warranties against
+ * infringement of any proprietary rights of a third party.
+ *
+ * Silicon Laboratories, Inc. will not be liable for any consequential,
+ * incidental, or special damages, or any other relief, or for any claim by
+ * any third party, arising from your use of this Software.
+ *
+ *****************************************************************************/
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFM32PG1B_AF_Ports
+ * @{
+ *****************************************************************************/
+
+/** AF port number for location number i */
+#define AF_CMU_CLK0_PORT(i)         ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 5 : (i) == 7 ? 5 :  -1)
+#define AF_CMU_CLK1_PORT(i)         ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 5 : (i) == 7 ? 5 :  -1)
+#define AF_PRS_CH0_PORT(i)          ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 :  -1)
+#define AF_PRS_CH1_PORT(i)          ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 :  -1)
+#define AF_PRS_CH2_PORT(i)          ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 :  -1)
+#define AF_PRS_CH3_PORT(i)          ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : (i) == 8 ? 3 : (i) == 9 ? 3 : (i) == 10 ? 3 : (i) == 11 ? 3 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 :  -1)
+#define AF_PRS_CH4_PORT(i)          ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 3 :  -1)
+#define AF_PRS_CH5_PORT(i)          ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 3 :  -1)
+#define AF_PRS_CH6_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 3 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 :  -1)
+#define AF_PRS_CH7_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 0 :  -1)
+#define AF_PRS_CH8_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 0 : (i) == 10 ? 0 :  -1)
+#define AF_PRS_CH9_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 0 : (i) == 9 ? 0 : (i) == 10 ? 0 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 :  -1)
+#define AF_PRS_CH10_PORT(i)         ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 2 :  -1)
+#define AF_PRS_CH11_PORT(i)         ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 2 :  -1)
+#define AF_TIMER0_CC0_PORT(i)       ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 :  -1)
+#define AF_TIMER0_CC1_PORT(i)       ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 :  -1)
+#define AF_TIMER0_CC2_PORT(i)       ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 0 : (i) == 31 ? 0 :  -1)
+#define AF_TIMER0_CC3_PORT(i)       (-1)
+#define AF_TIMER0_CDTI0_PORT(i)     ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 :  -1)
+#define AF_TIMER0_CDTI1_PORT(i)     ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 :  -1)
+#define AF_TIMER0_CDTI2_PORT(i)     ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 2 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 0 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 :  -1)
+#define AF_TIMER0_CDTI3_PORT(i)     (-1)
+#define AF_TIMER1_CC0_PORT(i)       ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 :  -1)
+#define AF_TIMER1_CC1_PORT(i)       ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 :  -1)
+#define AF_TIMER1_CC2_PORT(i)       ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 0 : (i) == 31 ? 0 :  -1)
+#define AF_TIMER1_CC3_PORT(i)       ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 :  -1)
+#define AF_TIMER1_CDTI0_PORT(i)     (-1)
+#define AF_TIMER1_CDTI1_PORT(i)     (-1)
+#define AF_TIMER1_CDTI2_PORT(i)     (-1)
+#define AF_TIMER1_CDTI3_PORT(i)     (-1)
+#define AF_USART0_TX_PORT(i)        ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 :  -1)
+#define AF_USART0_RX_PORT(i)        ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 :  -1)
+#define AF_USART0_CLK_PORT(i)       ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 0 : (i) == 31 ? 0 :  -1)
+#define AF_USART0_CS_PORT(i)        ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 :  -1)
+#define AF_USART0_CTS_PORT(i)       ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 :  -1)
+#define AF_USART0_RTS_PORT(i)       ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 2 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 0 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 :  -1)
+#define AF_USART1_TX_PORT(i)        ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 :  -1)
+#define AF_USART1_RX_PORT(i)        ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 :  -1)
+#define AF_USART1_CLK_PORT(i)       ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 0 : (i) == 31 ? 0 :  -1)
+#define AF_USART1_CS_PORT(i)        ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 :  -1)
+#define AF_USART1_CTS_PORT(i)       ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 :  -1)
+#define AF_USART1_RTS_PORT(i)       ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 2 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 0 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 :  -1)
+#define AF_LEUART0_TX_PORT(i)       ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 :  -1)
+#define AF_LEUART0_RX_PORT(i)       ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 :  -1)
+#define AF_LETIMER0_OUT0_PORT(i)    ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 :  -1)
+#define AF_LETIMER0_OUT1_PORT(i)    ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 :  -1)
+#define AF_PCNT0_S0IN_PORT(i)       ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 :  -1)
+#define AF_PCNT0_S1IN_PORT(i)       ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 :  -1)
+#define AF_I2C0_SDA_PORT(i)         ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 :  -1)
+#define AF_I2C0_SCL_PORT(i)         ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 :  -1)
+#define AF_ACMP0_OUT_PORT(i)        ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 :  -1)
+#define AF_ACMP1_OUT_PORT(i)        ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 :  -1)
+#define AF_DBG_TDI_PORT(i)          ((i) == 0 ? 5 :  -1)
+#define AF_DBG_TDO_PORT(i)          ((i) == 0 ? 5 :  -1)
+#define AF_DBG_SWV_PORT(i)          ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 2 :  -1)
+#define AF_DBG_SWDIOTMS_PORT(i)     ((i) == 0 ? 5 :  -1)
+#define AF_DBG_SWCLKTCK_PORT(i)     ((i) == 0 ? 5 :  -1)
+
+/** @} End of group EFM32PG1B_AF_Ports */
+/** @} End of group Parts */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG_STK3401/efm32pg1b_cmu.h	Fri Jan 15 07:45:16 2016 +0000
@@ -0,0 +1,1781 @@
+/**************************************************************************//**
+ * @file efm32pg1b_cmu.h
+ * @brief EFM32PG1B_CMU register and bit field definitions
+ * @version 4.2.0
+ ******************************************************************************
+ * @section License
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ ******************************************************************************
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software.@n
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.@n
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is
+ * providing the Software "AS IS", with no express or implied warranties of any
+ * kind, including, but not limited to, any implied warranties of
+ * merchantability or fitness for any particular purpose or warranties against
+ * infringement of any proprietary rights of a third party.
+ *
+ * Silicon Laboratories, Inc. will not be liable for any consequential,
+ * incidental, or special damages, or any other relief, or for any claim by
+ * any third party, arising from your use of this Software.
+ *
+ *****************************************************************************/
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFM32PG1B_CMU
+ * @{
+ * @brief EFM32PG1B_CMU Register Declaration
+ *****************************************************************************/
+typedef struct
+{
+  __IO uint32_t CTRL;                /**< CMU Control Register  */
+
+  uint32_t      RESERVED0[3];        /**< Reserved for future use **/
+  __IO uint32_t HFRCOCTRL;           /**< HFRCO Control Register  */
+
+  uint32_t      RESERVED1[1];        /**< Reserved for future use **/
+  __IO uint32_t AUXHFRCOCTRL;        /**< AUXHFRCO Control Register  */
+
+  uint32_t      RESERVED2[1];        /**< Reserved for future use **/
+  __IO uint32_t LFRCOCTRL;           /**< LFRCO Control Register  */
+  __IO uint32_t HFXOCTRL;            /**< HFXO Control Register  */
+  __IO uint32_t HFXOCTRL1;           /**< HFXO Control 1  */
+  __IO uint32_t HFXOSTARTUPCTRL;     /**< HFXO Startup Control  */
+  __IO uint32_t HFXOSTEADYSTATECTRL; /**< HFXO Steady State control  */
+  __IO uint32_t HFXOTIMEOUTCTRL;     /**< HFXO Timeout Control  */
+  __IO uint32_t LFXOCTRL;            /**< LFXO Control Register  */
+
+  uint32_t      RESERVED3[5];        /**< Reserved for future use **/
+  __IO uint32_t CALCTRL;             /**< Calibration Control Register  */
+  __IO uint32_t CALCNT;              /**< Calibration Counter Register  */
+  uint32_t      RESERVED4[2];        /**< Reserved for future use **/
+  __IO uint32_t OSCENCMD;            /**< Oscillator Enable/Disable Command Register  */
+  __IO uint32_t CMD;                 /**< Command Register  */
+  uint32_t      RESERVED5[2];        /**< Reserved for future use **/
+  __IO uint32_t DBGCLKSEL;           /**< Debug Trace Clock Select  */
+  __IO uint32_t HFCLKSEL;            /**< High Frequency Clock Select Command Register  */
+  uint32_t      RESERVED6[2];        /**< Reserved for future use **/
+  __IO uint32_t LFACLKSEL;           /**< Low Frequency A Clock Select Register  */
+  __IO uint32_t LFBCLKSEL;           /**< Low Frequency B Clock Select Register  */
+  __IO uint32_t LFECLKSEL;           /**< Low Frequency E Clock Select Register  */
+
+  uint32_t      RESERVED7[1];        /**< Reserved for future use **/
+  __I uint32_t  STATUS;              /**< Status Register  */
+  __I uint32_t  HFCLKSTATUS;         /**< HFCLK Status Register  */
+  uint32_t      RESERVED8[1];        /**< Reserved for future use **/
+  __I uint32_t  HFXOTRIMSTATUS;      /**< HFXO Trim Status  */
+  __I uint32_t  IF;                  /**< Interrupt Flag Register  */
+  __IO uint32_t IFS;                 /**< Interrupt Flag Set Register  */
+  __IO uint32_t IFC;                 /**< Interrupt Flag Clear Register  */
+  __IO uint32_t IEN;                 /**< Interrupt Enable Register  */
+  __IO uint32_t HFBUSCLKEN0;         /**< High Frequency Bus Clock Enable Register 0  */
+
+  uint32_t      RESERVED9[3];        /**< Reserved for future use **/
+  __IO uint32_t HFPERCLKEN0;         /**< High Frequency Peripheral Clock Enable Register 0  */
+
+  uint32_t      RESERVED10[7];       /**< Reserved for future use **/
+  __IO uint32_t LFACLKEN0;           /**< Low Frequency A Clock Enable Register 0  (Async Reg)  */
+  uint32_t      RESERVED11[1];       /**< Reserved for future use **/
+  __IO uint32_t LFBCLKEN0;           /**< Low Frequency B Clock Enable Register 0 (Async Reg)  */
+  uint32_t      RESERVED12[1];       /**< Reserved for future use **/
+  __IO uint32_t LFECLKEN0;           /**< Low Frequency E Clock Enable Register 0 (Async Reg)  */
+
+  uint32_t      RESERVED13[3];       /**< Reserved for future use **/
+  __IO uint32_t HFPRESC;             /**< High Frequency Clock Prescaler Register  */
+
+  uint32_t      RESERVED14[1];       /**< Reserved for future use **/
+  __IO uint32_t HFCOREPRESC;         /**< High Frequency Core Clock Prescaler Register  */
+  __IO uint32_t HFPERPRESC;          /**< High Frequency Peripheral Clock Prescaler Register  */
+
+  uint32_t      RESERVED15[1];       /**< Reserved for future use **/
+  __IO uint32_t HFEXPPRESC;          /**< High Frequency Export Clock Prescaler Register  */
+
+  uint32_t      RESERVED16[2];       /**< Reserved for future use **/
+  __IO uint32_t LFAPRESC0;           /**< Low Frequency A Prescaler Register 0 (Async Reg)  */
+  uint32_t      RESERVED17[1];       /**< Reserved for future use **/
+  __IO uint32_t LFBPRESC0;           /**< Low Frequency B Prescaler Register 0  (Async Reg)  */
+  uint32_t      RESERVED18[1];       /**< Reserved for future use **/
+  __IO uint32_t LFEPRESC0;           /**< Low Frequency E Prescaler Register 0  (Async Reg)  */
+  uint32_t      RESERVED19[3];       /**< Reserved for future use **/
+  __I uint32_t  SYNCBUSY;            /**< Synchronization Busy Register  */
+  __IO uint32_t FREEZE;              /**< Freeze Register  */
+  uint32_t      RESERVED20[2];       /**< Reserved for future use **/
+  __IO uint32_t PCNTCTRL;            /**< PCNT Control Register  */
+
+  uint32_t      RESERVED21[2];       /**< Reserved for future use **/
+  __IO uint32_t ADCCTRL;             /**< ADC Control Register  */
+  uint32_t      RESERVED22[4];       /**< Reserved for future use **/
+  __IO uint32_t ROUTEPEN;            /**< I/O Routing Pin Enable Register  */
+  __IO uint32_t ROUTELOC0;           /**< I/O Routing Location Register  */
+
+  uint32_t      RESERVED23[2];       /**< Reserved for future use **/
+  __IO uint32_t LOCK;                /**< Configuration Lock Register  */
+} CMU_TypeDef;                       /** @} */
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B_CMU_BitFields
+ * @{
+ *****************************************************************************/
+
+/* Bit fields for CMU CTRL */
+#define _CMU_CTRL_RESETVALUE                                0x00300000UL                          /**< Default value for CMU_CTRL */
+#define _CMU_CTRL_MASK                                      0x001101EFUL                          /**< Mask for CMU_CTRL */
+#define _CMU_CTRL_CLKOUTSEL0_SHIFT                          0                                     /**< Shift value for CMU_CLKOUTSEL0 */
+#define _CMU_CTRL_CLKOUTSEL0_MASK                           0xFUL                                 /**< Bit mask for CMU_CLKOUTSEL0 */
+#define _CMU_CTRL_CLKOUTSEL0_DEFAULT                        0x00000000UL                          /**< Mode DEFAULT for CMU_CTRL */
+#define _CMU_CTRL_CLKOUTSEL0_DISABLED                       0x00000000UL                          /**< Mode DISABLED for CMU_CTRL */
+#define _CMU_CTRL_CLKOUTSEL0_ULFRCO                         0x00000001UL                          /**< Mode ULFRCO for CMU_CTRL */
+#define _CMU_CTRL_CLKOUTSEL0_LFRCO                          0x00000002UL                          /**< Mode LFRCO for CMU_CTRL */
+#define _CMU_CTRL_CLKOUTSEL0_LFXO                           0x00000003UL                          /**< Mode LFXO for CMU_CTRL */
+#define _CMU_CTRL_CLKOUTSEL0_HFXO                           0x00000006UL                          /**< Mode HFXO for CMU_CTRL */
+#define _CMU_CTRL_CLKOUTSEL0_HFEXPCLK                       0x00000007UL                          /**< Mode HFEXPCLK for CMU_CTRL */
+#define _CMU_CTRL_CLKOUTSEL0_ULFRCOQ                        0x00000009UL                          /**< Mode ULFRCOQ for CMU_CTRL */
+#define _CMU_CTRL_CLKOUTSEL0_LFRCOQ                         0x0000000AUL                          /**< Mode LFRCOQ for CMU_CTRL */
+#define _CMU_CTRL_CLKOUTSEL0_LFXOQ                          0x0000000BUL                          /**< Mode LFXOQ for CMU_CTRL */
+#define _CMU_CTRL_CLKOUTSEL0_HFRCOQ                         0x0000000CUL                          /**< Mode HFRCOQ for CMU_CTRL */
+#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ                      0x0000000DUL                          /**< Mode AUXHFRCOQ for CMU_CTRL */
+#define _CMU_CTRL_CLKOUTSEL0_HFXOQ                          0x0000000EUL                          /**< Mode HFXOQ for CMU_CTRL */
+#define _CMU_CTRL_CLKOUTSEL0_HFSRCCLK                       0x0000000FUL                          /**< Mode HFSRCCLK for CMU_CTRL */
+#define CMU_CTRL_CLKOUTSEL0_DEFAULT                         (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 0)   /**< Shifted mode DEFAULT for CMU_CTRL */
+#define CMU_CTRL_CLKOUTSEL0_DISABLED                        (_CMU_CTRL_CLKOUTSEL0_DISABLED << 0)  /**< Shifted mode DISABLED for CMU_CTRL */
+#define CMU_CTRL_CLKOUTSEL0_ULFRCO                          (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 0)    /**< Shifted mode ULFRCO for CMU_CTRL */
+#define CMU_CTRL_CLKOUTSEL0_LFRCO                           (_CMU_CTRL_CLKOUTSEL0_LFRCO << 0)     /**< Shifted mode LFRCO for CMU_CTRL */
+#define CMU_CTRL_CLKOUTSEL0_LFXO                            (_CMU_CTRL_CLKOUTSEL0_LFXO << 0)      /**< Shifted mode LFXO for CMU_CTRL */
+#define CMU_CTRL_CLKOUTSEL0_HFXO                            (_CMU_CTRL_CLKOUTSEL0_HFXO << 0)      /**< Shifted mode HFXO for CMU_CTRL */
+#define CMU_CTRL_CLKOUTSEL0_HFEXPCLK                        (_CMU_CTRL_CLKOUTSEL0_HFEXPCLK << 0)  /**< Shifted mode HFEXPCLK for CMU_CTRL */
+#define CMU_CTRL_CLKOUTSEL0_ULFRCOQ                         (_CMU_CTRL_CLKOUTSEL0_ULFRCOQ << 0)   /**< Shifted mode ULFRCOQ for CMU_CTRL */
+#define CMU_CTRL_CLKOUTSEL0_LFRCOQ                          (_CMU_CTRL_CLKOUTSEL0_LFRCOQ << 0)    /**< Shifted mode LFRCOQ for CMU_CTRL */
+#define CMU_CTRL_CLKOUTSEL0_LFXOQ                           (_CMU_CTRL_CLKOUTSEL0_LFXOQ << 0)     /**< Shifted mode LFXOQ for CMU_CTRL */
+#define CMU_CTRL_CLKOUTSEL0_HFRCOQ                          (_CMU_CTRL_CLKOUTSEL0_HFRCOQ << 0)    /**< Shifted mode HFRCOQ for CMU_CTRL */
+#define CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ                       (_CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ << 0) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */
+#define CMU_CTRL_CLKOUTSEL0_HFXOQ                           (_CMU_CTRL_CLKOUTSEL0_HFXOQ << 0)     /**< Shifted mode HFXOQ for CMU_CTRL */
+#define CMU_CTRL_CLKOUTSEL0_HFSRCCLK                        (_CMU_CTRL_CLKOUTSEL0_HFSRCCLK << 0)  /**< Shifted mode HFSRCCLK for CMU_CTRL */
+#define _CMU_CTRL_CLKOUTSEL1_SHIFT                          5                                     /**< Shift value for CMU_CLKOUTSEL1 */
+#define _CMU_CTRL_CLKOUTSEL1_MASK                           0x1E0UL                               /**< Bit mask for CMU_CLKOUTSEL1 */
+#define _CMU_CTRL_CLKOUTSEL1_DEFAULT                        0x00000000UL                          /**< Mode DEFAULT for CMU_CTRL */
+#define _CMU_CTRL_CLKOUTSEL1_DISABLED                       0x00000000UL                          /**< Mode DISABLED for CMU_CTRL */
+#define _CMU_CTRL_CLKOUTSEL1_ULFRCO                         0x00000001UL                          /**< Mode ULFRCO for CMU_CTRL */
+#define _CMU_CTRL_CLKOUTSEL1_LFRCO                          0x00000002UL                          /**< Mode LFRCO for CMU_CTRL */
+#define _CMU_CTRL_CLKOUTSEL1_LFXO                           0x00000003UL                          /**< Mode LFXO for CMU_CTRL */
+#define _CMU_CTRL_CLKOUTSEL1_HFXO                           0x00000006UL                          /**< Mode HFXO for CMU_CTRL */
+#define _CMU_CTRL_CLKOUTSEL1_HFEXPCLK                       0x00000007UL                          /**< Mode HFEXPCLK for CMU_CTRL */
+#define _CMU_CTRL_CLKOUTSEL1_ULFRCOQ                        0x00000009UL                          /**< Mode ULFRCOQ for CMU_CTRL */
+#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ                         0x0000000AUL                          /**< Mode LFRCOQ for CMU_CTRL */
+#define _CMU_CTRL_CLKOUTSEL1_LFXOQ                          0x0000000BUL                          /**< Mode LFXOQ for CMU_CTRL */
+#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ                         0x0000000CUL                          /**< Mode HFRCOQ for CMU_CTRL */
+#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ                      0x0000000DUL                          /**< Mode AUXHFRCOQ for CMU_CTRL */
+#define _CMU_CTRL_CLKOUTSEL1_HFXOQ                          0x0000000EUL                          /**< Mode HFXOQ for CMU_CTRL */
+#define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK                       0x0000000FUL                          /**< Mode HFSRCCLK for CMU_CTRL */
+#define CMU_CTRL_CLKOUTSEL1_DEFAULT                         (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 5)   /**< Shifted mode DEFAULT for CMU_CTRL */
+#define CMU_CTRL_CLKOUTSEL1_DISABLED                        (_CMU_CTRL_CLKOUTSEL1_DISABLED << 5)  /**< Shifted mode DISABLED for CMU_CTRL */
+#define CMU_CTRL_CLKOUTSEL1_ULFRCO                          (_CMU_CTRL_CLKOUTSEL1_ULFRCO << 5)    /**< Shifted mode ULFRCO for CMU_CTRL */
+#define CMU_CTRL_CLKOUTSEL1_LFRCO                           (_CMU_CTRL_CLKOUTSEL1_LFRCO << 5)     /**< Shifted mode LFRCO for CMU_CTRL */
+#define CMU_CTRL_CLKOUTSEL1_LFXO                            (_CMU_CTRL_CLKOUTSEL1_LFXO << 5)      /**< Shifted mode LFXO for CMU_CTRL */
+#define CMU_CTRL_CLKOUTSEL1_HFXO                            (_CMU_CTRL_CLKOUTSEL1_HFXO << 5)      /**< Shifted mode HFXO for CMU_CTRL */
+#define CMU_CTRL_CLKOUTSEL1_HFEXPCLK                        (_CMU_CTRL_CLKOUTSEL1_HFEXPCLK << 5)  /**< Shifted mode HFEXPCLK for CMU_CTRL */
+#define CMU_CTRL_CLKOUTSEL1_ULFRCOQ                         (_CMU_CTRL_CLKOUTSEL1_ULFRCOQ << 5)   /**< Shifted mode ULFRCOQ for CMU_CTRL */
+#define CMU_CTRL_CLKOUTSEL1_LFRCOQ                          (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 5)    /**< Shifted mode LFRCOQ for CMU_CTRL */
+#define CMU_CTRL_CLKOUTSEL1_LFXOQ                           (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 5)     /**< Shifted mode LFXOQ for CMU_CTRL */
+#define CMU_CTRL_CLKOUTSEL1_HFRCOQ                          (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 5)    /**< Shifted mode HFRCOQ for CMU_CTRL */
+#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ                       (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 5) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */
+#define CMU_CTRL_CLKOUTSEL1_HFXOQ                           (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 5)     /**< Shifted mode HFXOQ for CMU_CTRL */
+#define CMU_CTRL_CLKOUTSEL1_HFSRCCLK                        (_CMU_CTRL_CLKOUTSEL1_HFSRCCLK << 5)  /**< Shifted mode HFSRCCLK for CMU_CTRL */
+#define CMU_CTRL_WSHFLE                                     (0x1UL << 16)                         /**< Wait State for High-Frequency LE Interface */
+#define _CMU_CTRL_WSHFLE_SHIFT                              16                                    /**< Shift value for CMU_WSHFLE */
+#define _CMU_CTRL_WSHFLE_MASK                               0x10000UL                             /**< Bit mask for CMU_WSHFLE */
+#define _CMU_CTRL_WSHFLE_DEFAULT                            0x00000000UL                          /**< Mode DEFAULT for CMU_CTRL */
+#define CMU_CTRL_WSHFLE_DEFAULT                             (_CMU_CTRL_WSHFLE_DEFAULT << 16)      /**< Shifted mode DEFAULT for CMU_CTRL */
+#define CMU_CTRL_HFPERCLKEN                                 (0x1UL << 20)                         /**< HFPERCLK Enable */
+#define _CMU_CTRL_HFPERCLKEN_SHIFT                          20                                    /**< Shift value for CMU_HFPERCLKEN */
+#define _CMU_CTRL_HFPERCLKEN_MASK                           0x100000UL                            /**< Bit mask for CMU_HFPERCLKEN */
+#define _CMU_CTRL_HFPERCLKEN_DEFAULT                        0x00000001UL                          /**< Mode DEFAULT for CMU_CTRL */
+#define CMU_CTRL_HFPERCLKEN_DEFAULT                         (_CMU_CTRL_HFPERCLKEN_DEFAULT << 20)  /**< Shifted mode DEFAULT for CMU_CTRL */
+
+/* Bit fields for CMU HFRCOCTRL */
+#define _CMU_HFRCOCTRL_RESETVALUE                           0xB1481F3CUL                                /**< Default value for CMU_HFRCOCTRL */
+#define _CMU_HFRCOCTRL_MASK                                 0xFFFF3F7FUL                                /**< Mask for CMU_HFRCOCTRL */
+#define _CMU_HFRCOCTRL_TUNING_SHIFT                         0                                           /**< Shift value for CMU_TUNING */
+#define _CMU_HFRCOCTRL_TUNING_MASK                          0x7FUL                                      /**< Bit mask for CMU_TUNING */
+#define _CMU_HFRCOCTRL_TUNING_DEFAULT                       0x0000003CUL                                /**< Mode DEFAULT for CMU_HFRCOCTRL */
+#define CMU_HFRCOCTRL_TUNING_DEFAULT                        (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0)        /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */
+#define _CMU_HFRCOCTRL_FINETUNING_SHIFT                     8                                           /**< Shift value for CMU_FINETUNING */
+#define _CMU_HFRCOCTRL_FINETUNING_MASK                      0x3F00UL                                    /**< Bit mask for CMU_FINETUNING */
+#define _CMU_HFRCOCTRL_FINETUNING_DEFAULT                   0x0000001FUL                                /**< Mode DEFAULT for CMU_HFRCOCTRL */
+#define CMU_HFRCOCTRL_FINETUNING_DEFAULT                    (_CMU_HFRCOCTRL_FINETUNING_DEFAULT << 8)    /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */
+#define _CMU_HFRCOCTRL_FREQRANGE_SHIFT                      16                                          /**< Shift value for CMU_FREQRANGE */
+#define _CMU_HFRCOCTRL_FREQRANGE_MASK                       0x1F0000UL                                  /**< Bit mask for CMU_FREQRANGE */
+#define _CMU_HFRCOCTRL_FREQRANGE_DEFAULT                    0x00000008UL                                /**< Mode DEFAULT for CMU_HFRCOCTRL */
+#define CMU_HFRCOCTRL_FREQRANGE_DEFAULT                     (_CMU_HFRCOCTRL_FREQRANGE_DEFAULT << 16)    /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */
+#define _CMU_HFRCOCTRL_CMPBIAS_SHIFT                        21                                          /**< Shift value for CMU_CMPBIAS */
+#define _CMU_HFRCOCTRL_CMPBIAS_MASK                         0xE00000UL                                  /**< Bit mask for CMU_CMPBIAS */
+#define _CMU_HFRCOCTRL_CMPBIAS_DEFAULT                      0x00000002UL                                /**< Mode DEFAULT for CMU_HFRCOCTRL */
+#define CMU_HFRCOCTRL_CMPBIAS_DEFAULT                       (_CMU_HFRCOCTRL_CMPBIAS_DEFAULT << 21)      /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */
+#define CMU_HFRCOCTRL_LDOHP                                 (0x1UL << 24)                               /**< HFRCO LDO High Power Mode */
+#define _CMU_HFRCOCTRL_LDOHP_SHIFT                          24                                          /**< Shift value for CMU_LDOHP */
+#define _CMU_HFRCOCTRL_LDOHP_MASK                           0x1000000UL                                 /**< Bit mask for CMU_LDOHP */
+#define _CMU_HFRCOCTRL_LDOHP_DEFAULT                        0x00000001UL                                /**< Mode DEFAULT for CMU_HFRCOCTRL */
+#define CMU_HFRCOCTRL_LDOHP_DEFAULT                         (_CMU_HFRCOCTRL_LDOHP_DEFAULT << 24)        /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */
+#define _CMU_HFRCOCTRL_CLKDIV_SHIFT                         25                                          /**< Shift value for CMU_CLKDIV */
+#define _CMU_HFRCOCTRL_CLKDIV_MASK                          0x6000000UL                                 /**< Bit mask for CMU_CLKDIV */
+#define _CMU_HFRCOCTRL_CLKDIV_DEFAULT                       0x00000000UL                                /**< Mode DEFAULT for CMU_HFRCOCTRL */
+#define _CMU_HFRCOCTRL_CLKDIV_DIV1                          0x00000000UL                                /**< Mode DIV1 for CMU_HFRCOCTRL */
+#define _CMU_HFRCOCTRL_CLKDIV_DIV2                          0x00000001UL                                /**< Mode DIV2 for CMU_HFRCOCTRL */
+#define _CMU_HFRCOCTRL_CLKDIV_DIV4                          0x00000002UL                                /**< Mode DIV4 for CMU_HFRCOCTRL */
+#define CMU_HFRCOCTRL_CLKDIV_DEFAULT                        (_CMU_HFRCOCTRL_CLKDIV_DEFAULT << 25)       /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */
+#define CMU_HFRCOCTRL_CLKDIV_DIV1                           (_CMU_HFRCOCTRL_CLKDIV_DIV1 << 25)          /**< Shifted mode DIV1 for CMU_HFRCOCTRL */
+#define CMU_HFRCOCTRL_CLKDIV_DIV2                           (_CMU_HFRCOCTRL_CLKDIV_DIV2 << 25)          /**< Shifted mode DIV2 for CMU_HFRCOCTRL */
+#define CMU_HFRCOCTRL_CLKDIV_DIV4                           (_CMU_HFRCOCTRL_CLKDIV_DIV4 << 25)          /**< Shifted mode DIV4 for CMU_HFRCOCTRL */
+#define CMU_HFRCOCTRL_FINETUNINGEN                          (0x1UL << 27)                               /**< Enable reference for fine tuning */
+#define _CMU_HFRCOCTRL_FINETUNINGEN_SHIFT                   27                                          /**< Shift value for CMU_FINETUNINGEN */
+#define _CMU_HFRCOCTRL_FINETUNINGEN_MASK                    0x8000000UL                                 /**< Bit mask for CMU_FINETUNINGEN */
+#define _CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT                 0x00000000UL                                /**< Mode DEFAULT for CMU_HFRCOCTRL */
+#define CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT                  (_CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */
+#define _CMU_HFRCOCTRL_VREFTC_SHIFT                         28                                          /**< Shift value for CMU_VREFTC */
+#define _CMU_HFRCOCTRL_VREFTC_MASK                          0xF0000000UL                                /**< Bit mask for CMU_VREFTC */
+#define _CMU_HFRCOCTRL_VREFTC_DEFAULT                       0x0000000BUL                                /**< Mode DEFAULT for CMU_HFRCOCTRL */
+#define CMU_HFRCOCTRL_VREFTC_DEFAULT                        (_CMU_HFRCOCTRL_VREFTC_DEFAULT << 28)       /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */
+
+/* Bit fields for CMU AUXHFRCOCTRL */
+#define _CMU_AUXHFRCOCTRL_RESETVALUE                        0xB1481F3CUL                                   /**< Default value for CMU_AUXHFRCOCTRL */
+#define _CMU_AUXHFRCOCTRL_MASK                              0xFFFF3F7FUL                                   /**< Mask for CMU_AUXHFRCOCTRL */
+#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT                      0                                              /**< Shift value for CMU_TUNING */
+#define _CMU_AUXHFRCOCTRL_TUNING_MASK                       0x7FUL                                         /**< Bit mask for CMU_TUNING */
+#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT                    0x0000003CUL                                   /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */
+#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT                     (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0)        /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */
+#define _CMU_AUXHFRCOCTRL_FINETUNING_SHIFT                  8                                              /**< Shift value for CMU_FINETUNING */
+#define _CMU_AUXHFRCOCTRL_FINETUNING_MASK                   0x3F00UL                                       /**< Bit mask for CMU_FINETUNING */
+#define _CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT                0x0000001FUL                                   /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */
+#define CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT                 (_CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT << 8)    /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */
+#define _CMU_AUXHFRCOCTRL_FREQRANGE_SHIFT                   16                                             /**< Shift value for CMU_FREQRANGE */
+#define _CMU_AUXHFRCOCTRL_FREQRANGE_MASK                    0x1F0000UL                                     /**< Bit mask for CMU_FREQRANGE */
+#define _CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT                 0x00000008UL                                   /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */
+#define CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT                  (_CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT << 16)    /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */
+#define _CMU_AUXHFRCOCTRL_CMPBIAS_SHIFT                     21                                             /**< Shift value for CMU_CMPBIAS */
+#define _CMU_AUXHFRCOCTRL_CMPBIAS_MASK                      0xE00000UL                                     /**< Bit mask for CMU_CMPBIAS */
+#define _CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT                   0x00000002UL                                   /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */
+#define CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT                    (_CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT << 21)      /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */
+#define CMU_AUXHFRCOCTRL_LDOHP                              (0x1UL << 24)                                  /**< AUXHFRCO LDO High Power Mode */
+#define _CMU_AUXHFRCOCTRL_LDOHP_SHIFT                       24                                             /**< Shift value for CMU_LDOHP */
+#define _CMU_AUXHFRCOCTRL_LDOHP_MASK                        0x1000000UL                                    /**< Bit mask for CMU_LDOHP */
+#define _CMU_AUXHFRCOCTRL_LDOHP_DEFAULT                     0x00000001UL                                   /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */
+#define CMU_AUXHFRCOCTRL_LDOHP_DEFAULT                      (_CMU_AUXHFRCOCTRL_LDOHP_DEFAULT << 24)        /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */
+#define _CMU_AUXHFRCOCTRL_CLKDIV_SHIFT                      25                                             /**< Shift value for CMU_CLKDIV */
+#define _CMU_AUXHFRCOCTRL_CLKDIV_MASK                       0x6000000UL                                    /**< Bit mask for CMU_CLKDIV */
+#define _CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT                    0x00000000UL                                   /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */
+#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV1                       0x00000000UL                                   /**< Mode DIV1 for CMU_AUXHFRCOCTRL */
+#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV2                       0x00000001UL                                   /**< Mode DIV2 for CMU_AUXHFRCOCTRL */
+#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV4                       0x00000002UL                                   /**< Mode DIV4 for CMU_AUXHFRCOCTRL */
+#define CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT                     (_CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT << 25)       /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */
+#define CMU_AUXHFRCOCTRL_CLKDIV_DIV1                        (_CMU_AUXHFRCOCTRL_CLKDIV_DIV1 << 25)          /**< Shifted mode DIV1 for CMU_AUXHFRCOCTRL */
+#define CMU_AUXHFRCOCTRL_CLKDIV_DIV2                        (_CMU_AUXHFRCOCTRL_CLKDIV_DIV2 << 25)          /**< Shifted mode DIV2 for CMU_AUXHFRCOCTRL */
+#define CMU_AUXHFRCOCTRL_CLKDIV_DIV4                        (_CMU_AUXHFRCOCTRL_CLKDIV_DIV4 << 25)          /**< Shifted mode DIV4 for CMU_AUXHFRCOCTRL */
+#define CMU_AUXHFRCOCTRL_FINETUNINGEN                       (0x1UL << 27)                                  /**< Enable reference for fine tuning */
+#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_SHIFT                27                                             /**< Shift value for CMU_FINETUNINGEN */
+#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_MASK                 0x8000000UL                                    /**< Bit mask for CMU_FINETUNINGEN */
+#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT              0x00000000UL                                   /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */
+#define CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT               (_CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */
+#define _CMU_AUXHFRCOCTRL_VREFTC_SHIFT                      28                                             /**< Shift value for CMU_VREFTC */
+#define _CMU_AUXHFRCOCTRL_VREFTC_MASK                       0xF0000000UL                                   /**< Bit mask for CMU_VREFTC */
+#define _CMU_AUXHFRCOCTRL_VREFTC_DEFAULT                    0x0000000BUL                                   /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */
+#define CMU_AUXHFRCOCTRL_VREFTC_DEFAULT                     (_CMU_AUXHFRCOCTRL_VREFTC_DEFAULT << 28)       /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */
+
+/* Bit fields for CMU LFRCOCTRL */
+#define _CMU_LFRCOCTRL_RESETVALUE                           0x81060100UL                              /**< Default value for CMU_LFRCOCTRL */
+#define _CMU_LFRCOCTRL_MASK                                 0xF30701FFUL                              /**< Mask for CMU_LFRCOCTRL */
+#define _CMU_LFRCOCTRL_TUNING_SHIFT                         0                                         /**< Shift value for CMU_TUNING */
+#define _CMU_LFRCOCTRL_TUNING_MASK                          0x1FFUL                                   /**< Bit mask for CMU_TUNING */
+#define _CMU_LFRCOCTRL_TUNING_DEFAULT                       0x00000100UL                              /**< Mode DEFAULT for CMU_LFRCOCTRL */
+#define CMU_LFRCOCTRL_TUNING_DEFAULT                        (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0)      /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */
+#define CMU_LFRCOCTRL_ENVREF                                (0x1UL << 16)                             /**< Enable duty cycling of vref */
+#define _CMU_LFRCOCTRL_ENVREF_SHIFT                         16                                        /**< Shift value for CMU_ENVREF */
+#define _CMU_LFRCOCTRL_ENVREF_MASK                          0x10000UL                                 /**< Bit mask for CMU_ENVREF */
+#define _CMU_LFRCOCTRL_ENVREF_DEFAULT                       0x00000000UL                              /**< Mode DEFAULT for CMU_LFRCOCTRL */
+#define CMU_LFRCOCTRL_ENVREF_DEFAULT                        (_CMU_LFRCOCTRL_ENVREF_DEFAULT << 16)     /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */
+#define CMU_LFRCOCTRL_ENCHOP                                (0x1UL << 17)                             /**< Enable comparator chopping */
+#define _CMU_LFRCOCTRL_ENCHOP_SHIFT                         17                                        /**< Shift value for CMU_ENCHOP */
+#define _CMU_LFRCOCTRL_ENCHOP_MASK                          0x20000UL                                 /**< Bit mask for CMU_ENCHOP */
+#define _CMU_LFRCOCTRL_ENCHOP_DEFAULT                       0x00000001UL                              /**< Mode DEFAULT for CMU_LFRCOCTRL */
+#define CMU_LFRCOCTRL_ENCHOP_DEFAULT                        (_CMU_LFRCOCTRL_ENCHOP_DEFAULT << 17)     /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */
+#define CMU_LFRCOCTRL_ENDEM                                 (0x1UL << 18)                             /**< Enable dynamic element matching */
+#define _CMU_LFRCOCTRL_ENDEM_SHIFT                          18                                        /**< Shift value for CMU_ENDEM */
+#define _CMU_LFRCOCTRL_ENDEM_MASK                           0x40000UL                                 /**< Bit mask for CMU_ENDEM */
+#define _CMU_LFRCOCTRL_ENDEM_DEFAULT                        0x00000001UL                              /**< Mode DEFAULT for CMU_LFRCOCTRL */
+#define CMU_LFRCOCTRL_ENDEM_DEFAULT                         (_CMU_LFRCOCTRL_ENDEM_DEFAULT << 18)      /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */
+#define _CMU_LFRCOCTRL_TIMEOUT_SHIFT                        24                                        /**< Shift value for CMU_TIMEOUT */
+#define _CMU_LFRCOCTRL_TIMEOUT_MASK                         0x3000000UL                               /**< Bit mask for CMU_TIMEOUT */
+#define _CMU_LFRCOCTRL_TIMEOUT_2CYCLES                      0x00000000UL                              /**< Mode 2CYCLES for CMU_LFRCOCTRL */
+#define _CMU_LFRCOCTRL_TIMEOUT_DEFAULT                      0x00000001UL                              /**< Mode DEFAULT for CMU_LFRCOCTRL */
+#define _CMU_LFRCOCTRL_TIMEOUT_16CYCLES                     0x00000001UL                              /**< Mode 16CYCLES for CMU_LFRCOCTRL */
+#define _CMU_LFRCOCTRL_TIMEOUT_32CYCLES                     0x00000002UL                              /**< Mode 32CYCLES for CMU_LFRCOCTRL */
+#define CMU_LFRCOCTRL_TIMEOUT_2CYCLES                       (_CMU_LFRCOCTRL_TIMEOUT_2CYCLES << 24)    /**< Shifted mode 2CYCLES for CMU_LFRCOCTRL */
+#define CMU_LFRCOCTRL_TIMEOUT_DEFAULT                       (_CMU_LFRCOCTRL_TIMEOUT_DEFAULT << 24)    /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */
+#define CMU_LFRCOCTRL_TIMEOUT_16CYCLES                      (_CMU_LFRCOCTRL_TIMEOUT_16CYCLES << 24)   /**< Shifted mode 16CYCLES for CMU_LFRCOCTRL */
+#define CMU_LFRCOCTRL_TIMEOUT_32CYCLES                      (_CMU_LFRCOCTRL_TIMEOUT_32CYCLES << 24)   /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */
+#define _CMU_LFRCOCTRL_GMCCURTUNE_SHIFT                     28                                        /**< Shift value for CMU_GMCCURTUNE */
+#define _CMU_LFRCOCTRL_GMCCURTUNE_MASK                      0xF0000000UL                              /**< Bit mask for CMU_GMCCURTUNE */
+#define _CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT                   0x00000008UL                              /**< Mode DEFAULT for CMU_LFRCOCTRL */
+#define CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT                    (_CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */
+
+/* Bit fields for CMU HFXOCTRL */
+#define _CMU_HFXOCTRL_RESETVALUE                            0x00000000UL                                     /**< Default value for CMU_HFXOCTRL */
+#define _CMU_HFXOCTRL_MASK                                  0x77000F31UL                                     /**< Mask for CMU_HFXOCTRL */
+#define CMU_HFXOCTRL_MODE                                   (0x1UL << 0)                                     /**< HFXO Mode */
+#define _CMU_HFXOCTRL_MODE_SHIFT                            0                                                /**< Shift value for CMU_MODE */
+#define _CMU_HFXOCTRL_MODE_MASK                             0x1UL                                            /**< Bit mask for CMU_MODE */
+#define _CMU_HFXOCTRL_MODE_DEFAULT                          0x00000000UL                                     /**< Mode DEFAULT for CMU_HFXOCTRL */
+#define _CMU_HFXOCTRL_MODE_XTAL                             0x00000000UL                                     /**< Mode XTAL for CMU_HFXOCTRL */
+#define _CMU_HFXOCTRL_MODE_EXTCLK                           0x00000001UL                                     /**< Mode EXTCLK for CMU_HFXOCTRL */
+#define CMU_HFXOCTRL_MODE_DEFAULT                           (_CMU_HFXOCTRL_MODE_DEFAULT << 0)                /**< Shifted mode DEFAULT for CMU_HFXOCTRL */
+#define CMU_HFXOCTRL_MODE_XTAL                              (_CMU_HFXOCTRL_MODE_XTAL << 0)                   /**< Shifted mode XTAL for CMU_HFXOCTRL */
+#define CMU_HFXOCTRL_MODE_EXTCLK                            (_CMU_HFXOCTRL_MODE_EXTCLK << 0)                 /**< Shifted mode EXTCLK for CMU_HFXOCTRL */
+#define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_SHIFT             4                                                /**< Shift value for CMU_PEAKDETSHUNTOPTMODE */
+#define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK              0x30UL                                           /**< Bit mask for CMU_PEAKDETSHUNTOPTMODE */
+#define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_DEFAULT           0x00000000UL                                     /**< Mode DEFAULT for CMU_HFXOCTRL */
+#define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD           0x00000000UL                                     /**< Mode AUTOCMD for CMU_HFXOCTRL */
+#define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_CMD               0x00000001UL                                     /**< Mode CMD for CMU_HFXOCTRL */
+#define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MANUAL            0x00000002UL                                     /**< Mode MANUAL for CMU_HFXOCTRL */
+#define CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_DEFAULT            (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */
+#define CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD            (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD << 4) /**< Shifted mode AUTOCMD for CMU_HFXOCTRL */
+#define CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_CMD                (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_CMD << 4)     /**< Shifted mode CMD for CMU_HFXOCTRL */
+#define CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MANUAL             (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MANUAL << 4)  /**< Shifted mode MANUAL for CMU_HFXOCTRL */
+#define CMU_HFXOCTRL_LOWPOWER                               (0x1UL << 8)                                     /**< Low power mode control. PSR performance is reduced to enable low current consumption. */
+#define _CMU_HFXOCTRL_LOWPOWER_SHIFT                        8                                                /**< Shift value for CMU_LOWPOWER */
+#define _CMU_HFXOCTRL_LOWPOWER_MASK                         0x100UL                                          /**< Bit mask for CMU_LOWPOWER */
+#define _CMU_HFXOCTRL_LOWPOWER_DEFAULT                      0x00000000UL                                     /**< Mode DEFAULT for CMU_HFXOCTRL */
+#define CMU_HFXOCTRL_LOWPOWER_DEFAULT                       (_CMU_HFXOCTRL_LOWPOWER_DEFAULT << 8)            /**< Shifted mode DEFAULT for CMU_HFXOCTRL */
+#define CMU_HFXOCTRL_XTI2GND                                (0x1UL << 9)                                     /**< Clamp HFXTAL_N pin to ground when HFXO oscillator is off and KEEPWARM=0. */
+#define _CMU_HFXOCTRL_XTI2GND_SHIFT                         9                                                /**< Shift value for CMU_XTI2GND */
+#define _CMU_HFXOCTRL_XTI2GND_MASK                          0x200UL                                          /**< Bit mask for CMU_XTI2GND */
+#define _CMU_HFXOCTRL_XTI2GND_DEFAULT                       0x00000000UL                                     /**< Mode DEFAULT for CMU_HFXOCTRL */
+#define CMU_HFXOCTRL_XTI2GND_DEFAULT                        (_CMU_HFXOCTRL_XTI2GND_DEFAULT << 9)             /**< Shifted mode DEFAULT for CMU_HFXOCTRL */
+#define CMU_HFXOCTRL_XTO2GND                                (0x1UL << 10)                                    /**< Clamp HFXTAL_P pin to ground when HFXO oscillator is off and KEEPWARM=0. */
+#define _CMU_HFXOCTRL_XTO2GND_SHIFT                         10                                               /**< Shift value for CMU_XTO2GND */
+#define _CMU_HFXOCTRL_XTO2GND_MASK                          0x400UL                                          /**< Bit mask for CMU_XTO2GND */
+#define _CMU_HFXOCTRL_XTO2GND_DEFAULT                       0x00000000UL                                     /**< Mode DEFAULT for CMU_HFXOCTRL */
+#define CMU_HFXOCTRL_XTO2GND_DEFAULT                        (_CMU_HFXOCTRL_XTO2GND_DEFAULT << 10)            /**< Shifted mode DEFAULT for CMU_HFXOCTRL */
+#define CMU_HFXOCTRL_KEEPWARM                               (0x1UL << 11)                                    /**< Keep HFXO warm when turning off HFXO. */
+#define _CMU_HFXOCTRL_KEEPWARM_SHIFT                        11                                               /**< Shift value for CMU_KEEPWARM */
+#define _CMU_HFXOCTRL_KEEPWARM_MASK                         0x800UL                                          /**< Bit mask for CMU_KEEPWARM */
+#define _CMU_HFXOCTRL_KEEPWARM_DEFAULT                      0x00000000UL                                     /**< Mode DEFAULT for CMU_HFXOCTRL */
+#define CMU_HFXOCTRL_KEEPWARM_DEFAULT                       (_CMU_HFXOCTRL_KEEPWARM_DEFAULT << 11)           /**< Shifted mode DEFAULT for CMU_HFXOCTRL */
+#define _CMU_HFXOCTRL_LFTIMEOUT_SHIFT                       24                                               /**< Shift value for CMU_LFTIMEOUT */
+#define _CMU_HFXOCTRL_LFTIMEOUT_MASK                        0x7000000UL                                      /**< Bit mask for CMU_LFTIMEOUT */
+#define _CMU_HFXOCTRL_LFTIMEOUT_DEFAULT                     0x00000000UL                                     /**< Mode DEFAULT for CMU_HFXOCTRL */
+#define _CMU_HFXOCTRL_LFTIMEOUT_0CYCLES                     0x00000000UL                                     /**< Mode 0CYCLES for CMU_HFXOCTRL */
+#define _CMU_HFXOCTRL_LFTIMEOUT_2CYCLES                     0x00000001UL                                     /**< Mode 2CYCLES for CMU_HFXOCTRL */
+#define _CMU_HFXOCTRL_LFTIMEOUT_4CYCLES                     0x00000002UL                                     /**< Mode 4CYCLES for CMU_HFXOCTRL */
+#define _CMU_HFXOCTRL_LFTIMEOUT_16CYCLES                    0x00000003UL                                     /**< Mode 16CYCLES for CMU_HFXOCTRL */
+#define _CMU_HFXOCTRL_LFTIMEOUT_32CYCLES                    0x00000004UL                                     /**< Mode 32CYCLES for CMU_HFXOCTRL */
+#define _CMU_HFXOCTRL_LFTIMEOUT_64CYCLES                    0x00000005UL                                     /**< Mode 64CYCLES for CMU_HFXOCTRL */
+#define _CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES                    0x00000006UL                                     /**< Mode 1KCYCLES for CMU_HFXOCTRL */
+#define _CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES                    0x00000007UL                                     /**< Mode 4KCYCLES for CMU_HFXOCTRL */
+#define CMU_HFXOCTRL_LFTIMEOUT_DEFAULT                      (_CMU_HFXOCTRL_LFTIMEOUT_DEFAULT << 24)          /**< Shifted mode DEFAULT for CMU_HFXOCTRL */
+#define CMU_HFXOCTRL_LFTIMEOUT_0CYCLES                      (_CMU_HFXOCTRL_LFTIMEOUT_0CYCLES << 24)          /**< Shifted mode 0CYCLES for CMU_HFXOCTRL */
+#define CMU_HFXOCTRL_LFTIMEOUT_2CYCLES                      (_CMU_HFXOCTRL_LFTIMEOUT_2CYCLES << 24)          /**< Shifted mode 2CYCLES for CMU_HFXOCTRL */
+#define CMU_HFXOCTRL_LFTIMEOUT_4CYCLES                      (_CMU_HFXOCTRL_LFTIMEOUT_4CYCLES << 24)          /**< Shifted mode 4CYCLES for CMU_HFXOCTRL */
+#define CMU_HFXOCTRL_LFTIMEOUT_16CYCLES                     (_CMU_HFXOCTRL_LFTIMEOUT_16CYCLES << 24)         /**< Shifted mode 16CYCLES for CMU_HFXOCTRL */
+#define CMU_HFXOCTRL_LFTIMEOUT_32CYCLES                     (_CMU_HFXOCTRL_LFTIMEOUT_32CYCLES << 24)         /**< Shifted mode 32CYCLES for CMU_HFXOCTRL */
+#define CMU_HFXOCTRL_LFTIMEOUT_64CYCLES                     (_CMU_HFXOCTRL_LFTIMEOUT_64CYCLES << 24)         /**< Shifted mode 64CYCLES for CMU_HFXOCTRL */
+#define CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES                     (_CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES << 24)         /**< Shifted mode 1KCYCLES for CMU_HFXOCTRL */
+#define CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES                     (_CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES << 24)         /**< Shifted mode 4KCYCLES for CMU_HFXOCTRL */
+#define CMU_HFXOCTRL_AUTOSTARTEM0EM1                        (0x1UL << 28)                                    /**< Automatically start of HFXO upon EM0/EM1 entry from EM2/EM3 */
+#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_SHIFT                 28                                               /**< Shift value for CMU_AUTOSTARTEM0EM1 */
+#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK                  0x10000000UL                                     /**< Bit mask for CMU_AUTOSTARTEM0EM1 */
+#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT               0x00000000UL                                     /**< Mode DEFAULT for CMU_HFXOCTRL */
+#define CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT                (_CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT << 28)    /**< Shifted mode DEFAULT for CMU_HFXOCTRL */
+#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1                     (0x1UL << 29)                                    /**< Automatically start and select of HFXO upon EM0/EM1 entry from EM2/EM3 */
+#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_SHIFT              29                                               /**< Shift value for CMU_AUTOSTARTSELEM0EM1 */
+#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK               0x20000000UL                                     /**< Bit mask for CMU_AUTOSTARTSELEM0EM1 */
+#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT            0x00000000UL                                     /**< Mode DEFAULT for CMU_HFXOCTRL */
+#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT             (_CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */
+#define CMU_HFXOCTRL_AUTOSTARTRDYSELRAC                     (0x1UL << 30)                                    /**< Automatically start HFXO on RAC wake-up and select it upon HFXO Ready */
+#define _CMU_HFXOCTRL_AUTOSTARTRDYSELRAC_SHIFT              30                                               /**< Shift value for CMU_AUTOSTARTRDYSELRAC */
+#define _CMU_HFXOCTRL_AUTOSTARTRDYSELRAC_MASK               0x40000000UL                                     /**< Bit mask for CMU_AUTOSTARTRDYSELRAC */
+#define _CMU_HFXOCTRL_AUTOSTARTRDYSELRAC_DEFAULT            0x00000000UL                                     /**< Mode DEFAULT for CMU_HFXOCTRL */
+#define CMU_HFXOCTRL_AUTOSTARTRDYSELRAC_DEFAULT             (_CMU_HFXOCTRL_AUTOSTARTRDYSELRAC_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */
+
+/* Bit fields for CMU HFXOCTRL1 */
+#define _CMU_HFXOCTRL1_RESETVALUE                           0x00000240UL                             /**< Default value for CMU_HFXOCTRL1 */
+#define _CMU_HFXOCTRL1_MASK                                 0x00000277UL                             /**< Mask for CMU_HFXOCTRL1 */
+#define _CMU_HFXOCTRL1_PEAKDETTHR_SHIFT                     0                                        /**< Shift value for CMU_PEAKDETTHR */
+#define _CMU_HFXOCTRL1_PEAKDETTHR_MASK                      0x7UL                                    /**< Bit mask for CMU_PEAKDETTHR */
+#define _CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT                   0x00000000UL                             /**< Mode DEFAULT for CMU_HFXOCTRL1 */
+#define CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT                    (_CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOCTRL1 */
+#define _CMU_HFXOCTRL1_REGLVL_SHIFT                         4                                        /**< Shift value for CMU_REGLVL */
+#define _CMU_HFXOCTRL1_REGLVL_MASK                          0x70UL                                   /**< Bit mask for CMU_REGLVL */
+#define _CMU_HFXOCTRL1_REGLVL_DEFAULT                       0x00000004UL                             /**< Mode DEFAULT for CMU_HFXOCTRL1 */
+#define CMU_HFXOCTRL1_REGLVL_DEFAULT                        (_CMU_HFXOCTRL1_REGLVL_DEFAULT << 4)     /**< Shifted mode DEFAULT for CMU_HFXOCTRL1 */
+#define CMU_HFXOCTRL1_XTIBIASEN                             (0x1UL << 9)                             /**< Reserved for internal use. Do not change. */
+#define _CMU_HFXOCTRL1_XTIBIASEN_SHIFT                      9                                        /**< Shift value for CMU_XTIBIASEN */
+#define _CMU_HFXOCTRL1_XTIBIASEN_MASK                       0x200UL                                  /**< Bit mask for CMU_XTIBIASEN */
+#define _CMU_HFXOCTRL1_XTIBIASEN_DEFAULT                    0x00000001UL                             /**< Mode DEFAULT for CMU_HFXOCTRL1 */
+#define CMU_HFXOCTRL1_XTIBIASEN_DEFAULT                     (_CMU_HFXOCTRL1_XTIBIASEN_DEFAULT << 9)  /**< Shifted mode DEFAULT for CMU_HFXOCTRL1 */
+
+/* Bit fields for CMU HFXOSTARTUPCTRL */
+#define _CMU_HFXOSTARTUPCTRL_RESETVALUE                     0xA1250060UL                                          /**< Default value for CMU_HFXOSTARTUPCTRL */
+#define _CMU_HFXOSTARTUPCTRL_MASK                           0xFFEFF87FUL                                          /**< Mask for CMU_HFXOSTARTUPCTRL */
+#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT             0                                                     /**< Shift value for CMU_IBTRIMXOCORE */
+#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK              0x7FUL                                                /**< Bit mask for CMU_IBTRIMXOCORE */
+#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT           0x00000060UL                                          /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */
+#define CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT            (_CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT << 0)      /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */
+#define _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT                    11                                                    /**< Shift value for CMU_CTUNE */
+#define _CMU_HFXOSTARTUPCTRL_CTUNE_MASK                     0xFF800UL                                             /**< Bit mask for CMU_CTUNE */
+#define _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT                  0x000000A0UL                                          /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */
+#define CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT                   (_CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT << 11)            /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */
+#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCOREWARM_SHIFT         21                                                    /**< Shift value for CMU_IBTRIMXOCOREWARM */
+#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCOREWARM_MASK          0xFE00000UL                                           /**< Bit mask for CMU_IBTRIMXOCOREWARM */
+#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCOREWARM_DEFAULT       0x00000009UL                                          /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */
+#define CMU_HFXOSTARTUPCTRL_IBTRIMXOCOREWARM_DEFAULT        (_CMU_HFXOSTARTUPCTRL_IBTRIMXOCOREWARM_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */
+#define _CMU_HFXOSTARTUPCTRL_REGISHWARM_SHIFT               28                                                    /**< Shift value for CMU_REGISHWARM */
+#define _CMU_HFXOSTARTUPCTRL_REGISHWARM_MASK                0xF0000000UL                                          /**< Bit mask for CMU_REGISHWARM */
+#define _CMU_HFXOSTARTUPCTRL_REGISHWARM_DEFAULT             0x0000000AUL                                          /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */
+#define CMU_HFXOSTARTUPCTRL_REGISHWARM_DEFAULT              (_CMU_HFXOSTARTUPCTRL_REGISHWARM_DEFAULT << 28)       /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */
+
+/* Bit fields for CMU HFXOSTEADYSTATECTRL */
+#define _CMU_HFXOSTEADYSTATECTRL_RESETVALUE                 0xA30AAD09UL                                         /**< Default value for CMU_HFXOSTEADYSTATECTRL */
+#define _CMU_HFXOSTEADYSTATECTRL_MASK                       0xF70FFFFFUL                                         /**< Mask for CMU_HFXOSTEADYSTATECTRL */
+#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT         0                                                    /**< Shift value for CMU_IBTRIMXOCORE */
+#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK          0x7FUL                                               /**< Bit mask for CMU_IBTRIMXOCORE */
+#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT       0x00000009UL                                         /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */
+#define CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT        (_CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */
+#define _CMU_HFXOSTEADYSTATECTRL_REGISH_SHIFT               7                                                    /**< Shift value for CMU_REGISH */
+#define _CMU_HFXOSTEADYSTATECTRL_REGISH_MASK                0x780UL                                              /**< Bit mask for CMU_REGISH */
+#define _CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT             0x0000000AUL                                         /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */
+#define CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT              (_CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT << 7)       /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */
+#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT                11                                                   /**< Shift value for CMU_CTUNE */
+#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK                 0xFF800UL                                            /**< Bit mask for CMU_CTUNE */
+#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT              0x00000155UL                                         /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */
+#define CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT               (_CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT << 11)       /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */
+#define _CMU_HFXOSTEADYSTATECTRL_REGSELILOW_SHIFT           24                                                   /**< Shift value for CMU_REGSELILOW */
+#define _CMU_HFXOSTEADYSTATECTRL_REGSELILOW_MASK            0x3000000UL                                          /**< Bit mask for CMU_REGSELILOW */
+#define _CMU_HFXOSTEADYSTATECTRL_REGSELILOW_DEFAULT         0x00000003UL                                         /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */
+#define CMU_HFXOSTEADYSTATECTRL_REGSELILOW_DEFAULT          (_CMU_HFXOSTEADYSTATECTRL_REGSELILOW_DEFAULT << 24)  /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */
+#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN                   (0x1UL << 26)                                        /**< Enables oscillator peak detectors */
+#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_SHIFT            26                                                   /**< Shift value for CMU_PEAKDETEN */
+#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_MASK             0x4000000UL                                          /**< Bit mask for CMU_PEAKDETEN */
+#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT          0x00000000UL                                         /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */
+#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT           (_CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT << 26)   /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */
+#define _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_SHIFT          28                                                   /**< Shift value for CMU_REGISHUPPER */
+#define _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_MASK           0xF0000000UL                                         /**< Bit mask for CMU_REGISHUPPER */
+#define _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_DEFAULT        0x0000000AUL                                         /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */
+#define CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_DEFAULT         (_CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */
+
+/* Bit fields for CMU HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_RESETVALUE                     0x00026667UL                                            /**< Default value for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_MASK                           0x000FFFFFUL                                            /**< Mask for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT           0                                                       /**< Shift value for CMU_STARTUPTIMEOUT */
+#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_MASK            0xFUL                                                   /**< Bit mask for CMU_STARTUPTIMEOUT */
+#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES         0x00000000UL                                            /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES         0x00000001UL                                            /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES        0x00000002UL                                            /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES        0x00000003UL                                            /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES       0x00000004UL                                            /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES        0x00000005UL                                            /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES        0x00000006UL                                            /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT         0x00000007UL                                            /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES        0x00000007UL                                            /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES        0x00000008UL                                            /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES       0x00000009UL                                            /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES       0x0000000AUL                                            /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES          (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES << 0)      /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES          (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES << 0)      /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES         (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES << 0)     /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES         (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES << 0)     /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES        (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES << 0)    /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES         (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES << 0)     /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES         (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES << 0)     /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT          (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT << 0)      /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES         (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES << 0)     /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES         (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES << 0)     /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES        (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES << 0)    /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES        (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES << 0)    /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT            4                                                       /**< Shift value for CMU_STEADYTIMEOUT */
+#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_MASK             0xF0UL                                                  /**< Bit mask for CMU_STEADYTIMEOUT */
+#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES          0x00000000UL                                            /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES          0x00000001UL                                            /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES         0x00000002UL                                            /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES         0x00000003UL                                            /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES        0x00000004UL                                            /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES         0x00000005UL                                            /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT          0x00000006UL                                            /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES         0x00000006UL                                            /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES         0x00000007UL                                            /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES         0x00000008UL                                            /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES        0x00000009UL                                            /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES        0x0000000AUL                                            /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES           (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES << 4)       /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES           (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES << 4)       /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES          (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES << 4)      /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES          (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES << 4)      /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES         (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES << 4)     /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES          (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES << 4)      /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT           (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT << 4)       /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES          (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES << 4)      /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES          (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES << 4)      /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES          (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES << 4)      /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES         (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES << 4)     /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES         (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES << 4)     /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_SHIFT        8                                                       /**< Shift value for CMU_WARMSTEADYTIMEOUT */
+#define _CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_MASK         0xF00UL                                                 /**< Bit mask for CMU_WARMSTEADYTIMEOUT */
+#define _CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_2CYCLES      0x00000000UL                                            /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_4CYCLES      0x00000001UL                                            /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_16CYCLES     0x00000002UL                                            /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_32CYCLES     0x00000003UL                                            /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_256CYCLES    0x00000004UL                                            /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_1KCYCLES     0x00000005UL                                            /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_DEFAULT      0x00000006UL                                            /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_2KCYCLES     0x00000006UL                                            /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_4KCYCLES     0x00000007UL                                            /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_8KCYCLES     0x00000008UL                                            /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_16KCYCLES    0x00000009UL                                            /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_32KCYCLES    0x0000000AUL                                            /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_2CYCLES       (_CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_2CYCLES << 8)   /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_4CYCLES       (_CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_4CYCLES << 8)   /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_16CYCLES      (_CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_16CYCLES << 8)  /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_32CYCLES      (_CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_32CYCLES << 8)  /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_256CYCLES     (_CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_256CYCLES << 8) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_1KCYCLES      (_CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_1KCYCLES << 8)  /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_DEFAULT       (_CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_DEFAULT << 8)   /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_2KCYCLES      (_CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_2KCYCLES << 8)  /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_4KCYCLES      (_CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_4KCYCLES << 8)  /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_8KCYCLES      (_CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_8KCYCLES << 8)  /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_16KCYCLES     (_CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_16KCYCLES << 8) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_32KCYCLES     (_CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_32KCYCLES << 8) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT           12                                                      /**< Shift value for CMU_PEAKDETTIMEOUT */
+#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_MASK            0xF000UL                                                /**< Bit mask for CMU_PEAKDETTIMEOUT */
+#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES         0x00000000UL                                            /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES         0x00000001UL                                            /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES        0x00000002UL                                            /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES        0x00000003UL                                            /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES       0x00000004UL                                            /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES        0x00000005UL                                            /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT         0x00000006UL                                            /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES        0x00000006UL                                            /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES        0x00000007UL                                            /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES        0x00000008UL                                            /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES       0x00000009UL                                            /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES       0x0000000AUL                                            /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES          (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES << 12)     /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES          (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES << 12)     /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES         (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES << 12)    /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES         (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES << 12)    /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES        (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES << 12)   /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES         (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES << 12)    /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT          (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT << 12)     /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES         (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES << 12)    /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES         (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES << 12)    /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES         (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES << 12)    /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES        (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES << 12)   /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES        (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES << 12)   /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_SHIFT          16                                                      /**< Shift value for CMU_SHUNTOPTTIMEOUT */
+#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_MASK           0xF0000UL                                               /**< Bit mask for CMU_SHUNTOPTTIMEOUT */
+#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2CYCLES        0x00000000UL                                            /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4CYCLES        0x00000001UL                                            /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT        0x00000002UL                                            /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16CYCLES       0x00000002UL                                            /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32CYCLES       0x00000003UL                                            /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_256CYCLES      0x00000004UL                                            /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_1KCYCLES       0x00000005UL                                            /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2KCYCLES       0x00000006UL                                            /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4KCYCLES       0x00000007UL                                            /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_8KCYCLES       0x00000008UL                                            /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16KCYCLES      0x00000009UL                                            /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32KCYCLES      0x0000000AUL                                            /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2CYCLES         (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2CYCLES << 16)    /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4CYCLES         (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4CYCLES << 16)    /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT         (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT << 16)    /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16CYCLES        (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16CYCLES << 16)   /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32CYCLES        (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32CYCLES << 16)   /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_256CYCLES       (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_256CYCLES << 16)  /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_1KCYCLES        (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_1KCYCLES << 16)   /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2KCYCLES        (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2KCYCLES << 16)   /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4KCYCLES        (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4KCYCLES << 16)   /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_8KCYCLES        (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_8KCYCLES << 16)   /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16KCYCLES       (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16KCYCLES << 16)  /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32KCYCLES       (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32KCYCLES << 16)  /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */
+
+/* Bit fields for CMU LFXOCTRL */
+#define _CMU_LFXOCTRL_RESETVALUE                            0x07009000UL                            /**< Default value for CMU_LFXOCTRL */
+#define _CMU_LFXOCTRL_MASK                                  0x0713DB7FUL                            /**< Mask for CMU_LFXOCTRL */
+#define _CMU_LFXOCTRL_TUNING_SHIFT                          0                                       /**< Shift value for CMU_TUNING */
+#define _CMU_LFXOCTRL_TUNING_MASK                           0x7FUL                                  /**< Bit mask for CMU_TUNING */
+#define _CMU_LFXOCTRL_TUNING_DEFAULT                        0x00000000UL                            /**< Mode DEFAULT for CMU_LFXOCTRL */
+#define CMU_LFXOCTRL_TUNING_DEFAULT                         (_CMU_LFXOCTRL_TUNING_DEFAULT << 0)     /**< Shifted mode DEFAULT for CMU_LFXOCTRL */
+#define _CMU_LFXOCTRL_MODE_SHIFT                            8                                       /**< Shift value for CMU_MODE */
+#define _CMU_LFXOCTRL_MODE_MASK                             0x300UL                                 /**< Bit mask for CMU_MODE */
+#define _CMU_LFXOCTRL_MODE_DEFAULT                          0x00000000UL                            /**< Mode DEFAULT for CMU_LFXOCTRL */
+#define _CMU_LFXOCTRL_MODE_XTAL                             0x00000000UL                            /**< Mode XTAL for CMU_LFXOCTRL */
+#define _CMU_LFXOCTRL_MODE_BUFEXTCLK                        0x00000001UL                            /**< Mode BUFEXTCLK for CMU_LFXOCTRL */
+#define _CMU_LFXOCTRL_MODE_DIGEXTCLK                        0x00000002UL                            /**< Mode DIGEXTCLK for CMU_LFXOCTRL */
+#define CMU_LFXOCTRL_MODE_DEFAULT                           (_CMU_LFXOCTRL_MODE_DEFAULT << 8)       /**< Shifted mode DEFAULT for CMU_LFXOCTRL */
+#define CMU_LFXOCTRL_MODE_XTAL                              (_CMU_LFXOCTRL_MODE_XTAL << 8)          /**< Shifted mode XTAL for CMU_LFXOCTRL */
+#define CMU_LFXOCTRL_MODE_BUFEXTCLK                         (_CMU_LFXOCTRL_MODE_BUFEXTCLK << 8)     /**< Shifted mode BUFEXTCLK for CMU_LFXOCTRL */
+#define CMU_LFXOCTRL_MODE_DIGEXTCLK                         (_CMU_LFXOCTRL_MODE_DIGEXTCLK << 8)     /**< Shifted mode DIGEXTCLK for CMU_LFXOCTRL */
+#define _CMU_LFXOCTRL_GAIN_SHIFT                            11                                      /**< Shift value for CMU_GAIN */
+#define _CMU_LFXOCTRL_GAIN_MASK                             0x1800UL                                /**< Bit mask for CMU_GAIN */
+#define _CMU_LFXOCTRL_GAIN_DEFAULT                          0x00000002UL                            /**< Mode DEFAULT for CMU_LFXOCTRL */
+#define CMU_LFXOCTRL_GAIN_DEFAULT                           (_CMU_LFXOCTRL_GAIN_DEFAULT << 11)      /**< Shifted mode DEFAULT for CMU_LFXOCTRL */
+#define CMU_LFXOCTRL_HIGHAMPL                               (0x1UL << 14)                           /**< LFXO High XTAL Oscillation Amplitude Enable */
+#define _CMU_LFXOCTRL_HIGHAMPL_SHIFT                        14                                      /**< Shift value for CMU_HIGHAMPL */
+#define _CMU_LFXOCTRL_HIGHAMPL_MASK                         0x4000UL                                /**< Bit mask for CMU_HIGHAMPL */
+#define _CMU_LFXOCTRL_HIGHAMPL_DEFAULT                      0x00000000UL                            /**< Mode DEFAULT for CMU_LFXOCTRL */
+#define CMU_LFXOCTRL_HIGHAMPL_DEFAULT                       (_CMU_LFXOCTRL_HIGHAMPL_DEFAULT << 14)  /**< Shifted mode DEFAULT for CMU_LFXOCTRL */
+#define CMU_LFXOCTRL_AGC                                    (0x1UL << 15)                           /**< LFXO AGC Enable */
+#define _CMU_LFXOCTRL_AGC_SHIFT                             15                                      /**< Shift value for CMU_AGC */
+#define _CMU_LFXOCTRL_AGC_MASK                              0x8000UL                                /**< Bit mask for CMU_AGC */
+#define _CMU_LFXOCTRL_AGC_DEFAULT                           0x00000001UL                            /**< Mode DEFAULT for CMU_LFXOCTRL */
+#define CMU_LFXOCTRL_AGC_DEFAULT                            (_CMU_LFXOCTRL_AGC_DEFAULT << 15)       /**< Shifted mode DEFAULT for CMU_LFXOCTRL */
+#define _CMU_LFXOCTRL_CUR_SHIFT                             16                                      /**< Shift value for CMU_CUR */
+#define _CMU_LFXOCTRL_CUR_MASK                              0x30000UL                               /**< Bit mask for CMU_CUR */
+#define _CMU_LFXOCTRL_CUR_DEFAULT                           0x00000000UL                            /**< Mode DEFAULT for CMU_LFXOCTRL */
+#define CMU_LFXOCTRL_CUR_DEFAULT                            (_CMU_LFXOCTRL_CUR_DEFAULT << 16)       /**< Shifted mode DEFAULT for CMU_LFXOCTRL */
+#define CMU_LFXOCTRL_BUFCUR                                 (0x1UL << 20)                           /**< LFXO Buffer Bias Current */
+#define _CMU_LFXOCTRL_BUFCUR_SHIFT                          20                                      /**< Shift value for CMU_BUFCUR */
+#define _CMU_LFXOCTRL_BUFCUR_MASK                           0x100000UL                              /**< Bit mask for CMU_BUFCUR */
+#define _CMU_LFXOCTRL_BUFCUR_DEFAULT                        0x00000000UL                            /**< Mode DEFAULT for CMU_LFXOCTRL */
+#define CMU_LFXOCTRL_BUFCUR_DEFAULT                         (_CMU_LFXOCTRL_BUFCUR_DEFAULT << 20)    /**< Shifted mode DEFAULT for CMU_LFXOCTRL */
+#define _CMU_LFXOCTRL_TIMEOUT_SHIFT                         24                                      /**< Shift value for CMU_TIMEOUT */
+#define _CMU_LFXOCTRL_TIMEOUT_MASK                          0x7000000UL                             /**< Bit mask for CMU_TIMEOUT */
+#define _CMU_LFXOCTRL_TIMEOUT_2CYCLES                       0x00000000UL                            /**< Mode 2CYCLES for CMU_LFXOCTRL */
+#define _CMU_LFXOCTRL_TIMEOUT_256CYCLES                     0x00000001UL                            /**< Mode 256CYCLES for CMU_LFXOCTRL */
+#define _CMU_LFXOCTRL_TIMEOUT_1KCYCLES                      0x00000002UL                            /**< Mode 1KCYCLES for CMU_LFXOCTRL */
+#define _CMU_LFXOCTRL_TIMEOUT_2KCYCLES                      0x00000003UL                            /**< Mode 2KCYCLES for CMU_LFXOCTRL */
+#define _CMU_LFXOCTRL_TIMEOUT_4KCYCLES                      0x00000004UL                            /**< Mode 4KCYCLES for CMU_LFXOCTRL */
+#define _CMU_LFXOCTRL_TIMEOUT_8KCYCLES                      0x00000005UL                            /**< Mode 8KCYCLES for CMU_LFXOCTRL */
+#define _CMU_LFXOCTRL_TIMEOUT_16KCYCLES                     0x00000006UL                            /**< Mode 16KCYCLES for CMU_LFXOCTRL */
+#define _CMU_LFXOCTRL_TIMEOUT_DEFAULT                       0x00000007UL                            /**< Mode DEFAULT for CMU_LFXOCTRL */
+#define _CMU_LFXOCTRL_TIMEOUT_32KCYCLES                     0x00000007UL                            /**< Mode 32KCYCLES for CMU_LFXOCTRL */
+#define CMU_LFXOCTRL_TIMEOUT_2CYCLES                        (_CMU_LFXOCTRL_TIMEOUT_2CYCLES << 24)   /**< Shifted mode 2CYCLES for CMU_LFXOCTRL */
+#define CMU_LFXOCTRL_TIMEOUT_256CYCLES                      (_CMU_LFXOCTRL_TIMEOUT_256CYCLES << 24) /**< Shifted mode 256CYCLES for CMU_LFXOCTRL */
+#define CMU_LFXOCTRL_TIMEOUT_1KCYCLES                       (_CMU_LFXOCTRL_TIMEOUT_1KCYCLES << 24)  /**< Shifted mode 1KCYCLES for CMU_LFXOCTRL */
+#define CMU_LFXOCTRL_TIMEOUT_2KCYCLES                       (_CMU_LFXOCTRL_TIMEOUT_2KCYCLES << 24)  /**< Shifted mode 2KCYCLES for CMU_LFXOCTRL */
+#define CMU_LFXOCTRL_TIMEOUT_4KCYCLES                       (_CMU_LFXOCTRL_TIMEOUT_4KCYCLES << 24)  /**< Shifted mode 4KCYCLES for CMU_LFXOCTRL */
+#define CMU_LFXOCTRL_TIMEOUT_8KCYCLES                       (_CMU_LFXOCTRL_TIMEOUT_8KCYCLES << 24)  /**< Shifted mode 8KCYCLES for CMU_LFXOCTRL */
+#define CMU_LFXOCTRL_TIMEOUT_16KCYCLES                      (_CMU_LFXOCTRL_TIMEOUT_16KCYCLES << 24) /**< Shifted mode 16KCYCLES for CMU_LFXOCTRL */
+#define CMU_LFXOCTRL_TIMEOUT_DEFAULT                        (_CMU_LFXOCTRL_TIMEOUT_DEFAULT << 24)   /**< Shifted mode DEFAULT for CMU_LFXOCTRL */
+#define CMU_LFXOCTRL_TIMEOUT_32KCYCLES                      (_CMU_LFXOCTRL_TIMEOUT_32KCYCLES << 24) /**< Shifted mode 32KCYCLES for CMU_LFXOCTRL */
+
+/* Bit fields for CMU CALCTRL */
+#define _CMU_CALCTRL_RESETVALUE                             0x00000000UL                            /**< Default value for CMU_CALCTRL */
+#define _CMU_CALCTRL_MASK                                   0x0F0F0177UL                            /**< Mask for CMU_CALCTRL */
+#define _CMU_CALCTRL_UPSEL_SHIFT                            0                                       /**< Shift value for CMU_UPSEL */
+#define _CMU_CALCTRL_UPSEL_MASK                             0x7UL                                   /**< Bit mask for CMU_UPSEL */
+#define _CMU_CALCTRL_UPSEL_DEFAULT                          0x00000000UL                            /**< Mode DEFAULT for CMU_CALCTRL */
+#define _CMU_CALCTRL_UPSEL_HFXO                             0x00000000UL                            /**< Mode HFXO for CMU_CALCTRL */
+#define _CMU_CALCTRL_UPSEL_LFXO                             0x00000001UL                            /**< Mode LFXO for CMU_CALCTRL */
+#define _CMU_CALCTRL_UPSEL_HFRCO                            0x00000002UL                            /**< Mode HFRCO for CMU_CALCTRL */
+#define _CMU_CALCTRL_UPSEL_LFRCO                            0x00000003UL                            /**< Mode LFRCO for CMU_CALCTRL */
+#define _CMU_CALCTRL_UPSEL_AUXHFRCO                         0x00000004UL                            /**< Mode AUXHFRCO for CMU_CALCTRL */
+#define _CMU_CALCTRL_UPSEL_PRS                              0x00000005UL                            /**< Mode PRS for CMU_CALCTRL */
+#define CMU_CALCTRL_UPSEL_DEFAULT                           (_CMU_CALCTRL_UPSEL_DEFAULT << 0)       /**< Shifted mode DEFAULT for CMU_CALCTRL */
+#define CMU_CALCTRL_UPSEL_HFXO                              (_CMU_CALCTRL_UPSEL_HFXO << 0)          /**< Shifted mode HFXO for CMU_CALCTRL */
+#define CMU_CALCTRL_UPSEL_LFXO                              (_CMU_CALCTRL_UPSEL_LFXO << 0)          /**< Shifted mode LFXO for CMU_CALCTRL */
+#define CMU_CALCTRL_UPSEL_HFRCO                             (_CMU_CALCTRL_UPSEL_HFRCO << 0)         /**< Shifted mode HFRCO for CMU_CALCTRL */
+#define CMU_CALCTRL_UPSEL_LFRCO                             (_CMU_CALCTRL_UPSEL_LFRCO << 0)         /**< Shifted mode LFRCO for CMU_CALCTRL */
+#define CMU_CALCTRL_UPSEL_AUXHFRCO                          (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0)      /**< Shifted mode AUXHFRCO for CMU_CALCTRL */
+#define CMU_CALCTRL_UPSEL_PRS                               (_CMU_CALCTRL_UPSEL_PRS << 0)           /**< Shifted mode PRS for CMU_CALCTRL */
+#define _CMU_CALCTRL_DOWNSEL_SHIFT                          4                                       /**< Shift value for CMU_DOWNSEL */
+#define _CMU_CALCTRL_DOWNSEL_MASK                           0x70UL                                  /**< Bit mask for CMU_DOWNSEL */
+#define _CMU_CALCTRL_DOWNSEL_DEFAULT                        0x00000000UL                            /**< Mode DEFAULT for CMU_CALCTRL */
+#define _CMU_CALCTRL_DOWNSEL_HFCLK                          0x00000000UL                            /**< Mode HFCLK for CMU_CALCTRL */
+#define _CMU_CALCTRL_DOWNSEL_HFXO                           0x00000001UL                            /**< Mode HFXO for CMU_CALCTRL */
+#define _CMU_CALCTRL_DOWNSEL_LFXO                           0x00000002UL                            /**< Mode LFXO for CMU_CALCTRL */
+#define _CMU_CALCTRL_DOWNSEL_HFRCO                          0x00000003UL                            /**< Mode HFRCO for CMU_CALCTRL */
+#define _CMU_CALCTRL_DOWNSEL_LFRCO                          0x00000004UL                            /**< Mode LFRCO for CMU_CALCTRL */
+#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO                       0x00000005UL                            /**< Mode AUXHFRCO for CMU_CALCTRL */
+#define _CMU_CALCTRL_DOWNSEL_PRS                            0x00000006UL                            /**< Mode PRS for CMU_CALCTRL */
+#define CMU_CALCTRL_DOWNSEL_DEFAULT                         (_CMU_CALCTRL_DOWNSEL_DEFAULT << 4)     /**< Shifted mode DEFAULT for CMU_CALCTRL */
+#define CMU_CALCTRL_DOWNSEL_HFCLK                           (_CMU_CALCTRL_DOWNSEL_HFCLK << 4)       /**< Shifted mode HFCLK for CMU_CALCTRL */
+#define CMU_CALCTRL_DOWNSEL_HFXO                            (_CMU_CALCTRL_DOWNSEL_HFXO << 4)        /**< Shifted mode HFXO for CMU_CALCTRL */
+#define CMU_CALCTRL_DOWNSEL_LFXO                            (_CMU_CALCTRL_DOWNSEL_LFXO << 4)        /**< Shifted mode LFXO for CMU_CALCTRL */
+#define CMU_CALCTRL_DOWNSEL_HFRCO                           (_CMU_CALCTRL_DOWNSEL_HFRCO << 4)       /**< Shifted mode HFRCO for CMU_CALCTRL */
+#define CMU_CALCTRL_DOWNSEL_LFRCO                           (_CMU_CALCTRL_DOWNSEL_LFRCO << 4)       /**< Shifted mode LFRCO for CMU_CALCTRL */
+#define CMU_CALCTRL_DOWNSEL_AUXHFRCO                        (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 4)    /**< Shifted mode AUXHFRCO for CMU_CALCTRL */
+#define CMU_CALCTRL_DOWNSEL_PRS                             (_CMU_CALCTRL_DOWNSEL_PRS << 4)         /**< Shifted mode PRS for CMU_CALCTRL */
+#define CMU_CALCTRL_CONT                                    (0x1UL << 8)                            /**< Continuous Calibration */
+#define _CMU_CALCTRL_CONT_SHIFT                             8                                       /**< Shift value for CMU_CONT */
+#define _CMU_CALCTRL_CONT_MASK                              0x100UL                                 /**< Bit mask for CMU_CONT */
+#define _CMU_CALCTRL_CONT_DEFAULT                           0x00000000UL                            /**< Mode DEFAULT for CMU_CALCTRL */
+#define CMU_CALCTRL_CONT_DEFAULT                            (_CMU_CALCTRL_CONT_DEFAULT << 8)        /**< Shifted mode DEFAULT for CMU_CALCTRL */
+#define _CMU_CALCTRL_PRSUPSEL_SHIFT                         16                                      /**< Shift value for CMU_PRSUPSEL */
+#define _CMU_CALCTRL_PRSUPSEL_MASK                          0xF0000UL                               /**< Bit mask for CMU_PRSUPSEL */
+#define _CMU_CALCTRL_PRSUPSEL_DEFAULT                       0x00000000UL                            /**< Mode DEFAULT for CMU_CALCTRL */
+#define _CMU_CALCTRL_PRSUPSEL_PRSCH0                        0x00000000UL                            /**< Mode PRSCH0 for CMU_CALCTRL */
+#define _CMU_CALCTRL_PRSUPSEL_PRSCH1                        0x00000001UL                            /**< Mode PRSCH1 for CMU_CALCTRL */
+#define _CMU_CALCTRL_PRSUPSEL_PRSCH2                        0x00000002UL                            /**< Mode PRSCH2 for CMU_CALCTRL */
+#define _CMU_CALCTRL_PRSUPSEL_PRSCH3                        0x00000003UL                            /**< Mode PRSCH3 for CMU_CALCTRL */
+#define _CMU_CALCTRL_PRSUPSEL_PRSCH4                        0x00000004UL                            /**< Mode PRSCH4 for CMU_CALCTRL */
+#define _CMU_CALCTRL_PRSUPSEL_PRSCH5                        0x00000005UL                            /**< Mode PRSCH5 for CMU_CALCTRL */
+#define _CMU_CALCTRL_PRSUPSEL_PRSCH6                        0x00000006UL                            /**< Mode PRSCH6 for CMU_CALCTRL */
+#define _CMU_CALCTRL_PRSUPSEL_PRSCH7                        0x00000007UL                            /**< Mode PRSCH7 for CMU_CALCTRL */
+#define _CMU_CALCTRL_PRSUPSEL_PRSCH8                        0x00000008UL                            /**< Mode PRSCH8 for CMU_CALCTRL */
+#define _CMU_CALCTRL_PRSUPSEL_PRSCH9                        0x00000009UL                            /**< Mode PRSCH9 for CMU_CALCTRL */
+#define _CMU_CALCTRL_PRSUPSEL_PRSCH10                       0x0000000AUL                            /**< Mode PRSCH10 for CMU_CALCTRL */
+#define _CMU_CALCTRL_PRSUPSEL_PRSCH11                       0x0000000BUL                            /**< Mode PRSCH11 for CMU_CALCTRL */
+#define CMU_CALCTRL_PRSUPSEL_DEFAULT                        (_CMU_CALCTRL_PRSUPSEL_DEFAULT << 16)   /**< Shifted mode DEFAULT for CMU_CALCTRL */
+#define CMU_CALCTRL_PRSUPSEL_PRSCH0                         (_CMU_CALCTRL_PRSUPSEL_PRSCH0 << 16)    /**< Shifted mode PRSCH0 for CMU_CALCTRL */
+#define CMU_CALCTRL_PRSUPSEL_PRSCH1                         (_CMU_CALCTRL_PRSUPSEL_PRSCH1 << 16)    /**< Shifted mode PRSCH1 for CMU_CALCTRL */
+#define CMU_CALCTRL_PRSUPSEL_PRSCH2                         (_CMU_CALCTRL_PRSUPSEL_PRSCH2 << 16)    /**< Shifted mode PRSCH2 for CMU_CALCTRL */
+#define CMU_CALCTRL_PRSUPSEL_PRSCH3                         (_CMU_CALCTRL_PRSUPSEL_PRSCH3 << 16)    /**< Shifted mode PRSCH3 for CMU_CALCTRL */
+#define CMU_CALCTRL_PRSUPSEL_PRSCH4                         (_CMU_CALCTRL_PRSUPSEL_PRSCH4 << 16)    /**< Shifted mode PRSCH4 for CMU_CALCTRL */
+#define CMU_CALCTRL_PRSUPSEL_PRSCH5                         (_CMU_CALCTRL_PRSUPSEL_PRSCH5 << 16)    /**< Shifted mode PRSCH5 for CMU_CALCTRL */
+#define CMU_CALCTRL_PRSUPSEL_PRSCH6                         (_CMU_CALCTRL_PRSUPSEL_PRSCH6 << 16)    /**< Shifted mode PRSCH6 for CMU_CALCTRL */
+#define CMU_CALCTRL_PRSUPSEL_PRSCH7                         (_CMU_CALCTRL_PRSUPSEL_PRSCH7 << 16)    /**< Shifted mode PRSCH7 for CMU_CALCTRL */
+#define CMU_CALCTRL_PRSUPSEL_PRSCH8                         (_CMU_CALCTRL_PRSUPSEL_PRSCH8 << 16)    /**< Shifted mode PRSCH8 for CMU_CALCTRL */
+#define CMU_CALCTRL_PRSUPSEL_PRSCH9                         (_CMU_CALCTRL_PRSUPSEL_PRSCH9 << 16)    /**< Shifted mode PRSCH9 for CMU_CALCTRL */
+#define CMU_CALCTRL_PRSUPSEL_PRSCH10                        (_CMU_CALCTRL_PRSUPSEL_PRSCH10 << 16)   /**< Shifted mode PRSCH10 for CMU_CALCTRL */
+#define CMU_CALCTRL_PRSUPSEL_PRSCH11                        (_CMU_CALCTRL_PRSUPSEL_PRSCH11 << 16)   /**< Shifted mode PRSCH11 for CMU_CALCTRL */
+#define _CMU_CALCTRL_PRSDOWNSEL_SHIFT                       24                                      /**< Shift value for CMU_PRSDOWNSEL */
+#define _CMU_CALCTRL_PRSDOWNSEL_MASK                        0xF000000UL                             /**< Bit mask for CMU_PRSDOWNSEL */
+#define _CMU_CALCTRL_PRSDOWNSEL_DEFAULT                     0x00000000UL                            /**< Mode DEFAULT for CMU_CALCTRL */
+#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH0                      0x00000000UL                            /**< Mode PRSCH0 for CMU_CALCTRL */
+#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH1                      0x00000001UL                            /**< Mode PRSCH1 for CMU_CALCTRL */
+#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH2                      0x00000002UL                            /**< Mode PRSCH2 for CMU_CALCTRL */
+#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH3                      0x00000003UL                            /**< Mode PRSCH3 for CMU_CALCTRL */
+#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH4                      0x00000004UL                            /**< Mode PRSCH4 for CMU_CALCTRL */
+#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH5                      0x00000005UL                            /**< Mode PRSCH5 for CMU_CALCTRL */
+#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH6                      0x00000006UL                            /**< Mode PRSCH6 for CMU_CALCTRL */
+#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH7                      0x00000007UL                            /**< Mode PRSCH7 for CMU_CALCTRL */
+#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH8                      0x00000008UL                            /**< Mode PRSCH8 for CMU_CALCTRL */
+#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH9                      0x00000009UL                            /**< Mode PRSCH9 for CMU_CALCTRL */
+#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH10                     0x0000000AUL                            /**< Mode PRSCH10 for CMU_CALCTRL */
+#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH11                     0x0000000BUL                            /**< Mode PRSCH11 for CMU_CALCTRL */
+#define CMU_CALCTRL_PRSDOWNSEL_DEFAULT                      (_CMU_CALCTRL_PRSDOWNSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CALCTRL */
+#define CMU_CALCTRL_PRSDOWNSEL_PRSCH0                       (_CMU_CALCTRL_PRSDOWNSEL_PRSCH0 << 24)  /**< Shifted mode PRSCH0 for CMU_CALCTRL */
+#define CMU_CALCTRL_PRSDOWNSEL_PRSCH1                       (_CMU_CALCTRL_PRSDOWNSEL_PRSCH1 << 24)  /**< Shifted mode PRSCH1 for CMU_CALCTRL */
+#define CMU_CALCTRL_PRSDOWNSEL_PRSCH2                       (_CMU_CALCTRL_PRSDOWNSEL_PRSCH2 << 24)  /**< Shifted mode PRSCH2 for CMU_CALCTRL */
+#define CMU_CALCTRL_PRSDOWNSEL_PRSCH3                       (_CMU_CALCTRL_PRSDOWNSEL_PRSCH3 << 24)  /**< Shifted mode PRSCH3 for CMU_CALCTRL */
+#define CMU_CALCTRL_PRSDOWNSEL_PRSCH4                       (_CMU_CALCTRL_PRSDOWNSEL_PRSCH4 << 24)  /**< Shifted mode PRSCH4 for CMU_CALCTRL */
+#define CMU_CALCTRL_PRSDOWNSEL_PRSCH5                       (_CMU_CALCTRL_PRSDOWNSEL_PRSCH5 << 24)  /**< Shifted mode PRSCH5 for CMU_CALCTRL */
+#define CMU_CALCTRL_PRSDOWNSEL_PRSCH6                       (_CMU_CALCTRL_PRSDOWNSEL_PRSCH6 << 24)  /**< Shifted mode PRSCH6 for CMU_CALCTRL */
+#define CMU_CALCTRL_PRSDOWNSEL_PRSCH7                       (_CMU_CALCTRL_PRSDOWNSEL_PRSCH7 << 24)  /**< Shifted mode PRSCH7 for CMU_CALCTRL */
+#define CMU_CALCTRL_PRSDOWNSEL_PRSCH8                       (_CMU_CALCTRL_PRSDOWNSEL_PRSCH8 << 24)  /**< Shifted mode PRSCH8 for CMU_CALCTRL */
+#define CMU_CALCTRL_PRSDOWNSEL_PRSCH9                       (_CMU_CALCTRL_PRSDOWNSEL_PRSCH9 << 24)  /**< Shifted mode PRSCH9 for CMU_CALCTRL */
+#define CMU_CALCTRL_PRSDOWNSEL_PRSCH10                      (_CMU_CALCTRL_PRSDOWNSEL_PRSCH10 << 24) /**< Shifted mode PRSCH10 for CMU_CALCTRL */
+#define CMU_CALCTRL_PRSDOWNSEL_PRSCH11                      (_CMU_CALCTRL_PRSDOWNSEL_PRSCH11 << 24) /**< Shifted mode PRSCH11 for CMU_CALCTRL */
+
+/* Bit fields for CMU CALCNT */
+#define _CMU_CALCNT_RESETVALUE                              0x00000000UL                      /**< Default value for CMU_CALCNT */
+#define _CMU_CALCNT_MASK                                    0x000FFFFFUL                      /**< Mask for CMU_CALCNT */
+#define _CMU_CALCNT_CALCNT_SHIFT                            0                                 /**< Shift value for CMU_CALCNT */
+#define _CMU_CALCNT_CALCNT_MASK                             0xFFFFFUL                         /**< Bit mask for CMU_CALCNT */
+#define _CMU_CALCNT_CALCNT_DEFAULT                          0x00000000UL                      /**< Mode DEFAULT for CMU_CALCNT */
+#define CMU_CALCNT_CALCNT_DEFAULT                           (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */
+
+/* Bit fields for CMU OSCENCMD */
+#define _CMU_OSCENCMD_RESETVALUE                            0x00000000UL                             /**< Default value for CMU_OSCENCMD */
+#define _CMU_OSCENCMD_MASK                                  0x000003FFUL                             /**< Mask for CMU_OSCENCMD */
+#define CMU_OSCENCMD_HFRCOEN                                (0x1UL << 0)                             /**< HFRCO Enable */
+#define _CMU_OSCENCMD_HFRCOEN_SHIFT                         0                                        /**< Shift value for CMU_HFRCOEN */
+#define _CMU_OSCENCMD_HFRCOEN_MASK                          0x1UL                                    /**< Bit mask for CMU_HFRCOEN */
+#define _CMU_OSCENCMD_HFRCOEN_DEFAULT                       0x00000000UL                             /**< Mode DEFAULT for CMU_OSCENCMD */
+#define CMU_OSCENCMD_HFRCOEN_DEFAULT                        (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0)     /**< Shifted mode DEFAULT for CMU_OSCENCMD */
+#define CMU_OSCENCMD_HFRCODIS                               (0x1UL << 1)                             /**< HFRCO Disable */
+#define _CMU_OSCENCMD_HFRCODIS_SHIFT                        1                                        /**< Shift value for CMU_HFRCODIS */
+#define _CMU_OSCENCMD_HFRCODIS_MASK                         0x2UL                                    /**< Bit mask for CMU_HFRCODIS */
+#define _CMU_OSCENCMD_HFRCODIS_DEFAULT                      0x00000000UL                             /**< Mode DEFAULT for CMU_OSCENCMD */
+#define CMU_OSCENCMD_HFRCODIS_DEFAULT                       (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1)    /**< Shifted mode DEFAULT for CMU_OSCENCMD */
+#define CMU_OSCENCMD_HFXOEN                                 (0x1UL << 2)                             /**< HFXO Enable */
+#define _CMU_OSCENCMD_HFXOEN_SHIFT                          2                                        /**< Shift value for CMU_HFXOEN */
+#define _CMU_OSCENCMD_HFXOEN_MASK                           0x4UL                                    /**< Bit mask for CMU_HFXOEN */
+#define _CMU_OSCENCMD_HFXOEN_DEFAULT                        0x00000000UL                             /**< Mode DEFAULT for CMU_OSCENCMD */
+#define CMU_OSCENCMD_HFXOEN_DEFAULT                         (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2)      /**< Shifted mode DEFAULT for CMU_OSCENCMD */
+#define CMU_OSCENCMD_HFXODIS                                (0x1UL << 3)                             /**< HFXO Disable */
+#define _CMU_OSCENCMD_HFXODIS_SHIFT                         3                                        /**< Shift value for CMU_HFXODIS */
+#define _CMU_OSCENCMD_HFXODIS_MASK                          0x8UL                                    /**< Bit mask for CMU_HFXODIS */
+#define _CMU_OSCENCMD_HFXODIS_DEFAULT                       0x00000000UL                             /**< Mode DEFAULT for CMU_OSCENCMD */
+#define CMU_OSCENCMD_HFXODIS_DEFAULT                        (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3)     /**< Shifted mode DEFAULT for CMU_OSCENCMD */
+#define CMU_OSCENCMD_AUXHFRCOEN                             (0x1UL << 4)                             /**< AUXHFRCO Enable */
+#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT                      4                                        /**< Shift value for CMU_AUXHFRCOEN */
+#define _CMU_OSCENCMD_AUXHFRCOEN_MASK                       0x10UL                                   /**< Bit mask for CMU_AUXHFRCOEN */
+#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT                    0x00000000UL                             /**< Mode DEFAULT for CMU_OSCENCMD */
+#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT                     (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4)  /**< Shifted mode DEFAULT for CMU_OSCENCMD */
+#define CMU_OSCENCMD_AUXHFRCODIS                            (0x1UL << 5)                             /**< AUXHFRCO Disable */
+#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT                     5                                        /**< Shift value for CMU_AUXHFRCODIS */
+#define _CMU_OSCENCMD_AUXHFRCODIS_MASK                      0x20UL                                   /**< Bit mask for CMU_AUXHFRCODIS */
+#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT                   0x00000000UL                             /**< Mode DEFAULT for CMU_OSCENCMD */
+#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT                    (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
+#define CMU_OSCENCMD_LFRCOEN                                (0x1UL << 6)                             /**< LFRCO Enable */
+#define _CMU_OSCENCMD_LFRCOEN_SHIFT                         6                                        /**< Shift value for CMU_LFRCOEN */
+#define _CMU_OSCENCMD_LFRCOEN_MASK                          0x40UL                                   /**< Bit mask for CMU_LFRCOEN */
+#define _CMU_OSCENCMD_LFRCOEN_DEFAULT                       0x00000000UL                             /**< Mode DEFAULT for CMU_OSCENCMD */
+#define CMU_OSCENCMD_LFRCOEN_DEFAULT                        (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6)     /**< Shifted mode DEFAULT for CMU_OSCENCMD */
+#define CMU_OSCENCMD_LFRCODIS                               (0x1UL << 7)                             /**< LFRCO Disable */
+#define _CMU_OSCENCMD_LFRCODIS_SHIFT                        7                                        /**< Shift value for CMU_LFRCODIS */
+#define _CMU_OSCENCMD_LFRCODIS_MASK                         0x80UL                                   /**< Bit mask for CMU_LFRCODIS */
+#define _CMU_OSCENCMD_LFRCODIS_DEFAULT                      0x00000000UL                             /**< Mode DEFAULT for CMU_OSCENCMD */
+#define CMU_OSCENCMD_LFRCODIS_DEFAULT                       (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7)    /**< Shifted mode DEFAULT for CMU_OSCENCMD */
+#define CMU_OSCENCMD_LFXOEN                                 (0x1UL << 8)                             /**< LFXO Enable */
+#define _CMU_OSCENCMD_LFXOEN_SHIFT                          8                                        /**< Shift value for CMU_LFXOEN */
+#define _CMU_OSCENCMD_LFXOEN_MASK                           0x100UL                                  /**< Bit mask for CMU_LFXOEN */
+#define _CMU_OSCENCMD_LFXOEN_DEFAULT                        0x00000000UL                             /**< Mode DEFAULT for CMU_OSCENCMD */
+#define CMU_OSCENCMD_LFXOEN_DEFAULT                         (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8)      /**< Shifted mode DEFAULT for CMU_OSCENCMD */
+#define CMU_OSCENCMD_LFXODIS                                (0x1UL << 9)                             /**< LFXO Disable */
+#define _CMU_OSCENCMD_LFXODIS_SHIFT                         9                                        /**< Shift value for CMU_LFXODIS */
+#define _CMU_OSCENCMD_LFXODIS_MASK                          0x200UL                                  /**< Bit mask for CMU_LFXODIS */
+#define _CMU_OSCENCMD_LFXODIS_DEFAULT                       0x00000000UL                             /**< Mode DEFAULT for CMU_OSCENCMD */
+#define CMU_OSCENCMD_LFXODIS_DEFAULT                        (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9)     /**< Shifted mode DEFAULT for CMU_OSCENCMD */
+
+/* Bit fields for CMU CMD */
+#define _CMU_CMD_RESETVALUE                                 0x00000000UL                              /**< Default value for CMU_CMD */
+#define _CMU_CMD_MASK                                       0x00000033UL                              /**< Mask for CMU_CMD */
+#define CMU_CMD_CALSTART                                    (0x1UL << 0)                              /**< Calibration Start */
+#define _CMU_CMD_CALSTART_SHIFT                             0                                         /**< Shift value for CMU_CALSTART */
+#define _CMU_CMD_CALSTART_MASK                              0x1UL                                     /**< Bit mask for CMU_CALSTART */
+#define _CMU_CMD_CALSTART_DEFAULT                           0x00000000UL                              /**< Mode DEFAULT for CMU_CMD */
+#define CMU_CMD_CALSTART_DEFAULT                            (_CMU_CMD_CALSTART_DEFAULT << 0)          /**< Shifted mode DEFAULT for CMU_CMD */
+#define CMU_CMD_CALSTOP                                     (0x1UL << 1)                              /**< Calibration Stop */
+#define _CMU_CMD_CALSTOP_SHIFT                              1                                         /**< Shift value for CMU_CALSTOP */
+#define _CMU_CMD_CALSTOP_MASK                               0x2UL                                     /**< Bit mask for CMU_CALSTOP */
+#define _CMU_CMD_CALSTOP_DEFAULT                            0x00000000UL                              /**< Mode DEFAULT for CMU_CMD */
+#define CMU_CMD_CALSTOP_DEFAULT                             (_CMU_CMD_CALSTOP_DEFAULT << 1)           /**< Shifted mode DEFAULT for CMU_CMD */
+#define CMU_CMD_HFXOPEAKDETSTART                            (0x1UL << 4)                              /**< HFXO Peak Detection Start */
+#define _CMU_CMD_HFXOPEAKDETSTART_SHIFT                     4                                         /**< Shift value for CMU_HFXOPEAKDETSTART */
+#define _CMU_CMD_HFXOPEAKDETSTART_MASK                      0x10UL                                    /**< Bit mask for CMU_HFXOPEAKDETSTART */
+#define _CMU_CMD_HFXOPEAKDETSTART_DEFAULT                   0x00000000UL                              /**< Mode DEFAULT for CMU_CMD */
+#define CMU_CMD_HFXOPEAKDETSTART_DEFAULT                    (_CMU_CMD_HFXOPEAKDETSTART_DEFAULT << 4)  /**< Shifted mode DEFAULT for CMU_CMD */
+#define CMU_CMD_HFXOSHUNTOPTSTART                           (0x1UL << 5)                              /**< HFXO Shunt Current Optimization Start */
+#define _CMU_CMD_HFXOSHUNTOPTSTART_SHIFT                    5                                         /**< Shift value for CMU_HFXOSHUNTOPTSTART */
+#define _CMU_CMD_HFXOSHUNTOPTSTART_MASK                     0x20UL                                    /**< Bit mask for CMU_HFXOSHUNTOPTSTART */
+#define _CMU_CMD_HFXOSHUNTOPTSTART_DEFAULT                  0x00000000UL                              /**< Mode DEFAULT for CMU_CMD */
+#define CMU_CMD_HFXOSHUNTOPTSTART_DEFAULT                   (_CMU_CMD_HFXOSHUNTOPTSTART_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CMD */
+
+/* Bit fields for CMU DBGCLKSEL */
+#define _CMU_DBGCLKSEL_RESETVALUE                           0x00000000UL                       /**< Default value for CMU_DBGCLKSEL */
+#define _CMU_DBGCLKSEL_MASK                                 0x00000001UL                       /**< Mask for CMU_DBGCLKSEL */
+#define _CMU_DBGCLKSEL_DBG_SHIFT                            0                                  /**< Shift value for CMU_DBG */
+#define _CMU_DBGCLKSEL_DBG_MASK                             0x1UL                              /**< Bit mask for CMU_DBG */
+#define _CMU_DBGCLKSEL_DBG_DEFAULT                          0x00000000UL                       /**< Mode DEFAULT for CMU_DBGCLKSEL */
+#define _CMU_DBGCLKSEL_DBG_AUXHFRCO                         0x00000000UL                       /**< Mode AUXHFRCO for CMU_DBGCLKSEL */
+#define _CMU_DBGCLKSEL_DBG_HFCLK                            0x00000001UL                       /**< Mode HFCLK for CMU_DBGCLKSEL */
+#define CMU_DBGCLKSEL_DBG_DEFAULT                           (_CMU_DBGCLKSEL_DBG_DEFAULT << 0)  /**< Shifted mode DEFAULT for CMU_DBGCLKSEL */
+#define CMU_DBGCLKSEL_DBG_AUXHFRCO                          (_CMU_DBGCLKSEL_DBG_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_DBGCLKSEL */
+#define CMU_DBGCLKSEL_DBG_HFCLK                             (_CMU_DBGCLKSEL_DBG_HFCLK << 0)    /**< Shifted mode HFCLK for CMU_DBGCLKSEL */
+
+/* Bit fields for CMU HFCLKSEL */
+#define _CMU_HFCLKSEL_RESETVALUE                            0x00000000UL                    /**< Default value for CMU_HFCLKSEL */
+#define _CMU_HFCLKSEL_MASK                                  0x00000007UL                    /**< Mask for CMU_HFCLKSEL */
+#define _CMU_HFCLKSEL_HF_SHIFT                              0                               /**< Shift value for CMU_HF */
+#define _CMU_HFCLKSEL_HF_MASK                               0x7UL                           /**< Bit mask for CMU_HF */
+#define _CMU_HFCLKSEL_HF_DEFAULT                            0x00000000UL                    /**< Mode DEFAULT for CMU_HFCLKSEL */
+#define _CMU_HFCLKSEL_HF_HFRCO                              0x00000001UL                    /**< Mode HFRCO for CMU_HFCLKSEL */
+#define _CMU_HFCLKSEL_HF_HFXO                               0x00000002UL                    /**< Mode HFXO for CMU_HFCLKSEL */
+#define _CMU_HFCLKSEL_HF_LFRCO                              0x00000003UL                    /**< Mode LFRCO for CMU_HFCLKSEL */
+#define _CMU_HFCLKSEL_HF_LFXO                               0x00000004UL                    /**< Mode LFXO for CMU_HFCLKSEL */
+#define CMU_HFCLKSEL_HF_DEFAULT                             (_CMU_HFCLKSEL_HF_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSEL */
+#define CMU_HFCLKSEL_HF_HFRCO                               (_CMU_HFCLKSEL_HF_HFRCO << 0)   /**< Shifted mode HFRCO for CMU_HFCLKSEL */
+#define CMU_HFCLKSEL_HF_HFXO                                (_CMU_HFCLKSEL_HF_HFXO << 0)    /**< Shifted mode HFXO for CMU_HFCLKSEL */
+#define CMU_HFCLKSEL_HF_LFRCO                               (_CMU_HFCLKSEL_HF_LFRCO << 0)   /**< Shifted mode LFRCO for CMU_HFCLKSEL */
+#define CMU_HFCLKSEL_HF_LFXO                                (_CMU_HFCLKSEL_HF_LFXO << 0)    /**< Shifted mode LFXO for CMU_HFCLKSEL */
+
+/* Bit fields for CMU LFACLKSEL */
+#define _CMU_LFACLKSEL_RESETVALUE                           0x00000000UL                       /**< Default value for CMU_LFACLKSEL */
+#define _CMU_LFACLKSEL_MASK                                 0x00000007UL                       /**< Mask for CMU_LFACLKSEL */
+#define _CMU_LFACLKSEL_LFA_SHIFT                            0                                  /**< Shift value for CMU_LFA */
+#define _CMU_LFACLKSEL_LFA_MASK                             0x7UL                              /**< Bit mask for CMU_LFA */
+#define _CMU_LFACLKSEL_LFA_DEFAULT                          0x00000000UL                       /**< Mode DEFAULT for CMU_LFACLKSEL */
+#define _CMU_LFACLKSEL_LFA_DISABLED                         0x00000000UL                       /**< Mode DISABLED for CMU_LFACLKSEL */
+#define _CMU_LFACLKSEL_LFA_LFRCO                            0x00000001UL                       /**< Mode LFRCO for CMU_LFACLKSEL */
+#define _CMU_LFACLKSEL_LFA_LFXO                             0x00000002UL                       /**< Mode LFXO for CMU_LFACLKSEL */
+#define _CMU_LFACLKSEL_LFA_ULFRCO                           0x00000004UL                       /**< Mode ULFRCO for CMU_LFACLKSEL */
+#define CMU_LFACLKSEL_LFA_DEFAULT                           (_CMU_LFACLKSEL_LFA_DEFAULT << 0)  /**< Shifted mode DEFAULT for CMU_LFACLKSEL */
+#define CMU_LFACLKSEL_LFA_DISABLED                          (_CMU_LFACLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFACLKSEL */
+#define CMU_LFACLKSEL_LFA_LFRCO                             (_CMU_LFACLKSEL_LFA_LFRCO << 0)    /**< Shifted mode LFRCO for CMU_LFACLKSEL */
+#define CMU_LFACLKSEL_LFA_LFXO                              (_CMU_LFACLKSEL_LFA_LFXO << 0)     /**< Shifted mode LFXO for CMU_LFACLKSEL */
+#define CMU_LFACLKSEL_LFA_ULFRCO                            (_CMU_LFACLKSEL_LFA_ULFRCO << 0)   /**< Shifted mode ULFRCO for CMU_LFACLKSEL */
+
+/* Bit fields for CMU LFBCLKSEL */
+#define _CMU_LFBCLKSEL_RESETVALUE                           0x00000000UL                       /**< Default value for CMU_LFBCLKSEL */
+#define _CMU_LFBCLKSEL_MASK                                 0x00000007UL                       /**< Mask for CMU_LFBCLKSEL */
+#define _CMU_LFBCLKSEL_LFB_SHIFT                            0                                  /**< Shift value for CMU_LFB */
+#define _CMU_LFBCLKSEL_LFB_MASK                             0x7UL                              /**< Bit mask for CMU_LFB */
+#define _CMU_LFBCLKSEL_LFB_DEFAULT                          0x00000000UL                       /**< Mode DEFAULT for CMU_LFBCLKSEL */
+#define _CMU_LFBCLKSEL_LFB_DISABLED                         0x00000000UL                       /**< Mode DISABLED for CMU_LFBCLKSEL */
+#define _CMU_LFBCLKSEL_LFB_LFRCO                            0x00000001UL                       /**< Mode LFRCO for CMU_LFBCLKSEL */
+#define _CMU_LFBCLKSEL_LFB_LFXO                             0x00000002UL                       /**< Mode LFXO for CMU_LFBCLKSEL */
+#define _CMU_LFBCLKSEL_LFB_HFCLKLE                          0x00000003UL                       /**< Mode HFCLKLE for CMU_LFBCLKSEL */
+#define _CMU_LFBCLKSEL_LFB_ULFRCO                           0x00000004UL                       /**< Mode ULFRCO for CMU_LFBCLKSEL */
+#define CMU_LFBCLKSEL_LFB_DEFAULT                           (_CMU_LFBCLKSEL_LFB_DEFAULT << 0)  /**< Shifted mode DEFAULT for CMU_LFBCLKSEL */
+#define CMU_LFBCLKSEL_LFB_DISABLED                          (_CMU_LFBCLKSEL_LFB_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFBCLKSEL */
+#define CMU_LFBCLKSEL_LFB_LFRCO                             (_CMU_LFBCLKSEL_LFB_LFRCO << 0)    /**< Shifted mode LFRCO for CMU_LFBCLKSEL */
+#define CMU_LFBCLKSEL_LFB_LFXO                              (_CMU_LFBCLKSEL_LFB_LFXO << 0)     /**< Shifted mode LFXO for CMU_LFBCLKSEL */
+#define CMU_LFBCLKSEL_LFB_HFCLKLE                           (_CMU_LFBCLKSEL_LFB_HFCLKLE << 0)  /**< Shifted mode HFCLKLE for CMU_LFBCLKSEL */
+#define CMU_LFBCLKSEL_LFB_ULFRCO                            (_CMU_LFBCLKSEL_LFB_ULFRCO << 0)   /**< Shifted mode ULFRCO for CMU_LFBCLKSEL */
+
+/* Bit fields for CMU LFECLKSEL */
+#define _CMU_LFECLKSEL_RESETVALUE                           0x00000000UL                       /**< Default value for CMU_LFECLKSEL */
+#define _CMU_LFECLKSEL_MASK                                 0x00000007UL                       /**< Mask for CMU_LFECLKSEL */
+#define _CMU_LFECLKSEL_LFE_SHIFT                            0                                  /**< Shift value for CMU_LFE */
+#define _CMU_LFECLKSEL_LFE_MASK                             0x7UL                              /**< Bit mask for CMU_LFE */
+#define _CMU_LFECLKSEL_LFE_DEFAULT                          0x00000000UL                       /**< Mode DEFAULT for CMU_LFECLKSEL */
+#define _CMU_LFECLKSEL_LFE_DISABLED                         0x00000000UL                       /**< Mode DISABLED for CMU_LFECLKSEL */
+#define _CMU_LFECLKSEL_LFE_LFRCO                            0x00000001UL                       /**< Mode LFRCO for CMU_LFECLKSEL */
+#define _CMU_LFECLKSEL_LFE_LFXO                             0x00000002UL                       /**< Mode LFXO for CMU_LFECLKSEL */
+#define _CMU_LFECLKSEL_LFE_ULFRCO                           0x00000004UL                       /**< Mode ULFRCO for CMU_LFECLKSEL */
+#define CMU_LFECLKSEL_LFE_DEFAULT                           (_CMU_LFECLKSEL_LFE_DEFAULT << 0)  /**< Shifted mode DEFAULT for CMU_LFECLKSEL */
+#define CMU_LFECLKSEL_LFE_DISABLED                          (_CMU_LFECLKSEL_LFE_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFECLKSEL */
+#define CMU_LFECLKSEL_LFE_LFRCO                             (_CMU_LFECLKSEL_LFE_LFRCO << 0)    /**< Shifted mode LFRCO for CMU_LFECLKSEL */
+#define CMU_LFECLKSEL_LFE_LFXO                              (_CMU_LFECLKSEL_LFE_LFXO << 0)     /**< Shifted mode LFXO for CMU_LFECLKSEL */
+#define CMU_LFECLKSEL_LFE_ULFRCO                            (_CMU_LFECLKSEL_LFE_ULFRCO << 0)   /**< Shifted mode ULFRCO for CMU_LFECLKSEL */
+
+/* Bit fields for CMU STATUS */
+#define _CMU_STATUS_RESETVALUE                              0x00010003UL                                /**< Default value for CMU_STATUS */
+#define _CMU_STATUS_MASK                                    0x07D103FFUL                                /**< Mask for CMU_STATUS */
+#define CMU_STATUS_HFRCOENS                                 (0x1UL << 0)                                /**< HFRCO Enable Status */
+#define _CMU_STATUS_HFRCOENS_SHIFT                          0                                           /**< Shift value for CMU_HFRCOENS */
+#define _CMU_STATUS_HFRCOENS_MASK                           0x1UL                                       /**< Bit mask for CMU_HFRCOENS */
+#define _CMU_STATUS_HFRCOENS_DEFAULT                        0x00000001UL                                /**< Mode DEFAULT for CMU_STATUS */
+#define CMU_STATUS_HFRCOENS_DEFAULT                         (_CMU_STATUS_HFRCOENS_DEFAULT << 0)         /**< Shifted mode DEFAULT for CMU_STATUS */
+#define CMU_STATUS_HFRCORDY                                 (0x1UL << 1)                                /**< HFRCO Ready */
+#define _CMU_STATUS_HFRCORDY_SHIFT                          1                                           /**< Shift value for CMU_HFRCORDY */
+#define _CMU_STATUS_HFRCORDY_MASK                           0x2UL                                       /**< Bit mask for CMU_HFRCORDY */
+#define _CMU_STATUS_HFRCORDY_DEFAULT                        0x00000001UL                                /**< Mode DEFAULT for CMU_STATUS */
+#define CMU_STATUS_HFRCORDY_DEFAULT                         (_CMU_STATUS_HFRCORDY_DEFAULT << 1)         /**< Shifted mode DEFAULT for CMU_STATUS */
+#define CMU_STATUS_HFXOENS                                  (0x1UL << 2)                                /**< HFXO Enable Status */
+#define _CMU_STATUS_HFXOENS_SHIFT                           2                                           /**< Shift value for CMU_HFXOENS */
+#define _CMU_STATUS_HFXOENS_MASK                            0x4UL                                       /**< Bit mask for CMU_HFXOENS */
+#define _CMU_STATUS_HFXOENS_DEFAULT                         0x00000000UL                                /**< Mode DEFAULT for CMU_STATUS */
+#define CMU_STATUS_HFXOENS_DEFAULT                          (_CMU_STATUS_HFXOENS_DEFAULT << 2)          /**< Shifted mode DEFAULT for CMU_STATUS */
+#define CMU_STATUS_HFXORDY                                  (0x1UL << 3)                                /**< HFXO Ready */
+#define _CMU_STATUS_HFXORDY_SHIFT                           3                                           /**< Shift value for CMU_HFXORDY */
+#define _CMU_STATUS_HFXORDY_MASK                            0x8UL                                       /**< Bit mask for CMU_HFXORDY */
+#define _CMU_STATUS_HFXORDY_DEFAULT                         0x00000000UL                                /**< Mode DEFAULT for CMU_STATUS */
+#define CMU_STATUS_HFXORDY_DEFAULT                          (_CMU_STATUS_HFXORDY_DEFAULT << 3)          /**< Shifted mode DEFAULT for CMU_STATUS */
+#define CMU_STATUS_AUXHFRCOENS                              (0x1UL << 4)                                /**< AUXHFRCO Enable Status */
+#define _CMU_STATUS_AUXHFRCOENS_SHIFT                       4                                           /**< Shift value for CMU_AUXHFRCOENS */
+#define _CMU_STATUS_AUXHFRCOENS_MASK                        0x10UL                                      /**< Bit mask for CMU_AUXHFRCOENS */
+#define _CMU_STATUS_AUXHFRCOENS_DEFAULT                     0x00000000UL                                /**< Mode DEFAULT for CMU_STATUS */
+#define CMU_STATUS_AUXHFRCOENS_DEFAULT                      (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4)      /**< Shifted mode DEFAULT for CMU_STATUS */
+#define CMU_STATUS_AUXHFRCORDY                              (0x1UL << 5)                                /**< AUXHFRCO Ready */
+#define _CMU_STATUS_AUXHFRCORDY_SHIFT                       5                                           /**< Shift value for CMU_AUXHFRCORDY */
+#define _CMU_STATUS_AUXHFRCORDY_MASK                        0x20UL                                      /**< Bit mask for CMU_AUXHFRCORDY */
+#define _CMU_STATUS_AUXHFRCORDY_DEFAULT                     0x00000000UL                                /**< Mode DEFAULT for CMU_STATUS */
+#define CMU_STATUS_AUXHFRCORDY_DEFAULT                      (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5)      /**< Shifted mode DEFAULT for CMU_STATUS */
+#define CMU_STATUS_LFRCOENS                                 (0x1UL << 6)                                /**< LFRCO Enable Status */
+#define _CMU_STATUS_LFRCOENS_SHIFT                          6                                           /**< Shift value for CMU_LFRCOENS */
+#define _CMU_STATUS_LFRCOENS_MASK                           0x40UL                                      /**< Bit mask for CMU_LFRCOENS */
+#define _CMU_STATUS_LFRCOENS_DEFAULT                        0x00000000UL                                /**< Mode DEFAULT for CMU_STATUS */
+#define CMU_STATUS_LFRCOENS_DEFAULT                         (_CMU_STATUS_LFRCOENS_DEFAULT << 6)         /**< Shifted mode DEFAULT for CMU_STATUS */
+#define CMU_STATUS_LFRCORDY                                 (0x1UL << 7)                                /**< LFRCO Ready */
+#define _CMU_STATUS_LFRCORDY_SHIFT                          7                                           /**< Shift value for CMU_LFRCORDY */
+#define _CMU_STATUS_LFRCORDY_MASK                           0x80UL                                      /**< Bit mask for CMU_LFRCORDY */
+#define _CMU_STATUS_LFRCORDY_DEFAULT                        0x00000000UL                                /**< Mode DEFAULT for CMU_STATUS */
+#define CMU_STATUS_LFRCORDY_DEFAULT                         (_CMU_STATUS_LFRCORDY_DEFAULT << 7)         /**< Shifted mode DEFAULT for CMU_STATUS */
+#define CMU_STATUS_LFXOENS                                  (0x1UL << 8)                                /**< LFXO Enable Status */
+#define _CMU_STATUS_LFXOENS_SHIFT                           8                                           /**< Shift value for CMU_LFXOENS */
+#define _CMU_STATUS_LFXOENS_MASK                            0x100UL                                     /**< Bit mask for CMU_LFXOENS */
+#define _CMU_STATUS_LFXOENS_DEFAULT                         0x00000000UL                                /**< Mode DEFAULT for CMU_STATUS */
+#define CMU_STATUS_LFXOENS_DEFAULT                          (_CMU_STATUS_LFXOENS_DEFAULT << 8)          /**< Shifted mode DEFAULT for CMU_STATUS */
+#define CMU_STATUS_LFXORDY                                  (0x1UL << 9)                                /**< LFXO Ready */
+#define _CMU_STATUS_LFXORDY_SHIFT                           9                                           /**< Shift value for CMU_LFXORDY */
+#define _CMU_STATUS_LFXORDY_MASK                            0x200UL                                     /**< Bit mask for CMU_LFXORDY */
+#define _CMU_STATUS_LFXORDY_DEFAULT                         0x00000000UL                                /**< Mode DEFAULT for CMU_STATUS */
+#define CMU_STATUS_LFXORDY_DEFAULT                          (_CMU_STATUS_LFXORDY_DEFAULT << 9)          /**< Shifted mode DEFAULT for CMU_STATUS */
+#define CMU_STATUS_CALRDY                                   (0x1UL << 16)                               /**< Calibration Ready */
+#define _CMU_STATUS_CALRDY_SHIFT                            16                                          /**< Shift value for CMU_CALRDY */
+#define _CMU_STATUS_CALRDY_MASK                             0x10000UL                                   /**< Bit mask for CMU_CALRDY */
+#define _CMU_STATUS_CALRDY_DEFAULT                          0x00000001UL                                /**< Mode DEFAULT for CMU_STATUS */
+#define CMU_STATUS_CALRDY_DEFAULT                           (_CMU_STATUS_CALRDY_DEFAULT << 16)          /**< Shifted mode DEFAULT for CMU_STATUS */
+#define CMU_STATUS_HFXOWARMS                                (0x1UL << 20)                               /**< HFXO Warm Status */
+#define _CMU_STATUS_HFXOWARMS_SHIFT                         20                                          /**< Shift value for CMU_HFXOWARMS */
+#define _CMU_STATUS_HFXOWARMS_MASK                          0x100000UL                                  /**< Bit mask for CMU_HFXOWARMS */
+#define _CMU_STATUS_HFXOWARMS_DEFAULT                       0x00000000UL                                /**< Mode DEFAULT for CMU_STATUS */
+#define CMU_STATUS_HFXOWARMS_DEFAULT                        (_CMU_STATUS_HFXOWARMS_DEFAULT << 20)       /**< Shifted mode DEFAULT for CMU_STATUS */
+#define CMU_STATUS_HFXOPEAKDETRDY                           (0x1UL << 22)                               /**< HFXO Peak Detection Ready */
+#define _CMU_STATUS_HFXOPEAKDETRDY_SHIFT                    22                                          /**< Shift value for CMU_HFXOPEAKDETRDY */
+#define _CMU_STATUS_HFXOPEAKDETRDY_MASK                     0x400000UL                                  /**< Bit mask for CMU_HFXOPEAKDETRDY */
+#define _CMU_STATUS_HFXOPEAKDETRDY_DEFAULT                  0x00000000UL                                /**< Mode DEFAULT for CMU_STATUS */
+#define CMU_STATUS_HFXOPEAKDETRDY_DEFAULT                   (_CMU_STATUS_HFXOPEAKDETRDY_DEFAULT << 22)  /**< Shifted mode DEFAULT for CMU_STATUS */
+#define CMU_STATUS_HFXOSHUNTOPTRDY                          (0x1UL << 23)                               /**< HFXO Shunt Current Optimization ready */
+#define _CMU_STATUS_HFXOSHUNTOPTRDY_SHIFT                   23                                          /**< Shift value for CMU_HFXOSHUNTOPTRDY */
+#define _CMU_STATUS_HFXOSHUNTOPTRDY_MASK                    0x800000UL                                  /**< Bit mask for CMU_HFXOSHUNTOPTRDY */
+#define _CMU_STATUS_HFXOSHUNTOPTRDY_DEFAULT                 0x00000000UL                                /**< Mode DEFAULT for CMU_STATUS */
+#define CMU_STATUS_HFXOSHUNTOPTRDY_DEFAULT                  (_CMU_STATUS_HFXOSHUNTOPTRDY_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_STATUS */
+#define CMU_STATUS_HFXOAMPHIGH                              (0x1UL << 24)                               /**< HFXO oscillation amplitude is too high */
+#define _CMU_STATUS_HFXOAMPHIGH_SHIFT                       24                                          /**< Shift value for CMU_HFXOAMPHIGH */
+#define _CMU_STATUS_HFXOAMPHIGH_MASK                        0x1000000UL                                 /**< Bit mask for CMU_HFXOAMPHIGH */
+#define _CMU_STATUS_HFXOAMPHIGH_DEFAULT                     0x00000000UL                                /**< Mode DEFAULT for CMU_STATUS */
+#define CMU_STATUS_HFXOAMPHIGH_DEFAULT                      (_CMU_STATUS_HFXOAMPHIGH_DEFAULT << 24)     /**< Shifted mode DEFAULT for CMU_STATUS */
+#define CMU_STATUS_HFXOAMPLOW                               (0x1UL << 25)                               /**< HFXO amplitude tuning value too low */
+#define _CMU_STATUS_HFXOAMPLOW_SHIFT                        25                                          /**< Shift value for CMU_HFXOAMPLOW */
+#define _CMU_STATUS_HFXOAMPLOW_MASK                         0x2000000UL                                 /**< Bit mask for CMU_HFXOAMPLOW */
+#define _CMU_STATUS_HFXOAMPLOW_DEFAULT                      0x00000000UL                                /**< Mode DEFAULT for CMU_STATUS */
+#define CMU_STATUS_HFXOAMPLOW_DEFAULT                       (_CMU_STATUS_HFXOAMPLOW_DEFAULT << 25)      /**< Shifted mode DEFAULT for CMU_STATUS */
+#define CMU_STATUS_HFXOREGILOW                              (0x1UL << 26)                               /**< HFXO regulator shunt current too low */
+#define _CMU_STATUS_HFXOREGILOW_SHIFT                       26                                          /**< Shift value for CMU_HFXOREGILOW */
+#define _CMU_STATUS_HFXOREGILOW_MASK                        0x4000000UL                                 /**< Bit mask for CMU_HFXOREGILOW */
+#define _CMU_STATUS_HFXOREGILOW_DEFAULT                     0x00000000UL                                /**< Mode DEFAULT for CMU_STATUS */
+#define CMU_STATUS_HFXOREGILOW_DEFAULT                      (_CMU_STATUS_HFXOREGILOW_DEFAULT << 26)     /**< Shifted mode DEFAULT for CMU_STATUS */
+
+/* Bit fields for CMU HFCLKSTATUS */
+#define _CMU_HFCLKSTATUS_RESETVALUE                         0x00000001UL                             /**< Default value for CMU_HFCLKSTATUS */
+#define _CMU_HFCLKSTATUS_MASK                               0x00000007UL                             /**< Mask for CMU_HFCLKSTATUS */
+#define _CMU_HFCLKSTATUS_SELECTED_SHIFT                     0                                        /**< Shift value for CMU_SELECTED */
+#define _CMU_HFCLKSTATUS_SELECTED_MASK                      0x7UL                                    /**< Bit mask for CMU_SELECTED */
+#define _CMU_HFCLKSTATUS_SELECTED_DEFAULT                   0x00000001UL                             /**< Mode DEFAULT for CMU_HFCLKSTATUS */
+#define _CMU_HFCLKSTATUS_SELECTED_HFRCO                     0x00000001UL                             /**< Mode HFRCO for CMU_HFCLKSTATUS */
+#define _CMU_HFCLKSTATUS_SELECTED_HFXO                      0x00000002UL                             /**< Mode HFXO for CMU_HFCLKSTATUS */
+#define _CMU_HFCLKSTATUS_SELECTED_LFRCO                     0x00000003UL                             /**< Mode LFRCO for CMU_HFCLKSTATUS */
+#define _CMU_HFCLKSTATUS_SELECTED_LFXO                      0x00000004UL                             /**< Mode LFXO for CMU_HFCLKSTATUS */
+#define CMU_HFCLKSTATUS_SELECTED_DEFAULT                    (_CMU_HFCLKSTATUS_SELECTED_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSTATUS */
+#define CMU_HFCLKSTATUS_SELECTED_HFRCO                      (_CMU_HFCLKSTATUS_SELECTED_HFRCO << 0)   /**< Shifted mode HFRCO for CMU_HFCLKSTATUS */
+#define CMU_HFCLKSTATUS_SELECTED_HFXO                       (_CMU_HFCLKSTATUS_SELECTED_HFXO << 0)    /**< Shifted mode HFXO for CMU_HFCLKSTATUS */
+#define CMU_HFCLKSTATUS_SELECTED_LFRCO                      (_CMU_HFCLKSTATUS_SELECTED_LFRCO << 0)   /**< Shifted mode LFRCO for CMU_HFCLKSTATUS */
+#define CMU_HFCLKSTATUS_SELECTED_LFXO                       (_CMU_HFCLKSTATUS_SELECTED_LFXO << 0)    /**< Shifted mode LFXO for CMU_HFCLKSTATUS */
+
+/* Bit fields for CMU HFXOTRIMSTATUS */
+#define _CMU_HFXOTRIMSTATUS_RESETVALUE                      0x00000500UL                                    /**< Default value for CMU_HFXOTRIMSTATUS */
+#define _CMU_HFXOTRIMSTATUS_MASK                            0x000007FFUL                                    /**< Mask for CMU_HFXOTRIMSTATUS */
+#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_SHIFT              0                                               /**< Shift value for CMU_IBTRIMXOCORE */
+#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_MASK               0x7FUL                                          /**< Bit mask for CMU_IBTRIMXOCORE */
+#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT            0x00000000UL                                    /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */
+#define CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT             (_CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */
+#define _CMU_HFXOTRIMSTATUS_REGISH_SHIFT                    7                                               /**< Shift value for CMU_REGISH */
+#define _CMU_HFXOTRIMSTATUS_REGISH_MASK                     0x780UL                                         /**< Bit mask for CMU_REGISH */
+#define _CMU_HFXOTRIMSTATUS_REGISH_DEFAULT                  0x0000000AUL                                    /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */
+#define CMU_HFXOTRIMSTATUS_REGISH_DEFAULT                   (_CMU_HFXOTRIMSTATUS_REGISH_DEFAULT << 7)       /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */
+
+/* Bit fields for CMU IF */
+#define _CMU_IF_RESETVALUE                                  0x00000001UL                            /**< Default value for CMU_IF */
+#define _CMU_IF_MASK                                        0x80007F7FUL                            /**< Mask for CMU_IF */
+#define CMU_IF_HFRCORDY                                     (0x1UL << 0)                            /**< HFRCO Ready Interrupt Flag */
+#define _CMU_IF_HFRCORDY_SHIFT                              0                                       /**< Shift value for CMU_HFRCORDY */
+#define _CMU_IF_HFRCORDY_MASK                               0x1UL                                   /**< Bit mask for CMU_HFRCORDY */
+#define _CMU_IF_HFRCORDY_DEFAULT                            0x00000001UL                            /**< Mode DEFAULT for CMU_IF */
+#define CMU_IF_HFRCORDY_DEFAULT                             (_CMU_IF_HFRCORDY_DEFAULT << 0)         /**< Shifted mode DEFAULT for CMU_IF */
+#define CMU_IF_HFXORDY                                      (0x1UL << 1)                            /**< HFXO Ready Interrupt Flag */
+#define _CMU_IF_HFXORDY_SHIFT                               1                                       /**< Shift value for CMU_HFXORDY */
+#define _CMU_IF_HFXORDY_MASK                                0x2UL                                   /**< Bit mask for CMU_HFXORDY */
+#define _CMU_IF_HFXORDY_DEFAULT                             0x00000000UL                            /**< Mode DEFAULT for CMU_IF */
+#define CMU_IF_HFXORDY_DEFAULT                              (_CMU_IF_HFXORDY_DEFAULT << 1)          /**< Shifted mode DEFAULT for CMU_IF */
+#define CMU_IF_LFRCORDY                                     (0x1UL << 2)                            /**< LFRCO Ready Interrupt Flag */
+#define _CMU_IF_LFRCORDY_SHIFT                              2                                       /**< Shift value for CMU_LFRCORDY */
+#define _CMU_IF_LFRCORDY_MASK                               0x4UL                                   /**< Bit mask for CMU_LFRCORDY */
+#define _CMU_IF_LFRCORDY_DEFAULT                            0x00000000UL                            /**< Mode DEFAULT for CMU_IF */
+#define CMU_IF_LFRCORDY_DEFAULT                             (_CMU_IF_LFRCORDY_DEFAULT << 2)         /**< Shifted mode DEFAULT for CMU_IF */
+#define CMU_IF_LFXORDY                                      (0x1UL << 3)                            /**< LFXO Ready Interrupt Flag */
+#define _CMU_IF_LFXORDY_SHIFT                               3                                       /**< Shift value for CMU_LFXORDY */
+#define _CMU_IF_LFXORDY_MASK                                0x8UL                                   /**< Bit mask for CMU_LFXORDY */
+#define _CMU_IF_LFXORDY_DEFAULT                             0x00000000UL                            /**< Mode DEFAULT for CMU_IF */
+#define CMU_IF_LFXORDY_DEFAULT                              (_CMU_IF_LFXORDY_DEFAULT << 3)          /**< Shifted mode DEFAULT for CMU_IF */
+#define CMU_IF_AUXHFRCORDY                                  (0x1UL << 4)                            /**< AUXHFRCO Ready Interrupt Flag */
+#define _CMU_IF_AUXHFRCORDY_SHIFT                           4                                       /**< Shift value for CMU_AUXHFRCORDY */
+#define _CMU_IF_AUXHFRCORDY_MASK                            0x10UL                                  /**< Bit mask for CMU_AUXHFRCORDY */
+#define _CMU_IF_AUXHFRCORDY_DEFAULT                         0x00000000UL                            /**< Mode DEFAULT for CMU_IF */
+#define CMU_IF_AUXHFRCORDY_DEFAULT                          (_CMU_IF_AUXHFRCORDY_DEFAULT << 4)      /**< Shifted mode DEFAULT for CMU_IF */
+#define CMU_IF_CALRDY                                       (0x1UL << 5)                            /**< Calibration Ready Interrupt Flag */
+#define _CMU_IF_CALRDY_SHIFT                                5                                       /**< Shift value for CMU_CALRDY */
+#define _CMU_IF_CALRDY_MASK                                 0x20UL                                  /**< Bit mask for CMU_CALRDY */
+#define _CMU_IF_CALRDY_DEFAULT                              0x00000000UL                            /**< Mode DEFAULT for CMU_IF */
+#define CMU_IF_CALRDY_DEFAULT                               (_CMU_IF_CALRDY_DEFAULT << 5)           /**< Shifted mode DEFAULT for CMU_IF */
+#define CMU_IF_CALOF                                        (0x1UL << 6)                            /**< Calibration Overflow Interrupt Flag */
+#define _CMU_IF_CALOF_SHIFT                                 6                                       /**< Shift value for CMU_CALOF */
+#define _CMU_IF_CALOF_MASK                                  0x40UL                                  /**< Bit mask for CMU_CALOF */
+#define _CMU_IF_CALOF_DEFAULT                               0x00000000UL                            /**< Mode DEFAULT for CMU_IF */
+#define CMU_IF_CALOF_DEFAULT                                (_CMU_IF_CALOF_DEFAULT << 6)            /**< Shifted mode DEFAULT for CMU_IF */
+#define CMU_IF_HFXODISERR                                   (0x1UL << 8)                            /**< HFXO Disable Error Interrupt Flag */
+#define _CMU_IF_HFXODISERR_SHIFT                            8                                       /**< Shift value for CMU_HFXODISERR */
+#define _CMU_IF_HFXODISERR_MASK                             0x100UL                                 /**< Bit mask for CMU_HFXODISERR */
+#define _CMU_IF_HFXODISERR_DEFAULT                          0x00000000UL                            /**< Mode DEFAULT for CMU_IF */
+#define CMU_IF_HFXODISERR_DEFAULT                           (_CMU_IF_HFXODISERR_DEFAULT << 8)       /**< Shifted mode DEFAULT for CMU_IF */
+#define CMU_IF_HFXOAUTOSW                                   (0x1UL << 9)                            /**< HFXO Automatic Switch Interrupt Flag */
+#define _CMU_IF_HFXOAUTOSW_SHIFT                            9                                       /**< Shift value for CMU_HFXOAUTOSW */
+#define _CMU_IF_HFXOAUTOSW_MASK                             0x200UL                                 /**< Bit mask for CMU_HFXOAUTOSW */
+#define _CMU_IF_HFXOAUTOSW_DEFAULT                          0x00000000UL                            /**< Mode DEFAULT for CMU_IF */
+#define CMU_IF_HFXOAUTOSW_DEFAULT                           (_CMU_IF_HFXOAUTOSW_DEFAULT << 9)       /**< Shifted mode DEFAULT for CMU_IF */
+#define CMU_IF_HFXOPEAKDETERR                               (0x1UL << 10)                           /**< HFXO Automatic Peak Detection Error Interrupt Flag */
+#define _CMU_IF_HFXOPEAKDETERR_SHIFT                        10                                      /**< Shift value for CMU_HFXOPEAKDETERR */
+#define _CMU_IF_HFXOPEAKDETERR_MASK                         0x400UL                                 /**< Bit mask for CMU_HFXOPEAKDETERR */
+#define _CMU_IF_HFXOPEAKDETERR_DEFAULT                      0x00000000UL                            /**< Mode DEFAULT for CMU_IF */
+#define CMU_IF_HFXOPEAKDETERR_DEFAULT                       (_CMU_IF_HFXOPEAKDETERR_DEFAULT << 10)  /**< Shifted mode DEFAULT for CMU_IF */
+#define CMU_IF_HFXOPEAKDETRDY                               (0x1UL << 11)                           /**< HFXO Automatic Peak Detection Ready Interrupt Flag */
+#define _CMU_IF_HFXOPEAKDETRDY_SHIFT                        11                                      /**< Shift value for CMU_HFXOPEAKDETRDY */
+#define _CMU_IF_HFXOPEAKDETRDY_MASK                         0x800UL                                 /**< Bit mask for CMU_HFXOPEAKDETRDY */
+#define _CMU_IF_HFXOPEAKDETRDY_DEFAULT                      0x00000000UL                            /**< Mode DEFAULT for CMU_IF */
+#define CMU_IF_HFXOPEAKDETRDY_DEFAULT                       (_CMU_IF_HFXOPEAKDETRDY_DEFAULT << 11)  /**< Shifted mode DEFAULT for CMU_IF */
+#define CMU_IF_HFXOSHUNTOPTRDY                              (0x1UL << 12)                           /**< HFXO Automatic Shunt Current Optimization Ready Interrupt Flag */
+#define _CMU_IF_HFXOSHUNTOPTRDY_SHIFT                       12                                      /**< Shift value for CMU_HFXOSHUNTOPTRDY */
+#define _CMU_IF_HFXOSHUNTOPTRDY_MASK                        0x1000UL                                /**< Bit mask for CMU_HFXOSHUNTOPTRDY */
+#define _CMU_IF_HFXOSHUNTOPTRDY_DEFAULT                     0x00000000UL                            /**< Mode DEFAULT for CMU_IF */
+#define CMU_IF_HFXOSHUNTOPTRDY_DEFAULT                      (_CMU_IF_HFXOSHUNTOPTRDY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_IF */
+#define CMU_IF_HFRCODIS                                     (0x1UL << 13)                           /**< HFRCO Disable Interrupt Flag */
+#define _CMU_IF_HFRCODIS_SHIFT                              13                                      /**< Shift value for CMU_HFRCODIS */
+#define _CMU_IF_HFRCODIS_MASK                               0x2000UL                                /**< Bit mask for CMU_HFRCODIS */
+#define _CMU_IF_HFRCODIS_DEFAULT                            0x00000000UL                            /**< Mode DEFAULT for CMU_IF */
+#define CMU_IF_HFRCODIS_DEFAULT                             (_CMU_IF_HFRCODIS_DEFAULT << 13)        /**< Shifted mode DEFAULT for CMU_IF */
+#define CMU_IF_LFTIMEOUTERR                                 (0x1UL << 14)                           /**< Low Frequency Timeout Error Interrupt Flag */
+#define _CMU_IF_LFTIMEOUTERR_SHIFT                          14                                      /**< Shift value for CMU_LFTIMEOUTERR */
+#define _CMU_IF_LFTIMEOUTERR_MASK                           0x4000UL                                /**< Bit mask for CMU_LFTIMEOUTERR */
+#define _CMU_IF_LFTIMEOUTERR_DEFAULT                        0x00000000UL                            /**< Mode DEFAULT for CMU_IF */
+#define CMU_IF_LFTIMEOUTERR_DEFAULT                         (_CMU_IF_LFTIMEOUTERR_DEFAULT << 14)    /**< Shifted mode DEFAULT for CMU_IF */
+#define CMU_IF_CMUERR                                       (0x1UL << 31)                           /**< CMU Error Interrupt Flag */
+#define _CMU_IF_CMUERR_SHIFT                                31                                      /**< Shift value for CMU_CMUERR */
+#define _CMU_IF_CMUERR_MASK                                 0x80000000UL                            /**< Bit mask for CMU_CMUERR */
+#define _CMU_IF_CMUERR_DEFAULT                              0x00000000UL                            /**< Mode DEFAULT for CMU_IF */
+#define CMU_IF_CMUERR_DEFAULT                               (_CMU_IF_CMUERR_DEFAULT << 31)          /**< Shifted mode DEFAULT for CMU_IF */
+
+/* Bit fields for CMU IFS */
+#define _CMU_IFS_RESETVALUE                                 0x00000000UL                             /**< Default value for CMU_IFS */
+#define _CMU_IFS_MASK                                       0x80007F7FUL                             /**< Mask for CMU_IFS */
+#define CMU_IFS_HFRCORDY                                    (0x1UL << 0)                             /**< Set HFRCORDY Interrupt Flag */
+#define _CMU_IFS_HFRCORDY_SHIFT                             0                                        /**< Shift value for CMU_HFRCORDY */
+#define _CMU_IFS_HFRCORDY_MASK                              0x1UL                                    /**< Bit mask for CMU_HFRCORDY */
+#define _CMU_IFS_HFRCORDY_DEFAULT                           0x00000000UL                             /**< Mode DEFAULT for CMU_IFS */
+#define CMU_IFS_HFRCORDY_DEFAULT                            (_CMU_IFS_HFRCORDY_DEFAULT << 0)         /**< Shifted mode DEFAULT for CMU_IFS */
+#define CMU_IFS_HFXORDY                                     (0x1UL << 1)                             /**< Set HFXORDY Interrupt Flag */
+#define _CMU_IFS_HFXORDY_SHIFT                              1                                        /**< Shift value for CMU_HFXORDY */
+#define _CMU_IFS_HFXORDY_MASK                               0x2UL                                    /**< Bit mask for CMU_HFXORDY */
+#define _CMU_IFS_HFXORDY_DEFAULT                            0x00000000UL                             /**< Mode DEFAULT for CMU_IFS */
+#define CMU_IFS_HFXORDY_DEFAULT                             (_CMU_IFS_HFXORDY_DEFAULT << 1)          /**< Shifted mode DEFAULT for CMU_IFS */
+#define CMU_IFS_LFRCORDY                                    (0x1UL << 2)                             /**< Set LFRCORDY Interrupt Flag */
+#define _CMU_IFS_LFRCORDY_SHIFT                             2                                        /**< Shift value for CMU_LFRCORDY */
+#define _CMU_IFS_LFRCORDY_MASK                              0x4UL                                    /**< Bit mask for CMU_LFRCORDY */
+#define _CMU_IFS_LFRCORDY_DEFAULT                           0x00000000UL                             /**< Mode DEFAULT for CMU_IFS */
+#define CMU_IFS_LFRCORDY_DEFAULT                            (_CMU_IFS_LFRCORDY_DEFAULT << 2)         /**< Shifted mode DEFAULT for CMU_IFS */
+#define CMU_IFS_LFXORDY                                     (0x1UL << 3)                             /**< Set LFXORDY Interrupt Flag */
+#define _CMU_IFS_LFXORDY_SHIFT                              3                                        /**< Shift value for CMU_LFXORDY */
+#define _CMU_IFS_LFXORDY_MASK                               0x8UL                                    /**< Bit mask for CMU_LFXORDY */
+#define _CMU_IFS_LFXORDY_DEFAULT                            0x00000000UL                             /**< Mode DEFAULT for CMU_IFS */
+#define CMU_IFS_LFXORDY_DEFAULT                             (_CMU_IFS_LFXORDY_DEFAULT << 3)          /**< Shifted mode DEFAULT for CMU_IFS */
+#define CMU_IFS_AUXHFRCORDY                                 (0x1UL << 4)                             /**< Set AUXHFRCORDY Interrupt Flag */
+#define _CMU_IFS_AUXHFRCORDY_SHIFT                          4                                        /**< Shift value for CMU_AUXHFRCORDY */
+#define _CMU_IFS_AUXHFRCORDY_MASK                           0x10UL                                   /**< Bit mask for CMU_AUXHFRCORDY */
+#define _CMU_IFS_AUXHFRCORDY_DEFAULT                        0x00000000UL                             /**< Mode DEFAULT for CMU_IFS */
+#define CMU_IFS_AUXHFRCORDY_DEFAULT                         (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4)      /**< Shifted mode DEFAULT for CMU_IFS */
+#define CMU_IFS_CALRDY                                      (0x1UL << 5)                             /**< Set CALRDY Interrupt Flag */
+#define _CMU_IFS_CALRDY_SHIFT                               5                                        /**< Shift value for CMU_CALRDY */
+#define _CMU_IFS_CALRDY_MASK                                0x20UL                                   /**< Bit mask for CMU_CALRDY */
+#define _CMU_IFS_CALRDY_DEFAULT                             0x00000000UL                             /**< Mode DEFAULT for CMU_IFS */
+#define CMU_IFS_CALRDY_DEFAULT                              (_CMU_IFS_CALRDY_DEFAULT << 5)           /**< Shifted mode DEFAULT for CMU_IFS */
+#define CMU_IFS_CALOF                                       (0x1UL << 6)                             /**< Set CALOF Interrupt Flag */
+#define _CMU_IFS_CALOF_SHIFT                                6                                        /**< Shift value for CMU_CALOF */
+#define _CMU_IFS_CALOF_MASK                                 0x40UL                                   /**< Bit mask for CMU_CALOF */
+#define _CMU_IFS_CALOF_DEFAULT                              0x00000000UL                             /**< Mode DEFAULT for CMU_IFS */
+#define CMU_IFS_CALOF_DEFAULT                               (_CMU_IFS_CALOF_DEFAULT << 6)            /**< Shifted mode DEFAULT for CMU_IFS */
+#define CMU_IFS_HFXODISERR                                  (0x1UL << 8)                             /**< Set HFXODISERR Interrupt Flag */
+#define _CMU_IFS_HFXODISERR_SHIFT                           8                                        /**< Shift value for CMU_HFXODISERR */
+#define _CMU_IFS_HFXODISERR_MASK                            0x100UL                                  /**< Bit mask for CMU_HFXODISERR */
+#define _CMU_IFS_HFXODISERR_DEFAULT                         0x00000000UL                             /**< Mode DEFAULT for CMU_IFS */
+#define CMU_IFS_HFXODISERR_DEFAULT                          (_CMU_IFS_HFXODISERR_DEFAULT << 8)       /**< Shifted mode DEFAULT for CMU_IFS */
+#define CMU_IFS_HFXOAUTOSW                                  (0x1UL << 9)                             /**< Set HFXOAUTOSW Interrupt Flag */
+#define _CMU_IFS_HFXOAUTOSW_SHIFT                           9                                        /**< Shift value for CMU_HFXOAUTOSW */
+#define _CMU_IFS_HFXOAUTOSW_MASK                            0x200UL                                  /**< Bit mask for CMU_HFXOAUTOSW */
+#define _CMU_IFS_HFXOAUTOSW_DEFAULT                         0x00000000UL                             /**< Mode DEFAULT for CMU_IFS */
+#define CMU_IFS_HFXOAUTOSW_DEFAULT                          (_CMU_IFS_HFXOAUTOSW_DEFAULT << 9)       /**< Shifted mode DEFAULT for CMU_IFS */
+#define CMU_IFS_HFXOPEAKDETERR                              (0x1UL << 10)                            /**< Set HFXOPEAKDETERR Interrupt Flag */
+#define _CMU_IFS_HFXOPEAKDETERR_SHIFT                       10                                       /**< Shift value for CMU_HFXOPEAKDETERR */
+#define _CMU_IFS_HFXOPEAKDETERR_MASK                        0x400UL                                  /**< Bit mask for CMU_HFXOPEAKDETERR */
+#define _CMU_IFS_HFXOPEAKDETERR_DEFAULT                     0x00000000UL                             /**< Mode DEFAULT for CMU_IFS */
+#define CMU_IFS_HFXOPEAKDETERR_DEFAULT                      (_CMU_IFS_HFXOPEAKDETERR_DEFAULT << 10)  /**< Shifted mode DEFAULT for CMU_IFS */
+#define CMU_IFS_HFXOPEAKDETRDY                              (0x1UL << 11)                            /**< Set HFXOPEAKDETRDY Interrupt Flag */
+#define _CMU_IFS_HFXOPEAKDETRDY_SHIFT                       11                                       /**< Shift value for CMU_HFXOPEAKDETRDY */
+#define _CMU_IFS_HFXOPEAKDETRDY_MASK                        0x800UL                                  /**< Bit mask for CMU_HFXOPEAKDETRDY */
+#define _CMU_IFS_HFXOPEAKDETRDY_DEFAULT                     0x00000000UL                             /**< Mode DEFAULT for CMU_IFS */
+#define CMU_IFS_HFXOPEAKDETRDY_DEFAULT                      (_CMU_IFS_HFXOPEAKDETRDY_DEFAULT << 11)  /**< Shifted mode DEFAULT for CMU_IFS */
+#define CMU_IFS_HFXOSHUNTOPTRDY                             (0x1UL << 12)                            /**< Set HFXOSHUNTOPTRDY Interrupt Flag */
+#define _CMU_IFS_HFXOSHUNTOPTRDY_SHIFT                      12                                       /**< Shift value for CMU_HFXOSHUNTOPTRDY */
+#define _CMU_IFS_HFXOSHUNTOPTRDY_MASK                       0x1000UL                                 /**< Bit mask for CMU_HFXOSHUNTOPTRDY */
+#define _CMU_IFS_HFXOSHUNTOPTRDY_DEFAULT                    0x00000000UL                             /**< Mode DEFAULT for CMU_IFS */
+#define CMU_IFS_HFXOSHUNTOPTRDY_DEFAULT                     (_CMU_IFS_HFXOSHUNTOPTRDY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_IFS */
+#define CMU_IFS_HFRCODIS                                    (0x1UL << 13)                            /**< Set HFRCODIS Interrupt Flag */
+#define _CMU_IFS_HFRCODIS_SHIFT                             13                                       /**< Shift value for CMU_HFRCODIS */
+#define _CMU_IFS_HFRCODIS_MASK                              0x2000UL                                 /**< Bit mask for CMU_HFRCODIS */
+#define _CMU_IFS_HFRCODIS_DEFAULT                           0x00000000UL                             /**< Mode DEFAULT for CMU_IFS */
+#define CMU_IFS_HFRCODIS_DEFAULT                            (_CMU_IFS_HFRCODIS_DEFAULT << 13)        /**< Shifted mode DEFAULT for CMU_IFS */
+#define CMU_IFS_LFTIMEOUTERR                                (0x1UL << 14)                            /**< Set LFTIMEOUTERR Interrupt Flag */
+#define _CMU_IFS_LFTIMEOUTERR_SHIFT                         14                                       /**< Shift value for CMU_LFTIMEOUTERR */
+#define _CMU_IFS_LFTIMEOUTERR_MASK                          0x4000UL                                 /**< Bit mask for CMU_LFTIMEOUTERR */
+#define _CMU_IFS_LFTIMEOUTERR_DEFAULT                       0x00000000UL                             /**< Mode DEFAULT for CMU_IFS */
+#define CMU_IFS_LFTIMEOUTERR_DEFAULT                        (_CMU_IFS_LFTIMEOUTERR_DEFAULT << 14)    /**< Shifted mode DEFAULT for CMU_IFS */
+#define CMU_IFS_CMUERR                                      (0x1UL << 31)                            /**< Set CMUERR Interrupt Flag */
+#define _CMU_IFS_CMUERR_SHIFT                               31                                       /**< Shift value for CMU_CMUERR */
+#define _CMU_IFS_CMUERR_MASK                                0x80000000UL                             /**< Bit mask for CMU_CMUERR */
+#define _CMU_IFS_CMUERR_DEFAULT                             0x00000000UL                             /**< Mode DEFAULT for CMU_IFS */
+#define CMU_IFS_CMUERR_DEFAULT                              (_CMU_IFS_CMUERR_DEFAULT << 31)          /**< Shifted mode DEFAULT for CMU_IFS */
+
+/* Bit fields for CMU IFC */
+#define _CMU_IFC_RESETVALUE                                 0x00000000UL                             /**< Default value for CMU_IFC */
+#define _CMU_IFC_MASK                                       0x80007F7FUL                             /**< Mask for CMU_IFC */
+#define CMU_IFC_HFRCORDY                                    (0x1UL << 0)                             /**< Clear HFRCORDY Interrupt Flag */
+#define _CMU_IFC_HFRCORDY_SHIFT                             0                                        /**< Shift value for CMU_HFRCORDY */
+#define _CMU_IFC_HFRCORDY_MASK                              0x1UL                                    /**< Bit mask for CMU_HFRCORDY */
+#define _CMU_IFC_HFRCORDY_DEFAULT                           0x00000000UL                             /**< Mode DEFAULT for CMU_IFC */
+#define CMU_IFC_HFRCORDY_DEFAULT                            (_CMU_IFC_HFRCORDY_DEFAULT << 0)         /**< Shifted mode DEFAULT for CMU_IFC */
+#define CMU_IFC_HFXORDY                                     (0x1UL << 1)                             /**< Clear HFXORDY Interrupt Flag */
+#define _CMU_IFC_HFXORDY_SHIFT                              1                                        /**< Shift value for CMU_HFXORDY */
+#define _CMU_IFC_HFXORDY_MASK                               0x2UL                                    /**< Bit mask for CMU_HFXORDY */
+#define _CMU_IFC_HFXORDY_DEFAULT                            0x00000000UL                             /**< Mode DEFAULT for CMU_IFC */
+#define CMU_IFC_HFXORDY_DEFAULT                             (_CMU_IFC_HFXORDY_DEFAULT << 1)          /**< Shifted mode DEFAULT for CMU_IFC */
+#define CMU_IFC_LFRCORDY                                    (0x1UL << 2)                             /**< Clear LFRCORDY Interrupt Flag */
+#define _CMU_IFC_LFRCORDY_SHIFT                             2                                        /**< Shift value for CMU_LFRCORDY */
+#define _CMU_IFC_LFRCORDY_MASK                              0x4UL                                    /**< Bit mask for CMU_LFRCORDY */
+#define _CMU_IFC_LFRCORDY_DEFAULT                           0x00000000UL                             /**< Mode DEFAULT for CMU_IFC */
+#define CMU_IFC_LFRCORDY_DEFAULT                            (_CMU_IFC_LFRCORDY_DEFAULT << 2)         /**< Shifted mode DEFAULT for CMU_IFC */
+#define CMU_IFC_LFXORDY                                     (0x1UL << 3)                             /**< Clear LFXORDY Interrupt Flag */
+#define _CMU_IFC_LFXORDY_SHIFT                              3                                        /**< Shift value for CMU_LFXORDY */
+#define _CMU_IFC_LFXORDY_MASK                               0x8UL                                    /**< Bit mask for CMU_LFXORDY */
+#define _CMU_IFC_LFXORDY_DEFAULT                            0x00000000UL                             /**< Mode DEFAULT for CMU_IFC */
+#define CMU_IFC_LFXORDY_DEFAULT                             (_CMU_IFC_LFXORDY_DEFAULT << 3)          /**< Shifted mode DEFAULT for CMU_IFC */
+#define CMU_IFC_AUXHFRCORDY                                 (0x1UL << 4)                             /**< Clear AUXHFRCORDY Interrupt Flag */
+#define _CMU_IFC_AUXHFRCORDY_SHIFT                          4                                        /**< Shift value for CMU_AUXHFRCORDY */
+#define _CMU_IFC_AUXHFRCORDY_MASK                           0x10UL                                   /**< Bit mask for CMU_AUXHFRCORDY */
+#define _CMU_IFC_AUXHFRCORDY_DEFAULT                        0x00000000UL                             /**< Mode DEFAULT for CMU_IFC */
+#define CMU_IFC_AUXHFRCORDY_DEFAULT                         (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4)      /**< Shifted mode DEFAULT for CMU_IFC */
+#define CMU_IFC_CALRDY                                      (0x1UL << 5)                             /**< Clear CALRDY Interrupt Flag */
+#define _CMU_IFC_CALRDY_SHIFT                               5                                        /**< Shift value for CMU_CALRDY */
+#define _CMU_IFC_CALRDY_MASK                                0x20UL                                   /**< Bit mask for CMU_CALRDY */
+#define _CMU_IFC_CALRDY_DEFAULT                             0x00000000UL                             /**< Mode DEFAULT for CMU_IFC */
+#define CMU_IFC_CALRDY_DEFAULT                              (_CMU_IFC_CALRDY_DEFAULT << 5)           /**< Shifted mode DEFAULT for CMU_IFC */
+#define CMU_IFC_CALOF                                       (0x1UL << 6)                             /**< Clear CALOF Interrupt Flag */
+#define _CMU_IFC_CALOF_SHIFT                                6                                        /**< Shift value for CMU_CALOF */
+#define _CMU_IFC_CALOF_MASK                                 0x40UL                                   /**< Bit mask for CMU_CALOF */
+#define _CMU_IFC_CALOF_DEFAULT                              0x00000000UL                             /**< Mode DEFAULT for CMU_IFC */
+#define CMU_IFC_CALOF_DEFAULT                               (_CMU_IFC_CALOF_DEFAULT << 6)            /**< Shifted mode DEFAULT for CMU_IFC */
+#define CMU_IFC_HFXODISERR                                  (0x1UL << 8)                             /**< Clear HFXODISERR Interrupt Flag */
+#define _CMU_IFC_HFXODISERR_SHIFT                           8                                        /**< Shift value for CMU_HFXODISERR */
+#define _CMU_IFC_HFXODISERR_MASK                            0x100UL                                  /**< Bit mask for CMU_HFXODISERR */
+#define _CMU_IFC_HFXODISERR_DEFAULT                         0x00000000UL                             /**< Mode DEFAULT for CMU_IFC */
+#define CMU_IFC_HFXODISERR_DEFAULT                          (_CMU_IFC_HFXODISERR_DEFAULT << 8)       /**< Shifted mode DEFAULT for CMU_IFC */
+#define CMU_IFC_HFXOAUTOSW                                  (0x1UL << 9)                             /**< Clear HFXOAUTOSW Interrupt Flag */
+#define _CMU_IFC_HFXOAUTOSW_SHIFT                           9                                        /**< Shift value for CMU_HFXOAUTOSW */
+#define _CMU_IFC_HFXOAUTOSW_MASK                            0x200UL                                  /**< Bit mask for CMU_HFXOAUTOSW */
+#define _CMU_IFC_HFXOAUTOSW_DEFAULT                         0x00000000UL                             /**< Mode DEFAULT for CMU_IFC */
+#define CMU_IFC_HFXOAUTOSW_DEFAULT                          (_CMU_IFC_HFXOAUTOSW_DEFAULT << 9)       /**< Shifted mode DEFAULT for CMU_IFC */
+#define CMU_IFC_HFXOPEAKDETERR                              (0x1UL << 10)                            /**< Clear HFXOPEAKDETERR Interrupt Flag */
+#define _CMU_IFC_HFXOPEAKDETERR_SHIFT                       10                                       /**< Shift value for CMU_HFXOPEAKDETERR */
+#define _CMU_IFC_HFXOPEAKDETERR_MASK                        0x400UL                                  /**< Bit mask for CMU_HFXOPEAKDETERR */
+#define _CMU_IFC_HFXOPEAKDETERR_DEFAULT                     0x00000000UL                             /**< Mode DEFAULT for CMU_IFC */
+#define CMU_IFC_HFXOPEAKDETERR_DEFAULT                      (_CMU_IFC_HFXOPEAKDETERR_DEFAULT << 10)  /**< Shifted mode DEFAULT for CMU_IFC */
+#define CMU_IFC_HFXOPEAKDETRDY                              (0x1UL << 11)                            /**< Clear HFXOPEAKDETRDY Interrupt Flag */
+#define _CMU_IFC_HFXOPEAKDETRDY_SHIFT                       11                                       /**< Shift value for CMU_HFXOPEAKDETRDY */
+#define _CMU_IFC_HFXOPEAKDETRDY_MASK                        0x800UL                                  /**< Bit mask for CMU_HFXOPEAKDETRDY */
+#define _CMU_IFC_HFXOPEAKDETRDY_DEFAULT                     0x00000000UL                             /**< Mode DEFAULT for CMU_IFC */
+#define CMU_IFC_HFXOPEAKDETRDY_DEFAULT                      (_CMU_IFC_HFXOPEAKDETRDY_DEFAULT << 11)  /**< Shifted mode DEFAULT for CMU_IFC */
+#define CMU_IFC_HFXOSHUNTOPTRDY                             (0x1UL << 12)                            /**< Clear HFXOSHUNTOPTRDY Interrupt Flag */
+#define _CMU_IFC_HFXOSHUNTOPTRDY_SHIFT                      12                                       /**< Shift value for CMU_HFXOSHUNTOPTRDY */
+#define _CMU_IFC_HFXOSHUNTOPTRDY_MASK                       0x1000UL                                 /**< Bit mask for CMU_HFXOSHUNTOPTRDY */
+#define _CMU_IFC_HFXOSHUNTOPTRDY_DEFAULT                    0x00000000UL                             /**< Mode DEFAULT for CMU_IFC */
+#define CMU_IFC_HFXOSHUNTOPTRDY_DEFAULT                     (_CMU_IFC_HFXOSHUNTOPTRDY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_IFC */
+#define CMU_IFC_HFRCODIS                                    (0x1UL << 13)                            /**< Clear HFRCODIS Interrupt Flag */
+#define _CMU_IFC_HFRCODIS_SHIFT                             13                                       /**< Shift value for CMU_HFRCODIS */
+#define _CMU_IFC_HFRCODIS_MASK                              0x2000UL                                 /**< Bit mask for CMU_HFRCODIS */
+#define _CMU_IFC_HFRCODIS_DEFAULT                           0x00000000UL                             /**< Mode DEFAULT for CMU_IFC */
+#define CMU_IFC_HFRCODIS_DEFAULT                            (_CMU_IFC_HFRCODIS_DEFAULT << 13)        /**< Shifted mode DEFAULT for CMU_IFC */
+#define CMU_IFC_LFTIMEOUTERR                                (0x1UL << 14)                            /**< Clear LFTIMEOUTERR Interrupt Flag */
+#define _CMU_IFC_LFTIMEOUTERR_SHIFT                         14                                       /**< Shift value for CMU_LFTIMEOUTERR */
+#define _CMU_IFC_LFTIMEOUTERR_MASK                          0x4000UL                                 /**< Bit mask for CMU_LFTIMEOUTERR */
+#define _CMU_IFC_LFTIMEOUTERR_DEFAULT                       0x00000000UL                             /**< Mode DEFAULT for CMU_IFC */
+#define CMU_IFC_LFTIMEOUTERR_DEFAULT                        (_CMU_IFC_LFTIMEOUTERR_DEFAULT << 14)    /**< Shifted mode DEFAULT for CMU_IFC */
+#define CMU_IFC_CMUERR                                      (0x1UL << 31)                            /**< Clear CMUERR Interrupt Flag */
+#define _CMU_IFC_CMUERR_SHIFT                               31                                       /**< Shift value for CMU_CMUERR */
+#define _CMU_IFC_CMUERR_MASK                                0x80000000UL                             /**< Bit mask for CMU_CMUERR */
+#define _CMU_IFC_CMUERR_DEFAULT                             0x00000000UL                             /**< Mode DEFAULT for CMU_IFC */
+#define CMU_IFC_CMUERR_DEFAULT                              (_CMU_IFC_CMUERR_DEFAULT << 31)          /**< Shifted mode DEFAULT for CMU_IFC */
+
+/* Bit fields for CMU IEN */
+#define _CMU_IEN_RESETVALUE                                 0x00000000UL                             /**< Default value for CMU_IEN */
+#define _CMU_IEN_MASK                                       0x80007F7FUL                             /**< Mask for CMU_IEN */
+#define CMU_IEN_HFRCORDY                                    (0x1UL << 0)                             /**< HFRCORDY Interrupt Enable */
+#define _CMU_IEN_HFRCORDY_SHIFT                             0                                        /**< Shift value for CMU_HFRCORDY */
+#define _CMU_IEN_HFRCORDY_MASK                              0x1UL                                    /**< Bit mask for CMU_HFRCORDY */
+#define _CMU_IEN_HFRCORDY_DEFAULT                           0x00000000UL                             /**< Mode DEFAULT for CMU_IEN */
+#define CMU_IEN_HFRCORDY_DEFAULT                            (_CMU_IEN_HFRCORDY_DEFAULT << 0)         /**< Shifted mode DEFAULT for CMU_IEN */
+#define CMU_IEN_HFXORDY                                     (0x1UL << 1)                             /**< HFXORDY Interrupt Enable */
+#define _CMU_IEN_HFXORDY_SHIFT                              1                                        /**< Shift value for CMU_HFXORDY */
+#define _CMU_IEN_HFXORDY_MASK                               0x2UL                                    /**< Bit mask for CMU_HFXORDY */
+#define _CMU_IEN_HFXORDY_DEFAULT                            0x00000000UL                             /**< Mode DEFAULT for CMU_IEN */
+#define CMU_IEN_HFXORDY_DEFAULT                             (_CMU_IEN_HFXORDY_DEFAULT << 1)          /**< Shifted mode DEFAULT for CMU_IEN */
+#define CMU_IEN_LFRCORDY                                    (0x1UL << 2)                             /**< LFRCORDY Interrupt Enable */
+#define _CMU_IEN_LFRCORDY_SHIFT                             2                                        /**< Shift value for CMU_LFRCORDY */
+#define _CMU_IEN_LFRCORDY_MASK                              0x4UL                                    /**< Bit mask for CMU_LFRCORDY */
+#define _CMU_IEN_LFRCORDY_DEFAULT                           0x00000000UL                             /**< Mode DEFAULT for CMU_IEN */
+#define CMU_IEN_LFRCORDY_DEFAULT                            (_CMU_IEN_LFRCORDY_DEFAULT << 2)         /**< Shifted mode DEFAULT for CMU_IEN */
+#define CMU_IEN_LFXORDY                                     (0x1UL << 3)                             /**< LFXORDY Interrupt Enable */
+#define _CMU_IEN_LFXORDY_SHIFT                              3                                        /**< Shift value for CMU_LFXORDY */
+#define _CMU_IEN_LFXORDY_MASK                               0x8UL                                    /**< Bit mask for CMU_LFXORDY */
+#define _CMU_IEN_LFXORDY_DEFAULT                            0x00000000UL                             /**< Mode DEFAULT for CMU_IEN */
+#define CMU_IEN_LFXORDY_DEFAULT                             (_CMU_IEN_LFXORDY_DEFAULT << 3)          /**< Shifted mode DEFAULT for CMU_IEN */
+#define CMU_IEN_AUXHFRCORDY                                 (0x1UL << 4)                             /**< AUXHFRCORDY Interrupt Enable */
+#define _CMU_IEN_AUXHFRCORDY_SHIFT                          4                                        /**< Shift value for CMU_AUXHFRCORDY */
+#define _CMU_IEN_AUXHFRCORDY_MASK                           0x10UL                                   /**< Bit mask for CMU_AUXHFRCORDY */
+#define _CMU_IEN_AUXHFRCORDY_DEFAULT                        0x00000000UL                             /**< Mode DEFAULT for CMU_IEN */
+#define CMU_IEN_AUXHFRCORDY_DEFAULT                         (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4)      /**< Shifted mode DEFAULT for CMU_IEN */
+#define CMU_IEN_CALRDY                                      (0x1UL << 5)                             /**< CALRDY Interrupt Enable */
+#define _CMU_IEN_CALRDY_SHIFT                               5                                        /**< Shift value for CMU_CALRDY */
+#define _CMU_IEN_CALRDY_MASK                                0x20UL                                   /**< Bit mask for CMU_CALRDY */
+#define _CMU_IEN_CALRDY_DEFAULT                             0x00000000UL                             /**< Mode DEFAULT for CMU_IEN */
+#define CMU_IEN_CALRDY_DEFAULT                              (_CMU_IEN_CALRDY_DEFAULT << 5)           /**< Shifted mode DEFAULT for CMU_IEN */
+#define CMU_IEN_CALOF                                       (0x1UL << 6)                             /**< CALOF Interrupt Enable */
+#define _CMU_IEN_CALOF_SHIFT                                6                                        /**< Shift value for CMU_CALOF */
+#define _CMU_IEN_CALOF_MASK                                 0x40UL                                   /**< Bit mask for CMU_CALOF */
+#define _CMU_IEN_CALOF_DEFAULT                              0x00000000UL                             /**< Mode DEFAULT for CMU_IEN */
+#define CMU_IEN_CALOF_DEFAULT                               (_CMU_IEN_CALOF_DEFAULT << 6)            /**< Shifted mode DEFAULT for CMU_IEN */
+#define CMU_IEN_HFXODISERR                                  (0x1UL << 8)                             /**< HFXODISERR Interrupt Enable */
+#define _CMU_IEN_HFXODISERR_SHIFT                           8                                        /**< Shift value for CMU_HFXODISERR */
+#define _CMU_IEN_HFXODISERR_MASK                            0x100UL                                  /**< Bit mask for CMU_HFXODISERR */
+#define _CMU_IEN_HFXODISERR_DEFAULT                         0x00000000UL                             /**< Mode DEFAULT for CMU_IEN */
+#define CMU_IEN_HFXODISERR_DEFAULT                          (_CMU_IEN_HFXODISERR_DEFAULT << 8)       /**< Shifted mode DEFAULT for CMU_IEN */
+#define CMU_IEN_HFXOAUTOSW                                  (0x1UL << 9)                             /**< HFXOAUTOSW Interrupt Enable */
+#define _CMU_IEN_HFXOAUTOSW_SHIFT                           9                                        /**< Shift value for CMU_HFXOAUTOSW */
+#define _CMU_IEN_HFXOAUTOSW_MASK                            0x200UL                                  /**< Bit mask for CMU_HFXOAUTOSW */
+#define _CMU_IEN_HFXOAUTOSW_DEFAULT                         0x00000000UL                             /**< Mode DEFAULT for CMU_IEN */
+#define CMU_IEN_HFXOAUTOSW_DEFAULT                          (_CMU_IEN_HFXOAUTOSW_DEFAULT << 9)       /**< Shifted mode DEFAULT for CMU_IEN */
+#define CMU_IEN_HFXOPEAKDETERR                              (0x1UL << 10)                            /**< HFXOPEAKDETERR Interrupt Enable */
+#define _CMU_IEN_HFXOPEAKDETERR_SHIFT                       10                                       /**< Shift value for CMU_HFXOPEAKDETERR */
+#define _CMU_IEN_HFXOPEAKDETERR_MASK                        0x400UL                                  /**< Bit mask for CMU_HFXOPEAKDETERR */
+#define _CMU_IEN_HFXOPEAKDETERR_DEFAULT                     0x00000000UL                             /**< Mode DEFAULT for CMU_IEN */
+#define CMU_IEN_HFXOPEAKDETERR_DEFAULT                      (_CMU_IEN_HFXOPEAKDETERR_DEFAULT << 10)  /**< Shifted mode DEFAULT for CMU_IEN */
+#define CMU_IEN_HFXOPEAKDETRDY                              (0x1UL << 11)                            /**< HFXOPEAKDETRDY Interrupt Enable */
+#define _CMU_IEN_HFXOPEAKDETRDY_SHIFT                       11                                       /**< Shift value for CMU_HFXOPEAKDETRDY */
+#define _CMU_IEN_HFXOPEAKDETRDY_MASK                        0x800UL                                  /**< Bit mask for CMU_HFXOPEAKDETRDY */
+#define _CMU_IEN_HFXOPEAKDETRDY_DEFAULT                     0x00000000UL                             /**< Mode DEFAULT for CMU_IEN */
+#define CMU_IEN_HFXOPEAKDETRDY_DEFAULT                      (_CMU_IEN_HFXOPEAKDETRDY_DEFAULT << 11)  /**< Shifted mode DEFAULT for CMU_IEN */
+#define CMU_IEN_HFXOSHUNTOPTRDY                             (0x1UL << 12)                            /**< HFXOSHUNTOPTRDY Interrupt Enable */
+#define _CMU_IEN_HFXOSHUNTOPTRDY_SHIFT                      12                                       /**< Shift value for CMU_HFXOSHUNTOPTRDY */
+#define _CMU_IEN_HFXOSHUNTOPTRDY_MASK                       0x1000UL                                 /**< Bit mask for CMU_HFXOSHUNTOPTRDY */
+#define _CMU_IEN_HFXOSHUNTOPTRDY_DEFAULT                    0x00000000UL                             /**< Mode DEFAULT for CMU_IEN */
+#define CMU_IEN_HFXOSHUNTOPTRDY_DEFAULT                     (_CMU_IEN_HFXOSHUNTOPTRDY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_IEN */
+#define CMU_IEN_HFRCODIS                                    (0x1UL << 13)                            /**< HFRCODIS Interrupt Enable */
+#define _CMU_IEN_HFRCODIS_SHIFT                             13                                       /**< Shift value for CMU_HFRCODIS */
+#define _CMU_IEN_HFRCODIS_MASK                              0x2000UL                                 /**< Bit mask for CMU_HFRCODIS */
+#define _CMU_IEN_HFRCODIS_DEFAULT                           0x00000000UL                             /**< Mode DEFAULT for CMU_IEN */
+#define CMU_IEN_HFRCODIS_DEFAULT                            (_CMU_IEN_HFRCODIS_DEFAULT << 13)        /**< Shifted mode DEFAULT for CMU_IEN */
+#define CMU_IEN_LFTIMEOUTERR                                (0x1UL << 14)                            /**< LFTIMEOUTERR Interrupt Enable */
+#define _CMU_IEN_LFTIMEOUTERR_SHIFT                         14                                       /**< Shift value for CMU_LFTIMEOUTERR */
+#define _CMU_IEN_LFTIMEOUTERR_MASK                          0x4000UL                                 /**< Bit mask for CMU_LFTIMEOUTERR */
+#define _CMU_IEN_LFTIMEOUTERR_DEFAULT                       0x00000000UL                             /**< Mode DEFAULT for CMU_IEN */
+#define CMU_IEN_LFTIMEOUTERR_DEFAULT                        (_CMU_IEN_LFTIMEOUTERR_DEFAULT << 14)    /**< Shifted mode DEFAULT for CMU_IEN */
+#define CMU_IEN_CMUERR                                      (0x1UL << 31)                            /**< CMUERR Interrupt Enable */
+#define _CMU_IEN_CMUERR_SHIFT                               31                                       /**< Shift value for CMU_CMUERR */
+#define _CMU_IEN_CMUERR_MASK                                0x80000000UL                             /**< Bit mask for CMU_CMUERR */
+#define _CMU_IEN_CMUERR_DEFAULT                             0x00000000UL                             /**< Mode DEFAULT for CMU_IEN */
+#define CMU_IEN_CMUERR_DEFAULT                              (_CMU_IEN_CMUERR_DEFAULT << 31)          /**< Shifted mode DEFAULT for CMU_IEN */
+
+/* Bit fields for CMU HFBUSCLKEN0 */
+#define _CMU_HFBUSCLKEN0_RESETVALUE                         0x00000000UL                           /**< Default value for CMU_HFBUSCLKEN0 */
+#define _CMU_HFBUSCLKEN0_MASK                               0x0000003FUL                           /**< Mask for CMU_HFBUSCLKEN0 */
+#define CMU_HFBUSCLKEN0_LE                                  (0x1UL << 0)                           /**< Low Energy Peripheral Interface Clock Enable */
+#define _CMU_HFBUSCLKEN0_LE_SHIFT                           0                                      /**< Shift value for CMU_LE */
+#define _CMU_HFBUSCLKEN0_LE_MASK                            0x1UL                                  /**< Bit mask for CMU_LE */
+#define _CMU_HFBUSCLKEN0_LE_DEFAULT                         0x00000000UL                           /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */
+#define CMU_HFBUSCLKEN0_LE_DEFAULT                          (_CMU_HFBUSCLKEN0_LE_DEFAULT << 0)     /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */
+#define CMU_HFBUSCLKEN0_CRYPTO                              (0x1UL << 1)                           /**< Advanced Encryption Standard Accelerator Clock Enable */
+#define _CMU_HFBUSCLKEN0_CRYPTO_SHIFT                       1                                      /**< Shift value for CMU_CRYPTO */
+#define _CMU_HFBUSCLKEN0_CRYPTO_MASK                        0x2UL                                  /**< Bit mask for CMU_CRYPTO */
+#define _CMU_HFBUSCLKEN0_CRYPTO_DEFAULT                     0x00000000UL                           /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */
+#define CMU_HFBUSCLKEN0_CRYPTO_DEFAULT                      (_CMU_HFBUSCLKEN0_CRYPTO_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */
+#define CMU_HFBUSCLKEN0_GPIO                                (0x1UL << 2)                           /**< General purpose Input/Output Clock Enable */
+#define _CMU_HFBUSCLKEN0_GPIO_SHIFT                         2                                      /**< Shift value for CMU_GPIO */
+#define _CMU_HFBUSCLKEN0_GPIO_MASK                          0x4UL                                  /**< Bit mask for CMU_GPIO */
+#define _CMU_HFBUSCLKEN0_GPIO_DEFAULT                       0x00000000UL                           /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */
+#define CMU_HFBUSCLKEN0_GPIO_DEFAULT                        (_CMU_HFBUSCLKEN0_GPIO_DEFAULT << 2)   /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */
+#define CMU_HFBUSCLKEN0_PRS                                 (0x1UL << 3)                           /**< Peripheral Reflex System Clock Enable */
+#define _CMU_HFBUSCLKEN0_PRS_SHIFT                          3                                      /**< Shift value for CMU_PRS */
+#define _CMU_HFBUSCLKEN0_PRS_MASK                           0x8UL                                  /**< Bit mask for CMU_PRS */
+#define _CMU_HFBUSCLKEN0_PRS_DEFAULT                        0x00000000UL                           /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */
+#define CMU_HFBUSCLKEN0_PRS_DEFAULT                         (_CMU_HFBUSCLKEN0_PRS_DEFAULT << 3)    /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */
+#define CMU_HFBUSCLKEN0_LDMA                                (0x1UL << 4)                           /**< Linked Direct Memory Access Controller Clock Enable */
+#define _CMU_HFBUSCLKEN0_LDMA_SHIFT                         4                                      /**< Shift value for CMU_LDMA */
+#define _CMU_HFBUSCLKEN0_LDMA_MASK                          0x10UL                                 /**< Bit mask for CMU_LDMA */
+#define _CMU_HFBUSCLKEN0_LDMA_DEFAULT                       0x00000000UL                           /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */
+#define CMU_HFBUSCLKEN0_LDMA_DEFAULT                        (_CMU_HFBUSCLKEN0_LDMA_DEFAULT << 4)   /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */
+#define CMU_HFBUSCLKEN0_GPCRC                               (0x1UL << 5)                           /**< General Purpose CRC Clock Enable */
+#define _CMU_HFBUSCLKEN0_GPCRC_SHIFT                        5                                      /**< Shift value for CMU_GPCRC */
+#define _CMU_HFBUSCLKEN0_GPCRC_MASK                         0x20UL                                 /**< Bit mask for CMU_GPCRC */
+#define _CMU_HFBUSCLKEN0_GPCRC_DEFAULT                      0x00000000UL                           /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */
+#define CMU_HFBUSCLKEN0_GPCRC_DEFAULT                       (_CMU_HFBUSCLKEN0_GPCRC_DEFAULT << 5)  /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */
+
+/* Bit fields for CMU HFPERCLKEN0 */
+#define _CMU_HFPERCLKEN0_RESETVALUE                         0x00000000UL                              /**< Default value for CMU_HFPERCLKEN0 */
+#define _CMU_HFPERCLKEN0_MASK                               0x000003FFUL                              /**< Mask for CMU_HFPERCLKEN0 */
+#define CMU_HFPERCLKEN0_TIMER0                              (0x1UL << 0)                              /**< Timer 0 Clock Enable */
+#define _CMU_HFPERCLKEN0_TIMER0_SHIFT                       0                                         /**< Shift value for CMU_TIMER0 */
+#define _CMU_HFPERCLKEN0_TIMER0_MASK                        0x1UL                                     /**< Bit mask for CMU_TIMER0 */
+#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT                     0x00000000UL                              /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
+#define CMU_HFPERCLKEN0_TIMER0_DEFAULT                      (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 0)    /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
+#define CMU_HFPERCLKEN0_TIMER1                              (0x1UL << 1)                              /**< Timer 1 Clock Enable */
+#define _CMU_HFPERCLKEN0_TIMER1_SHIFT                       1                                         /**< Shift value for CMU_TIMER1 */
+#define _CMU_HFPERCLKEN0_TIMER1_MASK                        0x2UL                                     /**< Bit mask for CMU_TIMER1 */
+#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT                     0x00000000UL                              /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
+#define CMU_HFPERCLKEN0_TIMER1_DEFAULT                      (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 1)    /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
+#define CMU_HFPERCLKEN0_USART0                              (0x1UL << 2)                              /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */
+#define _CMU_HFPERCLKEN0_USART0_SHIFT                       2                                         /**< Shift value for CMU_USART0 */
+#define _CMU_HFPERCLKEN0_USART0_MASK                        0x4UL                                     /**< Bit mask for CMU_USART0 */
+#define _CMU_HFPERCLKEN0_USART0_DEFAULT                     0x00000000UL                              /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
+#define CMU_HFPERCLKEN0_USART0_DEFAULT                      (_CMU_HFPERCLKEN0_USART0_DEFAULT << 2)    /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
+#define CMU_HFPERCLKEN0_USART1                              (0x1UL << 3)                              /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */
+#define _CMU_HFPERCLKEN0_USART1_SHIFT                       3                                         /**< Shift value for CMU_USART1 */
+#define _CMU_HFPERCLKEN0_USART1_MASK                        0x8UL                                     /**< Bit mask for CMU_USART1 */
+#define _CMU_HFPERCLKEN0_USART1_DEFAULT                     0x00000000UL                              /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
+#define CMU_HFPERCLKEN0_USART1_DEFAULT                      (_CMU_HFPERCLKEN0_USART1_DEFAULT << 3)    /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
+#define CMU_HFPERCLKEN0_ACMP0                               (0x1UL << 4)                              /**< Analog Comparator 0 Clock Enable */
+#define _CMU_HFPERCLKEN0_ACMP0_SHIFT                        4                                         /**< Shift value for CMU_ACMP0 */
+#define _CMU_HFPERCLKEN0_ACMP0_MASK                         0x10UL                                    /**< Bit mask for CMU_ACMP0 */
+#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT                      0x00000000UL                              /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
+#define CMU_HFPERCLKEN0_ACMP0_DEFAULT                       (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 4)     /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
+#define CMU_HFPERCLKEN0_ACMP1                               (0x1UL << 5)                              /**< Analog Comparator 1 Clock Enable */
+#define _CMU_HFPERCLKEN0_ACMP1_SHIFT                        5                                         /**< Shift value for CMU_ACMP1 */
+#define _CMU_HFPERCLKEN0_ACMP1_MASK                         0x20UL                                    /**< Bit mask for CMU_ACMP1 */
+#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT                      0x00000000UL                              /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
+#define CMU_HFPERCLKEN0_ACMP1_DEFAULT                       (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 5)     /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
+#define CMU_HFPERCLKEN0_CRYOTIMER                           (0x1UL << 6)                              /**< CryoTimer Clock Enable */
+#define _CMU_HFPERCLKEN0_CRYOTIMER_SHIFT                    6                                         /**< Shift value for CMU_CRYOTIMER */
+#define _CMU_HFPERCLKEN0_CRYOTIMER_MASK                     0x40UL                                    /**< Bit mask for CMU_CRYOTIMER */
+#define _CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT                  0x00000000UL                              /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
+#define CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT                   (_CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
+#define CMU_HFPERCLKEN0_I2C0                                (0x1UL << 7)                              /**< I2C 0 Clock Enable */
+#define _CMU_HFPERCLKEN0_I2C0_SHIFT                         7                                         /**< Shift value for CMU_I2C0 */
+#define _CMU_HFPERCLKEN0_I2C0_MASK                          0x80UL                                    /**< Bit mask for CMU_I2C0 */
+#define _CMU_HFPERCLKEN0_I2C0_DEFAULT                       0x00000000UL                              /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
+#define CMU_HFPERCLKEN0_I2C0_DEFAULT                        (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 7)      /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
+#define CMU_HFPERCLKEN0_ADC0                                (0x1UL << 8)                              /**< Analog to Digital Converter 0 Clock Enable */
+#define _CMU_HFPERCLKEN0_ADC0_SHIFT                         8                                         /**< Shift value for CMU_ADC0 */
+#define _CMU_HFPERCLKEN0_ADC0_MASK                          0x100UL                                   /**< Bit mask for CMU_ADC0 */
+#define _CMU_HFPERCLKEN0_ADC0_DEFAULT                       0x00000000UL                              /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
+#define CMU_HFPERCLKEN0_ADC0_DEFAULT                        (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 8)      /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
+#define CMU_HFPERCLKEN0_IDAC0                               (0x1UL << 9)                              /**< Current Digital to Analog Converter 0 Clock Enable */
+#define _CMU_HFPERCLKEN0_IDAC0_SHIFT                        9                                         /**< Shift value for CMU_IDAC0 */
+#define _CMU_HFPERCLKEN0_IDAC0_MASK                         0x200UL                                   /**< Bit mask for CMU_IDAC0 */
+#define _CMU_HFPERCLKEN0_IDAC0_DEFAULT                      0x00000000UL                              /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
+#define CMU_HFPERCLKEN0_IDAC0_DEFAULT                       (_CMU_HFPERCLKEN0_IDAC0_DEFAULT << 9)     /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
+
+/* Bit fields for CMU LFACLKEN0 */
+#define _CMU_LFACLKEN0_RESETVALUE                           0x00000000UL                           /**< Default value for CMU_LFACLKEN0 */
+#define _CMU_LFACLKEN0_MASK                                 0x00000001UL                           /**< Mask for CMU_LFACLKEN0 */
+#define CMU_LFACLKEN0_LETIMER0                              (0x1UL << 0)                           /**< Low Energy Timer 0 Clock Enable */
+#define _CMU_LFACLKEN0_LETIMER0_SHIFT                       0                                      /**< Shift value for CMU_LETIMER0 */
+#define _CMU_LFACLKEN0_LETIMER0_MASK                        0x1UL                                  /**< Bit mask for CMU_LETIMER0 */
+#define _CMU_LFACLKEN0_LETIMER0_DEFAULT                     0x00000000UL                           /**< Mode DEFAULT for CMU_LFACLKEN0 */
+#define CMU_LFACLKEN0_LETIMER0_DEFAULT                      (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */
+
+/* Bit fields for CMU LFBCLKEN0 */
+#define _CMU_LFBCLKEN0_RESETVALUE                           0x00000000UL                          /**< Default value for CMU_LFBCLKEN0 */
+#define _CMU_LFBCLKEN0_MASK                                 0x00000001UL                          /**< Mask for CMU_LFBCLKEN0 */
+#define CMU_LFBCLKEN0_LEUART0                               (0x1UL << 0)                          /**< Low Energy UART 0 Clock Enable */
+#define _CMU_LFBCLKEN0_LEUART0_SHIFT                        0                                     /**< Shift value for CMU_LEUART0 */
+#define _CMU_LFBCLKEN0_LEUART0_MASK                         0x1UL                                 /**< Bit mask for CMU_LEUART0 */
+#define _CMU_LFBCLKEN0_LEUART0_DEFAULT                      0x00000000UL                          /**< Mode DEFAULT for CMU_LFBCLKEN0 */
+#define CMU_LFBCLKEN0_LEUART0_DEFAULT                       (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */
+
+/* Bit fields for CMU LFECLKEN0 */
+#define _CMU_LFECLKEN0_RESETVALUE                           0x00000000UL                       /**< Default value for CMU_LFECLKEN0 */
+#define _CMU_LFECLKEN0_MASK                                 0x00000001UL                       /**< Mask for CMU_LFECLKEN0 */
+#define CMU_LFECLKEN0_RTCC                                  (0x1UL << 0)                       /**< Real-Time Counter and Calendar Clock Enable */
+#define _CMU_LFECLKEN0_RTCC_SHIFT                           0                                  /**< Shift value for CMU_RTCC */
+#define _CMU_LFECLKEN0_RTCC_MASK                            0x1UL                              /**< Bit mask for CMU_RTCC */
+#define _CMU_LFECLKEN0_RTCC_DEFAULT                         0x00000000UL                       /**< Mode DEFAULT for CMU_LFECLKEN0 */
+#define CMU_LFECLKEN0_RTCC_DEFAULT                          (_CMU_LFECLKEN0_RTCC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKEN0 */
+
+/* Bit fields for CMU HFPRESC */
+#define _CMU_HFPRESC_RESETVALUE                             0x00000000UL                              /**< Default value for CMU_HFPRESC */
+#define _CMU_HFPRESC_MASK                                   0x01001F00UL                              /**< Mask for CMU_HFPRESC */
+#define _CMU_HFPRESC_PRESC_SHIFT                            8                                         /**< Shift value for CMU_PRESC */
+#define _CMU_HFPRESC_PRESC_MASK                             0x1F00UL                                  /**< Bit mask for CMU_PRESC */
+#define _CMU_HFPRESC_PRESC_DEFAULT                          0x00000000UL                              /**< Mode DEFAULT for CMU_HFPRESC */
+#define _CMU_HFPRESC_PRESC_NODIVISION                       0x00000000UL                              /**< Mode NODIVISION for CMU_HFPRESC */
+#define CMU_HFPRESC_PRESC_DEFAULT                           (_CMU_HFPRESC_PRESC_DEFAULT << 8)         /**< Shifted mode DEFAULT for CMU_HFPRESC */
+#define CMU_HFPRESC_PRESC_NODIVISION                        (_CMU_HFPRESC_PRESC_NODIVISION << 8)      /**< Shifted mode NODIVISION for CMU_HFPRESC */
+#define _CMU_HFPRESC_HFCLKLEPRESC_SHIFT                     24                                        /**< Shift value for CMU_HFCLKLEPRESC */
+#define _CMU_HFPRESC_HFCLKLEPRESC_MASK                      0x1000000UL                               /**< Bit mask for CMU_HFCLKLEPRESC */
+#define _CMU_HFPRESC_HFCLKLEPRESC_DEFAULT                   0x00000000UL                              /**< Mode DEFAULT for CMU_HFPRESC */
+#define _CMU_HFPRESC_HFCLKLEPRESC_DIV2                      0x00000000UL                              /**< Mode DIV2 for CMU_HFPRESC */
+#define _CMU_HFPRESC_HFCLKLEPRESC_DIV4                      0x00000001UL                              /**< Mode DIV4 for CMU_HFPRESC */
+#define CMU_HFPRESC_HFCLKLEPRESC_DEFAULT                    (_CMU_HFPRESC_HFCLKLEPRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPRESC */
+#define CMU_HFPRESC_HFCLKLEPRESC_DIV2                       (_CMU_HFPRESC_HFCLKLEPRESC_DIV2 << 24)    /**< Shifted mode DIV2 for CMU_HFPRESC */
+#define CMU_HFPRESC_HFCLKLEPRESC_DIV4                       (_CMU_HFPRESC_HFCLKLEPRESC_DIV4 << 24)    /**< Shifted mode DIV4 for CMU_HFPRESC */
+
+/* Bit fields for CMU HFCOREPRESC */
+#define _CMU_HFCOREPRESC_RESETVALUE                         0x00000000UL                             /**< Default value for CMU_HFCOREPRESC */
+#define _CMU_HFCOREPRESC_MASK                               0x0001FF00UL                             /**< Mask for CMU_HFCOREPRESC */
+#define _CMU_HFCOREPRESC_PRESC_SHIFT                        8                                        /**< Shift value for CMU_PRESC */
+#define _CMU_HFCOREPRESC_PRESC_MASK                         0x1FF00UL                                /**< Bit mask for CMU_PRESC */
+#define _CMU_HFCOREPRESC_PRESC_DEFAULT                      0x00000000UL                             /**< Mode DEFAULT for CMU_HFCOREPRESC */
+#define _CMU_HFCOREPRESC_PRESC_NODIVISION                   0x00000000UL                             /**< Mode NODIVISION for CMU_HFCOREPRESC */
+#define CMU_HFCOREPRESC_PRESC_DEFAULT                       (_CMU_HFCOREPRESC_PRESC_DEFAULT << 8)    /**< Shifted mode DEFAULT for CMU_HFCOREPRESC */
+#define CMU_HFCOREPRESC_PRESC_NODIVISION                    (_CMU_HFCOREPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFCOREPRESC */
+
+/* Bit fields for CMU HFPERPRESC */
+#define _CMU_HFPERPRESC_RESETVALUE                          0x00000000UL                            /**< Default value for CMU_HFPERPRESC */
+#define _CMU_HFPERPRESC_MASK                                0x0001FF00UL                            /**< Mask for CMU_HFPERPRESC */
+#define _CMU_HFPERPRESC_PRESC_SHIFT                         8                                       /**< Shift value for CMU_PRESC */
+#define _CMU_HFPERPRESC_PRESC_MASK                          0x1FF00UL                               /**< Bit mask for CMU_PRESC */
+#define _CMU_HFPERPRESC_PRESC_DEFAULT                       0x00000000UL                            /**< Mode DEFAULT for CMU_HFPERPRESC */
+#define _CMU_HFPERPRESC_PRESC_NODIVISION                    0x00000000UL                            /**< Mode NODIVISION for CMU_HFPERPRESC */
+#define CMU_HFPERPRESC_PRESC_DEFAULT                        (_CMU_HFPERPRESC_PRESC_DEFAULT << 8)    /**< Shifted mode DEFAULT for CMU_HFPERPRESC */
+#define CMU_HFPERPRESC_PRESC_NODIVISION                     (_CMU_HFPERPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESC */
+
+/* Bit fields for CMU HFEXPPRESC */
+#define _CMU_HFEXPPRESC_RESETVALUE                          0x00000000UL                            /**< Default value for CMU_HFEXPPRESC */
+#define _CMU_HFEXPPRESC_MASK                                0x00001F00UL                            /**< Mask for CMU_HFEXPPRESC */
+#define _CMU_HFEXPPRESC_PRESC_SHIFT                         8                                       /**< Shift value for CMU_PRESC */
+#define _CMU_HFEXPPRESC_PRESC_MASK                          0x1F00UL                                /**< Bit mask for CMU_PRESC */
+#define _CMU_HFEXPPRESC_PRESC_DEFAULT                       0x00000000UL                            /**< Mode DEFAULT for CMU_HFEXPPRESC */
+#define _CMU_HFEXPPRESC_PRESC_NODIVISION                    0x00000000UL                            /**< Mode NODIVISION for CMU_HFEXPPRESC */
+#define CMU_HFEXPPRESC_PRESC_DEFAULT                        (_CMU_HFEXPPRESC_PRESC_DEFAULT << 8)    /**< Shifted mode DEFAULT for CMU_HFEXPPRESC */
+#define CMU_HFEXPPRESC_PRESC_NODIVISION                     (_CMU_HFEXPPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFEXPPRESC */
+
+/* Bit fields for CMU LFAPRESC0 */
+#define _CMU_LFAPRESC0_RESETVALUE                           0x00000000UL                            /**< Default value for CMU_LFAPRESC0 */
+#define _CMU_LFAPRESC0_MASK                                 0x0000000FUL                            /**< Mask for CMU_LFAPRESC0 */
+#define _CMU_LFAPRESC0_LETIMER0_SHIFT                       0                                       /**< Shift value for CMU_LETIMER0 */
+#define _CMU_LFAPRESC0_LETIMER0_MASK                        0xFUL                                   /**< Bit mask for CMU_LETIMER0 */
+#define _CMU_LFAPRESC0_LETIMER0_DIV1                        0x00000000UL                            /**< Mode DIV1 for CMU_LFAPRESC0 */
+#define _CMU_LFAPRESC0_LETIMER0_DIV2                        0x00000001UL                            /**< Mode DIV2 for CMU_LFAPRESC0 */
+#define _CMU_LFAPRESC0_LETIMER0_DIV4                        0x00000002UL                            /**< Mode DIV4 for CMU_LFAPRESC0 */
+#define _CMU_LFAPRESC0_LETIMER0_DIV8                        0x00000003UL                            /**< Mode DIV8 for CMU_LFAPRESC0 */
+#define _CMU_LFAPRESC0_LETIMER0_DIV16                       0x00000004UL                            /**< Mode DIV16 for CMU_LFAPRESC0 */
+#define _CMU_LFAPRESC0_LETIMER0_DIV32                       0x00000005UL                            /**< Mode DIV32 for CMU_LFAPRESC0 */
+#define _CMU_LFAPRESC0_LETIMER0_DIV64                       0x00000006UL                            /**< Mode DIV64 for CMU_LFAPRESC0 */
+#define _CMU_LFAPRESC0_LETIMER0_DIV128                      0x00000007UL                            /**< Mode DIV128 for CMU_LFAPRESC0 */
+#define _CMU_LFAPRESC0_LETIMER0_DIV256                      0x00000008UL                            /**< Mode DIV256 for CMU_LFAPRESC0 */
+#define _CMU_LFAPRESC0_LETIMER0_DIV512                      0x00000009UL                            /**< Mode DIV512 for CMU_LFAPRESC0 */
+#define _CMU_LFAPRESC0_LETIMER0_DIV1024                     0x0000000AUL                            /**< Mode DIV1024 for CMU_LFAPRESC0 */
+#define _CMU_LFAPRESC0_LETIMER0_DIV2048                     0x0000000BUL                            /**< Mode DIV2048 for CMU_LFAPRESC0 */
+#define _CMU_LFAPRESC0_LETIMER0_DIV4096                     0x0000000CUL                            /**< Mode DIV4096 for CMU_LFAPRESC0 */
+#define _CMU_LFAPRESC0_LETIMER0_DIV8192                     0x0000000DUL                            /**< Mode DIV8192 for CMU_LFAPRESC0 */
+#define _CMU_LFAPRESC0_LETIMER0_DIV16384                    0x0000000EUL                            /**< Mode DIV16384 for CMU_LFAPRESC0 */
+#define _CMU_LFAPRESC0_LETIMER0_DIV32768                    0x0000000FUL                            /**< Mode DIV32768 for CMU_LFAPRESC0 */
+#define CMU_LFAPRESC0_LETIMER0_DIV1                         (_CMU_LFAPRESC0_LETIMER0_DIV1 << 0)     /**< Shifted mode DIV1 for CMU_LFAPRESC0 */
+#define CMU_LFAPRESC0_LETIMER0_DIV2                         (_CMU_LFAPRESC0_LETIMER0_DIV2 << 0)     /**< Shifted mode DIV2 for CMU_LFAPRESC0 */
+#define CMU_LFAPRESC0_LETIMER0_DIV4                         (_CMU_LFAPRESC0_LETIMER0_DIV4 << 0)     /**< Shifted mode DIV4 for CMU_LFAPRESC0 */
+#define CMU_LFAPRESC0_LETIMER0_DIV8                         (_CMU_LFAPRESC0_LETIMER0_DIV8 << 0)     /**< Shifted mode DIV8 for CMU_LFAPRESC0 */
+#define CMU_LFAPRESC0_LETIMER0_DIV16                        (_CMU_LFAPRESC0_LETIMER0_DIV16 << 0)    /**< Shifted mode DIV16 for CMU_LFAPRESC0 */
+#define CMU_LFAPRESC0_LETIMER0_DIV32                        (_CMU_LFAPRESC0_LETIMER0_DIV32 << 0)    /**< Shifted mode DIV32 for CMU_LFAPRESC0 */
+#define CMU_LFAPRESC0_LETIMER0_DIV64                        (_CMU_LFAPRESC0_LETIMER0_DIV64 << 0)    /**< Shifted mode DIV64 for CMU_LFAPRESC0 */
+#define CMU_LFAPRESC0_LETIMER0_DIV128                       (_CMU_LFAPRESC0_LETIMER0_DIV128 << 0)   /**< Shifted mode DIV128 for CMU_LFAPRESC0 */
+#define CMU_LFAPRESC0_LETIMER0_DIV256                       (_CMU_LFAPRESC0_LETIMER0_DIV256 << 0)   /**< Shifted mode DIV256 for CMU_LFAPRESC0 */
+#define CMU_LFAPRESC0_LETIMER0_DIV512                       (_CMU_LFAPRESC0_LETIMER0_DIV512 << 0)   /**< Shifted mode DIV512 for CMU_LFAPRESC0 */
+#define CMU_LFAPRESC0_LETIMER0_DIV1024                      (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 0)  /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */
+#define CMU_LFAPRESC0_LETIMER0_DIV2048                      (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 0)  /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */
+#define CMU_LFAPRESC0_LETIMER0_DIV4096                      (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 0)  /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */
+#define CMU_LFAPRESC0_LETIMER0_DIV8192                      (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 0)  /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */
+#define CMU_LFAPRESC0_LETIMER0_DIV16384                     (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 0) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */
+#define CMU_LFAPRESC0_LETIMER0_DIV32768                     (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 0) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */
+
+/* Bit fields for CMU LFBPRESC0 */
+#define _CMU_LFBPRESC0_RESETVALUE                           0x00000000UL                       /**< Default value for CMU_LFBPRESC0 */
+#define _CMU_LFBPRESC0_MASK                                 0x00000003UL                       /**< Mask for CMU_LFBPRESC0 */
+#define _CMU_LFBPRESC0_LEUART0_SHIFT                        0                                  /**< Shift value for CMU_LEUART0 */
+#define _CMU_LFBPRESC0_LEUART0_MASK                         0x3UL                              /**< Bit mask for CMU_LEUART0 */
+#define _CMU_LFBPRESC0_LEUART0_DIV1                         0x00000000UL                       /**< Mode DIV1 for CMU_LFBPRESC0 */
+#define _CMU_LFBPRESC0_LEUART0_DIV2                         0x00000001UL                       /**< Mode DIV2 for CMU_LFBPRESC0 */
+#define _CMU_LFBPRESC0_LEUART0_DIV4                         0x00000002UL                       /**< Mode DIV4 for CMU_LFBPRESC0 */
+#define _CMU_LFBPRESC0_LEUART0_DIV8                         0x00000003UL                       /**< Mode DIV8 for CMU_LFBPRESC0 */
+#define CMU_LFBPRESC0_LEUART0_DIV1                          (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */
+#define CMU_LFBPRESC0_LEUART0_DIV2                          (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */
+#define CMU_LFBPRESC0_LEUART0_DIV4                          (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */
+#define CMU_LFBPRESC0_LEUART0_DIV8                          (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */
+
+/* Bit fields for CMU LFEPRESC0 */
+#define _CMU_LFEPRESC0_RESETVALUE                           0x00000000UL                    /**< Default value for CMU_LFEPRESC0 */
+#define _CMU_LFEPRESC0_MASK                                 0x0000000FUL                    /**< Mask for CMU_LFEPRESC0 */
+#define _CMU_LFEPRESC0_RTCC_SHIFT                           0                               /**< Shift value for CMU_RTCC */
+#define _CMU_LFEPRESC0_RTCC_MASK                            0xFUL                           /**< Bit mask for CMU_RTCC */
+#define _CMU_LFEPRESC0_RTCC_DIV1                            0x00000000UL                    /**< Mode DIV1 for CMU_LFEPRESC0 */
+#define CMU_LFEPRESC0_RTCC_DIV1                             (_CMU_LFEPRESC0_RTCC_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFEPRESC0 */
+
+/* Bit fields for CMU SYNCBUSY */
+#define _CMU_SYNCBUSY_RESETVALUE                            0x00000000UL                               /**< Default value for CMU_SYNCBUSY */
+#define _CMU_SYNCBUSY_MASK                                  0x3F050055UL                               /**< Mask for CMU_SYNCBUSY */
+#define CMU_SYNCBUSY_LFACLKEN0                              (0x1UL << 0)                               /**< Low Frequency A Clock Enable 0 Busy */
+#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT                       0                                          /**< Shift value for CMU_LFACLKEN0 */
+#define _CMU_SYNCBUSY_LFACLKEN0_MASK                        0x1UL                                      /**< Bit mask for CMU_LFACLKEN0 */
+#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT                     0x00000000UL                               /**< Mode DEFAULT for CMU_SYNCBUSY */
+#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT                      (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0)     /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
+#define CMU_SYNCBUSY_LFAPRESC0                              (0x1UL << 2)                               /**< Low Frequency A Prescaler 0 Busy */
+#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT                       2                                          /**< Shift value for CMU_LFAPRESC0 */
+#define _CMU_SYNCBUSY_LFAPRESC0_MASK                        0x4UL                                      /**< Bit mask for CMU_LFAPRESC0 */
+#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT                     0x00000000UL                               /**< Mode DEFAULT for CMU_SYNCBUSY */
+#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT                      (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2)     /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
+#define CMU_SYNCBUSY_LFBCLKEN0                              (0x1UL << 4)                               /**< Low Frequency B Clock Enable 0 Busy */
+#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT                       4                                          /**< Shift value for CMU_LFBCLKEN0 */
+#define _CMU_SYNCBUSY_LFBCLKEN0_MASK                        0x10UL                                     /**< Bit mask for CMU_LFBCLKEN0 */
+#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT                     0x00000000UL                               /**< Mode DEFAULT for CMU_SYNCBUSY */
+#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT                      (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4)     /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
+#define CMU_SYNCBUSY_LFBPRESC0                              (0x1UL << 6)                               /**< Low Frequency B Prescaler 0 Busy */
+#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT                       6                                          /**< Shift value for CMU_LFBPRESC0 */
+#define _CMU_SYNCBUSY_LFBPRESC0_MASK                        0x40UL                                     /**< Bit mask for CMU_LFBPRESC0 */
+#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT                     0x00000000UL                               /**< Mode DEFAULT for CMU_SYNCBUSY */
+#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT                      (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6)     /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
+#define CMU_SYNCBUSY_LFECLKEN0                              (0x1UL << 16)                              /**< Low Frequency E Clock Enable 0 Busy */
+#define _CMU_SYNCBUSY_LFECLKEN0_SHIFT                       16                                         /**< Shift value for CMU_LFECLKEN0 */
+#define _CMU_SYNCBUSY_LFECLKEN0_MASK                        0x10000UL                                  /**< Bit mask for CMU_LFECLKEN0 */
+#define _CMU_SYNCBUSY_LFECLKEN0_DEFAULT                     0x00000000UL                               /**< Mode DEFAULT for CMU_SYNCBUSY */
+#define CMU_SYNCBUSY_LFECLKEN0_DEFAULT                      (_CMU_SYNCBUSY_LFECLKEN0_DEFAULT << 16)    /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
+#define CMU_SYNCBUSY_LFEPRESC0                              (0x1UL << 18)                              /**< Low Frequency E Prescaler 0 Busy */
+#define _CMU_SYNCBUSY_LFEPRESC0_SHIFT                       18                                         /**< Shift value for CMU_LFEPRESC0 */
+#define _CMU_SYNCBUSY_LFEPRESC0_MASK                        0x40000UL                                  /**< Bit mask for CMU_LFEPRESC0 */
+#define _CMU_SYNCBUSY_LFEPRESC0_DEFAULT                     0x00000000UL                               /**< Mode DEFAULT for CMU_SYNCBUSY */
+#define CMU_SYNCBUSY_LFEPRESC0_DEFAULT                      (_CMU_SYNCBUSY_LFEPRESC0_DEFAULT << 18)    /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
+#define CMU_SYNCBUSY_HFRCOBSY                               (0x1UL << 24)                              /**< HFRCO Busy */
+#define _CMU_SYNCBUSY_HFRCOBSY_SHIFT                        24                                         /**< Shift value for CMU_HFRCOBSY */
+#define _CMU_SYNCBUSY_HFRCOBSY_MASK                         0x1000000UL                                /**< Bit mask for CMU_HFRCOBSY */
+#define _CMU_SYNCBUSY_HFRCOBSY_DEFAULT                      0x00000000UL                               /**< Mode DEFAULT for CMU_SYNCBUSY */
+#define CMU_SYNCBUSY_HFRCOBSY_DEFAULT                       (_CMU_SYNCBUSY_HFRCOBSY_DEFAULT << 24)     /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
+#define CMU_SYNCBUSY_AUXHFRCOBSY                            (0x1UL << 25)                              /**< AUXHFRCO Busy */
+#define _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT                     25                                         /**< Shift value for CMU_AUXHFRCOBSY */
+#define _CMU_SYNCBUSY_AUXHFRCOBSY_MASK                      0x2000000UL                                /**< Bit mask for CMU_AUXHFRCOBSY */
+#define _CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT                   0x00000000UL                               /**< Mode DEFAULT for CMU_SYNCBUSY */
+#define CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT                    (_CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT << 25)  /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
+#define CMU_SYNCBUSY_LFRCOBSY                               (0x1UL << 26)                              /**< LFRCO Busy */
+#define _CMU_SYNCBUSY_LFRCOBSY_SHIFT                        26                                         /**< Shift value for CMU_LFRCOBSY */
+#define _CMU_SYNCBUSY_LFRCOBSY_MASK                         0x4000000UL                                /**< Bit mask for CMU_LFRCOBSY */
+#define _CMU_SYNCBUSY_LFRCOBSY_DEFAULT                      0x00000000UL                               /**< Mode DEFAULT for CMU_SYNCBUSY */
+#define CMU_SYNCBUSY_LFRCOBSY_DEFAULT                       (_CMU_SYNCBUSY_LFRCOBSY_DEFAULT << 26)     /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
+#define CMU_SYNCBUSY_LFRCOVREFBSY                           (0x1UL << 27)                              /**< LFRCO VREF Busy */
+#define _CMU_SYNCBUSY_LFRCOVREFBSY_SHIFT                    27                                         /**< Shift value for CMU_LFRCOVREFBSY */
+#define _CMU_SYNCBUSY_LFRCOVREFBSY_MASK                     0x8000000UL                                /**< Bit mask for CMU_LFRCOVREFBSY */
+#define _CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT                  0x00000000UL                               /**< Mode DEFAULT for CMU_SYNCBUSY */
+#define CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT                   (_CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
+#define CMU_SYNCBUSY_HFXOBSY                                (0x1UL << 28)                              /**< HFXO Busy */
+#define _CMU_SYNCBUSY_HFXOBSY_SHIFT                         28                                         /**< Shift value for CMU_HFXOBSY */
+#define _CMU_SYNCBUSY_HFXOBSY_MASK                          0x10000000UL                               /**< Bit mask for CMU_HFXOBSY */
+#define _CMU_SYNCBUSY_HFXOBSY_DEFAULT                       0x00000000UL                               /**< Mode DEFAULT for CMU_SYNCBUSY */
+#define CMU_SYNCBUSY_HFXOBSY_DEFAULT                        (_CMU_SYNCBUSY_HFXOBSY_DEFAULT << 28)      /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
+#define CMU_SYNCBUSY_LFXOBSY                                (0x1UL << 29)                              /**< LFXO Busy */
+#define _CMU_SYNCBUSY_LFXOBSY_SHIFT                         29                                         /**< Shift value for CMU_LFXOBSY */
+#define _CMU_SYNCBUSY_LFXOBSY_MASK                          0x20000000UL                               /**< Bit mask for CMU_LFXOBSY */
+#define _CMU_SYNCBUSY_LFXOBSY_DEFAULT                       0x00000000UL                               /**< Mode DEFAULT for CMU_SYNCBUSY */
+#define CMU_SYNCBUSY_LFXOBSY_DEFAULT                        (_CMU_SYNCBUSY_LFXOBSY_DEFAULT << 29)      /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
+
+/* Bit fields for CMU FREEZE */
+#define _CMU_FREEZE_RESETVALUE                              0x00000000UL                         /**< Default value for CMU_FREEZE */
+#define _CMU_FREEZE_MASK                                    0x00000001UL                         /**< Mask for CMU_FREEZE */
+#define CMU_FREEZE_REGFREEZE                                (0x1UL << 0)                         /**< Register Update Freeze */
+#define _CMU_FREEZE_REGFREEZE_SHIFT                         0                                    /**< Shift value for CMU_REGFREEZE */
+#define _CMU_FREEZE_REGFREEZE_MASK                          0x1UL                                /**< Bit mask for CMU_REGFREEZE */
+#define _CMU_FREEZE_REGFREEZE_DEFAULT                       0x00000000UL                         /**< Mode DEFAULT for CMU_FREEZE */
+#define _CMU_FREEZE_REGFREEZE_UPDATE                        0x00000000UL                         /**< Mode UPDATE for CMU_FREEZE */
+#define _CMU_FREEZE_REGFREEZE_FREEZE                        0x00000001UL                         /**< Mode FREEZE for CMU_FREEZE */
+#define CMU_FREEZE_REGFREEZE_DEFAULT                        (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */
+#define CMU_FREEZE_REGFREEZE_UPDATE                         (_CMU_FREEZE_REGFREEZE_UPDATE << 0)  /**< Shifted mode UPDATE for CMU_FREEZE */
+#define CMU_FREEZE_REGFREEZE_FREEZE                         (_CMU_FREEZE_REGFREEZE_FREEZE << 0)  /**< Shifted mode FREEZE for CMU_FREEZE */
+
+/* Bit fields for CMU PCNTCTRL */
+#define _CMU_PCNTCTRL_RESETVALUE                            0x00000000UL                             /**< Default value for CMU_PCNTCTRL */
+#define _CMU_PCNTCTRL_MASK                                  0x00000003UL                             /**< Mask for CMU_PCNTCTRL */
+#define CMU_PCNTCTRL_PCNT0CLKEN                             (0x1UL << 0)                             /**< PCNT0 Clock Enable */
+#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT                      0                                        /**< Shift value for CMU_PCNT0CLKEN */
+#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK                       0x1UL                                    /**< Bit mask for CMU_PCNT0CLKEN */
+#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT                    0x00000000UL                             /**< Mode DEFAULT for CMU_PCNTCTRL */
+#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT                     (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0)  /**< Shifted mode DEFAULT for CMU_PCNTCTRL */
+#define CMU_PCNTCTRL_PCNT0CLKSEL                            (0x1UL << 1)                             /**< PCNT0 Clock Select */
+#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT                     1                                        /**< Shift value for CMU_PCNT0CLKSEL */
+#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK                      0x2UL                                    /**< Bit mask for CMU_PCNT0CLKSEL */
+#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT                   0x00000000UL                             /**< Mode DEFAULT for CMU_PCNTCTRL */
+#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK                    0x00000000UL                             /**< Mode LFACLK for CMU_PCNTCTRL */
+#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0                   0x00000001UL                             /**< Mode PCNT0S0 for CMU_PCNTCTRL */
+#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT                    (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */
+#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK                     (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1)  /**< Shifted mode LFACLK for CMU_PCNTCTRL */
+#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0                    (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */
+
+/* Bit fields for CMU ADCCTRL */
+#define _CMU_ADCCTRL_RESETVALUE                             0x00000000UL                            /**< Default value for CMU_ADCCTRL */
+#define _CMU_ADCCTRL_MASK                                   0x00000130UL                            /**< Mask for CMU_ADCCTRL */
+#define _CMU_ADCCTRL_ADC0CLKSEL_SHIFT                       4                                       /**< Shift value for CMU_ADC0CLKSEL */
+#define _CMU_ADCCTRL_ADC0CLKSEL_MASK                        0x30UL                                  /**< Bit mask for CMU_ADC0CLKSEL */
+#define _CMU_ADCCTRL_ADC0CLKSEL_DEFAULT                     0x00000000UL                            /**< Mode DEFAULT for CMU_ADCCTRL */
+#define _CMU_ADCCTRL_ADC0CLKSEL_DISABLED                    0x00000000UL                            /**< Mode DISABLED for CMU_ADCCTRL */
+#define _CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO                    0x00000001UL                            /**< Mode AUXHFRCO for CMU_ADCCTRL */
+#define _CMU_ADCCTRL_ADC0CLKSEL_HFXO                        0x00000002UL                            /**< Mode HFXO for CMU_ADCCTRL */
+#define _CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK                    0x00000003UL                            /**< Mode HFSRCCLK for CMU_ADCCTRL */
+#define CMU_ADCCTRL_ADC0CLKSEL_DEFAULT                      (_CMU_ADCCTRL_ADC0CLKSEL_DEFAULT << 4)  /**< Shifted mode DEFAULT for CMU_ADCCTRL */
+#define CMU_ADCCTRL_ADC0CLKSEL_DISABLED                     (_CMU_ADCCTRL_ADC0CLKSEL_DISABLED << 4) /**< Shifted mode DISABLED for CMU_ADCCTRL */
+#define CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO                     (_CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */
+#define CMU_ADCCTRL_ADC0CLKSEL_HFXO                         (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << 4)     /**< Shifted mode HFXO for CMU_ADCCTRL */
+#define CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK                     (_CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK << 4) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */
+#define CMU_ADCCTRL_ADC0CLKINV                              (0x1UL << 8)                            /**< Invert clock selected by ADC0CLKSEL */
+#define _CMU_ADCCTRL_ADC0CLKINV_SHIFT                       8                                       /**< Shift value for CMU_ADC0CLKINV */
+#define _CMU_ADCCTRL_ADC0CLKINV_MASK                        0x100UL                                 /**< Bit mask for CMU_ADC0CLKINV */
+#define _CMU_ADCCTRL_ADC0CLKINV_DEFAULT                     0x00000000UL                            /**< Mode DEFAULT for CMU_ADCCTRL */
+#define CMU_ADCCTRL_ADC0CLKINV_DEFAULT                      (_CMU_ADCCTRL_ADC0CLKINV_DEFAULT << 8)  /**< Shifted mode DEFAULT for CMU_ADCCTRL */
+
+/* Bit fields for CMU ROUTEPEN */
+#define _CMU_ROUTEPEN_RESETVALUE                            0x00000000UL                            /**< Default value for CMU_ROUTEPEN */
+#define _CMU_ROUTEPEN_MASK                                  0x00000003UL                            /**< Mask for CMU_ROUTEPEN */
+#define CMU_ROUTEPEN_CLKOUT0PEN                             (0x1UL << 0)                            /**< CLKOUT0 Pin Enable */
+#define _CMU_ROUTEPEN_CLKOUT0PEN_SHIFT                      0                                       /**< Shift value for CMU_CLKOUT0PEN */
+#define _CMU_ROUTEPEN_CLKOUT0PEN_MASK                       0x1UL                                   /**< Bit mask for CMU_CLKOUT0PEN */
+#define _CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT                    0x00000000UL                            /**< Mode DEFAULT for CMU_ROUTEPEN */
+#define CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT                     (_CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */
+#define CMU_ROUTEPEN_CLKOUT1PEN                             (0x1UL << 1)                            /**< CLKOUT1 Pin Enable */
+#define _CMU_ROUTEPEN_CLKOUT1PEN_SHIFT                      1                                       /**< Shift value for CMU_CLKOUT1PEN */
+#define _CMU_ROUTEPEN_CLKOUT1PEN_MASK                       0x2UL                                   /**< Bit mask for CMU_CLKOUT1PEN */
+#define _CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT                    0x00000000UL                            /**< Mode DEFAULT for CMU_ROUTEPEN */
+#define CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT                     (_CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */
+
+/* Bit fields for CMU ROUTELOC0 */
+#define _CMU_ROUTELOC0_RESETVALUE                           0x00000000UL                             /**< Default value for CMU_ROUTELOC0 */
+#define _CMU_ROUTELOC0_MASK                                 0x00000707UL                             /**< Mask for CMU_ROUTELOC0 */
+#define _CMU_ROUTELOC0_CLKOUT0LOC_SHIFT                     0                                        /**< Shift value for CMU_CLKOUT0LOC */
+#define _CMU_ROUTELOC0_CLKOUT0LOC_MASK                      0x7UL                                    /**< Bit mask for CMU_CLKOUT0LOC */
+#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC0                      0x00000000UL                             /**< Mode LOC0 for CMU_ROUTELOC0 */
+#define _CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT                   0x00000000UL                             /**< Mode DEFAULT for CMU_ROUTELOC0 */
+#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC1                      0x00000001UL                             /**< Mode LOC1 for CMU_ROUTELOC0 */
+#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC2                      0x00000002UL                             /**< Mode LOC2 for CMU_ROUTELOC0 */
+#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC3                      0x00000003UL                             /**< Mode LOC3 for CMU_ROUTELOC0 */
+#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC4                      0x00000004UL                             /**< Mode LOC4 for CMU_ROUTELOC0 */
+#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC5                      0x00000005UL                             /**< Mode LOC5 for CMU_ROUTELOC0 */
+#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC6                      0x00000006UL                             /**< Mode LOC6 for CMU_ROUTELOC0 */
+#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC7                      0x00000007UL                             /**< Mode LOC7 for CMU_ROUTELOC0 */
+#define CMU_ROUTELOC0_CLKOUT0LOC_LOC0                       (_CMU_ROUTELOC0_CLKOUT0LOC_LOC0 << 0)    /**< Shifted mode LOC0 for CMU_ROUTELOC0 */
+#define CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT                    (_CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */
+#define CMU_ROUTELOC0_CLKOUT0LOC_LOC1                       (_CMU_ROUTELOC0_CLKOUT0LOC_LOC1 << 0)    /**< Shifted mode LOC1 for CMU_ROUTELOC0 */
+#define CMU_ROUTELOC0_CLKOUT0LOC_LOC2                       (_CMU_ROUTELOC0_CLKOUT0LOC_LOC2 << 0)    /**< Shifted mode LOC2 for CMU_ROUTELOC0 */
+#define CMU_ROUTELOC0_CLKOUT0LOC_LOC3                       (_CMU_ROUTELOC0_CLKOUT0LOC_LOC3 << 0)    /**< Shifted mode LOC3 for CMU_ROUTELOC0 */
+#define CMU_ROUTELOC0_CLKOUT0LOC_LOC4                       (_CMU_ROUTELOC0_CLKOUT0LOC_LOC4 << 0)    /**< Shifted mode LOC4 for CMU_ROUTELOC0 */
+#define CMU_ROUTELOC0_CLKOUT0LOC_LOC5                       (_CMU_ROUTELOC0_CLKOUT0LOC_LOC5 << 0)    /**< Shifted mode LOC5 for CMU_ROUTELOC0 */
+#define CMU_ROUTELOC0_CLKOUT0LOC_LOC6                       (_CMU_ROUTELOC0_CLKOUT0LOC_LOC6 << 0)    /**< Shifted mode LOC6 for CMU_ROUTELOC0 */
+#define CMU_ROUTELOC0_CLKOUT0LOC_LOC7                       (_CMU_ROUTELOC0_CLKOUT0LOC_LOC7 << 0)    /**< Shifted mode LOC7 for CMU_ROUTELOC0 */
+#define _CMU_ROUTELOC0_CLKOUT1LOC_SHIFT                     8                                        /**< Shift value for CMU_CLKOUT1LOC */
+#define _CMU_ROUTELOC0_CLKOUT1LOC_MASK                      0x700UL                                  /**< Bit mask for CMU_CLKOUT1LOC */
+#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC0                      0x00000000UL                             /**< Mode LOC0 for CMU_ROUTELOC0 */
+#define _CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT                   0x00000000UL                             /**< Mode DEFAULT for CMU_ROUTELOC0 */
+#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC1                      0x00000001UL                             /**< Mode LOC1 for CMU_ROUTELOC0 */
+#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC2                      0x00000002UL                             /**< Mode LOC2 for CMU_ROUTELOC0 */
+#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC3                      0x00000003UL                             /**< Mode LOC3 for CMU_ROUTELOC0 */
+#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC4                      0x00000004UL                             /**< Mode LOC4 for CMU_ROUTELOC0 */
+#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC5                      0x00000005UL                             /**< Mode LOC5 for CMU_ROUTELOC0 */
+#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC6                      0x00000006UL                             /**< Mode LOC6 for CMU_ROUTELOC0 */
+#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC7                      0x00000007UL                             /**< Mode LOC7 for CMU_ROUTELOC0 */
+#define CMU_ROUTELOC0_CLKOUT1LOC_LOC0                       (_CMU_ROUTELOC0_CLKOUT1LOC_LOC0 << 8)    /**< Shifted mode LOC0 for CMU_ROUTELOC0 */
+#define CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT                    (_CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */
+#define CMU_ROUTELOC0_CLKOUT1LOC_LOC1                       (_CMU_ROUTELOC0_CLKOUT1LOC_LOC1 << 8)    /**< Shifted mode LOC1 for CMU_ROUTELOC0 */
+#define CMU_ROUTELOC0_CLKOUT1LOC_LOC2                       (_CMU_ROUTELOC0_CLKOUT1LOC_LOC2 << 8)    /**< Shifted mode LOC2 for CMU_ROUTELOC0 */
+#define CMU_ROUTELOC0_CLKOUT1LOC_LOC3                       (_CMU_ROUTELOC0_CLKOUT1LOC_LOC3 << 8)    /**< Shifted mode LOC3 for CMU_ROUTELOC0 */
+#define CMU_ROUTELOC0_CLKOUT1LOC_LOC4                       (_CMU_ROUTELOC0_CLKOUT1LOC_LOC4 << 8)    /**< Shifted mode LOC4 for CMU_ROUTELOC0 */
+#define CMU_ROUTELOC0_CLKOUT1LOC_LOC5                       (_CMU_ROUTELOC0_CLKOUT1LOC_LOC5 << 8)    /**< Shifted mode LOC5 for CMU_ROUTELOC0 */
+#define CMU_ROUTELOC0_CLKOUT1LOC_LOC6                       (_CMU_ROUTELOC0_CLKOUT1LOC_LOC6 << 8)    /**< Shifted mode LOC6 for CMU_ROUTELOC0 */
+#define CMU_ROUTELOC0_CLKOUT1LOC_LOC7                       (_CMU_ROUTELOC0_CLKOUT1LOC_LOC7 << 8)    /**< Shifted mode LOC7 for CMU_ROUTELOC0 */
+
+/* Bit fields for CMU LOCK */
+#define _CMU_LOCK_RESETVALUE                                0x00000000UL                      /**< Default value for CMU_LOCK */
+#define _CMU_LOCK_MASK                                      0x0000FFFFUL                      /**< Mask for CMU_LOCK */
+#define _CMU_LOCK_LOCKKEY_SHIFT                             0                                 /**< Shift value for CMU_LOCKKEY */
+#define _CMU_LOCK_LOCKKEY_MASK                              0xFFFFUL                          /**< Bit mask for CMU_LOCKKEY */
+#define _CMU_LOCK_LOCKKEY_DEFAULT                           0x00000000UL                      /**< Mode DEFAULT for CMU_LOCK */
+#define _CMU_LOCK_LOCKKEY_LOCK                              0x00000000UL                      /**< Mode LOCK for CMU_LOCK */
+#define _CMU_LOCK_LOCKKEY_UNLOCKED                          0x00000000UL                      /**< Mode UNLOCKED for CMU_LOCK */
+#define _CMU_LOCK_LOCKKEY_LOCKED                            0x00000001UL                      /**< Mode LOCKED for CMU_LOCK */
+#define _CMU_LOCK_LOCKKEY_UNLOCK                            0x0000580EUL                      /**< Mode UNLOCK for CMU_LOCK */
+#define CMU_LOCK_LOCKKEY_DEFAULT                            (_CMU_LOCK_LOCKKEY_DEFAULT << 0)  /**< Shifted mode DEFAULT for CMU_LOCK */
+#define CMU_LOCK_LOCKKEY_LOCK                               (_CMU_LOCK_LOCKKEY_LOCK << 0)     /**< Shifted mode LOCK for CMU_LOCK */
+#define CMU_LOCK_LOCKKEY_UNLOCKED                           (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */
+#define CMU_LOCK_LOCKKEY_LOCKED                             (_CMU_LOCK_LOCKKEY_LOCKED << 0)   /**< Shifted mode LOCKED for CMU_LOCK */
+#define CMU_LOCK_LOCKKEY_UNLOCK                             (_CMU_LOCK_LOCKKEY_UNLOCK << 0)   /**< Shifted mode UNLOCK for CMU_LOCK */
+
+/** @} End of group EFM32PG1B_CMU */
+/** @} End of group Parts */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG_STK3401/efm32pg1b_cryotimer.h	Fri Jan 15 07:45:16 2016 +0000
@@ -0,0 +1,165 @@
+/**************************************************************************//**
+ * @file efm32pg1b_cryotimer.h
+ * @brief EFM32PG1B_CRYOTIMER register and bit field definitions
+ * @version 4.2.0
+ ******************************************************************************
+ * @section License
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ ******************************************************************************
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software.@n
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.@n
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is
+ * providing the Software "AS IS", with no express or implied warranties of any
+ * kind, including, but not limited to, any implied warranties of
+ * merchantability or fitness for any particular purpose or warranties against
+ * infringement of any proprietary rights of a third party.
+ *
+ * Silicon Laboratories, Inc. will not be liable for any consequential,
+ * incidental, or special damages, or any other relief, or for any claim by
+ * any third party, arising from your use of this Software.
+ *
+ *****************************************************************************/
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFM32PG1B_CRYOTIMER
+ * @{
+ * @brief EFM32PG1B_CRYOTIMER Register Declaration
+ *****************************************************************************/
+typedef struct
+{
+  __IO uint32_t CTRL;      /**< Control Register  */
+  __IO uint32_t PERIODSEL; /**< Interrupt Duration  */
+  __I uint32_t  CNT;       /**< Counter Value  */
+  __IO uint32_t EM4WUEN;   /**< Wake Up Enable  */
+  __I uint32_t  IF;        /**< Interrupt Flag Register  */
+  __IO uint32_t IFS;       /**< Interrupt Flag Set Register  */
+  __IO uint32_t IFC;       /**< Interrupt Flag Clear Register  */
+  __IO uint32_t IEN;       /**< Interrupt Enable Register  */
+} CRYOTIMER_TypeDef;       /** @} */
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B_CRYOTIMER_BitFields
+ * @{
+ *****************************************************************************/
+
+/* Bit fields for CRYOTIMER CTRL */
+#define _CRYOTIMER_CTRL_RESETVALUE                0x00000000UL                            /**< Default value for CRYOTIMER_CTRL */
+#define _CRYOTIMER_CTRL_MASK                      0x000000EFUL                            /**< Mask for CRYOTIMER_CTRL */
+#define CRYOTIMER_CTRL_EN                         (0x1UL << 0)                            /**< Enable CRYOTIMER */
+#define _CRYOTIMER_CTRL_EN_SHIFT                  0                                       /**< Shift value for CRYOTIMER_EN */
+#define _CRYOTIMER_CTRL_EN_MASK                   0x1UL                                   /**< Bit mask for CRYOTIMER_EN */
+#define _CRYOTIMER_CTRL_EN_DEFAULT                0x00000000UL                            /**< Mode DEFAULT for CRYOTIMER_CTRL */
+#define CRYOTIMER_CTRL_EN_DEFAULT                 (_CRYOTIMER_CTRL_EN_DEFAULT << 0)       /**< Shifted mode DEFAULT for CRYOTIMER_CTRL */
+#define CRYOTIMER_CTRL_DEBUGRUN                   (0x1UL << 1)                            /**< Debug Mode Run Enable */
+#define _CRYOTIMER_CTRL_DEBUGRUN_SHIFT            1                                       /**< Shift value for CRYOTIMER_DEBUGRUN */
+#define _CRYOTIMER_CTRL_DEBUGRUN_MASK             0x2UL                                   /**< Bit mask for CRYOTIMER_DEBUGRUN */
+#define _CRYOTIMER_CTRL_DEBUGRUN_DEFAULT          0x00000000UL                            /**< Mode DEFAULT for CRYOTIMER_CTRL */
+#define CRYOTIMER_CTRL_DEBUGRUN_DEFAULT           (_CRYOTIMER_CTRL_DEBUGRUN_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYOTIMER_CTRL */
+#define _CRYOTIMER_CTRL_OSCSEL_SHIFT              2                                       /**< Shift value for CRYOTIMER_OSCSEL */
+#define _CRYOTIMER_CTRL_OSCSEL_MASK               0xCUL                                   /**< Bit mask for CRYOTIMER_OSCSEL */
+#define _CRYOTIMER_CTRL_OSCSEL_DEFAULT            0x00000000UL                            /**< Mode DEFAULT for CRYOTIMER_CTRL */
+#define _CRYOTIMER_CTRL_OSCSEL_LFRCO              0x00000000UL                            /**< Mode LFRCO for CRYOTIMER_CTRL */
+#define _CRYOTIMER_CTRL_OSCSEL_LFXO               0x00000001UL                            /**< Mode LFXO for CRYOTIMER_CTRL */
+#define _CRYOTIMER_CTRL_OSCSEL_ULFRCO             0x00000002UL                            /**< Mode ULFRCO for CRYOTIMER_CTRL */
+#define CRYOTIMER_CTRL_OSCSEL_DEFAULT             (_CRYOTIMER_CTRL_OSCSEL_DEFAULT << 2)   /**< Shifted mode DEFAULT for CRYOTIMER_CTRL */
+#define CRYOTIMER_CTRL_OSCSEL_LFRCO               (_CRYOTIMER_CTRL_OSCSEL_LFRCO << 2)     /**< Shifted mode LFRCO for CRYOTIMER_CTRL */
+#define CRYOTIMER_CTRL_OSCSEL_LFXO                (_CRYOTIMER_CTRL_OSCSEL_LFXO << 2)      /**< Shifted mode LFXO for CRYOTIMER_CTRL */
+#define CRYOTIMER_CTRL_OSCSEL_ULFRCO              (_CRYOTIMER_CTRL_OSCSEL_ULFRCO << 2)    /**< Shifted mode ULFRCO for CRYOTIMER_CTRL */
+#define _CRYOTIMER_CTRL_PRESC_SHIFT               5                                       /**< Shift value for CRYOTIMER_PRESC */
+#define _CRYOTIMER_CTRL_PRESC_MASK                0xE0UL                                  /**< Bit mask for CRYOTIMER_PRESC */
+#define _CRYOTIMER_CTRL_PRESC_DEFAULT             0x00000000UL                            /**< Mode DEFAULT for CRYOTIMER_CTRL */
+#define _CRYOTIMER_CTRL_PRESC_DIV1                0x00000000UL                            /**< Mode DIV1 for CRYOTIMER_CTRL */
+#define _CRYOTIMER_CTRL_PRESC_DIV2                0x00000001UL                            /**< Mode DIV2 for CRYOTIMER_CTRL */
+#define _CRYOTIMER_CTRL_PRESC_DIV4                0x00000002UL                            /**< Mode DIV4 for CRYOTIMER_CTRL */
+#define _CRYOTIMER_CTRL_PRESC_DIV8                0x00000003UL                            /**< Mode DIV8 for CRYOTIMER_CTRL */
+#define _CRYOTIMER_CTRL_PRESC_DIV16               0x00000004UL                            /**< Mode DIV16 for CRYOTIMER_CTRL */
+#define _CRYOTIMER_CTRL_PRESC_DIV32               0x00000005UL                            /**< Mode DIV32 for CRYOTIMER_CTRL */
+#define _CRYOTIMER_CTRL_PRESC_DIV64               0x00000006UL                            /**< Mode DIV64 for CRYOTIMER_CTRL */
+#define _CRYOTIMER_CTRL_PRESC_DIV128              0x00000007UL                            /**< Mode DIV128 for CRYOTIMER_CTRL */
+#define CRYOTIMER_CTRL_PRESC_DEFAULT              (_CRYOTIMER_CTRL_PRESC_DEFAULT << 5)    /**< Shifted mode DEFAULT for CRYOTIMER_CTRL */
+#define CRYOTIMER_CTRL_PRESC_DIV1                 (_CRYOTIMER_CTRL_PRESC_DIV1 << 5)       /**< Shifted mode DIV1 for CRYOTIMER_CTRL */
+#define CRYOTIMER_CTRL_PRESC_DIV2                 (_CRYOTIMER_CTRL_PRESC_DIV2 << 5)       /**< Shifted mode DIV2 for CRYOTIMER_CTRL */
+#define CRYOTIMER_CTRL_PRESC_DIV4                 (_CRYOTIMER_CTRL_PRESC_DIV4 << 5)       /**< Shifted mode DIV4 for CRYOTIMER_CTRL */
+#define CRYOTIMER_CTRL_PRESC_DIV8                 (_CRYOTIMER_CTRL_PRESC_DIV8 << 5)       /**< Shifted mode DIV8 for CRYOTIMER_CTRL */
+#define CRYOTIMER_CTRL_PRESC_DIV16                (_CRYOTIMER_CTRL_PRESC_DIV16 << 5)      /**< Shifted mode DIV16 for CRYOTIMER_CTRL */
+#define CRYOTIMER_CTRL_PRESC_DIV32                (_CRYOTIMER_CTRL_PRESC_DIV32 << 5)      /**< Shifted mode DIV32 for CRYOTIMER_CTRL */
+#define CRYOTIMER_CTRL_PRESC_DIV64                (_CRYOTIMER_CTRL_PRESC_DIV64 << 5)      /**< Shifted mode DIV64 for CRYOTIMER_CTRL */
+#define CRYOTIMER_CTRL_PRESC_DIV128               (_CRYOTIMER_CTRL_PRESC_DIV128 << 5)     /**< Shifted mode DIV128 for CRYOTIMER_CTRL */
+
+/* Bit fields for CRYOTIMER PERIODSEL */
+#define _CRYOTIMER_PERIODSEL_RESETVALUE           0x00000020UL                                  /**< Default value for CRYOTIMER_PERIODSEL */
+#define _CRYOTIMER_PERIODSEL_MASK                 0x0000003FUL                                  /**< Mask for CRYOTIMER_PERIODSEL */
+#define _CRYOTIMER_PERIODSEL_PERIODSEL_SHIFT      0                                             /**< Shift value for CRYOTIMER_PERIODSEL */
+#define _CRYOTIMER_PERIODSEL_PERIODSEL_MASK       0x3FUL                                        /**< Bit mask for CRYOTIMER_PERIODSEL */
+#define _CRYOTIMER_PERIODSEL_PERIODSEL_DEFAULT    0x00000020UL                                  /**< Mode DEFAULT for CRYOTIMER_PERIODSEL */
+#define CRYOTIMER_PERIODSEL_PERIODSEL_DEFAULT     (_CRYOTIMER_PERIODSEL_PERIODSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_PERIODSEL */
+
+/* Bit fields for CRYOTIMER CNT */
+#define _CRYOTIMER_CNT_RESETVALUE                 0x00000000UL                      /**< Default value for CRYOTIMER_CNT */
+#define _CRYOTIMER_CNT_MASK                       0xFFFFFFFFUL                      /**< Mask for CRYOTIMER_CNT */
+#define _CRYOTIMER_CNT_CNT_SHIFT                  0                                 /**< Shift value for CRYOTIMER_CNT */
+#define _CRYOTIMER_CNT_CNT_MASK                   0xFFFFFFFFUL                      /**< Bit mask for CRYOTIMER_CNT */
+#define _CRYOTIMER_CNT_CNT_DEFAULT                0x00000000UL                      /**< Mode DEFAULT for CRYOTIMER_CNT */
+#define CRYOTIMER_CNT_CNT_DEFAULT                 (_CRYOTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_CNT */
+
+/* Bit fields for CRYOTIMER EM4WUEN */
+#define _CRYOTIMER_EM4WUEN_RESETVALUE             0x00000000UL                            /**< Default value for CRYOTIMER_EM4WUEN */
+#define _CRYOTIMER_EM4WUEN_MASK                   0x00000001UL                            /**< Mask for CRYOTIMER_EM4WUEN */
+#define CRYOTIMER_EM4WUEN_EM4WU                   (0x1UL << 0)                            /**< EM4 Wake-up enable */
+#define _CRYOTIMER_EM4WUEN_EM4WU_SHIFT            0                                       /**< Shift value for CRYOTIMER_EM4WU */
+#define _CRYOTIMER_EM4WUEN_EM4WU_MASK             0x1UL                                   /**< Bit mask for CRYOTIMER_EM4WU */
+#define _CRYOTIMER_EM4WUEN_EM4WU_DEFAULT          0x00000000UL                            /**< Mode DEFAULT for CRYOTIMER_EM4WUEN */
+#define CRYOTIMER_EM4WUEN_EM4WU_DEFAULT           (_CRYOTIMER_EM4WUEN_EM4WU_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_EM4WUEN */
+
+/* Bit fields for CRYOTIMER IF */
+#define _CRYOTIMER_IF_RESETVALUE                  0x00000000UL                        /**< Default value for CRYOTIMER_IF */
+#define _CRYOTIMER_IF_MASK                        0x00000001UL                        /**< Mask for CRYOTIMER_IF */
+#define CRYOTIMER_IF_PERIOD                       (0x1UL << 0)                        /**< Wakeup event/Interrupt */
+#define _CRYOTIMER_IF_PERIOD_SHIFT                0                                   /**< Shift value for CRYOTIMER_PERIOD */
+#define _CRYOTIMER_IF_PERIOD_MASK                 0x1UL                               /**< Bit mask for CRYOTIMER_PERIOD */
+#define _CRYOTIMER_IF_PERIOD_DEFAULT              0x00000000UL                        /**< Mode DEFAULT for CRYOTIMER_IF */
+#define CRYOTIMER_IF_PERIOD_DEFAULT               (_CRYOTIMER_IF_PERIOD_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_IF */
+
+/* Bit fields for CRYOTIMER IFS */
+#define _CRYOTIMER_IFS_RESETVALUE                 0x00000000UL                         /**< Default value for CRYOTIMER_IFS */
+#define _CRYOTIMER_IFS_MASK                       0x00000001UL                         /**< Mask for CRYOTIMER_IFS */
+#define CRYOTIMER_IFS_PERIOD                      (0x1UL << 0)                         /**< Set PERIOD Interrupt Flag */
+#define _CRYOTIMER_IFS_PERIOD_SHIFT               0                                    /**< Shift value for CRYOTIMER_PERIOD */
+#define _CRYOTIMER_IFS_PERIOD_MASK                0x1UL                                /**< Bit mask for CRYOTIMER_PERIOD */
+#define _CRYOTIMER_IFS_PERIOD_DEFAULT             0x00000000UL                         /**< Mode DEFAULT for CRYOTIMER_IFS */
+#define CRYOTIMER_IFS_PERIOD_DEFAULT              (_CRYOTIMER_IFS_PERIOD_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_IFS */
+
+/* Bit fields for CRYOTIMER IFC */
+#define _CRYOTIMER_IFC_RESETVALUE                 0x00000000UL                         /**< Default value for CRYOTIMER_IFC */
+#define _CRYOTIMER_IFC_MASK                       0x00000001UL                         /**< Mask for CRYOTIMER_IFC */
+#define CRYOTIMER_IFC_PERIOD                      (0x1UL << 0)                         /**< Clear PERIOD Interrupt Flag */
+#define _CRYOTIMER_IFC_PERIOD_SHIFT               0                                    /**< Shift value for CRYOTIMER_PERIOD */
+#define _CRYOTIMER_IFC_PERIOD_MASK                0x1UL                                /**< Bit mask for CRYOTIMER_PERIOD */
+#define _CRYOTIMER_IFC_PERIOD_DEFAULT             0x00000000UL                         /**< Mode DEFAULT for CRYOTIMER_IFC */
+#define CRYOTIMER_IFC_PERIOD_DEFAULT              (_CRYOTIMER_IFC_PERIOD_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_IFC */
+
+/* Bit fields for CRYOTIMER IEN */
+#define _CRYOTIMER_IEN_RESETVALUE                 0x00000000UL                         /**< Default value for CRYOTIMER_IEN */
+#define _CRYOTIMER_IEN_MASK                       0x00000001UL                         /**< Mask for CRYOTIMER_IEN */
+#define CRYOTIMER_IEN_PERIOD                      (0x1UL << 0)                         /**< PERIOD Interrupt Enable */
+#define _CRYOTIMER_IEN_PERIOD_SHIFT               0                                    /**< Shift value for CRYOTIMER_PERIOD */
+#define _CRYOTIMER_IEN_PERIOD_MASK                0x1UL                                /**< Bit mask for CRYOTIMER_PERIOD */
+#define _CRYOTIMER_IEN_PERIOD_DEFAULT             0x00000000UL                         /**< Mode DEFAULT for CRYOTIMER_IEN */
+#define CRYOTIMER_IEN_PERIOD_DEFAULT              (_CRYOTIMER_IEN_PERIOD_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_IEN */
+
+/** @} End of group EFM32PG1B_CRYOTIMER */
+/** @} End of group Parts */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG_STK3401/efm32pg1b_crypto.h	Fri Jan 15 07:45:16 2016 +0000
@@ -0,0 +1,1226 @@
+/**************************************************************************//**
+ * @file efm32pg1b_crypto.h
+ * @brief EFM32PG1B_CRYPTO register and bit field definitions
+ * @version 4.2.0
+ ******************************************************************************
+ * @section License
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ ******************************************************************************
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software.@n
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.@n
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is
+ * providing the Software "AS IS", with no express or implied warranties of any
+ * kind, including, but not limited to, any implied warranties of
+ * merchantability or fitness for any particular purpose or warranties against
+ * infringement of any proprietary rights of a third party.
+ *
+ * Silicon Laboratories, Inc. will not be liable for any consequential,
+ * incidental, or special damages, or any other relief, or for any claim by
+ * any third party, arising from your use of this Software.
+ *
+ *****************************************************************************/
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFM32PG1B_CRYPTO
+ * @{
+ * @brief EFM32PG1B_CRYPTO Register Declaration
+ *****************************************************************************/
+typedef struct
+{
+  __IO uint32_t CTRL;           /**< Control Register  */
+  __IO uint32_t WAC;            /**< Wide Arithmetic Configuration  */
+  __IO uint32_t CMD;            /**< Command Register  */
+  uint32_t      RESERVED0[1];   /**< Reserved for future use **/
+  __I uint32_t  STATUS;         /**< Status Register  */
+  __I uint32_t  DSTATUS;        /**< Data Status Register  */
+  __I uint32_t  CSTATUS;        /**< Control Status Register  */
+  uint32_t      RESERVED1[1];   /**< Reserved for future use **/
+  __IO uint32_t KEY;            /**< KEY Register Access  */
+  __IO uint32_t KEYBUF;         /**< KEY Buffer Register Access  */
+  uint32_t      RESERVED2[2];   /**< Reserved for future use **/
+  __IO uint32_t SEQCTRL;        /**< Sequence Control  */
+  __IO uint32_t SEQCTRLB;       /**< Sequence Control B  */
+  uint32_t      RESERVED3[2];   /**< Reserved for future use **/
+  __I uint32_t  IF;             /**< AES Interrupt Flags  */
+  __IO uint32_t IFS;            /**< Interrupt Flag Set Register  */
+  __IO uint32_t IFC;            /**< Interrupt Flag Clear Register  */
+  __IO uint32_t IEN;            /**< Interrupt Enable Register  */
+  __IO uint32_t SEQ0;           /**< Sequence register 0  */
+  __IO uint32_t SEQ1;           /**< Sequence Register 1  */
+  __IO uint32_t SEQ2;           /**< Sequence Register 2  */
+  __IO uint32_t SEQ3;           /**< Sequence Register 3  */
+  __IO uint32_t SEQ4;           /**< Sequence Register 4  */
+  uint32_t      RESERVED4[7];   /**< Reserved for future use **/
+  __IO uint32_t DATA0;          /**< DATA0 Register Access  */
+  __IO uint32_t DATA1;          /**< DATA1 Register Access  */
+  __IO uint32_t DATA2;          /**< DATA2 Register Access  */
+  __IO uint32_t DATA3;          /**< DATA3 Register Access  */
+  uint32_t      RESERVED5[4];   /**< Reserved for future use **/
+  __IO uint32_t DATA0XOR;       /**< DATA0XOR Register Access  */
+  uint32_t      RESERVED6[3];   /**< Reserved for future use **/
+  __IO uint32_t DATA0BYTE;      /**< DATA0 Register Byte Access  */
+  __IO uint32_t DATA1BYTE;      /**< DATA1 Register Byte Access  */
+  uint32_t      RESERVED7[1];   /**< Reserved for future use **/
+  __IO uint32_t DATA0XORBYTE;   /**< DATA0 Register Byte XOR Access  */
+  __IO uint32_t DATA0BYTE12;    /**< DATA0 Register Byte 12 Access  */
+  __IO uint32_t DATA0BYTE13;    /**< DATA0 Register Byte 13 Access  */
+  __IO uint32_t DATA0BYTE14;    /**< DATA0 Register Byte 14 Access  */
+  __IO uint32_t DATA0BYTE15;    /**< DATA0 Register Byte 15 Access  */
+  uint32_t      RESERVED8[12];  /**< Reserved for future use **/
+  __IO uint32_t DDATA0;         /**< DDATA0 Register Access  */
+  __IO uint32_t DDATA1;         /**< DDATA1 Register Access  */
+  __IO uint32_t DDATA2;         /**< DDATA2 Register Access  */
+  __IO uint32_t DDATA3;         /**< DDATA3 Register Access  */
+  __IO uint32_t DDATA4;         /**< DDATA4 Register Access  */
+  uint32_t      RESERVED9[7];   /**< Reserved for future use **/
+  __IO uint32_t DDATA0BIG;      /**< DDATA0 Register Big Endian Access  */
+  uint32_t      RESERVED10[3];  /**< Reserved for future use **/
+  __IO uint32_t DDATA0BYTE;     /**< DDATA0 Register Byte Access  */
+  __IO uint32_t DDATA1BYTE;     /**< DDATA1 Register Byte Access  */
+  __IO uint32_t DDATA0BYTE32;   /**< DDATA0 Register Byte 32 access.  */
+  uint32_t      RESERVED11[13]; /**< Reserved for future use **/
+  __IO uint32_t QDATA0;         /**< QDATA0 Register Access  */
+  __IO uint32_t QDATA1;         /**< QDATA1 Register Access  */
+  uint32_t      RESERVED12[7];  /**< Reserved for future use **/
+  __IO uint32_t QDATA1BIG;      /**< QDATA1 Register Big Endian Access  */
+  uint32_t      RESERVED13[6];  /**< Reserved for future use **/
+  __IO uint32_t QDATA0BYTE;     /**< QDATA0 Register Byte Access  */
+  __IO uint32_t QDATA1BYTE;     /**< QDATA1 Register Byte Access  */
+} CRYPTO_TypeDef;               /** @} */
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B_CRYPTO_BitFields
+ * @{
+ *****************************************************************************/
+
+/* Bit fields for CRYPTO CTRL */
+#define _CRYPTO_CTRL_RESETVALUE                      0x00000000UL                               /**< Default value for CRYPTO_CTRL */
+#define _CRYPTO_CTRL_MASK                            0xB333C407UL                               /**< Mask for CRYPTO_CTRL */
+#define CRYPTO_CTRL_AES                              (0x1UL << 0)                               /**< AES Mode */
+#define _CRYPTO_CTRL_AES_SHIFT                       0                                          /**< Shift value for CRYPTO_AES */
+#define _CRYPTO_CTRL_AES_MASK                        0x1UL                                      /**< Bit mask for CRYPTO_AES */
+#define _CRYPTO_CTRL_AES_DEFAULT                     0x00000000UL                               /**< Mode DEFAULT for CRYPTO_CTRL */
+#define _CRYPTO_CTRL_AES_AES128                      0x00000000UL                               /**< Mode AES128 for CRYPTO_CTRL */
+#define _CRYPTO_CTRL_AES_AES256                      0x00000001UL                               /**< Mode AES256 for CRYPTO_CTRL */
+#define CRYPTO_CTRL_AES_DEFAULT                      (_CRYPTO_CTRL_AES_DEFAULT << 0)            /**< Shifted mode DEFAULT for CRYPTO_CTRL */
+#define CRYPTO_CTRL_AES_AES128                       (_CRYPTO_CTRL_AES_AES128 << 0)             /**< Shifted mode AES128 for CRYPTO_CTRL */
+#define CRYPTO_CTRL_AES_AES256                       (_CRYPTO_CTRL_AES_AES256 << 0)             /**< Shifted mode AES256 for CRYPTO_CTRL */
+#define CRYPTO_CTRL_KEYBUFDIS                        (0x1UL << 1)                               /**< Key Buffer Disable */
+#define _CRYPTO_CTRL_KEYBUFDIS_SHIFT                 1                                          /**< Shift value for CRYPTO_KEYBUFDIS */
+#define _CRYPTO_CTRL_KEYBUFDIS_MASK                  0x2UL                                      /**< Bit mask for CRYPTO_KEYBUFDIS */
+#define _CRYPTO_CTRL_KEYBUFDIS_DEFAULT               0x00000000UL                               /**< Mode DEFAULT for CRYPTO_CTRL */
+#define CRYPTO_CTRL_KEYBUFDIS_DEFAULT                (_CRYPTO_CTRL_KEYBUFDIS_DEFAULT << 1)      /**< Shifted mode DEFAULT for CRYPTO_CTRL */
+#define CRYPTO_CTRL_SHA                              (0x1UL << 2)                               /**< SHA Mode */
+#define _CRYPTO_CTRL_SHA_SHIFT                       2                                          /**< Shift value for CRYPTO_SHA */
+#define _CRYPTO_CTRL_SHA_MASK                        0x4UL                                      /**< Bit mask for CRYPTO_SHA */
+#define _CRYPTO_CTRL_SHA_DEFAULT                     0x00000000UL                               /**< Mode DEFAULT for CRYPTO_CTRL */
+#define _CRYPTO_CTRL_SHA_SHA1                        0x00000000UL                               /**< Mode SHA1 for CRYPTO_CTRL */
+#define _CRYPTO_CTRL_SHA_SHA2                        0x00000001UL                               /**< Mode SHA2 for CRYPTO_CTRL */
+#define CRYPTO_CTRL_SHA_DEFAULT                      (_CRYPTO_CTRL_SHA_DEFAULT << 2)            /**< Shifted mode DEFAULT for CRYPTO_CTRL */
+#define CRYPTO_CTRL_SHA_SHA1                         (_CRYPTO_CTRL_SHA_SHA1 << 2)               /**< Shifted mode SHA1 for CRYPTO_CTRL */
+#define CRYPTO_CTRL_SHA_SHA2                         (_CRYPTO_CTRL_SHA_SHA2 << 2)               /**< Shifted mode SHA2 for CRYPTO_CTRL */
+#define CRYPTO_CTRL_NOBUSYSTALL                      (0x1UL << 10)                              /**< No Stalling of Bus When Busy */
+#define _CRYPTO_CTRL_NOBUSYSTALL_SHIFT               10                                         /**< Shift value for CRYPTO_NOBUSYSTALL */
+#define _CRYPTO_CTRL_NOBUSYSTALL_MASK                0x400UL                                    /**< Bit mask for CRYPTO_NOBUSYSTALL */
+#define _CRYPTO_CTRL_NOBUSYSTALL_DEFAULT             0x00000000UL                               /**< Mode DEFAULT for CRYPTO_CTRL */
+#define CRYPTO_CTRL_NOBUSYSTALL_DEFAULT              (_CRYPTO_CTRL_NOBUSYSTALL_DEFAULT << 10)   /**< Shifted mode DEFAULT for CRYPTO_CTRL */
+#define _CRYPTO_CTRL_INCWIDTH_SHIFT                  14                                         /**< Shift value for CRYPTO_INCWIDTH */
+#define _CRYPTO_CTRL_INCWIDTH_MASK                   0xC000UL                                   /**< Bit mask for CRYPTO_INCWIDTH */
+#define _CRYPTO_CTRL_INCWIDTH_DEFAULT                0x00000000UL                               /**< Mode DEFAULT for CRYPTO_CTRL */
+#define _CRYPTO_CTRL_INCWIDTH_INCWIDTH1              0x00000000UL                               /**< Mode INCWIDTH1 for CRYPTO_CTRL */
+#define _CRYPTO_CTRL_INCWIDTH_INCWIDTH2              0x00000001UL                               /**< Mode INCWIDTH2 for CRYPTO_CTRL */
+#define _CRYPTO_CTRL_INCWIDTH_INCWIDTH3              0x00000002UL                               /**< Mode INCWIDTH3 for CRYPTO_CTRL */
+#define _CRYPTO_CTRL_INCWIDTH_INCWIDTH4              0x00000003UL                               /**< Mode INCWIDTH4 for CRYPTO_CTRL */
+#define CRYPTO_CTRL_INCWIDTH_DEFAULT                 (_CRYPTO_CTRL_INCWIDTH_DEFAULT << 14)      /**< Shifted mode DEFAULT for CRYPTO_CTRL */
+#define CRYPTO_CTRL_INCWIDTH_INCWIDTH1               (_CRYPTO_CTRL_INCWIDTH_INCWIDTH1 << 14)    /**< Shifted mode INCWIDTH1 for CRYPTO_CTRL */
+#define CRYPTO_CTRL_INCWIDTH_INCWIDTH2               (_CRYPTO_CTRL_INCWIDTH_INCWIDTH2 << 14)    /**< Shifted mode INCWIDTH2 for CRYPTO_CTRL */
+#define CRYPTO_CTRL_INCWIDTH_INCWIDTH3               (_CRYPTO_CTRL_INCWIDTH_INCWIDTH3 << 14)    /**< Shifted mode INCWIDTH3 for CRYPTO_CTRL */
+#define CRYPTO_CTRL_INCWIDTH_INCWIDTH4               (_CRYPTO_CTRL_INCWIDTH_INCWIDTH4 << 14)    /**< Shifted mode INCWIDTH4 for CRYPTO_CTRL */
+#define _CRYPTO_CTRL_DMA0MODE_SHIFT                  16                                         /**< Shift value for CRYPTO_DMA0MODE */
+#define _CRYPTO_CTRL_DMA0MODE_MASK                   0x30000UL                                  /**< Bit mask for CRYPTO_DMA0MODE */
+#define _CRYPTO_CTRL_DMA0MODE_DEFAULT                0x00000000UL                               /**< Mode DEFAULT for CRYPTO_CTRL */
+#define _CRYPTO_CTRL_DMA0MODE_FULL                   0x00000000UL                               /**< Mode FULL for CRYPTO_CTRL */
+#define _CRYPTO_CTRL_DMA0MODE_LENLIMIT               0x00000001UL                               /**< Mode LENLIMIT for CRYPTO_CTRL */
+#define _CRYPTO_CTRL_DMA0MODE_FULLBYTE               0x00000002UL                               /**< Mode FULLBYTE for CRYPTO_CTRL */
+#define _CRYPTO_CTRL_DMA0MODE_LENLIMITBYTE           0x00000003UL                               /**< Mode LENLIMITBYTE for CRYPTO_CTRL */
+#define CRYPTO_CTRL_DMA0MODE_DEFAULT                 (_CRYPTO_CTRL_DMA0MODE_DEFAULT << 16)      /**< Shifted mode DEFAULT for CRYPTO_CTRL */
+#define CRYPTO_CTRL_DMA0MODE_FULL                    (_CRYPTO_CTRL_DMA0MODE_FULL << 16)         /**< Shifted mode FULL for CRYPTO_CTRL */
+#define CRYPTO_CTRL_DMA0MODE_LENLIMIT                (_CRYPTO_CTRL_DMA0MODE_LENLIMIT << 16)     /**< Shifted mode LENLIMIT for CRYPTO_CTRL */
+#define CRYPTO_CTRL_DMA0MODE_FULLBYTE                (_CRYPTO_CTRL_DMA0MODE_FULLBYTE << 16)     /**< Shifted mode FULLBYTE for CRYPTO_CTRL */
+#define CRYPTO_CTRL_DMA0MODE_LENLIMITBYTE            (_CRYPTO_CTRL_DMA0MODE_LENLIMITBYTE << 16) /**< Shifted mode LENLIMITBYTE for CRYPTO_CTRL */
+#define _CRYPTO_CTRL_DMA0RSEL_SHIFT                  20                                         /**< Shift value for CRYPTO_DMA0RSEL */
+#define _CRYPTO_CTRL_DMA0RSEL_MASK                   0x300000UL                                 /**< Bit mask for CRYPTO_DMA0RSEL */
+#define _CRYPTO_CTRL_DMA0RSEL_DEFAULT                0x00000000UL                               /**< Mode DEFAULT for CRYPTO_CTRL */
+#define _CRYPTO_CTRL_DMA0RSEL_DATA0                  0x00000000UL                               /**< Mode DATA0 for CRYPTO_CTRL */
+#define _CRYPTO_CTRL_DMA0RSEL_DDATA0                 0x00000001UL                               /**< Mode DDATA0 for CRYPTO_CTRL */
+#define _CRYPTO_CTRL_DMA0RSEL_DDATA0BIG              0x00000002UL                               /**< Mode DDATA0BIG for CRYPTO_CTRL */
+#define _CRYPTO_CTRL_DMA0RSEL_QDATA0                 0x00000003UL                               /**< Mode QDATA0 for CRYPTO_CTRL */
+#define CRYPTO_CTRL_DMA0RSEL_DEFAULT                 (_CRYPTO_CTRL_DMA0RSEL_DEFAULT << 20)      /**< Shifted mode DEFAULT for CRYPTO_CTRL */
+#define CRYPTO_CTRL_DMA0RSEL_DATA0                   (_CRYPTO_CTRL_DMA0RSEL_DATA0 << 20)        /**< Shifted mode DATA0 for CRYPTO_CTRL */
+#define CRYPTO_CTRL_DMA0RSEL_DDATA0                  (_CRYPTO_CTRL_DMA0RSEL_DDATA0 << 20)       /**< Shifted mode DDATA0 for CRYPTO_CTRL */
+#define CRYPTO_CTRL_DMA0RSEL_DDATA0BIG               (_CRYPTO_CTRL_DMA0RSEL_DDATA0BIG << 20)    /**< Shifted mode DDATA0BIG for CRYPTO_CTRL */
+#define CRYPTO_CTRL_DMA0RSEL_QDATA0                  (_CRYPTO_CTRL_DMA0RSEL_QDATA0 << 20)       /**< Shifted mode QDATA0 for CRYPTO_CTRL */
+#define _CRYPTO_CTRL_DMA1MODE_SHIFT                  24                                         /**< Shift value for CRYPTO_DMA1MODE */
+#define _CRYPTO_CTRL_DMA1MODE_MASK                   0x3000000UL                                /**< Bit mask for CRYPTO_DMA1MODE */
+#define _CRYPTO_CTRL_DMA1MODE_DEFAULT                0x00000000UL                               /**< Mode DEFAULT for CRYPTO_CTRL */
+#define _CRYPTO_CTRL_DMA1MODE_FULL                   0x00000000UL                               /**< Mode FULL for CRYPTO_CTRL */
+#define _CRYPTO_CTRL_DMA1MODE_LENLIMIT               0x00000001UL                               /**< Mode LENLIMIT for CRYPTO_CTRL */
+#define _CRYPTO_CTRL_DMA1MODE_FULLBYTE               0x00000002UL                               /**< Mode FULLBYTE for CRYPTO_CTRL */
+#define _CRYPTO_CTRL_DMA1MODE_LENLIMITBYTE           0x00000003UL                               /**< Mode LENLIMITBYTE for CRYPTO_CTRL */
+#define CRYPTO_CTRL_DMA1MODE_DEFAULT                 (_CRYPTO_CTRL_DMA1MODE_DEFAULT << 24)      /**< Shifted mode DEFAULT for CRYPTO_CTRL */
+#define CRYPTO_CTRL_DMA1MODE_FULL                    (_CRYPTO_CTRL_DMA1MODE_FULL << 24)         /**< Shifted mode FULL for CRYPTO_CTRL */
+#define CRYPTO_CTRL_DMA1MODE_LENLIMIT                (_CRYPTO_CTRL_DMA1MODE_LENLIMIT << 24)     /**< Shifted mode LENLIMIT for CRYPTO_CTRL */
+#define CRYPTO_CTRL_DMA1MODE_FULLBYTE                (_CRYPTO_CTRL_DMA1MODE_FULLBYTE << 24)     /**< Shifted mode FULLBYTE for CRYPTO_CTRL */
+#define CRYPTO_CTRL_DMA1MODE_LENLIMITBYTE            (_CRYPTO_CTRL_DMA1MODE_LENLIMITBYTE << 24) /**< Shifted mode LENLIMITBYTE for CRYPTO_CTRL */
+#define _CRYPTO_CTRL_DMA1RSEL_SHIFT                  28                                         /**< Shift value for CRYPTO_DMA1RSEL */
+#define _CRYPTO_CTRL_DMA1RSEL_MASK                   0x30000000UL                               /**< Bit mask for CRYPTO_DMA1RSEL */
+#define _CRYPTO_CTRL_DMA1RSEL_DEFAULT                0x00000000UL                               /**< Mode DEFAULT for CRYPTO_CTRL */
+#define _CRYPTO_CTRL_DMA1RSEL_DATA1                  0x00000000UL                               /**< Mode DATA1 for CRYPTO_CTRL */
+#define _CRYPTO_CTRL_DMA1RSEL_DDATA1                 0x00000001UL                               /**< Mode DDATA1 for CRYPTO_CTRL */
+#define _CRYPTO_CTRL_DMA1RSEL_QDATA1                 0x00000002UL                               /**< Mode QDATA1 for CRYPTO_CTRL */
+#define _CRYPTO_CTRL_DMA1RSEL_QDATA1BIG              0x00000003UL                               /**< Mode QDATA1BIG for CRYPTO_CTRL */
+#define CRYPTO_CTRL_DMA1RSEL_DEFAULT                 (_CRYPTO_CTRL_DMA1RSEL_DEFAULT << 28)      /**< Shifted mode DEFAULT for CRYPTO_CTRL */
+#define CRYPTO_CTRL_DMA1RSEL_DATA1                   (_CRYPTO_CTRL_DMA1RSEL_DATA1 << 28)        /**< Shifted mode DATA1 for CRYPTO_CTRL */
+#define CRYPTO_CTRL_DMA1RSEL_DDATA1                  (_CRYPTO_CTRL_DMA1RSEL_DDATA1 << 28)       /**< Shifted mode DDATA1 for CRYPTO_CTRL */
+#define CRYPTO_CTRL_DMA1RSEL_QDATA1                  (_CRYPTO_CTRL_DMA1RSEL_QDATA1 << 28)       /**< Shifted mode QDATA1 for CRYPTO_CTRL */
+#define CRYPTO_CTRL_DMA1RSEL_QDATA1BIG               (_CRYPTO_CTRL_DMA1RSEL_QDATA1BIG << 28)    /**< Shifted mode QDATA1BIG for CRYPTO_CTRL */
+#define CRYPTO_CTRL_COMBDMA0WEREQ                    (0x1UL << 31)                              /**< Combined Data0 Write DMA Request */
+#define _CRYPTO_CTRL_COMBDMA0WEREQ_SHIFT             31                                         /**< Shift value for CRYPTO_COMBDMA0WEREQ */
+#define _CRYPTO_CTRL_COMBDMA0WEREQ_MASK              0x80000000UL                               /**< Bit mask for CRYPTO_COMBDMA0WEREQ */
+#define _CRYPTO_CTRL_COMBDMA0WEREQ_DEFAULT           0x00000000UL                               /**< Mode DEFAULT for CRYPTO_CTRL */
+#define CRYPTO_CTRL_COMBDMA0WEREQ_DEFAULT            (_CRYPTO_CTRL_COMBDMA0WEREQ_DEFAULT << 31) /**< Shifted mode DEFAULT for CRYPTO_CTRL */
+
+/* Bit fields for CRYPTO WAC */
+#define _CRYPTO_WAC_RESETVALUE                       0x00000000UL                            /**< Default value for CRYPTO_WAC */
+#define _CRYPTO_WAC_MASK                             0x00000F1FUL                            /**< Mask for CRYPTO_WAC */
+#define _CRYPTO_WAC_MODULUS_SHIFT                    0                                       /**< Shift value for CRYPTO_MODULUS */
+#define _CRYPTO_WAC_MODULUS_MASK                     0xFUL                                   /**< Bit mask for CRYPTO_MODULUS */
+#define _CRYPTO_WAC_MODULUS_DEFAULT                  0x00000000UL                            /**< Mode DEFAULT for CRYPTO_WAC */
+#define _CRYPTO_WAC_MODULUS_BIN256                   0x00000000UL                            /**< Mode BIN256 for CRYPTO_WAC */
+#define _CRYPTO_WAC_MODULUS_BIN128                   0x00000001UL                            /**< Mode BIN128 for CRYPTO_WAC */
+#define _CRYPTO_WAC_MODULUS_ECCBIN233P               0x00000002UL                            /**< Mode ECCBIN233P for CRYPTO_WAC */
+#define _CRYPTO_WAC_MODULUS_ECCBIN163P               0x00000003UL                            /**< Mode ECCBIN163P for CRYPTO_WAC */
+#define _CRYPTO_WAC_MODULUS_GCMBIN128                0x00000004UL                            /**< Mode GCMBIN128 for CRYPTO_WAC */
+#define _CRYPTO_WAC_MODULUS_ECCPRIME256P             0x00000005UL                            /**< Mode ECCPRIME256P for CRYPTO_WAC */
+#define _CRYPTO_WAC_MODULUS_ECCPRIME224P             0x00000006UL                            /**< Mode ECCPRIME224P for CRYPTO_WAC */
+#define _CRYPTO_WAC_MODULUS_ECCPRIME192P             0x00000007UL                            /**< Mode ECCPRIME192P for CRYPTO_WAC */
+#define _CRYPTO_WAC_MODULUS_ECCBIN233N               0x00000008UL                            /**< Mode ECCBIN233N for CRYPTO_WAC */
+#define _CRYPTO_WAC_MODULUS_ECCBIN233KN              0x00000009UL                            /**< Mode ECCBIN233KN for CRYPTO_WAC */
+#define _CRYPTO_WAC_MODULUS_ECCBIN163N               0x0000000AUL                            /**< Mode ECCBIN163N for CRYPTO_WAC */
+#define _CRYPTO_WAC_MODULUS_ECCBIN163KN              0x0000000BUL                            /**< Mode ECCBIN163KN for CRYPTO_WAC */
+#define _CRYPTO_WAC_MODULUS_ECCPRIME256N             0x0000000CUL                            /**< Mode ECCPRIME256N for CRYPTO_WAC */
+#define _CRYPTO_WAC_MODULUS_ECCPRIME224N             0x0000000DUL                            /**< Mode ECCPRIME224N for CRYPTO_WAC */
+#define _CRYPTO_WAC_MODULUS_ECCPRIME192N             0x0000000EUL                            /**< Mode ECCPRIME192N for CRYPTO_WAC */
+#define CRYPTO_WAC_MODULUS_DEFAULT                   (_CRYPTO_WAC_MODULUS_DEFAULT << 0)      /**< Shifted mode DEFAULT for CRYPTO_WAC */
+#define CRYPTO_WAC_MODULUS_BIN256                    (_CRYPTO_WAC_MODULUS_BIN256 << 0)       /**< Shifted mode BIN256 for CRYPTO_WAC */
+#define CRYPTO_WAC_MODULUS_BIN128                    (_CRYPTO_WAC_MODULUS_BIN128 << 0)       /**< Shifted mode BIN128 for CRYPTO_WAC */
+#define CRYPTO_WAC_MODULUS_ECCBIN233P                (_CRYPTO_WAC_MODULUS_ECCBIN233P << 0)   /**< Shifted mode ECCBIN233P for CRYPTO_WAC */
+#define CRYPTO_WAC_MODULUS_ECCBIN163P                (_CRYPTO_WAC_MODULUS_ECCBIN163P << 0)   /**< Shifted mode ECCBIN163P for CRYPTO_WAC */
+#define CRYPTO_WAC_MODULUS_GCMBIN128                 (_CRYPTO_WAC_MODULUS_GCMBIN128 << 0)    /**< Shifted mode GCMBIN128 for CRYPTO_WAC */
+#define CRYPTO_WAC_MODULUS_ECCPRIME256P              (_CRYPTO_WAC_MODULUS_ECCPRIME256P << 0) /**< Shifted mode ECCPRIME256P for CRYPTO_WAC */
+#define CRYPTO_WAC_MODULUS_ECCPRIME224P              (_CRYPTO_WAC_MODULUS_ECCPRIME224P << 0) /**< Shifted mode ECCPRIME224P for CRYPTO_WAC */
+#define CRYPTO_WAC_MODULUS_ECCPRIME192P              (_CRYPTO_WAC_MODULUS_ECCPRIME192P << 0) /**< Shifted mode ECCPRIME192P for CRYPTO_WAC */
+#define CRYPTO_WAC_MODULUS_ECCBIN233N                (_CRYPTO_WAC_MODULUS_ECCBIN233N << 0)   /**< Shifted mode ECCBIN233N for CRYPTO_WAC */
+#define CRYPTO_WAC_MODULUS_ECCBIN233KN               (_CRYPTO_WAC_MODULUS_ECCBIN233KN << 0)  /**< Shifted mode ECCBIN233KN for CRYPTO_WAC */
+#define CRYPTO_WAC_MODULUS_ECCBIN163N                (_CRYPTO_WAC_MODULUS_ECCBIN163N << 0)   /**< Shifted mode ECCBIN163N for CRYPTO_WAC */
+#define CRYPTO_WAC_MODULUS_ECCBIN163KN               (_CRYPTO_WAC_MODULUS_ECCBIN163KN << 0)  /**< Shifted mode ECCBIN163KN for CRYPTO_WAC */
+#define CRYPTO_WAC_MODULUS_ECCPRIME256N              (_CRYPTO_WAC_MODULUS_ECCPRIME256N << 0) /**< Shifted mode ECCPRIME256N for CRYPTO_WAC */
+#define CRYPTO_WAC_MODULUS_ECCPRIME224N              (_CRYPTO_WAC_MODULUS_ECCPRIME224N << 0) /**< Shifted mode ECCPRIME224N for CRYPTO_WAC */
+#define CRYPTO_WAC_MODULUS_ECCPRIME192N              (_CRYPTO_WAC_MODULUS_ECCPRIME192N << 0) /**< Shifted mode ECCPRIME192N for CRYPTO_WAC */
+#define CRYPTO_WAC_MODOP                             (0x1UL << 4)                            /**< Modular Operation Field Type */
+#define _CRYPTO_WAC_MODOP_SHIFT                      4                                       /**< Shift value for CRYPTO_MODOP */
+#define _CRYPTO_WAC_MODOP_MASK                       0x10UL                                  /**< Bit mask for CRYPTO_MODOP */
+#define _CRYPTO_WAC_MODOP_DEFAULT                    0x00000000UL                            /**< Mode DEFAULT for CRYPTO_WAC */
+#define _CRYPTO_WAC_MODOP_BINARY                     0x00000000UL                            /**< Mode BINARY for CRYPTO_WAC */
+#define _CRYPTO_WAC_MODOP_REGULAR                    0x00000001UL                            /**< Mode REGULAR for CRYPTO_WAC */
+#define CRYPTO_WAC_MODOP_DEFAULT                     (_CRYPTO_WAC_MODOP_DEFAULT << 4)        /**< Shifted mode DEFAULT for CRYPTO_WAC */
+#define CRYPTO_WAC_MODOP_BINARY                      (_CRYPTO_WAC_MODOP_BINARY << 4)         /**< Shifted mode BINARY for CRYPTO_WAC */
+#define CRYPTO_WAC_MODOP_REGULAR                     (_CRYPTO_WAC_MODOP_REGULAR << 4)        /**< Shifted mode REGULAR for CRYPTO_WAC */
+#define _CRYPTO_WAC_MULWIDTH_SHIFT                   8                                       /**< Shift value for CRYPTO_MULWIDTH */
+#define _CRYPTO_WAC_MULWIDTH_MASK                    0x300UL                                 /**< Bit mask for CRYPTO_MULWIDTH */
+#define _CRYPTO_WAC_MULWIDTH_DEFAULT                 0x00000000UL                            /**< Mode DEFAULT for CRYPTO_WAC */
+#define _CRYPTO_WAC_MULWIDTH_MUL256                  0x00000000UL                            /**< Mode MUL256 for CRYPTO_WAC */
+#define _CRYPTO_WAC_MULWIDTH_MUL128                  0x00000001UL                            /**< Mode MUL128 for CRYPTO_WAC */
+#define _CRYPTO_WAC_MULWIDTH_MULMOD                  0x00000002UL                            /**< Mode MULMOD for CRYPTO_WAC */
+#define CRYPTO_WAC_MULWIDTH_DEFAULT                  (_CRYPTO_WAC_MULWIDTH_DEFAULT << 8)     /**< Shifted mode DEFAULT for CRYPTO_WAC */
+#define CRYPTO_WAC_MULWIDTH_MUL256                   (_CRYPTO_WAC_MULWIDTH_MUL256 << 8)      /**< Shifted mode MUL256 for CRYPTO_WAC */
+#define CRYPTO_WAC_MULWIDTH_MUL128                   (_CRYPTO_WAC_MULWIDTH_MUL128 << 8)      /**< Shifted mode MUL128 for CRYPTO_WAC */
+#define CRYPTO_WAC_MULWIDTH_MULMOD                   (_CRYPTO_WAC_MULWIDTH_MULMOD << 8)      /**< Shifted mode MULMOD for CRYPTO_WAC */
+#define _CRYPTO_WAC_RESULTWIDTH_SHIFT                10                                      /**< Shift value for CRYPTO_RESULTWIDTH */
+#define _CRYPTO_WAC_RESULTWIDTH_MASK                 0xC00UL                                 /**< Bit mask for CRYPTO_RESULTWIDTH */
+#define _CRYPTO_WAC_RESULTWIDTH_DEFAULT              0x00000000UL                            /**< Mode DEFAULT for CRYPTO_WAC */
+#define _CRYPTO_WAC_RESULTWIDTH_256BIT               0x00000000UL                            /**< Mode 256BIT for CRYPTO_WAC */
+#define _CRYPTO_WAC_RESULTWIDTH_128BIT               0x00000001UL                            /**< Mode 128BIT for CRYPTO_WAC */
+#define _CRYPTO_WAC_RESULTWIDTH_260BIT               0x00000002UL                            /**< Mode 260BIT for CRYPTO_WAC */
+#define CRYPTO_WAC_RESULTWIDTH_DEFAULT               (_CRYPTO_WAC_RESULTWIDTH_DEFAULT << 10) /**< Shifted mode DEFAULT for CRYPTO_WAC */
+#define CRYPTO_WAC_RESULTWIDTH_256BIT                (_CRYPTO_WAC_RESULTWIDTH_256BIT << 10)  /**< Shifted mode 256BIT for CRYPTO_WAC */
+#define CRYPTO_WAC_RESULTWIDTH_128BIT                (_CRYPTO_WAC_RESULTWIDTH_128BIT << 10)  /**< Shifted mode 128BIT for CRYPTO_WAC */
+#define CRYPTO_WAC_RESULTWIDTH_260BIT                (_CRYPTO_WAC_RESULTWIDTH_260BIT << 10)  /**< Shifted mode 260BIT for CRYPTO_WAC */
+
+/* Bit fields for CRYPTO CMD */
+#define _CRYPTO_CMD_RESETVALUE                       0x00000000UL                                /**< Default value for CRYPTO_CMD */
+#define _CRYPTO_CMD_MASK                             0x00000EFFUL                                /**< Mask for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SHIFT                      0                                           /**< Shift value for CRYPTO_INSTR */
+#define _CRYPTO_CMD_INSTR_MASK                       0xFFUL                                      /**< Bit mask for CRYPTO_INSTR */
+#define _CRYPTO_CMD_INSTR_DEFAULT                    0x00000000UL                                /**< Mode DEFAULT for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_END                        0x00000000UL                                /**< Mode END for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_EXEC                       0x00000001UL                                /**< Mode EXEC for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DATA1INC                   0x00000003UL                                /**< Mode DATA1INC for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DATA1INCCLR                0x00000004UL                                /**< Mode DATA1INCCLR for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_AESENC                     0x00000005UL                                /**< Mode AESENC for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_AESDEC                     0x00000006UL                                /**< Mode AESDEC for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SHA                        0x00000007UL                                /**< Mode SHA for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_ADD                        0x00000008UL                                /**< Mode ADD for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_ADDC                       0x00000009UL                                /**< Mode ADDC for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_MADD                       0x0000000CUL                                /**< Mode MADD for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_MADD32                     0x0000000DUL                                /**< Mode MADD32 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SUB                        0x00000010UL                                /**< Mode SUB for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SUBC                       0x00000011UL                                /**< Mode SUBC for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_MSUB                       0x00000014UL                                /**< Mode MSUB for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_MUL                        0x00000018UL                                /**< Mode MUL for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_MULC                       0x00000019UL                                /**< Mode MULC for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_MMUL                       0x0000001CUL                                /**< Mode MMUL for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_MULO                       0x0000001DUL                                /**< Mode MULO for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SHL                        0x00000020UL                                /**< Mode SHL for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SHLC                       0x00000021UL                                /**< Mode SHLC for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SHLB                       0x00000022UL                                /**< Mode SHLB for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SHL1                       0x00000023UL                                /**< Mode SHL1 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SHR                        0x00000024UL                                /**< Mode SHR for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SHRC                       0x00000025UL                                /**< Mode SHRC for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SHRB                       0x00000026UL                                /**< Mode SHRB for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SHR1                       0x00000027UL                                /**< Mode SHR1 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_ADDO                       0x00000028UL                                /**< Mode ADDO for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_ADDIC                      0x00000029UL                                /**< Mode ADDIC for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_CLR                        0x00000030UL                                /**< Mode CLR for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_XOR                        0x00000031UL                                /**< Mode XOR for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_INV                        0x00000032UL                                /**< Mode INV for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_CSET                       0x00000034UL                                /**< Mode CSET for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_CCLR                       0x00000035UL                                /**< Mode CCLR for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_BBSWAP128                  0x00000036UL                                /**< Mode BBSWAP128 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_INC                        0x00000038UL                                /**< Mode INC for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DEC                        0x00000039UL                                /**< Mode DEC for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SHRA                       0x0000003EUL                                /**< Mode SHRA for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DATA0TODATA0               0x00000040UL                                /**< Mode DATA0TODATA0 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DATA0TODATA0XOR            0x00000041UL                                /**< Mode DATA0TODATA0XOR for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DATA0TODATA0XORLEN         0x00000042UL                                /**< Mode DATA0TODATA0XORLEN for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DATA0TODATA1               0x00000044UL                                /**< Mode DATA0TODATA1 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DATA0TODATA2               0x00000045UL                                /**< Mode DATA0TODATA2 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DATA0TODATA3               0x00000046UL                                /**< Mode DATA0TODATA3 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DATA1TODATA0               0x00000048UL                                /**< Mode DATA1TODATA0 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DATA1TODATA0XOR            0x00000049UL                                /**< Mode DATA1TODATA0XOR for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DATA1TODATA0XORLEN         0x0000004AUL                                /**< Mode DATA1TODATA0XORLEN for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DATA1TODATA2               0x0000004DUL                                /**< Mode DATA1TODATA2 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DATA1TODATA3               0x0000004EUL                                /**< Mode DATA1TODATA3 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DATA2TODATA0               0x00000050UL                                /**< Mode DATA2TODATA0 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DATA2TODATA0XOR            0x00000051UL                                /**< Mode DATA2TODATA0XOR for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DATA2TODATA0XORLEN         0x00000052UL                                /**< Mode DATA2TODATA0XORLEN for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DATA2TODATA1               0x00000054UL                                /**< Mode DATA2TODATA1 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DATA2TODATA3               0x00000056UL                                /**< Mode DATA2TODATA3 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DATA3TODATA0               0x00000058UL                                /**< Mode DATA3TODATA0 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DATA3TODATA0XOR            0x00000059UL                                /**< Mode DATA3TODATA0XOR for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DATA3TODATA0XORLEN         0x0000005AUL                                /**< Mode DATA3TODATA0XORLEN for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DATA3TODATA1               0x0000005CUL                                /**< Mode DATA3TODATA1 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DATA3TODATA2               0x0000005DUL                                /**< Mode DATA3TODATA2 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DATATODMA0                 0x00000063UL                                /**< Mode DATATODMA0 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DATA0TOBUF                 0x00000064UL                                /**< Mode DATA0TOBUF for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DATA0TOBUFXOR              0x00000065UL                                /**< Mode DATA0TOBUFXOR for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DATATODMA1                 0x0000006BUL                                /**< Mode DATATODMA1 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DATA1TOBUF                 0x0000006CUL                                /**< Mode DATA1TOBUF for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DATA1TOBUFXOR              0x0000006DUL                                /**< Mode DATA1TOBUFXOR for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DMA0TODATA                 0x00000070UL                                /**< Mode DMA0TODATA for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DMA0TODATAXOR              0x00000071UL                                /**< Mode DMA0TODATAXOR for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DMA1TODATA                 0x00000072UL                                /**< Mode DMA1TODATA for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_BUFTODATA0                 0x00000078UL                                /**< Mode BUFTODATA0 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_BUFTODATA0XOR              0x00000079UL                                /**< Mode BUFTODATA0XOR for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_BUFTODATA1                 0x0000007AUL                                /**< Mode BUFTODATA1 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DDATA0TODDATA1             0x00000081UL                                /**< Mode DDATA0TODDATA1 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DDATA0TODDATA2             0x00000082UL                                /**< Mode DDATA0TODDATA2 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DDATA0TODDATA3             0x00000083UL                                /**< Mode DDATA0TODDATA3 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DDATA0TODDATA4             0x00000084UL                                /**< Mode DDATA0TODDATA4 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DDATA0LTODATA0             0x00000085UL                                /**< Mode DDATA0LTODATA0 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DDATA0HTODATA1             0x00000086UL                                /**< Mode DDATA0HTODATA1 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DDATA0LTODATA2             0x00000087UL                                /**< Mode DDATA0LTODATA2 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DDATA1TODDATA0             0x00000088UL                                /**< Mode DDATA1TODDATA0 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DDATA1TODDATA2             0x0000008AUL                                /**< Mode DDATA1TODDATA2 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DDATA1TODDATA3             0x0000008BUL                                /**< Mode DDATA1TODDATA3 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DDATA1TODDATA4             0x0000008CUL                                /**< Mode DDATA1TODDATA4 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DDATA1LTODATA0             0x0000008DUL                                /**< Mode DDATA1LTODATA0 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DDATA1HTODATA1             0x0000008EUL                                /**< Mode DDATA1HTODATA1 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DDATA1LTODATA2             0x0000008FUL                                /**< Mode DDATA1LTODATA2 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DDATA2TODDATA0             0x00000090UL                                /**< Mode DDATA2TODDATA0 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DDATA2TODDATA1             0x00000091UL                                /**< Mode DDATA2TODDATA1 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DDATA2TODDATA3             0x00000093UL                                /**< Mode DDATA2TODDATA3 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DDATA2TODDATA4             0x00000094UL                                /**< Mode DDATA2TODDATA4 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DDATA2LTODATA2             0x00000097UL                                /**< Mode DDATA2LTODATA2 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DDATA3TODDATA0             0x00000098UL                                /**< Mode DDATA3TODDATA0 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DDATA3TODDATA1             0x00000099UL                                /**< Mode DDATA3TODDATA1 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DDATA3TODDATA2             0x0000009AUL                                /**< Mode DDATA3TODDATA2 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DDATA3TODDATA4             0x0000009CUL                                /**< Mode DDATA3TODDATA4 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DDATA3LTODATA0             0x0000009DUL                                /**< Mode DDATA3LTODATA0 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DDATA3HTODATA1             0x0000009EUL                                /**< Mode DDATA3HTODATA1 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DDATA4TODDATA0             0x000000A0UL                                /**< Mode DDATA4TODDATA0 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DDATA4TODDATA1             0x000000A1UL                                /**< Mode DDATA4TODDATA1 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DDATA4TODDATA2             0x000000A2UL                                /**< Mode DDATA4TODDATA2 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DDATA4TODDATA3             0x000000A3UL                                /**< Mode DDATA4TODDATA3 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DDATA4LTODATA0             0x000000A5UL                                /**< Mode DDATA4LTODATA0 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DDATA4HTODATA1             0x000000A6UL                                /**< Mode DDATA4HTODATA1 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DDATA4LTODATA2             0x000000A7UL                                /**< Mode DDATA4LTODATA2 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DATA0TODDATA0              0x000000A8UL                                /**< Mode DATA0TODDATA0 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DATA0TODDATA1              0x000000A9UL                                /**< Mode DATA0TODDATA1 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DATA1TODDATA0              0x000000B0UL                                /**< Mode DATA1TODDATA0 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DATA1TODDATA1              0x000000B1UL                                /**< Mode DATA1TODDATA1 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DATA2TODDATA0              0x000000B8UL                                /**< Mode DATA2TODDATA0 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DATA2TODDATA1              0x000000B9UL                                /**< Mode DATA2TODDATA1 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DATA2TODDATA2              0x000000BAUL                                /**< Mode DATA2TODDATA2 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDDATA0DDATA0            0x000000C0UL                                /**< Mode SELDDATA0DDATA0 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDDATA1DDATA0            0x000000C1UL                                /**< Mode SELDDATA1DDATA0 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDDATA2DDATA0            0x000000C2UL                                /**< Mode SELDDATA2DDATA0 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDDATA3DDATA0            0x000000C3UL                                /**< Mode SELDDATA3DDATA0 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDDATA4DDATA0            0x000000C4UL                                /**< Mode SELDDATA4DDATA0 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDATA0DDATA0             0x000000C5UL                                /**< Mode SELDATA0DDATA0 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDATA1DDATA0             0x000000C6UL                                /**< Mode SELDATA1DDATA0 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDATA2DDATA0             0x000000C7UL                                /**< Mode SELDATA2DDATA0 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDDATA0DDATA1            0x000000C8UL                                /**< Mode SELDDATA0DDATA1 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDDATA1DDATA1            0x000000C9UL                                /**< Mode SELDDATA1DDATA1 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDDATA2DDATA1            0x000000CAUL                                /**< Mode SELDDATA2DDATA1 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDDATA3DDATA1            0x000000CBUL                                /**< Mode SELDDATA3DDATA1 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDDATA4DDATA1            0x000000CCUL                                /**< Mode SELDDATA4DDATA1 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDATA0DDATA1             0x000000CDUL                                /**< Mode SELDATA0DDATA1 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDATA1DDATA1             0x000000CEUL                                /**< Mode SELDATA1DDATA1 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDATA2DDATA1             0x000000CFUL                                /**< Mode SELDATA2DDATA1 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDDATA0DDATA2            0x000000D0UL                                /**< Mode SELDDATA0DDATA2 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDDATA1DDATA2            0x000000D1UL                                /**< Mode SELDDATA1DDATA2 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDDATA2DDATA2            0x000000D2UL                                /**< Mode SELDDATA2DDATA2 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDDATA3DDATA2            0x000000D3UL                                /**< Mode SELDDATA3DDATA2 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDDATA4DDATA2            0x000000D4UL                                /**< Mode SELDDATA4DDATA2 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDATA0DDATA2             0x000000D5UL                                /**< Mode SELDATA0DDATA2 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDATA1DDATA2             0x000000D6UL                                /**< Mode SELDATA1DDATA2 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDATA2DDATA2             0x000000D7UL                                /**< Mode SELDATA2DDATA2 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDDATA0DDATA3            0x000000D8UL                                /**< Mode SELDDATA0DDATA3 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDDATA1DDATA3            0x000000D9UL                                /**< Mode SELDDATA1DDATA3 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDDATA2DDATA3            0x000000DAUL                                /**< Mode SELDDATA2DDATA3 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDDATA3DDATA3            0x000000DBUL                                /**< Mode SELDDATA3DDATA3 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDDATA4DDATA3            0x000000DCUL                                /**< Mode SELDDATA4DDATA3 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDATA0DDATA3             0x000000DDUL                                /**< Mode SELDATA0DDATA3 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDATA1DDATA3             0x000000DEUL                                /**< Mode SELDATA1DDATA3 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDATA2DDATA3             0x000000DFUL                                /**< Mode SELDATA2DDATA3 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDDATA0DDATA4            0x000000E0UL                                /**< Mode SELDDATA0DDATA4 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDDATA1DDATA4            0x000000E1UL                                /**< Mode SELDDATA1DDATA4 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDDATA2DDATA4            0x000000E2UL                                /**< Mode SELDDATA2DDATA4 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDDATA3DDATA4            0x000000E3UL                                /**< Mode SELDDATA3DDATA4 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDDATA4DDATA4            0x000000E4UL                                /**< Mode SELDDATA4DDATA4 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDATA0DDATA4             0x000000E5UL                                /**< Mode SELDATA0DDATA4 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDATA1DDATA4             0x000000E6UL                                /**< Mode SELDATA1DDATA4 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDATA2DDATA4             0x000000E7UL                                /**< Mode SELDATA2DDATA4 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDDATA0DATA0             0x000000E8UL                                /**< Mode SELDDATA0DATA0 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDDATA1DATA0             0x000000E9UL                                /**< Mode SELDDATA1DATA0 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDDATA2DATA0             0x000000EAUL                                /**< Mode SELDDATA2DATA0 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDDATA3DATA0             0x000000EBUL                                /**< Mode SELDDATA3DATA0 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDDATA4DATA0             0x000000ECUL                                /**< Mode SELDDATA4DATA0 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDATA0DATA0              0x000000EDUL                                /**< Mode SELDATA0DATA0 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDATA1DATA0              0x000000EEUL                                /**< Mode SELDATA1DATA0 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDATA2DATA0              0x000000EFUL                                /**< Mode SELDATA2DATA0 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDDATA0DATA1             0x000000F0UL                                /**< Mode SELDDATA0DATA1 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDDATA1DATA1             0x000000F1UL                                /**< Mode SELDDATA1DATA1 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDDATA2DATA1             0x000000F2UL                                /**< Mode SELDDATA2DATA1 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDDATA3DATA1             0x000000F3UL                                /**< Mode SELDDATA3DATA1 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDDATA4DATA1             0x000000F4UL                                /**< Mode SELDDATA4DATA1 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDATA0DATA1              0x000000F5UL                                /**< Mode SELDATA0DATA1 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDATA1DATA1              0x000000F6UL                                /**< Mode SELDATA1DATA1 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDATA2DATA1              0x000000F7UL                                /**< Mode SELDATA2DATA1 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_EXECIFA                    0x000000F8UL                                /**< Mode EXECIFA for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_EXECIFB                    0x000000F9UL                                /**< Mode EXECIFB for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_EXECIFNLAST                0x000000FAUL                                /**< Mode EXECIFNLAST for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_EXECIFLAST                 0x000000FBUL                                /**< Mode EXECIFLAST for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_EXECIFCARRY                0x000000FCUL                                /**< Mode EXECIFCARRY for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_EXECIFNCARRY               0x000000FDUL                                /**< Mode EXECIFNCARRY for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_EXECALWAYS                 0x000000FEUL                                /**< Mode EXECALWAYS for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DEFAULT                     (_CRYPTO_CMD_INSTR_DEFAULT << 0)            /**< Shifted mode DEFAULT for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_END                         (_CRYPTO_CMD_INSTR_END << 0)                /**< Shifted mode END for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_EXEC                        (_CRYPTO_CMD_INSTR_EXEC << 0)               /**< Shifted mode EXEC for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DATA1INC                    (_CRYPTO_CMD_INSTR_DATA1INC << 0)           /**< Shifted mode DATA1INC for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DATA1INCCLR                 (_CRYPTO_CMD_INSTR_DATA1INCCLR << 0)        /**< Shifted mode DATA1INCCLR for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_AESENC                      (_CRYPTO_CMD_INSTR_AESENC << 0)             /**< Shifted mode AESENC for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_AESDEC                      (_CRYPTO_CMD_INSTR_AESDEC << 0)             /**< Shifted mode AESDEC for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SHA                         (_CRYPTO_CMD_INSTR_SHA << 0)                /**< Shifted mode SHA for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_ADD                         (_CRYPTO_CMD_INSTR_ADD << 0)                /**< Shifted mode ADD for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_ADDC                        (_CRYPTO_CMD_INSTR_ADDC << 0)               /**< Shifted mode ADDC for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_MADD                        (_CRYPTO_CMD_INSTR_MADD << 0)               /**< Shifted mode MADD for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_MADD32                      (_CRYPTO_CMD_INSTR_MADD32 << 0)             /**< Shifted mode MADD32 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SUB                         (_CRYPTO_CMD_INSTR_SUB << 0)                /**< Shifted mode SUB for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SUBC                        (_CRYPTO_CMD_INSTR_SUBC << 0)               /**< Shifted mode SUBC for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_MSUB                        (_CRYPTO_CMD_INSTR_MSUB << 0)               /**< Shifted mode MSUB for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_MUL                         (_CRYPTO_CMD_INSTR_MUL << 0)                /**< Shifted mode MUL for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_MULC                        (_CRYPTO_CMD_INSTR_MULC << 0)               /**< Shifted mode MULC for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_MMUL                        (_CRYPTO_CMD_INSTR_MMUL << 0)               /**< Shifted mode MMUL for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_MULO                        (_CRYPTO_CMD_INSTR_MULO << 0)               /**< Shifted mode MULO for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SHL                         (_CRYPTO_CMD_INSTR_SHL << 0)                /**< Shifted mode SHL for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SHLC                        (_CRYPTO_CMD_INSTR_SHLC << 0)               /**< Shifted mode SHLC for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SHLB                        (_CRYPTO_CMD_INSTR_SHLB << 0)               /**< Shifted mode SHLB for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SHL1                        (_CRYPTO_CMD_INSTR_SHL1 << 0)               /**< Shifted mode SHL1 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SHR                         (_CRYPTO_CMD_INSTR_SHR << 0)                /**< Shifted mode SHR for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SHRC                        (_CRYPTO_CMD_INSTR_SHRC << 0)               /**< Shifted mode SHRC for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SHRB                        (_CRYPTO_CMD_INSTR_SHRB << 0)               /**< Shifted mode SHRB for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SHR1                        (_CRYPTO_CMD_INSTR_SHR1 << 0)               /**< Shifted mode SHR1 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_ADDO                        (_CRYPTO_CMD_INSTR_ADDO << 0)               /**< Shifted mode ADDO for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_ADDIC                       (_CRYPTO_CMD_INSTR_ADDIC << 0)              /**< Shifted mode ADDIC for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_CLR                         (_CRYPTO_CMD_INSTR_CLR << 0)                /**< Shifted mode CLR for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_XOR                         (_CRYPTO_CMD_INSTR_XOR << 0)                /**< Shifted mode XOR for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_INV                         (_CRYPTO_CMD_INSTR_INV << 0)                /**< Shifted mode INV for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_CSET                        (_CRYPTO_CMD_INSTR_CSET << 0)               /**< Shifted mode CSET for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_CCLR                        (_CRYPTO_CMD_INSTR_CCLR << 0)               /**< Shifted mode CCLR for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_BBSWAP128                   (_CRYPTO_CMD_INSTR_BBSWAP128 << 0)          /**< Shifted mode BBSWAP128 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_INC                         (_CRYPTO_CMD_INSTR_INC << 0)                /**< Shifted mode INC for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DEC                         (_CRYPTO_CMD_INSTR_DEC << 0)                /**< Shifted mode DEC for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SHRA                        (_CRYPTO_CMD_INSTR_SHRA << 0)               /**< Shifted mode SHRA for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DATA0TODATA0                (_CRYPTO_CMD_INSTR_DATA0TODATA0 << 0)       /**< Shifted mode DATA0TODATA0 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DATA0TODATA0XOR             (_CRYPTO_CMD_INSTR_DATA0TODATA0XOR << 0)    /**< Shifted mode DATA0TODATA0XOR for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DATA0TODATA0XORLEN          (_CRYPTO_CMD_INSTR_DATA0TODATA0XORLEN << 0) /**< Shifted mode DATA0TODATA0XORLEN for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DATA0TODATA1                (_CRYPTO_CMD_INSTR_DATA0TODATA1 << 0)       /**< Shifted mode DATA0TODATA1 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DATA0TODATA2                (_CRYPTO_CMD_INSTR_DATA0TODATA2 << 0)       /**< Shifted mode DATA0TODATA2 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DATA0TODATA3                (_CRYPTO_CMD_INSTR_DATA0TODATA3 << 0)       /**< Shifted mode DATA0TODATA3 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DATA1TODATA0                (_CRYPTO_CMD_INSTR_DATA1TODATA0 << 0)       /**< Shifted mode DATA1TODATA0 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DATA1TODATA0XOR             (_CRYPTO_CMD_INSTR_DATA1TODATA0XOR << 0)    /**< Shifted mode DATA1TODATA0XOR for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DATA1TODATA0XORLEN          (_CRYPTO_CMD_INSTR_DATA1TODATA0XORLEN << 0) /**< Shifted mode DATA1TODATA0XORLEN for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DATA1TODATA2                (_CRYPTO_CMD_INSTR_DATA1TODATA2 << 0)       /**< Shifted mode DATA1TODATA2 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DATA1TODATA3                (_CRYPTO_CMD_INSTR_DATA1TODATA3 << 0)       /**< Shifted mode DATA1TODATA3 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DATA2TODATA0                (_CRYPTO_CMD_INSTR_DATA2TODATA0 << 0)       /**< Shifted mode DATA2TODATA0 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DATA2TODATA0XOR             (_CRYPTO_CMD_INSTR_DATA2TODATA0XOR << 0)    /**< Shifted mode DATA2TODATA0XOR for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DATA2TODATA0XORLEN          (_CRYPTO_CMD_INSTR_DATA2TODATA0XORLEN << 0) /**< Shifted mode DATA2TODATA0XORLEN for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DATA2TODATA1                (_CRYPTO_CMD_INSTR_DATA2TODATA1 << 0)       /**< Shifted mode DATA2TODATA1 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DATA2TODATA3                (_CRYPTO_CMD_INSTR_DATA2TODATA3 << 0)       /**< Shifted mode DATA2TODATA3 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DATA3TODATA0                (_CRYPTO_CMD_INSTR_DATA3TODATA0 << 0)       /**< Shifted mode DATA3TODATA0 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DATA3TODATA0XOR             (_CRYPTO_CMD_INSTR_DATA3TODATA0XOR << 0)    /**< Shifted mode DATA3TODATA0XOR for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DATA3TODATA0XORLEN          (_CRYPTO_CMD_INSTR_DATA3TODATA0XORLEN << 0) /**< Shifted mode DATA3TODATA0XORLEN for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DATA3TODATA1                (_CRYPTO_CMD_INSTR_DATA3TODATA1 << 0)       /**< Shifted mode DATA3TODATA1 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DATA3TODATA2                (_CRYPTO_CMD_INSTR_DATA3TODATA2 << 0)       /**< Shifted mode DATA3TODATA2 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DATATODMA0                  (_CRYPTO_CMD_INSTR_DATATODMA0 << 0)         /**< Shifted mode DATATODMA0 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DATA0TOBUF                  (_CRYPTO_CMD_INSTR_DATA0TOBUF << 0)         /**< Shifted mode DATA0TOBUF for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DATA0TOBUFXOR               (_CRYPTO_CMD_INSTR_DATA0TOBUFXOR << 0)      /**< Shifted mode DATA0TOBUFXOR for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DATATODMA1                  (_CRYPTO_CMD_INSTR_DATATODMA1 << 0)         /**< Shifted mode DATATODMA1 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DATA1TOBUF                  (_CRYPTO_CMD_INSTR_DATA1TOBUF << 0)         /**< Shifted mode DATA1TOBUF for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DATA1TOBUFXOR               (_CRYPTO_CMD_INSTR_DATA1TOBUFXOR << 0)      /**< Shifted mode DATA1TOBUFXOR for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DMA0TODATA                  (_CRYPTO_CMD_INSTR_DMA0TODATA << 0)         /**< Shifted mode DMA0TODATA for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DMA0TODATAXOR               (_CRYPTO_CMD_INSTR_DMA0TODATAXOR << 0)      /**< Shifted mode DMA0TODATAXOR for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DMA1TODATA                  (_CRYPTO_CMD_INSTR_DMA1TODATA << 0)         /**< Shifted mode DMA1TODATA for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_BUFTODATA0                  (_CRYPTO_CMD_INSTR_BUFTODATA0 << 0)         /**< Shifted mode BUFTODATA0 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_BUFTODATA0XOR               (_CRYPTO_CMD_INSTR_BUFTODATA0XOR << 0)      /**< Shifted mode BUFTODATA0XOR for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_BUFTODATA1                  (_CRYPTO_CMD_INSTR_BUFTODATA1 << 0)         /**< Shifted mode BUFTODATA1 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DDATA0TODDATA1              (_CRYPTO_CMD_INSTR_DDATA0TODDATA1 << 0)     /**< Shifted mode DDATA0TODDATA1 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DDATA0TODDATA2              (_CRYPTO_CMD_INSTR_DDATA0TODDATA2 << 0)     /**< Shifted mode DDATA0TODDATA2 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DDATA0TODDATA3              (_CRYPTO_CMD_INSTR_DDATA0TODDATA3 << 0)     /**< Shifted mode DDATA0TODDATA3 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DDATA0TODDATA4              (_CRYPTO_CMD_INSTR_DDATA0TODDATA4 << 0)     /**< Shifted mode DDATA0TODDATA4 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DDATA0LTODATA0              (_CRYPTO_CMD_INSTR_DDATA0LTODATA0 << 0)     /**< Shifted mode DDATA0LTODATA0 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DDATA0HTODATA1              (_CRYPTO_CMD_INSTR_DDATA0HTODATA1 << 0)     /**< Shifted mode DDATA0HTODATA1 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DDATA0LTODATA2              (_CRYPTO_CMD_INSTR_DDATA0LTODATA2 << 0)     /**< Shifted mode DDATA0LTODATA2 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DDATA1TODDATA0              (_CRYPTO_CMD_INSTR_DDATA1TODDATA0 << 0)     /**< Shifted mode DDATA1TODDATA0 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DDATA1TODDATA2              (_CRYPTO_CMD_INSTR_DDATA1TODDATA2 << 0)     /**< Shifted mode DDATA1TODDATA2 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DDATA1TODDATA3              (_CRYPTO_CMD_INSTR_DDATA1TODDATA3 << 0)     /**< Shifted mode DDATA1TODDATA3 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DDATA1TODDATA4              (_CRYPTO_CMD_INSTR_DDATA1TODDATA4 << 0)     /**< Shifted mode DDATA1TODDATA4 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DDATA1LTODATA0              (_CRYPTO_CMD_INSTR_DDATA1LTODATA0 << 0)     /**< Shifted mode DDATA1LTODATA0 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DDATA1HTODATA1              (_CRYPTO_CMD_INSTR_DDATA1HTODATA1 << 0)     /**< Shifted mode DDATA1HTODATA1 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DDATA1LTODATA2              (_CRYPTO_CMD_INSTR_DDATA1LTODATA2 << 0)     /**< Shifted mode DDATA1LTODATA2 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DDATA2TODDATA0              (_CRYPTO_CMD_INSTR_DDATA2TODDATA0 << 0)     /**< Shifted mode DDATA2TODDATA0 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DDATA2TODDATA1              (_CRYPTO_CMD_INSTR_DDATA2TODDATA1 << 0)     /**< Shifted mode DDATA2TODDATA1 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DDATA2TODDATA3              (_CRYPTO_CMD_INSTR_DDATA2TODDATA3 << 0)     /**< Shifted mode DDATA2TODDATA3 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DDATA2TODDATA4              (_CRYPTO_CMD_INSTR_DDATA2TODDATA4 << 0)     /**< Shifted mode DDATA2TODDATA4 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DDATA2LTODATA2              (_CRYPTO_CMD_INSTR_DDATA2LTODATA2 << 0)     /**< Shifted mode DDATA2LTODATA2 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DDATA3TODDATA0              (_CRYPTO_CMD_INSTR_DDATA3TODDATA0 << 0)     /**< Shifted mode DDATA3TODDATA0 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DDATA3TODDATA1              (_CRYPTO_CMD_INSTR_DDATA3TODDATA1 << 0)     /**< Shifted mode DDATA3TODDATA1 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DDATA3TODDATA2              (_CRYPTO_CMD_INSTR_DDATA3TODDATA2 << 0)     /**< Shifted mode DDATA3TODDATA2 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DDATA3TODDATA4              (_CRYPTO_CMD_INSTR_DDATA3TODDATA4 << 0)     /**< Shifted mode DDATA3TODDATA4 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DDATA3LTODATA0              (_CRYPTO_CMD_INSTR_DDATA3LTODATA0 << 0)     /**< Shifted mode DDATA3LTODATA0 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DDATA3HTODATA1              (_CRYPTO_CMD_INSTR_DDATA3HTODATA1 << 0)     /**< Shifted mode DDATA3HTODATA1 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DDATA4TODDATA0              (_CRYPTO_CMD_INSTR_DDATA4TODDATA0 << 0)     /**< Shifted mode DDATA4TODDATA0 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DDATA4TODDATA1              (_CRYPTO_CMD_INSTR_DDATA4TODDATA1 << 0)     /**< Shifted mode DDATA4TODDATA1 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DDATA4TODDATA2              (_CRYPTO_CMD_INSTR_DDATA4TODDATA2 << 0)     /**< Shifted mode DDATA4TODDATA2 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DDATA4TODDATA3              (_CRYPTO_CMD_INSTR_DDATA4TODDATA3 << 0)     /**< Shifted mode DDATA4TODDATA3 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DDATA4LTODATA0              (_CRYPTO_CMD_INSTR_DDATA4LTODATA0 << 0)     /**< Shifted mode DDATA4LTODATA0 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DDATA4HTODATA1              (_CRYPTO_CMD_INSTR_DDATA4HTODATA1 << 0)     /**< Shifted mode DDATA4HTODATA1 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DDATA4LTODATA2              (_CRYPTO_CMD_INSTR_DDATA4LTODATA2 << 0)     /**< Shifted mode DDATA4LTODATA2 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DATA0TODDATA0               (_CRYPTO_CMD_INSTR_DATA0TODDATA0 << 0)      /**< Shifted mode DATA0TODDATA0 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DATA0TODDATA1               (_CRYPTO_CMD_INSTR_DATA0TODDATA1 << 0)      /**< Shifted mode DATA0TODDATA1 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DATA1TODDATA0               (_CRYPTO_CMD_INSTR_DATA1TODDATA0 << 0)      /**< Shifted mode DATA1TODDATA0 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DATA1TODDATA1               (_CRYPTO_CMD_INSTR_DATA1TODDATA1 << 0)      /**< Shifted mode DATA1TODDATA1 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DATA2TODDATA0               (_CRYPTO_CMD_INSTR_DATA2TODDATA0 << 0)      /**< Shifted mode DATA2TODDATA0 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DATA2TODDATA1               (_CRYPTO_CMD_INSTR_DATA2TODDATA1 << 0)      /**< Shifted mode DATA2TODDATA1 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DATA2TODDATA2               (_CRYPTO_CMD_INSTR_DATA2TODDATA2 << 0)      /**< Shifted mode DATA2TODDATA2 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDDATA0DDATA0             (_CRYPTO_CMD_INSTR_SELDDATA0DDATA0 << 0)    /**< Shifted mode SELDDATA0DDATA0 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDDATA1DDATA0             (_CRYPTO_CMD_INSTR_SELDDATA1DDATA0 << 0)    /**< Shifted mode SELDDATA1DDATA0 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDDATA2DDATA0             (_CRYPTO_CMD_INSTR_SELDDATA2DDATA0 << 0)    /**< Shifted mode SELDDATA2DDATA0 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDDATA3DDATA0             (_CRYPTO_CMD_INSTR_SELDDATA3DDATA0 << 0)    /**< Shifted mode SELDDATA3DDATA0 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDDATA4DDATA0             (_CRYPTO_CMD_INSTR_SELDDATA4DDATA0 << 0)    /**< Shifted mode SELDDATA4DDATA0 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDATA0DDATA0              (_CRYPTO_CMD_INSTR_SELDATA0DDATA0 << 0)     /**< Shifted mode SELDATA0DDATA0 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDATA1DDATA0              (_CRYPTO_CMD_INSTR_SELDATA1DDATA0 << 0)     /**< Shifted mode SELDATA1DDATA0 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDATA2DDATA0              (_CRYPTO_CMD_INSTR_SELDATA2DDATA0 << 0)     /**< Shifted mode SELDATA2DDATA0 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDDATA0DDATA1             (_CRYPTO_CMD_INSTR_SELDDATA0DDATA1 << 0)    /**< Shifted mode SELDDATA0DDATA1 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDDATA1DDATA1             (_CRYPTO_CMD_INSTR_SELDDATA1DDATA1 << 0)    /**< Shifted mode SELDDATA1DDATA1 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDDATA2DDATA1             (_CRYPTO_CMD_INSTR_SELDDATA2DDATA1 << 0)    /**< Shifted mode SELDDATA2DDATA1 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDDATA3DDATA1             (_CRYPTO_CMD_INSTR_SELDDATA3DDATA1 << 0)    /**< Shifted mode SELDDATA3DDATA1 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDDATA4DDATA1             (_CRYPTO_CMD_INSTR_SELDDATA4DDATA1 << 0)    /**< Shifted mode SELDDATA4DDATA1 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDATA0DDATA1              (_CRYPTO_CMD_INSTR_SELDATA0DDATA1 << 0)     /**< Shifted mode SELDATA0DDATA1 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDATA1DDATA1              (_CRYPTO_CMD_INSTR_SELDATA1DDATA1 << 0)     /**< Shifted mode SELDATA1DDATA1 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDATA2DDATA1              (_CRYPTO_CMD_INSTR_SELDATA2DDATA1 << 0)     /**< Shifted mode SELDATA2DDATA1 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDDATA0DDATA2             (_CRYPTO_CMD_INSTR_SELDDATA0DDATA2 << 0)    /**< Shifted mode SELDDATA0DDATA2 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDDATA1DDATA2             (_CRYPTO_CMD_INSTR_SELDDATA1DDATA2 << 0)    /**< Shifted mode SELDDATA1DDATA2 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDDATA2DDATA2             (_CRYPTO_CMD_INSTR_SELDDATA2DDATA2 << 0)    /**< Shifted mode SELDDATA2DDATA2 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDDATA3DDATA2             (_CRYPTO_CMD_INSTR_SELDDATA3DDATA2 << 0)    /**< Shifted mode SELDDATA3DDATA2 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDDATA4DDATA2             (_CRYPTO_CMD_INSTR_SELDDATA4DDATA2 << 0)    /**< Shifted mode SELDDATA4DDATA2 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDATA0DDATA2              (_CRYPTO_CMD_INSTR_SELDATA0DDATA2 << 0)     /**< Shifted mode SELDATA0DDATA2 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDATA1DDATA2              (_CRYPTO_CMD_INSTR_SELDATA1DDATA2 << 0)     /**< Shifted mode SELDATA1DDATA2 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDATA2DDATA2              (_CRYPTO_CMD_INSTR_SELDATA2DDATA2 << 0)     /**< Shifted mode SELDATA2DDATA2 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDDATA0DDATA3             (_CRYPTO_CMD_INSTR_SELDDATA0DDATA3 << 0)    /**< Shifted mode SELDDATA0DDATA3 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDDATA1DDATA3             (_CRYPTO_CMD_INSTR_SELDDATA1DDATA3 << 0)    /**< Shifted mode SELDDATA1DDATA3 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDDATA2DDATA3             (_CRYPTO_CMD_INSTR_SELDDATA2DDATA3 << 0)    /**< Shifted mode SELDDATA2DDATA3 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDDATA3DDATA3             (_CRYPTO_CMD_INSTR_SELDDATA3DDATA3 << 0)    /**< Shifted mode SELDDATA3DDATA3 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDDATA4DDATA3             (_CRYPTO_CMD_INSTR_SELDDATA4DDATA3 << 0)    /**< Shifted mode SELDDATA4DDATA3 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDATA0DDATA3              (_CRYPTO_CMD_INSTR_SELDATA0DDATA3 << 0)     /**< Shifted mode SELDATA0DDATA3 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDATA1DDATA3              (_CRYPTO_CMD_INSTR_SELDATA1DDATA3 << 0)     /**< Shifted mode SELDATA1DDATA3 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDATA2DDATA3              (_CRYPTO_CMD_INSTR_SELDATA2DDATA3 << 0)     /**< Shifted mode SELDATA2DDATA3 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDDATA0DDATA4             (_CRYPTO_CMD_INSTR_SELDDATA0DDATA4 << 0)    /**< Shifted mode SELDDATA0DDATA4 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDDATA1DDATA4             (_CRYPTO_CMD_INSTR_SELDDATA1DDATA4 << 0)    /**< Shifted mode SELDDATA1DDATA4 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDDATA2DDATA4             (_CRYPTO_CMD_INSTR_SELDDATA2DDATA4 << 0)    /**< Shifted mode SELDDATA2DDATA4 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDDATA3DDATA4             (_CRYPTO_CMD_INSTR_SELDDATA3DDATA4 << 0)    /**< Shifted mode SELDDATA3DDATA4 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDDATA4DDATA4             (_CRYPTO_CMD_INSTR_SELDDATA4DDATA4 << 0)    /**< Shifted mode SELDDATA4DDATA4 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDATA0DDATA4              (_CRYPTO_CMD_INSTR_SELDATA0DDATA4 << 0)     /**< Shifted mode SELDATA0DDATA4 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDATA1DDATA4              (_CRYPTO_CMD_INSTR_SELDATA1DDATA4 << 0)     /**< Shifted mode SELDATA1DDATA4 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDATA2DDATA4              (_CRYPTO_CMD_INSTR_SELDATA2DDATA4 << 0)     /**< Shifted mode SELDATA2DDATA4 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDDATA0DATA0              (_CRYPTO_CMD_INSTR_SELDDATA0DATA0 << 0)     /**< Shifted mode SELDDATA0DATA0 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDDATA1DATA0              (_CRYPTO_CMD_INSTR_SELDDATA1DATA0 << 0)     /**< Shifted mode SELDDATA1DATA0 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDDATA2DATA0              (_CRYPTO_CMD_INSTR_SELDDATA2DATA0 << 0)     /**< Shifted mode SELDDATA2DATA0 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDDATA3DATA0              (_CRYPTO_CMD_INSTR_SELDDATA3DATA0 << 0)     /**< Shifted mode SELDDATA3DATA0 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDDATA4DATA0              (_CRYPTO_CMD_INSTR_SELDDATA4DATA0 << 0)     /**< Shifted mode SELDDATA4DATA0 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDATA0DATA0               (_CRYPTO_CMD_INSTR_SELDATA0DATA0 << 0)      /**< Shifted mode SELDATA0DATA0 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDATA1DATA0               (_CRYPTO_CMD_INSTR_SELDATA1DATA0 << 0)      /**< Shifted mode SELDATA1DATA0 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDATA2DATA0               (_CRYPTO_CMD_INSTR_SELDATA2DATA0 << 0)      /**< Shifted mode SELDATA2DATA0 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDDATA0DATA1              (_CRYPTO_CMD_INSTR_SELDDATA0DATA1 << 0)     /**< Shifted mode SELDDATA0DATA1 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDDATA1DATA1              (_CRYPTO_CMD_INSTR_SELDDATA1DATA1 << 0)     /**< Shifted mode SELDDATA1DATA1 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDDATA2DATA1              (_CRYPTO_CMD_INSTR_SELDDATA2DATA1 << 0)     /**< Shifted mode SELDDATA2DATA1 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDDATA3DATA1              (_CRYPTO_CMD_INSTR_SELDDATA3DATA1 << 0)     /**< Shifted mode SELDDATA3DATA1 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDDATA4DATA1              (_CRYPTO_CMD_INSTR_SELDDATA4DATA1 << 0)     /**< Shifted mode SELDDATA4DATA1 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDATA0DATA1               (_CRYPTO_CMD_INSTR_SELDATA0DATA1 << 0)      /**< Shifted mode SELDATA0DATA1 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDATA1DATA1               (_CRYPTO_CMD_INSTR_SELDATA1DATA1 << 0)      /**< Shifted mode SELDATA1DATA1 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDATA2DATA1               (_CRYPTO_CMD_INSTR_SELDATA2DATA1 << 0)      /**< Shifted mode SELDATA2DATA1 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_EXECIFA                     (_CRYPTO_CMD_INSTR_EXECIFA << 0)            /**< Shifted mode EXECIFA for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_EXECIFB                     (_CRYPTO_CMD_INSTR_EXECIFB << 0)            /**< Shifted mode EXECIFB for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_EXECIFNLAST                 (_CRYPTO_CMD_INSTR_EXECIFNLAST << 0)        /**< Shifted mode EXECIFNLAST for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_EXECIFLAST                  (_CRYPTO_CMD_INSTR_EXECIFLAST << 0)         /**< Shifted mode EXECIFLAST for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_EXECIFCARRY                 (_CRYPTO_CMD_INSTR_EXECIFCARRY << 0)        /**< Shifted mode EXECIFCARRY for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_EXECIFNCARRY                (_CRYPTO_CMD_INSTR_EXECIFNCARRY << 0)       /**< Shifted mode EXECIFNCARRY for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_EXECALWAYS                  (_CRYPTO_CMD_INSTR_EXECALWAYS << 0)         /**< Shifted mode EXECALWAYS for CRYPTO_CMD */
+#define CRYPTO_CMD_SEQSTART                          (0x1UL << 9)                                /**< Encryption/Decryption SEQUENCE Start */
+#define _CRYPTO_CMD_SEQSTART_SHIFT                   9                                           /**< Shift value for CRYPTO_SEQSTART */
+#define _CRYPTO_CMD_SEQSTART_MASK                    0x200UL                                     /**< Bit mask for CRYPTO_SEQSTART */
+#define _CRYPTO_CMD_SEQSTART_DEFAULT                 0x00000000UL                                /**< Mode DEFAULT for CRYPTO_CMD */
+#define CRYPTO_CMD_SEQSTART_DEFAULT                  (_CRYPTO_CMD_SEQSTART_DEFAULT << 9)         /**< Shifted mode DEFAULT for CRYPTO_CMD */
+#define CRYPTO_CMD_SEQSTOP                           (0x1UL << 10)                               /**< Sequence Stop */
+#define _CRYPTO_CMD_SEQSTOP_SHIFT                    10                                          /**< Shift value for CRYPTO_SEQSTOP */
+#define _CRYPTO_CMD_SEQSTOP_MASK                     0x400UL                                     /**< Bit mask for CRYPTO_SEQSTOP */
+#define _CRYPTO_CMD_SEQSTOP_DEFAULT                  0x00000000UL                                /**< Mode DEFAULT for CRYPTO_CMD */
+#define CRYPTO_CMD_SEQSTOP_DEFAULT                   (_CRYPTO_CMD_SEQSTOP_DEFAULT << 10)         /**< Shifted mode DEFAULT for CRYPTO_CMD */
+#define CRYPTO_CMD_SEQSTEP                           (0x1UL << 11)                               /**< Sequence Step */
+#define _CRYPTO_CMD_SEQSTEP_SHIFT                    11                                          /**< Shift value for CRYPTO_SEQSTEP */
+#define _CRYPTO_CMD_SEQSTEP_MASK                     0x800UL                                     /**< Bit mask for CRYPTO_SEQSTEP */
+#define _CRYPTO_CMD_SEQSTEP_DEFAULT                  0x00000000UL                                /**< Mode DEFAULT for CRYPTO_CMD */
+#define CRYPTO_CMD_SEQSTEP_DEFAULT                   (_CRYPTO_CMD_SEQSTEP_DEFAULT << 11)         /**< Shifted mode DEFAULT for CRYPTO_CMD */
+
+/* Bit fields for CRYPTO STATUS */
+#define _CRYPTO_STATUS_RESETVALUE                    0x00000000UL                               /**< Default value for CRYPTO_STATUS */
+#define _CRYPTO_STATUS_MASK                          0x00000007UL                               /**< Mask for CRYPTO_STATUS */
+#define CRYPTO_STATUS_SEQRUNNING                     (0x1UL << 0)                               /**< AES SEQUENCE Running */
+#define _CRYPTO_STATUS_SEQRUNNING_SHIFT              0                                          /**< Shift value for CRYPTO_SEQRUNNING */
+#define _CRYPTO_STATUS_SEQRUNNING_MASK               0x1UL                                      /**< Bit mask for CRYPTO_SEQRUNNING */
+#define _CRYPTO_STATUS_SEQRUNNING_DEFAULT            0x00000000UL                               /**< Mode DEFAULT for CRYPTO_STATUS */
+#define CRYPTO_STATUS_SEQRUNNING_DEFAULT             (_CRYPTO_STATUS_SEQRUNNING_DEFAULT << 0)   /**< Shifted mode DEFAULT for CRYPTO_STATUS */
+#define CRYPTO_STATUS_INSTRRUNNING                   (0x1UL << 1)                               /**< Action is active */
+#define _CRYPTO_STATUS_INSTRRUNNING_SHIFT            1                                          /**< Shift value for CRYPTO_INSTRRUNNING */
+#define _CRYPTO_STATUS_INSTRRUNNING_MASK             0x2UL                                      /**< Bit mask for CRYPTO_INSTRRUNNING */
+#define _CRYPTO_STATUS_INSTRRUNNING_DEFAULT          0x00000000UL                               /**< Mode DEFAULT for CRYPTO_STATUS */
+#define CRYPTO_STATUS_INSTRRUNNING_DEFAULT           (_CRYPTO_STATUS_INSTRRUNNING_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTO_STATUS */
+#define CRYPTO_STATUS_DMAACTIVE                      (0x1UL << 2)                               /**< DMA Action is active */
+#define _CRYPTO_STATUS_DMAACTIVE_SHIFT               2                                          /**< Shift value for CRYPTO_DMAACTIVE */
+#define _CRYPTO_STATUS_DMAACTIVE_MASK                0x4UL                                      /**< Bit mask for CRYPTO_DMAACTIVE */
+#define _CRYPTO_STATUS_DMAACTIVE_DEFAULT             0x00000000UL                               /**< Mode DEFAULT for CRYPTO_STATUS */
+#define CRYPTO_STATUS_DMAACTIVE_DEFAULT              (_CRYPTO_STATUS_DMAACTIVE_DEFAULT << 2)    /**< Shifted mode DEFAULT for CRYPTO_STATUS */
+
+/* Bit fields for CRYPTO DSTATUS */
+#define _CRYPTO_DSTATUS_RESETVALUE                   0x00000000UL                                 /**< Default value for CRYPTO_DSTATUS */
+#define _CRYPTO_DSTATUS_MASK                         0x011F0F0FUL                                 /**< Mask for CRYPTO_DSTATUS */
+#define _CRYPTO_DSTATUS_DATA0ZERO_SHIFT              0                                            /**< Shift value for CRYPTO_DATA0ZERO */
+#define _CRYPTO_DSTATUS_DATA0ZERO_MASK               0xFUL                                        /**< Bit mask for CRYPTO_DATA0ZERO */
+#define _CRYPTO_DSTATUS_DATA0ZERO_DEFAULT            0x00000000UL                                 /**< Mode DEFAULT for CRYPTO_DSTATUS */
+#define _CRYPTO_DSTATUS_DATA0ZERO_ZERO0TO31          0x00000001UL                                 /**< Mode ZERO0TO31 for CRYPTO_DSTATUS */
+#define _CRYPTO_DSTATUS_DATA0ZERO_ZERO32TO63         0x00000002UL                                 /**< Mode ZERO32TO63 for CRYPTO_DSTATUS */
+#define _CRYPTO_DSTATUS_DATA0ZERO_ZERO64TO95         0x00000004UL                                 /**< Mode ZERO64TO95 for CRYPTO_DSTATUS */
+#define _CRYPTO_DSTATUS_DATA0ZERO_ZERO96TO127        0x00000008UL                                 /**< Mode ZERO96TO127 for CRYPTO_DSTATUS */
+#define CRYPTO_DSTATUS_DATA0ZERO_DEFAULT             (_CRYPTO_DSTATUS_DATA0ZERO_DEFAULT << 0)     /**< Shifted mode DEFAULT for CRYPTO_DSTATUS */
+#define CRYPTO_DSTATUS_DATA0ZERO_ZERO0TO31           (_CRYPTO_DSTATUS_DATA0ZERO_ZERO0TO31 << 0)   /**< Shifted mode ZERO0TO31 for CRYPTO_DSTATUS */
+#define CRYPTO_DSTATUS_DATA0ZERO_ZERO32TO63          (_CRYPTO_DSTATUS_DATA0ZERO_ZERO32TO63 << 0)  /**< Shifted mode ZERO32TO63 for CRYPTO_DSTATUS */
+#define CRYPTO_DSTATUS_DATA0ZERO_ZERO64TO95          (_CRYPTO_DSTATUS_DATA0ZERO_ZERO64TO95 << 0)  /**< Shifted mode ZERO64TO95 for CRYPTO_DSTATUS */
+#define CRYPTO_DSTATUS_DATA0ZERO_ZERO96TO127         (_CRYPTO_DSTATUS_DATA0ZERO_ZERO96TO127 << 0) /**< Shifted mode ZERO96TO127 for CRYPTO_DSTATUS */
+#define _CRYPTO_DSTATUS_DDATA0LSBS_SHIFT             8                                            /**< Shift value for CRYPTO_DDATA0LSBS */
+#define _CRYPTO_DSTATUS_DDATA0LSBS_MASK              0xF00UL                                      /**< Bit mask for CRYPTO_DDATA0LSBS */
+#define _CRYPTO_DSTATUS_DDATA0LSBS_DEFAULT           0x00000000UL                                 /**< Mode DEFAULT for CRYPTO_DSTATUS */
+#define CRYPTO_DSTATUS_DDATA0LSBS_DEFAULT            (_CRYPTO_DSTATUS_DDATA0LSBS_DEFAULT << 8)    /**< Shifted mode DEFAULT for CRYPTO_DSTATUS */
+#define _CRYPTO_DSTATUS_DDATA0MSBS_SHIFT             16                                           /**< Shift value for CRYPTO_DDATA0MSBS */
+#define _CRYPTO_DSTATUS_DDATA0MSBS_MASK              0xF0000UL                                    /**< Bit mask for CRYPTO_DDATA0MSBS */
+#define _CRYPTO_DSTATUS_DDATA0MSBS_DEFAULT           0x00000000UL                                 /**< Mode DEFAULT for CRYPTO_DSTATUS */
+#define CRYPTO_DSTATUS_DDATA0MSBS_DEFAULT            (_CRYPTO_DSTATUS_DDATA0MSBS_DEFAULT << 16)   /**< Shifted mode DEFAULT for CRYPTO_DSTATUS */
+#define CRYPTO_DSTATUS_DDATA1MSB                     (0x1UL << 20)                                /**< MSB in DDATA1 */
+#define _CRYPTO_DSTATUS_DDATA1MSB_SHIFT              20                                           /**< Shift value for CRYPTO_DDATA1MSB */
+#define _CRYPTO_DSTATUS_DDATA1MSB_MASK               0x100000UL                                   /**< Bit mask for CRYPTO_DDATA1MSB */
+#define _CRYPTO_DSTATUS_DDATA1MSB_DEFAULT            0x00000000UL                                 /**< Mode DEFAULT for CRYPTO_DSTATUS */
+#define CRYPTO_DSTATUS_DDATA1MSB_DEFAULT             (_CRYPTO_DSTATUS_DDATA1MSB_DEFAULT << 20)    /**< Shifted mode DEFAULT for CRYPTO_DSTATUS */
+#define CRYPTO_DSTATUS_CARRY                         (0x1UL << 24)                                /**< Carry From Arithmetic Operation */
+#define _CRYPTO_DSTATUS_CARRY_SHIFT                  24                                           /**< Shift value for CRYPTO_CARRY */
+#define _CRYPTO_DSTATUS_CARRY_MASK                   0x1000000UL                                  /**< Bit mask for CRYPTO_CARRY */
+#define _CRYPTO_DSTATUS_CARRY_DEFAULT                0x00000000UL                                 /**< Mode DEFAULT for CRYPTO_DSTATUS */
+#define CRYPTO_DSTATUS_CARRY_DEFAULT                 (_CRYPTO_DSTATUS_CARRY_DEFAULT << 24)        /**< Shifted mode DEFAULT for CRYPTO_DSTATUS */
+
+/* Bit fields for CRYPTO CSTATUS */
+#define _CRYPTO_CSTATUS_RESETVALUE                   0x00000201UL                            /**< Default value for CRYPTO_CSTATUS */
+#define _CRYPTO_CSTATUS_MASK                         0x01F30707UL                            /**< Mask for CRYPTO_CSTATUS */
+#define _CRYPTO_CSTATUS_V0_SHIFT                     0                                       /**< Shift value for CRYPTO_V0 */
+#define _CRYPTO_CSTATUS_V0_MASK                      0x7UL                                   /**< Bit mask for CRYPTO_V0 */
+#define _CRYPTO_CSTATUS_V0_DDATA0                    0x00000000UL                            /**< Mode DDATA0 for CRYPTO_CSTATUS */
+#define _CRYPTO_CSTATUS_V0_DEFAULT                   0x00000001UL                            /**< Mode DEFAULT for CRYPTO_CSTATUS */
+#define _CRYPTO_CSTATUS_V0_DDATA1                    0x00000001UL                            /**< Mode DDATA1 for CRYPTO_CSTATUS */
+#define _CRYPTO_CSTATUS_V0_DDATA2                    0x00000002UL                            /**< Mode DDATA2 for CRYPTO_CSTATUS */
+#define _CRYPTO_CSTATUS_V0_DDATA3                    0x00000003UL                            /**< Mode DDATA3 for CRYPTO_CSTATUS */
+#define _CRYPTO_CSTATUS_V0_DDATA4                    0x00000004UL                            /**< Mode DDATA4 for CRYPTO_CSTATUS */
+#define _CRYPTO_CSTATUS_V0_DATA0                     0x00000005UL                            /**< Mode DATA0 for CRYPTO_CSTATUS */
+#define _CRYPTO_CSTATUS_V0_DATA1                     0x00000006UL                            /**< Mode DATA1 for CRYPTO_CSTATUS */
+#define _CRYPTO_CSTATUS_V0_DATA2                     0x00000007UL                            /**< Mode DATA2 for CRYPTO_CSTATUS */
+#define CRYPTO_CSTATUS_V0_DDATA0                     (_CRYPTO_CSTATUS_V0_DDATA0 << 0)        /**< Shifted mode DDATA0 for CRYPTO_CSTATUS */
+#define CRYPTO_CSTATUS_V0_DEFAULT                    (_CRYPTO_CSTATUS_V0_DEFAULT << 0)       /**< Shifted mode DEFAULT for CRYPTO_CSTATUS */
+#define CRYPTO_CSTATUS_V0_DDATA1                     (_CRYPTO_CSTATUS_V0_DDATA1 << 0)        /**< Shifted mode DDATA1 for CRYPTO_CSTATUS */
+#define CRYPTO_CSTATUS_V0_DDATA2                     (_CRYPTO_CSTATUS_V0_DDATA2 << 0)        /**< Shifted mode DDATA2 for CRYPTO_CSTATUS */
+#define CRYPTO_CSTATUS_V0_DDATA3                     (_CRYPTO_CSTATUS_V0_DDATA3 << 0)        /**< Shifted mode DDATA3 for CRYPTO_CSTATUS */
+#define CRYPTO_CSTATUS_V0_DDATA4                     (_CRYPTO_CSTATUS_V0_DDATA4 << 0)        /**< Shifted mode DDATA4 for CRYPTO_CSTATUS */
+#define CRYPTO_CSTATUS_V0_DATA0                      (_CRYPTO_CSTATUS_V0_DATA0 << 0)         /**< Shifted mode DATA0 for CRYPTO_CSTATUS */
+#define CRYPTO_CSTATUS_V0_DATA1                      (_CRYPTO_CSTATUS_V0_DATA1 << 0)         /**< Shifted mode DATA1 for CRYPTO_CSTATUS */
+#define CRYPTO_CSTATUS_V0_DATA2                      (_CRYPTO_CSTATUS_V0_DATA2 << 0)         /**< Shifted mode DATA2 for CRYPTO_CSTATUS */
+#define _CRYPTO_CSTATUS_V1_SHIFT                     8                                       /**< Shift value for CRYPTO_V1 */
+#define _CRYPTO_CSTATUS_V1_MASK                      0x700UL                                 /**< Bit mask for CRYPTO_V1 */
+#define _CRYPTO_CSTATUS_V1_DDATA0                    0x00000000UL                            /**< Mode DDATA0 for CRYPTO_CSTATUS */
+#define _CRYPTO_CSTATUS_V1_DDATA1                    0x00000001UL                            /**< Mode DDATA1 for CRYPTO_CSTATUS */
+#define _CRYPTO_CSTATUS_V1_DEFAULT                   0x00000002UL                            /**< Mode DEFAULT for CRYPTO_CSTATUS */
+#define _CRYPTO_CSTATUS_V1_DDATA2                    0x00000002UL                            /**< Mode DDATA2 for CRYPTO_CSTATUS */
+#define _CRYPTO_CSTATUS_V1_DDATA3                    0x00000003UL                            /**< Mode DDATA3 for CRYPTO_CSTATUS */
+#define _CRYPTO_CSTATUS_V1_DDATA4                    0x00000004UL                            /**< Mode DDATA4 for CRYPTO_CSTATUS */
+#define _CRYPTO_CSTATUS_V1_DATA0                     0x00000005UL                            /**< Mode DATA0 for CRYPTO_CSTATUS */
+#define _CRYPTO_CSTATUS_V1_DATA1                     0x00000006UL                            /**< Mode DATA1 for CRYPTO_CSTATUS */
+#define _CRYPTO_CSTATUS_V1_DATA2                     0x00000007UL                            /**< Mode DATA2 for CRYPTO_CSTATUS */
+#define CRYPTO_CSTATUS_V1_DDATA0                     (_CRYPTO_CSTATUS_V1_DDATA0 << 8)        /**< Shifted mode DDATA0 for CRYPTO_CSTATUS */
+#define CRYPTO_CSTATUS_V1_DDATA1                     (_CRYPTO_CSTATUS_V1_DDATA1 << 8)        /**< Shifted mode DDATA1 for CRYPTO_CSTATUS */
+#define CRYPTO_CSTATUS_V1_DEFAULT                    (_CRYPTO_CSTATUS_V1_DEFAULT << 8)       /**< Shifted mode DEFAULT for CRYPTO_CSTATUS */
+#define CRYPTO_CSTATUS_V1_DDATA2                     (_CRYPTO_CSTATUS_V1_DDATA2 << 8)        /**< Shifted mode DDATA2 for CRYPTO_CSTATUS */
+#define CRYPTO_CSTATUS_V1_DDATA3                     (_CRYPTO_CSTATUS_V1_DDATA3 << 8)        /**< Shifted mode DDATA3 for CRYPTO_CSTATUS */
+#define CRYPTO_CSTATUS_V1_DDATA4                     (_CRYPTO_CSTATUS_V1_DDATA4 << 8)        /**< Shifted mode DDATA4 for CRYPTO_CSTATUS */
+#define CRYPTO_CSTATUS_V1_DATA0                      (_CRYPTO_CSTATUS_V1_DATA0 << 8)         /**< Shifted mode DATA0 for CRYPTO_CSTATUS */
+#define CRYPTO_CSTATUS_V1_DATA1                      (_CRYPTO_CSTATUS_V1_DATA1 << 8)         /**< Shifted mode DATA1 for CRYPTO_CSTATUS */
+#define CRYPTO_CSTATUS_V1_DATA2                      (_CRYPTO_CSTATUS_V1_DATA2 << 8)         /**< Shifted mode DATA2 for CRYPTO_CSTATUS */
+#define CRYPTO_CSTATUS_SEQPART                       (0x1UL << 16)                           /**< Sequence Part */
+#define _CRYPTO_CSTATUS_SEQPART_SHIFT                16                                      /**< Shift value for CRYPTO_SEQPART */
+#define _CRYPTO_CSTATUS_SEQPART_MASK                 0x10000UL                               /**< Bit mask for CRYPTO_SEQPART */
+#define _CRYPTO_CSTATUS_SEQPART_DEFAULT              0x00000000UL                            /**< Mode DEFAULT for CRYPTO_CSTATUS */
+#define _CRYPTO_CSTATUS_SEQPART_SEQA                 0x00000000UL                            /**< Mode SEQA for CRYPTO_CSTATUS */
+#define _CRYPTO_CSTATUS_SEQPART_SEQB                 0x00000001UL                            /**< Mode SEQB for CRYPTO_CSTATUS */
+#define CRYPTO_CSTATUS_SEQPART_DEFAULT               (_CRYPTO_CSTATUS_SEQPART_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_CSTATUS */
+#define CRYPTO_CSTATUS_SEQPART_SEQA                  (_CRYPTO_CSTATUS_SEQPART_SEQA << 16)    /**< Shifted mode SEQA for CRYPTO_CSTATUS */
+#define CRYPTO_CSTATUS_SEQPART_SEQB                  (_CRYPTO_CSTATUS_SEQPART_SEQB << 16)    /**< Shifted mode SEQB for CRYPTO_CSTATUS */
+#define CRYPTO_CSTATUS_SEQSKIP                       (0x1UL << 17)                           /**< Sequence Skip Next Instruction */
+#define _CRYPTO_CSTATUS_SEQSKIP_SHIFT                17                                      /**< Shift value for CRYPTO_SEQSKIP */
+#define _CRYPTO_CSTATUS_SEQSKIP_MASK                 0x20000UL                               /**< Bit mask for CRYPTO_SEQSKIP */
+#define _CRYPTO_CSTATUS_SEQSKIP_DEFAULT              0x00000000UL                            /**< Mode DEFAULT for CRYPTO_CSTATUS */
+#define CRYPTO_CSTATUS_SEQSKIP_DEFAULT               (_CRYPTO_CSTATUS_SEQSKIP_DEFAULT << 17) /**< Shifted mode DEFAULT for CRYPTO_CSTATUS */
+#define _CRYPTO_CSTATUS_SEQIP_SHIFT                  20                                      /**< Shift value for CRYPTO_SEQIP */
+#define _CRYPTO_CSTATUS_SEQIP_MASK                   0x1F00000UL                             /**< Bit mask for CRYPTO_SEQIP */
+#define _CRYPTO_CSTATUS_SEQIP_DEFAULT                0x00000000UL                            /**< Mode DEFAULT for CRYPTO_CSTATUS */
+#define CRYPTO_CSTATUS_SEQIP_DEFAULT                 (_CRYPTO_CSTATUS_SEQIP_DEFAULT << 20)   /**< Shifted mode DEFAULT for CRYPTO_CSTATUS */
+
+/* Bit fields for CRYPTO KEY */
+#define _CRYPTO_KEY_RESETVALUE                       0x00000000UL                   /**< Default value for CRYPTO_KEY */
+#define _CRYPTO_KEY_MASK                             0xFFFFFFFFUL                   /**< Mask for CRYPTO_KEY */
+#define _CRYPTO_KEY_KEY_SHIFT                        0                              /**< Shift value for CRYPTO_KEY */
+#define _CRYPTO_KEY_KEY_MASK                         0xFFFFFFFFUL                   /**< Bit mask for CRYPTO_KEY */
+#define _CRYPTO_KEY_KEY_DEFAULT                      0x00000000UL                   /**< Mode DEFAULT for CRYPTO_KEY */
+#define CRYPTO_KEY_KEY_DEFAULT                       (_CRYPTO_KEY_KEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_KEY */
+
+/* Bit fields for CRYPTO KEYBUF */
+#define _CRYPTO_KEYBUF_RESETVALUE                    0x00000000UL                         /**< Default value for CRYPTO_KEYBUF */
+#define _CRYPTO_KEYBUF_MASK                          0xFFFFFFFFUL                         /**< Mask for CRYPTO_KEYBUF */
+#define _CRYPTO_KEYBUF_KEYBUF_SHIFT                  0                                    /**< Shift value for CRYPTO_KEYBUF */
+#define _CRYPTO_KEYBUF_KEYBUF_MASK                   0xFFFFFFFFUL                         /**< Bit mask for CRYPTO_KEYBUF */
+#define _CRYPTO_KEYBUF_KEYBUF_DEFAULT                0x00000000UL                         /**< Mode DEFAULT for CRYPTO_KEYBUF */
+#define CRYPTO_KEYBUF_KEYBUF_DEFAULT                 (_CRYPTO_KEYBUF_KEYBUF_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_KEYBUF */
+
+/* Bit fields for CRYPTO SEQCTRL */
+#define _CRYPTO_SEQCTRL_RESETVALUE                   0x00000000UL                              /**< Default value for CRYPTO_SEQCTRL */
+#define _CRYPTO_SEQCTRL_MASK                         0xBF303FFFUL                              /**< Mask for CRYPTO_SEQCTRL */
+#define _CRYPTO_SEQCTRL_LENGTHA_SHIFT                0                                         /**< Shift value for CRYPTO_LENGTHA */
+#define _CRYPTO_SEQCTRL_LENGTHA_MASK                 0x3FFFUL                                  /**< Bit mask for CRYPTO_LENGTHA */
+#define _CRYPTO_SEQCTRL_LENGTHA_DEFAULT              0x00000000UL                              /**< Mode DEFAULT for CRYPTO_SEQCTRL */
+#define CRYPTO_SEQCTRL_LENGTHA_DEFAULT               (_CRYPTO_SEQCTRL_LENGTHA_DEFAULT << 0)    /**< Shifted mode DEFAULT for CRYPTO_SEQCTRL */
+#define _CRYPTO_SEQCTRL_BLOCKSIZE_SHIFT              20                                        /**< Shift value for CRYPTO_BLOCKSIZE */
+#define _CRYPTO_SEQCTRL_BLOCKSIZE_MASK               0x300000UL                                /**< Bit mask for CRYPTO_BLOCKSIZE */
+#define _CRYPTO_SEQCTRL_BLOCKSIZE_DEFAULT            0x00000000UL                              /**< Mode DEFAULT for CRYPTO_SEQCTRL */
+#define _CRYPTO_SEQCTRL_BLOCKSIZE_16BYTES            0x00000000UL                              /**< Mode 16BYTES for CRYPTO_SEQCTRL */
+#define _CRYPTO_SEQCTRL_BLOCKSIZE_32BYTES            0x00000001UL                              /**< Mode 32BYTES for CRYPTO_SEQCTRL */
+#define _CRYPTO_SEQCTRL_BLOCKSIZE_64BYTES            0x00000002UL                              /**< Mode 64BYTES for CRYPTO_SEQCTRL */
+#define CRYPTO_SEQCTRL_BLOCKSIZE_DEFAULT             (_CRYPTO_SEQCTRL_BLOCKSIZE_DEFAULT << 20) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRL */
+#define CRYPTO_SEQCTRL_BLOCKSIZE_16BYTES             (_CRYPTO_SEQCTRL_BLOCKSIZE_16BYTES << 20) /**< Shifted mode 16BYTES for CRYPTO_SEQCTRL */
+#define CRYPTO_SEQCTRL_BLOCKSIZE_32BYTES             (_CRYPTO_SEQCTRL_BLOCKSIZE_32BYTES << 20) /**< Shifted mode 32BYTES for CRYPTO_SEQCTRL */
+#define CRYPTO_SEQCTRL_BLOCKSIZE_64BYTES             (_CRYPTO_SEQCTRL_BLOCKSIZE_64BYTES << 20) /**< Shifted mode 64BYTES for CRYPTO_SEQCTRL */
+#define _CRYPTO_SEQCTRL_DMA0SKIP_SHIFT               24                                        /**< Shift value for CRYPTO_DMA0SKIP */
+#define _CRYPTO_SEQCTRL_DMA0SKIP_MASK                0x3000000UL                               /**< Bit mask for CRYPTO_DMA0SKIP */
+#define _CRYPTO_SEQCTRL_DMA0SKIP_DEFAULT             0x00000000UL                              /**< Mode DEFAULT for CRYPTO_SEQCTRL */
+#define CRYPTO_SEQCTRL_DMA0SKIP_DEFAULT              (_CRYPTO_SEQCTRL_DMA0SKIP_DEFAULT << 24)  /**< Shifted mode DEFAULT for CRYPTO_SEQCTRL */
+#define _CRYPTO_SEQCTRL_DMA1SKIP_SHIFT               26                                        /**< Shift value for CRYPTO_DMA1SKIP */
+#define _CRYPTO_SEQCTRL_DMA1SKIP_MASK                0xC000000UL                               /**< Bit mask for CRYPTO_DMA1SKIP */
+#define _CRYPTO_SEQCTRL_DMA1SKIP_DEFAULT             0x00000000UL                              /**< Mode DEFAULT for CRYPTO_SEQCTRL */
+#define CRYPTO_SEQCTRL_DMA1SKIP_DEFAULT              (_CRYPTO_SEQCTRL_DMA1SKIP_DEFAULT << 26)  /**< Shifted mode DEFAULT for CRYPTO_SEQCTRL */
+#define CRYPTO_SEQCTRL_DMA0PRESA                     (0x1UL << 28)                             /**< DMA0 Preserve A */
+#define _CRYPTO_SEQCTRL_DMA0PRESA_SHIFT              28                                        /**< Shift value for CRYPTO_DMA0PRESA */
+#define _CRYPTO_SEQCTRL_DMA0PRESA_MASK               0x10000000UL                              /**< Bit mask for CRYPTO_DMA0PRESA */
+#define _CRYPTO_SEQCTRL_DMA0PRESA_DEFAULT            0x00000000UL                              /**< Mode DEFAULT for CRYPTO_SEQCTRL */
+#define CRYPTO_SEQCTRL_DMA0PRESA_DEFAULT             (_CRYPTO_SEQCTRL_DMA0PRESA_DEFAULT << 28) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRL */
+#define CRYPTO_SEQCTRL_DMA1PRESA                     (0x1UL << 29)                             /**< DMA1 Preserve A */
+#define _CRYPTO_SEQCTRL_DMA1PRESA_SHIFT              29                                        /**< Shift value for CRYPTO_DMA1PRESA */
+#define _CRYPTO_SEQCTRL_DMA1PRESA_MASK               0x20000000UL                              /**< Bit mask for CRYPTO_DMA1PRESA */
+#define _CRYPTO_SEQCTRL_DMA1PRESA_DEFAULT            0x00000000UL                              /**< Mode DEFAULT for CRYPTO_SEQCTRL */
+#define CRYPTO_SEQCTRL_DMA1PRESA_DEFAULT             (_CRYPTO_SEQCTRL_DMA1PRESA_DEFAULT << 29) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRL */
+#define CRYPTO_SEQCTRL_HALT                          (0x1UL << 31)                             /**< Halt Sequence */
+#define _CRYPTO_SEQCTRL_HALT_SHIFT                   31                                        /**< Shift value for CRYPTO_HALT */
+#define _CRYPTO_SEQCTRL_HALT_MASK                    0x80000000UL                              /**< Bit mask for CRYPTO_HALT */
+#define _CRYPTO_SEQCTRL_HALT_DEFAULT                 0x00000000UL                              /**< Mode DEFAULT for CRYPTO_SEQCTRL */
+#define CRYPTO_SEQCTRL_HALT_DEFAULT                  (_CRYPTO_SEQCTRL_HALT_DEFAULT << 31)      /**< Shifted mode DEFAULT for CRYPTO_SEQCTRL */
+
+/* Bit fields for CRYPTO SEQCTRLB */
+#define _CRYPTO_SEQCTRLB_RESETVALUE                  0x00000000UL                               /**< Default value for CRYPTO_SEQCTRLB */
+#define _CRYPTO_SEQCTRLB_MASK                        0x30003FFFUL                               /**< Mask for CRYPTO_SEQCTRLB */
+#define _CRYPTO_SEQCTRLB_LENGTHB_SHIFT               0                                          /**< Shift value for CRYPTO_LENGTHB */
+#define _CRYPTO_SEQCTRLB_LENGTHB_MASK                0x3FFFUL                                   /**< Bit mask for CRYPTO_LENGTHB */
+#define _CRYPTO_SEQCTRLB_LENGTHB_DEFAULT             0x00000000UL                               /**< Mode DEFAULT for CRYPTO_SEQCTRLB */
+#define CRYPTO_SEQCTRLB_LENGTHB_DEFAULT              (_CRYPTO_SEQCTRLB_LENGTHB_DEFAULT << 0)    /**< Shifted mode DEFAULT for CRYPTO_SEQCTRLB */
+#define CRYPTO_SEQCTRLB_DMA0PRESB                    (0x1UL << 28)                              /**< DMA0 Preserve B */
+#define _CRYPTO_SEQCTRLB_DMA0PRESB_SHIFT             28                                         /**< Shift value for CRYPTO_DMA0PRESB */
+#define _CRYPTO_SEQCTRLB_DMA0PRESB_MASK              0x10000000UL                               /**< Bit mask for CRYPTO_DMA0PRESB */
+#define _CRYPTO_SEQCTRLB_DMA0PRESB_DEFAULT           0x00000000UL                               /**< Mode DEFAULT for CRYPTO_SEQCTRLB */
+#define CRYPTO_SEQCTRLB_DMA0PRESB_DEFAULT            (_CRYPTO_SEQCTRLB_DMA0PRESB_DEFAULT << 28) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRLB */
+#define CRYPTO_SEQCTRLB_DMA1PRESB                    (0x1UL << 29)                              /**< DMA1 Preserve B */
+#define _CRYPTO_SEQCTRLB_DMA1PRESB_SHIFT             29                                         /**< Shift value for CRYPTO_DMA1PRESB */
+#define _CRYPTO_SEQCTRLB_DMA1PRESB_MASK              0x20000000UL                               /**< Bit mask for CRYPTO_DMA1PRESB */
+#define _CRYPTO_SEQCTRLB_DMA1PRESB_DEFAULT           0x00000000UL                               /**< Mode DEFAULT for CRYPTO_SEQCTRLB */
+#define CRYPTO_SEQCTRLB_DMA1PRESB_DEFAULT            (_CRYPTO_SEQCTRLB_DMA1PRESB_DEFAULT << 29) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRLB */
+
+/* Bit fields for CRYPTO IF */
+#define _CRYPTO_IF_RESETVALUE                        0x00000000UL                        /**< Default value for CRYPTO_IF */
+#define _CRYPTO_IF_MASK                              0x00000003UL                        /**< Mask for CRYPTO_IF */
+#define CRYPTO_IF_INSTRDONE                          (0x1UL << 0)                        /**< Instruction done */
+#define _CRYPTO_IF_INSTRDONE_SHIFT                   0                                   /**< Shift value for CRYPTO_INSTRDONE */
+#define _CRYPTO_IF_INSTRDONE_MASK                    0x1UL                               /**< Bit mask for CRYPTO_INSTRDONE */
+#define _CRYPTO_IF_INSTRDONE_DEFAULT                 0x00000000UL                        /**< Mode DEFAULT for CRYPTO_IF */
+#define CRYPTO_IF_INSTRDONE_DEFAULT                  (_CRYPTO_IF_INSTRDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_IF */
+#define CRYPTO_IF_SEQDONE                            (0x1UL << 1)                        /**< Sequence Done */
+#define _CRYPTO_IF_SEQDONE_SHIFT                     1                                   /**< Shift value for CRYPTO_SEQDONE */
+#define _CRYPTO_IF_SEQDONE_MASK                      0x2UL                               /**< Bit mask for CRYPTO_SEQDONE */
+#define _CRYPTO_IF_SEQDONE_DEFAULT                   0x00000000UL                        /**< Mode DEFAULT for CRYPTO_IF */
+#define CRYPTO_IF_SEQDONE_DEFAULT                    (_CRYPTO_IF_SEQDONE_DEFAULT << 1)   /**< Shifted mode DEFAULT for CRYPTO_IF */
+
+/* Bit fields for CRYPTO IFS */
+#define _CRYPTO_IFS_RESETVALUE                       0x00000000UL                         /**< Default value for CRYPTO_IFS */
+#define _CRYPTO_IFS_MASK                             0x0000000FUL                         /**< Mask for CRYPTO_IFS */
+#define CRYPTO_IFS_INSTRDONE                         (0x1UL << 0)                         /**< Set INSTRDONE Interrupt Flag */
+#define _CRYPTO_IFS_INSTRDONE_SHIFT                  0                                    /**< Shift value for CRYPTO_INSTRDONE */
+#define _CRYPTO_IFS_INSTRDONE_MASK                   0x1UL                                /**< Bit mask for CRYPTO_INSTRDONE */
+#define _CRYPTO_IFS_INSTRDONE_DEFAULT                0x00000000UL                         /**< Mode DEFAULT for CRYPTO_IFS */
+#define CRYPTO_IFS_INSTRDONE_DEFAULT                 (_CRYPTO_IFS_INSTRDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_IFS */
+#define CRYPTO_IFS_SEQDONE                           (0x1UL << 1)                         /**< Set SEQDONE Interrupt Flag */
+#define _CRYPTO_IFS_SEQDONE_SHIFT                    1                                    /**< Shift value for CRYPTO_SEQDONE */
+#define _CRYPTO_IFS_SEQDONE_MASK                     0x2UL                                /**< Bit mask for CRYPTO_SEQDONE */
+#define _CRYPTO_IFS_SEQDONE_DEFAULT                  0x00000000UL                         /**< Mode DEFAULT for CRYPTO_IFS */
+#define CRYPTO_IFS_SEQDONE_DEFAULT                   (_CRYPTO_IFS_SEQDONE_DEFAULT << 1)   /**< Shifted mode DEFAULT for CRYPTO_IFS */
+#define CRYPTO_IFS_BUFOF                             (0x1UL << 2)                         /**< Set BUFOF Interrupt Flag */
+#define _CRYPTO_IFS_BUFOF_SHIFT                      2                                    /**< Shift value for CRYPTO_BUFOF */
+#define _CRYPTO_IFS_BUFOF_MASK                       0x4UL                                /**< Bit mask for CRYPTO_BUFOF */
+#define _CRYPTO_IFS_BUFOF_DEFAULT                    0x00000000UL                         /**< Mode DEFAULT for CRYPTO_IFS */
+#define CRYPTO_IFS_BUFOF_DEFAULT                     (_CRYPTO_IFS_BUFOF_DEFAULT << 2)     /**< Shifted mode DEFAULT for CRYPTO_IFS */
+#define CRYPTO_IFS_BUFUF                             (0x1UL << 3)                         /**< Set BUFUF Interrupt Flag */
+#define _CRYPTO_IFS_BUFUF_SHIFT                      3                                    /**< Shift value for CRYPTO_BUFUF */
+#define _CRYPTO_IFS_BUFUF_MASK                       0x8UL                                /**< Bit mask for CRYPTO_BUFUF */
+#define _CRYPTO_IFS_BUFUF_DEFAULT                    0x00000000UL                         /**< Mode DEFAULT for CRYPTO_IFS */
+#define CRYPTO_IFS_BUFUF_DEFAULT                     (_CRYPTO_IFS_BUFUF_DEFAULT << 3)     /**< Shifted mode DEFAULT for CRYPTO_IFS */
+
+/* Bit fields for CRYPTO IFC */
+#define _CRYPTO_IFC_RESETVALUE                       0x00000000UL                         /**< Default value for CRYPTO_IFC */
+#define _CRYPTO_IFC_MASK                             0x0000000FUL                         /**< Mask for CRYPTO_IFC */
+#define CRYPTO_IFC_INSTRDONE                         (0x1UL << 0)                         /**< Clear INSTRDONE Interrupt Flag */
+#define _CRYPTO_IFC_INSTRDONE_SHIFT                  0                                    /**< Shift value for CRYPTO_INSTRDONE */
+#define _CRYPTO_IFC_INSTRDONE_MASK                   0x1UL                                /**< Bit mask for CRYPTO_INSTRDONE */
+#define _CRYPTO_IFC_INSTRDONE_DEFAULT                0x00000000UL                         /**< Mode DEFAULT for CRYPTO_IFC */
+#define CRYPTO_IFC_INSTRDONE_DEFAULT                 (_CRYPTO_IFC_INSTRDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_IFC */
+#define CRYPTO_IFC_SEQDONE                           (0x1UL << 1)                         /**< Clear SEQDONE Interrupt Flag */
+#define _CRYPTO_IFC_SEQDONE_SHIFT                    1                                    /**< Shift value for CRYPTO_SEQDONE */
+#define _CRYPTO_IFC_SEQDONE_MASK                     0x2UL                                /**< Bit mask for CRYPTO_SEQDONE */
+#define _CRYPTO_IFC_SEQDONE_DEFAULT                  0x00000000UL                         /**< Mode DEFAULT for CRYPTO_IFC */
+#define CRYPTO_IFC_SEQDONE_DEFAULT                   (_CRYPTO_IFC_SEQDONE_DEFAULT << 1)   /**< Shifted mode DEFAULT for CRYPTO_IFC */
+#define CRYPTO_IFC_BUFOF                             (0x1UL << 2)                         /**< Clear BUFOF Interrupt Flag */
+#define _CRYPTO_IFC_BUFOF_SHIFT                      2                                    /**< Shift value for CRYPTO_BUFOF */
+#define _CRYPTO_IFC_BUFOF_MASK                       0x4UL                                /**< Bit mask for CRYPTO_BUFOF */
+#define _CRYPTO_IFC_BUFOF_DEFAULT                    0x00000000UL                         /**< Mode DEFAULT for CRYPTO_IFC */
+#define CRYPTO_IFC_BUFOF_DEFAULT                     (_CRYPTO_IFC_BUFOF_DEFAULT << 2)     /**< Shifted mode DEFAULT for CRYPTO_IFC */
+#define CRYPTO_IFC_BUFUF                             (0x1UL << 3)                         /**< Clear BUFUF Interrupt Flag */
+#define _CRYPTO_IFC_BUFUF_SHIFT                      3                                    /**< Shift value for CRYPTO_BUFUF */
+#define _CRYPTO_IFC_BUFUF_MASK                       0x8UL                                /**< Bit mask for CRYPTO_BUFUF */
+#define _CRYPTO_IFC_BUFUF_DEFAULT                    0x00000000UL                         /**< Mode DEFAULT for CRYPTO_IFC */
+#define CRYPTO_IFC_BUFUF_DEFAULT                     (_CRYPTO_IFC_BUFUF_DEFAULT << 3)     /**< Shifted mode DEFAULT for CRYPTO_IFC */
+
+/* Bit fields for CRYPTO IEN */
+#define _CRYPTO_IEN_RESETVALUE                       0x00000000UL                         /**< Default value for CRYPTO_IEN */
+#define _CRYPTO_IEN_MASK                             0x0000000FUL                         /**< Mask for CRYPTO_IEN */
+#define CRYPTO_IEN_INSTRDONE                         (0x1UL << 0)                         /**< INSTRDONE Interrupt Enable */
+#define _CRYPTO_IEN_INSTRDONE_SHIFT                  0                                    /**< Shift value for CRYPTO_INSTRDONE */
+#define _CRYPTO_IEN_INSTRDONE_MASK                   0x1UL                                /**< Bit mask for CRYPTO_INSTRDONE */
+#define _CRYPTO_IEN_INSTRDONE_DEFAULT                0x00000000UL                         /**< Mode DEFAULT for CRYPTO_IEN */
+#define CRYPTO_IEN_INSTRDONE_DEFAULT                 (_CRYPTO_IEN_INSTRDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_IEN */
+#define CRYPTO_IEN_SEQDONE                           (0x1UL << 1)                         /**< SEQDONE Interrupt Enable */
+#define _CRYPTO_IEN_SEQDONE_SHIFT                    1                                    /**< Shift value for CRYPTO_SEQDONE */
+#define _CRYPTO_IEN_SEQDONE_MASK                     0x2UL                                /**< Bit mask for CRYPTO_SEQDONE */
+#define _CRYPTO_IEN_SEQDONE_DEFAULT                  0x00000000UL                         /**< Mode DEFAULT for CRYPTO_IEN */
+#define CRYPTO_IEN_SEQDONE_DEFAULT                   (_CRYPTO_IEN_SEQDONE_DEFAULT << 1)   /**< Shifted mode DEFAULT for CRYPTO_IEN */
+#define CRYPTO_IEN_BUFOF                             (0x1UL << 2)                         /**< BUFOF Interrupt Enable */
+#define _CRYPTO_IEN_BUFOF_SHIFT                      2                                    /**< Shift value for CRYPTO_BUFOF */
+#define _CRYPTO_IEN_BUFOF_MASK                       0x4UL                                /**< Bit mask for CRYPTO_BUFOF */
+#define _CRYPTO_IEN_BUFOF_DEFAULT                    0x00000000UL                         /**< Mode DEFAULT for CRYPTO_IEN */
+#define CRYPTO_IEN_BUFOF_DEFAULT                     (_CRYPTO_IEN_BUFOF_DEFAULT << 2)     /**< Shifted mode DEFAULT for CRYPTO_IEN */
+#define CRYPTO_IEN_BUFUF                             (0x1UL << 3)                         /**< BUFUF Interrupt Enable */
+#define _CRYPTO_IEN_BUFUF_SHIFT                      3                                    /**< Shift value for CRYPTO_BUFUF */
+#define _CRYPTO_IEN_BUFUF_MASK                       0x8UL                                /**< Bit mask for CRYPTO_BUFUF */
+#define _CRYPTO_IEN_BUFUF_DEFAULT                    0x00000000UL                         /**< Mode DEFAULT for CRYPTO_IEN */
+#define CRYPTO_IEN_BUFUF_DEFAULT                     (_CRYPTO_IEN_BUFUF_DEFAULT << 3)     /**< Shifted mode DEFAULT for CRYPTO_IEN */
+
+/* Bit fields for CRYPTO SEQ0 */
+#define _CRYPTO_SEQ0_RESETVALUE                      0x00000000UL                        /**< Default value for CRYPTO_SEQ0 */
+#define _CRYPTO_SEQ0_MASK                            0xFFFFFFFFUL                        /**< Mask for CRYPTO_SEQ0 */
+#define _CRYPTO_SEQ0_INSTR0_SHIFT                    0                                   /**< Shift value for CRYPTO_INSTR0 */
+#define _CRYPTO_SEQ0_INSTR0_MASK                     0xFFUL                              /**< Bit mask for CRYPTO_INSTR0 */
+#define _CRYPTO_SEQ0_INSTR0_DEFAULT                  0x00000000UL                        /**< Mode DEFAULT for CRYPTO_SEQ0 */
+#define CRYPTO_SEQ0_INSTR0_DEFAULT                   (_CRYPTO_SEQ0_INSTR0_DEFAULT << 0)  /**< Shifted mode DEFAULT for CRYPTO_SEQ0 */
+#define _CRYPTO_SEQ0_INSTR1_SHIFT                    8                                   /**< Shift value for CRYPTO_INSTR1 */
+#define _CRYPTO_SEQ0_INSTR1_MASK                     0xFF00UL                            /**< Bit mask for CRYPTO_INSTR1 */
+#define _CRYPTO_SEQ0_INSTR1_DEFAULT                  0x00000000UL                        /**< Mode DEFAULT for CRYPTO_SEQ0 */
+#define CRYPTO_SEQ0_INSTR1_DEFAULT                   (_CRYPTO_SEQ0_INSTR1_DEFAULT << 8)  /**< Shifted mode DEFAULT for CRYPTO_SEQ0 */
+#define _CRYPTO_SEQ0_INSTR2_SHIFT                    16                                  /**< Shift value for CRYPTO_INSTR2 */
+#define _CRYPTO_SEQ0_INSTR2_MASK                     0xFF0000UL                          /**< Bit mask for CRYPTO_INSTR2 */
+#define _CRYPTO_SEQ0_INSTR2_DEFAULT                  0x00000000UL                        /**< Mode DEFAULT for CRYPTO_SEQ0 */
+#define CRYPTO_SEQ0_INSTR2_DEFAULT                   (_CRYPTO_SEQ0_INSTR2_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_SEQ0 */
+#define _CRYPTO_SEQ0_INSTR3_SHIFT                    24                                  /**< Shift value for CRYPTO_INSTR3 */
+#define _CRYPTO_SEQ0_INSTR3_MASK                     0xFF000000UL                        /**< Bit mask for CRYPTO_INSTR3 */
+#define _CRYPTO_SEQ0_INSTR3_DEFAULT                  0x00000000UL                        /**< Mode DEFAULT for CRYPTO_SEQ0 */
+#define CRYPTO_SEQ0_INSTR3_DEFAULT                   (_CRYPTO_SEQ0_INSTR3_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_SEQ0 */
+
+/* Bit fields for CRYPTO SEQ1 */
+#define _CRYPTO_SEQ1_RESETVALUE                      0x00000000UL                        /**< Default value for CRYPTO_SEQ1 */
+#define _CRYPTO_SEQ1_MASK                            0xFFFFFFFFUL                        /**< Mask for CRYPTO_SEQ1 */
+#define _CRYPTO_SEQ1_INSTR4_SHIFT                    0                                   /**< Shift value for CRYPTO_INSTR4 */
+#define _CRYPTO_SEQ1_INSTR4_MASK                     0xFFUL                              /**< Bit mask for CRYPTO_INSTR4 */
+#define _CRYPTO_SEQ1_INSTR4_DEFAULT                  0x00000000UL                        /**< Mode DEFAULT for CRYPTO_SEQ1 */
+#define CRYPTO_SEQ1_INSTR4_DEFAULT                   (_CRYPTO_SEQ1_INSTR4_DEFAULT << 0)  /**< Shifted mode DEFAULT for CRYPTO_SEQ1 */
+#define _CRYPTO_SEQ1_INSTR5_SHIFT                    8                                   /**< Shift value for CRYPTO_INSTR5 */
+#define _CRYPTO_SEQ1_INSTR5_MASK                     0xFF00UL                            /**< Bit mask for CRYPTO_INSTR5 */
+#define _CRYPTO_SEQ1_INSTR5_DEFAULT                  0x00000000UL                        /**< Mode DEFAULT for CRYPTO_SEQ1 */
+#define CRYPTO_SEQ1_INSTR5_DEFAULT                   (_CRYPTO_SEQ1_INSTR5_DEFAULT << 8)  /**< Shifted mode DEFAULT for CRYPTO_SEQ1 */
+#define _CRYPTO_SEQ1_INSTR6_SHIFT                    16                                  /**< Shift value for CRYPTO_INSTR6 */
+#define _CRYPTO_SEQ1_INSTR6_MASK                     0xFF0000UL                          /**< Bit mask for CRYPTO_INSTR6 */
+#define _CRYPTO_SEQ1_INSTR6_DEFAULT                  0x00000000UL                        /**< Mode DEFAULT for CRYPTO_SEQ1 */
+#define CRYPTO_SEQ1_INSTR6_DEFAULT                   (_CRYPTO_SEQ1_INSTR6_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_SEQ1 */
+#define _CRYPTO_SEQ1_INSTR7_SHIFT                    24                                  /**< Shift value for CRYPTO_INSTR7 */
+#define _CRYPTO_SEQ1_INSTR7_MASK                     0xFF000000UL                        /**< Bit mask for CRYPTO_INSTR7 */
+#define _CRYPTO_SEQ1_INSTR7_DEFAULT                  0x00000000UL                        /**< Mode DEFAULT for CRYPTO_SEQ1 */
+#define CRYPTO_SEQ1_INSTR7_DEFAULT                   (_CRYPTO_SEQ1_INSTR7_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_SEQ1 */
+
+/* Bit fields for CRYPTO SEQ2 */
+#define _CRYPTO_SEQ2_RESETVALUE                      0x00000000UL                         /**< Default value for CRYPTO_SEQ2 */
+#define _CRYPTO_SEQ2_MASK                            0xFFFFFFFFUL                         /**< Mask for CRYPTO_SEQ2 */
+#define _CRYPTO_SEQ2_INSTR8_SHIFT                    0                                    /**< Shift value for CRYPTO_INSTR8 */
+#define _CRYPTO_SEQ2_INSTR8_MASK                     0xFFUL                               /**< Bit mask for CRYPTO_INSTR8 */
+#define _CRYPTO_SEQ2_INSTR8_DEFAULT                  0x00000000UL                         /**< Mode DEFAULT for CRYPTO_SEQ2 */
+#define CRYPTO_SEQ2_INSTR8_DEFAULT                   (_CRYPTO_SEQ2_INSTR8_DEFAULT << 0)   /**< Shifted mode DEFAULT for CRYPTO_SEQ2 */
+#define _CRYPTO_SEQ2_INSTR9_SHIFT                    8                                    /**< Shift value for CRYPTO_INSTR9 */
+#define _CRYPTO_SEQ2_INSTR9_MASK                     0xFF00UL                             /**< Bit mask for CRYPTO_INSTR9 */
+#define _CRYPTO_SEQ2_INSTR9_DEFAULT                  0x00000000UL                         /**< Mode DEFAULT for CRYPTO_SEQ2 */
+#define CRYPTO_SEQ2_INSTR9_DEFAULT                   (_CRYPTO_SEQ2_INSTR9_DEFAULT << 8)   /**< Shifted mode DEFAULT for CRYPTO_SEQ2 */
+#define _CRYPTO_SEQ2_INSTR10_SHIFT                   16                                   /**< Shift value for CRYPTO_INSTR10 */
+#define _CRYPTO_SEQ2_INSTR10_MASK                    0xFF0000UL                           /**< Bit mask for CRYPTO_INSTR10 */
+#define _CRYPTO_SEQ2_INSTR10_DEFAULT                 0x00000000UL                         /**< Mode DEFAULT for CRYPTO_SEQ2 */
+#define CRYPTO_SEQ2_INSTR10_DEFAULT                  (_CRYPTO_SEQ2_INSTR10_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_SEQ2 */
+#define _CRYPTO_SEQ2_INSTR11_SHIFT                   24                                   /**< Shift value for CRYPTO_INSTR11 */
+#define _CRYPTO_SEQ2_INSTR11_MASK                    0xFF000000UL                         /**< Bit mask for CRYPTO_INSTR11 */
+#define _CRYPTO_SEQ2_INSTR11_DEFAULT                 0x00000000UL                         /**< Mode DEFAULT for CRYPTO_SEQ2 */
+#define CRYPTO_SEQ2_INSTR11_DEFAULT                  (_CRYPTO_SEQ2_INSTR11_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_SEQ2 */
+
+/* Bit fields for CRYPTO SEQ3 */
+#define _CRYPTO_SEQ3_RESETVALUE                      0x00000000UL                         /**< Default value for CRYPTO_SEQ3 */
+#define _CRYPTO_SEQ3_MASK                            0xFFFFFFFFUL                         /**< Mask for CRYPTO_SEQ3 */
+#define _CRYPTO_SEQ3_INSTR12_SHIFT                   0                                    /**< Shift value for CRYPTO_INSTR12 */
+#define _CRYPTO_SEQ3_INSTR12_MASK                    0xFFUL                               /**< Bit mask for CRYPTO_INSTR12 */
+#define _CRYPTO_SEQ3_INSTR12_DEFAULT                 0x00000000UL                         /**< Mode DEFAULT for CRYPTO_SEQ3 */
+#define CRYPTO_SEQ3_INSTR12_DEFAULT                  (_CRYPTO_SEQ3_INSTR12_DEFAULT << 0)  /**< Shifted mode DEFAULT for CRYPTO_SEQ3 */
+#define _CRYPTO_SEQ3_INSTR13_SHIFT                   8                                    /**< Shift value for CRYPTO_INSTR13 */
+#define _CRYPTO_SEQ3_INSTR13_MASK                    0xFF00UL                             /**< Bit mask for CRYPTO_INSTR13 */
+#define _CRYPTO_SEQ3_INSTR13_DEFAULT                 0x00000000UL                         /**< Mode DEFAULT for CRYPTO_SEQ3 */
+#define CRYPTO_SEQ3_INSTR13_DEFAULT                  (_CRYPTO_SEQ3_INSTR13_DEFAULT << 8)  /**< Shifted mode DEFAULT for CRYPTO_SEQ3 */
+#define _CRYPTO_SEQ3_INSTR14_SHIFT                   16                                   /**< Shift value for CRYPTO_INSTR14 */
+#define _CRYPTO_SEQ3_INSTR14_MASK                    0xFF0000UL                           /**< Bit mask for CRYPTO_INSTR14 */
+#define _CRYPTO_SEQ3_INSTR14_DEFAULT                 0x00000000UL                         /**< Mode DEFAULT for CRYPTO_SEQ3 */
+#define CRYPTO_SEQ3_INSTR14_DEFAULT                  (_CRYPTO_SEQ3_INSTR14_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_SEQ3 */
+#define _CRYPTO_SEQ3_INSTR15_SHIFT                   24                                   /**< Shift value for CRYPTO_INSTR15 */
+#define _CRYPTO_SEQ3_INSTR15_MASK                    0xFF000000UL                         /**< Bit mask for CRYPTO_INSTR15 */
+#define _CRYPTO_SEQ3_INSTR15_DEFAULT                 0x00000000UL                         /**< Mode DEFAULT for CRYPTO_SEQ3 */
+#define CRYPTO_SEQ3_INSTR15_DEFAULT                  (_CRYPTO_SEQ3_INSTR15_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_SEQ3 */
+
+/* Bit fields for CRYPTO SEQ4 */
+#define _CRYPTO_SEQ4_RESETVALUE                      0x00000000UL                         /**< Default value for CRYPTO_SEQ4 */
+#define _CRYPTO_SEQ4_MASK                            0xFFFFFFFFUL                         /**< Mask for CRYPTO_SEQ4 */
+#define _CRYPTO_SEQ4_INSTR16_SHIFT                   0                                    /**< Shift value for CRYPTO_INSTR16 */
+#define _CRYPTO_SEQ4_INSTR16_MASK                    0xFFUL                               /**< Bit mask for CRYPTO_INSTR16 */
+#define _CRYPTO_SEQ4_INSTR16_DEFAULT                 0x00000000UL                         /**< Mode DEFAULT for CRYPTO_SEQ4 */
+#define CRYPTO_SEQ4_INSTR16_DEFAULT                  (_CRYPTO_SEQ4_INSTR16_DEFAULT << 0)  /**< Shifted mode DEFAULT for CRYPTO_SEQ4 */
+#define _CRYPTO_SEQ4_INSTR17_SHIFT                   8                                    /**< Shift value for CRYPTO_INSTR17 */
+#define _CRYPTO_SEQ4_INSTR17_MASK                    0xFF00UL                             /**< Bit mask for CRYPTO_INSTR17 */
+#define _CRYPTO_SEQ4_INSTR17_DEFAULT                 0x00000000UL                         /**< Mode DEFAULT for CRYPTO_SEQ4 */
+#define CRYPTO_SEQ4_INSTR17_DEFAULT                  (_CRYPTO_SEQ4_INSTR17_DEFAULT << 8)  /**< Shifted mode DEFAULT for CRYPTO_SEQ4 */
+#define _CRYPTO_SEQ4_INSTR18_SHIFT                   16                                   /**< Shift value for CRYPTO_INSTR18 */
+#define _CRYPTO_SEQ4_INSTR18_MASK                    0xFF0000UL                           /**< Bit mask for CRYPTO_INSTR18 */
+#define _CRYPTO_SEQ4_INSTR18_DEFAULT                 0x00000000UL                         /**< Mode DEFAULT for CRYPTO_SEQ4 */
+#define CRYPTO_SEQ4_INSTR18_DEFAULT                  (_CRYPTO_SEQ4_INSTR18_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_SEQ4 */
+#define _CRYPTO_SEQ4_INSTR19_SHIFT                   24                                   /**< Shift value for CRYPTO_INSTR19 */
+#define _CRYPTO_SEQ4_INSTR19_MASK                    0xFF000000UL                         /**< Bit mask for CRYPTO_INSTR19 */
+#define _CRYPTO_SEQ4_INSTR19_DEFAULT                 0x00000000UL                         /**< Mode DEFAULT for CRYPTO_SEQ4 */
+#define CRYPTO_SEQ4_INSTR19_DEFAULT                  (_CRYPTO_SEQ4_INSTR19_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_SEQ4 */
+
+/* Bit fields for CRYPTO DATA0 */
+#define _CRYPTO_DATA0_RESETVALUE                     0x00000000UL                       /**< Default value for CRYPTO_DATA0 */
+#define _CRYPTO_DATA0_MASK                           0xFFFFFFFFUL                       /**< Mask for CRYPTO_DATA0 */
+#define _CRYPTO_DATA0_DATA0_SHIFT                    0                                  /**< Shift value for CRYPTO_DATA0 */
+#define _CRYPTO_DATA0_DATA0_MASK                     0xFFFFFFFFUL                       /**< Bit mask for CRYPTO_DATA0 */
+#define _CRYPTO_DATA0_DATA0_DEFAULT                  0x00000000UL                       /**< Mode DEFAULT for CRYPTO_DATA0 */
+#define CRYPTO_DATA0_DATA0_DEFAULT                   (_CRYPTO_DATA0_DATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0 */
+
+/* Bit fields for CRYPTO DATA1 */
+#define _CRYPTO_DATA1_RESETVALUE                     0x00000000UL                       /**< Default value for CRYPTO_DATA1 */
+#define _CRYPTO_DATA1_MASK                           0xFFFFFFFFUL                       /**< Mask for CRYPTO_DATA1 */
+#define _CRYPTO_DATA1_DATA1_SHIFT                    0                                  /**< Shift value for CRYPTO_DATA1 */
+#define _CRYPTO_DATA1_DATA1_MASK                     0xFFFFFFFFUL                       /**< Bit mask for CRYPTO_DATA1 */
+#define _CRYPTO_DATA1_DATA1_DEFAULT                  0x00000000UL                       /**< Mode DEFAULT for CRYPTO_DATA1 */
+#define CRYPTO_DATA1_DATA1_DEFAULT                   (_CRYPTO_DATA1_DATA1_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA1 */
+
+/* Bit fields for CRYPTO DATA2 */
+#define _CRYPTO_DATA2_RESETVALUE                     0x00000000UL                       /**< Default value for CRYPTO_DATA2 */
+#define _CRYPTO_DATA2_MASK                           0xFFFFFFFFUL                       /**< Mask for CRYPTO_DATA2 */
+#define _CRYPTO_DATA2_DATA2_SHIFT                    0                                  /**< Shift value for CRYPTO_DATA2 */
+#define _CRYPTO_DATA2_DATA2_MASK                     0xFFFFFFFFUL                       /**< Bit mask for CRYPTO_DATA2 */
+#define _CRYPTO_DATA2_DATA2_DEFAULT                  0x00000000UL                       /**< Mode DEFAULT for CRYPTO_DATA2 */
+#define CRYPTO_DATA2_DATA2_DEFAULT                   (_CRYPTO_DATA2_DATA2_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA2 */
+
+/* Bit fields for CRYPTO DATA3 */
+#define _CRYPTO_DATA3_RESETVALUE                     0x00000000UL                       /**< Default value for CRYPTO_DATA3 */
+#define _CRYPTO_DATA3_MASK                           0xFFFFFFFFUL                       /**< Mask for CRYPTO_DATA3 */
+#define _CRYPTO_DATA3_DATA3_SHIFT                    0                                  /**< Shift value for CRYPTO_DATA3 */
+#define _CRYPTO_DATA3_DATA3_MASK                     0xFFFFFFFFUL                       /**< Bit mask for CRYPTO_DATA3 */
+#define _CRYPTO_DATA3_DATA3_DEFAULT                  0x00000000UL                       /**< Mode DEFAULT for CRYPTO_DATA3 */
+#define CRYPTO_DATA3_DATA3_DEFAULT                   (_CRYPTO_DATA3_DATA3_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA3 */
+
+/* Bit fields for CRYPTO DATA0XOR */
+#define _CRYPTO_DATA0XOR_RESETVALUE                  0x00000000UL                             /**< Default value for CRYPTO_DATA0XOR */
+#define _CRYPTO_DATA0XOR_MASK                        0xFFFFFFFFUL                             /**< Mask for CRYPTO_DATA0XOR */
+#define _CRYPTO_DATA0XOR_DATA0XOR_SHIFT              0                                        /**< Shift value for CRYPTO_DATA0XOR */
+#define _CRYPTO_DATA0XOR_DATA0XOR_MASK               0xFFFFFFFFUL                             /**< Bit mask for CRYPTO_DATA0XOR */
+#define _CRYPTO_DATA0XOR_DATA0XOR_DEFAULT            0x00000000UL                             /**< Mode DEFAULT for CRYPTO_DATA0XOR */
+#define CRYPTO_DATA0XOR_DATA0XOR_DEFAULT             (_CRYPTO_DATA0XOR_DATA0XOR_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0XOR */
+
+/* Bit fields for CRYPTO DATA0BYTE */
+#define _CRYPTO_DATA0BYTE_RESETVALUE                 0x00000000UL                               /**< Default value for CRYPTO_DATA0BYTE */
+#define _CRYPTO_DATA0BYTE_MASK                       0x000000FFUL                               /**< Mask for CRYPTO_DATA0BYTE */
+#define _CRYPTO_DATA0BYTE_DATA0BYTE_SHIFT            0                                          /**< Shift value for CRYPTO_DATA0BYTE */
+#define _CRYPTO_DATA0BYTE_DATA0BYTE_MASK             0xFFUL                                     /**< Bit mask for CRYPTO_DATA0BYTE */
+#define _CRYPTO_DATA0BYTE_DATA0BYTE_DEFAULT          0x00000000UL                               /**< Mode DEFAULT for CRYPTO_DATA0BYTE */
+#define CRYPTO_DATA0BYTE_DATA0BYTE_DEFAULT           (_CRYPTO_DATA0BYTE_DATA0BYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0BYTE */
+
+/* Bit fields for CRYPTO DATA1BYTE */
+#define _CRYPTO_DATA1BYTE_RESETVALUE                 0x00000000UL                               /**< Default value for CRYPTO_DATA1BYTE */
+#define _CRYPTO_DATA1BYTE_MASK                       0x000000FFUL                               /**< Mask for CRYPTO_DATA1BYTE */
+#define _CRYPTO_DATA1BYTE_DATA1BYTE_SHIFT            0                                          /**< Shift value for CRYPTO_DATA1BYTE */
+#define _CRYPTO_DATA1BYTE_DATA1BYTE_MASK             0xFFUL                                     /**< Bit mask for CRYPTO_DATA1BYTE */
+#define _CRYPTO_DATA1BYTE_DATA1BYTE_DEFAULT          0x00000000UL                               /**< Mode DEFAULT for CRYPTO_DATA1BYTE */
+#define CRYPTO_DATA1BYTE_DATA1BYTE_DEFAULT           (_CRYPTO_DATA1BYTE_DATA1BYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA1BYTE */
+
+/* Bit fields for CRYPTO DATA0XORBYTE */
+#define _CRYPTO_DATA0XORBYTE_RESETVALUE              0x00000000UL                                     /**< Default value for CRYPTO_DATA0XORBYTE */
+#define _CRYPTO_DATA0XORBYTE_MASK                    0x000000FFUL                                     /**< Mask for CRYPTO_DATA0XORBYTE */
+#define _CRYPTO_DATA0XORBYTE_DATA0XORBYTE_SHIFT      0                                                /**< Shift value for CRYPTO_DATA0XORBYTE */
+#define _CRYPTO_DATA0XORBYTE_DATA0XORBYTE_MASK       0xFFUL                                           /**< Bit mask for CRYPTO_DATA0XORBYTE */
+#define _CRYPTO_DATA0XORBYTE_DATA0XORBYTE_DEFAULT    0x00000000UL                                     /**< Mode DEFAULT for CRYPTO_DATA0XORBYTE */
+#define CRYPTO_DATA0XORBYTE_DATA0XORBYTE_DEFAULT     (_CRYPTO_DATA0XORBYTE_DATA0XORBYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0XORBYTE */
+
+/* Bit fields for CRYPTO DATA0BYTE12 */
+#define _CRYPTO_DATA0BYTE12_RESETVALUE               0x00000000UL                                   /**< Default value for CRYPTO_DATA0BYTE12 */
+#define _CRYPTO_DATA0BYTE12_MASK                     0x000000FFUL                                   /**< Mask for CRYPTO_DATA0BYTE12 */
+#define _CRYPTO_DATA0BYTE12_DATA0BYTE12_SHIFT        0                                              /**< Shift value for CRYPTO_DATA0BYTE12 */
+#define _CRYPTO_DATA0BYTE12_DATA0BYTE12_MASK         0xFFUL                                         /**< Bit mask for CRYPTO_DATA0BYTE12 */
+#define _CRYPTO_DATA0BYTE12_DATA0BYTE12_DEFAULT      0x00000000UL                                   /**< Mode DEFAULT for CRYPTO_DATA0BYTE12 */
+#define CRYPTO_DATA0BYTE12_DATA0BYTE12_DEFAULT       (_CRYPTO_DATA0BYTE12_DATA0BYTE12_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0BYTE12 */
+
+/* Bit fields for CRYPTO DATA0BYTE13 */
+#define _CRYPTO_DATA0BYTE13_RESETVALUE               0x00000000UL                                   /**< Default value for CRYPTO_DATA0BYTE13 */
+#define _CRYPTO_DATA0BYTE13_MASK                     0x000000FFUL                                   /**< Mask for CRYPTO_DATA0BYTE13 */
+#define _CRYPTO_DATA0BYTE13_DATA0BYTE13_SHIFT        0                                              /**< Shift value for CRYPTO_DATA0BYTE13 */
+#define _CRYPTO_DATA0BYTE13_DATA0BYTE13_MASK         0xFFUL                                         /**< Bit mask for CRYPTO_DATA0BYTE13 */
+#define _CRYPTO_DATA0BYTE13_DATA0BYTE13_DEFAULT      0x00000000UL                                   /**< Mode DEFAULT for CRYPTO_DATA0BYTE13 */
+#define CRYPTO_DATA0BYTE13_DATA0BYTE13_DEFAULT       (_CRYPTO_DATA0BYTE13_DATA0BYTE13_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0BYTE13 */
+
+/* Bit fields for CRYPTO DATA0BYTE14 */
+#define _CRYPTO_DATA0BYTE14_RESETVALUE               0x00000000UL                                   /**< Default value for CRYPTO_DATA0BYTE14 */
+#define _CRYPTO_DATA0BYTE14_MASK                     0x000000FFUL                                   /**< Mask for CRYPTO_DATA0BYTE14 */
+#define _CRYPTO_DATA0BYTE14_DATA0BYTE14_SHIFT        0                                              /**< Shift value for CRYPTO_DATA0BYTE14 */
+#define _CRYPTO_DATA0BYTE14_DATA0BYTE14_MASK         0xFFUL                                         /**< Bit mask for CRYPTO_DATA0BYTE14 */
+#define _CRYPTO_DATA0BYTE14_DATA0BYTE14_DEFAULT      0x00000000UL                                   /**< Mode DEFAULT for CRYPTO_DATA0BYTE14 */
+#define CRYPTO_DATA0BYTE14_DATA0BYTE14_DEFAULT       (_CRYPTO_DATA0BYTE14_DATA0BYTE14_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0BYTE14 */
+
+/* Bit fields for CRYPTO DATA0BYTE15 */
+#define _CRYPTO_DATA0BYTE15_RESETVALUE               0x00000000UL                                   /**< Default value for CRYPTO_DATA0BYTE15 */
+#define _CRYPTO_DATA0BYTE15_MASK                     0x000000FFUL                                   /**< Mask for CRYPTO_DATA0BYTE15 */
+#define _CRYPTO_DATA0BYTE15_DATA0BYTE15_SHIFT        0                                              /**< Shift value for CRYPTO_DATA0BYTE15 */
+#define _CRYPTO_DATA0BYTE15_DATA0BYTE15_MASK         0xFFUL                                         /**< Bit mask for CRYPTO_DATA0BYTE15 */
+#define _CRYPTO_DATA0BYTE15_DATA0BYTE15_DEFAULT      0x00000000UL                                   /**< Mode DEFAULT for CRYPTO_DATA0BYTE15 */
+#define CRYPTO_DATA0BYTE15_DATA0BYTE15_DEFAULT       (_CRYPTO_DATA0BYTE15_DATA0BYTE15_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0BYTE15 */
+
+/* Bit fields for CRYPTO DDATA0 */
+#define _CRYPTO_DDATA0_RESETVALUE                    0x00000000UL                         /**< Default value for CRYPTO_DDATA0 */
+#define _CRYPTO_DDATA0_MASK                          0xFFFFFFFFUL                         /**< Mask for CRYPTO_DDATA0 */
+#define _CRYPTO_DDATA0_DDATA0_SHIFT                  0                                    /**< Shift value for CRYPTO_DDATA0 */
+#define _CRYPTO_DDATA0_DDATA0_MASK                   0xFFFFFFFFUL                         /**< Bit mask for CRYPTO_DDATA0 */
+#define _CRYPTO_DDATA0_DDATA0_DEFAULT                0x00000000UL                         /**< Mode DEFAULT for CRYPTO_DDATA0 */
+#define CRYPTO_DDATA0_DDATA0_DEFAULT                 (_CRYPTO_DDATA0_DDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA0 */
+
+/* Bit fields for CRYPTO DDATA1 */
+#define _CRYPTO_DDATA1_RESETVALUE                    0x00000000UL                         /**< Default value for CRYPTO_DDATA1 */
+#define _CRYPTO_DDATA1_MASK                          0xFFFFFFFFUL                         /**< Mask for CRYPTO_DDATA1 */
+#define _CRYPTO_DDATA1_DDATA1_SHIFT                  0                                    /**< Shift value for CRYPTO_DDATA1 */
+#define _CRYPTO_DDATA1_DDATA1_MASK                   0xFFFFFFFFUL                         /**< Bit mask for CRYPTO_DDATA1 */
+#define _CRYPTO_DDATA1_DDATA1_DEFAULT                0x00000000UL                         /**< Mode DEFAULT for CRYPTO_DDATA1 */
+#define CRYPTO_DDATA1_DDATA1_DEFAULT                 (_CRYPTO_DDATA1_DDATA1_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA1 */
+
+/* Bit fields for CRYPTO DDATA2 */
+#define _CRYPTO_DDATA2_RESETVALUE                    0x00000000UL                         /**< Default value for CRYPTO_DDATA2 */
+#define _CRYPTO_DDATA2_MASK                          0xFFFFFFFFUL                         /**< Mask for CRYPTO_DDATA2 */
+#define _CRYPTO_DDATA2_DDATA2_SHIFT                  0                                    /**< Shift value for CRYPTO_DDATA2 */
+#define _CRYPTO_DDATA2_DDATA2_MASK                   0xFFFFFFFFUL                         /**< Bit mask for CRYPTO_DDATA2 */
+#define _CRYPTO_DDATA2_DDATA2_DEFAULT                0x00000000UL                         /**< Mode DEFAULT for CRYPTO_DDATA2 */
+#define CRYPTO_DDATA2_DDATA2_DEFAULT                 (_CRYPTO_DDATA2_DDATA2_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA2 */
+
+/* Bit fields for CRYPTO DDATA3 */
+#define _CRYPTO_DDATA3_RESETVALUE                    0x00000000UL                         /**< Default value for CRYPTO_DDATA3 */
+#define _CRYPTO_DDATA3_MASK                          0xFFFFFFFFUL                         /**< Mask for CRYPTO_DDATA3 */
+#define _CRYPTO_DDATA3_DDATA3_SHIFT                  0                                    /**< Shift value for CRYPTO_DDATA3 */
+#define _CRYPTO_DDATA3_DDATA3_MASK                   0xFFFFFFFFUL                         /**< Bit mask for CRYPTO_DDATA3 */
+#define _CRYPTO_DDATA3_DDATA3_DEFAULT                0x00000000UL                         /**< Mode DEFAULT for CRYPTO_DDATA3 */
+#define CRYPTO_DDATA3_DDATA3_DEFAULT                 (_CRYPTO_DDATA3_DDATA3_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA3 */
+
+/* Bit fields for CRYPTO DDATA4 */
+#define _CRYPTO_DDATA4_RESETVALUE                    0x00000000UL                         /**< Default value for CRYPTO_DDATA4 */
+#define _CRYPTO_DDATA4_MASK                          0xFFFFFFFFUL                         /**< Mask for CRYPTO_DDATA4 */
+#define _CRYPTO_DDATA4_DDATA4_SHIFT                  0                                    /**< Shift value for CRYPTO_DDATA4 */
+#define _CRYPTO_DDATA4_DDATA4_MASK                   0xFFFFFFFFUL                         /**< Bit mask for CRYPTO_DDATA4 */
+#define _CRYPTO_DDATA4_DDATA4_DEFAULT                0x00000000UL                         /**< Mode DEFAULT for CRYPTO_DDATA4 */
+#define CRYPTO_DDATA4_DDATA4_DEFAULT                 (_CRYPTO_DDATA4_DDATA4_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA4 */
+
+/* Bit fields for CRYPTO DDATA0BIG */
+#define _CRYPTO_DDATA0BIG_RESETVALUE                 0x00000000UL                               /**< Default value for CRYPTO_DDATA0BIG */
+#define _CRYPTO_DDATA0BIG_MASK                       0xFFFFFFFFUL                               /**< Mask for CRYPTO_DDATA0BIG */
+#define _CRYPTO_DDATA0BIG_DDATA0BIG_SHIFT            0                                          /**< Shift value for CRYPTO_DDATA0BIG */
+#define _CRYPTO_DDATA0BIG_DDATA0BIG_MASK             0xFFFFFFFFUL                               /**< Bit mask for CRYPTO_DDATA0BIG */
+#define _CRYPTO_DDATA0BIG_DDATA0BIG_DEFAULT          0x00000000UL                               /**< Mode DEFAULT for CRYPTO_DDATA0BIG */
+#define CRYPTO_DDATA0BIG_DDATA0BIG_DEFAULT           (_CRYPTO_DDATA0BIG_DDATA0BIG_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA0BIG */
+
+/* Bit fields for CRYPTO DDATA0BYTE */
+#define _CRYPTO_DDATA0BYTE_RESETVALUE                0x00000000UL                                 /**< Default value for CRYPTO_DDATA0BYTE */
+#define _CRYPTO_DDATA0BYTE_MASK                      0x000000FFUL                                 /**< Mask for CRYPTO_DDATA0BYTE */
+#define _CRYPTO_DDATA0BYTE_DDATA0BYTE_SHIFT          0                                            /**< Shift value for CRYPTO_DDATA0BYTE */
+#define _CRYPTO_DDATA0BYTE_DDATA0BYTE_MASK           0xFFUL                                       /**< Bit mask for CRYPTO_DDATA0BYTE */
+#define _CRYPTO_DDATA0BYTE_DDATA0BYTE_DEFAULT        0x00000000UL                                 /**< Mode DEFAULT for CRYPTO_DDATA0BYTE */
+#define CRYPTO_DDATA0BYTE_DDATA0BYTE_DEFAULT         (_CRYPTO_DDATA0BYTE_DDATA0BYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA0BYTE */
+
+/* Bit fields for CRYPTO DDATA1BYTE */
+#define _CRYPTO_DDATA1BYTE_RESETVALUE                0x00000000UL                                 /**< Default value for CRYPTO_DDATA1BYTE */
+#define _CRYPTO_DDATA1BYTE_MASK                      0x000000FFUL                                 /**< Mask for CRYPTO_DDATA1BYTE */
+#define _CRYPTO_DDATA1BYTE_DDATA1BYTE_SHIFT          0                                            /**< Shift value for CRYPTO_DDATA1BYTE */
+#define _CRYPTO_DDATA1BYTE_DDATA1BYTE_MASK           0xFFUL                                       /**< Bit mask for CRYPTO_DDATA1BYTE */
+#define _CRYPTO_DDATA1BYTE_DDATA1BYTE_DEFAULT        0x00000000UL                                 /**< Mode DEFAULT for CRYPTO_DDATA1BYTE */
+#define CRYPTO_DDATA1BYTE_DDATA1BYTE_DEFAULT         (_CRYPTO_DDATA1BYTE_DDATA1BYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA1BYTE */
+
+/* Bit fields for CRYPTO DDATA0BYTE32 */
+#define _CRYPTO_DDATA0BYTE32_RESETVALUE              0x00000000UL                                     /**< Default value for CRYPTO_DDATA0BYTE32 */
+#define _CRYPTO_DDATA0BYTE32_MASK                    0x0000000FUL                                     /**< Mask for CRYPTO_DDATA0BYTE32 */
+#define _CRYPTO_DDATA0BYTE32_DDATA0BYTE32_SHIFT      0                                                /**< Shift value for CRYPTO_DDATA0BYTE32 */
+#define _CRYPTO_DDATA0BYTE32_DDATA0BYTE32_MASK       0xFUL                                            /**< Bit mask for CRYPTO_DDATA0BYTE32 */
+#define _CRYPTO_DDATA0BYTE32_DDATA0BYTE32_DEFAULT    0x00000000UL                                     /**< Mode DEFAULT for CRYPTO_DDATA0BYTE32 */
+#define CRYPTO_DDATA0BYTE32_DDATA0BYTE32_DEFAULT     (_CRYPTO_DDATA0BYTE32_DDATA0BYTE32_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA0BYTE32 */
+
+/* Bit fields for CRYPTO QDATA0 */
+#define _CRYPTO_QDATA0_RESETVALUE                    0x00000000UL                         /**< Default value for CRYPTO_QDATA0 */
+#define _CRYPTO_QDATA0_MASK                          0xFFFFFFFFUL                         /**< Mask for CRYPTO_QDATA0 */
+#define _CRYPTO_QDATA0_QDATA0_SHIFT                  0                                    /**< Shift value for CRYPTO_QDATA0 */
+#define _CRYPTO_QDATA0_QDATA0_MASK                   0xFFFFFFFFUL                         /**< Bit mask for CRYPTO_QDATA0 */
+#define _CRYPTO_QDATA0_QDATA0_DEFAULT                0x00000000UL                         /**< Mode DEFAULT for CRYPTO_QDATA0 */
+#define CRYPTO_QDATA0_QDATA0_DEFAULT                 (_CRYPTO_QDATA0_QDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_QDATA0 */
+
+/* Bit fields for CRYPTO QDATA1 */
+#define _CRYPTO_QDATA1_RESETVALUE                    0x00000000UL                         /**< Default value for CRYPTO_QDATA1 */
+#define _CRYPTO_QDATA1_MASK                          0xFFFFFFFFUL                         /**< Mask for CRYPTO_QDATA1 */
+#define _CRYPTO_QDATA1_QDATA1_SHIFT                  0                                    /**< Shift value for CRYPTO_QDATA1 */
+#define _CRYPTO_QDATA1_QDATA1_MASK                   0xFFFFFFFFUL                         /**< Bit mask for CRYPTO_QDATA1 */
+#define _CRYPTO_QDATA1_QDATA1_DEFAULT                0x00000000UL                         /**< Mode DEFAULT for CRYPTO_QDATA1 */
+#define CRYPTO_QDATA1_QDATA1_DEFAULT                 (_CRYPTO_QDATA1_QDATA1_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_QDATA1 */
+
+/* Bit fields for CRYPTO QDATA1BIG */
+#define _CRYPTO_QDATA1BIG_RESETVALUE                 0x00000000UL                               /**< Default value for CRYPTO_QDATA1BIG */
+#define _CRYPTO_QDATA1BIG_MASK                       0xFFFFFFFFUL                               /**< Mask for CRYPTO_QDATA1BIG */
+#define _CRYPTO_QDATA1BIG_QDATA1BIG_SHIFT            0                                          /**< Shift value for CRYPTO_QDATA1BIG */
+#define _CRYPTO_QDATA1BIG_QDATA1BIG_MASK             0xFFFFFFFFUL                               /**< Bit mask for CRYPTO_QDATA1BIG */
+#define _CRYPTO_QDATA1BIG_QDATA1BIG_DEFAULT          0x00000000UL                               /**< Mode DEFAULT for CRYPTO_QDATA1BIG */
+#define CRYPTO_QDATA1BIG_QDATA1BIG_DEFAULT           (_CRYPTO_QDATA1BIG_QDATA1BIG_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_QDATA1BIG */
+
+/* Bit fields for CRYPTO QDATA0BYTE */
+#define _CRYPTO_QDATA0BYTE_RESETVALUE                0x00000000UL                                 /**< Default value for CRYPTO_QDATA0BYTE */
+#define _CRYPTO_QDATA0BYTE_MASK                      0x000000FFUL                                 /**< Mask for CRYPTO_QDATA0BYTE */
+#define _CRYPTO_QDATA0BYTE_QDATA0BYTE_SHIFT          0                                            /**< Shift value for CRYPTO_QDATA0BYTE */
+#define _CRYPTO_QDATA0BYTE_QDATA0BYTE_MASK           0xFFUL                                       /**< Bit mask for CRYPTO_QDATA0BYTE */
+#define _CRYPTO_QDATA0BYTE_QDATA0BYTE_DEFAULT        0x00000000UL                                 /**< Mode DEFAULT for CRYPTO_QDATA0BYTE */
+#define CRYPTO_QDATA0BYTE_QDATA0BYTE_DEFAULT         (_CRYPTO_QDATA0BYTE_QDATA0BYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_QDATA0BYTE */
+
+/* Bit fields for CRYPTO QDATA1BYTE */
+#define _CRYPTO_QDATA1BYTE_RESETVALUE                0x00000000UL                                 /**< Default value for CRYPTO_QDATA1BYTE */
+#define _CRYPTO_QDATA1BYTE_MASK                      0x000000FFUL                                 /**< Mask for CRYPTO_QDATA1BYTE */
+#define _CRYPTO_QDATA1BYTE_QDATA1BYTE_SHIFT          0                                            /**< Shift value for CRYPTO_QDATA1BYTE */
+#define _CRYPTO_QDATA1BYTE_QDATA1BYTE_MASK           0xFFUL                                       /**< Bit mask for CRYPTO_QDATA1BYTE */
+#define _CRYPTO_QDATA1BYTE_QDATA1BYTE_DEFAULT        0x00000000UL                                 /**< Mode DEFAULT for CRYPTO_QDATA1BYTE */
+#define CRYPTO_QDATA1BYTE_QDATA1BYTE_DEFAULT         (_CRYPTO_QDATA1BYTE_QDATA1BYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_QDATA1BYTE */
+
+/** @} End of group EFM32PG1B_CRYPTO */
+/** @} End of group Parts */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG_STK3401/efm32pg1b_devinfo.h	Fri Jan 15 07:45:16 2016 +0000
@@ -0,0 +1,754 @@
+/**************************************************************************//**
+ * @file efm32pg1b_devinfo.h
+ * @brief EFM32PG1B_DEVINFO register and bit field definitions
+ * @version 4.2.0
+ ******************************************************************************
+ * @section License
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ ******************************************************************************
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software.@n
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.@n
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is
+ * providing the Software "AS IS", with no express or implied warranties of any
+ * kind, including, but not limited to, any implied warranties of
+ * merchantability or fitness for any particular purpose or warranties against
+ * infringement of any proprietary rights of a third party.
+ *
+ * Silicon Laboratories, Inc. will not be liable for any consequential,
+ * incidental, or special damages, or any other relief, or for any claim by
+ * any third party, arising from your use of this Software.
+ *
+ *****************************************************************************/
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFM32PG1B_DEVINFO
+ * @{
+ *****************************************************************************/
+
+typedef struct
+{
+  __I uint32_t CAL;              /**< CRC of DI-page and calibration temperature  */
+  uint32_t     RESERVED0[9];     /**< Reserved for future use **/
+  __I uint32_t EUI48L;           /**< EUI48 OUI and Unique identifier  */
+  __I uint32_t EUI48H;           /**< OUI  */
+  __I uint32_t CUSTOMINFO;       /**< Custom information  */
+  __I uint32_t MEMINFO;          /**< Flash page size and misc. chip information  */
+  uint32_t     RESERVED1[2];     /**< Reserved for future use **/
+  __I uint32_t UNIQUEL;          /**< Low 32 bits of device unique number  */
+  __I uint32_t UNIQUEH;          /**< High 32 bits of device unique number  */
+  __I uint32_t MSIZE;            /**< Flash and SRAM Memory size in kB  */
+  __I uint32_t PART;             /**< Part description  */
+  __I uint32_t DEVINFOREV;       /**< Device information page revision  */
+  __I uint32_t EMUTEMP;          /**< EMU Temperature Calibration Information  */
+  uint32_t     RESERVED2[2];     /**< Reserved for future use **/
+  __I uint32_t ADC0CAL0;         /**< ADC0 calibration register 0  */
+  __I uint32_t ADC0CAL1;         /**< ADC0 calibration register 1  */
+  __I uint32_t ADC0CAL2;         /**< ADC0 calibration register 2  */
+  __I uint32_t ADC0CAL3;         /**< ADC0 calibration register 3  */
+  uint32_t     RESERVED3[4];     /**< Reserved for future use **/
+  __I uint32_t HFRCOCAL0;        /**< HFRCO Calibration Register (4 MHz)  */
+  uint32_t     RESERVED4[2];     /**< Reserved for future use **/
+  __I uint32_t HFRCOCAL3;        /**< HFRCO Calibration Register (7 MHz)  */
+  uint32_t     RESERVED5[2];     /**< Reserved for future use **/
+  __I uint32_t HFRCOCAL6;        /**< HFRCO Calibration Register (13 MHz)  */
+  __I uint32_t HFRCOCAL7;        /**< HFRCO Calibration Register (16 MHz)  */
+  __I uint32_t HFRCOCAL8;        /**< HFRCO Calibration Register (19 MHz)  */
+  uint32_t     RESERVED6[1];     /**< Reserved for future use **/
+  __I uint32_t HFRCOCAL10;       /**< HFRCO Calibration Register (26 MHz)  */
+  __I uint32_t HFRCOCAL11;       /**< HFRCO Calibration Register (32 MHz)  */
+  __I uint32_t HFRCOCAL12;       /**< HFRCO Calibration Register (38 MHz)  */
+  uint32_t     RESERVED7[11];    /**< Reserved for future use **/
+  __I uint32_t AUXHFRCOCAL0;     /**< AUXHFRCO Calibration Register (4 MHz)  */
+  uint32_t     RESERVED8[2];     /**< Reserved for future use **/
+  __I uint32_t AUXHFRCOCAL3;     /**< AUXHFRCO Calibration Register (7 MHz)  */
+  uint32_t     RESERVED9[2];     /**< Reserved for future use **/
+  __I uint32_t AUXHFRCOCAL6;     /**< AUXHFRCO Calibration Register (13 MHz)  */
+  __I uint32_t AUXHFRCOCAL7;     /**< AUXHFRCO Calibration Register (16 MHz)  */
+  __I uint32_t AUXHFRCOCAL8;     /**< AUXHFRCO Calibration Register (19 MHz)  */
+  uint32_t     RESERVED10[1];    /**< Reserved for future use **/
+  __I uint32_t AUXHFRCOCAL10;    /**< AUXHFRCO Calibration Register (26 MHz)  */
+  __I uint32_t AUXHFRCOCAL11;    /**< AUXHFRCO Calibration Register (32 MHz)  */
+  __I uint32_t AUXHFRCOCAL12;    /**< AUXHFRCO Calibration Register (38 MHz)  */
+  uint32_t     RESERVED11[11];   /**< Reserved for future use **/
+  __I uint32_t VMONCAL0;         /**< VMON Calibration Register 0  */
+  __I uint32_t VMONCAL1;         /**< VMON Calibration Register 1  */
+  __I uint32_t VMONCAL2;         /**< VMON Calibration Register 2  */
+  uint32_t     RESERVED12[3];    /**< Reserved for future use **/
+  __I uint32_t IDAC0CAL0;        /**< IDAC0 Calibration Register 0  */
+  __I uint32_t IDAC0CAL1;        /**< IDAC0 Calibration Register 1  */
+  uint32_t     RESERVED13[2];    /**< Reserved for future use **/
+  __I uint32_t DCDCLNVCTRL0;     /**< DCDC Low-noise VREF Trim Register 0  */
+  __I uint32_t DCDCLPVCTRL0;     /**< DCDC Low-power VREF Trim Register 0  */
+  __I uint32_t DCDCLPVCTRL1;     /**< DCDC Low-power VREF Trim Register 1  */
+  __I uint32_t DCDCLPVCTRL2;     /**< DCDC Low-power VREF Trim Register 2  */
+  __I uint32_t DCDCLPVCTRL3;     /**< DCDC Low-power VREF Trim Register 3  */
+  __I uint32_t DCDCLPCMPHYSSEL0; /**< DCDC LPCMPHYSSEL Trim Register 0  */
+  __I uint32_t DCDCLPCMPHYSSEL1; /**< DCDC LPCMPHYSSEL Trim Register 1  */
+} DEVINFO_TypeDef;               /** @} */
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B_DEVINFO_BitFields
+ * @{
+ *****************************************************************************/
+
+/* Bit fields for DEVINFO CAL */
+#define _DEVINFO_CAL_MASK                                        0x00FFFFFFUL /**< Mask for DEVINFO_CAL */
+#define _DEVINFO_CAL_CRC_SHIFT                                   0            /**< Shift value for CRC */
+#define _DEVINFO_CAL_CRC_MASK                                    0xFFFFUL     /**< Bit mask for CRC */
+#define _DEVINFO_CAL_TEMP_SHIFT                                  16           /**< Shift value for TEMP */
+#define _DEVINFO_CAL_TEMP_MASK                                   0xFF0000UL   /**< Bit mask for TEMP */
+
+/* Bit fields for DEVINFO EUI48L */
+#define _DEVINFO_EUI48L_MASK                                     0xFFFFFFFFUL /**< Mask for DEVINFO_EUI48L */
+#define _DEVINFO_EUI48L_UNIQUEID_SHIFT                           0            /**< Shift value for UNIQUEID */
+#define _DEVINFO_EUI48L_UNIQUEID_MASK                            0xFFFFFFUL   /**< Bit mask for UNIQUEID */
+#define _DEVINFO_EUI48L_OUI48L_SHIFT                             24           /**< Shift value for OUI48L */
+#define _DEVINFO_EUI48L_OUI48L_MASK                              0xFF000000UL /**< Bit mask for OUI48L */
+
+/* Bit fields for DEVINFO EUI48H */
+#define _DEVINFO_EUI48H_MASK                                     0x0000FFFFUL /**< Mask for DEVINFO_EUI48H */
+#define _DEVINFO_EUI48H_OUI48H_SHIFT                             0            /**< Shift value for OUI48H */
+#define _DEVINFO_EUI48H_OUI48H_MASK                              0xFFFFUL     /**< Bit mask for OUI48H */
+
+/* Bit fields for DEVINFO CUSTOMINFO */
+#define _DEVINFO_CUSTOMINFO_MASK                                 0xFFFF0000UL /**< Mask for DEVINFO_CUSTOMINFO */
+#define _DEVINFO_CUSTOMINFO_PARTNO_SHIFT                         16           /**< Shift value for PARTNO */
+#define _DEVINFO_CUSTOMINFO_PARTNO_MASK                          0xFFFF0000UL /**< Bit mask for PARTNO */
+
+/* Bit fields for DEVINFO MEMINFO */
+#define _DEVINFO_MEMINFO_MASK                                    0xFFFFFFFFUL                               /**< Mask for DEVINFO_MEMINFO */
+#define _DEVINFO_MEMINFO_TEMPGRADE_SHIFT                         0                                          /**< Shift value for TEMPGRADE */
+#define _DEVINFO_MEMINFO_TEMPGRADE_MASK                          0xFFUL                                     /**< Bit mask for TEMPGRADE */
+#define _DEVINFO_MEMINFO_TEMPGRADE_N40TO85                       0x00000000UL                               /**< Mode N40TO85 for DEVINFO_MEMINFO */
+#define _DEVINFO_MEMINFO_TEMPGRADE_N40TO125                      0x00000001UL                               /**< Mode N40TO125 for DEVINFO_MEMINFO */
+#define _DEVINFO_MEMINFO_TEMPGRADE_N40TO105                      0x00000002UL                               /**< Mode N40TO105 for DEVINFO_MEMINFO */
+#define _DEVINFO_MEMINFO_TEMPGRADE_N0TO70                        0x00000003UL                               /**< Mode N0TO70 for DEVINFO_MEMINFO */
+#define DEVINFO_MEMINFO_TEMPGRADE_N40TO85                        (_DEVINFO_MEMINFO_TEMPGRADE_N40TO85 << 0)  /**< Shifted mode N40TO85 for DEVINFO_MEMINFO */
+#define DEVINFO_MEMINFO_TEMPGRADE_N40TO125                       (_DEVINFO_MEMINFO_TEMPGRADE_N40TO125 << 0) /**< Shifted mode N40TO125 for DEVINFO_MEMINFO */
+#define DEVINFO_MEMINFO_TEMPGRADE_N40TO105                       (_DEVINFO_MEMINFO_TEMPGRADE_N40TO105 << 0) /**< Shifted mode N40TO105 for DEVINFO_MEMINFO */
+#define DEVINFO_MEMINFO_TEMPGRADE_N0TO70                         (_DEVINFO_MEMINFO_TEMPGRADE_N0TO70 << 0)   /**< Shifted mode N0TO70 for DEVINFO_MEMINFO */
+#define _DEVINFO_MEMINFO_PKGTYPE_SHIFT                           8                                          /**< Shift value for PKGTYPE */
+#define _DEVINFO_MEMINFO_PKGTYPE_MASK                            0xFF00UL                                   /**< Bit mask for PKGTYPE */
+#define _DEVINFO_MEMINFO_PKGTYPE_WLCSP                           0x0000004AUL                               /**< Mode WLCSP for DEVINFO_MEMINFO */
+#define _DEVINFO_MEMINFO_PKGTYPE_QFN                             0x0000004DUL                               /**< Mode QFN for DEVINFO_MEMINFO */
+#define _DEVINFO_MEMINFO_PKGTYPE_QFP                             0x00000051UL                               /**< Mode QFP for DEVINFO_MEMINFO */
+#define DEVINFO_MEMINFO_PKGTYPE_WLCSP                            (_DEVINFO_MEMINFO_PKGTYPE_WLCSP << 8)      /**< Shifted mode WLCSP for DEVINFO_MEMINFO */
+#define DEVINFO_MEMINFO_PKGTYPE_QFN                              (_DEVINFO_MEMINFO_PKGTYPE_QFN << 8)        /**< Shifted mode QFN for DEVINFO_MEMINFO */
+#define DEVINFO_MEMINFO_PKGTYPE_QFP                              (_DEVINFO_MEMINFO_PKGTYPE_QFP << 8)        /**< Shifted mode QFP for DEVINFO_MEMINFO */
+#define _DEVINFO_MEMINFO_PINCOUNT_SHIFT                          16                                         /**< Shift value for PINCOUNT */
+#define _DEVINFO_MEMINFO_PINCOUNT_MASK                           0xFF0000UL                                 /**< Bit mask for PINCOUNT */
+#define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_SHIFT                   24                                         /**< Shift value for FLASH_PAGE_SIZE */
+#define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_MASK                    0xFF000000UL                               /**< Bit mask for FLASH_PAGE_SIZE */
+
+/* Bit fields for DEVINFO UNIQUEL */
+#define _DEVINFO_UNIQUEL_MASK                                    0xFFFFFFFFUL /**< Mask for DEVINFO_UNIQUEL */
+#define _DEVINFO_UNIQUEL_UNIQUEL_SHIFT                           0            /**< Shift value for UNIQUEL */
+#define _DEVINFO_UNIQUEL_UNIQUEL_MASK                            0xFFFFFFFFUL /**< Bit mask for UNIQUEL */
+
+/* Bit fields for DEVINFO UNIQUEH */
+#define _DEVINFO_UNIQUEH_MASK                                    0xFFFFFFFFUL /**< Mask for DEVINFO_UNIQUEH */
+#define _DEVINFO_UNIQUEH_UNIQUEH_SHIFT                           0            /**< Shift value for UNIQUEH */
+#define _DEVINFO_UNIQUEH_UNIQUEH_MASK                            0xFFFFFFFFUL /**< Bit mask for UNIQUEH */
+
+/* Bit fields for DEVINFO MSIZE */
+#define _DEVINFO_MSIZE_MASK                                      0xFFFFFFFFUL /**< Mask for DEVINFO_MSIZE */
+#define _DEVINFO_MSIZE_FLASH_SHIFT                               0            /**< Shift value for FLASH */
+#define _DEVINFO_MSIZE_FLASH_MASK                                0xFFFFUL     /**< Bit mask for FLASH */
+#define _DEVINFO_MSIZE_SRAM_SHIFT                                16           /**< Shift value for SRAM */
+#define _DEVINFO_MSIZE_SRAM_MASK                                 0xFFFF0000UL /**< Bit mask for SRAM */
+
+/* Bit fields for DEVINFO PART */
+#define _DEVINFO_PART_MASK                                       0xFFFFFFFFUL                                  /**< Mask for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_NUMBER_SHIFT                        0                                             /**< Shift value for DEVICE_NUMBER */
+#define _DEVINFO_PART_DEVICE_NUMBER_MASK                         0xFFFFUL                                      /**< Bit mask for DEVICE_NUMBER */
+#define _DEVINFO_PART_DEVICE_FAMILY_SHIFT                        16                                            /**< Shift value for DEVICE_FAMILY */
+#define _DEVINFO_PART_DEVICE_FAMILY_MASK                         0xFF0000UL                                    /**< Bit mask for DEVICE_FAMILY */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P                    0x00000010UL                                  /**< Mode EFR32MG1P for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B                    0x00000011UL                                  /**< Mode EFR32MG1B for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V                    0x00000012UL                                  /**< Mode EFR32MG1V for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P                    0x00000013UL                                  /**< Mode EFR32BG1P for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B                    0x00000014UL                                  /**< Mode EFR32BG1B for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V                    0x00000015UL                                  /**< Mode EFR32BG1V for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG1P                    0x00000016UL                                  /**< Mode EFR32ZG1P for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG1B                    0x00000017UL                                  /**< Mode EFR32ZG1B for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG1V                    0x00000018UL                                  /**< Mode EFR32ZG1V for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P                    0x00000019UL                                  /**< Mode EFR32FG1P for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B                    0x0000001AUL                                  /**< Mode EFR32FG1B for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V                    0x0000001BUL                                  /**< Mode EFR32FG1V for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_G                            0x00000047UL                                  /**< Mode G for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFM32G                       0x00000047UL                                  /**< Mode EFM32G for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFM32GG                      0x00000048UL                                  /**< Mode EFM32GG for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_GG                           0x00000048UL                                  /**< Mode GG for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_TG                           0x00000049UL                                  /**< Mode TG for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFM32TG                      0x00000049UL                                  /**< Mode EFM32TG for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFM32LG                      0x0000004AUL                                  /**< Mode EFM32LG for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_LG                           0x0000004AUL                                  /**< Mode LG for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFM32WG                      0x0000004BUL                                  /**< Mode EFM32WG for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_WG                           0x0000004BUL                                  /**< Mode WG for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_ZG                           0x0000004CUL                                  /**< Mode ZG for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFM32ZG                      0x0000004CUL                                  /**< Mode EFM32ZG for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_HG                           0x0000004DUL                                  /**< Mode HG for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFM32HG                      0x0000004DUL                                  /**< Mode EFM32HG for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B                    0x00000051UL                                  /**< Mode EFM32PG1B for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B                    0x00000053UL                                  /**< Mode EFM32JG1B for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EZR32LG                      0x00000078UL                                  /**< Mode EZR32LG for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EZR32WG                      0x00000079UL                                  /**< Mode EZR32WG for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EZR32HG                      0x0000007AUL                                  /**< Mode EZR32HG for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P                     (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P << 16) /**< Shifted mode EFR32MG1P for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B                     (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B << 16) /**< Shifted mode EFR32MG1B for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V                     (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V << 16) /**< Shifted mode EFR32MG1V for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P                     (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P << 16) /**< Shifted mode EFR32BG1P for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B                     (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B << 16) /**< Shifted mode EFR32BG1B for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V                     (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V << 16) /**< Shifted mode EFR32BG1V for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32ZG1P                     (_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG1P << 16) /**< Shifted mode EFR32ZG1P for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32ZG1B                     (_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG1B << 16) /**< Shifted mode EFR32ZG1B for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32ZG1V                     (_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG1V << 16) /**< Shifted mode EFR32ZG1V for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P                     (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P << 16) /**< Shifted mode EFR32FG1P for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B                     (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B << 16) /**< Shifted mode EFR32FG1B for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V                     (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V << 16) /**< Shifted mode EFR32FG1V for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_G                             (_DEVINFO_PART_DEVICE_FAMILY_G << 16)         /**< Shifted mode G for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFM32G                        (_DEVINFO_PART_DEVICE_FAMILY_EFM32G << 16)    /**< Shifted mode EFM32G for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFM32GG                       (_DEVINFO_PART_DEVICE_FAMILY_EFM32GG << 16)   /**< Shifted mode EFM32GG for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_GG                            (_DEVINFO_PART_DEVICE_FAMILY_GG << 16)        /**< Shifted mode GG for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_TG                            (_DEVINFO_PART_DEVICE_FAMILY_TG << 16)        /**< Shifted mode TG for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFM32TG                       (_DEVINFO_PART_DEVICE_FAMILY_EFM32TG << 16)   /**< Shifted mode EFM32TG for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFM32LG                       (_DEVINFO_PART_DEVICE_FAMILY_EFM32LG << 16)   /**< Shifted mode EFM32LG for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_LG                            (_DEVINFO_PART_DEVICE_FAMILY_LG << 16)        /**< Shifted mode LG for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFM32WG                       (_DEVINFO_PART_DEVICE_FAMILY_EFM32WG << 16)   /**< Shifted mode EFM32WG for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_WG                            (_DEVINFO_PART_DEVICE_FAMILY_WG << 16)        /**< Shifted mode WG for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_ZG                            (_DEVINFO_PART_DEVICE_FAMILY_ZG << 16)        /**< Shifted mode ZG for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFM32ZG                       (_DEVINFO_PART_DEVICE_FAMILY_EFM32ZG << 16)   /**< Shifted mode EFM32ZG for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_HG                            (_DEVINFO_PART_DEVICE_FAMILY_HG << 16)        /**< Shifted mode HG for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFM32HG                       (_DEVINFO_PART_DEVICE_FAMILY_EFM32HG << 16)   /**< Shifted mode EFM32HG for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B                     (_DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B << 16) /**< Shifted mode EFM32PG1B for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B                     (_DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B << 16) /**< Shifted mode EFM32JG1B for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EZR32LG                       (_DEVINFO_PART_DEVICE_FAMILY_EZR32LG << 16)   /**< Shifted mode EZR32LG for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EZR32WG                       (_DEVINFO_PART_DEVICE_FAMILY_EZR32WG << 16)   /**< Shifted mode EZR32WG for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EZR32HG                       (_DEVINFO_PART_DEVICE_FAMILY_EZR32HG << 16)   /**< Shifted mode EZR32HG for DEVINFO_PART */
+#define _DEVINFO_PART_PROD_REV_SHIFT                             24                                            /**< Shift value for PROD_REV */
+#define _DEVINFO_PART_PROD_REV_MASK                              0xFF000000UL                                  /**< Bit mask for PROD_REV */
+
+/* Bit fields for DEVINFO DEVINFOREV */
+#define _DEVINFO_DEVINFOREV_MASK                                 0x000000FFUL /**< Mask for DEVINFO_DEVINFOREV */
+#define _DEVINFO_DEVINFOREV_DEVINFOREV_SHIFT                     0            /**< Shift value for DEVINFOREV */
+#define _DEVINFO_DEVINFOREV_DEVINFOREV_MASK                      0xFFUL       /**< Bit mask for DEVINFOREV */
+
+/* Bit fields for DEVINFO EMUTEMP */
+#define _DEVINFO_EMUTEMP_MASK                                    0x000000FFUL /**< Mask for DEVINFO_EMUTEMP */
+#define _DEVINFO_EMUTEMP_EMUTEMPROOM_SHIFT                       0            /**< Shift value for EMUTEMPROOM */
+#define _DEVINFO_EMUTEMP_EMUTEMPROOM_MASK                        0xFFUL       /**< Bit mask for EMUTEMPROOM */
+
+/* Bit fields for DEVINFO ADC0CAL0 */
+#define _DEVINFO_ADC0CAL0_MASK                                   0x7FFF7FFFUL /**< Mask for DEVINFO_ADC0CAL0 */
+#define _DEVINFO_ADC0CAL0_OFFSET1V25_SHIFT                       0            /**< Shift value for OFFSET1V25 */
+#define _DEVINFO_ADC0CAL0_OFFSET1V25_MASK                        0xFUL        /**< Bit mask for OFFSET1V25 */
+#define _DEVINFO_ADC0CAL0_NEGSEOFFSET1V25_SHIFT                  4            /**< Shift value for NEGSEOFFSET1V25 */
+#define _DEVINFO_ADC0CAL0_NEGSEOFFSET1V25_MASK                   0xF0UL       /**< Bit mask for NEGSEOFFSET1V25 */
+#define _DEVINFO_ADC0CAL0_GAIN1V25_SHIFT                         8            /**< Shift value for GAIN1V25 */
+#define _DEVINFO_ADC0CAL0_GAIN1V25_MASK                          0x7F00UL     /**< Bit mask for GAIN1V25 */
+#define _DEVINFO_ADC0CAL0_OFFSET2V5_SHIFT                        16           /**< Shift value for OFFSET2V5 */
+#define _DEVINFO_ADC0CAL0_OFFSET2V5_MASK                         0xF0000UL    /**< Bit mask for OFFSET2V5 */
+#define _DEVINFO_ADC0CAL0_NEGSEOFFSET2V5_SHIFT                   20           /**< Shift value for NEGSEOFFSET2V5 */
+#define _DEVINFO_ADC0CAL0_NEGSEOFFSET2V5_MASK                    0xF00000UL   /**< Bit mask for NEGSEOFFSET2V5 */
+#define _DEVINFO_ADC0CAL0_GAIN2V5_SHIFT                          24           /**< Shift value for GAIN2V5 */
+#define _DEVINFO_ADC0CAL0_GAIN2V5_MASK                           0x7F000000UL /**< Bit mask for GAIN2V5 */
+
+/* Bit fields for DEVINFO ADC0CAL1 */
+#define _DEVINFO_ADC0CAL1_MASK                                   0x7FFF7FFFUL /**< Mask for DEVINFO_ADC0CAL1 */
+#define _DEVINFO_ADC0CAL1_OFFSETVDD_SHIFT                        0            /**< Shift value for OFFSETVDD */
+#define _DEVINFO_ADC0CAL1_OFFSETVDD_MASK                         0xFUL        /**< Bit mask for OFFSETVDD */
+#define _DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_SHIFT                   4            /**< Shift value for NEGSEOFFSETVDD */
+#define _DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_MASK                    0xF0UL       /**< Bit mask for NEGSEOFFSETVDD */
+#define _DEVINFO_ADC0CAL1_GAINVDD_SHIFT                          8            /**< Shift value for GAINVDD */
+#define _DEVINFO_ADC0CAL1_GAINVDD_MASK                           0x7F00UL     /**< Bit mask for GAINVDD */
+#define _DEVINFO_ADC0CAL1_OFFSET5VDIFF_SHIFT                     16           /**< Shift value for OFFSET5VDIFF */
+#define _DEVINFO_ADC0CAL1_OFFSET5VDIFF_MASK                      0xF0000UL    /**< Bit mask for OFFSET5VDIFF */
+#define _DEVINFO_ADC0CAL1_NEGSEOFFSET5VDIFF_SHIFT                20           /**< Shift value for NEGSEOFFSET5VDIFF */
+#define _DEVINFO_ADC0CAL1_NEGSEOFFSET5VDIFF_MASK                 0xF00000UL   /**< Bit mask for NEGSEOFFSET5VDIFF */
+#define _DEVINFO_ADC0CAL1_GAIN5VDIFF_SHIFT                       24           /**< Shift value for GAIN5VDIFF */
+#define _DEVINFO_ADC0CAL1_GAIN5VDIFF_MASK                        0x7F000000UL /**< Bit mask for GAIN5VDIFF */
+
+/* Bit fields for DEVINFO ADC0CAL2 */
+#define _DEVINFO_ADC0CAL2_MASK                                   0x000000FFUL /**< Mask for DEVINFO_ADC0CAL2 */
+#define _DEVINFO_ADC0CAL2_OFFSET2XVDD_SHIFT                      0            /**< Shift value for OFFSET2XVDD */
+#define _DEVINFO_ADC0CAL2_OFFSET2XVDD_MASK                       0xFUL        /**< Bit mask for OFFSET2XVDD */
+#define _DEVINFO_ADC0CAL2_NEGSEOFFSET2XVDD_SHIFT                 4            /**< Shift value for NEGSEOFFSET2XVDD */
+#define _DEVINFO_ADC0CAL2_NEGSEOFFSET2XVDD_MASK                  0xF0UL       /**< Bit mask for NEGSEOFFSET2XVDD */
+
+/* Bit fields for DEVINFO ADC0CAL3 */
+#define _DEVINFO_ADC0CAL3_MASK                                   0x0000FFF0UL /**< Mask for DEVINFO_ADC0CAL3 */
+#define _DEVINFO_ADC0CAL3_TEMPREAD1V25_SHIFT                     4            /**< Shift value for TEMPREAD1V25 */
+#define _DEVINFO_ADC0CAL3_TEMPREAD1V25_MASK                      0xFFF0UL     /**< Bit mask for TEMPREAD1V25 */
+
+/* Bit fields for DEVINFO HFRCOCAL0 */
+#define _DEVINFO_HFRCOCAL0_MASK                                  0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL0 */
+#define _DEVINFO_HFRCOCAL0_TUNING_SHIFT                          0            /**< Shift value for TUNING */
+#define _DEVINFO_HFRCOCAL0_TUNING_MASK                           0x7FUL       /**< Bit mask for TUNING */
+#define _DEVINFO_HFRCOCAL0_FINETUNING_SHIFT                      8            /**< Shift value for FINETUNING */
+#define _DEVINFO_HFRCOCAL0_FINETUNING_MASK                       0x3F00UL     /**< Bit mask for FINETUNING */
+#define _DEVINFO_HFRCOCAL0_FREQRANGE_SHIFT                       16           /**< Shift value for FREQRANGE */
+#define _DEVINFO_HFRCOCAL0_FREQRANGE_MASK                        0x1F0000UL   /**< Bit mask for FREQRANGE */
+#define _DEVINFO_HFRCOCAL0_CMPBIAS_SHIFT                         21           /**< Shift value for CMPBIAS */
+#define _DEVINFO_HFRCOCAL0_CMPBIAS_MASK                          0xE00000UL   /**< Bit mask for CMPBIAS */
+#define _DEVINFO_HFRCOCAL0_LDOHP_SHIFT                           24           /**< Shift value for LDOHP */
+#define _DEVINFO_HFRCOCAL0_LDOHP_MASK                            0x1000000UL  /**< Bit mask for LDOHP */
+#define _DEVINFO_HFRCOCAL0_CLKDIV_SHIFT                          25           /**< Shift value for CLKDIV */
+#define _DEVINFO_HFRCOCAL0_CLKDIV_MASK                           0x6000000UL  /**< Bit mask for CLKDIV */
+#define _DEVINFO_HFRCOCAL0_FINETUNINGEN_SHIFT                    27           /**< Shift value for FINETUNINGEN */
+#define _DEVINFO_HFRCOCAL0_FINETUNINGEN_MASK                     0x8000000UL  /**< Bit mask for FINETUNINGEN */
+#define _DEVINFO_HFRCOCAL0_VREFTC_SHIFT                          28           /**< Shift value for VREFTC */
+#define _DEVINFO_HFRCOCAL0_VREFTC_MASK                           0xF0000000UL /**< Bit mask for VREFTC */
+
+/* Bit fields for DEVINFO HFRCOCAL3 */
+#define _DEVINFO_HFRCOCAL3_MASK                                  0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL3 */
+#define _DEVINFO_HFRCOCAL3_TUNING_SHIFT                          0            /**< Shift value for TUNING */
+#define _DEVINFO_HFRCOCAL3_TUNING_MASK                           0x7FUL       /**< Bit mask for TUNING */
+#define _DEVINFO_HFRCOCAL3_FINETUNING_SHIFT                      8            /**< Shift value for FINETUNING */
+#define _DEVINFO_HFRCOCAL3_FINETUNING_MASK                       0x3F00UL     /**< Bit mask for FINETUNING */
+#define _DEVINFO_HFRCOCAL3_FREQRANGE_SHIFT                       16           /**< Shift value for FREQRANGE */
+#define _DEVINFO_HFRCOCAL3_FREQRANGE_MASK                        0x1F0000UL   /**< Bit mask for FREQRANGE */
+#define _DEVINFO_HFRCOCAL3_CMPBIAS_SHIFT                         21           /**< Shift value for CMPBIAS */
+#define _DEVINFO_HFRCOCAL3_CMPBIAS_MASK                          0xE00000UL   /**< Bit mask for CMPBIAS */
+#define _DEVINFO_HFRCOCAL3_LDOHP_SHIFT                           24           /**< Shift value for LDOHP */
+#define _DEVINFO_HFRCOCAL3_LDOHP_MASK                            0x1000000UL  /**< Bit mask for LDOHP */
+#define _DEVINFO_HFRCOCAL3_CLKDIV_SHIFT                          25           /**< Shift value for CLKDIV */
+#define _DEVINFO_HFRCOCAL3_CLKDIV_MASK                           0x6000000UL  /**< Bit mask for CLKDIV */
+#define _DEVINFO_HFRCOCAL3_FINETUNINGEN_SHIFT                    27           /**< Shift value for FINETUNINGEN */
+#define _DEVINFO_HFRCOCAL3_FINETUNINGEN_MASK                     0x8000000UL  /**< Bit mask for FINETUNINGEN */
+#define _DEVINFO_HFRCOCAL3_VREFTC_SHIFT                          28           /**< Shift value for VREFTC */
+#define _DEVINFO_HFRCOCAL3_VREFTC_MASK                           0xF0000000UL /**< Bit mask for VREFTC */
+
+/* Bit fields for DEVINFO HFRCOCAL6 */
+#define _DEVINFO_HFRCOCAL6_MASK                                  0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL6 */
+#define _DEVINFO_HFRCOCAL6_TUNING_SHIFT                          0            /**< Shift value for TUNING */
+#define _DEVINFO_HFRCOCAL6_TUNING_MASK                           0x7FUL       /**< Bit mask for TUNING */
+#define _DEVINFO_HFRCOCAL6_FINETUNING_SHIFT                      8            /**< Shift value for FINETUNING */
+#define _DEVINFO_HFRCOCAL6_FINETUNING_MASK                       0x3F00UL     /**< Bit mask for FINETUNING */
+#define _DEVINFO_HFRCOCAL6_FREQRANGE_SHIFT                       16           /**< Shift value for FREQRANGE */
+#define _DEVINFO_HFRCOCAL6_FREQRANGE_MASK                        0x1F0000UL   /**< Bit mask for FREQRANGE */
+#define _DEVINFO_HFRCOCAL6_CMPBIAS_SHIFT                         21           /**< Shift value for CMPBIAS */
+#define _DEVINFO_HFRCOCAL6_CMPBIAS_MASK                          0xE00000UL   /**< Bit mask for CMPBIAS */
+#define _DEVINFO_HFRCOCAL6_LDOHP_SHIFT                           24           /**< Shift value for LDOHP */
+#define _DEVINFO_HFRCOCAL6_LDOHP_MASK                            0x1000000UL  /**< Bit mask for LDOHP */
+#define _DEVINFO_HFRCOCAL6_CLKDIV_SHIFT                          25           /**< Shift value for CLKDIV */
+#define _DEVINFO_HFRCOCAL6_CLKDIV_MASK                           0x6000000UL  /**< Bit mask for CLKDIV */
+#define _DEVINFO_HFRCOCAL6_FINETUNINGEN_SHIFT                    27           /**< Shift value for FINETUNINGEN */
+#define _DEVINFO_HFRCOCAL6_FINETUNINGEN_MASK                     0x8000000UL  /**< Bit mask for FINETUNINGEN */
+#define _DEVINFO_HFRCOCAL6_VREFTC_SHIFT                          28           /**< Shift value for VREFTC */
+#define _DEVINFO_HFRCOCAL6_VREFTC_MASK                           0xF0000000UL /**< Bit mask for VREFTC */
+
+/* Bit fields for DEVINFO HFRCOCAL7 */
+#define _DEVINFO_HFRCOCAL7_MASK                                  0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL7 */
+#define _DEVINFO_HFRCOCAL7_TUNING_SHIFT                          0            /**< Shift value for TUNING */
+#define _DEVINFO_HFRCOCAL7_TUNING_MASK                           0x7FUL       /**< Bit mask for TUNING */
+#define _DEVINFO_HFRCOCAL7_FINETUNING_SHIFT                      8            /**< Shift value for FINETUNING */
+#define _DEVINFO_HFRCOCAL7_FINETUNING_MASK                       0x3F00UL     /**< Bit mask for FINETUNING */
+#define _DEVINFO_HFRCOCAL7_FREQRANGE_SHIFT                       16           /**< Shift value for FREQRANGE */
+#define _DEVINFO_HFRCOCAL7_FREQRANGE_MASK                        0x1F0000UL   /**< Bit mask for FREQRANGE */
+#define _DEVINFO_HFRCOCAL7_CMPBIAS_SHIFT                         21           /**< Shift value for CMPBIAS */
+#define _DEVINFO_HFRCOCAL7_CMPBIAS_MASK                          0xE00000UL   /**< Bit mask for CMPBIAS */
+#define _DEVINFO_HFRCOCAL7_LDOHP_SHIFT                           24           /**< Shift value for LDOHP */
+#define _DEVINFO_HFRCOCAL7_LDOHP_MASK                            0x1000000UL  /**< Bit mask for LDOHP */
+#define _DEVINFO_HFRCOCAL7_CLKDIV_SHIFT                          25           /**< Shift value for CLKDIV */
+#define _DEVINFO_HFRCOCAL7_CLKDIV_MASK                           0x6000000UL  /**< Bit mask for CLKDIV */
+#define _DEVINFO_HFRCOCAL7_FINETUNINGEN_SHIFT                    27           /**< Shift value for FINETUNINGEN */
+#define _DEVINFO_HFRCOCAL7_FINETUNINGEN_MASK                     0x8000000UL  /**< Bit mask for FINETUNINGEN */
+#define _DEVINFO_HFRCOCAL7_VREFTC_SHIFT                          28           /**< Shift value for VREFTC */
+#define _DEVINFO_HFRCOCAL7_VREFTC_MASK                           0xF0000000UL /**< Bit mask for VREFTC */
+
+/* Bit fields for DEVINFO HFRCOCAL8 */
+#define _DEVINFO_HFRCOCAL8_MASK                                  0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL8 */
+#define _DEVINFO_HFRCOCAL8_TUNING_SHIFT                          0            /**< Shift value for TUNING */
+#define _DEVINFO_HFRCOCAL8_TUNING_MASK                           0x7FUL       /**< Bit mask for TUNING */
+#define _DEVINFO_HFRCOCAL8_FINETUNING_SHIFT                      8            /**< Shift value for FINETUNING */
+#define _DEVINFO_HFRCOCAL8_FINETUNING_MASK                       0x3F00UL     /**< Bit mask for FINETUNING */
+#define _DEVINFO_HFRCOCAL8_FREQRANGE_SHIFT                       16           /**< Shift value for FREQRANGE */
+#define _DEVINFO_HFRCOCAL8_FREQRANGE_MASK                        0x1F0000UL   /**< Bit mask for FREQRANGE */
+#define _DEVINFO_HFRCOCAL8_CMPBIAS_SHIFT                         21           /**< Shift value for CMPBIAS */
+#define _DEVINFO_HFRCOCAL8_CMPBIAS_MASK                          0xE00000UL   /**< Bit mask for CMPBIAS */
+#define _DEVINFO_HFRCOCAL8_LDOHP_SHIFT                           24           /**< Shift value for LDOHP */
+#define _DEVINFO_HFRCOCAL8_LDOHP_MASK                            0x1000000UL  /**< Bit mask for LDOHP */
+#define _DEVINFO_HFRCOCAL8_CLKDIV_SHIFT                          25           /**< Shift value for CLKDIV */
+#define _DEVINFO_HFRCOCAL8_CLKDIV_MASK                           0x6000000UL  /**< Bit mask for CLKDIV */
+#define _DEVINFO_HFRCOCAL8_FINETUNINGEN_SHIFT                    27           /**< Shift value for FINETUNINGEN */
+#define _DEVINFO_HFRCOCAL8_FINETUNINGEN_MASK                     0x8000000UL  /**< Bit mask for FINETUNINGEN */
+#define _DEVINFO_HFRCOCAL8_VREFTC_SHIFT                          28           /**< Shift value for VREFTC */
+#define _DEVINFO_HFRCOCAL8_VREFTC_MASK                           0xF0000000UL /**< Bit mask for VREFTC */
+
+/* Bit fields for DEVINFO HFRCOCAL10 */
+#define _DEVINFO_HFRCOCAL10_MASK                                 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL10 */
+#define _DEVINFO_HFRCOCAL10_TUNING_SHIFT                         0            /**< Shift value for TUNING */
+#define _DEVINFO_HFRCOCAL10_TUNING_MASK                          0x7FUL       /**< Bit mask for TUNING */
+#define _DEVINFO_HFRCOCAL10_FINETUNING_SHIFT                     8            /**< Shift value for FINETUNING */
+#define _DEVINFO_HFRCOCAL10_FINETUNING_MASK                      0x3F00UL     /**< Bit mask for FINETUNING */
+#define _DEVINFO_HFRCOCAL10_FREQRANGE_SHIFT                      16           /**< Shift value for FREQRANGE */
+#define _DEVINFO_HFRCOCAL10_FREQRANGE_MASK                       0x1F0000UL   /**< Bit mask for FREQRANGE */
+#define _DEVINFO_HFRCOCAL10_CMPBIAS_SHIFT                        21           /**< Shift value for CMPBIAS */
+#define _DEVINFO_HFRCOCAL10_CMPBIAS_MASK                         0xE00000UL   /**< Bit mask for CMPBIAS */
+#define _DEVINFO_HFRCOCAL10_LDOHP_SHIFT                          24           /**< Shift value for LDOHP */
+#define _DEVINFO_HFRCOCAL10_LDOHP_MASK                           0x1000000UL  /**< Bit mask for LDOHP */
+#define _DEVINFO_HFRCOCAL10_CLKDIV_SHIFT                         25           /**< Shift value for CLKDIV */
+#define _DEVINFO_HFRCOCAL10_CLKDIV_MASK                          0x6000000UL  /**< Bit mask for CLKDIV */
+#define _DEVINFO_HFRCOCAL10_FINETUNINGEN_SHIFT                   27           /**< Shift value for FINETUNINGEN */
+#define _DEVINFO_HFRCOCAL10_FINETUNINGEN_MASK                    0x8000000UL  /**< Bit mask for FINETUNINGEN */
+#define _DEVINFO_HFRCOCAL10_VREFTC_SHIFT                         28           /**< Shift value for VREFTC */
+#define _DEVINFO_HFRCOCAL10_VREFTC_MASK                          0xF0000000UL /**< Bit mask for VREFTC */
+
+/* Bit fields for DEVINFO HFRCOCAL11 */
+#define _DEVINFO_HFRCOCAL11_MASK                                 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL11 */
+#define _DEVINFO_HFRCOCAL11_TUNING_SHIFT                         0            /**< Shift value for TUNING */
+#define _DEVINFO_HFRCOCAL11_TUNING_MASK                          0x7FUL       /**< Bit mask for TUNING */
+#define _DEVINFO_HFRCOCAL11_FINETUNING_SHIFT                     8            /**< Shift value for FINETUNING */
+#define _DEVINFO_HFRCOCAL11_FINETUNING_MASK                      0x3F00UL     /**< Bit mask for FINETUNING */
+#define _DEVINFO_HFRCOCAL11_FREQRANGE_SHIFT                      16           /**< Shift value for FREQRANGE */
+#define _DEVINFO_HFRCOCAL11_FREQRANGE_MASK                       0x1F0000UL   /**< Bit mask for FREQRANGE */
+#define _DEVINFO_HFRCOCAL11_CMPBIAS_SHIFT                        21           /**< Shift value for CMPBIAS */
+#define _DEVINFO_HFRCOCAL11_CMPBIAS_MASK                         0xE00000UL   /**< Bit mask for CMPBIAS */
+#define _DEVINFO_HFRCOCAL11_LDOHP_SHIFT                          24           /**< Shift value for LDOHP */
+#define _DEVINFO_HFRCOCAL11_LDOHP_MASK                           0x1000000UL  /**< Bit mask for LDOHP */
+#define _DEVINFO_HFRCOCAL11_CLKDIV_SHIFT                         25           /**< Shift value for CLKDIV */
+#define _DEVINFO_HFRCOCAL11_CLKDIV_MASK                          0x6000000UL  /**< Bit mask for CLKDIV */
+#define _DEVINFO_HFRCOCAL11_FINETUNINGEN_SHIFT                   27           /**< Shift value for FINETUNINGEN */
+#define _DEVINFO_HFRCOCAL11_FINETUNINGEN_MASK                    0x8000000UL  /**< Bit mask for FINETUNINGEN */
+#define _DEVINFO_HFRCOCAL11_VREFTC_SHIFT                         28           /**< Shift value for VREFTC */
+#define _DEVINFO_HFRCOCAL11_VREFTC_MASK                          0xF0000000UL /**< Bit mask for VREFTC */
+
+/* Bit fields for DEVINFO HFRCOCAL12 */
+#define _DEVINFO_HFRCOCAL12_MASK                                 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL12 */
+#define _DEVINFO_HFRCOCAL12_TUNING_SHIFT                         0            /**< Shift value for TUNING */
+#define _DEVINFO_HFRCOCAL12_TUNING_MASK                          0x7FUL       /**< Bit mask for TUNING */
+#define _DEVINFO_HFRCOCAL12_FINETUNING_SHIFT                     8            /**< Shift value for FINETUNING */
+#define _DEVINFO_HFRCOCAL12_FINETUNING_MASK                      0x3F00UL     /**< Bit mask for FINETUNING */
+#define _DEVINFO_HFRCOCAL12_FREQRANGE_SHIFT                      16           /**< Shift value for FREQRANGE */
+#define _DEVINFO_HFRCOCAL12_FREQRANGE_MASK                       0x1F0000UL   /**< Bit mask for FREQRANGE */
+#define _DEVINFO_HFRCOCAL12_CMPBIAS_SHIFT                        21           /**< Shift value for CMPBIAS */
+#define _DEVINFO_HFRCOCAL12_CMPBIAS_MASK                         0xE00000UL   /**< Bit mask for CMPBIAS */
+#define _DEVINFO_HFRCOCAL12_LDOHP_SHIFT                          24           /**< Shift value for LDOHP */
+#define _DEVINFO_HFRCOCAL12_LDOHP_MASK                           0x1000000UL  /**< Bit mask for LDOHP */
+#define _DEVINFO_HFRCOCAL12_CLKDIV_SHIFT                         25           /**< Shift value for CLKDIV */
+#define _DEVINFO_HFRCOCAL12_CLKDIV_MASK                          0x6000000UL  /**< Bit mask for CLKDIV */
+#define _DEVINFO_HFRCOCAL12_FINETUNINGEN_SHIFT                   27           /**< Shift value for FINETUNINGEN */
+#define _DEVINFO_HFRCOCAL12_FINETUNINGEN_MASK                    0x8000000UL  /**< Bit mask for FINETUNINGEN */
+#define _DEVINFO_HFRCOCAL12_VREFTC_SHIFT                         28           /**< Shift value for VREFTC */
+#define _DEVINFO_HFRCOCAL12_VREFTC_MASK                          0xF0000000UL /**< Bit mask for VREFTC */
+
+/* Bit fields for DEVINFO AUXHFRCOCAL0 */
+#define _DEVINFO_AUXHFRCOCAL0_MASK                               0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL0 */
+#define _DEVINFO_AUXHFRCOCAL0_TUNING_SHIFT                       0            /**< Shift value for TUNING */
+#define _DEVINFO_AUXHFRCOCAL0_TUNING_MASK                        0x7FUL       /**< Bit mask for TUNING */
+#define _DEVINFO_AUXHFRCOCAL0_FINETUNING_SHIFT                   8            /**< Shift value for FINETUNING */
+#define _DEVINFO_AUXHFRCOCAL0_FINETUNING_MASK                    0x3F00UL     /**< Bit mask for FINETUNING */
+#define _DEVINFO_AUXHFRCOCAL0_FREQRANGE_SHIFT                    16           /**< Shift value for FREQRANGE */
+#define _DEVINFO_AUXHFRCOCAL0_FREQRANGE_MASK                     0x1F0000UL   /**< Bit mask for FREQRANGE */
+#define _DEVINFO_AUXHFRCOCAL0_CMPBIAS_SHIFT                      21           /**< Shift value for CMPBIAS */
+#define _DEVINFO_AUXHFRCOCAL0_CMPBIAS_MASK                       0xE00000UL   /**< Bit mask for CMPBIAS */
+#define _DEVINFO_AUXHFRCOCAL0_LDOHP_SHIFT                        24           /**< Shift value for LDOHP */
+#define _DEVINFO_AUXHFRCOCAL0_LDOHP_MASK                         0x1000000UL  /**< Bit mask for LDOHP */
+#define _DEVINFO_AUXHFRCOCAL0_CLKDIV_SHIFT                       25           /**< Shift value for CLKDIV */
+#define _DEVINFO_AUXHFRCOCAL0_CLKDIV_MASK                        0x6000000UL  /**< Bit mask for CLKDIV */
+#define _DEVINFO_AUXHFRCOCAL0_FINETUNINGEN_SHIFT                 27           /**< Shift value for FINETUNINGEN */
+#define _DEVINFO_AUXHFRCOCAL0_FINETUNINGEN_MASK                  0x8000000UL  /**< Bit mask for FINETUNINGEN */
+#define _DEVINFO_AUXHFRCOCAL0_VREFTC_SHIFT                       28           /**< Shift value for VREFTC */
+#define _DEVINFO_AUXHFRCOCAL0_VREFTC_MASK                        0xF0000000UL /**< Bit mask for VREFTC */
+
+/* Bit fields for DEVINFO AUXHFRCOCAL3 */
+#define _DEVINFO_AUXHFRCOCAL3_MASK                               0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL3 */
+#define _DEVINFO_AUXHFRCOCAL3_TUNING_SHIFT                       0            /**< Shift value for TUNING */
+#define _DEVINFO_AUXHFRCOCAL3_TUNING_MASK                        0x7FUL       /**< Bit mask for TUNING */
+#define _DEVINFO_AUXHFRCOCAL3_FINETUNING_SHIFT                   8            /**< Shift value for FINETUNING */
+#define _DEVINFO_AUXHFRCOCAL3_FINETUNING_MASK                    0x3F00UL     /**< Bit mask for FINETUNING */
+#define _DEVINFO_AUXHFRCOCAL3_FREQRANGE_SHIFT                    16           /**< Shift value for FREQRANGE */
+#define _DEVINFO_AUXHFRCOCAL3_FREQRANGE_MASK                     0x1F0000UL   /**< Bit mask for FREQRANGE */
+#define _DEVINFO_AUXHFRCOCAL3_CMPBIAS_SHIFT                      21           /**< Shift value for CMPBIAS */
+#define _DEVINFO_AUXHFRCOCAL3_CMPBIAS_MASK                       0xE00000UL   /**< Bit mask for CMPBIAS */
+#define _DEVINFO_AUXHFRCOCAL3_LDOHP_SHIFT                        24           /**< Shift value for LDOHP */
+#define _DEVINFO_AUXHFRCOCAL3_LDOHP_MASK                         0x1000000UL  /**< Bit mask for LDOHP */
+#define _DEVINFO_AUXHFRCOCAL3_CLKDIV_SHIFT                       25           /**< Shift value for CLKDIV */
+#define _DEVINFO_AUXHFRCOCAL3_CLKDIV_MASK                        0x6000000UL  /**< Bit mask for CLKDIV */
+#define _DEVINFO_AUXHFRCOCAL3_FINETUNINGEN_SHIFT                 27           /**< Shift value for FINETUNINGEN */
+#define _DEVINFO_AUXHFRCOCAL3_FINETUNINGEN_MASK                  0x8000000UL  /**< Bit mask for FINETUNINGEN */
+#define _DEVINFO_AUXHFRCOCAL3_VREFTC_SHIFT                       28           /**< Shift value for VREFTC */
+#define _DEVINFO_AUXHFRCOCAL3_VREFTC_MASK                        0xF0000000UL /**< Bit mask for VREFTC */
+
+/* Bit fields for DEVINFO AUXHFRCOCAL6 */
+#define _DEVINFO_AUXHFRCOCAL6_MASK                               0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL6 */
+#define _DEVINFO_AUXHFRCOCAL6_TUNING_SHIFT                       0            /**< Shift value for TUNING */
+#define _DEVINFO_AUXHFRCOCAL6_TUNING_MASK                        0x7FUL       /**< Bit mask for TUNING */
+#define _DEVINFO_AUXHFRCOCAL6_FINETUNING_SHIFT                   8            /**< Shift value for FINETUNING */
+#define _DEVINFO_AUXHFRCOCAL6_FINETUNING_MASK                    0x3F00UL     /**< Bit mask for FINETUNING */
+#define _DEVINFO_AUXHFRCOCAL6_FREQRANGE_SHIFT                    16           /**< Shift value for FREQRANGE */
+#define _DEVINFO_AUXHFRCOCAL6_FREQRANGE_MASK                     0x1F0000UL   /**< Bit mask for FREQRANGE */
+#define _DEVINFO_AUXHFRCOCAL6_CMPBIAS_SHIFT                      21           /**< Shift value for CMPBIAS */
+#define _DEVINFO_AUXHFRCOCAL6_CMPBIAS_MASK                       0xE00000UL   /**< Bit mask for CMPBIAS */
+#define _DEVINFO_AUXHFRCOCAL6_LDOHP_SHIFT                        24           /**< Shift value for LDOHP */
+#define _DEVINFO_AUXHFRCOCAL6_LDOHP_MASK                         0x1000000UL  /**< Bit mask for LDOHP */
+#define _DEVINFO_AUXHFRCOCAL6_CLKDIV_SHIFT                       25           /**< Shift value for CLKDIV */
+#define _DEVINFO_AUXHFRCOCAL6_CLKDIV_MASK                        0x6000000UL  /**< Bit mask for CLKDIV */
+#define _DEVINFO_AUXHFRCOCAL6_FINETUNINGEN_SHIFT                 27           /**< Shift value for FINETUNINGEN */
+#define _DEVINFO_AUXHFRCOCAL6_FINETUNINGEN_MASK                  0x8000000UL  /**< Bit mask for FINETUNINGEN */
+#define _DEVINFO_AUXHFRCOCAL6_VREFTC_SHIFT                       28           /**< Shift value for VREFTC */
+#define _DEVINFO_AUXHFRCOCAL6_VREFTC_MASK                        0xF0000000UL /**< Bit mask for VREFTC */
+
+/* Bit fields for DEVINFO AUXHFRCOCAL7 */
+#define _DEVINFO_AUXHFRCOCAL7_MASK                               0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL7 */
+#define _DEVINFO_AUXHFRCOCAL7_TUNING_SHIFT                       0            /**< Shift value for TUNING */
+#define _DEVINFO_AUXHFRCOCAL7_TUNING_MASK                        0x7FUL       /**< Bit mask for TUNING */
+#define _DEVINFO_AUXHFRCOCAL7_FINETUNING_SHIFT                   8            /**< Shift value for FINETUNING */
+#define _DEVINFO_AUXHFRCOCAL7_FINETUNING_MASK                    0x3F00UL     /**< Bit mask for FINETUNING */
+#define _DEVINFO_AUXHFRCOCAL7_FREQRANGE_SHIFT                    16           /**< Shift value for FREQRANGE */
+#define _DEVINFO_AUXHFRCOCAL7_FREQRANGE_MASK                     0x1F0000UL   /**< Bit mask for FREQRANGE */
+#define _DEVINFO_AUXHFRCOCAL7_CMPBIAS_SHIFT                      21           /**< Shift value for CMPBIAS */
+#define _DEVINFO_AUXHFRCOCAL7_CMPBIAS_MASK                       0xE00000UL   /**< Bit mask for CMPBIAS */
+#define _DEVINFO_AUXHFRCOCAL7_LDOHP_SHIFT                        24           /**< Shift value for LDOHP */
+#define _DEVINFO_AUXHFRCOCAL7_LDOHP_MASK                         0x1000000UL  /**< Bit mask for LDOHP */
+#define _DEVINFO_AUXHFRCOCAL7_CLKDIV_SHIFT                       25           /**< Shift value for CLKDIV */
+#define _DEVINFO_AUXHFRCOCAL7_CLKDIV_MASK                        0x6000000UL  /**< Bit mask for CLKDIV */
+#define _DEVINFO_AUXHFRCOCAL7_FINETUNINGEN_SHIFT                 27           /**< Shift value for FINETUNINGEN */
+#define _DEVINFO_AUXHFRCOCAL7_FINETUNINGEN_MASK                  0x8000000UL  /**< Bit mask for FINETUNINGEN */
+#define _DEVINFO_AUXHFRCOCAL7_VREFTC_SHIFT                       28           /**< Shift value for VREFTC */
+#define _DEVINFO_AUXHFRCOCAL7_VREFTC_MASK                        0xF0000000UL /**< Bit mask for VREFTC */
+
+/* Bit fields for DEVINFO AUXHFRCOCAL8 */
+#define _DEVINFO_AUXHFRCOCAL8_MASK                               0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL8 */
+#define _DEVINFO_AUXHFRCOCAL8_TUNING_SHIFT                       0            /**< Shift value for TUNING */
+#define _DEVINFO_AUXHFRCOCAL8_TUNING_MASK                        0x7FUL       /**< Bit mask for TUNING */
+#define _DEVINFO_AUXHFRCOCAL8_FINETUNING_SHIFT                   8            /**< Shift value for FINETUNING */
+#define _DEVINFO_AUXHFRCOCAL8_FINETUNING_MASK                    0x3F00UL     /**< Bit mask for FINETUNING */
+#define _DEVINFO_AUXHFRCOCAL8_FREQRANGE_SHIFT                    16           /**< Shift value for FREQRANGE */
+#define _DEVINFO_AUXHFRCOCAL8_FREQRANGE_MASK                     0x1F0000UL   /**< Bit mask for FREQRANGE */
+#define _DEVINFO_AUXHFRCOCAL8_CMPBIAS_SHIFT                      21           /**< Shift value for CMPBIAS */
+#define _DEVINFO_AUXHFRCOCAL8_CMPBIAS_MASK                       0xE00000UL   /**< Bit mask for CMPBIAS */
+#define _DEVINFO_AUXHFRCOCAL8_LDOHP_SHIFT                        24           /**< Shift value for LDOHP */
+#define _DEVINFO_AUXHFRCOCAL8_LDOHP_MASK                         0x1000000UL  /**< Bit mask for LDOHP */
+#define _DEVINFO_AUXHFRCOCAL8_CLKDIV_SHIFT                       25           /**< Shift value for CLKDIV */
+#define _DEVINFO_AUXHFRCOCAL8_CLKDIV_MASK                        0x6000000UL  /**< Bit mask for CLKDIV */
+#define _DEVINFO_AUXHFRCOCAL8_FINETUNINGEN_SHIFT                 27           /**< Shift value for FINETUNINGEN */
+#define _DEVINFO_AUXHFRCOCAL8_FINETUNINGEN_MASK                  0x8000000UL  /**< Bit mask for FINETUNINGEN */
+#define _DEVINFO_AUXHFRCOCAL8_VREFTC_SHIFT                       28           /**< Shift value for VREFTC */
+#define _DEVINFO_AUXHFRCOCAL8_VREFTC_MASK                        0xF0000000UL /**< Bit mask for VREFTC */
+
+/* Bit fields for DEVINFO AUXHFRCOCAL10 */
+#define _DEVINFO_AUXHFRCOCAL10_MASK                              0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL10 */
+#define _DEVINFO_AUXHFRCOCAL10_TUNING_SHIFT                      0            /**< Shift value for TUNING */
+#define _DEVINFO_AUXHFRCOCAL10_TUNING_MASK                       0x7FUL       /**< Bit mask for TUNING */
+#define _DEVINFO_AUXHFRCOCAL10_FINETUNING_SHIFT                  8            /**< Shift value for FINETUNING */
+#define _DEVINFO_AUXHFRCOCAL10_FINETUNING_MASK                   0x3F00UL     /**< Bit mask for FINETUNING */
+#define _DEVINFO_AUXHFRCOCAL10_FREQRANGE_SHIFT                   16           /**< Shift value for FREQRANGE */
+#define _DEVINFO_AUXHFRCOCAL10_FREQRANGE_MASK                    0x1F0000UL   /**< Bit mask for FREQRANGE */
+#define _DEVINFO_AUXHFRCOCAL10_CMPBIAS_SHIFT                     21           /**< Shift value for CMPBIAS */
+#define _DEVINFO_AUXHFRCOCAL10_CMPBIAS_MASK                      0xE00000UL   /**< Bit mask for CMPBIAS */
+#define _DEVINFO_AUXHFRCOCAL10_LDOHP_SHIFT                       24           /**< Shift value for LDOHP */
+#define _DEVINFO_AUXHFRCOCAL10_LDOHP_MASK                        0x1000000UL  /**< Bit mask for LDOHP */
+#define _DEVINFO_AUXHFRCOCAL10_CLKDIV_SHIFT                      25           /**< Shift value for CLKDIV */
+#define _DEVINFO_AUXHFRCOCAL10_CLKDIV_MASK                       0x6000000UL  /**< Bit mask for CLKDIV */
+#define _DEVINFO_AUXHFRCOCAL10_FINETUNINGEN_SHIFT                27           /**< Shift value for FINETUNINGEN */
+#define _DEVINFO_AUXHFRCOCAL10_FINETUNINGEN_MASK                 0x8000000UL  /**< Bit mask for FINETUNINGEN */
+#define _DEVINFO_AUXHFRCOCAL10_VREFTC_SHIFT                      28           /**< Shift value for VREFTC */
+#define _DEVINFO_AUXHFRCOCAL10_VREFTC_MASK                       0xF0000000UL /**< Bit mask for VREFTC */
+
+/* Bit fields for DEVINFO AUXHFRCOCAL11 */
+#define _DEVINFO_AUXHFRCOCAL11_MASK                              0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL11 */
+#define _DEVINFO_AUXHFRCOCAL11_TUNING_SHIFT                      0            /**< Shift value for TUNING */
+#define _DEVINFO_AUXHFRCOCAL11_TUNING_MASK                       0x7FUL       /**< Bit mask for TUNING */
+#define _DEVINFO_AUXHFRCOCAL11_FINETUNING_SHIFT                  8            /**< Shift value for FINETUNING */
+#define _DEVINFO_AUXHFRCOCAL11_FINETUNING_MASK                   0x3F00UL     /**< Bit mask for FINETUNING */
+#define _DEVINFO_AUXHFRCOCAL11_FREQRANGE_SHIFT                   16           /**< Shift value for FREQRANGE */
+#define _DEVINFO_AUXHFRCOCAL11_FREQRANGE_MASK                    0x1F0000UL   /**< Bit mask for FREQRANGE */
+#define _DEVINFO_AUXHFRCOCAL11_CMPBIAS_SHIFT                     21           /**< Shift value for CMPBIAS */
+#define _DEVINFO_AUXHFRCOCAL11_CMPBIAS_MASK                      0xE00000UL   /**< Bit mask for CMPBIAS */
+#define _DEVINFO_AUXHFRCOCAL11_LDOHP_SHIFT                       24           /**< Shift value for LDOHP */
+#define _DEVINFO_AUXHFRCOCAL11_LDOHP_MASK                        0x1000000UL  /**< Bit mask for LDOHP */
+#define _DEVINFO_AUXHFRCOCAL11_CLKDIV_SHIFT                      25           /**< Shift value for CLKDIV */
+#define _DEVINFO_AUXHFRCOCAL11_CLKDIV_MASK                       0x6000000UL  /**< Bit mask for CLKDIV */
+#define _DEVINFO_AUXHFRCOCAL11_FINETUNINGEN_SHIFT                27           /**< Shift value for FINETUNINGEN */
+#define _DEVINFO_AUXHFRCOCAL11_FINETUNINGEN_MASK                 0x8000000UL  /**< Bit mask for FINETUNINGEN */
+#define _DEVINFO_AUXHFRCOCAL11_VREFTC_SHIFT                      28           /**< Shift value for VREFTC */
+#define _DEVINFO_AUXHFRCOCAL11_VREFTC_MASK                       0xF0000000UL /**< Bit mask for VREFTC */
+
+/* Bit fields for DEVINFO AUXHFRCOCAL12 */
+#define _DEVINFO_AUXHFRCOCAL12_MASK                              0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL12 */
+#define _DEVINFO_AUXHFRCOCAL12_TUNING_SHIFT                      0            /**< Shift value for TUNING */
+#define _DEVINFO_AUXHFRCOCAL12_TUNING_MASK                       0x7FUL       /**< Bit mask for TUNING */
+#define _DEVINFO_AUXHFRCOCAL12_FINETUNING_SHIFT                  8            /**< Shift value for FINETUNING */
+#define _DEVINFO_AUXHFRCOCAL12_FINETUNING_MASK                   0x3F00UL     /**< Bit mask for FINETUNING */
+#define _DEVINFO_AUXHFRCOCAL12_FREQRANGE_SHIFT                   16           /**< Shift value for FREQRANGE */
+#define _DEVINFO_AUXHFRCOCAL12_FREQRANGE_MASK                    0x1F0000UL   /**< Bit mask for FREQRANGE */
+#define _DEVINFO_AUXHFRCOCAL12_CMPBIAS_SHIFT                     21           /**< Shift value for CMPBIAS */
+#define _DEVINFO_AUXHFRCOCAL12_CMPBIAS_MASK                      0xE00000UL   /**< Bit mask for CMPBIAS */
+#define _DEVINFO_AUXHFRCOCAL12_LDOHP_SHIFT                       24           /**< Shift value for LDOHP */
+#define _DEVINFO_AUXHFRCOCAL12_LDOHP_MASK                        0x1000000UL  /**< Bit mask for LDOHP */
+#define _DEVINFO_AUXHFRCOCAL12_CLKDIV_SHIFT                      25           /**< Shift value for CLKDIV */
+#define _DEVINFO_AUXHFRCOCAL12_CLKDIV_MASK                       0x6000000UL  /**< Bit mask for CLKDIV */
+#define _DEVINFO_AUXHFRCOCAL12_FINETUNINGEN_SHIFT                27           /**< Shift value for FINETUNINGEN */
+#define _DEVINFO_AUXHFRCOCAL12_FINETUNINGEN_MASK                 0x8000000UL  /**< Bit mask for FINETUNINGEN */
+#define _DEVINFO_AUXHFRCOCAL12_VREFTC_SHIFT                      28           /**< Shift value for VREFTC */
+#define _DEVINFO_AUXHFRCOCAL12_VREFTC_MASK                       0xF0000000UL /**< Bit mask for VREFTC */
+
+/* Bit fields for DEVINFO VMONCAL0 */
+#define _DEVINFO_VMONCAL0_MASK                                   0xFFFFFFFFUL /**< Mask for DEVINFO_VMONCAL0 */
+#define _DEVINFO_VMONCAL0_AVDD1V86THRESFINE_SHIFT                0            /**< Shift value for AVDD1V86THRESFINE */
+#define _DEVINFO_VMONCAL0_AVDD1V86THRESFINE_MASK                 0xFUL        /**< Bit mask for AVDD1V86THRESFINE */
+#define _DEVINFO_VMONCAL0_AVDD1V86THRESCOARSE_SHIFT              4            /**< Shift value for AVDD1V86THRESCOARSE */
+#define _DEVINFO_VMONCAL0_AVDD1V86THRESCOARSE_MASK               0xF0UL       /**< Bit mask for AVDD1V86THRESCOARSE */
+#define _DEVINFO_VMONCAL0_AVDD2V98THRESFINE_SHIFT                8            /**< Shift value for AVDD2V98THRESFINE */
+#define _DEVINFO_VMONCAL0_AVDD2V98THRESFINE_MASK                 0xF00UL      /**< Bit mask for AVDD2V98THRESFINE */
+#define _DEVINFO_VMONCAL0_AVDD2V98THRESCOARSE_SHIFT              12           /**< Shift value for AVDD2V98THRESCOARSE */
+#define _DEVINFO_VMONCAL0_AVDD2V98THRESCOARSE_MASK               0xF000UL     /**< Bit mask for AVDD2V98THRESCOARSE */
+#define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESFINE_SHIFT             16           /**< Shift value for ALTAVDD1V86THRESFINE */
+#define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESFINE_MASK              0xF0000UL    /**< Bit mask for ALTAVDD1V86THRESFINE */
+#define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESCOARSE_SHIFT           20           /**< Shift value for ALTAVDD1V86THRESCOARSE */
+#define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESCOARSE_MASK            0xF00000UL   /**< Bit mask for ALTAVDD1V86THRESCOARSE */
+#define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESFINE_SHIFT             24           /**< Shift value for ALTAVDD2V98THRESFINE */
+#define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESFINE_MASK              0xF000000UL  /**< Bit mask for ALTAVDD2V98THRESFINE */
+#define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESCOARSE_SHIFT           28           /**< Shift value for ALTAVDD2V98THRESCOARSE */
+#define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESCOARSE_MASK            0xF0000000UL /**< Bit mask for ALTAVDD2V98THRESCOARSE */
+
+/* Bit fields for DEVINFO VMONCAL1 */
+#define _DEVINFO_VMONCAL1_MASK                                   0xFFFFFFFFUL /**< Mask for DEVINFO_VMONCAL1 */
+#define _DEVINFO_VMONCAL1_DVDD1V86THRESFINE_SHIFT                0            /**< Shift value for DVDD1V86THRESFINE */
+#define _DEVINFO_VMONCAL1_DVDD1V86THRESFINE_MASK                 0xFUL        /**< Bit mask for DVDD1V86THRESFINE */
+#define _DEVINFO_VMONCAL1_DVDD1V86THRESCOARSE_SHIFT              4            /**< Shift value for DVDD1V86THRESCOARSE */
+#define _DEVINFO_VMONCAL1_DVDD1V86THRESCOARSE_MASK               0xF0UL       /**< Bit mask for DVDD1V86THRESCOARSE */
+#define _DEVINFO_VMONCAL1_DVDD2V98THRESFINE_SHIFT                8            /**< Shift value for DVDD2V98THRESFINE */
+#define _DEVINFO_VMONCAL1_DVDD2V98THRESFINE_MASK                 0xF00UL      /**< Bit mask for DVDD2V98THRESFINE */
+#define _DEVINFO_VMONCAL1_DVDD2V98THRESCOARSE_SHIFT              12           /**< Shift value for DVDD2V98THRESCOARSE */
+#define _DEVINFO_VMONCAL1_DVDD2V98THRESCOARSE_MASK               0xF000UL     /**< Bit mask for DVDD2V98THRESCOARSE */
+#define _DEVINFO_VMONCAL1_IO01V86THRESFINE_SHIFT                 16           /**< Shift value for IO01V86THRESFINE */
+#define _DEVINFO_VMONCAL1_IO01V86THRESFINE_MASK                  0xF0000UL    /**< Bit mask for IO01V86THRESFINE */
+#define _DEVINFO_VMONCAL1_IO01V86THRESCOARSE_SHIFT               20           /**< Shift value for IO01V86THRESCOARSE */
+#define _DEVINFO_VMONCAL1_IO01V86THRESCOARSE_MASK                0xF00000UL   /**< Bit mask for IO01V86THRESCOARSE */
+#define _DEVINFO_VMONCAL1_IO02V98THRESFINE_SHIFT                 24           /**< Shift value for IO02V98THRESFINE */
+#define _DEVINFO_VMONCAL1_IO02V98THRESFINE_MASK                  0xF000000UL  /**< Bit mask for IO02V98THRESFINE */
+#define _DEVINFO_VMONCAL1_IO02V98THRESCOARSE_SHIFT               28           /**< Shift value for IO02V98THRESCOARSE */
+#define _DEVINFO_VMONCAL1_IO02V98THRESCOARSE_MASK                0xF0000000UL /**< Bit mask for IO02V98THRESCOARSE */
+
+/* Bit fields for DEVINFO VMONCAL2 */
+#define _DEVINFO_VMONCAL2_MASK                                   0xFFFFFFFFUL /**< Mask for DEVINFO_VMONCAL2 */
+#define _DEVINFO_VMONCAL2_PAVDD1V86THRESFINE_SHIFT               0            /**< Shift value for PAVDD1V86THRESFINE */
+#define _DEVINFO_VMONCAL2_PAVDD1V86THRESFINE_MASK                0xFUL        /**< Bit mask for PAVDD1V86THRESFINE */
+#define _DEVINFO_VMONCAL2_PAVDD1V86THRESCOARSE_SHIFT             4            /**< Shift value for PAVDD1V86THRESCOARSE */
+#define _DEVINFO_VMONCAL2_PAVDD1V86THRESCOARSE_MASK              0xF0UL       /**< Bit mask for PAVDD1V86THRESCOARSE */
+#define _DEVINFO_VMONCAL2_PAVDD2V98THRESFINE_SHIFT               8            /**< Shift value for PAVDD2V98THRESFINE */
+#define _DEVINFO_VMONCAL2_PAVDD2V98THRESFINE_MASK                0xF00UL      /**< Bit mask for PAVDD2V98THRESFINE */
+#define _DEVINFO_VMONCAL2_PAVDD2V98THRESCOARSE_SHIFT             12           /**< Shift value for PAVDD2V98THRESCOARSE */
+#define _DEVINFO_VMONCAL2_PAVDD2V98THRESCOARSE_MASK              0xF000UL     /**< Bit mask for PAVDD2V98THRESCOARSE */
+#define _DEVINFO_VMONCAL2_FVDD1V86THRESFINE_SHIFT                16           /**< Shift value for FVDD1V86THRESFINE */
+#define _DEVINFO_VMONCAL2_FVDD1V86THRESFINE_MASK                 0xF0000UL    /**< Bit mask for FVDD1V86THRESFINE */
+#define _DEVINFO_VMONCAL2_FVDD1V86THRESCOARSE_SHIFT              20           /**< Shift value for FVDD1V86THRESCOARSE */
+#define _DEVINFO_VMONCAL2_FVDD1V86THRESCOARSE_MASK               0xF00000UL   /**< Bit mask for FVDD1V86THRESCOARSE */
+#define _DEVINFO_VMONCAL2_FVDD2V98THRESFINE_SHIFT                24           /**< Shift value for FVDD2V98THRESFINE */
+#define _DEVINFO_VMONCAL2_FVDD2V98THRESFINE_MASK                 0xF000000UL  /**< Bit mask for FVDD2V98THRESFINE */
+#define _DEVINFO_VMONCAL2_FVDD2V98THRESCOARSE_SHIFT              28           /**< Shift value for FVDD2V98THRESCOARSE */
+#define _DEVINFO_VMONCAL2_FVDD2V98THRESCOARSE_MASK               0xF0000000UL /**< Bit mask for FVDD2V98THRESCOARSE */
+
+/* Bit fields for DEVINFO IDAC0CAL0 */
+#define _DEVINFO_IDAC0CAL0_MASK                                  0xFFFFFFFFUL /**< Mask for DEVINFO_IDAC0CAL0 */
+#define _DEVINFO_IDAC0CAL0_SOURCERANGE0TUNING_SHIFT              0            /**< Shift value for SOURCERANGE0TUNING */
+#define _DEVINFO_IDAC0CAL0_SOURCERANGE0TUNING_MASK               0xFFUL       /**< Bit mask for SOURCERANGE0TUNING */
+#define _DEVINFO_IDAC0CAL0_SOURCERANGE1TUNING_SHIFT              8            /**< Shift value for SOURCERANGE1TUNING */
+#define _DEVINFO_IDAC0CAL0_SOURCERANGE1TUNING_MASK               0xFF00UL     /**< Bit mask for SOURCERANGE1TUNING */
+#define _DEVINFO_IDAC0CAL0_SOURCERANGE2TUNING_SHIFT              16           /**< Shift value for SOURCERANGE2TUNING */
+#define _DEVINFO_IDAC0CAL0_SOURCERANGE2TUNING_MASK               0xFF0000UL   /**< Bit mask for SOURCERANGE2TUNING */
+#define _DEVINFO_IDAC0CAL0_SOURCERANGE3TUNING_SHIFT              24           /**< Shift value for SOURCERANGE3TUNING */
+#define _DEVINFO_IDAC0CAL0_SOURCERANGE3TUNING_MASK               0xFF000000UL /**< Bit mask for SOURCERANGE3TUNING */
+
+/* Bit fields for DEVINFO IDAC0CAL1 */
+#define _DEVINFO_IDAC0CAL1_MASK                                  0xFFFFFFFFUL /**< Mask for DEVINFO_IDAC0CAL1 */
+#define _DEVINFO_IDAC0CAL1_SINKRANGE0TUNING_SHIFT                0            /**< Shift value for SINKRANGE0TUNING */
+#define _DEVINFO_IDAC0CAL1_SINKRANGE0TUNING_MASK                 0xFFUL       /**< Bit mask for SINKRANGE0TUNING */
+#define _DEVINFO_IDAC0CAL1_SINKRANGE1TUNING_SHIFT                8            /**< Shift value for SINKRANGE1TUNING */
+#define _DEVINFO_IDAC0CAL1_SINKRANGE1TUNING_MASK                 0xFF00UL     /**< Bit mask for SINKRANGE1TUNING */
+#define _DEVINFO_IDAC0CAL1_SINKRANGE2TUNING_SHIFT                16           /**< Shift value for SINKRANGE2TUNING */
+#define _DEVINFO_IDAC0CAL1_SINKRANGE2TUNING_MASK                 0xFF0000UL   /**< Bit mask for SINKRANGE2TUNING */
+#define _DEVINFO_IDAC0CAL1_SINKRANGE3TUNING_SHIFT                24           /**< Shift value for SINKRANGE3TUNING */
+#define _DEVINFO_IDAC0CAL1_SINKRANGE3TUNING_MASK                 0xFF000000UL /**< Bit mask for SINKRANGE3TUNING */
+
+/* Bit fields for DEVINFO DCDCLNVCTRL0 */
+#define _DEVINFO_DCDCLNVCTRL0_MASK                               0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLNVCTRL0 */
+#define _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_SHIFT                    0            /**< Shift value for 1V2LNATT0 */
+#define _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_MASK                     0xFFUL       /**< Bit mask for 1V2LNATT0 */
+#define _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_SHIFT                    8            /**< Shift value for 1V8LNATT0 */
+#define _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_MASK                     0xFF00UL     /**< Bit mask for 1V8LNATT0 */
+#define _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_SHIFT                    16           /**< Shift value for 1V8LNATT1 */
+#define _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_MASK                     0xFF0000UL   /**< Bit mask for 1V8LNATT1 */
+#define _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_SHIFT                    24           /**< Shift value for 3V0LNATT1 */
+#define _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_MASK                     0xFF000000UL /**< Bit mask for 3V0LNATT1 */
+
+/* Bit fields for DEVINFO DCDCLPVCTRL0 */
+#define _DEVINFO_DCDCLPVCTRL0_MASK                               0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPVCTRL0 */
+#define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_SHIFT          0            /**< Shift value for 1V2LPATT0LPCMPBIAS0 */
+#define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_MASK           0xFFUL       /**< Bit mask for 1V2LPATT0LPCMPBIAS0 */
+#define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_SHIFT          8            /**< Shift value for 1V8LPATT0LPCMPBIAS0 */
+#define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_MASK           0xFF00UL     /**< Bit mask for 1V8LPATT0LPCMPBIAS0 */
+#define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_SHIFT          16           /**< Shift value for 1V2LPATT0LPCMPBIAS1 */
+#define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_MASK           0xFF0000UL   /**< Bit mask for 1V2LPATT0LPCMPBIAS1 */
+#define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_SHIFT          24           /**< Shift value for 1V8LPATT0LPCMPBIAS1 */
+#define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_MASK           0xFF000000UL /**< Bit mask for 1V8LPATT0LPCMPBIAS1 */
+
+/* Bit fields for DEVINFO DCDCLPVCTRL1 */
+#define _DEVINFO_DCDCLPVCTRL1_MASK                               0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPVCTRL1 */
+#define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_SHIFT          0            /**< Shift value for 1V2LPATT0LPCMPBIAS2 */
+#define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_MASK           0xFFUL       /**< Bit mask for 1V2LPATT0LPCMPBIAS2 */
+#define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_SHIFT          8            /**< Shift value for 1V8LPATT0LPCMPBIAS2 */
+#define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_MASK           0xFF00UL     /**< Bit mask for 1V8LPATT0LPCMPBIAS2 */
+#define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_SHIFT          16           /**< Shift value for 1V2LPATT0LPCMPBIAS3 */
+#define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_MASK           0xFF0000UL   /**< Bit mask for 1V2LPATT0LPCMPBIAS3 */
+#define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_SHIFT          24           /**< Shift value for 1V8LPATT0LPCMPBIAS3 */
+#define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_MASK           0xFF000000UL /**< Bit mask for 1V8LPATT0LPCMPBIAS3 */
+
+/* Bit fields for DEVINFO DCDCLPVCTRL2 */
+#define _DEVINFO_DCDCLPVCTRL2_MASK                               0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPVCTRL2 */
+#define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_SHIFT          0            /**< Shift value for 1V8LPATT1LPCMPBIAS0 */
+#define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_MASK           0xFFUL       /**< Bit mask for 1V8LPATT1LPCMPBIAS0 */
+#define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_SHIFT          8            /**< Shift value for 3V0LPATT1LPCMPBIAS0 */
+#define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_MASK           0xFF00UL     /**< Bit mask for 3V0LPATT1LPCMPBIAS0 */
+#define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_SHIFT          16           /**< Shift value for 1V8LPATT1LPCMPBIAS1 */
+#define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_MASK           0xFF0000UL   /**< Bit mask for 1V8LPATT1LPCMPBIAS1 */
+#define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_SHIFT          24           /**< Shift value for 3V0LPATT1LPCMPBIAS1 */
+#define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_MASK           0xFF000000UL /**< Bit mask for 3V0LPATT1LPCMPBIAS1 */
+
+/* Bit fields for DEVINFO DCDCLPVCTRL3 */
+#define _DEVINFO_DCDCLPVCTRL3_MASK                               0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPVCTRL3 */
+#define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_SHIFT          0            /**< Shift value for 1V8LPATT1LPCMPBIAS2 */
+#define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_MASK           0xFFUL       /**< Bit mask for 1V8LPATT1LPCMPBIAS2 */
+#define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_SHIFT          8            /**< Shift value for 3V0LPATT1LPCMPBIAS2 */
+#define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_MASK           0xFF00UL     /**< Bit mask for 3V0LPATT1LPCMPBIAS2 */
+#define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_SHIFT          16           /**< Shift value for 1V8LPATT1LPCMPBIAS3 */
+#define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_MASK           0xFF0000UL   /**< Bit mask for 1V8LPATT1LPCMPBIAS3 */
+#define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_SHIFT          24           /**< Shift value for 3V0LPATT1LPCMPBIAS3 */
+#define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_MASK           0xFF000000UL /**< Bit mask for 3V0LPATT1LPCMPBIAS3 */
+
+/* Bit fields for DEVINFO DCDCLPCMPHYSSEL0 */
+#define _DEVINFO_DCDCLPCMPHYSSEL0_MASK                           0x0000FFFFUL /**< Mask for DEVINFO_DCDCLPCMPHYSSEL0 */
+#define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_SHIFT        0            /**< Shift value for LPCMPHYSSELLPATT0 */
+#define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_MASK         0xFFUL       /**< Bit mask for LPCMPHYSSELLPATT0 */
+#define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_SHIFT        8            /**< Shift value for LPCMPHYSSELLPATT1 */
+#define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_MASK         0xFF00UL     /**< Bit mask for LPCMPHYSSELLPATT1 */
+
+/* Bit fields for DEVINFO DCDCLPCMPHYSSEL1 */
+#define _DEVINFO_DCDCLPCMPHYSSEL1_MASK                           0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPCMPHYSSEL1 */
+#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_SHIFT    0            /**< Shift value for LPCMPHYSSELLPCMPBIAS0 */
+#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_MASK     0xFFUL       /**< Bit mask for LPCMPHYSSELLPCMPBIAS0 */
+#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_SHIFT    8            /**< Shift value for LPCMPHYSSELLPCMPBIAS1 */
+#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_MASK     0xFF00UL     /**< Bit mask for LPCMPHYSSELLPCMPBIAS1 */
+#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_SHIFT    16           /**< Shift value for LPCMPHYSSELLPCMPBIAS2 */
+#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_MASK     0xFF0000UL   /**< Bit mask for LPCMPHYSSELLPCMPBIAS2 */
+#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_SHIFT    24           /**< Shift value for LPCMPHYSSELLPCMPBIAS3 */
+#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_MASK     0xFF000000UL /**< Bit mask for LPCMPHYSSELLPCMPBIAS3 */
+
+/** @} End of group EFM32PG1B_DEVINFO */
+/** @} End of group Parts */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG_STK3401/efm32pg1b_dma_descriptor.h	Fri Jan 15 07:45:16 2016 +0000
@@ -0,0 +1,52 @@
+/**************************************************************************//**
+ * @file efm32pg1b_dma_descriptor.h
+ * @brief EFM32PG1B_DMA_DESCRIPTOR register and bit field definitions
+ * @version 4.2.0
+ ******************************************************************************
+ * @section License
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ ******************************************************************************
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software.@n
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.@n
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is
+ * providing the Software "AS IS", with no express or implied warranties of any
+ * kind, including, but not limited to, any implied warranties of
+ * merchantability or fitness for any particular purpose or warranties against
+ * infringement of any proprietary rights of a third party.
+ *
+ * Silicon Laboratories, Inc. will not be liable for any consequential,
+ * incidental, or special damages, or any other relief, or for any claim by
+ * any third party, arising from your use of this Software.
+ *
+ *****************************************************************************/
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFM32PG1B_DMA_DESCRIPTOR
+ * @{
+ *****************************************************************************/
+typedef struct
+{
+  /* Note! Use of double __IO (volatile) qualifier to ensure that both */
+  /* pointer and referenced memory are declared volatile. */
+  __IO uint32_t    CTRL;       /**< DMA control register */
+  __IO void * __IO SRC;        /**< DMA source address */
+  __IO void * __IO DST;        /**< DMA destination address */
+  __IO void * __IO LINK;       /**< DMA link address */
+} DMA_DESCRIPTOR_TypeDef;      /**< @} */
+
+/** @} End of group Parts */
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG_STK3401/efm32pg1b_dmareq.h	Fri Jan 15 07:45:16 2016 +0000
@@ -0,0 +1,76 @@
+/**************************************************************************//**
+ * @file efm32pg1b_dmareq.h
+ * @brief EFM32PG1B_DMAREQ register and bit field definitions
+ * @version 4.2.0
+ ******************************************************************************
+ * @section License
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ ******************************************************************************
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software.@n
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.@n
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is
+ * providing the Software "AS IS", with no express or implied warranties of any
+ * kind, including, but not limited to, any implied warranties of
+ * merchantability or fitness for any particular purpose or warranties against
+ * infringement of any proprietary rights of a third party.
+ *
+ * Silicon Laboratories, Inc. will not be liable for any consequential,
+ * incidental, or special damages, or any other relief, or for any claim by
+ * any third party, arising from your use of this Software.
+ *
+ *****************************************************************************/
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B_DMAREQ_BitFields
+ * @{
+ *****************************************************************************/
+#define DMAREQ_PRS_REQ0               ((1 << 16) + 0)  /**< DMA channel select for PRS_REQ0 */
+#define DMAREQ_PRS_REQ1               ((1 << 16) + 1)  /**< DMA channel select for PRS_REQ1 */
+#define DMAREQ_ADC0_SINGLE            ((8 << 16) + 0)  /**< DMA channel select for ADC0_SINGLE */
+#define DMAREQ_ADC0_SCAN              ((8 << 16) + 1)  /**< DMA channel select for ADC0_SCAN */
+#define DMAREQ_USART0_RXDATAV         ((12 << 16) + 0) /**< DMA channel select for USART0_RXDATAV */
+#define DMAREQ_USART0_TXBL            ((12 << 16) + 1) /**< DMA channel select for USART0_TXBL */
+#define DMAREQ_USART0_TXEMPTY         ((12 << 16) + 2) /**< DMA channel select for USART0_TXEMPTY */
+#define DMAREQ_USART1_RXDATAV         ((13 << 16) + 0) /**< DMA channel select for USART1_RXDATAV */
+#define DMAREQ_USART1_TXBL            ((13 << 16) + 1) /**< DMA channel select for USART1_TXBL */
+#define DMAREQ_USART1_TXEMPTY         ((13 << 16) + 2) /**< DMA channel select for USART1_TXEMPTY */
+#define DMAREQ_USART1_RXDATAVRIGHT    ((13 << 16) + 3) /**< DMA channel select for USART1_RXDATAVRIGHT */
+#define DMAREQ_USART1_TXBLRIGHT       ((13 << 16) + 4) /**< DMA channel select for USART1_TXBLRIGHT */
+#define DMAREQ_LEUART0_RXDATAV        ((16 << 16) + 0) /**< DMA channel select for LEUART0_RXDATAV */
+#define DMAREQ_LEUART0_TXBL           ((16 << 16) + 1) /**< DMA channel select for LEUART0_TXBL */
+#define DMAREQ_LEUART0_TXEMPTY        ((16 << 16) + 2) /**< DMA channel select for LEUART0_TXEMPTY */
+#define DMAREQ_I2C0_RXDATAV           ((20 << 16) + 0) /**< DMA channel select for I2C0_RXDATAV */
+#define DMAREQ_I2C0_TXBL              ((20 << 16) + 1) /**< DMA channel select for I2C0_TXBL */
+#define DMAREQ_TIMER0_UFOF            ((24 << 16) + 0) /**< DMA channel select for TIMER0_UFOF */
+#define DMAREQ_TIMER0_CC0             ((24 << 16) + 1) /**< DMA channel select for TIMER0_CC0 */
+#define DMAREQ_TIMER0_CC1             ((24 << 16) + 2) /**< DMA channel select for TIMER0_CC1 */
+#define DMAREQ_TIMER0_CC2             ((24 << 16) + 3) /**< DMA channel select for TIMER0_CC2 */
+#define DMAREQ_TIMER1_UFOF            ((25 << 16) + 0) /**< DMA channel select for TIMER1_UFOF */
+#define DMAREQ_TIMER1_CC0             ((25 << 16) + 1) /**< DMA channel select for TIMER1_CC0 */
+#define DMAREQ_TIMER1_CC1             ((25 << 16) + 2) /**< DMA channel select for TIMER1_CC1 */
+#define DMAREQ_TIMER1_CC2             ((25 << 16) + 3) /**< DMA channel select for TIMER1_CC2 */
+#define DMAREQ_TIMER1_CC3             ((25 << 16) + 4) /**< DMA channel select for TIMER1_CC3 */
+#define DMAREQ_MSC_WDATA              ((48 << 16) + 0) /**< DMA channel select for MSC_WDATA */
+#define DMAREQ_CRYPTO_DATA0WR         ((49 << 16) + 0) /**< DMA channel select for CRYPTO_DATA0WR */
+#define DMAREQ_CRYPTO_DATA0XWR        ((49 << 16) + 1) /**< DMA channel select for CRYPTO_DATA0XWR */
+#define DMAREQ_CRYPTO_DATA0RD         ((49 << 16) + 2) /**< DMA channel select for CRYPTO_DATA0RD */
+#define DMAREQ_CRYPTO_DATA1WR         ((49 << 16) + 3) /**< DMA channel select for CRYPTO_DATA1WR */
+#define DMAREQ_CRYPTO_DATA1RD         ((49 << 16) + 4) /**< DMA channel select for CRYPTO_DATA1RD */
+
+/** @} End of group EFM32PG1B_DMAREQ */
+/** @} End of group Parts */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG_STK3401/efm32pg1b_emu.h	Fri Jan 15 07:45:16 2016 +0000
@@ -0,0 +1,1042 @@
+/**************************************************************************//**
+ * @file efm32pg1b_emu.h
+ * @brief EFM32PG1B_EMU register and bit field definitions
+ * @version 4.2.0
+ ******************************************************************************
+ * @section License
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ ******************************************************************************
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software.@n
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.@n
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is
+ * providing the Software "AS IS", with no express or implied warranties of any
+ * kind, including, but not limited to, any implied warranties of
+ * merchantability or fitness for any particular purpose or warranties against
+ * infringement of any proprietary rights of a third party.
+ *
+ * Silicon Laboratories, Inc. will not be liable for any consequential,
+ * incidental, or special damages, or any other relief, or for any claim by
+ * any third party, arising from your use of this Software.
+ *
+ *****************************************************************************/
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFM32PG1B_EMU
+ * @{
+ * @brief EFM32PG1B_EMU Register Declaration
+ *****************************************************************************/
+typedef struct
+{
+  __IO uint32_t CTRL;            /**< Control Register  */
+  __I uint32_t  STATUS;          /**< Status Register  */
+  __IO uint32_t LOCK;            /**< Configuration Lock Register  */
+  __IO uint32_t RAM0CTRL;        /**< Memory Control Register  */
+  __IO uint32_t CMD;             /**< Command Register  */
+  __IO uint32_t PERACTCONF;      /**< Peripheral to Peripheral Activation Clock Configuration  */
+  __IO uint32_t EM4CTRL;         /**< EM4 Control Register  */
+  __IO uint32_t TEMPLIMITS;      /**< Temperature limits for interrupt generation  */
+  __I uint32_t  TEMP;            /**< Value of last temperature measurement  */
+  __I uint32_t  IF;              /**< Interrupt Flag Register  */
+  __IO uint32_t IFS;             /**< Interrupt Flag Set Register  */
+  __IO uint32_t IFC;             /**< Interrupt Flag Clear Register  */
+  __IO uint32_t IEN;             /**< Interrupt Enable Register  */
+  __IO uint32_t PWRLOCK;         /**< Regulator and Supply Lock Register  */
+  __IO uint32_t PWRCFG;          /**< Power Configuration Register.  */
+  __IO uint32_t PWRCTRL;         /**< Power Control Register.  */
+  __IO uint32_t DCDCCTRL;        /**< DCDC Control  */
+
+  uint32_t      RESERVED0[2];    /**< Reserved for future use **/
+  __IO uint32_t DCDCMISCCTRL;    /**< DCDC Miscellaneous Control Register  */
+  __IO uint32_t DCDCZDETCTRL;    /**< DCDC Power Train NFET Zero Current Detector Control Register  */
+  __IO uint32_t DCDCCLIMCTRL;    /**< DCDC Power Train PFET Current Limiter Control Register  */
+
+  uint32_t      RESERVED1[1];    /**< Reserved for future use **/
+  __IO uint32_t DCDCLNVCTRL;     /**< DCDC Low Noise Voltage Register  */
+  __IO uint32_t DCDCTIMING;      /**< DCDC Controller Timing Value Register  */
+  __IO uint32_t DCDCLPVCTRL;     /**< DCDC Low Power Voltage Register  */
+
+  uint32_t      RESERVED2[1];    /**< Reserved for future use **/
+  __IO uint32_t DCDCLPCTRL;      /**< DCDC Low Power Control Register  */
+  __IO uint32_t DCDCLNFREQCTRL;  /**< DCDC Low Noise Controller Frequency Control  */
+
+  uint32_t      RESERVED3[1];    /**< Reserved for future use **/
+  __I uint32_t  DCDCSYNC;        /**< DCDC Read Status Register  */
+
+  uint32_t      RESERVED4[5];    /**< Reserved for future use **/
+  __IO uint32_t VMONAVDDCTRL;    /**< VMON AVDD Channel Control  */
+  __IO uint32_t VMONALTAVDDCTRL; /**< Alternate VMON AVDD Channel Control  */
+  __IO uint32_t VMONDVDDCTRL;    /**< VMON DVDD Channel Control  */
+  __IO uint32_t VMONIO0CTRL;     /**< VMON IOVDD0 Channel Control  */
+} EMU_TypeDef;                   /** @} */
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B_EMU_BitFields
+ * @{
+ *****************************************************************************/
+
+/* Bit fields for EMU CTRL */
+#define _EMU_CTRL_RESETVALUE                         0x00000000UL                      /**< Default value for EMU_CTRL */
+#define _EMU_CTRL_MASK                               0x00000002UL                      /**< Mask for EMU_CTRL */
+#define EMU_CTRL_EM2BLOCK                            (0x1UL << 1)                      /**< Energy Mode 2 Block */
+#define _EMU_CTRL_EM2BLOCK_SHIFT                     1                                 /**< Shift value for EMU_EM2BLOCK */
+#define _EMU_CTRL_EM2BLOCK_MASK                      0x2UL                             /**< Bit mask for EMU_EM2BLOCK */
+#define _EMU_CTRL_EM2BLOCK_DEFAULT                   0x00000000UL                      /**< Mode DEFAULT for EMU_CTRL */
+#define EMU_CTRL_EM2BLOCK_DEFAULT                    (_EMU_CTRL_EM2BLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_CTRL */
+
+/* Bit fields for EMU STATUS */
+#define _EMU_STATUS_RESETVALUE                       0x00000000UL                           /**< Default value for EMU_STATUS */
+#define _EMU_STATUS_MASK                             0x0010011FUL                           /**< Mask for EMU_STATUS */
+#define EMU_STATUS_VMONRDY                           (0x1UL << 0)                           /**< VMON ready */
+#define _EMU_STATUS_VMONRDY_SHIFT                    0                                      /**< Shift value for EMU_VMONRDY */
+#define _EMU_STATUS_VMONRDY_MASK                     0x1UL                                  /**< Bit mask for EMU_VMONRDY */
+#define _EMU_STATUS_VMONRDY_DEFAULT                  0x00000000UL                           /**< Mode DEFAULT for EMU_STATUS */
+#define EMU_STATUS_VMONRDY_DEFAULT                   (_EMU_STATUS_VMONRDY_DEFAULT << 0)     /**< Shifted mode DEFAULT for EMU_STATUS */
+#define EMU_STATUS_VMONAVDD                          (0x1UL << 1)                           /**< VMON AVDD Channel. */
+#define _EMU_STATUS_VMONAVDD_SHIFT                   1                                      /**< Shift value for EMU_VMONAVDD */
+#define _EMU_STATUS_VMONAVDD_MASK                    0x2UL                                  /**< Bit mask for EMU_VMONAVDD */
+#define _EMU_STATUS_VMONAVDD_DEFAULT                 0x00000000UL                           /**< Mode DEFAULT for EMU_STATUS */
+#define EMU_STATUS_VMONAVDD_DEFAULT                  (_EMU_STATUS_VMONAVDD_DEFAULT << 1)    /**< Shifted mode DEFAULT for EMU_STATUS */
+#define EMU_STATUS_VMONALTAVDD                       (0x1UL << 2)                           /**< Alternate VMON AVDD Channel. */
+#define _EMU_STATUS_VMONALTAVDD_SHIFT                2                                      /**< Shift value for EMU_VMONALTAVDD */
+#define _EMU_STATUS_VMONALTAVDD_MASK                 0x4UL                                  /**< Bit mask for EMU_VMONALTAVDD */
+#define _EMU_STATUS_VMONALTAVDD_DEFAULT              0x00000000UL                           /**< Mode DEFAULT for EMU_STATUS */
+#define EMU_STATUS_VMONALTAVDD_DEFAULT               (_EMU_STATUS_VMONALTAVDD_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_STATUS */
+#define EMU_STATUS_VMONDVDD                          (0x1UL << 3)                           /**< VMON DVDD Channel. */
+#define _EMU_STATUS_VMONDVDD_SHIFT                   3                                      /**< Shift value for EMU_VMONDVDD */
+#define _EMU_STATUS_VMONDVDD_MASK                    0x8UL                                  /**< Bit mask for EMU_VMONDVDD */
+#define _EMU_STATUS_VMONDVDD_DEFAULT                 0x00000000UL                           /**< Mode DEFAULT for EMU_STATUS */
+#define EMU_STATUS_VMONDVDD_DEFAULT                  (_EMU_STATUS_VMONDVDD_DEFAULT << 3)    /**< Shifted mode DEFAULT for EMU_STATUS */
+#define EMU_STATUS_VMONIO0                           (0x1UL << 4)                           /**< VMON IOVDD0 Channel. */
+#define _EMU_STATUS_VMONIO0_SHIFT                    4                                      /**< Shift value for EMU_VMONIO0 */
+#define _EMU_STATUS_VMONIO0_MASK                     0x10UL                                 /**< Bit mask for EMU_VMONIO0 */
+#define _EMU_STATUS_VMONIO0_DEFAULT                  0x00000000UL                           /**< Mode DEFAULT for EMU_STATUS */
+#define EMU_STATUS_VMONIO0_DEFAULT                   (_EMU_STATUS_VMONIO0_DEFAULT << 4)     /**< Shifted mode DEFAULT for EMU_STATUS */
+#define EMU_STATUS_VMONFVDD                          (0x1UL << 8)                           /**< VMON VDDFLASH Channel. */
+#define _EMU_STATUS_VMONFVDD_SHIFT                   8                                      /**< Shift value for EMU_VMONFVDD */
+#define _EMU_STATUS_VMONFVDD_MASK                    0x100UL                                /**< Bit mask for EMU_VMONFVDD */
+#define _EMU_STATUS_VMONFVDD_DEFAULT                 0x00000000UL                           /**< Mode DEFAULT for EMU_STATUS */
+#define EMU_STATUS_VMONFVDD_DEFAULT                  (_EMU_STATUS_VMONFVDD_DEFAULT << 8)    /**< Shifted mode DEFAULT for EMU_STATUS */
+#define EMU_STATUS_EM4IORET                          (0x1UL << 20)                          /**< IO Retention Status */
+#define _EMU_STATUS_EM4IORET_SHIFT                   20                                     /**< Shift value for EMU_EM4IORET */
+#define _EMU_STATUS_EM4IORET_MASK                    0x100000UL                             /**< Bit mask for EMU_EM4IORET */
+#define _EMU_STATUS_EM4IORET_DEFAULT                 0x00000000UL                           /**< Mode DEFAULT for EMU_STATUS */
+#define _EMU_STATUS_EM4IORET_DISABLED                0x00000000UL                           /**< Mode DISABLED for EMU_STATUS */
+#define _EMU_STATUS_EM4IORET_ENABLED                 0x00000001UL                           /**< Mode ENABLED for EMU_STATUS */
+#define EMU_STATUS_EM4IORET_DEFAULT                  (_EMU_STATUS_EM4IORET_DEFAULT << 20)   /**< Shifted mode DEFAULT for EMU_STATUS */
+#define EMU_STATUS_EM4IORET_DISABLED                 (_EMU_STATUS_EM4IORET_DISABLED << 20)  /**< Shifted mode DISABLED for EMU_STATUS */
+#define EMU_STATUS_EM4IORET_ENABLED                  (_EMU_STATUS_EM4IORET_ENABLED << 20)   /**< Shifted mode ENABLED for EMU_STATUS */
+
+/* Bit fields for EMU LOCK */
+#define _EMU_LOCK_RESETVALUE                         0x00000000UL                      /**< Default value for EMU_LOCK */
+#define _EMU_LOCK_MASK                               0x0000FFFFUL                      /**< Mask for EMU_LOCK */
+#define _EMU_LOCK_LOCKKEY_SHIFT                      0                                 /**< Shift value for EMU_LOCKKEY */
+#define _EMU_LOCK_LOCKKEY_MASK                       0xFFFFUL                          /**< Bit mask for EMU_LOCKKEY */
+#define _EMU_LOCK_LOCKKEY_DEFAULT                    0x00000000UL                      /**< Mode DEFAULT for EMU_LOCK */
+#define _EMU_LOCK_LOCKKEY_LOCK                       0x00000000UL                      /**< Mode LOCK for EMU_LOCK */
+#define _EMU_LOCK_LOCKKEY_UNLOCKED                   0x00000000UL                      /**< Mode UNLOCKED for EMU_LOCK */
+#define _EMU_LOCK_LOCKKEY_LOCKED                     0x00000001UL                      /**< Mode LOCKED for EMU_LOCK */
+#define _EMU_LOCK_LOCKKEY_UNLOCK                     0x0000ADE8UL                      /**< Mode UNLOCK for EMU_LOCK */
+#define EMU_LOCK_LOCKKEY_DEFAULT                     (_EMU_LOCK_LOCKKEY_DEFAULT << 0)  /**< Shifted mode DEFAULT for EMU_LOCK */
+#define EMU_LOCK_LOCKKEY_LOCK                        (_EMU_LOCK_LOCKKEY_LOCK << 0)     /**< Shifted mode LOCK for EMU_LOCK */
+#define EMU_LOCK_LOCKKEY_UNLOCKED                    (_EMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_LOCK */
+#define EMU_LOCK_LOCKKEY_LOCKED                      (_EMU_LOCK_LOCKKEY_LOCKED << 0)   /**< Shifted mode LOCKED for EMU_LOCK */
+#define EMU_LOCK_LOCKKEY_UNLOCK                      (_EMU_LOCK_LOCKKEY_UNLOCK << 0)   /**< Shifted mode UNLOCK for EMU_LOCK */
+
+/* Bit fields for EMU RAM0CTRL */
+#define _EMU_RAM0CTRL_RESETVALUE                     0x00000000UL                              /**< Default value for EMU_RAM0CTRL */
+#define _EMU_RAM0CTRL_MASK                           0x0000000FUL                              /**< Mask for EMU_RAM0CTRL */
+#define _EMU_RAM0CTRL_RAMPOWERDOWN_SHIFT             0                                         /**< Shift value for EMU_RAMPOWERDOWN */
+#define _EMU_RAM0CTRL_RAMPOWERDOWN_MASK              0xFUL                                     /**< Bit mask for EMU_RAMPOWERDOWN */
+#define _EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT           0x00000000UL                              /**< Mode DEFAULT for EMU_RAM0CTRL */
+#define _EMU_RAM0CTRL_RAMPOWERDOWN_NONE              0x00000000UL                              /**< Mode NONE for EMU_RAM0CTRL */
+#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK4              0x00000008UL                              /**< Mode BLK4 for EMU_RAM0CTRL */
+#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO4           0x0000000CUL                              /**< Mode BLK3TO4 for EMU_RAM0CTRL */
+#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO4           0x0000000EUL                              /**< Mode BLK2TO4 for EMU_RAM0CTRL */
+#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO4           0x0000000FUL                              /**< Mode BLK1TO4 for EMU_RAM0CTRL */
+#define EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT            (_EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM0CTRL */
+#define EMU_RAM0CTRL_RAMPOWERDOWN_NONE               (_EMU_RAM0CTRL_RAMPOWERDOWN_NONE << 0)    /**< Shifted mode NONE for EMU_RAM0CTRL */
+#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK4               (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK4 << 0)    /**< Shifted mode BLK4 for EMU_RAM0CTRL */
+#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO4            (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO4 << 0) /**< Shifted mode BLK3TO4 for EMU_RAM0CTRL */
+#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO4            (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO4 << 0) /**< Shifted mode BLK2TO4 for EMU_RAM0CTRL */
+#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO4            (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO4 << 0) /**< Shifted mode BLK1TO4 for EMU_RAM0CTRL */
+
+/* Bit fields for EMU CMD */
+#define _EMU_CMD_RESETVALUE                          0x00000000UL                       /**< Default value for EMU_CMD */
+#define _EMU_CMD_MASK                                0x00000001UL                       /**< Mask for EMU_CMD */
+#define EMU_CMD_EM4UNLATCH                           (0x1UL << 0)                       /**< EM4 Unlatch */
+#define _EMU_CMD_EM4UNLATCH_SHIFT                    0                                  /**< Shift value for EMU_EM4UNLATCH */
+#define _EMU_CMD_EM4UNLATCH_MASK                     0x1UL                              /**< Bit mask for EMU_EM4UNLATCH */
+#define _EMU_CMD_EM4UNLATCH_DEFAULT                  0x00000000UL                       /**< Mode DEFAULT for EMU_CMD */
+#define EMU_CMD_EM4UNLATCH_DEFAULT                   (_EMU_CMD_EM4UNLATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_CMD */
+
+/* Bit fields for EMU PERACTCONF */
+#define _EMU_PERACTCONF_RESETVALUE                   0x00000000UL                          /**< Default value for EMU_PERACTCONF */
+#define _EMU_PERACTCONF_MASK                         0x00000001UL                          /**< Mask for EMU_PERACTCONF */
+#define EMU_PERACTCONF_RACPER                        (0x1UL << 0)                          /**< Enable PER clock when RAC is activated */
+#define _EMU_PERACTCONF_RACPER_SHIFT                 0                                     /**< Shift value for EMU_RACPER */
+#define _EMU_PERACTCONF_RACPER_MASK                  0x1UL                                 /**< Bit mask for EMU_RACPER */
+#define _EMU_PERACTCONF_RACPER_DEFAULT               0x00000000UL                          /**< Mode DEFAULT for EMU_PERACTCONF */
+#define EMU_PERACTCONF_RACPER_DEFAULT                (_EMU_PERACTCONF_RACPER_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PERACTCONF */
+
+/* Bit fields for EMU EM4CTRL */
+#define _EMU_EM4CTRL_RESETVALUE                      0x00000000UL                               /**< Default value for EMU_EM4CTRL */
+#define _EMU_EM4CTRL_MASK                            0x0003003FUL                               /**< Mask for EMU_EM4CTRL */
+#define EMU_EM4CTRL_EM4STATE                         (0x1UL << 0)                               /**< Energy Mode 4 State */
+#define _EMU_EM4CTRL_EM4STATE_SHIFT                  0                                          /**< Shift value for EMU_EM4STATE */
+#define _EMU_EM4CTRL_EM4STATE_MASK                   0x1UL                                      /**< Bit mask for EMU_EM4STATE */
+#define _EMU_EM4CTRL_EM4STATE_DEFAULT                0x00000000UL                               /**< Mode DEFAULT for EMU_EM4CTRL */
+#define _EMU_EM4CTRL_EM4STATE_EM4S                   0x00000000UL                               /**< Mode EM4S for EMU_EM4CTRL */
+#define _EMU_EM4CTRL_EM4STATE_EM4H                   0x00000001UL                               /**< Mode EM4H for EMU_EM4CTRL */
+#define EMU_EM4CTRL_EM4STATE_DEFAULT                 (_EMU_EM4CTRL_EM4STATE_DEFAULT << 0)       /**< Shifted mode DEFAULT for EMU_EM4CTRL */
+#define EMU_EM4CTRL_EM4STATE_EM4S                    (_EMU_EM4CTRL_EM4STATE_EM4S << 0)          /**< Shifted mode EM4S for EMU_EM4CTRL */
+#define EMU_EM4CTRL_EM4STATE_EM4H                    (_EMU_EM4CTRL_EM4STATE_EM4H << 0)          /**< Shifted mode EM4H for EMU_EM4CTRL */
+#define EMU_EM4CTRL_RETAINLFRCO                      (0x1UL << 1)                               /**< LFRCO Retain during EM4 */
+#define _EMU_EM4CTRL_RETAINLFRCO_SHIFT               1                                          /**< Shift value for EMU_RETAINLFRCO */
+#define _EMU_EM4CTRL_RETAINLFRCO_MASK                0x2UL                                      /**< Bit mask for EMU_RETAINLFRCO */
+#define _EMU_EM4CTRL_RETAINLFRCO_DEFAULT             0x00000000UL                               /**< Mode DEFAULT for EMU_EM4CTRL */
+#define EMU_EM4CTRL_RETAINLFRCO_DEFAULT              (_EMU_EM4CTRL_RETAINLFRCO_DEFAULT << 1)    /**< Shifted mode DEFAULT for EMU_EM4CTRL */
+#define EMU_EM4CTRL_RETAINLFXO                       (0x1UL << 2)                               /**< LFXO Retain during EM4 */
+#define _EMU_EM4CTRL_RETAINLFXO_SHIFT                2                                          /**< Shift value for EMU_RETAINLFXO */
+#define _EMU_EM4CTRL_RETAINLFXO_MASK                 0x4UL                                      /**< Bit mask for EMU_RETAINLFXO */
+#define _EMU_EM4CTRL_RETAINLFXO_DEFAULT              0x00000000UL                               /**< Mode DEFAULT for EMU_EM4CTRL */
+#define EMU_EM4CTRL_RETAINLFXO_DEFAULT               (_EMU_EM4CTRL_RETAINLFXO_DEFAULT << 2)     /**< Shifted mode DEFAULT for EMU_EM4CTRL */
+#define EMU_EM4CTRL_RETAINULFRCO                     (0x1UL << 3)                               /**< ULFRCO Retain during EM4S */
+#define _EMU_EM4CTRL_RETAINULFRCO_SHIFT              3                                          /**< Shift value for EMU_RETAINULFRCO */
+#define _EMU_EM4CTRL_RETAINULFRCO_MASK               0x8UL                                      /**< Bit mask for EMU_RETAINULFRCO */
+#define _EMU_EM4CTRL_RETAINULFRCO_DEFAULT            0x00000000UL                               /**< Mode DEFAULT for EMU_EM4CTRL */
+#define EMU_EM4CTRL_RETAINULFRCO_DEFAULT             (_EMU_EM4CTRL_RETAINULFRCO_DEFAULT << 3)   /**< Shifted mode DEFAULT for EMU_EM4CTRL */
+#define _EMU_EM4CTRL_EM4IORETMODE_SHIFT              4                                          /**< Shift value for EMU_EM4IORETMODE */
+#define _EMU_EM4CTRL_EM4IORETMODE_MASK               0x30UL                                     /**< Bit mask for EMU_EM4IORETMODE */
+#define _EMU_EM4CTRL_EM4IORETMODE_DEFAULT            0x00000000UL                               /**< Mode DEFAULT for EMU_EM4CTRL */
+#define _EMU_EM4CTRL_EM4IORETMODE_DISABLE            0x00000000UL                               /**< Mode DISABLE for EMU_EM4CTRL */
+#define _EMU_EM4CTRL_EM4IORETMODE_EM4EXIT            0x00000001UL                               /**< Mode EM4EXIT for EMU_EM4CTRL */
+#define _EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH          0x00000002UL                               /**< Mode SWUNLATCH for EMU_EM4CTRL */
+#define EMU_EM4CTRL_EM4IORETMODE_DEFAULT             (_EMU_EM4CTRL_EM4IORETMODE_DEFAULT << 4)   /**< Shifted mode DEFAULT for EMU_EM4CTRL */
+#define EMU_EM4CTRL_EM4IORETMODE_DISABLE             (_EMU_EM4CTRL_EM4IORETMODE_DISABLE << 4)   /**< Shifted mode DISABLE for EMU_EM4CTRL */
+#define EMU_EM4CTRL_EM4IORETMODE_EM4EXIT             (_EMU_EM4CTRL_EM4IORETMODE_EM4EXIT << 4)   /**< Shifted mode EM4EXIT for EMU_EM4CTRL */
+#define EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH           (_EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH << 4) /**< Shifted mode SWUNLATCH for EMU_EM4CTRL */
+#define _EMU_EM4CTRL_EM4ENTRY_SHIFT                  16                                         /**< Shift value for EMU_EM4ENTRY */
+#define _EMU_EM4CTRL_EM4ENTRY_MASK                   0x30000UL                                  /**< Bit mask for EMU_EM4ENTRY */
+#define _EMU_EM4CTRL_EM4ENTRY_DEFAULT                0x00000000UL                               /**< Mode DEFAULT for EMU_EM4CTRL */
+#define EMU_EM4CTRL_EM4ENTRY_DEFAULT                 (_EMU_EM4CTRL_EM4ENTRY_DEFAULT << 16)      /**< Shifted mode DEFAULT for EMU_EM4CTRL */
+
+/* Bit fields for EMU TEMPLIMITS */
+#define _EMU_TEMPLIMITS_RESETVALUE                   0x0000FF00UL                            /**< Default value for EMU_TEMPLIMITS */
+#define _EMU_TEMPLIMITS_MASK                         0x0001FFFFUL                            /**< Mask for EMU_TEMPLIMITS */
+#define _EMU_TEMPLIMITS_TEMPLOW_SHIFT                0                                       /**< Shift value for EMU_TEMPLOW */
+#define _EMU_TEMPLIMITS_TEMPLOW_MASK                 0xFFUL                                  /**< Bit mask for EMU_TEMPLOW */
+#define _EMU_TEMPLIMITS_TEMPLOW_DEFAULT              0x00000000UL                            /**< Mode DEFAULT for EMU_TEMPLIMITS */
+#define EMU_TEMPLIMITS_TEMPLOW_DEFAULT               (_EMU_TEMPLIMITS_TEMPLOW_DEFAULT << 0)  /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */
+#define _EMU_TEMPLIMITS_TEMPHIGH_SHIFT               8                                       /**< Shift value for EMU_TEMPHIGH */
+#define _EMU_TEMPLIMITS_TEMPHIGH_MASK                0xFF00UL                                /**< Bit mask for EMU_TEMPHIGH */
+#define _EMU_TEMPLIMITS_TEMPHIGH_DEFAULT             0x000000FFUL                            /**< Mode DEFAULT for EMU_TEMPLIMITS */
+#define EMU_TEMPLIMITS_TEMPHIGH_DEFAULT              (_EMU_TEMPLIMITS_TEMPHIGH_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */
+#define EMU_TEMPLIMITS_EM4WUEN                       (0x1UL << 16)                           /**< Enable EM4 Wakeup due to low/high temerature */
+#define _EMU_TEMPLIMITS_EM4WUEN_SHIFT                16                                      /**< Shift value for EMU_EM4WUEN */
+#define _EMU_TEMPLIMITS_EM4WUEN_MASK                 0x10000UL                               /**< Bit mask for EMU_EM4WUEN */
+#define _EMU_TEMPLIMITS_EM4WUEN_DEFAULT              0x00000000UL                            /**< Mode DEFAULT for EMU_TEMPLIMITS */
+#define EMU_TEMPLIMITS_EM4WUEN_DEFAULT               (_EMU_TEMPLIMITS_EM4WUEN_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */
+
+/* Bit fields for EMU TEMP */
+#define _EMU_TEMP_RESETVALUE                         0x00000000UL                  /**< Default value for EMU_TEMP */
+#define _EMU_TEMP_MASK                               0x000000FFUL                  /**< Mask for EMU_TEMP */
+#define _EMU_TEMP_TEMP_SHIFT                         0                             /**< Shift value for EMU_TEMP */
+#define _EMU_TEMP_TEMP_MASK                          0xFFUL                        /**< Bit mask for EMU_TEMP */
+#define _EMU_TEMP_TEMP_DEFAULT                       0x00000000UL                  /**< Mode DEFAULT for EMU_TEMP */
+#define EMU_TEMP_TEMP_DEFAULT                        (_EMU_TEMP_TEMP_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMP */
+
+/* Bit fields for EMU IF */
+#define _EMU_IF_RESETVALUE                           0x00000000UL                                 /**< Default value for EMU_IF */
+#define _EMU_IF_MASK                                 0xE11FC0FFUL                                 /**< Mask for EMU_IF */
+#define EMU_IF_VMONAVDDFALL                          (0x1UL << 0)                                 /**< VMON AVDD Channel Fall */
+#define _EMU_IF_VMONAVDDFALL_SHIFT                   0                                            /**< Shift value for EMU_VMONAVDDFALL */
+#define _EMU_IF_VMONAVDDFALL_MASK                    0x1UL                                        /**< Bit mask for EMU_VMONAVDDFALL */
+#define _EMU_IF_VMONAVDDFALL_DEFAULT                 0x00000000UL                                 /**< Mode DEFAULT for EMU_IF */
+#define EMU_IF_VMONAVDDFALL_DEFAULT                  (_EMU_IF_VMONAVDDFALL_DEFAULT << 0)          /**< Shifted mode DEFAULT for EMU_IF */
+#define EMU_IF_VMONAVDDRISE                          (0x1UL << 1)                                 /**< VMON AVDD Channel Rise */
+#define _EMU_IF_VMONAVDDRISE_SHIFT                   1                                            /**< Shift value for EMU_VMONAVDDRISE */
+#define _EMU_IF_VMONAVDDRISE_MASK                    0x2UL                                        /**< Bit mask for EMU_VMONAVDDRISE */
+#define _EMU_IF_VMONAVDDRISE_DEFAULT                 0x00000000UL                                 /**< Mode DEFAULT for EMU_IF */
+#define EMU_IF_VMONAVDDRISE_DEFAULT                  (_EMU_IF_VMONAVDDRISE_DEFAULT << 1)          /**< Shifted mode DEFAULT for EMU_IF */
+#define EMU_IF_VMONALTAVDDFALL                       (0x1UL << 2)                                 /**< Alternate VMON AVDD Channel Fall */
+#define _EMU_IF_VMONALTAVDDFALL_SHIFT                2                                            /**< Shift value for EMU_VMONALTAVDDFALL */
+#define _EMU_IF_VMONALTAVDDFALL_MASK                 0x4UL                                        /**< Bit mask for EMU_VMONALTAVDDFALL */
+#define _EMU_IF_VMONALTAVDDFALL_DEFAULT              0x00000000UL                                 /**< Mode DEFAULT for EMU_IF */
+#define EMU_IF_VMONALTAVDDFALL_DEFAULT               (_EMU_IF_VMONALTAVDDFALL_DEFAULT << 2)       /**< Shifted mode DEFAULT for EMU_IF */
+#define EMU_IF_VMONALTAVDDRISE                       (0x1UL << 3)                                 /**< Alternate VMON AVDD Channel Rise */
+#define _EMU_IF_VMONALTAVDDRISE_SHIFT                3                                            /**< Shift value for EMU_VMONALTAVDDRISE */
+#define _EMU_IF_VMONALTAVDDRISE_MASK                 0x8UL                                        /**< Bit mask for EMU_VMONALTAVDDRISE */
+#define _EMU_IF_VMONALTAVDDRISE_DEFAULT              0x00000000UL                                 /**< Mode DEFAULT for EMU_IF */
+#define EMU_IF_VMONALTAVDDRISE_DEFAULT               (_EMU_IF_VMONALTAVDDRISE_DEFAULT << 3)       /**< Shifted mode DEFAULT for EMU_IF */
+#define EMU_IF_VMONDVDDFALL                          (0x1UL << 4)                                 /**< VMON DVDD Channel Fall */
+#define _EMU_IF_VMONDVDDFALL_SHIFT                   4                                            /**< Shift value for EMU_VMONDVDDFALL */
+#define _EMU_IF_VMONDVDDFALL_MASK                    0x10UL                                       /**< Bit mask for EMU_VMONDVDDFALL */
+#define _EMU_IF_VMONDVDDFALL_DEFAULT                 0x00000000UL                                 /**< Mode DEFAULT for EMU_IF */
+#define EMU_IF_VMONDVDDFALL_DEFAULT                  (_EMU_IF_VMONDVDDFALL_DEFAULT << 4)          /**< Shifted mode DEFAULT for EMU_IF */
+#define EMU_IF_VMONDVDDRISE                          (0x1UL << 5)                                 /**< VMON DVDD Channel Rise */
+#define _EMU_IF_VMONDVDDRISE_SHIFT                   5                                            /**< Shift value for EMU_VMONDVDDRISE */
+#define _EMU_IF_VMONDVDDRISE_MASK                    0x20UL                                       /**< Bit mask for EMU_VMONDVDDRISE */
+#define _EMU_IF_VMONDVDDRISE_DEFAULT                 0x00000000UL                                 /**< Mode DEFAULT for EMU_IF */
+#define EMU_IF_VMONDVDDRISE_DEFAULT                  (_EMU_IF_VMONDVDDRISE_DEFAULT << 5)          /**< Shifted mode DEFAULT for EMU_IF */
+#define EMU_IF_VMONIO0FALL                           (0x1UL << 6)                                 /**< VMON IOVDD0 Channel Fall */
+#define _EMU_IF_VMONIO0FALL_SHIFT                    6                                            /**< Shift value for EMU_VMONIO0FALL */
+#define _EMU_IF_VMONIO0FALL_MASK                     0x40UL                                       /**< Bit mask for EMU_VMONIO0FALL */
+#define _EMU_IF_VMONIO0FALL_DEFAULT                  0x00000000UL                                 /**< Mode DEFAULT for EMU_IF */
+#define EMU_IF_VMONIO0FALL_DEFAULT                   (_EMU_IF_VMONIO0FALL_DEFAULT << 6)           /**< Shifted mode DEFAULT for EMU_IF */
+#define EMU_IF_VMONIO0RISE                           (0x1UL << 7)                                 /**< VMON IOVDD0 Channel Rise */
+#define _EMU_IF_VMONIO0RISE_SHIFT                    7                                            /**< Shift value for EMU_VMONIO0RISE */
+#define _EMU_IF_VMONIO0RISE_MASK                     0x80UL                                       /**< Bit mask for EMU_VMONIO0RISE */
+#define _EMU_IF_VMONIO0RISE_DEFAULT                  0x00000000UL                                 /**< Mode DEFAULT for EMU_IF */
+#define EMU_IF_VMONIO0RISE_DEFAULT                   (_EMU_IF_VMONIO0RISE_DEFAULT << 7)           /**< Shifted mode DEFAULT for EMU_IF */
+#define EMU_IF_VMONFVDDFALL                          (0x1UL << 14)                                /**< VMON VDDFLASH Channel Fall */
+#define _EMU_IF_VMONFVDDFALL_SHIFT                   14                                           /**< Shift value for EMU_VMONFVDDFALL */
+#define _EMU_IF_VMONFVDDFALL_MASK                    0x4000UL                                     /**< Bit mask for EMU_VMONFVDDFALL */
+#define _EMU_IF_VMONFVDDFALL_DEFAULT                 0x00000000UL                                 /**< Mode DEFAULT for EMU_IF */
+#define EMU_IF_VMONFVDDFALL_DEFAULT                  (_EMU_IF_VMONFVDDFALL_DEFAULT << 14)         /**< Shifted mode DEFAULT for EMU_IF */
+#define EMU_IF_VMONFVDDRISE                          (0x1UL << 15)                                /**< VMON VDDFLASH Channel Rise */
+#define _EMU_IF_VMONFVDDRISE_SHIFT                   15                                           /**< Shift value for EMU_VMONFVDDRISE */
+#define _EMU_IF_VMONFVDDRISE_MASK                    0x8000UL                                     /**< Bit mask for EMU_VMONFVDDRISE */
+#define _EMU_IF_VMONFVDDRISE_DEFAULT                 0x00000000UL                                 /**< Mode DEFAULT for EMU_IF */
+#define EMU_IF_VMONFVDDRISE_DEFAULT                  (_EMU_IF_VMONFVDDRISE_DEFAULT << 15)         /**< Shifted mode DEFAULT for EMU_IF */
+#define EMU_IF_PFETOVERCURRENTLIMIT                  (0x1UL << 16)                                /**< PFET current limit hit */
+#define _EMU_IF_PFETOVERCURRENTLIMIT_SHIFT           16                                           /**< Shift value for EMU_PFETOVERCURRENTLIMIT */
+#define _EMU_IF_PFETOVERCURRENTLIMIT_MASK            0x10000UL                                    /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */
+#define _EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT         0x00000000UL                                 /**< Mode DEFAULT for EMU_IF */
+#define EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT          (_EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IF */
+#define EMU_IF_NFETOVERCURRENTLIMIT                  (0x1UL << 17)                                /**< NFET current limit hit */
+#define _EMU_IF_NFETOVERCURRENTLIMIT_SHIFT           17                                           /**< Shift value for EMU_NFETOVERCURRENTLIMIT */
+#define _EMU_IF_NFETOVERCURRENTLIMIT_MASK            0x20000UL                                    /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */
+#define _EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT         0x00000000UL                                 /**< Mode DEFAULT for EMU_IF */
+#define EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT          (_EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IF */
+#define EMU_IF_DCDCLPRUNNING                         (0x1UL << 18)                                /**< LP mode is running */
+#define _EMU_IF_DCDCLPRUNNING_SHIFT                  18                                           /**< Shift value for EMU_DCDCLPRUNNING */
+#define _EMU_IF_DCDCLPRUNNING_MASK                   0x40000UL                                    /**< Bit mask for EMU_DCDCLPRUNNING */
+#define _EMU_IF_DCDCLPRUNNING_DEFAULT                0x00000000UL                                 /**< Mode DEFAULT for EMU_IF */
+#define EMU_IF_DCDCLPRUNNING_DEFAULT                 (_EMU_IF_DCDCLPRUNNING_DEFAULT << 18)        /**< Shifted mode DEFAULT for EMU_IF */
+#define EMU_IF_DCDCLNRUNNING                         (0x1UL << 19)                                /**< LN mode is running */
+#define _EMU_IF_DCDCLNRUNNING_SHIFT                  19                                           /**< Shift value for EMU_DCDCLNRUNNING */
+#define _EMU_IF_DCDCLNRUNNING_MASK                   0x80000UL                                    /**< Bit mask for EMU_DCDCLNRUNNING */
+#define _EMU_IF_DCDCLNRUNNING_DEFAULT                0x00000000UL                                 /**< Mode DEFAULT for EMU_IF */
+#define EMU_IF_DCDCLNRUNNING_DEFAULT                 (_EMU_IF_DCDCLNRUNNING_DEFAULT << 19)        /**< Shifted mode DEFAULT for EMU_IF */
+#define EMU_IF_DCDCINBYPASS                          (0x1UL << 20)                                /**< DCDC is in bypass */
+#define _EMU_IF_DCDCINBYPASS_SHIFT                   20                                           /**< Shift value for EMU_DCDCINBYPASS */
+#define _EMU_IF_DCDCINBYPASS_MASK                    0x100000UL                                   /**< Bit mask for EMU_DCDCINBYPASS */
+#define _EMU_IF_DCDCINBYPASS_DEFAULT                 0x00000000UL                                 /**< Mode DEFAULT for EMU_IF */
+#define EMU_IF_DCDCINBYPASS_DEFAULT                  (_EMU_IF_DCDCINBYPASS_DEFAULT << 20)         /**< Shifted mode DEFAULT for EMU_IF */
+#define EMU_IF_EM23WAKEUP                            (0x1UL << 24)                                /**< Wakeup IRQ from EM2 and EM3 */
+#define _EMU_IF_EM23WAKEUP_SHIFT                     24                                           /**< Shift value for EMU_EM23WAKEUP */
+#define _EMU_IF_EM23WAKEUP_MASK                      0x1000000UL                                  /**< Bit mask for EMU_EM23WAKEUP */
+#define _EMU_IF_EM23WAKEUP_DEFAULT                   0x00000000UL                                 /**< Mode DEFAULT for EMU_IF */
+#define EMU_IF_EM23WAKEUP_DEFAULT                    (_EMU_IF_EM23WAKEUP_DEFAULT << 24)           /**< Shifted mode DEFAULT for EMU_IF */
+#define EMU_IF_TEMP                                  (0x1UL << 29)                                /**< New Temperature Measurement Valid */
+#define _EMU_IF_TEMP_SHIFT                           29                                           /**< Shift value for EMU_TEMP */
+#define _EMU_IF_TEMP_MASK                            0x20000000UL                                 /**< Bit mask for EMU_TEMP */
+#define _EMU_IF_TEMP_DEFAULT                         0x00000000UL                                 /**< Mode DEFAULT for EMU_IF */
+#define EMU_IF_TEMP_DEFAULT                          (_EMU_IF_TEMP_DEFAULT << 29)                 /**< Shifted mode DEFAULT for EMU_IF */
+#define EMU_IF_TEMPLOW                               (0x1UL << 30)                                /**< Temperature Low Limit Reached */
+#define _EMU_IF_TEMPLOW_SHIFT                        30                                           /**< Shift value for EMU_TEMPLOW */
+#define _EMU_IF_TEMPLOW_MASK                         0x40000000UL                                 /**< Bit mask for EMU_TEMPLOW */
+#define _EMU_IF_TEMPLOW_DEFAULT                      0x00000000UL                                 /**< Mode DEFAULT for EMU_IF */
+#define EMU_IF_TEMPLOW_DEFAULT                       (_EMU_IF_TEMPLOW_DEFAULT << 30)              /**< Shifted mode DEFAULT for EMU_IF */
+#define EMU_IF_TEMPHIGH                              (0x1UL << 31)                                /**< Temperature High Limit Reached */
+#define _EMU_IF_TEMPHIGH_SHIFT                       31                                           /**< Shift value for EMU_TEMPHIGH */
+#define _EMU_IF_TEMPHIGH_MASK                        0x80000000UL                                 /**< Bit mask for EMU_TEMPHIGH */
+#define _EMU_IF_TEMPHIGH_DEFAULT                     0x00000000UL                                 /**< Mode DEFAULT for EMU_IF */
+#define EMU_IF_TEMPHIGH_DEFAULT                      (_EMU_IF_TEMPHIGH_DEFAULT << 31)             /**< Shifted mode DEFAULT for EMU_IF */
+
+/* Bit fields for EMU IFS */
+#define _EMU_IFS_RESETVALUE                          0x00000000UL                                  /**< Default value for EMU_IFS */
+#define _EMU_IFS_MASK                                0xE11FF0FFUL                                  /**< Mask for EMU_IFS */
+#define EMU_IFS_VMONAVDDFALL                         (0x1UL << 0)                                  /**< Set VMONAVDDFALL Interrupt Flag */
+#define _EMU_IFS_VMONAVDDFALL_SHIFT                  0                                             /**< Shift value for EMU_VMONAVDDFALL */
+#define _EMU_IFS_VMONAVDDFALL_MASK                   0x1UL                                         /**< Bit mask for EMU_VMONAVDDFALL */
+#define _EMU_IFS_VMONAVDDFALL_DEFAULT                0x00000000UL                                  /**< Mode DEFAULT for EMU_IFS */
+#define EMU_IFS_VMONAVDDFALL_DEFAULT                 (_EMU_IFS_VMONAVDDFALL_DEFAULT << 0)          /**< Shifted mode DEFAULT for EMU_IFS */
+#define EMU_IFS_VMONAVDDRISE                         (0x1UL << 1)                                  /**< Set VMONAVDDRISE Interrupt Flag */
+#define _EMU_IFS_VMONAVDDRISE_SHIFT                  1                                             /**< Shift value for EMU_VMONAVDDRISE */
+#define _EMU_IFS_VMONAVDDRISE_MASK                   0x2UL                                         /**< Bit mask for EMU_VMONAVDDRISE */
+#define _EMU_IFS_VMONAVDDRISE_DEFAULT                0x00000000UL                                  /**< Mode DEFAULT for EMU_IFS */
+#define EMU_IFS_VMONAVDDRISE_DEFAULT                 (_EMU_IFS_VMONAVDDRISE_DEFAULT << 1)          /**< Shifted mode DEFAULT for EMU_IFS */
+#define EMU_IFS_VMONALTAVDDFALL                      (0x1UL << 2)                                  /**< Set VMONALTAVDDFALL Interrupt Flag */
+#define _EMU_IFS_VMONALTAVDDFALL_SHIFT               2                                             /**< Shift value for EMU_VMONALTAVDDFALL */
+#define _EMU_IFS_VMONALTAVDDFALL_MASK                0x4UL                                         /**< Bit mask for EMU_VMONALTAVDDFALL */
+#define _EMU_IFS_VMONALTAVDDFALL_DEFAULT             0x00000000UL                                  /**< Mode DEFAULT for EMU_IFS */
+#define EMU_IFS_VMONALTAVDDFALL_DEFAULT              (_EMU_IFS_VMONALTAVDDFALL_DEFAULT << 2)       /**< Shifted mode DEFAULT for EMU_IFS */
+#define EMU_IFS_VMONALTAVDDRISE                      (0x1UL << 3)                                  /**< Set VMONALTAVDDRISE Interrupt Flag */
+#define _EMU_IFS_VMONALTAVDDRISE_SHIFT               3                                             /**< Shift value for EMU_VMONALTAVDDRISE */
+#define _EMU_IFS_VMONALTAVDDRISE_MASK                0x8UL                                         /**< Bit mask for EMU_VMONALTAVDDRISE */
+#define _EMU_IFS_VMONALTAVDDRISE_DEFAULT             0x00000000UL                                  /**< Mode DEFAULT for EMU_IFS */
+#define EMU_IFS_VMONALTAVDDRISE_DEFAULT              (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3)       /**< Shifted mode DEFAULT for EMU_IFS */
+#define EMU_IFS_VMONDVDDFALL                         (0x1UL << 4)                                  /**< Set VMONDVDDFALL Interrupt Flag */
+#define _EMU_IFS_VMONDVDDFALL_SHIFT                  4                                             /**< Shift value for EMU_VMONDVDDFALL */
+#define _EMU_IFS_VMONDVDDFALL_MASK                   0x10UL                                        /**< Bit mask for EMU_VMONDVDDFALL */
+#define _EMU_IFS_VMONDVDDFALL_DEFAULT                0x00000000UL                                  /**< Mode DEFAULT for EMU_IFS */
+#define EMU_IFS_VMONDVDDFALL_DEFAULT                 (_EMU_IFS_VMONDVDDFALL_DEFAULT << 4)          /**< Shifted mode DEFAULT for EMU_IFS */
+#define EMU_IFS_VMONDVDDRISE                         (0x1UL << 5)                                  /**< Set VMONDVDDRISE Interrupt Flag */
+#define _EMU_IFS_VMONDVDDRISE_SHIFT                  5                                             /**< Shift value for EMU_VMONDVDDRISE */
+#define _EMU_IFS_VMONDVDDRISE_MASK                   0x20UL                                        /**< Bit mask for EMU_VMONDVDDRISE */
+#define _EMU_IFS_VMONDVDDRISE_DEFAULT                0x00000000UL                                  /**< Mode DEFAULT for EMU_IFS */
+#define EMU_IFS_VMONDVDDRISE_DEFAULT                 (_EMU_IFS_VMONDVDDRISE_DEFAULT << 5)          /**< Shifted mode DEFAULT for EMU_IFS */
+#define EMU_IFS_VMONIO0FALL                          (0x1UL << 6)                                  /**< Set VMONIO0FALL Interrupt Flag */
+#define _EMU_IFS_VMONIO0FALL_SHIFT                   6                                             /**< Shift value for EMU_VMONIO0FALL */
+#define _EMU_IFS_VMONIO0FALL_MASK                    0x40UL                                        /**< Bit mask for EMU_VMONIO0FALL */
+#define _EMU_IFS_VMONIO0FALL_DEFAULT                 0x00000000UL                                  /**< Mode DEFAULT for EMU_IFS */
+#define EMU_IFS_VMONIO0FALL_DEFAULT                  (_EMU_IFS_VMONIO0FALL_DEFAULT << 6)           /**< Shifted mode DEFAULT for EMU_IFS */
+#define EMU_IFS_VMONIO0RISE                          (0x1UL << 7)                                  /**< Set VMONIO0RISE Interrupt Flag */
+#define _EMU_IFS_VMONIO0RISE_SHIFT                   7                                             /**< Shift value for EMU_VMONIO0RISE */
+#define _EMU_IFS_VMONIO0RISE_MASK                    0x80UL                                        /**< Bit mask for EMU_VMONIO0RISE */
+#define _EMU_IFS_VMONIO0RISE_DEFAULT                 0x00000000UL                                  /**< Mode DEFAULT for EMU_IFS */
+#define EMU_IFS_VMONIO0RISE_DEFAULT                  (_EMU_IFS_VMONIO0RISE_DEFAULT << 7)           /**< Shifted mode DEFAULT for EMU_IFS */
+#define EMU_IFS_VMONPAVDDFALL                        (0x1UL << 12)                                 /**< Set VMONPAVDDFALL Interrupt Flag */
+#define _EMU_IFS_VMONPAVDDFALL_SHIFT                 12                                            /**< Shift value for EMU_VMONPAVDDFALL */
+#define _EMU_IFS_VMONPAVDDFALL_MASK                  0x1000UL                                      /**< Bit mask for EMU_VMONPAVDDFALL */
+#define _EMU_IFS_VMONPAVDDFALL_DEFAULT               0x00000000UL                                  /**< Mode DEFAULT for EMU_IFS */
+#define EMU_IFS_VMONPAVDDFALL_DEFAULT                (_EMU_IFS_VMONPAVDDFALL_DEFAULT << 12)        /**< Shifted mode DEFAULT for EMU_IFS */
+#define EMU_IFS_VMONPAVDDRISE                        (0x1UL << 13)                                 /**< Set VMONPAVDDRISE Interrupt Flag */
+#define _EMU_IFS_VMONPAVDDRISE_SHIFT                 13                                            /**< Shift value for EMU_VMONPAVDDRISE */
+#define _EMU_IFS_VMONPAVDDRISE_MASK                  0x2000UL                                      /**< Bit mask for EMU_VMONPAVDDRISE */
+#define _EMU_IFS_VMONPAVDDRISE_DEFAULT               0x00000000UL                                  /**< Mode DEFAULT for EMU_IFS */
+#define EMU_IFS_VMONPAVDDRISE_DEFAULT                (_EMU_IFS_VMONPAVDDRISE_DEFAULT << 13)        /**< Shifted mode DEFAULT for EMU_IFS */
+#define EMU_IFS_VMONFVDDFALL                         (0x1UL << 14)                                 /**< Set VMONFVDDFALL Interrupt Flag */
+#define _EMU_IFS_VMONFVDDFALL_SHIFT                  14                                            /**< Shift value for EMU_VMONFVDDFALL */
+#define _EMU_IFS_VMONFVDDFALL_MASK                   0x4000UL                                      /**< Bit mask for EMU_VMONFVDDFALL */
+#define _EMU_IFS_VMONFVDDFALL_DEFAULT                0x00000000UL                                  /**< Mode DEFAULT for EMU_IFS */
+#define EMU_IFS_VMONFVDDFALL_DEFAULT                 (_EMU_IFS_VMONFVDDFALL_DEFAULT << 14)         /**< Shifted mode DEFAULT for EMU_IFS */
+#define EMU_IFS_VMONFVDDRISE                         (0x1UL << 15)                                 /**< Set VMONFVDDRISE Interrupt Flag */
+#define _EMU_IFS_VMONFVDDRISE_SHIFT                  15                                            /**< Shift value for EMU_VMONFVDDRISE */
+#define _EMU_IFS_VMONFVDDRISE_MASK                   0x8000UL                                      /**< Bit mask for EMU_VMONFVDDRISE */
+#define _EMU_IFS_VMONFVDDRISE_DEFAULT                0x00000000UL                                  /**< Mode DEFAULT for EMU_IFS */
+#define EMU_IFS_VMONFVDDRISE_DEFAULT                 (_EMU_IFS_VMONFVDDRISE_DEFAULT << 15)         /**< Shifted mode DEFAULT for EMU_IFS */
+#define EMU_IFS_PFETOVERCURRENTLIMIT                 (0x1UL << 16)                                 /**< Set PFETOVERCURRENTLIMIT Interrupt Flag */
+#define _EMU_IFS_PFETOVERCURRENTLIMIT_SHIFT          16                                            /**< Shift value for EMU_PFETOVERCURRENTLIMIT */
+#define _EMU_IFS_PFETOVERCURRENTLIMIT_MASK           0x10000UL                                     /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */
+#define _EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT        0x00000000UL                                  /**< Mode DEFAULT for EMU_IFS */
+#define EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT         (_EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFS */
+#define EMU_IFS_NFETOVERCURRENTLIMIT                 (0x1UL << 17)                                 /**< Set NFETOVERCURRENTLIMIT Interrupt Flag */
+#define _EMU_IFS_NFETOVERCURRENTLIMIT_SHIFT          17                                            /**< Shift value for EMU_NFETOVERCURRENTLIMIT */
+#define _EMU_IFS_NFETOVERCURRENTLIMIT_MASK           0x20000UL                                     /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */
+#define _EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT        0x00000000UL                                  /**< Mode DEFAULT for EMU_IFS */
+#define EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT         (_EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFS */
+#define EMU_IFS_DCDCLPRUNNING                        (0x1UL << 18)                                 /**< Set DCDCLPRUNNING Interrupt Flag */
+#define _EMU_IFS_DCDCLPRUNNING_SHIFT                 18                                            /**< Shift value for EMU_DCDCLPRUNNING */
+#define _EMU_IFS_DCDCLPRUNNING_MASK                  0x40000UL                                     /**< Bit mask for EMU_DCDCLPRUNNING */
+#define _EMU_IFS_DCDCLPRUNNING_DEFAULT               0x00000000UL                                  /**< Mode DEFAULT for EMU_IFS */
+#define EMU_IFS_DCDCLPRUNNING_DEFAULT                (_EMU_IFS_DCDCLPRUNNING_DEFAULT << 18)        /**< Shifted mode DEFAULT for EMU_IFS */
+#define EMU_IFS_DCDCLNRUNNING                        (0x1UL << 19)                                 /**< Set DCDCLNRUNNING Interrupt Flag */
+#define _EMU_IFS_DCDCLNRUNNING_SHIFT                 19                                            /**< Shift value for EMU_DCDCLNRUNNING */
+#define _EMU_IFS_DCDCLNRUNNING_MASK                  0x80000UL                                     /**< Bit mask for EMU_DCDCLNRUNNING */
+#define _EMU_IFS_DCDCLNRUNNING_DEFAULT               0x00000000UL                                  /**< Mode DEFAULT for EMU_IFS */
+#define EMU_IFS_DCDCLNRUNNING_DEFAULT                (_EMU_IFS_DCDCLNRUNNING_DEFAULT << 19)        /**< Shifted mode DEFAULT for EMU_IFS */
+#define EMU_IFS_DCDCINBYPASS                         (0x1UL << 20)                                 /**< Set DCDCINBYPASS Interrupt Flag */
+#define _EMU_IFS_DCDCINBYPASS_SHIFT                  20                                            /**< Shift value for EMU_DCDCINBYPASS */
+#define _EMU_IFS_DCDCINBYPASS_MASK                   0x100000UL                                    /**< Bit mask for EMU_DCDCINBYPASS */
+#define _EMU_IFS_DCDCINBYPASS_DEFAULT                0x00000000UL                                  /**< Mode DEFAULT for EMU_IFS */
+#define EMU_IFS_DCDCINBYPASS_DEFAULT                 (_EMU_IFS_DCDCINBYPASS_DEFAULT << 20)         /**< Shifted mode DEFAULT for EMU_IFS */
+#define EMU_IFS_EM23WAKEUP                           (0x1UL << 24)                                 /**< Set EM23WAKEUP Interrupt Flag */
+#define _EMU_IFS_EM23WAKEUP_SHIFT                    24                                            /**< Shift value for EMU_EM23WAKEUP */
+#define _EMU_IFS_EM23WAKEUP_MASK                     0x1000000UL                                   /**< Bit mask for EMU_EM23WAKEUP */
+#define _EMU_IFS_EM23WAKEUP_DEFAULT                  0x00000000UL                                  /**< Mode DEFAULT for EMU_IFS */
+#define EMU_IFS_EM23WAKEUP_DEFAULT                   (_EMU_IFS_EM23WAKEUP_DEFAULT << 24)           /**< Shifted mode DEFAULT for EMU_IFS */
+#define EMU_IFS_TEMP                                 (0x1UL << 29)                                 /**< Set TEMP Interrupt Flag */
+#define _EMU_IFS_TEMP_SHIFT                          29                                            /**< Shift value for EMU_TEMP */
+#define _EMU_IFS_TEMP_MASK                           0x20000000UL                                  /**< Bit mask for EMU_TEMP */
+#define _EMU_IFS_TEMP_DEFAULT                        0x00000000UL                                  /**< Mode DEFAULT for EMU_IFS */
+#define EMU_IFS_TEMP_DEFAULT                         (_EMU_IFS_TEMP_DEFAULT << 29)                 /**< Shifted mode DEFAULT for EMU_IFS */
+#define EMU_IFS_TEMPLOW                              (0x1UL << 30)                                 /**< Set TEMPLOW Interrupt Flag */
+#define _EMU_IFS_TEMPLOW_SHIFT                       30                                            /**< Shift value for EMU_TEMPLOW */
+#define _EMU_IFS_TEMPLOW_MASK                        0x40000000UL                                  /**< Bit mask for EMU_TEMPLOW */
+#define _EMU_IFS_TEMPLOW_DEFAULT                     0x00000000UL                                  /**< Mode DEFAULT for EMU_IFS */
+#define EMU_IFS_TEMPLOW_DEFAULT                      (_EMU_IFS_TEMPLOW_DEFAULT << 30)              /**< Shifted mode DEFAULT for EMU_IFS */
+#define EMU_IFS_TEMPHIGH                             (0x1UL << 31)                                 /**< Set TEMPHIGH Interrupt Flag */
+#define _EMU_IFS_TEMPHIGH_SHIFT                      31                                            /**< Shift value for EMU_TEMPHIGH */
+#define _EMU_IFS_TEMPHIGH_MASK                       0x80000000UL                                  /**< Bit mask for EMU_TEMPHIGH */
+#define _EMU_IFS_TEMPHIGH_DEFAULT                    0x00000000UL                                  /**< Mode DEFAULT for EMU_IFS */
+#define EMU_IFS_TEMPHIGH_DEFAULT                     (_EMU_IFS_TEMPHIGH_DEFAULT << 31)             /**< Shifted mode DEFAULT for EMU_IFS */
+
+/* Bit fields for EMU IFC */
+#define _EMU_IFC_RESETVALUE                          0x00000000UL                                  /**< Default value for EMU_IFC */
+#define _EMU_IFC_MASK                                0xE11FF0FFUL                                  /**< Mask for EMU_IFC */
+#define EMU_IFC_VMONAVDDFALL                         (0x1UL << 0)                                  /**< Clear VMONAVDDFALL Interrupt Flag */
+#define _EMU_IFC_VMONAVDDFALL_SHIFT                  0                                             /**< Shift value for EMU_VMONAVDDFALL */
+#define _EMU_IFC_VMONAVDDFALL_MASK                   0x1UL                                         /**< Bit mask for EMU_VMONAVDDFALL */
+#define _EMU_IFC_VMONAVDDFALL_DEFAULT                0x00000000UL                                  /**< Mode DEFAULT for EMU_IFC */
+#define EMU_IFC_VMONAVDDFALL_DEFAULT                 (_EMU_IFC_VMONAVDDFALL_DEFAULT << 0)          /**< Shifted mode DEFAULT for EMU_IFC */
+#define EMU_IFC_VMONAVDDRISE                         (0x1UL << 1)                                  /**< Clear VMONAVDDRISE Interrupt Flag */
+#define _EMU_IFC_VMONAVDDRISE_SHIFT                  1                                             /**< Shift value for EMU_VMONAVDDRISE */
+#define _EMU_IFC_VMONAVDDRISE_MASK                   0x2UL                                         /**< Bit mask for EMU_VMONAVDDRISE */
+#define _EMU_IFC_VMONAVDDRISE_DEFAULT                0x00000000UL                                  /**< Mode DEFAULT for EMU_IFC */
+#define EMU_IFC_VMONAVDDRISE_DEFAULT                 (_EMU_IFC_VMONAVDDRISE_DEFAULT << 1)          /**< Shifted mode DEFAULT for EMU_IFC */
+#define EMU_IFC_VMONALTAVDDFALL                      (0x1UL << 2)                                  /**< Clear VMONALTAVDDFALL Interrupt Flag */
+#define _EMU_IFC_VMONALTAVDDFALL_SHIFT               2                                             /**< Shift value for EMU_VMONALTAVDDFALL */
+#define _EMU_IFC_VMONALTAVDDFALL_MASK                0x4UL                                         /**< Bit mask for EMU_VMONALTAVDDFALL */
+#define _EMU_IFC_VMONALTAVDDFALL_DEFAULT             0x00000000UL                                  /**< Mode DEFAULT for EMU_IFC */
+#define EMU_IFC_VMONALTAVDDFALL_DEFAULT              (_EMU_IFC_VMONALTAVDDFALL_DEFAULT << 2)       /**< Shifted mode DEFAULT for EMU_IFC */
+#define EMU_IFC_VMONALTAVDDRISE                      (0x1UL << 3)                                  /**< Clear VMONALTAVDDRISE Interrupt Flag */
+#define _EMU_IFC_VMONALTAVDDRISE_SHIFT               3                                             /**< Shift value for EMU_VMONALTAVDDRISE */
+#define _EMU_IFC_VMONALTAVDDRISE_MASK                0x8UL                                         /**< Bit mask for EMU_VMONALTAVDDRISE */
+#define _EMU_IFC_VMONALTAVDDRISE_DEFAULT             0x00000000UL                                  /**< Mode DEFAULT for EMU_IFC */
+#define EMU_IFC_VMONALTAVDDRISE_DEFAULT              (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3)       /**< Shifted mode DEFAULT for EMU_IFC */
+#define EMU_IFC_VMONDVDDFALL                         (0x1UL << 4)                                  /**< Clear VMONDVDDFALL Interrupt Flag */
+#define _EMU_IFC_VMONDVDDFALL_SHIFT                  4                                             /**< Shift value for EMU_VMONDVDDFALL */
+#define _EMU_IFC_VMONDVDDFALL_MASK                   0x10UL                                        /**< Bit mask for EMU_VMONDVDDFALL */
+#define _EMU_IFC_VMONDVDDFALL_DEFAULT                0x00000000UL                                  /**< Mode DEFAULT for EMU_IFC */
+#define EMU_IFC_VMONDVDDFALL_DEFAULT                 (_EMU_IFC_VMONDVDDFALL_DEFAULT << 4)          /**< Shifted mode DEFAULT for EMU_IFC */
+#define EMU_IFC_VMONDVDDRISE                         (0x1UL << 5)                                  /**< Clear VMONDVDDRISE Interrupt Flag */
+#define _EMU_IFC_VMONDVDDRISE_SHIFT                  5                                             /**< Shift value for EMU_VMONDVDDRISE */
+#define _EMU_IFC_VMONDVDDRISE_MASK                   0x20UL                                        /**< Bit mask for EMU_VMONDVDDRISE */
+#define _EMU_IFC_VMONDVDDRISE_DEFAULT                0x00000000UL                                  /**< Mode DEFAULT for EMU_IFC */
+#define EMU_IFC_VMONDVDDRISE_DEFAULT                 (_EMU_IFC_VMONDVDDRISE_DEFAULT << 5)          /**< Shifted mode DEFAULT for EMU_IFC */
+#define EMU_IFC_VMONIO0FALL                          (0x1UL << 6)                                  /**< Clear VMONIO0FALL Interrupt Flag */
+#define _EMU_IFC_VMONIO0FALL_SHIFT                   6                                             /**< Shift value for EMU_VMONIO0FALL */
+#define _EMU_IFC_VMONIO0FALL_MASK                    0x40UL                                        /**< Bit mask for EMU_VMONIO0FALL */
+#define _EMU_IFC_VMONIO0FALL_DEFAULT                 0x00000000UL                                  /**< Mode DEFAULT for EMU_IFC */
+#define EMU_IFC_VMONIO0FALL_DEFAULT                  (_EMU_IFC_VMONIO0FALL_DEFAULT << 6)           /**< Shifted mode DEFAULT for EMU_IFC */
+#define EMU_IFC_VMONIO0RISE                          (0x1UL << 7)                                  /**< Clear VMONIO0RISE Interrupt Flag */
+#define _EMU_IFC_VMONIO0RISE_SHIFT                   7                                             /**< Shift value for EMU_VMONIO0RISE */
+#define _EMU_IFC_VMONIO0RISE_MASK                    0x80UL                                        /**< Bit mask for EMU_VMONIO0RISE */
+#define _EMU_IFC_VMONIO0RISE_DEFAULT                 0x00000000UL                                  /**< Mode DEFAULT for EMU_IFC */
+#define EMU_IFC_VMONIO0RISE_DEFAULT                  (_EMU_IFC_VMONIO0RISE_DEFAULT << 7)           /**< Shifted mode DEFAULT for EMU_IFC */
+#define EMU_IFC_VMONPAVDDFALL                        (0x1UL << 12)                                 /**< Clear VMONPAVDDFALL Interrupt Flag */
+#define _EMU_IFC_VMONPAVDDFALL_SHIFT                 12                                            /**< Shift value for EMU_VMONPAVDDFALL */
+#define _EMU_IFC_VMONPAVDDFALL_MASK                  0x1000UL                                      /**< Bit mask for EMU_VMONPAVDDFALL */
+#define _EMU_IFC_VMONPAVDDFALL_DEFAULT               0x00000000UL                                  /**< Mode DEFAULT for EMU_IFC */
+#define EMU_IFC_VMONPAVDDFALL_DEFAULT                (_EMU_IFC_VMONPAVDDFALL_DEFAULT << 12)        /**< Shifted mode DEFAULT for EMU_IFC */
+#define EMU_IFC_VMONPAVDDRISE                        (0x1UL << 13)                                 /**< Clear VMONPAVDDRISE Interrupt Flag */
+#define _EMU_IFC_VMONPAVDDRISE_SHIFT                 13                                            /**< Shift value for EMU_VMONPAVDDRISE */
+#define _EMU_IFC_VMONPAVDDRISE_MASK                  0x2000UL                                      /**< Bit mask for EMU_VMONPAVDDRISE */
+#define _EMU_IFC_VMONPAVDDRISE_DEFAULT               0x00000000UL                                  /**< Mode DEFAULT for EMU_IFC */
+#define EMU_IFC_VMONPAVDDRISE_DEFAULT                (_EMU_IFC_VMONPAVDDRISE_DEFAULT << 13)        /**< Shifted mode DEFAULT for EMU_IFC */
+#define EMU_IFC_VMONFVDDFALL                         (0x1UL << 14)                                 /**< Clear VMONFVDDFALL Interrupt Flag */
+#define _EMU_IFC_VMONFVDDFALL_SHIFT                  14                                            /**< Shift value for EMU_VMONFVDDFALL */
+#define _EMU_IFC_VMONFVDDFALL_MASK                   0x4000UL                                      /**< Bit mask for EMU_VMONFVDDFALL */
+#define _EMU_IFC_VMONFVDDFALL_DEFAULT                0x00000000UL                                  /**< Mode DEFAULT for EMU_IFC */
+#define EMU_IFC_VMONFVDDFALL_DEFAULT                 (_EMU_IFC_VMONFVDDFALL_DEFAULT << 14)         /**< Shifted mode DEFAULT for EMU_IFC */
+#define EMU_IFC_VMONFVDDRISE                         (0x1UL << 15)                                 /**< Clear VMONFVDDRISE Interrupt Flag */
+#define _EMU_IFC_VMONFVDDRISE_SHIFT                  15                                            /**< Shift value for EMU_VMONFVDDRISE */
+#define _EMU_IFC_VMONFVDDRISE_MASK                   0x8000UL                                      /**< Bit mask for EMU_VMONFVDDRISE */
+#define _EMU_IFC_VMONFVDDRISE_DEFAULT                0x00000000UL                                  /**< Mode DEFAULT for EMU_IFC */
+#define EMU_IFC_VMONFVDDRISE_DEFAULT                 (_EMU_IFC_VMONFVDDRISE_DEFAULT << 15)         /**< Shifted mode DEFAULT for EMU_IFC */
+#define EMU_IFC_PFETOVERCURRENTLIMIT                 (0x1UL << 16)                                 /**< Clear PFETOVERCURRENTLIMIT Interrupt Flag */
+#define _EMU_IFC_PFETOVERCURRENTLIMIT_SHIFT          16                                            /**< Shift value for EMU_PFETOVERCURRENTLIMIT */
+#define _EMU_IFC_PFETOVERCURRENTLIMIT_MASK           0x10000UL                                     /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */
+#define _EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT        0x00000000UL                                  /**< Mode DEFAULT for EMU_IFC */
+#define EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT         (_EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFC */
+#define EMU_IFC_NFETOVERCURRENTLIMIT                 (0x1UL << 17)                                 /**< Clear NFETOVERCURRENTLIMIT Interrupt Flag */
+#define _EMU_IFC_NFETOVERCURRENTLIMIT_SHIFT          17                                            /**< Shift value for EMU_NFETOVERCURRENTLIMIT */
+#define _EMU_IFC_NFETOVERCURRENTLIMIT_MASK           0x20000UL                                     /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */
+#define _EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT        0x00000000UL                                  /**< Mode DEFAULT for EMU_IFC */
+#define EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT         (_EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFC */
+#define EMU_IFC_DCDCLPRUNNING                        (0x1UL << 18)                                 /**< Clear DCDCLPRUNNING Interrupt Flag */
+#define _EMU_IFC_DCDCLPRUNNING_SHIFT                 18                                            /**< Shift value for EMU_DCDCLPRUNNING */
+#define _EMU_IFC_DCDCLPRUNNING_MASK                  0x40000UL                                     /**< Bit mask for EMU_DCDCLPRUNNING */
+#define _EMU_IFC_DCDCLPRUNNING_DEFAULT               0x00000000UL                                  /**< Mode DEFAULT for EMU_IFC */
+#define EMU_IFC_DCDCLPRUNNING_DEFAULT                (_EMU_IFC_DCDCLPRUNNING_DEFAULT << 18)        /**< Shifted mode DEFAULT for EMU_IFC */
+#define EMU_IFC_DCDCLNRUNNING                        (0x1UL << 19)                                 /**< Clear DCDCLNRUNNING Interrupt Flag */
+#define _EMU_IFC_DCDCLNRUNNING_SHIFT                 19                                            /**< Shift value for EMU_DCDCLNRUNNING */
+#define _EMU_IFC_DCDCLNRUNNING_MASK                  0x80000UL                                     /**< Bit mask for EMU_DCDCLNRUNNING */
+#define _EMU_IFC_DCDCLNRUNNING_DEFAULT               0x00000000UL                                  /**< Mode DEFAULT for EMU_IFC */
+#define EMU_IFC_DCDCLNRUNNING_DEFAULT                (_EMU_IFC_DCDCLNRUNNING_DEFAULT << 19)        /**< Shifted mode DEFAULT for EMU_IFC */
+#define EMU_IFC_DCDCINBYPASS                         (0x1UL << 20)                                 /**< Clear DCDCINBYPASS Interrupt Flag */
+#define _EMU_IFC_DCDCINBYPASS_SHIFT                  20                                            /**< Shift value for EMU_DCDCINBYPASS */
+#define _EMU_IFC_DCDCINBYPASS_MASK                   0x100000UL                                    /**< Bit mask for EMU_DCDCINBYPASS */
+#define _EMU_IFC_DCDCINBYPASS_DEFAULT                0x00000000UL                                  /**< Mode DEFAULT for EMU_IFC */
+#define EMU_IFC_DCDCINBYPASS_DEFAULT                 (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20)         /**< Shifted mode DEFAULT for EMU_IFC */
+#define EMU_IFC_EM23WAKEUP                           (0x1UL << 24)                                 /**< Clear EM23WAKEUP Interrupt Flag */
+#define _EMU_IFC_EM23WAKEUP_SHIFT                    24                                            /**< Shift value for EMU_EM23WAKEUP */
+#define _EMU_IFC_EM23WAKEUP_MASK                     0x1000000UL                                   /**< Bit mask for EMU_EM23WAKEUP */
+#define _EMU_IFC_EM23WAKEUP_DEFAULT                  0x00000000UL                                  /**< Mode DEFAULT for EMU_IFC */
+#define EMU_IFC_EM23WAKEUP_DEFAULT                   (_EMU_IFC_EM23WAKEUP_DEFAULT << 24)           /**< Shifted mode DEFAULT for EMU_IFC */
+#define EMU_IFC_TEMP                                 (0x1UL << 29)                                 /**< Clear TEMP Interrupt Flag */
+#define _EMU_IFC_TEMP_SHIFT                          29                                            /**< Shift value for EMU_TEMP */
+#define _EMU_IFC_TEMP_MASK                           0x20000000UL                                  /**< Bit mask for EMU_TEMP */
+#define _EMU_IFC_TEMP_DEFAULT                        0x00000000UL                                  /**< Mode DEFAULT for EMU_IFC */
+#define EMU_IFC_TEMP_DEFAULT                         (_EMU_IFC_TEMP_DEFAULT << 29)                 /**< Shifted mode DEFAULT for EMU_IFC */
+#define EMU_IFC_TEMPLOW                              (0x1UL << 30)                                 /**< Clear TEMPLOW Interrupt Flag */
+#define _EMU_IFC_TEMPLOW_SHIFT                       30                                            /**< Shift value for EMU_TEMPLOW */
+#define _EMU_IFC_TEMPLOW_MASK                        0x40000000UL                                  /**< Bit mask for EMU_TEMPLOW */
+#define _EMU_IFC_TEMPLOW_DEFAULT                     0x00000000UL                                  /**< Mode DEFAULT for EMU_IFC */
+#define EMU_IFC_TEMPLOW_DEFAULT                      (_EMU_IFC_TEMPLOW_DEFAULT << 30)              /**< Shifted mode DEFAULT for EMU_IFC */
+#define EMU_IFC_TEMPHIGH                             (0x1UL << 31)                                 /**< Clear TEMPHIGH Interrupt Flag */
+#define _EMU_IFC_TEMPHIGH_SHIFT                      31                                            /**< Shift value for EMU_TEMPHIGH */
+#define _EMU_IFC_TEMPHIGH_MASK                       0x80000000UL                                  /**< Bit mask for EMU_TEMPHIGH */
+#define _EMU_IFC_TEMPHIGH_DEFAULT                    0x00000000UL                                  /**< Mode DEFAULT for EMU_IFC */
+#define EMU_IFC_TEMPHIGH_DEFAULT                     (_EMU_IFC_TEMPHIGH_DEFAULT << 31)             /**< Shifted mode DEFAULT for EMU_IFC */
+
+/* Bit fields for EMU IEN */
+#define _EMU_IEN_RESETVALUE                          0x00000000UL                                  /**< Default value for EMU_IEN */
+#define _EMU_IEN_MASK                                0xE11FF0FFUL                                  /**< Mask for EMU_IEN */
+#define EMU_IEN_VMONAVDDFALL                         (0x1UL << 0)                                  /**< VMONAVDDFALL Interrupt Enable */
+#define _EMU_IEN_VMONAVDDFALL_SHIFT                  0                                             /**< Shift value for EMU_VMONAVDDFALL */
+#define _EMU_IEN_VMONAVDDFALL_MASK                   0x1UL                                         /**< Bit mask for EMU_VMONAVDDFALL */
+#define _EMU_IEN_VMONAVDDFALL_DEFAULT                0x00000000UL                                  /**< Mode DEFAULT for EMU_IEN */
+#define EMU_IEN_VMONAVDDFALL_DEFAULT                 (_EMU_IEN_VMONAVDDFALL_DEFAULT << 0)          /**< Shifted mode DEFAULT for EMU_IEN */
+#define EMU_IEN_VMONAVDDRISE                         (0x1UL << 1)                                  /**< VMONAVDDRISE Interrupt Enable */
+#define _EMU_IEN_VMONAVDDRISE_SHIFT                  1                                             /**< Shift value for EMU_VMONAVDDRISE */
+#define _EMU_IEN_VMONAVDDRISE_MASK                   0x2UL                                         /**< Bit mask for EMU_VMONAVDDRISE */
+#define _EMU_IEN_VMONAVDDRISE_DEFAULT                0x00000000UL                                  /**< Mode DEFAULT for EMU_IEN */
+#define EMU_IEN_VMONAVDDRISE_DEFAULT                 (_EMU_IEN_VMONAVDDRISE_DEFAULT << 1)          /**< Shifted mode DEFAULT for EMU_IEN */
+#define EMU_IEN_VMONALTAVDDFALL                      (0x1UL << 2)                                  /**< VMONALTAVDDFALL Interrupt Enable */
+#define _EMU_IEN_VMONALTAVDDFALL_SHIFT               2                                             /**< Shift value for EMU_VMONALTAVDDFALL */
+#define _EMU_IEN_VMONALTAVDDFALL_MASK                0x4UL                                         /**< Bit mask for EMU_VMONALTAVDDFALL */
+#define _EMU_IEN_VMONALTAVDDFALL_DEFAULT             0x00000000UL                                  /**< Mode DEFAULT for EMU_IEN */
+#define EMU_IEN_VMONALTAVDDFALL_DEFAULT              (_EMU_IEN_VMONALTAVDDFALL_DEFAULT << 2)       /**< Shifted mode DEFAULT for EMU_IEN */
+#define EMU_IEN_VMONALTAVDDRISE                      (0x1UL << 3)                                  /**< VMONALTAVDDRISE Interrupt Enable */
+#define _EMU_IEN_VMONALTAVDDRISE_SHIFT               3                                             /**< Shift value for EMU_VMONALTAVDDRISE */
+#define _EMU_IEN_VMONALTAVDDRISE_MASK                0x8UL                                         /**< Bit mask for EMU_VMONALTAVDDRISE */
+#define _EMU_IEN_VMONALTAVDDRISE_DEFAULT             0x00000000UL                                  /**< Mode DEFAULT for EMU_IEN */
+#define EMU_IEN_VMONALTAVDDRISE_DEFAULT              (_EMU_IEN_VMONALTAVDDRISE_DEFAULT << 3)       /**< Shifted mode DEFAULT for EMU_IEN */
+#define EMU_IEN_VMONDVDDFALL                         (0x1UL << 4)                                  /**< VMONDVDDFALL Interrupt Enable */
+#define _EMU_IEN_VMONDVDDFALL_SHIFT                  4                                             /**< Shift value for EMU_VMONDVDDFALL */
+#define _EMU_IEN_VMONDVDDFALL_MASK                   0x10UL                                        /**< Bit mask for EMU_VMONDVDDFALL */
+#define _EMU_IEN_VMONDVDDFALL_DEFAULT                0x00000000UL                                  /**< Mode DEFAULT for EMU_IEN */
+#define EMU_IEN_VMONDVDDFALL_DEFAULT                 (_EMU_IEN_VMONDVDDFALL_DEFAULT << 4)          /**< Shifted mode DEFAULT for EMU_IEN */
+#define EMU_IEN_VMONDVDDRISE                         (0x1UL << 5)                                  /**< VMONDVDDRISE Interrupt Enable */
+#define _EMU_IEN_VMONDVDDRISE_SHIFT                  5                                             /**< Shift value for EMU_VMONDVDDRISE */
+#define _EMU_IEN_VMONDVDDRISE_MASK                   0x20UL                                        /**< Bit mask for EMU_VMONDVDDRISE */
+#define _EMU_IEN_VMONDVDDRISE_DEFAULT                0x00000000UL                                  /**< Mode DEFAULT for EMU_IEN */
+#define EMU_IEN_VMONDVDDRISE_DEFAULT                 (_EMU_IEN_VMONDVDDRISE_DEFAULT << 5)          /**< Shifted mode DEFAULT for EMU_IEN */
+#define EMU_IEN_VMONIO0FALL                          (0x1UL << 6)                                  /**< VMONIO0FALL Interrupt Enable */
+#define _EMU_IEN_VMONIO0FALL_SHIFT                   6                                             /**< Shift value for EMU_VMONIO0FALL */
+#define _EMU_IEN_VMONIO0FALL_MASK                    0x40UL                                        /**< Bit mask for EMU_VMONIO0FALL */
+#define _EMU_IEN_VMONIO0FALL_DEFAULT                 0x00000000UL                                  /**< Mode DEFAULT for EMU_IEN */
+#define EMU_IEN_VMONIO0FALL_DEFAULT                  (_EMU_IEN_VMONIO0FALL_DEFAULT << 6)           /**< Shifted mode DEFAULT for EMU_IEN */
+#define EMU_IEN_VMONIO0RISE                          (0x1UL << 7)                                  /**< VMONIO0RISE Interrupt Enable */
+#define _EMU_IEN_VMONIO0RISE_SHIFT                   7                                             /**< Shift value for EMU_VMONIO0RISE */
+#define _EMU_IEN_VMONIO0RISE_MASK                    0x80UL                                        /**< Bit mask for EMU_VMONIO0RISE */
+#define _EMU_IEN_VMONIO0RISE_DEFAULT                 0x00000000UL                                  /**< Mode DEFAULT for EMU_IEN */
+#define EMU_IEN_VMONIO0RISE_DEFAULT                  (_EMU_IEN_VMONIO0RISE_DEFAULT << 7)           /**< Shifted mode DEFAULT for EMU_IEN */
+#define EMU_IEN_VMONPAVDDFALL                        (0x1UL << 12)                                 /**< VMONPAVDDFALL Interrupt Enable */
+#define _EMU_IEN_VMONPAVDDFALL_SHIFT                 12                                            /**< Shift value for EMU_VMONPAVDDFALL */
+#define _EMU_IEN_VMONPAVDDFALL_MASK                  0x1000UL                                      /**< Bit mask for EMU_VMONPAVDDFALL */
+#define _EMU_IEN_VMONPAVDDFALL_DEFAULT               0x00000000UL                                  /**< Mode DEFAULT for EMU_IEN */
+#define EMU_IEN_VMONPAVDDFALL_DEFAULT                (_EMU_IEN_VMONPAVDDFALL_DEFAULT << 12)        /**< Shifted mode DEFAULT for EMU_IEN */
+#define EMU_IEN_VMONPAVDDRISE                        (0x1UL << 13)                                 /**< VMONPAVDDRISE Interrupt Enable */
+#define _EMU_IEN_VMONPAVDDRISE_SHIFT                 13                                            /**< Shift value for EMU_VMONPAVDDRISE */
+#define _EMU_IEN_VMONPAVDDRISE_MASK                  0x2000UL                                      /**< Bit mask for EMU_VMONPAVDDRISE */
+#define _EMU_IEN_VMONPAVDDRISE_DEFAULT               0x00000000UL                                  /**< Mode DEFAULT for EMU_IEN */
+#define EMU_IEN_VMONPAVDDRISE_DEFAULT                (_EMU_IEN_VMONPAVDDRISE_DEFAULT << 13)        /**< Shifted mode DEFAULT for EMU_IEN */
+#define EMU_IEN_VMONFVDDFALL                         (0x1UL << 14)                                 /**< VMONFVDDFALL Interrupt Enable */
+#define _EMU_IEN_VMONFVDDFALL_SHIFT                  14                                            /**< Shift value for EMU_VMONFVDDFALL */
+#define _EMU_IEN_VMONFVDDFALL_MASK                   0x4000UL                                      /**< Bit mask for EMU_VMONFVDDFALL */
+#define _EMU_IEN_VMONFVDDFALL_DEFAULT                0x00000000UL                                  /**< Mode DEFAULT for EMU_IEN */
+#define EMU_IEN_VMONFVDDFALL_DEFAULT                 (_EMU_IEN_VMONFVDDFALL_DEFAULT << 14)         /**< Shifted mode DEFAULT for EMU_IEN */
+#define EMU_IEN_VMONFVDDRISE                         (0x1UL << 15)                                 /**< VMONFVDDRISE Interrupt Enable */
+#define _EMU_IEN_VMONFVDDRISE_SHIFT                  15                                            /**< Shift value for EMU_VMONFVDDRISE */
+#define _EMU_IEN_VMONFVDDRISE_MASK                   0x8000UL                                      /**< Bit mask for EMU_VMONFVDDRISE */
+#define _EMU_IEN_VMONFVDDRISE_DEFAULT                0x00000000UL                                  /**< Mode DEFAULT for EMU_IEN */
+#define EMU_IEN_VMONFVDDRISE_DEFAULT                 (_EMU_IEN_VMONFVDDRISE_DEFAULT << 15)         /**< Shifted mode DEFAULT for EMU_IEN */
+#define EMU_IEN_PFETOVERCURRENTLIMIT                 (0x1UL << 16)                                 /**< PFETOVERCURRENTLIMIT Interrupt Enable */
+#define _EMU_IEN_PFETOVERCURRENTLIMIT_SHIFT          16                                            /**< Shift value for EMU_PFETOVERCURRENTLIMIT */
+#define _EMU_IEN_PFETOVERCURRENTLIMIT_MASK           0x10000UL                                     /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */
+#define _EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT        0x00000000UL                                  /**< Mode DEFAULT for EMU_IEN */
+#define EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT         (_EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IEN */
+#define EMU_IEN_NFETOVERCURRENTLIMIT                 (0x1UL << 17)                                 /**< NFETOVERCURRENTLIMIT Interrupt Enable */
+#define _EMU_IEN_NFETOVERCURRENTLIMIT_SHIFT          17                                            /**< Shift value for EMU_NFETOVERCURRENTLIMIT */
+#define _EMU_IEN_NFETOVERCURRENTLIMIT_MASK           0x20000UL                                     /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */
+#define _EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT        0x00000000UL                                  /**< Mode DEFAULT for EMU_IEN */
+#define EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT         (_EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IEN */
+#define EMU_IEN_DCDCLPRUNNING                        (0x1UL << 18)                                 /**< DCDCLPRUNNING Interrupt Enable */
+#define _EMU_IEN_DCDCLPRUNNING_SHIFT                 18                                            /**< Shift value for EMU_DCDCLPRUNNING */
+#define _EMU_IEN_DCDCLPRUNNING_MASK                  0x40000UL                                     /**< Bit mask for EMU_DCDCLPRUNNING */
+#define _EMU_IEN_DCDCLPRUNNING_DEFAULT               0x00000000UL                                  /**< Mode DEFAULT for EMU_IEN */
+#define EMU_IEN_DCDCLPRUNNING_DEFAULT                (_EMU_IEN_DCDCLPRUNNING_DEFAULT << 18)        /**< Shifted mode DEFAULT for EMU_IEN */
+#define EMU_IEN_DCDCLNRUNNING                        (0x1UL << 19)                                 /**< DCDCLNRUNNING Interrupt Enable */
+#define _EMU_IEN_DCDCLNRUNNING_SHIFT                 19                                            /**< Shift value for EMU_DCDCLNRUNNING */
+#define _EMU_IEN_DCDCLNRUNNING_MASK                  0x80000UL                                     /**< Bit mask for EMU_DCDCLNRUNNING */
+#define _EMU_IEN_DCDCLNRUNNING_DEFAULT               0x00000000UL                                  /**< Mode DEFAULT for EMU_IEN */
+#define EMU_IEN_DCDCLNRUNNING_DEFAULT                (_EMU_IEN_DCDCLNRUNNING_DEFAULT << 19)        /**< Shifted mode DEFAULT for EMU_IEN */
+#define EMU_IEN_DCDCINBYPASS                         (0x1UL << 20)                                 /**< DCDCINBYPASS Interrupt Enable */
+#define _EMU_IEN_DCDCINBYPASS_SHIFT                  20                                            /**< Shift value for EMU_DCDCINBYPASS */
+#define _EMU_IEN_DCDCINBYPASS_MASK                   0x100000UL                                    /**< Bit mask for EMU_DCDCINBYPASS */
+#define _EMU_IEN_DCDCINBYPASS_DEFAULT                0x00000000UL                                  /**< Mode DEFAULT for EMU_IEN */
+#define EMU_IEN_DCDCINBYPASS_DEFAULT                 (_EMU_IEN_DCDCINBYPASS_DEFAULT << 20)         /**< Shifted mode DEFAULT for EMU_IEN */
+#define EMU_IEN_EM23WAKEUP                           (0x1UL << 24)                                 /**< EM23WAKEUP Interrupt Enable */
+#define _EMU_IEN_EM23WAKEUP_SHIFT                    24                                            /**< Shift value for EMU_EM23WAKEUP */
+#define _EMU_IEN_EM23WAKEUP_MASK                     0x1000000UL                                   /**< Bit mask for EMU_EM23WAKEUP */
+#define _EMU_IEN_EM23WAKEUP_DEFAULT                  0x00000000UL                                  /**< Mode DEFAULT for EMU_IEN */
+#define EMU_IEN_EM23WAKEUP_DEFAULT                   (_EMU_IEN_EM23WAKEUP_DEFAULT << 24)           /**< Shifted mode DEFAULT for EMU_IEN */
+#define EMU_IEN_TEMP                                 (0x1UL << 29)                                 /**< TEMP Interrupt Enable */
+#define _EMU_IEN_TEMP_SHIFT                          29                                            /**< Shift value for EMU_TEMP */
+#define _EMU_IEN_TEMP_MASK                           0x20000000UL                                  /**< Bit mask for EMU_TEMP */
+#define _EMU_IEN_TEMP_DEFAULT                        0x00000000UL                                  /**< Mode DEFAULT for EMU_IEN */
+#define EMU_IEN_TEMP_DEFAULT                         (_EMU_IEN_TEMP_DEFAULT << 29)                 /**< Shifted mode DEFAULT for EMU_IEN */
+#define EMU_IEN_TEMPLOW                              (0x1UL << 30)                                 /**< TEMPLOW Interrupt Enable */
+#define _EMU_IEN_TEMPLOW_SHIFT                       30                                            /**< Shift value for EMU_TEMPLOW */
+#define _EMU_IEN_TEMPLOW_MASK                        0x40000000UL                                  /**< Bit mask for EMU_TEMPLOW */
+#define _EMU_IEN_TEMPLOW_DEFAULT                     0x00000000UL                                  /**< Mode DEFAULT for EMU_IEN */
+#define EMU_IEN_TEMPLOW_DEFAULT                      (_EMU_IEN_TEMPLOW_DEFAULT << 30)              /**< Shifted mode DEFAULT for EMU_IEN */
+#define EMU_IEN_TEMPHIGH                             (0x1UL << 31)                                 /**< TEMPHIGH Interrupt Enable */
+#define _EMU_IEN_TEMPHIGH_SHIFT                      31                                            /**< Shift value for EMU_TEMPHIGH */
+#define _EMU_IEN_TEMPHIGH_MASK                       0x80000000UL                                  /**< Bit mask for EMU_TEMPHIGH */
+#define _EMU_IEN_TEMPHIGH_DEFAULT                    0x00000000UL                                  /**< Mode DEFAULT for EMU_IEN */
+#define EMU_IEN_TEMPHIGH_DEFAULT                     (_EMU_IEN_TEMPHIGH_DEFAULT << 31)             /**< Shifted mode DEFAULT for EMU_IEN */
+
+/* Bit fields for EMU PWRLOCK */
+#define _EMU_PWRLOCK_RESETVALUE                      0x00000000UL                         /**< Default value for EMU_PWRLOCK */
+#define _EMU_PWRLOCK_MASK                            0x0000FFFFUL                         /**< Mask for EMU_PWRLOCK */
+#define _EMU_PWRLOCK_LOCKKEY_SHIFT                   0                                    /**< Shift value for EMU_LOCKKEY */
+#define _EMU_PWRLOCK_LOCKKEY_MASK                    0xFFFFUL                             /**< Bit mask for EMU_LOCKKEY */
+#define _EMU_PWRLOCK_LOCKKEY_DEFAULT                 0x00000000UL                         /**< Mode DEFAULT for EMU_PWRLOCK */
+#define _EMU_PWRLOCK_LOCKKEY_LOCK                    0x00000000UL                         /**< Mode LOCK for EMU_PWRLOCK */
+#define _EMU_PWRLOCK_LOCKKEY_UNLOCKED                0x00000000UL                         /**< Mode UNLOCKED for EMU_PWRLOCK */
+#define _EMU_PWRLOCK_LOCKKEY_LOCKED                  0x00000001UL                         /**< Mode LOCKED for EMU_PWRLOCK */
+#define _EMU_PWRLOCK_LOCKKEY_UNLOCK                  0x0000ADE8UL                         /**< Mode UNLOCK for EMU_PWRLOCK */
+#define EMU_PWRLOCK_LOCKKEY_DEFAULT                  (_EMU_PWRLOCK_LOCKKEY_DEFAULT << 0)  /**< Shifted mode DEFAULT for EMU_PWRLOCK */
+#define EMU_PWRLOCK_LOCKKEY_LOCK                     (_EMU_PWRLOCK_LOCKKEY_LOCK << 0)     /**< Shifted mode LOCK for EMU_PWRLOCK */
+#define EMU_PWRLOCK_LOCKKEY_UNLOCKED                 (_EMU_PWRLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_PWRLOCK */
+#define EMU_PWRLOCK_LOCKKEY_LOCKED                   (_EMU_PWRLOCK_LOCKKEY_LOCKED << 0)   /**< Shifted mode LOCKED for EMU_PWRLOCK */
+#define EMU_PWRLOCK_LOCKKEY_UNLOCK                   (_EMU_PWRLOCK_LOCKKEY_UNLOCK << 0)   /**< Shifted mode UNLOCK for EMU_PWRLOCK */
+
+/* Bit fields for EMU PWRCFG */
+#define _EMU_PWRCFG_RESETVALUE                       0x00000000UL                         /**< Default value for EMU_PWRCFG */
+#define _EMU_PWRCFG_MASK                             0x0000000FUL                         /**< Mask for EMU_PWRCFG */
+#define _EMU_PWRCFG_PWRCFG_SHIFT                     0                                    /**< Shift value for EMU_PWRCFG */
+#define _EMU_PWRCFG_PWRCFG_MASK                      0xFUL                                /**< Bit mask for EMU_PWRCFG */
+#define _EMU_PWRCFG_PWRCFG_DEFAULT                   0x00000000UL                         /**< Mode DEFAULT for EMU_PWRCFG */
+#define _EMU_PWRCFG_PWRCFG_STARTUP                   0x00000000UL                         /**< Mode STARTUP for EMU_PWRCFG */
+#define _EMU_PWRCFG_PWRCFG_NODCDC                    0x00000001UL                         /**< Mode NODCDC for EMU_PWRCFG */
+#define _EMU_PWRCFG_PWRCFG_DCDCTODVDD                0x00000002UL                         /**< Mode DCDCTODVDD for EMU_PWRCFG */
+#define EMU_PWRCFG_PWRCFG_DEFAULT                    (_EMU_PWRCFG_PWRCFG_DEFAULT << 0)    /**< Shifted mode DEFAULT for EMU_PWRCFG */
+#define EMU_PWRCFG_PWRCFG_STARTUP                    (_EMU_PWRCFG_PWRCFG_STARTUP << 0)    /**< Shifted mode STARTUP for EMU_PWRCFG */
+#define EMU_PWRCFG_PWRCFG_NODCDC                     (_EMU_PWRCFG_PWRCFG_NODCDC << 0)     /**< Shifted mode NODCDC for EMU_PWRCFG */
+#define EMU_PWRCFG_PWRCFG_DCDCTODVDD                 (_EMU_PWRCFG_PWRCFG_DCDCTODVDD << 0) /**< Shifted mode DCDCTODVDD for EMU_PWRCFG */
+
+/* Bit fields for EMU PWRCTRL */
+#define _EMU_PWRCTRL_RESETVALUE                      0x00000000UL                      /**< Default value for EMU_PWRCTRL */
+#define _EMU_PWRCTRL_MASK                            0x00000020UL                      /**< Mask for EMU_PWRCTRL */
+#define EMU_PWRCTRL_ANASW                            (0x1UL << 5)                      /**< Analog Switch Selection */
+#define _EMU_PWRCTRL_ANASW_SHIFT                     5                                 /**< Shift value for EMU_ANASW */
+#define _EMU_PWRCTRL_ANASW_MASK                      0x20UL                            /**< Bit mask for EMU_ANASW */
+#define _EMU_PWRCTRL_ANASW_DEFAULT                   0x00000000UL                      /**< Mode DEFAULT for EMU_PWRCTRL */
+#define _EMU_PWRCTRL_ANASW_AVDD                      0x00000000UL                      /**< Mode AVDD for EMU_PWRCTRL */
+#define _EMU_PWRCTRL_ANASW_DVDD                      0x00000001UL                      /**< Mode DVDD for EMU_PWRCTRL */
+#define EMU_PWRCTRL_ANASW_DEFAULT                    (_EMU_PWRCTRL_ANASW_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_PWRCTRL */
+#define EMU_PWRCTRL_ANASW_AVDD                       (_EMU_PWRCTRL_ANASW_AVDD << 5)    /**< Shifted mode AVDD for EMU_PWRCTRL */
+#define EMU_PWRCTRL_ANASW_DVDD                       (_EMU_PWRCTRL_ANASW_DVDD << 5)    /**< Shifted mode DVDD for EMU_PWRCTRL */
+
+/* Bit fields for EMU DCDCCTRL */
+#define _EMU_DCDCCTRL_RESETVALUE                     0x00000030UL                              /**< Default value for EMU_DCDCCTRL */
+#define _EMU_DCDCCTRL_MASK                           0x00000033UL                              /**< Mask for EMU_DCDCCTRL */
+#define _EMU_DCDCCTRL_DCDCMODE_SHIFT                 0                                         /**< Shift value for EMU_DCDCMODE */
+#define _EMU_DCDCCTRL_DCDCMODE_MASK                  0x3UL                                     /**< Bit mask for EMU_DCDCMODE */
+#define _EMU_DCDCCTRL_DCDCMODE_DEFAULT               0x00000000UL                              /**< Mode DEFAULT for EMU_DCDCCTRL */
+#define _EMU_DCDCCTRL_DCDCMODE_BYPASS                0x00000000UL                              /**< Mode BYPASS for EMU_DCDCCTRL */
+#define _EMU_DCDCCTRL_DCDCMODE_LOWNOISE              0x00000001UL                              /**< Mode LOWNOISE for EMU_DCDCCTRL */
+#define _EMU_DCDCCTRL_DCDCMODE_LOWPOWER              0x00000002UL                              /**< Mode LOWPOWER for EMU_DCDCCTRL */
+#define _EMU_DCDCCTRL_DCDCMODE_OFF                   0x00000003UL                              /**< Mode OFF for EMU_DCDCCTRL */
+#define EMU_DCDCCTRL_DCDCMODE_DEFAULT                (_EMU_DCDCCTRL_DCDCMODE_DEFAULT << 0)     /**< Shifted mode DEFAULT for EMU_DCDCCTRL */
+#define EMU_DCDCCTRL_DCDCMODE_BYPASS                 (_EMU_DCDCCTRL_DCDCMODE_BYPASS << 0)      /**< Shifted mode BYPASS for EMU_DCDCCTRL */
+#define EMU_DCDCCTRL_DCDCMODE_LOWNOISE               (_EMU_DCDCCTRL_DCDCMODE_LOWNOISE << 0)    /**< Shifted mode LOWNOISE for EMU_DCDCCTRL */
+#define EMU_DCDCCTRL_DCDCMODE_LOWPOWER               (_EMU_DCDCCTRL_DCDCMODE_LOWPOWER << 0)    /**< Shifted mode LOWPOWER for EMU_DCDCCTRL */
+#define EMU_DCDCCTRL_DCDCMODE_OFF                    (_EMU_DCDCCTRL_DCDCMODE_OFF << 0)         /**< Shifted mode OFF for EMU_DCDCCTRL */
+#define EMU_DCDCCTRL_DCDCMODEEM23                    (0x1UL << 4)                              /**< Reserved for internal use. Do not change. */
+#define _EMU_DCDCCTRL_DCDCMODEEM23_SHIFT             4                                         /**< Shift value for EMU_DCDCMODEEM23 */
+#define _EMU_DCDCCTRL_DCDCMODEEM23_MASK              0x10UL                                    /**< Bit mask for EMU_DCDCMODEEM23 */
+#define _EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT           0x00000001UL                              /**< Mode DEFAULT for EMU_DCDCCTRL */
+#define EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT            (_EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */
+#define EMU_DCDCCTRL_DCDCMODEEM4                     (0x1UL << 5)                              /**< Reserved for internal use. Do not change. */
+#define _EMU_DCDCCTRL_DCDCMODEEM4_SHIFT              5                                         /**< Shift value for EMU_DCDCMODEEM4 */
+#define _EMU_DCDCCTRL_DCDCMODEEM4_MASK               0x20UL                                    /**< Bit mask for EMU_DCDCMODEEM4 */
+#define _EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT            0x00000001UL                              /**< Mode DEFAULT for EMU_DCDCCTRL */
+#define EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT             (_EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT << 5)  /**< Shifted mode DEFAULT for EMU_DCDCCTRL */
+
+/* Bit fields for EMU DCDCMISCCTRL */
+#define _EMU_DCDCMISCCTRL_RESETVALUE                 0x33307700UL                                    /**< Default value for EMU_DCDCMISCCTRL */
+#define _EMU_DCDCMISCCTRL_MASK                       0x377FFF01UL                                    /**< Mask for EMU_DCDCMISCCTRL */
+#define EMU_DCDCMISCCTRL_LNFORCECCM                  (0x1UL << 0)                                    /**< Force DCDC into CCM mode in low noise operation */
+#define _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT           0                                               /**< Shift value for EMU_LNFORCECCM */
+#define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK            0x1UL                                           /**< Bit mask for EMU_LNFORCECCM */
+#define _EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT         0x00000000UL                                    /**< Mode DEFAULT for EMU_DCDCMISCCTRL */
+#define EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT          (_EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT << 0)     /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */
+#define _EMU_DCDCMISCCTRL_PFETCNT_SHIFT              8                                               /**< Shift value for EMU_PFETCNT */
+#define _EMU_DCDCMISCCTRL_PFETCNT_MASK               0xF00UL                                         /**< Bit mask for EMU_PFETCNT */
+#define _EMU_DCDCMISCCTRL_PFETCNT_DEFAULT            0x00000007UL                                    /**< Mode DEFAULT for EMU_DCDCMISCCTRL */
+#define EMU_DCDCMISCCTRL_PFETCNT_DEFAULT             (_EMU_DCDCMISCCTRL_PFETCNT_DEFAULT << 8)        /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */
+#define _EMU_DCDCMISCCTRL_NFETCNT_SHIFT              12                                              /**< Shift value for EMU_NFETCNT */
+#define _EMU_DCDCMISCCTRL_NFETCNT_MASK               0xF000UL                                        /**< Bit mask for EMU_NFETCNT */
+#define _EMU_DCDCMISCCTRL_NFETCNT_DEFAULT            0x00000007UL                                    /**< Mode DEFAULT for EMU_DCDCMISCCTRL */
+#define EMU_DCDCMISCCTRL_NFETCNT_DEFAULT             (_EMU_DCDCMISCCTRL_NFETCNT_DEFAULT << 12)       /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */
+#define _EMU_DCDCMISCCTRL_BYPLIMSEL_SHIFT            16                                              /**< Shift value for EMU_BYPLIMSEL */
+#define _EMU_DCDCMISCCTRL_BYPLIMSEL_MASK             0xF0000UL                                       /**< Bit mask for EMU_BYPLIMSEL */
+#define _EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT          0x00000000UL                                    /**< Mode DEFAULT for EMU_DCDCMISCCTRL */
+#define EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT           (_EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT << 16)     /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */
+#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_SHIFT        20                                              /**< Shift value for EMU_LPCLIMILIMSEL */
+#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK         0x700000UL                                      /**< Bit mask for EMU_LPCLIMILIMSEL */
+#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT      0x00000003UL                                    /**< Mode DEFAULT for EMU_DCDCMISCCTRL */
+#define EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT       (_EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */
+#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT        24                                              /**< Shift value for EMU_LNCLIMILIMSEL */
+#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK         0x7000000UL                                     /**< Bit mask for EMU_LNCLIMILIMSEL */
+#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT      0x00000003UL                                    /**< Mode DEFAULT for EMU_DCDCMISCCTRL */
+#define EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT       (_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */
+#define _EMU_DCDCMISCCTRL_LPCMPBIAS_SHIFT            28                                              /**< Shift value for EMU_LPCMPBIAS */
+#define _EMU_DCDCMISCCTRL_LPCMPBIAS_MASK             0x30000000UL                                    /**< Bit mask for EMU_LPCMPBIAS */
+#define _EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS0            0x00000000UL                                    /**< Mode BIAS0 for EMU_DCDCMISCCTRL */
+#define _EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS1            0x00000001UL                                    /**< Mode BIAS1 for EMU_DCDCMISCCTRL */
+#define _EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS2            0x00000002UL                                    /**< Mode BIAS2 for EMU_DCDCMISCCTRL */
+#define _EMU_DCDCMISCCTRL_LPCMPBIAS_DEFAULT          0x00000003UL                                    /**< Mode DEFAULT for EMU_DCDCMISCCTRL */
+#define _EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS3            0x00000003UL                                    /**< Mode BIAS3 for EMU_DCDCMISCCTRL */
+#define EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS0             (_EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS0 << 28)       /**< Shifted mode BIAS0 for EMU_DCDCMISCCTRL */
+#define EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS1             (_EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS1 << 28)       /**< Shifted mode BIAS1 for EMU_DCDCMISCCTRL */
+#define EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS2             (_EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS2 << 28)       /**< Shifted mode BIAS2 for EMU_DCDCMISCCTRL */
+#define EMU_DCDCMISCCTRL_LPCMPBIAS_DEFAULT           (_EMU_DCDCMISCCTRL_LPCMPBIAS_DEFAULT << 28)     /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */
+#define EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS3             (_EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS3 << 28)       /**< Shifted mode BIAS3 for EMU_DCDCMISCCTRL */
+
+/* Bit fields for EMU DCDCZDETCTRL */
+#define _EMU_DCDCZDETCTRL_RESETVALUE                 0x00000130UL                                  /**< Default value for EMU_DCDCZDETCTRL */
+#define _EMU_DCDCZDETCTRL_MASK                       0x00000370UL                                  /**< Mask for EMU_DCDCZDETCTRL */
+#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_SHIFT          4                                             /**< Shift value for EMU_ZDETILIMSEL */
+#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK           0x70UL                                        /**< Bit mask for EMU_ZDETILIMSEL */
+#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT        0x00000003UL                                  /**< Mode DEFAULT for EMU_DCDCZDETCTRL */
+#define EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT         (_EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT << 4)  /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */
+#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_SHIFT         8                                             /**< Shift value for EMU_ZDETBLANKDLY */
+#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_MASK          0x300UL                                       /**< Bit mask for EMU_ZDETBLANKDLY */
+#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT       0x00000001UL                                  /**< Mode DEFAULT for EMU_DCDCZDETCTRL */
+#define EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT        (_EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */
+
+/* Bit fields for EMU DCDCCLIMCTRL */
+#define _EMU_DCDCCLIMCTRL_RESETVALUE                 0x00002100UL                                  /**< Default value for EMU_DCDCCLIMCTRL */
+#define _EMU_DCDCCLIMCTRL_MASK                       0x00002300UL                                  /**< Mask for EMU_DCDCCLIMCTRL */
+#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_SHIFT         8                                             /**< Shift value for EMU_CLIMBLANKDLY */
+#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_MASK          0x300UL                                       /**< Bit mask for EMU_CLIMBLANKDLY */
+#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT       0x00000001UL                                  /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */
+#define EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT        (_EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */
+#define EMU_DCDCCLIMCTRL_BYPLIMEN                    (0x1UL << 13)                                 /**< Bypass Current Limit Enable */
+#define _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT             13                                            /**< Shift value for EMU_BYPLIMEN */
+#define _EMU_DCDCCLIMCTRL_BYPLIMEN_MASK              0x2000UL                                      /**< Bit mask for EMU_BYPLIMEN */
+#define _EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT           0x00000001UL                                  /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */
+#define EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT            (_EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT << 13)    /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */
+
+/* Bit fields for EMU DCDCLNVCTRL */
+#define _EMU_DCDCLNVCTRL_RESETVALUE                  0x00007100UL                           /**< Default value for EMU_DCDCLNVCTRL */
+#define _EMU_DCDCLNVCTRL_MASK                        0x00007F02UL                           /**< Mask for EMU_DCDCLNVCTRL */
+#define EMU_DCDCLNVCTRL_LNATT                        (0x1UL << 1)                           /**< Low Noise Mode Feedback Attenuation */
+#define _EMU_DCDCLNVCTRL_LNATT_SHIFT                 1                                      /**< Shift value for EMU_LNATT */
+#define _EMU_DCDCLNVCTRL_LNATT_MASK                  0x2UL                                  /**< Bit mask for EMU_LNATT */
+#define _EMU_DCDCLNVCTRL_LNATT_DEFAULT               0x00000000UL                           /**< Mode DEFAULT for EMU_DCDCLNVCTRL */
+#define _EMU_DCDCLNVCTRL_LNATT_DIV3                  0x00000000UL                           /**< Mode DIV3 for EMU_DCDCLNVCTRL */
+#define _EMU_DCDCLNVCTRL_LNATT_DIV6                  0x00000001UL                           /**< Mode DIV6 for EMU_DCDCLNVCTRL */
+#define EMU_DCDCLNVCTRL_LNATT_DEFAULT                (_EMU_DCDCLNVCTRL_LNATT_DEFAULT << 1)  /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */
+#define EMU_DCDCLNVCTRL_LNATT_DIV3                   (_EMU_DCDCLNVCTRL_LNATT_DIV3 << 1)     /**< Shifted mode DIV3 for EMU_DCDCLNVCTRL */
+#define EMU_DCDCLNVCTRL_LNATT_DIV6                   (_EMU_DCDCLNVCTRL_LNATT_DIV6 << 1)     /**< Shifted mode DIV6 for EMU_DCDCLNVCTRL */
+#define _EMU_DCDCLNVCTRL_LNVREF_SHIFT                8                                      /**< Shift value for EMU_LNVREF */
+#define _EMU_DCDCLNVCTRL_LNVREF_MASK                 0x7F00UL                               /**< Bit mask for EMU_LNVREF */
+#define _EMU_DCDCLNVCTRL_LNVREF_DEFAULT              0x00000071UL                           /**< Mode DEFAULT for EMU_DCDCLNVCTRL */
+#define EMU_DCDCLNVCTRL_LNVREF_DEFAULT               (_EMU_DCDCLNVCTRL_LNVREF_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */
+
+/* Bit fields for EMU DCDCTIMING */
+#define _EMU_DCDCTIMING_RESETVALUE                   0x0FF1F8FFUL                                  /**< Default value for EMU_DCDCTIMING */
+#define _EMU_DCDCTIMING_MASK                         0x6FF1F8FFUL                                  /**< Mask for EMU_DCDCTIMING */
+#define _EMU_DCDCTIMING_LPINITWAIT_SHIFT             0                                             /**< Shift value for EMU_LPINITWAIT */
+#define _EMU_DCDCTIMING_LPINITWAIT_MASK              0xFFUL                                        /**< Bit mask for EMU_LPINITWAIT */
+#define _EMU_DCDCTIMING_LPINITWAIT_DEFAULT           0x000000FFUL                                  /**< Mode DEFAULT for EMU_DCDCTIMING */
+#define EMU_DCDCTIMING_LPINITWAIT_DEFAULT            (_EMU_DCDCTIMING_LPINITWAIT_DEFAULT << 0)     /**< Shifted mode DEFAULT for EMU_DCDCTIMING */
+#define EMU_DCDCTIMING_COMPENPRCHGEN                 (0x1UL << 11)                                 /**< LN mode precharge enable */
+#define _EMU_DCDCTIMING_COMPENPRCHGEN_SHIFT          11                                            /**< Shift value for EMU_COMPENPRCHGEN */
+#define _EMU_DCDCTIMING_COMPENPRCHGEN_MASK           0x800UL                                       /**< Bit mask for EMU_COMPENPRCHGEN */
+#define _EMU_DCDCTIMING_COMPENPRCHGEN_DEFAULT        0x00000001UL                                  /**< Mode DEFAULT for EMU_DCDCTIMING */
+#define EMU_DCDCTIMING_COMPENPRCHGEN_DEFAULT         (_EMU_DCDCTIMING_COMPENPRCHGEN_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_DCDCTIMING */
+#define _EMU_DCDCTIMING_LNWAIT_SHIFT                 12                                            /**< Shift value for EMU_LNWAIT */
+#define _EMU_DCDCTIMING_LNWAIT_MASK                  0x1F000UL                                     /**< Bit mask for EMU_LNWAIT */
+#define _EMU_DCDCTIMING_LNWAIT_DEFAULT               0x0000001FUL                                  /**< Mode DEFAULT for EMU_DCDCTIMING */
+#define EMU_DCDCTIMING_LNWAIT_DEFAULT                (_EMU_DCDCTIMING_LNWAIT_DEFAULT << 12)        /**< Shifted mode DEFAULT for EMU_DCDCTIMING */
+#define _EMU_DCDCTIMING_BYPWAIT_SHIFT                20                                            /**< Shift value for EMU_BYPWAIT */
+#define _EMU_DCDCTIMING_BYPWAIT_MASK                 0xFF00000UL                                   /**< Bit mask for EMU_BYPWAIT */
+#define _EMU_DCDCTIMING_BYPWAIT_DEFAULT              0x000000FFUL                                  /**< Mode DEFAULT for EMU_DCDCTIMING */
+#define EMU_DCDCTIMING_BYPWAIT_DEFAULT               (_EMU_DCDCTIMING_BYPWAIT_DEFAULT << 20)       /**< Shifted mode DEFAULT for EMU_DCDCTIMING */
+#define _EMU_DCDCTIMING_DUTYSCALE_SHIFT              29                                            /**< Shift value for EMU_DUTYSCALE */
+#define _EMU_DCDCTIMING_DUTYSCALE_MASK               0x60000000UL                                  /**< Bit mask for EMU_DUTYSCALE */
+#define _EMU_DCDCTIMING_DUTYSCALE_DEFAULT            0x00000000UL                                  /**< Mode DEFAULT for EMU_DCDCTIMING */
+#define EMU_DCDCTIMING_DUTYSCALE_DEFAULT             (_EMU_DCDCTIMING_DUTYSCALE_DEFAULT << 29)     /**< Shifted mode DEFAULT for EMU_DCDCTIMING */
+
+/* Bit fields for EMU DCDCLPVCTRL */
+#define _EMU_DCDCLPVCTRL_RESETVALUE                  0x00000168UL                           /**< Default value for EMU_DCDCLPVCTRL */
+#define _EMU_DCDCLPVCTRL_MASK                        0x000001FFUL                           /**< Mask for EMU_DCDCLPVCTRL */
+#define EMU_DCDCLPVCTRL_LPATT                        (0x1UL << 0)                           /**< Low power feedback attenuation */
+#define _EMU_DCDCLPVCTRL_LPATT_SHIFT                 0                                      /**< Shift value for EMU_LPATT */
+#define _EMU_DCDCLPVCTRL_LPATT_MASK                  0x1UL                                  /**< Bit mask for EMU_LPATT */
+#define _EMU_DCDCLPVCTRL_LPATT_DEFAULT               0x00000000UL                           /**< Mode DEFAULT for EMU_DCDCLPVCTRL */
+#define _EMU_DCDCLPVCTRL_LPATT_DIV4                  0x00000000UL                           /**< Mode DIV4 for EMU_DCDCLPVCTRL */
+#define _EMU_DCDCLPVCTRL_LPATT_DIV8                  0x00000001UL                           /**< Mode DIV8 for EMU_DCDCLPVCTRL */
+#define EMU_DCDCLPVCTRL_LPATT_DEFAULT                (_EMU_DCDCLPVCTRL_LPATT_DEFAULT << 0)  /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */
+#define EMU_DCDCLPVCTRL_LPATT_DIV4                   (_EMU_DCDCLPVCTRL_LPATT_DIV4 << 0)     /**< Shifted mode DIV4 for EMU_DCDCLPVCTRL */
+#define EMU_DCDCLPVCTRL_LPATT_DIV8                   (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0)     /**< Shifted mode DIV8 for EMU_DCDCLPVCTRL */
+#define _EMU_DCDCLPVCTRL_LPVREF_SHIFT                1                                      /**< Shift value for EMU_LPVREF */
+#define _EMU_DCDCLPVCTRL_LPVREF_MASK                 0x1FEUL                                /**< Bit mask for EMU_LPVREF */
+#define _EMU_DCDCLPVCTRL_LPVREF_DEFAULT              0x000000B4UL                           /**< Mode DEFAULT for EMU_DCDCLPVCTRL */
+#define EMU_DCDCLPVCTRL_LPVREF_DEFAULT               (_EMU_DCDCLPVCTRL_LPVREF_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */
+
+/* Bit fields for EMU DCDCLPCTRL */
+#define _EMU_DCDCLPCTRL_RESETVALUE                   0x00007000UL                                 /**< Default value for EMU_DCDCLPCTRL */
+#define _EMU_DCDCLPCTRL_MASK                         0x0700F000UL                                 /**< Mask for EMU_DCDCLPCTRL */
+#define _EMU_DCDCLPCTRL_LPCMPHYSSEL_SHIFT            12                                           /**< Shift value for EMU_LPCMPHYSSEL */
+#define _EMU_DCDCLPCTRL_LPCMPHYSSEL_MASK             0xF000UL                                     /**< Bit mask for EMU_LPCMPHYSSEL */
+#define _EMU_DCDCLPCTRL_LPCMPHYSSEL_DEFAULT          0x00000007UL                                 /**< Mode DEFAULT for EMU_DCDCLPCTRL */
+#define EMU_DCDCLPCTRL_LPCMPHYSSEL_DEFAULT           (_EMU_DCDCLPCTRL_LPCMPHYSSEL_DEFAULT << 12)  /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */
+#define EMU_DCDCLPCTRL_LPVREFDUTYEN                  (0x1UL << 24)                                /**< Lp mode duty cycling enable */
+#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_SHIFT           24                                           /**< Shift value for EMU_LPVREFDUTYEN */
+#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_MASK            0x1000000UL                                  /**< Bit mask for EMU_LPVREFDUTYEN */
+#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT         0x00000000UL                                 /**< Mode DEFAULT for EMU_DCDCLPCTRL */
+#define EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT          (_EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */
+#define _EMU_DCDCLPCTRL_LPBLANK_SHIFT                25                                           /**< Shift value for EMU_LPBLANK */
+#define _EMU_DCDCLPCTRL_LPBLANK_MASK                 0x6000000UL                                  /**< Bit mask for EMU_LPBLANK */
+#define _EMU_DCDCLPCTRL_LPBLANK_DEFAULT              0x00000000UL                                 /**< Mode DEFAULT for EMU_DCDCLPCTRL */
+#define EMU_DCDCLPCTRL_LPBLANK_DEFAULT               (_EMU_DCDCLPCTRL_LPBLANK_DEFAULT << 25)      /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */
+
+/* Bit fields for EMU DCDCLNFREQCTRL */
+#define _EMU_DCDCLNFREQCTRL_RESETVALUE               0x10000000UL                                /**< Default value for EMU_DCDCLNFREQCTRL */
+#define _EMU_DCDCLNFREQCTRL_MASK                     0x1F000007UL                                /**< Mask for EMU_DCDCLNFREQCTRL */
+#define _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT            0                                           /**< Shift value for EMU_RCOBAND */
+#define _EMU_DCDCLNFREQCTRL_RCOBAND_MASK             0x7UL                                       /**< Bit mask for EMU_RCOBAND */
+#define _EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT          0x00000000UL                                /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */
+#define EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT           (_EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT << 0)  /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */
+#define _EMU_DCDCLNFREQCTRL_RCOTRIM_SHIFT            24                                          /**< Shift value for EMU_RCOTRIM */
+#define _EMU_DCDCLNFREQCTRL_RCOTRIM_MASK             0x1F000000UL                                /**< Bit mask for EMU_RCOTRIM */
+#define _EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT          0x00000010UL                                /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */
+#define EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT           (_EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */
+
+/* Bit fields for EMU DCDCSYNC */
+#define _EMU_DCDCSYNC_RESETVALUE                     0x00000000UL                              /**< Default value for EMU_DCDCSYNC */
+#define _EMU_DCDCSYNC_MASK                           0x00000001UL                              /**< Mask for EMU_DCDCSYNC */
+#define EMU_DCDCSYNC_DCDCCTRLBUSY                    (0x1UL << 0)                              /**< DCDC CTRL Register Transfer Busy. */
+#define _EMU_DCDCSYNC_DCDCCTRLBUSY_SHIFT             0                                         /**< Shift value for EMU_DCDCCTRLBUSY */
+#define _EMU_DCDCSYNC_DCDCCTRLBUSY_MASK              0x1UL                                     /**< Bit mask for EMU_DCDCCTRLBUSY */
+#define _EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT           0x00000000UL                              /**< Mode DEFAULT for EMU_DCDCSYNC */
+#define EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT            (_EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCSYNC */
+
+/* Bit fields for EMU VMONAVDDCTRL */
+#define _EMU_VMONAVDDCTRL_RESETVALUE                 0x00000000UL                                      /**< Default value for EMU_VMONAVDDCTRL */
+#define _EMU_VMONAVDDCTRL_MASK                       0x00FFFF0DUL                                      /**< Mask for EMU_VMONAVDDCTRL */
+#define EMU_VMONAVDDCTRL_EN                          (0x1UL << 0)                                      /**< Enable */
+#define _EMU_VMONAVDDCTRL_EN_SHIFT                   0                                                 /**< Shift value for EMU_EN */
+#define _EMU_VMONAVDDCTRL_EN_MASK                    0x1UL                                             /**< Bit mask for EMU_EN */
+#define _EMU_VMONAVDDCTRL_EN_DEFAULT                 0x00000000UL                                      /**< Mode DEFAULT for EMU_VMONAVDDCTRL */
+#define EMU_VMONAVDDCTRL_EN_DEFAULT                  (_EMU_VMONAVDDCTRL_EN_DEFAULT << 0)               /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */
+#define EMU_VMONAVDDCTRL_RISEWU                      (0x1UL << 2)                                      /**< Rise Wakeup */
+#define _EMU_VMONAVDDCTRL_RISEWU_SHIFT               2                                                 /**< Shift value for EMU_RISEWU */
+#define _EMU_VMONAVDDCTRL_RISEWU_MASK                0x4UL                                             /**< Bit mask for EMU_RISEWU */
+#define _EMU_VMONAVDDCTRL_RISEWU_DEFAULT             0x00000000UL                                      /**< Mode DEFAULT for EMU_VMONAVDDCTRL */
+#define EMU_VMONAVDDCTRL_RISEWU_DEFAULT              (_EMU_VMONAVDDCTRL_RISEWU_DEFAULT << 2)           /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */
+#define EMU_VMONAVDDCTRL_FALLWU                      (0x1UL << 3)                                      /**< Fall Wakeup */
+#define _EMU_VMONAVDDCTRL_FALLWU_SHIFT               3                                                 /**< Shift value for EMU_FALLWU */
+#define _EMU_VMONAVDDCTRL_FALLWU_MASK                0x8UL                                             /**< Bit mask for EMU_FALLWU */
+#define _EMU_VMONAVDDCTRL_FALLWU_DEFAULT             0x00000000UL                                      /**< Mode DEFAULT for EMU_VMONAVDDCTRL */
+#define EMU_VMONAVDDCTRL_FALLWU_DEFAULT              (_EMU_VMONAVDDCTRL_FALLWU_DEFAULT << 3)           /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */
+#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT        8                                                 /**< Shift value for EMU_FALLTHRESFINE */
+#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_MASK         0xF00UL                                           /**< Bit mask for EMU_FALLTHRESFINE */
+#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT      0x00000000UL                                      /**< Mode DEFAULT for EMU_VMONAVDDCTRL */
+#define EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT       (_EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT << 8)    /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */
+#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT      12                                                /**< Shift value for EMU_FALLTHRESCOARSE */
+#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_MASK       0xF000UL                                          /**< Bit mask for EMU_FALLTHRESCOARSE */
+#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT    0x00000000UL                                      /**< Mode DEFAULT for EMU_VMONAVDDCTRL */
+#define EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT     (_EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */
+#define _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT        16                                                /**< Shift value for EMU_RISETHRESFINE */
+#define _EMU_VMONAVDDCTRL_RISETHRESFINE_MASK         0xF0000UL                                         /**< Bit mask for EMU_RISETHRESFINE */
+#define _EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT      0x00000000UL                                      /**< Mode DEFAULT for EMU_VMONAVDDCTRL */
+#define EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT       (_EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT << 16)   /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */
+#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT      20                                                /**< Shift value for EMU_RISETHRESCOARSE */
+#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_MASK       0xF00000UL                                        /**< Bit mask for EMU_RISETHRESCOARSE */
+#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT    0x00000000UL                                      /**< Mode DEFAULT for EMU_VMONAVDDCTRL */
+#define EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT     (_EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */
+
+/* Bit fields for EMU VMONALTAVDDCTRL */
+#define _EMU_VMONALTAVDDCTRL_RESETVALUE              0x00000000UL                                     /**< Default value for EMU_VMONALTAVDDCTRL */
+#define _EMU_VMONALTAVDDCTRL_MASK                    0x0000FF0DUL                                     /**< Mask for EMU_VMONALTAVDDCTRL */
+#define EMU_VMONALTAVDDCTRL_EN                       (0x1UL << 0)                                     /**< Enable */
+#define _EMU_VMONALTAVDDCTRL_EN_SHIFT                0                                                /**< Shift value for EMU_EN */
+#define _EMU_VMONALTAVDDCTRL_EN_MASK                 0x1UL                                            /**< Bit mask for EMU_EN */
+#define _EMU_VMONALTAVDDCTRL_EN_DEFAULT              0x00000000UL                                     /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */
+#define EMU_VMONALTAVDDCTRL_EN_DEFAULT               (_EMU_VMONALTAVDDCTRL_EN_DEFAULT << 0)           /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */
+#define EMU_VMONALTAVDDCTRL_RISEWU                   (0x1UL << 2)                                     /**< Rise Wakeup */
+#define _EMU_VMONALTAVDDCTRL_RISEWU_SHIFT            2                                                /**< Shift value for EMU_RISEWU */
+#define _EMU_VMONALTAVDDCTRL_RISEWU_MASK             0x4UL                                            /**< Bit mask for EMU_RISEWU */
+#define _EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT          0x00000000UL                                     /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */
+#define EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT           (_EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT << 2)       /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */
+#define EMU_VMONALTAVDDCTRL_FALLWU                   (0x1UL << 3)                                     /**< Fall Wakeup */
+#define _EMU_VMONALTAVDDCTRL_FALLWU_SHIFT            3                                                /**< Shift value for EMU_FALLWU */
+#define _EMU_VMONALTAVDDCTRL_FALLWU_MASK             0x8UL                                            /**< Bit mask for EMU_FALLWU */
+#define _EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT          0x00000000UL                                     /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */
+#define EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT           (_EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT << 3)       /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */
+#define _EMU_VMONALTAVDDCTRL_THRESFINE_SHIFT         8                                                /**< Shift value for EMU_THRESFINE */
+#define _EMU_VMONALTAVDDCTRL_THRESFINE_MASK          0xF00UL                                          /**< Bit mask for EMU_THRESFINE */
+#define _EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT       0x00000000UL                                     /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */
+#define EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT        (_EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT << 8)    /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */
+#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_SHIFT       12                                               /**< Shift value for EMU_THRESCOARSE */
+#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_MASK        0xF000UL                                         /**< Bit mask for EMU_THRESCOARSE */
+#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT     0x00000000UL                                     /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */
+#define EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT      (_EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */
+
+/* Bit fields for EMU VMONDVDDCTRL */
+#define _EMU_VMONDVDDCTRL_RESETVALUE                 0x00000000UL                                  /**< Default value for EMU_VMONDVDDCTRL */
+#define _EMU_VMONDVDDCTRL_MASK                       0x0000FF0DUL                                  /**< Mask for EMU_VMONDVDDCTRL */
+#define EMU_VMONDVDDCTRL_EN                          (0x1UL << 0)                                  /**< Enable */
+#define _EMU_VMONDVDDCTRL_EN_SHIFT                   0                                             /**< Shift value for EMU_EN */
+#define _EMU_VMONDVDDCTRL_EN_MASK                    0x1UL                                         /**< Bit mask for EMU_EN */
+#define _EMU_VMONDVDDCTRL_EN_DEFAULT                 0x00000000UL                                  /**< Mode DEFAULT for EMU_VMONDVDDCTRL */
+#define EMU_VMONDVDDCTRL_EN_DEFAULT                  (_EMU_VMONDVDDCTRL_EN_DEFAULT << 0)           /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */
+#define EMU_VMONDVDDCTRL_RISEWU                      (0x1UL << 2)                                  /**< Rise Wakeup */
+#define _EMU_VMONDVDDCTRL_RISEWU_SHIFT               2                                             /**< Shift value for EMU_RISEWU */
+#define _EMU_VMONDVDDCTRL_RISEWU_MASK                0x4UL                                         /**< Bit mask for EMU_RISEWU */
+#define _EMU_VMONDVDDCTRL_RISEWU_DEFAULT             0x00000000UL                                  /**< Mode DEFAULT for EMU_VMONDVDDCTRL */
+#define EMU_VMONDVDDCTRL_RISEWU_DEFAULT              (_EMU_VMONDVDDCTRL_RISEWU_DEFAULT << 2)       /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */
+#define EMU_VMONDVDDCTRL_FALLWU                      (0x1UL << 3)                                  /**< Fall Wakeup */
+#define _EMU_VMONDVDDCTRL_FALLWU_SHIFT               3                                             /**< Shift value for EMU_FALLWU */
+#define _EMU_VMONDVDDCTRL_FALLWU_MASK                0x8UL                                         /**< Bit mask for EMU_FALLWU */
+#define _EMU_VMONDVDDCTRL_FALLWU_DEFAULT             0x00000000UL                                  /**< Mode DEFAULT for EMU_VMONDVDDCTRL */
+#define EMU_VMONDVDDCTRL_FALLWU_DEFAULT              (_EMU_VMONDVDDCTRL_FALLWU_DEFAULT << 3)       /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */
+#define _EMU_VMONDVDDCTRL_THRESFINE_SHIFT            8                                             /**< Shift value for EMU_THRESFINE */
+#define _EMU_VMONDVDDCTRL_THRESFINE_MASK             0xF00UL                                       /**< Bit mask for EMU_THRESFINE */
+#define _EMU_VMONDVDDCTRL_THRESFINE_DEFAULT          0x00000000UL                                  /**< Mode DEFAULT for EMU_VMONDVDDCTRL */
+#define EMU_VMONDVDDCTRL_THRESFINE_DEFAULT           (_EMU_VMONDVDDCTRL_THRESFINE_DEFAULT << 8)    /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */
+#define _EMU_VMONDVDDCTRL_THRESCOARSE_SHIFT          12                                            /**< Shift value for EMU_THRESCOARSE */
+#define _EMU_VMONDVDDCTRL_THRESCOARSE_MASK           0xF000UL                                      /**< Bit mask for EMU_THRESCOARSE */
+#define _EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT        0x00000000UL                                  /**< Mode DEFAULT for EMU_VMONDVDDCTRL */
+#define EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT         (_EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */
+
+/* Bit fields for EMU VMONIO0CTRL */
+#define _EMU_VMONIO0CTRL_RESETVALUE                  0x00000000UL                                 /**< Default value for EMU_VMONIO0CTRL */
+#define _EMU_VMONIO0CTRL_MASK                        0x0000FF1DUL                                 /**< Mask for EMU_VMONIO0CTRL */
+#define EMU_VMONIO0CTRL_EN                           (0x1UL << 0)                                 /**< Enable */
+#define _EMU_VMONIO0CTRL_EN_SHIFT                    0                                            /**< Shift value for EMU_EN */
+#define _EMU_VMONIO0CTRL_EN_MASK                     0x1UL                                        /**< Bit mask for EMU_EN */
+#define _EMU_VMONIO0CTRL_EN_DEFAULT                  0x00000000UL                                 /**< Mode DEFAULT for EMU_VMONIO0CTRL */
+#define EMU_VMONIO0CTRL_EN_DEFAULT                   (_EMU_VMONIO0CTRL_EN_DEFAULT << 0)           /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */
+#define EMU_VMONIO0CTRL_RISEWU                       (0x1UL << 2)                                 /**< Rise Wakeup */
+#define _EMU_VMONIO0CTRL_RISEWU_SHIFT                2                                            /**< Shift value for EMU_RISEWU */
+#define _EMU_VMONIO0CTRL_RISEWU_MASK                 0x4UL                                        /**< Bit mask for EMU_RISEWU */
+#define _EMU_VMONIO0CTRL_RISEWU_DEFAULT              0x00000000UL                                 /**< Mode DEFAULT for EMU_VMONIO0CTRL */
+#define EMU_VMONIO0CTRL_RISEWU_DEFAULT               (_EMU_VMONIO0CTRL_RISEWU_DEFAULT << 2)       /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */
+#define EMU_VMONIO0CTRL_FALLWU                       (0x1UL << 3)                                 /**< Fall Wakeup */
+#define _EMU_VMONIO0CTRL_FALLWU_SHIFT                3                                            /**< Shift value for EMU_FALLWU */
+#define _EMU_VMONIO0CTRL_FALLWU_MASK                 0x8UL                                        /**< Bit mask for EMU_FALLWU */
+#define _EMU_VMONIO0CTRL_FALLWU_DEFAULT              0x00000000UL                                 /**< Mode DEFAULT for EMU_VMONIO0CTRL */
+#define EMU_VMONIO0CTRL_FALLWU_DEFAULT               (_EMU_VMONIO0CTRL_FALLWU_DEFAULT << 3)       /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */
+#define EMU_VMONIO0CTRL_RETDIS                       (0x1UL << 4)                                 /**< EM4 IO0 Retention disable */
+#define _EMU_VMONIO0CTRL_RETDIS_SHIFT                4                                            /**< Shift value for EMU_RETDIS */
+#define _EMU_VMONIO0CTRL_RETDIS_MASK                 0x10UL                                       /**< Bit mask for EMU_RETDIS */
+#define _EMU_VMONIO0CTRL_RETDIS_DEFAULT              0x00000000UL                                 /**< Mode DEFAULT for EMU_VMONIO0CTRL */
+#define EMU_VMONIO0CTRL_RETDIS_DEFAULT               (_EMU_VMONIO0CTRL_RETDIS_DEFAULT << 4)       /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */
+#define _EMU_VMONIO0CTRL_THRESFINE_SHIFT             8                                            /**< Shift value for EMU_THRESFINE */
+#define _EMU_VMONIO0CTRL_THRESFINE_MASK              0xF00UL                                      /**< Bit mask for EMU_THRESFINE */
+#define _EMU_VMONIO0CTRL_THRESFINE_DEFAULT           0x00000000UL                                 /**< Mode DEFAULT for EMU_VMONIO0CTRL */
+#define EMU_VMONIO0CTRL_THRESFINE_DEFAULT            (_EMU_VMONIO0CTRL_THRESFINE_DEFAULT << 8)    /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */
+#define _EMU_VMONIO0CTRL_THRESCOARSE_SHIFT           12                                           /**< Shift value for EMU_THRESCOARSE */
+#define _EMU_VMONIO0CTRL_THRESCOARSE_MASK            0xF000UL                                     /**< Bit mask for EMU_THRESCOARSE */
+#define _EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT         0x00000000UL                                 /**< Mode DEFAULT for EMU_VMONIO0CTRL */
+#define EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT          (_EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */
+
+/** @} End of group EFM32PG1B_EMU */
+/** @} End of group Parts */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG_STK3401/efm32pg1b_fpueh.h	Fri Jan 15 07:45:16 2016 +0000
@@ -0,0 +1,192 @@
+/**************************************************************************//**
+ * @file efm32pg1b_fpueh.h
+ * @brief EFM32PG1B_FPUEH register and bit field definitions
+ * @version 4.2.0
+ ******************************************************************************
+ * @section License
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ ******************************************************************************
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software.@n
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.@n
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is
+ * providing the Software "AS IS", with no express or implied warranties of any
+ * kind, including, but not limited to, any implied warranties of
+ * merchantability or fitness for any particular purpose or warranties against
+ * infringement of any proprietary rights of a third party.
+ *
+ * Silicon Laboratories, Inc. will not be liable for any consequential,
+ * incidental, or special damages, or any other relief, or for any claim by
+ * any third party, arising from your use of this Software.
+ *
+ *****************************************************************************/
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFM32PG1B_FPUEH
+ * @{
+ * @brief EFM32PG1B_FPUEH Register Declaration
+ *****************************************************************************/
+typedef struct
+{
+  __I uint32_t  IF;  /**< Interrupt Flag Register  */
+  __IO uint32_t IFS; /**< Interrupt Flag Set Register  */
+  __IO uint32_t IFC; /**< Interrupt Flag Clear Register  */
+  __IO uint32_t IEN; /**< Interrupt Enable Register  */
+} FPUEH_TypeDef;     /** @} */
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B_FPUEH_BitFields
+ * @{
+ *****************************************************************************/
+
+/* Bit fields for FPUEH IF */
+#define _FPUEH_IF_RESETVALUE        0x00000000UL                   /**< Default value for FPUEH_IF */
+#define _FPUEH_IF_MASK              0x0000003FUL                   /**< Mask for FPUEH_IF */
+#define FPUEH_IF_FPIOC              (0x1UL << 0)                   /**< FPU invalid operation */
+#define _FPUEH_IF_FPIOC_SHIFT       0                              /**< Shift value for FPUEH_FPIOC */
+#define _FPUEH_IF_FPIOC_MASK        0x1UL                          /**< Bit mask for FPUEH_FPIOC */
+#define _FPUEH_IF_FPIOC_DEFAULT     0x00000000UL                   /**< Mode DEFAULT for FPUEH_IF */
+#define FPUEH_IF_FPIOC_DEFAULT      (_FPUEH_IF_FPIOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FPUEH_IF */
+#define FPUEH_IF_FPDZC              (0x1UL << 1)                   /**< FPU divide-by-zero exception */
+#define _FPUEH_IF_FPDZC_SHIFT       1                              /**< Shift value for FPUEH_FPDZC */
+#define _FPUEH_IF_FPDZC_MASK        0x2UL                          /**< Bit mask for FPUEH_FPDZC */
+#define _FPUEH_IF_FPDZC_DEFAULT     0x00000000UL                   /**< Mode DEFAULT for FPUEH_IF */
+#define FPUEH_IF_FPDZC_DEFAULT      (_FPUEH_IF_FPDZC_DEFAULT << 1) /**< Shifted mode DEFAULT for FPUEH_IF */
+#define FPUEH_IF_FPUFC              (0x1UL << 2)                   /**< FPU underflow exception */
+#define _FPUEH_IF_FPUFC_SHIFT       2                              /**< Shift value for FPUEH_FPUFC */
+#define _FPUEH_IF_FPUFC_MASK        0x4UL                          /**< Bit mask for FPUEH_FPUFC */
+#define _FPUEH_IF_FPUFC_DEFAULT     0x00000000UL                   /**< Mode DEFAULT for FPUEH_IF */
+#define FPUEH_IF_FPUFC_DEFAULT      (_FPUEH_IF_FPUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for FPUEH_IF */
+#define FPUEH_IF_FPOFC              (0x1UL << 3)                   /**< FPU overflow exception */
+#define _FPUEH_IF_FPOFC_SHIFT       3                              /**< Shift value for FPUEH_FPOFC */
+#define _FPUEH_IF_FPOFC_MASK        0x8UL                          /**< Bit mask for FPUEH_FPOFC */
+#define _FPUEH_IF_FPOFC_DEFAULT     0x00000000UL                   /**< Mode DEFAULT for FPUEH_IF */
+#define FPUEH_IF_FPOFC_DEFAULT      (_FPUEH_IF_FPOFC_DEFAULT << 3) /**< Shifted mode DEFAULT for FPUEH_IF */
+#define FPUEH_IF_FPIDC              (0x1UL << 4)                   /**< FPU input denormal exception */
+#define _FPUEH_IF_FPIDC_SHIFT       4                              /**< Shift value for FPUEH_FPIDC */
+#define _FPUEH_IF_FPIDC_MASK        0x10UL                         /**< Bit mask for FPUEH_FPIDC */
+#define _FPUEH_IF_FPIDC_DEFAULT     0x00000000UL                   /**< Mode DEFAULT for FPUEH_IF */
+#define FPUEH_IF_FPIDC_DEFAULT      (_FPUEH_IF_FPIDC_DEFAULT << 4) /**< Shifted mode DEFAULT for FPUEH_IF */
+#define FPUEH_IF_FPIXC              (0x1UL << 5)                   /**< FPU inexact exception */
+#define _FPUEH_IF_FPIXC_SHIFT       5                              /**< Shift value for FPUEH_FPIXC */
+#define _FPUEH_IF_FPIXC_MASK        0x20UL                         /**< Bit mask for FPUEH_FPIXC */
+#define _FPUEH_IF_FPIXC_DEFAULT     0x00000000UL                   /**< Mode DEFAULT for FPUEH_IF */
+#define FPUEH_IF_FPIXC_DEFAULT      (_FPUEH_IF_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IF */
+
+/* Bit fields for FPUEH IFS */
+#define _FPUEH_IFS_RESETVALUE       0x00000000UL                    /**< Default value for FPUEH_IFS */
+#define _FPUEH_IFS_MASK             0x0000003FUL                    /**< Mask for FPUEH_IFS */
+#define FPUEH_IFS_FPIOC             (0x1UL << 0)                    /**< Set FPIOC Interrupt Flag */
+#define _FPUEH_IFS_FPIOC_SHIFT      0                               /**< Shift value for FPUEH_FPIOC */
+#define _FPUEH_IFS_FPIOC_MASK       0x1UL                           /**< Bit mask for FPUEH_FPIOC */
+#define _FPUEH_IFS_FPIOC_DEFAULT    0x00000000UL                    /**< Mode DEFAULT for FPUEH_IFS */
+#define FPUEH_IFS_FPIOC_DEFAULT     (_FPUEH_IFS_FPIOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FPUEH_IFS */
+#define FPUEH_IFS_FPDZC             (0x1UL << 1)                    /**< Set FPDZC Interrupt Flag */
+#define _FPUEH_IFS_FPDZC_SHIFT      1                               /**< Shift value for FPUEH_FPDZC */
+#define _FPUEH_IFS_FPDZC_MASK       0x2UL                           /**< Bit mask for FPUEH_FPDZC */
+#define _FPUEH_IFS_FPDZC_DEFAULT    0x00000000UL                    /**< Mode DEFAULT for FPUEH_IFS */
+#define FPUEH_IFS_FPDZC_DEFAULT     (_FPUEH_IFS_FPDZC_DEFAULT << 1) /**< Shifted mode DEFAULT for FPUEH_IFS */
+#define FPUEH_IFS_FPUFC             (0x1UL << 2)                    /**< Set FPUFC Interrupt Flag */
+#define _FPUEH_IFS_FPUFC_SHIFT      2                               /**< Shift value for FPUEH_FPUFC */
+#define _FPUEH_IFS_FPUFC_MASK       0x4UL                           /**< Bit mask for FPUEH_FPUFC */
+#define _FPUEH_IFS_FPUFC_DEFAULT    0x00000000UL                    /**< Mode DEFAULT for FPUEH_IFS */
+#define FPUEH_IFS_FPUFC_DEFAULT     (_FPUEH_IFS_FPUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for FPUEH_IFS */
+#define FPUEH_IFS_FPOFC             (0x1UL << 3)                    /**< Set FPOFC Interrupt Flag */
+#define _FPUEH_IFS_FPOFC_SHIFT      3                               /**< Shift value for FPUEH_FPOFC */
+#define _FPUEH_IFS_FPOFC_MASK       0x8UL                           /**< Bit mask for FPUEH_FPOFC */
+#define _FPUEH_IFS_FPOFC_DEFAULT    0x00000000UL                    /**< Mode DEFAULT for FPUEH_IFS */
+#define FPUEH_IFS_FPOFC_DEFAULT     (_FPUEH_IFS_FPOFC_DEFAULT << 3) /**< Shifted mode DEFAULT for FPUEH_IFS */
+#define FPUEH_IFS_FPIDC             (0x1UL << 4)                    /**< Set FPIDC Interrupt Flag */
+#define _FPUEH_IFS_FPIDC_SHIFT      4                               /**< Shift value for FPUEH_FPIDC */
+#define _FPUEH_IFS_FPIDC_MASK       0x10UL                          /**< Bit mask for FPUEH_FPIDC */
+#define _FPUEH_IFS_FPIDC_DEFAULT    0x00000000UL                    /**< Mode DEFAULT for FPUEH_IFS */
+#define FPUEH_IFS_FPIDC_DEFAULT     (_FPUEH_IFS_FPIDC_DEFAULT << 4) /**< Shifted mode DEFAULT for FPUEH_IFS */
+#define FPUEH_IFS_FPIXC             (0x1UL << 5)                    /**< Set FPIXC Interrupt Flag */
+#define _FPUEH_IFS_FPIXC_SHIFT      5                               /**< Shift value for FPUEH_FPIXC */
+#define _FPUEH_IFS_FPIXC_MASK       0x20UL                          /**< Bit mask for FPUEH_FPIXC */
+#define _FPUEH_IFS_FPIXC_DEFAULT    0x00000000UL                    /**< Mode DEFAULT for FPUEH_IFS */
+#define FPUEH_IFS_FPIXC_DEFAULT     (_FPUEH_IFS_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IFS */
+
+/* Bit fields for FPUEH IFC */
+#define _FPUEH_IFC_RESETVALUE       0x00000000UL                    /**< Default value for FPUEH_IFC */
+#define _FPUEH_IFC_MASK             0x0000003FUL                    /**< Mask for FPUEH_IFC */
+#define FPUEH_IFC_FPIOC             (0x1UL << 0)                    /**< Clear FPIOC Interrupt Flag */
+#define _FPUEH_IFC_FPIOC_SHIFT      0                               /**< Shift value for FPUEH_FPIOC */
+#define _FPUEH_IFC_FPIOC_MASK       0x1UL                           /**< Bit mask for FPUEH_FPIOC */
+#define _FPUEH_IFC_FPIOC_DEFAULT    0x00000000UL                    /**< Mode DEFAULT for FPUEH_IFC */
+#define FPUEH_IFC_FPIOC_DEFAULT     (_FPUEH_IFC_FPIOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FPUEH_IFC */
+#define FPUEH_IFC_FPDZC             (0x1UL << 1)                    /**< Clear FPDZC Interrupt Flag */
+#define _FPUEH_IFC_FPDZC_SHIFT      1                               /**< Shift value for FPUEH_FPDZC */
+#define _FPUEH_IFC_FPDZC_MASK       0x2UL                           /**< Bit mask for FPUEH_FPDZC */
+#define _FPUEH_IFC_FPDZC_DEFAULT    0x00000000UL                    /**< Mode DEFAULT for FPUEH_IFC */
+#define FPUEH_IFC_FPDZC_DEFAULT     (_FPUEH_IFC_FPDZC_DEFAULT << 1) /**< Shifted mode DEFAULT for FPUEH_IFC */
+#define FPUEH_IFC_FPUFC             (0x1UL << 2)                    /**< Clear FPUFC Interrupt Flag */
+#define _FPUEH_IFC_FPUFC_SHIFT      2                               /**< Shift value for FPUEH_FPUFC */
+#define _FPUEH_IFC_FPUFC_MASK       0x4UL                           /**< Bit mask for FPUEH_FPUFC */
+#define _FPUEH_IFC_FPUFC_DEFAULT    0x00000000UL                    /**< Mode DEFAULT for FPUEH_IFC */
+#define FPUEH_IFC_FPUFC_DEFAULT     (_FPUEH_IFC_FPUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for FPUEH_IFC */
+#define FPUEH_IFC_FPOFC             (0x1UL << 3)                    /**< Clear FPOFC Interrupt Flag */
+#define _FPUEH_IFC_FPOFC_SHIFT      3                               /**< Shift value for FPUEH_FPOFC */
+#define _FPUEH_IFC_FPOFC_MASK       0x8UL                           /**< Bit mask for FPUEH_FPOFC */
+#define _FPUEH_IFC_FPOFC_DEFAULT    0x00000000UL                    /**< Mode DEFAULT for FPUEH_IFC */
+#define FPUEH_IFC_FPOFC_DEFAULT     (_FPUEH_IFC_FPOFC_DEFAULT << 3) /**< Shifted mode DEFAULT for FPUEH_IFC */
+#define FPUEH_IFC_FPIDC             (0x1UL << 4)                    /**< Clear FPIDC Interrupt Flag */
+#define _FPUEH_IFC_FPIDC_SHIFT      4                               /**< Shift value for FPUEH_FPIDC */
+#define _FPUEH_IFC_FPIDC_MASK       0x10UL                          /**< Bit mask for FPUEH_FPIDC */
+#define _FPUEH_IFC_FPIDC_DEFAULT    0x00000000UL                    /**< Mode DEFAULT for FPUEH_IFC */
+#define FPUEH_IFC_FPIDC_DEFAULT     (_FPUEH_IFC_FPIDC_DEFAULT << 4) /**< Shifted mode DEFAULT for FPUEH_IFC */
+#define FPUEH_IFC_FPIXC             (0x1UL << 5)                    /**< Clear FPIXC Interrupt Flag */
+#define _FPUEH_IFC_FPIXC_SHIFT      5                               /**< Shift value for FPUEH_FPIXC */
+#define _FPUEH_IFC_FPIXC_MASK       0x20UL                          /**< Bit mask for FPUEH_FPIXC */
+#define _FPUEH_IFC_FPIXC_DEFAULT    0x00000000UL                    /**< Mode DEFAULT for FPUEH_IFC */
+#define FPUEH_IFC_FPIXC_DEFAULT     (_FPUEH_IFC_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IFC */
+
+/* Bit fields for FPUEH IEN */
+#define _FPUEH_IEN_RESETVALUE       0x00000000UL                    /**< Default value for FPUEH_IEN */
+#define _FPUEH_IEN_MASK             0x0000003FUL                    /**< Mask for FPUEH_IEN */
+#define FPUEH_IEN_FPIOC             (0x1UL << 0)                    /**< FPIOC Interrupt Enable */
+#define _FPUEH_IEN_FPIOC_SHIFT      0                               /**< Shift value for FPUEH_FPIOC */
+#define _FPUEH_IEN_FPIOC_MASK       0x1UL                           /**< Bit mask for FPUEH_FPIOC */
+#define _FPUEH_IEN_FPIOC_DEFAULT    0x00000000UL                    /**< Mode DEFAULT for FPUEH_IEN */
+#define FPUEH_IEN_FPIOC_DEFAULT     (_FPUEH_IEN_FPIOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FPUEH_IEN */
+#define FPUEH_IEN_FPDZC             (0x1UL << 1)                    /**< FPDZC Interrupt Enable */
+#define _FPUEH_IEN_FPDZC_SHIFT      1                               /**< Shift value for FPUEH_FPDZC */
+#define _FPUEH_IEN_FPDZC_MASK       0x2UL                           /**< Bit mask for FPUEH_FPDZC */
+#define _FPUEH_IEN_FPDZC_DEFAULT    0x00000000UL                    /**< Mode DEFAULT for FPUEH_IEN */
+#define FPUEH_IEN_FPDZC_DEFAULT     (_FPUEH_IEN_FPDZC_DEFAULT << 1) /**< Shifted mode DEFAULT for FPUEH_IEN */
+#define FPUEH_IEN_FPUFC             (0x1UL << 2)                    /**< FPUFC Interrupt Enable */
+#define _FPUEH_IEN_FPUFC_SHIFT      2                               /**< Shift value for FPUEH_FPUFC */
+#define _FPUEH_IEN_FPUFC_MASK       0x4UL                           /**< Bit mask for FPUEH_FPUFC */
+#define _FPUEH_IEN_FPUFC_DEFAULT    0x00000000UL                    /**< Mode DEFAULT for FPUEH_IEN */
+#define FPUEH_IEN_FPUFC_DEFAULT     (_FPUEH_IEN_FPUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for FPUEH_IEN */
+#define FPUEH_IEN_FPOFC             (0x1UL << 3)                    /**< FPOFC Interrupt Enable */
+#define _FPUEH_IEN_FPOFC_SHIFT      3                               /**< Shift value for FPUEH_FPOFC */
+#define _FPUEH_IEN_FPOFC_MASK       0x8UL                           /**< Bit mask for FPUEH_FPOFC */
+#define _FPUEH_IEN_FPOFC_DEFAULT    0x00000000UL                    /**< Mode DEFAULT for FPUEH_IEN */
+#define FPUEH_IEN_FPOFC_DEFAULT     (_FPUEH_IEN_FPOFC_DEFAULT << 3) /**< Shifted mode DEFAULT for FPUEH_IEN */
+#define FPUEH_IEN_FPIDC             (0x1UL << 4)                    /**< FPIDC Interrupt Enable */
+#define _FPUEH_IEN_FPIDC_SHIFT      4                               /**< Shift value for FPUEH_FPIDC */
+#define _FPUEH_IEN_FPIDC_MASK       0x10UL                          /**< Bit mask for FPUEH_FPIDC */
+#define _FPUEH_IEN_FPIDC_DEFAULT    0x00000000UL                    /**< Mode DEFAULT for FPUEH_IEN */
+#define FPUEH_IEN_FPIDC_DEFAULT     (_FPUEH_IEN_FPIDC_DEFAULT << 4) /**< Shifted mode DEFAULT for FPUEH_IEN */
+#define FPUEH_IEN_FPIXC             (0x1UL << 5)                    /**< FPIXC Interrupt Enable */
+#define _FPUEH_IEN_FPIXC_SHIFT      5                               /**< Shift value for FPUEH_FPIXC */
+#define _FPUEH_IEN_FPIXC_MASK       0x20UL                          /**< Bit mask for FPUEH_FPIXC */
+#define _FPUEH_IEN_FPIXC_DEFAULT    0x00000000UL                    /**< Mode DEFAULT for FPUEH_IEN */
+#define FPUEH_IEN_FPIXC_DEFAULT     (_FPUEH_IEN_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IEN */
+
+/** @} End of group EFM32PG1B_FPUEH */
+/** @} End of group Parts */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG_STK3401/efm32pg1b_gpcrc.h	Fri Jan 15 07:45:16 2016 +0000
@@ -0,0 +1,181 @@
+/**************************************************************************//**
+ * @file efm32pg1b_gpcrc.h
+ * @brief EFM32PG1B_GPCRC register and bit field definitions
+ * @version 4.2.0
+ ******************************************************************************
+ * @section License
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ ******************************************************************************
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software.@n
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.@n
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is
+ * providing the Software "AS IS", with no express or implied warranties of any
+ * kind, including, but not limited to, any implied warranties of
+ * merchantability or fitness for any particular purpose or warranties against
+ * infringement of any proprietary rights of a third party.
+ *
+ * Silicon Laboratories, Inc. will not be liable for any consequential,
+ * incidental, or special damages, or any other relief, or for any claim by
+ * any third party, arising from your use of this Software.
+ *
+ *****************************************************************************/
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFM32PG1B_GPCRC
+ * @{
+ * @brief EFM32PG1B_GPCRC Register Declaration
+ *****************************************************************************/
+typedef struct
+{
+  __IO uint32_t CTRL;           /**< Control Register  */
+  __IO uint32_t CMD;            /**< Command Register  */
+  __IO uint32_t INIT;           /**< CRC Init Value  */
+  __IO uint32_t POLY;           /**< CRC Polynomial Value  */
+  __IO uint32_t INPUTDATA;      /**< Input 32-bit Data Register  */
+  __IO uint32_t INPUTDATAHWORD; /**< Input 16-bit Data Register  */
+  __IO uint32_t INPUTDATABYTE;  /**< Input 8-bit Data Register  */
+  __I uint32_t  DATA;           /**< CRC Data Register  */
+  __I uint32_t  DATAREV;        /**< CRC Data Reverse Register  */
+  __I uint32_t  DATABYTEREV;    /**< CRC Data Byte Reverse Register  */
+} GPCRC_TypeDef;                /** @} */
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B_GPCRC_BitFields
+ * @{
+ *****************************************************************************/
+
+/* Bit fields for GPCRC CTRL */
+#define _GPCRC_CTRL_RESETVALUE                          0x00000000UL                             /**< Default value for GPCRC_CTRL */
+#define _GPCRC_CTRL_MASK                                0x00002711UL                             /**< Mask for GPCRC_CTRL */
+#define GPCRC_CTRL_EN                                   (0x1UL << 0)                             /**< CRC Functionality Enable */
+#define _GPCRC_CTRL_EN_SHIFT                            0                                        /**< Shift value for GPCRC_EN */
+#define _GPCRC_CTRL_EN_MASK                             0x1UL                                    /**< Bit mask for GPCRC_EN */
+#define _GPCRC_CTRL_EN_DEFAULT                          0x00000000UL                             /**< Mode DEFAULT for GPCRC_CTRL */
+#define _GPCRC_CTRL_EN_DISABLE                          0x00000000UL                             /**< Mode DISABLE for GPCRC_CTRL */
+#define _GPCRC_CTRL_EN_ENABLE                           0x00000001UL                             /**< Mode ENABLE for GPCRC_CTRL */
+#define GPCRC_CTRL_EN_DEFAULT                           (_GPCRC_CTRL_EN_DEFAULT << 0)            /**< Shifted mode DEFAULT for GPCRC_CTRL */
+#define GPCRC_CTRL_EN_DISABLE                           (_GPCRC_CTRL_EN_DISABLE << 0)            /**< Shifted mode DISABLE for GPCRC_CTRL */
+#define GPCRC_CTRL_EN_ENABLE                            (_GPCRC_CTRL_EN_ENABLE << 0)             /**< Shifted mode ENABLE for GPCRC_CTRL */
+#define GPCRC_CTRL_POLYSEL                              (0x1UL << 4)                             /**< Polynomial Select */
+#define _GPCRC_CTRL_POLYSEL_SHIFT                       4                                        /**< Shift value for GPCRC_POLYSEL */
+#define _GPCRC_CTRL_POLYSEL_MASK                        0x10UL                                   /**< Bit mask for GPCRC_POLYSEL */
+#define _GPCRC_CTRL_POLYSEL_DEFAULT                     0x00000000UL                             /**< Mode DEFAULT for GPCRC_CTRL */
+#define _GPCRC_CTRL_POLYSEL_CRC32                       0x00000000UL                             /**< Mode CRC32 for GPCRC_CTRL */
+#define _GPCRC_CTRL_POLYSEL_16                          0x00000001UL                             /**< Mode 16 for GPCRC_CTRL */
+#define GPCRC_CTRL_POLYSEL_DEFAULT                      (_GPCRC_CTRL_POLYSEL_DEFAULT << 4)       /**< Shifted mode DEFAULT for GPCRC_CTRL */
+#define GPCRC_CTRL_POLYSEL_CRC32                        (_GPCRC_CTRL_POLYSEL_CRC32 << 4)         /**< Shifted mode CRC32 for GPCRC_CTRL */
+#define GPCRC_CTRL_POLYSEL_16                           (_GPCRC_CTRL_POLYSEL_16 << 4)            /**< Shifted mode 16 for GPCRC_CTRL */
+#define GPCRC_CTRL_BYTEMODE                             (0x1UL << 8)                             /**< Byte Mode Enable */
+#define _GPCRC_CTRL_BYTEMODE_SHIFT                      8                                        /**< Shift value for GPCRC_BYTEMODE */
+#define _GPCRC_CTRL_BYTEMODE_MASK                       0x100UL                                  /**< Bit mask for GPCRC_BYTEMODE */
+#define _GPCRC_CTRL_BYTEMODE_DEFAULT                    0x00000000UL                             /**< Mode DEFAULT for GPCRC_CTRL */
+#define GPCRC_CTRL_BYTEMODE_DEFAULT                     (_GPCRC_CTRL_BYTEMODE_DEFAULT << 8)      /**< Shifted mode DEFAULT for GPCRC_CTRL */
+#define GPCRC_CTRL_BITREVERSE                           (0x1UL << 9)                             /**< Byte-level Bit Reverse Enable */
+#define _GPCRC_CTRL_BITREVERSE_SHIFT                    9                                        /**< Shift value for GPCRC_BITREVERSE */
+#define _GPCRC_CTRL_BITREVERSE_MASK                     0x200UL                                  /**< Bit mask for GPCRC_BITREVERSE */
+#define _GPCRC_CTRL_BITREVERSE_DEFAULT                  0x00000000UL                             /**< Mode DEFAULT for GPCRC_CTRL */
+#define GPCRC_CTRL_BITREVERSE_DEFAULT                   (_GPCRC_CTRL_BITREVERSE_DEFAULT << 9)    /**< Shifted mode DEFAULT for GPCRC_CTRL */
+#define GPCRC_CTRL_BYTEREVERSE                          (0x1UL << 10)                            /**< Byte Reverse Mode */
+#define _GPCRC_CTRL_BYTEREVERSE_SHIFT                   10                                       /**< Shift value for GPCRC_BYTEREVERSE */
+#define _GPCRC_CTRL_BYTEREVERSE_MASK                    0x400UL                                  /**< Bit mask for GPCRC_BYTEREVERSE */
+#define _GPCRC_CTRL_BYTEREVERSE_DEFAULT                 0x00000000UL                             /**< Mode DEFAULT for GPCRC_CTRL */
+#define _GPCRC_CTRL_BYTEREVERSE_NORMAL                  0x00000000UL                             /**< Mode NORMAL for GPCRC_CTRL */
+#define _GPCRC_CTRL_BYTEREVERSE_REVERSED                0x00000001UL                             /**< Mode REVERSED for GPCRC_CTRL */
+#define GPCRC_CTRL_BYTEREVERSE_DEFAULT                  (_GPCRC_CTRL_BYTEREVERSE_DEFAULT << 10)  /**< Shifted mode DEFAULT for GPCRC_CTRL */
+#define GPCRC_CTRL_BYTEREVERSE_NORMAL                   (_GPCRC_CTRL_BYTEREVERSE_NORMAL << 10)   /**< Shifted mode NORMAL for GPCRC_CTRL */
+#define GPCRC_CTRL_BYTEREVERSE_REVERSED                 (_GPCRC_CTRL_BYTEREVERSE_REVERSED << 10) /**< Shifted mode REVERSED for GPCRC_CTRL */
+#define GPCRC_CTRL_AUTOINIT                             (0x1UL << 13)                            /**< Auto Init Enable */
+#define _GPCRC_CTRL_AUTOINIT_SHIFT                      13                                       /**< Shift value for GPCRC_AUTOINIT */
+#define _GPCRC_CTRL_AUTOINIT_MASK                       0x2000UL                                 /**< Bit mask for GPCRC_AUTOINIT */
+#define _GPCRC_CTRL_AUTOINIT_DEFAULT                    0x00000000UL                             /**< Mode DEFAULT for GPCRC_CTRL */
+#define GPCRC_CTRL_AUTOINIT_DEFAULT                     (_GPCRC_CTRL_AUTOINIT_DEFAULT << 13)     /**< Shifted mode DEFAULT for GPCRC_CTRL */
+
+/* Bit fields for GPCRC CMD */
+#define _GPCRC_CMD_RESETVALUE                           0x00000000UL                   /**< Default value for GPCRC_CMD */
+#define _GPCRC_CMD_MASK                                 0x00000001UL                   /**< Mask for GPCRC_CMD */
+#define GPCRC_CMD_INIT                                  (0x1UL << 0)                   /**< Initialization Enable */
+#define _GPCRC_CMD_INIT_SHIFT                           0                              /**< Shift value for GPCRC_INIT */
+#define _GPCRC_CMD_INIT_MASK                            0x1UL                          /**< Bit mask for GPCRC_INIT */
+#define _GPCRC_CMD_INIT_DEFAULT                         0x00000000UL                   /**< Mode DEFAULT for GPCRC_CMD */
+#define GPCRC_CMD_INIT_DEFAULT                          (_GPCRC_CMD_INIT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_CMD */
+
+/* Bit fields for GPCRC INIT */
+#define _GPCRC_INIT_RESETVALUE                          0x00000000UL                    /**< Default value for GPCRC_INIT */
+#define _GPCRC_INIT_MASK                                0xFFFFFFFFUL                    /**< Mask for GPCRC_INIT */
+#define _GPCRC_INIT_INIT_SHIFT                          0                               /**< Shift value for GPCRC_INIT */
+#define _GPCRC_INIT_INIT_MASK                           0xFFFFFFFFUL                    /**< Bit mask for GPCRC_INIT */
+#define _GPCRC_INIT_INIT_DEFAULT                        0x00000000UL                    /**< Mode DEFAULT for GPCRC_INIT */
+#define GPCRC_INIT_INIT_DEFAULT                         (_GPCRC_INIT_INIT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INIT */
+
+/* Bit fields for GPCRC POLY */
+#define _GPCRC_POLY_RESETVALUE                          0x00000000UL                    /**< Default value for GPCRC_POLY */
+#define _GPCRC_POLY_MASK                                0x0000FFFFUL                    /**< Mask for GPCRC_POLY */
+#define _GPCRC_POLY_POLY_SHIFT                          0                               /**< Shift value for GPCRC_POLY */
+#define _GPCRC_POLY_POLY_MASK                           0xFFFFUL                        /**< Bit mask for GPCRC_POLY */
+#define _GPCRC_POLY_POLY_DEFAULT                        0x00000000UL                    /**< Mode DEFAULT for GPCRC_POLY */
+#define GPCRC_POLY_POLY_DEFAULT                         (_GPCRC_POLY_POLY_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_POLY */
+
+/* Bit fields for GPCRC INPUTDATA */
+#define _GPCRC_INPUTDATA_RESETVALUE                     0x00000000UL                              /**< Default value for GPCRC_INPUTDATA */
+#define _GPCRC_INPUTDATA_MASK                           0xFFFFFFFFUL                              /**< Mask for GPCRC_INPUTDATA */
+#define _GPCRC_INPUTDATA_INPUTDATA_SHIFT                0                                         /**< Shift value for GPCRC_INPUTDATA */
+#define _GPCRC_INPUTDATA_INPUTDATA_MASK                 0xFFFFFFFFUL                              /**< Bit mask for GPCRC_INPUTDATA */
+#define _GPCRC_INPUTDATA_INPUTDATA_DEFAULT              0x00000000UL                              /**< Mode DEFAULT for GPCRC_INPUTDATA */
+#define GPCRC_INPUTDATA_INPUTDATA_DEFAULT               (_GPCRC_INPUTDATA_INPUTDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATA */
+
+/* Bit fields for GPCRC INPUTDATAHWORD */
+#define _GPCRC_INPUTDATAHWORD_RESETVALUE                0x00000000UL                                        /**< Default value for GPCRC_INPUTDATAHWORD */
+#define _GPCRC_INPUTDATAHWORD_MASK                      0x0000FFFFUL                                        /**< Mask for GPCRC_INPUTDATAHWORD */
+#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_SHIFT      0                                                   /**< Shift value for GPCRC_INPUTDATAHWORD */
+#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_MASK       0xFFFFUL                                            /**< Bit mask for GPCRC_INPUTDATAHWORD */
+#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT    0x00000000UL                                        /**< Mode DEFAULT for GPCRC_INPUTDATAHWORD */
+#define GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT     (_GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATAHWORD */
+
+/* Bit fields for GPCRC INPUTDATABYTE */
+#define _GPCRC_INPUTDATABYTE_RESETVALUE                 0x00000000UL                                      /**< Default value for GPCRC_INPUTDATABYTE */
+#define _GPCRC_INPUTDATABYTE_MASK                       0x000000FFUL                                      /**< Mask for GPCRC_INPUTDATABYTE */
+#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_SHIFT        0                                                 /**< Shift value for GPCRC_INPUTDATABYTE */
+#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_MASK         0xFFUL                                            /**< Bit mask for GPCRC_INPUTDATABYTE */
+#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT      0x00000000UL                                      /**< Mode DEFAULT for GPCRC_INPUTDATABYTE */
+#define GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT       (_GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATABYTE */
+
+/* Bit fields for GPCRC DATA */
+#define _GPCRC_DATA_RESETVALUE                          0x00000000UL                    /**< Default value for GPCRC_DATA */
+#define _GPCRC_DATA_MASK                                0xFFFFFFFFUL                    /**< Mask for GPCRC_DATA */
+#define _GPCRC_DATA_DATA_SHIFT                          0                               /**< Shift value for GPCRC_DATA */
+#define _GPCRC_DATA_DATA_MASK                           0xFFFFFFFFUL                    /**< Bit mask for GPCRC_DATA */
+#define _GPCRC_DATA_DATA_DEFAULT                        0x00000000UL                    /**< Mode DEFAULT for GPCRC_DATA */
+#define GPCRC_DATA_DATA_DEFAULT                         (_GPCRC_DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATA */
+
+/* Bit fields for GPCRC DATAREV */
+#define _GPCRC_DATAREV_RESETVALUE                       0x00000000UL                          /**< Default value for GPCRC_DATAREV */
+#define _GPCRC_DATAREV_MASK                             0xFFFFFFFFUL                          /**< Mask for GPCRC_DATAREV */
+#define _GPCRC_DATAREV_DATAREV_SHIFT                    0                                     /**< Shift value for GPCRC_DATAREV */
+#define _GPCRC_DATAREV_DATAREV_MASK                     0xFFFFFFFFUL                          /**< Bit mask for GPCRC_DATAREV */
+#define _GPCRC_DATAREV_DATAREV_DEFAULT                  0x00000000UL                          /**< Mode DEFAULT for GPCRC_DATAREV */
+#define GPCRC_DATAREV_DATAREV_DEFAULT                   (_GPCRC_DATAREV_DATAREV_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATAREV */
+
+/* Bit fields for GPCRC DATABYTEREV */
+#define _GPCRC_DATABYTEREV_RESETVALUE                   0x00000000UL                                  /**< Default value for GPCRC_DATABYTEREV */
+#define _GPCRC_DATABYTEREV_MASK                         0xFFFFFFFFUL                                  /**< Mask for GPCRC_DATABYTEREV */
+#define _GPCRC_DATABYTEREV_DATABYTEREV_SHIFT            0                                             /**< Shift value for GPCRC_DATABYTEREV */
+#define _GPCRC_DATABYTEREV_DATABYTEREV_MASK             0xFFFFFFFFUL                                  /**< Bit mask for GPCRC_DATABYTEREV */
+#define _GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT          0x00000000UL                                  /**< Mode DEFAULT for GPCRC_DATABYTEREV */
+#define GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT           (_GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATABYTEREV */
+
+/** @} End of group EFM32PG1B_GPCRC */
+/** @} End of group Parts */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG_STK3401/efm32pg1b_gpio.h	Fri Jan 15 07:45:16 2016 +0000
@@ -0,0 +1,1352 @@
+/**************************************************************************//**
+ * @file efm32pg1b_gpio.h
+ * @brief EFM32PG1B_GPIO register and bit field definitions
+ * @version 4.2.0
+ ******************************************************************************
+ * @section License
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ ******************************************************************************
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software.@n
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.@n
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is
+ * providing the Software "AS IS", with no express or implied warranties of any
+ * kind, including, but not limited to, any implied warranties of
+ * merchantability or fitness for any particular purpose or warranties against
+ * infringement of any proprietary rights of a third party.
+ *
+ * Silicon Laboratories, Inc. will not be liable for any consequential,
+ * incidental, or special damages, or any other relief, or for any claim by
+ * any third party, arising from your use of this Software.
+ *
+ *****************************************************************************/
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFM32PG1B_GPIO
+ * @{
+ * @brief EFM32PG1B_GPIO Register Declaration
+ *****************************************************************************/
+typedef struct
+{
+  GPIO_P_TypeDef P[12];          /**< Port configuration bits */
+
+  uint32_t       RESERVED0[112]; /**< Reserved for future use **/
+  __IO uint32_t  EXTIPSELL;      /**< External Interrupt Port Select Low Register  */
+  __IO uint32_t  EXTIPSELH;      /**< External Interrupt Port Select High Register  */
+  __IO uint32_t  EXTIPINSELL;    /**< External Interrupt Pin Select Low Register  */
+  __IO uint32_t  EXTIPINSELH;    /**< External Interrupt Pin Select High Register  */
+  __IO uint32_t  EXTIRISE;       /**< External Interrupt Rising Edge Trigger Register  */
+  __IO uint32_t  EXTIFALL;       /**< External Interrupt Falling Edge Trigger Register  */
+  __IO uint32_t  EXTILEVEL;      /**< External Interrupt Level Register  */
+  __I uint32_t   IF;             /**< Interrupt Flag Register  */
+  __IO uint32_t  IFS;            /**< Interrupt Flag Set Register  */
+  __IO uint32_t  IFC;            /**< Interrupt Flag Clear Register  */
+  __IO uint32_t  IEN;            /**< Interrupt Enable Register  */
+  __IO uint32_t  EM4WUEN;        /**< EM4 wake up Enable Register  */
+
+  uint32_t       RESERVED1[4];   /**< Reserved for future use **/
+  __IO uint32_t  ROUTEPEN;       /**< I/O Routing Pin Enable Register  */
+  __IO uint32_t  ROUTELOC0;      /**< I/O Routing Location Register  */
+
+  uint32_t       RESERVED2[2];   /**< Reserved for future use **/
+  __IO uint32_t  INSENSE;        /**< Input Sense Register  */
+  __IO uint32_t  LOCK;           /**< Configuration Lock Register  */
+} GPIO_TypeDef;                  /** @} */
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B_GPIO_BitFields
+ * @{
+ *****************************************************************************/
+
+/* Bit fields for GPIO P_CTRL */
+#define _GPIO_P_CTRL_RESETVALUE                         0x00600060UL                                  /**< Default value for GPIO_P_CTRL */
+#define _GPIO_P_CTRL_MASK                               0x10711071UL                                  /**< Mask for GPIO_P_CTRL */
+#define GPIO_P_CTRL_DRIVESTRENGTH                       (0x1UL << 0)                                  /**< Drive strength for port */
+#define _GPIO_P_CTRL_DRIVESTRENGTH_SHIFT                0                                             /**< Shift value for GPIO_DRIVESTRENGTH */
+#define _GPIO_P_CTRL_DRIVESTRENGTH_MASK                 0x1UL                                         /**< Bit mask for GPIO_DRIVESTRENGTH */
+#define _GPIO_P_CTRL_DRIVESTRENGTH_DEFAULT              0x00000000UL                                  /**< Mode DEFAULT for GPIO_P_CTRL */
+#define _GPIO_P_CTRL_DRIVESTRENGTH_STRONG               0x00000000UL                                  /**< Mode STRONG for GPIO_P_CTRL */
+#define _GPIO_P_CTRL_DRIVESTRENGTH_WEAK                 0x00000001UL                                  /**< Mode WEAK for GPIO_P_CTRL */
+#define GPIO_P_CTRL_DRIVESTRENGTH_DEFAULT               (_GPIO_P_CTRL_DRIVESTRENGTH_DEFAULT << 0)     /**< Shifted mode DEFAULT for GPIO_P_CTRL */
+#define GPIO_P_CTRL_DRIVESTRENGTH_STRONG                (_GPIO_P_CTRL_DRIVESTRENGTH_STRONG << 0)      /**< Shifted mode STRONG for GPIO_P_CTRL */
+#define GPIO_P_CTRL_DRIVESTRENGTH_WEAK                  (_GPIO_P_CTRL_DRIVESTRENGTH_WEAK << 0)        /**< Shifted mode WEAK for GPIO_P_CTRL */
+#define _GPIO_P_CTRL_SLEWRATE_SHIFT                     4                                             /**< Shift value for GPIO_SLEWRATE */
+#define _GPIO_P_CTRL_SLEWRATE_MASK                      0x70UL                                        /**< Bit mask for GPIO_SLEWRATE */
+#define _GPIO_P_CTRL_SLEWRATE_DEFAULT                   0x00000006UL                                  /**< Mode DEFAULT for GPIO_P_CTRL */
+#define GPIO_P_CTRL_SLEWRATE_DEFAULT                    (_GPIO_P_CTRL_SLEWRATE_DEFAULT << 4)          /**< Shifted mode DEFAULT for GPIO_P_CTRL */
+#define GPIO_P_CTRL_DINDIS                              (0x1UL << 12)                                 /**< Data In Disable */
+#define _GPIO_P_CTRL_DINDIS_SHIFT                       12                                            /**< Shift value for GPIO_DINDIS */
+#define _GPIO_P_CTRL_DINDIS_MASK                        0x1000UL                                      /**< Bit mask for GPIO_DINDIS */
+#define _GPIO_P_CTRL_DINDIS_DEFAULT                     0x00000000UL                                  /**< Mode DEFAULT for GPIO_P_CTRL */
+#define GPIO_P_CTRL_DINDIS_DEFAULT                      (_GPIO_P_CTRL_DINDIS_DEFAULT << 12)           /**< Shifted mode DEFAULT for GPIO_P_CTRL */
+#define GPIO_P_CTRL_DRIVESTRENGTHALT                    (0x1UL << 16)                                 /**< Alternate drive strength for port */
+#define _GPIO_P_CTRL_DRIVESTRENGTHALT_SHIFT             16                                            /**< Shift value for GPIO_DRIVESTRENGTHALT */
+#define _GPIO_P_CTRL_DRIVESTRENGTHALT_MASK              0x10000UL                                     /**< Bit mask for GPIO_DRIVESTRENGTHALT */
+#define _GPIO_P_CTRL_DRIVESTRENGTHALT_DEFAULT           0x00000000UL                                  /**< Mode DEFAULT for GPIO_P_CTRL */
+#define _GPIO_P_CTRL_DRIVESTRENGTHALT_STRONG            0x00000000UL                                  /**< Mode STRONG for GPIO_P_CTRL */
+#define _GPIO_P_CTRL_DRIVESTRENGTHALT_WEAK              0x00000001UL                                  /**< Mode WEAK for GPIO_P_CTRL */
+#define GPIO_P_CTRL_DRIVESTRENGTHALT_DEFAULT            (_GPIO_P_CTRL_DRIVESTRENGTHALT_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_P_CTRL */
+#define GPIO_P_CTRL_DRIVESTRENGTHALT_STRONG             (_GPIO_P_CTRL_DRIVESTRENGTHALT_STRONG << 16)  /**< Shifted mode STRONG for GPIO_P_CTRL */
+#define GPIO_P_CTRL_DRIVESTRENGTHALT_WEAK               (_GPIO_P_CTRL_DRIVESTRENGTHALT_WEAK << 16)    /**< Shifted mode WEAK for GPIO_P_CTRL */
+#define _GPIO_P_CTRL_SLEWRATEALT_SHIFT                  20                                            /**< Shift value for GPIO_SLEWRATEALT */
+#define _GPIO_P_CTRL_SLEWRATEALT_MASK                   0x700000UL                                    /**< Bit mask for GPIO_SLEWRATEALT */
+#define _GPIO_P_CTRL_SLEWRATEALT_DEFAULT                0x00000006UL                                  /**< Mode DEFAULT for GPIO_P_CTRL */
+#define GPIO_P_CTRL_SLEWRATEALT_DEFAULT                 (_GPIO_P_CTRL_SLEWRATEALT_DEFAULT << 20)      /**< Shifted mode DEFAULT for GPIO_P_CTRL */
+#define GPIO_P_CTRL_DINDISALT                           (0x1UL << 28)                                 /**< Alternate Data In Disable */
+#define _GPIO_P_CTRL_DINDISALT_SHIFT                    28                                            /**< Shift value for GPIO_DINDISALT */
+#define _GPIO_P_CTRL_DINDISALT_MASK                     0x10000000UL                                  /**< Bit mask for GPIO_DINDISALT */
+#define _GPIO_P_CTRL_DINDISALT_DEFAULT                  0x00000000UL                                  /**< Mode DEFAULT for GPIO_P_CTRL */
+#define GPIO_P_CTRL_DINDISALT_DEFAULT                   (_GPIO_P_CTRL_DINDISALT_DEFAULT << 28)        /**< Shifted mode DEFAULT for GPIO_P_CTRL */
+
+/* Bit fields for GPIO P_MODEL */
+#define _GPIO_P_MODEL_RESETVALUE                        0x00000000UL                                        /**< Default value for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MASK                              0xFFFFFFFFUL                                        /**< Mask for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE0_SHIFT                       0                                                   /**< Shift value for GPIO_MODE0 */
+#define _GPIO_P_MODEL_MODE0_MASK                        0xFUL                                               /**< Bit mask for GPIO_MODE0 */
+#define _GPIO_P_MODEL_MODE0_DEFAULT                     0x00000000UL                                        /**< Mode DEFAULT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE0_DISABLED                    0x00000000UL                                        /**< Mode DISABLED for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE0_INPUT                       0x00000001UL                                        /**< Mode INPUT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE0_INPUTPULL                   0x00000002UL                                        /**< Mode INPUTPULL for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE0_INPUTPULLFILTER             0x00000003UL                                        /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE0_PUSHPULL                    0x00000004UL                                        /**< Mode PUSHPULL for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE0_PUSHPULLALT                 0x00000005UL                                        /**< Mode PUSHPULLALT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE0_WIREDOR                     0x00000006UL                                        /**< Mode WIREDOR for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE0_WIREDORPULLDOWN             0x00000007UL                                        /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE0_WIREDAND                    0x00000008UL                                        /**< Mode WIREDAND for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE0_WIREDANDFILTER              0x00000009UL                                        /**< Mode WIREDANDFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE0_WIREDANDPULLUP              0x0000000AUL                                        /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER        0x0000000BUL                                        /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE0_WIREDANDALT                 0x0000000CUL                                        /**< Mode WIREDANDALT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE0_WIREDANDALTFILTER           0x0000000DUL                                        /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP           0x0000000EUL                                        /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER     0x0000000FUL                                        /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE0_DEFAULT                      (_GPIO_P_MODEL_MODE0_DEFAULT << 0)                  /**< Shifted mode DEFAULT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE0_DISABLED                     (_GPIO_P_MODEL_MODE0_DISABLED << 0)                 /**< Shifted mode DISABLED for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE0_INPUT                        (_GPIO_P_MODEL_MODE0_INPUT << 0)                    /**< Shifted mode INPUT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE0_INPUTPULL                    (_GPIO_P_MODEL_MODE0_INPUTPULL << 0)                /**< Shifted mode INPUTPULL for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE0_INPUTPULLFILTER              (_GPIO_P_MODEL_MODE0_INPUTPULLFILTER << 0)          /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE0_PUSHPULL                     (_GPIO_P_MODEL_MODE0_PUSHPULL << 0)                 /**< Shifted mode PUSHPULL for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE0_PUSHPULLALT                  (_GPIO_P_MODEL_MODE0_PUSHPULLALT << 0)              /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE0_WIREDOR                      (_GPIO_P_MODEL_MODE0_WIREDOR << 0)                  /**< Shifted mode WIREDOR for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE0_WIREDORPULLDOWN              (_GPIO_P_MODEL_MODE0_WIREDORPULLDOWN << 0)          /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE0_WIREDAND                     (_GPIO_P_MODEL_MODE0_WIREDAND << 0)                 /**< Shifted mode WIREDAND for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE0_WIREDANDFILTER               (_GPIO_P_MODEL_MODE0_WIREDANDFILTER << 0)           /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE0_WIREDANDPULLUP               (_GPIO_P_MODEL_MODE0_WIREDANDPULLUP << 0)           /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER         (_GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER << 0)     /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE0_WIREDANDALT                  (_GPIO_P_MODEL_MODE0_WIREDANDALT << 0)              /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE0_WIREDANDALTFILTER            (_GPIO_P_MODEL_MODE0_WIREDANDALTFILTER << 0)        /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP            (_GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP << 0)        /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER      (_GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER << 0)  /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE1_SHIFT                       4                                                   /**< Shift value for GPIO_MODE1 */
+#define _GPIO_P_MODEL_MODE1_MASK                        0xF0UL                                              /**< Bit mask for GPIO_MODE1 */
+#define _GPIO_P_MODEL_MODE1_DEFAULT                     0x00000000UL                                        /**< Mode DEFAULT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE1_DISABLED                    0x00000000UL                                        /**< Mode DISABLED for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE1_INPUT                       0x00000001UL                                        /**< Mode INPUT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE1_INPUTPULL                   0x00000002UL                                        /**< Mode INPUTPULL for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE1_INPUTPULLFILTER             0x00000003UL                                        /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE1_PUSHPULL                    0x00000004UL                                        /**< Mode PUSHPULL for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE1_PUSHPULLALT                 0x00000005UL                                        /**< Mode PUSHPULLALT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE1_WIREDOR                     0x00000006UL                                        /**< Mode WIREDOR for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE1_WIREDORPULLDOWN             0x00000007UL                                        /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE1_WIREDAND                    0x00000008UL                                        /**< Mode WIREDAND for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE1_WIREDANDFILTER              0x00000009UL                                        /**< Mode WIREDANDFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE1_WIREDANDPULLUP              0x0000000AUL                                        /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER        0x0000000BUL                                        /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE1_WIREDANDALT                 0x0000000CUL                                        /**< Mode WIREDANDALT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE1_WIREDANDALTFILTER           0x0000000DUL                                        /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE1_WIREDANDALTPULLUP           0x0000000EUL                                        /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE1_WIREDANDALTPULLUPFILTER     0x0000000FUL                                        /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE1_DEFAULT                      (_GPIO_P_MODEL_MODE1_DEFAULT << 4)                  /**< Shifted mode DEFAULT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE1_DISABLED                     (_GPIO_P_MODEL_MODE1_DISABLED << 4)                 /**< Shifted mode DISABLED for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE1_INPUT                        (_GPIO_P_MODEL_MODE1_INPUT << 4)                    /**< Shifted mode INPUT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE1_INPUTPULL                    (_GPIO_P_MODEL_MODE1_INPUTPULL << 4)                /**< Shifted mode INPUTPULL for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE1_INPUTPULLFILTER              (_GPIO_P_MODEL_MODE1_INPUTPULLFILTER << 4)          /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE1_PUSHPULL                     (_GPIO_P_MODEL_MODE1_PUSHPULL << 4)                 /**< Shifted mode PUSHPULL for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE1_PUSHPULLALT                  (_GPIO_P_MODEL_MODE1_PUSHPULLALT << 4)              /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE1_WIREDOR                      (_GPIO_P_MODEL_MODE1_WIREDOR << 4)                  /**< Shifted mode WIREDOR for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE1_WIREDORPULLDOWN              (_GPIO_P_MODEL_MODE1_WIREDORPULLDOWN << 4)          /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE1_WIREDAND                     (_GPIO_P_MODEL_MODE1_WIREDAND << 4)                 /**< Shifted mode WIREDAND for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE1_WIREDANDFILTER               (_GPIO_P_MODEL_MODE1_WIREDANDFILTER << 4)           /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE1_WIREDANDPULLUP               (_GPIO_P_MODEL_MODE1_WIREDANDPULLUP << 4)           /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER         (_GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER << 4)     /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE1_WIREDANDALT                  (_GPIO_P_MODEL_MODE1_WIREDANDALT << 4)              /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE1_WIREDANDALTFILTER            (_GPIO_P_MODEL_MODE1_WIREDANDALTFILTER << 4)        /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE1_WIREDANDALTPULLUP            (_GPIO_P_MODEL_MODE1_WIREDANDALTPULLUP << 4)        /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE1_WIREDANDALTPULLUPFILTER      (_GPIO_P_MODEL_MODE1_WIREDANDALTPULLUPFILTER << 4)  /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE2_SHIFT                       8                                                   /**< Shift value for GPIO_MODE2 */
+#define _GPIO_P_MODEL_MODE2_MASK                        0xF00UL                                             /**< Bit mask for GPIO_MODE2 */
+#define _GPIO_P_MODEL_MODE2_DEFAULT                     0x00000000UL                                        /**< Mode DEFAULT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE2_DISABLED                    0x00000000UL                                        /**< Mode DISABLED for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE2_INPUT                       0x00000001UL                                        /**< Mode INPUT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE2_INPUTPULL                   0x00000002UL                                        /**< Mode INPUTPULL for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE2_INPUTPULLFILTER             0x00000003UL                                        /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE2_PUSHPULL                    0x00000004UL                                        /**< Mode PUSHPULL for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE2_PUSHPULLALT                 0x00000005UL                                        /**< Mode PUSHPULLALT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE2_WIREDOR                     0x00000006UL                                        /**< Mode WIREDOR for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE2_WIREDORPULLDOWN             0x00000007UL                                        /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE2_WIREDAND                    0x00000008UL                                        /**< Mode WIREDAND for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE2_WIREDANDFILTER              0x00000009UL                                        /**< Mode WIREDANDFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE2_WIREDANDPULLUP              0x0000000AUL                                        /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER        0x0000000BUL                                        /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE2_WIREDANDALT                 0x0000000CUL                                        /**< Mode WIREDANDALT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE2_WIREDANDALTFILTER           0x0000000DUL                                        /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE2_WIREDANDALTPULLUP           0x0000000EUL                                        /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE2_WIREDANDALTPULLUPFILTER     0x0000000FUL                                        /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE2_DEFAULT                      (_GPIO_P_MODEL_MODE2_DEFAULT << 8)                  /**< Shifted mode DEFAULT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE2_DISABLED                     (_GPIO_P_MODEL_MODE2_DISABLED << 8)                 /**< Shifted mode DISABLED for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE2_INPUT                        (_GPIO_P_MODEL_MODE2_INPUT << 8)                    /**< Shifted mode INPUT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE2_INPUTPULL                    (_GPIO_P_MODEL_MODE2_INPUTPULL << 8)                /**< Shifted mode INPUTPULL for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE2_INPUTPULLFILTER              (_GPIO_P_MODEL_MODE2_INPUTPULLFILTER << 8)          /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE2_PUSHPULL                     (_GPIO_P_MODEL_MODE2_PUSHPULL << 8)                 /**< Shifted mode PUSHPULL for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE2_PUSHPULLALT                  (_GPIO_P_MODEL_MODE2_PUSHPULLALT << 8)              /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE2_WIREDOR                      (_GPIO_P_MODEL_MODE2_WIREDOR << 8)                  /**< Shifted mode WIREDOR for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE2_WIREDORPULLDOWN              (_GPIO_P_MODEL_MODE2_WIREDORPULLDOWN << 8)          /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE2_WIREDAND                     (_GPIO_P_MODEL_MODE2_WIREDAND << 8)                 /**< Shifted mode WIREDAND for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE2_WIREDANDFILTER               (_GPIO_P_MODEL_MODE2_WIREDANDFILTER << 8)           /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE2_WIREDANDPULLUP               (_GPIO_P_MODEL_MODE2_WIREDANDPULLUP << 8)           /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER         (_GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER << 8)     /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE2_WIREDANDALT                  (_GPIO_P_MODEL_MODE2_WIREDANDALT << 8)              /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE2_WIREDANDALTFILTER            (_GPIO_P_MODEL_MODE2_WIREDANDALTFILTER << 8)        /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE2_WIREDANDALTPULLUP            (_GPIO_P_MODEL_MODE2_WIREDANDALTPULLUP << 8)        /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE2_WIREDANDALTPULLUPFILTER      (_GPIO_P_MODEL_MODE2_WIREDANDALTPULLUPFILTER << 8)  /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE3_SHIFT                       12                                                  /**< Shift value for GPIO_MODE3 */
+#define _GPIO_P_MODEL_MODE3_MASK                        0xF000UL                                            /**< Bit mask for GPIO_MODE3 */
+#define _GPIO_P_MODEL_MODE3_DEFAULT                     0x00000000UL                                        /**< Mode DEFAULT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE3_DISABLED                    0x00000000UL                                        /**< Mode DISABLED for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE3_INPUT                       0x00000001UL                                        /**< Mode INPUT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE3_INPUTPULL                   0x00000002UL                                        /**< Mode INPUTPULL for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE3_INPUTPULLFILTER             0x00000003UL                                        /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE3_PUSHPULL                    0x00000004UL                                        /**< Mode PUSHPULL for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE3_PUSHPULLALT                 0x00000005UL                                        /**< Mode PUSHPULLALT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE3_WIREDOR                     0x00000006UL                                        /**< Mode WIREDOR for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE3_WIREDORPULLDOWN             0x00000007UL                                        /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE3_WIREDAND                    0x00000008UL                                        /**< Mode WIREDAND for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE3_WIREDANDFILTER              0x00000009UL                                        /**< Mode WIREDANDFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE3_WIREDANDPULLUP              0x0000000AUL                                        /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER        0x0000000BUL                                        /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE3_WIREDANDALT                 0x0000000CUL                                        /**< Mode WIREDANDALT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE3_WIREDANDALTFILTER           0x0000000DUL                                        /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE3_WIREDANDALTPULLUP           0x0000000EUL                                        /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE3_WIREDANDALTPULLUPFILTER     0x0000000FUL                                        /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE3_DEFAULT                      (_GPIO_P_MODEL_MODE3_DEFAULT << 12)                 /**< Shifted mode DEFAULT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE3_DISABLED                     (_GPIO_P_MODEL_MODE3_DISABLED << 12)                /**< Shifted mode DISABLED for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE3_INPUT                        (_GPIO_P_MODEL_MODE3_INPUT << 12)                   /**< Shifted mode INPUT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE3_INPUTPULL                    (_GPIO_P_MODEL_MODE3_INPUTPULL << 12)               /**< Shifted mode INPUTPULL for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE3_INPUTPULLFILTER              (_GPIO_P_MODEL_MODE3_INPUTPULLFILTER << 12)         /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE3_PUSHPULL                     (_GPIO_P_MODEL_MODE3_PUSHPULL << 12)                /**< Shifted mode PUSHPULL for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE3_PUSHPULLALT                  (_GPIO_P_MODEL_MODE3_PUSHPULLALT << 12)             /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE3_WIREDOR                      (_GPIO_P_MODEL_MODE3_WIREDOR << 12)                 /**< Shifted mode WIREDOR for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE3_WIREDORPULLDOWN              (_GPIO_P_MODEL_MODE3_WIREDORPULLDOWN << 12)         /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE3_WIREDAND                     (_GPIO_P_MODEL_MODE3_WIREDAND << 12)                /**< Shifted mode WIREDAND for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE3_WIREDANDFILTER               (_GPIO_P_MODEL_MODE3_WIREDANDFILTER << 12)          /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE3_WIREDANDPULLUP               (_GPIO_P_MODEL_MODE3_WIREDANDPULLUP << 12)          /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER         (_GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER << 12)    /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE3_WIREDANDALT                  (_GPIO_P_MODEL_MODE3_WIREDANDALT << 12)             /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE3_WIREDANDALTFILTER            (_GPIO_P_MODEL_MODE3_WIREDANDALTFILTER << 12)       /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE3_WIREDANDALTPULLUP            (_GPIO_P_MODEL_MODE3_WIREDANDALTPULLUP << 12)       /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE3_WIREDANDALTPULLUPFILTER      (_GPIO_P_MODEL_MODE3_WIREDANDALTPULLUPFILTER << 12) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE4_SHIFT                       16                                                  /**< Shift value for GPIO_MODE4 */
+#define _GPIO_P_MODEL_MODE4_MASK                        0xF0000UL                                           /**< Bit mask for GPIO_MODE4 */
+#define _GPIO_P_MODEL_MODE4_DEFAULT                     0x00000000UL                                        /**< Mode DEFAULT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE4_DISABLED                    0x00000000UL                                        /**< Mode DISABLED for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE4_INPUT                       0x00000001UL                                        /**< Mode INPUT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE4_INPUTPULL                   0x00000002UL                                        /**< Mode INPUTPULL for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE4_INPUTPULLFILTER             0x00000003UL                                        /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE4_PUSHPULL                    0x00000004UL                                        /**< Mode PUSHPULL for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE4_PUSHPULLALT                 0x00000005UL                                        /**< Mode PUSHPULLALT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE4_WIREDOR                     0x00000006UL                                        /**< Mode WIREDOR for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE4_WIREDORPULLDOWN             0x00000007UL                                        /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE4_WIREDAND                    0x00000008UL                                        /**< Mode WIREDAND for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE4_WIREDANDFILTER              0x00000009UL                                        /**< Mode WIREDANDFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE4_WIREDANDPULLUP              0x0000000AUL                                        /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER        0x0000000BUL                                        /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE4_WIREDANDALT                 0x0000000CUL                                        /**< Mode WIREDANDALT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE4_WIREDANDALTFILTER           0x0000000DUL                                        /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE4_WIREDANDALTPULLUP           0x0000000EUL                                        /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE4_WIREDANDALTPULLUPFILTER     0x0000000FUL                                        /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE4_DEFAULT                      (_GPIO_P_MODEL_MODE4_DEFAULT << 16)                 /**< Shifted mode DEFAULT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE4_DISABLED                     (_GPIO_P_MODEL_MODE4_DISABLED << 16)                /**< Shifted mode DISABLED for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE4_INPUT                        (_GPIO_P_MODEL_MODE4_INPUT << 16)                   /**< Shifted mode INPUT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE4_INPUTPULL                    (_GPIO_P_MODEL_MODE4_INPUTPULL << 16)               /**< Shifted mode INPUTPULL for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE4_INPUTPULLFILTER              (_GPIO_P_MODEL_MODE4_INPUTPULLFILTER << 16)         /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE4_PUSHPULL                     (_GPIO_P_MODEL_MODE4_PUSHPULL << 16)                /**< Shifted mode PUSHPULL for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE4_PUSHPULLALT                  (_GPIO_P_MODEL_MODE4_PUSHPULLALT << 16)             /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE4_WIREDOR                      (_GPIO_P_MODEL_MODE4_WIREDOR << 16)                 /**< Shifted mode WIREDOR for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE4_WIREDORPULLDOWN              (_GPIO_P_MODEL_MODE4_WIREDORPULLDOWN << 16)         /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE4_WIREDAND                     (_GPIO_P_MODEL_MODE4_WIREDAND << 16)                /**< Shifted mode WIREDAND for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE4_WIREDANDFILTER               (_GPIO_P_MODEL_MODE4_WIREDANDFILTER << 16)          /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE4_WIREDANDPULLUP               (_GPIO_P_MODEL_MODE4_WIREDANDPULLUP << 16)          /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER         (_GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER << 16)    /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE4_WIREDANDALT                  (_GPIO_P_MODEL_MODE4_WIREDANDALT << 16)             /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE4_WIREDANDALTFILTER            (_GPIO_P_MODEL_MODE4_WIREDANDALTFILTER << 16)       /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE4_WIREDANDALTPULLUP            (_GPIO_P_MODEL_MODE4_WIREDANDALTPULLUP << 16)       /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE4_WIREDANDALTPULLUPFILTER      (_GPIO_P_MODEL_MODE4_WIREDANDALTPULLUPFILTER << 16) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE5_SHIFT                       20                                                  /**< Shift value for GPIO_MODE5 */
+#define _GPIO_P_MODEL_MODE5_MASK                        0xF00000UL                                          /**< Bit mask for GPIO_MODE5 */
+#define _GPIO_P_MODEL_MODE5_DEFAULT                     0x00000000UL                                        /**< Mode DEFAULT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE5_DISABLED                    0x00000000UL                                        /**< Mode DISABLED for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE5_INPUT                       0x00000001UL                                        /**< Mode INPUT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE5_INPUTPULL                   0x00000002UL                                        /**< Mode INPUTPULL for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE5_INPUTPULLFILTER             0x00000003UL                                        /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE5_PUSHPULL                    0x00000004UL                                        /**< Mode PUSHPULL for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE5_PUSHPULLALT                 0x00000005UL                                        /**< Mode PUSHPULLALT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE5_WIREDOR                     0x00000006UL                                        /**< Mode WIREDOR for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE5_WIREDORPULLDOWN             0x00000007UL                                        /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE5_WIREDAND                    0x00000008UL                                        /**< Mode WIREDAND for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE5_WIREDANDFILTER              0x00000009UL                                        /**< Mode WIREDANDFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE5_WIREDANDPULLUP              0x0000000AUL                                        /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER        0x0000000BUL                                        /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE5_WIREDANDALT                 0x0000000CUL                                        /**< Mode WIREDANDALT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE5_WIREDANDALTFILTER           0x0000000DUL                                        /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE5_WIREDANDALTPULLUP           0x0000000EUL                                        /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE5_WIREDANDALTPULLUPFILTER     0x0000000FUL                                        /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE5_DEFAULT                      (_GPIO_P_MODEL_MODE5_DEFAULT << 20)                 /**< Shifted mode DEFAULT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE5_DISABLED                     (_GPIO_P_MODEL_MODE5_DISABLED << 20)                /**< Shifted mode DISABLED for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE5_INPUT                        (_GPIO_P_MODEL_MODE5_INPUT << 20)                   /**< Shifted mode INPUT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE5_INPUTPULL                    (_GPIO_P_MODEL_MODE5_INPUTPULL << 20)               /**< Shifted mode INPUTPULL for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE5_INPUTPULLFILTER              (_GPIO_P_MODEL_MODE5_INPUTPULLFILTER << 20)         /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE5_PUSHPULL                     (_GPIO_P_MODEL_MODE5_PUSHPULL << 20)                /**< Shifted mode PUSHPULL for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE5_PUSHPULLALT                  (_GPIO_P_MODEL_MODE5_PUSHPULLALT << 20)             /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE5_WIREDOR                      (_GPIO_P_MODEL_MODE5_WIREDOR << 20)                 /**< Shifted mode WIREDOR for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE5_WIREDORPULLDOWN              (_GPIO_P_MODEL_MODE5_WIREDORPULLDOWN << 20)         /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE5_WIREDAND                     (_GPIO_P_MODEL_MODE5_WIREDAND << 20)                /**< Shifted mode WIREDAND for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE5_WIREDANDFILTER               (_GPIO_P_MODEL_MODE5_WIREDANDFILTER << 20)          /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE5_WIREDANDPULLUP               (_GPIO_P_MODEL_MODE5_WIREDANDPULLUP << 20)          /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER         (_GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER << 20)    /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE5_WIREDANDALT                  (_GPIO_P_MODEL_MODE5_WIREDANDALT << 20)             /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE5_WIREDANDALTFILTER            (_GPIO_P_MODEL_MODE5_WIREDANDALTFILTER << 20)       /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE5_WIREDANDALTPULLUP            (_GPIO_P_MODEL_MODE5_WIREDANDALTPULLUP << 20)       /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE5_WIREDANDALTPULLUPFILTER      (_GPIO_P_MODEL_MODE5_WIREDANDALTPULLUPFILTER << 20) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE6_SHIFT                       24                                                  /**< Shift value for GPIO_MODE6 */
+#define _GPIO_P_MODEL_MODE6_MASK                        0xF000000UL                                         /**< Bit mask for GPIO_MODE6 */
+#define _GPIO_P_MODEL_MODE6_DEFAULT                     0x00000000UL                                        /**< Mode DEFAULT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE6_DISABLED                    0x00000000UL                                        /**< Mode DISABLED for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE6_INPUT                       0x00000001UL                                        /**< Mode INPUT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE6_INPUTPULL                   0x00000002UL                                        /**< Mode INPUTPULL for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE6_INPUTPULLFILTER             0x00000003UL                                        /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE6_PUSHPULL                    0x00000004UL                                        /**< Mode PUSHPULL for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE6_PUSHPULLALT                 0x00000005UL                                        /**< Mode PUSHPULLALT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE6_WIREDOR                     0x00000006UL                                        /**< Mode WIREDOR for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE6_WIREDORPULLDOWN             0x00000007UL                                        /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE6_WIREDAND                    0x00000008UL                                        /**< Mode WIREDAND for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE6_WIREDANDFILTER              0x00000009UL                                        /**< Mode WIREDANDFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE6_WIREDANDPULLUP              0x0000000AUL                                        /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER        0x0000000BUL                                        /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE6_WIREDANDALT                 0x0000000CUL                                        /**< Mode WIREDANDALT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE6_WIREDANDALTFILTER           0x0000000DUL                                        /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE6_WIREDANDALTPULLUP           0x0000000EUL                                        /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE6_WIREDANDALTPULLUPFILTER     0x0000000FUL                                        /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE6_DEFAULT                      (_GPIO_P_MODEL_MODE6_DEFAULT << 24)                 /**< Shifted mode DEFAULT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE6_DISABLED                     (_GPIO_P_MODEL_MODE6_DISABLED << 24)                /**< Shifted mode DISABLED for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE6_INPUT                        (_GPIO_P_MODEL_MODE6_INPUT << 24)                   /**< Shifted mode INPUT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE6_INPUTPULL                    (_GPIO_P_MODEL_MODE6_INPUTPULL << 24)               /**< Shifted mode INPUTPULL for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE6_INPUTPULLFILTER              (_GPIO_P_MODEL_MODE6_INPUTPULLFILTER << 24)         /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE6_PUSHPULL                     (_GPIO_P_MODEL_MODE6_PUSHPULL << 24)                /**< Shifted mode PUSHPULL for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE6_PUSHPULLALT                  (_GPIO_P_MODEL_MODE6_PUSHPULLALT << 24)             /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE6_WIREDOR                      (_GPIO_P_MODEL_MODE6_WIREDOR << 24)                 /**< Shifted mode WIREDOR for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE6_WIREDORPULLDOWN              (_GPIO_P_MODEL_MODE6_WIREDORPULLDOWN << 24)         /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE6_WIREDAND                     (_GPIO_P_MODEL_MODE6_WIREDAND << 24)                /**< Shifted mode WIREDAND for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE6_WIREDANDFILTER               (_GPIO_P_MODEL_MODE6_WIREDANDFILTER << 24)          /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE6_WIREDANDPULLUP               (_GPIO_P_MODEL_MODE6_WIREDANDPULLUP << 24)          /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER         (_GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER << 24)    /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE6_WIREDANDALT                  (_GPIO_P_MODEL_MODE6_WIREDANDALT << 24)             /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE6_WIREDANDALTFILTER            (_GPIO_P_MODEL_MODE6_WIREDANDALTFILTER << 24)       /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE6_WIREDANDALTPULLUP            (_GPIO_P_MODEL_MODE6_WIREDANDALTPULLUP << 24)       /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE6_WIREDANDALTPULLUPFILTER      (_GPIO_P_MODEL_MODE6_WIREDANDALTPULLUPFILTER << 24) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE7_SHIFT                       28                                                  /**< Shift value for GPIO_MODE7 */
+#define _GPIO_P_MODEL_MODE7_MASK                        0xF0000000UL                                        /**< Bit mask for GPIO_MODE7 */
+#define _GPIO_P_MODEL_MODE7_DEFAULT                     0x00000000UL                                        /**< Mode DEFAULT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE7_DISABLED                    0x00000000UL                                        /**< Mode DISABLED for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE7_INPUT                       0x00000001UL                                        /**< Mode INPUT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE7_INPUTPULL                   0x00000002UL                                        /**< Mode INPUTPULL for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE7_INPUTPULLFILTER             0x00000003UL                                        /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE7_PUSHPULL                    0x00000004UL                                        /**< Mode PUSHPULL for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE7_PUSHPULLALT                 0x00000005UL                                        /**< Mode PUSHPULLALT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE7_WIREDOR                     0x00000006UL                                        /**< Mode WIREDOR for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE7_WIREDORPULLDOWN             0x00000007UL                                        /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE7_WIREDAND                    0x00000008UL                                        /**< Mode WIREDAND for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE7_WIREDANDFILTER              0x00000009UL                                        /**< Mode WIREDANDFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE7_WIREDANDPULLUP              0x0000000AUL                                        /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER        0x0000000BUL                                        /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE7_WIREDANDALT                 0x0000000CUL                                        /**< Mode WIREDANDALT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE7_WIREDANDALTFILTER           0x0000000DUL                                        /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE7_WIREDANDALTPULLUP           0x0000000EUL                                        /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE7_WIREDANDALTPULLUPFILTER     0x0000000FUL                                        /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE7_DEFAULT                      (_GPIO_P_MODEL_MODE7_DEFAULT << 28)                 /**< Shifted mode DEFAULT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE7_DISABLED                     (_GPIO_P_MODEL_MODE7_DISABLED << 28)                /**< Shifted mode DISABLED for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE7_INPUT                        (_GPIO_P_MODEL_MODE7_INPUT << 28)                   /**< Shifted mode INPUT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE7_INPUTPULL                    (_GPIO_P_MODEL_MODE7_INPUTPULL << 28)               /**< Shifted mode INPUTPULL for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE7_INPUTPULLFILTER              (_GPIO_P_MODEL_MODE7_INPUTPULLFILTER << 28)         /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE7_PUSHPULL                     (_GPIO_P_MODEL_MODE7_PUSHPULL << 28)                /**< Shifted mode PUSHPULL for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE7_PUSHPULLALT                  (_GPIO_P_MODEL_MODE7_PUSHPULLALT << 28)             /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE7_WIREDOR                      (_GPIO_P_MODEL_MODE7_WIREDOR << 28)                 /**< Shifted mode WIREDOR for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE7_WIREDORPULLDOWN              (_GPIO_P_MODEL_MODE7_WIREDORPULLDOWN << 28)         /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE7_WIREDAND                     (_GPIO_P_MODEL_MODE7_WIREDAND << 28)                /**< Shifted mode WIREDAND for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE7_WIREDANDFILTER               (_GPIO_P_MODEL_MODE7_WIREDANDFILTER << 28)          /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE7_WIREDANDPULLUP               (_GPIO_P_MODEL_MODE7_WIREDANDPULLUP << 28)          /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER         (_GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER << 28)    /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE7_WIREDANDALT                  (_GPIO_P_MODEL_MODE7_WIREDANDALT << 28)             /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE7_WIREDANDALTFILTER            (_GPIO_P_MODEL_MODE7_WIREDANDALTFILTER << 28)       /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE7_WIREDANDALTPULLUP            (_GPIO_P_MODEL_MODE7_WIREDANDALTPULLUP << 28)       /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE7_WIREDANDALTPULLUPFILTER      (_GPIO_P_MODEL_MODE7_WIREDANDALTPULLUPFILTER << 28) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */
+
+/* Bit fields for GPIO P_MODEH */
+#define _GPIO_P_MODEH_RESETVALUE                        0x00000000UL                                         /**< Default value for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MASK                              0xFFFFFFFFUL                                         /**< Mask for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE8_SHIFT                       0                                                    /**< Shift value for GPIO_MODE8 */
+#define _GPIO_P_MODEH_MODE8_MASK                        0xFUL                                                /**< Bit mask for GPIO_MODE8 */
+#define _GPIO_P_MODEH_MODE8_DEFAULT                     0x00000000UL                                         /**< Mode DEFAULT for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE8_DISABLED                    0x00000000UL                                         /**< Mode DISABLED for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE8_INPUT                       0x00000001UL                                         /**< Mode INPUT for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE8_INPUTPULL                   0x00000002UL                                         /**< Mode INPUTPULL for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE8_INPUTPULLFILTER             0x00000003UL                                         /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE8_PUSHPULL                    0x00000004UL                                         /**< Mode PUSHPULL for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE8_PUSHPULLALT                 0x00000005UL                                         /**< Mode PUSHPULLALT for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE8_WIREDOR                     0x00000006UL                                         /**< Mode WIREDOR for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE8_WIREDORPULLDOWN             0x00000007UL                                         /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE8_WIREDAND                    0x00000008UL                                         /**< Mode WIREDAND for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE8_WIREDANDFILTER              0x00000009UL                                         /**< Mode WIREDANDFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE8_WIREDANDPULLUP              0x0000000AUL                                         /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE8_WIREDANDPULLUPFILTER        0x0000000BUL                                         /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE8_WIREDANDALT                 0x0000000CUL                                         /**< Mode WIREDANDALT for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE8_WIREDANDALTFILTER           0x0000000DUL                                         /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE8_WIREDANDALTPULLUP           0x0000000EUL                                         /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE8_WIREDANDALTPULLUPFILTER     0x0000000FUL                                         /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE8_DEFAULT                      (_GPIO_P_MODEH_MODE8_DEFAULT << 0)                   /**< Shifted mode DEFAULT for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE8_DISABLED                     (_GPIO_P_MODEH_MODE8_DISABLED << 0)                  /**< Shifted mode DISABLED for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE8_INPUT                        (_GPIO_P_MODEH_MODE8_INPUT << 0)                     /**< Shifted mode INPUT for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE8_INPUTPULL                    (_GPIO_P_MODEH_MODE8_INPUTPULL << 0)                 /**< Shifted mode INPUTPULL for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE8_INPUTPULLFILTER              (_GPIO_P_MODEH_MODE8_INPUTPULLFILTER << 0)           /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE8_PUSHPULL                     (_GPIO_P_MODEH_MODE8_PUSHPULL << 0)                  /**< Shifted mode PUSHPULL for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE8_PUSHPULLALT                  (_GPIO_P_MODEH_MODE8_PUSHPULLALT << 0)               /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE8_WIREDOR                      (_GPIO_P_MODEH_MODE8_WIREDOR << 0)                   /**< Shifted mode WIREDOR for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE8_WIREDORPULLDOWN              (_GPIO_P_MODEH_MODE8_WIREDORPULLDOWN << 0)           /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE8_WIREDAND                     (_GPIO_P_MODEH_MODE8_WIREDAND << 0)                  /**< Shifted mode WIREDAND for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE8_WIREDANDFILTER               (_GPIO_P_MODEH_MODE8_WIREDANDFILTER << 0)            /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE8_WIREDANDPULLUP               (_GPIO_P_MODEH_MODE8_WIREDANDPULLUP << 0)            /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE8_WIREDANDPULLUPFILTER         (_GPIO_P_MODEH_MODE8_WIREDANDPULLUPFILTER << 0)      /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE8_WIREDANDALT                  (_GPIO_P_MODEH_MODE8_WIREDANDALT << 0)               /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE8_WIREDANDALTFILTER            (_GPIO_P_MODEH_MODE8_WIREDANDALTFILTER << 0)         /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE8_WIREDANDALTPULLUP            (_GPIO_P_MODEH_MODE8_WIREDANDALTPULLUP << 0)         /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE8_WIREDANDALTPULLUPFILTER      (_GPIO_P_MODEH_MODE8_WIREDANDALTPULLUPFILTER << 0)   /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE9_SHIFT                       4                                                    /**< Shift value for GPIO_MODE9 */
+#define _GPIO_P_MODEH_MODE9_MASK                        0xF0UL                                               /**< Bit mask for GPIO_MODE9 */
+#define _GPIO_P_MODEH_MODE9_DEFAULT                     0x00000000UL                                         /**< Mode DEFAULT for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE9_DISABLED                    0x00000000UL                                         /**< Mode DISABLED for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE9_INPUT                       0x00000001UL                                         /**< Mode INPUT for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE9_INPUTPULL                   0x00000002UL                                         /**< Mode INPUTPULL for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE9_INPUTPULLFILTER             0x00000003UL                                         /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE9_PUSHPULL                    0x00000004UL                                         /**< Mode PUSHPULL for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE9_PUSHPULLALT                 0x00000005UL                                         /**< Mode PUSHPULLALT for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE9_WIREDOR                     0x00000006UL                                         /**< Mode WIREDOR for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE9_WIREDORPULLDOWN             0x00000007UL                                         /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE9_WIREDAND                    0x00000008UL                                         /**< Mode WIREDAND for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE9_WIREDANDFILTER              0x00000009UL                                         /**< Mode WIREDANDFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE9_WIREDANDPULLUP              0x0000000AUL                                         /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE9_WIREDANDPULLUPFILTER        0x0000000BUL                                         /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE9_WIREDANDALT                 0x0000000CUL                                         /**< Mode WIREDANDALT for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE9_WIREDANDALTFILTER           0x0000000DUL                                         /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE9_WIREDANDALTPULLUP           0x0000000EUL                                         /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE9_WIREDANDALTPULLUPFILTER     0x0000000FUL                                         /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE9_DEFAULT                      (_GPIO_P_MODEH_MODE9_DEFAULT << 4)                   /**< Shifted mode DEFAULT for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE9_DISABLED                     (_GPIO_P_MODEH_MODE9_DISABLED << 4)                  /**< Shifted mode DISABLED for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE9_INPUT                        (_GPIO_P_MODEH_MODE9_INPUT << 4)                     /**< Shifted mode INPUT for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE9_INPUTPULL                    (_GPIO_P_MODEH_MODE9_INPUTPULL << 4)                 /**< Shifted mode INPUTPULL for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE9_INPUTPULLFILTER              (_GPIO_P_MODEH_MODE9_INPUTPULLFILTER << 4)           /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE9_PUSHPULL                     (_GPIO_P_MODEH_MODE9_PUSHPULL << 4)                  /**< Shifted mode PUSHPULL for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE9_PUSHPULLALT                  (_GPIO_P_MODEH_MODE9_PUSHPULLALT << 4)               /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE9_WIREDOR                      (_GPIO_P_MODEH_MODE9_WIREDOR << 4)                   /**< Shifted mode WIREDOR for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE9_WIREDORPULLDOWN              (_GPIO_P_MODEH_MODE9_WIREDORPULLDOWN << 4)           /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE9_WIREDAND                     (_GPIO_P_MODEH_MODE9_WIREDAND << 4)                  /**< Shifted mode WIREDAND for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE9_WIREDANDFILTER               (_GPIO_P_MODEH_MODE9_WIREDANDFILTER << 4)            /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE9_WIREDANDPULLUP               (_GPIO_P_MODEH_MODE9_WIREDANDPULLUP << 4)            /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE9_WIREDANDPULLUPFILTER         (_GPIO_P_MODEH_MODE9_WIREDANDPULLUPFILTER << 4)      /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE9_WIREDANDALT                  (_GPIO_P_MODEH_MODE9_WIREDANDALT << 4)               /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE9_WIREDANDALTFILTER            (_GPIO_P_MODEH_MODE9_WIREDANDALTFILTER << 4)         /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE9_WIREDANDALTPULLUP            (_GPIO_P_MODEH_MODE9_WIREDANDALTPULLUP << 4)         /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE9_WIREDANDALTPULLUPFILTER      (_GPIO_P_MODEH_MODE9_WIREDANDALTPULLUPFILTER << 4)   /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE10_SHIFT                      8                                                    /**< Shift value for GPIO_MODE10 */
+#define _GPIO_P_MODEH_MODE10_MASK                       0xF00UL                                              /**< Bit mask for GPIO_MODE10 */
+#define _GPIO_P_MODEH_MODE10_DEFAULT                    0x00000000UL                                         /**< Mode DEFAULT for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE10_DISABLED                   0x00000000UL                                         /**< Mode DISABLED for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE10_INPUT                      0x00000001UL                                         /**< Mode INPUT for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE10_INPUTPULL                  0x00000002UL                                         /**< Mode INPUTPULL for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE10_INPUTPULLFILTER            0x00000003UL                                         /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE10_PUSHPULL                   0x00000004UL                                         /**< Mode PUSHPULL for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE10_PUSHPULLALT                0x00000005UL                                         /**< Mode PUSHPULLALT for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE10_WIREDOR                    0x00000006UL                                         /**< Mode WIREDOR for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE10_WIREDORPULLDOWN            0x00000007UL                                         /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE10_WIREDAND                   0x00000008UL                                         /**< Mode WIREDAND for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE10_WIREDANDFILTER             0x00000009UL                                         /**< Mode WIREDANDFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE10_WIREDANDPULLUP             0x0000000AUL                                         /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE10_WIREDANDPULLUPFILTER       0x0000000BUL                                         /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE10_WIREDANDALT                0x0000000CUL                                         /**< Mode WIREDANDALT for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE10_WIREDANDALTFILTER          0x0000000DUL                                         /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE10_WIREDANDALTPULLUP          0x0000000EUL                                         /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE10_WIREDANDALTPULLUPFILTER    0x0000000FUL                                         /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE10_DEFAULT                     (_GPIO_P_MODEH_MODE10_DEFAULT << 8)                  /**< Shifted mode DEFAULT for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE10_DISABLED                    (_GPIO_P_MODEH_MODE10_DISABLED << 8)                 /**< Shifted mode DISABLED for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE10_INPUT                       (_GPIO_P_MODEH_MODE10_INPUT << 8)                    /**< Shifted mode INPUT for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE10_INPUTPULL                   (_GPIO_P_MODEH_MODE10_INPUTPULL << 8)                /**< Shifted mode INPUTPULL for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE10_INPUTPULLFILTER             (_GPIO_P_MODEH_MODE10_INPUTPULLFILTER << 8)          /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE10_PUSHPULL                    (_GPIO_P_MODEH_MODE10_PUSHPULL << 8)                 /**< Shifted mode PUSHPULL for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE10_PUSHPULLALT                 (_GPIO_P_MODEH_MODE10_PUSHPULLALT << 8)              /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE10_WIREDOR                     (_GPIO_P_MODEH_MODE10_WIREDOR << 8)                  /**< Shifted mode WIREDOR for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE10_WIREDORPULLDOWN             (_GPIO_P_MODEH_MODE10_WIREDORPULLDOWN << 8)          /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE10_WIREDAND                    (_GPIO_P_MODEH_MODE10_WIREDAND << 8)                 /**< Shifted mode WIREDAND for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE10_WIREDANDFILTER              (_GPIO_P_MODEH_MODE10_WIREDANDFILTER << 8)           /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE10_WIREDANDPULLUP              (_GPIO_P_MODEH_MODE10_WIREDANDPULLUP << 8)           /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE10_WIREDANDPULLUPFILTER        (_GPIO_P_MODEH_MODE10_WIREDANDPULLUPFILTER << 8)     /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE10_WIREDANDALT                 (_GPIO_P_MODEH_MODE10_WIREDANDALT << 8)              /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE10_WIREDANDALTFILTER           (_GPIO_P_MODEH_MODE10_WIREDANDALTFILTER << 8)        /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE10_WIREDANDALTPULLUP           (_GPIO_P_MODEH_MODE10_WIREDANDALTPULLUP << 8)        /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE10_WIREDANDALTPULLUPFILTER     (_GPIO_P_MODEH_MODE10_WIREDANDALTPULLUPFILTER << 8)  /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE11_SHIFT                      12                                                   /**< Shift value for GPIO_MODE11 */
+#define _GPIO_P_MODEH_MODE11_MASK                       0xF000UL                                             /**< Bit mask for GPIO_MODE11 */
+#define _GPIO_P_MODEH_MODE11_DEFAULT                    0x00000000UL                                         /**< Mode DEFAULT for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE11_DISABLED                   0x00000000UL                                         /**< Mode DISABLED for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE11_INPUT                      0x00000001UL                                         /**< Mode INPUT for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE11_INPUTPULL                  0x00000002UL                                         /**< Mode INPUTPULL for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE11_INPUTPULLFILTER            0x00000003UL                                         /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE11_PUSHPULL                   0x00000004UL                                         /**< Mode PUSHPULL for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE11_PUSHPULLALT                0x00000005UL                                         /**< Mode PUSHPULLALT for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE11_WIREDOR                    0x00000006UL                                         /**< Mode WIREDOR for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE11_WIREDORPULLDOWN            0x00000007UL                                         /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE11_WIREDAND                   0x00000008UL                                         /**< Mode WIREDAND for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE11_WIREDANDFILTER             0x00000009UL                                         /**< Mode WIREDANDFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE11_WIREDANDPULLUP             0x0000000AUL                                         /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE11_WIREDANDPULLUPFILTER       0x0000000BUL                                         /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE11_WIREDANDALT                0x0000000CUL                                         /**< Mode WIREDANDALT for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE11_WIREDANDALTFILTER          0x0000000DUL                                         /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE11_WIREDANDALTPULLUP          0x0000000EUL                                         /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE11_WIREDANDALTPULLUPFILTER    0x0000000FUL                                         /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE11_DEFAULT                     (_GPIO_P_MODEH_MODE11_DEFAULT << 12)                 /**< Shifted mode DEFAULT for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE11_DISABLED                    (_GPIO_P_MODEH_MODE11_DISABLED << 12)                /**< Shifted mode DISABLED for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE11_INPUT                       (_GPIO_P_MODEH_MODE11_INPUT << 12)                   /**< Shifted mode INPUT for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE11_INPUTPULL                   (_GPIO_P_MODEH_MODE11_INPUTPULL << 12)               /**< Shifted mode INPUTPULL for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE11_INPUTPULLFILTER             (_GPIO_P_MODEH_MODE11_INPUTPULLFILTER << 12)         /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE11_PUSHPULL                    (_GPIO_P_MODEH_MODE11_PUSHPULL << 12)                /**< Shifted mode PUSHPULL for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE11_PUSHPULLALT                 (_GPIO_P_MODEH_MODE11_PUSHPULLALT << 12)             /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE11_WIREDOR                     (_GPIO_P_MODEH_MODE11_WIREDOR << 12)                 /**< Shifted mode WIREDOR for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE11_WIREDORPULLDOWN             (_GPIO_P_MODEH_MODE11_WIREDORPULLDOWN << 12)         /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE11_WIREDAND                    (_GPIO_P_MODEH_MODE11_WIREDAND << 12)                /**< Shifted mode WIREDAND for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE11_WIREDANDFILTER              (_GPIO_P_MODEH_MODE11_WIREDANDFILTER << 12)          /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE11_WIREDANDPULLUP              (_GPIO_P_MODEH_MODE11_WIREDANDPULLUP << 12)          /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE11_WIREDANDPULLUPFILTER        (_GPIO_P_MODEH_MODE11_WIREDANDPULLUPFILTER << 12)    /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE11_WIREDANDALT                 (_GPIO_P_MODEH_MODE11_WIREDANDALT << 12)             /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE11_WIREDANDALTFILTER           (_GPIO_P_MODEH_MODE11_WIREDANDALTFILTER << 12)       /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE11_WIREDANDALTPULLUP           (_GPIO_P_MODEH_MODE11_WIREDANDALTPULLUP << 12)       /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE11_WIREDANDALTPULLUPFILTER     (_GPIO_P_MODEH_MODE11_WIREDANDALTPULLUPFILTER << 12) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE12_SHIFT                      16                                                   /**< Shift value for GPIO_MODE12 */
+#define _GPIO_P_MODEH_MODE12_MASK                       0xF0000UL                                            /**< Bit mask for GPIO_MODE12 */
+#define _GPIO_P_MODEH_MODE12_DEFAULT                    0x00000000UL                                         /**< Mode DEFAULT for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE12_DISABLED                   0x00000000UL                                         /**< Mode DISABLED for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE12_INPUT                      0x00000001UL                                         /**< Mode INPUT for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE12_INPUTPULL                  0x00000002UL                                         /**< Mode INPUTPULL for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE12_INPUTPULLFILTER            0x00000003UL                                         /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE12_PUSHPULL                   0x00000004UL                                         /**< Mode PUSHPULL for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE12_PUSHPULLALT                0x00000005UL                                         /**< Mode PUSHPULLALT for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE12_WIREDOR                    0x00000006UL                                         /**< Mode WIREDOR for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE12_WIREDORPULLDOWN            0x00000007UL                                         /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE12_WIREDAND                   0x00000008UL                                         /**< Mode WIREDAND for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE12_WIREDANDFILTER             0x00000009UL                                         /**< Mode WIREDANDFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE12_WIREDANDPULLUP             0x0000000AUL                                         /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE12_WIREDANDPULLUPFILTER       0x0000000BUL                                         /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE12_WIREDANDALT                0x0000000CUL                                         /**< Mode WIREDANDALT for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE12_WIREDANDALTFILTER          0x0000000DUL                                         /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE12_WIREDANDALTPULLUP          0x0000000EUL                                         /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE12_WIREDANDALTPULLUPFILTER    0x0000000FUL                                         /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE12_DEFAULT                     (_GPIO_P_MODEH_MODE12_DEFAULT << 16)                 /**< Shifted mode DEFAULT for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE12_DISABLED                    (_GPIO_P_MODEH_MODE12_DISABLED << 16)                /**< Shifted mode DISABLED for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE12_INPUT                       (_GPIO_P_MODEH_MODE12_INPUT << 16)                   /**< Shifted mode INPUT for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE12_INPUTPULL                   (_GPIO_P_MODEH_MODE12_INPUTPULL << 16)               /**< Shifted mode INPUTPULL for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE12_INPUTPULLFILTER             (_GPIO_P_MODEH_MODE12_INPUTPULLFILTER << 16)         /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE12_PUSHPULL                    (_GPIO_P_MODEH_MODE12_PUSHPULL << 16)                /**< Shifted mode PUSHPULL for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE12_PUSHPULLALT                 (_GPIO_P_MODEH_MODE12_PUSHPULLALT << 16)             /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE12_WIREDOR                     (_GPIO_P_MODEH_MODE12_WIREDOR << 16)                 /**< Shifted mode WIREDOR for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE12_WIREDORPULLDOWN             (_GPIO_P_MODEH_MODE12_WIREDORPULLDOWN << 16)         /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE12_WIREDAND                    (_GPIO_P_MODEH_MODE12_WIREDAND << 16)                /**< Shifted mode WIREDAND for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE12_WIREDANDFILTER              (_GPIO_P_MODEH_MODE12_WIREDANDFILTER << 16)          /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE12_WIREDANDPULLUP              (_GPIO_P_MODEH_MODE12_WIREDANDPULLUP << 16)          /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE12_WIREDANDPULLUPFILTER        (_GPIO_P_MODEH_MODE12_WIREDANDPULLUPFILTER << 16)    /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE12_WIREDANDALT                 (_GPIO_P_MODEH_MODE12_WIREDANDALT << 16)             /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE12_WIREDANDALTFILTER           (_GPIO_P_MODEH_MODE12_WIREDANDALTFILTER << 16)       /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE12_WIREDANDALTPULLUP           (_GPIO_P_MODEH_MODE12_WIREDANDALTPULLUP << 16)       /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE12_WIREDANDALTPULLUPFILTER     (_GPIO_P_MODEH_MODE12_WIREDANDALTPULLUPFILTER << 16) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE13_SHIFT                      20                                                   /**< Shift value for GPIO_MODE13 */
+#define _GPIO_P_MODEH_MODE13_MASK                       0xF00000UL                                           /**< Bit mask for GPIO_MODE13 */
+#define _GPIO_P_MODEH_MODE13_DEFAULT                    0x00000000UL                                         /**< Mode DEFAULT for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE13_DISABLED                   0x00000000UL                                         /**< Mode DISABLED for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE13_INPUT                      0x00000001UL                                         /**< Mode INPUT for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE13_INPUTPULL                  0x00000002UL                                         /**< Mode INPUTPULL for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE13_INPUTPULLFILTER            0x00000003UL                                         /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE13_PUSHPULL                   0x00000004UL                                         /**< Mode PUSHPULL for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE13_PUSHPULLALT                0x00000005UL                                         /**< Mode PUSHPULLALT for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE13_WIREDOR                    0x00000006UL                                         /**< Mode WIREDOR for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE13_WIREDORPULLDOWN            0x00000007UL                                         /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE13_WIREDAND                   0x00000008UL                                         /**< Mode WIREDAND for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE13_WIREDANDFILTER             0x00000009UL                                         /**< Mode WIREDANDFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE13_WIREDANDPULLUP             0x0000000AUL                                         /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE13_WIREDANDPULLUPFILTER       0x0000000BUL                                         /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE13_WIREDANDALT                0x0000000CUL                                         /**< Mode WIREDANDALT for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE13_WIREDANDALTFILTER          0x0000000DUL                                         /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE13_WIREDANDALTPULLUP          0x0000000EUL                                         /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE13_WIREDANDALTPULLUPFILTER    0x0000000FUL                                         /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE13_DEFAULT                     (_GPIO_P_MODEH_MODE13_DEFAULT << 20)                 /**< Shifted mode DEFAULT for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE13_DISABLED                    (_GPIO_P_MODEH_MODE13_DISABLED << 20)                /**< Shifted mode DISABLED for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE13_INPUT                       (_GPIO_P_MODEH_MODE13_INPUT << 20)                   /**< Shifted mode INPUT for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE13_INPUTPULL                   (_GPIO_P_MODEH_MODE13_INPUTPULL << 20)               /**< Shifted mode INPUTPULL for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE13_INPUTPULLFILTER             (_GPIO_P_MODEH_MODE13_INPUTPULLFILTER << 20)         /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE13_PUSHPULL                    (_GPIO_P_MODEH_MODE13_PUSHPULL << 20)                /**< Shifted mode PUSHPULL for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE13_PUSHPULLALT                 (_GPIO_P_MODEH_MODE13_PUSHPULLALT << 20)             /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE13_WIREDOR                     (_GPIO_P_MODEH_MODE13_WIREDOR << 20)                 /**< Shifted mode WIREDOR for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE13_WIREDORPULLDOWN             (_GPIO_P_MODEH_MODE13_WIREDORPULLDOWN << 20)         /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE13_WIREDAND                    (_GPIO_P_MODEH_MODE13_WIREDAND << 20)                /**< Shifted mode WIREDAND for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE13_WIREDANDFILTER              (_GPIO_P_MODEH_MODE13_WIREDANDFILTER << 20)          /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE13_WIREDANDPULLUP              (_GPIO_P_MODEH_MODE13_WIREDANDPULLUP << 20)          /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE13_WIREDANDPULLUPFILTER        (_GPIO_P_MODEH_MODE13_WIREDANDPULLUPFILTER << 20)    /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE13_WIREDANDALT                 (_GPIO_P_MODEH_MODE13_WIREDANDALT << 20)             /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE13_WIREDANDALTFILTER           (_GPIO_P_MODEH_MODE13_WIREDANDALTFILTER << 20)       /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE13_WIREDANDALTPULLUP           (_GPIO_P_MODEH_MODE13_WIREDANDALTPULLUP << 20)       /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE13_WIREDANDALTPULLUPFILTER     (_GPIO_P_MODEH_MODE13_WIREDANDALTPULLUPFILTER << 20) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE14_SHIFT                      24                                                   /**< Shift value for GPIO_MODE14 */
+#define _GPIO_P_MODEH_MODE14_MASK                       0xF000000UL                                          /**< Bit mask for GPIO_MODE14 */
+#define _GPIO_P_MODEH_MODE14_DEFAULT                    0x00000000UL                                         /**< Mode DEFAULT for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE14_DISABLED                   0x00000000UL                                         /**< Mode DISABLED for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE14_INPUT                      0x00000001UL                                         /**< Mode INPUT for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE14_INPUTPULL                  0x00000002UL                                         /**< Mode INPUTPULL for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE14_INPUTPULLFILTER            0x00000003UL                                         /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE14_PUSHPULL                   0x00000004UL                                         /**< Mode PUSHPULL for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE14_PUSHPULLALT                0x00000005UL                                         /**< Mode PUSHPULLALT for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE14_WIREDOR                    0x00000006UL                                         /**< Mode WIREDOR for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE14_WIREDORPULLDOWN            0x00000007UL                                         /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE14_WIREDAND                   0x00000008UL                                         /**< Mode WIREDAND for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE14_WIREDANDFILTER             0x00000009UL                                         /**< Mode WIREDANDFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE14_WIREDANDPULLUP             0x0000000AUL                                         /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE14_WIREDANDPULLUPFILTER       0x0000000BUL                                         /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE14_WIREDANDALT                0x0000000CUL                                         /**< Mode WIREDANDALT for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE14_WIREDANDALTFILTER          0x0000000DUL                                         /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE14_WIREDANDALTPULLUP          0x0000000EUL                                         /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE14_WIREDANDALTPULLUPFILTER    0x0000000FUL                                         /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE14_DEFAULT                     (_GPIO_P_MODEH_MODE14_DEFAULT << 24)                 /**< Shifted mode DEFAULT for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE14_DISABLED                    (_GPIO_P_MODEH_MODE14_DISABLED << 24)                /**< Shifted mode DISABLED for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE14_INPUT                       (_GPIO_P_MODEH_MODE14_INPUT << 24)                   /**< Shifted mode INPUT for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE14_INPUTPULL                   (_GPIO_P_MODEH_MODE14_INPUTPULL << 24)               /**< Shifted mode INPUTPULL for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE14_INPUTPULLFILTER             (_GPIO_P_MODEH_MODE14_INPUTPULLFILTER << 24)         /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE14_PUSHPULL                    (_GPIO_P_MODEH_MODE14_PUSHPULL << 24)                /**< Shifted mode PUSHPULL for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE14_PUSHPULLALT                 (_GPIO_P_MODEH_MODE14_PUSHPULLALT << 24)             /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE14_WIREDOR                     (_GPIO_P_MODEH_MODE14_WIREDOR << 24)                 /**< Shifted mode WIREDOR for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE14_WIREDORPULLDOWN             (_GPIO_P_MODEH_MODE14_WIREDORPULLDOWN << 24)         /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE14_WIREDAND                    (_GPIO_P_MODEH_MODE14_WIREDAND << 24)                /**< Shifted mode WIREDAND for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE14_WIREDANDFILTER              (_GPIO_P_MODEH_MODE14_WIREDANDFILTER << 24)          /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE14_WIREDANDPULLUP              (_GPIO_P_MODEH_MODE14_WIREDANDPULLUP << 24)          /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE14_WIREDANDPULLUPFILTER        (_GPIO_P_MODEH_MODE14_WIREDANDPULLUPFILTER << 24)    /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE14_WIREDANDALT                 (_GPIO_P_MODEH_MODE14_WIREDANDALT << 24)             /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE14_WIREDANDALTFILTER           (_GPIO_P_MODEH_MODE14_WIREDANDALTFILTER << 24)       /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE14_WIREDANDALTPULLUP           (_GPIO_P_MODEH_MODE14_WIREDANDALTPULLUP << 24)       /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE14_WIREDANDALTPULLUPFILTER     (_GPIO_P_MODEH_MODE14_WIREDANDALTPULLUPFILTER << 24) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE15_SHIFT                      28                                                   /**< Shift value for GPIO_MODE15 */
+#define _GPIO_P_MODEH_MODE15_MASK                       0xF0000000UL                                         /**< Bit mask for GPIO_MODE15 */
+#define _GPIO_P_MODEH_MODE15_DEFAULT                    0x00000000UL                                         /**< Mode DEFAULT for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE15_DISABLED                   0x00000000UL                                         /**< Mode DISABLED for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE15_INPUT                      0x00000001UL                                         /**< Mode INPUT for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE15_INPUTPULL                  0x00000002UL                                         /**< Mode INPUTPULL for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE15_INPUTPULLFILTER            0x00000003UL                                         /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE15_PUSHPULL                   0x00000004UL                                         /**< Mode PUSHPULL for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE15_PUSHPULLALT                0x00000005UL                                         /**< Mode PUSHPULLALT for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE15_WIREDOR                    0x00000006UL                                         /**< Mode WIREDOR for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE15_WIREDORPULLDOWN            0x00000007UL                                         /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE15_WIREDAND                   0x00000008UL                                         /**< Mode WIREDAND for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE15_WIREDANDFILTER             0x00000009UL                                         /**< Mode WIREDANDFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE15_WIREDANDPULLUP             0x0000000AUL                                         /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE15_WIREDANDPULLUPFILTER       0x0000000BUL                                         /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE15_WIREDANDALT                0x0000000CUL                                         /**< Mode WIREDANDALT for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE15_WIREDANDALTFILTER          0x0000000DUL                                         /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE15_WIREDANDALTPULLUP          0x0000000EUL                                         /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE15_WIREDANDALTPULLUPFILTER    0x0000000FUL                                         /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE15_DEFAULT                     (_GPIO_P_MODEH_MODE15_DEFAULT << 28)                 /**< Shifted mode DEFAULT for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE15_DISABLED                    (_GPIO_P_MODEH_MODE15_DISABLED << 28)                /**< Shifted mode DISABLED for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE15_INPUT                       (_GPIO_P_MODEH_MODE15_INPUT << 28)                   /**< Shifted mode INPUT for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE15_INPUTPULL                   (_GPIO_P_MODEH_MODE15_INPUTPULL << 28)               /**< Shifted mode INPUTPULL for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE15_INPUTPULLFILTER             (_GPIO_P_MODEH_MODE15_INPUTPULLFILTER << 28)         /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE15_PUSHPULL                    (_GPIO_P_MODEH_MODE15_PUSHPULL << 28)                /**< Shifted mode PUSHPULL for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE15_PUSHPULLALT                 (_GPIO_P_MODEH_MODE15_PUSHPULLALT << 28)             /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE15_WIREDOR                     (_GPIO_P_MODEH_MODE15_WIREDOR << 28)                 /**< Shifted mode WIREDOR for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE15_WIREDORPULLDOWN             (_GPIO_P_MODEH_MODE15_WIREDORPULLDOWN << 28)         /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE15_WIREDAND                    (_GPIO_P_MODEH_MODE15_WIREDAND << 28)                /**< Shifted mode WIREDAND for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE15_WIREDANDFILTER              (_GPIO_P_MODEH_MODE15_WIREDANDFILTER << 28)          /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE15_WIREDANDPULLUP              (_GPIO_P_MODEH_MODE15_WIREDANDPULLUP << 28)          /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE15_WIREDANDPULLUPFILTER        (_GPIO_P_MODEH_MODE15_WIREDANDPULLUPFILTER << 28)    /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE15_WIREDANDALT                 (_GPIO_P_MODEH_MODE15_WIREDANDALT << 28)             /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE15_WIREDANDALTFILTER           (_GPIO_P_MODEH_MODE15_WIREDANDALTFILTER << 28)       /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE15_WIREDANDALTPULLUP           (_GPIO_P_MODEH_MODE15_WIREDANDALTPULLUP << 28)       /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE15_WIREDANDALTPULLUPFILTER     (_GPIO_P_MODEH_MODE15_WIREDANDALTPULLUPFILTER << 28) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */
+
+/* Bit fields for GPIO P_DOUT */
+#define _GPIO_P_DOUT_RESETVALUE                         0x00000000UL                     /**< Default value for GPIO_P_DOUT */
+#define _GPIO_P_DOUT_MASK                               0x0000FFFFUL                     /**< Mask for GPIO_P_DOUT */
+#define _GPIO_P_DOUT_DOUT_SHIFT                         0                                /**< Shift value for GPIO_DOUT */
+#define _GPIO_P_DOUT_DOUT_MASK                          0xFFFFUL                         /**< Bit mask for GPIO_DOUT */
+#define _GPIO_P_DOUT_DOUT_DEFAULT                       0x00000000UL                     /**< Mode DEFAULT for GPIO_P_DOUT */
+#define GPIO_P_DOUT_DOUT_DEFAULT                        (_GPIO_P_DOUT_DOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_DOUT */
+
+/* Bit fields for GPIO P_DOUTTGL */
+#define _GPIO_P_DOUTTGL_RESETVALUE                      0x00000000UL                           /**< Default value for GPIO_P_DOUTTGL */
+#define _GPIO_P_DOUTTGL_MASK                            0x0000FFFFUL                           /**< Mask for GPIO_P_DOUTTGL */
+#define _GPIO_P_DOUTTGL_DOUTTGL_SHIFT                   0                                      /**< Shift value for GPIO_DOUTTGL */
+#define _GPIO_P_DOUTTGL_DOUTTGL_MASK                    0xFFFFUL                               /**< Bit mask for GPIO_DOUTTGL */
+#define _GPIO_P_DOUTTGL_DOUTTGL_DEFAULT                 0x00000000UL                           /**< Mode DEFAULT for GPIO_P_DOUTTGL */
+#define GPIO_P_DOUTTGL_DOUTTGL_DEFAULT                  (_GPIO_P_DOUTTGL_DOUTTGL_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_DOUTTGL */
+
+/* Bit fields for GPIO P_DIN */
+#define _GPIO_P_DIN_RESETVALUE                          0x00000000UL                   /**< Default value for GPIO_P_DIN */
+#define _GPIO_P_DIN_MASK                                0x0000FFFFUL                   /**< Mask for GPIO_P_DIN */
+#define _GPIO_P_DIN_DIN_SHIFT                           0                              /**< Shift value for GPIO_DIN */
+#define _GPIO_P_DIN_DIN_MASK                            0xFFFFUL                       /**< Bit mask for GPIO_DIN */
+#define _GPIO_P_DIN_DIN_DEFAULT                         0x00000000UL                   /**< Mode DEFAULT for GPIO_P_DIN */
+#define GPIO_P_DIN_DIN_DEFAULT                          (_GPIO_P_DIN_DIN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_DIN */
+
+/* Bit fields for GPIO P_PINLOCKN */
+#define _GPIO_P_PINLOCKN_RESETVALUE                     0x0000FFFFUL                             /**< Default value for GPIO_P_PINLOCKN */
+#define _GPIO_P_PINLOCKN_MASK                           0x0000FFFFUL                             /**< Mask for GPIO_P_PINLOCKN */
+#define _GPIO_P_PINLOCKN_PINLOCKN_SHIFT                 0                                        /**< Shift value for GPIO_PINLOCKN */
+#define _GPIO_P_PINLOCKN_PINLOCKN_MASK                  0xFFFFUL                                 /**< Bit mask for GPIO_PINLOCKN */
+#define _GPIO_P_PINLOCKN_PINLOCKN_DEFAULT               0x0000FFFFUL                             /**< Mode DEFAULT for GPIO_P_PINLOCKN */
+#define GPIO_P_PINLOCKN_PINLOCKN_DEFAULT                (_GPIO_P_PINLOCKN_PINLOCKN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_PINLOCKN */
+
+/* Bit fields for GPIO P_OVTDIS */
+#define _GPIO_P_OVTDIS_RESETVALUE                       0x00000000UL                         /**< Default value for GPIO_P_OVTDIS */
+#define _GPIO_P_OVTDIS_MASK                             0x0000FFFFUL                         /**< Mask for GPIO_P_OVTDIS */
+#define _GPIO_P_OVTDIS_OVTDIS_SHIFT                     0                                    /**< Shift value for GPIO_OVTDIS */
+#define _GPIO_P_OVTDIS_OVTDIS_MASK                      0xFFFFUL                             /**< Bit mask for GPIO_OVTDIS */
+#define _GPIO_P_OVTDIS_OVTDIS_DEFAULT                   0x00000000UL                         /**< Mode DEFAULT for GPIO_P_OVTDIS */
+#define GPIO_P_OVTDIS_OVTDIS_DEFAULT                    (_GPIO_P_OVTDIS_OVTDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_OVTDIS */
+
+/* Bit fields for GPIO EXTIPSELL */
+#define _GPIO_EXTIPSELL_RESETVALUE                      0x00000000UL                              /**< Default value for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_MASK                            0xFFFFFFFFUL                              /**< Mask for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL0_SHIFT                 0                                         /**< Shift value for GPIO_EXTIPSEL0 */
+#define _GPIO_EXTIPSELL_EXTIPSEL0_MASK                  0xFUL                                     /**< Bit mask for GPIO_EXTIPSEL0 */
+#define _GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT               0x00000000UL                              /**< Mode DEFAULT for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTA                 0x00000000UL                              /**< Mode PORTA for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTB                 0x00000001UL                              /**< Mode PORTB for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTC                 0x00000002UL                              /**< Mode PORTC for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTD                 0x00000003UL                              /**< Mode PORTD for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTF                 0x00000005UL                              /**< Mode PORTF for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT                (_GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT << 0)  /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL0_PORTA                  (_GPIO_EXTIPSELL_EXTIPSEL0_PORTA << 0)    /**< Shifted mode PORTA for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL0_PORTB                  (_GPIO_EXTIPSELL_EXTIPSEL0_PORTB << 0)    /**< Shifted mode PORTB for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL0_PORTC                  (_GPIO_EXTIPSELL_EXTIPSEL0_PORTC << 0)    /**< Shifted mode PORTC for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL0_PORTD                  (_GPIO_EXTIPSELL_EXTIPSEL0_PORTD << 0)    /**< Shifted mode PORTD for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL0_PORTF                  (_GPIO_EXTIPSELL_EXTIPSEL0_PORTF << 0)    /**< Shifted mode PORTF for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL1_SHIFT                 4                                         /**< Shift value for GPIO_EXTIPSEL1 */
+#define _GPIO_EXTIPSELL_EXTIPSEL1_MASK                  0xF0UL                                    /**< Bit mask for GPIO_EXTIPSEL1 */
+#define _GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT               0x00000000UL                              /**< Mode DEFAULT for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTA                 0x00000000UL                              /**< Mode PORTA for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTB                 0x00000001UL                              /**< Mode PORTB for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTC                 0x00000002UL                              /**< Mode PORTC for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTD                 0x00000003UL                              /**< Mode PORTD for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTF                 0x00000005UL                              /**< Mode PORTF for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT                (_GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT << 4)  /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL1_PORTA                  (_GPIO_EXTIPSELL_EXTIPSEL1_PORTA << 4)    /**< Shifted mode PORTA for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL1_PORTB                  (_GPIO_EXTIPSELL_EXTIPSEL1_PORTB << 4)    /**< Shifted mode PORTB for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL1_PORTC                  (_GPIO_EXTIPSELL_EXTIPSEL1_PORTC << 4)    /**< Shifted mode PORTC for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL1_PORTD                  (_GPIO_EXTIPSELL_EXTIPSEL1_PORTD << 4)    /**< Shifted mode PORTD for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL1_PORTF                  (_GPIO_EXTIPSELL_EXTIPSEL1_PORTF << 4)    /**< Shifted mode PORTF for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL2_SHIFT                 8                                         /**< Shift value for GPIO_EXTIPSEL2 */
+#define _GPIO_EXTIPSELL_EXTIPSEL2_MASK                  0xF00UL                                   /**< Bit mask for GPIO_EXTIPSEL2 */
+#define _GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT               0x00000000UL                              /**< Mode DEFAULT for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTA                 0x00000000UL                              /**< Mode PORTA for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTB                 0x00000001UL                              /**< Mode PORTB for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTC                 0x00000002UL                              /**< Mode PORTC for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTD                 0x00000003UL                              /**< Mode PORTD for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTF                 0x00000005UL                              /**< Mode PORTF for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT                (_GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT << 8)  /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL2_PORTA                  (_GPIO_EXTIPSELL_EXTIPSEL2_PORTA << 8)    /**< Shifted mode PORTA for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL2_PORTB                  (_GPIO_EXTIPSELL_EXTIPSEL2_PORTB << 8)    /**< Shifted mode PORTB for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL2_PORTC                  (_GPIO_EXTIPSELL_EXTIPSEL2_PORTC << 8)    /**< Shifted mode PORTC for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL2_PORTD                  (_GPIO_EXTIPSELL_EXTIPSEL2_PORTD << 8)    /**< Shifted mode PORTD for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL2_PORTF                  (_GPIO_EXTIPSELL_EXTIPSEL2_PORTF << 8)    /**< Shifted mode PORTF for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL3_SHIFT                 12                                        /**< Shift value for GPIO_EXTIPSEL3 */
+#define _GPIO_EXTIPSELL_EXTIPSEL3_MASK                  0xF000UL                                  /**< Bit mask for GPIO_EXTIPSEL3 */
+#define _GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT               0x00000000UL                              /**< Mode DEFAULT for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTA                 0x00000000UL                              /**< Mode PORTA for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTB                 0x00000001UL                              /**< Mode PORTB for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTC                 0x00000002UL                              /**< Mode PORTC for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTD                 0x00000003UL                              /**< Mode PORTD for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTF                 0x00000005UL                              /**< Mode PORTF for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT                (_GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL3_PORTA                  (_GPIO_EXTIPSELL_EXTIPSEL3_PORTA << 12)   /**< Shifted mode PORTA for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL3_PORTB                  (_GPIO_EXTIPSELL_EXTIPSEL3_PORTB << 12)   /**< Shifted mode PORTB for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL3_PORTC                  (_GPIO_EXTIPSELL_EXTIPSEL3_PORTC << 12)   /**< Shifted mode PORTC for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL3_PORTD                  (_GPIO_EXTIPSELL_EXTIPSEL3_PORTD << 12)   /**< Shifted mode PORTD for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL3_PORTF                  (_GPIO_EXTIPSELL_EXTIPSEL3_PORTF << 12)   /**< Shifted mode PORTF for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL4_SHIFT                 16                                        /**< Shift value for GPIO_EXTIPSEL4 */
+#define _GPIO_EXTIPSELL_EXTIPSEL4_MASK                  0xF0000UL                                 /**< Bit mask for GPIO_EXTIPSEL4 */
+#define _GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT               0x00000000UL                              /**< Mode DEFAULT for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTA                 0x00000000UL                              /**< Mode PORTA for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTB                 0x00000001UL                              /**< Mode PORTB for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTC                 0x00000002UL                              /**< Mode PORTC for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTD                 0x00000003UL                              /**< Mode PORTD for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTF                 0x00000005UL                              /**< Mode PORTF for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT                (_GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL4_PORTA                  (_GPIO_EXTIPSELL_EXTIPSEL4_PORTA << 16)   /**< Shifted mode PORTA for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL4_PORTB                  (_GPIO_EXTIPSELL_EXTIPSEL4_PORTB << 16)   /**< Shifted mode PORTB for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL4_PORTC                  (_GPIO_EXTIPSELL_EXTIPSEL4_PORTC << 16)   /**< Shifted mode PORTC for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL4_PORTD                  (_GPIO_EXTIPSELL_EXTIPSEL4_PORTD << 16)   /**< Shifted mode PORTD for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL4_PORTF                  (_GPIO_EXTIPSELL_EXTIPSEL4_PORTF << 16)   /**< Shifted mode PORTF for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL5_SHIFT                 20                                        /**< Shift value for GPIO_EXTIPSEL5 */
+#define _GPIO_EXTIPSELL_EXTIPSEL5_MASK                  0xF00000UL                                /**< Bit mask for GPIO_EXTIPSEL5 */
+#define _GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT               0x00000000UL                              /**< Mode DEFAULT for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTA                 0x00000000UL                              /**< Mode PORTA for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTB                 0x00000001UL                              /**< Mode PORTB for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTC                 0x00000002UL                              /**< Mode PORTC for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTD                 0x00000003UL                              /**< Mode PORTD for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTF                 0x00000005UL                              /**< Mode PORTF for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT                (_GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL5_PORTA                  (_GPIO_EXTIPSELL_EXTIPSEL5_PORTA << 20)   /**< Shifted mode PORTA for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL5_PORTB                  (_GPIO_EXTIPSELL_EXTIPSEL5_PORTB << 20)   /**< Shifted mode PORTB for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL5_PORTC                  (_GPIO_EXTIPSELL_EXTIPSEL5_PORTC << 20)   /**< Shifted mode PORTC for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL5_PORTD                  (_GPIO_EXTIPSELL_EXTIPSEL5_PORTD << 20)   /**< Shifted mode PORTD for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL5_PORTF                  (_GPIO_EXTIPSELL_EXTIPSEL5_PORTF << 20)   /**< Shifted mode PORTF for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL6_SHIFT                 24                                        /**< Shift value for GPIO_EXTIPSEL6 */
+#define _GPIO_EXTIPSELL_EXTIPSEL6_MASK                  0xF000000UL                               /**< Bit mask for GPIO_EXTIPSEL6 */
+#define _GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT               0x00000000UL                              /**< Mode DEFAULT for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTA                 0x00000000UL                              /**< Mode PORTA for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTB                 0x00000001UL                              /**< Mode PORTB for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTC                 0x00000002UL                              /**< Mode PORTC for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTD                 0x00000003UL                              /**< Mode PORTD for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTF                 0x00000005UL                              /**< Mode PORTF for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT                (_GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL6_PORTA                  (_GPIO_EXTIPSELL_EXTIPSEL6_PORTA << 24)   /**< Shifted mode PORTA for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL6_PORTB                  (_GPIO_EXTIPSELL_EXTIPSEL6_PORTB << 24)   /**< Shifted mode PORTB for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL6_PORTC                  (_GPIO_EXTIPSELL_EXTIPSEL6_PORTC << 24)   /**< Shifted mode PORTC for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL6_PORTD                  (_GPIO_EXTIPSELL_EXTIPSEL6_PORTD << 24)   /**< Shifted mode PORTD for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL6_PORTF                  (_GPIO_EXTIPSELL_EXTIPSEL6_PORTF << 24)   /**< Shifted mode PORTF for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL7_SHIFT                 28                                        /**< Shift value for GPIO_EXTIPSEL7 */
+#define _GPIO_EXTIPSELL_EXTIPSEL7_MASK                  0xF0000000UL                              /**< Bit mask for GPIO_EXTIPSEL7 */
+#define _GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT               0x00000000UL                              /**< Mode DEFAULT for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTA                 0x00000000UL                              /**< Mode PORTA for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTB                 0x00000001UL                              /**< Mode PORTB for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTC                 0x00000002UL                              /**< Mode PORTC for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTD                 0x00000003UL                              /**< Mode PORTD for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTF                 0x00000005UL                              /**< Mode PORTF for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT                (_GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL7_PORTA                  (_GPIO_EXTIPSELL_EXTIPSEL7_PORTA << 28)   /**< Shifted mode PORTA for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL7_PORTB                  (_GPIO_EXTIPSELL_EXTIPSEL7_PORTB << 28)   /**< Shifted mode PORTB for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL7_PORTC                  (_GPIO_EXTIPSELL_EXTIPSEL7_PORTC << 28)   /**< Shifted mode PORTC for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL7_PORTD                  (_GPIO_EXTIPSELL_EXTIPSEL7_PORTD << 28)   /**< Shifted mode PORTD for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL7_PORTF                  (_GPIO_EXTIPSELL_EXTIPSEL7_PORTF << 28)   /**< Shifted mode PORTF for GPIO_EXTIPSELL */
+
+/* Bit fields for GPIO EXTIPSELH */
+#define _GPIO_EXTIPSELH_RESETVALUE                      0x00000000UL                               /**< Default value for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_MASK                            0xFFFFFFFFUL                               /**< Mask for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL8_SHIFT                 0                                          /**< Shift value for GPIO_EXTIPSEL8 */
+#define _GPIO_EXTIPSELH_EXTIPSEL8_MASK                  0xFUL                                      /**< Bit mask for GPIO_EXTIPSEL8 */
+#define _GPIO_EXTIPSELH_EXTIPSEL8_DEFAULT               0x00000000UL                               /**< Mode DEFAULT for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL8_PORTA                 0x00000000UL                               /**< Mode PORTA for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL8_PORTB                 0x00000001UL                               /**< Mode PORTB for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL8_PORTC                 0x00000002UL                               /**< Mode PORTC for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL8_PORTD                 0x00000003UL                               /**< Mode PORTD for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL8_PORTF                 0x00000005UL                               /**< Mode PORTF for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL8_DEFAULT                (_GPIO_EXTIPSELH_EXTIPSEL8_DEFAULT << 0)   /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL8_PORTA                  (_GPIO_EXTIPSELH_EXTIPSEL8_PORTA << 0)     /**< Shifted mode PORTA for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL8_PORTB                  (_GPIO_EXTIPSELH_EXTIPSEL8_PORTB << 0)     /**< Shifted mode PORTB for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL8_PORTC                  (_GPIO_EXTIPSELH_EXTIPSEL8_PORTC << 0)     /**< Shifted mode PORTC for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL8_PORTD                  (_GPIO_EXTIPSELH_EXTIPSEL8_PORTD << 0)     /**< Shifted mode PORTD for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL8_PORTF                  (_GPIO_EXTIPSELH_EXTIPSEL8_PORTF << 0)     /**< Shifted mode PORTF for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL9_SHIFT                 4                                          /**< Shift value for GPIO_EXTIPSEL9 */
+#define _GPIO_EXTIPSELH_EXTIPSEL9_MASK                  0xF0UL                                     /**< Bit mask for GPIO_EXTIPSEL9 */
+#define _GPIO_EXTIPSELH_EXTIPSEL9_DEFAULT               0x00000000UL                               /**< Mode DEFAULT for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL9_PORTA                 0x00000000UL                               /**< Mode PORTA for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL9_PORTB                 0x00000001UL                               /**< Mode PORTB for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL9_PORTC                 0x00000002UL                               /**< Mode PORTC for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL9_PORTD                 0x00000003UL                               /**< Mode PORTD for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL9_PORTF                 0x00000005UL                               /**< Mode PORTF for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL9_DEFAULT                (_GPIO_EXTIPSELH_EXTIPSEL9_DEFAULT << 4)   /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL9_PORTA                  (_GPIO_EXTIPSELH_EXTIPSEL9_PORTA << 4)     /**< Shifted mode PORTA for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL9_PORTB                  (_GPIO_EXTIPSELH_EXTIPSEL9_PORTB << 4)     /**< Shifted mode PORTB for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL9_PORTC                  (_GPIO_EXTIPSELH_EXTIPSEL9_PORTC << 4)     /**< Shifted mode PORTC for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL9_PORTD                  (_GPIO_EXTIPSELH_EXTIPSEL9_PORTD << 4)     /**< Shifted mode PORTD for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL9_PORTF                  (_GPIO_EXTIPSELH_EXTIPSEL9_PORTF << 4)     /**< Shifted mode PORTF for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL10_SHIFT                8                                          /**< Shift value for GPIO_EXTIPSEL10 */
+#define _GPIO_EXTIPSELH_EXTIPSEL10_MASK                 0xF00UL                                    /**< Bit mask for GPIO_EXTIPSEL10 */
+#define _GPIO_EXTIPSELH_EXTIPSEL10_DEFAULT              0x00000000UL                               /**< Mode DEFAULT for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL10_PORTA                0x00000000UL                               /**< Mode PORTA for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL10_PORTB                0x00000001UL                               /**< Mode PORTB for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL10_PORTC                0x00000002UL                               /**< Mode PORTC for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL10_PORTD                0x00000003UL                               /**< Mode PORTD for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL10_PORTF                0x00000005UL                               /**< Mode PORTF for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL10_DEFAULT               (_GPIO_EXTIPSELH_EXTIPSEL10_DEFAULT << 8)  /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL10_PORTA                 (_GPIO_EXTIPSELH_EXTIPSEL10_PORTA << 8)    /**< Shifted mode PORTA for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL10_PORTB                 (_GPIO_EXTIPSELH_EXTIPSEL10_PORTB << 8)    /**< Shifted mode PORTB for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL10_PORTC                 (_GPIO_EXTIPSELH_EXTIPSEL10_PORTC << 8)    /**< Shifted mode PORTC for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL10_PORTD                 (_GPIO_EXTIPSELH_EXTIPSEL10_PORTD << 8)    /**< Shifted mode PORTD for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL10_PORTF                 (_GPIO_EXTIPSELH_EXTIPSEL10_PORTF << 8)    /**< Shifted mode PORTF for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL11_SHIFT                12                                         /**< Shift value for GPIO_EXTIPSEL11 */
+#define _GPIO_EXTIPSELH_EXTIPSEL11_MASK                 0xF000UL                                   /**< Bit mask for GPIO_EXTIPSEL11 */
+#define _GPIO_EXTIPSELH_EXTIPSEL11_DEFAULT              0x00000000UL                               /**< Mode DEFAULT for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL11_PORTA                0x00000000UL                               /**< Mode PORTA for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL11_PORTB                0x00000001UL                               /**< Mode PORTB for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL11_PORTC                0x00000002UL                               /**< Mode PORTC for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL11_PORTD                0x00000003UL                               /**< Mode PORTD for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL11_PORTF                0x00000005UL                               /**< Mode PORTF for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL11_DEFAULT               (_GPIO_EXTIPSELH_EXTIPSEL11_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL11_PORTA                 (_GPIO_EXTIPSELH_EXTIPSEL11_PORTA << 12)   /**< Shifted mode PORTA for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL11_PORTB                 (_GPIO_EXTIPSELH_EXTIPSEL11_PORTB << 12)   /**< Shifted mode PORTB for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL11_PORTC                 (_GPIO_EXTIPSELH_EXTIPSEL11_PORTC << 12)   /**< Shifted mode PORTC for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL11_PORTD                 (_GPIO_EXTIPSELH_EXTIPSEL11_PORTD << 12)   /**< Shifted mode PORTD for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL11_PORTF                 (_GPIO_EXTIPSELH_EXTIPSEL11_PORTF << 12)   /**< Shifted mode PORTF for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL12_SHIFT                16                                         /**< Shift value for GPIO_EXTIPSEL12 */
+#define _GPIO_EXTIPSELH_EXTIPSEL12_MASK                 0xF0000UL                                  /**< Bit mask for GPIO_EXTIPSEL12 */
+#define _GPIO_EXTIPSELH_EXTIPSEL12_DEFAULT              0x00000000UL                               /**< Mode DEFAULT for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL12_PORTA                0x00000000UL                               /**< Mode PORTA for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL12_PORTB                0x00000001UL                               /**< Mode PORTB for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL12_PORTC                0x00000002UL                               /**< Mode PORTC for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL12_PORTD                0x00000003UL                               /**< Mode PORTD for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL12_PORTF                0x00000005UL                               /**< Mode PORTF for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL12_DEFAULT               (_GPIO_EXTIPSELH_EXTIPSEL12_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL12_PORTA                 (_GPIO_EXTIPSELH_EXTIPSEL12_PORTA << 16)   /**< Shifted mode PORTA for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL12_PORTB                 (_GPIO_EXTIPSELH_EXTIPSEL12_PORTB << 16)   /**< Shifted mode PORTB for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL12_PORTC                 (_GPIO_EXTIPSELH_EXTIPSEL12_PORTC << 16)   /**< Shifted mode PORTC for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL12_PORTD                 (_GPIO_EXTIPSELH_EXTIPSEL12_PORTD << 16)   /**< Shifted mode PORTD for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL12_PORTF                 (_GPIO_EXTIPSELH_EXTIPSEL12_PORTF << 16)   /**< Shifted mode PORTF for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL13_SHIFT                20                                         /**< Shift value for GPIO_EXTIPSEL13 */
+#define _GPIO_EXTIPSELH_EXTIPSEL13_MASK                 0xF00000UL                                 /**< Bit mask for GPIO_EXTIPSEL13 */
+#define _GPIO_EXTIPSELH_EXTIPSEL13_DEFAULT              0x00000000UL                               /**< Mode DEFAULT for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL13_PORTA                0x00000000UL                               /**< Mode PORTA for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL13_PORTB                0x00000001UL                               /**< Mode PORTB for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL13_PORTC                0x00000002UL                               /**< Mode PORTC for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL13_PORTD                0x00000003UL                               /**< Mode PORTD for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL13_PORTF                0x00000005UL                               /**< Mode PORTF for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL13_DEFAULT               (_GPIO_EXTIPSELH_EXTIPSEL13_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL13_PORTA                 (_GPIO_EXTIPSELH_EXTIPSEL13_PORTA << 20)   /**< Shifted mode PORTA for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL13_PORTB                 (_GPIO_EXTIPSELH_EXTIPSEL13_PORTB << 20)   /**< Shifted mode PORTB for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL13_PORTC                 (_GPIO_EXTIPSELH_EXTIPSEL13_PORTC << 20)   /**< Shifted mode PORTC for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL13_PORTD                 (_GPIO_EXTIPSELH_EXTIPSEL13_PORTD << 20)   /**< Shifted mode PORTD for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL13_PORTF                 (_GPIO_EXTIPSELH_EXTIPSEL13_PORTF << 20)   /**< Shifted mode PORTF for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL14_SHIFT                24                                         /**< Shift value for GPIO_EXTIPSEL14 */
+#define _GPIO_EXTIPSELH_EXTIPSEL14_MASK                 0xF000000UL                                /**< Bit mask for GPIO_EXTIPSEL14 */
+#define _GPIO_EXTIPSELH_EXTIPSEL14_DEFAULT              0x00000000UL                               /**< Mode DEFAULT for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL14_PORTA                0x00000000UL                               /**< Mode PORTA for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL14_PORTB                0x00000001UL                               /**< Mode PORTB for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL14_PORTC                0x00000002UL                               /**< Mode PORTC for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL14_PORTD                0x00000003UL                               /**< Mode PORTD for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL14_PORTF                0x00000005UL                               /**< Mode PORTF for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL14_DEFAULT               (_GPIO_EXTIPSELH_EXTIPSEL14_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL14_PORTA                 (_GPIO_EXTIPSELH_EXTIPSEL14_PORTA << 24)   /**< Shifted mode PORTA for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL14_PORTB                 (_GPIO_EXTIPSELH_EXTIPSEL14_PORTB << 24)   /**< Shifted mode PORTB for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL14_PORTC                 (_GPIO_EXTIPSELH_EXTIPSEL14_PORTC << 24)   /**< Shifted mode PORTC for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL14_PORTD                 (_GPIO_EXTIPSELH_EXTIPSEL14_PORTD << 24)   /**< Shifted mode PORTD for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL14_PORTF                 (_GPIO_EXTIPSELH_EXTIPSEL14_PORTF << 24)   /**< Shifted mode PORTF for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL15_SHIFT                28                                         /**< Shift value for GPIO_EXTIPSEL15 */
+#define _GPIO_EXTIPSELH_EXTIPSEL15_MASK                 0xF0000000UL                               /**< Bit mask for GPIO_EXTIPSEL15 */
+#define _GPIO_EXTIPSELH_EXTIPSEL15_DEFAULT              0x00000000UL                               /**< Mode DEFAULT for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL15_PORTA                0x00000000UL                               /**< Mode PORTA for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL15_PORTB                0x00000001UL                               /**< Mode PORTB for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL15_PORTC                0x00000002UL                               /**< Mode PORTC for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL15_PORTD                0x00000003UL                               /**< Mode PORTD for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL15_PORTF                0x00000005UL                               /**< Mode PORTF for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL15_DEFAULT               (_GPIO_EXTIPSELH_EXTIPSEL15_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL15_PORTA                 (_GPIO_EXTIPSELH_EXTIPSEL15_PORTA << 28)   /**< Shifted mode PORTA for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL15_PORTB                 (_GPIO_EXTIPSELH_EXTIPSEL15_PORTB << 28)   /**< Shifted mode PORTB for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL15_PORTC                 (_GPIO_EXTIPSELH_EXTIPSEL15_PORTC << 28)   /**< Shifted mode PORTC for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL15_PORTD                 (_GPIO_EXTIPSELH_EXTIPSEL15_PORTD << 28)   /**< Shifted mode PORTD for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL15_PORTF                 (_GPIO_EXTIPSELH_EXTIPSEL15_PORTF << 28)   /**< Shifted mode PORTF for GPIO_EXTIPSELH */
+
+/* Bit fields for GPIO EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_RESETVALUE                    0x32103210UL                                  /**< Default value for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_MASK                          0x33333333UL                                  /**< Mask for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL0_SHIFT             0                                             /**< Shift value for GPIO_EXTIPINSEL0 */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL0_MASK              0x3UL                                         /**< Bit mask for GPIO_EXTIPINSEL0 */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT           0x00000000UL                                  /**< Mode DEFAULT for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN0              0x00000000UL                                  /**< Mode PIN0 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN1              0x00000001UL                                  /**< Mode PIN1 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN2              0x00000002UL                                  /**< Mode PIN2 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN3              0x00000003UL                                  /**< Mode PIN3 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT            (_GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT << 0)  /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN0               (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN0 << 0)     /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN1               (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN1 << 0)     /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN2               (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN2 << 0)     /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN3               (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN3 << 0)     /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL1_SHIFT             4                                             /**< Shift value for GPIO_EXTIPINSEL1 */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL1_MASK              0x30UL                                        /**< Bit mask for GPIO_EXTIPINSEL1 */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN0              0x00000000UL                                  /**< Mode PIN0 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT           0x00000001UL                                  /**< Mode DEFAULT for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN1              0x00000001UL                                  /**< Mode PIN1 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN2              0x00000002UL                                  /**< Mode PIN2 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN3              0x00000003UL                                  /**< Mode PIN3 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN0               (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN0 << 4)     /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT            (_GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT << 4)  /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN1               (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN1 << 4)     /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN2               (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN2 << 4)     /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN3               (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN3 << 4)     /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL2_SHIFT             8                                             /**< Shift value for GPIO_EXTIPINSEL2 */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL2_MASK              0x300UL                                       /**< Bit mask for GPIO_EXTIPINSEL2 */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN0              0x00000000UL                                  /**< Mode PIN0 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN1              0x00000001UL                                  /**< Mode PIN1 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT           0x00000002UL                                  /**< Mode DEFAULT for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN2              0x00000002UL                                  /**< Mode PIN2 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN3              0x00000003UL                                  /**< Mode PIN3 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN0               (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN0 << 8)     /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN1               (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN1 << 8)     /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT            (_GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT << 8)  /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN2               (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN2 << 8)     /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN3               (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN3 << 8)     /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL3_SHIFT             12                                            /**< Shift value for GPIO_EXTIPINSEL3 */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL3_MASK              0x3000UL                                      /**< Bit mask for GPIO_EXTIPINSEL3 */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN0              0x00000000UL                                  /**< Mode PIN0 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN1              0x00000001UL                                  /**< Mode PIN1 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN2              0x00000002UL                                  /**< Mode PIN2 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT           0x00000003UL                                  /**< Mode DEFAULT for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN3              0x00000003UL                                  /**< Mode PIN3 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN0               (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN0 << 12)    /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN1               (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN1 << 12)    /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN2               (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN2 << 12)    /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT            (_GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN3               (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN3 << 12)    /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL4_SHIFT             16                                            /**< Shift value for GPIO_EXTIPINSEL4 */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL4_MASK              0x30000UL                                     /**< Bit mask for GPIO_EXTIPINSEL4 */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT           0x00000000UL                                  /**< Mode DEFAULT for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN4              0x00000000UL                                  /**< Mode PIN4 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN5              0x00000001UL                                  /**< Mode PIN5 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN6              0x00000002UL                                  /**< Mode PIN6 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN7              0x00000003UL                                  /**< Mode PIN7 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT            (_GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN4               (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN4 << 16)    /**< Shifted mode PIN4 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN5               (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN5 << 16)    /**< Shifted mode PIN5 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN6               (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN6 << 16)    /**< Shifted mode PIN6 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN7               (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN7 << 16)    /**< Shifted mode PIN7 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL5_SHIFT             20                                            /**< Shift value for GPIO_EXTIPINSEL5 */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL5_MASK              0x300000UL                                    /**< Bit mask for GPIO_EXTIPINSEL5 */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN4              0x00000000UL                                  /**< Mode PIN4 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT           0x00000001UL                                  /**< Mode DEFAULT for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN5              0x00000001UL                                  /**< Mode PIN5 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN6              0x00000002UL                                  /**< Mode PIN6 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN7              0x00000003UL                                  /**< Mode PIN7 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN4               (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN4 << 20)    /**< Shifted mode PIN4 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT            (_GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN5               (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN5 << 20)    /**< Shifted mode PIN5 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN6               (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN6 << 20)    /**< Shifted mode PIN6 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN7               (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN7 << 20)    /**< Shifted mode PIN7 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL6_SHIFT             24                                            /**< Shift value for GPIO_EXTIPINSEL6 */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL6_MASK              0x3000000UL                                   /**< Bit mask for GPIO_EXTIPINSEL6 */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN4              0x00000000UL                                  /**< Mode PIN4 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN5              0x00000001UL                                  /**< Mode PIN5 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT           0x00000002UL                                  /**< Mode DEFAULT for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN6              0x00000002UL                                  /**< Mode PIN6 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN7              0x00000003UL                                  /**< Mode PIN7 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN4               (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN4 << 24)    /**< Shifted mode PIN4 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN5               (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN5 << 24)    /**< Shifted mode PIN5 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT            (_GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN6               (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN6 << 24)    /**< Shifted mode PIN6 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN7               (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN7 << 24)    /**< Shifted mode PIN7 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL7_SHIFT             28                                            /**< Shift value for GPIO_EXTIPINSEL7 */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL7_MASK              0x30000000UL                                  /**< Bit mask for GPIO_EXTIPINSEL7 */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN4              0x00000000UL                                  /**< Mode PIN4 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN5              0x00000001UL                                  /**< Mode PIN5 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN6              0x00000002UL                                  /**< Mode PIN6 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT           0x00000003UL                                  /**< Mode DEFAULT for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN7              0x00000003UL                                  /**< Mode PIN7 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN4               (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN4 << 28)    /**< Shifted mode PIN4 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN5               (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN5 << 28)    /**< Shifted mode PIN5 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN6               (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN6 << 28)    /**< Shifted mode PIN6 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT            (_GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN7               (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN7 << 28)    /**< Shifted mode PIN7 for GPIO_EXTIPINSELL */
+
+/* Bit fields for GPIO EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_RESETVALUE                    0x32103210UL                                   /**< Default value for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_MASK                          0x33333333UL                                   /**< Mask for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL8_SHIFT             0                                              /**< Shift value for GPIO_EXTIPINSEL8 */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL8_MASK              0x3UL                                          /**< Bit mask for GPIO_EXTIPINSEL8 */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL8_DEFAULT           0x00000000UL                                   /**< Mode DEFAULT for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL8_PIN8              0x00000000UL                                   /**< Mode PIN8 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL8_PIN9              0x00000001UL                                   /**< Mode PIN9 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL8_PIN10             0x00000002UL                                   /**< Mode PIN10 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL8_PIN11             0x00000003UL                                   /**< Mode PIN11 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL8_DEFAULT            (_GPIO_EXTIPINSELH_EXTIPINSEL8_DEFAULT << 0)   /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL8_PIN8               (_GPIO_EXTIPINSELH_EXTIPINSEL8_PIN8 << 0)      /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL8_PIN9               (_GPIO_EXTIPINSELH_EXTIPINSEL8_PIN9 << 0)      /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL8_PIN10              (_GPIO_EXTIPINSELH_EXTIPINSEL8_PIN10 << 0)     /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL8_PIN11              (_GPIO_EXTIPINSELH_EXTIPINSEL8_PIN11 << 0)     /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL9_SHIFT             4                                              /**< Shift value for GPIO_EXTIPINSEL9 */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL9_MASK              0x30UL                                         /**< Bit mask for GPIO_EXTIPINSEL9 */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL9_PIN8              0x00000000UL                                   /**< Mode PIN8 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL9_DEFAULT           0x00000001UL                                   /**< Mode DEFAULT for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL9_PIN9              0x00000001UL                                   /**< Mode PIN9 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL9_PIN10             0x00000002UL                                   /**< Mode PIN10 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL9_PIN11             0x00000003UL                                   /**< Mode PIN11 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL9_PIN8               (_GPIO_EXTIPINSELH_EXTIPINSEL9_PIN8 << 4)      /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL9_DEFAULT            (_GPIO_EXTIPINSELH_EXTIPINSEL9_DEFAULT << 4)   /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL9_PIN9               (_GPIO_EXTIPINSELH_EXTIPINSEL9_PIN9 << 4)      /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL9_PIN10              (_GPIO_EXTIPINSELH_EXTIPINSEL9_PIN10 << 4)     /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL9_PIN11              (_GPIO_EXTIPINSELH_EXTIPINSEL9_PIN11 << 4)     /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL10_SHIFT            8                                              /**< Shift value for GPIO_EXTIPINSEL10 */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL10_MASK             0x300UL                                        /**< Bit mask for GPIO_EXTIPINSEL10 */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL10_PIN8             0x00000000UL                                   /**< Mode PIN8 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL10_PIN9             0x00000001UL                                   /**< Mode PIN9 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL10_DEFAULT          0x00000002UL                                   /**< Mode DEFAULT for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL10_PIN10            0x00000002UL                                   /**< Mode PIN10 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL10_PIN11            0x00000003UL                                   /**< Mode PIN11 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL10_PIN8              (_GPIO_EXTIPINSELH_EXTIPINSEL10_PIN8 << 8)     /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL10_PIN9              (_GPIO_EXTIPINSELH_EXTIPINSEL10_PIN9 << 8)     /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL10_DEFAULT           (_GPIO_EXTIPINSELH_EXTIPINSEL10_DEFAULT << 8)  /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL10_PIN10             (_GPIO_EXTIPINSELH_EXTIPINSEL10_PIN10 << 8)    /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL10_PIN11             (_GPIO_EXTIPINSELH_EXTIPINSEL10_PIN11 << 8)    /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL11_SHIFT            12                                             /**< Shift value for GPIO_EXTIPINSEL11 */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL11_MASK             0x3000UL                                       /**< Bit mask for GPIO_EXTIPINSEL11 */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL11_PIN8             0x00000000UL                                   /**< Mode PIN8 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL11_PIN9             0x00000001UL                                   /**< Mode PIN9 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL11_PIN10            0x00000002UL                                   /**< Mode PIN10 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL11_DEFAULT          0x00000003UL                                   /**< Mode DEFAULT for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL11_PIN11            0x00000003UL                                   /**< Mode PIN11 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL11_PIN8              (_GPIO_EXTIPINSELH_EXTIPINSEL11_PIN8 << 12)    /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL11_PIN9              (_GPIO_EXTIPINSELH_EXTIPINSEL11_PIN9 << 12)    /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL11_PIN10             (_GPIO_EXTIPINSELH_EXTIPINSEL11_PIN10 << 12)   /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL11_DEFAULT           (_GPIO_EXTIPINSELH_EXTIPINSEL11_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL11_PIN11             (_GPIO_EXTIPINSELH_EXTIPINSEL11_PIN11 << 12)   /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL12_SHIFT            16                                             /**< Shift value for GPIO_EXTIPINSEL12 */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL12_MASK             0x30000UL                                      /**< Bit mask for GPIO_EXTIPINSEL12 */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL12_DEFAULT          0x00000000UL                                   /**< Mode DEFAULT for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL12_PIN12            0x00000000UL                                   /**< Mode PIN12 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL12_PIN13            0x00000001UL                                   /**< Mode PIN13 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL12_PIN14            0x00000002UL                                   /**< Mode PIN14 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL12_PIN15            0x00000003UL                                   /**< Mode PIN15 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL12_DEFAULT           (_GPIO_EXTIPINSELH_EXTIPINSEL12_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL12_PIN12             (_GPIO_EXTIPINSELH_EXTIPINSEL12_PIN12 << 16)   /**< Shifted mode PIN12 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL12_PIN13             (_GPIO_EXTIPINSELH_EXTIPINSEL12_PIN13 << 16)   /**< Shifted mode PIN13 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL12_PIN14             (_GPIO_EXTIPINSELH_EXTIPINSEL12_PIN14 << 16)   /**< Shifted mode PIN14 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL12_PIN15             (_GPIO_EXTIPINSELH_EXTIPINSEL12_PIN15 << 16)   /**< Shifted mode PIN15 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL13_SHIFT            20                                             /**< Shift value for GPIO_EXTIPINSEL13 */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL13_MASK             0x300000UL                                     /**< Bit mask for GPIO_EXTIPINSEL13 */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL13_PIN12            0x00000000UL                                   /**< Mode PIN12 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL13_DEFAULT          0x00000001UL                                   /**< Mode DEFAULT for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL13_PIN13            0x00000001UL                                   /**< Mode PIN13 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL13_PIN14            0x00000002UL                                   /**< Mode PIN14 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL13_PIN15            0x00000003UL                                   /**< Mode PIN15 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL13_PIN12             (_GPIO_EXTIPINSELH_EXTIPINSEL13_PIN12 << 20)   /**< Shifted mode PIN12 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL13_DEFAULT           (_GPIO_EXTIPINSELH_EXTIPINSEL13_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL13_PIN13             (_GPIO_EXTIPINSELH_EXTIPINSEL13_PIN13 << 20)   /**< Shifted mode PIN13 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL13_PIN14             (_GPIO_EXTIPINSELH_EXTIPINSEL13_PIN14 << 20)   /**< Shifted mode PIN14 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL13_PIN15             (_GPIO_EXTIPINSELH_EXTIPINSEL13_PIN15 << 20)   /**< Shifted mode PIN15 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL14_SHIFT            24                                             /**< Shift value for GPIO_EXTIPINSEL14 */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL14_MASK             0x3000000UL                                    /**< Bit mask for GPIO_EXTIPINSEL14 */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL14_PIN12            0x00000000UL                                   /**< Mode PIN12 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL14_PIN13            0x00000001UL                                   /**< Mode PIN13 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL14_DEFAULT          0x00000002UL                                   /**< Mode DEFAULT for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL14_PIN14            0x00000002UL                                   /**< Mode PIN14 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL14_PIN15            0x00000003UL                                   /**< Mode PIN15 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL14_PIN12             (_GPIO_EXTIPINSELH_EXTIPINSEL14_PIN12 << 24)   /**< Shifted mode PIN12 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL14_PIN13             (_GPIO_EXTIPINSELH_EXTIPINSEL14_PIN13 << 24)   /**< Shifted mode PIN13 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL14_DEFAULT           (_GPIO_EXTIPINSELH_EXTIPINSEL14_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL14_PIN14             (_GPIO_EXTIPINSELH_EXTIPINSEL14_PIN14 << 24)   /**< Shifted mode PIN14 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL14_PIN15             (_GPIO_EXTIPINSELH_EXTIPINSEL14_PIN15 << 24)   /**< Shifted mode PIN15 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL15_SHIFT            28                                             /**< Shift value for GPIO_EXTIPINSEL15 */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL15_MASK             0x30000000UL                                   /**< Bit mask for GPIO_EXTIPINSEL15 */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL15_PIN12            0x00000000UL                                   /**< Mode PIN12 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL15_PIN13            0x00000001UL                                   /**< Mode PIN13 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL15_PIN14            0x00000002UL                                   /**< Mode PIN14 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL15_DEFAULT          0x00000003UL                                   /**< Mode DEFAULT for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL15_PIN15            0x00000003UL                                   /**< Mode PIN15 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL15_PIN12             (_GPIO_EXTIPINSELH_EXTIPINSEL15_PIN12 << 28)   /**< Shifted mode PIN12 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL15_PIN13             (_GPIO_EXTIPINSELH_EXTIPINSEL15_PIN13 << 28)   /**< Shifted mode PIN13 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL15_PIN14             (_GPIO_EXTIPINSELH_EXTIPINSEL15_PIN14 << 28)   /**< Shifted mode PIN14 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL15_DEFAULT           (_GPIO_EXTIPINSELH_EXTIPINSEL15_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL15_PIN15             (_GPIO_EXTIPINSELH_EXTIPINSEL15_PIN15 << 28)   /**< Shifted mode PIN15 for GPIO_EXTIPINSELH */
+
+/* Bit fields for GPIO EXTIRISE */
+#define _GPIO_EXTIRISE_RESETVALUE                       0x00000000UL                           /**< Default value for GPIO_EXTIRISE */
+#define _GPIO_EXTIRISE_MASK                             0x0000FFFFUL                           /**< Mask for GPIO_EXTIRISE */
+#define _GPIO_EXTIRISE_EXTIRISE_SHIFT                   0                                      /**< Shift value for GPIO_EXTIRISE */
+#define _GPIO_EXTIRISE_EXTIRISE_MASK                    0xFFFFUL                               /**< Bit mask for GPIO_EXTIRISE */
+#define _GPIO_EXTIRISE_EXTIRISE_DEFAULT                 0x00000000UL                           /**< Mode DEFAULT for GPIO_EXTIRISE */
+#define GPIO_EXTIRISE_EXTIRISE_DEFAULT                  (_GPIO_EXTIRISE_EXTIRISE_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIRISE */
+
+/* Bit fields for GPIO EXTIFALL */
+#define _GPIO_EXTIFALL_RESETVALUE                       0x00000000UL                           /**< Default value for GPIO_EXTIFALL */
+#define _GPIO_EXTIFALL_MASK                             0x0000FFFFUL                           /**< Mask for GPIO_EXTIFALL */
+#define _GPIO_EXTIFALL_EXTIFALL_SHIFT                   0                                      /**< Shift value for GPIO_EXTIFALL */
+#define _GPIO_EXTIFALL_EXTIFALL_MASK                    0xFFFFUL                               /**< Bit mask for GPIO_EXTIFALL */
+#define _GPIO_EXTIFALL_EXTIFALL_DEFAULT                 0x00000000UL                           /**< Mode DEFAULT for GPIO_EXTIFALL */
+#define GPIO_EXTIFALL_EXTIFALL_DEFAULT                  (_GPIO_EXTIFALL_EXTIFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIFALL */
+
+/* Bit fields for GPIO EXTILEVEL */
+#define _GPIO_EXTILEVEL_RESETVALUE                      0x00000000UL                            /**< Default value for GPIO_EXTILEVEL */
+#define _GPIO_EXTILEVEL_MASK                            0x13130000UL                            /**< Mask for GPIO_EXTILEVEL */
+#define GPIO_EXTILEVEL_EM4WU0                           (0x1UL << 16)                           /**< EM4 Wake Up Level for EM4WU0 Pin */
+#define _GPIO_EXTILEVEL_EM4WU0_SHIFT                    16                                      /**< Shift value for GPIO_EM4WU0 */
+#define _GPIO_EXTILEVEL_EM4WU0_MASK                     0x10000UL                               /**< Bit mask for GPIO_EM4WU0 */
+#define _GPIO_EXTILEVEL_EM4WU0_DEFAULT                  0x00000000UL                            /**< Mode DEFAULT for GPIO_EXTILEVEL */
+#define GPIO_EXTILEVEL_EM4WU0_DEFAULT                   (_GPIO_EXTILEVEL_EM4WU0_DEFAULT << 16)  /**< Shifted mode DEFAULT for GPIO_EXTILEVEL */
+#define GPIO_EXTILEVEL_EM4WU1                           (0x1UL << 17)                           /**< EM4 Wake Up Level for EM4WU1 Pin */
+#define _GPIO_EXTILEVEL_EM4WU1_SHIFT                    17                                      /**< Shift value for GPIO_EM4WU1 */
+#define _GPIO_EXTILEVEL_EM4WU1_MASK                     0x20000UL                               /**< Bit mask for GPIO_EM4WU1 */
+#define _GPIO_EXTILEVEL_EM4WU1_DEFAULT                  0x00000000UL                            /**< Mode DEFAULT for GPIO_EXTILEVEL */
+#define GPIO_EXTILEVEL_EM4WU1_DEFAULT                   (_GPIO_EXTILEVEL_EM4WU1_DEFAULT << 17)  /**< Shifted mode DEFAULT for GPIO_EXTILEVEL */
+#define GPIO_EXTILEVEL_EM4WU4                           (0x1UL << 20)                           /**< EM4 Wake Up Level for EM4WU4 Pin */
+#define _GPIO_EXTILEVEL_EM4WU4_SHIFT                    20                                      /**< Shift value for GPIO_EM4WU4 */
+#define _GPIO_EXTILEVEL_EM4WU4_MASK                     0x100000UL                              /**< Bit mask for GPIO_EM4WU4 */
+#define _GPIO_EXTILEVEL_EM4WU4_DEFAULT                  0x00000000UL                            /**< Mode DEFAULT for GPIO_EXTILEVEL */
+#define GPIO_EXTILEVEL_EM4WU4_DEFAULT                   (_GPIO_EXTILEVEL_EM4WU4_DEFAULT << 20)  /**< Shifted mode DEFAULT for GPIO_EXTILEVEL */
+#define GPIO_EXTILEVEL_EM4WU8                           (0x1UL << 24)                           /**< EM4 Wake Up Level for EM4WU8 Pin */
+#define _GPIO_EXTILEVEL_EM4WU8_SHIFT                    24                                      /**< Shift value for GPIO_EM4WU8 */
+#define _GPIO_EXTILEVEL_EM4WU8_MASK                     0x1000000UL                             /**< Bit mask for GPIO_EM4WU8 */
+#define _GPIO_EXTILEVEL_EM4WU8_DEFAULT                  0x00000000UL                            /**< Mode DEFAULT for GPIO_EXTILEVEL */
+#define GPIO_EXTILEVEL_EM4WU8_DEFAULT                   (_GPIO_EXTILEVEL_EM4WU8_DEFAULT << 24)  /**< Shifted mode DEFAULT for GPIO_EXTILEVEL */
+#define GPIO_EXTILEVEL_EM4WU9                           (0x1UL << 25)                           /**< EM4 Wake Up Level for EM4WU9 Pin */
+#define _GPIO_EXTILEVEL_EM4WU9_SHIFT                    25                                      /**< Shift value for GPIO_EM4WU9 */
+#define _GPIO_EXTILEVEL_EM4WU9_MASK                     0x2000000UL                             /**< Bit mask for GPIO_EM4WU9 */
+#define _GPIO_EXTILEVEL_EM4WU9_DEFAULT                  0x00000000UL                            /**< Mode DEFAULT for GPIO_EXTILEVEL */
+#define GPIO_EXTILEVEL_EM4WU9_DEFAULT                   (_GPIO_EXTILEVEL_EM4WU9_DEFAULT << 25)  /**< Shifted mode DEFAULT for GPIO_EXTILEVEL */
+#define GPIO_EXTILEVEL_EM4WU12                          (0x1UL << 28)                           /**< EM4 Wake Up Level for EM4WU12 Pin */
+#define _GPIO_EXTILEVEL_EM4WU12_SHIFT                   28                                      /**< Shift value for GPIO_EM4WU12 */
+#define _GPIO_EXTILEVEL_EM4WU12_MASK                    0x10000000UL                            /**< Bit mask for GPIO_EM4WU12 */
+#define _GPIO_EXTILEVEL_EM4WU12_DEFAULT                 0x00000000UL                            /**< Mode DEFAULT for GPIO_EXTILEVEL */
+#define GPIO_EXTILEVEL_EM4WU12_DEFAULT                  (_GPIO_EXTILEVEL_EM4WU12_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTILEVEL */
+
+/* Bit fields for GPIO IF */
+#define _GPIO_IF_RESETVALUE                             0x00000000UL                   /**< Default value for GPIO_IF */
+#define _GPIO_IF_MASK                                   0xFFFFFFFFUL                   /**< Mask for GPIO_IF */
+#define _GPIO_IF_EXT_SHIFT                              0                              /**< Shift value for GPIO_EXT */
+#define _GPIO_IF_EXT_MASK                               0xFFFFUL                       /**< Bit mask for GPIO_EXT */
+#define _GPIO_IF_EXT_DEFAULT                            0x00000000UL                   /**< Mode DEFAULT for GPIO_IF */
+#define GPIO_IF_EXT_DEFAULT                             (_GPIO_IF_EXT_DEFAULT << 0)    /**< Shifted mode DEFAULT for GPIO_IF */
+#define _GPIO_IF_EM4WU_SHIFT                            16                             /**< Shift value for GPIO_EM4WU */
+#define _GPIO_IF_EM4WU_MASK                             0xFFFF0000UL                   /**< Bit mask for GPIO_EM4WU */
+#define _GPIO_IF_EM4WU_DEFAULT                          0x00000000UL                   /**< Mode DEFAULT for GPIO_IF */
+#define GPIO_IF_EM4WU_DEFAULT                           (_GPIO_IF_EM4WU_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_IF */
+
+/* Bit fields for GPIO IFS */
+#define _GPIO_IFS_RESETVALUE                            0x00000000UL                    /**< Default value for GPIO_IFS */
+#define _GPIO_IFS_MASK                                  0xFFFFFFFFUL                    /**< Mask for GPIO_IFS */
+#define _GPIO_IFS_EXT_SHIFT                             0                               /**< Shift value for GPIO_EXT */
+#define _GPIO_IFS_EXT_MASK                              0xFFFFUL                        /**< Bit mask for GPIO_EXT */
+#define _GPIO_IFS_EXT_DEFAULT                           0x00000000UL                    /**< Mode DEFAULT for GPIO_IFS */
+#define GPIO_IFS_EXT_DEFAULT                            (_GPIO_IFS_EXT_DEFAULT << 0)    /**< Shifted mode DEFAULT for GPIO_IFS */
+#define _GPIO_IFS_EM4WU_SHIFT                           16                              /**< Shift value for GPIO_EM4WU */
+#define _GPIO_IFS_EM4WU_MASK                            0xFFFF0000UL                    /**< Bit mask for GPIO_EM4WU */
+#define _GPIO_IFS_EM4WU_DEFAULT                         0x00000000UL                    /**< Mode DEFAULT for GPIO_IFS */
+#define GPIO_IFS_EM4WU_DEFAULT                          (_GPIO_IFS_EM4WU_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_IFS */
+
+/* Bit fields for GPIO IFC */
+#define _GPIO_IFC_RESETVALUE                            0x00000000UL                    /**< Default value for GPIO_IFC */
+#define _GPIO_IFC_MASK                                  0xFFFFFFFFUL                    /**< Mask for GPIO_IFC */
+#define _GPIO_IFC_EXT_SHIFT                             0                               /**< Shift value for GPIO_EXT */
+#define _GPIO_IFC_EXT_MASK                              0xFFFFUL                        /**< Bit mask for GPIO_EXT */
+#define _GPIO_IFC_EXT_DEFAULT                           0x00000000UL                    /**< Mode DEFAULT for GPIO_IFC */
+#define GPIO_IFC_EXT_DEFAULT                            (_GPIO_IFC_EXT_DEFAULT << 0)    /**< Shifted mode DEFAULT for GPIO_IFC */
+#define _GPIO_IFC_EM4WU_SHIFT                           16                              /**< Shift value for GPIO_EM4WU */
+#define _GPIO_IFC_EM4WU_MASK                            0xFFFF0000UL                    /**< Bit mask for GPIO_EM4WU */
+#define _GPIO_IFC_EM4WU_DEFAULT                         0x00000000UL                    /**< Mode DEFAULT for GPIO_IFC */
+#define GPIO_IFC_EM4WU_DEFAULT                          (_GPIO_IFC_EM4WU_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_IFC */
+
+/* Bit fields for GPIO IEN */
+#define _GPIO_IEN_RESETVALUE                            0x00000000UL                    /**< Default value for GPIO_IEN */
+#define _GPIO_IEN_MASK                                  0xFFFFFFFFUL                    /**< Mask for GPIO_IEN */
+#define _GPIO_IEN_EXT_SHIFT                             0                               /**< Shift value for GPIO_EXT */
+#define _GPIO_IEN_EXT_MASK                              0xFFFFUL                        /**< Bit mask for GPIO_EXT */
+#define _GPIO_IEN_EXT_DEFAULT                           0x00000000UL                    /**< Mode DEFAULT for GPIO_IEN */
+#define GPIO_IEN_EXT_DEFAULT                            (_GPIO_IEN_EXT_DEFAULT << 0)    /**< Shifted mode DEFAULT for GPIO_IEN */
+#define _GPIO_IEN_EM4WU_SHIFT                           16                              /**< Shift value for GPIO_EM4WU */
+#define _GPIO_IEN_EM4WU_MASK                            0xFFFF0000UL                    /**< Bit mask for GPIO_EM4WU */
+#define _GPIO_IEN_EM4WU_DEFAULT                         0x00000000UL                    /**< Mode DEFAULT for GPIO_IEN */
+#define GPIO_IEN_EM4WU_DEFAULT                          (_GPIO_IEN_EM4WU_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_IEN */
+
+/* Bit fields for GPIO EM4WUEN */
+#define _GPIO_EM4WUEN_RESETVALUE                        0x00000000UL                          /**< Default value for GPIO_EM4WUEN */
+#define _GPIO_EM4WUEN_MASK                              0xFFFF0000UL                          /**< Mask for GPIO_EM4WUEN */
+#define _GPIO_EM4WUEN_EM4WUEN_SHIFT                     16                                    /**< Shift value for GPIO_EM4WUEN */
+#define _GPIO_EM4WUEN_EM4WUEN_MASK                      0xFFFF0000UL                          /**< Bit mask for GPIO_EM4WUEN */
+#define _GPIO_EM4WUEN_EM4WUEN_DEFAULT                   0x00000000UL                          /**< Mode DEFAULT for GPIO_EM4WUEN */
+#define GPIO_EM4WUEN_EM4WUEN_DEFAULT                    (_GPIO_EM4WUEN_EM4WUEN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EM4WUEN */
+
+/* Bit fields for GPIO ROUTEPEN */
+#define _GPIO_ROUTEPEN_RESETVALUE                       0x0000000FUL                              /**< Default value for GPIO_ROUTEPEN */
+#define _GPIO_ROUTEPEN_MASK                             0x0000001FUL                              /**< Mask for GPIO_ROUTEPEN */
+#define GPIO_ROUTEPEN_SWCLKTCKPEN                       (0x1UL << 0)                              /**< Serial Wire Clock and JTAG Test Clock Pin Enable */
+#define _GPIO_ROUTEPEN_SWCLKTCKPEN_SHIFT                0                                         /**< Shift value for GPIO_SWCLKTCKPEN */
+#define _GPIO_ROUTEPEN_SWCLKTCKPEN_MASK                 0x1UL                                     /**< Bit mask for GPIO_SWCLKTCKPEN */
+#define _GPIO_ROUTEPEN_SWCLKTCKPEN_DEFAULT              0x00000001UL                              /**< Mode DEFAULT for GPIO_ROUTEPEN */
+#define GPIO_ROUTEPEN_SWCLKTCKPEN_DEFAULT               (_GPIO_ROUTEPEN_SWCLKTCKPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */
+#define GPIO_ROUTEPEN_SWDIOTMSPEN                       (0x1UL << 1)                              /**< Serial Wire Data and JTAG Test Mode Select Pin Enable */
+#define _GPIO_ROUTEPEN_SWDIOTMSPEN_SHIFT                1                                         /**< Shift value for GPIO_SWDIOTMSPEN */
+#define _GPIO_ROUTEPEN_SWDIOTMSPEN_MASK                 0x2UL                                     /**< Bit mask for GPIO_SWDIOTMSPEN */
+#define _GPIO_ROUTEPEN_SWDIOTMSPEN_DEFAULT              0x00000001UL                              /**< Mode DEFAULT for GPIO_ROUTEPEN */
+#define GPIO_ROUTEPEN_SWDIOTMSPEN_DEFAULT               (_GPIO_ROUTEPEN_SWDIOTMSPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */
+#define GPIO_ROUTEPEN_TDOPEN                            (0x1UL << 2)                              /**< JTAG Test Debug Output Pin Enable */
+#define _GPIO_ROUTEPEN_TDOPEN_SHIFT                     2                                         /**< Shift value for GPIO_TDOPEN */
+#define _GPIO_ROUTEPEN_TDOPEN_MASK                      0x4UL                                     /**< Bit mask for GPIO_TDOPEN */
+#define _GPIO_ROUTEPEN_TDOPEN_DEFAULT                   0x00000001UL                              /**< Mode DEFAULT for GPIO_ROUTEPEN */
+#define GPIO_ROUTEPEN_TDOPEN_DEFAULT                    (_GPIO_ROUTEPEN_TDOPEN_DEFAULT << 2)      /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */
+#define GPIO_ROUTEPEN_TDIPEN                            (0x1UL << 3)                              /**< JTAG Test Debug Input Pin Enable */
+#define _GPIO_ROUTEPEN_TDIPEN_SHIFT                     3                                         /**< Shift value for GPIO_TDIPEN */
+#define _GPIO_ROUTEPEN_TDIPEN_MASK                      0x8UL                                     /**< Bit mask for GPIO_TDIPEN */
+#define _GPIO_ROUTEPEN_TDIPEN_DEFAULT                   0x00000001UL                              /**< Mode DEFAULT for GPIO_ROUTEPEN */
+#define GPIO_ROUTEPEN_TDIPEN_DEFAULT                    (_GPIO_ROUTEPEN_TDIPEN_DEFAULT << 3)      /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */
+#define GPIO_ROUTEPEN_SWVPEN                            (0x1UL << 4)                              /**< Serial Wire Viewer Output Pin Enable */
+#define _GPIO_ROUTEPEN_SWVPEN_SHIFT                     4                                         /**< Shift value for GPIO_SWVPEN */
+#define _GPIO_ROUTEPEN_SWVPEN_MASK                      0x10UL                                    /**< Bit mask for GPIO_SWVPEN */
+#define _GPIO_ROUTEPEN_SWVPEN_DEFAULT                   0x00000000UL                              /**< Mode DEFAULT for GPIO_ROUTEPEN */
+#define GPIO_ROUTEPEN_SWVPEN_DEFAULT                    (_GPIO_ROUTEPEN_SWVPEN_DEFAULT << 4)      /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */
+
+/* Bit fields for GPIO ROUTELOC0 */
+#define _GPIO_ROUTELOC0_RESETVALUE                      0x00000000UL                          /**< Default value for GPIO_ROUTELOC0 */
+#define _GPIO_ROUTELOC0_MASK                            0x00000003UL                          /**< Mask for GPIO_ROUTELOC0 */
+#define _GPIO_ROUTELOC0_SWVLOC_SHIFT                    0                                     /**< Shift value for GPIO_SWVLOC */
+#define _GPIO_ROUTELOC0_SWVLOC_MASK                     0x3UL                                 /**< Bit mask for GPIO_SWVLOC */
+#define _GPIO_ROUTELOC0_SWVLOC_LOC0                     0x00000000UL                          /**< Mode LOC0 for GPIO_ROUTELOC0 */
+#define _GPIO_ROUTELOC0_SWVLOC_DEFAULT                  0x00000000UL                          /**< Mode DEFAULT for GPIO_ROUTELOC0 */
+#define _GPIO_ROUTELOC0_SWVLOC_LOC1                     0x00000001UL                          /**< Mode LOC1 for GPIO_ROUTELOC0 */
+#define _GPIO_ROUTELOC0_SWVLOC_LOC2                     0x00000002UL                          /**< Mode LOC2 for GPIO_ROUTELOC0 */
+#define _GPIO_ROUTELOC0_SWVLOC_LOC3                     0x00000003UL                          /**< Mode LOC3 for GPIO_ROUTELOC0 */
+#define GPIO_ROUTELOC0_SWVLOC_LOC0                      (_GPIO_ROUTELOC0_SWVLOC_LOC0 << 0)    /**< Shifted mode LOC0 for GPIO_ROUTELOC0 */
+#define GPIO_ROUTELOC0_SWVLOC_DEFAULT                   (_GPIO_ROUTELOC0_SWVLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_ROUTELOC0 */
+#define GPIO_ROUTELOC0_SWVLOC_LOC1                      (_GPIO_ROUTELOC0_SWVLOC_LOC1 << 0)    /**< Shifted mode LOC1 for GPIO_ROUTELOC0 */
+#define GPIO_ROUTELOC0_SWVLOC_LOC2                      (_GPIO_ROUTELOC0_SWVLOC_LOC2 << 0)    /**< Shifted mode LOC2 for GPIO_ROUTELOC0 */
+#define GPIO_ROUTELOC0_SWVLOC_LOC3                      (_GPIO_ROUTELOC0_SWVLOC_LOC3 << 0)    /**< Shifted mode LOC3 for GPIO_ROUTELOC0 */
+
+/* Bit fields for GPIO INSENSE */
+#define _GPIO_INSENSE_RESETVALUE                        0x00000003UL                       /**< Default value for GPIO_INSENSE */
+#define _GPIO_INSENSE_MASK                              0x00000003UL                       /**< Mask for GPIO_INSENSE */
+#define GPIO_INSENSE_INT                                (0x1UL << 0)                       /**< Interrupt Sense Enable */
+#define _GPIO_INSENSE_INT_SHIFT                         0                                  /**< Shift value for GPIO_INT */
+#define _GPIO_INSENSE_INT_MASK                          0x1UL                              /**< Bit mask for GPIO_INT */
+#define _GPIO_INSENSE_INT_DEFAULT                       0x00000001UL                       /**< Mode DEFAULT for GPIO_INSENSE */
+#define GPIO_INSENSE_INT_DEFAULT                        (_GPIO_INSENSE_INT_DEFAULT << 0)   /**< Shifted mode DEFAULT for GPIO_INSENSE */
+#define GPIO_INSENSE_EM4WU                              (0x1UL << 1)                       /**< EM4WU Interrupt Sense Enable */
+#define _GPIO_INSENSE_EM4WU_SHIFT                       1                                  /**< Shift value for GPIO_EM4WU */
+#define _GPIO_INSENSE_EM4WU_MASK                        0x2UL                              /**< Bit mask for GPIO_EM4WU */
+#define _GPIO_INSENSE_EM4WU_DEFAULT                     0x00000001UL                       /**< Mode DEFAULT for GPIO_INSENSE */
+#define GPIO_INSENSE_EM4WU_DEFAULT                      (_GPIO_INSENSE_EM4WU_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_INSENSE */
+
+/* Bit fields for GPIO LOCK */
+#define _GPIO_LOCK_RESETVALUE                           0x00000000UL                       /**< Default value for GPIO_LOCK */
+#define _GPIO_LOCK_MASK                                 0x0000FFFFUL                       /**< Mask for GPIO_LOCK */
+#define _GPIO_LOCK_LOCKKEY_SHIFT                        0                                  /**< Shift value for GPIO_LOCKKEY */
+#define _GPIO_LOCK_LOCKKEY_MASK                         0xFFFFUL                           /**< Bit mask for GPIO_LOCKKEY */
+#define _GPIO_LOCK_LOCKKEY_DEFAULT                      0x00000000UL                       /**< Mode DEFAULT for GPIO_LOCK */
+#define _GPIO_LOCK_LOCKKEY_LOCK                         0x00000000UL                       /**< Mode LOCK for GPIO_LOCK */
+#define _GPIO_LOCK_LOCKKEY_UNLOCKED                     0x00000000UL                       /**< Mode UNLOCKED for GPIO_LOCK */
+#define _GPIO_LOCK_LOCKKEY_LOCKED                       0x00000001UL                       /**< Mode LOCKED for GPIO_LOCK */
+#define _GPIO_LOCK_LOCKKEY_UNLOCK                       0x0000A534UL                       /**< Mode UNLOCK for GPIO_LOCK */
+#define GPIO_LOCK_LOCKKEY_DEFAULT                       (_GPIO_LOCK_LOCKKEY_DEFAULT << 0)  /**< Shifted mode DEFAULT for GPIO_LOCK */
+#define GPIO_LOCK_LOCKKEY_LOCK                          (_GPIO_LOCK_LOCKKEY_LOCK << 0)     /**< Shifted mode LOCK for GPIO_LOCK */
+#define GPIO_LOCK_LOCKKEY_UNLOCKED                      (_GPIO_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for GPIO_LOCK */
+#define GPIO_LOCK_LOCKKEY_LOCKED                        (_GPIO_LOCK_LOCKKEY_LOCKED << 0)   /**< Shifted mode LOCKED for GPIO_LOCK */
+#define GPIO_LOCK_LOCKKEY_UNLOCK                        (_GPIO_LOCK_LOCKKEY_UNLOCK << 0)   /**< Shifted mode UNLOCK for GPIO_LOCK */
+
+/** @} End of group EFM32PG1B_GPIO */
+/** @} End of group Parts */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG_STK3401/efm32pg1b_gpio_p.h	Fri Jan 15 07:45:16 2016 +0000
@@ -0,0 +1,56 @@
+/**************************************************************************//**
+ * @file efm32pg1b_gpio_p.h
+ * @brief EFM32PG1B_GPIO_P register and bit field definitions
+ * @version 4.2.0
+ ******************************************************************************
+ * @section License
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ ******************************************************************************
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software.@n
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.@n
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is
+ * providing the Software "AS IS", with no express or implied warranties of any
+ * kind, including, but not limited to, any implied warranties of
+ * merchantability or fitness for any particular purpose or warranties against
+ * infringement of any proprietary rights of a third party.
+ *
+ * Silicon Laboratories, Inc. will not be liable for any consequential,
+ * incidental, or special damages, or any other relief, or for any claim by
+ * any third party, arising from your use of this Software.
+ *
+ *****************************************************************************/
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @brief GPIO_P EFM32PG1B GPIO P
+ *****************************************************************************/
+typedef struct
+{
+  __IO uint32_t CTRL;         /**< Port Control Register  */
+  __IO uint32_t MODEL;        /**< Port Pin Mode Low Register  */
+  __IO uint32_t MODEH;        /**< Port Pin Mode High Register  */
+  __IO uint32_t DOUT;         /**< Port Data Out Register  */
+  uint32_t      RESERVED0[2]; /**< Reserved for future use **/
+  __IO uint32_t DOUTTGL;      /**< Port Data Out Toggle Register  */
+  __I uint32_t  DIN;          /**< Port Data In Register  */
+  __IO uint32_t PINLOCKN;     /**< Port Unlocked Pins Register  */
+  uint32_t      RESERVED1[1]; /**< Reserved for future use **/
+  __IO uint32_t OVTDIS;       /**< Over Voltage Disable for all modes  */
+  uint32_t      RESERVED2[1]; /**< Reserved future */
+} GPIO_P_TypeDef;
+
+/** @} End of group Parts */
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG_STK3401/efm32pg1b_i2c.h	Fri Jan 15 07:45:16 2016 +0000
@@ -0,0 +1,921 @@
+/**************************************************************************//**
+ * @file efm32pg1b_i2c.h
+ * @brief EFM32PG1B_I2C register and bit field definitions
+ * @version 4.2.0
+ ******************************************************************************
+ * @section License
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ ******************************************************************************
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software.@n
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.@n
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is
+ * providing the Software "AS IS", with no express or implied warranties of any
+ * kind, including, but not limited to, any implied warranties of
+ * merchantability or fitness for any particular purpose or warranties against
+ * infringement of any proprietary rights of a third party.
+ *
+ * Silicon Laboratories, Inc. will not be liable for any consequential,
+ * incidental, or special damages, or any other relief, or for any claim by
+ * any third party, arising from your use of this Software.
+ *
+ *****************************************************************************/
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFM32PG1B_I2C
+ * @{
+ * @brief EFM32PG1B_I2C Register Declaration
+ *****************************************************************************/
+typedef struct
+{
+  __IO uint32_t CTRL;      /**< Control Register  */
+  __IO uint32_t CMD;       /**< Command Register  */
+  __I uint32_t  STATE;     /**< State Register  */
+  __I uint32_t  STATUS;    /**< Status Register  */
+  __IO uint32_t CLKDIV;    /**< Clock Division Register  */
+  __IO uint32_t SADDR;     /**< Slave Address Register  */
+  __IO uint32_t SADDRMASK; /**< Slave Address Mask Register  */
+  __I uint32_t  RXDATA;    /**< Receive Buffer Data Register  */
+  __I uint32_t  RXDOUBLE;  /**< Receive Buffer Double Data Register  */
+  __I uint32_t  RXDATAP;   /**< Receive Buffer Data Peek Register  */
+  __I uint32_t  RXDOUBLEP; /**< Receive Buffer Double Data Peek Register  */
+  __IO uint32_t TXDATA;    /**< Transmit Buffer Data Register  */
+  __IO uint32_t TXDOUBLE;  /**< Transmit Buffer Double Data Register  */
+  __I uint32_t  IF;        /**< Interrupt Flag Register  */
+  __IO uint32_t IFS;       /**< Interrupt Flag Set Register  */
+  __IO uint32_t IFC;       /**< Interrupt Flag Clear Register  */
+  __IO uint32_t IEN;       /**< Interrupt Enable Register  */
+  __IO uint32_t ROUTEPEN;  /**< I/O Routing Pin Enable Register  */
+  __IO uint32_t ROUTELOC0; /**< I/O Routing Location Register  */
+} I2C_TypeDef;             /** @} */
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B_I2C_BitFields
+ * @{
+ *****************************************************************************/
+
+/* Bit fields for I2C CTRL */
+#define _I2C_CTRL_RESETVALUE               0x00000000UL                     /**< Default value for I2C_CTRL */
+#define _I2C_CTRL_MASK                     0x0007B3FFUL                     /**< Mask for I2C_CTRL */
+#define I2C_CTRL_EN                        (0x1UL << 0)                     /**< I2C Enable */
+#define _I2C_CTRL_EN_SHIFT                 0                                /**< Shift value for I2C_EN */
+#define _I2C_CTRL_EN_MASK                  0x1UL                            /**< Bit mask for I2C_EN */
+#define _I2C_CTRL_EN_DEFAULT               0x00000000UL                     /**< Mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_EN_DEFAULT                (_I2C_CTRL_EN_DEFAULT << 0)      /**< Shifted mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_SLAVE                     (0x1UL << 1)                     /**< Addressable as Slave */
+#define _I2C_CTRL_SLAVE_SHIFT              1                                /**< Shift value for I2C_SLAVE */
+#define _I2C_CTRL_SLAVE_MASK               0x2UL                            /**< Bit mask for I2C_SLAVE */
+#define _I2C_CTRL_SLAVE_DEFAULT            0x00000000UL                     /**< Mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_SLAVE_DEFAULT             (_I2C_CTRL_SLAVE_DEFAULT << 1)   /**< Shifted mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_AUTOACK                   (0x1UL << 2)                     /**< Automatic Acknowledge */
+#define _I2C_CTRL_AUTOACK_SHIFT            2                                /**< Shift value for I2C_AUTOACK */
+#define _I2C_CTRL_AUTOACK_MASK             0x4UL                            /**< Bit mask for I2C_AUTOACK */
+#define _I2C_CTRL_AUTOACK_DEFAULT          0x00000000UL                     /**< Mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_AUTOACK_DEFAULT           (_I2C_CTRL_AUTOACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_AUTOSE                    (0x1UL << 3)                     /**< Automatic STOP when Empty */
+#define _I2C_CTRL_AUTOSE_SHIFT             3                                /**< Shift value for I2C_AUTOSE */
+#define _I2C_CTRL_AUTOSE_MASK              0x8UL                            /**< Bit mask for I2C_AUTOSE */
+#define _I2C_CTRL_AUTOSE_DEFAULT           0x00000000UL                     /**< Mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_AUTOSE_DEFAULT            (_I2C_CTRL_AUTOSE_DEFAULT << 3)  /**< Shifted mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_AUTOSN                    (0x1UL << 4)                     /**< Automatic STOP on NACK */
+#define _I2C_CTRL_AUTOSN_SHIFT             4                                /**< Shift value for I2C_AUTOSN */
+#define _I2C_CTRL_AUTOSN_MASK              0x10UL                           /**< Bit mask for I2C_AUTOSN */
+#define _I2C_CTRL_AUTOSN_DEFAULT           0x00000000UL                     /**< Mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_AUTOSN_DEFAULT            (_I2C_CTRL_AUTOSN_DEFAULT << 4)  /**< Shifted mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_ARBDIS                    (0x1UL << 5)                     /**< Arbitration Disable */
+#define _I2C_CTRL_ARBDIS_SHIFT             5                                /**< Shift value for I2C_ARBDIS */
+#define _I2C_CTRL_ARBDIS_MASK              0x20UL                           /**< Bit mask for I2C_ARBDIS */
+#define _I2C_CTRL_ARBDIS_DEFAULT           0x00000000UL                     /**< Mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_ARBDIS_DEFAULT            (_I2C_CTRL_ARBDIS_DEFAULT << 5)  /**< Shifted mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_GCAMEN                    (0x1UL << 6)                     /**< General Call Address Match Enable */
+#define _I2C_CTRL_GCAMEN_SHIFT             6                                /**< Shift value for I2C_GCAMEN */
+#define _I2C_CTRL_GCAMEN_MASK              0x40UL                           /**< Bit mask for I2C_GCAMEN */
+#define _I2C_CTRL_GCAMEN_DEFAULT           0x00000000UL                     /**< Mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_GCAMEN_DEFAULT            (_I2C_CTRL_GCAMEN_DEFAULT << 6)  /**< Shifted mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_TXBIL                     (0x1UL << 7)                     /**< TX Buffer Interrupt Level */
+#define _I2C_CTRL_TXBIL_SHIFT              7                                /**< Shift value for I2C_TXBIL */
+#define _I2C_CTRL_TXBIL_MASK               0x80UL                           /**< Bit mask for I2C_TXBIL */
+#define _I2C_CTRL_TXBIL_DEFAULT            0x00000000UL                     /**< Mode DEFAULT for I2C_CTRL */
+#define _I2C_CTRL_TXBIL_EMPTY              0x00000000UL                     /**< Mode EMPTY for I2C_CTRL */
+#define _I2C_CTRL_TXBIL_HALFFULL           0x00000001UL                     /**< Mode HALFFULL for I2C_CTRL */
+#define I2C_CTRL_TXBIL_DEFAULT             (_I2C_CTRL_TXBIL_DEFAULT << 7)   /**< Shifted mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_TXBIL_EMPTY               (_I2C_CTRL_TXBIL_EMPTY << 7)     /**< Shifted mode EMPTY for I2C_CTRL */
+#define I2C_CTRL_TXBIL_HALFFULL            (_I2C_CTRL_TXBIL_HALFFULL << 7)  /**< Shifted mode HALFFULL for I2C_CTRL */
+#define _I2C_CTRL_CLHR_SHIFT               8                                /**< Shift value for I2C_CLHR */
+#define _I2C_CTRL_CLHR_MASK                0x300UL                          /**< Bit mask for I2C_CLHR */
+#define _I2C_CTRL_CLHR_DEFAULT             0x00000000UL                     /**< Mode DEFAULT for I2C_CTRL */
+#define _I2C_CTRL_CLHR_STANDARD            0x00000000UL                     /**< Mode STANDARD for I2C_CTRL */
+#define _I2C_CTRL_CLHR_ASYMMETRIC          0x00000001UL                     /**< Mode ASYMMETRIC for I2C_CTRL */
+#define _I2C_CTRL_CLHR_FAST                0x00000002UL                     /**< Mode FAST for I2C_CTRL */
+#define I2C_CTRL_CLHR_DEFAULT              (_I2C_CTRL_CLHR_DEFAULT << 8)    /**< Shifted mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_CLHR_STANDARD             (_I2C_CTRL_CLHR_STANDARD << 8)   /**< Shifted mode STANDARD for I2C_CTRL */
+#define I2C_CTRL_CLHR_ASYMMETRIC           (_I2C_CTRL_CLHR_ASYMMETRIC << 8) /**< Shifted mode ASYMMETRIC for I2C_CTRL */
+#define I2C_CTRL_CLHR_FAST                 (_I2C_CTRL_CLHR_FAST << 8)       /**< Shifted mode FAST for I2C_CTRL */
+#define _I2C_CTRL_BITO_SHIFT               12                               /**< Shift value for I2C_BITO */
+#define _I2C_CTRL_BITO_MASK                0x3000UL                         /**< Bit mask for I2C_BITO */
+#define _I2C_CTRL_BITO_DEFAULT             0x00000000UL                     /**< Mode DEFAULT for I2C_CTRL */
+#define _I2C_CTRL_BITO_OFF                 0x00000000UL                     /**< Mode OFF for I2C_CTRL */
+#define _I2C_CTRL_BITO_40PCC               0x00000001UL                     /**< Mode 40PCC for I2C_CTRL */
+#define _I2C_CTRL_BITO_80PCC               0x00000002UL                     /**< Mode 80PCC for I2C_CTRL */
+#define _I2C_CTRL_BITO_160PCC              0x00000003UL                     /**< Mode 160PCC for I2C_CTRL */
+#define I2C_CTRL_BITO_DEFAULT              (_I2C_CTRL_BITO_DEFAULT << 12)   /**< Shifted mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_BITO_OFF                  (_I2C_CTRL_BITO_OFF << 12)       /**< Shifted mode OFF for I2C_CTRL */
+#define I2C_CTRL_BITO_40PCC                (_I2C_CTRL_BITO_40PCC << 12)     /**< Shifted mode 40PCC for I2C_CTRL */
+#define I2C_CTRL_BITO_80PCC                (_I2C_CTRL_BITO_80PCC << 12)     /**< Shifted mode 80PCC for I2C_CTRL */
+#define I2C_CTRL_BITO_160PCC               (_I2C_CTRL_BITO_160PCC << 12)    /**< Shifted mode 160PCC for I2C_CTRL */
+#define I2C_CTRL_GIBITO                    (0x1UL << 15)                    /**< Go Idle on Bus Idle Timeout  */
+#define _I2C_CTRL_GIBITO_SHIFT             15                               /**< Shift value for I2C_GIBITO */
+#define _I2C_CTRL_GIBITO_MASK              0x8000UL                         /**< Bit mask for I2C_GIBITO */
+#define _I2C_CTRL_GIBITO_DEFAULT           0x00000000UL                     /**< Mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_GIBITO_DEFAULT            (_I2C_CTRL_GIBITO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_CTRL */
+#define _I2C_CTRL_CLTO_SHIFT               16                               /**< Shift value for I2C_CLTO */
+#define _I2C_CTRL_CLTO_MASK                0x70000UL                        /**< Bit mask for I2C_CLTO */
+#define _I2C_CTRL_CLTO_DEFAULT             0x00000000UL                     /**< Mode DEFAULT for I2C_CTRL */
+#define _I2C_CTRL_CLTO_OFF                 0x00000000UL                     /**< Mode OFF for I2C_CTRL */
+#define _I2C_CTRL_CLTO_40PCC               0x00000001UL                     /**< Mode 40PCC for I2C_CTRL */
+#define _I2C_CTRL_CLTO_80PCC               0x00000002UL                     /**< Mode 80PCC for I2C_CTRL */
+#define _I2C_CTRL_CLTO_160PCC              0x00000003UL                     /**< Mode 160PCC for I2C_CTRL */
+#define _I2C_CTRL_CLTO_320PCC              0x00000004UL                     /**< Mode 320PCC for I2C_CTRL */
+#define _I2C_CTRL_CLTO_1024PCC             0x00000005UL                     /**< Mode 1024PCC for I2C_CTRL */
+#define I2C_CTRL_CLTO_DEFAULT              (_I2C_CTRL_CLTO_DEFAULT << 16)   /**< Shifted mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_CLTO_OFF                  (_I2C_CTRL_CLTO_OFF << 16)       /**< Shifted mode OFF for I2C_CTRL */
+#define I2C_CTRL_CLTO_40PCC                (_I2C_CTRL_CLTO_40PCC << 16)     /**< Shifted mode 40PCC for I2C_CTRL */
+#define I2C_CTRL_CLTO_80PCC                (_I2C_CTRL_CLTO_80PCC << 16)     /**< Shifted mode 80PCC for I2C_CTRL */
+#define I2C_CTRL_CLTO_160PCC               (_I2C_CTRL_CLTO_160PCC << 16)    /**< Shifted mode 160PCC for I2C_CTRL */
+#define I2C_CTRL_CLTO_320PCC               (_I2C_CTRL_CLTO_320PCC << 16)    /**< Shifted mode 320PCC for I2C_CTRL */
+#define I2C_CTRL_CLTO_1024PCC              (_I2C_CTRL_CLTO_1024PCC << 16)   /**< Shifted mode 1024PCC for I2C_CTRL */
+
+/* Bit fields for I2C CMD */
+#define _I2C_CMD_RESETVALUE                0x00000000UL                    /**< Default value for I2C_CMD */
+#define _I2C_CMD_MASK                      0x000000FFUL                    /**< Mask for I2C_CMD */
+#define I2C_CMD_START                      (0x1UL << 0)                    /**< Send start condition */
+#define _I2C_CMD_START_SHIFT               0                               /**< Shift value for I2C_START */
+#define _I2C_CMD_START_MASK                0x1UL                           /**< Bit mask for I2C_START */
+#define _I2C_CMD_START_DEFAULT             0x00000000UL                    /**< Mode DEFAULT for I2C_CMD */
+#define I2C_CMD_START_DEFAULT              (_I2C_CMD_START_DEFAULT << 0)   /**< Shifted mode DEFAULT for I2C_CMD */
+#define I2C_CMD_STOP                       (0x1UL << 1)                    /**< Send stop condition */
+#define _I2C_CMD_STOP_SHIFT                1                               /**< Shift value for I2C_STOP */
+#define _I2C_CMD_STOP_MASK                 0x2UL                           /**< Bit mask for I2C_STOP */
+#define _I2C_CMD_STOP_DEFAULT              0x00000000UL                    /**< Mode DEFAULT for I2C_CMD */
+#define I2C_CMD_STOP_DEFAULT               (_I2C_CMD_STOP_DEFAULT << 1)    /**< Shifted mode DEFAULT for I2C_CMD */
+#define I2C_CMD_ACK                        (0x1UL << 2)                    /**< Send ACK */
+#define _I2C_CMD_ACK_SHIFT                 2                               /**< Shift value for I2C_ACK */
+#define _I2C_CMD_ACK_MASK                  0x4UL                           /**< Bit mask for I2C_ACK */
+#define _I2C_CMD_ACK_DEFAULT               0x00000000UL                    /**< Mode DEFAULT for I2C_CMD */
+#define I2C_CMD_ACK_DEFAULT                (_I2C_CMD_ACK_DEFAULT << 2)     /**< Shifted mode DEFAULT for I2C_CMD */
+#define I2C_CMD_NACK                       (0x1UL << 3)                    /**< Send NACK */
+#define _I2C_CMD_NACK_SHIFT                3                               /**< Shift value for I2C_NACK */
+#define _I2C_CMD_NACK_MASK                 0x8UL                           /**< Bit mask for I2C_NACK */
+#define _I2C_CMD_NACK_DEFAULT              0x00000000UL                    /**< Mode DEFAULT for I2C_CMD */
+#define I2C_CMD_NACK_DEFAULT               (_I2C_CMD_NACK_DEFAULT << 3)    /**< Shifted mode DEFAULT for I2C_CMD */
+#define I2C_CMD_CONT                       (0x1UL << 4)                    /**< Continue transmission */
+#define _I2C_CMD_CONT_SHIFT                4                               /**< Shift value for I2C_CONT */
+#define _I2C_CMD_CONT_MASK                 0x10UL                          /**< Bit mask for I2C_CONT */
+#define _I2C_CMD_CONT_DEFAULT              0x00000000UL                    /**< Mode DEFAULT for I2C_CMD */
+#define I2C_CMD_CONT_DEFAULT               (_I2C_CMD_CONT_DEFAULT << 4)    /**< Shifted mode DEFAULT for I2C_CMD */
+#define I2C_CMD_ABORT                      (0x1UL << 5)                    /**< Abort transmission */
+#define _I2C_CMD_ABORT_SHIFT               5                               /**< Shift value for I2C_ABORT */
+#define _I2C_CMD_ABORT_MASK                0x20UL                          /**< Bit mask for I2C_ABORT */
+#define _I2C_CMD_ABORT_DEFAULT             0x00000000UL                    /**< Mode DEFAULT for I2C_CMD */
+#define I2C_CMD_ABORT_DEFAULT              (_I2C_CMD_ABORT_DEFAULT << 5)   /**< Shifted mode DEFAULT for I2C_CMD */
+#define I2C_CMD_CLEARTX                    (0x1UL << 6)                    /**< Clear TX */
+#define _I2C_CMD_CLEARTX_SHIFT             6                               /**< Shift value for I2C_CLEARTX */
+#define _I2C_CMD_CLEARTX_MASK              0x40UL                          /**< Bit mask for I2C_CLEARTX */
+#define _I2C_CMD_CLEARTX_DEFAULT           0x00000000UL                    /**< Mode DEFAULT for I2C_CMD */
+#define I2C_CMD_CLEARTX_DEFAULT            (_I2C_CMD_CLEARTX_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CMD */
+#define I2C_CMD_CLEARPC                    (0x1UL << 7)                    /**< Clear Pending Commands */
+#define _I2C_CMD_CLEARPC_SHIFT             7                               /**< Shift value for I2C_CLEARPC */
+#define _I2C_CMD_CLEARPC_MASK              0x80UL                          /**< Bit mask for I2C_CLEARPC */
+#define _I2C_CMD_CLEARPC_DEFAULT           0x00000000UL                    /**< Mode DEFAULT for I2C_CMD */
+#define I2C_CMD_CLEARPC_DEFAULT            (_I2C_CMD_CLEARPC_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_CMD */
+
+/* Bit fields for I2C STATE */
+#define _I2C_STATE_RESETVALUE              0x00000001UL                          /**< Default value for I2C_STATE */
+#define _I2C_STATE_MASK                    0x000000FFUL                          /**< Mask for I2C_STATE */
+#define I2C_STATE_BUSY                     (0x1UL << 0)                          /**< Bus Busy */
+#define _I2C_STATE_BUSY_SHIFT              0                                     /**< Shift value for I2C_BUSY */
+#define _I2C_STATE_BUSY_MASK               0x1UL                                 /**< Bit mask for I2C_BUSY */
+#define _I2C_STATE_BUSY_DEFAULT            0x00000001UL                          /**< Mode DEFAULT for I2C_STATE */
+#define I2C_STATE_BUSY_DEFAULT             (_I2C_STATE_BUSY_DEFAULT << 0)        /**< Shifted mode DEFAULT for I2C_STATE */
+#define I2C_STATE_MASTER                   (0x1UL << 1)                          /**< Master */
+#define _I2C_STATE_MASTER_SHIFT            1                                     /**< Shift value for I2C_MASTER */
+#define _I2C_STATE_MASTER_MASK             0x2UL                                 /**< Bit mask for I2C_MASTER */
+#define _I2C_STATE_MASTER_DEFAULT          0x00000000UL                          /**< Mode DEFAULT for I2C_STATE */
+#define I2C_STATE_MASTER_DEFAULT           (_I2C_STATE_MASTER_DEFAULT << 1)      /**< Shifted mode DEFAULT for I2C_STATE */
+#define I2C_STATE_TRANSMITTER              (0x1UL << 2)                          /**< Transmitter */
+#define _I2C_STATE_TRANSMITTER_SHIFT       2                                     /**< Shift value for I2C_TRANSMITTER */
+#define _I2C_STATE_TRANSMITTER_MASK        0x4UL                                 /**< Bit mask for I2C_TRANSMITTER */
+#define _I2C_STATE_TRANSMITTER_DEFAULT     0x00000000UL                          /**< Mode DEFAULT for I2C_STATE */
+#define I2C_STATE_TRANSMITTER_DEFAULT      (_I2C_STATE_TRANSMITTER_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATE */
+#define I2C_STATE_NACKED                   (0x1UL << 3)                          /**< Nack Received */
+#define _I2C_STATE_NACKED_SHIFT            3                                     /**< Shift value for I2C_NACKED */
+#define _I2C_STATE_NACKED_MASK             0x8UL                                 /**< Bit mask for I2C_NACKED */
+#define _I2C_STATE_NACKED_DEFAULT          0x00000000UL                          /**< Mode DEFAULT for I2C_STATE */
+#define I2C_STATE_NACKED_DEFAULT           (_I2C_STATE_NACKED_DEFAULT << 3)      /**< Shifted mode DEFAULT for I2C_STATE */
+#define I2C_STATE_BUSHOLD                  (0x1UL << 4)                          /**< Bus Held */
+#define _I2C_STATE_BUSHOLD_SHIFT           4                                     /**< Shift value for I2C_BUSHOLD */
+#define _I2C_STATE_BUSHOLD_MASK            0x10UL                                /**< Bit mask for I2C_BUSHOLD */
+#define _I2C_STATE_BUSHOLD_DEFAULT         0x00000000UL                          /**< Mode DEFAULT for I2C_STATE */
+#define I2C_STATE_BUSHOLD_DEFAULT          (_I2C_STATE_BUSHOLD_DEFAULT << 4)     /**< Shifted mode DEFAULT for I2C_STATE */
+#define _I2C_STATE_STATE_SHIFT             5                                     /**< Shift value for I2C_STATE */
+#define _I2C_STATE_STATE_MASK              0xE0UL                                /**< Bit mask for I2C_STATE */
+#define _I2C_STATE_STATE_DEFAULT           0x00000000UL                          /**< Mode DEFAULT for I2C_STATE */
+#define _I2C_STATE_STATE_IDLE              0x00000000UL                          /**< Mode IDLE for I2C_STATE */
+#define _I2C_STATE_STATE_WAIT              0x00000001UL                          /**< Mode WAIT for I2C_STATE */
+#define _I2C_STATE_STATE_START             0x00000002UL                          /**< Mode START for I2C_STATE */
+#define _I2C_STATE_STATE_ADDR              0x00000003UL                          /**< Mode ADDR for I2C_STATE */
+#define _I2C_STATE_STATE_ADDRACK           0x00000004UL                          /**< Mode ADDRACK for I2C_STATE */
+#define _I2C_STATE_STATE_DATA              0x00000005UL                          /**< Mode DATA for I2C_STATE */
+#define _I2C_STATE_STATE_DATAACK           0x00000006UL                          /**< Mode DATAACK for I2C_STATE */
+#define I2C_STATE_STATE_DEFAULT            (_I2C_STATE_STATE_DEFAULT << 5)       /**< Shifted mode DEFAULT for I2C_STATE */
+#define I2C_STATE_STATE_IDLE               (_I2C_STATE_STATE_IDLE << 5)          /**< Shifted mode IDLE for I2C_STATE */
+#define I2C_STATE_STATE_WAIT               (_I2C_STATE_STATE_WAIT << 5)          /**< Shifted mode WAIT for I2C_STATE */
+#define I2C_STATE_STATE_START              (_I2C_STATE_STATE_START << 5)         /**< Shifted mode START for I2C_STATE */
+#define I2C_STATE_STATE_ADDR               (_I2C_STATE_STATE_ADDR << 5)          /**< Shifted mode ADDR for I2C_STATE */
+#define I2C_STATE_STATE_ADDRACK            (_I2C_STATE_STATE_ADDRACK << 5)       /**< Shifted mode ADDRACK for I2C_STATE */
+#define I2C_STATE_STATE_DATA               (_I2C_STATE_STATE_DATA << 5)          /**< Shifted mode DATA for I2C_STATE */
+#define I2C_STATE_STATE_DATAACK            (_I2C_STATE_STATE_DATAACK << 5)       /**< Shifted mode DATAACK for I2C_STATE */
+
+/* Bit fields for I2C STATUS */
+#define _I2C_STATUS_RESETVALUE             0x00000080UL                       /**< Default value for I2C_STATUS */
+#define _I2C_STATUS_MASK                   0x000003FFUL                       /**< Mask for I2C_STATUS */
+#define I2C_STATUS_PSTART                  (0x1UL << 0)                       /**< Pending START */
+#define _I2C_STATUS_PSTART_SHIFT           0                                  /**< Shift value for I2C_PSTART */
+#define _I2C_STATUS_PSTART_MASK            0x1UL                              /**< Bit mask for I2C_PSTART */
+#define _I2C_STATUS_PSTART_DEFAULT         0x00000000UL                       /**< Mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_PSTART_DEFAULT          (_I2C_STATUS_PSTART_DEFAULT << 0)  /**< Shifted mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_PSTOP                   (0x1UL << 1)                       /**< Pending STOP */
+#define _I2C_STATUS_PSTOP_SHIFT            1                                  /**< Shift value for I2C_PSTOP */
+#define _I2C_STATUS_PSTOP_MASK             0x2UL                              /**< Bit mask for I2C_PSTOP */
+#define _I2C_STATUS_PSTOP_DEFAULT          0x00000000UL                       /**< Mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_PSTOP_DEFAULT           (_I2C_STATUS_PSTOP_DEFAULT << 1)   /**< Shifted mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_PACK                    (0x1UL << 2)                       /**< Pending ACK */
+#define _I2C_STATUS_PACK_SHIFT             2                                  /**< Shift value for I2C_PACK */
+#define _I2C_STATUS_PACK_MASK              0x4UL                              /**< Bit mask for I2C_PACK */
+#define _I2C_STATUS_PACK_DEFAULT           0x00000000UL                       /**< Mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_PACK_DEFAULT            (_I2C_STATUS_PACK_DEFAULT << 2)    /**< Shifted mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_PNACK                   (0x1UL << 3)                       /**< Pending NACK */
+#define _I2C_STATUS_PNACK_SHIFT            3                                  /**< Shift value for I2C_PNACK */
+#define _I2C_STATUS_PNACK_MASK             0x8UL                              /**< Bit mask for I2C_PNACK */
+#define _I2C_STATUS_PNACK_DEFAULT          0x00000000UL                       /**< Mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_PNACK_DEFAULT           (_I2C_STATUS_PNACK_DEFAULT << 3)   /**< Shifted mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_PCONT                   (0x1UL << 4)                       /**< Pending continue */
+#define _I2C_STATUS_PCONT_SHIFT            4                                  /**< Shift value for I2C_PCONT */
+#define _I2C_STATUS_PCONT_MASK             0x10UL                             /**< Bit mask for I2C_PCONT */
+#define _I2C_STATUS_PCONT_DEFAULT          0x00000000UL                       /**< Mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_PCONT_DEFAULT           (_I2C_STATUS_PCONT_DEFAULT << 4)   /**< Shifted mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_PABORT                  (0x1UL << 5)                       /**< Pending abort */
+#define _I2C_STATUS_PABORT_SHIFT           5                                  /**< Shift value for I2C_PABORT */
+#define _I2C_STATUS_PABORT_MASK            0x20UL                             /**< Bit mask for I2C_PABORT */
+#define _I2C_STATUS_PABORT_DEFAULT         0x00000000UL                       /**< Mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_PABORT_DEFAULT          (_I2C_STATUS_PABORT_DEFAULT << 5)  /**< Shifted mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_TXC                     (0x1UL << 6)                       /**< TX Complete */
+#define _I2C_STATUS_TXC_SHIFT              6                                  /**< Shift value for I2C_TXC */
+#define _I2C_STATUS_TXC_MASK               0x40UL                             /**< Bit mask for I2C_TXC */
+#define _I2C_STATUS_TXC_DEFAULT            0x00000000UL                       /**< Mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_TXC_DEFAULT             (_I2C_STATUS_TXC_DEFAULT << 6)     /**< Shifted mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_TXBL                    (0x1UL << 7)                       /**< TX Buffer Level */
+#define _I2C_STATUS_TXBL_SHIFT             7                                  /**< Shift value for I2C_TXBL */
+#define _I2C_STATUS_TXBL_MASK              0x80UL                             /**< Bit mask for I2C_TXBL */
+#define _I2C_STATUS_TXBL_DEFAULT           0x00000001UL                       /**< Mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_TXBL_DEFAULT            (_I2C_STATUS_TXBL_DEFAULT << 7)    /**< Shifted mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_RXDATAV                 (0x1UL << 8)                       /**< RX Data Valid */
+#define _I2C_STATUS_RXDATAV_SHIFT          8                                  /**< Shift value for I2C_RXDATAV */
+#define _I2C_STATUS_RXDATAV_MASK           0x100UL                            /**< Bit mask for I2C_RXDATAV */
+#define _I2C_STATUS_RXDATAV_DEFAULT        0x00000000UL                       /**< Mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_RXDATAV_DEFAULT         (_I2C_STATUS_RXDATAV_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_RXFULL                  (0x1UL << 9)                       /**< RX FIFO Full */
+#define _I2C_STATUS_RXFULL_SHIFT           9                                  /**< Shift value for I2C_RXFULL */
+#define _I2C_STATUS_RXFULL_MASK            0x200UL                            /**< Bit mask for I2C_RXFULL */
+#define _I2C_STATUS_RXFULL_DEFAULT         0x00000000UL                       /**< Mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_RXFULL_DEFAULT          (_I2C_STATUS_RXFULL_DEFAULT << 9)  /**< Shifted mode DEFAULT for I2C_STATUS */
+
+/* Bit fields for I2C CLKDIV */
+#define _I2C_CLKDIV_RESETVALUE             0x00000000UL                   /**< Default value for I2C_CLKDIV */
+#define _I2C_CLKDIV_MASK                   0x000001FFUL                   /**< Mask for I2C_CLKDIV */
+#define _I2C_CLKDIV_DIV_SHIFT              0                              /**< Shift value for I2C_DIV */
+#define _I2C_CLKDIV_DIV_MASK               0x1FFUL                        /**< Bit mask for I2C_DIV */
+#define _I2C_CLKDIV_DIV_DEFAULT            0x00000000UL                   /**< Mode DEFAULT for I2C_CLKDIV */
+#define I2C_CLKDIV_DIV_DEFAULT             (_I2C_CLKDIV_DIV_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CLKDIV */
+
+/* Bit fields for I2C SADDR */
+#define _I2C_SADDR_RESETVALUE              0x00000000UL                   /**< Default value for I2C_SADDR */
+#define _I2C_SADDR_MASK                    0x000000FEUL                   /**< Mask for I2C_SADDR */
+#define _I2C_SADDR_ADDR_SHIFT              1                              /**< Shift value for I2C_ADDR */
+#define _I2C_SADDR_ADDR_MASK               0xFEUL                         /**< Bit mask for I2C_ADDR */
+#define _I2C_SADDR_ADDR_DEFAULT            0x00000000UL                   /**< Mode DEFAULT for I2C_SADDR */
+#define I2C_SADDR_ADDR_DEFAULT             (_I2C_SADDR_ADDR_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDR */
+
+/* Bit fields for I2C SADDRMASK */
+#define _I2C_SADDRMASK_RESETVALUE          0x00000000UL                       /**< Default value for I2C_SADDRMASK */
+#define _I2C_SADDRMASK_MASK                0x000000FEUL                       /**< Mask for I2C_SADDRMASK */
+#define _I2C_SADDRMASK_MASK_SHIFT          1                                  /**< Shift value for I2C_MASK */
+#define _I2C_SADDRMASK_MASK_MASK           0xFEUL                             /**< Bit mask for I2C_MASK */
+#define _I2C_SADDRMASK_MASK_DEFAULT        0x00000000UL                       /**< Mode DEFAULT for I2C_SADDRMASK */
+#define I2C_SADDRMASK_MASK_DEFAULT         (_I2C_SADDRMASK_MASK_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDRMASK */
+
+/* Bit fields for I2C RXDATA */
+#define _I2C_RXDATA_RESETVALUE             0x00000000UL                      /**< Default value for I2C_RXDATA */
+#define _I2C_RXDATA_MASK                   0x000000FFUL                      /**< Mask for I2C_RXDATA */
+#define _I2C_RXDATA_RXDATA_SHIFT           0                                 /**< Shift value for I2C_RXDATA */
+#define _I2C_RXDATA_RXDATA_MASK            0xFFUL                            /**< Bit mask for I2C_RXDATA */
+#define _I2C_RXDATA_RXDATA_DEFAULT         0x00000000UL                      /**< Mode DEFAULT for I2C_RXDATA */
+#define I2C_RXDATA_RXDATA_DEFAULT          (_I2C_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATA */
+
+/* Bit fields for I2C RXDOUBLE */
+#define _I2C_RXDOUBLE_RESETVALUE           0x00000000UL                         /**< Default value for I2C_RXDOUBLE */
+#define _I2C_RXDOUBLE_MASK                 0x0000FFFFUL                         /**< Mask for I2C_RXDOUBLE */
+#define _I2C_RXDOUBLE_RXDATA0_SHIFT        0                                    /**< Shift value for I2C_RXDATA0 */
+#define _I2C_RXDOUBLE_RXDATA0_MASK         0xFFUL                               /**< Bit mask for I2C_RXDATA0 */
+#define _I2C_RXDOUBLE_RXDATA0_DEFAULT      0x00000000UL                         /**< Mode DEFAULT for I2C_RXDOUBLE */
+#define I2C_RXDOUBLE_RXDATA0_DEFAULT       (_I2C_RXDOUBLE_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDOUBLE */
+#define _I2C_RXDOUBLE_RXDATA1_SHIFT        8                                    /**< Shift value for I2C_RXDATA1 */
+#define _I2C_RXDOUBLE_RXDATA1_MASK         0xFF00UL                             /**< Bit mask for I2C_RXDATA1 */
+#define _I2C_RXDOUBLE_RXDATA1_DEFAULT      0x00000000UL                         /**< Mode DEFAULT for I2C_RXDOUBLE */
+#define I2C_RXDOUBLE_RXDATA1_DEFAULT       (_I2C_RXDOUBLE_RXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_RXDOUBLE */
+
+/* Bit fields for I2C RXDATAP */
+#define _I2C_RXDATAP_RESETVALUE            0x00000000UL                        /**< Default value for I2C_RXDATAP */
+#define _I2C_RXDATAP_MASK                  0x000000FFUL                        /**< Mask for I2C_RXDATAP */
+#define _I2C_RXDATAP_RXDATAP_SHIFT         0                                   /**< Shift value for I2C_RXDATAP */
+#define _I2C_RXDATAP_RXDATAP_MASK          0xFFUL                              /**< Bit mask for I2C_RXDATAP */
+#define _I2C_RXDATAP_RXDATAP_DEFAULT       0x00000000UL                        /**< Mode DEFAULT for I2C_RXDATAP */
+#define I2C_RXDATAP_RXDATAP_DEFAULT        (_I2C_RXDATAP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATAP */
+
+/* Bit fields for I2C RXDOUBLEP */
+#define _I2C_RXDOUBLEP_RESETVALUE          0x00000000UL                           /**< Default value for I2C_RXDOUBLEP */
+#define _I2C_RXDOUBLEP_MASK                0x0000FFFFUL                           /**< Mask for I2C_RXDOUBLEP */
+#define _I2C_RXDOUBLEP_RXDATAP0_SHIFT      0                                      /**< Shift value for I2C_RXDATAP0 */
+#define _I2C_RXDOUBLEP_RXDATAP0_MASK       0xFFUL                                 /**< Bit mask for I2C_RXDATAP0 */
+#define _I2C_RXDOUBLEP_RXDATAP0_DEFAULT    0x00000000UL                           /**< Mode DEFAULT for I2C_RXDOUBLEP */
+#define I2C_RXDOUBLEP_RXDATAP0_DEFAULT     (_I2C_RXDOUBLEP_RXDATAP0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDOUBLEP */
+#define _I2C_RXDOUBLEP_RXDATAP1_SHIFT      8                                      /**< Shift value for I2C_RXDATAP1 */
+#define _I2C_RXDOUBLEP_RXDATAP1_MASK       0xFF00UL                               /**< Bit mask for I2C_RXDATAP1 */
+#define _I2C_RXDOUBLEP_RXDATAP1_DEFAULT    0x00000000UL                           /**< Mode DEFAULT for I2C_RXDOUBLEP */
+#define I2C_RXDOUBLEP_RXDATAP1_DEFAULT     (_I2C_RXDOUBLEP_RXDATAP1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_RXDOUBLEP */
+
+/* Bit fields for I2C TXDATA */
+#define _I2C_TXDATA_RESETVALUE             0x00000000UL                      /**< Default value for I2C_TXDATA */
+#define _I2C_TXDATA_MASK                   0x000000FFUL                      /**< Mask for I2C_TXDATA */
+#define _I2C_TXDATA_TXDATA_SHIFT           0                                 /**< Shift value for I2C_TXDATA */
+#define _I2C_TXDATA_TXDATA_MASK            0xFFUL                            /**< Bit mask for I2C_TXDATA */
+#define _I2C_TXDATA_TXDATA_DEFAULT         0x00000000UL                      /**< Mode DEFAULT for I2C_TXDATA */
+#define I2C_TXDATA_TXDATA_DEFAULT          (_I2C_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_TXDATA */
+
+/* Bit fields for I2C TXDOUBLE */
+#define _I2C_TXDOUBLE_RESETVALUE           0x00000000UL                         /**< Default value for I2C_TXDOUBLE */
+#define _I2C_TXDOUBLE_MASK                 0x0000FFFFUL                         /**< Mask for I2C_TXDOUBLE */
+#define _I2C_TXDOUBLE_TXDATA0_SHIFT        0                                    /**< Shift value for I2C_TXDATA0 */
+#define _I2C_TXDOUBLE_TXDATA0_MASK         0xFFUL                               /**< Bit mask for I2C_TXDATA0 */
+#define _I2C_TXDOUBLE_TXDATA0_DEFAULT      0x00000000UL                         /**< Mode DEFAULT for I2C_TXDOUBLE */
+#define I2C_TXDOUBLE_TXDATA0_DEFAULT       (_I2C_TXDOUBLE_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_TXDOUBLE */
+#define _I2C_TXDOUBLE_TXDATA1_SHIFT        8                                    /**< Shift value for I2C_TXDATA1 */
+#define _I2C_TXDOUBLE_TXDATA1_MASK         0xFF00UL                             /**< Bit mask for I2C_TXDATA1 */
+#define _I2C_TXDOUBLE_TXDATA1_DEFAULT      0x00000000UL                         /**< Mode DEFAULT for I2C_TXDOUBLE */
+#define I2C_TXDOUBLE_TXDATA1_DEFAULT       (_I2C_TXDOUBLE_TXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_TXDOUBLE */
+
+/* Bit fields for I2C IF */
+#define _I2C_IF_RESETVALUE                 0x00000010UL                    /**< Default value for I2C_IF */
+#define _I2C_IF_MASK                       0x0007FFFFUL                    /**< Mask for I2C_IF */
+#define I2C_IF_START                       (0x1UL << 0)                    /**< START condition Interrupt Flag */
+#define _I2C_IF_START_SHIFT                0                               /**< Shift value for I2C_START */
+#define _I2C_IF_START_MASK                 0x1UL                           /**< Bit mask for I2C_START */
+#define _I2C_IF_START_DEFAULT              0x00000000UL                    /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_START_DEFAULT               (_I2C_IF_START_DEFAULT << 0)    /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_RSTART                      (0x1UL << 1)                    /**< Repeated START condition Interrupt Flag */
+#define _I2C_IF_RSTART_SHIFT               1                               /**< Shift value for I2C_RSTART */
+#define _I2C_IF_RSTART_MASK                0x2UL                           /**< Bit mask for I2C_RSTART */
+#define _I2C_IF_RSTART_DEFAULT             0x00000000UL                    /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_RSTART_DEFAULT              (_I2C_IF_RSTART_DEFAULT << 1)   /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_ADDR                        (0x1UL << 2)                    /**< Address Interrupt Flag */
+#define _I2C_IF_ADDR_SHIFT                 2                               /**< Shift value for I2C_ADDR */
+#define _I2C_IF_ADDR_MASK                  0x4UL                           /**< Bit mask for I2C_ADDR */
+#define _I2C_IF_ADDR_DEFAULT               0x00000000UL                    /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_ADDR_DEFAULT                (_I2C_IF_ADDR_DEFAULT << 2)     /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_TXC                         (0x1UL << 3)                    /**< Transfer Completed Interrupt Flag */
+#define _I2C_IF_TXC_SHIFT                  3                               /**< Shift value for I2C_TXC */
+#define _I2C_IF_TXC_MASK                   0x8UL                           /**< Bit mask for I2C_TXC */
+#define _I2C_IF_TXC_DEFAULT                0x00000000UL                    /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_TXC_DEFAULT                 (_I2C_IF_TXC_DEFAULT << 3)      /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_TXBL                        (0x1UL << 4)                    /**< Transmit Buffer Level Interrupt Flag */
+#define _I2C_IF_TXBL_SHIFT                 4                               /**< Shift value for I2C_TXBL */
+#define _I2C_IF_TXBL_MASK                  0x10UL                          /**< Bit mask for I2C_TXBL */
+#define _I2C_IF_TXBL_DEFAULT               0x00000000UL                    /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_TXBL_DEFAULT                (_I2C_IF_TXBL_DEFAULT << 4)     /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_RXDATAV                     (0x1UL << 5)                    /**< Receive Data Valid Interrupt Flag */
+#define _I2C_IF_RXDATAV_SHIFT              5                               /**< Shift value for I2C_RXDATAV */
+#define _I2C_IF_RXDATAV_MASK               0x20UL                          /**< Bit mask for I2C_RXDATAV */
+#define _I2C_IF_RXDATAV_DEFAULT            0x00000000UL                    /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_RXDATAV_DEFAULT             (_I2C_IF_RXDATAV_DEFAULT << 5)  /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_ACK                         (0x1UL << 6)                    /**< Acknowledge Received Interrupt Flag */
+#define _I2C_IF_ACK_SHIFT                  6                               /**< Shift value for I2C_ACK */
+#define _I2C_IF_ACK_MASK                   0x40UL                          /**< Bit mask for I2C_ACK */
+#define _I2C_IF_ACK_DEFAULT                0x00000000UL                    /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_ACK_DEFAULT                 (_I2C_IF_ACK_DEFAULT << 6)      /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_NACK                        (0x1UL << 7)                    /**< Not Acknowledge Received Interrupt Flag */
+#define _I2C_IF_NACK_SHIFT                 7                               /**< Shift value for I2C_NACK */
+#define _I2C_IF_NACK_MASK                  0x80UL                          /**< Bit mask for I2C_NACK */
+#define _I2C_IF_NACK_DEFAULT               0x00000000UL                    /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_NACK_DEFAULT                (_I2C_IF_NACK_DEFAULT << 7)     /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_MSTOP                       (0x1UL << 8)                    /**< Master STOP Condition Interrupt Flag */
+#define _I2C_IF_MSTOP_SHIFT                8                               /**< Shift value for I2C_MSTOP */
+#define _I2C_IF_MSTOP_MASK                 0x100UL                         /**< Bit mask for I2C_MSTOP */
+#define _I2C_IF_MSTOP_DEFAULT              0x00000000UL                    /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_MSTOP_DEFAULT               (_I2C_IF_MSTOP_DEFAULT << 8)    /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_ARBLOST                     (0x1UL << 9)                    /**< Arbitration Lost Interrupt Flag */
+#define _I2C_IF_ARBLOST_SHIFT              9                               /**< Shift value for I2C_ARBLOST */
+#define _I2C_IF_ARBLOST_MASK               0x200UL                         /**< Bit mask for I2C_ARBLOST */
+#define _I2C_IF_ARBLOST_DEFAULT            0x00000000UL                    /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_ARBLOST_DEFAULT             (_I2C_IF_ARBLOST_DEFAULT << 9)  /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_BUSERR                      (0x1UL << 10)                   /**< Bus Error Interrupt Flag */
+#define _I2C_IF_BUSERR_SHIFT               10                              /**< Shift value for I2C_BUSERR */
+#define _I2C_IF_BUSERR_MASK                0x400UL                         /**< Bit mask for I2C_BUSERR */
+#define _I2C_IF_BUSERR_DEFAULT             0x00000000UL                    /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_BUSERR_DEFAULT              (_I2C_IF_BUSERR_DEFAULT << 10)  /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_BUSHOLD                     (0x1UL << 11)                   /**< Bus Held Interrupt Flag */
+#define _I2C_IF_BUSHOLD_SHIFT              11                              /**< Shift value for I2C_BUSHOLD */
+#define _I2C_IF_BUSHOLD_MASK               0x800UL                         /**< Bit mask for I2C_BUSHOLD */
+#define _I2C_IF_BUSHOLD_DEFAULT            0x00000000UL                    /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_BUSHOLD_DEFAULT             (_I2C_IF_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_TXOF                        (0x1UL << 12)                   /**< Transmit Buffer Overflow Interrupt Flag */
+#define _I2C_IF_TXOF_SHIFT                 12                              /**< Shift value for I2C_TXOF */
+#define _I2C_IF_TXOF_MASK                  0x1000UL                        /**< Bit mask for I2C_TXOF */
+#define _I2C_IF_TXOF_DEFAULT               0x00000000UL                    /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_TXOF_DEFAULT                (_I2C_IF_TXOF_DEFAULT << 12)    /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_RXUF                        (0x1UL << 13)                   /**< Receive Buffer Underflow Interrupt Flag */
+#define _I2C_IF_RXUF_SHIFT                 13                              /**< Shift value for I2C_RXUF */
+#define _I2C_IF_RXUF_MASK                  0x2000UL                        /**< Bit mask for I2C_RXUF */
+#define _I2C_IF_RXUF_DEFAULT               0x00000000UL                    /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_RXUF_DEFAULT                (_I2C_IF_RXUF_DEFAULT << 13)    /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_BITO                        (0x1UL << 14)                   /**< Bus Idle Timeout Interrupt Flag */
+#define _I2C_IF_BITO_SHIFT                 14                              /**< Shift value for I2C_BITO */
+#define _I2C_IF_BITO_MASK                  0x4000UL                        /**< Bit mask for I2C_BITO */
+#define _I2C_IF_BITO_DEFAULT               0x00000000UL                    /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_BITO_DEFAULT                (_I2C_IF_BITO_DEFAULT << 14)    /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_CLTO                        (0x1UL << 15)                   /**< Clock Low Timeout Interrupt Flag */
+#define _I2C_IF_CLTO_SHIFT                 15                              /**< Shift value for I2C_CLTO */
+#define _I2C_IF_CLTO_MASK                  0x8000UL                        /**< Bit mask for I2C_CLTO */
+#define _I2C_IF_CLTO_DEFAULT               0x00000000UL                    /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_CLTO_DEFAULT                (_I2C_IF_CLTO_DEFAULT << 15)    /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_SSTOP                       (0x1UL << 16)                   /**< Slave STOP condition Interrupt Flag */
+#define _I2C_IF_SSTOP_SHIFT                16                              /**< Shift value for I2C_SSTOP */
+#define _I2C_IF_SSTOP_MASK                 0x10000UL                       /**< Bit mask for I2C_SSTOP */
+#define _I2C_IF_SSTOP_DEFAULT              0x00000000UL                    /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_SSTOP_DEFAULT               (_I2C_IF_SSTOP_DEFAULT << 16)   /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_RXFULL                      (0x1UL << 17)                   /**< Receive Buffer Full Interrupt Flag */
+#define _I2C_IF_RXFULL_SHIFT               17                              /**< Shift value for I2C_RXFULL */
+#define _I2C_IF_RXFULL_MASK                0x20000UL                       /**< Bit mask for I2C_RXFULL */
+#define _I2C_IF_RXFULL_DEFAULT             0x00000000UL                    /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_RXFULL_DEFAULT              (_I2C_IF_RXFULL_DEFAULT << 17)  /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_CLERR                       (0x1UL << 18)                   /**< Clock Low Error Interrupt Flag */
+#define _I2C_IF_CLERR_SHIFT                18                              /**< Shift value for I2C_CLERR */
+#define _I2C_IF_CLERR_MASK                 0x40000UL                       /**< Bit mask for I2C_CLERR */
+#define _I2C_IF_CLERR_DEFAULT              0x00000000UL                    /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_CLERR_DEFAULT               (_I2C_IF_CLERR_DEFAULT << 18)   /**< Shifted mode DEFAULT for I2C_IF */
+
+/* Bit fields for I2C IFS */
+#define _I2C_IFS_RESETVALUE                0x00000000UL                     /**< Default value for I2C_IFS */
+#define _I2C_IFS_MASK                      0x0007FFCFUL                     /**< Mask for I2C_IFS */
+#define I2C_IFS_START                      (0x1UL << 0)                     /**< Set START Interrupt Flag */
+#define _I2C_IFS_START_SHIFT               0                                /**< Shift value for I2C_START */
+#define _I2C_IFS_START_MASK                0x1UL                            /**< Bit mask for I2C_START */
+#define _I2C_IFS_START_DEFAULT             0x00000000UL                     /**< Mode DEFAULT for I2C_IFS */
+#define I2C_IFS_START_DEFAULT              (_I2C_IFS_START_DEFAULT << 0)    /**< Shifted mode DEFAULT for I2C_IFS */
+#define I2C_IFS_RSTART                     (0x1UL << 1)                     /**< Set RSTART Interrupt Flag */
+#define _I2C_IFS_RSTART_SHIFT              1                                /**< Shift value for I2C_RSTART */
+#define _I2C_IFS_RSTART_MASK               0x2UL                            /**< Bit mask for I2C_RSTART */
+#define _I2C_IFS_RSTART_DEFAULT            0x00000000UL                     /**< Mode DEFAULT for I2C_IFS */
+#define I2C_IFS_RSTART_DEFAULT             (_I2C_IFS_RSTART_DEFAULT << 1)   /**< Shifted mode DEFAULT for I2C_IFS */
+#define I2C_IFS_ADDR                       (0x1UL << 2)                     /**< Set ADDR Interrupt Flag */
+#define _I2C_IFS_ADDR_SHIFT                2                                /**< Shift value for I2C_ADDR */
+#define _I2C_IFS_ADDR_MASK                 0x4UL                            /**< Bit mask for I2C_ADDR */
+#define _I2C_IFS_ADDR_DEFAULT              0x00000000UL                     /**< Mode DEFAULT for I2C_IFS */
+#define I2C_IFS_ADDR_DEFAULT               (_I2C_IFS_ADDR_DEFAULT << 2)     /**< Shifted mode DEFAULT for I2C_IFS */
+#define I2C_IFS_TXC                        (0x1UL << 3)                     /**< Set TXC Interrupt Flag */
+#define _I2C_IFS_TXC_SHIFT                 3                                /**< Shift value for I2C_TXC */
+#define _I2C_IFS_TXC_MASK                  0x8UL                            /**< Bit mask for I2C_TXC */
+#define _I2C_IFS_TXC_DEFAULT               0x00000000UL                     /**< Mode DEFAULT for I2C_IFS */
+#define I2C_IFS_TXC_DEFAULT                (_I2C_IFS_TXC_DEFAULT << 3)      /**< Shifted mode DEFAULT for I2C_IFS */
+#define I2C_IFS_ACK                        (0x1UL << 6)                     /**< Set ACK Interrupt Flag */
+#define _I2C_IFS_ACK_SHIFT                 6                                /**< Shift value for I2C_ACK */
+#define _I2C_IFS_ACK_MASK                  0x40UL                           /**< Bit mask for I2C_ACK */
+#define _I2C_IFS_ACK_DEFAULT               0x00000000UL                     /**< Mode DEFAULT for I2C_IFS */
+#define I2C_IFS_ACK_DEFAULT                (_I2C_IFS_ACK_DEFAULT << 6)      /**< Shifted mode DEFAULT for I2C_IFS */
+#define I2C_IFS_NACK                       (0x1UL << 7)                     /**< Set NACK Interrupt Flag */
+#define _I2C_IFS_NACK_SHIFT                7                                /**< Shift value for I2C_NACK */
+#define _I2C_IFS_NACK_MASK                 0x80UL                           /**< Bit mask for I2C_NACK */
+#define _I2C_IFS_NACK_DEFAULT              0x00000000UL                     /**< Mode DEFAULT for I2C_IFS */
+#define I2C_IFS_NACK_DEFAULT               (_I2C_IFS_NACK_DEFAULT << 7)     /**< Shifted mode DEFAULT for I2C_IFS */
+#define I2C_IFS_MSTOP                      (0x1UL << 8)                     /**< Set MSTOP Interrupt Flag */
+#define _I2C_IFS_MSTOP_SHIFT               8                                /**< Shift value for I2C_MSTOP */
+#define _I2C_IFS_MSTOP_MASK                0x100UL                          /**< Bit mask for I2C_MSTOP */
+#define _I2C_IFS_MSTOP_DEFAULT             0x00000000UL                     /**< Mode DEFAULT for I2C_IFS */
+#define I2C_IFS_MSTOP_DEFAULT              (_I2C_IFS_MSTOP_DEFAULT << 8)    /**< Shifted mode DEFAULT for I2C_IFS */
+#define I2C_IFS_ARBLOST                    (0x1UL << 9)                     /**< Set ARBLOST Interrupt Flag */
+#define _I2C_IFS_ARBLOST_SHIFT             9                                /**< Shift value for I2C_ARBLOST */
+#define _I2C_IFS_ARBLOST_MASK              0x200UL                          /**< Bit mask for I2C_ARBLOST */
+#define _I2C_IFS_ARBLOST_DEFAULT           0x00000000UL                     /**< Mode DEFAULT for I2C_IFS */
+#define I2C_IFS_ARBLOST_DEFAULT            (_I2C_IFS_ARBLOST_DEFAULT << 9)  /**< Shifted mode DEFAULT for I2C_IFS */
+#define I2C_IFS_BUSERR                     (0x1UL << 10)                    /**< Set BUSERR Interrupt Flag */
+#define _I2C_IFS_BUSERR_SHIFT              10                               /**< Shift value for I2C_BUSERR */
+#define _I2C_IFS_BUSERR_MASK               0x400UL                          /**< Bit mask for I2C_BUSERR */
+#define _I2C_IFS_BUSERR_DEFAULT            0x00000000UL                     /**< Mode DEFAULT for I2C_IFS */
+#define I2C_IFS_BUSERR_DEFAULT             (_I2C_IFS_BUSERR_DEFAULT << 10)  /**< Shifted mode DEFAULT for I2C_IFS */
+#define I2C_IFS_BUSHOLD                    (0x1UL << 11)                    /**< Set BUSHOLD Interrupt Flag */
+#define _I2C_IFS_BUSHOLD_SHIFT             11                               /**< Shift value for I2C_BUSHOLD */
+#define _I2C_IFS_BUSHOLD_MASK              0x800UL                          /**< Bit mask for I2C_BUSHOLD */
+#define _I2C_IFS_BUSHOLD_DEFAULT           0x00000000UL                     /**< Mode DEFAULT for I2C_IFS */
+#define I2C_IFS_BUSHOLD_DEFAULT            (_I2C_IFS_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IFS */
+#define I2C_IFS_TXOF                       (0x1UL << 12)                    /**< Set TXOF Interrupt Flag */
+#define _I2C_IFS_TXOF_SHIFT                12                               /**< Shift value for I2C_TXOF */
+#define _I2C_IFS_TXOF_MASK                 0x1000UL                         /**< Bit mask for I2C_TXOF */
+#define _I2C_IFS_TXOF_DEFAULT              0x00000000UL                     /**< Mode DEFAULT for I2C_IFS */
+#define I2C_IFS_TXOF_DEFAULT               (_I2C_IFS_TXOF_DEFAULT << 12)    /**< Shifted mode DEFAULT for I2C_IFS */
+#define I2C_IFS_RXUF                       (0x1UL << 13)                    /**< Set RXUF Interrupt Flag */
+#define _I2C_IFS_RXUF_SHIFT                13                               /**< Shift value for I2C_RXUF */
+#define _I2C_IFS_RXUF_MASK                 0x2000UL                         /**< Bit mask for I2C_RXUF */
+#define _I2C_IFS_RXUF_DEFAULT              0x00000000UL                     /**< Mode DEFAULT for I2C_IFS */
+#define I2C_IFS_RXUF_DEFAULT               (_I2C_IFS_RXUF_DEFAULT << 13)    /**< Shifted mode DEFAULT for I2C_IFS */
+#define I2C_IFS_BITO                       (0x1UL << 14)                    /**< Set BITO Interrupt Flag */
+#define _I2C_IFS_BITO_SHIFT                14                               /**< Shift value for I2C_BITO */
+#define _I2C_IFS_BITO_MASK                 0x4000UL                         /**< Bit mask for I2C_BITO */
+#define _I2C_IFS_BITO_DEFAULT              0x00000000UL                     /**< Mode DEFAULT for I2C_IFS */
+#define I2C_IFS_BITO_DEFAULT               (_I2C_IFS_BITO_DEFAULT << 14)    /**< Shifted mode DEFAULT for I2C_IFS */
+#define I2C_IFS_CLTO                       (0x1UL << 15)                    /**< Set CLTO Interrupt Flag */
+#define _I2C_IFS_CLTO_SHIFT                15                               /**< Shift value for I2C_CLTO */
+#define _I2C_IFS_CLTO_MASK                 0x8000UL                         /**< Bit mask for I2C_CLTO */
+#define _I2C_IFS_CLTO_DEFAULT              0x00000000UL                     /**< Mode DEFAULT for I2C_IFS */
+#define I2C_IFS_CLTO_DEFAULT               (_I2C_IFS_CLTO_DEFAULT << 15)    /**< Shifted mode DEFAULT for I2C_IFS */
+#define I2C_IFS_SSTOP                      (0x1UL << 16)                    /**< Set SSTOP Interrupt Flag */
+#define _I2C_IFS_SSTOP_SHIFT               16                               /**< Shift value for I2C_SSTOP */
+#define _I2C_IFS_SSTOP_MASK                0x10000UL                        /**< Bit mask for I2C_SSTOP */
+#define _I2C_IFS_SSTOP_DEFAULT             0x00000000UL                     /**< Mode DEFAULT for I2C_IFS */
+#define I2C_IFS_SSTOP_DEFAULT              (_I2C_IFS_SSTOP_DEFAULT << 16)   /**< Shifted mode DEFAULT for I2C_IFS */
+#define I2C_IFS_RXFULL                     (0x1UL << 17)                    /**< Set RXFULL Interrupt Flag */
+#define _I2C_IFS_RXFULL_SHIFT              17                               /**< Shift value for I2C_RXFULL */
+#define _I2C_IFS_RXFULL_MASK               0x20000UL                        /**< Bit mask for I2C_RXFULL */
+#define _I2C_IFS_RXFULL_DEFAULT            0x00000000UL                     /**< Mode DEFAULT for I2C_IFS */
+#define I2C_IFS_RXFULL_DEFAULT             (_I2C_IFS_RXFULL_DEFAULT << 17)  /**< Shifted mode DEFAULT for I2C_IFS */
+#define I2C_IFS_CLERR                      (0x1UL << 18)                    /**< Set CLERR Interrupt Flag */
+#define _I2C_IFS_CLERR_SHIFT               18                               /**< Shift value for I2C_CLERR */
+#define _I2C_IFS_CLERR_MASK                0x40000UL                        /**< Bit mask for I2C_CLERR */
+#define _I2C_IFS_CLERR_DEFAULT             0x00000000UL                     /**< Mode DEFAULT for I2C_IFS */
+#define I2C_IFS_CLERR_DEFAULT              (_I2C_IFS_CLERR_DEFAULT << 18)   /**< Shifted mode DEFAULT for I2C_IFS */
+
+/* Bit fields for I2C IFC */
+#define _I2C_IFC_RESETVALUE                0x00000000UL                     /**< Default value for I2C_IFC */
+#define _I2C_IFC_MASK                      0x0007FFCFUL                     /**< Mask for I2C_IFC */
+#define I2C_IFC_START                      (0x1UL << 0)                     /**< Clear START Interrupt Flag */
+#define _I2C_IFC_START_SHIFT               0                                /**< Shift value for I2C_START */
+#define _I2C_IFC_START_MASK                0x1UL                            /**< Bit mask for I2C_START */
+#define _I2C_IFC_START_DEFAULT             0x00000000UL                     /**< Mode DEFAULT for I2C_IFC */
+#define I2C_IFC_START_DEFAULT              (_I2C_IFC_START_DEFAULT << 0)    /**< Shifted mode DEFAULT for I2C_IFC */
+#define I2C_IFC_RSTART                     (0x1UL << 1)                     /**< Clear RSTART Interrupt Flag */
+#define _I2C_IFC_RSTART_SHIFT              1                                /**< Shift value for I2C_RSTART */
+#define _I2C_IFC_RSTART_MASK               0x2UL                            /**< Bit mask for I2C_RSTART */
+#define _I2C_IFC_RSTART_DEFAULT            0x00000000UL                     /**< Mode DEFAULT for I2C_IFC */
+#define I2C_IFC_RSTART_DEFAULT             (_I2C_IFC_RSTART_DEFAULT << 1)   /**< Shifted mode DEFAULT for I2C_IFC */
+#define I2C_IFC_ADDR                       (0x1UL << 2)                     /**< Clear ADDR Interrupt Flag */
+#define _I2C_IFC_ADDR_SHIFT                2                                /**< Shift value for I2C_ADDR */
+#define _I2C_IFC_ADDR_MASK                 0x4UL                            /**< Bit mask for I2C_ADDR */
+#define _I2C_IFC_ADDR_DEFAULT              0x00000000UL                     /**< Mode DEFAULT for I2C_IFC */
+#define I2C_IFC_ADDR_DEFAULT               (_I2C_IFC_ADDR_DEFAULT << 2)     /**< Shifted mode DEFAULT for I2C_IFC */
+#define I2C_IFC_TXC                        (0x1UL << 3)                     /**< Clear TXC Interrupt Flag */
+#define _I2C_IFC_TXC_SHIFT                 3                                /**< Shift value for I2C_TXC */
+#define _I2C_IFC_TXC_MASK                  0x8UL                            /**< Bit mask for I2C_TXC */
+#define _I2C_IFC_TXC_DEFAULT               0x00000000UL                     /**< Mode DEFAULT for I2C_IFC */
+#define I2C_IFC_TXC_DEFAULT                (_I2C_IFC_TXC_DEFAULT << 3)      /**< Shifted mode DEFAULT for I2C_IFC */
+#define I2C_IFC_ACK                        (0x1UL << 6)                     /**< Clear ACK Interrupt Flag */
+#define _I2C_IFC_ACK_SHIFT                 6                                /**< Shift value for I2C_ACK */
+#define _I2C_IFC_ACK_MASK                  0x40UL                           /**< Bit mask for I2C_ACK */
+#define _I2C_IFC_ACK_DEFAULT               0x00000000UL                     /**< Mode DEFAULT for I2C_IFC */
+#define I2C_IFC_ACK_DEFAULT                (_I2C_IFC_ACK_DEFAULT << 6)      /**< Shifted mode DEFAULT for I2C_IFC */
+#define I2C_IFC_NACK                       (0x1UL << 7)                     /**< Clear NACK Interrupt Flag */
+#define _I2C_IFC_NACK_SHIFT                7                                /**< Shift value for I2C_NACK */
+#define _I2C_IFC_NACK_MASK                 0x80UL                           /**< Bit mask for I2C_NACK */
+#define _I2C_IFC_NACK_DEFAULT              0x00000000UL                     /**< Mode DEFAULT for I2C_IFC */
+#define I2C_IFC_NACK_DEFAULT               (_I2C_IFC_NACK_DEFAULT << 7)     /**< Shifted mode DEFAULT for I2C_IFC */
+#define I2C_IFC_MSTOP                      (0x1UL << 8)                     /**< Clear MSTOP Interrupt Flag */
+#define _I2C_IFC_MSTOP_SHIFT               8                                /**< Shift value for I2C_MSTOP */
+#define _I2C_IFC_MSTOP_MASK                0x100UL                          /**< Bit mask for I2C_MSTOP */
+#define _I2C_IFC_MSTOP_DEFAULT             0x00000000UL                     /**< Mode DEFAULT for I2C_IFC */
+#define I2C_IFC_MSTOP_DEFAULT              (_I2C_IFC_MSTOP_DEFAULT << 8)    /**< Shifted mode DEFAULT for I2C_IFC */
+#define I2C_IFC_ARBLOST                    (0x1UL << 9)                     /**< Clear ARBLOST Interrupt Flag */
+#define _I2C_IFC_ARBLOST_SHIFT             9                                /**< Shift value for I2C_ARBLOST */
+#define _I2C_IFC_ARBLOST_MASK              0x200UL                          /**< Bit mask for I2C_ARBLOST */
+#define _I2C_IFC_ARBLOST_DEFAULT           0x00000000UL                     /**< Mode DEFAULT for I2C_IFC */
+#define I2C_IFC_ARBLOST_DEFAULT            (_I2C_IFC_ARBLOST_DEFAULT << 9)  /**< Shifted mode DEFAULT for I2C_IFC */
+#define I2C_IFC_BUSERR                     (0x1UL << 10)                    /**< Clear BUSERR Interrupt Flag */
+#define _I2C_IFC_BUSERR_SHIFT              10                               /**< Shift value for I2C_BUSERR */
+#define _I2C_IFC_BUSERR_MASK               0x400UL                          /**< Bit mask for I2C_BUSERR */
+#define _I2C_IFC_BUSERR_DEFAULT            0x00000000UL                     /**< Mode DEFAULT for I2C_IFC */
+#define I2C_IFC_BUSERR_DEFAULT             (_I2C_IFC_BUSERR_DEFAULT << 10)  /**< Shifted mode DEFAULT for I2C_IFC */
+#define I2C_IFC_BUSHOLD                    (0x1UL << 11)                    /**< Clear BUSHOLD Interrupt Flag */
+#define _I2C_IFC_BUSHOLD_SHIFT             11                               /**< Shift value for I2C_BUSHOLD */
+#define _I2C_IFC_BUSHOLD_MASK              0x800UL                          /**< Bit mask for I2C_BUSHOLD */
+#define _I2C_IFC_BUSHOLD_DEFAULT           0x00000000UL                     /**< Mode DEFAULT for I2C_IFC */
+#define I2C_IFC_BUSHOLD_DEFAULT            (_I2C_IFC_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IFC */
+#define I2C_IFC_TXOF                       (0x1UL << 12)                    /**< Clear TXOF Interrupt Flag */
+#define _I2C_IFC_TXOF_SHIFT                12                               /**< Shift value for I2C_TXOF */
+#define _I2C_IFC_TXOF_MASK                 0x1000UL                         /**< Bit mask for I2C_TXOF */
+#define _I2C_IFC_TXOF_DEFAULT              0x00000000UL                     /**< Mode DEFAULT for I2C_IFC */
+#define I2C_IFC_TXOF_DEFAULT               (_I2C_IFC_TXOF_DEFAULT << 12)    /**< Shifted mode DEFAULT for I2C_IFC */
+#define I2C_IFC_RXUF                       (0x1UL << 13)                    /**< Clear RXUF Interrupt Flag */
+#define _I2C_IFC_RXUF_SHIFT                13                               /**< Shift value for I2C_RXUF */
+#define _I2C_IFC_RXUF_MASK                 0x2000UL                         /**< Bit mask for I2C_RXUF */
+#define _I2C_IFC_RXUF_DEFAULT              0x00000000UL                     /**< Mode DEFAULT for I2C_IFC */
+#define I2C_IFC_RXUF_DEFAULT               (_I2C_IFC_RXUF_DEFAULT << 13)    /**< Shifted mode DEFAULT for I2C_IFC */
+#define I2C_IFC_BITO                       (0x1UL << 14)                    /**< Clear BITO Interrupt Flag */
+#define _I2C_IFC_BITO_SHIFT                14                               /**< Shift value for I2C_BITO */
+#define _I2C_IFC_BITO_MASK                 0x4000UL                         /**< Bit mask for I2C_BITO */
+#define _I2C_IFC_BITO_DEFAULT              0x00000000UL                     /**< Mode DEFAULT for I2C_IFC */
+#define I2C_IFC_BITO_DEFAULT               (_I2C_IFC_BITO_DEFAULT << 14)    /**< Shifted mode DEFAULT for I2C_IFC */
+#define I2C_IFC_CLTO                       (0x1UL << 15)                    /**< Clear CLTO Interrupt Flag */
+#define _I2C_IFC_CLTO_SHIFT                15                               /**< Shift value for I2C_CLTO */
+#define _I2C_IFC_CLTO_MASK                 0x8000UL                         /**< Bit mask for I2C_CLTO */
+#define _I2C_IFC_CLTO_DEFAULT              0x00000000UL                     /**< Mode DEFAULT for I2C_IFC */
+#define I2C_IFC_CLTO_DEFAULT               (_I2C_IFC_CLTO_DEFAULT << 15)    /**< Shifted mode DEFAULT for I2C_IFC */
+#define I2C_IFC_SSTOP                      (0x1UL << 16)                    /**< Clear SSTOP Interrupt Flag */
+#define _I2C_IFC_SSTOP_SHIFT               16                               /**< Shift value for I2C_SSTOP */
+#define _I2C_IFC_SSTOP_MASK                0x10000UL                        /**< Bit mask for I2C_SSTOP */
+#define _I2C_IFC_SSTOP_DEFAULT             0x00000000UL                     /**< Mode DEFAULT for I2C_IFC */
+#define I2C_IFC_SSTOP_DEFAULT              (_I2C_IFC_SSTOP_DEFAULT << 16)   /**< Shifted mode DEFAULT for I2C_IFC */
+#define I2C_IFC_RXFULL                     (0x1UL << 17)                    /**< Clear RXFULL Interrupt Flag */
+#define _I2C_IFC_RXFULL_SHIFT              17                               /**< Shift value for I2C_RXFULL */
+#define _I2C_IFC_RXFULL_MASK               0x20000UL                        /**< Bit mask for I2C_RXFULL */
+#define _I2C_IFC_RXFULL_DEFAULT            0x00000000UL                     /**< Mode DEFAULT for I2C_IFC */
+#define I2C_IFC_RXFULL_DEFAULT             (_I2C_IFC_RXFULL_DEFAULT << 17)  /**< Shifted mode DEFAULT for I2C_IFC */
+#define I2C_IFC_CLERR                      (0x1UL << 18)                    /**< Clear CLERR Interrupt Flag */
+#define _I2C_IFC_CLERR_SHIFT               18                               /**< Shift value for I2C_CLERR */
+#define _I2C_IFC_CLERR_MASK                0x40000UL                        /**< Bit mask for I2C_CLERR */
+#define _I2C_IFC_CLERR_DEFAULT             0x00000000UL                     /**< Mode DEFAULT for I2C_IFC */
+#define I2C_IFC_CLERR_DEFAULT              (_I2C_IFC_CLERR_DEFAULT << 18)   /**< Shifted mode DEFAULT for I2C_IFC */
+
+/* Bit fields for I2C IEN */
+#define _I2C_IEN_RESETVALUE                0x00000000UL                     /**< Default value for I2C_IEN */
+#define _I2C_IEN_MASK                      0x0007FFFFUL                     /**< Mask for I2C_IEN */
+#define I2C_IEN_START                      (0x1UL << 0)                     /**< START Interrupt Enable */
+#define _I2C_IEN_START_SHIFT               0                                /**< Shift value for I2C_START */
+#define _I2C_IEN_START_MASK                0x1UL                            /**< Bit mask for I2C_START */
+#define _I2C_IEN_START_DEFAULT             0x00000000UL                     /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_START_DEFAULT              (_I2C_IEN_START_DEFAULT << 0)    /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_RSTART                     (0x1UL << 1)                     /**< RSTART Interrupt Enable */
+#define _I2C_IEN_RSTART_SHIFT              1                                /**< Shift value for I2C_RSTART */
+#define _I2C_IEN_RSTART_MASK               0x2UL                            /**< Bit mask for I2C_RSTART */
+#define _I2C_IEN_RSTART_DEFAULT            0x00000000UL                     /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_RSTART_DEFAULT             (_I2C_IEN_RSTART_DEFAULT << 1)   /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_ADDR                       (0x1UL << 2)                     /**< ADDR Interrupt Enable */
+#define _I2C_IEN_ADDR_SHIFT                2                                /**< Shift value for I2C_ADDR */
+#define _I2C_IEN_ADDR_MASK                 0x4UL                            /**< Bit mask for I2C_ADDR */
+#define _I2C_IEN_ADDR_DEFAULT              0x00000000UL                     /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_ADDR_DEFAULT               (_I2C_IEN_ADDR_DEFAULT << 2)     /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_TXC                        (0x1UL << 3)                     /**< TXC Interrupt Enable */
+#define _I2C_IEN_TXC_SHIFT                 3                                /**< Shift value for I2C_TXC */
+#define _I2C_IEN_TXC_MASK                  0x8UL                            /**< Bit mask for I2C_TXC */
+#define _I2C_IEN_TXC_DEFAULT               0x00000000UL                     /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_TXC_DEFAULT                (_I2C_IEN_TXC_DEFAULT << 3)      /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_TXBL                       (0x1UL << 4)                     /**< TXBL Interrupt Enable */
+#define _I2C_IEN_TXBL_SHIFT                4                                /**< Shift value for I2C_TXBL */
+#define _I2C_IEN_TXBL_MASK                 0x10UL                           /**< Bit mask for I2C_TXBL */
+#define _I2C_IEN_TXBL_DEFAULT              0x00000000UL                     /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_TXBL_DEFAULT               (_I2C_IEN_TXBL_DEFAULT << 4)     /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_RXDATAV                    (0x1UL << 5)                     /**< RXDATAV Interrupt Enable */
+#define _I2C_IEN_RXDATAV_SHIFT             5                                /**< Shift value for I2C_RXDATAV */
+#define _I2C_IEN_RXDATAV_MASK              0x20UL                           /**< Bit mask for I2C_RXDATAV */
+#define _I2C_IEN_RXDATAV_DEFAULT           0x00000000UL                     /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_RXDATAV_DEFAULT            (_I2C_IEN_RXDATAV_DEFAULT << 5)  /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_ACK                        (0x1UL << 6)                     /**< ACK Interrupt Enable */
+#define _I2C_IEN_ACK_SHIFT                 6                                /**< Shift value for I2C_ACK */
+#define _I2C_IEN_ACK_MASK                  0x40UL                           /**< Bit mask for I2C_ACK */
+#define _I2C_IEN_ACK_DEFAULT               0x00000000UL                     /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_ACK_DEFAULT                (_I2C_IEN_ACK_DEFAULT << 6)      /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_NACK                       (0x1UL << 7)                     /**< NACK Interrupt Enable */
+#define _I2C_IEN_NACK_SHIFT                7                                /**< Shift value for I2C_NACK */
+#define _I2C_IEN_NACK_MASK                 0x80UL                           /**< Bit mask for I2C_NACK */
+#define _I2C_IEN_NACK_DEFAULT              0x00000000UL                     /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_NACK_DEFAULT               (_I2C_IEN_NACK_DEFAULT << 7)     /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_MSTOP                      (0x1UL << 8)                     /**< MSTOP Interrupt Enable */
+#define _I2C_IEN_MSTOP_SHIFT               8                                /**< Shift value for I2C_MSTOP */
+#define _I2C_IEN_MSTOP_MASK                0x100UL                          /**< Bit mask for I2C_MSTOP */
+#define _I2C_IEN_MSTOP_DEFAULT             0x00000000UL                     /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_MSTOP_DEFAULT              (_I2C_IEN_MSTOP_DEFAULT << 8)    /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_ARBLOST                    (0x1UL << 9)                     /**< ARBLOST Interrupt Enable */
+#define _I2C_IEN_ARBLOST_SHIFT             9                                /**< Shift value for I2C_ARBLOST */
+#define _I2C_IEN_ARBLOST_MASK              0x200UL                          /**< Bit mask for I2C_ARBLOST */
+#define _I2C_IEN_ARBLOST_DEFAULT           0x00000000UL                     /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_ARBLOST_DEFAULT            (_I2C_IEN_ARBLOST_DEFAULT << 9)  /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_BUSERR                     (0x1UL << 10)                    /**< BUSERR Interrupt Enable */
+#define _I2C_IEN_BUSERR_SHIFT              10                               /**< Shift value for I2C_BUSERR */
+#define _I2C_IEN_BUSERR_MASK               0x400UL                          /**< Bit mask for I2C_BUSERR */
+#define _I2C_IEN_BUSERR_DEFAULT            0x00000000UL                     /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_BUSERR_DEFAULT             (_I2C_IEN_BUSERR_DEFAULT << 10)  /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_BUSHOLD                    (0x1UL << 11)                    /**< BUSHOLD Interrupt Enable */
+#define _I2C_IEN_BUSHOLD_SHIFT             11                               /**< Shift value for I2C_BUSHOLD */
+#define _I2C_IEN_BUSHOLD_MASK              0x800UL                          /**< Bit mask for I2C_BUSHOLD */
+#define _I2C_IEN_BUSHOLD_DEFAULT           0x00000000UL                     /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_BUSHOLD_DEFAULT            (_I2C_IEN_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_TXOF                       (0x1UL << 12)                    /**< TXOF Interrupt Enable */
+#define _I2C_IEN_TXOF_SHIFT                12                               /**< Shift value for I2C_TXOF */
+#define _I2C_IEN_TXOF_MASK                 0x1000UL                         /**< Bit mask for I2C_TXOF */
+#define _I2C_IEN_TXOF_DEFAULT              0x00000000UL                     /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_TXOF_DEFAULT               (_I2C_IEN_TXOF_DEFAULT << 12)    /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_RXUF                       (0x1UL << 13)                    /**< RXUF Interrupt Enable */
+#define _I2C_IEN_RXUF_SHIFT                13                               /**< Shift value for I2C_RXUF */
+#define _I2C_IEN_RXUF_MASK                 0x2000UL                         /**< Bit mask for I2C_RXUF */
+#define _I2C_IEN_RXUF_DEFAULT              0x00000000UL                     /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_RXUF_DEFAULT               (_I2C_IEN_RXUF_DEFAULT << 13)    /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_BITO                       (0x1UL << 14)                    /**< BITO Interrupt Enable */
+#define _I2C_IEN_BITO_SHIFT                14                               /**< Shift value for I2C_BITO */
+#define _I2C_IEN_BITO_MASK                 0x4000UL                         /**< Bit mask for I2C_BITO */
+#define _I2C_IEN_BITO_DEFAULT              0x00000000UL                     /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_BITO_DEFAULT               (_I2C_IEN_BITO_DEFAULT << 14)    /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_CLTO                       (0x1UL << 15)                    /**< CLTO Interrupt Enable */
+#define _I2C_IEN_CLTO_SHIFT                15                               /**< Shift value for I2C_CLTO */
+#define _I2C_IEN_CLTO_MASK                 0x8000UL                         /**< Bit mask for I2C_CLTO */
+#define _I2C_IEN_CLTO_DEFAULT              0x00000000UL                     /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_CLTO_DEFAULT               (_I2C_IEN_CLTO_DEFAULT << 15)    /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_SSTOP                      (0x1UL << 16)                    /**< SSTOP Interrupt Enable */
+#define _I2C_IEN_SSTOP_SHIFT               16                               /**< Shift value for I2C_SSTOP */
+#define _I2C_IEN_SSTOP_MASK                0x10000UL                        /**< Bit mask for I2C_SSTOP */
+#define _I2C_IEN_SSTOP_DEFAULT             0x00000000UL                     /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_SSTOP_DEFAULT              (_I2C_IEN_SSTOP_DEFAULT << 16)   /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_RXFULL                     (0x1UL << 17)                    /**< RXFULL Interrupt Enable */
+#define _I2C_IEN_RXFULL_SHIFT              17                               /**< Shift value for I2C_RXFULL */
+#define _I2C_IEN_RXFULL_MASK               0x20000UL                        /**< Bit mask for I2C_RXFULL */
+#define _I2C_IEN_RXFULL_DEFAULT            0x00000000UL                     /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_RXFULL_DEFAULT             (_I2C_IEN_RXFULL_DEFAULT << 17)  /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_CLERR                      (0x1UL << 18)                    /**< CLERR Interrupt Enable */
+#define _I2C_IEN_CLERR_SHIFT               18                               /**< Shift value for I2C_CLERR */
+#define _I2C_IEN_CLERR_MASK                0x40000UL                        /**< Bit mask for I2C_CLERR */
+#define _I2C_IEN_CLERR_DEFAULT             0x00000000UL                     /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_CLERR_DEFAULT              (_I2C_IEN_CLERR_DEFAULT << 18)   /**< Shifted mode DEFAULT for I2C_IEN */
+
+/* Bit fields for I2C ROUTEPEN */
+#define _I2C_ROUTEPEN_RESETVALUE           0x00000000UL                        /**< Default value for I2C_ROUTEPEN */
+#define _I2C_ROUTEPEN_MASK                 0x00000003UL                        /**< Mask for I2C_ROUTEPEN */
+#define I2C_ROUTEPEN_SDAPEN                (0x1UL << 0)                        /**< SDA Pin Enable */
+#define _I2C_ROUTEPEN_SDAPEN_SHIFT         0                                   /**< Shift value for I2C_SDAPEN */
+#define _I2C_ROUTEPEN_SDAPEN_MASK          0x1UL                               /**< Bit mask for I2C_SDAPEN */
+#define _I2C_ROUTEPEN_SDAPEN_DEFAULT       0x00000000UL                        /**< Mode DEFAULT for I2C_ROUTEPEN */
+#define I2C_ROUTEPEN_SDAPEN_DEFAULT        (_I2C_ROUTEPEN_SDAPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_ROUTEPEN */
+#define I2C_ROUTEPEN_SCLPEN                (0x1UL << 1)                        /**< SCL Pin Enable */
+#define _I2C_ROUTEPEN_SCLPEN_SHIFT         1                                   /**< Shift value for I2C_SCLPEN */
+#define _I2C_ROUTEPEN_SCLPEN_MASK          0x2UL                               /**< Bit mask for I2C_SCLPEN */
+#define _I2C_ROUTEPEN_SCLPEN_DEFAULT       0x00000000UL                        /**< Mode DEFAULT for I2C_ROUTEPEN */
+#define I2C_ROUTEPEN_SCLPEN_DEFAULT        (_I2C_ROUTEPEN_SCLPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_ROUTEPEN */
+
+/* Bit fields for I2C ROUTELOC0 */
+#define _I2C_ROUTELOC0_RESETVALUE          0x00000000UL                         /**< Default value for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_MASK                0x00001F1FUL                         /**< Mask for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SDALOC_SHIFT        0                                    /**< Shift value for I2C_SDALOC */
+#define _I2C_ROUTELOC0_SDALOC_MASK         0x1FUL                               /**< Bit mask for I2C_SDALOC */
+#define _I2C_ROUTELOC0_SDALOC_LOC0         0x00000000UL                         /**< Mode LOC0 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SDALOC_DEFAULT      0x00000000UL                         /**< Mode DEFAULT for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SDALOC_LOC1         0x00000001UL                         /**< Mode LOC1 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SDALOC_LOC2         0x00000002UL                         /**< Mode LOC2 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SDALOC_LOC3         0x00000003UL                         /**< Mode LOC3 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SDALOC_LOC4         0x00000004UL                         /**< Mode LOC4 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SDALOC_LOC5         0x00000005UL                         /**< Mode LOC5 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SDALOC_LOC6         0x00000006UL                         /**< Mode LOC6 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SDALOC_LOC7         0x00000007UL                         /**< Mode LOC7 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SDALOC_LOC8         0x00000008UL                         /**< Mode LOC8 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SDALOC_LOC9         0x00000009UL                         /**< Mode LOC9 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SDALOC_LOC10        0x0000000AUL                         /**< Mode LOC10 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SDALOC_LOC11        0x0000000BUL                         /**< Mode LOC11 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SDALOC_LOC12        0x0000000CUL                         /**< Mode LOC12 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SDALOC_LOC13        0x0000000DUL                         /**< Mode LOC13 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SDALOC_LOC14        0x0000000EUL                         /**< Mode LOC14 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SDALOC_LOC15        0x0000000FUL                         /**< Mode LOC15 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SDALOC_LOC16        0x00000010UL                         /**< Mode LOC16 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SDALOC_LOC17        0x00000011UL                         /**< Mode LOC17 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SDALOC_LOC18        0x00000012UL                         /**< Mode LOC18 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SDALOC_LOC19        0x00000013UL                         /**< Mode LOC19 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SDALOC_LOC20        0x00000014UL                         /**< Mode LOC20 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SDALOC_LOC21        0x00000015UL                         /**< Mode LOC21 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SDALOC_LOC22        0x00000016UL                         /**< Mode LOC22 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SDALOC_LOC23        0x00000017UL                         /**< Mode LOC23 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SDALOC_LOC24        0x00000018UL                         /**< Mode LOC24 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SDALOC_LOC25        0x00000019UL                         /**< Mode LOC25 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SDALOC_LOC26        0x0000001AUL                         /**< Mode LOC26 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SDALOC_LOC27        0x0000001BUL                         /**< Mode LOC27 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SDALOC_LOC28        0x0000001CUL                         /**< Mode LOC28 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SDALOC_LOC29        0x0000001DUL                         /**< Mode LOC29 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SDALOC_LOC30        0x0000001EUL                         /**< Mode LOC30 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SDALOC_LOC31        0x0000001FUL                         /**< Mode LOC31 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SDALOC_LOC0          (_I2C_ROUTELOC0_SDALOC_LOC0 << 0)    /**< Shifted mode LOC0 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SDALOC_DEFAULT       (_I2C_ROUTELOC0_SDALOC_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SDALOC_LOC1          (_I2C_ROUTELOC0_SDALOC_LOC1 << 0)    /**< Shifted mode LOC1 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SDALOC_LOC2          (_I2C_ROUTELOC0_SDALOC_LOC2 << 0)    /**< Shifted mode LOC2 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SDALOC_LOC3          (_I2C_ROUTELOC0_SDALOC_LOC3 << 0)    /**< Shifted mode LOC3 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SDALOC_LOC4          (_I2C_ROUTELOC0_SDALOC_LOC4 << 0)    /**< Shifted mode LOC4 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SDALOC_LOC5          (_I2C_ROUTELOC0_SDALOC_LOC5 << 0)    /**< Shifted mode LOC5 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SDALOC_LOC6          (_I2C_ROUTELOC0_SDALOC_LOC6 << 0)    /**< Shifted mode LOC6 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SDALOC_LOC7          (_I2C_ROUTELOC0_SDALOC_LOC7 << 0)    /**< Shifted mode LOC7 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SDALOC_LOC8          (_I2C_ROUTELOC0_SDALOC_LOC8 << 0)    /**< Shifted mode LOC8 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SDALOC_LOC9          (_I2C_ROUTELOC0_SDALOC_LOC9 << 0)    /**< Shifted mode LOC9 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SDALOC_LOC10         (_I2C_ROUTELOC0_SDALOC_LOC10 << 0)   /**< Shifted mode LOC10 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SDALOC_LOC11         (_I2C_ROUTELOC0_SDALOC_LOC11 << 0)   /**< Shifted mode LOC11 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SDALOC_LOC12         (_I2C_ROUTELOC0_SDALOC_LOC12 << 0)   /**< Shifted mode LOC12 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SDALOC_LOC13         (_I2C_ROUTELOC0_SDALOC_LOC13 << 0)   /**< Shifted mode LOC13 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SDALOC_LOC14         (_I2C_ROUTELOC0_SDALOC_LOC14 << 0)   /**< Shifted mode LOC14 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SDALOC_LOC15         (_I2C_ROUTELOC0_SDALOC_LOC15 << 0)   /**< Shifted mode LOC15 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SDALOC_LOC16         (_I2C_ROUTELOC0_SDALOC_LOC16 << 0)   /**< Shifted mode LOC16 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SDALOC_LOC17         (_I2C_ROUTELOC0_SDALOC_LOC17 << 0)   /**< Shifted mode LOC17 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SDALOC_LOC18         (_I2C_ROUTELOC0_SDALOC_LOC18 << 0)   /**< Shifted mode LOC18 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SDALOC_LOC19         (_I2C_ROUTELOC0_SDALOC_LOC19 << 0)   /**< Shifted mode LOC19 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SDALOC_LOC20         (_I2C_ROUTELOC0_SDALOC_LOC20 << 0)   /**< Shifted mode LOC20 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SDALOC_LOC21         (_I2C_ROUTELOC0_SDALOC_LOC21 << 0)   /**< Shifted mode LOC21 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SDALOC_LOC22         (_I2C_ROUTELOC0_SDALOC_LOC22 << 0)   /**< Shifted mode LOC22 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SDALOC_LOC23         (_I2C_ROUTELOC0_SDALOC_LOC23 << 0)   /**< Shifted mode LOC23 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SDALOC_LOC24         (_I2C_ROUTELOC0_SDALOC_LOC24 << 0)   /**< Shifted mode LOC24 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SDALOC_LOC25         (_I2C_ROUTELOC0_SDALOC_LOC25 << 0)   /**< Shifted mode LOC25 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SDALOC_LOC26         (_I2C_ROUTELOC0_SDALOC_LOC26 << 0)   /**< Shifted mode LOC26 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SDALOC_LOC27         (_I2C_ROUTELOC0_SDALOC_LOC27 << 0)   /**< Shifted mode LOC27 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SDALOC_LOC28         (_I2C_ROUTELOC0_SDALOC_LOC28 << 0)   /**< Shifted mode LOC28 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SDALOC_LOC29         (_I2C_ROUTELOC0_SDALOC_LOC29 << 0)   /**< Shifted mode LOC29 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SDALOC_LOC30         (_I2C_ROUTELOC0_SDALOC_LOC30 << 0)   /**< Shifted mode LOC30 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SDALOC_LOC31         (_I2C_ROUTELOC0_SDALOC_LOC31 << 0)   /**< Shifted mode LOC31 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SCLLOC_SHIFT        8                                    /**< Shift value for I2C_SCLLOC */
+#define _I2C_ROUTELOC0_SCLLOC_MASK         0x1F00UL                             /**< Bit mask for I2C_SCLLOC */
+#define _I2C_ROUTELOC0_SCLLOC_LOC0         0x00000000UL                         /**< Mode LOC0 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SCLLOC_DEFAULT      0x00000000UL                         /**< Mode DEFAULT for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SCLLOC_LOC1         0x00000001UL                         /**< Mode LOC1 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SCLLOC_LOC2         0x00000002UL                         /**< Mode LOC2 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SCLLOC_LOC3         0x00000003UL                         /**< Mode LOC3 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SCLLOC_LOC4         0x00000004UL                         /**< Mode LOC4 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SCLLOC_LOC5         0x00000005UL                         /**< Mode LOC5 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SCLLOC_LOC6         0x00000006UL                         /**< Mode LOC6 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SCLLOC_LOC7         0x00000007UL                         /**< Mode LOC7 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SCLLOC_LOC8         0x00000008UL                         /**< Mode LOC8 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SCLLOC_LOC9         0x00000009UL                         /**< Mode LOC9 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SCLLOC_LOC10        0x0000000AUL                         /**< Mode LOC10 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SCLLOC_LOC11        0x0000000BUL                         /**< Mode LOC11 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SCLLOC_LOC12        0x0000000CUL                         /**< Mode LOC12 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SCLLOC_LOC13        0x0000000DUL                         /**< Mode LOC13 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SCLLOC_LOC14        0x0000000EUL                         /**< Mode LOC14 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SCLLOC_LOC15        0x0000000FUL                         /**< Mode LOC15 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SCLLOC_LOC16        0x00000010UL                         /**< Mode LOC16 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SCLLOC_LOC17        0x00000011UL                         /**< Mode LOC17 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SCLLOC_LOC18        0x00000012UL                         /**< Mode LOC18 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SCLLOC_LOC19        0x00000013UL                         /**< Mode LOC19 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SCLLOC_LOC20        0x00000014UL                         /**< Mode LOC20 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SCLLOC_LOC21        0x00000015UL                         /**< Mode LOC21 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SCLLOC_LOC22        0x00000016UL                         /**< Mode LOC22 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SCLLOC_LOC23        0x00000017UL                         /**< Mode LOC23 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SCLLOC_LOC24        0x00000018UL                         /**< Mode LOC24 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SCLLOC_LOC25        0x00000019UL                         /**< Mode LOC25 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SCLLOC_LOC26        0x0000001AUL                         /**< Mode LOC26 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SCLLOC_LOC27        0x0000001BUL                         /**< Mode LOC27 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SCLLOC_LOC28        0x0000001CUL                         /**< Mode LOC28 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SCLLOC_LOC29        0x0000001DUL                         /**< Mode LOC29 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SCLLOC_LOC30        0x0000001EUL                         /**< Mode LOC30 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SCLLOC_LOC31        0x0000001FUL                         /**< Mode LOC31 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SCLLOC_LOC0          (_I2C_ROUTELOC0_SCLLOC_LOC0 << 8)    /**< Shifted mode LOC0 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SCLLOC_DEFAULT       (_I2C_ROUTELOC0_SCLLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SCLLOC_LOC1          (_I2C_ROUTELOC0_SCLLOC_LOC1 << 8)    /**< Shifted mode LOC1 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SCLLOC_LOC2          (_I2C_ROUTELOC0_SCLLOC_LOC2 << 8)    /**< Shifted mode LOC2 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SCLLOC_LOC3          (_I2C_ROUTELOC0_SCLLOC_LOC3 << 8)    /**< Shifted mode LOC3 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SCLLOC_LOC4          (_I2C_ROUTELOC0_SCLLOC_LOC4 << 8)    /**< Shifted mode LOC4 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SCLLOC_LOC5          (_I2C_ROUTELOC0_SCLLOC_LOC5 << 8)    /**< Shifted mode LOC5 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SCLLOC_LOC6          (_I2C_ROUTELOC0_SCLLOC_LOC6 << 8)    /**< Shifted mode LOC6 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SCLLOC_LOC7          (_I2C_ROUTELOC0_SCLLOC_LOC7 << 8)    /**< Shifted mode LOC7 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SCLLOC_LOC8          (_I2C_ROUTELOC0_SCLLOC_LOC8 << 8)    /**< Shifted mode LOC8 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SCLLOC_LOC9          (_I2C_ROUTELOC0_SCLLOC_LOC9 << 8)    /**< Shifted mode LOC9 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SCLLOC_LOC10         (_I2C_ROUTELOC0_SCLLOC_LOC10 << 8)   /**< Shifted mode LOC10 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SCLLOC_LOC11         (_I2C_ROUTELOC0_SCLLOC_LOC11 << 8)   /**< Shifted mode LOC11 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SCLLOC_LOC12         (_I2C_ROUTELOC0_SCLLOC_LOC12 << 8)   /**< Shifted mode LOC12 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SCLLOC_LOC13         (_I2C_ROUTELOC0_SCLLOC_LOC13 << 8)   /**< Shifted mode LOC13 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SCLLOC_LOC14         (_I2C_ROUTELOC0_SCLLOC_LOC14 << 8)   /**< Shifted mode LOC14 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SCLLOC_LOC15         (_I2C_ROUTELOC0_SCLLOC_LOC15 << 8)   /**< Shifted mode LOC15 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SCLLOC_LOC16         (_I2C_ROUTELOC0_SCLLOC_LOC16 << 8)   /**< Shifted mode LOC16 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SCLLOC_LOC17         (_I2C_ROUTELOC0_SCLLOC_LOC17 << 8)   /**< Shifted mode LOC17 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SCLLOC_LOC18         (_I2C_ROUTELOC0_SCLLOC_LOC18 << 8)   /**< Shifted mode LOC18 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SCLLOC_LOC19         (_I2C_ROUTELOC0_SCLLOC_LOC19 << 8)   /**< Shifted mode LOC19 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SCLLOC_LOC20         (_I2C_ROUTELOC0_SCLLOC_LOC20 << 8)   /**< Shifted mode LOC20 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SCLLOC_LOC21         (_I2C_ROUTELOC0_SCLLOC_LOC21 << 8)   /**< Shifted mode LOC21 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SCLLOC_LOC22         (_I2C_ROUTELOC0_SCLLOC_LOC22 << 8)   /**< Shifted mode LOC22 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SCLLOC_LOC23         (_I2C_ROUTELOC0_SCLLOC_LOC23 << 8)   /**< Shifted mode LOC23 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SCLLOC_LOC24         (_I2C_ROUTELOC0_SCLLOC_LOC24 << 8)   /**< Shifted mode LOC24 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SCLLOC_LOC25         (_I2C_ROUTELOC0_SCLLOC_LOC25 << 8)   /**< Shifted mode LOC25 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SCLLOC_LOC26         (_I2C_ROUTELOC0_SCLLOC_LOC26 << 8)   /**< Shifted mode LOC26 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SCLLOC_LOC27         (_I2C_ROUTELOC0_SCLLOC_LOC27 << 8)   /**< Shifted mode LOC27 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SCLLOC_LOC28         (_I2C_ROUTELOC0_SCLLOC_LOC28 << 8)   /**< Shifted mode LOC28 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SCLLOC_LOC29         (_I2C_ROUTELOC0_SCLLOC_LOC29 << 8)   /**< Shifted mode LOC29 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SCLLOC_LOC30         (_I2C_ROUTELOC0_SCLLOC_LOC30 << 8)   /**< Shifted mode LOC30 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SCLLOC_LOC31         (_I2C_ROUTELOC0_SCLLOC_LOC31 << 8)   /**< Shifted mode LOC31 for I2C_ROUTELOC0 */
+
+/** @} End of group EFM32PG1B_I2C */
+/** @} End of group Parts */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG_STK3401/efm32pg1b_idac.h	Fri Jan 15 07:45:16 2016 +0000
@@ -0,0 +1,332 @@
+/**************************************************************************//**
+ * @file efm32pg1b_idac.h
+ * @brief EFM32PG1B_IDAC register and bit field definitions
+ * @version 4.2.0
+ ******************************************************************************
+ * @section License
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ ******************************************************************************
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software.@n
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.@n
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is
+ * providing the Software "AS IS", with no express or implied warranties of any
+ * kind, including, but not limited to, any implied warranties of
+ * merchantability or fitness for any particular purpose or warranties against
+ * infringement of any proprietary rights of a third party.
+ *
+ * Silicon Laboratories, Inc. will not be liable for any consequential,
+ * incidental, or special damages, or any other relief, or for any claim by
+ * any third party, arising from your use of this Software.
+ *
+ *****************************************************************************/
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFM32PG1B_IDAC
+ * @{
+ * @brief EFM32PG1B_IDAC Register Declaration
+ *****************************************************************************/
+typedef struct
+{
+  __IO uint32_t CTRL;          /**< Control Register  */
+  __IO uint32_t CURPROG;       /**< Current Programming Register  */
+  uint32_t      RESERVED0[1];  /**< Reserved for future use **/
+  __IO uint32_t DUTYCONFIG;    /**< Duty Cycle Configauration Register  */
+
+  uint32_t      RESERVED1[2];  /**< Reserved for future use **/
+  __I uint32_t  STATUS;        /**< Status Register  */
+  uint32_t      RESERVED2[1];  /**< Reserved for future use **/
+  __I uint32_t  IF;            /**< Interrupt Flag Register  */
+  __IO uint32_t IFS;           /**< Interrupt Flag Set Register  */
+  __IO uint32_t IFC;           /**< Interrupt Flag Clear Register  */
+  __IO uint32_t IEN;           /**< Interrupt Enable Register  */
+  uint32_t      RESERVED3[1];  /**< Reserved for future use **/
+  __I uint32_t  APORTREQ;      /**< APORT Request Status Register  */
+  __I uint32_t  APORTCONFLICT; /**< APORT Request Status Register  */
+} IDAC_TypeDef;                /** @} */
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B_IDAC_BitFields
+ * @{
+ *****************************************************************************/
+
+/* Bit fields for IDAC CTRL */
+#define _IDAC_CTRL_RESETVALUE                          0x00000000UL                              /**< Default value for IDAC_CTRL */
+#define _IDAC_CTRL_MASK                                0x00F17FFFUL                              /**< Mask for IDAC_CTRL */
+#define IDAC_CTRL_EN                                   (0x1UL << 0)                              /**< Current DAC Enable */
+#define _IDAC_CTRL_EN_SHIFT                            0                                         /**< Shift value for IDAC_EN */
+#define _IDAC_CTRL_EN_MASK                             0x1UL                                     /**< Bit mask for IDAC_EN */
+#define _IDAC_CTRL_EN_DEFAULT                          0x00000000UL                              /**< Mode DEFAULT for IDAC_CTRL */
+#define IDAC_CTRL_EN_DEFAULT                           (_IDAC_CTRL_EN_DEFAULT << 0)              /**< Shifted mode DEFAULT for IDAC_CTRL */
+#define IDAC_CTRL_CURSINK                              (0x1UL << 1)                              /**< Current Sink Enable */
+#define _IDAC_CTRL_CURSINK_SHIFT                       1                                         /**< Shift value for IDAC_CURSINK */
+#define _IDAC_CTRL_CURSINK_MASK                        0x2UL                                     /**< Bit mask for IDAC_CURSINK */
+#define _IDAC_CTRL_CURSINK_DEFAULT                     0x00000000UL                              /**< Mode DEFAULT for IDAC_CTRL */
+#define IDAC_CTRL_CURSINK_DEFAULT                      (_IDAC_CTRL_CURSINK_DEFAULT << 1)         /**< Shifted mode DEFAULT for IDAC_CTRL */
+#define IDAC_CTRL_MINOUTTRANS                          (0x1UL << 2)                              /**< Minimum Output Transition Enable */
+#define _IDAC_CTRL_MINOUTTRANS_SHIFT                   2                                         /**< Shift value for IDAC_MINOUTTRANS */
+#define _IDAC_CTRL_MINOUTTRANS_MASK                    0x4UL                                     /**< Bit mask for IDAC_MINOUTTRANS */
+#define _IDAC_CTRL_MINOUTTRANS_DEFAULT                 0x00000000UL                              /**< Mode DEFAULT for IDAC_CTRL */
+#define IDAC_CTRL_MINOUTTRANS_DEFAULT                  (_IDAC_CTRL_MINOUTTRANS_DEFAULT << 2)     /**< Shifted mode DEFAULT for IDAC_CTRL */
+#define IDAC_CTRL_OUTEN                                (0x1UL << 3)                              /**< Output Enable */
+#define _IDAC_CTRL_OUTEN_SHIFT                         3                                         /**< Shift value for IDAC_OUTEN */
+#define _IDAC_CTRL_OUTEN_MASK                          0x8UL                                     /**< Bit mask for IDAC_OUTEN */
+#define _IDAC_CTRL_OUTEN_DEFAULT                       0x00000000UL                              /**< Mode DEFAULT for IDAC_CTRL */
+#define IDAC_CTRL_OUTEN_DEFAULT                        (_IDAC_CTRL_OUTEN_DEFAULT << 3)           /**< Shifted mode DEFAULT for IDAC_CTRL */
+#define _IDAC_CTRL_APORTOUTSEL_SHIFT                   4                                         /**< Shift value for IDAC_APORTOUTSEL */
+#define _IDAC_CTRL_APORTOUTSEL_MASK                    0xFF0UL                                   /**< Bit mask for IDAC_APORTOUTSEL */
+#define _IDAC_CTRL_APORTOUTSEL_DEFAULT                 0x00000000UL                              /**< Mode DEFAULT for IDAC_CTRL */
+#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH0              0x00000020UL                              /**< Mode APORT1XCH0 for IDAC_CTRL */
+#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH1              0x00000021UL                              /**< Mode APORT1YCH1 for IDAC_CTRL */
+#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH2              0x00000022UL                              /**< Mode APORT1XCH2 for IDAC_CTRL */
+#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH3              0x00000023UL                              /**< Mode APORT1YCH3 for IDAC_CTRL */
+#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH4              0x00000024UL                              /**< Mode APORT1XCH4 for IDAC_CTRL */
+#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH5              0x00000025UL                              /**< Mode APORT1YCH5 for IDAC_CTRL */
+#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH6              0x00000026UL                              /**< Mode APORT1XCH6 for IDAC_CTRL */
+#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH7              0x00000027UL                              /**< Mode APORT1YCH7 for IDAC_CTRL */
+#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH8              0x00000028UL                              /**< Mode APORT1XCH8 for IDAC_CTRL */
+#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH9              0x00000029UL                              /**< Mode APORT1YCH9 for IDAC_CTRL */
+#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH10             0x0000002AUL                              /**< Mode APORT1XCH10 for IDAC_CTRL */
+#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH11             0x0000002BUL                              /**< Mode APORT1YCH11 for IDAC_CTRL */
+#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH12             0x0000002CUL                              /**< Mode APORT1XCH12 for IDAC_CTRL */
+#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH13             0x0000002DUL                              /**< Mode APORT1YCH13 for IDAC_CTRL */
+#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH14             0x0000002EUL                              /**< Mode APORT1XCH14 for IDAC_CTRL */
+#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH15             0x0000002FUL                              /**< Mode APORT1YCH15 for IDAC_CTRL */
+#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH16             0x00000030UL                              /**< Mode APORT1XCH16 for IDAC_CTRL */
+#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH17             0x00000031UL                              /**< Mode APORT1YCH17 for IDAC_CTRL */
+#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH18             0x00000032UL                              /**< Mode APORT1XCH18 for IDAC_CTRL */
+#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH19             0x00000033UL                              /**< Mode APORT1YCH19 for IDAC_CTRL */
+#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH20             0x00000034UL                              /**< Mode APORT1XCH20 for IDAC_CTRL */
+#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH21             0x00000035UL                              /**< Mode APORT1YCH21 for IDAC_CTRL */
+#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH22             0x00000036UL                              /**< Mode APORT1XCH22 for IDAC_CTRL */
+#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH23             0x00000037UL                              /**< Mode APORT1YCH23 for IDAC_CTRL */
+#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH24             0x00000038UL                              /**< Mode APORT1XCH24 for IDAC_CTRL */
+#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH25             0x00000039UL                              /**< Mode APORT1YCH25 for IDAC_CTRL */
+#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH26             0x0000003AUL                              /**< Mode APORT1XCH26 for IDAC_CTRL */
+#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH27             0x0000003BUL                              /**< Mode APORT1YCH27 for IDAC_CTRL */
+#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH28             0x0000003CUL                              /**< Mode APORT1XCH28 for IDAC_CTRL */
+#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH29             0x0000003DUL                              /**< Mode APORT1YCH29 for IDAC_CTRL */
+#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH30             0x0000003EUL                              /**< Mode APORT1XCH30 for IDAC_CTRL */
+#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH31             0x0000003FUL                              /**< Mode APORT1YCH31 for IDAC_CTRL */
+#define IDAC_CTRL_APORTOUTSEL_DEFAULT                  (_IDAC_CTRL_APORTOUTSEL_DEFAULT << 4)     /**< Shifted mode DEFAULT for IDAC_CTRL */
+#define IDAC_CTRL_APORTOUTSEL_APORT1XCH0               (_IDAC_CTRL_APORTOUTSEL_APORT1XCH0 << 4)  /**< Shifted mode APORT1XCH0 for IDAC_CTRL */
+#define IDAC_CTRL_APORTOUTSEL_APORT1YCH1               (_IDAC_CTRL_APORTOUTSEL_APORT1YCH1 << 4)  /**< Shifted mode APORT1YCH1 for IDAC_CTRL */
+#define IDAC_CTRL_APORTOUTSEL_APORT1XCH2               (_IDAC_CTRL_APORTOUTSEL_APORT1XCH2 << 4)  /**< Shifted mode APORT1XCH2 for IDAC_CTRL */
+#define IDAC_CTRL_APORTOUTSEL_APORT1YCH3               (_IDAC_CTRL_APORTOUTSEL_APORT1YCH3 << 4)  /**< Shifted mode APORT1YCH3 for IDAC_CTRL */
+#define IDAC_CTRL_APORTOUTSEL_APORT1XCH4               (_IDAC_CTRL_APORTOUTSEL_APORT1XCH4 << 4)  /**< Shifted mode APORT1XCH4 for IDAC_CTRL */
+#define IDAC_CTRL_APORTOUTSEL_APORT1YCH5               (_IDAC_CTRL_APORTOUTSEL_APORT1YCH5 << 4)  /**< Shifted mode APORT1YCH5 for IDAC_CTRL */
+#define IDAC_CTRL_APORTOUTSEL_APORT1XCH6               (_IDAC_CTRL_APORTOUTSEL_APORT1XCH6 << 4)  /**< Shifted mode APORT1XCH6 for IDAC_CTRL */
+#define IDAC_CTRL_APORTOUTSEL_APORT1YCH7               (_IDAC_CTRL_APORTOUTSEL_APORT1YCH7 << 4)  /**< Shifted mode APORT1YCH7 for IDAC_CTRL */
+#define IDAC_CTRL_APORTOUTSEL_APORT1XCH8               (_IDAC_CTRL_APORTOUTSEL_APORT1XCH8 << 4)  /**< Shifted mode APORT1XCH8 for IDAC_CTRL */
+#define IDAC_CTRL_APORTOUTSEL_APORT1YCH9               (_IDAC_CTRL_APORTOUTSEL_APORT1YCH9 << 4)  /**< Shifted mode APORT1YCH9 for IDAC_CTRL */
+#define IDAC_CTRL_APORTOUTSEL_APORT1XCH10              (_IDAC_CTRL_APORTOUTSEL_APORT1XCH10 << 4) /**< Shifted mode APORT1XCH10 for IDAC_CTRL */
+#define IDAC_CTRL_APORTOUTSEL_APORT1YCH11              (_IDAC_CTRL_APORTOUTSEL_APORT1YCH11 << 4) /**< Shifted mode APORT1YCH11 for IDAC_CTRL */
+#define IDAC_CTRL_APORTOUTSEL_APORT1XCH12              (_IDAC_CTRL_APORTOUTSEL_APORT1XCH12 << 4) /**< Shifted mode APORT1XCH12 for IDAC_CTRL */
+#define IDAC_CTRL_APORTOUTSEL_APORT1YCH13              (_IDAC_CTRL_APORTOUTSEL_APORT1YCH13 << 4) /**< Shifted mode APORT1YCH13 for IDAC_CTRL */
+#define IDAC_CTRL_APORTOUTSEL_APORT1XCH14              (_IDAC_CTRL_APORTOUTSEL_APORT1XCH14 << 4) /**< Shifted mode APORT1XCH14 for IDAC_CTRL */
+#define IDAC_CTRL_APORTOUTSEL_APORT1YCH15              (_IDAC_CTRL_APORTOUTSEL_APORT1YCH15 << 4) /**< Shifted mode APORT1YCH15 for IDAC_CTRL */
+#define IDAC_CTRL_APORTOUTSEL_APORT1XCH16              (_IDAC_CTRL_APORTOUTSEL_APORT1XCH16 << 4) /**< Shifted mode APORT1XCH16 for IDAC_CTRL */
+#define IDAC_CTRL_APORTOUTSEL_APORT1YCH17              (_IDAC_CTRL_APORTOUTSEL_APORT1YCH17 << 4) /**< Shifted mode APORT1YCH17 for IDAC_CTRL */
+#define IDAC_CTRL_APORTOUTSEL_APORT1XCH18              (_IDAC_CTRL_APORTOUTSEL_APORT1XCH18 << 4) /**< Shifted mode APORT1XCH18 for IDAC_CTRL */
+#define IDAC_CTRL_APORTOUTSEL_APORT1YCH19              (_IDAC_CTRL_APORTOUTSEL_APORT1YCH19 << 4) /**< Shifted mode APORT1YCH19 for IDAC_CTRL */
+#define IDAC_CTRL_APORTOUTSEL_APORT1XCH20              (_IDAC_CTRL_APORTOUTSEL_APORT1XCH20 << 4) /**< Shifted mode APORT1XCH20 for IDAC_CTRL */
+#define IDAC_CTRL_APORTOUTSEL_APORT1YCH21              (_IDAC_CTRL_APORTOUTSEL_APORT1YCH21 << 4) /**< Shifted mode APORT1YCH21 for IDAC_CTRL */
+#define IDAC_CTRL_APORTOUTSEL_APORT1XCH22              (_IDAC_CTRL_APORTOUTSEL_APORT1XCH22 << 4) /**< Shifted mode APORT1XCH22 for IDAC_CTRL */
+#define IDAC_CTRL_APORTOUTSEL_APORT1YCH23              (_IDAC_CTRL_APORTOUTSEL_APORT1YCH23 << 4) /**< Shifted mode APORT1YCH23 for IDAC_CTRL */
+#define IDAC_CTRL_APORTOUTSEL_APORT1XCH24              (_IDAC_CTRL_APORTOUTSEL_APORT1XCH24 << 4) /**< Shifted mode APORT1XCH24 for IDAC_CTRL */
+#define IDAC_CTRL_APORTOUTSEL_APORT1YCH25              (_IDAC_CTRL_APORTOUTSEL_APORT1YCH25 << 4) /**< Shifted mode APORT1YCH25 for IDAC_CTRL */
+#define IDAC_CTRL_APORTOUTSEL_APORT1XCH26              (_IDAC_CTRL_APORTOUTSEL_APORT1XCH26 << 4) /**< Shifted mode APORT1XCH26 for IDAC_CTRL */
+#define IDAC_CTRL_APORTOUTSEL_APORT1YCH27              (_IDAC_CTRL_APORTOUTSEL_APORT1YCH27 << 4) /**< Shifted mode APORT1YCH27 for IDAC_CTRL */
+#define IDAC_CTRL_APORTOUTSEL_APORT1XCH28              (_IDAC_CTRL_APORTOUTSEL_APORT1XCH28 << 4) /**< Shifted mode APORT1XCH28 for IDAC_CTRL */
+#define IDAC_CTRL_APORTOUTSEL_APORT1YCH29              (_IDAC_CTRL_APORTOUTSEL_APORT1YCH29 << 4) /**< Shifted mode APORT1YCH29 for IDAC_CTRL */
+#define IDAC_CTRL_APORTOUTSEL_APORT1XCH30              (_IDAC_CTRL_APORTOUTSEL_APORT1XCH30 << 4) /**< Shifted mode APORT1XCH30 for IDAC_CTRL */
+#define IDAC_CTRL_APORTOUTSEL_APORT1YCH31              (_IDAC_CTRL_APORTOUTSEL_APORT1YCH31 << 4) /**< Shifted mode APORT1YCH31 for IDAC_CTRL */
+#define IDAC_CTRL_PWRSEL                               (0x1UL << 12)                             /**< Power Select */
+#define _IDAC_CTRL_PWRSEL_SHIFT                        12                                        /**< Shift value for IDAC_PWRSEL */
+#define _IDAC_CTRL_PWRSEL_MASK                         0x1000UL                                  /**< Bit mask for IDAC_PWRSEL */
+#define _IDAC_CTRL_PWRSEL_DEFAULT                      0x00000000UL                              /**< Mode DEFAULT for IDAC_CTRL */
+#define _IDAC_CTRL_PWRSEL_ANA                          0x00000000UL                              /**< Mode ANA for IDAC_CTRL */
+#define _IDAC_CTRL_PWRSEL_IO                           0x00000001UL                              /**< Mode IO for IDAC_CTRL */
+#define IDAC_CTRL_PWRSEL_DEFAULT                       (_IDAC_CTRL_PWRSEL_DEFAULT << 12)         /**< Shifted mode DEFAULT for IDAC_CTRL */
+#define IDAC_CTRL_PWRSEL_ANA                           (_IDAC_CTRL_PWRSEL_ANA << 12)             /**< Shifted mode ANA for IDAC_CTRL */
+#define IDAC_CTRL_PWRSEL_IO                            (_IDAC_CTRL_PWRSEL_IO << 12)              /**< Shifted mode IO for IDAC_CTRL */
+#define IDAC_CTRL_EM2DELAY                             (0x1UL << 13)                             /**< EM2 Delay */
+#define _IDAC_CTRL_EM2DELAY_SHIFT                      13                                        /**< Shift value for IDAC_EM2DELAY */
+#define _IDAC_CTRL_EM2DELAY_MASK                       0x2000UL                                  /**< Bit mask for IDAC_EM2DELAY */
+#define _IDAC_CTRL_EM2DELAY_DEFAULT                    0x00000000UL                              /**< Mode DEFAULT for IDAC_CTRL */
+#define IDAC_CTRL_EM2DELAY_DEFAULT                     (_IDAC_CTRL_EM2DELAY_DEFAULT << 13)       /**< Shifted mode DEFAULT for IDAC_CTRL */
+#define IDAC_CTRL_APORTMASTERDIS                       (0x1UL << 14)                             /**< APORT Bus Master Disable */
+#define _IDAC_CTRL_APORTMASTERDIS_SHIFT                14                                        /**< Shift value for IDAC_APORTMASTERDIS */
+#define _IDAC_CTRL_APORTMASTERDIS_MASK                 0x4000UL                                  /**< Bit mask for IDAC_APORTMASTERDIS */
+#define _IDAC_CTRL_APORTMASTERDIS_DEFAULT              0x00000000UL                              /**< Mode DEFAULT for IDAC_CTRL */
+#define IDAC_CTRL_APORTMASTERDIS_DEFAULT               (_IDAC_CTRL_APORTMASTERDIS_DEFAULT << 14) /**< Shifted mode DEFAULT for IDAC_CTRL */
+#define IDAC_CTRL_OUTENPRS                             (0x1UL << 16)                             /**< PRS Controlled Output Enable */
+#define _IDAC_CTRL_OUTENPRS_SHIFT                      16                                        /**< Shift value for IDAC_OUTENPRS */
+#define _IDAC_CTRL_OUTENPRS_MASK                       0x10000UL                                 /**< Bit mask for IDAC_OUTENPRS */
+#define _IDAC_CTRL_OUTENPRS_DEFAULT                    0x00000000UL                              /**< Mode DEFAULT for IDAC_CTRL */
+#define IDAC_CTRL_OUTENPRS_DEFAULT                     (_IDAC_CTRL_OUTENPRS_DEFAULT << 16)       /**< Shifted mode DEFAULT for IDAC_CTRL */
+#define _IDAC_CTRL_PRSSEL_SHIFT                        20                                        /**< Shift value for IDAC_PRSSEL */
+#define _IDAC_CTRL_PRSSEL_MASK                         0xF00000UL                                /**< Bit mask for IDAC_PRSSEL */
+#define _IDAC_CTRL_PRSSEL_DEFAULT                      0x00000000UL                              /**< Mode DEFAULT for IDAC_CTRL */
+#define _IDAC_CTRL_PRSSEL_PRSCH0                       0x00000000UL                              /**< Mode PRSCH0 for IDAC_CTRL */
+#define _IDAC_CTRL_PRSSEL_PRSCH1                       0x00000001UL                              /**< Mode PRSCH1 for IDAC_CTRL */
+#define _IDAC_CTRL_PRSSEL_PRSCH2                       0x00000002UL                              /**< Mode PRSCH2 for IDAC_CTRL */
+#define _IDAC_CTRL_PRSSEL_PRSCH3                       0x00000003UL                              /**< Mode PRSCH3 for IDAC_CTRL */
+#define _IDAC_CTRL_PRSSEL_PRSCH4                       0x00000004UL                              /**< Mode PRSCH4 for IDAC_CTRL */
+#define _IDAC_CTRL_PRSSEL_PRSCH5                       0x00000005UL                              /**< Mode PRSCH5 for IDAC_CTRL */
+#define _IDAC_CTRL_PRSSEL_PRSCH6                       0x00000006UL                              /**< Mode PRSCH6 for IDAC_CTRL */
+#define _IDAC_CTRL_PRSSEL_PRSCH7                       0x00000007UL                              /**< Mode PRSCH7 for IDAC_CTRL */
+#define _IDAC_CTRL_PRSSEL_PRSCH8                       0x00000008UL                              /**< Mode PRSCH8 for IDAC_CTRL */
+#define _IDAC_CTRL_PRSSEL_PRSCH9                       0x00000009UL                              /**< Mode PRSCH9 for IDAC_CTRL */
+#define _IDAC_CTRL_PRSSEL_PRSCH10                      0x0000000AUL                              /**< Mode PRSCH10 for IDAC_CTRL */
+#define _IDAC_CTRL_PRSSEL_PRSCH11                      0x0000000BUL                              /**< Mode PRSCH11 for IDAC_CTRL */
+#define IDAC_CTRL_PRSSEL_DEFAULT                       (_IDAC_CTRL_PRSSEL_DEFAULT << 20)         /**< Shifted mode DEFAULT for IDAC_CTRL */
+#define IDAC_CTRL_PRSSEL_PRSCH0                        (_IDAC_CTRL_PRSSEL_PRSCH0 << 20)          /**< Shifted mode PRSCH0 for IDAC_CTRL */
+#define IDAC_CTRL_PRSSEL_PRSCH1                        (_IDAC_CTRL_PRSSEL_PRSCH1 << 20)          /**< Shifted mode PRSCH1 for IDAC_CTRL */
+#define IDAC_CTRL_PRSSEL_PRSCH2                        (_IDAC_CTRL_PRSSEL_PRSCH2 << 20)          /**< Shifted mode PRSCH2 for IDAC_CTRL */
+#define IDAC_CTRL_PRSSEL_PRSCH3                        (_IDAC_CTRL_PRSSEL_PRSCH3 << 20)          /**< Shifted mode PRSCH3 for IDAC_CTRL */
+#define IDAC_CTRL_PRSSEL_PRSCH4                        (_IDAC_CTRL_PRSSEL_PRSCH4 << 20)          /**< Shifted mode PRSCH4 for IDAC_CTRL */
+#define IDAC_CTRL_PRSSEL_PRSCH5                        (_IDAC_CTRL_PRSSEL_PRSCH5 << 20)          /**< Shifted mode PRSCH5 for IDAC_CTRL */
+#define IDAC_CTRL_PRSSEL_PRSCH6                        (_IDAC_CTRL_PRSSEL_PRSCH6 << 20)          /**< Shifted mode PRSCH6 for IDAC_CTRL */
+#define IDAC_CTRL_PRSSEL_PRSCH7                        (_IDAC_CTRL_PRSSEL_PRSCH7 << 20)          /**< Shifted mode PRSCH7 for IDAC_CTRL */
+#define IDAC_CTRL_PRSSEL_PRSCH8                        (_IDAC_CTRL_PRSSEL_PRSCH8 << 20)          /**< Shifted mode PRSCH8 for IDAC_CTRL */
+#define IDAC_CTRL_PRSSEL_PRSCH9                        (_IDAC_CTRL_PRSSEL_PRSCH9 << 20)          /**< Shifted mode PRSCH9 for IDAC_CTRL */
+#define IDAC_CTRL_PRSSEL_PRSCH10                       (_IDAC_CTRL_PRSSEL_PRSCH10 << 20)         /**< Shifted mode PRSCH10 for IDAC_CTRL */
+#define IDAC_CTRL_PRSSEL_PRSCH11                       (_IDAC_CTRL_PRSSEL_PRSCH11 << 20)         /**< Shifted mode PRSCH11 for IDAC_CTRL */
+
+/* Bit fields for IDAC CURPROG */
+#define _IDAC_CURPROG_RESETVALUE                       0x009B0000UL                          /**< Default value for IDAC_CURPROG */
+#define _IDAC_CURPROG_MASK                             0x00FF1F03UL                          /**< Mask for IDAC_CURPROG */
+#define _IDAC_CURPROG_RANGESEL_SHIFT                   0                                     /**< Shift value for IDAC_RANGESEL */
+#define _IDAC_CURPROG_RANGESEL_MASK                    0x3UL                                 /**< Bit mask for IDAC_RANGESEL */
+#define _IDAC_CURPROG_RANGESEL_DEFAULT                 0x00000000UL                          /**< Mode DEFAULT for IDAC_CURPROG */
+#define _IDAC_CURPROG_RANGESEL_RANGE0                  0x00000000UL                          /**< Mode RANGE0 for IDAC_CURPROG */
+#define _IDAC_CURPROG_RANGESEL_RANGE1                  0x00000001UL                          /**< Mode RANGE1 for IDAC_CURPROG */
+#define _IDAC_CURPROG_RANGESEL_RANGE2                  0x00000002UL                          /**< Mode RANGE2 for IDAC_CURPROG */
+#define _IDAC_CURPROG_RANGESEL_RANGE3                  0x00000003UL                          /**< Mode RANGE3 for IDAC_CURPROG */
+#define IDAC_CURPROG_RANGESEL_DEFAULT                  (_IDAC_CURPROG_RANGESEL_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_CURPROG */
+#define IDAC_CURPROG_RANGESEL_RANGE0                   (_IDAC_CURPROG_RANGESEL_RANGE0 << 0)  /**< Shifted mode RANGE0 for IDAC_CURPROG */
+#define IDAC_CURPROG_RANGESEL_RANGE1                   (_IDAC_CURPROG_RANGESEL_RANGE1 << 0)  /**< Shifted mode RANGE1 for IDAC_CURPROG */
+#define IDAC_CURPROG_RANGESEL_RANGE2                   (_IDAC_CURPROG_RANGESEL_RANGE2 << 0)  /**< Shifted mode RANGE2 for IDAC_CURPROG */
+#define IDAC_CURPROG_RANGESEL_RANGE3                   (_IDAC_CURPROG_RANGESEL_RANGE3 << 0)  /**< Shifted mode RANGE3 for IDAC_CURPROG */
+#define _IDAC_CURPROG_STEPSEL_SHIFT                    8                                     /**< Shift value for IDAC_STEPSEL */
+#define _IDAC_CURPROG_STEPSEL_MASK                     0x1F00UL                              /**< Bit mask for IDAC_STEPSEL */
+#define _IDAC_CURPROG_STEPSEL_DEFAULT                  0x00000000UL                          /**< Mode DEFAULT for IDAC_CURPROG */
+#define IDAC_CURPROG_STEPSEL_DEFAULT                   (_IDAC_CURPROG_STEPSEL_DEFAULT << 8)  /**< Shifted mode DEFAULT for IDAC_CURPROG */
+#define _IDAC_CURPROG_TUNING_SHIFT                     16                                    /**< Shift value for IDAC_TUNING */
+#define _IDAC_CURPROG_TUNING_MASK                      0xFF0000UL                            /**< Bit mask for IDAC_TUNING */
+#define _IDAC_CURPROG_TUNING_DEFAULT                   0x0000009BUL                          /**< Mode DEFAULT for IDAC_CURPROG */
+#define IDAC_CURPROG_TUNING_DEFAULT                    (_IDAC_CURPROG_TUNING_DEFAULT << 16)  /**< Shifted mode DEFAULT for IDAC_CURPROG */
+
+/* Bit fields for IDAC DUTYCONFIG */
+#define _IDAC_DUTYCONFIG_RESETVALUE                    0x00000000UL                                    /**< Default value for IDAC_DUTYCONFIG */
+#define _IDAC_DUTYCONFIG_MASK                          0x00000002UL                                    /**< Mask for IDAC_DUTYCONFIG */
+#define IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS                (0x1UL << 1)                                    /**< Duty Cycle Enable. */
+#define _IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_SHIFT         1                                               /**< Shift value for IDAC_EM2DUTYCYCLEDIS */
+#define _IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_MASK          0x2UL                                           /**< Bit mask for IDAC_EM2DUTYCYCLEDIS */
+#define _IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_DEFAULT       0x00000000UL                                    /**< Mode DEFAULT for IDAC_DUTYCONFIG */
+#define IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_DEFAULT        (_IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_DUTYCONFIG */
+
+/* Bit fields for IDAC STATUS */
+#define _IDAC_STATUS_RESETVALUE                        0x00000000UL                              /**< Default value for IDAC_STATUS */
+#define _IDAC_STATUS_MASK                              0x00000002UL                              /**< Mask for IDAC_STATUS */
+#define IDAC_STATUS_APORTCONFLICT                      (0x1UL << 1)                              /**< APORT Conflict Output */
+#define _IDAC_STATUS_APORTCONFLICT_SHIFT               1                                         /**< Shift value for IDAC_APORTCONFLICT */
+#define _IDAC_STATUS_APORTCONFLICT_MASK                0x2UL                                     /**< Bit mask for IDAC_APORTCONFLICT */
+#define _IDAC_STATUS_APORTCONFLICT_DEFAULT             0x00000000UL                              /**< Mode DEFAULT for IDAC_STATUS */
+#define IDAC_STATUS_APORTCONFLICT_DEFAULT              (_IDAC_STATUS_APORTCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_STATUS */
+
+/* Bit fields for IDAC IF */
+#define _IDAC_IF_RESETVALUE                            0x00000000UL                          /**< Default value for IDAC_IF */
+#define _IDAC_IF_MASK                                  0x00000002UL                          /**< Mask for IDAC_IF */
+#define IDAC_IF_APORTCONFLICT                          (0x1UL << 1)                          /**< APORT Conflict Interrupt Flag */
+#define _IDAC_IF_APORTCONFLICT_SHIFT                   1                                     /**< Shift value for IDAC_APORTCONFLICT */
+#define _IDAC_IF_APORTCONFLICT_MASK                    0x2UL                                 /**< Bit mask for IDAC_APORTCONFLICT */
+#define _IDAC_IF_APORTCONFLICT_DEFAULT                 0x00000000UL                          /**< Mode DEFAULT for IDAC_IF */
+#define IDAC_IF_APORTCONFLICT_DEFAULT                  (_IDAC_IF_APORTCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_IF */
+
+/* Bit fields for IDAC IFS */
+#define _IDAC_IFS_RESETVALUE                           0x00000000UL                           /**< Default value for IDAC_IFS */
+#define _IDAC_IFS_MASK                                 0x00000003UL                           /**< Mask for IDAC_IFS */
+#define IDAC_IFS_CURSTABLE                             (0x1UL << 0)                           /**< Set CURSTABLE Interrupt Flag */
+#define _IDAC_IFS_CURSTABLE_SHIFT                      0                                      /**< Shift value for IDAC_CURSTABLE */
+#define _IDAC_IFS_CURSTABLE_MASK                       0x1UL                                  /**< Bit mask for IDAC_CURSTABLE */
+#define _IDAC_IFS_CURSTABLE_DEFAULT                    0x00000000UL                           /**< Mode DEFAULT for IDAC_IFS */
+#define IDAC_IFS_CURSTABLE_DEFAULT                     (_IDAC_IFS_CURSTABLE_DEFAULT << 0)     /**< Shifted mode DEFAULT for IDAC_IFS */
+#define IDAC_IFS_APORTCONFLICT                         (0x1UL << 1)                           /**< Set APORTCONFLICT Interrupt Flag */
+#define _IDAC_IFS_APORTCONFLICT_SHIFT                  1                                      /**< Shift value for IDAC_APORTCONFLICT */
+#define _IDAC_IFS_APORTCONFLICT_MASK                   0x2UL                                  /**< Bit mask for IDAC_APORTCONFLICT */
+#define _IDAC_IFS_APORTCONFLICT_DEFAULT                0x00000000UL                           /**< Mode DEFAULT for IDAC_IFS */
+#define IDAC_IFS_APORTCONFLICT_DEFAULT                 (_IDAC_IFS_APORTCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_IFS */
+
+/* Bit fields for IDAC IFC */
+#define _IDAC_IFC_RESETVALUE                           0x00000000UL                           /**< Default value for IDAC_IFC */
+#define _IDAC_IFC_MASK                                 0x00000003UL                           /**< Mask for IDAC_IFC */
+#define IDAC_IFC_CURSTABLE                             (0x1UL << 0)                           /**< Clear CURSTABLE Interrupt Flag */
+#define _IDAC_IFC_CURSTABLE_SHIFT                      0                                      /**< Shift value for IDAC_CURSTABLE */
+#define _IDAC_IFC_CURSTABLE_MASK                       0x1UL                                  /**< Bit mask for IDAC_CURSTABLE */
+#define _IDAC_IFC_CURSTABLE_DEFAULT                    0x00000000UL                           /**< Mode DEFAULT for IDAC_IFC */
+#define IDAC_IFC_CURSTABLE_DEFAULT                     (_IDAC_IFC_CURSTABLE_DEFAULT << 0)     /**< Shifted mode DEFAULT for IDAC_IFC */
+#define IDAC_IFC_APORTCONFLICT                         (0x1UL << 1)                           /**< Clear APORTCONFLICT Interrupt Flag */
+#define _IDAC_IFC_APORTCONFLICT_SHIFT                  1                                      /**< Shift value for IDAC_APORTCONFLICT */
+#define _IDAC_IFC_APORTCONFLICT_MASK                   0x2UL                                  /**< Bit mask for IDAC_APORTCONFLICT */
+#define _IDAC_IFC_APORTCONFLICT_DEFAULT                0x00000000UL                           /**< Mode DEFAULT for IDAC_IFC */
+#define IDAC_IFC_APORTCONFLICT_DEFAULT                 (_IDAC_IFC_APORTCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_IFC */
+
+/* Bit fields for IDAC IEN */
+#define _IDAC_IEN_RESETVALUE                           0x00000000UL                           /**< Default value for IDAC_IEN */
+#define _IDAC_IEN_MASK                                 0x00000003UL                           /**< Mask for IDAC_IEN */
+#define IDAC_IEN_CURSTABLE                             (0x1UL << 0)                           /**< CURSTABLE Interrupt Enable */
+#define _IDAC_IEN_CURSTABLE_SHIFT                      0                                      /**< Shift value for IDAC_CURSTABLE */
+#define _IDAC_IEN_CURSTABLE_MASK                       0x1UL                                  /**< Bit mask for IDAC_CURSTABLE */
+#define _IDAC_IEN_CURSTABLE_DEFAULT                    0x00000000UL                           /**< Mode DEFAULT for IDAC_IEN */
+#define IDAC_IEN_CURSTABLE_DEFAULT                     (_IDAC_IEN_CURSTABLE_DEFAULT << 0)     /**< Shifted mode DEFAULT for IDAC_IEN */
+#define IDAC_IEN_APORTCONFLICT                         (0x1UL << 1)                           /**< APORTCONFLICT Interrupt Enable */
+#define _IDAC_IEN_APORTCONFLICT_SHIFT                  1                                      /**< Shift value for IDAC_APORTCONFLICT */
+#define _IDAC_IEN_APORTCONFLICT_MASK                   0x2UL                                  /**< Bit mask for IDAC_APORTCONFLICT */
+#define _IDAC_IEN_APORTCONFLICT_DEFAULT                0x00000000UL                           /**< Mode DEFAULT for IDAC_IEN */
+#define IDAC_IEN_APORTCONFLICT_DEFAULT                 (_IDAC_IEN_APORTCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_IEN */
+
+/* Bit fields for IDAC APORTREQ */
+#define _IDAC_APORTREQ_RESETVALUE                      0x00000000UL                             /**< Default value for IDAC_APORTREQ */
+#define _IDAC_APORTREQ_MASK                            0x0000000CUL                             /**< Mask for IDAC_APORTREQ */
+#define IDAC_APORTREQ_APORT1XREQ                       (0x1UL << 2)                             /**< 1 if the APORT bus connected to APORT1X is requested */
+#define _IDAC_APORTREQ_APORT1XREQ_SHIFT                2                                        /**< Shift value for IDAC_APORT1XREQ */
+#define _IDAC_APORTREQ_APORT1XREQ_MASK                 0x4UL                                    /**< Bit mask for IDAC_APORT1XREQ */
+#define _IDAC_APORTREQ_APORT1XREQ_DEFAULT              0x00000000UL                             /**< Mode DEFAULT for IDAC_APORTREQ */
+#define IDAC_APORTREQ_APORT1XREQ_DEFAULT               (_IDAC_APORTREQ_APORT1XREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for IDAC_APORTREQ */
+#define IDAC_APORTREQ_APORT1YREQ                       (0x1UL << 3)                             /**< 1 if the bus connected to APORT1Y is requested */
+#define _IDAC_APORTREQ_APORT1YREQ_SHIFT                3                                        /**< Shift value for IDAC_APORT1YREQ */
+#define _IDAC_APORTREQ_APORT1YREQ_MASK                 0x8UL                                    /**< Bit mask for IDAC_APORT1YREQ */
+#define _IDAC_APORTREQ_APORT1YREQ_DEFAULT              0x00000000UL                             /**< Mode DEFAULT for IDAC_APORTREQ */
+#define IDAC_APORTREQ_APORT1YREQ_DEFAULT               (_IDAC_APORTREQ_APORT1YREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for IDAC_APORTREQ */
+
+/* Bit fields for IDAC APORTCONFLICT */
+#define _IDAC_APORTCONFLICT_RESETVALUE                 0x00000000UL                                       /**< Default value for IDAC_APORTCONFLICT */
+#define _IDAC_APORTCONFLICT_MASK                       0x0000000CUL                                       /**< Mask for IDAC_APORTCONFLICT */
+#define IDAC_APORTCONFLICT_APORT1XCONFLICT             (0x1UL << 2)                                       /**< 1 if the bus connected to APORT1X is in conflict with another peripheral */
+#define _IDAC_APORTCONFLICT_APORT1XCONFLICT_SHIFT      2                                                  /**< Shift value for IDAC_APORT1XCONFLICT */
+#define _IDAC_APORTCONFLICT_APORT1XCONFLICT_MASK       0x4UL                                              /**< Bit mask for IDAC_APORT1XCONFLICT */
+#define _IDAC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT    0x00000000UL                                       /**< Mode DEFAULT for IDAC_APORTCONFLICT */
+#define IDAC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT     (_IDAC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for IDAC_APORTCONFLICT */
+#define IDAC_APORTCONFLICT_APORT1YCONFLICT             (0x1UL << 3)                                       /**< 1 if the bus connected to APORT1Y is in conflict with another peripheral */
+#define _IDAC_APORTCONFLICT_APORT1YCONFLICT_SHIFT      3                                                  /**< Shift value for IDAC_APORT1YCONFLICT */
+#define _IDAC_APORTCONFLICT_APORT1YCONFLICT_MASK       0x8UL                                              /**< Bit mask for IDAC_APORT1YCONFLICT */
+#define _IDAC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT    0x00000000UL                                       /**< Mode DEFAULT for IDAC_APORTCONFLICT */
+#define IDAC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT     (_IDAC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for IDAC_APORTCONFLICT */
+
+/** @} End of group EFM32PG1B_IDAC */
+/** @} End of group Parts */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG_STK3401/efm32pg1b_ldma.h	Fri Jan 15 07:45:16 2016 +0000
@@ -0,0 +1,561 @@
+/**************************************************************************//**
+ * @file efm32pg1b_ldma.h
+ * @brief EFM32PG1B_LDMA register and bit field definitions
+ * @version 4.2.0
+ ******************************************************************************
+ * @section License
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ ******************************************************************************
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software.@n
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.@n
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is
+ * providing the Software "AS IS", with no express or implied warranties of any
+ * kind, including, but not limited to, any implied warranties of
+ * merchantability or fitness for any particular purpose or warranties against
+ * infringement of any proprietary rights of a third party.
+ *
+ * Silicon Laboratories, Inc. will not be liable for any consequential,
+ * incidental, or special damages, or any other relief, or for any claim by
+ * any third party, arising from your use of this Software.
+ *
+ *****************************************************************************/
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFM32PG1B_LDMA
+ * @{
+ * @brief EFM32PG1B_LDMA Register Declaration
+ *****************************************************************************/
+typedef struct
+{
+  __IO uint32_t   CTRL;         /**< DMA Control Register  */
+  __I uint32_t    STATUS;       /**< DMA Status Register  */
+  __IO uint32_t   SYNC;         /**< DMA Synchronization Trigger Register (Single-Cycle RMW)  */
+  uint32_t        RESERVED0[5]; /**< Reserved for future use **/
+  __IO uint32_t   CHEN;         /**< DMA Channel Enable Register (Single-Cycle RMW)  */
+  __I uint32_t    CHBUSY;       /**< DMA Channel Busy Register  */
+  __IO uint32_t   CHDONE;       /**< DMA Channel Linking Done Register (Single-Cycle RMW)  */
+  __IO uint32_t   DBGHALT;      /**< DMA Channel Debug Halt Register  */
+  __IO uint32_t   SWREQ;        /**< DMA Channel Software Transfer Request Register  */
+  __IO uint32_t   REQDIS;       /**< DMA Channel Request Disable Register  */
+  __I uint32_t    REQPEND;      /**< DMA Channel Requests Pending Register  */
+  __IO uint32_t   LINKLOAD;     /**< DMA Channel Link Load Register  */
+  __IO uint32_t   REQCLEAR;     /**< DMA Channel Request Clear Register  */
+  uint32_t        RESERVED1[7]; /**< Reserved for future use **/
+  __I uint32_t    IF;           /**< Interrupt Flag Register  */
+  __IO uint32_t   IFS;          /**< Interrupt Flag Set Register  */
+  __IO uint32_t   IFC;          /**< Interrupt Flag Clear Register  */
+  __IO uint32_t   IEN;          /**< Interrupt Enable register  */
+
+  uint32_t        RESERVED2[4]; /**< Reserved registers */
+  LDMA_CH_TypeDef CH[8];        /**< DMA Channel Registers */
+} LDMA_TypeDef;                 /** @} */
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B_LDMA_BitFields
+ * @{
+ *****************************************************************************/
+
+/* Bit fields for LDMA CTRL */
+#define _LDMA_CTRL_RESETVALUE                        0x07000000UL                           /**< Default value for LDMA_CTRL */
+#define _LDMA_CTRL_MASK                              0x0700FFFFUL                           /**< Mask for LDMA_CTRL */
+#define _LDMA_CTRL_SYNCPRSSETEN_SHIFT                0                                      /**< Shift value for LDMA_SYNCPRSSETEN */
+#define _LDMA_CTRL_SYNCPRSSETEN_MASK                 0xFFUL                                 /**< Bit mask for LDMA_SYNCPRSSETEN */
+#define _LDMA_CTRL_SYNCPRSSETEN_DEFAULT              0x00000000UL                           /**< Mode DEFAULT for LDMA_CTRL */
+#define LDMA_CTRL_SYNCPRSSETEN_DEFAULT               (_LDMA_CTRL_SYNCPRSSETEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CTRL */
+#define _LDMA_CTRL_SYNCPRSCLREN_SHIFT                8                                      /**< Shift value for LDMA_SYNCPRSCLREN */
+#define _LDMA_CTRL_SYNCPRSCLREN_MASK                 0xFF00UL                               /**< Bit mask for LDMA_SYNCPRSCLREN */
+#define _LDMA_CTRL_SYNCPRSCLREN_DEFAULT              0x00000000UL                           /**< Mode DEFAULT for LDMA_CTRL */
+#define LDMA_CTRL_SYNCPRSCLREN_DEFAULT               (_LDMA_CTRL_SYNCPRSCLREN_DEFAULT << 8) /**< Shifted mode DEFAULT for LDMA_CTRL */
+#define _LDMA_CTRL_NUMFIXED_SHIFT                    24                                     /**< Shift value for LDMA_NUMFIXED */
+#define _LDMA_CTRL_NUMFIXED_MASK                     0x7000000UL                            /**< Bit mask for LDMA_NUMFIXED */
+#define _LDMA_CTRL_NUMFIXED_DEFAULT                  0x00000007UL                           /**< Mode DEFAULT for LDMA_CTRL */
+#define LDMA_CTRL_NUMFIXED_DEFAULT                   (_LDMA_CTRL_NUMFIXED_DEFAULT << 24)    /**< Shifted mode DEFAULT for LDMA_CTRL */
+
+/* Bit fields for LDMA STATUS */
+#define _LDMA_STATUS_RESETVALUE                      0x08100000UL                           /**< Default value for LDMA_STATUS */
+#define _LDMA_STATUS_MASK                            0x1F1F073BUL                           /**< Mask for LDMA_STATUS */
+#define LDMA_STATUS_ANYBUSY                          (0x1UL << 0)                           /**< Any DMA Channel Busy */
+#define _LDMA_STATUS_ANYBUSY_SHIFT                   0                                      /**< Shift value for LDMA_ANYBUSY */
+#define _LDMA_STATUS_ANYBUSY_MASK                    0x1UL                                  /**< Bit mask for LDMA_ANYBUSY */
+#define _LDMA_STATUS_ANYBUSY_DEFAULT                 0x00000000UL                           /**< Mode DEFAULT for LDMA_STATUS */
+#define LDMA_STATUS_ANYBUSY_DEFAULT                  (_LDMA_STATUS_ANYBUSY_DEFAULT << 0)    /**< Shifted mode DEFAULT for LDMA_STATUS */
+#define LDMA_STATUS_ANYREQ                           (0x1UL << 1)                           /**< Any DMA Channel Request Pending */
+#define _LDMA_STATUS_ANYREQ_SHIFT                    1                                      /**< Shift value for LDMA_ANYREQ */
+#define _LDMA_STATUS_ANYREQ_MASK                     0x2UL                                  /**< Bit mask for LDMA_ANYREQ */
+#define _LDMA_STATUS_ANYREQ_DEFAULT                  0x00000000UL                           /**< Mode DEFAULT for LDMA_STATUS */
+#define LDMA_STATUS_ANYREQ_DEFAULT                   (_LDMA_STATUS_ANYREQ_DEFAULT << 1)     /**< Shifted mode DEFAULT for LDMA_STATUS */
+#define _LDMA_STATUS_CHGRANT_SHIFT                   3                                      /**< Shift value for LDMA_CHGRANT */
+#define _LDMA_STATUS_CHGRANT_MASK                    0x38UL                                 /**< Bit mask for LDMA_CHGRANT */
+#define _LDMA_STATUS_CHGRANT_DEFAULT                 0x00000000UL                           /**< Mode DEFAULT for LDMA_STATUS */
+#define LDMA_STATUS_CHGRANT_DEFAULT                  (_LDMA_STATUS_CHGRANT_DEFAULT << 3)    /**< Shifted mode DEFAULT for LDMA_STATUS */
+#define _LDMA_STATUS_CHERROR_SHIFT                   8                                      /**< Shift value for LDMA_CHERROR */
+#define _LDMA_STATUS_CHERROR_MASK                    0x700UL                                /**< Bit mask for LDMA_CHERROR */
+#define _LDMA_STATUS_CHERROR_DEFAULT                 0x00000000UL                           /**< Mode DEFAULT for LDMA_STATUS */
+#define LDMA_STATUS_CHERROR_DEFAULT                  (_LDMA_STATUS_CHERROR_DEFAULT << 8)    /**< Shifted mode DEFAULT for LDMA_STATUS */
+#define _LDMA_STATUS_FIFOLEVEL_SHIFT                 16                                     /**< Shift value for LDMA_FIFOLEVEL */
+#define _LDMA_STATUS_FIFOLEVEL_MASK                  0x1F0000UL                             /**< Bit mask for LDMA_FIFOLEVEL */
+#define _LDMA_STATUS_FIFOLEVEL_DEFAULT               0x00000010UL                           /**< Mode DEFAULT for LDMA_STATUS */
+#define LDMA_STATUS_FIFOLEVEL_DEFAULT                (_LDMA_STATUS_FIFOLEVEL_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_STATUS */
+#define _LDMA_STATUS_CHNUM_SHIFT                     24                                     /**< Shift value for LDMA_CHNUM */
+#define _LDMA_STATUS_CHNUM_MASK                      0x1F000000UL                           /**< Bit mask for LDMA_CHNUM */
+#define _LDMA_STATUS_CHNUM_DEFAULT                   0x00000008UL                           /**< Mode DEFAULT for LDMA_STATUS */
+#define LDMA_STATUS_CHNUM_DEFAULT                    (_LDMA_STATUS_CHNUM_DEFAULT << 24)     /**< Shifted mode DEFAULT for LDMA_STATUS */
+
+/* Bit fields for LDMA SYNC */
+#define _LDMA_SYNC_RESETVALUE                        0x00000000UL                       /**< Default value for LDMA_SYNC */
+#define _LDMA_SYNC_MASK                              0x000000FFUL                       /**< Mask for LDMA_SYNC */
+#define _LDMA_SYNC_SYNCTRIG_SHIFT                    0                                  /**< Shift value for LDMA_SYNCTRIG */
+#define _LDMA_SYNC_SYNCTRIG_MASK                     0xFFUL                             /**< Bit mask for LDMA_SYNCTRIG */
+#define _LDMA_SYNC_SYNCTRIG_DEFAULT                  0x00000000UL                       /**< Mode DEFAULT for LDMA_SYNC */
+#define LDMA_SYNC_SYNCTRIG_DEFAULT                   (_LDMA_SYNC_SYNCTRIG_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNC */
+
+/* Bit fields for LDMA CHEN */
+#define _LDMA_CHEN_RESETVALUE                        0x00000000UL                   /**< Default value for LDMA_CHEN */
+#define _LDMA_CHEN_MASK                              0x000000FFUL                   /**< Mask for LDMA_CHEN */
+#define _LDMA_CHEN_CHEN_SHIFT                        0                              /**< Shift value for LDMA_CHEN */
+#define _LDMA_CHEN_CHEN_MASK                         0xFFUL                         /**< Bit mask for LDMA_CHEN */
+#define _LDMA_CHEN_CHEN_DEFAULT                      0x00000000UL                   /**< Mode DEFAULT for LDMA_CHEN */
+#define LDMA_CHEN_CHEN_DEFAULT                       (_LDMA_CHEN_CHEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHEN */
+
+/* Bit fields for LDMA CHBUSY */
+#define _LDMA_CHBUSY_RESETVALUE                      0x00000000UL                     /**< Default value for LDMA_CHBUSY */
+#define _LDMA_CHBUSY_MASK                            0x000000FFUL                     /**< Mask for LDMA_CHBUSY */
+#define _LDMA_CHBUSY_BUSY_SHIFT                      0                                /**< Shift value for LDMA_BUSY */
+#define _LDMA_CHBUSY_BUSY_MASK                       0xFFUL                           /**< Bit mask for LDMA_BUSY */
+#define _LDMA_CHBUSY_BUSY_DEFAULT                    0x00000000UL                     /**< Mode DEFAULT for LDMA_CHBUSY */
+#define LDMA_CHBUSY_BUSY_DEFAULT                     (_LDMA_CHBUSY_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHBUSY */
+
+/* Bit fields for LDMA CHDONE */
+#define _LDMA_CHDONE_RESETVALUE                      0x00000000UL                       /**< Default value for LDMA_CHDONE */
+#define _LDMA_CHDONE_MASK                            0x000000FFUL                       /**< Mask for LDMA_CHDONE */
+#define _LDMA_CHDONE_CHDONE_SHIFT                    0                                  /**< Shift value for LDMA_CHDONE */
+#define _LDMA_CHDONE_CHDONE_MASK                     0xFFUL                             /**< Bit mask for LDMA_CHDONE */
+#define _LDMA_CHDONE_CHDONE_DEFAULT                  0x00000000UL                       /**< Mode DEFAULT for LDMA_CHDONE */
+#define LDMA_CHDONE_CHDONE_DEFAULT                   (_LDMA_CHDONE_CHDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHDONE */
+
+/* Bit fields for LDMA DBGHALT */
+#define _LDMA_DBGHALT_RESETVALUE                     0x00000000UL                         /**< Default value for LDMA_DBGHALT */
+#define _LDMA_DBGHALT_MASK                           0x000000FFUL                         /**< Mask for LDMA_DBGHALT */
+#define _LDMA_DBGHALT_DBGHALT_SHIFT                  0                                    /**< Shift value for LDMA_DBGHALT */
+#define _LDMA_DBGHALT_DBGHALT_MASK                   0xFFUL                               /**< Bit mask for LDMA_DBGHALT */
+#define _LDMA_DBGHALT_DBGHALT_DEFAULT                0x00000000UL                         /**< Mode DEFAULT for LDMA_DBGHALT */
+#define LDMA_DBGHALT_DBGHALT_DEFAULT                 (_LDMA_DBGHALT_DBGHALT_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_DBGHALT */
+
+/* Bit fields for LDMA SWREQ */
+#define _LDMA_SWREQ_RESETVALUE                       0x00000000UL                     /**< Default value for LDMA_SWREQ */
+#define _LDMA_SWREQ_MASK                             0x000000FFUL                     /**< Mask for LDMA_SWREQ */
+#define _LDMA_SWREQ_SWREQ_SHIFT                      0                                /**< Shift value for LDMA_SWREQ */
+#define _LDMA_SWREQ_SWREQ_MASK                       0xFFUL                           /**< Bit mask for LDMA_SWREQ */
+#define _LDMA_SWREQ_SWREQ_DEFAULT                    0x00000000UL                     /**< Mode DEFAULT for LDMA_SWREQ */
+#define LDMA_SWREQ_SWREQ_DEFAULT                     (_LDMA_SWREQ_SWREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SWREQ */
+
+/* Bit fields for LDMA REQDIS */
+#define _LDMA_REQDIS_RESETVALUE                      0x00000000UL                       /**< Default value for LDMA_REQDIS */
+#define _LDMA_REQDIS_MASK                            0x000000FFUL                       /**< Mask for LDMA_REQDIS */
+#define _LDMA_REQDIS_REQDIS_SHIFT                    0                                  /**< Shift value for LDMA_REQDIS */
+#define _LDMA_REQDIS_REQDIS_MASK                     0xFFUL                             /**< Bit mask for LDMA_REQDIS */
+#define _LDMA_REQDIS_REQDIS_DEFAULT                  0x00000000UL                       /**< Mode DEFAULT for LDMA_REQDIS */
+#define LDMA_REQDIS_REQDIS_DEFAULT                   (_LDMA_REQDIS_REQDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQDIS */
+
+/* Bit fields for LDMA REQPEND */
+#define _LDMA_REQPEND_RESETVALUE                     0x00000000UL                         /**< Default value for LDMA_REQPEND */
+#define _LDMA_REQPEND_MASK                           0x000000FFUL                         /**< Mask for LDMA_REQPEND */
+#define _LDMA_REQPEND_REQPEND_SHIFT                  0                                    /**< Shift value for LDMA_REQPEND */
+#define _LDMA_REQPEND_REQPEND_MASK                   0xFFUL                               /**< Bit mask for LDMA_REQPEND */
+#define _LDMA_REQPEND_REQPEND_DEFAULT                0x00000000UL                         /**< Mode DEFAULT for LDMA_REQPEND */
+#define LDMA_REQPEND_REQPEND_DEFAULT                 (_LDMA_REQPEND_REQPEND_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQPEND */
+
+/* Bit fields for LDMA LINKLOAD */
+#define _LDMA_LINKLOAD_RESETVALUE                    0x00000000UL                           /**< Default value for LDMA_LINKLOAD */
+#define _LDMA_LINKLOAD_MASK                          0x000000FFUL                           /**< Mask for LDMA_LINKLOAD */
+#define _LDMA_LINKLOAD_LINKLOAD_SHIFT                0                                      /**< Shift value for LDMA_LINKLOAD */
+#define _LDMA_LINKLOAD_LINKLOAD_MASK                 0xFFUL                                 /**< Bit mask for LDMA_LINKLOAD */
+#define _LDMA_LINKLOAD_LINKLOAD_DEFAULT              0x00000000UL                           /**< Mode DEFAULT for LDMA_LINKLOAD */
+#define LDMA_LINKLOAD_LINKLOAD_DEFAULT               (_LDMA_LINKLOAD_LINKLOAD_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_LINKLOAD */
+
+/* Bit fields for LDMA REQCLEAR */
+#define _LDMA_REQCLEAR_RESETVALUE                    0x00000000UL                           /**< Default value for LDMA_REQCLEAR */
+#define _LDMA_REQCLEAR_MASK                          0x000000FFUL                           /**< Mask for LDMA_REQCLEAR */
+#define _LDMA_REQCLEAR_REQCLEAR_SHIFT                0                                      /**< Shift value for LDMA_REQCLEAR */
+#define _LDMA_REQCLEAR_REQCLEAR_MASK                 0xFFUL                                 /**< Bit mask for LDMA_REQCLEAR */
+#define _LDMA_REQCLEAR_REQCLEAR_DEFAULT              0x00000000UL                           /**< Mode DEFAULT for LDMA_REQCLEAR */
+#define LDMA_REQCLEAR_REQCLEAR_DEFAULT               (_LDMA_REQCLEAR_REQCLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQCLEAR */
+
+/* Bit fields for LDMA IF */
+#define _LDMA_IF_RESETVALUE                          0x00000000UL                   /**< Default value for LDMA_IF */
+#define _LDMA_IF_MASK                                0x800000FFUL                   /**< Mask for LDMA_IF */
+#define _LDMA_IF_DONE_SHIFT                          0                              /**< Shift value for LDMA_DONE */
+#define _LDMA_IF_DONE_MASK                           0xFFUL                         /**< Bit mask for LDMA_DONE */
+#define _LDMA_IF_DONE_DEFAULT                        0x00000000UL                   /**< Mode DEFAULT for LDMA_IF */
+#define LDMA_IF_DONE_DEFAULT                         (_LDMA_IF_DONE_DEFAULT << 0)   /**< Shifted mode DEFAULT for LDMA_IF */
+#define LDMA_IF_ERROR                                (0x1UL << 31)                  /**< Transfer Error Interrupt Flag */
+#define _LDMA_IF_ERROR_SHIFT                         31                             /**< Shift value for LDMA_ERROR */
+#define _LDMA_IF_ERROR_MASK                          0x80000000UL                   /**< Bit mask for LDMA_ERROR */
+#define _LDMA_IF_ERROR_DEFAULT                       0x00000000UL                   /**< Mode DEFAULT for LDMA_IF */
+#define LDMA_IF_ERROR_DEFAULT                        (_LDMA_IF_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IF */
+
+/* Bit fields for LDMA IFS */
+#define _LDMA_IFS_RESETVALUE                         0x00000000UL                    /**< Default value for LDMA_IFS */
+#define _LDMA_IFS_MASK                               0x800000FFUL                    /**< Mask for LDMA_IFS */
+#define _LDMA_IFS_DONE_SHIFT                         0                               /**< Shift value for LDMA_DONE */
+#define _LDMA_IFS_DONE_MASK                          0xFFUL                          /**< Bit mask for LDMA_DONE */
+#define _LDMA_IFS_DONE_DEFAULT                       0x00000000UL                    /**< Mode DEFAULT for LDMA_IFS */
+#define LDMA_IFS_DONE_DEFAULT                        (_LDMA_IFS_DONE_DEFAULT << 0)   /**< Shifted mode DEFAULT for LDMA_IFS */
+#define LDMA_IFS_ERROR                               (0x1UL << 31)                   /**< Set ERROR Interrupt Flag */
+#define _LDMA_IFS_ERROR_SHIFT                        31                              /**< Shift value for LDMA_ERROR */
+#define _LDMA_IFS_ERROR_MASK                         0x80000000UL                    /**< Bit mask for LDMA_ERROR */
+#define _LDMA_IFS_ERROR_DEFAULT                      0x00000000UL                    /**< Mode DEFAULT for LDMA_IFS */
+#define LDMA_IFS_ERROR_DEFAULT                       (_LDMA_IFS_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IFS */
+
+/* Bit fields for LDMA IFC */
+#define _LDMA_IFC_RESETVALUE                         0x00000000UL                    /**< Default value for LDMA_IFC */
+#define _LDMA_IFC_MASK                               0x800000FFUL                    /**< Mask for LDMA_IFC */
+#define _LDMA_IFC_DONE_SHIFT                         0                               /**< Shift value for LDMA_DONE */
+#define _LDMA_IFC_DONE_MASK                          0xFFUL                          /**< Bit mask for LDMA_DONE */
+#define _LDMA_IFC_DONE_DEFAULT                       0x00000000UL                    /**< Mode DEFAULT for LDMA_IFC */
+#define LDMA_IFC_DONE_DEFAULT                        (_LDMA_IFC_DONE_DEFAULT << 0)   /**< Shifted mode DEFAULT for LDMA_IFC */
+#define LDMA_IFC_ERROR                               (0x1UL << 31)                   /**< Clear ERROR Interrupt Flag */
+#define _LDMA_IFC_ERROR_SHIFT                        31                              /**< Shift value for LDMA_ERROR */
+#define _LDMA_IFC_ERROR_MASK                         0x80000000UL                    /**< Bit mask for LDMA_ERROR */
+#define _LDMA_IFC_ERROR_DEFAULT                      0x00000000UL                    /**< Mode DEFAULT for LDMA_IFC */
+#define LDMA_IFC_ERROR_DEFAULT                       (_LDMA_IFC_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IFC */
+
+/* Bit fields for LDMA IEN */
+#define _LDMA_IEN_RESETVALUE                         0x00000000UL                    /**< Default value for LDMA_IEN */
+#define _LDMA_IEN_MASK                               0x800000FFUL                    /**< Mask for LDMA_IEN */
+#define _LDMA_IEN_DONE_SHIFT                         0                               /**< Shift value for LDMA_DONE */
+#define _LDMA_IEN_DONE_MASK                          0xFFUL                          /**< Bit mask for LDMA_DONE */
+#define _LDMA_IEN_DONE_DEFAULT                       0x00000000UL                    /**< Mode DEFAULT for LDMA_IEN */
+#define LDMA_IEN_DONE_DEFAULT                        (_LDMA_IEN_DONE_DEFAULT << 0)   /**< Shifted mode DEFAULT for LDMA_IEN */
+#define LDMA_IEN_ERROR                               (0x1UL << 31)                   /**< ERROR Interrupt Enable */
+#define _LDMA_IEN_ERROR_SHIFT                        31                              /**< Shift value for LDMA_ERROR */
+#define _LDMA_IEN_ERROR_MASK                         0x80000000UL                    /**< Bit mask for LDMA_ERROR */
+#define _LDMA_IEN_ERROR_DEFAULT                      0x00000000UL                    /**< Mode DEFAULT for LDMA_IEN */
+#define LDMA_IEN_ERROR_DEFAULT                       (_LDMA_IEN_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IEN */
+
+/* Bit fields for LDMA CH_REQSEL */
+#define _LDMA_CH_REQSEL_RESETVALUE                   0x00000000UL                                     /**< Default value for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_MASK                         0x003F000FUL                                     /**< Mask for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SIGSEL_SHIFT                 0                                                /**< Shift value for LDMA_SIGSEL */
+#define _LDMA_CH_REQSEL_SIGSEL_MASK                  0xFUL                                            /**< Bit mask for LDMA_SIGSEL */
+#define _LDMA_CH_REQSEL_SIGSEL_PRSREQ0               0x00000000UL                                     /**< Mode PRSREQ0 for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE            0x00000000UL                                     /**< Mode ADC0SINGLE for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV         0x00000000UL                                     /**< Mode USART0RXDATAV for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV         0x00000000UL                                     /**< Mode USART1RXDATAV for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV        0x00000000UL                                     /**< Mode LEUART0RXDATAV for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV           0x00000000UL                                     /**< Mode I2C0RXDATAV for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF            0x00000000UL                                     /**< Mode TIMER0UFOF for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF            0x00000000UL                                     /**< Mode TIMER1UFOF for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SIGSEL_MSCWDATA              0x00000000UL                                     /**< Mode MSCWDATA for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0WR         0x00000000UL                                     /**< Mode CRYPTODATA0WR for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SIGSEL_PRSREQ1               0x00000001UL                                     /**< Mode PRSREQ1 for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SIGSEL_ADC0SCAN              0x00000001UL                                     /**< Mode ADC0SCAN for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SIGSEL_USART0TXBL            0x00000001UL                                     /**< Mode USART0TXBL for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SIGSEL_USART1TXBL            0x00000001UL                                     /**< Mode USART1TXBL for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL           0x00000001UL                                     /**< Mode LEUART0TXBL for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SIGSEL_I2C0TXBL              0x00000001UL                                     /**< Mode I2C0TXBL for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SIGSEL_TIMER0CC0             0x00000001UL                                     /**< Mode TIMER0CC0 for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SIGSEL_TIMER1CC0             0x00000001UL                                     /**< Mode TIMER1CC0 for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0XWR        0x00000001UL                                     /**< Mode CRYPTODATA0XWR for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY         0x00000002UL                                     /**< Mode USART0TXEMPTY for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY         0x00000002UL                                     /**< Mode USART1TXEMPTY for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY        0x00000002UL                                     /**< Mode LEUART0TXEMPTY for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SIGSEL_TIMER0CC1             0x00000002UL                                     /**< Mode TIMER0CC1 for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SIGSEL_TIMER1CC1             0x00000002UL                                     /**< Mode TIMER1CC1 for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0RD         0x00000002UL                                     /**< Mode CRYPTODATA0RD for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT    0x00000003UL                                     /**< Mode USART1RXDATAVRIGHT for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SIGSEL_TIMER0CC2             0x00000003UL                                     /**< Mode TIMER0CC2 for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SIGSEL_TIMER1CC2             0x00000003UL                                     /**< Mode TIMER1CC2 for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1WR         0x00000003UL                                     /**< Mode CRYPTODATA1WR for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT       0x00000004UL                                     /**< Mode USART1TXBLRIGHT for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SIGSEL_TIMER1CC3             0x00000004UL                                     /**< Mode TIMER1CC3 for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1RD         0x00000004UL                                     /**< Mode CRYPTODATA1RD for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SIGSEL_PRSREQ0                (_LDMA_CH_REQSEL_SIGSEL_PRSREQ0 << 0)            /**< Shifted mode PRSREQ0 for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE             (_LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE << 0)         /**< Shifted mode ADC0SINGLE for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV          (_LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV << 0)      /**< Shifted mode USART0RXDATAV for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV          (_LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV << 0)      /**< Shifted mode USART1RXDATAV for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV         (_LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV << 0)     /**< Shifted mode LEUART0RXDATAV for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV            (_LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV << 0)        /**< Shifted mode I2C0RXDATAV for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF             (_LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF << 0)         /**< Shifted mode TIMER0UFOF for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF             (_LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF << 0)         /**< Shifted mode TIMER1UFOF for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SIGSEL_MSCWDATA               (_LDMA_CH_REQSEL_SIGSEL_MSCWDATA << 0)           /**< Shifted mode MSCWDATA for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0WR          (_LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0WR << 0)      /**< Shifted mode CRYPTODATA0WR for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SIGSEL_PRSREQ1                (_LDMA_CH_REQSEL_SIGSEL_PRSREQ1 << 0)            /**< Shifted mode PRSREQ1 for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SIGSEL_ADC0SCAN               (_LDMA_CH_REQSEL_SIGSEL_ADC0SCAN << 0)           /**< Shifted mode ADC0SCAN for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SIGSEL_USART0TXBL             (_LDMA_CH_REQSEL_SIGSEL_USART0TXBL << 0)         /**< Shifted mode USART0TXBL for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SIGSEL_USART1TXBL             (_LDMA_CH_REQSEL_SIGSEL_USART1TXBL << 0)         /**< Shifted mode USART1TXBL for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL            (_LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL << 0)        /**< Shifted mode LEUART0TXBL for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SIGSEL_I2C0TXBL               (_LDMA_CH_REQSEL_SIGSEL_I2C0TXBL << 0)           /**< Shifted mode I2C0TXBL for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SIGSEL_TIMER0CC0              (_LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 << 0)          /**< Shifted mode TIMER0CC0 for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SIGSEL_TIMER1CC0              (_LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 << 0)          /**< Shifted mode TIMER1CC0 for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0XWR         (_LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0XWR << 0)     /**< Shifted mode CRYPTODATA0XWR for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY          (_LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY << 0)      /**< Shifted mode USART0TXEMPTY for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY          (_LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY << 0)      /**< Shifted mode USART1TXEMPTY for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY         (_LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY << 0)     /**< Shifted mode LEUART0TXEMPTY for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SIGSEL_TIMER0CC1              (_LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 << 0)          /**< Shifted mode TIMER0CC1 for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SIGSEL_TIMER1CC1              (_LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 << 0)          /**< Shifted mode TIMER1CC1 for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0RD          (_LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0RD << 0)      /**< Shifted mode CRYPTODATA0RD for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT     (_LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT << 0) /**< Shifted mode USART1RXDATAVRIGHT for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SIGSEL_TIMER0CC2              (_LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 << 0)          /**< Shifted mode TIMER0CC2 for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SIGSEL_TIMER1CC2              (_LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 << 0)          /**< Shifted mode TIMER1CC2 for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1WR          (_LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1WR << 0)      /**< Shifted mode CRYPTODATA1WR for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT        (_LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT << 0)    /**< Shifted mode USART1TXBLRIGHT for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SIGSEL_TIMER1CC3              (_LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 << 0)          /**< Shifted mode TIMER1CC3 for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1RD          (_LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1RD << 0)      /**< Shifted mode CRYPTODATA1RD for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SOURCESEL_SHIFT              16                                               /**< Shift value for LDMA_SOURCESEL */
+#define _LDMA_CH_REQSEL_SOURCESEL_MASK               0x3F0000UL                                       /**< Bit mask for LDMA_SOURCESEL */
+#define _LDMA_CH_REQSEL_SOURCESEL_NONE               0x00000000UL                                     /**< Mode NONE for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SOURCESEL_PRS                0x00000001UL                                     /**< Mode PRS for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SOURCESEL_ADC0               0x00000008UL                                     /**< Mode ADC0 for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SOURCESEL_USART0             0x0000000CUL                                     /**< Mode USART0 for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SOURCESEL_USART1             0x0000000DUL                                     /**< Mode USART1 for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SOURCESEL_LEUART0            0x00000010UL                                     /**< Mode LEUART0 for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SOURCESEL_I2C0               0x00000014UL                                     /**< Mode I2C0 for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SOURCESEL_TIMER0             0x00000018UL                                     /**< Mode TIMER0 for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SOURCESEL_TIMER1             0x00000019UL                                     /**< Mode TIMER1 for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SOURCESEL_MSC                0x00000030UL                                     /**< Mode MSC for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SOURCESEL_CRYPTO             0x00000031UL                                     /**< Mode CRYPTO for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SOURCESEL_NONE                (_LDMA_CH_REQSEL_SOURCESEL_NONE << 16)           /**< Shifted mode NONE for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SOURCESEL_PRS                 (_LDMA_CH_REQSEL_SOURCESEL_PRS << 16)            /**< Shifted mode PRS for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SOURCESEL_ADC0                (_LDMA_CH_REQSEL_SOURCESEL_ADC0 << 16)           /**< Shifted mode ADC0 for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SOURCESEL_USART0              (_LDMA_CH_REQSEL_SOURCESEL_USART0 << 16)         /**< Shifted mode USART0 for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SOURCESEL_USART1              (_LDMA_CH_REQSEL_SOURCESEL_USART1 << 16)         /**< Shifted mode USART1 for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SOURCESEL_LEUART0             (_LDMA_CH_REQSEL_SOURCESEL_LEUART0 << 16)        /**< Shifted mode LEUART0 for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SOURCESEL_I2C0                (_LDMA_CH_REQSEL_SOURCESEL_I2C0 << 16)           /**< Shifted mode I2C0 for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SOURCESEL_TIMER0              (_LDMA_CH_REQSEL_SOURCESEL_TIMER0 << 16)         /**< Shifted mode TIMER0 for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SOURCESEL_TIMER1              (_LDMA_CH_REQSEL_SOURCESEL_TIMER1 << 16)         /**< Shifted mode TIMER1 for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SOURCESEL_MSC                 (_LDMA_CH_REQSEL_SOURCESEL_MSC << 16)            /**< Shifted mode MSC for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SOURCESEL_CRYPTO              (_LDMA_CH_REQSEL_SOURCESEL_CRYPTO << 16)         /**< Shifted mode CRYPTO for LDMA_CH_REQSEL */
+
+/* Bit fields for LDMA CH_CFG */
+#define _LDMA_CH_CFG_RESETVALUE                      0x00000000UL                             /**< Default value for LDMA_CH_CFG */
+#define _LDMA_CH_CFG_MASK                            0x00330000UL                             /**< Mask for LDMA_CH_CFG */
+#define _LDMA_CH_CFG_ARBSLOTS_SHIFT                  16                                       /**< Shift value for LDMA_ARBSLOTS */
+#define _LDMA_CH_CFG_ARBSLOTS_MASK                   0x30000UL                                /**< Bit mask for LDMA_ARBSLOTS */
+#define _LDMA_CH_CFG_ARBSLOTS_DEFAULT                0x00000000UL                             /**< Mode DEFAULT for LDMA_CH_CFG */
+#define _LDMA_CH_CFG_ARBSLOTS_ONE                    0x00000000UL                             /**< Mode ONE for LDMA_CH_CFG */
+#define _LDMA_CH_CFG_ARBSLOTS_TWO                    0x00000001UL                             /**< Mode TWO for LDMA_CH_CFG */
+#define _LDMA_CH_CFG_ARBSLOTS_FOUR                   0x00000002UL                             /**< Mode FOUR for LDMA_CH_CFG */
+#define _LDMA_CH_CFG_ARBSLOTS_EIGHT                  0x00000003UL                             /**< Mode EIGHT for LDMA_CH_CFG */
+#define LDMA_CH_CFG_ARBSLOTS_DEFAULT                 (_LDMA_CH_CFG_ARBSLOTS_DEFAULT << 16)    /**< Shifted mode DEFAULT for LDMA_CH_CFG */
+#define LDMA_CH_CFG_ARBSLOTS_ONE                     (_LDMA_CH_CFG_ARBSLOTS_ONE << 16)        /**< Shifted mode ONE for LDMA_CH_CFG */
+#define LDMA_CH_CFG_ARBSLOTS_TWO                     (_LDMA_CH_CFG_ARBSLOTS_TWO << 16)        /**< Shifted mode TWO for LDMA_CH_CFG */
+#define LDMA_CH_CFG_ARBSLOTS_FOUR                    (_LDMA_CH_CFG_ARBSLOTS_FOUR << 16)       /**< Shifted mode FOUR for LDMA_CH_CFG */
+#define LDMA_CH_CFG_ARBSLOTS_EIGHT                   (_LDMA_CH_CFG_ARBSLOTS_EIGHT << 16)      /**< Shifted mode EIGHT for LDMA_CH_CFG */
+#define LDMA_CH_CFG_SRCINCSIGN                       (0x1UL << 20)                            /**< Source Address Increment Sign */
+#define _LDMA_CH_CFG_SRCINCSIGN_SHIFT                20                                       /**< Shift value for LDMA_SRCINCSIGN */
+#define _LDMA_CH_CFG_SRCINCSIGN_MASK                 0x100000UL                               /**< Bit mask for LDMA_SRCINCSIGN */
+#define _LDMA_CH_CFG_SRCINCSIGN_DEFAULT              0x00000000UL                             /**< Mode DEFAULT for LDMA_CH_CFG */
+#define _LDMA_CH_CFG_SRCINCSIGN_POSITIVE             0x00000000UL                             /**< Mode POSITIVE for LDMA_CH_CFG */
+#define _LDMA_CH_CFG_SRCINCSIGN_NEGATIVE             0x00000001UL                             /**< Mode NEGATIVE for LDMA_CH_CFG */
+#define LDMA_CH_CFG_SRCINCSIGN_DEFAULT               (_LDMA_CH_CFG_SRCINCSIGN_DEFAULT << 20)  /**< Shifted mode DEFAULT for LDMA_CH_CFG */
+#define LDMA_CH_CFG_SRCINCSIGN_POSITIVE              (_LDMA_CH_CFG_SRCINCSIGN_POSITIVE << 20) /**< Shifted mode POSITIVE for LDMA_CH_CFG */
+#define LDMA_CH_CFG_SRCINCSIGN_NEGATIVE              (_LDMA_CH_CFG_SRCINCSIGN_NEGATIVE << 20) /**< Shifted mode NEGATIVE for LDMA_CH_CFG */
+#define LDMA_CH_CFG_DSTINCSIGN                       (0x1UL << 21)                            /**< Destination Address Increment Sign */
+#define _LDMA_CH_CFG_DSTINCSIGN_SHIFT                21                                       /**< Shift value for LDMA_DSTINCSIGN */
+#define _LDMA_CH_CFG_DSTINCSIGN_MASK                 0x200000UL                               /**< Bit mask for LDMA_DSTINCSIGN */
+#define _LDMA_CH_CFG_DSTINCSIGN_DEFAULT              0x00000000UL                             /**< Mode DEFAULT for LDMA_CH_CFG */
+#define _LDMA_CH_CFG_DSTINCSIGN_POSITIVE             0x00000000UL                             /**< Mode POSITIVE for LDMA_CH_CFG */
+#define _LDMA_CH_CFG_DSTINCSIGN_NEGATIVE             0x00000001UL                             /**< Mode NEGATIVE for LDMA_CH_CFG */
+#define LDMA_CH_CFG_DSTINCSIGN_DEFAULT               (_LDMA_CH_CFG_DSTINCSIGN_DEFAULT << 21)  /**< Shifted mode DEFAULT for LDMA_CH_CFG */
+#define LDMA_CH_CFG_DSTINCSIGN_POSITIVE              (_LDMA_CH_CFG_DSTINCSIGN_POSITIVE << 21) /**< Shifted mode POSITIVE for LDMA_CH_CFG */
+#define LDMA_CH_CFG_DSTINCSIGN_NEGATIVE              (_LDMA_CH_CFG_DSTINCSIGN_NEGATIVE << 21) /**< Shifted mode NEGATIVE for LDMA_CH_CFG */
+
+/* Bit fields for LDMA CH_LOOP */
+#define _LDMA_CH_LOOP_RESETVALUE                     0x00000000UL                         /**< Default value for LDMA_CH_LOOP */
+#define _LDMA_CH_LOOP_MASK                           0x000000FFUL                         /**< Mask for LDMA_CH_LOOP */
+#define _LDMA_CH_LOOP_LOOPCNT_SHIFT                  0                                    /**< Shift value for LDMA_LOOPCNT */
+#define _LDMA_CH_LOOP_LOOPCNT_MASK                   0xFFUL                               /**< Bit mask for LDMA_LOOPCNT */
+#define _LDMA_CH_LOOP_LOOPCNT_DEFAULT                0x00000000UL                         /**< Mode DEFAULT for LDMA_CH_LOOP */
+#define LDMA_CH_LOOP_LOOPCNT_DEFAULT                 (_LDMA_CH_LOOP_LOOPCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_LOOP */
+
+/* Bit fields for LDMA CH_CTRL */
+#define _LDMA_CH_CTRL_RESETVALUE                     0x00000000UL                                /**< Default value for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_MASK                           0xFFFFFFFBUL                                /**< Mask for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_STRUCTTYPE_SHIFT               0                                           /**< Shift value for LDMA_STRUCTTYPE */
+#define _LDMA_CH_CTRL_STRUCTTYPE_MASK                0x3UL                                       /**< Bit mask for LDMA_STRUCTTYPE */
+#define _LDMA_CH_CTRL_STRUCTTYPE_DEFAULT             0x00000000UL                                /**< Mode DEFAULT for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_STRUCTTYPE_TRANSFER            0x00000000UL                                /**< Mode TRANSFER for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE         0x00000001UL                                /**< Mode SYNCHRONIZE for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_STRUCTTYPE_WRITE               0x00000002UL                                /**< Mode WRITE for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_STRUCTTYPE_DEFAULT              (_LDMA_CH_CTRL_STRUCTTYPE_DEFAULT << 0)     /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_STRUCTTYPE_TRANSFER             (_LDMA_CH_CTRL_STRUCTTYPE_TRANSFER << 0)    /**< Shifted mode TRANSFER for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE          (_LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE << 0) /**< Shifted mode SYNCHRONIZE for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_STRUCTTYPE_WRITE                (_LDMA_CH_CTRL_STRUCTTYPE_WRITE << 0)       /**< Shifted mode WRITE for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_STRUCTREQ                       (0x1UL << 3)                                /**< Structure DMA Transfer Request */
+#define _LDMA_CH_CTRL_STRUCTREQ_SHIFT                3                                           /**< Shift value for LDMA_STRUCTREQ */
+#define _LDMA_CH_CTRL_STRUCTREQ_MASK                 0x8UL                                       /**< Bit mask for LDMA_STRUCTREQ */
+#define _LDMA_CH_CTRL_STRUCTREQ_DEFAULT              0x00000000UL                                /**< Mode DEFAULT for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_STRUCTREQ_DEFAULT               (_LDMA_CH_CTRL_STRUCTREQ_DEFAULT << 3)      /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_XFERCNT_SHIFT                  4                                           /**< Shift value for LDMA_XFERCNT */
+#define _LDMA_CH_CTRL_XFERCNT_MASK                   0x7FF0UL                                    /**< Bit mask for LDMA_XFERCNT */
+#define _LDMA_CH_CTRL_XFERCNT_DEFAULT                0x00000000UL                                /**< Mode DEFAULT for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_XFERCNT_DEFAULT                 (_LDMA_CH_CTRL_XFERCNT_DEFAULT << 4)        /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_BYTESWAP                        (0x1UL << 15)                               /**< Endian Byte Swap */
+#define _LDMA_CH_CTRL_BYTESWAP_SHIFT                 15                                          /**< Shift value for LDMA_BYTESWAP */
+#define _LDMA_CH_CTRL_BYTESWAP_MASK                  0x8000UL                                    /**< Bit mask for LDMA_BYTESWAP */
+#define _LDMA_CH_CTRL_BYTESWAP_DEFAULT               0x00000000UL                                /**< Mode DEFAULT for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_BYTESWAP_DEFAULT                (_LDMA_CH_CTRL_BYTESWAP_DEFAULT << 15)      /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_BLOCKSIZE_SHIFT                16                                          /**< Shift value for LDMA_BLOCKSIZE */
+#define _LDMA_CH_CTRL_BLOCKSIZE_MASK                 0xF0000UL                                   /**< Bit mask for LDMA_BLOCKSIZE */
+#define _LDMA_CH_CTRL_BLOCKSIZE_DEFAULT              0x00000000UL                                /**< Mode DEFAULT for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT1                0x00000000UL                                /**< Mode UNIT1 for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT2                0x00000001UL                                /**< Mode UNIT2 for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT3                0x00000002UL                                /**< Mode UNIT3 for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT4                0x00000003UL                                /**< Mode UNIT4 for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT6                0x00000004UL                                /**< Mode UNIT6 for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT8                0x00000005UL                                /**< Mode UNIT8 for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT16               0x00000007UL                                /**< Mode UNIT16 for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT32               0x00000009UL                                /**< Mode UNIT32 for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT64               0x0000000AUL                                /**< Mode UNIT64 for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT128              0x0000000BUL                                /**< Mode UNIT128 for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT256              0x0000000CUL                                /**< Mode UNIT256 for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT512              0x0000000DUL                                /**< Mode UNIT512 for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT1024             0x0000000EUL                                /**< Mode UNIT1024 for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_BLOCKSIZE_ALL                  0x0000000FUL                                /**< Mode ALL for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_BLOCKSIZE_DEFAULT               (_LDMA_CH_CTRL_BLOCKSIZE_DEFAULT << 16)     /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_BLOCKSIZE_UNIT1                 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT1 << 16)       /**< Shifted mode UNIT1 for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_BLOCKSIZE_UNIT2                 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT2 << 16)       /**< Shifted mode UNIT2 for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_BLOCKSIZE_UNIT3                 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT3 << 16)       /**< Shifted mode UNIT3 for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_BLOCKSIZE_UNIT4                 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT4 << 16)       /**< Shifted mode UNIT4 for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_BLOCKSIZE_UNIT6                 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT6 << 16)       /**< Shifted mode UNIT6 for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_BLOCKSIZE_UNIT8                 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT8 << 16)       /**< Shifted mode UNIT8 for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_BLOCKSIZE_UNIT16                (_LDMA_CH_CTRL_BLOCKSIZE_UNIT16 << 16)      /**< Shifted mode UNIT16 for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_BLOCKSIZE_UNIT32                (_LDMA_CH_CTRL_BLOCKSIZE_UNIT32 << 16)      /**< Shifted mode UNIT32 for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_BLOCKSIZE_UNIT64                (_LDMA_CH_CTRL_BLOCKSIZE_UNIT64 << 16)      /**< Shifted mode UNIT64 for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_BLOCKSIZE_UNIT128               (_LDMA_CH_CTRL_BLOCKSIZE_UNIT128 << 16)     /**< Shifted mode UNIT128 for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_BLOCKSIZE_UNIT256               (_LDMA_CH_CTRL_BLOCKSIZE_UNIT256 << 16)     /**< Shifted mode UNIT256 for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_BLOCKSIZE_UNIT512               (_LDMA_CH_CTRL_BLOCKSIZE_UNIT512 << 16)     /**< Shifted mode UNIT512 for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_BLOCKSIZE_UNIT1024              (_LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 << 16)    /**< Shifted mode UNIT1024 for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_BLOCKSIZE_ALL                   (_LDMA_CH_CTRL_BLOCKSIZE_ALL << 16)         /**< Shifted mode ALL for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_DONEIFSEN                       (0x1UL << 20)                               /**< DMA Operation Done Interrupt Flag Set Enable */
+#define _LDMA_CH_CTRL_DONEIFSEN_SHIFT                20                                          /**< Shift value for LDMA_DONEIFSEN */
+#define _LDMA_CH_CTRL_DONEIFSEN_MASK                 0x100000UL                                  /**< Bit mask for LDMA_DONEIFSEN */
+#define _LDMA_CH_CTRL_DONEIFSEN_DEFAULT              0x00000000UL                                /**< Mode DEFAULT for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_DONEIFSEN_DEFAULT               (_LDMA_CH_CTRL_DONEIFSEN_DEFAULT << 20)     /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_REQMODE                         (0x1UL << 21)                               /**< DMA Request Transfer Mode Select */
+#define _LDMA_CH_CTRL_REQMODE_SHIFT                  21                                          /**< Shift value for LDMA_REQMODE */
+#define _LDMA_CH_CTRL_REQMODE_MASK                   0x200000UL                                  /**< Bit mask for LDMA_REQMODE */
+#define _LDMA_CH_CTRL_REQMODE_DEFAULT                0x00000000UL                                /**< Mode DEFAULT for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_REQMODE_BLOCK                  0x00000000UL                                /**< Mode BLOCK for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_REQMODE_ALL                    0x00000001UL                                /**< Mode ALL for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_REQMODE_DEFAULT                 (_LDMA_CH_CTRL_REQMODE_DEFAULT << 21)       /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_REQMODE_BLOCK                   (_LDMA_CH_CTRL_REQMODE_BLOCK << 21)         /**< Shifted mode BLOCK for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_REQMODE_ALL                     (_LDMA_CH_CTRL_REQMODE_ALL << 21)           /**< Shifted mode ALL for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_DECLOOPCNT                      (0x1UL << 22)                               /**< Decrement Loop Count */
+#define _LDMA_CH_CTRL_DECLOOPCNT_SHIFT               22                                          /**< Shift value for LDMA_DECLOOPCNT */
+#define _LDMA_CH_CTRL_DECLOOPCNT_MASK                0x400000UL                                  /**< Bit mask for LDMA_DECLOOPCNT */
+#define _LDMA_CH_CTRL_DECLOOPCNT_DEFAULT             0x00000000UL                                /**< Mode DEFAULT for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_DECLOOPCNT_DEFAULT              (_LDMA_CH_CTRL_DECLOOPCNT_DEFAULT << 22)    /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_IGNORESREQ                      (0x1UL << 23)                               /**< Ignore Sreq */
+#define _LDMA_CH_CTRL_IGNORESREQ_SHIFT               23                                          /**< Shift value for LDMA_IGNORESREQ */
+#define _LDMA_CH_CTRL_IGNORESREQ_MASK                0x800000UL                                  /**< Bit mask for LDMA_IGNORESREQ */
+#define _LDMA_CH_CTRL_IGNORESREQ_DEFAULT             0x00000000UL                                /**< Mode DEFAULT for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_IGNORESREQ_DEFAULT              (_LDMA_CH_CTRL_IGNORESREQ_DEFAULT << 23)    /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_SRCINC_SHIFT                   24                                          /**< Shift value for LDMA_SRCINC */
+#define _LDMA_CH_CTRL_SRCINC_MASK                    0x3000000UL                                 /**< Bit mask for LDMA_SRCINC */
+#define _LDMA_CH_CTRL_SRCINC_DEFAULT                 0x00000000UL                                /**< Mode DEFAULT for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_SRCINC_ONE                     0x00000000UL                                /**< Mode ONE for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_SRCINC_TWO                     0x00000001UL                                /**< Mode TWO for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_SRCINC_FOUR                    0x00000002UL                                /**< Mode FOUR for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_SRCINC_NONE                    0x00000003UL                                /**< Mode NONE for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_SRCINC_DEFAULT                  (_LDMA_CH_CTRL_SRCINC_DEFAULT << 24)        /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_SRCINC_ONE                      (_LDMA_CH_CTRL_SRCINC_ONE << 24)            /**< Shifted mode ONE for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_SRCINC_TWO                      (_LDMA_CH_CTRL_SRCINC_TWO << 24)            /**< Shifted mode TWO for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_SRCINC_FOUR                     (_LDMA_CH_CTRL_SRCINC_FOUR << 24)           /**< Shifted mode FOUR for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_SRCINC_NONE                     (_LDMA_CH_CTRL_SRCINC_NONE << 24)           /**< Shifted mode NONE for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_SIZE_SHIFT                     26                                          /**< Shift value for LDMA_SIZE */
+#define _LDMA_CH_CTRL_SIZE_MASK                      0xC000000UL                                 /**< Bit mask for LDMA_SIZE */
+#define _LDMA_CH_CTRL_SIZE_DEFAULT                   0x00000000UL                                /**< Mode DEFAULT for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_SIZE_BYTE                      0x00000000UL                                /**< Mode BYTE for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_SIZE_HALFWORD                  0x00000001UL                                /**< Mode HALFWORD for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_SIZE_WORD                      0x00000002UL                                /**< Mode WORD for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_SIZE_DEFAULT                    (_LDMA_CH_CTRL_SIZE_DEFAULT << 26)          /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_SIZE_BYTE                       (_LDMA_CH_CTRL_SIZE_BYTE << 26)             /**< Shifted mode BYTE for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_SIZE_HALFWORD                   (_LDMA_CH_CTRL_SIZE_HALFWORD << 26)         /**< Shifted mode HALFWORD for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_SIZE_WORD                       (_LDMA_CH_CTRL_SIZE_WORD << 26)             /**< Shifted mode WORD for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_DSTINC_SHIFT                   28                                          /**< Shift value for LDMA_DSTINC */
+#define _LDMA_CH_CTRL_DSTINC_MASK                    0x30000000UL                                /**< Bit mask for LDMA_DSTINC */
+#define _LDMA_CH_CTRL_DSTINC_DEFAULT                 0x00000000UL                                /**< Mode DEFAULT for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_DSTINC_ONE                     0x00000000UL                                /**< Mode ONE for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_DSTINC_TWO                     0x00000001UL                                /**< Mode TWO for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_DSTINC_FOUR                    0x00000002UL                                /**< Mode FOUR for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_DSTINC_NONE                    0x00000003UL                                /**< Mode NONE for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_DSTINC_DEFAULT                  (_LDMA_CH_CTRL_DSTINC_DEFAULT << 28)        /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_DSTINC_ONE                      (_LDMA_CH_CTRL_DSTINC_ONE << 28)            /**< Shifted mode ONE for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_DSTINC_TWO                      (_LDMA_CH_CTRL_DSTINC_TWO << 28)            /**< Shifted mode TWO for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_DSTINC_FOUR                     (_LDMA_CH_CTRL_DSTINC_FOUR << 28)           /**< Shifted mode FOUR for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_DSTINC_NONE                     (_LDMA_CH_CTRL_DSTINC_NONE << 28)           /**< Shifted mode NONE for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_SRCMODE                         (0x1UL << 30)                               /**< Source Addressing Mode */
+#define _LDMA_CH_CTRL_SRCMODE_SHIFT                  30                                          /**< Shift value for LDMA_SRCMODE */
+#define _LDMA_CH_CTRL_SRCMODE_MASK                   0x40000000UL                                /**< Bit mask for LDMA_SRCMODE */
+#define _LDMA_CH_CTRL_SRCMODE_DEFAULT                0x00000000UL                                /**< Mode DEFAULT for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_SRCMODE_ABSOLUTE               0x00000000UL                                /**< Mode ABSOLUTE for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_SRCMODE_RELATIVE               0x00000001UL                                /**< Mode RELATIVE for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_SRCMODE_DEFAULT                 (_LDMA_CH_CTRL_SRCMODE_DEFAULT << 30)       /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_SRCMODE_ABSOLUTE                (_LDMA_CH_CTRL_SRCMODE_ABSOLUTE << 30)      /**< Shifted mode ABSOLUTE for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_SRCMODE_RELATIVE                (_LDMA_CH_CTRL_SRCMODE_RELATIVE << 30)      /**< Shifted mode RELATIVE for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_DSTMODE                         (0x1UL << 31)                               /**< Destination Addressing Mode */
+#define _LDMA_CH_CTRL_DSTMODE_SHIFT                  31                                          /**< Shift value for LDMA_DSTMODE */
+#define _LDMA_CH_CTRL_DSTMODE_MASK                   0x80000000UL                                /**< Bit mask for LDMA_DSTMODE */
+#define _LDMA_CH_CTRL_DSTMODE_DEFAULT                0x00000000UL                                /**< Mode DEFAULT for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_DSTMODE_ABSOLUTE               0x00000000UL                                /**< Mode ABSOLUTE for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_DSTMODE_RELATIVE               0x00000001UL                                /**< Mode RELATIVE for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_DSTMODE_DEFAULT                 (_LDMA_CH_CTRL_DSTMODE_DEFAULT << 31)       /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_DSTMODE_ABSOLUTE                (_LDMA_CH_CTRL_DSTMODE_ABSOLUTE << 31)      /**< Shifted mode ABSOLUTE for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_DSTMODE_RELATIVE                (_LDMA_CH_CTRL_DSTMODE_RELATIVE << 31)      /**< Shifted mode RELATIVE for LDMA_CH_CTRL */
+
+/* Bit fields for LDMA CH_SRC */
+#define _LDMA_CH_SRC_RESETVALUE                      0x00000000UL                        /**< Default value for LDMA_CH_SRC */
+#define _LDMA_CH_SRC_MASK                            0xFFFFFFFFUL                        /**< Mask for LDMA_CH_SRC */
+#define _LDMA_CH_SRC_SRCADDR_SHIFT                   0                                   /**< Shift value for LDMA_SRCADDR */
+#define _LDMA_CH_SRC_SRCADDR_MASK                    0xFFFFFFFFUL                        /**< Bit mask for LDMA_SRCADDR */
+#define _LDMA_CH_SRC_SRCADDR_DEFAULT                 0x00000000UL                        /**< Mode DEFAULT for LDMA_CH_SRC */
+#define LDMA_CH_SRC_SRCADDR_DEFAULT                  (_LDMA_CH_SRC_SRCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_SRC */
+
+/* Bit fields for LDMA CH_DST */
+#define _LDMA_CH_DST_RESETVALUE                      0x00000000UL                        /**< Default value for LDMA_CH_DST */
+#define _LDMA_CH_DST_MASK                            0xFFFFFFFFUL                        /**< Mask for LDMA_CH_DST */
+#define _LDMA_CH_DST_DSTADDR_SHIFT                   0                                   /**< Shift value for LDMA_DSTADDR */
+#define _LDMA_CH_DST_DSTADDR_MASK                    0xFFFFFFFFUL                        /**< Bit mask for LDMA_DSTADDR */
+#define _LDMA_CH_DST_DSTADDR_DEFAULT                 0x00000000UL                        /**< Mode DEFAULT for LDMA_CH_DST */
+#define LDMA_CH_DST_DSTADDR_DEFAULT                  (_LDMA_CH_DST_DSTADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_DST */
+
+/* Bit fields for LDMA CH_LINK */
+#define _LDMA_CH_LINK_RESETVALUE                     0x00000000UL                           /**< Default value for LDMA_CH_LINK */
+#define _LDMA_CH_LINK_MASK                           0xFFFFFFFFUL                           /**< Mask for LDMA_CH_LINK */
+#define LDMA_CH_LINK_LINKMODE                        (0x1UL << 0)                           /**< Link Structure Addressing Mode */
+#define _LDMA_CH_LINK_LINKMODE_SHIFT                 0                                      /**< Shift value for LDMA_LINKMODE */
+#define _LDMA_CH_LINK_LINKMODE_MASK                  0x1UL                                  /**< Bit mask for LDMA_LINKMODE */
+#define _LDMA_CH_LINK_LINKMODE_DEFAULT               0x00000000UL                           /**< Mode DEFAULT for LDMA_CH_LINK */
+#define _LDMA_CH_LINK_LINKMODE_ABSOLUTE              0x00000000UL                           /**< Mode ABSOLUTE for LDMA_CH_LINK */
+#define _LDMA_CH_LINK_LINKMODE_RELATIVE              0x00000001UL                           /**< Mode RELATIVE for LDMA_CH_LINK */
+#define LDMA_CH_LINK_LINKMODE_DEFAULT                (_LDMA_CH_LINK_LINKMODE_DEFAULT << 0)  /**< Shifted mode DEFAULT for LDMA_CH_LINK */
+#define LDMA_CH_LINK_LINKMODE_ABSOLUTE               (_LDMA_CH_LINK_LINKMODE_ABSOLUTE << 0) /**< Shifted mode ABSOLUTE for LDMA_CH_LINK */
+#define LDMA_CH_LINK_LINKMODE_RELATIVE               (_LDMA_CH_LINK_LINKMODE_RELATIVE << 0) /**< Shifted mode RELATIVE for LDMA_CH_LINK */
+#define LDMA_CH_LINK_LINK                            (0x1UL << 1)                           /**< Link Next Structure */
+#define _LDMA_CH_LINK_LINK_SHIFT                     1                                      /**< Shift value for LDMA_LINK */
+#define _LDMA_CH_LINK_LINK_MASK                      0x2UL                                  /**< Bit mask for LDMA_LINK */
+#define _LDMA_CH_LINK_LINK_DEFAULT                   0x00000000UL                           /**< Mode DEFAULT for LDMA_CH_LINK */
+#define LDMA_CH_LINK_LINK_DEFAULT                    (_LDMA_CH_LINK_LINK_DEFAULT << 1)      /**< Shifted mode DEFAULT for LDMA_CH_LINK */
+#define _LDMA_CH_LINK_LINKADDR_SHIFT                 2                                      /**< Shift value for LDMA_LINKADDR */
+#define _LDMA_CH_LINK_LINKADDR_MASK                  0xFFFFFFFCUL                           /**< Bit mask for LDMA_LINKADDR */
+#define _LDMA_CH_LINK_LINKADDR_DEFAULT               0x00000000UL                           /**< Mode DEFAULT for LDMA_CH_LINK */
+#define LDMA_CH_LINK_LINKADDR_DEFAULT                (_LDMA_CH_LINK_LINKADDR_DEFAULT << 2)  /**< Shifted mode DEFAULT for LDMA_CH_LINK */
+
+/** @} End of group EFM32PG1B_LDMA */
+/** @} End of group Parts */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG_STK3401/efm32pg1b_ldma_ch.h	Fri Jan 15 07:45:16 2016 +0000
@@ -0,0 +1,53 @@
+/**************************************************************************//**
+ * @file efm32pg1b_ldma_ch.h
+ * @brief EFM32PG1B_LDMA_CH register and bit field definitions
+ * @version 4.2.0
+ ******************************************************************************
+ * @section License
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ ******************************************************************************
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software.@n
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.@n
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is
+ * providing the Software "AS IS", with no express or implied warranties of any
+ * kind, including, but not limited to, any implied warranties of
+ * merchantability or fitness for any particular purpose or warranties against
+ * infringement of any proprietary rights of a third party.
+ *
+ * Silicon Laboratories, Inc. will not be liable for any consequential,
+ * incidental, or special damages, or any other relief, or for any claim by
+ * any third party, arising from your use of this Software.
+ *
+ *****************************************************************************/
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @brief LDMA_CH EFM32PG1B LDMA CH
+ *****************************************************************************/
+typedef struct
+{
+  __IO uint32_t REQSEL;       /**< Channel Peripheral Request Select Register  */
+  __IO uint32_t CFG;          /**< Channel Configuration Register  */
+  __IO uint32_t LOOP;         /**< Channel Loop Counter Register  */
+  __IO uint32_t CTRL;         /**< Channel Descriptor Control Word Register  */
+  __IO uint32_t SRC;          /**< Channel Descriptor Source Data Address Register  */
+  __IO uint32_t DST;          /**< Channel Descriptor Destination Data Address Register  */
+  __IO uint32_t LINK;         /**< Channel Descriptor Link Structure Address Register  */
+  uint32_t      RESERVED0[5]; /**< Reserved future */
+} LDMA_CH_TypeDef;
+
+/** @} End of group Parts */
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG_STK3401/efm32pg1b_letimer.h	Fri Jan 15 07:45:16 2016 +0000
@@ -0,0 +1,620 @@
+/**************************************************************************//**
+ * @file efm32pg1b_letimer.h
+ * @brief EFM32PG1B_LETIMER register and bit field definitions
+ * @version 4.2.0
+ ******************************************************************************
+ * @section License
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ ******************************************************************************
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software.@n
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.@n
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is
+ * providing the Software "AS IS", with no express or implied warranties of any
+ * kind, including, but not limited to, any implied warranties of
+ * merchantability or fitness for any particular purpose or warranties against
+ * infringement of any proprietary rights of a third party.
+ *
+ * Silicon Laboratories, Inc. will not be liable for any consequential,
+ * incidental, or special damages, or any other relief, or for any claim by
+ * any third party, arising from your use of this Software.
+ *
+ *****************************************************************************/
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFM32PG1B_LETIMER
+ * @{
+ * @brief EFM32PG1B_LETIMER Register Declaration
+ *****************************************************************************/
+typedef struct
+{
+  __IO uint32_t CTRL;         /**< Control Register  */
+  __IO uint32_t CMD;          /**< Command Register  */
+  __I uint32_t  STATUS;       /**< Status Register  */
+  __IO uint32_t CNT;          /**< Counter Value Register  */
+  __IO uint32_t COMP0;        /**< Compare Value Register 0  */
+  __IO uint32_t COMP1;        /**< Compare Value Register 1  */
+  __IO uint32_t REP0;         /**< Repeat Counter Register 0  */
+  __IO uint32_t REP1;         /**< Repeat Counter Register 1  */
+  __I uint32_t  IF;           /**< Interrupt Flag Register  */
+  __IO uint32_t IFS;          /**< Interrupt Flag Set Register  */
+  __IO uint32_t IFC;          /**< Interrupt Flag Clear Register  */
+  __IO uint32_t IEN;          /**< Interrupt Enable Register  */
+
+  uint32_t      RESERVED0[1]; /**< Reserved for future use **/
+  __I uint32_t  SYNCBUSY;     /**< Synchronization Busy Register  */
+
+  uint32_t      RESERVED1[2]; /**< Reserved for future use **/
+  __IO uint32_t ROUTEPEN;     /**< I/O Routing Pin Enable Register  */
+  __IO uint32_t ROUTELOC0;    /**< I/O Routing Location Register  */
+
+  uint32_t      RESERVED2[2]; /**< Reserved for future use **/
+  __IO uint32_t PRSSEL;       /**< PRS Input Select Register  */
+} LETIMER_TypeDef;            /** @} */
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B_LETIMER_BitFields
+ * @{
+ *****************************************************************************/
+
+/* Bit fields for LETIMER CTRL */
+#define _LETIMER_CTRL_RESETVALUE                0x00000000UL                           /**< Default value for LETIMER_CTRL */
+#define _LETIMER_CTRL_MASK                      0x000013FFUL                           /**< Mask for LETIMER_CTRL */
+#define _LETIMER_CTRL_REPMODE_SHIFT             0                                      /**< Shift value for LETIMER_REPMODE */
+#define _LETIMER_CTRL_REPMODE_MASK              0x3UL                                  /**< Bit mask for LETIMER_REPMODE */
+#define _LETIMER_CTRL_REPMODE_DEFAULT           0x00000000UL                           /**< Mode DEFAULT for LETIMER_CTRL */
+#define _LETIMER_CTRL_REPMODE_FREE              0x00000000UL                           /**< Mode FREE for LETIMER_CTRL */
+#define _LETIMER_CTRL_REPMODE_ONESHOT           0x00000001UL                           /**< Mode ONESHOT for LETIMER_CTRL */
+#define _LETIMER_CTRL_REPMODE_BUFFERED          0x00000002UL                           /**< Mode BUFFERED for LETIMER_CTRL */
+#define _LETIMER_CTRL_REPMODE_DOUBLE            0x00000003UL                           /**< Mode DOUBLE for LETIMER_CTRL */
+#define LETIMER_CTRL_REPMODE_DEFAULT            (_LETIMER_CTRL_REPMODE_DEFAULT << 0)   /**< Shifted mode DEFAULT for LETIMER_CTRL */
+#define LETIMER_CTRL_REPMODE_FREE               (_LETIMER_CTRL_REPMODE_FREE << 0)      /**< Shifted mode FREE for LETIMER_CTRL */
+#define LETIMER_CTRL_REPMODE_ONESHOT            (_LETIMER_CTRL_REPMODE_ONESHOT << 0)   /**< Shifted mode ONESHOT for LETIMER_CTRL */
+#define LETIMER_CTRL_REPMODE_BUFFERED           (_LETIMER_CTRL_REPMODE_BUFFERED << 0)  /**< Shifted mode BUFFERED for LETIMER_CTRL */
+#define LETIMER_CTRL_REPMODE_DOUBLE             (_LETIMER_CTRL_REPMODE_DOUBLE << 0)    /**< Shifted mode DOUBLE for LETIMER_CTRL */
+#define _LETIMER_CTRL_UFOA0_SHIFT               2                                      /**< Shift value for LETIMER_UFOA0 */
+#define _LETIMER_CTRL_UFOA0_MASK                0xCUL                                  /**< Bit mask for LETIMER_UFOA0 */
+#define _LETIMER_CTRL_UFOA0_DEFAULT             0x00000000UL                           /**< Mode DEFAULT for LETIMER_CTRL */
+#define _LETIMER_CTRL_UFOA0_NONE                0x00000000UL                           /**< Mode NONE for LETIMER_CTRL */
+#define _LETIMER_CTRL_UFOA0_TOGGLE              0x00000001UL                           /**< Mode TOGGLE for LETIMER_CTRL */
+#define _LETIMER_CTRL_UFOA0_PULSE               0x00000002UL                           /**< Mode PULSE for LETIMER_CTRL */
+#define _LETIMER_CTRL_UFOA0_PWM                 0x00000003UL                           /**< Mode PWM for LETIMER_CTRL */
+#define LETIMER_CTRL_UFOA0_DEFAULT              (_LETIMER_CTRL_UFOA0_DEFAULT << 2)     /**< Shifted mode DEFAULT for LETIMER_CTRL */
+#define LETIMER_CTRL_UFOA0_NONE                 (_LETIMER_CTRL_UFOA0_NONE << 2)        /**< Shifted mode NONE for LETIMER_CTRL */
+#define LETIMER_CTRL_UFOA0_TOGGLE               (_LETIMER_CTRL_UFOA0_TOGGLE << 2)      /**< Shifted mode TOGGLE for LETIMER_CTRL */
+#define LETIMER_CTRL_UFOA0_PULSE                (_LETIMER_CTRL_UFOA0_PULSE << 2)       /**< Shifted mode PULSE for LETIMER_CTRL */
+#define LETIMER_CTRL_UFOA0_PWM                  (_LETIMER_CTRL_UFOA0_PWM << 2)         /**< Shifted mode PWM for LETIMER_CTRL */
+#define _LETIMER_CTRL_UFOA1_SHIFT               4                                      /**< Shift value for LETIMER_UFOA1 */
+#define _LETIMER_CTRL_UFOA1_MASK                0x30UL                                 /**< Bit mask for LETIMER_UFOA1 */
+#define _LETIMER_CTRL_UFOA1_DEFAULT             0x00000000UL                           /**< Mode DEFAULT for LETIMER_CTRL */
+#define _LETIMER_CTRL_UFOA1_NONE                0x00000000UL                           /**< Mode NONE for LETIMER_CTRL */
+#define _LETIMER_CTRL_UFOA1_TOGGLE              0x00000001UL                           /**< Mode TOGGLE for LETIMER_CTRL */
+#define _LETIMER_CTRL_UFOA1_PULSE               0x00000002UL                           /**< Mode PULSE for LETIMER_CTRL */
+#define _LETIMER_CTRL_UFOA1_PWM                 0x00000003UL                           /**< Mode PWM for LETIMER_CTRL */
+#define LETIMER_CTRL_UFOA1_DEFAULT              (_LETIMER_CTRL_UFOA1_DEFAULT << 4)     /**< Shifted mode DEFAULT for LETIMER_CTRL */
+#define LETIMER_CTRL_UFOA1_NONE                 (_LETIMER_CTRL_UFOA1_NONE << 4)        /**< Shifted mode NONE for LETIMER_CTRL */
+#define LETIMER_CTRL_UFOA1_TOGGLE               (_LETIMER_CTRL_UFOA1_TOGGLE << 4)      /**< Shifted mode TOGGLE for LETIMER_CTRL */
+#define LETIMER_CTRL_UFOA1_PULSE                (_LETIMER_CTRL_UFOA1_PULSE << 4)       /**< Shifted mode PULSE for LETIMER_CTRL */
+#define LETIMER_CTRL_UFOA1_PWM                  (_LETIMER_CTRL_UFOA1_PWM << 4)         /**< Shifted mode PWM for LETIMER_CTRL */
+#define LETIMER_CTRL_OPOL0                      (0x1UL << 6)                           /**< Output 0 Polarity */
+#define _LETIMER_CTRL_OPOL0_SHIFT               6                                      /**< Shift value for LETIMER_OPOL0 */
+#define _LETIMER_CTRL_OPOL0_MASK                0x40UL                                 /**< Bit mask for LETIMER_OPOL0 */
+#define _LETIMER_CTRL_OPOL0_DEFAULT             0x00000000UL                           /**< Mode DEFAULT for LETIMER_CTRL */
+#define LETIMER_CTRL_OPOL0_DEFAULT              (_LETIMER_CTRL_OPOL0_DEFAULT << 6)     /**< Shifted mode DEFAULT for LETIMER_CTRL */
+#define LETIMER_CTRL_OPOL1                      (0x1UL << 7)                           /**< Output 1 Polarity */
+#define _LETIMER_CTRL_OPOL1_SHIFT               7                                      /**< Shift value for LETIMER_OPOL1 */
+#define _LETIMER_CTRL_OPOL1_MASK                0x80UL                                 /**< Bit mask for LETIMER_OPOL1 */
+#define _LETIMER_CTRL_OPOL1_DEFAULT             0x00000000UL                           /**< Mode DEFAULT for LETIMER_CTRL */
+#define LETIMER_CTRL_OPOL1_DEFAULT              (_LETIMER_CTRL_OPOL1_DEFAULT << 7)     /**< Shifted mode DEFAULT for LETIMER_CTRL */
+#define LETIMER_CTRL_BUFTOP                     (0x1UL << 8)                           /**< Buffered Top */
+#define _LETIMER_CTRL_BUFTOP_SHIFT              8                                      /**< Shift value for LETIMER_BUFTOP */
+#define _LETIMER_CTRL_BUFTOP_MASK               0x100UL                                /**< Bit mask for LETIMER_BUFTOP */
+#define _LETIMER_CTRL_BUFTOP_DEFAULT            0x00000000UL                           /**< Mode DEFAULT for LETIMER_CTRL */
+#define LETIMER_CTRL_BUFTOP_DEFAULT             (_LETIMER_CTRL_BUFTOP_DEFAULT << 8)    /**< Shifted mode DEFAULT for LETIMER_CTRL */
+#define LETIMER_CTRL_COMP0TOP                   (0x1UL << 9)                           /**< Compare Value 0 Is Top Value */
+#define _LETIMER_CTRL_COMP0TOP_SHIFT            9                                      /**< Shift value for LETIMER_COMP0TOP */
+#define _LETIMER_CTRL_COMP0TOP_MASK             0x200UL                                /**< Bit mask for LETIMER_COMP0TOP */
+#define _LETIMER_CTRL_COMP0TOP_DEFAULT          0x00000000UL                           /**< Mode DEFAULT for LETIMER_CTRL */
+#define LETIMER_CTRL_COMP0TOP_DEFAULT           (_LETIMER_CTRL_COMP0TOP_DEFAULT << 9)  /**< Shifted mode DEFAULT for LETIMER_CTRL */
+#define LETIMER_CTRL_DEBUGRUN                   (0x1UL << 12)                          /**< Debug Mode Run Enable */
+#define _LETIMER_CTRL_DEBUGRUN_SHIFT            12                                     /**< Shift value for LETIMER_DEBUGRUN */
+#define _LETIMER_CTRL_DEBUGRUN_MASK             0x1000UL                               /**< Bit mask for LETIMER_DEBUGRUN */
+#define _LETIMER_CTRL_DEBUGRUN_DEFAULT          0x00000000UL                           /**< Mode DEFAULT for LETIMER_CTRL */
+#define LETIMER_CTRL_DEBUGRUN_DEFAULT           (_LETIMER_CTRL_DEBUGRUN_DEFAULT << 12) /**< Shifted mode DEFAULT for LETIMER_CTRL */
+
+/* Bit fields for LETIMER CMD */
+#define _LETIMER_CMD_RESETVALUE                 0x00000000UL                      /**< Default value for LETIMER_CMD */
+#define _LETIMER_CMD_MASK                       0x0000001FUL                      /**< Mask for LETIMER_CMD */
+#define LETIMER_CMD_START                       (0x1UL << 0)                      /**< Start LETIMER */
+#define _LETIMER_CMD_START_SHIFT                0                                 /**< Shift value for LETIMER_START */
+#define _LETIMER_CMD_START_MASK                 0x1UL                             /**< Bit mask for LETIMER_START */
+#define _LETIMER_CMD_START_DEFAULT              0x00000000UL                      /**< Mode DEFAULT for LETIMER_CMD */
+#define LETIMER_CMD_START_DEFAULT               (_LETIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CMD */
+#define LETIMER_CMD_STOP                        (0x1UL << 1)                      /**< Stop LETIMER */
+#define _LETIMER_CMD_STOP_SHIFT                 1                                 /**< Shift value for LETIMER_STOP */
+#define _LETIMER_CMD_STOP_MASK                  0x2UL                             /**< Bit mask for LETIMER_STOP */
+#define _LETIMER_CMD_STOP_DEFAULT               0x00000000UL                      /**< Mode DEFAULT for LETIMER_CMD */
+#define LETIMER_CMD_STOP_DEFAULT                (_LETIMER_CMD_STOP_DEFAULT << 1)  /**< Shifted mode DEFAULT for LETIMER_CMD */
+#define LETIMER_CMD_CLEAR                       (0x1UL << 2)                      /**< Clear LETIMER */
+#define _LETIMER_CMD_CLEAR_SHIFT                2                                 /**< Shift value for LETIMER_CLEAR */
+#define _LETIMER_CMD_CLEAR_MASK                 0x4UL                             /**< Bit mask for LETIMER_CLEAR */
+#define _LETIMER_CMD_CLEAR_DEFAULT              0x00000000UL                      /**< Mode DEFAULT for LETIMER_CMD */
+#define LETIMER_CMD_CLEAR_DEFAULT               (_LETIMER_CMD_CLEAR_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_CMD */
+#define LETIMER_CMD_CTO0                        (0x1UL << 3)                      /**< Clear Toggle Output 0 */
+#define _LETIMER_CMD_CTO0_SHIFT                 3                                 /**< Shift value for LETIMER_CTO0 */
+#define _LETIMER_CMD_CTO0_MASK                  0x8UL                             /**< Bit mask for LETIMER_CTO0 */
+#define _LETIMER_CMD_CTO0_DEFAULT               0x00000000UL                      /**< Mode DEFAULT for LETIMER_CMD */
+#define LETIMER_CMD_CTO0_DEFAULT                (_LETIMER_CMD_CTO0_DEFAULT << 3)  /**< Shifted mode DEFAULT for LETIMER_CMD */
+#define LETIMER_CMD_CTO1                        (0x1UL << 4)                      /**< Clear Toggle Output 1 */
+#define _LETIMER_CMD_CTO1_SHIFT                 4                                 /**< Shift value for LETIMER_CTO1 */
+#define _LETIMER_CMD_CTO1_MASK                  0x10UL                            /**< Bit mask for LETIMER_CTO1 */
+#define _LETIMER_CMD_CTO1_DEFAULT               0x00000000UL                      /**< Mode DEFAULT for LETIMER_CMD */
+#define LETIMER_CMD_CTO1_DEFAULT                (_LETIMER_CMD_CTO1_DEFAULT << 4)  /**< Shifted mode DEFAULT for LETIMER_CMD */
+
+/* Bit fields for LETIMER STATUS */
+#define _LETIMER_STATUS_RESETVALUE              0x00000000UL                           /**< Default value for LETIMER_STATUS */
+#define _LETIMER_STATUS_MASK                    0x00000001UL                           /**< Mask for LETIMER_STATUS */
+#define LETIMER_STATUS_RUNNING                  (0x1UL << 0)                           /**< LETIMER Running */
+#define _LETIMER_STATUS_RUNNING_SHIFT           0                                      /**< Shift value for LETIMER_RUNNING */
+#define _LETIMER_STATUS_RUNNING_MASK            0x1UL                                  /**< Bit mask for LETIMER_RUNNING */
+#define _LETIMER_STATUS_RUNNING_DEFAULT         0x00000000UL                           /**< Mode DEFAULT for LETIMER_STATUS */
+#define LETIMER_STATUS_RUNNING_DEFAULT          (_LETIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_STATUS */
+
+/* Bit fields for LETIMER CNT */
+#define _LETIMER_CNT_RESETVALUE                 0x00000000UL                    /**< Default value for LETIMER_CNT */
+#define _LETIMER_CNT_MASK                       0x0000FFFFUL                    /**< Mask for LETIMER_CNT */
+#define _LETIMER_CNT_CNT_SHIFT                  0                               /**< Shift value for LETIMER_CNT */
+#define _LETIMER_CNT_CNT_MASK                   0xFFFFUL                        /**< Bit mask for LETIMER_CNT */
+#define _LETIMER_CNT_CNT_DEFAULT                0x00000000UL                    /**< Mode DEFAULT for LETIMER_CNT */
+#define LETIMER_CNT_CNT_DEFAULT                 (_LETIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CNT */
+
+/* Bit fields for LETIMER COMP0 */
+#define _LETIMER_COMP0_RESETVALUE               0x00000000UL                        /**< Default value for LETIMER_COMP0 */
+#define _LETIMER_COMP0_MASK                     0x0000FFFFUL                        /**< Mask for LETIMER_COMP0 */
+#define _LETIMER_COMP0_COMP0_SHIFT              0                                   /**< Shift value for LETIMER_COMP0 */
+#define _LETIMER_COMP0_COMP0_MASK               0xFFFFUL                            /**< Bit mask for LETIMER_COMP0 */
+#define _LETIMER_COMP0_COMP0_DEFAULT            0x00000000UL                        /**< Mode DEFAULT for LETIMER_COMP0 */
+#define LETIMER_COMP0_COMP0_DEFAULT             (_LETIMER_COMP0_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_COMP0 */
+
+/* Bit fields for LETIMER COMP1 */
+#define _LETIMER_COMP1_RESETVALUE               0x00000000UL                        /**< Default value for LETIMER_COMP1 */
+#define _LETIMER_COMP1_MASK                     0x0000FFFFUL                        /**< Mask for LETIMER_COMP1 */
+#define _LETIMER_COMP1_COMP1_SHIFT              0                                   /**< Shift value for LETIMER_COMP1 */
+#define _LETIMER_COMP1_COMP1_MASK               0xFFFFUL                            /**< Bit mask for LETIMER_COMP1 */
+#define _LETIMER_COMP1_COMP1_DEFAULT            0x00000000UL                        /**< Mode DEFAULT for LETIMER_COMP1 */
+#define LETIMER_COMP1_COMP1_DEFAULT             (_LETIMER_COMP1_COMP1_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_COMP1 */
+
+/* Bit fields for LETIMER REP0 */
+#define _LETIMER_REP0_RESETVALUE                0x00000000UL                      /**< Default value for LETIMER_REP0 */
+#define _LETIMER_REP0_MASK                      0x000000FFUL                      /**< Mask for LETIMER_REP0 */
+#define _LETIMER_REP0_REP0_SHIFT                0                                 /**< Shift value for LETIMER_REP0 */
+#define _LETIMER_REP0_REP0_MASK                 0xFFUL                            /**< Bit mask for LETIMER_REP0 */
+#define _LETIMER_REP0_REP0_DEFAULT              0x00000000UL                      /**< Mode DEFAULT for LETIMER_REP0 */
+#define LETIMER_REP0_REP0_DEFAULT               (_LETIMER_REP0_REP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_REP0 */
+
+/* Bit fields for LETIMER REP1 */
+#define _LETIMER_REP1_RESETVALUE                0x00000000UL                      /**< Default value for LETIMER_REP1 */
+#define _LETIMER_REP1_MASK                      0x000000FFUL                      /**< Mask for LETIMER_REP1 */
+#define _LETIMER_REP1_REP1_SHIFT                0                                 /**< Shift value for LETIMER_REP1 */
+#define _LETIMER_REP1_REP1_MASK                 0xFFUL                            /**< Bit mask for LETIMER_REP1 */
+#define _LETIMER_REP1_REP1_DEFAULT              0x00000000UL                      /**< Mode DEFAULT for LETIMER_REP1 */
+#define LETIMER_REP1_REP1_DEFAULT               (_LETIMER_REP1_REP1_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_REP1 */
+
+/* Bit fields for LETIMER IF */
+#define _LETIMER_IF_RESETVALUE                  0x00000000UL                     /**< Default value for LETIMER_IF */
+#define _LETIMER_IF_MASK                        0x0000001FUL                     /**< Mask for LETIMER_IF */
+#define LETIMER_IF_COMP0                        (0x1UL << 0)                     /**< Compare Match 0 Interrupt Flag */
+#define _LETIMER_IF_COMP0_SHIFT                 0                                /**< Shift value for LETIMER_COMP0 */
+#define _LETIMER_IF_COMP0_MASK                  0x1UL                            /**< Bit mask for LETIMER_COMP0 */
+#define _LETIMER_IF_COMP0_DEFAULT               0x00000000UL                     /**< Mode DEFAULT for LETIMER_IF */
+#define LETIMER_IF_COMP0_DEFAULT                (_LETIMER_IF_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IF */
+#define LETIMER_IF_COMP1                        (0x1UL << 1)                     /**< Compare Match 1 Interrupt Flag */
+#define _LETIMER_IF_COMP1_SHIFT                 1                                /**< Shift value for LETIMER_COMP1 */
+#define _LETIMER_IF_COMP1_MASK                  0x2UL                            /**< Bit mask for LETIMER_COMP1 */
+#define _LETIMER_IF_COMP1_DEFAULT               0x00000000UL                     /**< Mode DEFAULT for LETIMER_IF */
+#define LETIMER_IF_COMP1_DEFAULT                (_LETIMER_IF_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IF */
+#define LETIMER_IF_UF                           (0x1UL << 2)                     /**< Underflow Interrupt Flag */
+#define _LETIMER_IF_UF_SHIFT                    2                                /**< Shift value for LETIMER_UF */
+#define _LETIMER_IF_UF_MASK                     0x4UL                            /**< Bit mask for LETIMER_UF */
+#define _LETIMER_IF_UF_DEFAULT                  0x00000000UL                     /**< Mode DEFAULT for LETIMER_IF */
+#define LETIMER_IF_UF_DEFAULT                   (_LETIMER_IF_UF_DEFAULT << 2)    /**< Shifted mode DEFAULT for LETIMER_IF */
+#define LETIMER_IF_REP0                         (0x1UL << 3)                     /**< Repeat Counter 0 Interrupt Flag */
+#define _LETIMER_IF_REP0_SHIFT                  3                                /**< Shift value for LETIMER_REP0 */
+#define _LETIMER_IF_REP0_MASK                   0x8UL                            /**< Bit mask for LETIMER_REP0 */
+#define _LETIMER_IF_REP0_DEFAULT                0x00000000UL                     /**< Mode DEFAULT for LETIMER_IF */
+#define LETIMER_IF_REP0_DEFAULT                 (_LETIMER_IF_REP0_DEFAULT << 3)  /**< Shifted mode DEFAULT for LETIMER_IF */
+#define LETIMER_IF_REP1                         (0x1UL << 4)                     /**< Repeat Counter 1 Interrupt Flag */
+#define _LETIMER_IF_REP1_SHIFT                  4                                /**< Shift value for LETIMER_REP1 */
+#define _LETIMER_IF_REP1_MASK                   0x10UL                           /**< Bit mask for LETIMER_REP1 */
+#define _LETIMER_IF_REP1_DEFAULT                0x00000000UL                     /**< Mode DEFAULT for LETIMER_IF */
+#define LETIMER_IF_REP1_DEFAULT                 (_LETIMER_IF_REP1_DEFAULT << 4)  /**< Shifted mode DEFAULT for LETIMER_IF */
+
+/* Bit fields for LETIMER IFS */
+#define _LETIMER_IFS_RESETVALUE                 0x00000000UL                      /**< Default value for LETIMER_IFS */
+#define _LETIMER_IFS_MASK                       0x0000001FUL                      /**< Mask for LETIMER_IFS */
+#define LETIMER_IFS_COMP0                       (0x1UL << 0)                      /**< Set COMP0 Interrupt Flag */
+#define _LETIMER_IFS_COMP0_SHIFT                0                                 /**< Shift value for LETIMER_COMP0 */
+#define _LETIMER_IFS_COMP0_MASK                 0x1UL                             /**< Bit mask for LETIMER_COMP0 */
+#define _LETIMER_IFS_COMP0_DEFAULT              0x00000000UL                      /**< Mode DEFAULT for LETIMER_IFS */
+#define LETIMER_IFS_COMP0_DEFAULT               (_LETIMER_IFS_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IFS */
+#define LETIMER_IFS_COMP1                       (0x1UL << 1)                      /**< Set COMP1 Interrupt Flag */
+#define _LETIMER_IFS_COMP1_SHIFT                1                                 /**< Shift value for LETIMER_COMP1 */
+#define _LETIMER_IFS_COMP1_MASK                 0x2UL                             /**< Bit mask for LETIMER_COMP1 */
+#define _LETIMER_IFS_COMP1_DEFAULT              0x00000000UL                      /**< Mode DEFAULT for LETIMER_IFS */
+#define LETIMER_IFS_COMP1_DEFAULT               (_LETIMER_IFS_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IFS */
+#define LETIMER_IFS_UF                          (0x1UL << 2)                      /**< Set UF Interrupt Flag */
+#define _LETIMER_IFS_UF_SHIFT                   2                                 /**< Shift value for LETIMER_UF */
+#define _LETIMER_IFS_UF_MASK                    0x4UL                             /**< Bit mask for LETIMER_UF */
+#define _LETIMER_IFS_UF_DEFAULT                 0x00000000UL                      /**< Mode DEFAULT for LETIMER_IFS */
+#define LETIMER_IFS_UF_DEFAULT                  (_LETIMER_IFS_UF_DEFAULT << 2)    /**< Shifted mode DEFAULT for LETIMER_IFS */
+#define LETIMER_IFS_REP0                        (0x1UL << 3)                      /**< Set REP0 Interrupt Flag */
+#define _LETIMER_IFS_REP0_SHIFT                 3                                 /**< Shift value for LETIMER_REP0 */
+#define _LETIMER_IFS_REP0_MASK                  0x8UL                             /**< Bit mask for LETIMER_REP0 */
+#define _LETIMER_IFS_REP0_DEFAULT               0x00000000UL                      /**< Mode DEFAULT for LETIMER_IFS */
+#define LETIMER_IFS_REP0_DEFAULT                (_LETIMER_IFS_REP0_DEFAULT << 3)  /**< Shifted mode DEFAULT for LETIMER_IFS */
+#define LETIMER_IFS_REP1                        (0x1UL << 4)                      /**< Set REP1 Interrupt Flag */
+#define _LETIMER_IFS_REP1_SHIFT                 4                                 /**< Shift value for LETIMER_REP1 */
+#define _LETIMER_IFS_REP1_MASK                  0x10UL                            /**< Bit mask for LETIMER_REP1 */
+#define _LETIMER_IFS_REP1_DEFAULT               0x00000000UL                      /**< Mode DEFAULT for LETIMER_IFS */
+#define LETIMER_IFS_REP1_DEFAULT                (_LETIMER_IFS_REP1_DEFAULT << 4)  /**< Shifted mode DEFAULT for LETIMER_IFS */
+
+/* Bit fields for LETIMER IFC */
+#define _LETIMER_IFC_RESETVALUE                 0x00000000UL                      /**< Default value for LETIMER_IFC */
+#define _LETIMER_IFC_MASK                       0x0000001FUL                      /**< Mask for LETIMER_IFC */
+#define LETIMER_IFC_COMP0                       (0x1UL << 0)                      /**< Clear COMP0 Interrupt Flag */
+#define _LETIMER_IFC_COMP0_SHIFT                0                                 /**< Shift value for LETIMER_COMP0 */
+#define _LETIMER_IFC_COMP0_MASK                 0x1UL                             /**< Bit mask for LETIMER_COMP0 */
+#define _LETIMER_IFC_COMP0_DEFAULT              0x00000000UL                      /**< Mode DEFAULT for LETIMER_IFC */
+#define LETIMER_IFC_COMP0_DEFAULT               (_LETIMER_IFC_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IFC */
+#define LETIMER_IFC_COMP1                       (0x1UL << 1)                      /**< Clear COMP1 Interrupt Flag */
+#define _LETIMER_IFC_COMP1_SHIFT                1                                 /**< Shift value for LETIMER_COMP1 */
+#define _LETIMER_IFC_COMP1_MASK                 0x2UL                             /**< Bit mask for LETIMER_COMP1 */
+#define _LETIMER_IFC_COMP1_DEFAULT              0x00000000UL                      /**< Mode DEFAULT for LETIMER_IFC */
+#define LETIMER_IFC_COMP1_DEFAULT               (_LETIMER_IFC_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IFC */
+#define LETIMER_IFC_UF                          (0x1UL << 2)                      /**< Clear UF Interrupt Flag */
+#define _LETIMER_IFC_UF_SHIFT                   2                                 /**< Shift value for LETIMER_UF */
+#define _LETIMER_IFC_UF_MASK                    0x4UL                             /**< Bit mask for LETIMER_UF */
+#define _LETIMER_IFC_UF_DEFAULT                 0x00000000UL                      /**< Mode DEFAULT for LETIMER_IFC */
+#define LETIMER_IFC_UF_DEFAULT                  (_LETIMER_IFC_UF_DEFAULT << 2)    /**< Shifted mode DEFAULT for LETIMER_IFC */
+#define LETIMER_IFC_REP0                        (0x1UL << 3)                      /**< Clear REP0 Interrupt Flag */
+#define _LETIMER_IFC_REP0_SHIFT                 3                                 /**< Shift value for LETIMER_REP0 */
+#define _LETIMER_IFC_REP0_MASK                  0x8UL                             /**< Bit mask for LETIMER_REP0 */
+#define _LETIMER_IFC_REP0_DEFAULT               0x00000000UL                      /**< Mode DEFAULT for LETIMER_IFC */
+#define LETIMER_IFC_REP0_DEFAULT                (_LETIMER_IFC_REP0_DEFAULT << 3)  /**< Shifted mode DEFAULT for LETIMER_IFC */
+#define LETIMER_IFC_REP1                        (0x1UL << 4)                      /**< Clear REP1 Interrupt Flag */
+#define _LETIMER_IFC_REP1_SHIFT                 4                                 /**< Shift value for LETIMER_REP1 */
+#define _LETIMER_IFC_REP1_MASK                  0x10UL                            /**< Bit mask for LETIMER_REP1 */
+#define _LETIMER_IFC_REP1_DEFAULT               0x00000000UL                      /**< Mode DEFAULT for LETIMER_IFC */
+#define LETIMER_IFC_REP1_DEFAULT                (_LETIMER_IFC_REP1_DEFAULT << 4)  /**< Shifted mode DEFAULT for LETIMER_IFC */
+
+/* Bit fields for LETIMER IEN */
+#define _LETIMER_IEN_RESETVALUE                 0x00000000UL                      /**< Default value for LETIMER_IEN */
+#define _LETIMER_IEN_MASK                       0x0000001FUL                      /**< Mask for LETIMER_IEN */
+#define LETIMER_IEN_COMP0                       (0x1UL << 0)                      /**< COMP0 Interrupt Enable */
+#define _LETIMER_IEN_COMP0_SHIFT                0                                 /**< Shift value for LETIMER_COMP0 */
+#define _LETIMER_IEN_COMP0_MASK                 0x1UL                             /**< Bit mask for LETIMER_COMP0 */
+#define _LETIMER_IEN_COMP0_DEFAULT              0x00000000UL                      /**< Mode DEFAULT for LETIMER_IEN */
+#define LETIMER_IEN_COMP0_DEFAULT               (_LETIMER_IEN_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IEN */
+#define LETIMER_IEN_COMP1                       (0x1UL << 1)                      /**< COMP1 Interrupt Enable */
+#define _LETIMER_IEN_COMP1_SHIFT                1                                 /**< Shift value for LETIMER_COMP1 */
+#define _LETIMER_IEN_COMP1_MASK                 0x2UL                             /**< Bit mask for LETIMER_COMP1 */
+#define _LETIMER_IEN_COMP1_DEFAULT              0x00000000UL                      /**< Mode DEFAULT for LETIMER_IEN */
+#define LETIMER_IEN_COMP1_DEFAULT               (_LETIMER_IEN_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IEN */
+#define LETIMER_IEN_UF                          (0x1UL << 2)                      /**< UF Interrupt Enable */
+#define _LETIMER_IEN_UF_SHIFT                   2                                 /**< Shift value for LETIMER_UF */
+#define _LETIMER_IEN_UF_MASK                    0x4UL                             /**< Bit mask for LETIMER_UF */
+#define _LETIMER_IEN_UF_DEFAULT                 0x00000000UL                      /**< Mode DEFAULT for LETIMER_IEN */
+#define LETIMER_IEN_UF_DEFAULT                  (_LETIMER_IEN_UF_DEFAULT << 2)    /**< Shifted mode DEFAULT for LETIMER_IEN */
+#define LETIMER_IEN_REP0                        (0x1UL << 3)                      /**< REP0 Interrupt Enable */
+#define _LETIMER_IEN_REP0_SHIFT                 3                                 /**< Shift value for LETIMER_REP0 */
+#define _LETIMER_IEN_REP0_MASK                  0x8UL                             /**< Bit mask for LETIMER_REP0 */
+#define _LETIMER_IEN_REP0_DEFAULT               0x00000000UL                      /**< Mode DEFAULT for LETIMER_IEN */
+#define LETIMER_IEN_REP0_DEFAULT                (_LETIMER_IEN_REP0_DEFAULT << 3)  /**< Shifted mode DEFAULT for LETIMER_IEN */
+#define LETIMER_IEN_REP1                        (0x1UL << 4)                      /**< REP1 Interrupt Enable */
+#define _LETIMER_IEN_REP1_SHIFT                 4                                 /**< Shift value for LETIMER_REP1 */
+#define _LETIMER_IEN_REP1_MASK                  0x10UL                            /**< Bit mask for LETIMER_REP1 */
+#define _LETIMER_IEN_REP1_DEFAULT               0x00000000UL                      /**< Mode DEFAULT for LETIMER_IEN */
+#define LETIMER_IEN_REP1_DEFAULT                (_LETIMER_IEN_REP1_DEFAULT << 4)  /**< Shifted mode DEFAULT for LETIMER_IEN */
+
+/* Bit fields for LETIMER SYNCBUSY */
+#define _LETIMER_SYNCBUSY_RESETVALUE            0x00000000UL                         /**< Default value for LETIMER_SYNCBUSY */
+#define _LETIMER_SYNCBUSY_MASK                  0x00000002UL                         /**< Mask for LETIMER_SYNCBUSY */
+#define LETIMER_SYNCBUSY_CMD                    (0x1UL << 1)                         /**< CMD Register Busy */
+#define _LETIMER_SYNCBUSY_CMD_SHIFT             1                                    /**< Shift value for LETIMER_CMD */
+#define _LETIMER_SYNCBUSY_CMD_MASK              0x2UL                                /**< Bit mask for LETIMER_CMD */
+#define _LETIMER_SYNCBUSY_CMD_DEFAULT           0x00000000UL                         /**< Mode DEFAULT for LETIMER_SYNCBUSY */
+#define LETIMER_SYNCBUSY_CMD_DEFAULT            (_LETIMER_SYNCBUSY_CMD_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */
+
+/* Bit fields for LETIMER ROUTEPEN */
+#define _LETIMER_ROUTEPEN_RESETVALUE            0x00000000UL                             /**< Default value for LETIMER_ROUTEPEN */
+#define _LETIMER_ROUTEPEN_MASK                  0x00000003UL                             /**< Mask for LETIMER_ROUTEPEN */
+#define LETIMER_ROUTEPEN_OUT0PEN                (0x1UL << 0)                             /**< Output 0 Pin Enable */
+#define _LETIMER_ROUTEPEN_OUT0PEN_SHIFT         0                                        /**< Shift value for LETIMER_OUT0PEN */
+#define _LETIMER_ROUTEPEN_OUT0PEN_MASK          0x1UL                                    /**< Bit mask for LETIMER_OUT0PEN */
+#define _LETIMER_ROUTEPEN_OUT0PEN_DEFAULT       0x00000000UL                             /**< Mode DEFAULT for LETIMER_ROUTEPEN */
+#define LETIMER_ROUTEPEN_OUT0PEN_DEFAULT        (_LETIMER_ROUTEPEN_OUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_ROUTEPEN */
+#define LETIMER_ROUTEPEN_OUT1PEN                (0x1UL << 1)                             /**< Output 1 Pin Enable */
+#define _LETIMER_ROUTEPEN_OUT1PEN_SHIFT         1                                        /**< Shift value for LETIMER_OUT1PEN */
+#define _LETIMER_ROUTEPEN_OUT1PEN_MASK          0x2UL                                    /**< Bit mask for LETIMER_OUT1PEN */
+#define _LETIMER_ROUTEPEN_OUT1PEN_DEFAULT       0x00000000UL                             /**< Mode DEFAULT for LETIMER_ROUTEPEN */
+#define LETIMER_ROUTEPEN_OUT1PEN_DEFAULT        (_LETIMER_ROUTEPEN_OUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_ROUTEPEN */
+
+/* Bit fields for LETIMER ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_RESETVALUE           0x00000000UL                              /**< Default value for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_MASK                 0x00001F1FUL                              /**< Mask for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT0LOC_SHIFT        0                                         /**< Shift value for LETIMER_OUT0LOC */
+#define _LETIMER_ROUTELOC0_OUT0LOC_MASK         0x1FUL                                    /**< Bit mask for LETIMER_OUT0LOC */
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC0         0x00000000UL                              /**< Mode LOC0 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT0LOC_DEFAULT      0x00000000UL                              /**< Mode DEFAULT for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC1         0x00000001UL                              /**< Mode LOC1 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC2         0x00000002UL                              /**< Mode LOC2 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC3         0x00000003UL                              /**< Mode LOC3 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC4         0x00000004UL                              /**< Mode LOC4 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC5         0x00000005UL                              /**< Mode LOC5 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC6         0x00000006UL                              /**< Mode LOC6 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC7         0x00000007UL                              /**< Mode LOC7 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC8         0x00000008UL                              /**< Mode LOC8 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC9         0x00000009UL                              /**< Mode LOC9 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC10        0x0000000AUL                              /**< Mode LOC10 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC11        0x0000000BUL                              /**< Mode LOC11 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC12        0x0000000CUL                              /**< Mode LOC12 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC13        0x0000000DUL                              /**< Mode LOC13 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC14        0x0000000EUL                              /**< Mode LOC14 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC15        0x0000000FUL                              /**< Mode LOC15 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC16        0x00000010UL                              /**< Mode LOC16 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC17        0x00000011UL                              /**< Mode LOC17 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC18        0x00000012UL                              /**< Mode LOC18 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC19        0x00000013UL                              /**< Mode LOC19 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC20        0x00000014UL                              /**< Mode LOC20 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC21        0x00000015UL                              /**< Mode LOC21 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC22        0x00000016UL                              /**< Mode LOC22 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC23        0x00000017UL                              /**< Mode LOC23 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC24        0x00000018UL                              /**< Mode LOC24 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC25        0x00000019UL                              /**< Mode LOC25 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC26        0x0000001AUL                              /**< Mode LOC26 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC27        0x0000001BUL                              /**< Mode LOC27 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC28        0x0000001CUL                              /**< Mode LOC28 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC29        0x0000001DUL                              /**< Mode LOC29 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC30        0x0000001EUL                              /**< Mode LOC30 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC31        0x0000001FUL                              /**< Mode LOC31 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC0          (_LETIMER_ROUTELOC0_OUT0LOC_LOC0 << 0)    /**< Shifted mode LOC0 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT0LOC_DEFAULT       (_LETIMER_ROUTELOC0_OUT0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC1          (_LETIMER_ROUTELOC0_OUT0LOC_LOC1 << 0)    /**< Shifted mode LOC1 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC2          (_LETIMER_ROUTELOC0_OUT0LOC_LOC2 << 0)    /**< Shifted mode LOC2 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC3          (_LETIMER_ROUTELOC0_OUT0LOC_LOC3 << 0)    /**< Shifted mode LOC3 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC4          (_LETIMER_ROUTELOC0_OUT0LOC_LOC4 << 0)    /**< Shifted mode LOC4 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC5          (_LETIMER_ROUTELOC0_OUT0LOC_LOC5 << 0)    /**< Shifted mode LOC5 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC6          (_LETIMER_ROUTELOC0_OUT0LOC_LOC6 << 0)    /**< Shifted mode LOC6 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC7          (_LETIMER_ROUTELOC0_OUT0LOC_LOC7 << 0)    /**< Shifted mode LOC7 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC8          (_LETIMER_ROUTELOC0_OUT0LOC_LOC8 << 0)    /**< Shifted mode LOC8 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC9          (_LETIMER_ROUTELOC0_OUT0LOC_LOC9 << 0)    /**< Shifted mode LOC9 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC10         (_LETIMER_ROUTELOC0_OUT0LOC_LOC10 << 0)   /**< Shifted mode LOC10 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC11         (_LETIMER_ROUTELOC0_OUT0LOC_LOC11 << 0)   /**< Shifted mode LOC11 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC12         (_LETIMER_ROUTELOC0_OUT0LOC_LOC12 << 0)   /**< Shifted mode LOC12 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC13         (_LETIMER_ROUTELOC0_OUT0LOC_LOC13 << 0)   /**< Shifted mode LOC13 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC14         (_LETIMER_ROUTELOC0_OUT0LOC_LOC14 << 0)   /**< Shifted mode LOC14 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC15         (_LETIMER_ROUTELOC0_OUT0LOC_LOC15 << 0)   /**< Shifted mode LOC15 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC16         (_LETIMER_ROUTELOC0_OUT0LOC_LOC16 << 0)   /**< Shifted mode LOC16 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC17         (_LETIMER_ROUTELOC0_OUT0LOC_LOC17 << 0)   /**< Shifted mode LOC17 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC18         (_LETIMER_ROUTELOC0_OUT0LOC_LOC18 << 0)   /**< Shifted mode LOC18 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC19         (_LETIMER_ROUTELOC0_OUT0LOC_LOC19 << 0)   /**< Shifted mode LOC19 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC20         (_LETIMER_ROUTELOC0_OUT0LOC_LOC20 << 0)   /**< Shifted mode LOC20 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC21         (_LETIMER_ROUTELOC0_OUT0LOC_LOC21 << 0)   /**< Shifted mode LOC21 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC22         (_LETIMER_ROUTELOC0_OUT0LOC_LOC22 << 0)   /**< Shifted mode LOC22 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC23         (_LETIMER_ROUTELOC0_OUT0LOC_LOC23 << 0)   /**< Shifted mode LOC23 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC24         (_LETIMER_ROUTELOC0_OUT0LOC_LOC24 << 0)   /**< Shifted mode LOC24 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC25         (_LETIMER_ROUTELOC0_OUT0LOC_LOC25 << 0)   /**< Shifted mode LOC25 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC26         (_LETIMER_ROUTELOC0_OUT0LOC_LOC26 << 0)   /**< Shifted mode LOC26 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC27         (_LETIMER_ROUTELOC0_OUT0LOC_LOC27 << 0)   /**< Shifted mode LOC27 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC28         (_LETIMER_ROUTELOC0_OUT0LOC_LOC28 << 0)   /**< Shifted mode LOC28 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC29         (_LETIMER_ROUTELOC0_OUT0LOC_LOC29 << 0)   /**< Shifted mode LOC29 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC30         (_LETIMER_ROUTELOC0_OUT0LOC_LOC30 << 0)   /**< Shifted mode LOC30 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC31         (_LETIMER_ROUTELOC0_OUT0LOC_LOC31 << 0)   /**< Shifted mode LOC31 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT1LOC_SHIFT        8                                         /**< Shift value for LETIMER_OUT1LOC */
+#define _LETIMER_ROUTELOC0_OUT1LOC_MASK         0x1F00UL                                  /**< Bit mask for LETIMER_OUT1LOC */
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC0         0x00000000UL                              /**< Mode LOC0 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT1LOC_DEFAULT      0x00000000UL                              /**< Mode DEFAULT for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC1         0x00000001UL                              /**< Mode LOC1 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC2         0x00000002UL                              /**< Mode LOC2 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC3         0x00000003UL                              /**< Mode LOC3 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC4         0x00000004UL                              /**< Mode LOC4 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC5         0x00000005UL                              /**< Mode LOC5 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC6         0x00000006UL                              /**< Mode LOC6 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC7         0x00000007UL                              /**< Mode LOC7 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC8         0x00000008UL                              /**< Mode LOC8 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC9         0x00000009UL                              /**< Mode LOC9 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC10        0x0000000AUL                              /**< Mode LOC10 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC11        0x0000000BUL                              /**< Mode LOC11 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC12        0x0000000CUL                              /**< Mode LOC12 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC13        0x0000000DUL                              /**< Mode LOC13 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC14        0x0000000EUL                              /**< Mode LOC14 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC15        0x0000000FUL                              /**< Mode LOC15 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC16        0x00000010UL                              /**< Mode LOC16 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC17        0x00000011UL                              /**< Mode LOC17 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC18        0x00000012UL                              /**< Mode LOC18 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC19        0x00000013UL                              /**< Mode LOC19 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC20        0x00000014UL                              /**< Mode LOC20 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC21        0x00000015UL                              /**< Mode LOC21 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC22        0x00000016UL                              /**< Mode LOC22 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC23        0x00000017UL                              /**< Mode LOC23 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC24        0x00000018UL                              /**< Mode LOC24 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC25        0x00000019UL                              /**< Mode LOC25 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC26        0x0000001AUL                              /**< Mode LOC26 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC27        0x0000001BUL                              /**< Mode LOC27 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC28        0x0000001CUL                              /**< Mode LOC28 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC29        0x0000001DUL                              /**< Mode LOC29 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC30        0x0000001EUL                              /**< Mode LOC30 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC31        0x0000001FUL                              /**< Mode LOC31 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC0          (_LETIMER_ROUTELOC0_OUT1LOC_LOC0 << 8)    /**< Shifted mode LOC0 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT1LOC_DEFAULT       (_LETIMER_ROUTELOC0_OUT1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC1          (_LETIMER_ROUTELOC0_OUT1LOC_LOC1 << 8)    /**< Shifted mode LOC1 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC2          (_LETIMER_ROUTELOC0_OUT1LOC_LOC2 << 8)    /**< Shifted mode LOC2 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC3          (_LETIMER_ROUTELOC0_OUT1LOC_LOC3 << 8)    /**< Shifted mode LOC3 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC4          (_LETIMER_ROUTELOC0_OUT1LOC_LOC4 << 8)    /**< Shifted mode LOC4 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC5          (_LETIMER_ROUTELOC0_OUT1LOC_LOC5 << 8)    /**< Shifted mode LOC5 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC6          (_LETIMER_ROUTELOC0_OUT1LOC_LOC6 << 8)    /**< Shifted mode LOC6 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC7          (_LETIMER_ROUTELOC0_OUT1LOC_LOC7 << 8)    /**< Shifted mode LOC7 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC8          (_LETIMER_ROUTELOC0_OUT1LOC_LOC8 << 8)    /**< Shifted mode LOC8 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC9          (_LETIMER_ROUTELOC0_OUT1LOC_LOC9 << 8)    /**< Shifted mode LOC9 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC10         (_LETIMER_ROUTELOC0_OUT1LOC_LOC10 << 8)   /**< Shifted mode LOC10 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC11         (_LETIMER_ROUTELOC0_OUT1LOC_LOC11 << 8)   /**< Shifted mode LOC11 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC12         (_LETIMER_ROUTELOC0_OUT1LOC_LOC12 << 8)   /**< Shifted mode LOC12 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC13         (_LETIMER_ROUTELOC0_OUT1LOC_LOC13 << 8)   /**< Shifted mode LOC13 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC14         (_LETIMER_ROUTELOC0_OUT1LOC_LOC14 << 8)   /**< Shifted mode LOC14 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC15         (_LETIMER_ROUTELOC0_OUT1LOC_LOC15 << 8)   /**< Shifted mode LOC15 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC16         (_LETIMER_ROUTELOC0_OUT1LOC_LOC16 << 8)   /**< Shifted mode LOC16 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC17         (_LETIMER_ROUTELOC0_OUT1LOC_LOC17 << 8)   /**< Shifted mode LOC17 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC18         (_LETIMER_ROUTELOC0_OUT1LOC_LOC18 << 8)   /**< Shifted mode LOC18 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC19         (_LETIMER_ROUTELOC0_OUT1LOC_LOC19 << 8)   /**< Shifted mode LOC19 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC20         (_LETIMER_ROUTELOC0_OUT1LOC_LOC20 << 8)   /**< Shifted mode LOC20 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC21         (_LETIMER_ROUTELOC0_OUT1LOC_LOC21 << 8)   /**< Shifted mode LOC21 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC22         (_LETIMER_ROUTELOC0_OUT1LOC_LOC22 << 8)   /**< Shifted mode LOC22 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC23         (_LETIMER_ROUTELOC0_OUT1LOC_LOC23 << 8)   /**< Shifted mode LOC23 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC24         (_LETIMER_ROUTELOC0_OUT1LOC_LOC24 << 8)   /**< Shifted mode LOC24 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC25         (_LETIMER_ROUTELOC0_OUT1LOC_LOC25 << 8)   /**< Shifted mode LOC25 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC26         (_LETIMER_ROUTELOC0_OUT1LOC_LOC26 << 8)   /**< Shifted mode LOC26 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC27         (_LETIMER_ROUTELOC0_OUT1LOC_LOC27 << 8)   /**< Shifted mode LOC27 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC28         (_LETIMER_ROUTELOC0_OUT1LOC_LOC28 << 8)   /**< Shifted mode LOC28 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC29         (_LETIMER_ROUTELOC0_OUT1LOC_LOC29 << 8)   /**< Shifted mode LOC29 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC30         (_LETIMER_ROUTELOC0_OUT1LOC_LOC30 << 8)   /**< Shifted mode LOC30 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC31         (_LETIMER_ROUTELOC0_OUT1LOC_LOC31 << 8)   /**< Shifted mode LOC31 for LETIMER_ROUTELOC0 */
+
+/* Bit fields for LETIMER PRSSEL */
+#define _LETIMER_PRSSEL_RESETVALUE              0x00000000UL                                 /**< Default value for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_MASK                    0x0CCCF3CFUL                                 /**< Mask for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSSTARTSEL_SHIFT       0                                            /**< Shift value for LETIMER_PRSSTARTSEL */
+#define _LETIMER_PRSSEL_PRSSTARTSEL_MASK        0xFUL                                        /**< Bit mask for LETIMER_PRSSTARTSEL */
+#define _LETIMER_PRSSEL_PRSSTARTSEL_DEFAULT     0x00000000UL                                 /**< Mode DEFAULT for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH0      0x00000000UL                                 /**< Mode PRSCH0 for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH1      0x00000001UL                                 /**< Mode PRSCH1 for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH2      0x00000002UL                                 /**< Mode PRSCH2 for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH3      0x00000003UL                                 /**< Mode PRSCH3 for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH4      0x00000004UL                                 /**< Mode PRSCH4 for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH5      0x00000005UL                                 /**< Mode PRSCH5 for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH6      0x00000006UL                                 /**< Mode PRSCH6 for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH7      0x00000007UL                                 /**< Mode PRSCH7 for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH8      0x00000008UL                                 /**< Mode PRSCH8 for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH9      0x00000009UL                                 /**< Mode PRSCH9 for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH10     0x0000000AUL                                 /**< Mode PRSCH10 for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH11     0x0000000BUL                                 /**< Mode PRSCH11 for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSSTARTSEL_DEFAULT      (_LETIMER_PRSSEL_PRSSTARTSEL_DEFAULT << 0)   /**< Shifted mode DEFAULT for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH0       (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH0 << 0)    /**< Shifted mode PRSCH0 for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH1       (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH1 << 0)    /**< Shifted mode PRSCH1 for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH2       (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH2 << 0)    /**< Shifted mode PRSCH2 for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH3       (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH3 << 0)    /**< Shifted mode PRSCH3 for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH4       (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH4 << 0)    /**< Shifted mode PRSCH4 for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH5       (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH5 << 0)    /**< Shifted mode PRSCH5 for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH6       (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH6 << 0)    /**< Shifted mode PRSCH6 for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH7       (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH7 << 0)    /**< Shifted mode PRSCH7 for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH8       (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH8 << 0)    /**< Shifted mode PRSCH8 for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH9       (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH9 << 0)    /**< Shifted mode PRSCH9 for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH10      (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH10 << 0)   /**< Shifted mode PRSCH10 for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH11      (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH11 << 0)   /**< Shifted mode PRSCH11 for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSSTOPSEL_SHIFT        6                                            /**< Shift value for LETIMER_PRSSTOPSEL */
+#define _LETIMER_PRSSEL_PRSSTOPSEL_MASK         0x3C0UL                                      /**< Bit mask for LETIMER_PRSSTOPSEL */
+#define _LETIMER_PRSSEL_PRSSTOPSEL_DEFAULT      0x00000000UL                                 /**< Mode DEFAULT for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH0       0x00000000UL                                 /**< Mode PRSCH0 for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH1       0x00000001UL                                 /**< Mode PRSCH1 for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH2       0x00000002UL                                 /**< Mode PRSCH2 for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH3       0x00000003UL                                 /**< Mode PRSCH3 for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH4       0x00000004UL                                 /**< Mode PRSCH4 for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH5       0x00000005UL                                 /**< Mode PRSCH5 for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH6       0x00000006UL                                 /**< Mode PRSCH6 for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH7       0x00000007UL                                 /**< Mode PRSCH7 for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH8       0x00000008UL                                 /**< Mode PRSCH8 for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH9       0x00000009UL                                 /**< Mode PRSCH9 for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH10      0x0000000AUL                                 /**< Mode PRSCH10 for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH11      0x0000000BUL                                 /**< Mode PRSCH11 for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSSTOPSEL_DEFAULT       (_LETIMER_PRSSEL_PRSSTOPSEL_DEFAULT << 6)    /**< Shifted mode DEFAULT for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH0        (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH0 << 6)     /**< Shifted mode PRSCH0 for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH1        (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH1 << 6)     /**< Shifted mode PRSCH1 for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH2        (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH2 << 6)     /**< Shifted mode PRSCH2 for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH3        (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH3 << 6)     /**< Shifted mode PRSCH3 for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH4        (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH4 << 6)     /**< Shifted mode PRSCH4 for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH5        (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH5 << 6)     /**< Shifted mode PRSCH5 for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH6        (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH6 << 6)     /**< Shifted mode PRSCH6 for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH7        (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH7 << 6)     /**< Shifted mode PRSCH7 for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH8        (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH8 << 6)     /**< Shifted mode PRSCH8 for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH9        (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH9 << 6)     /**< Shifted mode PRSCH9 for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH10       (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH10 << 6)    /**< Shifted mode PRSCH10 for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH11       (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH11 << 6)    /**< Shifted mode PRSCH11 for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSCLEARSEL_SHIFT       12                                           /**< Shift value for LETIMER_PRSCLEARSEL */
+#define _LETIMER_PRSSEL_PRSCLEARSEL_MASK        0xF000UL                                     /**< Bit mask for LETIMER_PRSCLEARSEL */
+#define _LETIMER_PRSSEL_PRSCLEARSEL_DEFAULT     0x00000000UL                                 /**< Mode DEFAULT for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH0      0x00000000UL                                 /**< Mode PRSCH0 for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH1      0x00000001UL                                 /**< Mode PRSCH1 for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH2      0x00000002UL                                 /**< Mode PRSCH2 for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH3      0x00000003UL                                 /**< Mode PRSCH3 for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH4      0x00000004UL                                 /**< Mode PRSCH4 for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH5      0x00000005UL                                 /**< Mode PRSCH5 for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH6      0x00000006UL                                 /**< Mode PRSCH6 for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH7      0x00000007UL                                 /**< Mode PRSCH7 for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH8      0x00000008UL                                 /**< Mode PRSCH8 for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH9      0x00000009UL                                 /**< Mode PRSCH9 for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH10     0x0000000AUL                                 /**< Mode PRSCH10 for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH11     0x0000000BUL                                 /**< Mode PRSCH11 for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSCLEARSEL_DEFAULT      (_LETIMER_PRSSEL_PRSCLEARSEL_DEFAULT << 12)  /**< Shifted mode DEFAULT for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH0       (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH0 << 12)   /**< Shifted mode PRSCH0 for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH1       (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH1 << 12)   /**< Shifted mode PRSCH1 for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH2       (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH2 << 12)   /**< Shifted mode PRSCH2 for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH3       (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH3 << 12)   /**< Shifted mode PRSCH3 for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH4       (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH4 << 12)   /**< Shifted mode PRSCH4 for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH5       (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH5 << 12)   /**< Shifted mode PRSCH5 for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH6       (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH6 << 12)   /**< Shifted mode PRSCH6 for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH7       (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH7 << 12)   /**< Shifted mode PRSCH7 for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH8       (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH8 << 12)   /**< Shifted mode PRSCH8 for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH9       (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH9 << 12)   /**< Shifted mode PRSCH9 for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH10      (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH10 << 12)  /**< Shifted mode PRSCH10 for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH11      (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH11 << 12)  /**< Shifted mode PRSCH11 for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSSTARTMODE_SHIFT      18                                           /**< Shift value for LETIMER_PRSSTARTMODE */
+#define _LETIMER_PRSSEL_PRSSTARTMODE_MASK       0xC0000UL                                    /**< Bit mask for LETIMER_PRSSTARTMODE */
+#define _LETIMER_PRSSEL_PRSSTARTMODE_DEFAULT    0x00000000UL                                 /**< Mode DEFAULT for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSSTARTMODE_NONE       0x00000000UL                                 /**< Mode NONE for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSSTARTMODE_RISING     0x00000001UL                                 /**< Mode RISING for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSSTARTMODE_FALLING    0x00000002UL                                 /**< Mode FALLING for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSSTARTMODE_BOTH       0x00000003UL                                 /**< Mode BOTH for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSSTARTMODE_DEFAULT     (_LETIMER_PRSSEL_PRSSTARTMODE_DEFAULT << 18) /**< Shifted mode DEFAULT for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSSTARTMODE_NONE        (_LETIMER_PRSSEL_PRSSTARTMODE_NONE << 18)    /**< Shifted mode NONE for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSSTARTMODE_RISING      (_LETIMER_PRSSEL_PRSSTARTMODE_RISING << 18)  /**< Shifted mode RISING for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSSTARTMODE_FALLING     (_LETIMER_PRSSEL_PRSSTARTMODE_FALLING << 18) /**< Shifted mode FALLING for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSSTARTMODE_BOTH        (_LETIMER_PRSSEL_PRSSTARTMODE_BOTH << 18)    /**< Shifted mode BOTH for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSSTOPMODE_SHIFT       22                                           /**< Shift value for LETIMER_PRSSTOPMODE */
+#define _LETIMER_PRSSEL_PRSSTOPMODE_MASK        0xC00000UL                                   /**< Bit mask for LETIMER_PRSSTOPMODE */
+#define _LETIMER_PRSSEL_PRSSTOPMODE_DEFAULT     0x00000000UL                                 /**< Mode DEFAULT for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSSTOPMODE_NONE        0x00000000UL                                 /**< Mode NONE for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSSTOPMODE_RISING      0x00000001UL                                 /**< Mode RISING for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSSTOPMODE_FALLING     0x00000002UL                                 /**< Mode FALLING for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSSTOPMODE_BOTH        0x00000003UL                                 /**< Mode BOTH for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSSTOPMODE_DEFAULT      (_LETIMER_PRSSEL_PRSSTOPMODE_DEFAULT << 22)  /**< Shifted mode DEFAULT for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSSTOPMODE_NONE         (_LETIMER_PRSSEL_PRSSTOPMODE_NONE << 22)     /**< Shifted mode NONE for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSSTOPMODE_RISING       (_LETIMER_PRSSEL_PRSSTOPMODE_RISING << 22)   /**< Shifted mode RISING for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSSTOPMODE_FALLING      (_LETIMER_PRSSEL_PRSSTOPMODE_FALLING << 22)  /**< Shifted mode FALLING for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSSTOPMODE_BOTH         (_LETIMER_PRSSEL_PRSSTOPMODE_BOTH << 22)     /**< Shifted mode BOTH for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSCLEARMODE_SHIFT      26                                           /**< Shift value for LETIMER_PRSCLEARMODE */
+#define _LETIMER_PRSSEL_PRSCLEARMODE_MASK       0xC000000UL                                  /**< Bit mask for LETIMER_PRSCLEARMODE */
+#define _LETIMER_PRSSEL_PRSCLEARMODE_DEFAULT    0x00000000UL                                 /**< Mode DEFAULT for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSCLEARMODE_NONE       0x00000000UL                                 /**< Mode NONE for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSCLEARMODE_RISING     0x00000001UL                                 /**< Mode RISING for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSCLEARMODE_FALLING    0x00000002UL                                 /**< Mode FALLING for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSCLEARMODE_BOTH       0x00000003UL                                 /**< Mode BOTH for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSCLEARMODE_DEFAULT     (_LETIMER_PRSSEL_PRSCLEARMODE_DEFAULT << 26) /**< Shifted mode DEFAULT for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSCLEARMODE_NONE        (_LETIMER_PRSSEL_PRSCLEARMODE_NONE << 26)    /**< Shifted mode NONE for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSCLEARMODE_RISING      (_LETIMER_PRSSEL_PRSCLEARMODE_RISING << 26)  /**< Shifted mode RISING for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSCLEARMODE_FALLING     (_LETIMER_PRSSEL_PRSCLEARMODE_FALLING << 26) /**< Shifted mode FALLING for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSCLEARMODE_BOTH        (_LETIMER_PRSSEL_PRSCLEARMODE_BOTH << 26)    /**< Shifted mode BOTH for LETIMER_PRSSEL */
+
+/** @} End of group EFM32PG1B_LETIMER */
+/** @} End of group Parts */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG_STK3401/efm32pg1b_leuart.h	Fri Jan 15 07:45:16 2016 +0000
@@ -0,0 +1,835 @@
+/**************************************************************************//**
+ * @file efm32pg1b_leuart.h
+ * @brief EFM32PG1B_LEUART register and bit field definitions
+ * @version 4.2.0
+ ******************************************************************************
+ * @section License
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ ******************************************************************************
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software.@n
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.@n
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is
+ * providing the Software "AS IS", with no express or implied warranties of any
+ * kind, including, but not limited to, any implied warranties of
+ * merchantability or fitness for any particular purpose or warranties against
+ * infringement of any proprietary rights of a third party.
+ *
+ * Silicon Laboratories, Inc. will not be liable for any consequential,
+ * incidental, or special damages, or any other relief, or for any claim by
+ * any third party, arising from your use of this Software.
+ *
+ *****************************************************************************/
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFM32PG1B_LEUART
+ * @{
+ * @brief EFM32PG1B_LEUART Register Declaration
+ *****************************************************************************/
+typedef struct
+{
+  __IO uint32_t CTRL;         /**< Control Register  */
+  __IO uint32_t CMD;          /**< Command Register  */
+  __I uint32_t  STATUS;       /**< Status Register  */
+  __IO uint32_t CLKDIV;       /**< Clock Control Register  */
+  __IO uint32_t STARTFRAME;   /**< Start Frame Register  */
+  __IO uint32_t SIGFRAME;     /**< Signal Frame Register  */
+  __I uint32_t  RXDATAX;      /**< Receive Buffer Data Extended Register  */
+  __I uint32_t  RXDATA;       /**< Receive Buffer Data Register  */
+  __I uint32_t  RXDATAXP;     /**< Receive Buffer Data Extended Peek Register  */
+  __IO uint32_t TXDATAX;      /**< Transmit Buffer Data Extended Register  */
+  __IO uint32_t TXDATA;       /**< Transmit Buffer Data Register  */
+  __I uint32_t  IF;           /**< Interrupt Flag Register  */
+  __IO uint32_t IFS;          /**< Interrupt Flag Set Register  */
+  __IO uint32_t IFC;          /**< Interrupt Flag Clear Register  */
+  __IO uint32_t IEN;          /**< Interrupt Enable Register  */
+  __IO uint32_t PULSECTRL;    /**< Pulse Control Register  */
+
+  __IO uint32_t FREEZE;       /**< Freeze Register  */
+  __I uint32_t  SYNCBUSY;     /**< Synchronization Busy Register  */
+
+  uint32_t      RESERVED0[3]; /**< Reserved for future use **/
+  __IO uint32_t ROUTEPEN;     /**< I/O Routing Pin Enable Register  */
+  __IO uint32_t ROUTELOC0;    /**< I/O Routing Location Register  */
+  uint32_t      RESERVED1[2]; /**< Reserved for future use **/
+  __IO uint32_t INPUT;        /**< LEUART Input Register  */
+} LEUART_TypeDef;             /** @} */
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B_LEUART_BitFields
+ * @{
+ *****************************************************************************/
+
+/* Bit fields for LEUART CTRL */
+#define _LEUART_CTRL_RESETVALUE                  0x00000000UL                         /**< Default value for LEUART_CTRL */
+#define _LEUART_CTRL_MASK                        0x0000FFFFUL                         /**< Mask for LEUART_CTRL */
+#define LEUART_CTRL_AUTOTRI                      (0x1UL << 0)                         /**< Automatic Transmitter Tristate */
+#define _LEUART_CTRL_AUTOTRI_SHIFT               0                                    /**< Shift value for LEUART_AUTOTRI */
+#define _LEUART_CTRL_AUTOTRI_MASK                0x1UL                                /**< Bit mask for LEUART_AUTOTRI */
+#define _LEUART_CTRL_AUTOTRI_DEFAULT             0x00000000UL                         /**< Mode DEFAULT for LEUART_CTRL */
+#define LEUART_CTRL_AUTOTRI_DEFAULT              (_LEUART_CTRL_AUTOTRI_DEFAULT << 0)  /**< Shifted mode DEFAULT for LEUART_CTRL */
+#define LEUART_CTRL_DATABITS                     (0x1UL << 1)                         /**< Data-Bit Mode */
+#define _LEUART_CTRL_DATABITS_SHIFT              1                                    /**< Shift value for LEUART_DATABITS */
+#define _LEUART_CTRL_DATABITS_MASK               0x2UL                                /**< Bit mask for LEUART_DATABITS */
+#define _LEUART_CTRL_DATABITS_DEFAULT            0x00000000UL                         /**< Mode DEFAULT for LEUART_CTRL */
+#define _LEUART_CTRL_DATABITS_EIGHT              0x00000000UL                         /**< Mode EIGHT for LEUART_CTRL */
+#define _LEUART_CTRL_DATABITS_NINE               0x00000001UL                         /**< Mode NINE for LEUART_CTRL */
+#define LEUART_CTRL_DATABITS_DEFAULT             (_LEUART_CTRL_DATABITS_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_CTRL */
+#define LEUART_CTRL_DATABITS_EIGHT               (_LEUART_CTRL_DATABITS_EIGHT << 1)   /**< Shifted mode EIGHT for LEUART_CTRL */
+#define LEUART_CTRL_DATABITS_NINE                (_LEUART_CTRL_DATABITS_NINE << 1)    /**< Shifted mode NINE for LEUART_CTRL */
+#define _LEUART_CTRL_PARITY_SHIFT                2                                    /**< Shift value for LEUART_PARITY */
+#define _LEUART_CTRL_PARITY_MASK                 0xCUL                                /**< Bit mask for LEUART_PARITY */
+#define _LEUART_CTRL_PARITY_DEFAULT              0x00000000UL                         /**< Mode DEFAULT for LEUART_CTRL */
+#define _LEUART_CTRL_PARITY_NONE                 0x00000000UL                         /**< Mode NONE for LEUART_CTRL */
+#define _LEUART_CTRL_PARITY_EVEN                 0x00000002UL                         /**< Mode EVEN for LEUART_CTRL */
+#define _LEUART_CTRL_PARITY_ODD                  0x00000003UL                         /**< Mode ODD for LEUART_CTRL */
+#define LEUART_CTRL_PARITY_DEFAULT               (_LEUART_CTRL_PARITY_DEFAULT << 2)   /**< Shifted mode DEFAULT for LEUART_CTRL */
+#define LEUART_CTRL_PARITY_NONE                  (_LEUART_CTRL_PARITY_NONE << 2)      /**< Shifted mode NONE for LEUART_CTRL */
+#define LEUART_CTRL_PARITY_EVEN                  (_LEUART_CTRL_PARITY_EVEN << 2)      /**< Shifted mode EVEN for LEUART_CTRL */
+#define LEUART_CTRL_PARITY_ODD                   (_LEUART_CTRL_PARITY_ODD << 2)       /**< Shifted mode ODD for LEUART_CTRL */
+#define LEUART_CTRL_STOPBITS                     (0x1UL << 4)                         /**< Stop-Bit Mode */
+#define _LEUART_CTRL_STOPBITS_SHIFT              4                                    /**< Shift value for LEUART_STOPBITS */
+#define _LEUART_CTRL_STOPBITS_MASK               0x10UL                               /**< Bit mask for LEUART_STOPBITS */
+#define _LEUART_CTRL_STOPBITS_DEFAULT            0x00000000UL                         /**< Mode DEFAULT for LEUART_CTRL */
+#define _LEUART_CTRL_STOPBITS_ONE                0x00000000UL                         /**< Mode ONE for LEUART_CTRL */
+#define _LEUART_CTRL_STOPBITS_TWO                0x00000001UL                         /**< Mode TWO for LEUART_CTRL */
+#define LEUART_CTRL_STOPBITS_DEFAULT             (_LEUART_CTRL_STOPBITS_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_CTRL */
+#define LEUART_CTRL_STOPBITS_ONE                 (_LEUART_CTRL_STOPBITS_ONE << 4)     /**< Shifted mode ONE for LEUART_CTRL */
+#define LEUART_CTRL_STOPBITS_TWO                 (_LEUART_CTRL_STOPBITS_TWO << 4)     /**< Shifted mode TWO for LEUART_CTRL */
+#define LEUART_CTRL_INV                          (0x1UL << 5)                         /**< Invert Input And Output */
+#define _LEUART_CTRL_INV_SHIFT                   5                                    /**< Shift value for LEUART_INV */
+#define _LEUART_CTRL_INV_MASK                    0x20UL                               /**< Bit mask for LEUART_INV */
+#define _LEUART_CTRL_INV_DEFAULT                 0x00000000UL                         /**< Mode DEFAULT for LEUART_CTRL */
+#define LEUART_CTRL_INV_DEFAULT                  (_LEUART_CTRL_INV_DEFAULT << 5)      /**< Shifted mode DEFAULT for LEUART_CTRL */
+#define LEUART_CTRL_ERRSDMA                      (0x1UL << 6)                         /**< Clear RX DMA On Error */
+#define _LEUART_CTRL_ERRSDMA_SHIFT               6                                    /**< Shift value for LEUART_ERRSDMA */
+#define _LEUART_CTRL_ERRSDMA_MASK                0x40UL                               /**< Bit mask for LEUART_ERRSDMA */
+#define _LEUART_CTRL_ERRSDMA_DEFAULT             0x00000000UL                         /**< Mode DEFAULT for LEUART_CTRL */
+#define LEUART_CTRL_ERRSDMA_DEFAULT              (_LEUART_CTRL_ERRSDMA_DEFAULT << 6)  /**< Shifted mode DEFAULT for LEUART_CTRL */
+#define LEUART_CTRL_LOOPBK                       (0x1UL << 7)                         /**< Loopback Enable */
+#define _LEUART_CTRL_LOOPBK_SHIFT                7                                    /**< Shift value for LEUART_LOOPBK */
+#define _LEUART_CTRL_LOOPBK_MASK                 0x80UL                               /**< Bit mask for LEUART_LOOPBK */
+#define _LEUART_CTRL_LOOPBK_DEFAULT              0x00000000UL                         /**< Mode DEFAULT for LEUART_CTRL */
+#define LEUART_CTRL_LOOPBK_DEFAULT               (_LEUART_CTRL_LOOPBK_DEFAULT << 7)   /**< Shifted mode DEFAULT for LEUART_CTRL */
+#define LEUART_CTRL_SFUBRX                       (0x1UL << 8)                         /**< Start-Frame UnBlock RX */
+#define _LEUART_CTRL_SFUBRX_SHIFT                8                                    /**< Shift value for LEUART_SFUBRX */
+#define _LEUART_CTRL_SFUBRX_MASK                 0x100UL                              /**< Bit mask for LEUART_SFUBRX */
+#define _LEUART_CTRL_SFUBRX_DEFAULT              0x00000000UL                         /**< Mode DEFAULT for LEUART_CTRL */
+#define LEUART_CTRL_SFUBRX_DEFAULT               (_LEUART_CTRL_SFUBRX_DEFAULT << 8)   /**< Shifted mode DEFAULT for LEUART_CTRL */
+#define LEUART_CTRL_MPM                          (0x1UL << 9)                         /**< Multi-Processor Mode */
+#define _LEUART_CTRL_MPM_SHIFT                   9                                    /**< Shift value for LEUART_MPM */
+#define _LEUART_CTRL_MPM_MASK                    0x200UL                              /**< Bit mask for LEUART_MPM */
+#define _LEUART_CTRL_MPM_DEFAULT                 0x00000000UL                         /**< Mode DEFAULT for LEUART_CTRL */
+#define LEUART_CTRL_MPM_DEFAULT                  (_LEUART_CTRL_MPM_DEFAULT << 9)      /**< Shifted mode DEFAULT for LEUART_CTRL */
+#define LEUART_CTRL_MPAB                         (0x1UL << 10)                        /**< Multi-Processor Address-Bit */
+#define _LEUART_CTRL_MPAB_SHIFT                  10                                   /**< Shift value for LEUART_MPAB */
+#define _LEUART_CTRL_MPAB_MASK                   0x400UL                              /**< Bit mask for LEUART_MPAB */
+#define _LEUART_CTRL_MPAB_DEFAULT                0x00000000UL                         /**< Mode DEFAULT for LEUART_CTRL */
+#define LEUART_CTRL_MPAB_DEFAULT                 (_LEUART_CTRL_MPAB_DEFAULT << 10)    /**< Shifted mode DEFAULT for LEUART_CTRL */
+#define LEUART_CTRL_BIT8DV                       (0x1UL << 11)                        /**< Bit 8 Default Value */
+#define _LEUART_CTRL_BIT8DV_SHIFT                11                                   /**< Shift value for LEUART_BIT8DV */
+#define _LEUART_CTRL_BIT8DV_MASK                 0x800UL                              /**< Bit mask for LEUART_BIT8DV */
+#define _LEUART_CTRL_BIT8DV_DEFAULT              0x00000000UL                         /**< Mode DEFAULT for LEUART_CTRL */
+#define LEUART_CTRL_BIT8DV_DEFAULT               (_LEUART_CTRL_BIT8DV_DEFAULT << 11)  /**< Shifted mode DEFAULT for LEUART_CTRL */
+#define LEUART_CTRL_RXDMAWU                      (0x1UL << 12)                        /**< RX DMA Wakeup */
+#define _LEUART_CTRL_RXDMAWU_SHIFT               12                                   /**< Shift value for LEUART_RXDMAWU */
+#define _LEUART_CTRL_RXDMAWU_MASK                0x1000UL                             /**< Bit mask for LEUART_RXDMAWU */
+#define _LEUART_CTRL_RXDMAWU_DEFAULT             0x00000000UL                         /**< Mode DEFAULT for LEUART_CTRL */
+#define LEUART_CTRL_RXDMAWU_DEFAULT              (_LEUART_CTRL_RXDMAWU_DEFAULT << 12) /**< Shifted mode DEFAULT for LEUART_CTRL */
+#define LEUART_CTRL_TXDMAWU                      (0x1UL << 13)                        /**< TX DMA Wakeup */
+#define _LEUART_CTRL_TXDMAWU_SHIFT               13                                   /**< Shift value for LEUART_TXDMAWU */
+#define _LEUART_CTRL_TXDMAWU_MASK                0x2000UL                             /**< Bit mask for LEUART_TXDMAWU */
+#define _LEUART_CTRL_TXDMAWU_DEFAULT             0x00000000UL                         /**< Mode DEFAULT for LEUART_CTRL */
+#define LEUART_CTRL_TXDMAWU_DEFAULT              (_LEUART_CTRL_TXDMAWU_DEFAULT << 13) /**< Shifted mode DEFAULT for LEUART_CTRL */
+#define _LEUART_CTRL_TXDELAY_SHIFT               14                                   /**< Shift value for LEUART_TXDELAY */
+#define _LEUART_CTRL_TXDELAY_MASK                0xC000UL                             /**< Bit mask for LEUART_TXDELAY */
+#define _LEUART_CTRL_TXDELAY_DEFAULT             0x00000000UL                         /**< Mode DEFAULT for LEUART_CTRL */
+#define _LEUART_CTRL_TXDELAY_NONE                0x00000000UL                         /**< Mode NONE for LEUART_CTRL */
+#define _LEUART_CTRL_TXDELAY_SINGLE              0x00000001UL                         /**< Mode SINGLE for LEUART_CTRL */
+#define _LEUART_CTRL_TXDELAY_DOUBLE              0x00000002UL                         /**< Mode DOUBLE for LEUART_CTRL */
+#define _LEUART_CTRL_TXDELAY_TRIPLE              0x00000003UL                         /**< Mode TRIPLE for LEUART_CTRL */
+#define LEUART_CTRL_TXDELAY_DEFAULT              (_LEUART_CTRL_TXDELAY_DEFAULT << 14) /**< Shifted mode DEFAULT for LEUART_CTRL */
+#define LEUART_CTRL_TXDELAY_NONE                 (_LEUART_CTRL_TXDELAY_NONE << 14)    /**< Shifted mode NONE for LEUART_CTRL */
+#define LEUART_CTRL_TXDELAY_SINGLE               (_LEUART_CTRL_TXDELAY_SINGLE << 14)  /**< Shifted mode SINGLE for LEUART_CTRL */
+#define LEUART_CTRL_TXDELAY_DOUBLE               (_LEUART_CTRL_TXDELAY_DOUBLE << 14)  /**< Shifted mode DOUBLE for LEUART_CTRL */
+#define LEUART_CTRL_TXDELAY_TRIPLE               (_LEUART_CTRL_TXDELAY_TRIPLE << 14)  /**< Shifted mode TRIPLE for LEUART_CTRL */
+
+/* Bit fields for LEUART CMD */
+#define _LEUART_CMD_RESETVALUE                   0x00000000UL                          /**< Default value for LEUART_CMD */
+#define _LEUART_CMD_MASK                         0x000000FFUL                          /**< Mask for LEUART_CMD */
+#define LEUART_CMD_RXEN                          (0x1UL << 0)                          /**< Receiver Enable */
+#define _LEUART_CMD_RXEN_SHIFT                   0                                     /**< Shift value for LEUART_RXEN */
+#define _LEUART_CMD_RXEN_MASK                    0x1UL                                 /**< Bit mask for LEUART_RXEN */
+#define _LEUART_CMD_RXEN_DEFAULT                 0x00000000UL                          /**< Mode DEFAULT for LEUART_CMD */
+#define LEUART_CMD_RXEN_DEFAULT                  (_LEUART_CMD_RXEN_DEFAULT << 0)       /**< Shifted mode DEFAULT for LEUART_CMD */
+#define LEUART_CMD_RXDIS                         (0x1UL << 1)                          /**< Receiver Disable */
+#define _LEUART_CMD_RXDIS_SHIFT                  1                                     /**< Shift value for LEUART_RXDIS */
+#define _LEUART_CMD_RXDIS_MASK                   0x2UL                                 /**< Bit mask for LEUART_RXDIS */
+#define _LEUART_CMD_RXDIS_DEFAULT                0x00000000UL                          /**< Mode DEFAULT for LEUART_CMD */
+#define LEUART_CMD_RXDIS_DEFAULT                 (_LEUART_CMD_RXDIS_DEFAULT << 1)      /**< Shifted mode DEFAULT for LEUART_CMD */
+#define LEUART_CMD_TXEN                          (0x1UL << 2)                          /**< Transmitter Enable */
+#define _LEUART_CMD_TXEN_SHIFT                   2                                     /**< Shift value for LEUART_TXEN */
+#define _LEUART_CMD_TXEN_MASK                    0x4UL                                 /**< Bit mask for LEUART_TXEN */
+#define _LEUART_CMD_TXEN_DEFAULT                 0x00000000UL                          /**< Mode DEFAULT for LEUART_CMD */
+#define LEUART_CMD_TXEN_DEFAULT                  (_LEUART_CMD_TXEN_DEFAULT << 2)       /**< Shifted mode DEFAULT for LEUART_CMD */
+#define LEUART_CMD_TXDIS                         (0x1UL << 3)                          /**< Transmitter Disable */
+#define _LEUART_CMD_TXDIS_SHIFT                  3                                     /**< Shift value for LEUART_TXDIS */
+#define _LEUART_CMD_TXDIS_MASK                   0x8UL                                 /**< Bit mask for LEUART_TXDIS */
+#define _LEUART_CMD_TXDIS_DEFAULT                0x00000000UL                          /**< Mode DEFAULT for LEUART_CMD */
+#define LEUART_CMD_TXDIS_DEFAULT                 (_LEUART_CMD_TXDIS_DEFAULT << 3)      /**< Shifted mode DEFAULT for LEUART_CMD */
+#define LEUART_CMD_RXBLOCKEN                     (0x1UL << 4)                          /**< Receiver Block Enable */
+#define _LEUART_CMD_RXBLOCKEN_SHIFT              4                                     /**< Shift value for LEUART_RXBLOCKEN */
+#define _LEUART_CMD_RXBLOCKEN_MASK               0x10UL                                /**< Bit mask for LEUART_RXBLOCKEN */
+#define _LEUART_CMD_RXBLOCKEN_DEFAULT            0x00000000UL                          /**< Mode DEFAULT for LEUART_CMD */
+#define LEUART_CMD_RXBLOCKEN_DEFAULT             (_LEUART_CMD_RXBLOCKEN_DEFAULT << 4)  /**< Shifted mode DEFAULT for LEUART_CMD */
+#define LEUART_CMD_RXBLOCKDIS                    (0x1UL << 5)                          /**< Receiver Block Disable */
+#define _LEUART_CMD_RXBLOCKDIS_SHIFT             5                                     /**< Shift value for LEUART_RXBLOCKDIS */
+#define _LEUART_CMD_RXBLOCKDIS_MASK              0x20UL                                /**< Bit mask for LEUART_RXBLOCKDIS */
+#define _LEUART_CMD_RXBLOCKDIS_DEFAULT           0x00000000UL                          /**< Mode DEFAULT for LEUART_CMD */
+#define LEUART_CMD_RXBLOCKDIS_DEFAULT            (_LEUART_CMD_RXBLOCKDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_CMD */
+#define LEUART_CMD_CLEARTX                       (0x1UL << 6)                          /**< Clear TX */
+#define _LEUART_CMD_CLEARTX_SHIFT                6                                     /**< Shift value for LEUART_CLEARTX */
+#define _LEUART_CMD_CLEARTX_MASK                 0x40UL                                /**< Bit mask for LEUART_CLEARTX */
+#define _LEUART_CMD_CLEARTX_DEFAULT              0x00000000UL                          /**< Mode DEFAULT for LEUART_CMD */
+#define LEUART_CMD_CLEARTX_DEFAULT               (_LEUART_CMD_CLEARTX_DEFAULT << 6)    /**< Shifted mode DEFAULT for LEUART_CMD */
+#define LEUART_CMD_CLEARRX                       (0x1UL << 7)                          /**< Clear RX */
+#define _LEUART_CMD_CLEARRX_SHIFT                7                                     /**< Shift value for LEUART_CLEARRX */
+#define _LEUART_CMD_CLEARRX_MASK                 0x80UL                                /**< Bit mask for LEUART_CLEARRX */
+#define _LEUART_CMD_CLEARRX_DEFAULT              0x00000000UL                          /**< Mode DEFAULT for LEUART_CMD */
+#define LEUART_CMD_CLEARRX_DEFAULT               (_LEUART_CMD_CLEARRX_DEFAULT << 7)    /**< Shifted mode DEFAULT for LEUART_CMD */
+
+/* Bit fields for LEUART STATUS */
+#define _LEUART_STATUS_RESETVALUE                0x00000050UL                          /**< Default value for LEUART_STATUS */
+#define _LEUART_STATUS_MASK                      0x0000007FUL                          /**< Mask for LEUART_STATUS */
+#define LEUART_STATUS_RXENS                      (0x1UL << 0)                          /**< Receiver Enable Status */
+#define _LEUART_STATUS_RXENS_SHIFT               0                                     /**< Shift value for LEUART_RXENS */
+#define _LEUART_STATUS_RXENS_MASK                0x1UL                                 /**< Bit mask for LEUART_RXENS */
+#define _LEUART_STATUS_RXENS_DEFAULT             0x00000000UL                          /**< Mode DEFAULT for LEUART_STATUS */
+#define LEUART_STATUS_RXENS_DEFAULT              (_LEUART_STATUS_RXENS_DEFAULT << 0)   /**< Shifted mode DEFAULT for LEUART_STATUS */
+#define LEUART_STATUS_TXENS                      (0x1UL << 1)                          /**< Transmitter Enable Status */
+#define _LEUART_STATUS_TXENS_SHIFT               1                                     /**< Shift value for LEUART_TXENS */
+#define _LEUART_STATUS_TXENS_MASK                0x2UL                                 /**< Bit mask for LEUART_TXENS */
+#define _LEUART_STATUS_TXENS_DEFAULT             0x00000000UL                          /**< Mode DEFAULT for LEUART_STATUS */
+#define LEUART_STATUS_TXENS_DEFAULT              (_LEUART_STATUS_TXENS_DEFAULT << 1)   /**< Shifted mode DEFAULT for LEUART_STATUS */
+#define LEUART_STATUS_RXBLOCK                    (0x1UL << 2)                          /**< Block Incoming Data */
+#define _LEUART_STATUS_RXBLOCK_SHIFT             2                                     /**< Shift value for LEUART_RXBLOCK */
+#define _LEUART_STATUS_RXBLOCK_MASK              0x4UL                                 /**< Bit mask for LEUART_RXBLOCK */
+#define _LEUART_STATUS_RXBLOCK_DEFAULT           0x00000000UL                          /**< Mode DEFAULT for LEUART_STATUS */
+#define LEUART_STATUS_RXBLOCK_DEFAULT            (_LEUART_STATUS_RXBLOCK_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_STATUS */
+#define LEUART_STATUS_TXC                        (0x1UL << 3)                          /**< TX Complete */
+#define _LEUART_STATUS_TXC_SHIFT                 3                                     /**< Shift value for LEUART_TXC */
+#define _LEUART_STATUS_TXC_MASK                  0x8UL                                 /**< Bit mask for LEUART_TXC */
+#define _LEUART_STATUS_TXC_DEFAULT               0x00000000UL                          /**< Mode DEFAULT for LEUART_STATUS */
+#define LEUART_STATUS_TXC_DEFAULT                (_LEUART_STATUS_TXC_DEFAULT << 3)     /**< Shifted mode DEFAULT for LEUART_STATUS */
+#define LEUART_STATUS_TXBL                       (0x1UL << 4)                          /**< TX Buffer Level */
+#define _LEUART_STATUS_TXBL_SHIFT                4                                     /**< Shift value for LEUART_TXBL */
+#define _LEUART_STATUS_TXBL_MASK                 0x10UL                                /**< Bit mask for LEUART_TXBL */
+#define _LEUART_STATUS_TXBL_DEFAULT              0x00000001UL                          /**< Mode DEFAULT for LEUART_STATUS */
+#define LEUART_STATUS_TXBL_DEFAULT               (_LEUART_STATUS_TXBL_DEFAULT << 4)    /**< Shifted mode DEFAULT for LEUART_STATUS */
+#define LEUART_STATUS_RXDATAV                    (0x1UL << 5)                          /**< RX Data Valid */
+#define _LEUART_STATUS_RXDATAV_SHIFT             5                                     /**< Shift value for LEUART_RXDATAV */
+#define _LEUART_STATUS_RXDATAV_MASK              0x20UL                                /**< Bit mask for LEUART_RXDATAV */
+#define _LEUART_STATUS_RXDATAV_DEFAULT           0x00000000UL                          /**< Mode DEFAULT for LEUART_STATUS */
+#define LEUART_STATUS_RXDATAV_DEFAULT            (_LEUART_STATUS_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_STATUS */
+#define LEUART_STATUS_TXIDLE                     (0x1UL << 6)                          /**< TX Idle */
+#define _LEUART_STATUS_TXIDLE_SHIFT              6                                     /**< Shift value for LEUART_TXIDLE */
+#define _LEUART_STATUS_TXIDLE_MASK               0x40UL                                /**< Bit mask for LEUART_TXIDLE */
+#define _LEUART_STATUS_TXIDLE_DEFAULT            0x00000001UL                          /**< Mode DEFAULT for LEUART_STATUS */
+#define LEUART_STATUS_TXIDLE_DEFAULT             (_LEUART_STATUS_TXIDLE_DEFAULT << 6)  /**< Shifted mode DEFAULT for LEUART_STATUS */
+
+/* Bit fields for LEUART CLKDIV */
+#define _LEUART_CLKDIV_RESETVALUE                0x00000000UL                      /**< Default value for LEUART_CLKDIV */
+#define _LEUART_CLKDIV_MASK                      0x0001FFF8UL                      /**< Mask for LEUART_CLKDIV */
+#define _LEUART_CLKDIV_DIV_SHIFT                 3                                 /**< Shift value for LEUART_DIV */
+#define _LEUART_CLKDIV_DIV_MASK                  0x1FFF8UL                         /**< Bit mask for LEUART_DIV */
+#define _LEUART_CLKDIV_DIV_DEFAULT               0x00000000UL                      /**< Mode DEFAULT for LEUART_CLKDIV */
+#define LEUART_CLKDIV_DIV_DEFAULT                (_LEUART_CLKDIV_DIV_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_CLKDIV */
+
+/* Bit fields for LEUART STARTFRAME */
+#define _LEUART_STARTFRAME_RESETVALUE            0x00000000UL                                 /**< Default value for LEUART_STARTFRAME */
+#define _LEUART_STARTFRAME_MASK                  0x000001FFUL                                 /**< Mask for LEUART_STARTFRAME */
+#define _LEUART_STARTFRAME_STARTFRAME_SHIFT      0                                            /**< Shift value for LEUART_STARTFRAME */
+#define _LEUART_STARTFRAME_STARTFRAME_MASK       0x1FFUL                                      /**< Bit mask for LEUART_STARTFRAME */
+#define _LEUART_STARTFRAME_STARTFRAME_DEFAULT    0x00000000UL                                 /**< Mode DEFAULT for LEUART_STARTFRAME */
+#define LEUART_STARTFRAME_STARTFRAME_DEFAULT     (_LEUART_STARTFRAME_STARTFRAME_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_STARTFRAME */
+
+/* Bit fields for LEUART SIGFRAME */
+#define _LEUART_SIGFRAME_RESETVALUE              0x00000000UL                             /**< Default value for LEUART_SIGFRAME */
+#define _LEUART_SIGFRAME_MASK                    0x000001FFUL                             /**< Mask for LEUART_SIGFRAME */
+#define _LEUART_SIGFRAME_SIGFRAME_SHIFT          0                                        /**< Shift value for LEUART_SIGFRAME */
+#define _LEUART_SIGFRAME_SIGFRAME_MASK           0x1FFUL                                  /**< Bit mask for LEUART_SIGFRAME */
+#define _LEUART_SIGFRAME_SIGFRAME_DEFAULT        0x00000000UL                             /**< Mode DEFAULT for LEUART_SIGFRAME */
+#define LEUART_SIGFRAME_SIGFRAME_DEFAULT         (_LEUART_SIGFRAME_SIGFRAME_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_SIGFRAME */
+
+/* Bit fields for LEUART RXDATAX */
+#define _LEUART_RXDATAX_RESETVALUE               0x00000000UL                          /**< Default value for LEUART_RXDATAX */
+#define _LEUART_RXDATAX_MASK                     0x0000C1FFUL                          /**< Mask for LEUART_RXDATAX */
+#define _LEUART_RXDATAX_RXDATA_SHIFT             0                                     /**< Shift value for LEUART_RXDATA */
+#define _LEUART_RXDATAX_RXDATA_MASK              0x1FFUL                               /**< Bit mask for LEUART_RXDATA */
+#define _LEUART_RXDATAX_RXDATA_DEFAULT           0x00000000UL                          /**< Mode DEFAULT for LEUART_RXDATAX */
+#define LEUART_RXDATAX_RXDATA_DEFAULT            (_LEUART_RXDATAX_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_RXDATAX */
+#define LEUART_RXDATAX_PERR                      (0x1UL << 14)                         /**< Receive Data Parity Error */
+#define _LEUART_RXDATAX_PERR_SHIFT               14                                    /**< Shift value for LEUART_PERR */
+#define _LEUART_RXDATAX_PERR_MASK                0x4000UL                              /**< Bit mask for LEUART_PERR */
+#define _LEUART_RXDATAX_PERR_DEFAULT             0x00000000UL                          /**< Mode DEFAULT for LEUART_RXDATAX */
+#define LEUART_RXDATAX_PERR_DEFAULT              (_LEUART_RXDATAX_PERR_DEFAULT << 14)  /**< Shifted mode DEFAULT for LEUART_RXDATAX */
+#define LEUART_RXDATAX_FERR                      (0x1UL << 15)                         /**< Receive Data Framing Error */
+#define _LEUART_RXDATAX_FERR_SHIFT               15                                    /**< Shift value for LEUART_FERR */
+#define _LEUART_RXDATAX_FERR_MASK                0x8000UL                              /**< Bit mask for LEUART_FERR */
+#define _LEUART_RXDATAX_FERR_DEFAULT             0x00000000UL                          /**< Mode DEFAULT for LEUART_RXDATAX */
+#define LEUART_RXDATAX_FERR_DEFAULT              (_LEUART_RXDATAX_FERR_DEFAULT << 15)  /**< Shifted mode DEFAULT for LEUART_RXDATAX */
+
+/* Bit fields for LEUART RXDATA */
+#define _LEUART_RXDATA_RESETVALUE                0x00000000UL                         /**< Default value for LEUART_RXDATA */
+#define _LEUART_RXDATA_MASK                      0x000000FFUL                         /**< Mask for LEUART_RXDATA */
+#define _LEUART_RXDATA_RXDATA_SHIFT              0                                    /**< Shift value for LEUART_RXDATA */
+#define _LEUART_RXDATA_RXDATA_MASK               0xFFUL                               /**< Bit mask for LEUART_RXDATA */
+#define _LEUART_RXDATA_RXDATA_DEFAULT            0x00000000UL                         /**< Mode DEFAULT for LEUART_RXDATA */
+#define LEUART_RXDATA_RXDATA_DEFAULT             (_LEUART_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_RXDATA */
+
+/* Bit fields for LEUART RXDATAXP */
+#define _LEUART_RXDATAXP_RESETVALUE              0x00000000UL                            /**< Default value for LEUART_RXDATAXP */
+#define _LEUART_RXDATAXP_MASK                    0x0000C1FFUL                            /**< Mask for LEUART_RXDATAXP */
+#define _LEUART_RXDATAXP_RXDATAP_SHIFT           0                                       /**< Shift value for LEUART_RXDATAP */
+#define _LEUART_RXDATAXP_RXDATAP_MASK            0x1FFUL                                 /**< Bit mask for LEUART_RXDATAP */
+#define _LEUART_RXDATAXP_RXDATAP_DEFAULT         0x00000000UL                            /**< Mode DEFAULT for LEUART_RXDATAXP */
+#define LEUART_RXDATAXP_RXDATAP_DEFAULT          (_LEUART_RXDATAXP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_RXDATAXP */
+#define LEUART_RXDATAXP_PERRP                    (0x1UL << 14)                           /**< Receive Data Parity Error Peek */
+#define _LEUART_RXDATAXP_PERRP_SHIFT             14                                      /**< Shift value for LEUART_PERRP */
+#define _LEUART_RXDATAXP_PERRP_MASK              0x4000UL                                /**< Bit mask for LEUART_PERRP */
+#define _LEUART_RXDATAXP_PERRP_DEFAULT           0x00000000UL                            /**< Mode DEFAULT for LEUART_RXDATAXP */
+#define LEUART_RXDATAXP_PERRP_DEFAULT            (_LEUART_RXDATAXP_PERRP_DEFAULT << 14)  /**< Shifted mode DEFAULT for LEUART_RXDATAXP */
+#define LEUART_RXDATAXP_FERRP                    (0x1UL << 15)                           /**< Receive Data Framing Error Peek */
+#define _LEUART_RXDATAXP_FERRP_SHIFT             15                                      /**< Shift value for LEUART_FERRP */
+#define _LEUART_RXDATAXP_FERRP_MASK              0x8000UL                                /**< Bit mask for LEUART_FERRP */
+#define _LEUART_RXDATAXP_FERRP_DEFAULT           0x00000000UL                            /**< Mode DEFAULT for LEUART_RXDATAXP */
+#define LEUART_RXDATAXP_FERRP_DEFAULT            (_LEUART_RXDATAXP_FERRP_DEFAULT << 15)  /**< Shifted mode DEFAULT for LEUART_RXDATAXP */
+
+/* Bit fields for LEUART TXDATAX */
+#define _LEUART_TXDATAX_RESETVALUE               0x00000000UL                            /**< Default value for LEUART_TXDATAX */
+#define _LEUART_TXDATAX_MASK                     0x0000E1FFUL                            /**< Mask for LEUART_TXDATAX */
+#define _LEUART_TXDATAX_TXDATA_SHIFT             0                                       /**< Shift value for LEUART_TXDATA */
+#define _LEUART_TXDATAX_TXDATA_MASK              0x1FFUL                                 /**< Bit mask for LEUART_TXDATA */
+#define _LEUART_TXDATAX_TXDATA_DEFAULT           0x00000000UL                            /**< Mode DEFAULT for LEUART_TXDATAX */
+#define LEUART_TXDATAX_TXDATA_DEFAULT            (_LEUART_TXDATAX_TXDATA_DEFAULT << 0)   /**< Shifted mode DEFAULT for LEUART_TXDATAX */
+#define LEUART_TXDATAX_TXBREAK                   (0x1UL << 13)                           /**< Transmit Data As Break */
+#define _LEUART_TXDATAX_TXBREAK_SHIFT            13                                      /**< Shift value for LEUART_TXBREAK */
+#define _LEUART_TXDATAX_TXBREAK_MASK             0x2000UL                                /**< Bit mask for LEUART_TXBREAK */
+#define _LEUART_TXDATAX_TXBREAK_DEFAULT          0x00000000UL                            /**< Mode DEFAULT for LEUART_TXDATAX */
+#define LEUART_TXDATAX_TXBREAK_DEFAULT           (_LEUART_TXDATAX_TXBREAK_DEFAULT << 13) /**< Shifted mode DEFAULT for LEUART_TXDATAX */
+#define LEUART_TXDATAX_TXDISAT                   (0x1UL << 14)                           /**< Disable TX After Transmission */
+#define _LEUART_TXDATAX_TXDISAT_SHIFT            14                                      /**< Shift value for LEUART_TXDISAT */
+#define _LEUART_TXDATAX_TXDISAT_MASK             0x4000UL                                /**< Bit mask for LEUART_TXDISAT */
+#define _LEUART_TXDATAX_TXDISAT_DEFAULT          0x00000000UL                            /**< Mode DEFAULT for LEUART_TXDATAX */
+#define LEUART_TXDATAX_TXDISAT_DEFAULT           (_LEUART_TXDATAX_TXDISAT_DEFAULT << 14) /**< Shifted mode DEFAULT for LEUART_TXDATAX */
+#define LEUART_TXDATAX_RXENAT                    (0x1UL << 15)                           /**< Enable RX After Transmission */
+#define _LEUART_TXDATAX_RXENAT_SHIFT             15                                      /**< Shift value for LEUART_RXENAT */
+#define _LEUART_TXDATAX_RXENAT_MASK              0x8000UL                                /**< Bit mask for LEUART_RXENAT */
+#define _LEUART_TXDATAX_RXENAT_DEFAULT           0x00000000UL                            /**< Mode DEFAULT for LEUART_TXDATAX */
+#define LEUART_TXDATAX_RXENAT_DEFAULT            (_LEUART_TXDATAX_RXENAT_DEFAULT << 15)  /**< Shifted mode DEFAULT for LEUART_TXDATAX */
+
+/* Bit fields for LEUART TXDATA */
+#define _LEUART_TXDATA_RESETVALUE                0x00000000UL                         /**< Default value for LEUART_TXDATA */
+#define _LEUART_TXDATA_MASK                      0x000000FFUL                         /**< Mask for LEUART_TXDATA */
+#define _LEUART_TXDATA_TXDATA_SHIFT              0                                    /**< Shift value for LEUART_TXDATA */
+#define _LEUART_TXDATA_TXDATA_MASK               0xFFUL                               /**< Bit mask for LEUART_TXDATA */
+#define _LEUART_TXDATA_TXDATA_DEFAULT            0x00000000UL                         /**< Mode DEFAULT for LEUART_TXDATA */
+#define LEUART_TXDATA_TXDATA_DEFAULT             (_LEUART_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_TXDATA */
+
+/* Bit fields for LEUART IF */
+#define _LEUART_IF_RESETVALUE                    0x00000002UL                      /**< Default value for LEUART_IF */
+#define _LEUART_IF_MASK                          0x000007FFUL                      /**< Mask for LEUART_IF */
+#define LEUART_IF_TXC                            (0x1UL << 0)                      /**< TX Complete Interrupt Flag */
+#define _LEUART_IF_TXC_SHIFT                     0                                 /**< Shift value for LEUART_TXC */
+#define _LEUART_IF_TXC_MASK                      0x1UL                             /**< Bit mask for LEUART_TXC */
+#define _LEUART_IF_TXC_DEFAULT                   0x00000000UL                      /**< Mode DEFAULT for LEUART_IF */
+#define LEUART_IF_TXC_DEFAULT                    (_LEUART_IF_TXC_DEFAULT << 0)     /**< Shifted mode DEFAULT for LEUART_IF */
+#define LEUART_IF_TXBL                           (0x1UL << 1)                      /**< TX Buffer Level Interrupt Flag */
+#define _LEUART_IF_TXBL_SHIFT                    1                                 /**< Shift value for LEUART_TXBL */
+#define _LEUART_IF_TXBL_MASK                     0x2UL                             /**< Bit mask for LEUART_TXBL */
+#define _LEUART_IF_TXBL_DEFAULT                  0x00000001UL                      /**< Mode DEFAULT for LEUART_IF */
+#define LEUART_IF_TXBL_DEFAULT                   (_LEUART_IF_TXBL_DEFAULT << 1)    /**< Shifted mode DEFAULT for LEUART_IF */
+#define LEUART_IF_RXDATAV                        (0x1UL << 2)                      /**< RX Data Valid Interrupt Flag */
+#define _LEUART_IF_RXDATAV_SHIFT                 2                                 /**< Shift value for LEUART_RXDATAV */
+#define _LEUART_IF_RXDATAV_MASK                  0x4UL                             /**< Bit mask for LEUART_RXDATAV */
+#define _LEUART_IF_RXDATAV_DEFAULT               0x00000000UL                      /**< Mode DEFAULT for LEUART_IF */
+#define LEUART_IF_RXDATAV_DEFAULT                (_LEUART_IF_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_IF */
+#define LEUART_IF_RXOF                           (0x1UL << 3)                      /**< RX Overflow Interrupt Flag */
+#define _LEUART_IF_RXOF_SHIFT                    3                                 /**< Shift value for LEUART_RXOF */
+#define _LEUART_IF_RXOF_MASK                     0x8UL                             /**< Bit mask for LEUART_RXOF */
+#define _LEUART_IF_RXOF_DEFAULT                  0x00000000UL                      /**< Mode DEFAULT for LEUART_IF */
+#define LEUART_IF_RXOF_DEFAULT                   (_LEUART_IF_RXOF_DEFAULT << 3)    /**< Shifted mode DEFAULT for LEUART_IF */
+#define LEUART_IF_RXUF                           (0x1UL << 4)                      /**< RX Underflow Interrupt Flag */
+#define _LEUART_IF_RXUF_SHIFT                    4                                 /**< Shift value for LEUART_RXUF */
+#define _LEUART_IF_RXUF_MASK                     0x10UL                            /**< Bit mask for LEUART_RXUF */
+#define _LEUART_IF_RXUF_DEFAULT                  0x00000000UL                      /**< Mode DEFAULT for LEUART_IF */
+#define LEUART_IF_RXUF_DEFAULT                   (_LEUART_IF_RXUF_DEFAULT << 4)    /**< Shifted mode DEFAULT for LEUART_IF */
+#define LEUART_IF_TXOF                           (0x1UL << 5)                      /**< TX Overflow Interrupt Flag */
+#define _LEUART_IF_TXOF_SHIFT                    5                                 /**< Shift value for LEUART_TXOF */
+#define _LEUART_IF_TXOF_MASK                     0x20UL                            /**< Bit mask for LEUART_TXOF */
+#define _LEUART_IF_TXOF_DEFAULT                  0x00000000UL                      /**< Mode DEFAULT for LEUART_IF */
+#define LEUART_IF_TXOF_DEFAULT                   (_LEUART_IF_TXOF_DEFAULT << 5)    /**< Shifted mode DEFAULT for LEUART_IF */
+#define LEUART_IF_PERR                           (0x1UL << 6)                      /**< Parity Error Interrupt Flag */
+#define _LEUART_IF_PERR_SHIFT                    6                                 /**< Shift value for LEUART_PERR */
+#define _LEUART_IF_PERR_MASK                     0x40UL                            /**< Bit mask for LEUART_PERR */
+#define _LEUART_IF_PERR_DEFAULT                  0x00000000UL                      /**< Mode DEFAULT for LEUART_IF */
+#define LEUART_IF_PERR_DEFAULT                   (_LEUART_IF_PERR_DEFAULT << 6)    /**< Shifted mode DEFAULT for LEUART_IF */
+#define LEUART_IF_FERR                           (0x1UL << 7)                      /**< Framing Error Interrupt Flag */
+#define _LEUART_IF_FERR_SHIFT                    7                                 /**< Shift value for LEUART_FERR */
+#define _LEUART_IF_FERR_MASK                     0x80UL                            /**< Bit mask for LEUART_FERR */
+#define _LEUART_IF_FERR_DEFAULT                  0x00000000UL                      /**< Mode DEFAULT for LEUART_IF */
+#define LEUART_IF_FERR_DEFAULT                   (_LEUART_IF_FERR_DEFAULT << 7)    /**< Shifted mode DEFAULT for LEUART_IF */
+#define LEUART_IF_MPAF                           (0x1UL << 8)                      /**< Multi-Processor Address Frame Interrupt Flag */
+#define _LEUART_IF_MPAF_SHIFT                    8                                 /**< Shift value for LEUART_MPAF */
+#define _LEUART_IF_MPAF_MASK                     0x100UL                           /**< Bit mask for LEUART_MPAF */
+#define _LEUART_IF_MPAF_DEFAULT                  0x00000000UL                      /**< Mode DEFAULT for LEUART_IF */
+#define LEUART_IF_MPAF_DEFAULT                   (_LEUART_IF_MPAF_DEFAULT << 8)    /**< Shifted mode DEFAULT for LEUART_IF */
+#define LEUART_IF_STARTF                         (0x1UL << 9)                      /**< Start Frame Interrupt Flag */
+#define _LEUART_IF_STARTF_SHIFT                  9                                 /**< Shift value for LEUART_STARTF */
+#define _LEUART_IF_STARTF_MASK                   0x200UL                           /**< Bit mask for LEUART_STARTF */
+#define _LEUART_IF_STARTF_DEFAULT                0x00000000UL                      /**< Mode DEFAULT for LEUART_IF */
+#define LEUART_IF_STARTF_DEFAULT                 (_LEUART_IF_STARTF_DEFAULT << 9)  /**< Shifted mode DEFAULT for LEUART_IF */
+#define LEUART_IF_SIGF                           (0x1UL << 10)                     /**< Signal Frame Interrupt Flag */
+#define _LEUART_IF_SIGF_SHIFT                    10                                /**< Shift value for LEUART_SIGF */
+#define _LEUART_IF_SIGF_MASK                     0x400UL                           /**< Bit mask for LEUART_SIGF */
+#define _LEUART_IF_SIGF_DEFAULT                  0x00000000UL                      /**< Mode DEFAULT for LEUART_IF */
+#define LEUART_IF_SIGF_DEFAULT                   (_LEUART_IF_SIGF_DEFAULT << 10)   /**< Shifted mode DEFAULT for LEUART_IF */
+
+/* Bit fields for LEUART IFS */
+#define _LEUART_IFS_RESETVALUE                   0x00000000UL                      /**< Default value for LEUART_IFS */
+#define _LEUART_IFS_MASK                         0x000007F9UL                      /**< Mask for LEUART_IFS */
+#define LEUART_IFS_TXC                           (0x1UL << 0)                      /**< Set TXC Interrupt Flag */
+#define _LEUART_IFS_TXC_SHIFT                    0                                 /**< Shift value for LEUART_TXC */
+#define _LEUART_IFS_TXC_MASK                     0x1UL                             /**< Bit mask for LEUART_TXC */
+#define _LEUART_IFS_TXC_DEFAULT                  0x00000000UL                      /**< Mode DEFAULT for LEUART_IFS */
+#define LEUART_IFS_TXC_DEFAULT                   (_LEUART_IFS_TXC_DEFAULT << 0)    /**< Shifted mode DEFAULT for LEUART_IFS */
+#define LEUART_IFS_RXOF                          (0x1UL << 3)                      /**< Set RXOF Interrupt Flag */
+#define _LEUART_IFS_RXOF_SHIFT                   3                                 /**< Shift value for LEUART_RXOF */
+#define _LEUART_IFS_RXOF_MASK                    0x8UL                             /**< Bit mask for LEUART_RXOF */
+#define _LEUART_IFS_RXOF_DEFAULT                 0x00000000UL                      /**< Mode DEFAULT for LEUART_IFS */
+#define LEUART_IFS_RXOF_DEFAULT                  (_LEUART_IFS_RXOF_DEFAULT << 3)   /**< Shifted mode DEFAULT for LEUART_IFS */
+#define LEUART_IFS_RXUF                          (0x1UL << 4)                      /**< Set RXUF Interrupt Flag */
+#define _LEUART_IFS_RXUF_SHIFT                   4                                 /**< Shift value for LEUART_RXUF */
+#define _LEUART_IFS_RXUF_MASK                    0x10UL                            /**< Bit mask for LEUART_RXUF */
+#define _LEUART_IFS_RXUF_DEFAULT                 0x00000000UL                      /**< Mode DEFAULT for LEUART_IFS */
+#define LEUART_IFS_RXUF_DEFAULT                  (_LEUART_IFS_RXUF_DEFAULT << 4)   /**< Shifted mode DEFAULT for LEUART_IFS */
+#define LEUART_IFS_TXOF                          (0x1UL << 5)                      /**< Set TXOF Interrupt Flag */
+#define _LEUART_IFS_TXOF_SHIFT                   5                                 /**< Shift value for LEUART_TXOF */
+#define _LEUART_IFS_TXOF_MASK                    0x20UL                            /**< Bit mask for LEUART_TXOF */
+#define _LEUART_IFS_TXOF_DEFAULT                 0x00000000UL                      /**< Mode DEFAULT for LEUART_IFS */
+#define LEUART_IFS_TXOF_DEFAULT                  (_LEUART_IFS_TXOF_DEFAULT << 5)   /**< Shifted mode DEFAULT for LEUART_IFS */
+#define LEUART_IFS_PERR                          (0x1UL << 6)                      /**< Set PERR Interrupt Flag */
+#define _LEUART_IFS_PERR_SHIFT                   6                                 /**< Shift value for LEUART_PERR */
+#define _LEUART_IFS_PERR_MASK                    0x40UL                            /**< Bit mask for LEUART_PERR */
+#define _LEUART_IFS_PERR_DEFAULT                 0x00000000UL                      /**< Mode DEFAULT for LEUART_IFS */
+#define LEUART_IFS_PERR_DEFAULT                  (_LEUART_IFS_PERR_DEFAULT << 6)   /**< Shifted mode DEFAULT for LEUART_IFS */
+#define LEUART_IFS_FERR                          (0x1UL << 7)                      /**< Set FERR Interrupt Flag */
+#define _LEUART_IFS_FERR_SHIFT                   7                                 /**< Shift value for LEUART_FERR */
+#define _LEUART_IFS_FERR_MASK                    0x80UL                            /**< Bit mask for LEUART_FERR */
+#define _LEUART_IFS_FERR_DEFAULT                 0x00000000UL                      /**< Mode DEFAULT for LEUART_IFS */
+#define LEUART_IFS_FERR_DEFAULT                  (_LEUART_IFS_FERR_DEFAULT << 7)   /**< Shifted mode DEFAULT for LEUART_IFS */
+#define LEUART_IFS_MPAF                          (0x1UL << 8)                      /**< Set MPAF Interrupt Flag */
+#define _LEUART_IFS_MPAF_SHIFT                   8                                 /**< Shift value for LEUART_MPAF */
+#define _LEUART_IFS_MPAF_MASK                    0x100UL                           /**< Bit mask for LEUART_MPAF */
+#define _LEUART_IFS_MPAF_DEFAULT                 0x00000000UL                      /**< Mode DEFAULT for LEUART_IFS */
+#define LEUART_IFS_MPAF_DEFAULT                  (_LEUART_IFS_MPAF_DEFAULT << 8)   /**< Shifted mode DEFAULT for LEUART_IFS */
+#define LEUART_IFS_STARTF                        (0x1UL << 9)                      /**< Set STARTF Interrupt Flag */
+#define _LEUART_IFS_STARTF_SHIFT                 9                                 /**< Shift value for LEUART_STARTF */
+#define _LEUART_IFS_STARTF_MASK                  0x200UL                           /**< Bit mask for LEUART_STARTF */
+#define _LEUART_IFS_STARTF_DEFAULT               0x00000000UL                      /**< Mode DEFAULT for LEUART_IFS */
+#define LEUART_IFS_STARTF_DEFAULT                (_LEUART_IFS_STARTF_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_IFS */
+#define LEUART_IFS_SIGF                          (0x1UL << 10)                     /**< Set SIGF Interrupt Flag */
+#define _LEUART_IFS_SIGF_SHIFT                   10                                /**< Shift value for LEUART_SIGF */
+#define _LEUART_IFS_SIGF_MASK                    0x400UL                           /**< Bit mask for LEUART_SIGF */
+#define _LEUART_IFS_SIGF_DEFAULT                 0x00000000UL                      /**< Mode DEFAULT for LEUART_IFS */
+#define LEUART_IFS_SIGF_DEFAULT                  (_LEUART_IFS_SIGF_DEFAULT << 10)  /**< Shifted mode DEFAULT for LEUART_IFS */
+
+/* Bit fields for LEUART IFC */
+#define _LEUART_IFC_RESETVALUE                   0x00000000UL                      /**< Default value for LEUART_IFC */
+#define _LEUART_IFC_MASK                         0x000007F9UL                      /**< Mask for LEUART_IFC */
+#define LEUART_IFC_TXC                           (0x1UL << 0)                      /**< Clear TXC Interrupt Flag */
+#define _LEUART_IFC_TXC_SHIFT                    0                                 /**< Shift value for LEUART_TXC */
+#define _LEUART_IFC_TXC_MASK                     0x1UL                             /**< Bit mask for LEUART_TXC */
+#define _LEUART_IFC_TXC_DEFAULT                  0x00000000UL                      /**< Mode DEFAULT for LEUART_IFC */
+#define LEUART_IFC_TXC_DEFAULT                   (_LEUART_IFC_TXC_DEFAULT << 0)    /**< Shifted mode DEFAULT for LEUART_IFC */
+#define LEUART_IFC_RXOF                          (0x1UL << 3)                      /**< Clear RXOF Interrupt Flag */
+#define _LEUART_IFC_RXOF_SHIFT                   3                                 /**< Shift value for LEUART_RXOF */
+#define _LEUART_IFC_RXOF_MASK                    0x8UL                             /**< Bit mask for LEUART_RXOF */
+#define _LEUART_IFC_RXOF_DEFAULT                 0x00000000UL                      /**< Mode DEFAULT for LEUART_IFC */
+#define LEUART_IFC_RXOF_DEFAULT                  (_LEUART_IFC_RXOF_DEFAULT << 3)   /**< Shifted mode DEFAULT for LEUART_IFC */
+#define LEUART_IFC_RXUF                          (0x1UL << 4)                      /**< Clear RXUF Interrupt Flag */
+#define _LEUART_IFC_RXUF_SHIFT                   4                                 /**< Shift value for LEUART_RXUF */
+#define _LEUART_IFC_RXUF_MASK                    0x10UL                            /**< Bit mask for LEUART_RXUF */
+#define _LEUART_IFC_RXUF_DEFAULT                 0x00000000UL                      /**< Mode DEFAULT for LEUART_IFC */
+#define LEUART_IFC_RXUF_DEFAULT                  (_LEUART_IFC_RXUF_DEFAULT << 4)   /**< Shifted mode DEFAULT for LEUART_IFC */
+#define LEUART_IFC_TXOF                          (0x1UL << 5)                      /**< Clear TXOF Interrupt Flag */
+#define _LEUART_IFC_TXOF_SHIFT                   5                                 /**< Shift value for LEUART_TXOF */
+#define _LEUART_IFC_TXOF_MASK                    0x20UL                            /**< Bit mask for LEUART_TXOF */
+#define _LEUART_IFC_TXOF_DEFAULT                 0x00000000UL                      /**< Mode DEFAULT for LEUART_IFC */
+#define LEUART_IFC_TXOF_DEFAULT                  (_LEUART_IFC_TXOF_DEFAULT << 5)   /**< Shifted mode DEFAULT for LEUART_IFC */
+#define LEUART_IFC_PERR                          (0x1UL << 6)                      /**< Clear PERR Interrupt Flag */
+#define _LEUART_IFC_PERR_SHIFT                   6                                 /**< Shift value for LEUART_PERR */
+#define _LEUART_IFC_PERR_MASK                    0x40UL                            /**< Bit mask for LEUART_PERR */
+#define _LEUART_IFC_PERR_DEFAULT                 0x00000000UL                      /**< Mode DEFAULT for LEUART_IFC */
+#define LEUART_IFC_PERR_DEFAULT                  (_LEUART_IFC_PERR_DEFAULT << 6)   /**< Shifted mode DEFAULT for LEUART_IFC */
+#define LEUART_IFC_FERR                          (0x1UL << 7)                      /**< Clear FERR Interrupt Flag */
+#define _LEUART_IFC_FERR_SHIFT                   7                                 /**< Shift value for LEUART_FERR */
+#define _LEUART_IFC_FERR_MASK                    0x80UL                            /**< Bit mask for LEUART_FERR */
+#define _LEUART_IFC_FERR_DEFAULT                 0x00000000UL                      /**< Mode DEFAULT for LEUART_IFC */
+#define LEUART_IFC_FERR_DEFAULT                  (_LEUART_IFC_FERR_DEFAULT << 7)   /**< Shifted mode DEFAULT for LEUART_IFC */
+#define LEUART_IFC_MPAF                          (0x1UL << 8)                      /**< Clear MPAF Interrupt Flag */
+#define _LEUART_IFC_MPAF_SHIFT                   8                                 /**< Shift value for LEUART_MPAF */
+#define _LEUART_IFC_MPAF_MASK                    0x100UL                           /**< Bit mask for LEUART_MPAF */
+#define _LEUART_IFC_MPAF_DEFAULT                 0x00000000UL                      /**< Mode DEFAULT for LEUART_IFC */
+#define LEUART_IFC_MPAF_DEFAULT                  (_LEUART_IFC_MPAF_DEFAULT << 8)   /**< Shifted mode DEFAULT for LEUART_IFC */
+#define LEUART_IFC_STARTF                        (0x1UL << 9)                      /**< Clear STARTF Interrupt Flag */
+#define _LEUART_IFC_STARTF_SHIFT                 9                                 /**< Shift value for LEUART_STARTF */
+#define _LEUART_IFC_STARTF_MASK                  0x200UL                           /**< Bit mask for LEUART_STARTF */
+#define _LEUART_IFC_STARTF_DEFAULT               0x00000000UL                      /**< Mode DEFAULT for LEUART_IFC */
+#define LEUART_IFC_STARTF_DEFAULT                (_LEUART_IFC_STARTF_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_IFC */
+#define LEUART_IFC_SIGF                          (0x1UL << 10)                     /**< Clear SIGF Interrupt Flag */
+#define _LEUART_IFC_SIGF_SHIFT                   10                                /**< Shift value for LEUART_SIGF */
+#define _LEUART_IFC_SIGF_MASK                    0x400UL                           /**< Bit mask for LEUART_SIGF */
+#define _LEUART_IFC_SIGF_DEFAULT                 0x00000000UL                      /**< Mode DEFAULT for LEUART_IFC */
+#define LEUART_IFC_SIGF_DEFAULT                  (_LEUART_IFC_SIGF_DEFAULT << 10)  /**< Shifted mode DEFAULT for LEUART_IFC */
+
+/* Bit fields for LEUART IEN */
+#define _LEUART_IEN_RESETVALUE                   0x00000000UL                       /**< Default value for LEUART_IEN */
+#define _LEUART_IEN_MASK                         0x000007FFUL                       /**< Mask for LEUART_IEN */
+#define LEUART_IEN_TXC                           (0x1UL << 0)                       /**< TXC Interrupt Enable */
+#define _LEUART_IEN_TXC_SHIFT                    0                                  /**< Shift value for LEUART_TXC */
+#define _LEUART_IEN_TXC_MASK                     0x1UL                              /**< Bit mask for LEUART_TXC */
+#define _LEUART_IEN_TXC_DEFAULT                  0x00000000UL                       /**< Mode DEFAULT for LEUART_IEN */
+#define LEUART_IEN_TXC_DEFAULT                   (_LEUART_IEN_TXC_DEFAULT << 0)     /**< Shifted mode DEFAULT for LEUART_IEN */
+#define LEUART_IEN_TXBL                          (0x1UL << 1)                       /**< TXBL Interrupt Enable */
+#define _LEUART_IEN_TXBL_SHIFT                   1                                  /**< Shift value for LEUART_TXBL */
+#define _LEUART_IEN_TXBL_MASK                    0x2UL                              /**< Bit mask for LEUART_TXBL */
+#define _LEUART_IEN_TXBL_DEFAULT                 0x00000000UL                       /**< Mode DEFAULT for LEUART_IEN */
+#define LEUART_IEN_TXBL_DEFAULT                  (_LEUART_IEN_TXBL_DEFAULT << 1)    /**< Shifted mode DEFAULT for LEUART_IEN */
+#define LEUART_IEN_RXDATAV                       (0x1UL << 2)                       /**< RXDATAV Interrupt Enable */
+#define _LEUART_IEN_RXDATAV_SHIFT                2                                  /**< Shift value for LEUART_RXDATAV */
+#define _LEUART_IEN_RXDATAV_MASK                 0x4UL                              /**< Bit mask for LEUART_RXDATAV */
+#define _LEUART_IEN_RXDATAV_DEFAULT              0x00000000UL                       /**< Mode DEFAULT for LEUART_IEN */
+#define LEUART_IEN_RXDATAV_DEFAULT               (_LEUART_IEN_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_IEN */
+#define LEUART_IEN_RXOF                          (0x1UL << 3)                       /**< RXOF Interrupt Enable */
+#define _LEUART_IEN_RXOF_SHIFT                   3                                  /**< Shift value for LEUART_RXOF */
+#define _LEUART_IEN_RXOF_MASK                    0x8UL                              /**< Bit mask for LEUART_RXOF */
+#define _LEUART_IEN_RXOF_DEFAULT                 0x00000000UL                       /**< Mode DEFAULT for LEUART_IEN */
+#define LEUART_IEN_RXOF_DEFAULT                  (_LEUART_IEN_RXOF_DEFAULT << 3)    /**< Shifted mode DEFAULT for LEUART_IEN */
+#define LEUART_IEN_RXUF                          (0x1UL << 4)                       /**< RXUF Interrupt Enable */
+#define _LEUART_IEN_RXUF_SHIFT                   4                                  /**< Shift value for LEUART_RXUF */
+#define _LEUART_IEN_RXUF_MASK                    0x10UL                             /**< Bit mask for LEUART_RXUF */
+#define _LEUART_IEN_RXUF_DEFAULT                 0x00000000UL                       /**< Mode DEFAULT for LEUART_IEN */
+#define LEUART_IEN_RXUF_DEFAULT                  (_LEUART_IEN_RXUF_DEFAULT << 4)    /**< Shifted mode DEFAULT for LEUART_IEN */
+#define LEUART_IEN_TXOF                          (0x1UL << 5)                       /**< TXOF Interrupt Enable */
+#define _LEUART_IEN_TXOF_SHIFT                   5                                  /**< Shift value for LEUART_TXOF */
+#define _LEUART_IEN_TXOF_MASK                    0x20UL                             /**< Bit mask for LEUART_TXOF */
+#define _LEUART_IEN_TXOF_DEFAULT                 0x00000000UL                       /**< Mode DEFAULT for LEUART_IEN */
+#define LEUART_IEN_TXOF_DEFAULT                  (_LEUART_IEN_TXOF_DEFAULT << 5)    /**< Shifted mode DEFAULT for LEUART_IEN */
+#define LEUART_IEN_PERR                          (0x1UL << 6)                       /**< PERR Interrupt Enable */
+#define _LEUART_IEN_PERR_SHIFT                   6                                  /**< Shift value for LEUART_PERR */
+#define _LEUART_IEN_PERR_MASK                    0x40UL                             /**< Bit mask for LEUART_PERR */
+#define _LEUART_IEN_PERR_DEFAULT                 0x00000000UL                       /**< Mode DEFAULT for LEUART_IEN */
+#define LEUART_IEN_PERR_DEFAULT                  (_LEUART_IEN_PERR_DEFAULT << 6)    /**< Shifted mode DEFAULT for LEUART_IEN */
+#define LEUART_IEN_FERR                          (0x1UL << 7)                       /**< FERR Interrupt Enable */
+#define _LEUART_IEN_FERR_SHIFT                   7                                  /**< Shift value for LEUART_FERR */
+#define _LEUART_IEN_FERR_MASK                    0x80UL                             /**< Bit mask for LEUART_FERR */
+#define _LEUART_IEN_FERR_DEFAULT                 0x00000000UL                       /**< Mode DEFAULT for LEUART_IEN */
+#define LEUART_IEN_FERR_DEFAULT                  (_LEUART_IEN_FERR_DEFAULT << 7)    /**< Shifted mode DEFAULT for LEUART_IEN */
+#define LEUART_IEN_MPAF                          (0x1UL << 8)                       /**< MPAF Interrupt Enable */
+#define _LEUART_IEN_MPAF_SHIFT                   8                                  /**< Shift value for LEUART_MPAF */
+#define _LEUART_IEN_MPAF_MASK                    0x100UL                            /**< Bit mask for LEUART_MPAF */
+#define _LEUART_IEN_MPAF_DEFAULT                 0x00000000UL                       /**< Mode DEFAULT for LEUART_IEN */
+#define LEUART_IEN_MPAF_DEFAULT                  (_LEUART_IEN_MPAF_DEFAULT << 8)    /**< Shifted mode DEFAULT for LEUART_IEN */
+#define LEUART_IEN_STARTF                        (0x1UL << 9)                       /**< STARTF Interrupt Enable */
+#define _LEUART_IEN_STARTF_SHIFT                 9                                  /**< Shift value for LEUART_STARTF */
+#define _LEUART_IEN_STARTF_MASK                  0x200UL                            /**< Bit mask for LEUART_STARTF */
+#define _LEUART_IEN_STARTF_DEFAULT               0x00000000UL                       /**< Mode DEFAULT for LEUART_IEN */
+#define LEUART_IEN_STARTF_DEFAULT                (_LEUART_IEN_STARTF_DEFAULT << 9)  /**< Shifted mode DEFAULT for LEUART_IEN */
+#define LEUART_IEN_SIGF                          (0x1UL << 10)                      /**< SIGF Interrupt Enable */
+#define _LEUART_IEN_SIGF_SHIFT                   10                                 /**< Shift value for LEUART_SIGF */
+#define _LEUART_IEN_SIGF_MASK                    0x400UL                            /**< Bit mask for LEUART_SIGF */
+#define _LEUART_IEN_SIGF_DEFAULT                 0x00000000UL                       /**< Mode DEFAULT for LEUART_IEN */
+#define LEUART_IEN_SIGF_DEFAULT                  (_LEUART_IEN_SIGF_DEFAULT << 10)   /**< Shifted mode DEFAULT for LEUART_IEN */
+
+/* Bit fields for LEUART PULSECTRL */
+#define _LEUART_PULSECTRL_RESETVALUE             0x00000000UL                               /**< Default value for LEUART_PULSECTRL */
+#define _LEUART_PULSECTRL_MASK                   0x0000003FUL                               /**< Mask for LEUART_PULSECTRL */
+#define _LEUART_PULSECTRL_PULSEW_SHIFT           0                                          /**< Shift value for LEUART_PULSEW */
+#define _LEUART_PULSECTRL_PULSEW_MASK            0xFUL                                      /**< Bit mask for LEUART_PULSEW */
+#define _LEUART_PULSECTRL_PULSEW_DEFAULT         0x00000000UL                               /**< Mode DEFAULT for LEUART_PULSECTRL */
+#define LEUART_PULSECTRL_PULSEW_DEFAULT          (_LEUART_PULSECTRL_PULSEW_DEFAULT << 0)    /**< Shifted mode DEFAULT for LEUART_PULSECTRL */
+#define LEUART_PULSECTRL_PULSEEN                 (0x1UL << 4)                               /**< Pulse Generator/Extender Enable */
+#define _LEUART_PULSECTRL_PULSEEN_SHIFT          4                                          /**< Shift value for LEUART_PULSEEN */
+#define _LEUART_PULSECTRL_PULSEEN_MASK           0x10UL                                     /**< Bit mask for LEUART_PULSEEN */
+#define _LEUART_PULSECTRL_PULSEEN_DEFAULT        0x00000000UL                               /**< Mode DEFAULT for LEUART_PULSECTRL */
+#define LEUART_PULSECTRL_PULSEEN_DEFAULT         (_LEUART_PULSECTRL_PULSEEN_DEFAULT << 4)   /**< Shifted mode DEFAULT for LEUART_PULSECTRL */
+#define LEUART_PULSECTRL_PULSEFILT               (0x1UL << 5)                               /**< Pulse Filter */
+#define _LEUART_PULSECTRL_PULSEFILT_SHIFT        5                                          /**< Shift value for LEUART_PULSEFILT */
+#define _LEUART_PULSECTRL_PULSEFILT_MASK         0x20UL                                     /**< Bit mask for LEUART_PULSEFILT */
+#define _LEUART_PULSECTRL_PULSEFILT_DEFAULT      0x00000000UL                               /**< Mode DEFAULT for LEUART_PULSECTRL */
+#define LEUART_PULSECTRL_PULSEFILT_DEFAULT       (_LEUART_PULSECTRL_PULSEFILT_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_PULSECTRL */
+
+/* Bit fields for LEUART FREEZE */
+#define _LEUART_FREEZE_RESETVALUE                0x00000000UL                            /**< Default value for LEUART_FREEZE */
+#define _LEUART_FREEZE_MASK                      0x00000001UL                            /**< Mask for LEUART_FREEZE */
+#define LEUART_FREEZE_REGFREEZE                  (0x1UL << 0)                            /**< Register Update Freeze */
+#define _LEUART_FREEZE_REGFREEZE_SHIFT           0                                       /**< Shift value for LEUART_REGFREEZE */
+#define _LEUART_FREEZE_REGFREEZE_MASK            0x1UL                                   /**< Bit mask for LEUART_REGFREEZE */
+#define _LEUART_FREEZE_REGFREEZE_DEFAULT         0x00000000UL                            /**< Mode DEFAULT for LEUART_FREEZE */
+#define _LEUART_FREEZE_REGFREEZE_UPDATE          0x00000000UL                            /**< Mode UPDATE for LEUART_FREEZE */
+#define _LEUART_FREEZE_REGFREEZE_FREEZE          0x00000001UL                            /**< Mode FREEZE for LEUART_FREEZE */
+#define LEUART_FREEZE_REGFREEZE_DEFAULT          (_LEUART_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_FREEZE */
+#define LEUART_FREEZE_REGFREEZE_UPDATE           (_LEUART_FREEZE_REGFREEZE_UPDATE << 0)  /**< Shifted mode UPDATE for LEUART_FREEZE */
+#define LEUART_FREEZE_REGFREEZE_FREEZE           (_LEUART_FREEZE_REGFREEZE_FREEZE << 0)  /**< Shifted mode FREEZE for LEUART_FREEZE */
+
+/* Bit fields for LEUART SYNCBUSY */
+#define _LEUART_SYNCBUSY_RESETVALUE              0x00000000UL                               /**< Default value for LEUART_SYNCBUSY */
+#define _LEUART_SYNCBUSY_MASK                    0x000000FFUL                               /**< Mask for LEUART_SYNCBUSY */
+#define LEUART_SYNCBUSY_CTRL                     (0x1UL << 0)                               /**< CTRL Register Busy */
+#define _LEUART_SYNCBUSY_CTRL_SHIFT              0                                          /**< Shift value for LEUART_CTRL */
+#define _LEUART_SYNCBUSY_CTRL_MASK               0x1UL                                      /**< Bit mask for LEUART_CTRL */
+#define _LEUART_SYNCBUSY_CTRL_DEFAULT            0x00000000UL                               /**< Mode DEFAULT for LEUART_SYNCBUSY */
+#define LEUART_SYNCBUSY_CTRL_DEFAULT             (_LEUART_SYNCBUSY_CTRL_DEFAULT << 0)       /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
+#define LEUART_SYNCBUSY_CMD                      (0x1UL << 1)                               /**< CMD Register Busy */
+#define _LEUART_SYNCBUSY_CMD_SHIFT               1                                          /**< Shift value for LEUART_CMD */
+#define _LEUART_SYNCBUSY_CMD_MASK                0x2UL                                      /**< Bit mask for LEUART_CMD */
+#define _LEUART_SYNCBUSY_CMD_DEFAULT             0x00000000UL                               /**< Mode DEFAULT for LEUART_SYNCBUSY */
+#define LEUART_SYNCBUSY_CMD_DEFAULT              (_LEUART_SYNCBUSY_CMD_DEFAULT << 1)        /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
+#define LEUART_SYNCBUSY_CLKDIV                   (0x1UL << 2)                               /**< CLKDIV Register Busy */
+#define _LEUART_SYNCBUSY_CLKDIV_SHIFT            2                                          /**< Shift value for LEUART_CLKDIV */
+#define _LEUART_SYNCBUSY_CLKDIV_MASK             0x4UL                                      /**< Bit mask for LEUART_CLKDIV */
+#define _LEUART_SYNCBUSY_CLKDIV_DEFAULT          0x00000000UL                               /**< Mode DEFAULT for LEUART_SYNCBUSY */
+#define LEUART_SYNCBUSY_CLKDIV_DEFAULT           (_LEUART_SYNCBUSY_CLKDIV_DEFAULT << 2)     /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
+#define LEUART_SYNCBUSY_STARTFRAME               (0x1UL << 3)                               /**< STARTFRAME Register Busy */
+#define _LEUART_SYNCBUSY_STARTFRAME_SHIFT        3                                          /**< Shift value for LEUART_STARTFRAME */
+#define _LEUART_SYNCBUSY_STARTFRAME_MASK         0x8UL                                      /**< Bit mask for LEUART_STARTFRAME */
+#define _LEUART_SYNCBUSY_STARTFRAME_DEFAULT      0x00000000UL                               /**< Mode DEFAULT for LEUART_SYNCBUSY */
+#define LEUART_SYNCBUSY_STARTFRAME_DEFAULT       (_LEUART_SYNCBUSY_STARTFRAME_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
+#define LEUART_SYNCBUSY_SIGFRAME                 (0x1UL << 4)                               /**< SIGFRAME Register Busy */
+#define _LEUART_SYNCBUSY_SIGFRAME_SHIFT          4                                          /**< Shift value for LEUART_SIGFRAME */
+#define _LEUART_SYNCBUSY_SIGFRAME_MASK           0x10UL                                     /**< Bit mask for LEUART_SIGFRAME */
+#define _LEUART_SYNCBUSY_SIGFRAME_DEFAULT        0x00000000UL                               /**< Mode DEFAULT for LEUART_SYNCBUSY */
+#define LEUART_SYNCBUSY_SIGFRAME_DEFAULT         (_LEUART_SYNCBUSY_SIGFRAME_DEFAULT << 4)   /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
+#define LEUART_SYNCBUSY_TXDATAX                  (0x1UL << 5)                               /**< TXDATAX Register Busy */
+#define _LEUART_SYNCBUSY_TXDATAX_SHIFT           5                                          /**< Shift value for LEUART_TXDATAX */
+#define _LEUART_SYNCBUSY_TXDATAX_MASK            0x20UL                                     /**< Bit mask for LEUART_TXDATAX */
+#define _LEUART_SYNCBUSY_TXDATAX_DEFAULT         0x00000000UL                               /**< Mode DEFAULT for LEUART_SYNCBUSY */
+#define LEUART_SYNCBUSY_TXDATAX_DEFAULT          (_LEUART_SYNCBUSY_TXDATAX_DEFAULT << 5)    /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
+#define LEUART_SYNCBUSY_TXDATA                   (0x1UL << 6)                               /**< TXDATA Register Busy */
+#define _LEUART_SYNCBUSY_TXDATA_SHIFT            6                                          /**< Shift value for LEUART_TXDATA */
+#define _LEUART_SYNCBUSY_TXDATA_MASK             0x40UL                                     /**< Bit mask for LEUART_TXDATA */
+#define _LEUART_SYNCBUSY_TXDATA_DEFAULT          0x00000000UL                               /**< Mode DEFAULT for LEUART_SYNCBUSY */
+#define LEUART_SYNCBUSY_TXDATA_DEFAULT           (_LEUART_SYNCBUSY_TXDATA_DEFAULT << 6)     /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
+#define LEUART_SYNCBUSY_PULSECTRL                (0x1UL << 7)                               /**< PULSECTRL Register Busy */
+#define _LEUART_SYNCBUSY_PULSECTRL_SHIFT         7                                          /**< Shift value for LEUART_PULSECTRL */
+#define _LEUART_SYNCBUSY_PULSECTRL_MASK          0x80UL                                     /**< Bit mask for LEUART_PULSECTRL */
+#define _LEUART_SYNCBUSY_PULSECTRL_DEFAULT       0x00000000UL                               /**< Mode DEFAULT for LEUART_SYNCBUSY */
+#define LEUART_SYNCBUSY_PULSECTRL_DEFAULT        (_LEUART_SYNCBUSY_PULSECTRL_DEFAULT << 7)  /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
+
+/* Bit fields for LEUART ROUTEPEN */
+#define _LEUART_ROUTEPEN_RESETVALUE              0x00000000UL                          /**< Default value for LEUART_ROUTEPEN */
+#define _LEUART_ROUTEPEN_MASK                    0x00000003UL                          /**< Mask for LEUART_ROUTEPEN */
+#define LEUART_ROUTEPEN_RXPEN                    (0x1UL << 0)                          /**< RX Pin Enable */
+#define _LEUART_ROUTEPEN_RXPEN_SHIFT             0                                     /**< Shift value for LEUART_RXPEN */
+#define _LEUART_ROUTEPEN_RXPEN_MASK              0x1UL                                 /**< Bit mask for LEUART_RXPEN */
+#define _LEUART_ROUTEPEN_RXPEN_DEFAULT           0x00000000UL                          /**< Mode DEFAULT for LEUART_ROUTEPEN */
+#define LEUART_ROUTEPEN_RXPEN_DEFAULT            (_LEUART_ROUTEPEN_RXPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_ROUTEPEN */
+#define LEUART_ROUTEPEN_TXPEN                    (0x1UL << 1)                          /**< TX Pin Enable */
+#define _LEUART_ROUTEPEN_TXPEN_SHIFT             1                                     /**< Shift value for LEUART_TXPEN */
+#define _LEUART_ROUTEPEN_TXPEN_MASK              0x2UL                                 /**< Bit mask for LEUART_TXPEN */
+#define _LEUART_ROUTEPEN_TXPEN_DEFAULT           0x00000000UL                          /**< Mode DEFAULT for LEUART_ROUTEPEN */
+#define LEUART_ROUTEPEN_TXPEN_DEFAULT            (_LEUART_ROUTEPEN_TXPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_ROUTEPEN */
+
+/* Bit fields for LEUART ROUTELOC0 */
+#define _LEUART_ROUTELOC0_RESETVALUE             0x00000000UL                           /**< Default value for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_MASK                   0x00001F1FUL                           /**< Mask for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_RXLOC_SHIFT            0                                      /**< Shift value for LEUART_RXLOC */
+#define _LEUART_ROUTELOC0_RXLOC_MASK             0x1FUL                                 /**< Bit mask for LEUART_RXLOC */
+#define _LEUART_ROUTELOC0_RXLOC_LOC0             0x00000000UL                           /**< Mode LOC0 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_RXLOC_DEFAULT          0x00000000UL                           /**< Mode DEFAULT for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_RXLOC_LOC1             0x00000001UL                           /**< Mode LOC1 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_RXLOC_LOC2             0x00000002UL                           /**< Mode LOC2 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_RXLOC_LOC3             0x00000003UL                           /**< Mode LOC3 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_RXLOC_LOC4             0x00000004UL                           /**< Mode LOC4 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_RXLOC_LOC5             0x00000005UL                           /**< Mode LOC5 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_RXLOC_LOC6             0x00000006UL                           /**< Mode LOC6 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_RXLOC_LOC7             0x00000007UL                           /**< Mode LOC7 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_RXLOC_LOC8             0x00000008UL                           /**< Mode LOC8 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_RXLOC_LOC9             0x00000009UL                           /**< Mode LOC9 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_RXLOC_LOC10            0x0000000AUL                           /**< Mode LOC10 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_RXLOC_LOC11            0x0000000BUL                           /**< Mode LOC11 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_RXLOC_LOC12            0x0000000CUL                           /**< Mode LOC12 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_RXLOC_LOC13            0x0000000DUL                           /**< Mode LOC13 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_RXLOC_LOC14            0x0000000EUL                           /**< Mode LOC14 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_RXLOC_LOC15            0x0000000FUL                           /**< Mode LOC15 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_RXLOC_LOC16            0x00000010UL                           /**< Mode LOC16 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_RXLOC_LOC17            0x00000011UL                           /**< Mode LOC17 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_RXLOC_LOC18            0x00000012UL                           /**< Mode LOC18 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_RXLOC_LOC19            0x00000013UL                           /**< Mode LOC19 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_RXLOC_LOC20            0x00000014UL                           /**< Mode LOC20 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_RXLOC_LOC21            0x00000015UL                           /**< Mode LOC21 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_RXLOC_LOC22            0x00000016UL                           /**< Mode LOC22 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_RXLOC_LOC23            0x00000017UL                           /**< Mode LOC23 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_RXLOC_LOC24            0x00000018UL                           /**< Mode LOC24 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_RXLOC_LOC25            0x00000019UL                           /**< Mode LOC25 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_RXLOC_LOC26            0x0000001AUL                           /**< Mode LOC26 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_RXLOC_LOC27            0x0000001BUL                           /**< Mode LOC27 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_RXLOC_LOC28            0x0000001CUL                           /**< Mode LOC28 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_RXLOC_LOC29            0x0000001DUL                           /**< Mode LOC29 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_RXLOC_LOC30            0x0000001EUL                           /**< Mode LOC30 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_RXLOC_LOC31            0x0000001FUL                           /**< Mode LOC31 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_RXLOC_LOC0              (_LEUART_ROUTELOC0_RXLOC_LOC0 << 0)    /**< Shifted mode LOC0 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_RXLOC_DEFAULT           (_LEUART_ROUTELOC0_RXLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_RXLOC_LOC1              (_LEUART_ROUTELOC0_RXLOC_LOC1 << 0)    /**< Shifted mode LOC1 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_RXLOC_LOC2              (_LEUART_ROUTELOC0_RXLOC_LOC2 << 0)    /**< Shifted mode LOC2 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_RXLOC_LOC3              (_LEUART_ROUTELOC0_RXLOC_LOC3 << 0)    /**< Shifted mode LOC3 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_RXLOC_LOC4              (_LEUART_ROUTELOC0_RXLOC_LOC4 << 0)    /**< Shifted mode LOC4 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_RXLOC_LOC5              (_LEUART_ROUTELOC0_RXLOC_LOC5 << 0)    /**< Shifted mode LOC5 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_RXLOC_LOC6              (_LEUART_ROUTELOC0_RXLOC_LOC6 << 0)    /**< Shifted mode LOC6 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_RXLOC_LOC7              (_LEUART_ROUTELOC0_RXLOC_LOC7 << 0)    /**< Shifted mode LOC7 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_RXLOC_LOC8              (_LEUART_ROUTELOC0_RXLOC_LOC8 << 0)    /**< Shifted mode LOC8 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_RXLOC_LOC9              (_LEUART_ROUTELOC0_RXLOC_LOC9 << 0)    /**< Shifted mode LOC9 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_RXLOC_LOC10             (_LEUART_ROUTELOC0_RXLOC_LOC10 << 0)   /**< Shifted mode LOC10 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_RXLOC_LOC11             (_LEUART_ROUTELOC0_RXLOC_LOC11 << 0)   /**< Shifted mode LOC11 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_RXLOC_LOC12             (_LEUART_ROUTELOC0_RXLOC_LOC12 << 0)   /**< Shifted mode LOC12 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_RXLOC_LOC13             (_LEUART_ROUTELOC0_RXLOC_LOC13 << 0)   /**< Shifted mode LOC13 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_RXLOC_LOC14             (_LEUART_ROUTELOC0_RXLOC_LOC14 << 0)   /**< Shifted mode LOC14 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_RXLOC_LOC15             (_LEUART_ROUTELOC0_RXLOC_LOC15 << 0)   /**< Shifted mode LOC15 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_RXLOC_LOC16             (_LEUART_ROUTELOC0_RXLOC_LOC16 << 0)   /**< Shifted mode LOC16 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_RXLOC_LOC17             (_LEUART_ROUTELOC0_RXLOC_LOC17 << 0)   /**< Shifted mode LOC17 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_RXLOC_LOC18             (_LEUART_ROUTELOC0_RXLOC_LOC18 << 0)   /**< Shifted mode LOC18 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_RXLOC_LOC19             (_LEUART_ROUTELOC0_RXLOC_LOC19 << 0)   /**< Shifted mode LOC19 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_RXLOC_LOC20             (_LEUART_ROUTELOC0_RXLOC_LOC20 << 0)   /**< Shifted mode LOC20 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_RXLOC_LOC21             (_LEUART_ROUTELOC0_RXLOC_LOC21 << 0)   /**< Shifted mode LOC21 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_RXLOC_LOC22             (_LEUART_ROUTELOC0_RXLOC_LOC22 << 0)   /**< Shifted mode LOC22 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_RXLOC_LOC23             (_LEUART_ROUTELOC0_RXLOC_LOC23 << 0)   /**< Shifted mode LOC23 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_RXLOC_LOC24             (_LEUART_ROUTELOC0_RXLOC_LOC24 << 0)   /**< Shifted mode LOC24 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_RXLOC_LOC25             (_LEUART_ROUTELOC0_RXLOC_LOC25 << 0)   /**< Shifted mode LOC25 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_RXLOC_LOC26             (_LEUART_ROUTELOC0_RXLOC_LOC26 << 0)   /**< Shifted mode LOC26 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_RXLOC_LOC27             (_LEUART_ROUTELOC0_RXLOC_LOC27 << 0)   /**< Shifted mode LOC27 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_RXLOC_LOC28             (_LEUART_ROUTELOC0_RXLOC_LOC28 << 0)   /**< Shifted mode LOC28 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_RXLOC_LOC29             (_LEUART_ROUTELOC0_RXLOC_LOC29 << 0)   /**< Shifted mode LOC29 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_RXLOC_LOC30             (_LEUART_ROUTELOC0_RXLOC_LOC30 << 0)   /**< Shifted mode LOC30 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_RXLOC_LOC31             (_LEUART_ROUTELOC0_RXLOC_LOC31 << 0)   /**< Shifted mode LOC31 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_TXLOC_SHIFT            8                                      /**< Shift value for LEUART_TXLOC */
+#define _LEUART_ROUTELOC0_TXLOC_MASK             0x1F00UL                               /**< Bit mask for LEUART_TXLOC */
+#define _LEUART_ROUTELOC0_TXLOC_LOC0             0x00000000UL                           /**< Mode LOC0 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_TXLOC_DEFAULT          0x00000000UL                           /**< Mode DEFAULT for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_TXLOC_LOC1             0x00000001UL                           /**< Mode LOC1 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_TXLOC_LOC2             0x00000002UL                           /**< Mode LOC2 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_TXLOC_LOC3             0x00000003UL                           /**< Mode LOC3 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_TXLOC_LOC4             0x00000004UL                           /**< Mode LOC4 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_TXLOC_LOC5             0x00000005UL                           /**< Mode LOC5 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_TXLOC_LOC6             0x00000006UL                           /**< Mode LOC6 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_TXLOC_LOC7             0x00000007UL                           /**< Mode LOC7 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_TXLOC_LOC8             0x00000008UL                           /**< Mode LOC8 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_TXLOC_LOC9             0x00000009UL                           /**< Mode LOC9 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_TXLOC_LOC10            0x0000000AUL                           /**< Mode LOC10 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_TXLOC_LOC11            0x0000000BUL                           /**< Mode LOC11 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_TXLOC_LOC12            0x0000000CUL                           /**< Mode LOC12 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_TXLOC_LOC13            0x0000000DUL                           /**< Mode LOC13 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_TXLOC_LOC14            0x0000000EUL                           /**< Mode LOC14 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_TXLOC_LOC15            0x0000000FUL                           /**< Mode LOC15 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_TXLOC_LOC16            0x00000010UL                           /**< Mode LOC16 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_TXLOC_LOC17            0x00000011UL                           /**< Mode LOC17 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_TXLOC_LOC18            0x00000012UL                           /**< Mode LOC18 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_TXLOC_LOC19            0x00000013UL                           /**< Mode LOC19 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_TXLOC_LOC20            0x00000014UL                           /**< Mode LOC20 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_TXLOC_LOC21            0x00000015UL                           /**< Mode LOC21 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_TXLOC_LOC22            0x00000016UL                           /**< Mode LOC22 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_TXLOC_LOC23            0x00000017UL                           /**< Mode LOC23 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_TXLOC_LOC24            0x00000018UL                           /**< Mode LOC24 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_TXLOC_LOC25            0x00000019UL                           /**< Mode LOC25 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_TXLOC_LOC26            0x0000001AUL                           /**< Mode LOC26 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_TXLOC_LOC27            0x0000001BUL                           /**< Mode LOC27 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_TXLOC_LOC28            0x0000001CUL                           /**< Mode LOC28 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_TXLOC_LOC29            0x0000001DUL                           /**< Mode LOC29 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_TXLOC_LOC30            0x0000001EUL                           /**< Mode LOC30 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_TXLOC_LOC31            0x0000001FUL                           /**< Mode LOC31 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_TXLOC_LOC0              (_LEUART_ROUTELOC0_TXLOC_LOC0 << 8)    /**< Shifted mode LOC0 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_TXLOC_DEFAULT           (_LEUART_ROUTELOC0_TXLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_TXLOC_LOC1              (_LEUART_ROUTELOC0_TXLOC_LOC1 << 8)    /**< Shifted mode LOC1 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_TXLOC_LOC2              (_LEUART_ROUTELOC0_TXLOC_LOC2 << 8)    /**< Shifted mode LOC2 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_TXLOC_LOC3              (_LEUART_ROUTELOC0_TXLOC_LOC3 << 8)    /**< Shifted mode LOC3 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_TXLOC_LOC4              (_LEUART_ROUTELOC0_TXLOC_LOC4 << 8)    /**< Shifted mode LOC4 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_TXLOC_LOC5              (_LEUART_ROUTELOC0_TXLOC_LOC5 << 8)    /**< Shifted mode LOC5 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_TXLOC_LOC6              (_LEUART_ROUTELOC0_TXLOC_LOC6 << 8)    /**< Shifted mode LOC6 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_TXLOC_LOC7              (_LEUART_ROUTELOC0_TXLOC_LOC7 << 8)    /**< Shifted mode LOC7 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_TXLOC_LOC8              (_LEUART_ROUTELOC0_TXLOC_LOC8 << 8)    /**< Shifted mode LOC8 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_TXLOC_LOC9              (_LEUART_ROUTELOC0_TXLOC_LOC9 << 8)    /**< Shifted mode LOC9 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_TXLOC_LOC10             (_LEUART_ROUTELOC0_TXLOC_LOC10 << 8)   /**< Shifted mode LOC10 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_TXLOC_LOC11             (_LEUART_ROUTELOC0_TXLOC_LOC11 << 8)   /**< Shifted mode LOC11 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_TXLOC_LOC12             (_LEUART_ROUTELOC0_TXLOC_LOC12 << 8)   /**< Shifted mode LOC12 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_TXLOC_LOC13             (_LEUART_ROUTELOC0_TXLOC_LOC13 << 8)   /**< Shifted mode LOC13 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_TXLOC_LOC14             (_LEUART_ROUTELOC0_TXLOC_LOC14 << 8)   /**< Shifted mode LOC14 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_TXLOC_LOC15             (_LEUART_ROUTELOC0_TXLOC_LOC15 << 8)   /**< Shifted mode LOC15 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_TXLOC_LOC16             (_LEUART_ROUTELOC0_TXLOC_LOC16 << 8)   /**< Shifted mode LOC16 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_TXLOC_LOC17             (_LEUART_ROUTELOC0_TXLOC_LOC17 << 8)   /**< Shifted mode LOC17 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_TXLOC_LOC18             (_LEUART_ROUTELOC0_TXLOC_LOC18 << 8)   /**< Shifted mode LOC18 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_TXLOC_LOC19             (_LEUART_ROUTELOC0_TXLOC_LOC19 << 8)   /**< Shifted mode LOC19 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_TXLOC_LOC20             (_LEUART_ROUTELOC0_TXLOC_LOC20 << 8)   /**< Shifted mode LOC20 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_TXLOC_LOC21             (_LEUART_ROUTELOC0_TXLOC_LOC21 << 8)   /**< Shifted mode LOC21 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_TXLOC_LOC22             (_LEUART_ROUTELOC0_TXLOC_LOC22 << 8)   /**< Shifted mode LOC22 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_TXLOC_LOC23             (_LEUART_ROUTELOC0_TXLOC_LOC23 << 8)   /**< Shifted mode LOC23 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_TXLOC_LOC24             (_LEUART_ROUTELOC0_TXLOC_LOC24 << 8)   /**< Shifted mode LOC24 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_TXLOC_LOC25             (_LEUART_ROUTELOC0_TXLOC_LOC25 << 8)   /**< Shifted mode LOC25 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_TXLOC_LOC26             (_LEUART_ROUTELOC0_TXLOC_LOC26 << 8)   /**< Shifted mode LOC26 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_TXLOC_LOC27             (_LEUART_ROUTELOC0_TXLOC_LOC27 << 8)   /**< Shifted mode LOC27 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_TXLOC_LOC28             (_LEUART_ROUTELOC0_TXLOC_LOC28 << 8)   /**< Shifted mode LOC28 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_TXLOC_LOC29             (_LEUART_ROUTELOC0_TXLOC_LOC29 << 8)   /**< Shifted mode LOC29 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_TXLOC_LOC30             (_LEUART_ROUTELOC0_TXLOC_LOC30 << 8)   /**< Shifted mode LOC30 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_TXLOC_LOC31             (_LEUART_ROUTELOC0_TXLOC_LOC31 << 8)   /**< Shifted mode LOC31 for LEUART_ROUTELOC0 */
+
+/* Bit fields for LEUART INPUT */
+#define _LEUART_INPUT_RESETVALUE                 0x00000000UL                          /**< Default value for LEUART_INPUT */
+#define _LEUART_INPUT_MASK                       0x0000002FUL                          /**< Mask for LEUART_INPUT */
+#define _LEUART_INPUT_RXPRSSEL_SHIFT             0                                     /**< Shift value for LEUART_RXPRSSEL */
+#define _LEUART_INPUT_RXPRSSEL_MASK              0xFUL                                 /**< Bit mask for LEUART_RXPRSSEL */
+#define _LEUART_INPUT_RXPRSSEL_DEFAULT           0x00000000UL                          /**< Mode DEFAULT for LEUART_INPUT */
+#define _LEUART_INPUT_RXPRSSEL_PRSCH0            0x00000000UL                          /**< Mode PRSCH0 for LEUART_INPUT */
+#define _LEUART_INPUT_RXPRSSEL_PRSCH1            0x00000001UL                          /**< Mode PRSCH1 for LEUART_INPUT */
+#define _LEUART_INPUT_RXPRSSEL_PRSCH2            0x00000002UL                          /**< Mode PRSCH2 for LEUART_INPUT */
+#define _LEUART_INPUT_RXPRSSEL_PRSCH3            0x00000003UL                          /**< Mode PRSCH3 for LEUART_INPUT */
+#define _LEUART_INPUT_RXPRSSEL_PRSCH4            0x00000004UL                          /**< Mode PRSCH4 for LEUART_INPUT */
+#define _LEUART_INPUT_RXPRSSEL_PRSCH5            0x00000005UL                          /**< Mode PRSCH5 for LEUART_INPUT */
+#define _LEUART_INPUT_RXPRSSEL_PRSCH6            0x00000006UL                          /**< Mode PRSCH6 for LEUART_INPUT */
+#define _LEUART_INPUT_RXPRSSEL_PRSCH7            0x00000007UL                          /**< Mode PRSCH7 for LEUART_INPUT */
+#define _LEUART_INPUT_RXPRSSEL_PRSCH8            0x00000008UL                          /**< Mode PRSCH8 for LEUART_INPUT */
+#define _LEUART_INPUT_RXPRSSEL_PRSCH9            0x00000009UL                          /**< Mode PRSCH9 for LEUART_INPUT */
+#define _LEUART_INPUT_RXPRSSEL_PRSCH10           0x0000000AUL                          /**< Mode PRSCH10 for LEUART_INPUT */
+#define _LEUART_INPUT_RXPRSSEL_PRSCH11           0x0000000BUL                          /**< Mode PRSCH11 for LEUART_INPUT */
+#define LEUART_INPUT_RXPRSSEL_DEFAULT            (_LEUART_INPUT_RXPRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_INPUT */
+#define LEUART_INPUT_RXPRSSEL_PRSCH0             (_LEUART_INPUT_RXPRSSEL_PRSCH0 << 0)  /**< Shifted mode PRSCH0 for LEUART_INPUT */
+#define LEUART_INPUT_RXPRSSEL_PRSCH1             (_LEUART_INPUT_RXPRSSEL_PRSCH1 << 0)  /**< Shifted mode PRSCH1 for LEUART_INPUT */
+#define LEUART_INPUT_RXPRSSEL_PRSCH2             (_LEUART_INPUT_RXPRSSEL_PRSCH2 << 0)  /**< Shifted mode PRSCH2 for LEUART_INPUT */
+#define LEUART_INPUT_RXPRSSEL_PRSCH3             (_LEUART_INPUT_RXPRSSEL_PRSCH3 << 0)  /**< Shifted mode PRSCH3 for LEUART_INPUT */
+#define LEUART_INPUT_RXPRSSEL_PRSCH4             (_LEUART_INPUT_RXPRSSEL_PRSCH4 << 0)  /**< Shifted mode PRSCH4 for LEUART_INPUT */
+#define LEUART_INPUT_RXPRSSEL_PRSCH5             (_LEUART_INPUT_RXPRSSEL_PRSCH5 << 0)  /**< Shifted mode PRSCH5 for LEUART_INPUT */
+#define LEUART_INPUT_RXPRSSEL_PRSCH6             (_LEUART_INPUT_RXPRSSEL_PRSCH6 << 0)  /**< Shifted mode PRSCH6 for LEUART_INPUT */
+#define LEUART_INPUT_RXPRSSEL_PRSCH7             (_LEUART_INPUT_RXPRSSEL_PRSCH7 << 0)  /**< Shifted mode PRSCH7 for LEUART_INPUT */
+#define LEUART_INPUT_RXPRSSEL_PRSCH8             (_LEUART_INPUT_RXPRSSEL_PRSCH8 << 0)  /**< Shifted mode PRSCH8 for LEUART_INPUT */
+#define LEUART_INPUT_RXPRSSEL_PRSCH9             (_LEUART_INPUT_RXPRSSEL_PRSCH9 << 0)  /**< Shifted mode PRSCH9 for LEUART_INPUT */
+#define LEUART_INPUT_RXPRSSEL_PRSCH10            (_LEUART_INPUT_RXPRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for LEUART_INPUT */
+#define LEUART_INPUT_RXPRSSEL_PRSCH11            (_LEUART_INPUT_RXPRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for LEUART_INPUT */
+#define LEUART_INPUT_RXPRS                       (0x1UL << 5)                          /**< PRS RX Enable */
+#define _LEUART_INPUT_RXPRS_SHIFT                5                                     /**< Shift value for LEUART_RXPRS */
+#define _LEUART_INPUT_RXPRS_MASK                 0x20UL                                /**< Bit mask for LEUART_RXPRS */
+#define _LEUART_INPUT_RXPRS_DEFAULT              0x00000000UL                          /**< Mode DEFAULT for LEUART_INPUT */
+#define LEUART_INPUT_RXPRS_DEFAULT               (_LEUART_INPUT_RXPRS_DEFAULT << 5)    /**< Shifted mode DEFAULT for LEUART_INPUT */
+
+/** @} End of group EFM32PG1B_LEUART */
+/** @} End of group Parts */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG_STK3401/efm32pg1b_msc.h	Fri Jan 15 07:45:16 2016 +0000
@@ -0,0 +1,500 @@
+/**************************************************************************//**
+ * @file efm32pg1b_msc.h
+ * @brief EFM32PG1B_MSC register and bit field definitions
+ * @version 4.2.0
+ ******************************************************************************
+ * @section License
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ ******************************************************************************
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software.@n
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.@n
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is
+ * providing the Software "AS IS", with no express or implied warranties of any
+ * kind, including, but not limited to, any implied warranties of
+ * merchantability or fitness for any particular purpose or warranties against
+ * infringement of any proprietary rights of a third party.
+ *
+ * Silicon Laboratories, Inc. will not be liable for any consequential,
+ * incidental, or special damages, or any other relief, or for any claim by
+ * any third party, arising from your use of this Software.
+ *
+ *****************************************************************************/
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFM32PG1B_MSC
+ * @{
+ * @brief EFM32PG1B_MSC Register Declaration
+ *****************************************************************************/
+typedef struct
+{
+  __IO uint32_t CTRL;         /**< Memory System Control Register  */
+  __IO uint32_t READCTRL;     /**< Read Control Register  */
+  __IO uint32_t WRITECTRL;    /**< Write Control Register  */
+  __IO uint32_t WRITECMD;     /**< Write Command Register  */
+  __IO uint32_t ADDRB;        /**< Page Erase/Write Address Buffer  */
+  uint32_t      RESERVED0[1]; /**< Reserved for future use **/
+  __IO uint32_t WDATA;        /**< Write Data Register  */
+  __I uint32_t  STATUS;       /**< Status Register  */
+
+  uint32_t      RESERVED1[4]; /**< Reserved for future use **/
+  __I uint32_t  IF;           /**< Interrupt Flag Register  */
+  __IO uint32_t IFS;          /**< Interrupt Flag Set Register  */
+  __IO uint32_t IFC;          /**< Interrupt Flag Clear Register  */
+  __IO uint32_t IEN;          /**< Interrupt Enable Register  */
+  __IO uint32_t LOCK;         /**< Configuration Lock Register  */
+  __IO uint32_t CACHECMD;     /**< Flash Cache Command Register  */
+  __I uint32_t  CACHEHITS;    /**< Cache Hits Performance Counter  */
+  __I uint32_t  CACHEMISSES;  /**< Cache Misses Performance Counter  */
+
+  uint32_t      RESERVED2[1]; /**< Reserved for future use **/
+  __IO uint32_t MASSLOCK;     /**< Mass Erase Lock Register  */
+  uint32_t      RESERVED3[1]; /**< Reserved for future use **/
+  __IO uint32_t STARTUP;      /**< Startup Control  */
+
+  uint32_t      RESERVED4[5]; /**< Reserved for future use **/
+  __IO uint32_t CMD;          /**< Command Register  */
+} MSC_TypeDef;                /** @} */
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B_MSC_BitFields
+ * @{
+ *****************************************************************************/
+
+/* Bit fields for MSC CTRL */
+#define _MSC_CTRL_RESETVALUE                    0x00000001UL                           /**< Default value for MSC_CTRL */
+#define _MSC_CTRL_MASK                          0x0000000FUL                           /**< Mask for MSC_CTRL */
+#define MSC_CTRL_ADDRFAULTEN                    (0x1UL << 0)                           /**< Invalid Address Bus Fault Response Enable */
+#define _MSC_CTRL_ADDRFAULTEN_SHIFT             0                                      /**< Shift value for MSC_ADDRFAULTEN */
+#define _MSC_CTRL_ADDRFAULTEN_MASK              0x1UL                                  /**< Bit mask for MSC_ADDRFAULTEN */
+#define _MSC_CTRL_ADDRFAULTEN_DEFAULT           0x00000001UL                           /**< Mode DEFAULT for MSC_CTRL */
+#define MSC_CTRL_ADDRFAULTEN_DEFAULT            (_MSC_CTRL_ADDRFAULTEN_DEFAULT << 0)   /**< Shifted mode DEFAULT for MSC_CTRL */
+#define MSC_CTRL_CLKDISFAULTEN                  (0x1UL << 1)                           /**< Clock-disabled Bus Fault Response Enable */
+#define _MSC_CTRL_CLKDISFAULTEN_SHIFT           1                                      /**< Shift value for MSC_CLKDISFAULTEN */
+#define _MSC_CTRL_CLKDISFAULTEN_MASK            0x2UL                                  /**< Bit mask for MSC_CLKDISFAULTEN */
+#define _MSC_CTRL_CLKDISFAULTEN_DEFAULT         0x00000000UL                           /**< Mode DEFAULT for MSC_CTRL */
+#define MSC_CTRL_CLKDISFAULTEN_DEFAULT          (_MSC_CTRL_CLKDISFAULTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CTRL */
+#define MSC_CTRL_PWRUPONDEMAND                  (0x1UL << 2)                           /**< Power Up On Demand During Wake Up */
+#define _MSC_CTRL_PWRUPONDEMAND_SHIFT           2                                      /**< Shift value for MSC_PWRUPONDEMAND */
+#define _MSC_CTRL_PWRUPONDEMAND_MASK            0x4UL                                  /**< Bit mask for MSC_PWRUPONDEMAND */
+#define _MSC_CTRL_PWRUPONDEMAND_DEFAULT         0x00000000UL                           /**< Mode DEFAULT for MSC_CTRL */
+#define MSC_CTRL_PWRUPONDEMAND_DEFAULT          (_MSC_CTRL_PWRUPONDEMAND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CTRL */
+#define MSC_CTRL_IFCREADCLEAR                   (0x1UL << 3)                           /**< IFC Read Clears IF */
+#define _MSC_CTRL_IFCREADCLEAR_SHIFT            3                                      /**< Shift value for MSC_IFCREADCLEAR */
+#define _MSC_CTRL_IFCREADCLEAR_MASK             0x8UL                                  /**< Bit mask for MSC_IFCREADCLEAR */
+#define _MSC_CTRL_IFCREADCLEAR_DEFAULT          0x00000000UL                           /**< Mode DEFAULT for MSC_CTRL */
+#define MSC_CTRL_IFCREADCLEAR_DEFAULT           (_MSC_CTRL_IFCREADCLEAR_DEFAULT << 3)  /**< Shifted mode DEFAULT for MSC_CTRL */
+
+/* Bit fields for MSC READCTRL */
+#define _MSC_READCTRL_RESETVALUE                0x01000100UL                          /**< Default value for MSC_READCTRL */
+#define _MSC_READCTRL_MASK                      0x13000338UL                          /**< Mask for MSC_READCTRL */
+#define MSC_READCTRL_IFCDIS                     (0x1UL << 3)                          /**< Internal Flash Cache Disable */
+#define _MSC_READCTRL_IFCDIS_SHIFT              3                                     /**< Shift value for MSC_IFCDIS */
+#define _MSC_READCTRL_IFCDIS_MASK               0x8UL                                 /**< Bit mask for MSC_IFCDIS */
+#define _MSC_READCTRL_IFCDIS_DEFAULT            0x00000000UL                          /**< Mode DEFAULT for MSC_READCTRL */
+#define MSC_READCTRL_IFCDIS_DEFAULT             (_MSC_READCTRL_IFCDIS_DEFAULT << 3)   /**< Shifted mode DEFAULT for MSC_READCTRL */
+#define MSC_READCTRL_AIDIS                      (0x1UL << 4)                          /**< Automatic Invalidate Disable */
+#define _MSC_READCTRL_AIDIS_SHIFT               4                                     /**< Shift value for MSC_AIDIS */
+#define _MSC_READCTRL_AIDIS_MASK                0x10UL                                /**< Bit mask for MSC_AIDIS */
+#define _MSC_READCTRL_AIDIS_DEFAULT             0x00000000UL                          /**< Mode DEFAULT for MSC_READCTRL */
+#define MSC_READCTRL_AIDIS_DEFAULT              (_MSC_READCTRL_AIDIS_DEFAULT << 4)    /**< Shifted mode DEFAULT for MSC_READCTRL */
+#define MSC_READCTRL_ICCDIS                     (0x1UL << 5)                          /**< Interrupt Context Cache Disable */
+#define _MSC_READCTRL_ICCDIS_SHIFT              5                                     /**< Shift value for MSC_ICCDIS */
+#define _MSC_READCTRL_ICCDIS_MASK               0x20UL                                /**< Bit mask for MSC_ICCDIS */
+#define _MSC_READCTRL_ICCDIS_DEFAULT            0x00000000UL                          /**< Mode DEFAULT for MSC_READCTRL */
+#define MSC_READCTRL_ICCDIS_DEFAULT             (_MSC_READCTRL_ICCDIS_DEFAULT << 5)   /**< Shifted mode DEFAULT for MSC_READCTRL */
+#define MSC_READCTRL_PREFETCH                   (0x1UL << 8)                          /**< Prefetch Mode */
+#define _MSC_READCTRL_PREFETCH_SHIFT            8                                     /**< Shift value for MSC_PREFETCH */
+#define _MSC_READCTRL_PREFETCH_MASK             0x100UL                               /**< Bit mask for MSC_PREFETCH */
+#define _MSC_READCTRL_PREFETCH_DEFAULT          0x00000001UL                          /**< Mode DEFAULT for MSC_READCTRL */
+#define MSC_READCTRL_PREFETCH_DEFAULT           (_MSC_READCTRL_PREFETCH_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_READCTRL */
+#define MSC_READCTRL_USEHPROT                   (0x1UL << 9)                          /**< AHB_HPROT Mode */
+#define _MSC_READCTRL_USEHPROT_SHIFT            9                                     /**< Shift value for MSC_USEHPROT */
+#define _MSC_READCTRL_USEHPROT_MASK             0x200UL                               /**< Bit mask for MSC_USEHPROT */
+#define _MSC_READCTRL_USEHPROT_DEFAULT          0x00000000UL                          /**< Mode DEFAULT for MSC_READCTRL */
+#define MSC_READCTRL_USEHPROT_DEFAULT           (_MSC_READCTRL_USEHPROT_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_READCTRL */
+#define _MSC_READCTRL_MODE_SHIFT                24                                    /**< Shift value for MSC_MODE */
+#define _MSC_READCTRL_MODE_MASK                 0x3000000UL                           /**< Bit mask for MSC_MODE */
+#define _MSC_READCTRL_MODE_WS0                  0x00000000UL                          /**< Mode WS0 for MSC_READCTRL */
+#define _MSC_READCTRL_MODE_DEFAULT              0x00000001UL                          /**< Mode DEFAULT for MSC_READCTRL */
+#define _MSC_READCTRL_MODE_WS1                  0x00000001UL                          /**< Mode WS1 for MSC_READCTRL */
+#define MSC_READCTRL_MODE_WS0                   (_MSC_READCTRL_MODE_WS0 << 24)        /**< Shifted mode WS0 for MSC_READCTRL */
+#define MSC_READCTRL_MODE_DEFAULT               (_MSC_READCTRL_MODE_DEFAULT << 24)    /**< Shifted mode DEFAULT for MSC_READCTRL */
+#define MSC_READCTRL_MODE_WS1                   (_MSC_READCTRL_MODE_WS1 << 24)        /**< Shifted mode WS1 for MSC_READCTRL */
+#define MSC_READCTRL_SCBTP                      (0x1UL << 28)                         /**< Suppress Conditional Branch Target Perfetch */
+#define _MSC_READCTRL_SCBTP_SHIFT               28                                    /**< Shift value for MSC_SCBTP */
+#define _MSC_READCTRL_SCBTP_MASK                0x10000000UL                          /**< Bit mask for MSC_SCBTP */
+#define _MSC_READCTRL_SCBTP_DEFAULT             0x00000000UL                          /**< Mode DEFAULT for MSC_READCTRL */
+#define MSC_READCTRL_SCBTP_DEFAULT              (_MSC_READCTRL_SCBTP_DEFAULT << 28)   /**< Shifted mode DEFAULT for MSC_READCTRL */
+
+/* Bit fields for MSC WRITECTRL */
+#define _MSC_WRITECTRL_RESETVALUE               0x00000000UL                                /**< Default value for MSC_WRITECTRL */
+#define _MSC_WRITECTRL_MASK                     0x00000003UL                                /**< Mask for MSC_WRITECTRL */
+#define MSC_WRITECTRL_WREN                      (0x1UL << 0)                                /**< Enable Write/Erase Controller  */
+#define _MSC_WRITECTRL_WREN_SHIFT               0                                           /**< Shift value for MSC_WREN */
+#define _MSC_WRITECTRL_WREN_MASK                0x1UL                                       /**< Bit mask for MSC_WREN */
+#define _MSC_WRITECTRL_WREN_DEFAULT             0x00000000UL                                /**< Mode DEFAULT for MSC_WRITECTRL */
+#define MSC_WRITECTRL_WREN_DEFAULT              (_MSC_WRITECTRL_WREN_DEFAULT << 0)          /**< Shifted mode DEFAULT for MSC_WRITECTRL */
+#define MSC_WRITECTRL_IRQERASEABORT             (0x1UL << 1)                                /**< Abort Page Erase on Interrupt */
+#define _MSC_WRITECTRL_IRQERASEABORT_SHIFT      1                                           /**< Shift value for MSC_IRQERASEABORT */
+#define _MSC_WRITECTRL_IRQERASEABORT_MASK       0x2UL                                       /**< Bit mask for MSC_IRQERASEABORT */
+#define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT    0x00000000UL                                /**< Mode DEFAULT for MSC_WRITECTRL */
+#define MSC_WRITECTRL_IRQERASEABORT_DEFAULT     (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECTRL */
+
+/* Bit fields for MSC WRITECMD */
+#define _MSC_WRITECMD_RESETVALUE                0x00000000UL                             /**< Default value for MSC_WRITECMD */
+#define _MSC_WRITECMD_MASK                      0x0000113FUL                             /**< Mask for MSC_WRITECMD */
+#define MSC_WRITECMD_LADDRIM                    (0x1UL << 0)                             /**< Load MSC_ADDRB into ADDR */
+#define _MSC_WRITECMD_LADDRIM_SHIFT             0                                        /**< Shift value for MSC_LADDRIM */
+#define _MSC_WRITECMD_LADDRIM_MASK              0x1UL                                    /**< Bit mask for MSC_LADDRIM */
+#define _MSC_WRITECMD_LADDRIM_DEFAULT           0x00000000UL                             /**< Mode DEFAULT for MSC_WRITECMD */
+#define MSC_WRITECMD_LADDRIM_DEFAULT            (_MSC_WRITECMD_LADDRIM_DEFAULT << 0)     /**< Shifted mode DEFAULT for MSC_WRITECMD */
+#define MSC_WRITECMD_ERASEPAGE                  (0x1UL << 1)                             /**< Erase Page */
+#define _MSC_WRITECMD_ERASEPAGE_SHIFT           1                                        /**< Shift value for MSC_ERASEPAGE */
+#define _MSC_WRITECMD_ERASEPAGE_MASK            0x2UL                                    /**< Bit mask for MSC_ERASEPAGE */
+#define _MSC_WRITECMD_ERASEPAGE_DEFAULT         0x00000000UL                             /**< Mode DEFAULT for MSC_WRITECMD */
+#define MSC_WRITECMD_ERASEPAGE_DEFAULT          (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1)   /**< Shifted mode DEFAULT for MSC_WRITECMD */
+#define MSC_WRITECMD_WRITEEND                   (0x1UL << 2)                             /**< End Write Mode */
+#define _MSC_WRITECMD_WRITEEND_SHIFT            2                                        /**< Shift value for MSC_WRITEEND */
+#define _MSC_WRITECMD_WRITEEND_MASK             0x4UL                                    /**< Bit mask for MSC_WRITEEND */
+#define _MSC_WRITECMD_WRITEEND_DEFAULT          0x00000000UL                             /**< Mode DEFAULT for MSC_WRITECMD */
+#define MSC_WRITECMD_WRITEEND_DEFAULT           (_MSC_WRITECMD_WRITEEND_DEFAULT << 2)    /**< Shifted mode DEFAULT for MSC_WRITECMD */
+#define MSC_WRITECMD_WRITEONCE                  (0x1UL << 3)                             /**< Word Write-Once Trigger */
+#define _MSC_WRITECMD_WRITEONCE_SHIFT           3                                        /**< Shift value for MSC_WRITEONCE */
+#define _MSC_WRITECMD_WRITEONCE_MASK            0x8UL                                    /**< Bit mask for MSC_WRITEONCE */
+#define _MSC_WRITECMD_WRITEONCE_DEFAULT         0x00000000UL                             /**< Mode DEFAULT for MSC_WRITECMD */
+#define MSC_WRITECMD_WRITEONCE_DEFAULT          (_MSC_WRITECMD_WRITEONCE_DEFAULT << 3)   /**< Shifted mode DEFAULT for MSC_WRITECMD */
+#define MSC_WRITECMD_WRITETRIG                  (0x1UL << 4)                             /**< Word Write Sequence Trigger */
+#define _MSC_WRITECMD_WRITETRIG_SHIFT           4                                        /**< Shift value for MSC_WRITETRIG */
+#define _MSC_WRITECMD_WRITETRIG_MASK            0x10UL                                   /**< Bit mask for MSC_WRITETRIG */
+#define _MSC_WRITECMD_WRITETRIG_DEFAULT         0x00000000UL                             /**< Mode DEFAULT for MSC_WRITECMD */
+#define MSC_WRITECMD_WRITETRIG_DEFAULT          (_MSC_WRITECMD_WRITETRIG_DEFAULT << 4)   /**< Shifted mode DEFAULT for MSC_WRITECMD */
+#define MSC_WRITECMD_ERASEABORT                 (0x1UL << 5)                             /**< Abort erase sequence */
+#define _MSC_WRITECMD_ERASEABORT_SHIFT          5                                        /**< Shift value for MSC_ERASEABORT */
+#define _MSC_WRITECMD_ERASEABORT_MASK           0x20UL                                   /**< Bit mask for MSC_ERASEABORT */
+#define _MSC_WRITECMD_ERASEABORT_DEFAULT        0x00000000UL                             /**< Mode DEFAULT for MSC_WRITECMD */
+#define MSC_WRITECMD_ERASEABORT_DEFAULT         (_MSC_WRITECMD_ERASEABORT_DEFAULT << 5)  /**< Shifted mode DEFAULT for MSC_WRITECMD */
+#define MSC_WRITECMD_ERASEMAIN0                 (0x1UL << 8)                             /**< Mass erase region 0 */
+#define _MSC_WRITECMD_ERASEMAIN0_SHIFT          8                                        /**< Shift value for MSC_ERASEMAIN0 */
+#define _MSC_WRITECMD_ERASEMAIN0_MASK           0x100UL                                  /**< Bit mask for MSC_ERASEMAIN0 */
+#define _MSC_WRITECMD_ERASEMAIN0_DEFAULT        0x00000000UL                             /**< Mode DEFAULT for MSC_WRITECMD */
+#define MSC_WRITECMD_ERASEMAIN0_DEFAULT         (_MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8)  /**< Shifted mode DEFAULT for MSC_WRITECMD */
+#define MSC_WRITECMD_CLEARWDATA                 (0x1UL << 12)                            /**< Clear WDATA state */
+#define _MSC_WRITECMD_CLEARWDATA_SHIFT          12                                       /**< Shift value for MSC_CLEARWDATA */
+#define _MSC_WRITECMD_CLEARWDATA_MASK           0x1000UL                                 /**< Bit mask for MSC_CLEARWDATA */
+#define _MSC_WRITECMD_CLEARWDATA_DEFAULT        0x00000000UL                             /**< Mode DEFAULT for MSC_WRITECMD */
+#define MSC_WRITECMD_CLEARWDATA_DEFAULT         (_MSC_WRITECMD_CLEARWDATA_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_WRITECMD */
+
+/* Bit fields for MSC ADDRB */
+#define _MSC_ADDRB_RESETVALUE                   0x00000000UL                    /**< Default value for MSC_ADDRB */
+#define _MSC_ADDRB_MASK                         0xFFFFFFFFUL                    /**< Mask for MSC_ADDRB */
+#define _MSC_ADDRB_ADDRB_SHIFT                  0                               /**< Shift value for MSC_ADDRB */
+#define _MSC_ADDRB_ADDRB_MASK                   0xFFFFFFFFUL                    /**< Bit mask for MSC_ADDRB */
+#define _MSC_ADDRB_ADDRB_DEFAULT                0x00000000UL                    /**< Mode DEFAULT for MSC_ADDRB */
+#define MSC_ADDRB_ADDRB_DEFAULT                 (_MSC_ADDRB_ADDRB_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ADDRB */
+
+/* Bit fields for MSC WDATA */
+#define _MSC_WDATA_RESETVALUE                   0x00000000UL                    /**< Default value for MSC_WDATA */
+#define _MSC_WDATA_MASK                         0xFFFFFFFFUL                    /**< Mask for MSC_WDATA */
+#define _MSC_WDATA_WDATA_SHIFT                  0                               /**< Shift value for MSC_WDATA */
+#define _MSC_WDATA_WDATA_MASK                   0xFFFFFFFFUL                    /**< Bit mask for MSC_WDATA */
+#define _MSC_WDATA_WDATA_DEFAULT                0x00000000UL                    /**< Mode DEFAULT for MSC_WDATA */
+#define MSC_WDATA_WDATA_DEFAULT                 (_MSC_WDATA_WDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WDATA */
+
+/* Bit fields for MSC STATUS */
+#define _MSC_STATUS_RESETVALUE                  0x00000008UL                            /**< Default value for MSC_STATUS */
+#define _MSC_STATUS_MASK                        0x0000007FUL                            /**< Mask for MSC_STATUS */
+#define MSC_STATUS_BUSY                         (0x1UL << 0)                            /**< Erase/Write Busy */
+#define _MSC_STATUS_BUSY_SHIFT                  0                                       /**< Shift value for MSC_BUSY */
+#define _MSC_STATUS_BUSY_MASK                   0x1UL                                   /**< Bit mask for MSC_BUSY */
+#define _MSC_STATUS_BUSY_DEFAULT                0x00000000UL                            /**< Mode DEFAULT for MSC_STATUS */
+#define MSC_STATUS_BUSY_DEFAULT                 (_MSC_STATUS_BUSY_DEFAULT << 0)         /**< Shifted mode DEFAULT for MSC_STATUS */
+#define MSC_STATUS_LOCKED                       (0x1UL << 1)                            /**< Access Locked */
+#define _MSC_STATUS_LOCKED_SHIFT                1                                       /**< Shift value for MSC_LOCKED */
+#define _MSC_STATUS_LOCKED_MASK                 0x2UL                                   /**< Bit mask for MSC_LOCKED */
+#define _MSC_STATUS_LOCKED_DEFAULT              0x00000000UL                            /**< Mode DEFAULT for MSC_STATUS */
+#define MSC_STATUS_LOCKED_DEFAULT               (_MSC_STATUS_LOCKED_DEFAULT << 1)       /**< Shifted mode DEFAULT for MSC_STATUS */
+#define MSC_STATUS_INVADDR                      (0x1UL << 2)                            /**< Invalid Write Address or Erase Page */
+#define _MSC_STATUS_INVADDR_SHIFT               2                                       /**< Shift value for MSC_INVADDR */
+#define _MSC_STATUS_INVADDR_MASK                0x4UL                                   /**< Bit mask for MSC_INVADDR */
+#define _MSC_STATUS_INVADDR_DEFAULT             0x00000000UL                            /**< Mode DEFAULT for MSC_STATUS */
+#define MSC_STATUS_INVADDR_DEFAULT              (_MSC_STATUS_INVADDR_DEFAULT << 2)      /**< Shifted mode DEFAULT for MSC_STATUS */
+#define MSC_STATUS_WDATAREADY                   (0x1UL << 3)                            /**< WDATA Write Ready */
+#define _MSC_STATUS_WDATAREADY_SHIFT            3                                       /**< Shift value for MSC_WDATAREADY */
+#define _MSC_STATUS_WDATAREADY_MASK             0x8UL                                   /**< Bit mask for MSC_WDATAREADY */
+#define _MSC_STATUS_WDATAREADY_DEFAULT          0x00000001UL                            /**< Mode DEFAULT for MSC_STATUS */
+#define MSC_STATUS_WDATAREADY_DEFAULT           (_MSC_STATUS_WDATAREADY_DEFAULT << 3)   /**< Shifted mode DEFAULT for MSC_STATUS */
+#define MSC_STATUS_WORDTIMEOUT                  (0x1UL << 4)                            /**< Flash Write Word Timeout */
+#define _MSC_STATUS_WORDTIMEOUT_SHIFT           4                                       /**< Shift value for MSC_WORDTIMEOUT */
+#define _MSC_STATUS_WORDTIMEOUT_MASK            0x10UL                                  /**< Bit mask for MSC_WORDTIMEOUT */
+#define _MSC_STATUS_WORDTIMEOUT_DEFAULT         0x00000000UL                            /**< Mode DEFAULT for MSC_STATUS */
+#define MSC_STATUS_WORDTIMEOUT_DEFAULT          (_MSC_STATUS_WORDTIMEOUT_DEFAULT << 4)  /**< Shifted mode DEFAULT for MSC_STATUS */
+#define MSC_STATUS_ERASEABORTED                 (0x1UL << 5)                            /**< The Current Flash Erase Operation Aborted */
+#define _MSC_STATUS_ERASEABORTED_SHIFT          5                                       /**< Shift value for MSC_ERASEABORTED */
+#define _MSC_STATUS_ERASEABORTED_MASK           0x20UL                                  /**< Bit mask for MSC_ERASEABORTED */
+#define _MSC_STATUS_ERASEABORTED_DEFAULT        0x00000000UL                            /**< Mode DEFAULT for MSC_STATUS */
+#define MSC_STATUS_ERASEABORTED_DEFAULT         (_MSC_STATUS_ERASEABORTED_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_STATUS */
+#define MSC_STATUS_PCRUNNING                    (0x1UL << 6)                            /**< Performance Counters Running */
+#define _MSC_STATUS_PCRUNNING_SHIFT             6                                       /**< Shift value for MSC_PCRUNNING */
+#define _MSC_STATUS_PCRUNNING_MASK              0x40UL                                  /**< Bit mask for MSC_PCRUNNING */
+#define _MSC_STATUS_PCRUNNING_DEFAULT           0x00000000UL                            /**< Mode DEFAULT for MSC_STATUS */
+#define MSC_STATUS_PCRUNNING_DEFAULT            (_MSC_STATUS_PCRUNNING_DEFAULT << 6)    /**< Shifted mode DEFAULT for MSC_STATUS */
+
+/* Bit fields for MSC IF */
+#define _MSC_IF_RESETVALUE                      0x00000000UL                    /**< Default value for MSC_IF */
+#define _MSC_IF_MASK                            0x0000003FUL                    /**< Mask for MSC_IF */
+#define MSC_IF_ERASE                            (0x1UL << 0)                    /**< Erase Done Interrupt Read Flag */
+#define _MSC_IF_ERASE_SHIFT                     0                               /**< Shift value for MSC_ERASE */
+#define _MSC_IF_ERASE_MASK                      0x1UL                           /**< Bit mask for MSC_ERASE */
+#define _MSC_IF_ERASE_DEFAULT                   0x00000000UL                    /**< Mode DEFAULT for MSC_IF */
+#define MSC_IF_ERASE_DEFAULT                    (_MSC_IF_ERASE_DEFAULT << 0)    /**< Shifted mode DEFAULT for MSC_IF */
+#define MSC_IF_WRITE                            (0x1UL << 1)                    /**< Write Done Interrupt Read Flag */
+#define _MSC_IF_WRITE_SHIFT                     1                               /**< Shift value for MSC_WRITE */
+#define _MSC_IF_WRITE_MASK                      0x2UL                           /**< Bit mask for MSC_WRITE */
+#define _MSC_IF_WRITE_DEFAULT                   0x00000000UL                    /**< Mode DEFAULT for MSC_IF */
+#define MSC_IF_WRITE_DEFAULT                    (_MSC_IF_WRITE_DEFAULT << 1)    /**< Shifted mode DEFAULT for MSC_IF */
+#define MSC_IF_CHOF                             (0x1UL << 2)                    /**< Cache Hits Overflow Interrupt Flag */
+#define _MSC_IF_CHOF_SHIFT                      2                               /**< Shift value for MSC_CHOF */
+#define _MSC_IF_CHOF_MASK                       0x4UL                           /**< Bit mask for MSC_CHOF */
+#define _MSC_IF_CHOF_DEFAULT                    0x00000000UL                    /**< Mode DEFAULT for MSC_IF */
+#define MSC_IF_CHOF_DEFAULT                     (_MSC_IF_CHOF_DEFAULT << 2)     /**< Shifted mode DEFAULT for MSC_IF */
+#define MSC_IF_CMOF                             (0x1UL << 3)                    /**< Cache Misses Overflow Interrupt Flag */
+#define _MSC_IF_CMOF_SHIFT                      3                               /**< Shift value for MSC_CMOF */
+#define _MSC_IF_CMOF_MASK                       0x8UL                           /**< Bit mask for MSC_CMOF */
+#define _MSC_IF_CMOF_DEFAULT                    0x00000000UL                    /**< Mode DEFAULT for MSC_IF */
+#define MSC_IF_CMOF_DEFAULT                     (_MSC_IF_CMOF_DEFAULT << 3)     /**< Shifted mode DEFAULT for MSC_IF */
+#define MSC_IF_PWRUPF                           (0x1UL << 4)                    /**< Flash Power Up Sequence Complete Flag */
+#define _MSC_IF_PWRUPF_SHIFT                    4                               /**< Shift value for MSC_PWRUPF */
+#define _MSC_IF_PWRUPF_MASK                     0x10UL                          /**< Bit mask for MSC_PWRUPF */
+#define _MSC_IF_PWRUPF_DEFAULT                  0x00000000UL                    /**< Mode DEFAULT for MSC_IF */
+#define MSC_IF_PWRUPF_DEFAULT                   (_MSC_IF_PWRUPF_DEFAULT << 4)   /**< Shifted mode DEFAULT for MSC_IF */
+#define MSC_IF_ICACHERR                         (0x1UL << 5)                    /**< iCache RAM Parity Error Flag */
+#define _MSC_IF_ICACHERR_SHIFT                  5                               /**< Shift value for MSC_ICACHERR */
+#define _MSC_IF_ICACHERR_MASK                   0x20UL                          /**< Bit mask for MSC_ICACHERR */
+#define _MSC_IF_ICACHERR_DEFAULT                0x00000000UL                    /**< Mode DEFAULT for MSC_IF */
+#define MSC_IF_ICACHERR_DEFAULT                 (_MSC_IF_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IF */
+
+/* Bit fields for MSC IFS */
+#define _MSC_IFS_RESETVALUE                     0x00000000UL                     /**< Default value for MSC_IFS */
+#define _MSC_IFS_MASK                           0x0000003FUL                     /**< Mask for MSC_IFS */
+#define MSC_IFS_ERASE                           (0x1UL << 0)                     /**< Set ERASE Interrupt Flag */
+#define _MSC_IFS_ERASE_SHIFT                    0                                /**< Shift value for MSC_ERASE */
+#define _MSC_IFS_ERASE_MASK                     0x1UL                            /**< Bit mask for MSC_ERASE */
+#define _MSC_IFS_ERASE_DEFAULT                  0x00000000UL                     /**< Mode DEFAULT for MSC_IFS */
+#define MSC_IFS_ERASE_DEFAULT                   (_MSC_IFS_ERASE_DEFAULT << 0)    /**< Shifted mode DEFAULT for MSC_IFS */
+#define MSC_IFS_WRITE                           (0x1UL << 1)                     /**< Set WRITE Interrupt Flag */
+#define _MSC_IFS_WRITE_SHIFT                    1                                /**< Shift value for MSC_WRITE */
+#define _MSC_IFS_WRITE_MASK                     0x2UL                            /**< Bit mask for MSC_WRITE */
+#define _MSC_IFS_WRITE_DEFAULT                  0x00000000UL                     /**< Mode DEFAULT for MSC_IFS */
+#define MSC_IFS_WRITE_DEFAULT                   (_MSC_IFS_WRITE_DEFAULT << 1)    /**< Shifted mode DEFAULT for MSC_IFS */
+#define MSC_IFS_CHOF                            (0x1UL << 2)                     /**< Set CHOF Interrupt Flag */
+#define _MSC_IFS_CHOF_SHIFT                     2                                /**< Shift value for MSC_CHOF */
+#define _MSC_IFS_CHOF_MASK                      0x4UL                            /**< Bit mask for MSC_CHOF */
+#define _MSC_IFS_CHOF_DEFAULT                   0x00000000UL                     /**< Mode DEFAULT for MSC_IFS */
+#define MSC_IFS_CHOF_DEFAULT                    (_MSC_IFS_CHOF_DEFAULT << 2)     /**< Shifted mode DEFAULT for MSC_IFS */
+#define MSC_IFS_CMOF                            (0x1UL << 3)                     /**< Set CMOF Interrupt Flag */
+#define _MSC_IFS_CMOF_SHIFT                     3                                /**< Shift value for MSC_CMOF */
+#define _MSC_IFS_CMOF_MASK                      0x8UL                            /**< Bit mask for MSC_CMOF */
+#define _MSC_IFS_CMOF_DEFAULT                   0x00000000UL                     /**< Mode DEFAULT for MSC_IFS */
+#define MSC_IFS_CMOF_DEFAULT                    (_MSC_IFS_CMOF_DEFAULT << 3)     /**< Shifted mode DEFAULT for MSC_IFS */
+#define MSC_IFS_PWRUPF                          (0x1UL << 4)                     /**< Set PWRUPF Interrupt Flag */
+#define _MSC_IFS_PWRUPF_SHIFT                   4                                /**< Shift value for MSC_PWRUPF */
+#define _MSC_IFS_PWRUPF_MASK                    0x10UL                           /**< Bit mask for MSC_PWRUPF */
+#define _MSC_IFS_PWRUPF_DEFAULT                 0x00000000UL                     /**< Mode DEFAULT for MSC_IFS */
+#define MSC_IFS_PWRUPF_DEFAULT                  (_MSC_IFS_PWRUPF_DEFAULT << 4)   /**< Shifted mode DEFAULT for MSC_IFS */
+#define MSC_IFS_ICACHERR                        (0x1UL << 5)                     /**< Set ICACHERR Interrupt Flag */
+#define _MSC_IFS_ICACHERR_SHIFT                 5                                /**< Shift value for MSC_ICACHERR */
+#define _MSC_IFS_ICACHERR_MASK                  0x20UL                           /**< Bit mask for MSC_ICACHERR */
+#define _MSC_IFS_ICACHERR_DEFAULT               0x00000000UL                     /**< Mode DEFAULT for MSC_IFS */
+#define MSC_IFS_ICACHERR_DEFAULT                (_MSC_IFS_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFS */
+
+/* Bit fields for MSC IFC */
+#define _MSC_IFC_RESETVALUE                     0x00000000UL                     /**< Default value for MSC_IFC */
+#define _MSC_IFC_MASK                           0x0000003FUL                     /**< Mask for MSC_IFC */
+#define MSC_IFC_ERASE                           (0x1UL << 0)                     /**< Clear ERASE Interrupt Flag */
+#define _MSC_IFC_ERASE_SHIFT                    0                                /**< Shift value for MSC_ERASE */
+#define _MSC_IFC_ERASE_MASK                     0x1UL                            /**< Bit mask for MSC_ERASE */
+#define _MSC_IFC_ERASE_DEFAULT                  0x00000000UL                     /**< Mode DEFAULT for MSC_IFC */
+#define MSC_IFC_ERASE_DEFAULT                   (_MSC_IFC_ERASE_DEFAULT << 0)    /**< Shifted mode DEFAULT for MSC_IFC */
+#define MSC_IFC_WRITE                           (0x1UL << 1)                     /**< Clear WRITE Interrupt Flag */
+#define _MSC_IFC_WRITE_SHIFT                    1                                /**< Shift value for MSC_WRITE */
+#define _MSC_IFC_WRITE_MASK                     0x2UL                            /**< Bit mask for MSC_WRITE */
+#define _MSC_IFC_WRITE_DEFAULT                  0x00000000UL                     /**< Mode DEFAULT for MSC_IFC */
+#define MSC_IFC_WRITE_DEFAULT                   (_MSC_IFC_WRITE_DEFAULT << 1)    /**< Shifted mode DEFAULT for MSC_IFC */
+#define MSC_IFC_CHOF                            (0x1UL << 2)                     /**< Clear CHOF Interrupt Flag */
+#define _MSC_IFC_CHOF_SHIFT                     2                                /**< Shift value for MSC_CHOF */
+#define _MSC_IFC_CHOF_MASK                      0x4UL                            /**< Bit mask for MSC_CHOF */
+#define _MSC_IFC_CHOF_DEFAULT                   0x00000000UL                     /**< Mode DEFAULT for MSC_IFC */
+#define MSC_IFC_CHOF_DEFAULT                    (_MSC_IFC_CHOF_DEFAULT << 2)     /**< Shifted mode DEFAULT for MSC_IFC */
+#define MSC_IFC_CMOF                            (0x1UL << 3)                     /**< Clear CMOF Interrupt Flag */
+#define _MSC_IFC_CMOF_SHIFT                     3                                /**< Shift value for MSC_CMOF */
+#define _MSC_IFC_CMOF_MASK                      0x8UL                            /**< Bit mask for MSC_CMOF */
+#define _MSC_IFC_CMOF_DEFAULT                   0x00000000UL                     /**< Mode DEFAULT for MSC_IFC */
+#define MSC_IFC_CMOF_DEFAULT                    (_MSC_IFC_CMOF_DEFAULT << 3)     /**< Shifted mode DEFAULT for MSC_IFC */
+#define MSC_IFC_PWRUPF                          (0x1UL << 4)                     /**< Clear PWRUPF Interrupt Flag */
+#define _MSC_IFC_PWRUPF_SHIFT                   4                                /**< Shift value for MSC_PWRUPF */
+#define _MSC_IFC_PWRUPF_MASK                    0x10UL                           /**< Bit mask for MSC_PWRUPF */
+#define _MSC_IFC_PWRUPF_DEFAULT                 0x00000000UL                     /**< Mode DEFAULT for MSC_IFC */
+#define MSC_IFC_PWRUPF_DEFAULT                  (_MSC_IFC_PWRUPF_DEFAULT << 4)   /**< Shifted mode DEFAULT for MSC_IFC */
+#define MSC_IFC_ICACHERR                        (0x1UL << 5)                     /**< Clear ICACHERR Interrupt Flag */
+#define _MSC_IFC_ICACHERR_SHIFT                 5                                /**< Shift value for MSC_ICACHERR */
+#define _MSC_IFC_ICACHERR_MASK                  0x20UL                           /**< Bit mask for MSC_ICACHERR */
+#define _MSC_IFC_ICACHERR_DEFAULT               0x00000000UL                     /**< Mode DEFAULT for MSC_IFC */
+#define MSC_IFC_ICACHERR_DEFAULT                (_MSC_IFC_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFC */
+
+/* Bit fields for MSC IEN */
+#define _MSC_IEN_RESETVALUE                     0x00000000UL                     /**< Default value for MSC_IEN */
+#define _MSC_IEN_MASK                           0x0000003FUL                     /**< Mask for MSC_IEN */
+#define MSC_IEN_ERASE                           (0x1UL << 0)                     /**< ERASE Interrupt Enable */
+#define _MSC_IEN_ERASE_SHIFT                    0                                /**< Shift value for MSC_ERASE */
+#define _MSC_IEN_ERASE_MASK                     0x1UL                            /**< Bit mask for MSC_ERASE */
+#define _MSC_IEN_ERASE_DEFAULT                  0x00000000UL                     /**< Mode DEFAULT for MSC_IEN */
+#define MSC_IEN_ERASE_DEFAULT                   (_MSC_IEN_ERASE_DEFAULT << 0)    /**< Shifted mode DEFAULT for MSC_IEN */
+#define MSC_IEN_WRITE                           (0x1UL << 1)                     /**< WRITE Interrupt Enable */
+#define _MSC_IEN_WRITE_SHIFT                    1                                /**< Shift value for MSC_WRITE */
+#define _MSC_IEN_WRITE_MASK                     0x2UL                            /**< Bit mask for MSC_WRITE */
+#define _MSC_IEN_WRITE_DEFAULT                  0x00000000UL                     /**< Mode DEFAULT for MSC_IEN */
+#define MSC_IEN_WRITE_DEFAULT                   (_MSC_IEN_WRITE_DEFAULT << 1)    /**< Shifted mode DEFAULT for MSC_IEN */
+#define MSC_IEN_CHOF                            (0x1UL << 2)                     /**< CHOF Interrupt Enable */
+#define _MSC_IEN_CHOF_SHIFT                     2                                /**< Shift value for MSC_CHOF */
+#define _MSC_IEN_CHOF_MASK                      0x4UL                            /**< Bit mask for MSC_CHOF */
+#define _MSC_IEN_CHOF_DEFAULT                   0x00000000UL                     /**< Mode DEFAULT for MSC_IEN */
+#define MSC_IEN_CHOF_DEFAULT                    (_MSC_IEN_CHOF_DEFAULT << 2)     /**< Shifted mode DEFAULT for MSC_IEN */
+#define MSC_IEN_CMOF                            (0x1UL << 3)                     /**< CMOF Interrupt Enable */
+#define _MSC_IEN_CMOF_SHIFT                     3                                /**< Shift value for MSC_CMOF */
+#define _MSC_IEN_CMOF_MASK                      0x8UL                            /**< Bit mask for MSC_CMOF */
+#define _MSC_IEN_CMOF_DEFAULT                   0x00000000UL                     /**< Mode DEFAULT for MSC_IEN */
+#define MSC_IEN_CMOF_DEFAULT                    (_MSC_IEN_CMOF_DEFAULT << 3)     /**< Shifted mode DEFAULT for MSC_IEN */
+#define MSC_IEN_PWRUPF                          (0x1UL << 4)                     /**< PWRUPF Interrupt Enable */
+#define _MSC_IEN_PWRUPF_SHIFT                   4                                /**< Shift value for MSC_PWRUPF */
+#define _MSC_IEN_PWRUPF_MASK                    0x10UL                           /**< Bit mask for MSC_PWRUPF */
+#define _MSC_IEN_PWRUPF_DEFAULT                 0x00000000UL                     /**< Mode DEFAULT for MSC_IEN */
+#define MSC_IEN_PWRUPF_DEFAULT                  (_MSC_IEN_PWRUPF_DEFAULT << 4)   /**< Shifted mode DEFAULT for MSC_IEN */
+#define MSC_IEN_ICACHERR                        (0x1UL << 5)                     /**< ICACHERR Interrupt Enable */
+#define _MSC_IEN_ICACHERR_SHIFT                 5                                /**< Shift value for MSC_ICACHERR */
+#define _MSC_IEN_ICACHERR_MASK                  0x20UL                           /**< Bit mask for MSC_ICACHERR */
+#define _MSC_IEN_ICACHERR_DEFAULT               0x00000000UL                     /**< Mode DEFAULT for MSC_IEN */
+#define MSC_IEN_ICACHERR_DEFAULT                (_MSC_IEN_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IEN */
+
+/* Bit fields for MSC LOCK */
+#define _MSC_LOCK_RESETVALUE                    0x00000000UL                      /**< Default value for MSC_LOCK */
+#define _MSC_LOCK_MASK                          0x0000FFFFUL                      /**< Mask for MSC_LOCK */
+#define _MSC_LOCK_LOCKKEY_SHIFT                 0                                 /**< Shift value for MSC_LOCKKEY */
+#define _MSC_LOCK_LOCKKEY_MASK                  0xFFFFUL                          /**< Bit mask for MSC_LOCKKEY */
+#define _MSC_LOCK_LOCKKEY_DEFAULT               0x00000000UL                      /**< Mode DEFAULT for MSC_LOCK */
+#define _MSC_LOCK_LOCKKEY_LOCK                  0x00000000UL                      /**< Mode LOCK for MSC_LOCK */
+#define _MSC_LOCK_LOCKKEY_UNLOCKED              0x00000000UL                      /**< Mode UNLOCKED for MSC_LOCK */
+#define _MSC_LOCK_LOCKKEY_LOCKED                0x00000001UL                      /**< Mode LOCKED for MSC_LOCK */
+#define _MSC_LOCK_LOCKKEY_UNLOCK                0x00001B71UL                      /**< Mode UNLOCK for MSC_LOCK */
+#define MSC_LOCK_LOCKKEY_DEFAULT                (_MSC_LOCK_LOCKKEY_DEFAULT << 0)  /**< Shifted mode DEFAULT for MSC_LOCK */
+#define MSC_LOCK_LOCKKEY_LOCK                   (_MSC_LOCK_LOCKKEY_LOCK << 0)     /**< Shifted mode LOCK for MSC_LOCK */
+#define MSC_LOCK_LOCKKEY_UNLOCKED               (_MSC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_LOCK */
+#define MSC_LOCK_LOCKKEY_LOCKED                 (_MSC_LOCK_LOCKKEY_LOCKED << 0)   /**< Shifted mode LOCKED for MSC_LOCK */
+#define MSC_LOCK_LOCKKEY_UNLOCK                 (_MSC_LOCK_LOCKKEY_UNLOCK << 0)   /**< Shifted mode UNLOCK for MSC_LOCK */
+
+/* Bit fields for MSC CACHECMD */
+#define _MSC_CACHECMD_RESETVALUE                0x00000000UL                          /**< Default value for MSC_CACHECMD */
+#define _MSC_CACHECMD_MASK                      0x00000007UL                          /**< Mask for MSC_CACHECMD */
+#define MSC_CACHECMD_INVCACHE                   (0x1UL << 0)                          /**< Invalidate Instruction Cache */
+#define _MSC_CACHECMD_INVCACHE_SHIFT            0                                     /**< Shift value for MSC_INVCACHE */
+#define _MSC_CACHECMD_INVCACHE_MASK             0x1UL                                 /**< Bit mask for MSC_INVCACHE */
+#define _MSC_CACHECMD_INVCACHE_DEFAULT          0x00000000UL                          /**< Mode DEFAULT for MSC_CACHECMD */
+#define MSC_CACHECMD_INVCACHE_DEFAULT           (_MSC_CACHECMD_INVCACHE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECMD */
+#define MSC_CACHECMD_STARTPC                    (0x1UL << 1)                          /**< Start Performance Counters */
+#define _MSC_CACHECMD_STARTPC_SHIFT             1                                     /**< Shift value for MSC_STARTPC */
+#define _MSC_CACHECMD_STARTPC_MASK              0x2UL                                 /**< Bit mask for MSC_STARTPC */
+#define _MSC_CACHECMD_STARTPC_DEFAULT           0x00000000UL                          /**< Mode DEFAULT for MSC_CACHECMD */
+#define MSC_CACHECMD_STARTPC_DEFAULT            (_MSC_CACHECMD_STARTPC_DEFAULT << 1)  /**< Shifted mode DEFAULT for MSC_CACHECMD */
+#define MSC_CACHECMD_STOPPC                     (0x1UL << 2)                          /**< Stop Performance Counters */
+#define _MSC_CACHECMD_STOPPC_SHIFT              2                                     /**< Shift value for MSC_STOPPC */
+#define _MSC_CACHECMD_STOPPC_MASK               0x4UL                                 /**< Bit mask for MSC_STOPPC */
+#define _MSC_CACHECMD_STOPPC_DEFAULT            0x00000000UL                          /**< Mode DEFAULT for MSC_CACHECMD */
+#define MSC_CACHECMD_STOPPC_DEFAULT             (_MSC_CACHECMD_STOPPC_DEFAULT << 2)   /**< Shifted mode DEFAULT for MSC_CACHECMD */
+
+/* Bit fields for MSC CACHEHITS */
+#define _MSC_CACHEHITS_RESETVALUE               0x00000000UL                            /**< Default value for MSC_CACHEHITS */
+#define _MSC_CACHEHITS_MASK                     0x000FFFFFUL                            /**< Mask for MSC_CACHEHITS */
+#define _MSC_CACHEHITS_CACHEHITS_SHIFT          0                                       /**< Shift value for MSC_CACHEHITS */
+#define _MSC_CACHEHITS_CACHEHITS_MASK           0xFFFFFUL                               /**< Bit mask for MSC_CACHEHITS */
+#define _MSC_CACHEHITS_CACHEHITS_DEFAULT        0x00000000UL                            /**< Mode DEFAULT for MSC_CACHEHITS */
+#define MSC_CACHEHITS_CACHEHITS_DEFAULT         (_MSC_CACHEHITS_CACHEHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEHITS */
+
+/* Bit fields for MSC CACHEMISSES */
+#define _MSC_CACHEMISSES_RESETVALUE             0x00000000UL                                /**< Default value for MSC_CACHEMISSES */
+#define _MSC_CACHEMISSES_MASK                   0x000FFFFFUL                                /**< Mask for MSC_CACHEMISSES */
+#define _MSC_CACHEMISSES_CACHEMISSES_SHIFT      0                                           /**< Shift value for MSC_CACHEMISSES */
+#define _MSC_CACHEMISSES_CACHEMISSES_MASK       0xFFFFFUL                                   /**< Bit mask for MSC_CACHEMISSES */
+#define _MSC_CACHEMISSES_CACHEMISSES_DEFAULT    0x00000000UL                                /**< Mode DEFAULT for MSC_CACHEMISSES */
+#define MSC_CACHEMISSES_CACHEMISSES_DEFAULT     (_MSC_CACHEMISSES_CACHEMISSES_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEMISSES */
+
+/* Bit fields for MSC MASSLOCK */
+#define _MSC_MASSLOCK_RESETVALUE                0x00000001UL                          /**< Default value for MSC_MASSLOCK */
+#define _MSC_MASSLOCK_MASK                      0x0000FFFFUL                          /**< Mask for MSC_MASSLOCK */
+#define _MSC_MASSLOCK_LOCKKEY_SHIFT             0                                     /**< Shift value for MSC_LOCKKEY */
+#define _MSC_MASSLOCK_LOCKKEY_MASK              0xFFFFUL                              /**< Bit mask for MSC_LOCKKEY */
+#define _MSC_MASSLOCK_LOCKKEY_LOCK              0x00000000UL                          /**< Mode LOCK for MSC_MASSLOCK */
+#define _MSC_MASSLOCK_LOCKKEY_UNLOCKED          0x00000000UL                          /**< Mode UNLOCKED for MSC_MASSLOCK */
+#define _MSC_MASSLOCK_LOCKKEY_DEFAULT           0x00000001UL                          /**< Mode DEFAULT for MSC_MASSLOCK */
+#define _MSC_MASSLOCK_LOCKKEY_LOCKED            0x00000001UL                          /**< Mode LOCKED for MSC_MASSLOCK */
+#define _MSC_MASSLOCK_LOCKKEY_UNLOCK            0x0000631AUL                          /**< Mode UNLOCK for MSC_MASSLOCK */
+#define MSC_MASSLOCK_LOCKKEY_LOCK               (_MSC_MASSLOCK_LOCKKEY_LOCK << 0)     /**< Shifted mode LOCK for MSC_MASSLOCK */
+#define MSC_MASSLOCK_LOCKKEY_UNLOCKED           (_MSC_MASSLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_MASSLOCK */
+#define MSC_MASSLOCK_LOCKKEY_DEFAULT            (_MSC_MASSLOCK_LOCKKEY_DEFAULT << 0)  /**< Shifted mode DEFAULT for MSC_MASSLOCK */
+#define MSC_MASSLOCK_LOCKKEY_LOCKED             (_MSC_MASSLOCK_LOCKKEY_LOCKED << 0)   /**< Shifted mode LOCKED for MSC_MASSLOCK */
+#define MSC_MASSLOCK_LOCKKEY_UNLOCK             (_MSC_MASSLOCK_LOCKKEY_UNLOCK << 0)   /**< Shifted mode UNLOCK for MSC_MASSLOCK */
+
+/* Bit fields for MSC STARTUP */
+#define _MSC_STARTUP_RESETVALUE                 0x1300104DUL                         /**< Default value for MSC_STARTUP */
+#define _MSC_STARTUP_MASK                       0x773FF3FFUL                         /**< Mask for MSC_STARTUP */
+#define _MSC_STARTUP_STDLY0_SHIFT               0                                    /**< Shift value for MSC_STDLY0 */
+#define _MSC_STARTUP_STDLY0_MASK                0x3FFUL                              /**< Bit mask for MSC_STDLY0 */
+#define _MSC_STARTUP_STDLY0_DEFAULT             0x0000004DUL                         /**< Mode DEFAULT for MSC_STARTUP */
+#define MSC_STARTUP_STDLY0_DEFAULT              (_MSC_STARTUP_STDLY0_DEFAULT << 0)   /**< Shifted mode DEFAULT for MSC_STARTUP */
+#define _MSC_STARTUP_STDLY1_SHIFT               12                                   /**< Shift value for MSC_STDLY1 */
+#define _MSC_STARTUP_STDLY1_MASK                0x3FF000UL                           /**< Bit mask for MSC_STDLY1 */
+#define _MSC_STARTUP_STDLY1_DEFAULT             0x00000001UL                         /**< Mode DEFAULT for MSC_STARTUP */
+#define MSC_STARTUP_STDLY1_DEFAULT              (_MSC_STARTUP_STDLY1_DEFAULT << 12)  /**< Shifted mode DEFAULT for MSC_STARTUP */
+#define MSC_STARTUP_ASTWAIT                     (0x1UL << 24)                        /**< Active Startup Wait */
+#define _MSC_STARTUP_ASTWAIT_SHIFT              24                                   /**< Shift value for MSC_ASTWAIT */
+#define _MSC_STARTUP_ASTWAIT_MASK               0x1000000UL                          /**< Bit mask for MSC_ASTWAIT */
+#define _MSC_STARTUP_ASTWAIT_DEFAULT            0x00000001UL                         /**< Mode DEFAULT for MSC_STARTUP */
+#define MSC_STARTUP_ASTWAIT_DEFAULT             (_MSC_STARTUP_ASTWAIT_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STARTUP */
+#define MSC_STARTUP_STWSEN                      (0x1UL << 25)                        /**< Startup Waitstates Enable */
+#define _MSC_STARTUP_STWSEN_SHIFT               25                                   /**< Shift value for MSC_STWSEN */
+#define _MSC_STARTUP_STWSEN_MASK                0x2000000UL                          /**< Bit mask for MSC_STWSEN */
+#define _MSC_STARTUP_STWSEN_DEFAULT             0x00000001UL                         /**< Mode DEFAULT for MSC_STARTUP */
+#define MSC_STARTUP_STWSEN_DEFAULT              (_MSC_STARTUP_STWSEN_DEFAULT << 25)  /**< Shifted mode DEFAULT for MSC_STARTUP */
+#define MSC_STARTUP_STWSAEN                     (0x1UL << 26)                        /**< Startup Waitstates Always Enable */
+#define _MSC_STARTUP_STWSAEN_SHIFT              26                                   /**< Shift value for MSC_STWSAEN */
+#define _MSC_STARTUP_STWSAEN_MASK               0x4000000UL                          /**< Bit mask for MSC_STWSAEN */
+#define _MSC_STARTUP_STWSAEN_DEFAULT            0x00000000UL                         /**< Mode DEFAULT for MSC_STARTUP */
+#define MSC_STARTUP_STWSAEN_DEFAULT             (_MSC_STARTUP_STWSAEN_DEFAULT << 26) /**< Shifted mode DEFAULT for MSC_STARTUP */
+#define _MSC_STARTUP_STWS_SHIFT                 28                                   /**< Shift value for MSC_STWS */
+#define _MSC_STARTUP_STWS_MASK                  0x70000000UL                         /**< Bit mask for MSC_STWS */
+#define _MSC_STARTUP_STWS_DEFAULT               0x00000001UL                         /**< Mode DEFAULT for MSC_STARTUP */
+#define MSC_STARTUP_STWS_DEFAULT                (_MSC_STARTUP_STWS_DEFAULT << 28)    /**< Shifted mode DEFAULT for MSC_STARTUP */
+
+/* Bit fields for MSC CMD */
+#define _MSC_CMD_RESETVALUE                     0x00000000UL                  /**< Default value for MSC_CMD */
+#define _MSC_CMD_MASK                           0x00000001UL                  /**< Mask for MSC_CMD */
+#define MSC_CMD_PWRUP                           (0x1UL << 0)                  /**< Flash Power Up Command */
+#define _MSC_CMD_PWRUP_SHIFT                    0                             /**< Shift value for MSC_PWRUP */
+#define _MSC_CMD_PWRUP_MASK                     0x1UL                         /**< Bit mask for MSC_PWRUP */
+#define _MSC_CMD_PWRUP_DEFAULT                  0x00000000UL                  /**< Mode DEFAULT for MSC_CMD */
+#define MSC_CMD_PWRUP_DEFAULT                   (_MSC_CMD_PWRUP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CMD */
+
+/** @} End of group EFM32PG1B_MSC */
+/** @} End of group Parts */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG_STK3401/efm32pg1b_pcnt.h	Fri Jan 15 07:45:16 2016 +0000
@@ -0,0 +1,706 @@
+/**************************************************************************//**
+ * @file efm32pg1b_pcnt.h
+ * @brief EFM32PG1B_PCNT register and bit field definitions
+ * @version 4.2.0
+ ******************************************************************************
+ * @section License
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ ******************************************************************************
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software.@n
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.@n
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is
+ * providing the Software "AS IS", with no express or implied warranties of any
+ * kind, including, but not limited to, any implied warranties of
+ * merchantability or fitness for any particular purpose or warranties against
+ * infringement of any proprietary rights of a third party.
+ *
+ * Silicon Laboratories, Inc. will not be liable for any consequential,
+ * incidental, or special damages, or any other relief, or for any claim by
+ * any third party, arising from your use of this Software.
+ *
+ *****************************************************************************/
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFM32PG1B_PCNT
+ * @{
+ * @brief EFM32PG1B_PCNT Register Declaration
+ *****************************************************************************/
+typedef struct
+{
+  __IO uint32_t CTRL;         /**< Control Register  */
+  __IO uint32_t CMD;          /**< Command Register  */
+  __I uint32_t  STATUS;       /**< Status Register  */
+  __I uint32_t  CNT;          /**< Counter Value Register  */
+  __I uint32_t  TOP;          /**< Top Value Register  */
+  __IO uint32_t TOPB;         /**< Top Value Buffer Register  */
+  __I uint32_t  IF;           /**< Interrupt Flag Register  */
+  __IO uint32_t IFS;          /**< Interrupt Flag Set Register  */
+  __IO uint32_t IFC;          /**< Interrupt Flag Clear Register  */
+  __IO uint32_t IEN;          /**< Interrupt Enable Register  */
+  uint32_t      RESERVED0[1]; /**< Reserved for future use **/
+  __IO uint32_t ROUTELOC0;    /**< I/O Routing Location Register  */
+
+  uint32_t      RESERVED1[4]; /**< Reserved for future use **/
+  __IO uint32_t FREEZE;       /**< Freeze Register  */
+  __I uint32_t  SYNCBUSY;     /**< Synchronization Busy Register  */
+
+  uint32_t      RESERVED2[7]; /**< Reserved for future use **/
+  __I uint32_t  AUXCNT;       /**< Auxiliary Counter Value Register  */
+  __IO uint32_t INPUT;        /**< PCNT Input Register  */
+  __IO uint32_t OVSCFG;       /**< Oversampling Config Register  */
+} PCNT_TypeDef;               /** @} */
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B_PCNT_BitFields
+ * @{
+ *****************************************************************************/
+
+/* Bit fields for PCNT CTRL */
+#define _PCNT_CTRL_RESETVALUE              0x00000000UL                          /**< Default value for PCNT_CTRL */
+#define _PCNT_CTRL_MASK                    0xBFDBFFFFUL                          /**< Mask for PCNT_CTRL */
+#define _PCNT_CTRL_MODE_SHIFT              0                                     /**< Shift value for PCNT_MODE */
+#define _PCNT_CTRL_MODE_MASK               0x7UL                                 /**< Bit mask for PCNT_MODE */
+#define _PCNT_CTRL_MODE_DEFAULT            0x00000000UL                          /**< Mode DEFAULT for PCNT_CTRL */
+#define _PCNT_CTRL_MODE_DISABLE            0x00000000UL                          /**< Mode DISABLE for PCNT_CTRL */
+#define _PCNT_CTRL_MODE_OVSSINGLE          0x00000001UL                          /**< Mode OVSSINGLE for PCNT_CTRL */
+#define _PCNT_CTRL_MODE_EXTCLKSINGLE       0x00000002UL                          /**< Mode EXTCLKSINGLE for PCNT_CTRL */
+#define _PCNT_CTRL_MODE_EXTCLKQUAD         0x00000003UL                          /**< Mode EXTCLKQUAD for PCNT_CTRL */
+#define _PCNT_CTRL_MODE_OVSQUAD1X          0x00000004UL                          /**< Mode OVSQUAD1X for PCNT_CTRL */
+#define _PCNT_CTRL_MODE_OVSQUAD2X          0x00000005UL                          /**< Mode OVSQUAD2X for PCNT_CTRL */
+#define _PCNT_CTRL_MODE_OVSQUAD4X          0x00000006UL                          /**< Mode OVSQUAD4X for PCNT_CTRL */
+#define PCNT_CTRL_MODE_DEFAULT             (_PCNT_CTRL_MODE_DEFAULT << 0)        /**< Shifted mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_MODE_DISABLE             (_PCNT_CTRL_MODE_DISABLE << 0)        /**< Shifted mode DISABLE for PCNT_CTRL */
+#define PCNT_CTRL_MODE_OVSSINGLE           (_PCNT_CTRL_MODE_OVSSINGLE << 0)      /**< Shifted mode OVSSINGLE for PCNT_CTRL */
+#define PCNT_CTRL_MODE_EXTCLKSINGLE        (_PCNT_CTRL_MODE_EXTCLKSINGLE << 0)   /**< Shifted mode EXTCLKSINGLE for PCNT_CTRL */
+#define PCNT_CTRL_MODE_EXTCLKQUAD          (_PCNT_CTRL_MODE_EXTCLKQUAD << 0)     /**< Shifted mode EXTCLKQUAD for PCNT_CTRL */
+#define PCNT_CTRL_MODE_OVSQUAD1X           (_PCNT_CTRL_MODE_OVSQUAD1X << 0)      /**< Shifted mode OVSQUAD1X for PCNT_CTRL */
+#define PCNT_CTRL_MODE_OVSQUAD2X           (_PCNT_CTRL_MODE_OVSQUAD2X << 0)      /**< Shifted mode OVSQUAD2X for PCNT_CTRL */
+#define PCNT_CTRL_MODE_OVSQUAD4X           (_PCNT_CTRL_MODE_OVSQUAD4X << 0)      /**< Shifted mode OVSQUAD4X for PCNT_CTRL */
+#define PCNT_CTRL_FILT                     (0x1UL << 3)                          /**< Enable Digital Pulse Width Filter */
+#define _PCNT_CTRL_FILT_SHIFT              3                                     /**< Shift value for PCNT_FILT */
+#define _PCNT_CTRL_FILT_MASK               0x8UL                                 /**< Bit mask for PCNT_FILT */
+#define _PCNT_CTRL_FILT_DEFAULT            0x00000000UL                          /**< Mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_FILT_DEFAULT             (_PCNT_CTRL_FILT_DEFAULT << 3)        /**< Shifted mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_RSTEN                    (0x1UL << 4)                          /**< Enable PCNT Clock Domain Reset */
+#define _PCNT_CTRL_RSTEN_SHIFT             4                                     /**< Shift value for PCNT_RSTEN */
+#define _PCNT_CTRL_RSTEN_MASK              0x10UL                                /**< Bit mask for PCNT_RSTEN */
+#define _PCNT_CTRL_RSTEN_DEFAULT           0x00000000UL                          /**< Mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_RSTEN_DEFAULT            (_PCNT_CTRL_RSTEN_DEFAULT << 4)       /**< Shifted mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_CNTRSTEN                 (0x1UL << 5)                          /**< Enable CNT Reset */
+#define _PCNT_CTRL_CNTRSTEN_SHIFT          5                                     /**< Shift value for PCNT_CNTRSTEN */
+#define _PCNT_CTRL_CNTRSTEN_MASK           0x20UL                                /**< Bit mask for PCNT_CNTRSTEN */
+#define _PCNT_CTRL_CNTRSTEN_DEFAULT        0x00000000UL                          /**< Mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_CNTRSTEN_DEFAULT         (_PCNT_CTRL_CNTRSTEN_DEFAULT << 5)    /**< Shifted mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_AUXCNTRSTEN              (0x1UL << 6)                          /**< Enable AUXCNT Reset */
+#define _PCNT_CTRL_AUXCNTRSTEN_SHIFT       6                                     /**< Shift value for PCNT_AUXCNTRSTEN */
+#define _PCNT_CTRL_AUXCNTRSTEN_MASK        0x40UL                                /**< Bit mask for PCNT_AUXCNTRSTEN */
+#define _PCNT_CTRL_AUXCNTRSTEN_DEFAULT     0x00000000UL                          /**< Mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_AUXCNTRSTEN_DEFAULT      (_PCNT_CTRL_AUXCNTRSTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_DEBUGHALT                (0x1UL << 7)                          /**< Debug Mode Halt Enable */
+#define _PCNT_CTRL_DEBUGHALT_SHIFT         7                                     /**< Shift value for PCNT_DEBUGHALT */
+#define _PCNT_CTRL_DEBUGHALT_MASK          0x80UL                                /**< Bit mask for PCNT_DEBUGHALT */
+#define _PCNT_CTRL_DEBUGHALT_DEFAULT       0x00000000UL                          /**< Mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_DEBUGHALT_DEFAULT        (_PCNT_CTRL_DEBUGHALT_DEFAULT << 7)   /**< Shifted mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_HYST                     (0x1UL << 8)                          /**< Enable Hysteresis */
+#define _PCNT_CTRL_HYST_SHIFT              8                                     /**< Shift value for PCNT_HYST */
+#define _PCNT_CTRL_HYST_MASK               0x100UL                               /**< Bit mask for PCNT_HYST */
+#define _PCNT_CTRL_HYST_DEFAULT            0x00000000UL                          /**< Mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_HYST_DEFAULT             (_PCNT_CTRL_HYST_DEFAULT << 8)        /**< Shifted mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_S1CDIR                   (0x1UL << 9)                          /**< Count direction determined by S1 */
+#define _PCNT_CTRL_S1CDIR_SHIFT            9                                     /**< Shift value for PCNT_S1CDIR */
+#define _PCNT_CTRL_S1CDIR_MASK             0x200UL                               /**< Bit mask for PCNT_S1CDIR */
+#define _PCNT_CTRL_S1CDIR_DEFAULT          0x00000000UL                          /**< Mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_S1CDIR_DEFAULT           (_PCNT_CTRL_S1CDIR_DEFAULT << 9)      /**< Shifted mode DEFAULT for PCNT_CTRL */
+#define _PCNT_CTRL_CNTEV_SHIFT             10                                    /**< Shift value for PCNT_CNTEV */
+#define _PCNT_CTRL_CNTEV_MASK              0xC00UL                               /**< Bit mask for PCNT_CNTEV */
+#define _PCNT_CTRL_CNTEV_DEFAULT           0x00000000UL                          /**< Mode DEFAULT for PCNT_CTRL */
+#define _PCNT_CTRL_CNTEV_BOTH              0x00000000UL                          /**< Mode BOTH for PCNT_CTRL */
+#define _PCNT_CTRL_CNTEV_UP                0x00000001UL                          /**< Mode UP for PCNT_CTRL */
+#define _PCNT_CTRL_CNTEV_DOWN              0x00000002UL                          /**< Mode DOWN for PCNT_CTRL */
+#define _PCNT_CTRL_CNTEV_NONE              0x00000003UL                          /**< Mode NONE for PCNT_CTRL */
+#define PCNT_CTRL_CNTEV_DEFAULT            (_PCNT_CTRL_CNTEV_DEFAULT << 10)      /**< Shifted mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_CNTEV_BOTH               (_PCNT_CTRL_CNTEV_BOTH << 10)         /**< Shifted mode BOTH for PCNT_CTRL */
+#define PCNT_CTRL_CNTEV_UP                 (_PCNT_CTRL_CNTEV_UP << 10)           /**< Shifted mode UP for PCNT_CTRL */
+#define PCNT_CTRL_CNTEV_DOWN               (_PCNT_CTRL_CNTEV_DOWN << 10)         /**< Shifted mode DOWN for PCNT_CTRL */
+#define PCNT_CTRL_CNTEV_NONE               (_PCNT_CTRL_CNTEV_NONE << 10)         /**< Shifted mode NONE for PCNT_CTRL */
+#define _PCNT_CTRL_AUXCNTEV_SHIFT          12                                    /**< Shift value for PCNT_AUXCNTEV */
+#define _PCNT_CTRL_AUXCNTEV_MASK           0x3000UL                              /**< Bit mask for PCNT_AUXCNTEV */
+#define _PCNT_CTRL_AUXCNTEV_DEFAULT        0x00000000UL                          /**< Mode DEFAULT for PCNT_CTRL */
+#define _PCNT_CTRL_AUXCNTEV_NONE           0x00000000UL                          /**< Mode NONE for PCNT_CTRL */
+#define _PCNT_CTRL_AUXCNTEV_UP             0x00000001UL                          /**< Mode UP for PCNT_CTRL */
+#define _PCNT_CTRL_AUXCNTEV_DOWN           0x00000002UL                          /**< Mode DOWN for PCNT_CTRL */
+#define _PCNT_CTRL_AUXCNTEV_BOTH           0x00000003UL                          /**< Mode BOTH for PCNT_CTRL */
+#define PCNT_CTRL_AUXCNTEV_DEFAULT         (_PCNT_CTRL_AUXCNTEV_DEFAULT << 12)   /**< Shifted mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_AUXCNTEV_NONE            (_PCNT_CTRL_AUXCNTEV_NONE << 12)      /**< Shifted mode NONE for PCNT_CTRL */
+#define PCNT_CTRL_AUXCNTEV_UP              (_PCNT_CTRL_AUXCNTEV_UP << 12)        /**< Shifted mode UP for PCNT_CTRL */
+#define PCNT_CTRL_AUXCNTEV_DOWN            (_PCNT_CTRL_AUXCNTEV_DOWN << 12)      /**< Shifted mode DOWN for PCNT_CTRL */
+#define PCNT_CTRL_AUXCNTEV_BOTH            (_PCNT_CTRL_AUXCNTEV_BOTH << 12)      /**< Shifted mode BOTH for PCNT_CTRL */
+#define PCNT_CTRL_CNTDIR                   (0x1UL << 14)                         /**< Non-Quadrature Mode Counter Direction Control */
+#define _PCNT_CTRL_CNTDIR_SHIFT            14                                    /**< Shift value for PCNT_CNTDIR */
+#define _PCNT_CTRL_CNTDIR_MASK             0x4000UL                              /**< Bit mask for PCNT_CNTDIR */
+#define _PCNT_CTRL_CNTDIR_DEFAULT          0x00000000UL                          /**< Mode DEFAULT for PCNT_CTRL */
+#define _PCNT_CTRL_CNTDIR_UP               0x00000000UL                          /**< Mode UP for PCNT_CTRL */
+#define _PCNT_CTRL_CNTDIR_DOWN             0x00000001UL                          /**< Mode DOWN for PCNT_CTRL */
+#define PCNT_CTRL_CNTDIR_DEFAULT           (_PCNT_CTRL_CNTDIR_DEFAULT << 14)     /**< Shifted mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_CNTDIR_UP                (_PCNT_CTRL_CNTDIR_UP << 14)          /**< Shifted mode UP for PCNT_CTRL */
+#define PCNT_CTRL_CNTDIR_DOWN              (_PCNT_CTRL_CNTDIR_DOWN << 14)        /**< Shifted mode DOWN for PCNT_CTRL */
+#define PCNT_CTRL_EDGE                     (0x1UL << 15)                         /**< Edge Select */
+#define _PCNT_CTRL_EDGE_SHIFT              15                                    /**< Shift value for PCNT_EDGE */
+#define _PCNT_CTRL_EDGE_MASK               0x8000UL                              /**< Bit mask for PCNT_EDGE */
+#define _PCNT_CTRL_EDGE_DEFAULT            0x00000000UL                          /**< Mode DEFAULT for PCNT_CTRL */
+#define _PCNT_CTRL_EDGE_POS                0x00000000UL                          /**< Mode POS for PCNT_CTRL */
+#define _PCNT_CTRL_EDGE_NEG                0x00000001UL                          /**< Mode NEG for PCNT_CTRL */
+#define PCNT_CTRL_EDGE_DEFAULT             (_PCNT_CTRL_EDGE_DEFAULT << 15)       /**< Shifted mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_EDGE_POS                 (_PCNT_CTRL_EDGE_POS << 15)           /**< Shifted mode POS for PCNT_CTRL */
+#define PCNT_CTRL_EDGE_NEG                 (_PCNT_CTRL_EDGE_NEG << 15)           /**< Shifted mode NEG for PCNT_CTRL */
+#define _PCNT_CTRL_TCCMODE_SHIFT           16                                    /**< Shift value for PCNT_TCCMODE */
+#define _PCNT_CTRL_TCCMODE_MASK            0x30000UL                             /**< Bit mask for PCNT_TCCMODE */
+#define _PCNT_CTRL_TCCMODE_DEFAULT         0x00000000UL                          /**< Mode DEFAULT for PCNT_CTRL */
+#define _PCNT_CTRL_TCCMODE_DISABLED        0x00000000UL                          /**< Mode DISABLED for PCNT_CTRL */
+#define _PCNT_CTRL_TCCMODE_LFA             0x00000001UL                          /**< Mode LFA for PCNT_CTRL */
+#define _PCNT_CTRL_TCCMODE_PRS             0x00000002UL                          /**< Mode PRS for PCNT_CTRL */
+#define PCNT_CTRL_TCCMODE_DEFAULT          (_PCNT_CTRL_TCCMODE_DEFAULT << 16)    /**< Shifted mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_TCCMODE_DISABLED         (_PCNT_CTRL_TCCMODE_DISABLED << 16)   /**< Shifted mode DISABLED for PCNT_CTRL */
+#define PCNT_CTRL_TCCMODE_LFA              (_PCNT_CTRL_TCCMODE_LFA << 16)        /**< Shifted mode LFA for PCNT_CTRL */
+#define PCNT_CTRL_TCCMODE_PRS              (_PCNT_CTRL_TCCMODE_PRS << 16)        /**< Shifted mode PRS for PCNT_CTRL */
+#define _PCNT_CTRL_TCCPRESC_SHIFT          19                                    /**< Shift value for PCNT_TCCPRESC */
+#define _PCNT_CTRL_TCCPRESC_MASK           0x180000UL                            /**< Bit mask for PCNT_TCCPRESC */
+#define _PCNT_CTRL_TCCPRESC_DEFAULT        0x00000000UL                          /**< Mode DEFAULT for PCNT_CTRL */
+#define _PCNT_CTRL_TCCPRESC_DIV1           0x00000000UL                          /**< Mode DIV1 for PCNT_CTRL */
+#define _PCNT_CTRL_TCCPRESC_DIV2           0x00000001UL                          /**< Mode DIV2 for PCNT_CTRL */
+#define _PCNT_CTRL_TCCPRESC_DIV4           0x00000002UL                          /**< Mode DIV4 for PCNT_CTRL */
+#define _PCNT_CTRL_TCCPRESC_DIV8           0x00000003UL                          /**< Mode DIV8 for PCNT_CTRL */
+#define PCNT_CTRL_TCCPRESC_DEFAULT         (_PCNT_CTRL_TCCPRESC_DEFAULT << 19)   /**< Shifted mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_TCCPRESC_DIV1            (_PCNT_CTRL_TCCPRESC_DIV1 << 19)      /**< Shifted mode DIV1 for PCNT_CTRL */
+#define PCNT_CTRL_TCCPRESC_DIV2            (_PCNT_CTRL_TCCPRESC_DIV2 << 19)      /**< Shifted mode DIV2 for PCNT_CTRL */
+#define PCNT_CTRL_TCCPRESC_DIV4            (_PCNT_CTRL_TCCPRESC_DIV4 << 19)      /**< Shifted mode DIV4 for PCNT_CTRL */
+#define PCNT_CTRL_TCCPRESC_DIV8            (_PCNT_CTRL_TCCPRESC_DIV8 << 19)      /**< Shifted mode DIV8 for PCNT_CTRL */
+#define _PCNT_CTRL_TCCCOMP_SHIFT           22                                    /**< Shift value for PCNT_TCCCOMP */
+#define _PCNT_CTRL_TCCCOMP_MASK            0xC00000UL                            /**< Bit mask for PCNT_TCCCOMP */
+#define _PCNT_CTRL_TCCCOMP_DEFAULT         0x00000000UL                          /**< Mode DEFAULT for PCNT_CTRL */
+#define _PCNT_CTRL_TCCCOMP_LTOE            0x00000000UL                          /**< Mode LTOE for PCNT_CTRL */
+#define _PCNT_CTRL_TCCCOMP_GTOE            0x00000001UL                          /**< Mode GTOE for PCNT_CTRL */
+#define _PCNT_CTRL_TCCCOMP_RANGE           0x00000002UL                          /**< Mode RANGE for PCNT_CTRL */
+#define PCNT_CTRL_TCCCOMP_DEFAULT          (_PCNT_CTRL_TCCCOMP_DEFAULT << 22)    /**< Shifted mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_TCCCOMP_LTOE             (_PCNT_CTRL_TCCCOMP_LTOE << 22)       /**< Shifted mode LTOE for PCNT_CTRL */
+#define PCNT_CTRL_TCCCOMP_GTOE             (_PCNT_CTRL_TCCCOMP_GTOE << 22)       /**< Shifted mode GTOE for PCNT_CTRL */
+#define PCNT_CTRL_TCCCOMP_RANGE            (_PCNT_CTRL_TCCCOMP_RANGE << 22)      /**< Shifted mode RANGE for PCNT_CTRL */
+#define PCNT_CTRL_PRSGATEEN                (0x1UL << 24)                         /**< PRS gate enable */
+#define _PCNT_CTRL_PRSGATEEN_SHIFT         24                                    /**< Shift value for PCNT_PRSGATEEN */
+#define _PCNT_CTRL_PRSGATEEN_MASK          0x1000000UL                           /**< Bit mask for PCNT_PRSGATEEN */
+#define _PCNT_CTRL_PRSGATEEN_DEFAULT       0x00000000UL                          /**< Mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_PRSGATEEN_DEFAULT        (_PCNT_CTRL_PRSGATEEN_DEFAULT << 24)  /**< Shifted mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_TCCPRSPOL                (0x1UL << 25)                         /**< TCC PRS polarity select */
+#define _PCNT_CTRL_TCCPRSPOL_SHIFT         25                                    /**< Shift value for PCNT_TCCPRSPOL */
+#define _PCNT_CTRL_TCCPRSPOL_MASK          0x2000000UL                           /**< Bit mask for PCNT_TCCPRSPOL */
+#define _PCNT_CTRL_TCCPRSPOL_DEFAULT       0x00000000UL                          /**< Mode DEFAULT for PCNT_CTRL */
+#define _PCNT_CTRL_TCCPRSPOL_RISING        0x00000000UL                          /**< Mode RISING for PCNT_CTRL */
+#define _PCNT_CTRL_TCCPRSPOL_FALLING       0x00000001UL                          /**< Mode FALLING for PCNT_CTRL */
+#define PCNT_CTRL_TCCPRSPOL_DEFAULT        (_PCNT_CTRL_TCCPRSPOL_DEFAULT << 25)  /**< Shifted mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_TCCPRSPOL_RISING         (_PCNT_CTRL_TCCPRSPOL_RISING << 25)   /**< Shifted mode RISING for PCNT_CTRL */
+#define PCNT_CTRL_TCCPRSPOL_FALLING        (_PCNT_CTRL_TCCPRSPOL_FALLING << 25)  /**< Shifted mode FALLING for PCNT_CTRL */
+#define _PCNT_CTRL_TCCPRSSEL_SHIFT         26                                    /**< Shift value for PCNT_TCCPRSSEL */
+#define _PCNT_CTRL_TCCPRSSEL_MASK          0x3C000000UL                          /**< Bit mask for PCNT_TCCPRSSEL */
+#define _PCNT_CTRL_TCCPRSSEL_DEFAULT       0x00000000UL                          /**< Mode DEFAULT for PCNT_CTRL */
+#define _PCNT_CTRL_TCCPRSSEL_PRSCH0        0x00000000UL                          /**< Mode PRSCH0 for PCNT_CTRL */
+#define _PCNT_CTRL_TCCPRSSEL_PRSCH1        0x00000001UL                          /**< Mode PRSCH1 for PCNT_CTRL */
+#define _PCNT_CTRL_TCCPRSSEL_PRSCH2        0x00000002UL                          /**< Mode PRSCH2 for PCNT_CTRL */
+#define _PCNT_CTRL_TCCPRSSEL_PRSCH3        0x00000003UL                          /**< Mode PRSCH3 for PCNT_CTRL */
+#define _PCNT_CTRL_TCCPRSSEL_PRSCH4        0x00000004UL                          /**< Mode PRSCH4 for PCNT_CTRL */
+#define _PCNT_CTRL_TCCPRSSEL_PRSCH5        0x00000005UL                          /**< Mode PRSCH5 for PCNT_CTRL */
+#define _PCNT_CTRL_TCCPRSSEL_PRSCH6        0x00000006UL                          /**< Mode PRSCH6 for PCNT_CTRL */
+#define _PCNT_CTRL_TCCPRSSEL_PRSCH7        0x00000007UL                          /**< Mode PRSCH7 for PCNT_CTRL */
+#define _PCNT_CTRL_TCCPRSSEL_PRSCH8        0x00000008UL                          /**< Mode PRSCH8 for PCNT_CTRL */
+#define _PCNT_CTRL_TCCPRSSEL_PRSCH9        0x00000009UL                          /**< Mode PRSCH9 for PCNT_CTRL */
+#define _PCNT_CTRL_TCCPRSSEL_PRSCH10       0x0000000AUL                          /**< Mode PRSCH10 for PCNT_CTRL */
+#define _PCNT_CTRL_TCCPRSSEL_PRSCH11       0x0000000BUL                          /**< Mode PRSCH11 for PCNT_CTRL */
+#define PCNT_CTRL_TCCPRSSEL_DEFAULT        (_PCNT_CTRL_TCCPRSSEL_DEFAULT << 26)  /**< Shifted mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_TCCPRSSEL_PRSCH0         (_PCNT_CTRL_TCCPRSSEL_PRSCH0 << 26)   /**< Shifted mode PRSCH0 for PCNT_CTRL */
+#define PCNT_CTRL_TCCPRSSEL_PRSCH1         (_PCNT_CTRL_TCCPRSSEL_PRSCH1 << 26)   /**< Shifted mode PRSCH1 for PCNT_CTRL */
+#define PCNT_CTRL_TCCPRSSEL_PRSCH2         (_PCNT_CTRL_TCCPRSSEL_PRSCH2 << 26)   /**< Shifted mode PRSCH2 for PCNT_CTRL */
+#define PCNT_CTRL_TCCPRSSEL_PRSCH3         (_PCNT_CTRL_TCCPRSSEL_PRSCH3 << 26)   /**< Shifted mode PRSCH3 for PCNT_CTRL */
+#define PCNT_CTRL_TCCPRSSEL_PRSCH4         (_PCNT_CTRL_TCCPRSSEL_PRSCH4 << 26)   /**< Shifted mode PRSCH4 for PCNT_CTRL */
+#define PCNT_CTRL_TCCPRSSEL_PRSCH5         (_PCNT_CTRL_TCCPRSSEL_PRSCH5 << 26)   /**< Shifted mode PRSCH5 for PCNT_CTRL */
+#define PCNT_CTRL_TCCPRSSEL_PRSCH6         (_PCNT_CTRL_TCCPRSSEL_PRSCH6 << 26)   /**< Shifted mode PRSCH6 for PCNT_CTRL */
+#define PCNT_CTRL_TCCPRSSEL_PRSCH7         (_PCNT_CTRL_TCCPRSSEL_PRSCH7 << 26)   /**< Shifted mode PRSCH7 for PCNT_CTRL */
+#define PCNT_CTRL_TCCPRSSEL_PRSCH8         (_PCNT_CTRL_TCCPRSSEL_PRSCH8 << 26)   /**< Shifted mode PRSCH8 for PCNT_CTRL */
+#define PCNT_CTRL_TCCPRSSEL_PRSCH9         (_PCNT_CTRL_TCCPRSSEL_PRSCH9 << 26)   /**< Shifted mode PRSCH9 for PCNT_CTRL */
+#define PCNT_CTRL_TCCPRSSEL_PRSCH10        (_PCNT_CTRL_TCCPRSSEL_PRSCH10 << 26)  /**< Shifted mode PRSCH10 for PCNT_CTRL */
+#define PCNT_CTRL_TCCPRSSEL_PRSCH11        (_PCNT_CTRL_TCCPRSSEL_PRSCH11 << 26)  /**< Shifted mode PRSCH11 for PCNT_CTRL */
+#define PCNT_CTRL_TOPBHFSEL                (0x1UL << 31)                         /**< TOPB High frequency value select */
+#define _PCNT_CTRL_TOPBHFSEL_SHIFT         31                                    /**< Shift value for PCNT_TOPBHFSEL */
+#define _PCNT_CTRL_TOPBHFSEL_MASK          0x80000000UL                          /**< Bit mask for PCNT_TOPBHFSEL */
+#define _PCNT_CTRL_TOPBHFSEL_DEFAULT       0x00000000UL                          /**< Mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_TOPBHFSEL_DEFAULT        (_PCNT_CTRL_TOPBHFSEL_DEFAULT << 31)  /**< Shifted mode DEFAULT for PCNT_CTRL */
+
+/* Bit fields for PCNT CMD */
+#define _PCNT_CMD_RESETVALUE               0x00000000UL                     /**< Default value for PCNT_CMD */
+#define _PCNT_CMD_MASK                     0x00000003UL                     /**< Mask for PCNT_CMD */
+#define PCNT_CMD_LCNTIM                    (0x1UL << 0)                     /**< Load CNT Immediately */
+#define _PCNT_CMD_LCNTIM_SHIFT             0                                /**< Shift value for PCNT_LCNTIM */
+#define _PCNT_CMD_LCNTIM_MASK              0x1UL                            /**< Bit mask for PCNT_LCNTIM */
+#define _PCNT_CMD_LCNTIM_DEFAULT           0x00000000UL                     /**< Mode DEFAULT for PCNT_CMD */
+#define PCNT_CMD_LCNTIM_DEFAULT            (_PCNT_CMD_LCNTIM_DEFAULT << 0)  /**< Shifted mode DEFAULT for PCNT_CMD */
+#define PCNT_CMD_LTOPBIM                   (0x1UL << 1)                     /**< Load TOPB Immediately */
+#define _PCNT_CMD_LTOPBIM_SHIFT            1                                /**< Shift value for PCNT_LTOPBIM */
+#define _PCNT_CMD_LTOPBIM_MASK             0x2UL                            /**< Bit mask for PCNT_LTOPBIM */
+#define _PCNT_CMD_LTOPBIM_DEFAULT          0x00000000UL                     /**< Mode DEFAULT for PCNT_CMD */
+#define PCNT_CMD_LTOPBIM_DEFAULT           (_PCNT_CMD_LTOPBIM_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_CMD */
+
+/* Bit fields for PCNT STATUS */
+#define _PCNT_STATUS_RESETVALUE            0x00000000UL                    /**< Default value for PCNT_STATUS */
+#define _PCNT_STATUS_MASK                  0x00000001UL                    /**< Mask for PCNT_STATUS */
+#define PCNT_STATUS_DIR                    (0x1UL << 0)                    /**< Current Counter Direction */
+#define _PCNT_STATUS_DIR_SHIFT             0                               /**< Shift value for PCNT_DIR */
+#define _PCNT_STATUS_DIR_MASK              0x1UL                           /**< Bit mask for PCNT_DIR */
+#define _PCNT_STATUS_DIR_DEFAULT           0x00000000UL                    /**< Mode DEFAULT for PCNT_STATUS */
+#define _PCNT_STATUS_DIR_UP                0x00000000UL                    /**< Mode UP for PCNT_STATUS */
+#define _PCNT_STATUS_DIR_DOWN              0x00000001UL                    /**< Mode DOWN for PCNT_STATUS */
+#define PCNT_STATUS_DIR_DEFAULT            (_PCNT_STATUS_DIR_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_STATUS */
+#define PCNT_STATUS_DIR_UP                 (_PCNT_STATUS_DIR_UP << 0)      /**< Shifted mode UP for PCNT_STATUS */
+#define PCNT_STATUS_DIR_DOWN               (_PCNT_STATUS_DIR_DOWN << 0)    /**< Shifted mode DOWN for PCNT_STATUS */
+
+/* Bit fields for PCNT CNT */
+#define _PCNT_CNT_RESETVALUE               0x00000000UL                 /**< Default value for PCNT_CNT */
+#define _PCNT_CNT_MASK                     0x0000FFFFUL                 /**< Mask for PCNT_CNT */
+#define _PCNT_CNT_CNT_SHIFT                0                            /**< Shift value for PCNT_CNT */
+#define _PCNT_CNT_CNT_MASK                 0xFFFFUL                     /**< Bit mask for PCNT_CNT */
+#define _PCNT_CNT_CNT_DEFAULT              0x00000000UL                 /**< Mode DEFAULT for PCNT_CNT */
+#define PCNT_CNT_CNT_DEFAULT               (_PCNT_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_CNT */
+
+/* Bit fields for PCNT TOP */
+#define _PCNT_TOP_RESETVALUE               0x000000FFUL                 /**< Default value for PCNT_TOP */
+#define _PCNT_TOP_MASK                     0x0000FFFFUL                 /**< Mask for PCNT_TOP */
+#define _PCNT_TOP_TOP_SHIFT                0                            /**< Shift value for PCNT_TOP */
+#define _PCNT_TOP_TOP_MASK                 0xFFFFUL                     /**< Bit mask for PCNT_TOP */
+#define _PCNT_TOP_TOP_DEFAULT              0x000000FFUL                 /**< Mode DEFAULT for PCNT_TOP */
+#define PCNT_TOP_TOP_DEFAULT               (_PCNT_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_TOP */
+
+/* Bit fields for PCNT TOPB */
+#define _PCNT_TOPB_RESETVALUE              0x000000FFUL                   /**< Default value for PCNT_TOPB */
+#define _PCNT_TOPB_MASK                    0x0000FFFFUL                   /**< Mask for PCNT_TOPB */
+#define _PCNT_TOPB_TOPB_SHIFT              0                              /**< Shift value for PCNT_TOPB */
+#define _PCNT_TOPB_TOPB_MASK               0xFFFFUL                       /**< Bit mask for PCNT_TOPB */
+#define _PCNT_TOPB_TOPB_DEFAULT            0x000000FFUL                   /**< Mode DEFAULT for PCNT_TOPB */
+#define PCNT_TOPB_TOPB_DEFAULT             (_PCNT_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_TOPB */
+
+/* Bit fields for PCNT IF */
+#define _PCNT_IF_RESETVALUE                0x00000000UL                    /**< Default value for PCNT_IF */
+#define _PCNT_IF_MASK                      0x0000003FUL                    /**< Mask for PCNT_IF */
+#define PCNT_IF_UF                         (0x1UL << 0)                    /**< Underflow Interrupt Read Flag */
+#define _PCNT_IF_UF_SHIFT                  0                               /**< Shift value for PCNT_UF */
+#define _PCNT_IF_UF_MASK                   0x1UL                           /**< Bit mask for PCNT_UF */
+#define _PCNT_IF_UF_DEFAULT                0x00000000UL                    /**< Mode DEFAULT for PCNT_IF */
+#define PCNT_IF_UF_DEFAULT                 (_PCNT_IF_UF_DEFAULT << 0)      /**< Shifted mode DEFAULT for PCNT_IF */
+#define PCNT_IF_OF                         (0x1UL << 1)                    /**< Overflow Interrupt Read Flag */
+#define _PCNT_IF_OF_SHIFT                  1                               /**< Shift value for PCNT_OF */
+#define _PCNT_IF_OF_MASK                   0x2UL                           /**< Bit mask for PCNT_OF */
+#define _PCNT_IF_OF_DEFAULT                0x00000000UL                    /**< Mode DEFAULT for PCNT_IF */
+#define PCNT_IF_OF_DEFAULT                 (_PCNT_IF_OF_DEFAULT << 1)      /**< Shifted mode DEFAULT for PCNT_IF */
+#define PCNT_IF_DIRCNG                     (0x1UL << 2)                    /**< Direction Change Detect Interrupt Flag */
+#define _PCNT_IF_DIRCNG_SHIFT              2                               /**< Shift value for PCNT_DIRCNG */
+#define _PCNT_IF_DIRCNG_MASK               0x4UL                           /**< Bit mask for PCNT_DIRCNG */
+#define _PCNT_IF_DIRCNG_DEFAULT            0x00000000UL                    /**< Mode DEFAULT for PCNT_IF */
+#define PCNT_IF_DIRCNG_DEFAULT             (_PCNT_IF_DIRCNG_DEFAULT << 2)  /**< Shifted mode DEFAULT for PCNT_IF */
+#define PCNT_IF_AUXOF                      (0x1UL << 3)                    /**< Overflow Interrupt Read Flag */
+#define _PCNT_IF_AUXOF_SHIFT               3                               /**< Shift value for PCNT_AUXOF */
+#define _PCNT_IF_AUXOF_MASK                0x8UL                           /**< Bit mask for PCNT_AUXOF */
+#define _PCNT_IF_AUXOF_DEFAULT             0x00000000UL                    /**< Mode DEFAULT for PCNT_IF */
+#define PCNT_IF_AUXOF_DEFAULT              (_PCNT_IF_AUXOF_DEFAULT << 3)   /**< Shifted mode DEFAULT for PCNT_IF */
+#define PCNT_IF_TCC                        (0x1UL << 4)                    /**< Triggered compare Interrupt Read Flag */
+#define _PCNT_IF_TCC_SHIFT                 4                               /**< Shift value for PCNT_TCC */
+#define _PCNT_IF_TCC_MASK                  0x10UL                          /**< Bit mask for PCNT_TCC */
+#define _PCNT_IF_TCC_DEFAULT               0x00000000UL                    /**< Mode DEFAULT for PCNT_IF */
+#define PCNT_IF_TCC_DEFAULT                (_PCNT_IF_TCC_DEFAULT << 4)     /**< Shifted mode DEFAULT for PCNT_IF */
+#define PCNT_IF_OQSTERR                    (0x1UL << 5)                    /**< Oversampling Quadrature State Error Interrupt */
+#define _PCNT_IF_OQSTERR_SHIFT             5                               /**< Shift value for PCNT_OQSTERR */
+#define _PCNT_IF_OQSTERR_MASK              0x20UL                          /**< Bit mask for PCNT_OQSTERR */
+#define _PCNT_IF_OQSTERR_DEFAULT           0x00000000UL                    /**< Mode DEFAULT for PCNT_IF */
+#define PCNT_IF_OQSTERR_DEFAULT            (_PCNT_IF_OQSTERR_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_IF */
+
+/* Bit fields for PCNT IFS */
+#define _PCNT_IFS_RESETVALUE               0x00000000UL                     /**< Default value for PCNT_IFS */
+#define _PCNT_IFS_MASK                     0x0000003FUL                     /**< Mask for PCNT_IFS */
+#define PCNT_IFS_UF                        (0x1UL << 0)                     /**< Set UF Interrupt Flag */
+#define _PCNT_IFS_UF_SHIFT                 0                                /**< Shift value for PCNT_UF */
+#define _PCNT_IFS_UF_MASK                  0x1UL                            /**< Bit mask for PCNT_UF */
+#define _PCNT_IFS_UF_DEFAULT               0x00000000UL                     /**< Mode DEFAULT for PCNT_IFS */
+#define PCNT_IFS_UF_DEFAULT                (_PCNT_IFS_UF_DEFAULT << 0)      /**< Shifted mode DEFAULT for PCNT_IFS */
+#define PCNT_IFS_OF                        (0x1UL << 1)                     /**< Set OF Interrupt Flag */
+#define _PCNT_IFS_OF_SHIFT                 1                                /**< Shift value for PCNT_OF */
+#define _PCNT_IFS_OF_MASK                  0x2UL                            /**< Bit mask for PCNT_OF */
+#define _PCNT_IFS_OF_DEFAULT               0x00000000UL                     /**< Mode DEFAULT for PCNT_IFS */
+#define PCNT_IFS_OF_DEFAULT                (_PCNT_IFS_OF_DEFAULT << 1)      /**< Shifted mode DEFAULT for PCNT_IFS */
+#define PCNT_IFS_DIRCNG                    (0x1UL << 2)                     /**< Set DIRCNG Interrupt Flag */
+#define _PCNT_IFS_DIRCNG_SHIFT             2                                /**< Shift value for PCNT_DIRCNG */
+#define _PCNT_IFS_DIRCNG_MASK              0x4UL                            /**< Bit mask for PCNT_DIRCNG */
+#define _PCNT_IFS_DIRCNG_DEFAULT           0x00000000UL                     /**< Mode DEFAULT for PCNT_IFS */
+#define PCNT_IFS_DIRCNG_DEFAULT            (_PCNT_IFS_DIRCNG_DEFAULT << 2)  /**< Shifted mode DEFAULT for PCNT_IFS */
+#define PCNT_IFS_AUXOF                     (0x1UL << 3)                     /**< Set AUXOF Interrupt Flag */
+#define _PCNT_IFS_AUXOF_SHIFT              3                                /**< Shift value for PCNT_AUXOF */
+#define _PCNT_IFS_AUXOF_MASK               0x8UL                            /**< Bit mask for PCNT_AUXOF */
+#define _PCNT_IFS_AUXOF_DEFAULT            0x00000000UL                     /**< Mode DEFAULT for PCNT_IFS */
+#define PCNT_IFS_AUXOF_DEFAULT             (_PCNT_IFS_AUXOF_DEFAULT << 3)   /**< Shifted mode DEFAULT for PCNT_IFS */
+#define PCNT_IFS_TCC                       (0x1UL << 4)                     /**< Set TCC Interrupt Flag */
+#define _PCNT_IFS_TCC_SHIFT                4                                /**< Shift value for PCNT_TCC */
+#define _PCNT_IFS_TCC_MASK                 0x10UL                           /**< Bit mask for PCNT_TCC */
+#define _PCNT_IFS_TCC_DEFAULT              0x00000000UL                     /**< Mode DEFAULT for PCNT_IFS */
+#define PCNT_IFS_TCC_DEFAULT               (_PCNT_IFS_TCC_DEFAULT << 4)     /**< Shifted mode DEFAULT for PCNT_IFS */
+#define PCNT_IFS_OQSTERR                   (0x1UL << 5)                     /**< Set OQSTERR Interrupt Flag */
+#define _PCNT_IFS_OQSTERR_SHIFT            5                                /**< Shift value for PCNT_OQSTERR */
+#define _PCNT_IFS_OQSTERR_MASK             0x20UL                           /**< Bit mask for PCNT_OQSTERR */
+#define _PCNT_IFS_OQSTERR_DEFAULT          0x00000000UL                     /**< Mode DEFAULT for PCNT_IFS */
+#define PCNT_IFS_OQSTERR_DEFAULT           (_PCNT_IFS_OQSTERR_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_IFS */
+
+/* Bit fields for PCNT IFC */
+#define _PCNT_IFC_RESETVALUE               0x00000000UL                     /**< Default value for PCNT_IFC */
+#define _PCNT_IFC_MASK                     0x0000003FUL                     /**< Mask for PCNT_IFC */
+#define PCNT_IFC_UF                        (0x1UL << 0)                     /**< Clear UF Interrupt Flag */
+#define _PCNT_IFC_UF_SHIFT                 0                                /**< Shift value for PCNT_UF */
+#define _PCNT_IFC_UF_MASK                  0x1UL                            /**< Bit mask for PCNT_UF */
+#define _PCNT_IFC_UF_DEFAULT               0x00000000UL                     /**< Mode DEFAULT for PCNT_IFC */
+#define PCNT_IFC_UF_DEFAULT                (_PCNT_IFC_UF_DEFAULT << 0)      /**< Shifted mode DEFAULT for PCNT_IFC */
+#define PCNT_IFC_OF                        (0x1UL << 1)                     /**< Clear OF Interrupt Flag */
+#define _PCNT_IFC_OF_SHIFT                 1                                /**< Shift value for PCNT_OF */
+#define _PCNT_IFC_OF_MASK                  0x2UL                            /**< Bit mask for PCNT_OF */
+#define _PCNT_IFC_OF_DEFAULT               0x00000000UL                     /**< Mode DEFAULT for PCNT_IFC */
+#define PCNT_IFC_OF_DEFAULT                (_PCNT_IFC_OF_DEFAULT << 1)      /**< Shifted mode DEFAULT for PCNT_IFC */
+#define PCNT_IFC_DIRCNG                    (0x1UL << 2)                     /**< Clear DIRCNG Interrupt Flag */
+#define _PCNT_IFC_DIRCNG_SHIFT             2                                /**< Shift value for PCNT_DIRCNG */
+#define _PCNT_IFC_DIRCNG_MASK              0x4UL                            /**< Bit mask for PCNT_DIRCNG */
+#define _PCNT_IFC_DIRCNG_DEFAULT           0x00000000UL                     /**< Mode DEFAULT for PCNT_IFC */
+#define PCNT_IFC_DIRCNG_DEFAULT            (_PCNT_IFC_DIRCNG_DEFAULT << 2)  /**< Shifted mode DEFAULT for PCNT_IFC */
+#define PCNT_IFC_AUXOF                     (0x1UL << 3)                     /**< Clear AUXOF Interrupt Flag */
+#define _PCNT_IFC_AUXOF_SHIFT              3                                /**< Shift value for PCNT_AUXOF */
+#define _PCNT_IFC_AUXOF_MASK               0x8UL                            /**< Bit mask for PCNT_AUXOF */
+#define _PCNT_IFC_AUXOF_DEFAULT            0x00000000UL                     /**< Mode DEFAULT for PCNT_IFC */
+#define PCNT_IFC_AUXOF_DEFAULT             (_PCNT_IFC_AUXOF_DEFAULT << 3)   /**< Shifted mode DEFAULT for PCNT_IFC */
+#define PCNT_IFC_TCC                       (0x1UL << 4)                     /**< Clear TCC Interrupt Flag */
+#define _PCNT_IFC_TCC_SHIFT                4                                /**< Shift value for PCNT_TCC */
+#define _PCNT_IFC_TCC_MASK                 0x10UL                           /**< Bit mask for PCNT_TCC */
+#define _PCNT_IFC_TCC_DEFAULT              0x00000000UL                     /**< Mode DEFAULT for PCNT_IFC */
+#define PCNT_IFC_TCC_DEFAULT               (_PCNT_IFC_TCC_DEFAULT << 4)     /**< Shifted mode DEFAULT for PCNT_IFC */
+#define PCNT_IFC_OQSTERR                   (0x1UL << 5)                     /**< Clear OQSTERR Interrupt Flag */
+#define _PCNT_IFC_OQSTERR_SHIFT            5                                /**< Shift value for PCNT_OQSTERR */
+#define _PCNT_IFC_OQSTERR_MASK             0x20UL                           /**< Bit mask for PCNT_OQSTERR */
+#define _PCNT_IFC_OQSTERR_DEFAULT          0x00000000UL                     /**< Mode DEFAULT for PCNT_IFC */
+#define PCNT_IFC_OQSTERR_DEFAULT           (_PCNT_IFC_OQSTERR_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_IFC */
+
+/* Bit fields for PCNT IEN */
+#define _PCNT_IEN_RESETVALUE               0x00000000UL                     /**< Default value for PCNT_IEN */
+#define _PCNT_IEN_MASK                     0x0000003FUL                     /**< Mask for PCNT_IEN */
+#define PCNT_IEN_UF                        (0x1UL << 0)                     /**< UF Interrupt Enable */
+#define _PCNT_IEN_UF_SHIFT                 0                                /**< Shift value for PCNT_UF */
+#define _PCNT_IEN_UF_MASK                  0x1UL                            /**< Bit mask for PCNT_UF */
+#define _PCNT_IEN_UF_DEFAULT               0x00000000UL                     /**< Mode DEFAULT for PCNT_IEN */
+#define PCNT_IEN_UF_DEFAULT                (_PCNT_IEN_UF_DEFAULT << 0)      /**< Shifted mode DEFAULT for PCNT_IEN */
+#define PCNT_IEN_OF                        (0x1UL << 1)                     /**< OF Interrupt Enable */
+#define _PCNT_IEN_OF_SHIFT                 1                                /**< Shift value for PCNT_OF */
+#define _PCNT_IEN_OF_MASK                  0x2UL                            /**< Bit mask for PCNT_OF */
+#define _PCNT_IEN_OF_DEFAULT               0x00000000UL                     /**< Mode DEFAULT for PCNT_IEN */
+#define PCNT_IEN_OF_DEFAULT                (_PCNT_IEN_OF_DEFAULT << 1)      /**< Shifted mode DEFAULT for PCNT_IEN */
+#define PCNT_IEN_DIRCNG                    (0x1UL << 2)                     /**< DIRCNG Interrupt Enable */
+#define _PCNT_IEN_DIRCNG_SHIFT             2                                /**< Shift value for PCNT_DIRCNG */
+#define _PCNT_IEN_DIRCNG_MASK              0x4UL                            /**< Bit mask for PCNT_DIRCNG */
+#define _PCNT_IEN_DIRCNG_DEFAULT           0x00000000UL                     /**< Mode DEFAULT for PCNT_IEN */
+#define PCNT_IEN_DIRCNG_DEFAULT            (_PCNT_IEN_DIRCNG_DEFAULT << 2)  /**< Shifted mode DEFAULT for PCNT_IEN */
+#define PCNT_IEN_AUXOF                     (0x1UL << 3)                     /**< AUXOF Interrupt Enable */
+#define _PCNT_IEN_AUXOF_SHIFT              3                                /**< Shift value for PCNT_AUXOF */
+#define _PCNT_IEN_AUXOF_MASK               0x8UL                            /**< Bit mask for PCNT_AUXOF */
+#define _PCNT_IEN_AUXOF_DEFAULT            0x00000000UL                     /**< Mode DEFAULT for PCNT_IEN */
+#define PCNT_IEN_AUXOF_DEFAULT             (_PCNT_IEN_AUXOF_DEFAULT << 3)   /**< Shifted mode DEFAULT for PCNT_IEN */
+#define PCNT_IEN_TCC                       (0x1UL << 4)                     /**< TCC Interrupt Enable */
+#define _PCNT_IEN_TCC_SHIFT                4                                /**< Shift value for PCNT_TCC */
+#define _PCNT_IEN_TCC_MASK                 0x10UL                           /**< Bit mask for PCNT_TCC */
+#define _PCNT_IEN_TCC_DEFAULT              0x00000000UL                     /**< Mode DEFAULT for PCNT_IEN */
+#define PCNT_IEN_TCC_DEFAULT               (_PCNT_IEN_TCC_DEFAULT << 4)     /**< Shifted mode DEFAULT for PCNT_IEN */
+#define PCNT_IEN_OQSTERR                   (0x1UL << 5)                     /**< OQSTERR Interrupt Enable */
+#define _PCNT_IEN_OQSTERR_SHIFT            5                                /**< Shift value for PCNT_OQSTERR */
+#define _PCNT_IEN_OQSTERR_MASK             0x20UL                           /**< Bit mask for PCNT_OQSTERR */
+#define _PCNT_IEN_OQSTERR_DEFAULT          0x00000000UL                     /**< Mode DEFAULT for PCNT_IEN */
+#define PCNT_IEN_OQSTERR_DEFAULT           (_PCNT_IEN_OQSTERR_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_IEN */
+
+/* Bit fields for PCNT ROUTELOC0 */
+#define _PCNT_ROUTELOC0_RESETVALUE         0x00000000UL                           /**< Default value for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_MASK               0x00001F1FUL                           /**< Mask for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S0INLOC_SHIFT      0                                      /**< Shift value for PCNT_S0INLOC */
+#define _PCNT_ROUTELOC0_S0INLOC_MASK       0x1FUL                                 /**< Bit mask for PCNT_S0INLOC */
+#define _PCNT_ROUTELOC0_S0INLOC_LOC0       0x00000000UL                           /**< Mode LOC0 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S0INLOC_DEFAULT    0x00000000UL                           /**< Mode DEFAULT for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S0INLOC_LOC1       0x00000001UL                           /**< Mode LOC1 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S0INLOC_LOC2       0x00000002UL                           /**< Mode LOC2 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S0INLOC_LOC3       0x00000003UL                           /**< Mode LOC3 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S0INLOC_LOC4       0x00000004UL                           /**< Mode LOC4 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S0INLOC_LOC5       0x00000005UL                           /**< Mode LOC5 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S0INLOC_LOC6       0x00000006UL                           /**< Mode LOC6 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S0INLOC_LOC7       0x00000007UL                           /**< Mode LOC7 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S0INLOC_LOC8       0x00000008UL                           /**< Mode LOC8 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S0INLOC_LOC9       0x00000009UL                           /**< Mode LOC9 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S0INLOC_LOC10      0x0000000AUL                           /**< Mode LOC10 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S0INLOC_LOC11      0x0000000BUL                           /**< Mode LOC11 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S0INLOC_LOC12      0x0000000CUL                           /**< Mode LOC12 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S0INLOC_LOC13      0x0000000DUL                           /**< Mode LOC13 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S0INLOC_LOC14      0x0000000EUL                           /**< Mode LOC14 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S0INLOC_LOC15      0x0000000FUL                           /**< Mode LOC15 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S0INLOC_LOC16      0x00000010UL                           /**< Mode LOC16 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S0INLOC_LOC17      0x00000011UL                           /**< Mode LOC17 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S0INLOC_LOC18      0x00000012UL                           /**< Mode LOC18 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S0INLOC_LOC19      0x00000013UL                           /**< Mode LOC19 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S0INLOC_LOC20      0x00000014UL                           /**< Mode LOC20 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S0INLOC_LOC21      0x00000015UL                           /**< Mode LOC21 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S0INLOC_LOC22      0x00000016UL                           /**< Mode LOC22 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S0INLOC_LOC23      0x00000017UL                           /**< Mode LOC23 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S0INLOC_LOC24      0x00000018UL                           /**< Mode LOC24 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S0INLOC_LOC25      0x00000019UL                           /**< Mode LOC25 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S0INLOC_LOC26      0x0000001AUL                           /**< Mode LOC26 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S0INLOC_LOC27      0x0000001BUL                           /**< Mode LOC27 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S0INLOC_LOC28      0x0000001CUL                           /**< Mode LOC28 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S0INLOC_LOC29      0x0000001DUL                           /**< Mode LOC29 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S0INLOC_LOC30      0x0000001EUL                           /**< Mode LOC30 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S0INLOC_LOC31      0x0000001FUL                           /**< Mode LOC31 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S0INLOC_LOC0        (_PCNT_ROUTELOC0_S0INLOC_LOC0 << 0)    /**< Shifted mode LOC0 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S0INLOC_DEFAULT     (_PCNT_ROUTELOC0_S0INLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S0INLOC_LOC1        (_PCNT_ROUTELOC0_S0INLOC_LOC1 << 0)    /**< Shifted mode LOC1 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S0INLOC_LOC2        (_PCNT_ROUTELOC0_S0INLOC_LOC2 << 0)    /**< Shifted mode LOC2 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S0INLOC_LOC3        (_PCNT_ROUTELOC0_S0INLOC_LOC3 << 0)    /**< Shifted mode LOC3 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S0INLOC_LOC4        (_PCNT_ROUTELOC0_S0INLOC_LOC4 << 0)    /**< Shifted mode LOC4 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S0INLOC_LOC5        (_PCNT_ROUTELOC0_S0INLOC_LOC5 << 0)    /**< Shifted mode LOC5 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S0INLOC_LOC6        (_PCNT_ROUTELOC0_S0INLOC_LOC6 << 0)    /**< Shifted mode LOC6 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S0INLOC_LOC7        (_PCNT_ROUTELOC0_S0INLOC_LOC7 << 0)    /**< Shifted mode LOC7 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S0INLOC_LOC8        (_PCNT_ROUTELOC0_S0INLOC_LOC8 << 0)    /**< Shifted mode LOC8 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S0INLOC_LOC9        (_PCNT_ROUTELOC0_S0INLOC_LOC9 << 0)    /**< Shifted mode LOC9 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S0INLOC_LOC10       (_PCNT_ROUTELOC0_S0INLOC_LOC10 << 0)   /**< Shifted mode LOC10 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S0INLOC_LOC11       (_PCNT_ROUTELOC0_S0INLOC_LOC11 << 0)   /**< Shifted mode LOC11 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S0INLOC_LOC12       (_PCNT_ROUTELOC0_S0INLOC_LOC12 << 0)   /**< Shifted mode LOC12 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S0INLOC_LOC13       (_PCNT_ROUTELOC0_S0INLOC_LOC13 << 0)   /**< Shifted mode LOC13 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S0INLOC_LOC14       (_PCNT_ROUTELOC0_S0INLOC_LOC14 << 0)   /**< Shifted mode LOC14 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S0INLOC_LOC15       (_PCNT_ROUTELOC0_S0INLOC_LOC15 << 0)   /**< Shifted mode LOC15 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S0INLOC_LOC16       (_PCNT_ROUTELOC0_S0INLOC_LOC16 << 0)   /**< Shifted mode LOC16 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S0INLOC_LOC17       (_PCNT_ROUTELOC0_S0INLOC_LOC17 << 0)   /**< Shifted mode LOC17 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S0INLOC_LOC18       (_PCNT_ROUTELOC0_S0INLOC_LOC18 << 0)   /**< Shifted mode LOC18 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S0INLOC_LOC19       (_PCNT_ROUTELOC0_S0INLOC_LOC19 << 0)   /**< Shifted mode LOC19 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S0INLOC_LOC20       (_PCNT_ROUTELOC0_S0INLOC_LOC20 << 0)   /**< Shifted mode LOC20 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S0INLOC_LOC21       (_PCNT_ROUTELOC0_S0INLOC_LOC21 << 0)   /**< Shifted mode LOC21 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S0INLOC_LOC22       (_PCNT_ROUTELOC0_S0INLOC_LOC22 << 0)   /**< Shifted mode LOC22 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S0INLOC_LOC23       (_PCNT_ROUTELOC0_S0INLOC_LOC23 << 0)   /**< Shifted mode LOC23 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S0INLOC_LOC24       (_PCNT_ROUTELOC0_S0INLOC_LOC24 << 0)   /**< Shifted mode LOC24 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S0INLOC_LOC25       (_PCNT_ROUTELOC0_S0INLOC_LOC25 << 0)   /**< Shifted mode LOC25 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S0INLOC_LOC26       (_PCNT_ROUTELOC0_S0INLOC_LOC26 << 0)   /**< Shifted mode LOC26 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S0INLOC_LOC27       (_PCNT_ROUTELOC0_S0INLOC_LOC27 << 0)   /**< Shifted mode LOC27 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S0INLOC_LOC28       (_PCNT_ROUTELOC0_S0INLOC_LOC28 << 0)   /**< Shifted mode LOC28 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S0INLOC_LOC29       (_PCNT_ROUTELOC0_S0INLOC_LOC29 << 0)   /**< Shifted mode LOC29 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S0INLOC_LOC30       (_PCNT_ROUTELOC0_S0INLOC_LOC30 << 0)   /**< Shifted mode LOC30 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S0INLOC_LOC31       (_PCNT_ROUTELOC0_S0INLOC_LOC31 << 0)   /**< Shifted mode LOC31 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S1INLOC_SHIFT      8                                      /**< Shift value for PCNT_S1INLOC */
+#define _PCNT_ROUTELOC0_S1INLOC_MASK       0x1F00UL                               /**< Bit mask for PCNT_S1INLOC */
+#define _PCNT_ROUTELOC0_S1INLOC_LOC0       0x00000000UL                           /**< Mode LOC0 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S1INLOC_DEFAULT    0x00000000UL                           /**< Mode DEFAULT for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S1INLOC_LOC1       0x00000001UL                           /**< Mode LOC1 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S1INLOC_LOC2       0x00000002UL                           /**< Mode LOC2 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S1INLOC_LOC3       0x00000003UL                           /**< Mode LOC3 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S1INLOC_LOC4       0x00000004UL                           /**< Mode LOC4 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S1INLOC_LOC5       0x00000005UL                           /**< Mode LOC5 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S1INLOC_LOC6       0x00000006UL                           /**< Mode LOC6 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S1INLOC_LOC7       0x00000007UL                           /**< Mode LOC7 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S1INLOC_LOC8       0x00000008UL                           /**< Mode LOC8 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S1INLOC_LOC9       0x00000009UL                           /**< Mode LOC9 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S1INLOC_LOC10      0x0000000AUL                           /**< Mode LOC10 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S1INLOC_LOC11      0x0000000BUL                           /**< Mode LOC11 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S1INLOC_LOC12      0x0000000CUL                           /**< Mode LOC12 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S1INLOC_LOC13      0x0000000DUL                           /**< Mode LOC13 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S1INLOC_LOC14      0x0000000EUL                           /**< Mode LOC14 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S1INLOC_LOC15      0x0000000FUL                           /**< Mode LOC15 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S1INLOC_LOC16      0x00000010UL                           /**< Mode LOC16 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S1INLOC_LOC17      0x00000011UL                           /**< Mode LOC17 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S1INLOC_LOC18      0x00000012UL                           /**< Mode LOC18 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S1INLOC_LOC19      0x00000013UL                           /**< Mode LOC19 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S1INLOC_LOC20      0x00000014UL                           /**< Mode LOC20 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S1INLOC_LOC21      0x00000015UL                           /**< Mode LOC21 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S1INLOC_LOC22      0x00000016UL                           /**< Mode LOC22 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S1INLOC_LOC23      0x00000017UL                           /**< Mode LOC23 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S1INLOC_LOC24      0x00000018UL                           /**< Mode LOC24 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S1INLOC_LOC25      0x00000019UL                           /**< Mode LOC25 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S1INLOC_LOC26      0x0000001AUL                           /**< Mode LOC26 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S1INLOC_LOC27      0x0000001BUL                           /**< Mode LOC27 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S1INLOC_LOC28      0x0000001CUL                           /**< Mode LOC28 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S1INLOC_LOC29      0x0000001DUL                           /**< Mode LOC29 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S1INLOC_LOC30      0x0000001EUL                           /**< Mode LOC30 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S1INLOC_LOC31      0x0000001FUL                           /**< Mode LOC31 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S1INLOC_LOC0        (_PCNT_ROUTELOC0_S1INLOC_LOC0 << 8)    /**< Shifted mode LOC0 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S1INLOC_DEFAULT     (_PCNT_ROUTELOC0_S1INLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S1INLOC_LOC1        (_PCNT_ROUTELOC0_S1INLOC_LOC1 << 8)    /**< Shifted mode LOC1 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S1INLOC_LOC2        (_PCNT_ROUTELOC0_S1INLOC_LOC2 << 8)    /**< Shifted mode LOC2 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S1INLOC_LOC3        (_PCNT_ROUTELOC0_S1INLOC_LOC3 << 8)    /**< Shifted mode LOC3 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S1INLOC_LOC4        (_PCNT_ROUTELOC0_S1INLOC_LOC4 << 8)    /**< Shifted mode LOC4 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S1INLOC_LOC5        (_PCNT_ROUTELOC0_S1INLOC_LOC5 << 8)    /**< Shifted mode LOC5 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S1INLOC_LOC6        (_PCNT_ROUTELOC0_S1INLOC_LOC6 << 8)    /**< Shifted mode LOC6 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S1INLOC_LOC7        (_PCNT_ROUTELOC0_S1INLOC_LOC7 << 8)    /**< Shifted mode LOC7 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S1INLOC_LOC8        (_PCNT_ROUTELOC0_S1INLOC_LOC8 << 8)    /**< Shifted mode LOC8 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S1INLOC_LOC9        (_PCNT_ROUTELOC0_S1INLOC_LOC9 << 8)    /**< Shifted mode LOC9 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S1INLOC_LOC10       (_PCNT_ROUTELOC0_S1INLOC_LOC10 << 8)   /**< Shifted mode LOC10 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S1INLOC_LOC11       (_PCNT_ROUTELOC0_S1INLOC_LOC11 << 8)   /**< Shifted mode LOC11 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S1INLOC_LOC12       (_PCNT_ROUTELOC0_S1INLOC_LOC12 << 8)   /**< Shifted mode LOC12 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S1INLOC_LOC13       (_PCNT_ROUTELOC0_S1INLOC_LOC13 << 8)   /**< Shifted mode LOC13 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S1INLOC_LOC14       (_PCNT_ROUTELOC0_S1INLOC_LOC14 << 8)   /**< Shifted mode LOC14 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S1INLOC_LOC15       (_PCNT_ROUTELOC0_S1INLOC_LOC15 << 8)   /**< Shifted mode LOC15 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S1INLOC_LOC16       (_PCNT_ROUTELOC0_S1INLOC_LOC16 << 8)   /**< Shifted mode LOC16 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S1INLOC_LOC17       (_PCNT_ROUTELOC0_S1INLOC_LOC17 << 8)   /**< Shifted mode LOC17 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S1INLOC_LOC18       (_PCNT_ROUTELOC0_S1INLOC_LOC18 << 8)   /**< Shifted mode LOC18 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S1INLOC_LOC19       (_PCNT_ROUTELOC0_S1INLOC_LOC19 << 8)   /**< Shifted mode LOC19 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S1INLOC_LOC20       (_PCNT_ROUTELOC0_S1INLOC_LOC20 << 8)   /**< Shifted mode LOC20 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S1INLOC_LOC21       (_PCNT_ROUTELOC0_S1INLOC_LOC21 << 8)   /**< Shifted mode LOC21 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S1INLOC_LOC22       (_PCNT_ROUTELOC0_S1INLOC_LOC22 << 8)   /**< Shifted mode LOC22 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S1INLOC_LOC23       (_PCNT_ROUTELOC0_S1INLOC_LOC23 << 8)   /**< Shifted mode LOC23 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S1INLOC_LOC24       (_PCNT_ROUTELOC0_S1INLOC_LOC24 << 8)   /**< Shifted mode LOC24 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S1INLOC_LOC25       (_PCNT_ROUTELOC0_S1INLOC_LOC25 << 8)   /**< Shifted mode LOC25 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S1INLOC_LOC26       (_PCNT_ROUTELOC0_S1INLOC_LOC26 << 8)   /**< Shifted mode LOC26 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S1INLOC_LOC27       (_PCNT_ROUTELOC0_S1INLOC_LOC27 << 8)   /**< Shifted mode LOC27 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S1INLOC_LOC28       (_PCNT_ROUTELOC0_S1INLOC_LOC28 << 8)   /**< Shifted mode LOC28 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S1INLOC_LOC29       (_PCNT_ROUTELOC0_S1INLOC_LOC29 << 8)   /**< Shifted mode LOC29 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S1INLOC_LOC30       (_PCNT_ROUTELOC0_S1INLOC_LOC30 << 8)   /**< Shifted mode LOC30 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S1INLOC_LOC31       (_PCNT_ROUTELOC0_S1INLOC_LOC31 << 8)   /**< Shifted mode LOC31 for PCNT_ROUTELOC0 */
+
+/* Bit fields for PCNT FREEZE */
+#define _PCNT_FREEZE_RESETVALUE            0x00000000UL                          /**< Default value for PCNT_FREEZE */
+#define _PCNT_FREEZE_MASK                  0x00000001UL                          /**< Mask for PCNT_FREEZE */
+#define PCNT_FREEZE_REGFREEZE              (0x1UL << 0)                          /**< Register Update Freeze */
+#define _PCNT_FREEZE_REGFREEZE_SHIFT       0                                     /**< Shift value for PCNT_REGFREEZE */
+#define _PCNT_FREEZE_REGFREEZE_MASK        0x1UL                                 /**< Bit mask for PCNT_REGFREEZE */
+#define _PCNT_FREEZE_REGFREEZE_DEFAULT     0x00000000UL                          /**< Mode DEFAULT for PCNT_FREEZE */
+#define _PCNT_FREEZE_REGFREEZE_UPDATE      0x00000000UL                          /**< Mode UPDATE for PCNT_FREEZE */
+#define _PCNT_FREEZE_REGFREEZE_FREEZE      0x00000001UL                          /**< Mode FREEZE for PCNT_FREEZE */
+#define PCNT_FREEZE_REGFREEZE_DEFAULT      (_PCNT_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_FREEZE */
+#define PCNT_FREEZE_REGFREEZE_UPDATE       (_PCNT_FREEZE_REGFREEZE_UPDATE << 0)  /**< Shifted mode UPDATE for PCNT_FREEZE */
+#define PCNT_FREEZE_REGFREEZE_FREEZE       (_PCNT_FREEZE_REGFREEZE_FREEZE << 0)  /**< Shifted mode FREEZE for PCNT_FREEZE */
+
+/* Bit fields for PCNT SYNCBUSY */
+#define _PCNT_SYNCBUSY_RESETVALUE          0x00000000UL                         /**< Default value for PCNT_SYNCBUSY */
+#define _PCNT_SYNCBUSY_MASK                0x0000000FUL                         /**< Mask for PCNT_SYNCBUSY */
+#define PCNT_SYNCBUSY_CTRL                 (0x1UL << 0)                         /**< CTRL Register Busy */
+#define _PCNT_SYNCBUSY_CTRL_SHIFT          0                                    /**< Shift value for PCNT_CTRL */
+#define _PCNT_SYNCBUSY_CTRL_MASK           0x1UL                                /**< Bit mask for PCNT_CTRL */
+#define _PCNT_SYNCBUSY_CTRL_DEFAULT        0x00000000UL                         /**< Mode DEFAULT for PCNT_SYNCBUSY */
+#define PCNT_SYNCBUSY_CTRL_DEFAULT         (_PCNT_SYNCBUSY_CTRL_DEFAULT << 0)   /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */
+#define PCNT_SYNCBUSY_CMD                  (0x1UL << 1)                         /**< CMD Register Busy */
+#define _PCNT_SYNCBUSY_CMD_SHIFT           1                                    /**< Shift value for PCNT_CMD */
+#define _PCNT_SYNCBUSY_CMD_MASK            0x2UL                                /**< Bit mask for PCNT_CMD */
+#define _PCNT_SYNCBUSY_CMD_DEFAULT         0x00000000UL                         /**< Mode DEFAULT for PCNT_SYNCBUSY */
+#define PCNT_SYNCBUSY_CMD_DEFAULT          (_PCNT_SYNCBUSY_CMD_DEFAULT << 1)    /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */
+#define PCNT_SYNCBUSY_TOPB                 (0x1UL << 2)                         /**< TOPB Register Busy */
+#define _PCNT_SYNCBUSY_TOPB_SHIFT          2                                    /**< Shift value for PCNT_TOPB */
+#define _PCNT_SYNCBUSY_TOPB_MASK           0x4UL                                /**< Bit mask for PCNT_TOPB */
+#define _PCNT_SYNCBUSY_TOPB_DEFAULT        0x00000000UL                         /**< Mode DEFAULT for PCNT_SYNCBUSY */
+#define PCNT_SYNCBUSY_TOPB_DEFAULT         (_PCNT_SYNCBUSY_TOPB_DEFAULT << 2)   /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */
+#define PCNT_SYNCBUSY_OVSCFG               (0x1UL << 3)                         /**< OVSCFG Register Busy */
+#define _PCNT_SYNCBUSY_OVSCFG_SHIFT        3                                    /**< Shift value for PCNT_OVSCFG */
+#define _PCNT_SYNCBUSY_OVSCFG_MASK         0x8UL                                /**< Bit mask for PCNT_OVSCFG */
+#define _PCNT_SYNCBUSY_OVSCFG_DEFAULT      0x00000000UL                         /**< Mode DEFAULT for PCNT_SYNCBUSY */
+#define PCNT_SYNCBUSY_OVSCFG_DEFAULT       (_PCNT_SYNCBUSY_OVSCFG_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */
+
+/* Bit fields for PCNT AUXCNT */
+#define _PCNT_AUXCNT_RESETVALUE            0x00000000UL                       /**< Default value for PCNT_AUXCNT */
+#define _PCNT_AUXCNT_MASK                  0x0000FFFFUL                       /**< Mask for PCNT_AUXCNT */
+#define _PCNT_AUXCNT_AUXCNT_SHIFT          0                                  /**< Shift value for PCNT_AUXCNT */
+#define _PCNT_AUXCNT_AUXCNT_MASK           0xFFFFUL                           /**< Bit mask for PCNT_AUXCNT */
+#define _PCNT_AUXCNT_AUXCNT_DEFAULT        0x00000000UL                       /**< Mode DEFAULT for PCNT_AUXCNT */
+#define PCNT_AUXCNT_AUXCNT_DEFAULT         (_PCNT_AUXCNT_AUXCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_AUXCNT */
+
+/* Bit fields for PCNT INPUT */
+#define _PCNT_INPUT_RESETVALUE             0x00000000UL                        /**< Default value for PCNT_INPUT */
+#define _PCNT_INPUT_MASK                   0x00000BEFUL                        /**< Mask for PCNT_INPUT */
+#define _PCNT_INPUT_S0PRSSEL_SHIFT         0                                   /**< Shift value for PCNT_S0PRSSEL */
+#define _PCNT_INPUT_S0PRSSEL_MASK          0xFUL                               /**< Bit mask for PCNT_S0PRSSEL */
+#define _PCNT_INPUT_S0PRSSEL_DEFAULT       0x00000000UL                        /**< Mode DEFAULT for PCNT_INPUT */
+#define _PCNT_INPUT_S0PRSSEL_PRSCH0        0x00000000UL                        /**< Mode PRSCH0 for PCNT_INPUT */
+#define _PCNT_INPUT_S0PRSSEL_PRSCH1        0x00000001UL                        /**< Mode PRSCH1 for PCNT_INPUT */
+#define _PCNT_INPUT_S0PRSSEL_PRSCH2        0x00000002UL                        /**< Mode PRSCH2 for PCNT_INPUT */
+#define _PCNT_INPUT_S0PRSSEL_PRSCH3        0x00000003UL                        /**< Mode PRSCH3 for PCNT_INPUT */
+#define _PCNT_INPUT_S0PRSSEL_PRSCH4        0x00000004UL                        /**< Mode PRSCH4 for PCNT_INPUT */
+#define _PCNT_INPUT_S0PRSSEL_PRSCH5        0x00000005UL                        /**< Mode PRSCH5 for PCNT_INPUT */
+#define _PCNT_INPUT_S0PRSSEL_PRSCH6        0x00000006UL                        /**< Mode PRSCH6 for PCNT_INPUT */
+#define _PCNT_INPUT_S0PRSSEL_PRSCH7        0x00000007UL                        /**< Mode PRSCH7 for PCNT_INPUT */
+#define _PCNT_INPUT_S0PRSSEL_PRSCH8        0x00000008UL                        /**< Mode PRSCH8 for PCNT_INPUT */
+#define _PCNT_INPUT_S0PRSSEL_PRSCH9        0x00000009UL                        /**< Mode PRSCH9 for PCNT_INPUT */
+#define _PCNT_INPUT_S0PRSSEL_PRSCH10       0x0000000AUL                        /**< Mode PRSCH10 for PCNT_INPUT */
+#define _PCNT_INPUT_S0PRSSEL_PRSCH11       0x0000000BUL                        /**< Mode PRSCH11 for PCNT_INPUT */
+#define PCNT_INPUT_S0PRSSEL_DEFAULT        (_PCNT_INPUT_S0PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_INPUT */
+#define PCNT_INPUT_S0PRSSEL_PRSCH0         (_PCNT_INPUT_S0PRSSEL_PRSCH0 << 0)  /**< Shifted mode PRSCH0 for PCNT_INPUT */
+#define PCNT_INPUT_S0PRSSEL_PRSCH1         (_PCNT_INPUT_S0PRSSEL_PRSCH1 << 0)  /**< Shifted mode PRSCH1 for PCNT_INPUT */
+#define PCNT_INPUT_S0PRSSEL_PRSCH2         (_PCNT_INPUT_S0PRSSEL_PRSCH2 << 0)  /**< Shifted mode PRSCH2 for PCNT_INPUT */
+#define PCNT_INPUT_S0PRSSEL_PRSCH3         (_PCNT_INPUT_S0PRSSEL_PRSCH3 << 0)  /**< Shifted mode PRSCH3 for PCNT_INPUT */
+#define PCNT_INPUT_S0PRSSEL_PRSCH4         (_PCNT_INPUT_S0PRSSEL_PRSCH4 << 0)  /**< Shifted mode PRSCH4 for PCNT_INPUT */
+#define PCNT_INPUT_S0PRSSEL_PRSCH5         (_PCNT_INPUT_S0PRSSEL_PRSCH5 << 0)  /**< Shifted mode PRSCH5 for PCNT_INPUT */
+#define PCNT_INPUT_S0PRSSEL_PRSCH6         (_PCNT_INPUT_S0PRSSEL_PRSCH6 << 0)  /**< Shifted mode PRSCH6 for PCNT_INPUT */
+#define PCNT_INPUT_S0PRSSEL_PRSCH7         (_PCNT_INPUT_S0PRSSEL_PRSCH7 << 0)  /**< Shifted mode PRSCH7 for PCNT_INPUT */
+#define PCNT_INPUT_S0PRSSEL_PRSCH8         (_PCNT_INPUT_S0PRSSEL_PRSCH8 << 0)  /**< Shifted mode PRSCH8 for PCNT_INPUT */
+#define PCNT_INPUT_S0PRSSEL_PRSCH9         (_PCNT_INPUT_S0PRSSEL_PRSCH9 << 0)  /**< Shifted mode PRSCH9 for PCNT_INPUT */
+#define PCNT_INPUT_S0PRSSEL_PRSCH10        (_PCNT_INPUT_S0PRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for PCNT_INPUT */
+#define PCNT_INPUT_S0PRSSEL_PRSCH11        (_PCNT_INPUT_S0PRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for PCNT_INPUT */
+#define PCNT_INPUT_S0PRSEN                 (0x1UL << 5)                        /**< S0IN PRS Enable */
+#define _PCNT_INPUT_S0PRSEN_SHIFT          5                                   /**< Shift value for PCNT_S0PRSEN */
+#define _PCNT_INPUT_S0PRSEN_MASK           0x20UL                              /**< Bit mask for PCNT_S0PRSEN */
+#define _PCNT_INPUT_S0PRSEN_DEFAULT        0x00000000UL                        /**< Mode DEFAULT for PCNT_INPUT */
+#define PCNT_INPUT_S0PRSEN_DEFAULT         (_PCNT_INPUT_S0PRSEN_DEFAULT << 5)  /**< Shifted mode DEFAULT for PCNT_INPUT */
+#define _PCNT_INPUT_S1PRSSEL_SHIFT         6                                   /**< Shift value for PCNT_S1PRSSEL */
+#define _PCNT_INPUT_S1PRSSEL_MASK          0x3C0UL                             /**< Bit mask for PCNT_S1PRSSEL */
+#define _PCNT_INPUT_S1PRSSEL_DEFAULT       0x00000000UL                        /**< Mode DEFAULT for PCNT_INPUT */
+#define _PCNT_INPUT_S1PRSSEL_PRSCH0        0x00000000UL                        /**< Mode PRSCH0 for PCNT_INPUT */
+#define _PCNT_INPUT_S1PRSSEL_PRSCH1        0x00000001UL                        /**< Mode PRSCH1 for PCNT_INPUT */
+#define _PCNT_INPUT_S1PRSSEL_PRSCH2        0x00000002UL                        /**< Mode PRSCH2 for PCNT_INPUT */
+#define _PCNT_INPUT_S1PRSSEL_PRSCH3        0x00000003UL                        /**< Mode PRSCH3 for PCNT_INPUT */
+#define _PCNT_INPUT_S1PRSSEL_PRSCH4        0x00000004UL                        /**< Mode PRSCH4 for PCNT_INPUT */
+#define _PCNT_INPUT_S1PRSSEL_PRSCH5        0x00000005UL                        /**< Mode PRSCH5 for PCNT_INPUT */
+#define _PCNT_INPUT_S1PRSSEL_PRSCH6        0x00000006UL                        /**< Mode PRSCH6 for PCNT_INPUT */
+#define _PCNT_INPUT_S1PRSSEL_PRSCH7        0x00000007UL                        /**< Mode PRSCH7 for PCNT_INPUT */
+#define _PCNT_INPUT_S1PRSSEL_PRSCH8        0x00000008UL                        /**< Mode PRSCH8 for PCNT_INPUT */
+#define _PCNT_INPUT_S1PRSSEL_PRSCH9        0x00000009UL                        /**< Mode PRSCH9 for PCNT_INPUT */
+#define _PCNT_INPUT_S1PRSSEL_PRSCH10       0x0000000AUL                        /**< Mode PRSCH10 for PCNT_INPUT */
+#define _PCNT_INPUT_S1PRSSEL_PRSCH11       0x0000000BUL                        /**< Mode PRSCH11 for PCNT_INPUT */
+#define PCNT_INPUT_S1PRSSEL_DEFAULT        (_PCNT_INPUT_S1PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PCNT_INPUT */
+#define PCNT_INPUT_S1PRSSEL_PRSCH0         (_PCNT_INPUT_S1PRSSEL_PRSCH0 << 6)  /**< Shifted mode PRSCH0 for PCNT_INPUT */
+#define PCNT_INPUT_S1PRSSEL_PRSCH1         (_PCNT_INPUT_S1PRSSEL_PRSCH1 << 6)  /**< Shifted mode PRSCH1 for PCNT_INPUT */
+#define PCNT_INPUT_S1PRSSEL_PRSCH2         (_PCNT_INPUT_S1PRSSEL_PRSCH2 << 6)  /**< Shifted mode PRSCH2 for PCNT_INPUT */
+#define PCNT_INPUT_S1PRSSEL_PRSCH3         (_PCNT_INPUT_S1PRSSEL_PRSCH3 << 6)  /**< Shifted mode PRSCH3 for PCNT_INPUT */
+#define PCNT_INPUT_S1PRSSEL_PRSCH4         (_PCNT_INPUT_S1PRSSEL_PRSCH4 << 6)  /**< Shifted mode PRSCH4 for PCNT_INPUT */
+#define PCNT_INPUT_S1PRSSEL_PRSCH5         (_PCNT_INPUT_S1PRSSEL_PRSCH5 << 6)  /**< Shifted mode PRSCH5 for PCNT_INPUT */
+#define PCNT_INPUT_S1PRSSEL_PRSCH6         (_PCNT_INPUT_S1PRSSEL_PRSCH6 << 6)  /**< Shifted mode PRSCH6 for PCNT_INPUT */
+#define PCNT_INPUT_S1PRSSEL_PRSCH7         (_PCNT_INPUT_S1PRSSEL_PRSCH7 << 6)  /**< Shifted mode PRSCH7 for PCNT_INPUT */
+#define PCNT_INPUT_S1PRSSEL_PRSCH8         (_PCNT_INPUT_S1PRSSEL_PRSCH8 << 6)  /**< Shifted mode PRSCH8 for PCNT_INPUT */
+#define PCNT_INPUT_S1PRSSEL_PRSCH9         (_PCNT_INPUT_S1PRSSEL_PRSCH9 << 6)  /**< Shifted mode PRSCH9 for PCNT_INPUT */
+#define PCNT_INPUT_S1PRSSEL_PRSCH10        (_PCNT_INPUT_S1PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PCNT_INPUT */
+#define PCNT_INPUT_S1PRSSEL_PRSCH11        (_PCNT_INPUT_S1PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PCNT_INPUT */
+#define PCNT_INPUT_S1PRSEN                 (0x1UL << 11)                       /**< S1IN PRS Enable */
+#define _PCNT_INPUT_S1PRSEN_SHIFT          11                                  /**< Shift value for PCNT_S1PRSEN */
+#define _PCNT_INPUT_S1PRSEN_MASK           0x800UL                             /**< Bit mask for PCNT_S1PRSEN */
+#define _PCNT_INPUT_S1PRSEN_DEFAULT        0x00000000UL                        /**< Mode DEFAULT for PCNT_INPUT */
+#define PCNT_INPUT_S1PRSEN_DEFAULT         (_PCNT_INPUT_S1PRSEN_DEFAULT << 11) /**< Shifted mode DEFAULT for PCNT_INPUT */
+
+/* Bit fields for PCNT OVSCFG */
+#define _PCNT_OVSCFG_RESETVALUE            0x00000000UL                           /**< Default value for PCNT_OVSCFG */
+#define _PCNT_OVSCFG_MASK                  0x000010FFUL                           /**< Mask for PCNT_OVSCFG */
+#define _PCNT_OVSCFG_FILTLEN_SHIFT         0                                      /**< Shift value for PCNT_FILTLEN */
+#define _PCNT_OVSCFG_FILTLEN_MASK          0xFFUL                                 /**< Bit mask for PCNT_FILTLEN */
+#define _PCNT_OVSCFG_FILTLEN_DEFAULT       0x00000000UL                           /**< Mode DEFAULT for PCNT_OVSCFG */
+#define PCNT_OVSCFG_FILTLEN_DEFAULT        (_PCNT_OVSCFG_FILTLEN_DEFAULT << 0)    /**< Shifted mode DEFAULT for PCNT_OVSCFG */
+#define PCNT_OVSCFG_FLUTTERRM              (0x1UL << 12)                          /**< Flutter Remove */
+#define _PCNT_OVSCFG_FLUTTERRM_SHIFT       12                                     /**< Shift value for PCNT_FLUTTERRM */
+#define _PCNT_OVSCFG_FLUTTERRM_MASK        0x1000UL                               /**< Bit mask for PCNT_FLUTTERRM */
+#define _PCNT_OVSCFG_FLUTTERRM_DEFAULT     0x00000000UL                           /**< Mode DEFAULT for PCNT_OVSCFG */
+#define PCNT_OVSCFG_FLUTTERRM_DEFAULT      (_PCNT_OVSCFG_FLUTTERRM_DEFAULT << 12) /**< Shifted mode DEFAULT for PCNT_OVSCFG */
+
+/** @} End of group EFM32PG1B_PCNT */
+/** @} End of group Parts */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG_STK3401/efm32pg1b_prs.h	Fri Jan 15 07:45:16 2016 +0000
@@ -0,0 +1,951 @@
+/**************************************************************************//**
+ * @file efm32pg1b_prs.h
+ * @brief EFM32PG1B_PRS register and bit field definitions
+ * @version 4.2.0
+ ******************************************************************************
+ * @section License
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ ******************************************************************************
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software.@n
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.@n
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is
+ * providing the Software "AS IS", with no express or implied warranties of any
+ * kind, including, but not limited to, any implied warranties of
+ * merchantability or fitness for any particular purpose or warranties against
+ * infringement of any proprietary rights of a third party.
+ *
+ * Silicon Laboratories, Inc. will not be liable for any consequential,
+ * incidental, or special damages, or any other relief, or for any claim by
+ * any third party, arising from your use of this Software.
+ *
+ *****************************************************************************/
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFM32PG1B_PRS
+ * @{
+ * @brief EFM32PG1B_PRS Register Declaration
+ *****************************************************************************/
+typedef struct
+{
+  __IO uint32_t  SWPULSE;      /**< Software Pulse Register  */
+  __IO uint32_t  SWLEVEL;      /**< Software Level Register  */
+  __IO uint32_t  ROUTEPEN;     /**< I/O Routing Pin Enable Register  */
+  uint32_t       RESERVED0[1]; /**< Reserved for future use **/
+  __IO uint32_t  ROUTELOC0;    /**< I/O Routing Location Register  */
+  __IO uint32_t  ROUTELOC1;    /**< I/O Routing Location Register  */
+  __IO uint32_t  ROUTELOC2;    /**< I/O Routing Location Register  */
+
+  uint32_t       RESERVED1[1]; /**< Reserved for future use **/
+  __IO uint32_t  CTRL;         /**< Control Register  */
+  __IO uint32_t  DMAREQ0;      /**< DMA Request 0 Register  */
+  __IO uint32_t  DMAREQ1;      /**< DMA Request 1 Register  */
+  uint32_t       RESERVED2[1]; /**< Reserved for future use **/
+  __I uint32_t   PEEK;         /**< PRS Channel Values  */
+
+  uint32_t       RESERVED3[3]; /**< Reserved registers */
+  PRS_CH_TypeDef CH[12];       /**< Channel registers */
+} PRS_TypeDef;                 /** @} */
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B_PRS_BitFields
+ * @{
+ *****************************************************************************/
+
+/* Bit fields for PRS SWPULSE */
+#define _PRS_SWPULSE_RESETVALUE                0x00000000UL                           /**< Default value for PRS_SWPULSE */
+#define _PRS_SWPULSE_MASK                      0x00000FFFUL                           /**< Mask for PRS_SWPULSE */
+#define PRS_SWPULSE_CH0PULSE                   (0x1UL << 0)                           /**< Channel 0 Pulse Generation */
+#define _PRS_SWPULSE_CH0PULSE_SHIFT            0                                      /**< Shift value for PRS_CH0PULSE */
+#define _PRS_SWPULSE_CH0PULSE_MASK             0x1UL                                  /**< Bit mask for PRS_CH0PULSE */
+#define _PRS_SWPULSE_CH0PULSE_DEFAULT          0x00000000UL                           /**< Mode DEFAULT for PRS_SWPULSE */
+#define PRS_SWPULSE_CH0PULSE_DEFAULT           (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0)   /**< Shifted mode DEFAULT for PRS_SWPULSE */
+#define PRS_SWPULSE_CH1PULSE                   (0x1UL << 1)                           /**< Channel 1 Pulse Generation */
+#define _PRS_SWPULSE_CH1PULSE_SHIFT            1                                      /**< Shift value for PRS_CH1PULSE */
+#define _PRS_SWPULSE_CH1PULSE_MASK             0x2UL                                  /**< Bit mask for PRS_CH1PULSE */
+#define _PRS_SWPULSE_CH1PULSE_DEFAULT          0x00000000UL                           /**< Mode DEFAULT for PRS_SWPULSE */
+#define PRS_SWPULSE_CH1PULSE_DEFAULT           (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1)   /**< Shifted mode DEFAULT for PRS_SWPULSE */
+#define PRS_SWPULSE_CH2PULSE                   (0x1UL << 2)                           /**< Channel 2 Pulse Generation */
+#define _PRS_SWPULSE_CH2PULSE_SHIFT            2                                      /**< Shift value for PRS_CH2PULSE */
+#define _PRS_SWPULSE_CH2PULSE_MASK             0x4UL                                  /**< Bit mask for PRS_CH2PULSE */
+#define _PRS_SWPULSE_CH2PULSE_DEFAULT          0x00000000UL                           /**< Mode DEFAULT for PRS_SWPULSE */
+#define PRS_SWPULSE_CH2PULSE_DEFAULT           (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2)   /**< Shifted mode DEFAULT for PRS_SWPULSE */
+#define PRS_SWPULSE_CH3PULSE                   (0x1UL << 3)                           /**< Channel 3 Pulse Generation */
+#define _PRS_SWPULSE_CH3PULSE_SHIFT            3                                      /**< Shift value for PRS_CH3PULSE */
+#define _PRS_SWPULSE_CH3PULSE_MASK             0x8UL                                  /**< Bit mask for PRS_CH3PULSE */
+#define _PRS_SWPULSE_CH3PULSE_DEFAULT          0x00000000UL                           /**< Mode DEFAULT for PRS_SWPULSE */
+#define PRS_SWPULSE_CH3PULSE_DEFAULT           (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3)   /**< Shifted mode DEFAULT for PRS_SWPULSE */
+#define PRS_SWPULSE_CH4PULSE                   (0x1UL << 4)                           /**< Channel 4 Pulse Generation */
+#define _PRS_SWPULSE_CH4PULSE_SHIFT            4                                      /**< Shift value for PRS_CH4PULSE */
+#define _PRS_SWPULSE_CH4PULSE_MASK             0x10UL                                 /**< Bit mask for PRS_CH4PULSE */
+#define _PRS_SWPULSE_CH4PULSE_DEFAULT          0x00000000UL                           /**< Mode DEFAULT for PRS_SWPULSE */
+#define PRS_SWPULSE_CH4PULSE_DEFAULT           (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4)   /**< Shifted mode DEFAULT for PRS_SWPULSE */
+#define PRS_SWPULSE_CH5PULSE                   (0x1UL << 5)                           /**< Channel 5 Pulse Generation */
+#define _PRS_SWPULSE_CH5PULSE_SHIFT            5                                      /**< Shift value for PRS_CH5PULSE */
+#define _PRS_SWPULSE_CH5PULSE_MASK             0x20UL                                 /**< Bit mask for PRS_CH5PULSE */
+#define _PRS_SWPULSE_CH5PULSE_DEFAULT          0x00000000UL                           /**< Mode DEFAULT for PRS_SWPULSE */
+#define PRS_SWPULSE_CH5PULSE_DEFAULT           (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5)   /**< Shifted mode DEFAULT for PRS_SWPULSE */
+#define PRS_SWPULSE_CH6PULSE                   (0x1UL << 6)                           /**< Channel 6 Pulse Generation */
+#define _PRS_SWPULSE_CH6PULSE_SHIFT            6                                      /**< Shift value for PRS_CH6PULSE */
+#define _PRS_SWPULSE_CH6PULSE_MASK             0x40UL                                 /**< Bit mask for PRS_CH6PULSE */
+#define _PRS_SWPULSE_CH6PULSE_DEFAULT          0x00000000UL                           /**< Mode DEFAULT for PRS_SWPULSE */
+#define PRS_SWPULSE_CH6PULSE_DEFAULT           (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6)   /**< Shifted mode DEFAULT for PRS_SWPULSE */
+#define PRS_SWPULSE_CH7PULSE                   (0x1UL << 7)                           /**< Channel 7 Pulse Generation */
+#define _PRS_SWPULSE_CH7PULSE_SHIFT            7                                      /**< Shift value for PRS_CH7PULSE */
+#define _PRS_SWPULSE_CH7PULSE_MASK             0x80UL                                 /**< Bit mask for PRS_CH7PULSE */
+#define _PRS_SWPULSE_CH7PULSE_DEFAULT          0x00000000UL                           /**< Mode DEFAULT for PRS_SWPULSE */
+#define PRS_SWPULSE_CH7PULSE_DEFAULT           (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7)   /**< Shifted mode DEFAULT for PRS_SWPULSE */
+#define PRS_SWPULSE_CH8PULSE                   (0x1UL << 8)                           /**< Channel 8 Pulse Generation */
+#define _PRS_SWPULSE_CH8PULSE_SHIFT            8                                      /**< Shift value for PRS_CH8PULSE */
+#define _PRS_SWPULSE_CH8PULSE_MASK             0x100UL                                /**< Bit mask for PRS_CH8PULSE */
+#define _PRS_SWPULSE_CH8PULSE_DEFAULT          0x00000000UL                           /**< Mode DEFAULT for PRS_SWPULSE */
+#define PRS_SWPULSE_CH8PULSE_DEFAULT           (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8)   /**< Shifted mode DEFAULT for PRS_SWPULSE */
+#define PRS_SWPULSE_CH9PULSE                   (0x1UL << 9)                           /**< Channel 9 Pulse Generation */
+#define _PRS_SWPULSE_CH9PULSE_SHIFT            9                                      /**< Shift value for PRS_CH9PULSE */
+#define _PRS_SWPULSE_CH9PULSE_MASK             0x200UL                                /**< Bit mask for PRS_CH9PULSE */
+#define _PRS_SWPULSE_CH9PULSE_DEFAULT          0x00000000UL                           /**< Mode DEFAULT for PRS_SWPULSE */
+#define PRS_SWPULSE_CH9PULSE_DEFAULT           (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9)   /**< Shifted mode DEFAULT for PRS_SWPULSE */
+#define PRS_SWPULSE_CH10PULSE                  (0x1UL << 10)                          /**< Channel 10 Pulse Generation */
+#define _PRS_SWPULSE_CH10PULSE_SHIFT           10                                     /**< Shift value for PRS_CH10PULSE */
+#define _PRS_SWPULSE_CH10PULSE_MASK            0x400UL                                /**< Bit mask for PRS_CH10PULSE */
+#define _PRS_SWPULSE_CH10PULSE_DEFAULT         0x00000000UL                           /**< Mode DEFAULT for PRS_SWPULSE */
+#define PRS_SWPULSE_CH10PULSE_DEFAULT          (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */
+#define PRS_SWPULSE_CH11PULSE                  (0x1UL << 11)                          /**< Channel 11 Pulse Generation */
+#define _PRS_SWPULSE_CH11PULSE_SHIFT           11                                     /**< Shift value for PRS_CH11PULSE */
+#define _PRS_SWPULSE_CH11PULSE_MASK            0x800UL                                /**< Bit mask for PRS_CH11PULSE */
+#define _PRS_SWPULSE_CH11PULSE_DEFAULT         0x00000000UL                           /**< Mode DEFAULT for PRS_SWPULSE */
+#define PRS_SWPULSE_CH11PULSE_DEFAULT          (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */
+
+/* Bit fields for PRS SWLEVEL */
+#define _PRS_SWLEVEL_RESETVALUE                0x00000000UL                           /**< Default value for PRS_SWLEVEL */
+#define _PRS_SWLEVEL_MASK                      0x00000FFFUL                           /**< Mask for PRS_SWLEVEL */
+#define PRS_SWLEVEL_CH0LEVEL                   (0x1UL << 0)                           /**< Channel 0 Software Level */
+#define _PRS_SWLEVEL_CH0LEVEL_SHIFT            0                                      /**< Shift value for PRS_CH0LEVEL */
+#define _PRS_SWLEVEL_CH0LEVEL_MASK             0x1UL                                  /**< Bit mask for PRS_CH0LEVEL */
+#define _PRS_SWLEVEL_CH0LEVEL_DEFAULT          0x00000000UL                           /**< Mode DEFAULT for PRS_SWLEVEL */
+#define PRS_SWLEVEL_CH0LEVEL_DEFAULT           (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0)   /**< Shifted mode DEFAULT for PRS_SWLEVEL */
+#define PRS_SWLEVEL_CH1LEVEL                   (0x1UL << 1)                           /**< Channel 1 Software Level */
+#define _PRS_SWLEVEL_CH1LEVEL_SHIFT            1                                      /**< Shift value for PRS_CH1LEVEL */
+#define _PRS_SWLEVEL_CH1LEVEL_MASK             0x2UL                                  /**< Bit mask for PRS_CH1LEVEL */
+#define _PRS_SWLEVEL_CH1LEVEL_DEFAULT          0x00000000UL                           /**< Mode DEFAULT for PRS_SWLEVEL */
+#define PRS_SWLEVEL_CH1LEVEL_DEFAULT           (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1)   /**< Shifted mode DEFAULT for PRS_SWLEVEL */
+#define PRS_SWLEVEL_CH2LEVEL                   (0x1UL << 2)                           /**< Channel 2 Software Level */
+#define _PRS_SWLEVEL_CH2LEVEL_SHIFT            2                                      /**< Shift value for PRS_CH2LEVEL */
+#define _PRS_SWLEVEL_CH2LEVEL_MASK             0x4UL                                  /**< Bit mask for PRS_CH2LEVEL */
+#define _PRS_SWLEVEL_CH2LEVEL_DEFAULT          0x00000000UL                           /**< Mode DEFAULT for PRS_SWLEVEL */
+#define PRS_SWLEVEL_CH2LEVEL_DEFAULT           (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2)   /**< Shifted mode DEFAULT for PRS_SWLEVEL */
+#define PRS_SWLEVEL_CH3LEVEL                   (0x1UL << 3)                           /**< Channel 3 Software Level */
+#define _PRS_SWLEVEL_CH3LEVEL_SHIFT            3                                      /**< Shift value for PRS_CH3LEVEL */
+#define _PRS_SWLEVEL_CH3LEVEL_MASK             0x8UL                                  /**< Bit mask for PRS_CH3LEVEL */
+#define _PRS_SWLEVEL_CH3LEVEL_DEFAULT          0x00000000UL                           /**< Mode DEFAULT for PRS_SWLEVEL */
+#define PRS_SWLEVEL_CH3LEVEL_DEFAULT           (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3)   /**< Shifted mode DEFAULT for PRS_SWLEVEL */
+#define PRS_SWLEVEL_CH4LEVEL                   (0x1UL << 4)                           /**< Channel 4 Software Level */
+#define _PRS_SWLEVEL_CH4LEVEL_SHIFT            4                                      /**< Shift value for PRS_CH4LEVEL */
+#define _PRS_SWLEVEL_CH4LEVEL_MASK             0x10UL                                 /**< Bit mask for PRS_CH4LEVEL */
+#define _PRS_SWLEVEL_CH4LEVEL_DEFAULT          0x00000000UL                           /**< Mode DEFAULT for PRS_SWLEVEL */
+#define PRS_SWLEVEL_CH4LEVEL_DEFAULT           (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4)   /**< Shifted mode DEFAULT for PRS_SWLEVEL */
+#define PRS_SWLEVEL_CH5LEVEL                   (0x1UL << 5)                           /**< Channel 5 Software Level */
+#define _PRS_SWLEVEL_CH5LEVEL_SHIFT            5                                      /**< Shift value for PRS_CH5LEVEL */
+#define _PRS_SWLEVEL_CH5LEVEL_MASK             0x20UL                                 /**< Bit mask for PRS_CH5LEVEL */
+#define _PRS_SWLEVEL_CH5LEVEL_DEFAULT          0x00000000UL                           /**< Mode DEFAULT for PRS_SWLEVEL */
+#define PRS_SWLEVEL_CH5LEVEL_DEFAULT           (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5)   /**< Shifted mode DEFAULT for PRS_SWLEVEL */
+#define PRS_SWLEVEL_CH6LEVEL                   (0x1UL << 6)                           /**< Channel 6 Software Level */
+#define _PRS_SWLEVEL_CH6LEVEL_SHIFT            6                                      /**< Shift value for PRS_CH6LEVEL */
+#define _PRS_SWLEVEL_CH6LEVEL_MASK             0x40UL                                 /**< Bit mask for PRS_CH6LEVEL */
+#define _PRS_SWLEVEL_CH6LEVEL_DEFAULT          0x00000000UL                           /**< Mode DEFAULT for PRS_SWLEVEL */
+#define PRS_SWLEVEL_CH6LEVEL_DEFAULT           (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6)   /**< Shifted mode DEFAULT for PRS_SWLEVEL */
+#define PRS_SWLEVEL_CH7LEVEL                   (0x1UL << 7)                           /**< Channel 7 Software Level */
+#define _PRS_SWLEVEL_CH7LEVEL_SHIFT            7                                      /**< Shift value for PRS_CH7LEVEL */
+#define _PRS_SWLEVEL_CH7LEVEL_MASK             0x80UL                                 /**< Bit mask for PRS_CH7LEVEL */
+#define _PRS_SWLEVEL_CH7LEVEL_DEFAULT          0x00000000UL                           /**< Mode DEFAULT for PRS_SWLEVEL */
+#define PRS_SWLEVEL_CH7LEVEL_DEFAULT           (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7)   /**< Shifted mode DEFAULT for PRS_SWLEVEL */
+#define PRS_SWLEVEL_CH8LEVEL                   (0x1UL << 8)                           /**< Channel 8 Software Level */
+#define _PRS_SWLEVEL_CH8LEVEL_SHIFT            8                                      /**< Shift value for PRS_CH8LEVEL */
+#define _PRS_SWLEVEL_CH8LEVEL_MASK             0x100UL                                /**< Bit mask for PRS_CH8LEVEL */
+#define _PRS_SWLEVEL_CH8LEVEL_DEFAULT          0x00000000UL                           /**< Mode DEFAULT for PRS_SWLEVEL */
+#define PRS_SWLEVEL_CH8LEVEL_DEFAULT           (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8)   /**< Shifted mode DEFAULT for PRS_SWLEVEL */
+#define PRS_SWLEVEL_CH9LEVEL                   (0x1UL << 9)                           /**< Channel 9 Software Level */
+#define _PRS_SWLEVEL_CH9LEVEL_SHIFT            9                                      /**< Shift value for PRS_CH9LEVEL */
+#define _PRS_SWLEVEL_CH9LEVEL_MASK             0x200UL                                /**< Bit mask for PRS_CH9LEVEL */
+#define _PRS_SWLEVEL_CH9LEVEL_DEFAULT          0x00000000UL                           /**< Mode DEFAULT for PRS_SWLEVEL */
+#define PRS_SWLEVEL_CH9LEVEL_DEFAULT           (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9)   /**< Shifted mode DEFAULT for PRS_SWLEVEL */
+#define PRS_SWLEVEL_CH10LEVEL                  (0x1UL << 10)                          /**< Channel 10 Software Level */
+#define _PRS_SWLEVEL_CH10LEVEL_SHIFT           10                                     /**< Shift value for PRS_CH10LEVEL */
+#define _PRS_SWLEVEL_CH10LEVEL_MASK            0x400UL                                /**< Bit mask for PRS_CH10LEVEL */
+#define _PRS_SWLEVEL_CH10LEVEL_DEFAULT         0x00000000UL                           /**< Mode DEFAULT for PRS_SWLEVEL */
+#define PRS_SWLEVEL_CH10LEVEL_DEFAULT          (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
+#define PRS_SWLEVEL_CH11LEVEL                  (0x1UL << 11)                          /**< Channel 11 Software Level */
+#define _PRS_SWLEVEL_CH11LEVEL_SHIFT           11                                     /**< Shift value for PRS_CH11LEVEL */
+#define _PRS_SWLEVEL_CH11LEVEL_MASK            0x800UL                                /**< Bit mask for PRS_CH11LEVEL */
+#define _PRS_SWLEVEL_CH11LEVEL_DEFAULT         0x00000000UL                           /**< Mode DEFAULT for PRS_SWLEVEL */
+#define PRS_SWLEVEL_CH11LEVEL_DEFAULT          (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
+
+/* Bit fields for PRS ROUTEPEN */
+#define _PRS_ROUTEPEN_RESETVALUE               0x00000000UL                          /**< Default value for PRS_ROUTEPEN */
+#define _PRS_ROUTEPEN_MASK                     0x00000FFFUL                          /**< Mask for PRS_ROUTEPEN */
+#define PRS_ROUTEPEN_CH0PEN                    (0x1UL << 0)                          /**< CH0 Pin Enable */
+#define _PRS_ROUTEPEN_CH0PEN_SHIFT             0                                     /**< Shift value for PRS_CH0PEN */
+#define _PRS_ROUTEPEN_CH0PEN_MASK              0x1UL                                 /**< Bit mask for PRS_CH0PEN */
+#define _PRS_ROUTEPEN_CH0PEN_DEFAULT           0x00000000UL                          /**< Mode DEFAULT for PRS_ROUTEPEN */
+#define PRS_ROUTEPEN_CH0PEN_DEFAULT            (_PRS_ROUTEPEN_CH0PEN_DEFAULT << 0)   /**< Shifted mode DEFAULT for PRS_ROUTEPEN */
+#define PRS_ROUTEPEN_CH1PEN                    (0x1UL << 1)                          /**< CH1 Pin Enable */
+#define _PRS_ROUTEPEN_CH1PEN_SHIFT             1                                     /**< Shift value for PRS_CH1PEN */
+#define _PRS_ROUTEPEN_CH1PEN_MASK              0x2UL                                 /**< Bit mask for PRS_CH1PEN */
+#define _PRS_ROUTEPEN_CH1PEN_DEFAULT           0x00000000UL                          /**< Mode DEFAULT for PRS_ROUTEPEN */
+#define PRS_ROUTEPEN_CH1PEN_DEFAULT            (_PRS_ROUTEPEN_CH1PEN_DEFAULT << 1)   /**< Shifted mode DEFAULT for PRS_ROUTEPEN */
+#define PRS_ROUTEPEN_CH2PEN                    (0x1UL << 2)                          /**< CH2 Pin Enable */
+#define _PRS_ROUTEPEN_CH2PEN_SHIFT             2                                     /**< Shift value for PRS_CH2PEN */
+#define _PRS_ROUTEPEN_CH2PEN_MASK              0x4UL                                 /**< Bit mask for PRS_CH2PEN */
+#define _PRS_ROUTEPEN_CH2PEN_DEFAULT           0x00000000UL                          /**< Mode DEFAULT for PRS_ROUTEPEN */
+#define PRS_ROUTEPEN_CH2PEN_DEFAULT            (_PRS_ROUTEPEN_CH2PEN_DEFAULT << 2)   /**< Shifted mode DEFAULT for PRS_ROUTEPEN */
+#define PRS_ROUTEPEN_CH3PEN                    (0x1UL << 3)                          /**< CH3 Pin Enable */
+#define _PRS_ROUTEPEN_CH3PEN_SHIFT             3                                     /**< Shift value for PRS_CH3PEN */
+#define _PRS_ROUTEPEN_CH3PEN_MASK              0x8UL                                 /**< Bit mask for PRS_CH3PEN */
+#define _PRS_ROUTEPEN_CH3PEN_DEFAULT           0x00000000UL                          /**< Mode DEFAULT for PRS_ROUTEPEN */
+#define PRS_ROUTEPEN_CH3PEN_DEFAULT            (_PRS_ROUTEPEN_CH3PEN_DEFAULT << 3)   /**< Shifted mode DEFAULT for PRS_ROUTEPEN */
+#define PRS_ROUTEPEN_CH4PEN                    (0x1UL << 4)                          /**< CH4 Pin Enable */
+#define _PRS_ROUTEPEN_CH4PEN_SHIFT             4                                     /**< Shift value for PRS_CH4PEN */
+#define _PRS_ROUTEPEN_CH4PEN_MASK              0x10UL                                /**< Bit mask for PRS_CH4PEN */
+#define _PRS_ROUTEPEN_CH4PEN_DEFAULT           0x00000000UL                          /**< Mode DEFAULT for PRS_ROUTEPEN */
+#define PRS_ROUTEPEN_CH4PEN_DEFAULT            (_PRS_ROUTEPEN_CH4PEN_DEFAULT << 4)   /**< Shifted mode DEFAULT for PRS_ROUTEPEN */
+#define PRS_ROUTEPEN_CH5PEN                    (0x1UL << 5)                          /**< CH5 Pin Enable */
+#define _PRS_ROUTEPEN_CH5PEN_SHIFT             5                                     /**< Shift value for PRS_CH5PEN */
+#define _PRS_ROUTEPEN_CH5PEN_MASK              0x20UL                                /**< Bit mask for PRS_CH5PEN */
+#define _PRS_ROUTEPEN_CH5PEN_DEFAULT           0x00000000UL                          /**< Mode DEFAULT for PRS_ROUTEPEN */
+#define PRS_ROUTEPEN_CH5PEN_DEFAULT            (_PRS_ROUTEPEN_CH5PEN_DEFAULT << 5)   /**< Shifted mode DEFAULT for PRS_ROUTEPEN */
+#define PRS_ROUTEPEN_CH6PEN                    (0x1UL << 6)                          /**< CH6 Pin Enable */
+#define _PRS_ROUTEPEN_CH6PEN_SHIFT             6                                     /**< Shift value for PRS_CH6PEN */
+#define _PRS_ROUTEPEN_CH6PEN_MASK              0x40UL                                /**< Bit mask for PRS_CH6PEN */
+#define _PRS_ROUTEPEN_CH6PEN_DEFAULT           0x00000000UL                          /**< Mode DEFAULT for PRS_ROUTEPEN */
+#define PRS_ROUTEPEN_CH6PEN_DEFAULT            (_PRS_ROUTEPEN_CH6PEN_DEFAULT << 6)   /**< Shifted mode DEFAULT for PRS_ROUTEPEN */
+#define PRS_ROUTEPEN_CH7PEN                    (0x1UL << 7)                          /**< CH7 Pin Enable */
+#define _PRS_ROUTEPEN_CH7PEN_SHIFT             7                                     /**< Shift value for PRS_CH7PEN */
+#define _PRS_ROUTEPEN_CH7PEN_MASK              0x80UL                                /**< Bit mask for PRS_CH7PEN */
+#define _PRS_ROUTEPEN_CH7PEN_DEFAULT           0x00000000UL                          /**< Mode DEFAULT for PRS_ROUTEPEN */
+#define PRS_ROUTEPEN_CH7PEN_DEFAULT            (_PRS_ROUTEPEN_CH7PEN_DEFAULT << 7)   /**< Shifted mode DEFAULT for PRS_ROUTEPEN */
+#define PRS_ROUTEPEN_CH8PEN                    (0x1UL << 8)                          /**< CH8 Pin Enable */
+#define _PRS_ROUTEPEN_CH8PEN_SHIFT             8                                     /**< Shift value for PRS_CH8PEN */
+#define _PRS_ROUTEPEN_CH8PEN_MASK              0x100UL                               /**< Bit mask for PRS_CH8PEN */
+#define _PRS_ROUTEPEN_CH8PEN_DEFAULT           0x00000000UL                          /**< Mode DEFAULT for PRS_ROUTEPEN */
+#define PRS_ROUTEPEN_CH8PEN_DEFAULT            (_PRS_ROUTEPEN_CH8PEN_DEFAULT << 8)   /**< Shifted mode DEFAULT for PRS_ROUTEPEN */
+#define PRS_ROUTEPEN_CH9PEN                    (0x1UL << 9)                          /**< CH9 Pin Enable */
+#define _PRS_ROUTEPEN_CH9PEN_SHIFT             9                                     /**< Shift value for PRS_CH9PEN */
+#define _PRS_ROUTEPEN_CH9PEN_MASK              0x200UL                               /**< Bit mask for PRS_CH9PEN */
+#define _PRS_ROUTEPEN_CH9PEN_DEFAULT           0x00000000UL                          /**< Mode DEFAULT for PRS_ROUTEPEN */
+#define PRS_ROUTEPEN_CH9PEN_DEFAULT            (_PRS_ROUTEPEN_CH9PEN_DEFAULT << 9)   /**< Shifted mode DEFAULT for PRS_ROUTEPEN */
+#define PRS_ROUTEPEN_CH10PEN                   (0x1UL << 10)                         /**< CH10 Pin Enable */
+#define _PRS_ROUTEPEN_CH10PEN_SHIFT            10                                    /**< Shift value for PRS_CH10PEN */
+#define _PRS_ROUTEPEN_CH10PEN_MASK             0x400UL                               /**< Bit mask for PRS_CH10PEN */
+#define _PRS_ROUTEPEN_CH10PEN_DEFAULT          0x00000000UL                          /**< Mode DEFAULT for PRS_ROUTEPEN */
+#define PRS_ROUTEPEN_CH10PEN_DEFAULT           (_PRS_ROUTEPEN_CH10PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */
+#define PRS_ROUTEPEN_CH11PEN                   (0x1UL << 11)                         /**< CH11 Pin Enable */
+#define _PRS_ROUTEPEN_CH11PEN_SHIFT            11                                    /**< Shift value for PRS_CH11PEN */
+#define _PRS_ROUTEPEN_CH11PEN_MASK             0x800UL                               /**< Bit mask for PRS_CH11PEN */
+#define _PRS_ROUTEPEN_CH11PEN_DEFAULT          0x00000000UL                          /**< Mode DEFAULT for PRS_ROUTEPEN */
+#define PRS_ROUTEPEN_CH11PEN_DEFAULT           (_PRS_ROUTEPEN_CH11PEN_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */
+
+/* Bit fields for PRS ROUTELOC0 */
+#define _PRS_ROUTELOC0_RESETVALUE              0x00000000UL                          /**< Default value for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_MASK                    0x0F07070FUL                          /**< Mask for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH0LOC_SHIFT            0                                     /**< Shift value for PRS_CH0LOC */
+#define _PRS_ROUTELOC0_CH0LOC_MASK             0xFUL                                 /**< Bit mask for PRS_CH0LOC */
+#define _PRS_ROUTELOC0_CH0LOC_LOC0             0x00000000UL                          /**< Mode LOC0 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH0LOC_DEFAULT          0x00000000UL                          /**< Mode DEFAULT for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH0LOC_LOC1             0x00000001UL                          /**< Mode LOC1 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH0LOC_LOC2             0x00000002UL                          /**< Mode LOC2 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH0LOC_LOC3             0x00000003UL                          /**< Mode LOC3 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH0LOC_LOC4             0x00000004UL                          /**< Mode LOC4 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH0LOC_LOC5             0x00000005UL                          /**< Mode LOC5 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH0LOC_LOC6             0x00000006UL                          /**< Mode LOC6 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH0LOC_LOC7             0x00000007UL                          /**< Mode LOC7 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH0LOC_LOC8             0x00000008UL                          /**< Mode LOC8 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH0LOC_LOC9             0x00000009UL                          /**< Mode LOC9 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH0LOC_LOC10            0x0000000AUL                          /**< Mode LOC10 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH0LOC_LOC11            0x0000000BUL                          /**< Mode LOC11 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH0LOC_LOC12            0x0000000CUL                          /**< Mode LOC12 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH0LOC_LOC13            0x0000000DUL                          /**< Mode LOC13 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH0LOC_LOC0              (_PRS_ROUTELOC0_CH0LOC_LOC0 << 0)     /**< Shifted mode LOC0 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH0LOC_DEFAULT           (_PRS_ROUTELOC0_CH0LOC_DEFAULT << 0)  /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH0LOC_LOC1              (_PRS_ROUTELOC0_CH0LOC_LOC1 << 0)     /**< Shifted mode LOC1 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH0LOC_LOC2              (_PRS_ROUTELOC0_CH0LOC_LOC2 << 0)     /**< Shifted mode LOC2 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH0LOC_LOC3              (_PRS_ROUTELOC0_CH0LOC_LOC3 << 0)     /**< Shifted mode LOC3 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH0LOC_LOC4              (_PRS_ROUTELOC0_CH0LOC_LOC4 << 0)     /**< Shifted mode LOC4 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH0LOC_LOC5              (_PRS_ROUTELOC0_CH0LOC_LOC5 << 0)     /**< Shifted mode LOC5 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH0LOC_LOC6              (_PRS_ROUTELOC0_CH0LOC_LOC6 << 0)     /**< Shifted mode LOC6 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH0LOC_LOC7              (_PRS_ROUTELOC0_CH0LOC_LOC7 << 0)     /**< Shifted mode LOC7 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH0LOC_LOC8              (_PRS_ROUTELOC0_CH0LOC_LOC8 << 0)     /**< Shifted mode LOC8 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH0LOC_LOC9              (_PRS_ROUTELOC0_CH0LOC_LOC9 << 0)     /**< Shifted mode LOC9 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH0LOC_LOC10             (_PRS_ROUTELOC0_CH0LOC_LOC10 << 0)    /**< Shifted mode LOC10 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH0LOC_LOC11             (_PRS_ROUTELOC0_CH0LOC_LOC11 << 0)    /**< Shifted mode LOC11 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH0LOC_LOC12             (_PRS_ROUTELOC0_CH0LOC_LOC12 << 0)    /**< Shifted mode LOC12 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH0LOC_LOC13             (_PRS_ROUTELOC0_CH0LOC_LOC13 << 0)    /**< Shifted mode LOC13 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH1LOC_SHIFT            8                                     /**< Shift value for PRS_CH1LOC */
+#define _PRS_ROUTELOC0_CH1LOC_MASK             0x700UL                               /**< Bit mask for PRS_CH1LOC */
+#define _PRS_ROUTELOC0_CH1LOC_LOC0             0x00000000UL                          /**< Mode LOC0 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH1LOC_DEFAULT          0x00000000UL                          /**< Mode DEFAULT for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH1LOC_LOC1             0x00000001UL                          /**< Mode LOC1 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH1LOC_LOC2             0x00000002UL                          /**< Mode LOC2 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH1LOC_LOC3             0x00000003UL                          /**< Mode LOC3 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH1LOC_LOC4             0x00000004UL                          /**< Mode LOC4 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH1LOC_LOC5             0x00000005UL                          /**< Mode LOC5 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH1LOC_LOC6             0x00000006UL                          /**< Mode LOC6 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH1LOC_LOC7             0x00000007UL                          /**< Mode LOC7 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH1LOC_LOC0              (_PRS_ROUTELOC0_CH1LOC_LOC0 << 8)     /**< Shifted mode LOC0 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH1LOC_DEFAULT           (_PRS_ROUTELOC0_CH1LOC_DEFAULT << 8)  /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH1LOC_LOC1              (_PRS_ROUTELOC0_CH1LOC_LOC1 << 8)     /**< Shifted mode LOC1 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH1LOC_LOC2              (_PRS_ROUTELOC0_CH1LOC_LOC2 << 8)     /**< Shifted mode LOC2 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH1LOC_LOC3              (_PRS_ROUTELOC0_CH1LOC_LOC3 << 8)     /**< Shifted mode LOC3 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH1LOC_LOC4              (_PRS_ROUTELOC0_CH1LOC_LOC4 << 8)     /**< Shifted mode LOC4 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH1LOC_LOC5              (_PRS_ROUTELOC0_CH1LOC_LOC5 << 8)     /**< Shifted mode LOC5 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH1LOC_LOC6              (_PRS_ROUTELOC0_CH1LOC_LOC6 << 8)     /**< Shifted mode LOC6 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH1LOC_LOC7              (_PRS_ROUTELOC0_CH1LOC_LOC7 << 8)     /**< Shifted mode LOC7 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH2LOC_SHIFT            16                                    /**< Shift value for PRS_CH2LOC */
+#define _PRS_ROUTELOC0_CH2LOC_MASK             0x70000UL                             /**< Bit mask for PRS_CH2LOC */
+#define _PRS_ROUTELOC0_CH2LOC_LOC0             0x00000000UL                          /**< Mode LOC0 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH2LOC_DEFAULT          0x00000000UL                          /**< Mode DEFAULT for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH2LOC_LOC1             0x00000001UL                          /**< Mode LOC1 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH2LOC_LOC2             0x00000002UL                          /**< Mode LOC2 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH2LOC_LOC3             0x00000003UL                          /**< Mode LOC3 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH2LOC_LOC4             0x00000004UL                          /**< Mode LOC4 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH2LOC_LOC5             0x00000005UL                          /**< Mode LOC5 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH2LOC_LOC6             0x00000006UL                          /**< Mode LOC6 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH2LOC_LOC7             0x00000007UL                          /**< Mode LOC7 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH2LOC_LOC0              (_PRS_ROUTELOC0_CH2LOC_LOC0 << 16)    /**< Shifted mode LOC0 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH2LOC_DEFAULT           (_PRS_ROUTELOC0_CH2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH2LOC_LOC1              (_PRS_ROUTELOC0_CH2LOC_LOC1 << 16)    /**< Shifted mode LOC1 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH2LOC_LOC2              (_PRS_ROUTELOC0_CH2LOC_LOC2 << 16)    /**< Shifted mode LOC2 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH2LOC_LOC3              (_PRS_ROUTELOC0_CH2LOC_LOC3 << 16)    /**< Shifted mode LOC3 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH2LOC_LOC4              (_PRS_ROUTELOC0_CH2LOC_LOC4 << 16)    /**< Shifted mode LOC4 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH2LOC_LOC5              (_PRS_ROUTELOC0_CH2LOC_LOC5 << 16)    /**< Shifted mode LOC5 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH2LOC_LOC6              (_PRS_ROUTELOC0_CH2LOC_LOC6 << 16)    /**< Shifted mode LOC6 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH2LOC_LOC7              (_PRS_ROUTELOC0_CH2LOC_LOC7 << 16)    /**< Shifted mode LOC7 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH3LOC_SHIFT            24                                    /**< Shift value for PRS_CH3LOC */
+#define _PRS_ROUTELOC0_CH3LOC_MASK             0xF000000UL                           /**< Bit mask for PRS_CH3LOC */
+#define _PRS_ROUTELOC0_CH3LOC_LOC0             0x00000000UL                          /**< Mode LOC0 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH3LOC_DEFAULT          0x00000000UL                          /**< Mode DEFAULT for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH3LOC_LOC1             0x00000001UL                          /**< Mode LOC1 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH3LOC_LOC2             0x00000002UL                          /**< Mode LOC2 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH3LOC_LOC3             0x00000003UL                          /**< Mode LOC3 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH3LOC_LOC4             0x00000004UL                          /**< Mode LOC4 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH3LOC_LOC5             0x00000005UL                          /**< Mode LOC5 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH3LOC_LOC6             0x00000006UL                          /**< Mode LOC6 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH3LOC_LOC7             0x00000007UL                          /**< Mode LOC7 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH3LOC_LOC8             0x00000008UL                          /**< Mode LOC8 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH3LOC_LOC9             0x00000009UL                          /**< Mode LOC9 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH3LOC_LOC10            0x0000000AUL                          /**< Mode LOC10 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH3LOC_LOC11            0x0000000BUL                          /**< Mode LOC11 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH3LOC_LOC12            0x0000000CUL                          /**< Mode LOC12 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH3LOC_LOC13            0x0000000DUL                          /**< Mode LOC13 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH3LOC_LOC14            0x0000000EUL                          /**< Mode LOC14 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH3LOC_LOC0              (_PRS_ROUTELOC0_CH3LOC_LOC0 << 24)    /**< Shifted mode LOC0 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH3LOC_DEFAULT           (_PRS_ROUTELOC0_CH3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH3LOC_LOC1              (_PRS_ROUTELOC0_CH3LOC_LOC1 << 24)    /**< Shifted mode LOC1 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH3LOC_LOC2              (_PRS_ROUTELOC0_CH3LOC_LOC2 << 24)    /**< Shifted mode LOC2 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH3LOC_LOC3              (_PRS_ROUTELOC0_CH3LOC_LOC3 << 24)    /**< Shifted mode LOC3 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH3LOC_LOC4              (_PRS_ROUTELOC0_CH3LOC_LOC4 << 24)    /**< Shifted mode LOC4 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH3LOC_LOC5              (_PRS_ROUTELOC0_CH3LOC_LOC5 << 24)    /**< Shifted mode LOC5 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH3LOC_LOC6              (_PRS_ROUTELOC0_CH3LOC_LOC6 << 24)    /**< Shifted mode LOC6 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH3LOC_LOC7              (_PRS_ROUTELOC0_CH3LOC_LOC7 << 24)    /**< Shifted mode LOC7 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH3LOC_LOC8              (_PRS_ROUTELOC0_CH3LOC_LOC8 << 24)    /**< Shifted mode LOC8 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH3LOC_LOC9              (_PRS_ROUTELOC0_CH3LOC_LOC9 << 24)    /**< Shifted mode LOC9 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH3LOC_LOC10             (_PRS_ROUTELOC0_CH3LOC_LOC10 << 24)   /**< Shifted mode LOC10 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH3LOC_LOC11             (_PRS_ROUTELOC0_CH3LOC_LOC11 << 24)   /**< Shifted mode LOC11 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH3LOC_LOC12             (_PRS_ROUTELOC0_CH3LOC_LOC12 << 24)   /**< Shifted mode LOC12 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH3LOC_LOC13             (_PRS_ROUTELOC0_CH3LOC_LOC13 << 24)   /**< Shifted mode LOC13 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH3LOC_LOC14             (_PRS_ROUTELOC0_CH3LOC_LOC14 << 24)   /**< Shifted mode LOC14 for PRS_ROUTELOC0 */
+
+/* Bit fields for PRS ROUTELOC1 */
+#define _PRS_ROUTELOC1_RESETVALUE              0x00000000UL                          /**< Default value for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_MASK                    0x0F1F0707UL                          /**< Mask for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH4LOC_SHIFT            0                                     /**< Shift value for PRS_CH4LOC */
+#define _PRS_ROUTELOC1_CH4LOC_MASK             0x7UL                                 /**< Bit mask for PRS_CH4LOC */
+#define _PRS_ROUTELOC1_CH4LOC_LOC0             0x00000000UL                          /**< Mode LOC0 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH4LOC_DEFAULT          0x00000000UL                          /**< Mode DEFAULT for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH4LOC_LOC1             0x00000001UL                          /**< Mode LOC1 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH4LOC_LOC2             0x00000002UL                          /**< Mode LOC2 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH4LOC_LOC3             0x00000003UL                          /**< Mode LOC3 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH4LOC_LOC4             0x00000004UL                          /**< Mode LOC4 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH4LOC_LOC5             0x00000005UL                          /**< Mode LOC5 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH4LOC_LOC6             0x00000006UL                          /**< Mode LOC6 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH4LOC_LOC0              (_PRS_ROUTELOC1_CH4LOC_LOC0 << 0)     /**< Shifted mode LOC0 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH4LOC_DEFAULT           (_PRS_ROUTELOC1_CH4LOC_DEFAULT << 0)  /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH4LOC_LOC1              (_PRS_ROUTELOC1_CH4LOC_LOC1 << 0)     /**< Shifted mode LOC1 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH4LOC_LOC2              (_PRS_ROUTELOC1_CH4LOC_LOC2 << 0)     /**< Shifted mode LOC2 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH4LOC_LOC3              (_PRS_ROUTELOC1_CH4LOC_LOC3 << 0)     /**< Shifted mode LOC3 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH4LOC_LOC4              (_PRS_ROUTELOC1_CH4LOC_LOC4 << 0)     /**< Shifted mode LOC4 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH4LOC_LOC5              (_PRS_ROUTELOC1_CH4LOC_LOC5 << 0)     /**< Shifted mode LOC5 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH4LOC_LOC6              (_PRS_ROUTELOC1_CH4LOC_LOC6 << 0)     /**< Shifted mode LOC6 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH5LOC_SHIFT            8                                     /**< Shift value for PRS_CH5LOC */
+#define _PRS_ROUTELOC1_CH5LOC_MASK             0x700UL                               /**< Bit mask for PRS_CH5LOC */
+#define _PRS_ROUTELOC1_CH5LOC_LOC0             0x00000000UL                          /**< Mode LOC0 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH5LOC_DEFAULT          0x00000000UL                          /**< Mode DEFAULT for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH5LOC_LOC1             0x00000001UL                          /**< Mode LOC1 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH5LOC_LOC2             0x00000002UL                          /**< Mode LOC2 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH5LOC_LOC3             0x00000003UL                          /**< Mode LOC3 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH5LOC_LOC4             0x00000004UL                          /**< Mode LOC4 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH5LOC_LOC5             0x00000005UL                          /**< Mode LOC5 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH5LOC_LOC6             0x00000006UL                          /**< Mode LOC6 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH5LOC_LOC0              (_PRS_ROUTELOC1_CH5LOC_LOC0 << 8)     /**< Shifted mode LOC0 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH5LOC_DEFAULT           (_PRS_ROUTELOC1_CH5LOC_DEFAULT << 8)  /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH5LOC_LOC1              (_PRS_ROUTELOC1_CH5LOC_LOC1 << 8)     /**< Shifted mode LOC1 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH5LOC_LOC2              (_PRS_ROUTELOC1_CH5LOC_LOC2 << 8)     /**< Shifted mode LOC2 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH5LOC_LOC3              (_PRS_ROUTELOC1_CH5LOC_LOC3 << 8)     /**< Shifted mode LOC3 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH5LOC_LOC4              (_PRS_ROUTELOC1_CH5LOC_LOC4 << 8)     /**< Shifted mode LOC4 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH5LOC_LOC5              (_PRS_ROUTELOC1_CH5LOC_LOC5 << 8)     /**< Shifted mode LOC5 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH5LOC_LOC6              (_PRS_ROUTELOC1_CH5LOC_LOC6 << 8)     /**< Shifted mode LOC6 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH6LOC_SHIFT            16                                    /**< Shift value for PRS_CH6LOC */
+#define _PRS_ROUTELOC1_CH6LOC_MASK             0x1F0000UL                            /**< Bit mask for PRS_CH6LOC */
+#define _PRS_ROUTELOC1_CH6LOC_LOC0             0x00000000UL                          /**< Mode LOC0 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH6LOC_DEFAULT          0x00000000UL                          /**< Mode DEFAULT for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH6LOC_LOC1             0x00000001UL                          /**< Mode LOC1 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH6LOC_LOC2             0x00000002UL                          /**< Mode LOC2 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH6LOC_LOC3             0x00000003UL                          /**< Mode LOC3 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH6LOC_LOC4             0x00000004UL                          /**< Mode LOC4 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH6LOC_LOC5             0x00000005UL                          /**< Mode LOC5 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH6LOC_LOC6             0x00000006UL                          /**< Mode LOC6 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH6LOC_LOC7             0x00000007UL                          /**< Mode LOC7 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH6LOC_LOC8             0x00000008UL                          /**< Mode LOC8 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH6LOC_LOC9             0x00000009UL                          /**< Mode LOC9 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH6LOC_LOC10            0x0000000AUL                          /**< Mode LOC10 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH6LOC_LOC11            0x0000000BUL                          /**< Mode LOC11 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH6LOC_LOC12            0x0000000CUL                          /**< Mode LOC12 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH6LOC_LOC13            0x0000000DUL                          /**< Mode LOC13 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH6LOC_LOC14            0x0000000EUL                          /**< Mode LOC14 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH6LOC_LOC15            0x0000000FUL                          /**< Mode LOC15 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH6LOC_LOC16            0x00000010UL                          /**< Mode LOC16 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH6LOC_LOC17            0x00000011UL                          /**< Mode LOC17 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH6LOC_LOC0              (_PRS_ROUTELOC1_CH6LOC_LOC0 << 16)    /**< Shifted mode LOC0 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH6LOC_DEFAULT           (_PRS_ROUTELOC1_CH6LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH6LOC_LOC1              (_PRS_ROUTELOC1_CH6LOC_LOC1 << 16)    /**< Shifted mode LOC1 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH6LOC_LOC2              (_PRS_ROUTELOC1_CH6LOC_LOC2 << 16)    /**< Shifted mode LOC2 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH6LOC_LOC3              (_PRS_ROUTELOC1_CH6LOC_LOC3 << 16)    /**< Shifted mode LOC3 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH6LOC_LOC4              (_PRS_ROUTELOC1_CH6LOC_LOC4 << 16)    /**< Shifted mode LOC4 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH6LOC_LOC5              (_PRS_ROUTELOC1_CH6LOC_LOC5 << 16)    /**< Shifted mode LOC5 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH6LOC_LOC6              (_PRS_ROUTELOC1_CH6LOC_LOC6 << 16)    /**< Shifted mode LOC6 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH6LOC_LOC7              (_PRS_ROUTELOC1_CH6LOC_LOC7 << 16)    /**< Shifted mode LOC7 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH6LOC_LOC8              (_PRS_ROUTELOC1_CH6LOC_LOC8 << 16)    /**< Shifted mode LOC8 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH6LOC_LOC9              (_PRS_ROUTELOC1_CH6LOC_LOC9 << 16)    /**< Shifted mode LOC9 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH6LOC_LOC10             (_PRS_ROUTELOC1_CH6LOC_LOC10 << 16)   /**< Shifted mode LOC10 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH6LOC_LOC11             (_PRS_ROUTELOC1_CH6LOC_LOC11 << 16)   /**< Shifted mode LOC11 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH6LOC_LOC12             (_PRS_ROUTELOC1_CH6LOC_LOC12 << 16)   /**< Shifted mode LOC12 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH6LOC_LOC13             (_PRS_ROUTELOC1_CH6LOC_LOC13 << 16)   /**< Shifted mode LOC13 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH6LOC_LOC14             (_PRS_ROUTELOC1_CH6LOC_LOC14 << 16)   /**< Shifted mode LOC14 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH6LOC_LOC15             (_PRS_ROUTELOC1_CH6LOC_LOC15 << 16)   /**< Shifted mode LOC15 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH6LOC_LOC16             (_PRS_ROUTELOC1_CH6LOC_LOC16 << 16)   /**< Shifted mode LOC16 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH6LOC_LOC17             (_PRS_ROUTELOC1_CH6LOC_LOC17 << 16)   /**< Shifted mode LOC17 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH7LOC_SHIFT            24                                    /**< Shift value for PRS_CH7LOC */
+#define _PRS_ROUTELOC1_CH7LOC_MASK             0xF000000UL                           /**< Bit mask for PRS_CH7LOC */
+#define _PRS_ROUTELOC1_CH7LOC_LOC0             0x00000000UL                          /**< Mode LOC0 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH7LOC_DEFAULT          0x00000000UL                          /**< Mode DEFAULT for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH7LOC_LOC1             0x00000001UL                          /**< Mode LOC1 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH7LOC_LOC2             0x00000002UL                          /**< Mode LOC2 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH7LOC_LOC3             0x00000003UL                          /**< Mode LOC3 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH7LOC_LOC4             0x00000004UL                          /**< Mode LOC4 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH7LOC_LOC5             0x00000005UL                          /**< Mode LOC5 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH7LOC_LOC6             0x00000006UL                          /**< Mode LOC6 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH7LOC_LOC7             0x00000007UL                          /**< Mode LOC7 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH7LOC_LOC8             0x00000008UL                          /**< Mode LOC8 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH7LOC_LOC9             0x00000009UL                          /**< Mode LOC9 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH7LOC_LOC10            0x0000000AUL                          /**< Mode LOC10 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH7LOC_LOC0              (_PRS_ROUTELOC1_CH7LOC_LOC0 << 24)    /**< Shifted mode LOC0 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH7LOC_DEFAULT           (_PRS_ROUTELOC1_CH7LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH7LOC_LOC1              (_PRS_ROUTELOC1_CH7LOC_LOC1 << 24)    /**< Shifted mode LOC1 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH7LOC_LOC2              (_PRS_ROUTELOC1_CH7LOC_LOC2 << 24)    /**< Shifted mode LOC2 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH7LOC_LOC3              (_PRS_ROUTELOC1_CH7LOC_LOC3 << 24)    /**< Shifted mode LOC3 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH7LOC_LOC4              (_PRS_ROUTELOC1_CH7LOC_LOC4 << 24)    /**< Shifted mode LOC4 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH7LOC_LOC5              (_PRS_ROUTELOC1_CH7LOC_LOC5 << 24)    /**< Shifted mode LOC5 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH7LOC_LOC6              (_PRS_ROUTELOC1_CH7LOC_LOC6 << 24)    /**< Shifted mode LOC6 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH7LOC_LOC7              (_PRS_ROUTELOC1_CH7LOC_LOC7 << 24)    /**< Shifted mode LOC7 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH7LOC_LOC8              (_PRS_ROUTELOC1_CH7LOC_LOC8 << 24)    /**< Shifted mode LOC8 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH7LOC_LOC9              (_PRS_ROUTELOC1_CH7LOC_LOC9 << 24)    /**< Shifted mode LOC9 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH7LOC_LOC10             (_PRS_ROUTELOC1_CH7LOC_LOC10 << 24)   /**< Shifted mode LOC10 for PRS_ROUTELOC1 */
+
+/* Bit fields for PRS ROUTELOC2 */
+#define _PRS_ROUTELOC2_RESETVALUE              0x00000000UL                           /**< Default value for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_MASK                    0x07071F0FUL                           /**< Mask for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH8LOC_SHIFT            0                                      /**< Shift value for PRS_CH8LOC */
+#define _PRS_ROUTELOC2_CH8LOC_MASK             0xFUL                                  /**< Bit mask for PRS_CH8LOC */
+#define _PRS_ROUTELOC2_CH8LOC_LOC0             0x00000000UL                           /**< Mode LOC0 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH8LOC_DEFAULT          0x00000000UL                           /**< Mode DEFAULT for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH8LOC_LOC1             0x00000001UL                           /**< Mode LOC1 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH8LOC_LOC2             0x00000002UL                           /**< Mode LOC2 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH8LOC_LOC3             0x00000003UL                           /**< Mode LOC3 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH8LOC_LOC4             0x00000004UL                           /**< Mode LOC4 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH8LOC_LOC5             0x00000005UL                           /**< Mode LOC5 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH8LOC_LOC6             0x00000006UL                           /**< Mode LOC6 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH8LOC_LOC7             0x00000007UL                           /**< Mode LOC7 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH8LOC_LOC8             0x00000008UL                           /**< Mode LOC8 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH8LOC_LOC9             0x00000009UL                           /**< Mode LOC9 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH8LOC_LOC10            0x0000000AUL                           /**< Mode LOC10 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH8LOC_LOC0              (_PRS_ROUTELOC2_CH8LOC_LOC0 << 0)      /**< Shifted mode LOC0 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH8LOC_DEFAULT           (_PRS_ROUTELOC2_CH8LOC_DEFAULT << 0)   /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH8LOC_LOC1              (_PRS_ROUTELOC2_CH8LOC_LOC1 << 0)      /**< Shifted mode LOC1 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH8LOC_LOC2              (_PRS_ROUTELOC2_CH8LOC_LOC2 << 0)      /**< Shifted mode LOC2 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH8LOC_LOC3              (_PRS_ROUTELOC2_CH8LOC_LOC3 << 0)      /**< Shifted mode LOC3 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH8LOC_LOC4              (_PRS_ROUTELOC2_CH8LOC_LOC4 << 0)      /**< Shifted mode LOC4 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH8LOC_LOC5              (_PRS_ROUTELOC2_CH8LOC_LOC5 << 0)      /**< Shifted mode LOC5 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH8LOC_LOC6              (_PRS_ROUTELOC2_CH8LOC_LOC6 << 0)      /**< Shifted mode LOC6 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH8LOC_LOC7              (_PRS_ROUTELOC2_CH8LOC_LOC7 << 0)      /**< Shifted mode LOC7 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH8LOC_LOC8              (_PRS_ROUTELOC2_CH8LOC_LOC8 << 0)      /**< Shifted mode LOC8 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH8LOC_LOC9              (_PRS_ROUTELOC2_CH8LOC_LOC9 << 0)      /**< Shifted mode LOC9 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH8LOC_LOC10             (_PRS_ROUTELOC2_CH8LOC_LOC10 << 0)     /**< Shifted mode LOC10 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH9LOC_SHIFT            8                                      /**< Shift value for PRS_CH9LOC */
+#define _PRS_ROUTELOC2_CH9LOC_MASK             0x1F00UL                               /**< Bit mask for PRS_CH9LOC */
+#define _PRS_ROUTELOC2_CH9LOC_LOC0             0x00000000UL                           /**< Mode LOC0 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH9LOC_DEFAULT          0x00000000UL                           /**< Mode DEFAULT for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH9LOC_LOC1             0x00000001UL                           /**< Mode LOC1 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH9LOC_LOC2             0x00000002UL                           /**< Mode LOC2 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH9LOC_LOC3             0x00000003UL                           /**< Mode LOC3 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH9LOC_LOC4             0x00000004UL                           /**< Mode LOC4 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH9LOC_LOC5             0x00000005UL                           /**< Mode LOC5 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH9LOC_LOC6             0x00000006UL                           /**< Mode LOC6 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH9LOC_LOC7             0x00000007UL                           /**< Mode LOC7 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH9LOC_LOC8             0x00000008UL                           /**< Mode LOC8 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH9LOC_LOC9             0x00000009UL                           /**< Mode LOC9 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH9LOC_LOC10            0x0000000AUL                           /**< Mode LOC10 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH9LOC_LOC11            0x0000000BUL                           /**< Mode LOC11 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH9LOC_LOC12            0x0000000CUL                           /**< Mode LOC12 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH9LOC_LOC13            0x0000000DUL                           /**< Mode LOC13 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH9LOC_LOC14            0x0000000EUL                           /**< Mode LOC14 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH9LOC_LOC15            0x0000000FUL                           /**< Mode LOC15 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH9LOC_LOC16            0x00000010UL                           /**< Mode LOC16 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH9LOC_LOC0              (_PRS_ROUTELOC2_CH9LOC_LOC0 << 8)      /**< Shifted mode LOC0 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH9LOC_DEFAULT           (_PRS_ROUTELOC2_CH9LOC_DEFAULT << 8)   /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH9LOC_LOC1              (_PRS_ROUTELOC2_CH9LOC_LOC1 << 8)      /**< Shifted mode LOC1 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH9LOC_LOC2              (_PRS_ROUTELOC2_CH9LOC_LOC2 << 8)      /**< Shifted mode LOC2 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH9LOC_LOC3              (_PRS_ROUTELOC2_CH9LOC_LOC3 << 8)      /**< Shifted mode LOC3 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH9LOC_LOC4              (_PRS_ROUTELOC2_CH9LOC_LOC4 << 8)      /**< Shifted mode LOC4 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH9LOC_LOC5              (_PRS_ROUTELOC2_CH9LOC_LOC5 << 8)      /**< Shifted mode LOC5 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH9LOC_LOC6              (_PRS_ROUTELOC2_CH9LOC_LOC6 << 8)      /**< Shifted mode LOC6 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH9LOC_LOC7              (_PRS_ROUTELOC2_CH9LOC_LOC7 << 8)      /**< Shifted mode LOC7 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH9LOC_LOC8              (_PRS_ROUTELOC2_CH9LOC_LOC8 << 8)      /**< Shifted mode LOC8 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH9LOC_LOC9              (_PRS_ROUTELOC2_CH9LOC_LOC9 << 8)      /**< Shifted mode LOC9 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH9LOC_LOC10             (_PRS_ROUTELOC2_CH9LOC_LOC10 << 8)     /**< Shifted mode LOC10 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH9LOC_LOC11             (_PRS_ROUTELOC2_CH9LOC_LOC11 << 8)     /**< Shifted mode LOC11 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH9LOC_LOC12             (_PRS_ROUTELOC2_CH9LOC_LOC12 << 8)     /**< Shifted mode LOC12 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH9LOC_LOC13             (_PRS_ROUTELOC2_CH9LOC_LOC13 << 8)     /**< Shifted mode LOC13 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH9LOC_LOC14             (_PRS_ROUTELOC2_CH9LOC_LOC14 << 8)     /**< Shifted mode LOC14 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH9LOC_LOC15             (_PRS_ROUTELOC2_CH9LOC_LOC15 << 8)     /**< Shifted mode LOC15 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH9LOC_LOC16             (_PRS_ROUTELOC2_CH9LOC_LOC16 << 8)     /**< Shifted mode LOC16 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH10LOC_SHIFT           16                                     /**< Shift value for PRS_CH10LOC */
+#define _PRS_ROUTELOC2_CH10LOC_MASK            0x70000UL                              /**< Bit mask for PRS_CH10LOC */
+#define _PRS_ROUTELOC2_CH10LOC_LOC0            0x00000000UL                           /**< Mode LOC0 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH10LOC_DEFAULT         0x00000000UL                           /**< Mode DEFAULT for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH10LOC_LOC1            0x00000001UL                           /**< Mode LOC1 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH10LOC_LOC2            0x00000002UL                           /**< Mode LOC2 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH10LOC_LOC3            0x00000003UL                           /**< Mode LOC3 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH10LOC_LOC4            0x00000004UL                           /**< Mode LOC4 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH10LOC_LOC5            0x00000005UL                           /**< Mode LOC5 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH10LOC_LOC0             (_PRS_ROUTELOC2_CH10LOC_LOC0 << 16)    /**< Shifted mode LOC0 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH10LOC_DEFAULT          (_PRS_ROUTELOC2_CH10LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH10LOC_LOC1             (_PRS_ROUTELOC2_CH10LOC_LOC1 << 16)    /**< Shifted mode LOC1 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH10LOC_LOC2             (_PRS_ROUTELOC2_CH10LOC_LOC2 << 16)    /**< Shifted mode LOC2 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH10LOC_LOC3             (_PRS_ROUTELOC2_CH10LOC_LOC3 << 16)    /**< Shifted mode LOC3 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH10LOC_LOC4             (_PRS_ROUTELOC2_CH10LOC_LOC4 << 16)    /**< Shifted mode LOC4 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH10LOC_LOC5             (_PRS_ROUTELOC2_CH10LOC_LOC5 << 16)    /**< Shifted mode LOC5 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH11LOC_SHIFT           24                                     /**< Shift value for PRS_CH11LOC */
+#define _PRS_ROUTELOC2_CH11LOC_MASK            0x7000000UL                            /**< Bit mask for PRS_CH11LOC */
+#define _PRS_ROUTELOC2_CH11LOC_LOC0            0x00000000UL                           /**< Mode LOC0 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH11LOC_DEFAULT         0x00000000UL                           /**< Mode DEFAULT for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH11LOC_LOC1            0x00000001UL                           /**< Mode LOC1 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH11LOC_LOC2            0x00000002UL                           /**< Mode LOC2 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH11LOC_LOC3            0x00000003UL                           /**< Mode LOC3 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH11LOC_LOC4            0x00000004UL                           /**< Mode LOC4 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH11LOC_LOC5            0x00000005UL                           /**< Mode LOC5 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH11LOC_LOC0             (_PRS_ROUTELOC2_CH11LOC_LOC0 << 24)    /**< Shifted mode LOC0 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH11LOC_DEFAULT          (_PRS_ROUTELOC2_CH11LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH11LOC_LOC1             (_PRS_ROUTELOC2_CH11LOC_LOC1 << 24)    /**< Shifted mode LOC1 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH11LOC_LOC2             (_PRS_ROUTELOC2_CH11LOC_LOC2 << 24)    /**< Shifted mode LOC2 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH11LOC_LOC3             (_PRS_ROUTELOC2_CH11LOC_LOC3 << 24)    /**< Shifted mode LOC3 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH11LOC_LOC4             (_PRS_ROUTELOC2_CH11LOC_LOC4 << 24)    /**< Shifted mode LOC4 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH11LOC_LOC5             (_PRS_ROUTELOC2_CH11LOC_LOC5 << 24)    /**< Shifted mode LOC5 for PRS_ROUTELOC2 */
+
+/* Bit fields for PRS CTRL */
+#define _PRS_CTRL_RESETVALUE                   0x00000000UL                         /**< Default value for PRS_CTRL */
+#define _PRS_CTRL_MASK                         0x0000001FUL                         /**< Mask for PRS_CTRL */
+#define PRS_CTRL_SEVONPRS                      (0x1UL << 0)                         /**< Set Event on PRS */
+#define _PRS_CTRL_SEVONPRS_SHIFT               0                                    /**< Shift value for PRS_SEVONPRS */
+#define _PRS_CTRL_SEVONPRS_MASK                0x1UL                                /**< Bit mask for PRS_SEVONPRS */
+#define _PRS_CTRL_SEVONPRS_DEFAULT             0x00000000UL                         /**< Mode DEFAULT for PRS_CTRL */
+#define PRS_CTRL_SEVONPRS_DEFAULT              (_PRS_CTRL_SEVONPRS_DEFAULT << 0)    /**< Shifted mode DEFAULT for PRS_CTRL */
+#define _PRS_CTRL_SEVONPRSSEL_SHIFT            1                                    /**< Shift value for PRS_SEVONPRSSEL */
+#define _PRS_CTRL_SEVONPRSSEL_MASK             0x1EUL                               /**< Bit mask for PRS_SEVONPRSSEL */
+#define _PRS_CTRL_SEVONPRSSEL_DEFAULT          0x00000000UL                         /**< Mode DEFAULT for PRS_CTRL */
+#define _PRS_CTRL_SEVONPRSSEL_PRSCH0           0x00000000UL                         /**< Mode PRSCH0 for PRS_CTRL */
+#define _PRS_CTRL_SEVONPRSSEL_PRSCH1           0x00000001UL                         /**< Mode PRSCH1 for PRS_CTRL */
+#define _PRS_CTRL_SEVONPRSSEL_PRSCH2           0x00000002UL                         /**< Mode PRSCH2 for PRS_CTRL */
+#define _PRS_CTRL_SEVONPRSSEL_PRSCH3           0x00000003UL                         /**< Mode PRSCH3 for PRS_CTRL */
+#define _PRS_CTRL_SEVONPRSSEL_PRSCH4           0x00000004UL                         /**< Mode PRSCH4 for PRS_CTRL */
+#define _PRS_CTRL_SEVONPRSSEL_PRSCH5           0x00000005UL                         /**< Mode PRSCH5 for PRS_CTRL */
+#define _PRS_CTRL_SEVONPRSSEL_PRSCH6           0x00000006UL                         /**< Mode PRSCH6 for PRS_CTRL */
+#define _PRS_CTRL_SEVONPRSSEL_PRSCH7           0x00000007UL                         /**< Mode PRSCH7 for PRS_CTRL */
+#define _PRS_CTRL_SEVONPRSSEL_PRSCH8           0x00000008UL                         /**< Mode PRSCH8 for PRS_CTRL */
+#define _PRS_CTRL_SEVONPRSSEL_PRSCH9           0x00000009UL                         /**< Mode PRSCH9 for PRS_CTRL */
+#define _PRS_CTRL_SEVONPRSSEL_PRSCH10          0x0000000AUL                         /**< Mode PRSCH10 for PRS_CTRL */
+#define _PRS_CTRL_SEVONPRSSEL_PRSCH11          0x0000000BUL                         /**< Mode PRSCH11 for PRS_CTRL */
+#define PRS_CTRL_SEVONPRSSEL_DEFAULT           (_PRS_CTRL_SEVONPRSSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_CTRL */
+#define PRS_CTRL_SEVONPRSSEL_PRSCH0            (_PRS_CTRL_SEVONPRSSEL_PRSCH0 << 1)  /**< Shifted mode PRSCH0 for PRS_CTRL */
+#define PRS_CTRL_SEVONPRSSEL_PRSCH1            (_PRS_CTRL_SEVONPRSSEL_PRSCH1 << 1)  /**< Shifted mode PRSCH1 for PRS_CTRL */
+#define PRS_CTRL_SEVONPRSSEL_PRSCH2            (_PRS_CTRL_SEVONPRSSEL_PRSCH2 << 1)  /**< Shifted mode PRSCH2 for PRS_CTRL */
+#define PRS_CTRL_SEVONPRSSEL_PRSCH3            (_PRS_CTRL_SEVONPRSSEL_PRSCH3 << 1)  /**< Shifted mode PRSCH3 for PRS_CTRL */
+#define PRS_CTRL_SEVONPRSSEL_PRSCH4            (_PRS_CTRL_SEVONPRSSEL_PRSCH4 << 1)  /**< Shifted mode PRSCH4 for PRS_CTRL */
+#define PRS_CTRL_SEVONPRSSEL_PRSCH5            (_PRS_CTRL_SEVONPRSSEL_PRSCH5 << 1)  /**< Shifted mode PRSCH5 for PRS_CTRL */
+#define PRS_CTRL_SEVONPRSSEL_PRSCH6            (_PRS_CTRL_SEVONPRSSEL_PRSCH6 << 1)  /**< Shifted mode PRSCH6 for PRS_CTRL */
+#define PRS_CTRL_SEVONPRSSEL_PRSCH7            (_PRS_CTRL_SEVONPRSSEL_PRSCH7 << 1)  /**< Shifted mode PRSCH7 for PRS_CTRL */
+#define PRS_CTRL_SEVONPRSSEL_PRSCH8            (_PRS_CTRL_SEVONPRSSEL_PRSCH8 << 1)  /**< Shifted mode PRSCH8 for PRS_CTRL */
+#define PRS_CTRL_SEVONPRSSEL_PRSCH9            (_PRS_CTRL_SEVONPRSSEL_PRSCH9 << 1)  /**< Shifted mode PRSCH9 for PRS_CTRL */
+#define PRS_CTRL_SEVONPRSSEL_PRSCH10           (_PRS_CTRL_SEVONPRSSEL_PRSCH10 << 1) /**< Shifted mode PRSCH10 for PRS_CTRL */
+#define PRS_CTRL_SEVONPRSSEL_PRSCH11           (_PRS_CTRL_SEVONPRSSEL_PRSCH11 << 1) /**< Shifted mode PRSCH11 for PRS_CTRL */
+
+/* Bit fields for PRS DMAREQ0 */
+#define _PRS_DMAREQ0_RESETVALUE                0x00000000UL                       /**< Default value for PRS_DMAREQ0 */
+#define _PRS_DMAREQ0_MASK                      0x000003C0UL                       /**< Mask for PRS_DMAREQ0 */
+#define _PRS_DMAREQ0_PRSSEL_SHIFT              6                                  /**< Shift value for PRS_PRSSEL */
+#define _PRS_DMAREQ0_PRSSEL_MASK               0x3C0UL                            /**< Bit mask for PRS_PRSSEL */
+#define _PRS_DMAREQ0_PRSSEL_DEFAULT            0x00000000UL                       /**< Mode DEFAULT for PRS_DMAREQ0 */
+#define _PRS_DMAREQ0_PRSSEL_PRSCH0             0x00000000UL                       /**< Mode PRSCH0 for PRS_DMAREQ0 */
+#define _PRS_DMAREQ0_PRSSEL_PRSCH1             0x00000001UL                       /**< Mode PRSCH1 for PRS_DMAREQ0 */
+#define _PRS_DMAREQ0_PRSSEL_PRSCH2             0x00000002UL                       /**< Mode PRSCH2 for PRS_DMAREQ0 */
+#define _PRS_DMAREQ0_PRSSEL_PRSCH3             0x00000003UL                       /**< Mode PRSCH3 for PRS_DMAREQ0 */
+#define _PRS_DMAREQ0_PRSSEL_PRSCH4             0x00000004UL                       /**< Mode PRSCH4 for PRS_DMAREQ0 */
+#define _PRS_DMAREQ0_PRSSEL_PRSCH5             0x00000005UL                       /**< Mode PRSCH5 for PRS_DMAREQ0 */
+#define _PRS_DMAREQ0_PRSSEL_PRSCH6             0x00000006UL                       /**< Mode PRSCH6 for PRS_DMAREQ0 */
+#define _PRS_DMAREQ0_PRSSEL_PRSCH7             0x00000007UL                       /**< Mode PRSCH7 for PRS_DMAREQ0 */
+#define _PRS_DMAREQ0_PRSSEL_PRSCH8             0x00000008UL                       /**< Mode PRSCH8 for PRS_DMAREQ0 */
+#define _PRS_DMAREQ0_PRSSEL_PRSCH9             0x00000009UL                       /**< Mode PRSCH9 for PRS_DMAREQ0 */
+#define _PRS_DMAREQ0_PRSSEL_PRSCH10            0x0000000AUL                       /**< Mode PRSCH10 for PRS_DMAREQ0 */
+#define _PRS_DMAREQ0_PRSSEL_PRSCH11            0x0000000BUL                       /**< Mode PRSCH11 for PRS_DMAREQ0 */
+#define PRS_DMAREQ0_PRSSEL_DEFAULT             (_PRS_DMAREQ0_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ0 */
+#define PRS_DMAREQ0_PRSSEL_PRSCH0              (_PRS_DMAREQ0_PRSSEL_PRSCH0 << 6)  /**< Shifted mode PRSCH0 for PRS_DMAREQ0 */
+#define PRS_DMAREQ0_PRSSEL_PRSCH1              (_PRS_DMAREQ0_PRSSEL_PRSCH1 << 6)  /**< Shifted mode PRSCH1 for PRS_DMAREQ0 */
+#define PRS_DMAREQ0_PRSSEL_PRSCH2              (_PRS_DMAREQ0_PRSSEL_PRSCH2 << 6)  /**< Shifted mode PRSCH2 for PRS_DMAREQ0 */
+#define PRS_DMAREQ0_PRSSEL_PRSCH3              (_PRS_DMAREQ0_PRSSEL_PRSCH3 << 6)  /**< Shifted mode PRSCH3 for PRS_DMAREQ0 */
+#define PRS_DMAREQ0_PRSSEL_PRSCH4              (_PRS_DMAREQ0_PRSSEL_PRSCH4 << 6)  /**< Shifted mode PRSCH4 for PRS_DMAREQ0 */
+#define PRS_DMAREQ0_PRSSEL_PRSCH5              (_PRS_DMAREQ0_PRSSEL_PRSCH5 << 6)  /**< Shifted mode PRSCH5 for PRS_DMAREQ0 */
+#define PRS_DMAREQ0_PRSSEL_PRSCH6              (_PRS_DMAREQ0_PRSSEL_PRSCH6 << 6)  /**< Shifted mode PRSCH6 for PRS_DMAREQ0 */
+#define PRS_DMAREQ0_PRSSEL_PRSCH7              (_PRS_DMAREQ0_PRSSEL_PRSCH7 << 6)  /**< Shifted mode PRSCH7 for PRS_DMAREQ0 */
+#define PRS_DMAREQ0_PRSSEL_PRSCH8              (_PRS_DMAREQ0_PRSSEL_PRSCH8 << 6)  /**< Shifted mode PRSCH8 for PRS_DMAREQ0 */
+#define PRS_DMAREQ0_PRSSEL_PRSCH9              (_PRS_DMAREQ0_PRSSEL_PRSCH9 << 6)  /**< Shifted mode PRSCH9 for PRS_DMAREQ0 */
+#define PRS_DMAREQ0_PRSSEL_PRSCH10             (_PRS_DMAREQ0_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ0 */
+#define PRS_DMAREQ0_PRSSEL_PRSCH11             (_PRS_DMAREQ0_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ0 */
+
+/* Bit fields for PRS DMAREQ1 */
+#define _PRS_DMAREQ1_RESETVALUE                0x00000000UL                       /**< Default value for PRS_DMAREQ1 */
+#define _PRS_DMAREQ1_MASK                      0x000003C0UL                       /**< Mask for PRS_DMAREQ1 */
+#define _PRS_DMAREQ1_PRSSEL_SHIFT              6                                  /**< Shift value for PRS_PRSSEL */
+#define _PRS_DMAREQ1_PRSSEL_MASK               0x3C0UL                            /**< Bit mask for PRS_PRSSEL */
+#define _PRS_DMAREQ1_PRSSEL_DEFAULT            0x00000000UL                       /**< Mode DEFAULT for PRS_DMAREQ1 */
+#define _PRS_DMAREQ1_PRSSEL_PRSCH0             0x00000000UL                       /**< Mode PRSCH0 for PRS_DMAREQ1 */
+#define _PRS_DMAREQ1_PRSSEL_PRSCH1             0x00000001UL                       /**< Mode PRSCH1 for PRS_DMAREQ1 */
+#define _PRS_DMAREQ1_PRSSEL_PRSCH2             0x00000002UL                       /**< Mode PRSCH2 for PRS_DMAREQ1 */
+#define _PRS_DMAREQ1_PRSSEL_PRSCH3             0x00000003UL                       /**< Mode PRSCH3 for PRS_DMAREQ1 */
+#define _PRS_DMAREQ1_PRSSEL_PRSCH4             0x00000004UL                       /**< Mode PRSCH4 for PRS_DMAREQ1 */
+#define _PRS_DMAREQ1_PRSSEL_PRSCH5             0x00000005UL                       /**< Mode PRSCH5 for PRS_DMAREQ1 */
+#define _PRS_DMAREQ1_PRSSEL_PRSCH6             0x00000006UL                       /**< Mode PRSCH6 for PRS_DMAREQ1 */
+#define _PRS_DMAREQ1_PRSSEL_PRSCH7             0x00000007UL                       /**< Mode PRSCH7 for PRS_DMAREQ1 */
+#define _PRS_DMAREQ1_PRSSEL_PRSCH8             0x00000008UL                       /**< Mode PRSCH8 for PRS_DMAREQ1 */
+#define _PRS_DMAREQ1_PRSSEL_PRSCH9             0x00000009UL                       /**< Mode PRSCH9 for PRS_DMAREQ1 */
+#define _PRS_DMAREQ1_PRSSEL_PRSCH10            0x0000000AUL                       /**< Mode PRSCH10 for PRS_DMAREQ1 */
+#define _PRS_DMAREQ1_PRSSEL_PRSCH11            0x0000000BUL                       /**< Mode PRSCH11 for PRS_DMAREQ1 */
+#define PRS_DMAREQ1_PRSSEL_DEFAULT             (_PRS_DMAREQ1_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ1 */
+#define PRS_DMAREQ1_PRSSEL_PRSCH0              (_PRS_DMAREQ1_PRSSEL_PRSCH0 << 6)  /**< Shifted mode PRSCH0 for PRS_DMAREQ1 */
+#define PRS_DMAREQ1_PRSSEL_PRSCH1              (_PRS_DMAREQ1_PRSSEL_PRSCH1 << 6)  /**< Shifted mode PRSCH1 for PRS_DMAREQ1 */
+#define PRS_DMAREQ1_PRSSEL_PRSCH2              (_PRS_DMAREQ1_PRSSEL_PRSCH2 << 6)  /**< Shifted mode PRSCH2 for PRS_DMAREQ1 */
+#define PRS_DMAREQ1_PRSSEL_PRSCH3              (_PRS_DMAREQ1_PRSSEL_PRSCH3 << 6)  /**< Shifted mode PRSCH3 for PRS_DMAREQ1 */
+#define PRS_DMAREQ1_PRSSEL_PRSCH4              (_PRS_DMAREQ1_PRSSEL_PRSCH4 << 6)  /**< Shifted mode PRSCH4 for PRS_DMAREQ1 */
+#define PRS_DMAREQ1_PRSSEL_PRSCH5              (_PRS_DMAREQ1_PRSSEL_PRSCH5 << 6)  /**< Shifted mode PRSCH5 for PRS_DMAREQ1 */
+#define PRS_DMAREQ1_PRSSEL_PRSCH6              (_PRS_DMAREQ1_PRSSEL_PRSCH6 << 6)  /**< Shifted mode PRSCH6 for PRS_DMAREQ1 */
+#define PRS_DMAREQ1_PRSSEL_PRSCH7              (_PRS_DMAREQ1_PRSSEL_PRSCH7 << 6)  /**< Shifted mode PRSCH7 for PRS_DMAREQ1 */
+#define PRS_DMAREQ1_PRSSEL_PRSCH8              (_PRS_DMAREQ1_PRSSEL_PRSCH8 << 6)  /**< Shifted mode PRSCH8 for PRS_DMAREQ1 */
+#define PRS_DMAREQ1_PRSSEL_PRSCH9              (_PRS_DMAREQ1_PRSSEL_PRSCH9 << 6)  /**< Shifted mode PRSCH9 for PRS_DMAREQ1 */
+#define PRS_DMAREQ1_PRSSEL_PRSCH10             (_PRS_DMAREQ1_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ1 */
+#define PRS_DMAREQ1_PRSSEL_PRSCH11             (_PRS_DMAREQ1_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ1 */
+
+/* Bit fields for PRS PEEK */
+#define _PRS_PEEK_RESETVALUE                   0x00000000UL                      /**< Default value for PRS_PEEK */
+#define _PRS_PEEK_MASK                         0x00000FFFUL                      /**< Mask for PRS_PEEK */
+#define PRS_PEEK_CH0VAL                        (0x1UL << 0)                      /**< Channel 0 Current Value */
+#define _PRS_PEEK_CH0VAL_SHIFT                 0                                 /**< Shift value for PRS_CH0VAL */
+#define _PRS_PEEK_CH0VAL_MASK                  0x1UL                             /**< Bit mask for PRS_CH0VAL */
+#define _PRS_PEEK_CH0VAL_DEFAULT               0x00000000UL                      /**< Mode DEFAULT for PRS_PEEK */
+#define PRS_PEEK_CH0VAL_DEFAULT                (_PRS_PEEK_CH0VAL_DEFAULT << 0)   /**< Shifted mode DEFAULT for PRS_PEEK */
+#define PRS_PEEK_CH1VAL                        (0x1UL << 1)                      /**< Channel 1 Current Value */
+#define _PRS_PEEK_CH1VAL_SHIFT                 1                                 /**< Shift value for PRS_CH1VAL */
+#define _PRS_PEEK_CH1VAL_MASK                  0x2UL                             /**< Bit mask for PRS_CH1VAL */
+#define _PRS_PEEK_CH1VAL_DEFAULT               0x00000000UL                      /**< Mode DEFAULT for PRS_PEEK */
+#define PRS_PEEK_CH1VAL_DEFAULT                (_PRS_PEEK_CH1VAL_DEFAULT << 1)   /**< Shifted mode DEFAULT for PRS_PEEK */
+#define PRS_PEEK_CH2VAL                        (0x1UL << 2)                      /**< Channel 2 Current Value */
+#define _PRS_PEEK_CH2VAL_SHIFT                 2                                 /**< Shift value for PRS_CH2VAL */
+#define _PRS_PEEK_CH2VAL_MASK                  0x4UL                             /**< Bit mask for PRS_CH2VAL */
+#define _PRS_PEEK_CH2VAL_DEFAULT               0x00000000UL                      /**< Mode DEFAULT for PRS_PEEK */
+#define PRS_PEEK_CH2VAL_DEFAULT                (_PRS_PEEK_CH2VAL_DEFAULT << 2)   /**< Shifted mode DEFAULT for PRS_PEEK */
+#define PRS_PEEK_CH3VAL                        (0x1UL << 3)                      /**< Channel 3 Current Value */
+#define _PRS_PEEK_CH3VAL_SHIFT                 3                                 /**< Shift value for PRS_CH3VAL */
+#define _PRS_PEEK_CH3VAL_MASK                  0x8UL                             /**< Bit mask for PRS_CH3VAL */
+#define _PRS_PEEK_CH3VAL_DEFAULT               0x00000000UL                      /**< Mode DEFAULT for PRS_PEEK */
+#define PRS_PEEK_CH3VAL_DEFAULT                (_PRS_PEEK_CH3VAL_DEFAULT << 3)   /**< Shifted mode DEFAULT for PRS_PEEK */
+#define PRS_PEEK_CH4VAL                        (0x1UL << 4)                      /**< Channel 4 Current Value */
+#define _PRS_PEEK_CH4VAL_SHIFT                 4                                 /**< Shift value for PRS_CH4VAL */
+#define _PRS_PEEK_CH4VAL_MASK                  0x10UL                            /**< Bit mask for PRS_CH4VAL */
+#define _PRS_PEEK_CH4VAL_DEFAULT               0x00000000UL                      /**< Mode DEFAULT for PRS_PEEK */
+#define PRS_PEEK_CH4VAL_DEFAULT                (_PRS_PEEK_CH4VAL_DEFAULT << 4)   /**< Shifted mode DEFAULT for PRS_PEEK */
+#define PRS_PEEK_CH5VAL                        (0x1UL << 5)                      /**< Channel 5 Current Value */
+#define _PRS_PEEK_CH5VAL_SHIFT                 5                                 /**< Shift value for PRS_CH5VAL */
+#define _PRS_PEEK_CH5VAL_MASK                  0x20UL                            /**< Bit mask for PRS_CH5VAL */
+#define _PRS_PEEK_CH5VAL_DEFAULT               0x00000000UL                      /**< Mode DEFAULT for PRS_PEEK */
+#define PRS_PEEK_CH5VAL_DEFAULT                (_PRS_PEEK_CH5VAL_DEFAULT << 5)   /**< Shifted mode DEFAULT for PRS_PEEK */
+#define PRS_PEEK_CH6VAL                        (0x1UL << 6)                      /**< Channel 6 Current Value */
+#define _PRS_PEEK_CH6VAL_SHIFT                 6                                 /**< Shift value for PRS_CH6VAL */
+#define _PRS_PEEK_CH6VAL_MASK                  0x40UL                            /**< Bit mask for PRS_CH6VAL */
+#define _PRS_PEEK_CH6VAL_DEFAULT               0x00000000UL                      /**< Mode DEFAULT for PRS_PEEK */
+#define PRS_PEEK_CH6VAL_DEFAULT                (_PRS_PEEK_CH6VAL_DEFAULT << 6)   /**< Shifted mode DEFAULT for PRS_PEEK */
+#define PRS_PEEK_CH7VAL                        (0x1UL << 7)                      /**< Channel 7 Current Value */
+#define _PRS_PEEK_CH7VAL_SHIFT                 7                                 /**< Shift value for PRS_CH7VAL */
+#define _PRS_PEEK_CH7VAL_MASK                  0x80UL                            /**< Bit mask for PRS_CH7VAL */
+#define _PRS_PEEK_CH7VAL_DEFAULT               0x00000000UL                      /**< Mode DEFAULT for PRS_PEEK */
+#define PRS_PEEK_CH7VAL_DEFAULT                (_PRS_PEEK_CH7VAL_DEFAULT << 7)   /**< Shifted mode DEFAULT for PRS_PEEK */
+#define PRS_PEEK_CH8VAL                        (0x1UL << 8)                      /**< Channel 8 Current Value */
+#define _PRS_PEEK_CH8VAL_SHIFT                 8                                 /**< Shift value for PRS_CH8VAL */
+#define _PRS_PEEK_CH8VAL_MASK                  0x100UL                           /**< Bit mask for PRS_CH8VAL */
+#define _PRS_PEEK_CH8VAL_DEFAULT               0x00000000UL                      /**< Mode DEFAULT for PRS_PEEK */
+#define PRS_PEEK_CH8VAL_DEFAULT                (_PRS_PEEK_CH8VAL_DEFAULT << 8)   /**< Shifted mode DEFAULT for PRS_PEEK */
+#define PRS_PEEK_CH9VAL                        (0x1UL << 9)                      /**< Channel 9 Current Value */
+#define _PRS_PEEK_CH9VAL_SHIFT                 9                                 /**< Shift value for PRS_CH9VAL */
+#define _PRS_PEEK_CH9VAL_MASK                  0x200UL                           /**< Bit mask for PRS_CH9VAL */
+#define _PRS_PEEK_CH9VAL_DEFAULT               0x00000000UL                      /**< Mode DEFAULT for PRS_PEEK */
+#define PRS_PEEK_CH9VAL_DEFAULT                (_PRS_PEEK_CH9VAL_DEFAULT << 9)   /**< Shifted mode DEFAULT for PRS_PEEK */
+#define PRS_PEEK_CH10VAL                       (0x1UL << 10)                     /**< Channel 10 Current Value */
+#define _PRS_PEEK_CH10VAL_SHIFT                10                                /**< Shift value for PRS_CH10VAL */
+#define _PRS_PEEK_CH10VAL_MASK                 0x400UL                           /**< Bit mask for PRS_CH10VAL */
+#define _PRS_PEEK_CH10VAL_DEFAULT              0x00000000UL                      /**< Mode DEFAULT for PRS_PEEK */
+#define PRS_PEEK_CH10VAL_DEFAULT               (_PRS_PEEK_CH10VAL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_PEEK */
+#define PRS_PEEK_CH11VAL                       (0x1UL << 11)                     /**< Channel 11 Current Value */
+#define _PRS_PEEK_CH11VAL_SHIFT                11                                /**< Shift value for PRS_CH11VAL */
+#define _PRS_PEEK_CH11VAL_MASK                 0x800UL                           /**< Bit mask for PRS_CH11VAL */
+#define _PRS_PEEK_CH11VAL_DEFAULT              0x00000000UL                      /**< Mode DEFAULT for PRS_PEEK */
+#define PRS_PEEK_CH11VAL_DEFAULT               (_PRS_PEEK_CH11VAL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_PEEK */
+
+/* Bit fields for PRS CH_CTRL */
+#define _PRS_CH_CTRL_RESETVALUE                0x00000000UL                               /**< Default value for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_MASK                      0x5E307F07UL                               /**< Mask for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_SHIFT              0                                          /**< Shift value for PRS_SIGSEL */
+#define _PRS_CH_CTRL_SIGSEL_MASK               0x7UL                                      /**< Bit mask for PRS_SIGSEL */
+#define _PRS_CH_CTRL_SIGSEL_PRSCH0             0x00000000UL                               /**< Mode PRSCH0 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_PRSCH8             0x00000000UL                               /**< Mode PRSCH8 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_ACMP0OUT           0x00000000UL                               /**< Mode ACMP0OUT for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_ACMP1OUT           0x00000000UL                               /**< Mode ACMP1OUT for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE         0x00000000UL                               /**< Mode ADC0SINGLE for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_USART0IRTX         0x00000000UL                               /**< Mode USART0IRTX for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_TIMER0UF           0x00000000UL                               /**< Mode TIMER0UF for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_TIMER1UF           0x00000000UL                               /**< Mode TIMER1UF for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN0           0x00000000UL                               /**< Mode GPIOPIN0 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN8           0x00000000UL                               /**< Mode GPIOPIN8 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0        0x00000000UL                               /**< Mode LETIMER0CH0 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_PCNT0TCC           0x00000000UL                               /**< Mode PCNT0TCC for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD    0x00000000UL                               /**< Mode CRYOTIMERPERIOD for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT0         0x00000000UL                               /**< Mode CMUCLKOUT0 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_PRSCH1             0x00000001UL                               /**< Mode PRSCH1 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_PRSCH9             0x00000001UL                               /**< Mode PRSCH9 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_ADC0SCAN           0x00000001UL                               /**< Mode ADC0SCAN for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_USART0TXC          0x00000001UL                               /**< Mode USART0TXC for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_USART1TXC          0x00000001UL                               /**< Mode USART1TXC for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_TIMER0OF           0x00000001UL                               /**< Mode TIMER0OF for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_TIMER1OF           0x00000001UL                               /**< Mode TIMER1OF for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_RTCCCCV0           0x00000001UL                               /**< Mode RTCCCCV0 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN1           0x00000001UL                               /**< Mode GPIOPIN1 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN9           0x00000001UL                               /**< Mode GPIOPIN9 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1        0x00000001UL                               /**< Mode LETIMER0CH1 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_PCNT0UFOF          0x00000001UL                               /**< Mode PCNT0UFOF for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT1         0x00000001UL                               /**< Mode CMUCLKOUT1 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_PRSCH2             0x00000002UL                               /**< Mode PRSCH2 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_PRSCH10            0x00000002UL                               /**< Mode PRSCH10 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV      0x00000002UL                               /**< Mode USART0RXDATAV for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV      0x00000002UL                               /**< Mode USART1RXDATAV for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_TIMER0CC0          0x00000002UL                               /**< Mode TIMER0CC0 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_TIMER1CC0          0x00000002UL                               /**< Mode TIMER1CC0 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_RTCCCCV1           0x00000002UL                               /**< Mode RTCCCCV1 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN2           0x00000002UL                               /**< Mode GPIOPIN2 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN10          0x00000002UL                               /**< Mode GPIOPIN10 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_PCNT0DIR           0x00000002UL                               /**< Mode PCNT0DIR for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_PRSCH3             0x00000003UL                               /**< Mode PRSCH3 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_PRSCH11            0x00000003UL                               /**< Mode PRSCH11 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_USART0RTS          0x00000003UL                               /**< Mode USART0RTS for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_USART1RTS          0x00000003UL                               /**< Mode USART1RTS for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_TIMER0CC1          0x00000003UL                               /**< Mode TIMER0CC1 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_TIMER1CC1          0x00000003UL                               /**< Mode TIMER1CC1 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_RTCCCCV2           0x00000003UL                               /**< Mode RTCCCCV2 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN3           0x00000003UL                               /**< Mode GPIOPIN3 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN11          0x00000003UL                               /**< Mode GPIOPIN11 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_PRSCH4             0x00000004UL                               /**< Mode PRSCH4 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_TIMER0CC2          0x00000004UL                               /**< Mode TIMER0CC2 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_TIMER1CC2          0x00000004UL                               /**< Mode TIMER1CC2 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN4           0x00000004UL                               /**< Mode GPIOPIN4 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN12          0x00000004UL                               /**< Mode GPIOPIN12 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_PRSCH5             0x00000005UL                               /**< Mode PRSCH5 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_USART0TX           0x00000005UL                               /**< Mode USART0TX for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_USART1TX           0x00000005UL                               /**< Mode USART1TX for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_TIMER1CC3          0x00000005UL                               /**< Mode TIMER1CC3 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN5           0x00000005UL                               /**< Mode GPIOPIN5 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN13          0x00000005UL                               /**< Mode GPIOPIN13 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_PRSCH6             0x00000006UL                               /**< Mode PRSCH6 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_USART0CS           0x00000006UL                               /**< Mode USART0CS for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_USART1CS           0x00000006UL                               /**< Mode USART1CS for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN6           0x00000006UL                               /**< Mode GPIOPIN6 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN14          0x00000006UL                               /**< Mode GPIOPIN14 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_PRSCH7             0x00000007UL                               /**< Mode PRSCH7 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN7           0x00000007UL                               /**< Mode GPIOPIN7 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN15          0x00000007UL                               /**< Mode GPIOPIN15 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_PRSCH0              (_PRS_CH_CTRL_SIGSEL_PRSCH0 << 0)          /**< Shifted mode PRSCH0 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_PRSCH8              (_PRS_CH_CTRL_SIGSEL_PRSCH8 << 0)          /**< Shifted mode PRSCH8 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_ACMP0OUT            (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0)        /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_ACMP1OUT            (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0)        /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_ADC0SINGLE          (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0)      /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_USART0IRTX          (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0)      /**< Shifted mode USART0IRTX for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_TIMER0UF            (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0)        /**< Shifted mode TIMER0UF for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_TIMER1UF            (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0)        /**< Shifted mode TIMER1UF for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN0            (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0)        /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN8            (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0)        /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_LETIMER0CH0         (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0)     /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_PCNT0TCC            (_PRS_CH_CTRL_SIGSEL_PCNT0TCC << 0)        /**< Shifted mode PCNT0TCC for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD     (_PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD << 0) /**< Shifted mode CRYOTIMERPERIOD for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT0          (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 << 0)      /**< Shifted mode CMUCLKOUT0 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_PRSCH1              (_PRS_CH_CTRL_SIGSEL_PRSCH1 << 0)          /**< Shifted mode PRSCH1 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_PRSCH9              (_PRS_CH_CTRL_SIGSEL_PRSCH9 << 0)          /**< Shifted mode PRSCH9 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_ADC0SCAN            (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0)        /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_USART0TXC           (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0)       /**< Shifted mode USART0TXC for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_USART1TXC           (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0)       /**< Shifted mode USART1TXC for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_TIMER0OF            (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0)        /**< Shifted mode TIMER0OF for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_TIMER1OF            (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0)        /**< Shifted mode TIMER1OF for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_RTCCCCV0            (_PRS_CH_CTRL_SIGSEL_RTCCCCV0 << 0)        /**< Shifted mode RTCCCCV0 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN1            (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0)        /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN9            (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0)        /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_LETIMER0CH1         (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0)     /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_PCNT0UFOF           (_PRS_CH_CTRL_SIGSEL_PCNT0UFOF << 0)       /**< Shifted mode PCNT0UFOF for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT1          (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 << 0)      /**< Shifted mode CMUCLKOUT1 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_PRSCH2              (_PRS_CH_CTRL_SIGSEL_PRSCH2 << 0)          /**< Shifted mode PRSCH2 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_PRSCH10             (_PRS_CH_CTRL_SIGSEL_PRSCH10 << 0)         /**< Shifted mode PRSCH10 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_USART0RXDATAV       (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0)   /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV       (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0)   /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_TIMER0CC0           (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0)       /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_TIMER1CC0           (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0)       /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_RTCCCCV1            (_PRS_CH_CTRL_SIGSEL_RTCCCCV1 << 0)        /**< Shifted mode RTCCCCV1 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN2            (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0)        /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN10           (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0)       /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_PCNT0DIR            (_PRS_CH_CTRL_SIGSEL_PCNT0DIR << 0)        /**< Shifted mode PCNT0DIR for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_PRSCH3              (_PRS_CH_CTRL_SIGSEL_PRSCH3 << 0)          /**< Shifted mode PRSCH3 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_PRSCH11             (_PRS_CH_CTRL_SIGSEL_PRSCH11 << 0)         /**< Shifted mode PRSCH11 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_USART0RTS           (_PRS_CH_CTRL_SIGSEL_USART0RTS << 0)       /**< Shifted mode USART0RTS for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_USART1RTS           (_PRS_CH_CTRL_SIGSEL_USART1RTS << 0)       /**< Shifted mode USART1RTS for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_TIMER0CC1           (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0)       /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_TIMER1CC1           (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0)       /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_RTCCCCV2            (_PRS_CH_CTRL_SIGSEL_RTCCCCV2 << 0)        /**< Shifted mode RTCCCCV2 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN3            (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0)        /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN11           (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0)       /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_PRSCH4              (_PRS_CH_CTRL_SIGSEL_PRSCH4 << 0)          /**< Shifted mode PRSCH4 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_TIMER0CC2           (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0)       /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_TIMER1CC2           (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0)       /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN4            (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0)        /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN12           (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0)       /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_PRSCH5              (_PRS_CH_CTRL_SIGSEL_PRSCH5 << 0)          /**< Shifted mode PRSCH5 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_USART0TX            (_PRS_CH_CTRL_SIGSEL_USART0TX << 0)        /**< Shifted mode USART0TX for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_USART1TX            (_PRS_CH_CTRL_SIGSEL_USART1TX << 0)        /**< Shifted mode USART1TX for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_TIMER1CC3           (_PRS_CH_CTRL_SIGSEL_TIMER1CC3 << 0)       /**< Shifted mode TIMER1CC3 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN5            (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0)        /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN13           (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0)       /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_PRSCH6              (_PRS_CH_CTRL_SIGSEL_PRSCH6 << 0)          /**< Shifted mode PRSCH6 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_USART0CS            (_PRS_CH_CTRL_SIGSEL_USART0CS << 0)        /**< Shifted mode USART0CS for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_USART1CS            (_PRS_CH_CTRL_SIGSEL_USART1CS << 0)        /**< Shifted mode USART1CS for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN6            (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0)        /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN14           (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0)       /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_PRSCH7              (_PRS_CH_CTRL_SIGSEL_PRSCH7 << 0)          /**< Shifted mode PRSCH7 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN7            (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0)        /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN15           (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0)       /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SOURCESEL_SHIFT           8                                          /**< Shift value for PRS_SOURCESEL */
+#define _PRS_CH_CTRL_SOURCESEL_MASK            0x7F00UL                                   /**< Bit mask for PRS_SOURCESEL */
+#define _PRS_CH_CTRL_SOURCESEL_NONE            0x00000000UL                               /**< Mode NONE for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SOURCESEL_PRSL            0x00000001UL                               /**< Mode PRSL for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SOURCESEL_PRSH            0x00000002UL                               /**< Mode PRSH for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SOURCESEL_ACMP0           0x00000006UL                               /**< Mode ACMP0 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SOURCESEL_ACMP1           0x00000007UL                               /**< Mode ACMP1 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SOURCESEL_ADC0            0x00000008UL                               /**< Mode ADC0 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SOURCESEL_USART0          0x00000010UL                               /**< Mode USART0 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SOURCESEL_USART1          0x00000011UL                               /**< Mode USART1 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SOURCESEL_TIMER0          0x0000001CUL                               /**< Mode TIMER0 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SOURCESEL_TIMER1          0x0000001DUL                               /**< Mode TIMER1 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SOURCESEL_RTCC            0x00000029UL                               /**< Mode RTCC for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SOURCESEL_GPIOL           0x00000030UL                               /**< Mode GPIOL for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SOURCESEL_GPIOH           0x00000031UL                               /**< Mode GPIOH for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SOURCESEL_LETIMER0        0x00000034UL                               /**< Mode LETIMER0 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SOURCESEL_PCNT0           0x00000036UL                               /**< Mode PCNT0 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SOURCESEL_CRYOTIMER       0x0000003CUL                               /**< Mode CRYOTIMER for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SOURCESEL_CMU             0x0000003DUL                               /**< Mode CMU for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SOURCESEL_NONE             (_PRS_CH_CTRL_SOURCESEL_NONE << 8)         /**< Shifted mode NONE for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SOURCESEL_PRSL             (_PRS_CH_CTRL_SOURCESEL_PRSL << 8)         /**< Shifted mode PRSL for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SOURCESEL_PRSH             (_PRS_CH_CTRL_SOURCESEL_PRSH << 8)         /**< Shifted mode PRSH for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SOURCESEL_ACMP0            (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 8)        /**< Shifted mode ACMP0 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SOURCESEL_ACMP1            (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 8)        /**< Shifted mode ACMP1 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SOURCESEL_ADC0             (_PRS_CH_CTRL_SOURCESEL_ADC0 << 8)         /**< Shifted mode ADC0 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SOURCESEL_USART0           (_PRS_CH_CTRL_SOURCESEL_USART0 << 8)       /**< Shifted mode USART0 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SOURCESEL_USART1           (_PRS_CH_CTRL_SOURCESEL_USART1 << 8)       /**< Shifted mode USART1 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SOURCESEL_TIMER0           (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 8)       /**< Shifted mode TIMER0 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SOURCESEL_TIMER1           (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 8)       /**< Shifted mode TIMER1 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SOURCESEL_RTCC             (_PRS_CH_CTRL_SOURCESEL_RTCC << 8)         /**< Shifted mode RTCC for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SOURCESEL_GPIOL            (_PRS_CH_CTRL_SOURCESEL_GPIOL << 8)        /**< Shifted mode GPIOL for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SOURCESEL_GPIOH            (_PRS_CH_CTRL_SOURCESEL_GPIOH << 8)        /**< Shifted mode GPIOH for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SOURCESEL_LETIMER0         (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 8)     /**< Shifted mode LETIMER0 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SOURCESEL_PCNT0            (_PRS_CH_CTRL_SOURCESEL_PCNT0 << 8)        /**< Shifted mode PCNT0 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SOURCESEL_CRYOTIMER        (_PRS_CH_CTRL_SOURCESEL_CRYOTIMER << 8)    /**< Shifted mode CRYOTIMER for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SOURCESEL_CMU              (_PRS_CH_CTRL_SOURCESEL_CMU << 8)          /**< Shifted mode CMU for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_EDSEL_SHIFT               20                                         /**< Shift value for PRS_EDSEL */
+#define _PRS_CH_CTRL_EDSEL_MASK                0x300000UL                                 /**< Bit mask for PRS_EDSEL */
+#define _PRS_CH_CTRL_EDSEL_DEFAULT             0x00000000UL                               /**< Mode DEFAULT for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_EDSEL_OFF                 0x00000000UL                               /**< Mode OFF for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_EDSEL_POSEDGE             0x00000001UL                               /**< Mode POSEDGE for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_EDSEL_NEGEDGE             0x00000002UL                               /**< Mode NEGEDGE for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_EDSEL_BOTHEDGES           0x00000003UL                               /**< Mode BOTHEDGES for PRS_CH_CTRL */
+#define PRS_CH_CTRL_EDSEL_DEFAULT              (_PRS_CH_CTRL_EDSEL_DEFAULT << 20)         /**< Shifted mode DEFAULT for PRS_CH_CTRL */
+#define PRS_CH_CTRL_EDSEL_OFF                  (_PRS_CH_CTRL_EDSEL_OFF << 20)             /**< Shifted mode OFF for PRS_CH_CTRL */
+#define PRS_CH_CTRL_EDSEL_POSEDGE              (_PRS_CH_CTRL_EDSEL_POSEDGE << 20)         /**< Shifted mode POSEDGE for PRS_CH_CTRL */
+#define PRS_CH_CTRL_EDSEL_NEGEDGE              (_PRS_CH_CTRL_EDSEL_NEGEDGE << 20)         /**< Shifted mode NEGEDGE for PRS_CH_CTRL */
+#define PRS_CH_CTRL_EDSEL_BOTHEDGES            (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 20)       /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */
+#define PRS_CH_CTRL_STRETCH                    (0x1UL << 25)                              /**< Stretch Channel Output */
+#define _PRS_CH_CTRL_STRETCH_SHIFT             25                                         /**< Shift value for PRS_STRETCH */
+#define _PRS_CH_CTRL_STRETCH_MASK              0x2000000UL                                /**< Bit mask for PRS_STRETCH */
+#define _PRS_CH_CTRL_STRETCH_DEFAULT           0x00000000UL                               /**< Mode DEFAULT for PRS_CH_CTRL */
+#define PRS_CH_CTRL_STRETCH_DEFAULT            (_PRS_CH_CTRL_STRETCH_DEFAULT << 25)       /**< Shifted mode DEFAULT for PRS_CH_CTRL */
+#define PRS_CH_CTRL_INV                        (0x1UL << 26)                              /**< Invert Channel */
+#define _PRS_CH_CTRL_INV_SHIFT                 26                                         /**< Shift value for PRS_INV */
+#define _PRS_CH_CTRL_INV_MASK                  0x4000000UL                                /**< Bit mask for PRS_INV */
+#define _PRS_CH_CTRL_INV_DEFAULT               0x00000000UL                               /**< Mode DEFAULT for PRS_CH_CTRL */
+#define PRS_CH_CTRL_INV_DEFAULT                (_PRS_CH_CTRL_INV_DEFAULT << 26)           /**< Shifted mode DEFAULT for PRS_CH_CTRL */
+#define PRS_CH_CTRL_ORPREV                     (0x1UL << 27)                              /**< Or Previous */
+#define _PRS_CH_CTRL_ORPREV_SHIFT              27                                         /**< Shift value for PRS_ORPREV */
+#define _PRS_CH_CTRL_ORPREV_MASK               0x8000000UL                                /**< Bit mask for PRS_ORPREV */
+#define _PRS_CH_CTRL_ORPREV_DEFAULT            0x00000000UL                               /**< Mode DEFAULT for PRS_CH_CTRL */
+#define PRS_CH_CTRL_ORPREV_DEFAULT             (_PRS_CH_CTRL_ORPREV_DEFAULT << 27)        /**< Shifted mode DEFAULT for PRS_CH_CTRL */
+#define PRS_CH_CTRL_ANDNEXT                    (0x1UL << 28)                              /**< And Next */
+#define _PRS_CH_CTRL_ANDNEXT_SHIFT             28                                         /**< Shift value for PRS_ANDNEXT */
+#define _PRS_CH_CTRL_ANDNEXT_MASK              0x10000000UL                               /**< Bit mask for PRS_ANDNEXT */
+#define _PRS_CH_CTRL_ANDNEXT_DEFAULT           0x00000000UL                               /**< Mode DEFAULT for PRS_CH_CTRL */
+#define PRS_CH_CTRL_ANDNEXT_DEFAULT            (_PRS_CH_CTRL_ANDNEXT_DEFAULT << 28)       /**< Shifted mode DEFAULT for PRS_CH_CTRL */
+#define PRS_CH_CTRL_ASYNC                      (0x1UL << 30)                              /**< Asynchronous reflex */
+#define _PRS_CH_CTRL_ASYNC_SHIFT               30                                         /**< Shift value for PRS_ASYNC */
+#define _PRS_CH_CTRL_ASYNC_MASK                0x40000000UL                               /**< Bit mask for PRS_ASYNC */
+#define _PRS_CH_CTRL_ASYNC_DEFAULT             0x00000000UL                               /**< Mode DEFAULT for PRS_CH_CTRL */
+#define PRS_CH_CTRL_ASYNC_DEFAULT              (_PRS_CH_CTRL_ASYNC_DEFAULT << 30)         /**< Shifted mode DEFAULT for PRS_CH_CTRL */
+
+/** @} End of group EFM32PG1B_PRS */
+/** @} End of group Parts */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG_STK3401/efm32pg1b_prs_ch.h	Fri Jan 15 07:45:16 2016 +0000
@@ -0,0 +1,46 @@
+/**************************************************************************//**
+ * @file efm32pg1b_prs_ch.h
+ * @brief EFM32PG1B_PRS_CH register and bit field definitions
+ * @version 4.2.0
+ ******************************************************************************
+ * @section License
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ ******************************************************************************
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software.@n
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.@n
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is
+ * providing the Software "AS IS", with no express or implied warranties of any
+ * kind, including, but not limited to, any implied warranties of
+ * merchantability or fitness for any particular purpose or warranties against
+ * infringement of any proprietary rights of a third party.
+ *
+ * Silicon Laboratories, Inc. will not be liable for any consequential,
+ * incidental, or special damages, or any other relief, or for any claim by
+ * any third party, arising from your use of this Software.
+ *
+ *****************************************************************************/
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @brief PRS_CH EFM32PG1B PRS CH
+ *****************************************************************************/
+typedef struct
+{
+  __IO uint32_t CTRL; /**< Channel Control Register  */
+} PRS_CH_TypeDef;
+
+/** @} End of group Parts */
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG_STK3401/efm32pg1b_prs_signals.h	Fri Jan 15 07:45:16 2016 +0000
@@ -0,0 +1,109 @@
+/**************************************************************************//**
+ * @file efm32pg1b_prs_signals.h
+ * @brief EFM32PG1B_PRS_SIGNALS register and bit field definitions
+ * @version 4.2.0
+ ******************************************************************************
+ * @section License
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ ******************************************************************************
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software.@n
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.@n
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is
+ * providing the Software "AS IS", with no express or implied warranties of any
+ * kind, including, but not limited to, any implied warranties of
+ * merchantability or fitness for any particular purpose or warranties against
+ * infringement of any proprietary rights of a third party.
+ *
+ * Silicon Laboratories, Inc. will not be liable for any consequential,
+ * incidental, or special damages, or any other relief, or for any claim by
+ * any third party, arising from your use of this Software.
+ *
+ *****************************************************************************/
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @addtogroup EFM32PG1B_PRS_Signals
+ * @{
+ * @brief PRS Signal names
+ *****************************************************************************/
+#define PRS_PRS_CH0             ((1 << 8) + 0)  /**< PRS PRS channel 0 */
+#define PRS_PRS_CH1             ((1 << 8) + 1)  /**< PRS PRS channel 1 */
+#define PRS_PRS_CH2             ((1 << 8) + 2)  /**< PRS PRS channel 2 */
+#define PRS_PRS_CH3             ((1 << 8) + 3)  /**< PRS PRS channel 3 */
+#define PRS_PRS_CH4             ((1 << 8) + 4)  /**< PRS PRS channel 4 */
+#define PRS_PRS_CH5             ((1 << 8) + 5)  /**< PRS PRS channel 5 */
+#define PRS_PRS_CH6             ((1 << 8) + 6)  /**< PRS PRS channel 6 */
+#define PRS_PRS_CH7             ((1 << 8) + 7)  /**< PRS PRS channel 7 */
+#define PRS_PRS_CH8             ((2 << 8) + 0)  /**< PRS PRS channel 8 */
+#define PRS_PRS_CH9             ((2 << 8) + 1)  /**< PRS PRS channel 9 */
+#define PRS_PRS_CH10            ((2 << 8) + 2)  /**< PRS PRS channel 10 */
+#define PRS_PRS_CH11            ((2 << 8) + 3)  /**< PRS PRS channel 11 */
+#define PRS_ACMP0_OUT           ((6 << 8) + 0)  /**< PRS Analog comparator output */
+#define PRS_ACMP1_OUT           ((7 << 8) + 0)  /**< PRS Analog comparator output */
+#define PRS_ADC0_SINGLE         ((8 << 8) + 0)  /**< PRS ADC single conversion done */
+#define PRS_ADC0_SCAN           ((8 << 8) + 1)  /**< PRS ADC scan conversion done */
+#define PRS_USART0_IRTX         ((16 << 8) + 0) /**< PRS USART 0 IRDA out */
+#define PRS_USART0_TXC          ((16 << 8) + 1) /**< PRS USART 0 TX complete */
+#define PRS_USART0_RXDATAV      ((16 << 8) + 2) /**< PRS USART 0 RX Data Valid */
+#define PRS_USART0_RTS          ((16 << 8) + 3) /**< PRS USART 0 RTS */
+#define PRS_USART0_TX           ((16 << 8) + 5) /**< PRS USART 0 TX */
+#define PRS_USART0_CS           ((16 << 8) + 6) /**< PRS USART 0 CS */
+#define PRS_USART1_TXC          ((17 << 8) + 1) /**< PRS USART 1 TX complete */
+#define PRS_USART1_RXDATAV      ((17 << 8) + 2) /**< PRS USART 1 RX Data Valid */
+#define PRS_USART1_RTS          ((17 << 8) + 3) /**< PRS USART 0 RTS */
+#define PRS_USART1_TX           ((17 << 8) + 5) /**< PRS USART 1 TX */
+#define PRS_USART1_CS           ((17 << 8) + 6) /**< PRS USART 1 CS */
+#define PRS_TIMER0_UF           ((28 << 8) + 0) /**< PRS Timer 0 Underflow */
+#define PRS_TIMER0_OF           ((28 << 8) + 1) /**< PRS Timer 0 Overflow */
+#define PRS_TIMER0_CC0          ((28 << 8) + 2) /**< PRS Timer 0 Compare/Capture 0 */
+#define PRS_TIMER0_CC1          ((28 << 8) + 3) /**< PRS Timer 0 Compare/Capture 1 */
+#define PRS_TIMER0_CC2          ((28 << 8) + 4) /**< PRS Timer 0 Compare/Capture 2 */
+#define PRS_TIMER1_UF           ((29 << 8) + 0) /**< PRS Timer 1 Underflow */
+#define PRS_TIMER1_OF           ((29 << 8) + 1) /**< PRS Timer 1 Overflow */
+#define PRS_TIMER1_CC0          ((29 << 8) + 2) /**< PRS Timer 1 Compare/Capture 0 */
+#define PRS_TIMER1_CC1          ((29 << 8) + 3) /**< PRS Timer 1 Compare/Capture 1 */
+#define PRS_TIMER1_CC2          ((29 << 8) + 4) /**< PRS Timer 1 Compare/Capture 2 */
+#define PRS_TIMER1_CC3          ((29 << 8) + 5) /**< PRS Timer 1 Compare/Capture 3 */
+#define PRS_RTCC_CCV0           ((41 << 8) + 1) /**< PRS RTCC Compare 0 */
+#define PRS_RTCC_CCV1           ((41 << 8) + 2) /**< PRS RTCC Compare 1 */
+#define PRS_RTCC_CCV2           ((41 << 8) + 3) /**< PRS RTCC Compare 2 */
+#define PRS_GPIO_PIN0           ((48 << 8) + 0) /**< PRS GPIO pin 0 */
+#define PRS_GPIO_PIN1           ((48 << 8) + 1) /**< PRS GPIO pin 1 */
+#define PRS_GPIO_PIN2           ((48 << 8) + 2) /**< PRS GPIO pin 2 */
+#define PRS_GPIO_PIN3           ((48 << 8) + 3) /**< PRS GPIO pin 3 */
+#define PRS_GPIO_PIN4           ((48 << 8) + 4) /**< PRS GPIO pin 4 */
+#define PRS_GPIO_PIN5           ((48 << 8) + 5) /**< PRS GPIO pin 5 */
+#define PRS_GPIO_PIN6           ((48 << 8) + 6) /**< PRS GPIO pin 6 */
+#define PRS_GPIO_PIN7           ((48 << 8) + 7) /**< PRS GPIO pin 7 */
+#define PRS_GPIO_PIN8           ((49 << 8) + 0) /**< PRS GPIO pin 8 */
+#define PRS_GPIO_PIN9           ((49 << 8) + 1) /**< PRS GPIO pin 9 */
+#define PRS_GPIO_PIN10          ((49 << 8) + 2) /**< PRS GPIO pin 10 */
+#define PRS_GPIO_PIN11          ((49 << 8) + 3) /**< PRS GPIO pin 11 */
+#define PRS_GPIO_PIN12          ((49 << 8) + 4) /**< PRS GPIO pin 12 */
+#define PRS_GPIO_PIN13          ((49 << 8) + 5) /**< PRS GPIO pin 13 */
+#define PRS_GPIO_PIN14          ((49 << 8) + 6) /**< PRS GPIO pin 14 */
+#define PRS_GPIO_PIN15          ((49 << 8) + 7) /**< PRS GPIO pin 15 */
+#define PRS_LETIMER0_CH0        ((52 << 8) + 0) /**< PRS LETIMER CH0 Out */
+#define PRS_LETIMER0_CH1        ((52 << 8) + 1) /**< PRS LETIMER CH1 Out */
+#define PRS_PCNT0_TCC           ((54 << 8) + 0) /**< PRS Triggered compare match */
+#define PRS_PCNT0_UFOF          ((54 << 8) + 1) /**< PRS Counter overflow or underflow */
+#define PRS_PCNT0_DIR           ((54 << 8) + 2) /**< PRS Counter direction */
+#define PRS_CRYOTIMER_PERIOD    ((60 << 8) + 0) /**< PRS CRYOTIMER Output */
+#define PRS_CMU_CLKOUT0         ((61 << 8) + 0) /**< PRS Clock Output 0 */
+#define PRS_CMU_CLKOUT1         ((61 << 8) + 1) /**< PRS Clock Output 1 */
+
+/** @} End of group EFM32PG1B_PRS */
+/** @} End of group Parts */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG_STK3401/efm32pg1b_rmu.h	Fri Jan 15 07:45:16 2016 +0000
@@ -0,0 +1,191 @@
+/**************************************************************************//**
+ * @file efm32pg1b_rmu.h
+ * @brief EFM32PG1B_RMU register and bit field definitions
+ * @version 4.2.0
+ ******************************************************************************
+ * @section License
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ ******************************************************************************
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software.@n
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.@n
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is
+ * providing the Software "AS IS", with no express or implied warranties of any
+ * kind, including, but not limited to, any implied warranties of
+ * merchantability or fitness for any particular purpose or warranties against
+ * infringement of any proprietary rights of a third party.
+ *
+ * Silicon Laboratories, Inc. will not be liable for any consequential,
+ * incidental, or special damages, or any other relief, or for any claim by
+ * any third party, arising from your use of this Software.
+ *
+ *****************************************************************************/
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFM32PG1B_RMU
+ * @{
+ * @brief EFM32PG1B_RMU Register Declaration
+ *****************************************************************************/
+typedef struct
+{
+  __IO uint32_t CTRL;     /**< Control Register  */
+  __I uint32_t  RSTCAUSE; /**< Reset Cause Register  */
+  __IO uint32_t CMD;      /**< Command Register  */
+  __IO uint32_t RST;      /**< Reset Control Register  */
+  __IO uint32_t LOCK;     /**< Configuration Lock Register  */
+} RMU_TypeDef;            /** @} */
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B_RMU_BitFields
+ * @{
+ *****************************************************************************/
+
+/* Bit fields for RMU CTRL */
+#define _RMU_CTRL_RESETVALUE               0x00004224UL                          /**< Default value for RMU_CTRL */
+#define _RMU_CTRL_MASK                     0x03007777UL                          /**< Mask for RMU_CTRL */
+#define _RMU_CTRL_WDOGRMODE_SHIFT          0                                     /**< Shift value for RMU_WDOGRMODE */
+#define _RMU_CTRL_WDOGRMODE_MASK           0x7UL                                 /**< Bit mask for RMU_WDOGRMODE */
+#define _RMU_CTRL_WDOGRMODE_DISABLED       0x00000000UL                          /**< Mode DISABLED for RMU_CTRL */
+#define _RMU_CTRL_WDOGRMODE_LIMITED        0x00000001UL                          /**< Mode LIMITED for RMU_CTRL */
+#define _RMU_CTRL_WDOGRMODE_EXTENDED       0x00000002UL                          /**< Mode EXTENDED for RMU_CTRL */
+#define _RMU_CTRL_WDOGRMODE_DEFAULT        0x00000004UL                          /**< Mode DEFAULT for RMU_CTRL */
+#define _RMU_CTRL_WDOGRMODE_FULL           0x00000004UL                          /**< Mode FULL for RMU_CTRL */
+#define RMU_CTRL_WDOGRMODE_DISABLED        (_RMU_CTRL_WDOGRMODE_DISABLED << 0)   /**< Shifted mode DISABLED for RMU_CTRL */
+#define RMU_CTRL_WDOGRMODE_LIMITED         (_RMU_CTRL_WDOGRMODE_LIMITED << 0)    /**< Shifted mode LIMITED for RMU_CTRL */
+#define RMU_CTRL_WDOGRMODE_EXTENDED        (_RMU_CTRL_WDOGRMODE_EXTENDED << 0)   /**< Shifted mode EXTENDED for RMU_CTRL */
+#define RMU_CTRL_WDOGRMODE_DEFAULT         (_RMU_CTRL_WDOGRMODE_DEFAULT << 0)    /**< Shifted mode DEFAULT for RMU_CTRL */
+#define RMU_CTRL_WDOGRMODE_FULL            (_RMU_CTRL_WDOGRMODE_FULL << 0)       /**< Shifted mode FULL for RMU_CTRL */
+#define _RMU_CTRL_LOCKUPRMODE_SHIFT        4                                     /**< Shift value for RMU_LOCKUPRMODE */
+#define _RMU_CTRL_LOCKUPRMODE_MASK         0x70UL                                /**< Bit mask for RMU_LOCKUPRMODE */
+#define _RMU_CTRL_LOCKUPRMODE_DISABLED     0x00000000UL                          /**< Mode DISABLED for RMU_CTRL */
+#define _RMU_CTRL_LOCKUPRMODE_LIMITED      0x00000001UL                          /**< Mode LIMITED for RMU_CTRL */
+#define _RMU_CTRL_LOCKUPRMODE_DEFAULT      0x00000002UL                          /**< Mode DEFAULT for RMU_CTRL */
+#define _RMU_CTRL_LOCKUPRMODE_EXTENDED     0x00000002UL                          /**< Mode EXTENDED for RMU_CTRL */
+#define _RMU_CTRL_LOCKUPRMODE_FULL         0x00000004UL                          /**< Mode FULL for RMU_CTRL */
+#define RMU_CTRL_LOCKUPRMODE_DISABLED      (_RMU_CTRL_LOCKUPRMODE_DISABLED << 4) /**< Shifted mode DISABLED for RMU_CTRL */
+#define RMU_CTRL_LOCKUPRMODE_LIMITED       (_RMU_CTRL_LOCKUPRMODE_LIMITED << 4)  /**< Shifted mode LIMITED for RMU_CTRL */
+#define RMU_CTRL_LOCKUPRMODE_DEFAULT       (_RMU_CTRL_LOCKUPRMODE_DEFAULT << 4)  /**< Shifted mode DEFAULT for RMU_CTRL */
+#define RMU_CTRL_LOCKUPRMODE_EXTENDED      (_RMU_CTRL_LOCKUPRMODE_EXTENDED << 4) /**< Shifted mode EXTENDED for RMU_CTRL */
+#define RMU_CTRL_LOCKUPRMODE_FULL          (_RMU_CTRL_LOCKUPRMODE_FULL << 4)     /**< Shifted mode FULL for RMU_CTRL */
+#define _RMU_CTRL_SYSRMODE_SHIFT           8                                     /**< Shift value for RMU_SYSRMODE */
+#define _RMU_CTRL_SYSRMODE_MASK            0x700UL                               /**< Bit mask for RMU_SYSRMODE */
+#define _RMU_CTRL_SYSRMODE_DISABLED        0x00000000UL                          /**< Mode DISABLED for RMU_CTRL */
+#define _RMU_CTRL_SYSRMODE_LIMITED         0x00000001UL                          /**< Mode LIMITED for RMU_CTRL */
+#define _RMU_CTRL_SYSRMODE_DEFAULT         0x00000002UL                          /**< Mode DEFAULT for RMU_CTRL */
+#define _RMU_CTRL_SYSRMODE_EXTENDED        0x00000002UL                          /**< Mode EXTENDED for RMU_CTRL */
+#define _RMU_CTRL_SYSRMODE_FULL            0x00000004UL                          /**< Mode FULL for RMU_CTRL */
+#define RMU_CTRL_SYSRMODE_DISABLED         (_RMU_CTRL_SYSRMODE_DISABLED << 8)    /**< Shifted mode DISABLED for RMU_CTRL */
+#define RMU_CTRL_SYSRMODE_LIMITED          (_RMU_CTRL_SYSRMODE_LIMITED << 8)     /**< Shifted mode LIMITED for RMU_CTRL */
+#define RMU_CTRL_SYSRMODE_DEFAULT          (_RMU_CTRL_SYSRMODE_DEFAULT << 8)     /**< Shifted mode DEFAULT for RMU_CTRL */
+#define RMU_CTRL_SYSRMODE_EXTENDED         (_RMU_CTRL_SYSRMODE_EXTENDED << 8)    /**< Shifted mode EXTENDED for RMU_CTRL */
+#define RMU_CTRL_SYSRMODE_FULL             (_RMU_CTRL_SYSRMODE_FULL << 8)        /**< Shifted mode FULL for RMU_CTRL */
+#define _RMU_CTRL_PINRMODE_SHIFT           12                                    /**< Shift value for RMU_PINRMODE */
+#define _RMU_CTRL_PINRMODE_MASK            0x7000UL                              /**< Bit mask for RMU_PINRMODE */
+#define _RMU_CTRL_PINRMODE_DISABLED        0x00000000UL                          /**< Mode DISABLED for RMU_CTRL */
+#define _RMU_CTRL_PINRMODE_LIMITED         0x00000001UL                          /**< Mode LIMITED for RMU_CTRL */
+#define _RMU_CTRL_PINRMODE_EXTENDED        0x00000002UL                          /**< Mode EXTENDED for RMU_CTRL */
+#define _RMU_CTRL_PINRMODE_DEFAULT         0x00000004UL                          /**< Mode DEFAULT for RMU_CTRL */
+#define _RMU_CTRL_PINRMODE_FULL            0x00000004UL                          /**< Mode FULL for RMU_CTRL */
+#define RMU_CTRL_PINRMODE_DISABLED         (_RMU_CTRL_PINRMODE_DISABLED << 12)   /**< Shifted mode DISABLED for RMU_CTRL */
+#define RMU_CTRL_PINRMODE_LIMITED          (_RMU_CTRL_PINRMODE_LIMITED << 12)    /**< Shifted mode LIMITED for RMU_CTRL */
+#define RMU_CTRL_PINRMODE_EXTENDED         (_RMU_CTRL_PINRMODE_EXTENDED << 12)   /**< Shifted mode EXTENDED for RMU_CTRL */
+#define RMU_CTRL_PINRMODE_DEFAULT          (_RMU_CTRL_PINRMODE_DEFAULT << 12)    /**< Shifted mode DEFAULT for RMU_CTRL */
+#define RMU_CTRL_PINRMODE_FULL             (_RMU_CTRL_PINRMODE_FULL << 12)       /**< Shifted mode FULL for RMU_CTRL */
+#define _RMU_CTRL_RESETSTATE_SHIFT         24                                    /**< Shift value for RMU_RESETSTATE */
+#define _RMU_CTRL_RESETSTATE_MASK          0x3000000UL                           /**< Bit mask for RMU_RESETSTATE */
+#define _RMU_CTRL_RESETSTATE_DEFAULT       0x00000000UL                          /**< Mode DEFAULT for RMU_CTRL */
+#define RMU_CTRL_RESETSTATE_DEFAULT        (_RMU_CTRL_RESETSTATE_DEFAULT << 24)  /**< Shifted mode DEFAULT for RMU_CTRL */
+
+/* Bit fields for RMU RSTCAUSE */
+#define _RMU_RSTCAUSE_RESETVALUE           0x00000000UL                            /**< Default value for RMU_RSTCAUSE */
+#define _RMU_RSTCAUSE_MASK                 0x00010F1DUL                            /**< Mask for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_PORST                 (0x1UL << 0)                            /**< Power On Reset */
+#define _RMU_RSTCAUSE_PORST_SHIFT          0                                       /**< Shift value for RMU_PORST */
+#define _RMU_RSTCAUSE_PORST_MASK           0x1UL                                   /**< Bit mask for RMU_PORST */
+#define _RMU_RSTCAUSE_PORST_DEFAULT        0x00000000UL                            /**< Mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_PORST_DEFAULT         (_RMU_RSTCAUSE_PORST_DEFAULT << 0)      /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_AVDDBOD               (0x1UL << 2)                            /**< Brown Out Detector AVDD Reset */
+#define _RMU_RSTCAUSE_AVDDBOD_SHIFT        2                                       /**< Shift value for RMU_AVDDBOD */
+#define _RMU_RSTCAUSE_AVDDBOD_MASK         0x4UL                                   /**< Bit mask for RMU_AVDDBOD */
+#define _RMU_RSTCAUSE_AVDDBOD_DEFAULT      0x00000000UL                            /**< Mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_AVDDBOD_DEFAULT       (_RMU_RSTCAUSE_AVDDBOD_DEFAULT << 2)    /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_DVDDBOD               (0x1UL << 3)                            /**< Brown Out Detector DVDD Reset */
+#define _RMU_RSTCAUSE_DVDDBOD_SHIFT        3                                       /**< Shift value for RMU_DVDDBOD */
+#define _RMU_RSTCAUSE_DVDDBOD_MASK         0x8UL                                   /**< Bit mask for RMU_DVDDBOD */
+#define _RMU_RSTCAUSE_DVDDBOD_DEFAULT      0x00000000UL                            /**< Mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_DVDDBOD_DEFAULT       (_RMU_RSTCAUSE_DVDDBOD_DEFAULT << 3)    /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_DECBOD                (0x1UL << 4)                            /**< Brown Out Detector Decouple Domain Reset */
+#define _RMU_RSTCAUSE_DECBOD_SHIFT         4                                       /**< Shift value for RMU_DECBOD */
+#define _RMU_RSTCAUSE_DECBOD_MASK          0x10UL                                  /**< Bit mask for RMU_DECBOD */
+#define _RMU_RSTCAUSE_DECBOD_DEFAULT       0x00000000UL                            /**< Mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_DECBOD_DEFAULT        (_RMU_RSTCAUSE_DECBOD_DEFAULT << 4)     /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_EXTRST                (0x1UL << 8)                            /**< External Pin Reset */
+#define _RMU_RSTCAUSE_EXTRST_SHIFT         8                                       /**< Shift value for RMU_EXTRST */
+#define _RMU_RSTCAUSE_EXTRST_MASK          0x100UL                                 /**< Bit mask for RMU_EXTRST */
+#define _RMU_RSTCAUSE_EXTRST_DEFAULT       0x00000000UL                            /**< Mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_EXTRST_DEFAULT        (_RMU_RSTCAUSE_EXTRST_DEFAULT << 8)     /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_LOCKUPRST             (0x1UL << 9)                            /**< LOCKUP Reset */
+#define _RMU_RSTCAUSE_LOCKUPRST_SHIFT      9                                       /**< Shift value for RMU_LOCKUPRST */
+#define _RMU_RSTCAUSE_LOCKUPRST_MASK       0x200UL                                 /**< Bit mask for RMU_LOCKUPRST */
+#define _RMU_RSTCAUSE_LOCKUPRST_DEFAULT    0x00000000UL                            /**< Mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_LOCKUPRST_DEFAULT     (_RMU_RSTCAUSE_LOCKUPRST_DEFAULT << 9)  /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_SYSREQRST             (0x1UL << 10)                           /**< System Request Reset */
+#define _RMU_RSTCAUSE_SYSREQRST_SHIFT      10                                      /**< Shift value for RMU_SYSREQRST */
+#define _RMU_RSTCAUSE_SYSREQRST_MASK       0x400UL                                 /**< Bit mask for RMU_SYSREQRST */
+#define _RMU_RSTCAUSE_SYSREQRST_DEFAULT    0x00000000UL                            /**< Mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_SYSREQRST_DEFAULT     (_RMU_RSTCAUSE_SYSREQRST_DEFAULT << 10) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_WDOGRST               (0x1UL << 11)                           /**< Watchdog Reset */
+#define _RMU_RSTCAUSE_WDOGRST_SHIFT        11                                      /**< Shift value for RMU_WDOGRST */
+#define _RMU_RSTCAUSE_WDOGRST_MASK         0x800UL                                 /**< Bit mask for RMU_WDOGRST */
+#define _RMU_RSTCAUSE_WDOGRST_DEFAULT      0x00000000UL                            /**< Mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_WDOGRST_DEFAULT       (_RMU_RSTCAUSE_WDOGRST_DEFAULT << 11)   /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_EM4RST                (0x1UL << 16)                           /**< EM4 Reset */
+#define _RMU_RSTCAUSE_EM4RST_SHIFT         16                                      /**< Shift value for RMU_EM4RST */
+#define _RMU_RSTCAUSE_EM4RST_MASK          0x10000UL                               /**< Bit mask for RMU_EM4RST */
+#define _RMU_RSTCAUSE_EM4RST_DEFAULT       0x00000000UL                            /**< Mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_EM4RST_DEFAULT        (_RMU_RSTCAUSE_EM4RST_DEFAULT << 16)    /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
+
+/* Bit fields for RMU CMD */
+#define _RMU_CMD_RESETVALUE                0x00000000UL                  /**< Default value for RMU_CMD */
+#define _RMU_CMD_MASK                      0x00000001UL                  /**< Mask for RMU_CMD */
+#define RMU_CMD_RCCLR                      (0x1UL << 0)                  /**< Reset Cause Clear */
+#define _RMU_CMD_RCCLR_SHIFT               0                             /**< Shift value for RMU_RCCLR */
+#define _RMU_CMD_RCCLR_MASK                0x1UL                         /**< Bit mask for RMU_RCCLR */
+#define _RMU_CMD_RCCLR_DEFAULT             0x00000000UL                  /**< Mode DEFAULT for RMU_CMD */
+#define RMU_CMD_RCCLR_DEFAULT              (_RMU_CMD_RCCLR_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_CMD */
+
+/* Bit fields for RMU RST */
+#define _RMU_RST_RESETVALUE                0x00000000UL /**< Default value for RMU_RST */
+#define _RMU_RST_MASK                      0x00000000UL /**< Mask for RMU_RST */
+
+/* Bit fields for RMU LOCK */
+#define _RMU_LOCK_RESETVALUE               0x00000000UL                      /**< Default value for RMU_LOCK */
+#define _RMU_LOCK_MASK                     0x0000FFFFUL                      /**< Mask for RMU_LOCK */
+#define _RMU_LOCK_LOCKKEY_SHIFT            0                                 /**< Shift value for RMU_LOCKKEY */
+#define _RMU_LOCK_LOCKKEY_MASK             0xFFFFUL                          /**< Bit mask for RMU_LOCKKEY */
+#define _RMU_LOCK_LOCKKEY_DEFAULT          0x00000000UL                      /**< Mode DEFAULT for RMU_LOCK */
+#define _RMU_LOCK_LOCKKEY_LOCK             0x00000000UL                      /**< Mode LOCK for RMU_LOCK */
+#define _RMU_LOCK_LOCKKEY_UNLOCKED         0x00000000UL                      /**< Mode UNLOCKED for RMU_LOCK */
+#define _RMU_LOCK_LOCKKEY_LOCKED           0x00000001UL                      /**< Mode LOCKED for RMU_LOCK */
+#define _RMU_LOCK_LOCKKEY_UNLOCK           0x0000E084UL                      /**< Mode UNLOCK for RMU_LOCK */
+#define RMU_LOCK_LOCKKEY_DEFAULT           (_RMU_LOCK_LOCKKEY_DEFAULT << 0)  /**< Shifted mode DEFAULT for RMU_LOCK */
+#define RMU_LOCK_LOCKKEY_LOCK              (_RMU_LOCK_LOCKKEY_LOCK << 0)     /**< Shifted mode LOCK for RMU_LOCK */
+#define RMU_LOCK_LOCKKEY_UNLOCKED          (_RMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for RMU_LOCK */
+#define RMU_LOCK_LOCKKEY_LOCKED            (_RMU_LOCK_LOCKKEY_LOCKED << 0)   /**< Shifted mode LOCKED for RMU_LOCK */
+#define RMU_LOCK_LOCKKEY_UNLOCK            (_RMU_LOCK_LOCKKEY_UNLOCK << 0)   /**< Shifted mode UNLOCK for RMU_LOCK */
+
+/** @} End of group EFM32PG1B_RMU */
+/** @} End of group Parts */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG_STK3401/efm32pg1b_romtable.h	Fri Jan 15 07:45:16 2016 +0000
@@ -0,0 +1,72 @@
+/**************************************************************************//**
+ * @file efm32pg1b_romtable.h
+ * @brief EFM32PG1B_ROMTABLE register and bit field definitions
+ * @version 4.2.0
+ ******************************************************************************
+ * @section License
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ ******************************************************************************
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software.@n
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.@n
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is
+ * providing the Software "AS IS", with no express or implied warranties of any
+ * kind, including, but not limited to, any implied warranties of
+ * merchantability or fitness for any particular purpose or warranties against
+ * infringement of any proprietary rights of a third party.
+ *
+ * Silicon Laboratories, Inc. will not be liable for any consequential,
+ * incidental, or special damages, or any other relief, or for any claim by
+ * any third party, arising from your use of this Software.
+ *
+ *****************************************************************************/
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFM32PG1B_ROMTABLE
+ * @{
+ * @brief Chip Information, Revision numbers
+ *****************************************************************************/
+typedef struct
+{
+  __I uint32_t PID4; /**< JEP_106_BANK */
+  __I uint32_t PID5; /**< Unused */
+  __I uint32_t PID6; /**< Unused */
+  __I uint32_t PID7; /**< Unused */
+  __I uint32_t PID0; /**< Chip family LSB, chip major revision */
+  __I uint32_t PID1; /**< JEP_106_NO, Chip family MSB */
+  __I uint32_t PID2; /**< Chip minor rev MSB, JEP_106_PRESENT, JEP_106_NO */
+  __I uint32_t PID3; /**< Chip minor rev LSB */
+  __I uint32_t CID0; /**< Unused */
+} ROMTABLE_TypeDef;  /** @} */
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B_ROMTABLE_BitFields
+ * @{
+ *****************************************************************************/
+/* Bit fields for EFM32PG1B_ROMTABLE */
+#define _ROMTABLE_PID0_FAMILYLSB_MASK       0x000000C0UL /**< Least Significant Bits [1:0] of CHIP FAMILY, mask */
+#define _ROMTABLE_PID0_FAMILYLSB_SHIFT      6            /**< Least Significant Bits [1:0] of CHIP FAMILY, shift */
+#define _ROMTABLE_PID0_REVMAJOR_MASK        0x0000003FUL /**< CHIP MAJOR Revison, mask */
+#define _ROMTABLE_PID0_REVMAJOR_SHIFT       0            /**< CHIP MAJOR Revison, shift */
+#define _ROMTABLE_PID1_FAMILYMSB_MASK       0x0000000FUL /**< Most Significant Bits [5:2] of CHIP FAMILY, mask */
+#define _ROMTABLE_PID1_FAMILYMSB_SHIFT      0            /**< Most Significant Bits [5:2] of CHIP FAMILY, shift */
+#define _ROMTABLE_PID2_REVMINORMSB_MASK     0x000000F0UL /**< Most Significant Bits [7:4] of CHIP MINOR revision, mask */
+#define _ROMTABLE_PID2_REVMINORMSB_SHIFT    4            /**< Most Significant Bits [7:4] of CHIP MINOR revision, mask */
+#define _ROMTABLE_PID3_REVMINORLSB_MASK     0x000000F0UL /**< Least Significant Bits [3:0] of CHIP MINOR revision, mask */
+#define _ROMTABLE_PID3_REVMINORLSB_SHIFT    4            /**< Least Significant Bits [3:0] of CHIP MINOR revision, shift */
+
+/** @} End of group EFM32PG1B_ROMTABLE */
+/** @} End of group Parts */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG_STK3401/efm32pg1b_rtcc.h	Fri Jan 15 07:45:16 2016 +0000
@@ -0,0 +1,695 @@
+/**************************************************************************//**
+ * @file efm32pg1b_rtcc.h
+ * @brief EFM32PG1B_RTCC register and bit field definitions
+ * @version 4.2.0
+ ******************************************************************************
+ * @section License
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ ******************************************************************************
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software.@n
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.@n
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is
+ * providing the Software "AS IS", with no express or implied warranties of any
+ * kind, including, but not limited to, any implied warranties of
+ * merchantability or fitness for any particular purpose or warranties against
+ * infringement of any proprietary rights of a third party.
+ *
+ * Silicon Laboratories, Inc. will not be liable for any consequential,
+ * incidental, or special damages, or any other relief, or for any claim by
+ * any third party, arising from your use of this Software.
+ *
+ *****************************************************************************/
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFM32PG1B_RTCC
+ * @{
+ * @brief EFM32PG1B_RTCC Register Declaration
+ *****************************************************************************/
+typedef struct
+{
+  __IO uint32_t    CTRL;          /**< Control Register  */
+  __IO uint32_t    PRECNT;        /**< Pre-Counter Value Register  */
+  __IO uint32_t    CNT;           /**< Counter Value Register  */
+  __I uint32_t     COMBCNT;       /**< Combined Pre-Counter and Counter Value Register  */
+  __IO uint32_t    TIME;          /**< Time of day register  */
+  __IO uint32_t    DATE;          /**< Date register  */
+  __I uint32_t     IF;            /**< RTCC Interrupt Flags  */
+  __IO uint32_t    IFS;           /**< Interrupt Flag Set Register  */
+  __IO uint32_t    IFC;           /**< Interrupt Flag Clear Register  */
+  __IO uint32_t    IEN;           /**< Interrupt Enable Register  */
+  __I uint32_t     STATUS;        /**< Status register  */
+  __IO uint32_t    CMD;           /**< Command Register  */
+  __I uint32_t     SYNCBUSY;      /**< Synchronization Busy Register  */
+  __IO uint32_t    POWERDOWN;     /**< Retention RAM power-down register  */
+  __IO uint32_t    LOCK;          /**< Configuration Lock Register  */
+  __IO uint32_t    EM4WUEN;       /**< Wake Up Enable  */
+
+  RTCC_CC_TypeDef  CC[3];         /**< Capture/Compare Channel */
+
+  uint32_t         RESERVED0[37]; /**< Reserved registers */
+  RTCC_RET_TypeDef RET[32];       /**< RetentionReg */
+} RTCC_TypeDef;                   /** @} */
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B_RTCC_BitFields
+ * @{
+ *****************************************************************************/
+
+/* Bit fields for RTCC CTRL */
+#define _RTCC_CTRL_RESETVALUE               0x00000000UL                            /**< Default value for RTCC_CTRL */
+#define _RTCC_CTRL_MASK                     0x00039F35UL                            /**< Mask for RTCC_CTRL */
+#define RTCC_CTRL_ENABLE                    (0x1UL << 0)                            /**< RTCC Enable */
+#define _RTCC_CTRL_ENABLE_SHIFT             0                                       /**< Shift value for RTCC_ENABLE */
+#define _RTCC_CTRL_ENABLE_MASK              0x1UL                                   /**< Bit mask for RTCC_ENABLE */
+#define _RTCC_CTRL_ENABLE_DEFAULT           0x00000000UL                            /**< Mode DEFAULT for RTCC_CTRL */
+#define RTCC_CTRL_ENABLE_DEFAULT            (_RTCC_CTRL_ENABLE_DEFAULT << 0)        /**< Shifted mode DEFAULT for RTCC_CTRL */
+#define RTCC_CTRL_DEBUGRUN                  (0x1UL << 2)                            /**< Debug Mode Run Enable */
+#define _RTCC_CTRL_DEBUGRUN_SHIFT           2                                       /**< Shift value for RTCC_DEBUGRUN */
+#define _RTCC_CTRL_DEBUGRUN_MASK            0x4UL                                   /**< Bit mask for RTCC_DEBUGRUN */
+#define _RTCC_CTRL_DEBUGRUN_DEFAULT         0x00000000UL                            /**< Mode DEFAULT for RTCC_CTRL */
+#define RTCC_CTRL_DEBUGRUN_DEFAULT          (_RTCC_CTRL_DEBUGRUN_DEFAULT << 2)      /**< Shifted mode DEFAULT for RTCC_CTRL */
+#define RTCC_CTRL_PRECCV0TOP                (0x1UL << 4)                            /**< Pre-counter CCV0 top value enable. */
+#define _RTCC_CTRL_PRECCV0TOP_SHIFT         4                                       /**< Shift value for RTCC_PRECCV0TOP */
+#define _RTCC_CTRL_PRECCV0TOP_MASK          0x10UL                                  /**< Bit mask for RTCC_PRECCV0TOP */
+#define _RTCC_CTRL_PRECCV0TOP_DEFAULT       0x00000000UL                            /**< Mode DEFAULT for RTCC_CTRL */
+#define RTCC_CTRL_PRECCV0TOP_DEFAULT        (_RTCC_CTRL_PRECCV0TOP_DEFAULT << 4)    /**< Shifted mode DEFAULT for RTCC_CTRL */
+#define RTCC_CTRL_CCV1TOP                   (0x1UL << 5)                            /**< CCV1 top value enable */
+#define _RTCC_CTRL_CCV1TOP_SHIFT            5                                       /**< Shift value for RTCC_CCV1TOP */
+#define _RTCC_CTRL_CCV1TOP_MASK             0x20UL                                  /**< Bit mask for RTCC_CCV1TOP */
+#define _RTCC_CTRL_CCV1TOP_DEFAULT          0x00000000UL                            /**< Mode DEFAULT for RTCC_CTRL */
+#define RTCC_CTRL_CCV1TOP_DEFAULT           (_RTCC_CTRL_CCV1TOP_DEFAULT << 5)       /**< Shifted mode DEFAULT for RTCC_CTRL */
+#define _RTCC_CTRL_CNTPRESC_SHIFT           8                                       /**< Shift value for RTCC_CNTPRESC */
+#define _RTCC_CTRL_CNTPRESC_MASK            0xF00UL                                 /**< Bit mask for RTCC_CNTPRESC */
+#define _RTCC_CTRL_CNTPRESC_DEFAULT         0x00000000UL                            /**< Mode DEFAULT for RTCC_CTRL */
+#define _RTCC_CTRL_CNTPRESC_DIV1            0x00000000UL                            /**< Mode DIV1 for RTCC_CTRL */
+#define _RTCC_CTRL_CNTPRESC_DIV2            0x00000001UL                            /**< Mode DIV2 for RTCC_CTRL */
+#define _RTCC_CTRL_CNTPRESC_DIV4            0x00000002UL                            /**< Mode DIV4 for RTCC_CTRL */
+#define _RTCC_CTRL_CNTPRESC_DIV8            0x00000003UL                            /**< Mode DIV8 for RTCC_CTRL */
+#define _RTCC_CTRL_CNTPRESC_DIV16           0x00000004UL                            /**< Mode DIV16 for RTCC_CTRL */
+#define _RTCC_CTRL_CNTPRESC_DIV32           0x00000005UL                            /**< Mode DIV32 for RTCC_CTRL */
+#define _RTCC_CTRL_CNTPRESC_DIV64           0x00000006UL                            /**< Mode DIV64 for RTCC_CTRL */
+#define _RTCC_CTRL_CNTPRESC_DIV128          0x00000007UL                            /**< Mode DIV128 for RTCC_CTRL */
+#define _RTCC_CTRL_CNTPRESC_DIV256          0x00000008UL                            /**< Mode DIV256 for RTCC_CTRL */
+#define _RTCC_CTRL_CNTPRESC_DIV512          0x00000009UL                            /**< Mode DIV512 for RTCC_CTRL */
+#define _RTCC_CTRL_CNTPRESC_DIV1024         0x0000000AUL                            /**< Mode DIV1024 for RTCC_CTRL */
+#define _RTCC_CTRL_CNTPRESC_DIV2048         0x0000000BUL                            /**< Mode DIV2048 for RTCC_CTRL */
+#define _RTCC_CTRL_CNTPRESC_DIV4096         0x0000000CUL                            /**< Mode DIV4096 for RTCC_CTRL */
+#define _RTCC_CTRL_CNTPRESC_DIV8192         0x0000000DUL                            /**< Mode DIV8192 for RTCC_CTRL */
+#define _RTCC_CTRL_CNTPRESC_DIV16384        0x0000000EUL                            /**< Mode DIV16384 for RTCC_CTRL */
+#define _RTCC_CTRL_CNTPRESC_DIV32768        0x0000000FUL                            /**< Mode DIV32768 for RTCC_CTRL */
+#define RTCC_CTRL_CNTPRESC_DEFAULT          (_RTCC_CTRL_CNTPRESC_DEFAULT << 8)      /**< Shifted mode DEFAULT for RTCC_CTRL */
+#define RTCC_CTRL_CNTPRESC_DIV1             (_RTCC_CTRL_CNTPRESC_DIV1 << 8)         /**< Shifted mode DIV1 for RTCC_CTRL */
+#define RTCC_CTRL_CNTPRESC_DIV2             (_RTCC_CTRL_CNTPRESC_DIV2 << 8)         /**< Shifted mode DIV2 for RTCC_CTRL */
+#define RTCC_CTRL_CNTPRESC_DIV4             (_RTCC_CTRL_CNTPRESC_DIV4 << 8)         /**< Shifted mode DIV4 for RTCC_CTRL */
+#define RTCC_CTRL_CNTPRESC_DIV8             (_RTCC_CTRL_CNTPRESC_DIV8 << 8)         /**< Shifted mode DIV8 for RTCC_CTRL */
+#define RTCC_CTRL_CNTPRESC_DIV16            (_RTCC_CTRL_CNTPRESC_DIV16 << 8)        /**< Shifted mode DIV16 for RTCC_CTRL */
+#define RTCC_CTRL_CNTPRESC_DIV32            (_RTCC_CTRL_CNTPRESC_DIV32 << 8)        /**< Shifted mode DIV32 for RTCC_CTRL */
+#define RTCC_CTRL_CNTPRESC_DIV64            (_RTCC_CTRL_CNTPRESC_DIV64 << 8)        /**< Shifted mode DIV64 for RTCC_CTRL */
+#define RTCC_CTRL_CNTPRESC_DIV128           (_RTCC_CTRL_CNTPRESC_DIV128 << 8)       /**< Shifted mode DIV128 for RTCC_CTRL */
+#define RTCC_CTRL_CNTPRESC_DIV256           (_RTCC_CTRL_CNTPRESC_DIV256 << 8)       /**< Shifted mode DIV256 for RTCC_CTRL */
+#define RTCC_CTRL_CNTPRESC_DIV512           (_RTCC_CTRL_CNTPRESC_DIV512 << 8)       /**< Shifted mode DIV512 for RTCC_CTRL */
+#define RTCC_CTRL_CNTPRESC_DIV1024          (_RTCC_CTRL_CNTPRESC_DIV1024 << 8)      /**< Shifted mode DIV1024 for RTCC_CTRL */
+#define RTCC_CTRL_CNTPRESC_DIV2048          (_RTCC_CTRL_CNTPRESC_DIV2048 << 8)      /**< Shifted mode DIV2048 for RTCC_CTRL */
+#define RTCC_CTRL_CNTPRESC_DIV4096          (_RTCC_CTRL_CNTPRESC_DIV4096 << 8)      /**< Shifted mode DIV4096 for RTCC_CTRL */
+#define RTCC_CTRL_CNTPRESC_DIV8192          (_RTCC_CTRL_CNTPRESC_DIV8192 << 8)      /**< Shifted mode DIV8192 for RTCC_CTRL */
+#define RTCC_CTRL_CNTPRESC_DIV16384         (_RTCC_CTRL_CNTPRESC_DIV16384 << 8)     /**< Shifted mode DIV16384 for RTCC_CTRL */
+#define RTCC_CTRL_CNTPRESC_DIV32768         (_RTCC_CTRL_CNTPRESC_DIV32768 << 8)     /**< Shifted mode DIV32768 for RTCC_CTRL */
+#define RTCC_CTRL_CNTTICK                   (0x1UL << 12)                           /**< Counter prescaler mode. */
+#define _RTCC_CTRL_CNTTICK_SHIFT            12                                      /**< Shift value for RTCC_CNTTICK */
+#define _RTCC_CTRL_CNTTICK_MASK             0x1000UL                                /**< Bit mask for RTCC_CNTTICK */
+#define _RTCC_CTRL_CNTTICK_DEFAULT          0x00000000UL                            /**< Mode DEFAULT for RTCC_CTRL */
+#define _RTCC_CTRL_CNTTICK_PRESC            0x00000000UL                            /**< Mode PRESC for RTCC_CTRL */
+#define _RTCC_CTRL_CNTTICK_CCV0MATCH        0x00000001UL                            /**< Mode CCV0MATCH for RTCC_CTRL */
+#define RTCC_CTRL_CNTTICK_DEFAULT           (_RTCC_CTRL_CNTTICK_DEFAULT << 12)      /**< Shifted mode DEFAULT for RTCC_CTRL */
+#define RTCC_CTRL_CNTTICK_PRESC             (_RTCC_CTRL_CNTTICK_PRESC << 12)        /**< Shifted mode PRESC for RTCC_CTRL */
+#define RTCC_CTRL_CNTTICK_CCV0MATCH         (_RTCC_CTRL_CNTTICK_CCV0MATCH << 12)    /**< Shifted mode CCV0MATCH for RTCC_CTRL */
+#define RTCC_CTRL_OSCFDETEN                 (0x1UL << 15)                           /**< Oscillator failure detection enable */
+#define _RTCC_CTRL_OSCFDETEN_SHIFT          15                                      /**< Shift value for RTCC_OSCFDETEN */
+#define _RTCC_CTRL_OSCFDETEN_MASK           0x8000UL                                /**< Bit mask for RTCC_OSCFDETEN */
+#define _RTCC_CTRL_OSCFDETEN_DEFAULT        0x00000000UL                            /**< Mode DEFAULT for RTCC_CTRL */
+#define RTCC_CTRL_OSCFDETEN_DEFAULT         (_RTCC_CTRL_OSCFDETEN_DEFAULT << 15)    /**< Shifted mode DEFAULT for RTCC_CTRL */
+#define RTCC_CTRL_CNTMODE                   (0x1UL << 16)                           /**< Main counter mode */
+#define _RTCC_CTRL_CNTMODE_SHIFT            16                                      /**< Shift value for RTCC_CNTMODE */
+#define _RTCC_CTRL_CNTMODE_MASK             0x10000UL                               /**< Bit mask for RTCC_CNTMODE */
+#define _RTCC_CTRL_CNTMODE_DEFAULT          0x00000000UL                            /**< Mode DEFAULT for RTCC_CTRL */
+#define _RTCC_CTRL_CNTMODE_NORMAL           0x00000000UL                            /**< Mode NORMAL for RTCC_CTRL */
+#define _RTCC_CTRL_CNTMODE_CALENDAR         0x00000001UL                            /**< Mode CALENDAR for RTCC_CTRL */
+#define RTCC_CTRL_CNTMODE_DEFAULT           (_RTCC_CTRL_CNTMODE_DEFAULT << 16)      /**< Shifted mode DEFAULT for RTCC_CTRL */
+#define RTCC_CTRL_CNTMODE_NORMAL            (_RTCC_CTRL_CNTMODE_NORMAL << 16)       /**< Shifted mode NORMAL for RTCC_CTRL */
+#define RTCC_CTRL_CNTMODE_CALENDAR          (_RTCC_CTRL_CNTMODE_CALENDAR << 16)     /**< Shifted mode CALENDAR for RTCC_CTRL */
+#define RTCC_CTRL_LYEARCORRDIS              (0x1UL << 17)                           /**< Leap year correction disabled. */
+#define _RTCC_CTRL_LYEARCORRDIS_SHIFT       17                                      /**< Shift value for RTCC_LYEARCORRDIS */
+#define _RTCC_CTRL_LYEARCORRDIS_MASK        0x20000UL                               /**< Bit mask for RTCC_LYEARCORRDIS */
+#define _RTCC_CTRL_LYEARCORRDIS_DEFAULT     0x00000000UL                            /**< Mode DEFAULT for RTCC_CTRL */
+#define RTCC_CTRL_LYEARCORRDIS_DEFAULT      (_RTCC_CTRL_LYEARCORRDIS_DEFAULT << 17) /**< Shifted mode DEFAULT for RTCC_CTRL */
+
+/* Bit fields for RTCC PRECNT */
+#define _RTCC_PRECNT_RESETVALUE             0x00000000UL                       /**< Default value for RTCC_PRECNT */
+#define _RTCC_PRECNT_MASK                   0x00007FFFUL                       /**< Mask for RTCC_PRECNT */
+#define _RTCC_PRECNT_PRECNT_SHIFT           0                                  /**< Shift value for RTCC_PRECNT */
+#define _RTCC_PRECNT_PRECNT_MASK            0x7FFFUL                           /**< Bit mask for RTCC_PRECNT */
+#define _RTCC_PRECNT_PRECNT_DEFAULT         0x00000000UL                       /**< Mode DEFAULT for RTCC_PRECNT */
+#define RTCC_PRECNT_PRECNT_DEFAULT          (_RTCC_PRECNT_PRECNT_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_PRECNT */
+
+/* Bit fields for RTCC CNT */
+#define _RTCC_CNT_RESETVALUE                0x00000000UL                 /**< Default value for RTCC_CNT */
+#define _RTCC_CNT_MASK                      0xFFFFFFFFUL                 /**< Mask for RTCC_CNT */
+#define _RTCC_CNT_CNT_SHIFT                 0                            /**< Shift value for RTCC_CNT */
+#define _RTCC_CNT_CNT_MASK                  0xFFFFFFFFUL                 /**< Bit mask for RTCC_CNT */
+#define _RTCC_CNT_CNT_DEFAULT               0x00000000UL                 /**< Mode DEFAULT for RTCC_CNT */
+#define RTCC_CNT_CNT_DEFAULT                (_RTCC_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CNT */
+
+/* Bit fields for RTCC COMBCNT */
+#define _RTCC_COMBCNT_RESETVALUE            0x00000000UL                         /**< Default value for RTCC_COMBCNT */
+#define _RTCC_COMBCNT_MASK                  0xFFFFFFFFUL                         /**< Mask for RTCC_COMBCNT */
+#define _RTCC_COMBCNT_PRECNT_SHIFT          0                                    /**< Shift value for RTCC_PRECNT */
+#define _RTCC_COMBCNT_PRECNT_MASK           0x7FFFUL                             /**< Bit mask for RTCC_PRECNT */
+#define _RTCC_COMBCNT_PRECNT_DEFAULT        0x00000000UL                         /**< Mode DEFAULT for RTCC_COMBCNT */
+#define RTCC_COMBCNT_PRECNT_DEFAULT         (_RTCC_COMBCNT_PRECNT_DEFAULT << 0)  /**< Shifted mode DEFAULT for RTCC_COMBCNT */
+#define _RTCC_COMBCNT_CNTLSB_SHIFT          15                                   /**< Shift value for RTCC_CNTLSB */
+#define _RTCC_COMBCNT_CNTLSB_MASK           0xFFFF8000UL                         /**< Bit mask for RTCC_CNTLSB */
+#define _RTCC_COMBCNT_CNTLSB_DEFAULT        0x00000000UL                         /**< Mode DEFAULT for RTCC_COMBCNT */
+#define RTCC_COMBCNT_CNTLSB_DEFAULT         (_RTCC_COMBCNT_CNTLSB_DEFAULT << 15) /**< Shifted mode DEFAULT for RTCC_COMBCNT */
+
+/* Bit fields for RTCC TIME */
+#define _RTCC_TIME_RESETVALUE               0x00000000UL                     /**< Default value for RTCC_TIME */
+#define _RTCC_TIME_MASK                     0x003F7F7FUL                     /**< Mask for RTCC_TIME */
+#define _RTCC_TIME_SECU_SHIFT               0                                /**< Shift value for RTCC_SECU */
+#define _RTCC_TIME_SECU_MASK                0xFUL                            /**< Bit mask for RTCC_SECU */
+#define _RTCC_TIME_SECU_DEFAULT             0x00000000UL                     /**< Mode DEFAULT for RTCC_TIME */
+#define RTCC_TIME_SECU_DEFAULT              (_RTCC_TIME_SECU_DEFAULT << 0)   /**< Shifted mode DEFAULT for RTCC_TIME */
+#define _RTCC_TIME_SECT_SHIFT               4                                /**< Shift value for RTCC_SECT */
+#define _RTCC_TIME_SECT_MASK                0x70UL                           /**< Bit mask for RTCC_SECT */
+#define _RTCC_TIME_SECT_DEFAULT             0x00000000UL                     /**< Mode DEFAULT for RTCC_TIME */
+#define RTCC_TIME_SECT_DEFAULT              (_RTCC_TIME_SECT_DEFAULT << 4)   /**< Shifted mode DEFAULT for RTCC_TIME */
+#define _RTCC_TIME_MINU_SHIFT               8                                /**< Shift value for RTCC_MINU */
+#define _RTCC_TIME_MINU_MASK                0xF00UL                          /**< Bit mask for RTCC_MINU */
+#define _RTCC_TIME_MINU_DEFAULT             0x00000000UL                     /**< Mode DEFAULT for RTCC_TIME */
+#define RTCC_TIME_MINU_DEFAULT              (_RTCC_TIME_MINU_DEFAULT << 8)   /**< Shifted mode DEFAULT for RTCC_TIME */
+#define _RTCC_TIME_MINT_SHIFT               12                               /**< Shift value for RTCC_MINT */
+#define _RTCC_TIME_MINT_MASK                0x7000UL                         /**< Bit mask for RTCC_MINT */
+#define _RTCC_TIME_MINT_DEFAULT             0x00000000UL                     /**< Mode DEFAULT for RTCC_TIME */
+#define RTCC_TIME_MINT_DEFAULT              (_RTCC_TIME_MINT_DEFAULT << 12)  /**< Shifted mode DEFAULT for RTCC_TIME */
+#define _RTCC_TIME_HOURU_SHIFT              16                               /**< Shift value for RTCC_HOURU */
+#define _RTCC_TIME_HOURU_MASK               0xF0000UL                        /**< Bit mask for RTCC_HOURU */
+#define _RTCC_TIME_HOURU_DEFAULT            0x00000000UL                     /**< Mode DEFAULT for RTCC_TIME */
+#define RTCC_TIME_HOURU_DEFAULT             (_RTCC_TIME_HOURU_DEFAULT << 16) /**< Shifted mode DEFAULT for RTCC_TIME */
+#define _RTCC_TIME_HOURT_SHIFT              20                               /**< Shift value for RTCC_HOURT */
+#define _RTCC_TIME_HOURT_MASK               0x300000UL                       /**< Bit mask for RTCC_HOURT */
+#define _RTCC_TIME_HOURT_DEFAULT            0x00000000UL                     /**< Mode DEFAULT for RTCC_TIME */
+#define RTCC_TIME_HOURT_DEFAULT             (_RTCC_TIME_HOURT_DEFAULT << 20) /**< Shifted mode DEFAULT for RTCC_TIME */
+
+/* Bit fields for RTCC DATE */
+#define _RTCC_DATE_RESETVALUE               0x00000000UL                      /**< Default value for RTCC_DATE */
+#define _RTCC_DATE_MASK                     0x07FF1F3FUL                      /**< Mask for RTCC_DATE */
+#define _RTCC_DATE_DAYOMU_SHIFT             0                                 /**< Shift value for RTCC_DAYOMU */
+#define _RTCC_DATE_DAYOMU_MASK              0xFUL                             /**< Bit mask for RTCC_DAYOMU */
+#define _RTCC_DATE_DAYOMU_DEFAULT           0x00000000UL                      /**< Mode DEFAULT for RTCC_DATE */
+#define RTCC_DATE_DAYOMU_DEFAULT            (_RTCC_DATE_DAYOMU_DEFAULT << 0)  /**< Shifted mode DEFAULT for RTCC_DATE */
+#define _RTCC_DATE_DAYOMT_SHIFT             4                                 /**< Shift value for RTCC_DAYOMT */
+#define _RTCC_DATE_DAYOMT_MASK              0x30UL                            /**< Bit mask for RTCC_DAYOMT */
+#define _RTCC_DATE_DAYOMT_DEFAULT           0x00000000UL                      /**< Mode DEFAULT for RTCC_DATE */
+#define RTCC_DATE_DAYOMT_DEFAULT            (_RTCC_DATE_DAYOMT_DEFAULT << 4)  /**< Shifted mode DEFAULT for RTCC_DATE */
+#define _RTCC_DATE_MONTHU_SHIFT             8                                 /**< Shift value for RTCC_MONTHU */
+#define _RTCC_DATE_MONTHU_MASK              0xF00UL                           /**< Bit mask for RTCC_MONTHU */
+#define _RTCC_DATE_MONTHU_DEFAULT           0x00000000UL                      /**< Mode DEFAULT for RTCC_DATE */
+#define RTCC_DATE_MONTHU_DEFAULT            (_RTCC_DATE_MONTHU_DEFAULT << 8)  /**< Shifted mode DEFAULT for RTCC_DATE */
+#define RTCC_DATE_MONTHT                    (0x1UL << 12)                     /**< Month, tens. */
+#define _RTCC_DATE_MONTHT_SHIFT             12                                /**< Shift value for RTCC_MONTHT */
+#define _RTCC_DATE_MONTHT_MASK              0x1000UL                          /**< Bit mask for RTCC_MONTHT */
+#define _RTCC_DATE_MONTHT_DEFAULT           0x00000000UL                      /**< Mode DEFAULT for RTCC_DATE */
+#define RTCC_DATE_MONTHT_DEFAULT            (_RTCC_DATE_MONTHT_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_DATE */
+#define _RTCC_DATE_YEARU_SHIFT              16                                /**< Shift value for RTCC_YEARU */
+#define _RTCC_DATE_YEARU_MASK               0xF0000UL                         /**< Bit mask for RTCC_YEARU */
+#define _RTCC_DATE_YEARU_DEFAULT            0x00000000UL                      /**< Mode DEFAULT for RTCC_DATE */
+#define RTCC_DATE_YEARU_DEFAULT             (_RTCC_DATE_YEARU_DEFAULT << 16)  /**< Shifted mode DEFAULT for RTCC_DATE */
+#define _RTCC_DATE_YEART_SHIFT              20                                /**< Shift value for RTCC_YEART */
+#define _RTCC_DATE_YEART_MASK               0xF00000UL                        /**< Bit mask for RTCC_YEART */
+#define _RTCC_DATE_YEART_DEFAULT            0x00000000UL                      /**< Mode DEFAULT for RTCC_DATE */
+#define RTCC_DATE_YEART_DEFAULT             (_RTCC_DATE_YEART_DEFAULT << 20)  /**< Shifted mode DEFAULT for RTCC_DATE */
+#define _RTCC_DATE_DAYOW_SHIFT              24                                /**< Shift value for RTCC_DAYOW */
+#define _RTCC_DATE_DAYOW_MASK               0x7000000UL                       /**< Bit mask for RTCC_DAYOW */
+#define _RTCC_DATE_DAYOW_DEFAULT            0x00000000UL                      /**< Mode DEFAULT for RTCC_DATE */
+#define RTCC_DATE_DAYOW_DEFAULT             (_RTCC_DATE_DAYOW_DEFAULT << 24)  /**< Shifted mode DEFAULT for RTCC_DATE */
+
+/* Bit fields for RTCC IF */
+#define _RTCC_IF_RESETVALUE                 0x00000000UL                       /**< Default value for RTCC_IF */
+#define _RTCC_IF_MASK                       0x000007FFUL                       /**< Mask for RTCC_IF */
+#define RTCC_IF_OF                          (0x1UL << 0)                       /**< Overflow Interrupt Flag */
+#define _RTCC_IF_OF_SHIFT                   0                                  /**< Shift value for RTCC_OF */
+#define _RTCC_IF_OF_MASK                    0x1UL                              /**< Bit mask for RTCC_OF */
+#define _RTCC_IF_OF_DEFAULT                 0x00000000UL                       /**< Mode DEFAULT for RTCC_IF */
+#define RTCC_IF_OF_DEFAULT                  (_RTCC_IF_OF_DEFAULT << 0)         /**< Shifted mode DEFAULT for RTCC_IF */
+#define RTCC_IF_CC0                         (0x1UL << 1)                       /**< Channel 0 Interrupt Flag */
+#define _RTCC_IF_CC0_SHIFT                  1                                  /**< Shift value for RTCC_CC0 */
+#define _RTCC_IF_CC0_MASK                   0x2UL                              /**< Bit mask for RTCC_CC0 */
+#define _RTCC_IF_CC0_DEFAULT                0x00000000UL                       /**< Mode DEFAULT for RTCC_IF */
+#define RTCC_IF_CC0_DEFAULT                 (_RTCC_IF_CC0_DEFAULT << 1)        /**< Shifted mode DEFAULT for RTCC_IF */
+#define RTCC_IF_CC1                         (0x1UL << 2)                       /**< Channel 1 Interrupt Flag */
+#define _RTCC_IF_CC1_SHIFT                  2                                  /**< Shift value for RTCC_CC1 */
+#define _RTCC_IF_CC1_MASK                   0x4UL                              /**< Bit mask for RTCC_CC1 */
+#define _RTCC_IF_CC1_DEFAULT                0x00000000UL                       /**< Mode DEFAULT for RTCC_IF */
+#define RTCC_IF_CC1_DEFAULT                 (_RTCC_IF_CC1_DEFAULT << 2)        /**< Shifted mode DEFAULT for RTCC_IF */
+#define RTCC_IF_CC2                         (0x1UL << 3)                       /**< Channel 2 Interrupt Flag */
+#define _RTCC_IF_CC2_SHIFT                  3                                  /**< Shift value for RTCC_CC2 */
+#define _RTCC_IF_CC2_MASK                   0x8UL                              /**< Bit mask for RTCC_CC2 */
+#define _RTCC_IF_CC2_DEFAULT                0x00000000UL                       /**< Mode DEFAULT for RTCC_IF */
+#define RTCC_IF_CC2_DEFAULT                 (_RTCC_IF_CC2_DEFAULT << 3)        /**< Shifted mode DEFAULT for RTCC_IF */
+#define RTCC_IF_OSCFAIL                     (0x1UL << 4)                       /**< Oscillator failure Interrupt Flag */
+#define _RTCC_IF_OSCFAIL_SHIFT              4                                  /**< Shift value for RTCC_OSCFAIL */
+#define _RTCC_IF_OSCFAIL_MASK               0x10UL                             /**< Bit mask for RTCC_OSCFAIL */
+#define _RTCC_IF_OSCFAIL_DEFAULT            0x00000000UL                       /**< Mode DEFAULT for RTCC_IF */
+#define RTCC_IF_OSCFAIL_DEFAULT             (_RTCC_IF_OSCFAIL_DEFAULT << 4)    /**< Shifted mode DEFAULT for RTCC_IF */
+#define RTCC_IF_CNTTICK                     (0x1UL << 5)                       /**< Main counter tick */
+#define _RTCC_IF_CNTTICK_SHIFT              5                                  /**< Shift value for RTCC_CNTTICK */
+#define _RTCC_IF_CNTTICK_MASK               0x20UL                             /**< Bit mask for RTCC_CNTTICK */
+#define _RTCC_IF_CNTTICK_DEFAULT            0x00000000UL                       /**< Mode DEFAULT for RTCC_IF */
+#define RTCC_IF_CNTTICK_DEFAULT             (_RTCC_IF_CNTTICK_DEFAULT << 5)    /**< Shifted mode DEFAULT for RTCC_IF */
+#define RTCC_IF_MINTICK                     (0x1UL << 6)                       /**< Minute tick */
+#define _RTCC_IF_MINTICK_SHIFT              6                                  /**< Shift value for RTCC_MINTICK */
+#define _RTCC_IF_MINTICK_MASK               0x40UL                             /**< Bit mask for RTCC_MINTICK */
+#define _RTCC_IF_MINTICK_DEFAULT            0x00000000UL                       /**< Mode DEFAULT for RTCC_IF */
+#define RTCC_IF_MINTICK_DEFAULT             (_RTCC_IF_MINTICK_DEFAULT << 6)    /**< Shifted mode DEFAULT for RTCC_IF */
+#define RTCC_IF_HOURTICK                    (0x1UL << 7)                       /**< Hour tick */
+#define _RTCC_IF_HOURTICK_SHIFT             7                                  /**< Shift value for RTCC_HOURTICK */
+#define _RTCC_IF_HOURTICK_MASK              0x80UL                             /**< Bit mask for RTCC_HOURTICK */
+#define _RTCC_IF_HOURTICK_DEFAULT           0x00000000UL                       /**< Mode DEFAULT for RTCC_IF */
+#define RTCC_IF_HOURTICK_DEFAULT            (_RTCC_IF_HOURTICK_DEFAULT << 7)   /**< Shifted mode DEFAULT for RTCC_IF */
+#define RTCC_IF_DAYTICK                     (0x1UL << 8)                       /**< Day tick */
+#define _RTCC_IF_DAYTICK_SHIFT              8                                  /**< Shift value for RTCC_DAYTICK */
+#define _RTCC_IF_DAYTICK_MASK               0x100UL                            /**< Bit mask for RTCC_DAYTICK */
+#define _RTCC_IF_DAYTICK_DEFAULT            0x00000000UL                       /**< Mode DEFAULT for RTCC_IF */
+#define RTCC_IF_DAYTICK_DEFAULT             (_RTCC_IF_DAYTICK_DEFAULT << 8)    /**< Shifted mode DEFAULT for RTCC_IF */
+#define RTCC_IF_DAYOWOF                     (0x1UL << 9)                       /**< Day of week overflow */
+#define _RTCC_IF_DAYOWOF_SHIFT              9                                  /**< Shift value for RTCC_DAYOWOF */
+#define _RTCC_IF_DAYOWOF_MASK               0x200UL                            /**< Bit mask for RTCC_DAYOWOF */
+#define _RTCC_IF_DAYOWOF_DEFAULT            0x00000000UL                       /**< Mode DEFAULT for RTCC_IF */
+#define RTCC_IF_DAYOWOF_DEFAULT             (_RTCC_IF_DAYOWOF_DEFAULT << 9)    /**< Shifted mode DEFAULT for RTCC_IF */
+#define RTCC_IF_MONTHTICK                   (0x1UL << 10)                      /**< Month tick */
+#define _RTCC_IF_MONTHTICK_SHIFT            10                                 /**< Shift value for RTCC_MONTHTICK */
+#define _RTCC_IF_MONTHTICK_MASK             0x400UL                            /**< Bit mask for RTCC_MONTHTICK */
+#define _RTCC_IF_MONTHTICK_DEFAULT          0x00000000UL                       /**< Mode DEFAULT for RTCC_IF */
+#define RTCC_IF_MONTHTICK_DEFAULT           (_RTCC_IF_MONTHTICK_DEFAULT << 10) /**< Shifted mode DEFAULT for RTCC_IF */
+
+/* Bit fields for RTCC IFS */
+#define _RTCC_IFS_RESETVALUE                0x00000000UL                        /**< Default value for RTCC_IFS */
+#define _RTCC_IFS_MASK                      0x000007FFUL                        /**< Mask for RTCC_IFS */
+#define RTCC_IFS_OF                         (0x1UL << 0)                        /**< Set OF Interrupt Flag */
+#define _RTCC_IFS_OF_SHIFT                  0                                   /**< Shift value for RTCC_OF */
+#define _RTCC_IFS_OF_MASK                   0x1UL                               /**< Bit mask for RTCC_OF */
+#define _RTCC_IFS_OF_DEFAULT                0x00000000UL                        /**< Mode DEFAULT for RTCC_IFS */
+#define RTCC_IFS_OF_DEFAULT                 (_RTCC_IFS_OF_DEFAULT << 0)         /**< Shifted mode DEFAULT for RTCC_IFS */
+#define RTCC_IFS_CC0                        (0x1UL << 1)                        /**< Set CC0 Interrupt Flag */
+#define _RTCC_IFS_CC0_SHIFT                 1                                   /**< Shift value for RTCC_CC0 */
+#define _RTCC_IFS_CC0_MASK                  0x2UL                               /**< Bit mask for RTCC_CC0 */
+#define _RTCC_IFS_CC0_DEFAULT               0x00000000UL                        /**< Mode DEFAULT for RTCC_IFS */
+#define RTCC_IFS_CC0_DEFAULT                (_RTCC_IFS_CC0_DEFAULT << 1)        /**< Shifted mode DEFAULT for RTCC_IFS */
+#define RTCC_IFS_CC1                        (0x1UL << 2)                        /**< Set CC1 Interrupt Flag */
+#define _RTCC_IFS_CC1_SHIFT                 2                                   /**< Shift value for RTCC_CC1 */
+#define _RTCC_IFS_CC1_MASK                  0x4UL                               /**< Bit mask for RTCC_CC1 */
+#define _RTCC_IFS_CC1_DEFAULT               0x00000000UL                        /**< Mode DEFAULT for RTCC_IFS */
+#define RTCC_IFS_CC1_DEFAULT                (_RTCC_IFS_CC1_DEFAULT << 2)        /**< Shifted mode DEFAULT for RTCC_IFS */
+#define RTCC_IFS_CC2                        (0x1UL << 3)                        /**< Set CC2 Interrupt Flag */
+#define _RTCC_IFS_CC2_SHIFT                 3                                   /**< Shift value for RTCC_CC2 */
+#define _RTCC_IFS_CC2_MASK                  0x8UL                               /**< Bit mask for RTCC_CC2 */
+#define _RTCC_IFS_CC2_DEFAULT               0x00000000UL                        /**< Mode DEFAULT for RTCC_IFS */
+#define RTCC_IFS_CC2_DEFAULT                (_RTCC_IFS_CC2_DEFAULT << 3)        /**< Shifted mode DEFAULT for RTCC_IFS */
+#define RTCC_IFS_OSCFAIL                    (0x1UL << 4)                        /**< Set OSCFAIL Interrupt Flag */
+#define _RTCC_IFS_OSCFAIL_SHIFT             4                                   /**< Shift value for RTCC_OSCFAIL */
+#define _RTCC_IFS_OSCFAIL_MASK              0x10UL                              /**< Bit mask for RTCC_OSCFAIL */
+#define _RTCC_IFS_OSCFAIL_DEFAULT           0x00000000UL                        /**< Mode DEFAULT for RTCC_IFS */
+#define RTCC_IFS_OSCFAIL_DEFAULT            (_RTCC_IFS_OSCFAIL_DEFAULT << 4)    /**< Shifted mode DEFAULT for RTCC_IFS */
+#define RTCC_IFS_CNTTICK                    (0x1UL << 5)                        /**< Set CNTTICK Interrupt Flag */
+#define _RTCC_IFS_CNTTICK_SHIFT             5                                   /**< Shift value for RTCC_CNTTICK */
+#define _RTCC_IFS_CNTTICK_MASK              0x20UL                              /**< Bit mask for RTCC_CNTTICK */
+#define _RTCC_IFS_CNTTICK_DEFAULT           0x00000000UL                        /**< Mode DEFAULT for RTCC_IFS */
+#define RTCC_IFS_CNTTICK_DEFAULT            (_RTCC_IFS_CNTTICK_DEFAULT << 5)    /**< Shifted mode DEFAULT for RTCC_IFS */
+#define RTCC_IFS_MINTICK                    (0x1UL << 6)                        /**< Set MINTICK Interrupt Flag */
+#define _RTCC_IFS_MINTICK_SHIFT             6                                   /**< Shift value for RTCC_MINTICK */
+#define _RTCC_IFS_MINTICK_MASK              0x40UL                              /**< Bit mask for RTCC_MINTICK */
+#define _RTCC_IFS_MINTICK_DEFAULT           0x00000000UL                        /**< Mode DEFAULT for RTCC_IFS */
+#define RTCC_IFS_MINTICK_DEFAULT            (_RTCC_IFS_MINTICK_DEFAULT << 6)    /**< Shifted mode DEFAULT for RTCC_IFS */
+#define RTCC_IFS_HOURTICK                   (0x1UL << 7)                        /**< Set HOURTICK Interrupt Flag */
+#define _RTCC_IFS_HOURTICK_SHIFT            7                                   /**< Shift value for RTCC_HOURTICK */
+#define _RTCC_IFS_HOURTICK_MASK             0x80UL                              /**< Bit mask for RTCC_HOURTICK */
+#define _RTCC_IFS_HOURTICK_DEFAULT          0x00000000UL                        /**< Mode DEFAULT for RTCC_IFS */
+#define RTCC_IFS_HOURTICK_DEFAULT           (_RTCC_IFS_HOURTICK_DEFAULT << 7)   /**< Shifted mode DEFAULT for RTCC_IFS */
+#define RTCC_IFS_DAYTICK                    (0x1UL << 8)                        /**< Set DAYTICK Interrupt Flag */
+#define _RTCC_IFS_DAYTICK_SHIFT             8                                   /**< Shift value for RTCC_DAYTICK */
+#define _RTCC_IFS_DAYTICK_MASK              0x100UL                             /**< Bit mask for RTCC_DAYTICK */
+#define _RTCC_IFS_DAYTICK_DEFAULT           0x00000000UL                        /**< Mode DEFAULT for RTCC_IFS */
+#define RTCC_IFS_DAYTICK_DEFAULT            (_RTCC_IFS_DAYTICK_DEFAULT << 8)    /**< Shifted mode DEFAULT for RTCC_IFS */
+#define RTCC_IFS_DAYOWOF                    (0x1UL << 9)                        /**< Set DAYOWOF Interrupt Flag */
+#define _RTCC_IFS_DAYOWOF_SHIFT             9                                   /**< Shift value for RTCC_DAYOWOF */
+#define _RTCC_IFS_DAYOWOF_MASK              0x200UL                             /**< Bit mask for RTCC_DAYOWOF */
+#define _RTCC_IFS_DAYOWOF_DEFAULT           0x00000000UL                        /**< Mode DEFAULT for RTCC_IFS */
+#define RTCC_IFS_DAYOWOF_DEFAULT            (_RTCC_IFS_DAYOWOF_DEFAULT << 9)    /**< Shifted mode DEFAULT for RTCC_IFS */
+#define RTCC_IFS_MONTHTICK                  (0x1UL << 10)                       /**< Set MONTHTICK Interrupt Flag */
+#define _RTCC_IFS_MONTHTICK_SHIFT           10                                  /**< Shift value for RTCC_MONTHTICK */
+#define _RTCC_IFS_MONTHTICK_MASK            0x400UL                             /**< Bit mask for RTCC_MONTHTICK */
+#define _RTCC_IFS_MONTHTICK_DEFAULT         0x00000000UL                        /**< Mode DEFAULT for RTCC_IFS */
+#define RTCC_IFS_MONTHTICK_DEFAULT          (_RTCC_IFS_MONTHTICK_DEFAULT << 10) /**< Shifted mode DEFAULT for RTCC_IFS */
+
+/* Bit fields for RTCC IFC */
+#define _RTCC_IFC_RESETVALUE                0x00000000UL                        /**< Default value for RTCC_IFC */
+#define _RTCC_IFC_MASK                      0x000007FFUL                        /**< Mask for RTCC_IFC */
+#define RTCC_IFC_OF                         (0x1UL << 0)                        /**< Clear OF Interrupt Flag */
+#define _RTCC_IFC_OF_SHIFT                  0                                   /**< Shift value for RTCC_OF */
+#define _RTCC_IFC_OF_MASK                   0x1UL                               /**< Bit mask for RTCC_OF */
+#define _RTCC_IFC_OF_DEFAULT                0x00000000UL                        /**< Mode DEFAULT for RTCC_IFC */
+#define RTCC_IFC_OF_DEFAULT                 (_RTCC_IFC_OF_DEFAULT << 0)         /**< Shifted mode DEFAULT for RTCC_IFC */
+#define RTCC_IFC_CC0                        (0x1UL << 1)                        /**< Clear CC0 Interrupt Flag */
+#define _RTCC_IFC_CC0_SHIFT                 1                                   /**< Shift value for RTCC_CC0 */
+#define _RTCC_IFC_CC0_MASK                  0x2UL                               /**< Bit mask for RTCC_CC0 */
+#define _RTCC_IFC_CC0_DEFAULT               0x00000000UL                        /**< Mode DEFAULT for RTCC_IFC */
+#define RTCC_IFC_CC0_DEFAULT                (_RTCC_IFC_CC0_DEFAULT << 1)        /**< Shifted mode DEFAULT for RTCC_IFC */
+#define RTCC_IFC_CC1                        (0x1UL << 2)                        /**< Clear CC1 Interrupt Flag */
+#define _RTCC_IFC_CC1_SHIFT                 2                                   /**< Shift value for RTCC_CC1 */
+#define _RTCC_IFC_CC1_MASK                  0x4UL                               /**< Bit mask for RTCC_CC1 */
+#define _RTCC_IFC_CC1_DEFAULT               0x00000000UL                        /**< Mode DEFAULT for RTCC_IFC */
+#define RTCC_IFC_CC1_DEFAULT                (_RTCC_IFC_CC1_DEFAULT << 2)        /**< Shifted mode DEFAULT for RTCC_IFC */
+#define RTCC_IFC_CC2                        (0x1UL << 3)                        /**< Clear CC2 Interrupt Flag */
+#define _RTCC_IFC_CC2_SHIFT                 3                                   /**< Shift value for RTCC_CC2 */
+#define _RTCC_IFC_CC2_MASK                  0x8UL                               /**< Bit mask for RTCC_CC2 */
+#define _RTCC_IFC_CC2_DEFAULT               0x00000000UL                        /**< Mode DEFAULT for RTCC_IFC */
+#define RTCC_IFC_CC2_DEFAULT                (_RTCC_IFC_CC2_DEFAULT << 3)        /**< Shifted mode DEFAULT for RTCC_IFC */
+#define RTCC_IFC_OSCFAIL                    (0x1UL << 4)                        /**< Clear OSCFAIL Interrupt Flag */
+#define _RTCC_IFC_OSCFAIL_SHIFT             4                                   /**< Shift value for RTCC_OSCFAIL */
+#define _RTCC_IFC_OSCFAIL_MASK              0x10UL                              /**< Bit mask for RTCC_OSCFAIL */
+#define _RTCC_IFC_OSCFAIL_DEFAULT           0x00000000UL                        /**< Mode DEFAULT for RTCC_IFC */
+#define RTCC_IFC_OSCFAIL_DEFAULT            (_RTCC_IFC_OSCFAIL_DEFAULT << 4)    /**< Shifted mode DEFAULT for RTCC_IFC */
+#define RTCC_IFC_CNTTICK                    (0x1UL << 5)                        /**< Clear CNTTICK Interrupt Flag */
+#define _RTCC_IFC_CNTTICK_SHIFT             5                                   /**< Shift value for RTCC_CNTTICK */
+#define _RTCC_IFC_CNTTICK_MASK              0x20UL                              /**< Bit mask for RTCC_CNTTICK */
+#define _RTCC_IFC_CNTTICK_DEFAULT           0x00000000UL                        /**< Mode DEFAULT for RTCC_IFC */
+#define RTCC_IFC_CNTTICK_DEFAULT            (_RTCC_IFC_CNTTICK_DEFAULT << 5)    /**< Shifted mode DEFAULT for RTCC_IFC */
+#define RTCC_IFC_MINTICK                    (0x1UL << 6)                        /**< Clear MINTICK Interrupt Flag */
+#define _RTCC_IFC_MINTICK_SHIFT             6                                   /**< Shift value for RTCC_MINTICK */
+#define _RTCC_IFC_MINTICK_MASK              0x40UL                              /**< Bit mask for RTCC_MINTICK */
+#define _RTCC_IFC_MINTICK_DEFAULT           0x00000000UL                        /**< Mode DEFAULT for RTCC_IFC */
+#define RTCC_IFC_MINTICK_DEFAULT            (_RTCC_IFC_MINTICK_DEFAULT << 6)    /**< Shifted mode DEFAULT for RTCC_IFC */
+#define RTCC_IFC_HOURTICK                   (0x1UL << 7)                        /**< Clear HOURTICK Interrupt Flag */
+#define _RTCC_IFC_HOURTICK_SHIFT            7                                   /**< Shift value for RTCC_HOURTICK */
+#define _RTCC_IFC_HOURTICK_MASK             0x80UL                              /**< Bit mask for RTCC_HOURTICK */
+#define _RTCC_IFC_HOURTICK_DEFAULT          0x00000000UL                        /**< Mode DEFAULT for RTCC_IFC */
+#define RTCC_IFC_HOURTICK_DEFAULT           (_RTCC_IFC_HOURTICK_DEFAULT << 7)   /**< Shifted mode DEFAULT for RTCC_IFC */
+#define RTCC_IFC_DAYTICK                    (0x1UL << 8)                        /**< Clear DAYTICK Interrupt Flag */
+#define _RTCC_IFC_DAYTICK_SHIFT             8                                   /**< Shift value for RTCC_DAYTICK */
+#define _RTCC_IFC_DAYTICK_MASK              0x100UL                             /**< Bit mask for RTCC_DAYTICK */
+#define _RTCC_IFC_DAYTICK_DEFAULT           0x00000000UL                        /**< Mode DEFAULT for RTCC_IFC */
+#define RTCC_IFC_DAYTICK_DEFAULT            (_RTCC_IFC_DAYTICK_DEFAULT << 8)    /**< Shifted mode DEFAULT for RTCC_IFC */
+#define RTCC_IFC_DAYOWOF                    (0x1UL << 9)                        /**< Clear DAYOWOF Interrupt Flag */
+#define _RTCC_IFC_DAYOWOF_SHIFT             9                                   /**< Shift value for RTCC_DAYOWOF */
+#define _RTCC_IFC_DAYOWOF_MASK              0x200UL                             /**< Bit mask for RTCC_DAYOWOF */
+#define _RTCC_IFC_DAYOWOF_DEFAULT           0x00000000UL                        /**< Mode DEFAULT for RTCC_IFC */
+#define RTCC_IFC_DAYOWOF_DEFAULT            (_RTCC_IFC_DAYOWOF_DEFAULT << 9)    /**< Shifted mode DEFAULT for RTCC_IFC */
+#define RTCC_IFC_MONTHTICK                  (0x1UL << 10)                       /**< Clear MONTHTICK Interrupt Flag */
+#define _RTCC_IFC_MONTHTICK_SHIFT           10                                  /**< Shift value for RTCC_MONTHTICK */
+#define _RTCC_IFC_MONTHTICK_MASK            0x400UL                             /**< Bit mask for RTCC_MONTHTICK */
+#define _RTCC_IFC_MONTHTICK_DEFAULT         0x00000000UL                        /**< Mode DEFAULT for RTCC_IFC */
+#define RTCC_IFC_MONTHTICK_DEFAULT          (_RTCC_IFC_MONTHTICK_DEFAULT << 10) /**< Shifted mode DEFAULT for RTCC_IFC */
+
+/* Bit fields for RTCC IEN */
+#define _RTCC_IEN_RESETVALUE                0x00000000UL                        /**< Default value for RTCC_IEN */
+#define _RTCC_IEN_MASK                      0x000007FFUL                        /**< Mask for RTCC_IEN */
+#define RTCC_IEN_OF                         (0x1UL << 0)                        /**< OF Interrupt Enable */
+#define _RTCC_IEN_OF_SHIFT                  0                                   /**< Shift value for RTCC_OF */
+#define _RTCC_IEN_OF_MASK                   0x1UL                               /**< Bit mask for RTCC_OF */
+#define _RTCC_IEN_OF_DEFAULT                0x00000000UL                        /**< Mode DEFAULT for RTCC_IEN */
+#define RTCC_IEN_OF_DEFAULT                 (_RTCC_IEN_OF_DEFAULT << 0)         /**< Shifted mode DEFAULT for RTCC_IEN */
+#define RTCC_IEN_CC0                        (0x1UL << 1)                        /**< CC0 Interrupt Enable */
+#define _RTCC_IEN_CC0_SHIFT                 1                                   /**< Shift value for RTCC_CC0 */
+#define _RTCC_IEN_CC0_MASK                  0x2UL                               /**< Bit mask for RTCC_CC0 */
+#define _RTCC_IEN_CC0_DEFAULT               0x00000000UL                        /**< Mode DEFAULT for RTCC_IEN */
+#define RTCC_IEN_CC0_DEFAULT                (_RTCC_IEN_CC0_DEFAULT << 1)        /**< Shifted mode DEFAULT for RTCC_IEN */
+#define RTCC_IEN_CC1                        (0x1UL << 2)                        /**< CC1 Interrupt Enable */
+#define _RTCC_IEN_CC1_SHIFT                 2                                   /**< Shift value for RTCC_CC1 */
+#define _RTCC_IEN_CC1_MASK                  0x4UL                               /**< Bit mask for RTCC_CC1 */
+#define _RTCC_IEN_CC1_DEFAULT               0x00000000UL                        /**< Mode DEFAULT for RTCC_IEN */
+#define RTCC_IEN_CC1_DEFAULT                (_RTCC_IEN_CC1_DEFAULT << 2)        /**< Shifted mode DEFAULT for RTCC_IEN */
+#define RTCC_IEN_CC2                        (0x1UL << 3)                        /**< CC2 Interrupt Enable */
+#define _RTCC_IEN_CC2_SHIFT                 3                                   /**< Shift value for RTCC_CC2 */
+#define _RTCC_IEN_CC2_MASK                  0x8UL                               /**< Bit mask for RTCC_CC2 */
+#define _RTCC_IEN_CC2_DEFAULT               0x00000000UL                        /**< Mode DEFAULT for RTCC_IEN */
+#define RTCC_IEN_CC2_DEFAULT                (_RTCC_IEN_CC2_DEFAULT << 3)        /**< Shifted mode DEFAULT for RTCC_IEN */
+#define RTCC_IEN_OSCFAIL                    (0x1UL << 4)                        /**< OSCFAIL Interrupt Enable */
+#define _RTCC_IEN_OSCFAIL_SHIFT             4                                   /**< Shift value for RTCC_OSCFAIL */
+#define _RTCC_IEN_OSCFAIL_MASK              0x10UL                              /**< Bit mask for RTCC_OSCFAIL */
+#define _RTCC_IEN_OSCFAIL_DEFAULT           0x00000000UL                        /**< Mode DEFAULT for RTCC_IEN */
+#define RTCC_IEN_OSCFAIL_DEFAULT            (_RTCC_IEN_OSCFAIL_DEFAULT << 4)    /**< Shifted mode DEFAULT for RTCC_IEN */
+#define RTCC_IEN_CNTTICK                    (0x1UL << 5)                        /**< CNTTICK Interrupt Enable */
+#define _RTCC_IEN_CNTTICK_SHIFT             5                                   /**< Shift value for RTCC_CNTTICK */
+#define _RTCC_IEN_CNTTICK_MASK              0x20UL                              /**< Bit mask for RTCC_CNTTICK */
+#define _RTCC_IEN_CNTTICK_DEFAULT           0x00000000UL                        /**< Mode DEFAULT for RTCC_IEN */
+#define RTCC_IEN_CNTTICK_DEFAULT            (_RTCC_IEN_CNTTICK_DEFAULT << 5)    /**< Shifted mode DEFAULT for RTCC_IEN */
+#define RTCC_IEN_MINTICK                    (0x1UL << 6)                        /**< MINTICK Interrupt Enable */
+#define _RTCC_IEN_MINTICK_SHIFT             6                                   /**< Shift value for RTCC_MINTICK */
+#define _RTCC_IEN_MINTICK_MASK              0x40UL                              /**< Bit mask for RTCC_MINTICK */
+#define _RTCC_IEN_MINTICK_DEFAULT           0x00000000UL                        /**< Mode DEFAULT for RTCC_IEN */
+#define RTCC_IEN_MINTICK_DEFAULT            (_RTCC_IEN_MINTICK_DEFAULT << 6)    /**< Shifted mode DEFAULT for RTCC_IEN */
+#define RTCC_IEN_HOURTICK                   (0x1UL << 7)                        /**< HOURTICK Interrupt Enable */
+#define _RTCC_IEN_HOURTICK_SHIFT            7                                   /**< Shift value for RTCC_HOURTICK */
+#define _RTCC_IEN_HOURTICK_MASK             0x80UL                              /**< Bit mask for RTCC_HOURTICK */
+#define _RTCC_IEN_HOURTICK_DEFAULT          0x00000000UL                        /**< Mode DEFAULT for RTCC_IEN */
+#define RTCC_IEN_HOURTICK_DEFAULT           (_RTCC_IEN_HOURTICK_DEFAULT << 7)   /**< Shifted mode DEFAULT for RTCC_IEN */
+#define RTCC_IEN_DAYTICK                    (0x1UL << 8)                        /**< DAYTICK Interrupt Enable */
+#define _RTCC_IEN_DAYTICK_SHIFT             8                                   /**< Shift value for RTCC_DAYTICK */
+#define _RTCC_IEN_DAYTICK_MASK              0x100UL                             /**< Bit mask for RTCC_DAYTICK */
+#define _RTCC_IEN_DAYTICK_DEFAULT           0x00000000UL                        /**< Mode DEFAULT for RTCC_IEN */
+#define RTCC_IEN_DAYTICK_DEFAULT            (_RTCC_IEN_DAYTICK_DEFAULT << 8)    /**< Shifted mode DEFAULT for RTCC_IEN */
+#define RTCC_IEN_DAYOWOF                    (0x1UL << 9)                        /**< DAYOWOF Interrupt Enable */
+#define _RTCC_IEN_DAYOWOF_SHIFT             9                                   /**< Shift value for RTCC_DAYOWOF */
+#define _RTCC_IEN_DAYOWOF_MASK              0x200UL                             /**< Bit mask for RTCC_DAYOWOF */
+#define _RTCC_IEN_DAYOWOF_DEFAULT           0x00000000UL                        /**< Mode DEFAULT for RTCC_IEN */
+#define RTCC_IEN_DAYOWOF_DEFAULT            (_RTCC_IEN_DAYOWOF_DEFAULT << 9)    /**< Shifted mode DEFAULT for RTCC_IEN */
+#define RTCC_IEN_MONTHTICK                  (0x1UL << 10)                       /**< MONTHTICK Interrupt Enable */
+#define _RTCC_IEN_MONTHTICK_SHIFT           10                                  /**< Shift value for RTCC_MONTHTICK */
+#define _RTCC_IEN_MONTHTICK_MASK            0x400UL                             /**< Bit mask for RTCC_MONTHTICK */
+#define _RTCC_IEN_MONTHTICK_DEFAULT         0x00000000UL                        /**< Mode DEFAULT for RTCC_IEN */
+#define RTCC_IEN_MONTHTICK_DEFAULT          (_RTCC_IEN_MONTHTICK_DEFAULT << 10) /**< Shifted mode DEFAULT for RTCC_IEN */
+
+/* Bit fields for RTCC STATUS */
+#define _RTCC_STATUS_RESETVALUE             0x00000000UL /**< Default value for RTCC_STATUS */
+#define _RTCC_STATUS_MASK                   0x00000000UL /**< Mask for RTCC_STATUS */
+
+/* Bit fields for RTCC CMD */
+#define _RTCC_CMD_RESETVALUE                0x00000000UL                       /**< Default value for RTCC_CMD */
+#define _RTCC_CMD_MASK                      0x00000001UL                       /**< Mask for RTCC_CMD */
+#define RTCC_CMD_CLRSTATUS                  (0x1UL << 0)                       /**< Clear RTCC_STATUS register. */
+#define _RTCC_CMD_CLRSTATUS_SHIFT           0                                  /**< Shift value for RTCC_CLRSTATUS */
+#define _RTCC_CMD_CLRSTATUS_MASK            0x1UL                              /**< Bit mask for RTCC_CLRSTATUS */
+#define _RTCC_CMD_CLRSTATUS_DEFAULT         0x00000000UL                       /**< Mode DEFAULT for RTCC_CMD */
+#define RTCC_CMD_CLRSTATUS_DEFAULT          (_RTCC_CMD_CLRSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CMD */
+
+/* Bit fields for RTCC SYNCBUSY */
+#define _RTCC_SYNCBUSY_RESETVALUE           0x00000000UL                      /**< Default value for RTCC_SYNCBUSY */
+#define _RTCC_SYNCBUSY_MASK                 0x00000020UL                      /**< Mask for RTCC_SYNCBUSY */
+#define RTCC_SYNCBUSY_CMD                   (0x1UL << 5)                      /**< CMD Register Busy */
+#define _RTCC_SYNCBUSY_CMD_SHIFT            5                                 /**< Shift value for RTCC_CMD */
+#define _RTCC_SYNCBUSY_CMD_MASK             0x20UL                            /**< Bit mask for RTCC_CMD */
+#define _RTCC_SYNCBUSY_CMD_DEFAULT          0x00000000UL                      /**< Mode DEFAULT for RTCC_SYNCBUSY */
+#define RTCC_SYNCBUSY_CMD_DEFAULT           (_RTCC_SYNCBUSY_CMD_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_SYNCBUSY */
+
+/* Bit fields for RTCC POWERDOWN */
+#define _RTCC_POWERDOWN_RESETVALUE          0x00000000UL                       /**< Default value for RTCC_POWERDOWN */
+#define _RTCC_POWERDOWN_MASK                0x00000001UL                       /**< Mask for RTCC_POWERDOWN */
+#define RTCC_POWERDOWN_RAM                  (0x1UL << 0)                       /**< Retention RAM power-down */
+#define _RTCC_POWERDOWN_RAM_SHIFT           0                                  /**< Shift value for RTCC_RAM */
+#define _RTCC_POWERDOWN_RAM_MASK            0x1UL                              /**< Bit mask for RTCC_RAM */
+#define _RTCC_POWERDOWN_RAM_DEFAULT         0x00000000UL                       /**< Mode DEFAULT for RTCC_POWERDOWN */
+#define RTCC_POWERDOWN_RAM_DEFAULT          (_RTCC_POWERDOWN_RAM_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_POWERDOWN */
+
+/* Bit fields for RTCC LOCK */
+#define _RTCC_LOCK_RESETVALUE               0x00000000UL                       /**< Default value for RTCC_LOCK */
+#define _RTCC_LOCK_MASK                     0x0000FFFFUL                       /**< Mask for RTCC_LOCK */
+#define _RTCC_LOCK_LOCKKEY_SHIFT            0                                  /**< Shift value for RTCC_LOCKKEY */
+#define _RTCC_LOCK_LOCKKEY_MASK             0xFFFFUL                           /**< Bit mask for RTCC_LOCKKEY */
+#define _RTCC_LOCK_LOCKKEY_DEFAULT          0x00000000UL                       /**< Mode DEFAULT for RTCC_LOCK */
+#define _RTCC_LOCK_LOCKKEY_LOCK             0x00000000UL                       /**< Mode LOCK for RTCC_LOCK */
+#define _RTCC_LOCK_LOCKKEY_UNLOCKED         0x00000000UL                       /**< Mode UNLOCKED for RTCC_LOCK */
+#define _RTCC_LOCK_LOCKKEY_LOCKED           0x00000001UL                       /**< Mode LOCKED for RTCC_LOCK */
+#define _RTCC_LOCK_LOCKKEY_UNLOCK           0x0000AEE8UL                       /**< Mode UNLOCK for RTCC_LOCK */
+#define RTCC_LOCK_LOCKKEY_DEFAULT           (_RTCC_LOCK_LOCKKEY_DEFAULT << 0)  /**< Shifted mode DEFAULT for RTCC_LOCK */
+#define RTCC_LOCK_LOCKKEY_LOCK              (_RTCC_LOCK_LOCKKEY_LOCK << 0)     /**< Shifted mode LOCK for RTCC_LOCK */
+#define RTCC_LOCK_LOCKKEY_UNLOCKED          (_RTCC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for RTCC_LOCK */
+#define RTCC_LOCK_LOCKKEY_LOCKED            (_RTCC_LOCK_LOCKKEY_LOCKED << 0)   /**< Shifted mode LOCKED for RTCC_LOCK */
+#define RTCC_LOCK_LOCKKEY_UNLOCK            (_RTCC_LOCK_LOCKKEY_UNLOCK << 0)   /**< Shifted mode UNLOCK for RTCC_LOCK */
+
+/* Bit fields for RTCC EM4WUEN */
+#define _RTCC_EM4WUEN_RESETVALUE            0x00000000UL                       /**< Default value for RTCC_EM4WUEN */
+#define _RTCC_EM4WUEN_MASK                  0x00000001UL                       /**< Mask for RTCC_EM4WUEN */
+#define RTCC_EM4WUEN_EM4WU                  (0x1UL << 0)                       /**< EM4 Wake-up enable */
+#define _RTCC_EM4WUEN_EM4WU_SHIFT           0                                  /**< Shift value for RTCC_EM4WU */
+#define _RTCC_EM4WUEN_EM4WU_MASK            0x1UL                              /**< Bit mask for RTCC_EM4WU */
+#define _RTCC_EM4WUEN_EM4WU_DEFAULT         0x00000000UL                       /**< Mode DEFAULT for RTCC_EM4WUEN */
+#define RTCC_EM4WUEN_EM4WU_DEFAULT          (_RTCC_EM4WUEN_EM4WU_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_EM4WUEN */
+
+/* Bit fields for RTCC CC_CTRL */
+#define _RTCC_CC_CTRL_RESETVALUE            0x00000000UL                            /**< Default value for RTCC_CC_CTRL */
+#define _RTCC_CC_CTRL_MASK                  0x0003FBFFUL                            /**< Mask for RTCC_CC_CTRL */
+#define _RTCC_CC_CTRL_MODE_SHIFT            0                                       /**< Shift value for CC_MODE */
+#define _RTCC_CC_CTRL_MODE_MASK             0x3UL                                   /**< Bit mask for CC_MODE */
+#define _RTCC_CC_CTRL_MODE_DEFAULT          0x00000000UL                            /**< Mode DEFAULT for RTCC_CC_CTRL */
+#define _RTCC_CC_CTRL_MODE_OFF              0x00000000UL                            /**< Mode OFF for RTCC_CC_CTRL */
+#define _RTCC_CC_CTRL_MODE_INPUTCAPTURE     0x00000001UL                            /**< Mode INPUTCAPTURE for RTCC_CC_CTRL */
+#define _RTCC_CC_CTRL_MODE_OUTPUTCOMPARE    0x00000002UL                            /**< Mode OUTPUTCOMPARE for RTCC_CC_CTRL */
+#define RTCC_CC_CTRL_MODE_DEFAULT           (_RTCC_CC_CTRL_MODE_DEFAULT << 0)       /**< Shifted mode DEFAULT for RTCC_CC_CTRL */
+#define RTCC_CC_CTRL_MODE_OFF               (_RTCC_CC_CTRL_MODE_OFF << 0)           /**< Shifted mode OFF for RTCC_CC_CTRL */
+#define RTCC_CC_CTRL_MODE_INPUTCAPTURE      (_RTCC_CC_CTRL_MODE_INPUTCAPTURE << 0)  /**< Shifted mode INPUTCAPTURE for RTCC_CC_CTRL */
+#define RTCC_CC_CTRL_MODE_OUTPUTCOMPARE     (_RTCC_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for RTCC_CC_CTRL */
+#define _RTCC_CC_CTRL_CMOA_SHIFT            2                                       /**< Shift value for CC_CMOA */
+#define _RTCC_CC_CTRL_CMOA_MASK             0xCUL                                   /**< Bit mask for CC_CMOA */
+#define _RTCC_CC_CTRL_CMOA_DEFAULT          0x00000000UL                            /**< Mode DEFAULT for RTCC_CC_CTRL */
+#define _RTCC_CC_CTRL_CMOA_PULSE            0x00000000UL                            /**< Mode PULSE for RTCC_CC_CTRL */
+#define _RTCC_CC_CTRL_CMOA_TOGGLE           0x00000001UL                            /**< Mode TOGGLE for RTCC_CC_CTRL */
+#define _RTCC_CC_CTRL_CMOA_CLEAR            0x00000002UL                            /**< Mode CLEAR for RTCC_CC_CTRL */
+#define _RTCC_CC_CTRL_CMOA_SET              0x00000003UL                            /**< Mode SET for RTCC_CC_CTRL */
+#define RTCC_CC_CTRL_CMOA_DEFAULT           (_RTCC_CC_CTRL_CMOA_DEFAULT << 2)       /**< Shifted mode DEFAULT for RTCC_CC_CTRL */
+#define RTCC_CC_CTRL_CMOA_PULSE             (_RTCC_CC_CTRL_CMOA_PULSE << 2)         /**< Shifted mode PULSE for RTCC_CC_CTRL */
+#define RTCC_CC_CTRL_CMOA_TOGGLE            (_RTCC_CC_CTRL_CMOA_TOGGLE << 2)        /**< Shifted mode TOGGLE for RTCC_CC_CTRL */
+#define RTCC_CC_CTRL_CMOA_CLEAR             (_RTCC_CC_CTRL_CMOA_CLEAR << 2)         /**< Shifted mode CLEAR for RTCC_CC_CTRL */
+#define RTCC_CC_CTRL_CMOA_SET               (_RTCC_CC_CTRL_CMOA_SET << 2)           /**< Shifted mode SET for RTCC_CC_CTRL */
+#define _RTCC_CC_CTRL_ICEDGE_SHIFT          4                                       /**< Shift value for CC_ICEDGE */
+#define _RTCC_CC_CTRL_ICEDGE_MASK           0x30UL                                  /**< Bit mask for CC_ICEDGE */
+#define _RTCC_CC_CTRL_ICEDGE_DEFAULT        0x00000000UL                            /**< Mode DEFAULT for RTCC_CC_CTRL */
+#define _RTCC_CC_CTRL_ICEDGE_RISING         0x00000000UL                            /**< Mode RISING for RTCC_CC_CTRL */
+#define _RTCC_CC_CTRL_ICEDGE_FALLING        0x00000001UL                            /**< Mode FALLING for RTCC_CC_CTRL */
+#define _RTCC_CC_CTRL_ICEDGE_BOTH           0x00000002UL                            /**< Mode BOTH for RTCC_CC_CTRL */
+#define _RTCC_CC_CTRL_ICEDGE_NONE           0x00000003UL                            /**< Mode NONE for RTCC_CC_CTRL */
+#define RTCC_CC_CTRL_ICEDGE_DEFAULT         (_RTCC_CC_CTRL_ICEDGE_DEFAULT << 4)     /**< Shifted mode DEFAULT for RTCC_CC_CTRL */
+#define RTCC_CC_CTRL_ICEDGE_RISING          (_RTCC_CC_CTRL_ICEDGE_RISING << 4)      /**< Shifted mode RISING for RTCC_CC_CTRL */
+#define RTCC_CC_CTRL_ICEDGE_FALLING         (_RTCC_CC_CTRL_ICEDGE_FALLING << 4)     /**< Shifted mode FALLING for RTCC_CC_CTRL */
+#define RTCC_CC_CTRL_ICEDGE_BOTH            (_RTCC_CC_CTRL_ICEDGE_BOTH << 4)        /**< Shifted mode BOTH for RTCC_CC_CTRL */
+#define RTCC_CC_CTRL_ICEDGE_NONE            (_RTCC_CC_CTRL_ICEDGE_NONE << 4)        /**< Shifted mode NONE for RTCC_CC_CTRL */
+#define _RTCC_CC_CTRL_PRSSEL_SHIFT          6                                       /**< Shift value for CC_PRSSEL */
+#define _RTCC_CC_CTRL_PRSSEL_MASK           0x3C0UL                                 /**< Bit mask for CC_PRSSEL */
+#define _RTCC_CC_CTRL_PRSSEL_DEFAULT        0x00000000UL                            /**< Mode DEFAULT for RTCC_CC_CTRL */
+#define _RTCC_CC_CTRL_PRSSEL_PRSCH0         0x00000000UL                            /**< Mode PRSCH0 for RTCC_CC_CTRL */
+#define _RTCC_CC_CTRL_PRSSEL_PRSCH1         0x00000001UL                            /**< Mode PRSCH1 for RTCC_CC_CTRL */
+#define _RTCC_CC_CTRL_PRSSEL_PRSCH2         0x00000002UL                            /**< Mode PRSCH2 for RTCC_CC_CTRL */
+#define _RTCC_CC_CTRL_PRSSEL_PRSCH3         0x00000003UL                            /**< Mode PRSCH3 for RTCC_CC_CTRL */
+#define _RTCC_CC_CTRL_PRSSEL_PRSCH4         0x00000004UL                            /**< Mode PRSCH4 for RTCC_CC_CTRL */
+#define _RTCC_CC_CTRL_PRSSEL_PRSCH5         0x00000005UL                            /**< Mode PRSCH5 for RTCC_CC_CTRL */
+#define _RTCC_CC_CTRL_PRSSEL_PRSCH6         0x00000006UL                            /**< Mode PRSCH6 for RTCC_CC_CTRL */
+#define _RTCC_CC_CTRL_PRSSEL_PRSCH7         0x00000007UL                            /**< Mode PRSCH7 for RTCC_CC_CTRL */
+#define _RTCC_CC_CTRL_PRSSEL_PRSCH8         0x00000008UL                            /**< Mode PRSCH8 for RTCC_CC_CTRL */
+#define _RTCC_CC_CTRL_PRSSEL_PRSCH9         0x00000009UL                            /**< Mode PRSCH9 for RTCC_CC_CTRL */
+#define _RTCC_CC_CTRL_PRSSEL_PRSCH10        0x0000000AUL                            /**< Mode PRSCH10 for RTCC_CC_CTRL */
+#define _RTCC_CC_CTRL_PRSSEL_PRSCH11        0x0000000BUL                            /**< Mode PRSCH11 for RTCC_CC_CTRL */
+#define RTCC_CC_CTRL_PRSSEL_DEFAULT         (_RTCC_CC_CTRL_PRSSEL_DEFAULT << 6)     /**< Shifted mode DEFAULT for RTCC_CC_CTRL */
+#define RTCC_CC_CTRL_PRSSEL_PRSCH0          (_RTCC_CC_CTRL_PRSSEL_PRSCH0 << 6)      /**< Shifted mode PRSCH0 for RTCC_CC_CTRL */
+#define RTCC_CC_CTRL_PRSSEL_PRSCH1          (_RTCC_CC_CTRL_PRSSEL_PRSCH1 << 6)      /**< Shifted mode PRSCH1 for RTCC_CC_CTRL */
+#define RTCC_CC_CTRL_PRSSEL_PRSCH2          (_RTCC_CC_CTRL_PRSSEL_PRSCH2 << 6)      /**< Shifted mode PRSCH2 for RTCC_CC_CTRL */
+#define RTCC_CC_CTRL_PRSSEL_PRSCH3          (_RTCC_CC_CTRL_PRSSEL_PRSCH3 << 6)      /**< Shifted mode PRSCH3 for RTCC_CC_CTRL */
+#define RTCC_CC_CTRL_PRSSEL_PRSCH4          (_RTCC_CC_CTRL_PRSSEL_PRSCH4 << 6)      /**< Shifted mode PRSCH4 for RTCC_CC_CTRL */
+#define RTCC_CC_CTRL_PRSSEL_PRSCH5          (_RTCC_CC_CTRL_PRSSEL_PRSCH5 << 6)      /**< Shifted mode PRSCH5 for RTCC_CC_CTRL */
+#define RTCC_CC_CTRL_PRSSEL_PRSCH6          (_RTCC_CC_CTRL_PRSSEL_PRSCH6 << 6)      /**< Shifted mode PRSCH6 for RTCC_CC_CTRL */
+#define RTCC_CC_CTRL_PRSSEL_PRSCH7          (_RTCC_CC_CTRL_PRSSEL_PRSCH7 << 6)      /**< Shifted mode PRSCH7 for RTCC_CC_CTRL */
+#define RTCC_CC_CTRL_PRSSEL_PRSCH8          (_RTCC_CC_CTRL_PRSSEL_PRSCH8 << 6)      /**< Shifted mode PRSCH8 for RTCC_CC_CTRL */
+#define RTCC_CC_CTRL_PRSSEL_PRSCH9          (_RTCC_CC_CTRL_PRSSEL_PRSCH9 << 6)      /**< Shifted mode PRSCH9 for RTCC_CC_CTRL */
+#define RTCC_CC_CTRL_PRSSEL_PRSCH10         (_RTCC_CC_CTRL_PRSSEL_PRSCH10 << 6)     /**< Shifted mode PRSCH10 for RTCC_CC_CTRL */
+#define RTCC_CC_CTRL_PRSSEL_PRSCH11         (_RTCC_CC_CTRL_PRSSEL_PRSCH11 << 6)     /**< Shifted mode PRSCH11 for RTCC_CC_CTRL */
+#define RTCC_CC_CTRL_COMPBASE               (0x1UL << 11)                           /**< Capture compare channel comparison base. */
+#define _RTCC_CC_CTRL_COMPBASE_SHIFT        11                                      /**< Shift value for CC_COMPBASE */
+#define _RTCC_CC_CTRL_COMPBASE_MASK         0x800UL                                 /**< Bit mask for CC_COMPBASE */
+#define _RTCC_CC_CTRL_COMPBASE_DEFAULT      0x00000000UL                            /**< Mode DEFAULT for RTCC_CC_CTRL */
+#define _RTCC_CC_CTRL_COMPBASE_CNT          0x00000000UL                            /**< Mode CNT for RTCC_CC_CTRL */
+#define _RTCC_CC_CTRL_COMPBASE_PRECNT       0x00000001UL                            /**< Mode PRECNT for RTCC_CC_CTRL */
+#define RTCC_CC_CTRL_COMPBASE_DEFAULT       (_RTCC_CC_CTRL_COMPBASE_DEFAULT << 11)  /**< Shifted mode DEFAULT for RTCC_CC_CTRL */
+#define RTCC_CC_CTRL_COMPBASE_CNT           (_RTCC_CC_CTRL_COMPBASE_CNT << 11)      /**< Shifted mode CNT for RTCC_CC_CTRL */
+#define RTCC_CC_CTRL_COMPBASE_PRECNT        (_RTCC_CC_CTRL_COMPBASE_PRECNT << 11)   /**< Shifted mode PRECNT for RTCC_CC_CTRL */
+#define _RTCC_CC_CTRL_COMPMASK_SHIFT        12                                      /**< Shift value for CC_COMPMASK */
+#define _RTCC_CC_CTRL_COMPMASK_MASK         0x1F000UL                               /**< Bit mask for CC_COMPMASK */
+#define _RTCC_CC_CTRL_COMPMASK_DEFAULT      0x00000000UL                            /**< Mode DEFAULT for RTCC_CC_CTRL */
+#define RTCC_CC_CTRL_COMPMASK_DEFAULT       (_RTCC_CC_CTRL_COMPMASK_DEFAULT << 12)  /**< Shifted mode DEFAULT for RTCC_CC_CTRL */
+#define RTCC_CC_CTRL_DAYCC                  (0x1UL << 17)                           /**< Day Capture/Compare selection */
+#define _RTCC_CC_CTRL_DAYCC_SHIFT           17                                      /**< Shift value for CC_DAYCC */
+#define _RTCC_CC_CTRL_DAYCC_MASK            0x20000UL                               /**< Bit mask for CC_DAYCC */
+#define _RTCC_CC_CTRL_DAYCC_DEFAULT         0x00000000UL                            /**< Mode DEFAULT for RTCC_CC_CTRL */
+#define _RTCC_CC_CTRL_DAYCC_MONTH           0x00000000UL                            /**< Mode MONTH for RTCC_CC_CTRL */
+#define _RTCC_CC_CTRL_DAYCC_WEEK            0x00000001UL                            /**< Mode WEEK for RTCC_CC_CTRL */
+#define RTCC_CC_CTRL_DAYCC_DEFAULT          (_RTCC_CC_CTRL_DAYCC_DEFAULT << 17)     /**< Shifted mode DEFAULT for RTCC_CC_CTRL */
+#define RTCC_CC_CTRL_DAYCC_MONTH            (_RTCC_CC_CTRL_DAYCC_MONTH << 17)       /**< Shifted mode MONTH for RTCC_CC_CTRL */
+#define RTCC_CC_CTRL_DAYCC_WEEK             (_RTCC_CC_CTRL_DAYCC_WEEK << 17)        /**< Shifted mode WEEK for RTCC_CC_CTRL */
+
+/* Bit fields for RTCC CC_CCV */
+#define _RTCC_CC_CCV_RESETVALUE             0x00000000UL                    /**< Default value for RTCC_CC_CCV */
+#define _RTCC_CC_CCV_MASK                   0xFFFFFFFFUL                    /**< Mask for RTCC_CC_CCV */
+#define _RTCC_CC_CCV_CCV_SHIFT              0                               /**< Shift value for CC_CCV */
+#define _RTCC_CC_CCV_CCV_MASK               0xFFFFFFFFUL                    /**< Bit mask for CC_CCV */
+#define _RTCC_CC_CCV_CCV_DEFAULT            0x00000000UL                    /**< Mode DEFAULT for RTCC_CC_CCV */
+#define RTCC_CC_CCV_CCV_DEFAULT             (_RTCC_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CC_CCV */
+
+/* Bit fields for RTCC CC_TIME */
+#define _RTCC_CC_TIME_RESETVALUE            0x00000000UL                        /**< Default value for RTCC_CC_TIME */
+#define _RTCC_CC_TIME_MASK                  0x003F7F7FUL                        /**< Mask for RTCC_CC_TIME */
+#define _RTCC_CC_TIME_SECU_SHIFT            0                                   /**< Shift value for CC_SECU */
+#define _RTCC_CC_TIME_SECU_MASK             0xFUL                               /**< Bit mask for CC_SECU */
+#define _RTCC_CC_TIME_SECU_DEFAULT          0x00000000UL                        /**< Mode DEFAULT for RTCC_CC_TIME */
+#define RTCC_CC_TIME_SECU_DEFAULT           (_RTCC_CC_TIME_SECU_DEFAULT << 0)   /**< Shifted mode DEFAULT for RTCC_CC_TIME */
+#define _RTCC_CC_TIME_SECT_SHIFT            4                                   /**< Shift value for CC_SECT */
+#define _RTCC_CC_TIME_SECT_MASK             0x70UL                              /**< Bit mask for CC_SECT */
+#define _RTCC_CC_TIME_SECT_DEFAULT          0x00000000UL                        /**< Mode DEFAULT for RTCC_CC_TIME */
+#define RTCC_CC_TIME_SECT_DEFAULT           (_RTCC_CC_TIME_SECT_DEFAULT << 4)   /**< Shifted mode DEFAULT for RTCC_CC_TIME */
+#define _RTCC_CC_TIME_MINU_SHIFT            8                                   /**< Shift value for CC_MINU */
+#define _RTCC_CC_TIME_MINU_MASK             0xF00UL                             /**< Bit mask for CC_MINU */
+#define _RTCC_CC_TIME_MINU_DEFAULT          0x00000000UL                        /**< Mode DEFAULT for RTCC_CC_TIME */
+#define RTCC_CC_TIME_MINU_DEFAULT           (_RTCC_CC_TIME_MINU_DEFAULT << 8)   /**< Shifted mode DEFAULT for RTCC_CC_TIME */
+#define _RTCC_CC_TIME_MINT_SHIFT            12                                  /**< Shift value for CC_MINT */
+#define _RTCC_CC_TIME_MINT_MASK             0x7000UL                            /**< Bit mask for CC_MINT */
+#define _RTCC_CC_TIME_MINT_DEFAULT          0x00000000UL                        /**< Mode DEFAULT for RTCC_CC_TIME */
+#define RTCC_CC_TIME_MINT_DEFAULT           (_RTCC_CC_TIME_MINT_DEFAULT << 12)  /**< Shifted mode DEFAULT for RTCC_CC_TIME */
+#define _RTCC_CC_TIME_HOURU_SHIFT           16                                  /**< Shift value for CC_HOURU */
+#define _RTCC_CC_TIME_HOURU_MASK            0xF0000UL                           /**< Bit mask for CC_HOURU */
+#define _RTCC_CC_TIME_HOURU_DEFAULT         0x00000000UL                        /**< Mode DEFAULT for RTCC_CC_TIME */
+#define RTCC_CC_TIME_HOURU_DEFAULT          (_RTCC_CC_TIME_HOURU_DEFAULT << 16) /**< Shifted mode DEFAULT for RTCC_CC_TIME */
+#define _RTCC_CC_TIME_HOURT_SHIFT           20                                  /**< Shift value for CC_HOURT */
+#define _RTCC_CC_TIME_HOURT_MASK            0x300000UL                          /**< Bit mask for CC_HOURT */
+#define _RTCC_CC_TIME_HOURT_DEFAULT         0x00000000UL                        /**< Mode DEFAULT for RTCC_CC_TIME */
+#define RTCC_CC_TIME_HOURT_DEFAULT          (_RTCC_CC_TIME_HOURT_DEFAULT << 20) /**< Shifted mode DEFAULT for RTCC_CC_TIME */
+
+/* Bit fields for RTCC CC_DATE */
+#define _RTCC_CC_DATE_RESETVALUE            0x00000000UL                         /**< Default value for RTCC_CC_DATE */
+#define _RTCC_CC_DATE_MASK                  0x00001F3FUL                         /**< Mask for RTCC_CC_DATE */
+#define _RTCC_CC_DATE_DAYU_SHIFT            0                                    /**< Shift value for CC_DAYU */
+#define _RTCC_CC_DATE_DAYU_MASK             0xFUL                                /**< Bit mask for CC_DAYU */
+#define _RTCC_CC_DATE_DAYU_DEFAULT          0x00000000UL                         /**< Mode DEFAULT for RTCC_CC_DATE */
+#define RTCC_CC_DATE_DAYU_DEFAULT           (_RTCC_CC_DATE_DAYU_DEFAULT << 0)    /**< Shifted mode DEFAULT for RTCC_CC_DATE */
+#define _RTCC_CC_DATE_DAYT_SHIFT            4                                    /**< Shift value for CC_DAYT */
+#define _RTCC_CC_DATE_DAYT_MASK             0x30UL                               /**< Bit mask for CC_DAYT */
+#define _RTCC_CC_DATE_DAYT_DEFAULT          0x00000000UL                         /**< Mode DEFAULT for RTCC_CC_DATE */
+#define RTCC_CC_DATE_DAYT_DEFAULT           (_RTCC_CC_DATE_DAYT_DEFAULT << 4)    /**< Shifted mode DEFAULT for RTCC_CC_DATE */
+#define _RTCC_CC_DATE_MONTHU_SHIFT          8                                    /**< Shift value for CC_MONTHU */
+#define _RTCC_CC_DATE_MONTHU_MASK           0xF00UL                              /**< Bit mask for CC_MONTHU */
+#define _RTCC_CC_DATE_MONTHU_DEFAULT        0x00000000UL                         /**< Mode DEFAULT for RTCC_CC_DATE */
+#define RTCC_CC_DATE_MONTHU_DEFAULT         (_RTCC_CC_DATE_MONTHU_DEFAULT << 8)  /**< Shifted mode DEFAULT for RTCC_CC_DATE */
+#define RTCC_CC_DATE_MONTHT                 (0x1UL << 12)                        /**< Month, tens. */
+#define _RTCC_CC_DATE_MONTHT_SHIFT          12                                   /**< Shift value for CC_MONTHT */
+#define _RTCC_CC_DATE_MONTHT_MASK           0x1000UL                             /**< Bit mask for CC_MONTHT */
+#define _RTCC_CC_DATE_MONTHT_DEFAULT        0x00000000UL                         /**< Mode DEFAULT for RTCC_CC_DATE */
+#define RTCC_CC_DATE_MONTHT_DEFAULT         (_RTCC_CC_DATE_MONTHT_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_CC_DATE */
+
+/* Bit fields for RTCC RET_REG */
+#define _RTCC_RET_REG_RESETVALUE            0x00000000UL                     /**< Default value for RTCC_RET_REG */
+#define _RTCC_RET_REG_MASK                  0xFFFFFFFFUL                     /**< Mask for RTCC_RET_REG */
+#define _RTCC_RET_REG_REG_SHIFT             0                                /**< Shift value for RET_REG */
+#define _RTCC_RET_REG_REG_MASK              0xFFFFFFFFUL                     /**< Bit mask for RET_REG */
+#define _RTCC_RET_REG_REG_DEFAULT           0x00000000UL                     /**< Mode DEFAULT for RTCC_RET_REG */
+#define RTCC_RET_REG_REG_DEFAULT            (_RTCC_RET_REG_REG_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_RET_REG */
+
+/** @} End of group EFM32PG1B_RTCC */
+/** @} End of group Parts */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG_STK3401/efm32pg1b_rtcc_cc.h	Fri Jan 15 07:45:16 2016 +0000
@@ -0,0 +1,49 @@
+/**************************************************************************//**
+ * @file efm32pg1b_rtcc_cc.h
+ * @brief EFM32PG1B_RTCC_CC register and bit field definitions
+ * @version 4.2.0
+ ******************************************************************************
+ * @section License
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ ******************************************************************************
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software.@n
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.@n
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is
+ * providing the Software "AS IS", with no express or implied warranties of any
+ * kind, including, but not limited to, any implied warranties of
+ * merchantability or fitness for any particular purpose or warranties against
+ * infringement of any proprietary rights of a third party.
+ *
+ * Silicon Laboratories, Inc. will not be liable for any consequential,
+ * incidental, or special damages, or any other relief, or for any claim by
+ * any third party, arising from your use of this Software.
+ *
+ *****************************************************************************/
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @brief RTCC_CC EFM32PG1B RTCC CC
+ *****************************************************************************/
+typedef struct
+{
+  __IO uint32_t CTRL; /**< CC Channel Control Register  */
+  __IO uint32_t CCV;  /**< Capture/Compare Value Register  */
+  __IO uint32_t TIME; /**< Capture/Compare Time Register  */
+  __IO uint32_t DATE; /**< Capture/Compare Date Register  */
+} RTCC_CC_TypeDef;
+
+/** @} End of group Parts */
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG_STK3401/efm32pg1b_rtcc_ret.h	Fri Jan 15 07:45:16 2016 +0000
@@ -0,0 +1,46 @@
+/**************************************************************************//**
+ * @file efm32pg1b_rtcc_ret.h
+ * @brief EFM32PG1B_RTCC_RET register and bit field definitions
+ * @version 4.2.0
+ ******************************************************************************
+ * @section License
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ ******************************************************************************
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software.@n
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.@n
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is
+ * providing the Software "AS IS", with no express or implied warranties of any
+ * kind, including, but not limited to, any implied warranties of
+ * merchantability or fitness for any particular purpose or warranties against
+ * infringement of any proprietary rights of a third party.
+ *
+ * Silicon Laboratories, Inc. will not be liable for any consequential,
+ * incidental, or special damages, or any other relief, or for any claim by
+ * any third party, arising from your use of this Software.
+ *
+ *****************************************************************************/
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @brief RTCC_RET EFM32PG1B RTCC RET
+ *****************************************************************************/
+typedef struct
+{
+  __IO uint32_t REG; /**< Retention register  */
+} RTCC_RET_TypeDef;
+
+/** @} End of group Parts */
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG_STK3401/efm32pg1b_timer.h	Fri Jan 15 07:45:16 2016 +0000
@@ -0,0 +1,1575 @@
+/**************************************************************************//**
+ * @file efm32pg1b_timer.h
+ * @brief EFM32PG1B_TIMER register and bit field definitions
+ * @version 4.2.0
+ ******************************************************************************
+ * @section License
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ ******************************************************************************
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software.@n
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.@n
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is
+ * providing the Software "AS IS", with no express or implied warranties of any
+ * kind, including, but not limited to, any implied warranties of
+ * merchantability or fitness for any particular purpose or warranties against
+ * infringement of any proprietary rights of a third party.
+ *
+ * Silicon Laboratories, Inc. will not be liable for any consequential,
+ * incidental, or special damages, or any other relief, or for any claim by
+ * any third party, arising from your use of this Software.
+ *
+ *****************************************************************************/
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFM32PG1B_TIMER
+ * @{
+ * @brief EFM32PG1B_TIMER Register Declaration
+ *****************************************************************************/
+typedef struct
+{
+  __IO uint32_t    CTRL;         /**< Control Register  */
+  __IO uint32_t    CMD;          /**< Command Register  */
+  __I uint32_t     STATUS;       /**< Status Register  */
+  __I uint32_t     IF;           /**< Interrupt Flag Register  */
+  __IO uint32_t    IFS;          /**< Interrupt Flag Set Register  */
+  __IO uint32_t    IFC;          /**< Interrupt Flag Clear Register  */
+  __IO uint32_t    IEN;          /**< Interrupt Enable Register  */
+  __IO uint32_t    TOP;          /**< Counter Top Value Register  */
+  __IO uint32_t    TOPB;         /**< Counter Top Value Buffer Register  */
+  __IO uint32_t    CNT;          /**< Counter Value Register  */
+  uint32_t         RESERVED0[1]; /**< Reserved for future use **/
+  __IO uint32_t    LOCK;         /**< TIMER Configuration Lock Register  */
+  __IO uint32_t    ROUTEPEN;     /**< I/O Routing Pin Enable Register  */
+  __IO uint32_t    ROUTELOC0;    /**< I/O Routing Location Register  */
+  uint32_t         RESERVED1[1]; /**< Reserved for future use **/
+  __IO uint32_t    ROUTELOC2;    /**< I/O Routing Location Register  */
+
+  uint32_t         RESERVED2[8]; /**< Reserved registers */
+  TIMER_CC_TypeDef CC[4];        /**< Compare/Capture Channel */
+
+  __IO uint32_t    DTCTRL;       /**< DTI Control Register  */
+  __IO uint32_t    DTTIME;       /**< DTI Time Control Register  */
+  __IO uint32_t    DTFC;         /**< DTI Fault Configuration Register  */
+  __IO uint32_t    DTOGEN;       /**< DTI Output Generation Enable Register  */
+  __I uint32_t     DTFAULT;      /**< DTI Fault Register  */
+  __IO uint32_t    DTFAULTC;     /**< DTI Fault Clear Register  */
+  __IO uint32_t    DTLOCK;       /**< DTI Configuration Lock Register  */
+} TIMER_TypeDef;                 /** @} */
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B_TIMER_BitFields
+ * @{
+ *****************************************************************************/
+
+/* Bit fields for TIMER CTRL */
+#define _TIMER_CTRL_RESETVALUE                     0x00000000UL                             /**< Default value for TIMER_CTRL */
+#define _TIMER_CTRL_MASK                           0x3F032FFBUL                             /**< Mask for TIMER_CTRL */
+#define _TIMER_CTRL_MODE_SHIFT                     0                                        /**< Shift value for TIMER_MODE */
+#define _TIMER_CTRL_MODE_MASK                      0x3UL                                    /**< Bit mask for TIMER_MODE */
+#define _TIMER_CTRL_MODE_DEFAULT                   0x00000000UL                             /**< Mode DEFAULT for TIMER_CTRL */
+#define _TIMER_CTRL_MODE_UP                        0x00000000UL                             /**< Mode UP for TIMER_CTRL */
+#define _TIMER_CTRL_MODE_DOWN                      0x00000001UL                             /**< Mode DOWN for TIMER_CTRL */
+#define _TIMER_CTRL_MODE_UPDOWN                    0x00000002UL                             /**< Mode UPDOWN for TIMER_CTRL */
+#define _TIMER_CTRL_MODE_QDEC                      0x00000003UL                             /**< Mode QDEC for TIMER_CTRL */
+#define TIMER_CTRL_MODE_DEFAULT                    (_TIMER_CTRL_MODE_DEFAULT << 0)          /**< Shifted mode DEFAULT for TIMER_CTRL */
+#define TIMER_CTRL_MODE_UP                         (_TIMER_CTRL_MODE_UP << 0)               /**< Shifted mode UP for TIMER_CTRL */
+#define TIMER_CTRL_MODE_DOWN                       (_TIMER_CTRL_MODE_DOWN << 0)             /**< Shifted mode DOWN for TIMER_CTRL */
+#define TIMER_CTRL_MODE_UPDOWN                     (_TIMER_CTRL_MODE_UPDOWN << 0)           /**< Shifted mode UPDOWN for TIMER_CTRL */
+#define TIMER_CTRL_MODE_QDEC                       (_TIMER_CTRL_MODE_QDEC << 0)             /**< Shifted mode QDEC for TIMER_CTRL */
+#define TIMER_CTRL_SYNC                            (0x1UL << 3)                             /**< Timer Start/Stop/Reload Synchronization */
+#define _TIMER_CTRL_SYNC_SHIFT                     3                                        /**< Shift value for TIMER_SYNC */
+#define _TIMER_CTRL_SYNC_MASK                      0x8UL                                    /**< Bit mask for TIMER_SYNC */
+#define _TIMER_CTRL_SYNC_DEFAULT                   0x00000000UL                             /**< Mode DEFAULT for TIMER_CTRL */
+#define TIMER_CTRL_SYNC_DEFAULT                    (_TIMER_CTRL_SYNC_DEFAULT << 3)          /**< Shifted mode DEFAULT for TIMER_CTRL */
+#define TIMER_CTRL_OSMEN                           (0x1UL << 4)                             /**< One-shot Mode Enable */
+#define _TIMER_CTRL_OSMEN_SHIFT                    4                                        /**< Shift value for TIMER_OSMEN */
+#define _TIMER_CTRL_OSMEN_MASK                     0x10UL                                   /**< Bit mask for TIMER_OSMEN */
+#define _TIMER_CTRL_OSMEN_DEFAULT                  0x00000000UL                             /**< Mode DEFAULT for TIMER_CTRL */
+#define TIMER_CTRL_OSMEN_DEFAULT                   (_TIMER_CTRL_OSMEN_DEFAULT << 4)         /**< Shifted mode DEFAULT for TIMER_CTRL */
+#define TIMER_CTRL_QDM                             (0x1UL << 5)                             /**< Quadrature Decoder Mode Selection */
+#define _TIMER_CTRL_QDM_SHIFT                      5                                        /**< Shift value for TIMER_QDM */
+#define _TIMER_CTRL_QDM_MASK                       0x20UL                                   /**< Bit mask for TIMER_QDM */
+#define _TIMER_CTRL_QDM_DEFAULT                    0x00000000UL                             /**< Mode DEFAULT for TIMER_CTRL */
+#define _TIMER_CTRL_QDM_X2                         0x00000000UL                             /**< Mode X2 for TIMER_CTRL */
+#define _TIMER_CTRL_QDM_X4                         0x00000001UL                             /**< Mode X4 for TIMER_CTRL */
+#define TIMER_CTRL_QDM_DEFAULT                     (_TIMER_CTRL_QDM_DEFAULT << 5)           /**< Shifted mode DEFAULT for TIMER_CTRL */
+#define TIMER_CTRL_QDM_X2                          (_TIMER_CTRL_QDM_X2 << 5)                /**< Shifted mode X2 for TIMER_CTRL */
+#define TIMER_CTRL_QDM_X4                          (_TIMER_CTRL_QDM_X4 << 5)                /**< Shifted mode X4 for TIMER_CTRL */
+#define TIMER_CTRL_DEBUGRUN                        (0x1UL << 6)                             /**< Debug Mode Run Enable */
+#define _TIMER_CTRL_DEBUGRUN_SHIFT                 6                                        /**< Shift value for TIMER_DEBUGRUN */
+#define _TIMER_CTRL_DEBUGRUN_MASK                  0x40UL                                   /**< Bit mask for TIMER_DEBUGRUN */
+#define _TIMER_CTRL_DEBUGRUN_DEFAULT               0x00000000UL                             /**< Mode DEFAULT for TIMER_CTRL */
+#define TIMER_CTRL_DEBUGRUN_DEFAULT                (_TIMER_CTRL_DEBUGRUN_DEFAULT << 6)      /**< Shifted mode DEFAULT for TIMER_CTRL */
+#define TIMER_CTRL_DMACLRACT                       (0x1UL << 7)                             /**< DMA Request Clear on Active */
+#define _TIMER_CTRL_DMACLRACT_SHIFT                7                                        /**< Shift value for TIMER_DMACLRACT */
+#define _TIMER_CTRL_DMACLRACT_MASK                 0x80UL                                   /**< Bit mask for TIMER_DMACLRACT */
+#define _TIMER_CTRL_DMACLRACT_DEFAULT              0x00000000UL                             /**< Mode DEFAULT for TIMER_CTRL */
+#define TIMER_CTRL_DMACLRACT_DEFAULT               (_TIMER_CTRL_DMACLRACT_DEFAULT << 7)     /**< Shifted mode DEFAULT for TIMER_CTRL */
+#define _TIMER_CTRL_RISEA_SHIFT                    8                                        /**< Shift value for TIMER_RISEA */
+#define _TIMER_CTRL_RISEA_MASK                     0x300UL                                  /**< Bit mask for TIMER_RISEA */
+#define _TIMER_CTRL_RISEA_DEFAULT                  0x00000000UL                             /**< Mode DEFAULT for TIMER_CTRL */
+#define _TIMER_CTRL_RISEA_NONE                     0x00000000UL                             /**< Mode NONE for TIMER_CTRL */
+#define _TIMER_CTRL_RISEA_START                    0x00000001UL                             /**< Mode START for TIMER_CTRL */
+#define _TIMER_CTRL_RISEA_STOP                     0x00000002UL                             /**< Mode STOP for TIMER_CTRL */
+#define _TIMER_CTRL_RISEA_RELOADSTART              0x00000003UL                             /**< Mode RELOADSTART for TIMER_CTRL */
+#define TIMER_CTRL_RISEA_DEFAULT                   (_TIMER_CTRL_RISEA_DEFAULT << 8)         /**< Shifted mode DEFAULT for TIMER_CTRL */
+#define TIMER_CTRL_RISEA_NONE                      (_TIMER_CTRL_RISEA_NONE << 8)            /**< Shifted mode NONE for TIMER_CTRL */
+#define TIMER_CTRL_RISEA_START                     (_TIMER_CTRL_RISEA_START << 8)           /**< Shifted mode START for TIMER_CTRL */
+#define TIMER_CTRL_RISEA_STOP                      (_TIMER_CTRL_RISEA_STOP << 8)            /**< Shifted mode STOP for TIMER_CTRL */
+#define TIMER_CTRL_RISEA_RELOADSTART               (_TIMER_CTRL_RISEA_RELOADSTART << 8)     /**< Shifted mode RELOADSTART for TIMER_CTRL */
+#define _TIMER_CTRL_FALLA_SHIFT                    10                                       /**< Shift value for TIMER_FALLA */
+#define _TIMER_CTRL_FALLA_MASK                     0xC00UL                                  /**< Bit mask for TIMER_FALLA */
+#define _TIMER_CTRL_FALLA_DEFAULT                  0x00000000UL                             /**< Mode DEFAULT for TIMER_CTRL */
+#define _TIMER_CTRL_FALLA_NONE                     0x00000000UL                             /**< Mode NONE for TIMER_CTRL */
+#define _TIMER_CTRL_FALLA_START                    0x00000001UL                             /**< Mode START for TIMER_CTRL */
+#define _TIMER_CTRL_FALLA_STOP                     0x00000002UL                             /**< Mode STOP for TIMER_CTRL */
+#define _TIMER_CTRL_FALLA_RELOADSTART              0x00000003UL                             /**< Mode RELOADSTART for TIMER_CTRL */
+#define TIMER_CTRL_FALLA_DEFAULT                   (_TIMER_CTRL_FALLA_DEFAULT << 10)        /**< Shifted mode DEFAULT for TIMER_CTRL */
+#define TIMER_CTRL_FALLA_NONE                      (_TIMER_CTRL_FALLA_NONE << 10)           /**< Shifted mode NONE for TIMER_CTRL */
+#define TIMER_CTRL_FALLA_START                     (_TIMER_CTRL_FALLA_START << 10)          /**< Shifted mode START for TIMER_CTRL */
+#define TIMER_CTRL_FALLA_STOP                      (_TIMER_CTRL_FALLA_STOP << 10)           /**< Shifted mode STOP for TIMER_CTRL */
+#define TIMER_CTRL_FALLA_RELOADSTART               (_TIMER_CTRL_FALLA_RELOADSTART << 10)    /**< Shifted mode RELOADSTART for TIMER_CTRL */
+#define TIMER_CTRL_X2CNT                           (0x1UL << 13)                            /**< 2x Count Mode */
+#define _TIMER_CTRL_X2CNT_SHIFT                    13                                       /**< Shift value for TIMER_X2CNT */
+#define _TIMER_CTRL_X2CNT_MASK                     0x2000UL                                 /**< Bit mask for TIMER_X2CNT */
+#define _TIMER_CTRL_X2CNT_DEFAULT                  0x00000000UL                             /**< Mode DEFAULT for TIMER_CTRL */
+#define TIMER_CTRL_X2CNT_DEFAULT                   (_TIMER_CTRL_X2CNT_DEFAULT << 13)        /**< Shifted mode DEFAULT for TIMER_CTRL */
+#define _TIMER_CTRL_CLKSEL_SHIFT                   16                                       /**< Shift value for TIMER_CLKSEL */
+#define _TIMER_CTRL_CLKSEL_MASK                    0x30000UL                                /**< Bit mask for TIMER_CLKSEL */
+#define _TIMER_CTRL_CLKSEL_DEFAULT                 0x00000000UL                             /**< Mode DEFAULT for TIMER_CTRL */
+#define _TIMER_CTRL_CLKSEL_PRESCHFPERCLK           0x00000000UL                             /**< Mode PRESCHFPERCLK for TIMER_CTRL */
+#define _TIMER_CTRL_CLKSEL_CC1                     0x00000001UL                             /**< Mode CC1 for TIMER_CTRL */
+#define _TIMER_CTRL_CLKSEL_TIMEROUF                0x00000002UL                             /**< Mode TIMEROUF for TIMER_CTRL */
+#define TIMER_CTRL_CLKSEL_DEFAULT                  (_TIMER_CTRL_CLKSEL_DEFAULT << 16)       /**< Shifted mode DEFAULT for TIMER_CTRL */
+#define TIMER_CTRL_CLKSEL_PRESCHFPERCLK            (_TIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for TIMER_CTRL */
+#define TIMER_CTRL_CLKSEL_CC1                      (_TIMER_CTRL_CLKSEL_CC1 << 16)           /**< Shifted mode CC1 for TIMER_CTRL */
+#define TIMER_CTRL_CLKSEL_TIMEROUF                 (_TIMER_CTRL_CLKSEL_TIMEROUF << 16)      /**< Shifted mode TIMEROUF for TIMER_CTRL */
+#define _TIMER_CTRL_PRESC_SHIFT                    24                                       /**< Shift value for TIMER_PRESC */
+#define _TIMER_CTRL_PRESC_MASK                     0xF000000UL                              /**< Bit mask for TIMER_PRESC */
+#define _TIMER_CTRL_PRESC_DEFAULT                  0x00000000UL                             /**< Mode DEFAULT for TIMER_CTRL */
+#define _TIMER_CTRL_PRESC_DIV1                     0x00000000UL                             /**< Mode DIV1 for TIMER_CTRL */
+#define _TIMER_CTRL_PRESC_DIV2                     0x00000001UL                             /**< Mode DIV2 for TIMER_CTRL */
+#define _TIMER_CTRL_PRESC_DIV4                     0x00000002UL                             /**< Mode DIV4 for TIMER_CTRL */
+#define _TIMER_CTRL_PRESC_DIV8                     0x00000003UL                             /**< Mode DIV8 for TIMER_CTRL */
+#define _TIMER_CTRL_PRESC_DIV16                    0x00000004UL                             /**< Mode DIV16 for TIMER_CTRL */
+#define _TIMER_CTRL_PRESC_DIV32                    0x00000005UL                             /**< Mode DIV32 for TIMER_CTRL */
+#define _TIMER_CTRL_PRESC_DIV64                    0x00000006UL                             /**< Mode DIV64 for TIMER_CTRL */
+#define _TIMER_CTRL_PRESC_DIV128                   0x00000007UL                             /**< Mode DIV128 for TIMER_CTRL */
+#define _TIMER_CTRL_PRESC_DIV256                   0x00000008UL                             /**< Mode DIV256 for TIMER_CTRL */
+#define _TIMER_CTRL_PRESC_DIV512                   0x00000009UL                             /**< Mode DIV512 for TIMER_CTRL */
+#define _TIMER_CTRL_PRESC_DIV1024                  0x0000000AUL                             /**< Mode DIV1024 for TIMER_CTRL */
+#define TIMER_CTRL_PRESC_DEFAULT                   (_TIMER_CTRL_PRESC_DEFAULT << 24)        /**< Shifted mode DEFAULT for TIMER_CTRL */
+#define TIMER_CTRL_PRESC_DIV1                      (_TIMER_CTRL_PRESC_DIV1 << 24)           /**< Shifted mode DIV1 for TIMER_CTRL */
+#define TIMER_CTRL_PRESC_DIV2                      (_TIMER_CTRL_PRESC_DIV2 << 24)           /**< Shifted mode DIV2 for TIMER_CTRL */
+#define TIMER_CTRL_PRESC_DIV4                      (_TIMER_CTRL_PRESC_DIV4 << 24)           /**< Shifted mode DIV4 for TIMER_CTRL */
+#define TIMER_CTRL_PRESC_DIV8                      (_TIMER_CTRL_PRESC_DIV8 << 24)           /**< Shifted mode DIV8 for TIMER_CTRL */
+#define TIMER_CTRL_PRESC_DIV16                     (_TIMER_CTRL_PRESC_DIV16 << 24)          /**< Shifted mode DIV16 for TIMER_CTRL */
+#define TIMER_CTRL_PRESC_DIV32                     (_TIMER_CTRL_PRESC_DIV32 << 24)          /**< Shifted mode DIV32 for TIMER_CTRL */
+#define TIMER_CTRL_PRESC_DIV64                     (_TIMER_CTRL_PRESC_DIV64 << 24)          /**< Shifted mode DIV64 for TIMER_CTRL */
+#define TIMER_CTRL_PRESC_DIV128                    (_TIMER_CTRL_PRESC_DIV128 << 24)         /**< Shifted mode DIV128 for TIMER_CTRL */
+#define TIMER_CTRL_PRESC_DIV256                    (_TIMER_CTRL_PRESC_DIV256 << 24)         /**< Shifted mode DIV256 for TIMER_CTRL */
+#define TIMER_CTRL_PRESC_DIV512                    (_TIMER_CTRL_PRESC_DIV512 << 24)         /**< Shifted mode DIV512 for TIMER_CTRL */
+#define TIMER_CTRL_PRESC_DIV1024                   (_TIMER_CTRL_PRESC_DIV1024 << 24)        /**< Shifted mode DIV1024 for TIMER_CTRL */
+#define TIMER_CTRL_ATI                             (0x1UL << 28)                            /**< Always Track Inputs */
+#define _TIMER_CTRL_ATI_SHIFT                      28                                       /**< Shift value for TIMER_ATI */
+#define _TIMER_CTRL_ATI_MASK                       0x10000000UL                             /**< Bit mask for TIMER_ATI */
+#define _TIMER_CTRL_ATI_DEFAULT                    0x00000000UL                             /**< Mode DEFAULT for TIMER_CTRL */
+#define TIMER_CTRL_ATI_DEFAULT                     (_TIMER_CTRL_ATI_DEFAULT << 28)          /**< Shifted mode DEFAULT for TIMER_CTRL */
+#define TIMER_CTRL_RSSCOIST                        (0x1UL << 29)                            /**< Reload-Start Sets Compare Ouptut initial State */
+#define _TIMER_CTRL_RSSCOIST_SHIFT                 29                                       /**< Shift value for TIMER_RSSCOIST */
+#define _TIMER_CTRL_RSSCOIST_MASK                  0x20000000UL                             /**< Bit mask for TIMER_RSSCOIST */
+#define _TIMER_CTRL_RSSCOIST_DEFAULT               0x00000000UL                             /**< Mode DEFAULT for TIMER_CTRL */
+#define TIMER_CTRL_RSSCOIST_DEFAULT                (_TIMER_CTRL_RSSCOIST_DEFAULT << 29)     /**< Shifted mode DEFAULT for TIMER_CTRL */
+
+/* Bit fields for TIMER CMD */
+#define _TIMER_CMD_RESETVALUE                      0x00000000UL                    /**< Default value for TIMER_CMD */
+#define _TIMER_CMD_MASK                            0x00000003UL                    /**< Mask for TIMER_CMD */
+#define TIMER_CMD_START                            (0x1UL << 0)                    /**< Start Timer */
+#define _TIMER_CMD_START_SHIFT                     0                               /**< Shift value for TIMER_START */
+#define _TIMER_CMD_START_MASK                      0x1UL                           /**< Bit mask for TIMER_START */
+#define _TIMER_CMD_START_DEFAULT                   0x00000000UL                    /**< Mode DEFAULT for TIMER_CMD */
+#define TIMER_CMD_START_DEFAULT                    (_TIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CMD */
+#define TIMER_CMD_STOP                             (0x1UL << 1)                    /**< Stop Timer */
+#define _TIMER_CMD_STOP_SHIFT                      1                               /**< Shift value for TIMER_STOP */
+#define _TIMER_CMD_STOP_MASK                       0x2UL                           /**< Bit mask for TIMER_STOP */
+#define _TIMER_CMD_STOP_DEFAULT                    0x00000000UL                    /**< Mode DEFAULT for TIMER_CMD */
+#define TIMER_CMD_STOP_DEFAULT                     (_TIMER_CMD_STOP_DEFAULT << 1)  /**< Shifted mode DEFAULT for TIMER_CMD */
+
+/* Bit fields for TIMER STATUS */
+#define _TIMER_STATUS_RESETVALUE                   0x00000000UL                          /**< Default value for TIMER_STATUS */
+#define _TIMER_STATUS_MASK                         0x0F0F0F07UL                          /**< Mask for TIMER_STATUS */
+#define TIMER_STATUS_RUNNING                       (0x1UL << 0)                          /**< Running */
+#define _TIMER_STATUS_RUNNING_SHIFT                0                                     /**< Shift value for TIMER_RUNNING */
+#define _TIMER_STATUS_RUNNING_MASK                 0x1UL                                 /**< Bit mask for TIMER_RUNNING */
+#define _TIMER_STATUS_RUNNING_DEFAULT              0x00000000UL                          /**< Mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_RUNNING_DEFAULT               (_TIMER_STATUS_RUNNING_DEFAULT << 0)  /**< Shifted mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_DIR                           (0x1UL << 1)                          /**< Direction */
+#define _TIMER_STATUS_DIR_SHIFT                    1                                     /**< Shift value for TIMER_DIR */
+#define _TIMER_STATUS_DIR_MASK                     0x2UL                                 /**< Bit mask for TIMER_DIR */
+#define _TIMER_STATUS_DIR_DEFAULT                  0x00000000UL                          /**< Mode DEFAULT for TIMER_STATUS */
+#define _TIMER_STATUS_DIR_UP                       0x00000000UL                          /**< Mode UP for TIMER_STATUS */
+#define _TIMER_STATUS_DIR_DOWN                     0x00000001UL                          /**< Mode DOWN for TIMER_STATUS */
+#define TIMER_STATUS_DIR_DEFAULT                   (_TIMER_STATUS_DIR_DEFAULT << 1)      /**< Shifted mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_DIR_UP                        (_TIMER_STATUS_DIR_UP << 1)           /**< Shifted mode UP for TIMER_STATUS */
+#define TIMER_STATUS_DIR_DOWN                      (_TIMER_STATUS_DIR_DOWN << 1)         /**< Shifted mode DOWN for TIMER_STATUS */
+#define TIMER_STATUS_TOPBV                         (0x1UL << 2)                          /**< TOPB Valid */
+#define _TIMER_STATUS_TOPBV_SHIFT                  2                                     /**< Shift value for TIMER_TOPBV */
+#define _TIMER_STATUS_TOPBV_MASK                   0x4UL                                 /**< Bit mask for TIMER_TOPBV */
+#define _TIMER_STATUS_TOPBV_DEFAULT                0x00000000UL                          /**< Mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_TOPBV_DEFAULT                 (_TIMER_STATUS_TOPBV_DEFAULT << 2)    /**< Shifted mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_CCVBV0                        (0x1UL << 8)                          /**< CC0 CCVB Valid */
+#define _TIMER_STATUS_CCVBV0_SHIFT                 8                                     /**< Shift value for TIMER_CCVBV0 */
+#define _TIMER_STATUS_CCVBV0_MASK                  0x100UL                               /**< Bit mask for TIMER_CCVBV0 */
+#define _TIMER_STATUS_CCVBV0_DEFAULT               0x00000000UL                          /**< Mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_CCVBV0_DEFAULT                (_TIMER_STATUS_CCVBV0_DEFAULT << 8)   /**< Shifted mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_CCVBV1                        (0x1UL << 9)                          /**< CC1 CCVB Valid */
+#define _TIMER_STATUS_CCVBV1_SHIFT                 9                                     /**< Shift value for TIMER_CCVBV1 */
+#define _TIMER_STATUS_CCVBV1_MASK                  0x200UL                               /**< Bit mask for TIMER_CCVBV1 */
+#define _TIMER_STATUS_CCVBV1_DEFAULT               0x00000000UL                          /**< Mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_CCVBV1_DEFAULT                (_TIMER_STATUS_CCVBV1_DEFAULT << 9)   /**< Shifted mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_CCVBV2                        (0x1UL << 10)                         /**< CC2 CCVB Valid */
+#define _TIMER_STATUS_CCVBV2_SHIFT                 10                                    /**< Shift value for TIMER_CCVBV2 */
+#define _TIMER_STATUS_CCVBV2_MASK                  0x400UL                               /**< Bit mask for TIMER_CCVBV2 */
+#define _TIMER_STATUS_CCVBV2_DEFAULT               0x00000000UL                          /**< Mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_CCVBV2_DEFAULT                (_TIMER_STATUS_CCVBV2_DEFAULT << 10)  /**< Shifted mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_CCVBV3                        (0x1UL << 11)                         /**< CC3 CCVB Valid */
+#define _TIMER_STATUS_CCVBV3_SHIFT                 11                                    /**< Shift value for TIMER_CCVBV3 */
+#define _TIMER_STATUS_CCVBV3_MASK                  0x800UL                               /**< Bit mask for TIMER_CCVBV3 */
+#define _TIMER_STATUS_CCVBV3_DEFAULT               0x00000000UL                          /**< Mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_CCVBV3_DEFAULT                (_TIMER_STATUS_CCVBV3_DEFAULT << 11)  /**< Shifted mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_ICV0                          (0x1UL << 16)                         /**< CC0 Input Capture Valid */
+#define _TIMER_STATUS_ICV0_SHIFT                   16                                    /**< Shift value for TIMER_ICV0 */
+#define _TIMER_STATUS_ICV0_MASK                    0x10000UL                             /**< Bit mask for TIMER_ICV0 */
+#define _TIMER_STATUS_ICV0_DEFAULT                 0x00000000UL                          /**< Mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_ICV0_DEFAULT                  (_TIMER_STATUS_ICV0_DEFAULT << 16)    /**< Shifted mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_ICV1                          (0x1UL << 17)                         /**< CC1 Input Capture Valid */
+#define _TIMER_STATUS_ICV1_SHIFT                   17                                    /**< Shift value for TIMER_ICV1 */
+#define _TIMER_STATUS_ICV1_MASK                    0x20000UL                             /**< Bit mask for TIMER_ICV1 */
+#define _TIMER_STATUS_ICV1_DEFAULT                 0x00000000UL                          /**< Mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_ICV1_DEFAULT                  (_TIMER_STATUS_ICV1_DEFAULT << 17)    /**< Shifted mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_ICV2                          (0x1UL << 18)                         /**< CC2 Input Capture Valid */
+#define _TIMER_STATUS_ICV2_SHIFT                   18                                    /**< Shift value for TIMER_ICV2 */
+#define _TIMER_STATUS_ICV2_MASK                    0x40000UL                             /**< Bit mask for TIMER_ICV2 */
+#define _TIMER_STATUS_ICV2_DEFAULT                 0x00000000UL                          /**< Mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_ICV2_DEFAULT                  (_TIMER_STATUS_ICV2_DEFAULT << 18)    /**< Shifted mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_ICV3                          (0x1UL << 19)                         /**< CC3 Input Capture Valid */
+#define _TIMER_STATUS_ICV3_SHIFT                   19                                    /**< Shift value for TIMER_ICV3 */
+#define _TIMER_STATUS_ICV3_MASK                    0x80000UL                             /**< Bit mask for TIMER_ICV3 */
+#define _TIMER_STATUS_ICV3_DEFAULT                 0x00000000UL                          /**< Mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_ICV3_DEFAULT                  (_TIMER_STATUS_ICV3_DEFAULT << 19)    /**< Shifted mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_CCPOL0                        (0x1UL << 24)                         /**< CC0 Polarity */
+#define _TIMER_STATUS_CCPOL0_SHIFT                 24                                    /**< Shift value for TIMER_CCPOL0 */
+#define _TIMER_STATUS_CCPOL0_MASK                  0x1000000UL                           /**< Bit mask for TIMER_CCPOL0 */
+#define _TIMER_STATUS_CCPOL0_DEFAULT               0x00000000UL                          /**< Mode DEFAULT for TIMER_STATUS */
+#define _TIMER_STATUS_CCPOL0_LOWRISE               0x00000000UL                          /**< Mode LOWRISE for TIMER_STATUS */
+#define _TIMER_STATUS_CCPOL0_HIGHFALL              0x00000001UL                          /**< Mode HIGHFALL for TIMER_STATUS */
+#define TIMER_STATUS_CCPOL0_DEFAULT                (_TIMER_STATUS_CCPOL0_DEFAULT << 24)  /**< Shifted mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_CCPOL0_LOWRISE                (_TIMER_STATUS_CCPOL0_LOWRISE << 24)  /**< Shifted mode LOWRISE for TIMER_STATUS */
+#define TIMER_STATUS_CCPOL0_HIGHFALL               (_TIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for TIMER_STATUS */
+#define TIMER_STATUS_CCPOL1                        (0x1UL << 25)                         /**< CC1 Polarity */
+#define _TIMER_STATUS_CCPOL1_SHIFT                 25                                    /**< Shift value for TIMER_CCPOL1 */
+#define _TIMER_STATUS_CCPOL1_MASK                  0x2000000UL                           /**< Bit mask for TIMER_CCPOL1 */
+#define _TIMER_STATUS_CCPOL1_DEFAULT               0x00000000UL                          /**< Mode DEFAULT for TIMER_STATUS */
+#define _TIMER_STATUS_CCPOL1_LOWRISE               0x00000000UL                          /**< Mode LOWRISE for TIMER_STATUS */
+#define _TIMER_STATUS_CCPOL1_HIGHFALL              0x00000001UL                          /**< Mode HIGHFALL for TIMER_STATUS */
+#define TIMER_STATUS_CCPOL1_DEFAULT                (_TIMER_STATUS_CCPOL1_DEFAULT << 25)  /**< Shifted mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_CCPOL1_LOWRISE                (_TIMER_STATUS_CCPOL1_LOWRISE << 25)  /**< Shifted mode LOWRISE for TIMER_STATUS */
+#define TIMER_STATUS_CCPOL1_HIGHFALL               (_TIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for TIMER_STATUS */
+#define TIMER_STATUS_CCPOL2                        (0x1UL << 26)                         /**< CC2 Polarity */
+#define _TIMER_STATUS_CCPOL2_SHIFT                 26                                    /**< Shift value for TIMER_CCPOL2 */
+#define _TIMER_STATUS_CCPOL2_MASK                  0x4000000UL                           /**< Bit mask for TIMER_CCPOL2 */
+#define _TIMER_STATUS_CCPOL2_DEFAULT               0x00000000UL                          /**< Mode DEFAULT for TIMER_STATUS */
+#define _TIMER_STATUS_CCPOL2_LOWRISE               0x00000000UL                          /**< Mode LOWRISE for TIMER_STATUS */
+#define _TIMER_STATUS_CCPOL2_HIGHFALL              0x00000001UL                          /**< Mode HIGHFALL for TIMER_STATUS */
+#define TIMER_STATUS_CCPOL2_DEFAULT                (_TIMER_STATUS_CCPOL2_DEFAULT << 26)  /**< Shifted mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_CCPOL2_LOWRISE                (_TIMER_STATUS_CCPOL2_LOWRISE << 26)  /**< Shifted mode LOWRISE for TIMER_STATUS */
+#define TIMER_STATUS_CCPOL2_HIGHFALL               (_TIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for TIMER_STATUS */
+#define TIMER_STATUS_CCPOL3                        (0x1UL << 27)                         /**< CC3 Polarity */
+#define _TIMER_STATUS_CCPOL3_SHIFT                 27                                    /**< Shift value for TIMER_CCPOL3 */
+#define _TIMER_STATUS_CCPOL3_MASK                  0x8000000UL                           /**< Bit mask for TIMER_CCPOL3 */
+#define _TIMER_STATUS_CCPOL3_DEFAULT               0x00000000UL                          /**< Mode DEFAULT for TIMER_STATUS */
+#define _TIMER_STATUS_CCPOL3_LOWRISE               0x00000000UL                          /**< Mode LOWRISE for TIMER_STATUS */
+#define _TIMER_STATUS_CCPOL3_HIGHFALL              0x00000001UL                          /**< Mode HIGHFALL for TIMER_STATUS */
+#define TIMER_STATUS_CCPOL3_DEFAULT                (_TIMER_STATUS_CCPOL3_DEFAULT << 27)  /**< Shifted mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_CCPOL3_LOWRISE                (_TIMER_STATUS_CCPOL3_LOWRISE << 27)  /**< Shifted mode LOWRISE for TIMER_STATUS */
+#define TIMER_STATUS_CCPOL3_HIGHFALL               (_TIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for TIMER_STATUS */
+
+/* Bit fields for TIMER IF */
+#define _TIMER_IF_RESETVALUE                       0x00000000UL                     /**< Default value for TIMER_IF */
+#define _TIMER_IF_MASK                             0x00000FF7UL                     /**< Mask for TIMER_IF */
+#define TIMER_IF_OF                                (0x1UL << 0)                     /**< Overflow Interrupt Flag */
+#define _TIMER_IF_OF_SHIFT                         0                                /**< Shift value for TIMER_OF */
+#define _TIMER_IF_OF_MASK                          0x1UL                            /**< Bit mask for TIMER_OF */
+#define _TIMER_IF_OF_DEFAULT                       0x00000000UL                     /**< Mode DEFAULT for TIMER_IF */
+#define TIMER_IF_OF_DEFAULT                        (_TIMER_IF_OF_DEFAULT << 0)      /**< Shifted mode DEFAULT for TIMER_IF */
+#define TIMER_IF_UF                                (0x1UL << 1)                     /**< Underflow Interrupt Flag */
+#define _TIMER_IF_UF_SHIFT                         1                                /**< Shift value for TIMER_UF */
+#define _TIMER_IF_UF_MASK                          0x2UL                            /**< Bit mask for TIMER_UF */
+#define _TIMER_IF_UF_DEFAULT                       0x00000000UL                     /**< Mode DEFAULT for TIMER_IF */
+#define TIMER_IF_UF_DEFAULT                        (_TIMER_IF_UF_DEFAULT << 1)      /**< Shifted mode DEFAULT for TIMER_IF */
+#define TIMER_IF_DIRCHG                            (0x1UL << 2)                     /**< Direction Change Detect Interrupt Flag */
+#define _TIMER_IF_DIRCHG_SHIFT                     2                                /**< Shift value for TIMER_DIRCHG */
+#define _TIMER_IF_DIRCHG_MASK                      0x4UL                            /**< Bit mask for TIMER_DIRCHG */
+#define _TIMER_IF_DIRCHG_DEFAULT                   0x00000000UL                     /**< Mode DEFAULT for TIMER_IF */
+#define TIMER_IF_DIRCHG_DEFAULT                    (_TIMER_IF_DIRCHG_DEFAULT << 2)  /**< Shifted mode DEFAULT for TIMER_IF */
+#define TIMER_IF_CC0                               (0x1UL << 4)                     /**< CC Channel 0 Interrupt Flag */
+#define _TIMER_IF_CC0_SHIFT                        4                                /**< Shift value for TIMER_CC0 */
+#define _TIMER_IF_CC0_MASK                         0x10UL                           /**< Bit mask for TIMER_CC0 */
+#define _TIMER_IF_CC0_DEFAULT                      0x00000000UL                     /**< Mode DEFAULT for TIMER_IF */
+#define TIMER_IF_CC0_DEFAULT                       (_TIMER_IF_CC0_DEFAULT << 4)     /**< Shifted mode DEFAULT for TIMER_IF */
+#define TIMER_IF_CC1                               (0x1UL << 5)                     /**< CC Channel 1 Interrupt Flag */
+#define _TIMER_IF_CC1_SHIFT                        5                                /**< Shift value for TIMER_CC1 */
+#define _TIMER_IF_CC1_MASK                         0x20UL                           /**< Bit mask for TIMER_CC1 */
+#define _TIMER_IF_CC1_DEFAULT                      0x00000000UL                     /**< Mode DEFAULT for TIMER_IF */
+#define TIMER_IF_CC1_DEFAULT                       (_TIMER_IF_CC1_DEFAULT << 5)     /**< Shifted mode DEFAULT for TIMER_IF */
+#define TIMER_IF_CC2                               (0x1UL << 6)                     /**< CC Channel 2 Interrupt Flag */
+#define _TIMER_IF_CC2_SHIFT                        6                                /**< Shift value for TIMER_CC2 */
+#define _TIMER_IF_CC2_MASK                         0x40UL                           /**< Bit mask for TIMER_CC2 */
+#define _TIMER_IF_CC2_DEFAULT                      0x00000000UL                     /**< Mode DEFAULT for TIMER_IF */
+#define TIMER_IF_CC2_DEFAULT                       (_TIMER_IF_CC2_DEFAULT << 6)     /**< Shifted mode DEFAULT for TIMER_IF */
+#define TIMER_IF_CC3                               (0x1UL << 7)                     /**< CC Channel 3 Interrupt Flag */
+#define _TIMER_IF_CC3_SHIFT                        7                                /**< Shift value for TIMER_CC3 */
+#define _TIMER_IF_CC3_MASK                         0x80UL                           /**< Bit mask for TIMER_CC3 */
+#define _TIMER_IF_CC3_DEFAULT                      0x00000000UL                     /**< Mode DEFAULT for TIMER_IF */
+#define TIMER_IF_CC3_DEFAULT                       (_TIMER_IF_CC3_DEFAULT << 7)     /**< Shifted mode DEFAULT for TIMER_IF */
+#define TIMER_IF_ICBOF0                            (0x1UL << 8)                     /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */
+#define _TIMER_IF_ICBOF0_SHIFT                     8                                /**< Shift value for TIMER_ICBOF0 */
+#define _TIMER_IF_ICBOF0_MASK                      0x100UL                          /**< Bit mask for TIMER_ICBOF0 */
+#define _TIMER_IF_ICBOF0_DEFAULT                   0x00000000UL                     /**< Mode DEFAULT for TIMER_IF */
+#define TIMER_IF_ICBOF0_DEFAULT                    (_TIMER_IF_ICBOF0_DEFAULT << 8)  /**< Shifted mode DEFAULT for TIMER_IF */
+#define TIMER_IF_ICBOF1                            (0x1UL << 9)                     /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */
+#define _TIMER_IF_ICBOF1_SHIFT                     9                                /**< Shift value for TIMER_ICBOF1 */
+#define _TIMER_IF_ICBOF1_MASK                      0x200UL                          /**< Bit mask for TIMER_ICBOF1 */
+#define _TIMER_IF_ICBOF1_DEFAULT                   0x00000000UL                     /**< Mode DEFAULT for TIMER_IF */
+#define TIMER_IF_ICBOF1_DEFAULT                    (_TIMER_IF_ICBOF1_DEFAULT << 9)  /**< Shifted mode DEFAULT for TIMER_IF */
+#define TIMER_IF_ICBOF2                            (0x1UL << 10)                    /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */
+#define _TIMER_IF_ICBOF2_SHIFT                     10                               /**< Shift value for TIMER_ICBOF2 */
+#define _TIMER_IF_ICBOF2_MASK                      0x400UL                          /**< Bit mask for TIMER_ICBOF2 */
+#define _TIMER_IF_ICBOF2_DEFAULT                   0x00000000UL                     /**< Mode DEFAULT for TIMER_IF */
+#define TIMER_IF_ICBOF2_DEFAULT                    (_TIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_IF */
+#define TIMER_IF_ICBOF3                            (0x1UL << 11)                    /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */
+#define _TIMER_IF_ICBOF3_SHIFT                     11                               /**< Shift value for TIMER_ICBOF3 */
+#define _TIMER_IF_ICBOF3_MASK                      0x800UL                          /**< Bit mask for TIMER_ICBOF3 */
+#define _TIMER_IF_ICBOF3_DEFAULT                   0x00000000UL                     /**< Mode DEFAULT for TIMER_IF */
+#define TIMER_IF_ICBOF3_DEFAULT                    (_TIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_IF */
+
+/* Bit fields for TIMER IFS */
+#define _TIMER_IFS_RESETVALUE                      0x00000000UL                      /**< Default value for TIMER_IFS */
+#define _TIMER_IFS_MASK                            0x00000FF7UL                      /**< Mask for TIMER_IFS */
+#define TIMER_IFS_OF                               (0x1UL << 0)                      /**< Set OF Interrupt Flag */
+#define _TIMER_IFS_OF_SHIFT                        0                                 /**< Shift value for TIMER_OF */
+#define _TIMER_IFS_OF_MASK                         0x1UL                             /**< Bit mask for TIMER_OF */
+#define _TIMER_IFS_OF_DEFAULT                      0x00000000UL                      /**< Mode DEFAULT for TIMER_IFS */
+#define TIMER_IFS_OF_DEFAULT                       (_TIMER_IFS_OF_DEFAULT << 0)      /**< Shifted mode DEFAULT for TIMER_IFS */
+#define TIMER_IFS_UF                               (0x1UL << 1)                      /**< Set UF Interrupt Flag */
+#define _TIMER_IFS_UF_SHIFT                        1                                 /**< Shift value for TIMER_UF */
+#define _TIMER_IFS_UF_MASK                         0x2UL                             /**< Bit mask for TIMER_UF */
+#define _TIMER_IFS_UF_DEFAULT                      0x00000000UL                      /**< Mode DEFAULT for TIMER_IFS */
+#define TIMER_IFS_UF_DEFAULT                       (_TIMER_IFS_UF_DEFAULT << 1)      /**< Shifted mode DEFAULT for TIMER_IFS */
+#define TIMER_IFS_DIRCHG                           (0x1UL << 2)                      /**< Set DIRCHG Interrupt Flag */
+#define _TIMER_IFS_DIRCHG_SHIFT                    2                                 /**< Shift value for TIMER_DIRCHG */
+#define _TIMER_IFS_DIRCHG_MASK                     0x4UL                             /**< Bit mask for TIMER_DIRCHG */
+#define _TIMER_IFS_DIRCHG_DEFAULT                  0x00000000UL                      /**< Mode DEFAULT for TIMER_IFS */
+#define TIMER_IFS_DIRCHG_DEFAULT                   (_TIMER_IFS_DIRCHG_DEFAULT << 2)  /**< Shifted mode DEFAULT for TIMER_IFS */
+#define TIMER_IFS_CC0                              (0x1UL << 4)                      /**< Set CC0 Interrupt Flag */
+#define _TIMER_IFS_CC0_SHIFT                       4                                 /**< Shift value for TIMER_CC0 */
+#define _TIMER_IFS_CC0_MASK                        0x10UL                            /**< Bit mask for TIMER_CC0 */
+#define _TIMER_IFS_CC0_DEFAULT                     0x00000000UL                      /**< Mode DEFAULT for TIMER_IFS */
+#define TIMER_IFS_CC0_DEFAULT                      (_TIMER_IFS_CC0_DEFAULT << 4)     /**< Shifted mode DEFAULT for TIMER_IFS */
+#define TIMER_IFS_CC1                              (0x1UL << 5)                      /**< Set CC1 Interrupt Flag */
+#define _TIMER_IFS_CC1_SHIFT                       5                                 /**< Shift value for TIMER_CC1 */
+#define _TIMER_IFS_CC1_MASK                        0x20UL                            /**< Bit mask for TIMER_CC1 */
+#define _TIMER_IFS_CC1_DEFAULT                     0x00000000UL                      /**< Mode DEFAULT for TIMER_IFS */
+#define TIMER_IFS_CC1_DEFAULT                      (_TIMER_IFS_CC1_DEFAULT << 5)     /**< Shifted mode DEFAULT for TIMER_IFS */
+#define TIMER_IFS_CC2                              (0x1UL << 6)                      /**< Set CC2 Interrupt Flag */
+#define _TIMER_IFS_CC2_SHIFT                       6                                 /**< Shift value for TIMER_CC2 */
+#define _TIMER_IFS_CC2_MASK                        0x40UL                            /**< Bit mask for TIMER_CC2 */
+#define _TIMER_IFS_CC2_DEFAULT                     0x00000000UL                      /**< Mode DEFAULT for TIMER_IFS */
+#define TIMER_IFS_CC2_DEFAULT                      (_TIMER_IFS_CC2_DEFAULT << 6)     /**< Shifted mode DEFAULT for TIMER_IFS */
+#define TIMER_IFS_CC3                              (0x1UL << 7)                      /**< Set CC3 Interrupt Flag */
+#define _TIMER_IFS_CC3_SHIFT                       7                                 /**< Shift value for TIMER_CC3 */
+#define _TIMER_IFS_CC3_MASK                        0x80UL                            /**< Bit mask for TIMER_CC3 */
+#define _TIMER_IFS_CC3_DEFAULT                     0x00000000UL                      /**< Mode DEFAULT for TIMER_IFS */
+#define TIMER_IFS_CC3_DEFAULT                      (_TIMER_IFS_CC3_DEFAULT << 7)     /**< Shifted mode DEFAULT for TIMER_IFS */
+#define TIMER_IFS_ICBOF0                           (0x1UL << 8)                      /**< Set ICBOF0 Interrupt Flag */
+#define _TIMER_IFS_ICBOF0_SHIFT                    8                                 /**< Shift value for TIMER_ICBOF0 */
+#define _TIMER_IFS_ICBOF0_MASK                     0x100UL                           /**< Bit mask for TIMER_ICBOF0 */
+#define _TIMER_IFS_ICBOF0_DEFAULT                  0x00000000UL                      /**< Mode DEFAULT for TIMER_IFS */
+#define TIMER_IFS_ICBOF0_DEFAULT                   (_TIMER_IFS_ICBOF0_DEFAULT << 8)  /**< Shifted mode DEFAULT for TIMER_IFS */
+#define TIMER_IFS_ICBOF1                           (0x1UL << 9)                      /**< Set ICBOF1 Interrupt Flag */
+#define _TIMER_IFS_ICBOF1_SHIFT                    9                                 /**< Shift value for TIMER_ICBOF1 */
+#define _TIMER_IFS_ICBOF1_MASK                     0x200UL                           /**< Bit mask for TIMER_ICBOF1 */
+#define _TIMER_IFS_ICBOF1_DEFAULT                  0x00000000UL                      /**< Mode DEFAULT for TIMER_IFS */
+#define TIMER_IFS_ICBOF1_DEFAULT                   (_TIMER_IFS_ICBOF1_DEFAULT << 9)  /**< Shifted mode DEFAULT for TIMER_IFS */
+#define TIMER_IFS_ICBOF2                           (0x1UL << 10)                     /**< Set ICBOF2 Interrupt Flag */
+#define _TIMER_IFS_ICBOF2_SHIFT                    10                                /**< Shift value for TIMER_ICBOF2 */
+#define _TIMER_IFS_ICBOF2_MASK                     0x400UL                           /**< Bit mask for TIMER_ICBOF2 */
+#define _TIMER_IFS_ICBOF2_DEFAULT                  0x00000000UL                      /**< Mode DEFAULT for TIMER_IFS */
+#define TIMER_IFS_ICBOF2_DEFAULT                   (_TIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_IFS */
+#define TIMER_IFS_ICBOF3                           (0x1UL << 11)                     /**< Set ICBOF3 Interrupt Flag */
+#define _TIMER_IFS_ICBOF3_SHIFT                    11                                /**< Shift value for TIMER_ICBOF3 */
+#define _TIMER_IFS_ICBOF3_MASK                     0x800UL                           /**< Bit mask for TIMER_ICBOF3 */
+#define _TIMER_IFS_ICBOF3_DEFAULT                  0x00000000UL                      /**< Mode DEFAULT for TIMER_IFS */
+#define TIMER_IFS_ICBOF3_DEFAULT                   (_TIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_IFS */
+
+/* Bit fields for TIMER IFC */
+#define _TIMER_IFC_RESETVALUE                      0x00000000UL                      /**< Default value for TIMER_IFC */
+#define _TIMER_IFC_MASK                            0x00000FF7UL                      /**< Mask for TIMER_IFC */
+#define TIMER_IFC_OF                               (0x1UL << 0)                      /**< Clear OF Interrupt Flag */
+#define _TIMER_IFC_OF_SHIFT                        0                                 /**< Shift value for TIMER_OF */
+#define _TIMER_IFC_OF_MASK                         0x1UL                             /**< Bit mask for TIMER_OF */
+#define _TIMER_IFC_OF_DEFAULT                      0x00000000UL                      /**< Mode DEFAULT for TIMER_IFC */
+#define TIMER_IFC_OF_DEFAULT                       (_TIMER_IFC_OF_DEFAULT << 0)      /**< Shifted mode DEFAULT for TIMER_IFC */
+#define TIMER_IFC_UF                               (0x1UL << 1)                      /**< Clear UF Interrupt Flag */
+#define _TIMER_IFC_UF_SHIFT                        1                                 /**< Shift value for TIMER_UF */
+#define _TIMER_IFC_UF_MASK                         0x2UL                             /**< Bit mask for TIMER_UF */
+#define _TIMER_IFC_UF_DEFAULT                      0x00000000UL                      /**< Mode DEFAULT for TIMER_IFC */
+#define TIMER_IFC_UF_DEFAULT                       (_TIMER_IFC_UF_DEFAULT << 1)      /**< Shifted mode DEFAULT for TIMER_IFC */
+#define TIMER_IFC_DIRCHG                           (0x1UL << 2)                      /**< Clear DIRCHG Interrupt Flag */
+#define _TIMER_IFC_DIRCHG_SHIFT                    2                                 /**< Shift value for TIMER_DIRCHG */
+#define _TIMER_IFC_DIRCHG_MASK                     0x4UL                             /**< Bit mask for TIMER_DIRCHG */
+#define _TIMER_IFC_DIRCHG_DEFAULT                  0x00000000UL                      /**< Mode DEFAULT for TIMER_IFC */
+#define TIMER_IFC_DIRCHG_DEFAULT                   (_TIMER_IFC_DIRCHG_DEFAULT << 2)  /**< Shifted mode DEFAULT for TIMER_IFC */
+#define TIMER_IFC_CC0                              (0x1UL << 4)                      /**< Clear CC0 Interrupt Flag */
+#define _TIMER_IFC_CC0_SHIFT                       4                                 /**< Shift value for TIMER_CC0 */
+#define _TIMER_IFC_CC0_MASK                        0x10UL                            /**< Bit mask for TIMER_CC0 */
+#define _TIMER_IFC_CC0_DEFAULT                     0x00000000UL                      /**< Mode DEFAULT for TIMER_IFC */
+#define TIMER_IFC_CC0_DEFAULT                      (_TIMER_IFC_CC0_DEFAULT << 4)     /**< Shifted mode DEFAULT for TIMER_IFC */
+#define TIMER_IFC_CC1                              (0x1UL << 5)                      /**< Clear CC1 Interrupt Flag */
+#define _TIMER_IFC_CC1_SHIFT                       5                                 /**< Shift value for TIMER_CC1 */
+#define _TIMER_IFC_CC1_MASK                        0x20UL                            /**< Bit mask for TIMER_CC1 */
+#define _TIMER_IFC_CC1_DEFAULT                     0x00000000UL                      /**< Mode DEFAULT for TIMER_IFC */
+#define TIMER_IFC_CC1_DEFAULT                      (_TIMER_IFC_CC1_DEFAULT << 5)     /**< Shifted mode DEFAULT for TIMER_IFC */
+#define TIMER_IFC_CC2                              (0x1UL << 6)                      /**< Clear CC2 Interrupt Flag */
+#define _TIMER_IFC_CC2_SHIFT                       6                                 /**< Shift value for TIMER_CC2 */
+#define _TIMER_IFC_CC2_MASK                        0x40UL                            /**< Bit mask for TIMER_CC2 */
+#define _TIMER_IFC_CC2_DEFAULT                     0x00000000UL                      /**< Mode DEFAULT for TIMER_IFC */
+#define TIMER_IFC_CC2_DEFAULT                      (_TIMER_IFC_CC2_DEFAULT << 6)     /**< Shifted mode DEFAULT for TIMER_IFC */
+#define TIMER_IFC_CC3                              (0x1UL << 7)                      /**< Clear CC3 Interrupt Flag */
+#define _TIMER_IFC_CC3_SHIFT                       7                                 /**< Shift value for TIMER_CC3 */
+#define _TIMER_IFC_CC3_MASK                        0x80UL                            /**< Bit mask for TIMER_CC3 */
+#define _TIMER_IFC_CC3_DEFAULT                     0x00000000UL                      /**< Mode DEFAULT for TIMER_IFC */
+#define TIMER_IFC_CC3_DEFAULT                      (_TIMER_IFC_CC3_DEFAULT << 7)     /**< Shifted mode DEFAULT for TIMER_IFC */
+#define TIMER_IFC_ICBOF0                           (0x1UL << 8)                      /**< Clear ICBOF0 Interrupt Flag */
+#define _TIMER_IFC_ICBOF0_SHIFT                    8                                 /**< Shift value for TIMER_ICBOF0 */
+#define _TIMER_IFC_ICBOF0_MASK                     0x100UL                           /**< Bit mask for TIMER_ICBOF0 */
+#define _TIMER_IFC_ICBOF0_DEFAULT                  0x00000000UL                      /**< Mode DEFAULT for TIMER_IFC */
+#define TIMER_IFC_ICBOF0_DEFAULT                   (_TIMER_IFC_ICBOF0_DEFAULT << 8)  /**< Shifted mode DEFAULT for TIMER_IFC */
+#define TIMER_IFC_ICBOF1                           (0x1UL << 9)                      /**< Clear ICBOF1 Interrupt Flag */
+#define _TIMER_IFC_ICBOF1_SHIFT                    9                                 /**< Shift value for TIMER_ICBOF1 */
+#define _TIMER_IFC_ICBOF1_MASK                     0x200UL                           /**< Bit mask for TIMER_ICBOF1 */
+#define _TIMER_IFC_ICBOF1_DEFAULT                  0x00000000UL                      /**< Mode DEFAULT for TIMER_IFC */
+#define TIMER_IFC_ICBOF1_DEFAULT                   (_TIMER_IFC_ICBOF1_DEFAULT << 9)  /**< Shifted mode DEFAULT for TIMER_IFC */
+#define TIMER_IFC_ICBOF2                           (0x1UL << 10)                     /**< Clear ICBOF2 Interrupt Flag */
+#define _TIMER_IFC_ICBOF2_SHIFT                    10                                /**< Shift value for TIMER_ICBOF2 */
+#define _TIMER_IFC_ICBOF2_MASK                     0x400UL                           /**< Bit mask for TIMER_ICBOF2 */
+#define _TIMER_IFC_ICBOF2_DEFAULT                  0x00000000UL                      /**< Mode DEFAULT for TIMER_IFC */
+#define TIMER_IFC_ICBOF2_DEFAULT                   (_TIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_IFC */
+#define TIMER_IFC_ICBOF3                           (0x1UL << 11)                     /**< Clear ICBOF3 Interrupt Flag */
+#define _TIMER_IFC_ICBOF3_SHIFT                    11                                /**< Shift value for TIMER_ICBOF3 */
+#define _TIMER_IFC_ICBOF3_MASK                     0x800UL                           /**< Bit mask for TIMER_ICBOF3 */
+#define _TIMER_IFC_ICBOF3_DEFAULT                  0x00000000UL                      /**< Mode DEFAULT for TIMER_IFC */
+#define TIMER_IFC_ICBOF3_DEFAULT                   (_TIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_IFC */
+
+/* Bit fields for TIMER IEN */
+#define _TIMER_IEN_RESETVALUE                      0x00000000UL                      /**< Default value for TIMER_IEN */
+#define _TIMER_IEN_MASK                            0x00000FF7UL                      /**< Mask for TIMER_IEN */
+#define TIMER_IEN_OF                               (0x1UL << 0)                      /**< OF Interrupt Enable */
+#define _TIMER_IEN_OF_SHIFT                        0                                 /**< Shift value for TIMER_OF */
+#define _TIMER_IEN_OF_MASK                         0x1UL                             /**< Bit mask for TIMER_OF */
+#define _TIMER_IEN_OF_DEFAULT                      0x00000000UL                      /**< Mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_OF_DEFAULT                       (_TIMER_IEN_OF_DEFAULT << 0)      /**< Shifted mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_UF                               (0x1UL << 1)                      /**< UF Interrupt Enable */
+#define _TIMER_IEN_UF_SHIFT                        1                                 /**< Shift value for TIMER_UF */
+#define _TIMER_IEN_UF_MASK                         0x2UL                             /**< Bit mask for TIMER_UF */
+#define _TIMER_IEN_UF_DEFAULT                      0x00000000UL                      /**< Mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_UF_DEFAULT                       (_TIMER_IEN_UF_DEFAULT << 1)      /**< Shifted mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_DIRCHG                           (0x1UL << 2)                      /**< DIRCHG Interrupt Enable */
+#define _TIMER_IEN_DIRCHG_SHIFT                    2                                 /**< Shift value for TIMER_DIRCHG */
+#define _TIMER_IEN_DIRCHG_MASK                     0x4UL                             /**< Bit mask for TIMER_DIRCHG */
+#define _TIMER_IEN_DIRCHG_DEFAULT                  0x00000000UL                      /**< Mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_DIRCHG_DEFAULT                   (_TIMER_IEN_DIRCHG_DEFAULT << 2)  /**< Shifted mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_CC0                              (0x1UL << 4)                      /**< CC0 Interrupt Enable */
+#define _TIMER_IEN_CC0_SHIFT                       4                                 /**< Shift value for TIMER_CC0 */
+#define _TIMER_IEN_CC0_MASK                        0x10UL                            /**< Bit mask for TIMER_CC0 */
+#define _TIMER_IEN_CC0_DEFAULT                     0x00000000UL                      /**< Mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_CC0_DEFAULT                      (_TIMER_IEN_CC0_DEFAULT << 4)     /**< Shifted mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_CC1                              (0x1UL << 5)                      /**< CC1 Interrupt Enable */
+#define _TIMER_IEN_CC1_SHIFT                       5                                 /**< Shift value for TIMER_CC1 */
+#define _TIMER_IEN_CC1_MASK                        0x20UL                            /**< Bit mask for TIMER_CC1 */
+#define _TIMER_IEN_CC1_DEFAULT                     0x00000000UL                      /**< Mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_CC1_DEFAULT                      (_TIMER_IEN_CC1_DEFAULT << 5)     /**< Shifted mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_CC2                              (0x1UL << 6)                      /**< CC2 Interrupt Enable */
+#define _TIMER_IEN_CC2_SHIFT                       6                                 /**< Shift value for TIMER_CC2 */
+#define _TIMER_IEN_CC2_MASK                        0x40UL                            /**< Bit mask for TIMER_CC2 */
+#define _TIMER_IEN_CC2_DEFAULT                     0x00000000UL                      /**< Mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_CC2_DEFAULT                      (_TIMER_IEN_CC2_DEFAULT << 6)     /**< Shifted mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_CC3                              (0x1UL << 7)                      /**< CC3 Interrupt Enable */
+#define _TIMER_IEN_CC3_SHIFT                       7                                 /**< Shift value for TIMER_CC3 */
+#define _TIMER_IEN_CC3_MASK                        0x80UL                            /**< Bit mask for TIMER_CC3 */
+#define _TIMER_IEN_CC3_DEFAULT                     0x00000000UL                      /**< Mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_CC3_DEFAULT                      (_TIMER_IEN_CC3_DEFAULT << 7)     /**< Shifted mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_ICBOF0                           (0x1UL << 8)                      /**< ICBOF0 Interrupt Enable */
+#define _TIMER_IEN_ICBOF0_SHIFT                    8                                 /**< Shift value for TIMER_ICBOF0 */
+#define _TIMER_IEN_ICBOF0_MASK                     0x100UL                           /**< Bit mask for TIMER_ICBOF0 */
+#define _TIMER_IEN_ICBOF0_DEFAULT                  0x00000000UL                      /**< Mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_ICBOF0_DEFAULT                   (_TIMER_IEN_ICBOF0_DEFAULT << 8)  /**< Shifted mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_ICBOF1                           (0x1UL << 9)                      /**< ICBOF1 Interrupt Enable */
+#define _TIMER_IEN_ICBOF1_SHIFT                    9                                 /**< Shift value for TIMER_ICBOF1 */
+#define _TIMER_IEN_ICBOF1_MASK                     0x200UL                           /**< Bit mask for TIMER_ICBOF1 */
+#define _TIMER_IEN_ICBOF1_DEFAULT                  0x00000000UL                      /**< Mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_ICBOF1_DEFAULT                   (_TIMER_IEN_ICBOF1_DEFAULT << 9)  /**< Shifted mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_ICBOF2                           (0x1UL << 10)                     /**< ICBOF2 Interrupt Enable */
+#define _TIMER_IEN_ICBOF2_SHIFT                    10                                /**< Shift value for TIMER_ICBOF2 */
+#define _TIMER_IEN_ICBOF2_MASK                     0x400UL                           /**< Bit mask for TIMER_ICBOF2 */
+#define _TIMER_IEN_ICBOF2_DEFAULT                  0x00000000UL                      /**< Mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_ICBOF2_DEFAULT                   (_TIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_ICBOF3                           (0x1UL << 11)                     /**< ICBOF3 Interrupt Enable */
+#define _TIMER_IEN_ICBOF3_SHIFT                    11                                /**< Shift value for TIMER_ICBOF3 */
+#define _TIMER_IEN_ICBOF3_MASK                     0x800UL                           /**< Bit mask for TIMER_ICBOF3 */
+#define _TIMER_IEN_ICBOF3_DEFAULT                  0x00000000UL                      /**< Mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_ICBOF3_DEFAULT                   (_TIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_IEN */
+
+/* Bit fields for TIMER TOP */
+#define _TIMER_TOP_RESETVALUE                      0x0000FFFFUL                  /**< Default value for TIMER_TOP */
+#define _TIMER_TOP_MASK                            0x0000FFFFUL                  /**< Mask for TIMER_TOP */
+#define _TIMER_TOP_TOP_SHIFT                       0                             /**< Shift value for TIMER_TOP */
+#define _TIMER_TOP_TOP_MASK                        0xFFFFUL                      /**< Bit mask for TIMER_TOP */
+#define _TIMER_TOP_TOP_DEFAULT                     0x0000FFFFUL                  /**< Mode DEFAULT for TIMER_TOP */
+#define TIMER_TOP_TOP_DEFAULT                      (_TIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_TOP */
+
+/* Bit fields for TIMER TOPB */
+#define _TIMER_TOPB_RESETVALUE                     0x00000000UL                    /**< Default value for TIMER_TOPB */
+#define _TIMER_TOPB_MASK                           0x0000FFFFUL                    /**< Mask for TIMER_TOPB */
+#define _TIMER_TOPB_TOPB_SHIFT                     0                               /**< Shift value for TIMER_TOPB */
+#define _TIMER_TOPB_TOPB_MASK                      0xFFFFUL                        /**< Bit mask for TIMER_TOPB */
+#define _TIMER_TOPB_TOPB_DEFAULT                   0x00000000UL                    /**< Mode DEFAULT for TIMER_TOPB */
+#define TIMER_TOPB_TOPB_DEFAULT                    (_TIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_TOPB */
+
+/* Bit fields for TIMER CNT */
+#define _TIMER_CNT_RESETVALUE                      0x00000000UL                  /**< Default value for TIMER_CNT */
+#define _TIMER_CNT_MASK                            0x0000FFFFUL                  /**< Mask for TIMER_CNT */
+#define _TIMER_CNT_CNT_SHIFT                       0                             /**< Shift value for TIMER_CNT */
+#define _TIMER_CNT_CNT_MASK                        0xFFFFUL                      /**< Bit mask for TIMER_CNT */
+#define _TIMER_CNT_CNT_DEFAULT                     0x00000000UL                  /**< Mode DEFAULT for TIMER_CNT */
+#define TIMER_CNT_CNT_DEFAULT                      (_TIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CNT */
+
+/* Bit fields for TIMER LOCK */
+#define _TIMER_LOCK_RESETVALUE                     0x00000000UL                             /**< Default value for TIMER_LOCK */
+#define _TIMER_LOCK_MASK                           0x0000FFFFUL                             /**< Mask for TIMER_LOCK */
+#define _TIMER_LOCK_TIMERLOCKKEY_SHIFT             0                                        /**< Shift value for TIMER_TIMERLOCKKEY */
+#define _TIMER_LOCK_TIMERLOCKKEY_MASK              0xFFFFUL                                 /**< Bit mask for TIMER_TIMERLOCKKEY */
+#define _TIMER_LOCK_TIMERLOCKKEY_DEFAULT           0x00000000UL                             /**< Mode DEFAULT for TIMER_LOCK */
+#define _TIMER_LOCK_TIMERLOCKKEY_LOCK              0x00000000UL                             /**< Mode LOCK for TIMER_LOCK */
+#define _TIMER_LOCK_TIMERLOCKKEY_UNLOCKED          0x00000000UL                             /**< Mode UNLOCKED for TIMER_LOCK */
+#define _TIMER_LOCK_TIMERLOCKKEY_LOCKED            0x00000001UL                             /**< Mode LOCKED for TIMER_LOCK */
+#define _TIMER_LOCK_TIMERLOCKKEY_UNLOCK            0x0000CE80UL                             /**< Mode UNLOCK for TIMER_LOCK */
+#define TIMER_LOCK_TIMERLOCKKEY_DEFAULT            (_TIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0)  /**< Shifted mode DEFAULT for TIMER_LOCK */
+#define TIMER_LOCK_TIMERLOCKKEY_LOCK               (_TIMER_LOCK_TIMERLOCKKEY_LOCK << 0)     /**< Shifted mode LOCK for TIMER_LOCK */
+#define TIMER_LOCK_TIMERLOCKKEY_UNLOCKED           (_TIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for TIMER_LOCK */
+#define TIMER_LOCK_TIMERLOCKKEY_LOCKED             (_TIMER_LOCK_TIMERLOCKKEY_LOCKED << 0)   /**< Shifted mode LOCKED for TIMER_LOCK */
+#define TIMER_LOCK_TIMERLOCKKEY_UNLOCK             (_TIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0)   /**< Shifted mode UNLOCK for TIMER_LOCK */
+
+/* Bit fields for TIMER ROUTEPEN */
+#define _TIMER_ROUTEPEN_RESETVALUE                 0x00000000UL                             /**< Default value for TIMER_ROUTEPEN */
+#define _TIMER_ROUTEPEN_MASK                       0x0000070FUL                             /**< Mask for TIMER_ROUTEPEN */
+#define TIMER_ROUTEPEN_CC0PEN                      (0x1UL << 0)                             /**< CC Channel 0 Pin Enable */
+#define _TIMER_ROUTEPEN_CC0PEN_SHIFT               0                                        /**< Shift value for TIMER_CC0PEN */
+#define _TIMER_ROUTEPEN_CC0PEN_MASK                0x1UL                                    /**< Bit mask for TIMER_CC0PEN */
+#define _TIMER_ROUTEPEN_CC0PEN_DEFAULT             0x00000000UL                             /**< Mode DEFAULT for TIMER_ROUTEPEN */
+#define TIMER_ROUTEPEN_CC0PEN_DEFAULT              (_TIMER_ROUTEPEN_CC0PEN_DEFAULT << 0)    /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */
+#define TIMER_ROUTEPEN_CC1PEN                      (0x1UL << 1)                             /**< CC Channel 1 Pin Enable */
+#define _TIMER_ROUTEPEN_CC1PEN_SHIFT               1                                        /**< Shift value for TIMER_CC1PEN */
+#define _TIMER_ROUTEPEN_CC1PEN_MASK                0x2UL                                    /**< Bit mask for TIMER_CC1PEN */
+#define _TIMER_ROUTEPEN_CC1PEN_DEFAULT             0x00000000UL                             /**< Mode DEFAULT for TIMER_ROUTEPEN */
+#define TIMER_ROUTEPEN_CC1PEN_DEFAULT              (_TIMER_ROUTEPEN_CC1PEN_DEFAULT << 1)    /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */
+#define TIMER_ROUTEPEN_CC2PEN                      (0x1UL << 2)                             /**< CC Channel 2 Pin Enable */
+#define _TIMER_ROUTEPEN_CC2PEN_SHIFT               2                                        /**< Shift value for TIMER_CC2PEN */
+#define _TIMER_ROUTEPEN_CC2PEN_MASK                0x4UL                                    /**< Bit mask for TIMER_CC2PEN */
+#define _TIMER_ROUTEPEN_CC2PEN_DEFAULT             0x00000000UL                             /**< Mode DEFAULT for TIMER_ROUTEPEN */
+#define TIMER_ROUTEPEN_CC2PEN_DEFAULT              (_TIMER_ROUTEPEN_CC2PEN_DEFAULT << 2)    /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */
+#define TIMER_ROUTEPEN_CC3PEN                      (0x1UL << 3)                             /**< CC Channel 3 Pin Enable */
+#define _TIMER_ROUTEPEN_CC3PEN_SHIFT               3                                        /**< Shift value for TIMER_CC3PEN */
+#define _TIMER_ROUTEPEN_CC3PEN_MASK                0x8UL                                    /**< Bit mask for TIMER_CC3PEN */
+#define _TIMER_ROUTEPEN_CC3PEN_DEFAULT             0x00000000UL                             /**< Mode DEFAULT for TIMER_ROUTEPEN */
+#define TIMER_ROUTEPEN_CC3PEN_DEFAULT              (_TIMER_ROUTEPEN_CC3PEN_DEFAULT << 3)    /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */
+#define TIMER_ROUTEPEN_CDTI0PEN                    (0x1UL << 8)                             /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */
+#define _TIMER_ROUTEPEN_CDTI0PEN_SHIFT             8                                        /**< Shift value for TIMER_CDTI0PEN */
+#define _TIMER_ROUTEPEN_CDTI0PEN_MASK              0x100UL                                  /**< Bit mask for TIMER_CDTI0PEN */
+#define _TIMER_ROUTEPEN_CDTI0PEN_DEFAULT           0x00000000UL                             /**< Mode DEFAULT for TIMER_ROUTEPEN */
+#define TIMER_ROUTEPEN_CDTI0PEN_DEFAULT            (_TIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8)  /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */
+#define TIMER_ROUTEPEN_CDTI1PEN                    (0x1UL << 9)                             /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */
+#define _TIMER_ROUTEPEN_CDTI1PEN_SHIFT             9                                        /**< Shift value for TIMER_CDTI1PEN */
+#define _TIMER_ROUTEPEN_CDTI1PEN_MASK              0x200UL                                  /**< Bit mask for TIMER_CDTI1PEN */
+#define _TIMER_ROUTEPEN_CDTI1PEN_DEFAULT           0x00000000UL                             /**< Mode DEFAULT for TIMER_ROUTEPEN */
+#define TIMER_ROUTEPEN_CDTI1PEN_DEFAULT            (_TIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9)  /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */
+#define TIMER_ROUTEPEN_CDTI2PEN                    (0x1UL << 10)                            /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */
+#define _TIMER_ROUTEPEN_CDTI2PEN_SHIFT             10                                       /**< Shift value for TIMER_CDTI2PEN */
+#define _TIMER_ROUTEPEN_CDTI2PEN_MASK              0x400UL                                  /**< Bit mask for TIMER_CDTI2PEN */
+#define _TIMER_ROUTEPEN_CDTI2PEN_DEFAULT           0x00000000UL                             /**< Mode DEFAULT for TIMER_ROUTEPEN */
+#define TIMER_ROUTEPEN_CDTI2PEN_DEFAULT            (_TIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */
+
+/* Bit fields for TIMER ROUTELOC0 */
+#define _TIMER_ROUTELOC0_RESETVALUE                0x00000000UL                            /**< Default value for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_MASK                      0x1F1F1F1FUL                            /**< Mask for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC0LOC_SHIFT              0                                       /**< Shift value for TIMER_CC0LOC */
+#define _TIMER_ROUTELOC0_CC0LOC_MASK               0x1FUL                                  /**< Bit mask for TIMER_CC0LOC */
+#define _TIMER_ROUTELOC0_CC0LOC_LOC0               0x00000000UL                            /**< Mode LOC0 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC0LOC_DEFAULT            0x00000000UL                            /**< Mode DEFAULT for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC0LOC_LOC1               0x00000001UL                            /**< Mode LOC1 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC0LOC_LOC2               0x00000002UL                            /**< Mode LOC2 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC0LOC_LOC3               0x00000003UL                            /**< Mode LOC3 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC0LOC_LOC4               0x00000004UL                            /**< Mode LOC4 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC0LOC_LOC5               0x00000005UL                            /**< Mode LOC5 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC0LOC_LOC6               0x00000006UL                            /**< Mode LOC6 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC0LOC_LOC7               0x00000007UL                            /**< Mode LOC7 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC0LOC_LOC8               0x00000008UL                            /**< Mode LOC8 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC0LOC_LOC9               0x00000009UL                            /**< Mode LOC9 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC0LOC_LOC10              0x0000000AUL                            /**< Mode LOC10 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC0LOC_LOC11              0x0000000BUL                            /**< Mode LOC11 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC0LOC_LOC12              0x0000000CUL                            /**< Mode LOC12 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC0LOC_LOC13              0x0000000DUL                            /**< Mode LOC13 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC0LOC_LOC14              0x0000000EUL                            /**< Mode LOC14 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC0LOC_LOC15              0x0000000FUL                            /**< Mode LOC15 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC0LOC_LOC16              0x00000010UL                            /**< Mode LOC16 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC0LOC_LOC17              0x00000011UL                            /**< Mode LOC17 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC0LOC_LOC18              0x00000012UL                            /**< Mode LOC18 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC0LOC_LOC19              0x00000013UL                            /**< Mode LOC19 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC0LOC_LOC20              0x00000014UL                            /**< Mode LOC20 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC0LOC_LOC21              0x00000015UL                            /**< Mode LOC21 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC0LOC_LOC22              0x00000016UL                            /**< Mode LOC22 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC0LOC_LOC23              0x00000017UL                            /**< Mode LOC23 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC0LOC_LOC24              0x00000018UL                            /**< Mode LOC24 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC0LOC_LOC25              0x00000019UL                            /**< Mode LOC25 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC0LOC_LOC26              0x0000001AUL                            /**< Mode LOC26 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC0LOC_LOC27              0x0000001BUL                            /**< Mode LOC27 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC0LOC_LOC28              0x0000001CUL                            /**< Mode LOC28 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC0LOC_LOC29              0x0000001DUL                            /**< Mode LOC29 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC0LOC_LOC30              0x0000001EUL                            /**< Mode LOC30 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC0LOC_LOC31              0x0000001FUL                            /**< Mode LOC31 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC0LOC_LOC0                (_TIMER_ROUTELOC0_CC0LOC_LOC0 << 0)     /**< Shifted mode LOC0 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC0LOC_DEFAULT             (_TIMER_ROUTELOC0_CC0LOC_DEFAULT << 0)  /**< Shifted mode DEFAULT for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC0LOC_LOC1                (_TIMER_ROUTELOC0_CC0LOC_LOC1 << 0)     /**< Shifted mode LOC1 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC0LOC_LOC2                (_TIMER_ROUTELOC0_CC0LOC_LOC2 << 0)     /**< Shifted mode LOC2 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC0LOC_LOC3                (_TIMER_ROUTELOC0_CC0LOC_LOC3 << 0)     /**< Shifted mode LOC3 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC0LOC_LOC4                (_TIMER_ROUTELOC0_CC0LOC_LOC4 << 0)     /**< Shifted mode LOC4 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC0LOC_LOC5                (_TIMER_ROUTELOC0_CC0LOC_LOC5 << 0)     /**< Shifted mode LOC5 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC0LOC_LOC6                (_TIMER_ROUTELOC0_CC0LOC_LOC6 << 0)     /**< Shifted mode LOC6 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC0LOC_LOC7                (_TIMER_ROUTELOC0_CC0LOC_LOC7 << 0)     /**< Shifted mode LOC7 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC0LOC_LOC8                (_TIMER_ROUTELOC0_CC0LOC_LOC8 << 0)     /**< Shifted mode LOC8 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC0LOC_LOC9                (_TIMER_ROUTELOC0_CC0LOC_LOC9 << 0)     /**< Shifted mode LOC9 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC0LOC_LOC10               (_TIMER_ROUTELOC0_CC0LOC_LOC10 << 0)    /**< Shifted mode LOC10 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC0LOC_LOC11               (_TIMER_ROUTELOC0_CC0LOC_LOC11 << 0)    /**< Shifted mode LOC11 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC0LOC_LOC12               (_TIMER_ROUTELOC0_CC0LOC_LOC12 << 0)    /**< Shifted mode LOC12 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC0LOC_LOC13               (_TIMER_ROUTELOC0_CC0LOC_LOC13 << 0)    /**< Shifted mode LOC13 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC0LOC_LOC14               (_TIMER_ROUTELOC0_CC0LOC_LOC14 << 0)    /**< Shifted mode LOC14 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC0LOC_LOC15               (_TIMER_ROUTELOC0_CC0LOC_LOC15 << 0)    /**< Shifted mode LOC15 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC0LOC_LOC16               (_TIMER_ROUTELOC0_CC0LOC_LOC16 << 0)    /**< Shifted mode LOC16 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC0LOC_LOC17               (_TIMER_ROUTELOC0_CC0LOC_LOC17 << 0)    /**< Shifted mode LOC17 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC0LOC_LOC18               (_TIMER_ROUTELOC0_CC0LOC_LOC18 << 0)    /**< Shifted mode LOC18 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC0LOC_LOC19               (_TIMER_ROUTELOC0_CC0LOC_LOC19 << 0)    /**< Shifted mode LOC19 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC0LOC_LOC20               (_TIMER_ROUTELOC0_CC0LOC_LOC20 << 0)    /**< Shifted mode LOC20 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC0LOC_LOC21               (_TIMER_ROUTELOC0_CC0LOC_LOC21 << 0)    /**< Shifted mode LOC21 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC0LOC_LOC22               (_TIMER_ROUTELOC0_CC0LOC_LOC22 << 0)    /**< Shifted mode LOC22 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC0LOC_LOC23               (_TIMER_ROUTELOC0_CC0LOC_LOC23 << 0)    /**< Shifted mode LOC23 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC0LOC_LOC24               (_TIMER_ROUTELOC0_CC0LOC_LOC24 << 0)    /**< Shifted mode LOC24 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC0LOC_LOC25               (_TIMER_ROUTELOC0_CC0LOC_LOC25 << 0)    /**< Shifted mode LOC25 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC0LOC_LOC26               (_TIMER_ROUTELOC0_CC0LOC_LOC26 << 0)    /**< Shifted mode LOC26 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC0LOC_LOC27               (_TIMER_ROUTELOC0_CC0LOC_LOC27 << 0)    /**< Shifted mode LOC27 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC0LOC_LOC28               (_TIMER_ROUTELOC0_CC0LOC_LOC28 << 0)    /**< Shifted mode LOC28 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC0LOC_LOC29               (_TIMER_ROUTELOC0_CC0LOC_LOC29 << 0)    /**< Shifted mode LOC29 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC0LOC_LOC30               (_TIMER_ROUTELOC0_CC0LOC_LOC30 << 0)    /**< Shifted mode LOC30 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC0LOC_LOC31               (_TIMER_ROUTELOC0_CC0LOC_LOC31 << 0)    /**< Shifted mode LOC31 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC1LOC_SHIFT              8                                       /**< Shift value for TIMER_CC1LOC */
+#define _TIMER_ROUTELOC0_CC1LOC_MASK               0x1F00UL                                /**< Bit mask for TIMER_CC1LOC */
+#define _TIMER_ROUTELOC0_CC1LOC_LOC0               0x00000000UL                            /**< Mode LOC0 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC1LOC_DEFAULT            0x00000000UL                            /**< Mode DEFAULT for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC1LOC_LOC1               0x00000001UL                            /**< Mode LOC1 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC1LOC_LOC2               0x00000002UL                            /**< Mode LOC2 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC1LOC_LOC3               0x00000003UL                            /**< Mode LOC3 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC1LOC_LOC4               0x00000004UL                            /**< Mode LOC4 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC1LOC_LOC5               0x00000005UL                            /**< Mode LOC5 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC1LOC_LOC6               0x00000006UL                            /**< Mode LOC6 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC1LOC_LOC7               0x00000007UL                            /**< Mode LOC7 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC1LOC_LOC8               0x00000008UL                            /**< Mode LOC8 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC1LOC_LOC9               0x00000009UL                            /**< Mode LOC9 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC1LOC_LOC10              0x0000000AUL                            /**< Mode LOC10 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC1LOC_LOC11              0x0000000BUL                            /**< Mode LOC11 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC1LOC_LOC12              0x0000000CUL                            /**< Mode LOC12 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC1LOC_LOC13              0x0000000DUL                            /**< Mode LOC13 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC1LOC_LOC14              0x0000000EUL                            /**< Mode LOC14 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC1LOC_LOC15              0x0000000FUL                            /**< Mode LOC15 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC1LOC_LOC16              0x00000010UL                            /**< Mode LOC16 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC1LOC_LOC17              0x00000011UL                            /**< Mode LOC17 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC1LOC_LOC18              0x00000012UL                            /**< Mode LOC18 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC1LOC_LOC19              0x00000013UL                            /**< Mode LOC19 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC1LOC_LOC20              0x00000014UL                            /**< Mode LOC20 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC1LOC_LOC21              0x00000015UL                            /**< Mode LOC21 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC1LOC_LOC22              0x00000016UL                            /**< Mode LOC22 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC1LOC_LOC23              0x00000017UL                            /**< Mode LOC23 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC1LOC_LOC24              0x00000018UL                            /**< Mode LOC24 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC1LOC_LOC25              0x00000019UL                            /**< Mode LOC25 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC1LOC_LOC26              0x0000001AUL                            /**< Mode LOC26 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC1LOC_LOC27              0x0000001BUL                            /**< Mode LOC27 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC1LOC_LOC28              0x0000001CUL                            /**< Mode LOC28 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC1LOC_LOC29              0x0000001DUL                            /**< Mode LOC29 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC1LOC_LOC30              0x0000001EUL                            /**< Mode LOC30 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC1LOC_LOC31              0x0000001FUL                            /**< Mode LOC31 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC1LOC_LOC0                (_TIMER_ROUTELOC0_CC1LOC_LOC0 << 8)     /**< Shifted mode LOC0 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC1LOC_DEFAULT             (_TIMER_ROUTELOC0_CC1LOC_DEFAULT << 8)  /**< Shifted mode DEFAULT for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC1LOC_LOC1                (_TIMER_ROUTELOC0_CC1LOC_LOC1 << 8)     /**< Shifted mode LOC1 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC1LOC_LOC2                (_TIMER_ROUTELOC0_CC1LOC_LOC2 << 8)     /**< Shifted mode LOC2 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC1LOC_LOC3                (_TIMER_ROUTELOC0_CC1LOC_LOC3 << 8)     /**< Shifted mode LOC3 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC1LOC_LOC4                (_TIMER_ROUTELOC0_CC1LOC_LOC4 << 8)     /**< Shifted mode LOC4 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC1LOC_LOC5                (_TIMER_ROUTELOC0_CC1LOC_LOC5 << 8)     /**< Shifted mode LOC5 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC1LOC_LOC6                (_TIMER_ROUTELOC0_CC1LOC_LOC6 << 8)     /**< Shifted mode LOC6 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC1LOC_LOC7                (_TIMER_ROUTELOC0_CC1LOC_LOC7 << 8)     /**< Shifted mode LOC7 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC1LOC_LOC8                (_TIMER_ROUTELOC0_CC1LOC_LOC8 << 8)     /**< Shifted mode LOC8 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC1LOC_LOC9                (_TIMER_ROUTELOC0_CC1LOC_LOC9 << 8)     /**< Shifted mode LOC9 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC1LOC_LOC10               (_TIMER_ROUTELOC0_CC1LOC_LOC10 << 8)    /**< Shifted mode LOC10 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC1LOC_LOC11               (_TIMER_ROUTELOC0_CC1LOC_LOC11 << 8)    /**< Shifted mode LOC11 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC1LOC_LOC12               (_TIMER_ROUTELOC0_CC1LOC_LOC12 << 8)    /**< Shifted mode LOC12 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC1LOC_LOC13               (_TIMER_ROUTELOC0_CC1LOC_LOC13 << 8)    /**< Shifted mode LOC13 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC1LOC_LOC14               (_TIMER_ROUTELOC0_CC1LOC_LOC14 << 8)    /**< Shifted mode LOC14 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC1LOC_LOC15               (_TIMER_ROUTELOC0_CC1LOC_LOC15 << 8)    /**< Shifted mode LOC15 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC1LOC_LOC16               (_TIMER_ROUTELOC0_CC1LOC_LOC16 << 8)    /**< Shifted mode LOC16 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC1LOC_LOC17               (_TIMER_ROUTELOC0_CC1LOC_LOC17 << 8)    /**< Shifted mode LOC17 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC1LOC_LOC18               (_TIMER_ROUTELOC0_CC1LOC_LOC18 << 8)    /**< Shifted mode LOC18 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC1LOC_LOC19               (_TIMER_ROUTELOC0_CC1LOC_LOC19 << 8)    /**< Shifted mode LOC19 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC1LOC_LOC20               (_TIMER_ROUTELOC0_CC1LOC_LOC20 << 8)    /**< Shifted mode LOC20 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC1LOC_LOC21               (_TIMER_ROUTELOC0_CC1LOC_LOC21 << 8)    /**< Shifted mode LOC21 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC1LOC_LOC22               (_TIMER_ROUTELOC0_CC1LOC_LOC22 << 8)    /**< Shifted mode LOC22 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC1LOC_LOC23               (_TIMER_ROUTELOC0_CC1LOC_LOC23 << 8)    /**< Shifted mode LOC23 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC1LOC_LOC24               (_TIMER_ROUTELOC0_CC1LOC_LOC24 << 8)    /**< Shifted mode LOC24 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC1LOC_LOC25               (_TIMER_ROUTELOC0_CC1LOC_LOC25 << 8)    /**< Shifted mode LOC25 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC1LOC_LOC26               (_TIMER_ROUTELOC0_CC1LOC_LOC26 << 8)    /**< Shifted mode LOC26 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC1LOC_LOC27               (_TIMER_ROUTELOC0_CC1LOC_LOC27 << 8)    /**< Shifted mode LOC27 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC1LOC_LOC28               (_TIMER_ROUTELOC0_CC1LOC_LOC28 << 8)    /**< Shifted mode LOC28 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC1LOC_LOC29               (_TIMER_ROUTELOC0_CC1LOC_LOC29 << 8)    /**< Shifted mode LOC29 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC1LOC_LOC30               (_TIMER_ROUTELOC0_CC1LOC_LOC30 << 8)    /**< Shifted mode LOC30 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC1LOC_LOC31               (_TIMER_ROUTELOC0_CC1LOC_LOC31 << 8)    /**< Shifted mode LOC31 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC2LOC_SHIFT              16                                      /**< Shift value for TIMER_CC2LOC */
+#define _TIMER_ROUTELOC0_CC2LOC_MASK               0x1F0000UL                              /**< Bit mask for TIMER_CC2LOC */
+#define _TIMER_ROUTELOC0_CC2LOC_LOC0               0x00000000UL                            /**< Mode LOC0 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC2LOC_DEFAULT            0x00000000UL                            /**< Mode DEFAULT for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC2LOC_LOC1               0x00000001UL                            /**< Mode LOC1 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC2LOC_LOC2               0x00000002UL                            /**< Mode LOC2 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC2LOC_LOC3               0x00000003UL                            /**< Mode LOC3 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC2LOC_LOC4               0x00000004UL                            /**< Mode LOC4 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC2LOC_LOC5               0x00000005UL                            /**< Mode LOC5 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC2LOC_LOC6               0x00000006UL                            /**< Mode LOC6 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC2LOC_LOC7               0x00000007UL                            /**< Mode LOC7 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC2LOC_LOC8               0x00000008UL                            /**< Mode LOC8 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC2LOC_LOC9               0x00000009UL                            /**< Mode LOC9 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC2LOC_LOC10              0x0000000AUL                            /**< Mode LOC10 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC2LOC_LOC11              0x0000000BUL                            /**< Mode LOC11 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC2LOC_LOC12              0x0000000CUL                            /**< Mode LOC12 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC2LOC_LOC13              0x0000000DUL                            /**< Mode LOC13 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC2LOC_LOC14              0x0000000EUL                            /**< Mode LOC14 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC2LOC_LOC15              0x0000000FUL                            /**< Mode LOC15 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC2LOC_LOC16              0x00000010UL                            /**< Mode LOC16 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC2LOC_LOC17              0x00000011UL                            /**< Mode LOC17 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC2LOC_LOC18              0x00000012UL                            /**< Mode LOC18 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC2LOC_LOC19              0x00000013UL                            /**< Mode LOC19 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC2LOC_LOC20              0x00000014UL                            /**< Mode LOC20 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC2LOC_LOC21              0x00000015UL                            /**< Mode LOC21 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC2LOC_LOC22              0x00000016UL                            /**< Mode LOC22 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC2LOC_LOC23              0x00000017UL                            /**< Mode LOC23 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC2LOC_LOC24              0x00000018UL                            /**< Mode LOC24 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC2LOC_LOC25              0x00000019UL                            /**< Mode LOC25 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC2LOC_LOC26              0x0000001AUL                            /**< Mode LOC26 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC2LOC_LOC27              0x0000001BUL                            /**< Mode LOC27 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC2LOC_LOC28              0x0000001CUL                            /**< Mode LOC28 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC2LOC_LOC29              0x0000001DUL                            /**< Mode LOC29 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC2LOC_LOC30              0x0000001EUL                            /**< Mode LOC30 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC2LOC_LOC31              0x0000001FUL                            /**< Mode LOC31 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC2LOC_LOC0                (_TIMER_ROUTELOC0_CC2LOC_LOC0 << 16)    /**< Shifted mode LOC0 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC2LOC_DEFAULT             (_TIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC2LOC_LOC1                (_TIMER_ROUTELOC0_CC2LOC_LOC1 << 16)    /**< Shifted mode LOC1 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC2LOC_LOC2                (_TIMER_ROUTELOC0_CC2LOC_LOC2 << 16)    /**< Shifted mode LOC2 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC2LOC_LOC3                (_TIMER_ROUTELOC0_CC2LOC_LOC3 << 16)    /**< Shifted mode LOC3 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC2LOC_LOC4                (_TIMER_ROUTELOC0_CC2LOC_LOC4 << 16)    /**< Shifted mode LOC4 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC2LOC_LOC5                (_TIMER_ROUTELOC0_CC2LOC_LOC5 << 16)    /**< Shifted mode LOC5 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC2LOC_LOC6                (_TIMER_ROUTELOC0_CC2LOC_LOC6 << 16)    /**< Shifted mode LOC6 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC2LOC_LOC7                (_TIMER_ROUTELOC0_CC2LOC_LOC7 << 16)    /**< Shifted mode LOC7 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC2LOC_LOC8                (_TIMER_ROUTELOC0_CC2LOC_LOC8 << 16)    /**< Shifted mode LOC8 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC2LOC_LOC9                (_TIMER_ROUTELOC0_CC2LOC_LOC9 << 16)    /**< Shifted mode LOC9 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC2LOC_LOC10               (_TIMER_ROUTELOC0_CC2LOC_LOC10 << 16)   /**< Shifted mode LOC10 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC2LOC_LOC11               (_TIMER_ROUTELOC0_CC2LOC_LOC11 << 16)   /**< Shifted mode LOC11 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC2LOC_LOC12               (_TIMER_ROUTELOC0_CC2LOC_LOC12 << 16)   /**< Shifted mode LOC12 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC2LOC_LOC13               (_TIMER_ROUTELOC0_CC2LOC_LOC13 << 16)   /**< Shifted mode LOC13 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC2LOC_LOC14               (_TIMER_ROUTELOC0_CC2LOC_LOC14 << 16)   /**< Shifted mode LOC14 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC2LOC_LOC15               (_TIMER_ROUTELOC0_CC2LOC_LOC15 << 16)   /**< Shifted mode LOC15 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC2LOC_LOC16               (_TIMER_ROUTELOC0_CC2LOC_LOC16 << 16)   /**< Shifted mode LOC16 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC2LOC_LOC17               (_TIMER_ROUTELOC0_CC2LOC_LOC17 << 16)   /**< Shifted mode LOC17 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC2LOC_LOC18               (_TIMER_ROUTELOC0_CC2LOC_LOC18 << 16)   /**< Shifted mode LOC18 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC2LOC_LOC19               (_TIMER_ROUTELOC0_CC2LOC_LOC19 << 16)   /**< Shifted mode LOC19 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC2LOC_LOC20               (_TIMER_ROUTELOC0_CC2LOC_LOC20 << 16)   /**< Shifted mode LOC20 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC2LOC_LOC21               (_TIMER_ROUTELOC0_CC2LOC_LOC21 << 16)   /**< Shifted mode LOC21 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC2LOC_LOC22               (_TIMER_ROUTELOC0_CC2LOC_LOC22 << 16)   /**< Shifted mode LOC22 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC2LOC_LOC23               (_TIMER_ROUTELOC0_CC2LOC_LOC23 << 16)   /**< Shifted mode LOC23 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC2LOC_LOC24               (_TIMER_ROUTELOC0_CC2LOC_LOC24 << 16)   /**< Shifted mode LOC24 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC2LOC_LOC25               (_TIMER_ROUTELOC0_CC2LOC_LOC25 << 16)   /**< Shifted mode LOC25 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC2LOC_LOC26               (_TIMER_ROUTELOC0_CC2LOC_LOC26 << 16)   /**< Shifted mode LOC26 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC2LOC_LOC27               (_TIMER_ROUTELOC0_CC2LOC_LOC27 << 16)   /**< Shifted mode LOC27 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC2LOC_LOC28               (_TIMER_ROUTELOC0_CC2LOC_LOC28 << 16)   /**< Shifted mode LOC28 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC2LOC_LOC29               (_TIMER_ROUTELOC0_CC2LOC_LOC29 << 16)   /**< Shifted mode LOC29 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC2LOC_LOC30               (_TIMER_ROUTELOC0_CC2LOC_LOC30 << 16)   /**< Shifted mode LOC30 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC2LOC_LOC31               (_TIMER_ROUTELOC0_CC2LOC_LOC31 << 16)   /**< Shifted mode LOC31 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC3LOC_SHIFT              24                                      /**< Shift value for TIMER_CC3LOC */
+#define _TIMER_ROUTELOC0_CC3LOC_MASK               0x1F000000UL                            /**< Bit mask for TIMER_CC3LOC */
+#define _TIMER_ROUTELOC0_CC3LOC_LOC0               0x00000000UL                            /**< Mode LOC0 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC3LOC_DEFAULT            0x00000000UL                            /**< Mode DEFAULT for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC3LOC_LOC1               0x00000001UL                            /**< Mode LOC1 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC3LOC_LOC2               0x00000002UL                            /**< Mode LOC2 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC3LOC_LOC3               0x00000003UL                            /**< Mode LOC3 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC3LOC_LOC4               0x00000004UL                            /**< Mode LOC4 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC3LOC_LOC5               0x00000005UL                            /**< Mode LOC5 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC3LOC_LOC6               0x00000006UL                            /**< Mode LOC6 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC3LOC_LOC7               0x00000007UL                            /**< Mode LOC7 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC3LOC_LOC8               0x00000008UL                            /**< Mode LOC8 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC3LOC_LOC9               0x00000009UL                            /**< Mode LOC9 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC3LOC_LOC10              0x0000000AUL                            /**< Mode LOC10 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC3LOC_LOC11              0x0000000BUL                            /**< Mode LOC11 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC3LOC_LOC12              0x0000000CUL                            /**< Mode LOC12 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC3LOC_LOC13              0x0000000DUL                            /**< Mode LOC13 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC3LOC_LOC14              0x0000000EUL                            /**< Mode LOC14 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC3LOC_LOC15              0x0000000FUL                            /**< Mode LOC15 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC3LOC_LOC16              0x00000010UL                            /**< Mode LOC16 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC3LOC_LOC17              0x00000011UL                            /**< Mode LOC17 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC3LOC_LOC18              0x00000012UL                            /**< Mode LOC18 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC3LOC_LOC19              0x00000013UL                            /**< Mode LOC19 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC3LOC_LOC20              0x00000014UL                            /**< Mode LOC20 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC3LOC_LOC21              0x00000015UL                            /**< Mode LOC21 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC3LOC_LOC22              0x00000016UL                            /**< Mode LOC22 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC3LOC_LOC23              0x00000017UL                            /**< Mode LOC23 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC3LOC_LOC24              0x00000018UL                            /**< Mode LOC24 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC3LOC_LOC25              0x00000019UL                            /**< Mode LOC25 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC3LOC_LOC26              0x0000001AUL                            /**< Mode LOC26 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC3LOC_LOC27              0x0000001BUL                            /**< Mode LOC27 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC3LOC_LOC28              0x0000001CUL                            /**< Mode LOC28 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC3LOC_LOC29              0x0000001DUL                            /**< Mode LOC29 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC3LOC_LOC30              0x0000001EUL                            /**< Mode LOC30 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC3LOC_LOC31              0x0000001FUL                            /**< Mode LOC31 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC3LOC_LOC0                (_TIMER_ROUTELOC0_CC3LOC_LOC0 << 24)    /**< Shifted mode LOC0 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC3LOC_DEFAULT             (_TIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC3LOC_LOC1                (_TIMER_ROUTELOC0_CC3LOC_LOC1 << 24)    /**< Shifted mode LOC1 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC3LOC_LOC2                (_TIMER_ROUTELOC0_CC3LOC_LOC2 << 24)    /**< Shifted mode LOC2 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC3LOC_LOC3                (_TIMER_ROUTELOC0_CC3LOC_LOC3 << 24)    /**< Shifted mode LOC3 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC3LOC_LOC4                (_TIMER_ROUTELOC0_CC3LOC_LOC4 << 24)    /**< Shifted mode LOC4 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC3LOC_LOC5                (_TIMER_ROUTELOC0_CC3LOC_LOC5 << 24)    /**< Shifted mode LOC5 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC3LOC_LOC6                (_TIMER_ROUTELOC0_CC3LOC_LOC6 << 24)    /**< Shifted mode LOC6 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC3LOC_LOC7                (_TIMER_ROUTELOC0_CC3LOC_LOC7 << 24)    /**< Shifted mode LOC7 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC3LOC_LOC8                (_TIMER_ROUTELOC0_CC3LOC_LOC8 << 24)    /**< Shifted mode LOC8 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC3LOC_LOC9                (_TIMER_ROUTELOC0_CC3LOC_LOC9 << 24)    /**< Shifted mode LOC9 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC3LOC_LOC10               (_TIMER_ROUTELOC0_CC3LOC_LOC10 << 24)   /**< Shifted mode LOC10 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC3LOC_LOC11               (_TIMER_ROUTELOC0_CC3LOC_LOC11 << 24)   /**< Shifted mode LOC11 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC3LOC_LOC12               (_TIMER_ROUTELOC0_CC3LOC_LOC12 << 24)   /**< Shifted mode LOC12 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC3LOC_LOC13               (_TIMER_ROUTELOC0_CC3LOC_LOC13 << 24)   /**< Shifted mode LOC13 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC3LOC_LOC14               (_TIMER_ROUTELOC0_CC3LOC_LOC14 << 24)   /**< Shifted mode LOC14 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC3LOC_LOC15               (_TIMER_ROUTELOC0_CC3LOC_LOC15 << 24)   /**< Shifted mode LOC15 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC3LOC_LOC16               (_TIMER_ROUTELOC0_CC3LOC_LOC16 << 24)   /**< Shifted mode LOC16 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC3LOC_LOC17               (_TIMER_ROUTELOC0_CC3LOC_LOC17 << 24)   /**< Shifted mode LOC17 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC3LOC_LOC18               (_TIMER_ROUTELOC0_CC3LOC_LOC18 << 24)   /**< Shifted mode LOC18 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC3LOC_LOC19               (_TIMER_ROUTELOC0_CC3LOC_LOC19 << 24)   /**< Shifted mode LOC19 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC3LOC_LOC20               (_TIMER_ROUTELOC0_CC3LOC_LOC20 << 24)   /**< Shifted mode LOC20 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC3LOC_LOC21               (_TIMER_ROUTELOC0_CC3LOC_LOC21 << 24)   /**< Shifted mode LOC21 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC3LOC_LOC22               (_TIMER_ROUTELOC0_CC3LOC_LOC22 << 24)   /**< Shifted mode LOC22 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC3LOC_LOC23               (_TIMER_ROUTELOC0_CC3LOC_LOC23 << 24)   /**< Shifted mode LOC23 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC3LOC_LOC24               (_TIMER_ROUTELOC0_CC3LOC_LOC24 << 24)   /**< Shifted mode LOC24 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC3LOC_LOC25               (_TIMER_ROUTELOC0_CC3LOC_LOC25 << 24)   /**< Shifted mode LOC25 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC3LOC_LOC26               (_TIMER_ROUTELOC0_CC3LOC_LOC26 << 24)   /**< Shifted mode LOC26 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC3LOC_LOC27               (_TIMER_ROUTELOC0_CC3LOC_LOC27 << 24)   /**< Shifted mode LOC27 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC3LOC_LOC28               (_TIMER_ROUTELOC0_CC3LOC_LOC28 << 24)   /**< Shifted mode LOC28 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC3LOC_LOC29               (_TIMER_ROUTELOC0_CC3LOC_LOC29 << 24)   /**< Shifted mode LOC29 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC3LOC_LOC30               (_TIMER_ROUTELOC0_CC3LOC_LOC30 << 24)   /**< Shifted mode LOC30 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC3LOC_LOC31               (_TIMER_ROUTELOC0_CC3LOC_LOC31 << 24)   /**< Shifted mode LOC31 for TIMER_ROUTELOC0 */
+
+/* Bit fields for TIMER ROUTELOC2 */
+#define _TIMER_ROUTELOC2_RESETVALUE                0x00000000UL                              /**< Default value for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_MASK                      0x001F1F1FUL                              /**< Mask for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI0LOC_SHIFT            0                                         /**< Shift value for TIMER_CDTI0LOC */
+#define _TIMER_ROUTELOC2_CDTI0LOC_MASK             0x1FUL                                    /**< Bit mask for TIMER_CDTI0LOC */
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC0             0x00000000UL                              /**< Mode LOC0 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI0LOC_DEFAULT          0x00000000UL                              /**< Mode DEFAULT for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC1             0x00000001UL                              /**< Mode LOC1 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC2             0x00000002UL                              /**< Mode LOC2 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC3             0x00000003UL                              /**< Mode LOC3 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC4             0x00000004UL                              /**< Mode LOC4 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC5             0x00000005UL                              /**< Mode LOC5 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC6             0x00000006UL                              /**< Mode LOC6 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC7             0x00000007UL                              /**< Mode LOC7 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC8             0x00000008UL                              /**< Mode LOC8 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC9             0x00000009UL                              /**< Mode LOC9 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC10            0x0000000AUL                              /**< Mode LOC10 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC11            0x0000000BUL                              /**< Mode LOC11 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC12            0x0000000CUL                              /**< Mode LOC12 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC13            0x0000000DUL                              /**< Mode LOC13 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC14            0x0000000EUL                              /**< Mode LOC14 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC15            0x0000000FUL                              /**< Mode LOC15 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC16            0x00000010UL                              /**< Mode LOC16 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC17            0x00000011UL                              /**< Mode LOC17 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC18            0x00000012UL                              /**< Mode LOC18 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC19            0x00000013UL                              /**< Mode LOC19 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC20            0x00000014UL                              /**< Mode LOC20 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC21            0x00000015UL                              /**< Mode LOC21 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC22            0x00000016UL                              /**< Mode LOC22 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC23            0x00000017UL                              /**< Mode LOC23 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC24            0x00000018UL                              /**< Mode LOC24 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC25            0x00000019UL                              /**< Mode LOC25 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC26            0x0000001AUL                              /**< Mode LOC26 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC27            0x0000001BUL                              /**< Mode LOC27 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC28            0x0000001CUL                              /**< Mode LOC28 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC29            0x0000001DUL                              /**< Mode LOC29 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC30            0x0000001EUL                              /**< Mode LOC30 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC31            0x0000001FUL                              /**< Mode LOC31 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC0              (_TIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0)     /**< Shifted mode LOC0 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI0LOC_DEFAULT           (_TIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0)  /**< Shifted mode DEFAULT for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC1              (_TIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0)     /**< Shifted mode LOC1 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC2              (_TIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0)     /**< Shifted mode LOC2 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC3              (_TIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0)     /**< Shifted mode LOC3 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC4              (_TIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0)     /**< Shifted mode LOC4 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC5              (_TIMER_ROUTELOC2_CDTI0LOC_LOC5 << 0)     /**< Shifted mode LOC5 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC6              (_TIMER_ROUTELOC2_CDTI0LOC_LOC6 << 0)     /**< Shifted mode LOC6 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC7              (_TIMER_ROUTELOC2_CDTI0LOC_LOC7 << 0)     /**< Shifted mode LOC7 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC8              (_TIMER_ROUTELOC2_CDTI0LOC_LOC8 << 0)     /**< Shifted mode LOC8 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC9              (_TIMER_ROUTELOC2_CDTI0LOC_LOC9 << 0)     /**< Shifted mode LOC9 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC10             (_TIMER_ROUTELOC2_CDTI0LOC_LOC10 << 0)    /**< Shifted mode LOC10 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC11             (_TIMER_ROUTELOC2_CDTI0LOC_LOC11 << 0)    /**< Shifted mode LOC11 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC12             (_TIMER_ROUTELOC2_CDTI0LOC_LOC12 << 0)    /**< Shifted mode LOC12 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC13             (_TIMER_ROUTELOC2_CDTI0LOC_LOC13 << 0)    /**< Shifted mode LOC13 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC14             (_TIMER_ROUTELOC2_CDTI0LOC_LOC14 << 0)    /**< Shifted mode LOC14 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC15             (_TIMER_ROUTELOC2_CDTI0LOC_LOC15 << 0)    /**< Shifted mode LOC15 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC16             (_TIMER_ROUTELOC2_CDTI0LOC_LOC16 << 0)    /**< Shifted mode LOC16 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC17             (_TIMER_ROUTELOC2_CDTI0LOC_LOC17 << 0)    /**< Shifted mode LOC17 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC18             (_TIMER_ROUTELOC2_CDTI0LOC_LOC18 << 0)    /**< Shifted mode LOC18 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC19             (_TIMER_ROUTELOC2_CDTI0LOC_LOC19 << 0)    /**< Shifted mode LOC19 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC20             (_TIMER_ROUTELOC2_CDTI0LOC_LOC20 << 0)    /**< Shifted mode LOC20 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC21             (_TIMER_ROUTELOC2_CDTI0LOC_LOC21 << 0)    /**< Shifted mode LOC21 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC22             (_TIMER_ROUTELOC2_CDTI0LOC_LOC22 << 0)    /**< Shifted mode LOC22 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC23             (_TIMER_ROUTELOC2_CDTI0LOC_LOC23 << 0)    /**< Shifted mode LOC23 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC24             (_TIMER_ROUTELOC2_CDTI0LOC_LOC24 << 0)    /**< Shifted mode LOC24 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC25             (_TIMER_ROUTELOC2_CDTI0LOC_LOC25 << 0)    /**< Shifted mode LOC25 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC26             (_TIMER_ROUTELOC2_CDTI0LOC_LOC26 << 0)    /**< Shifted mode LOC26 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC27             (_TIMER_ROUTELOC2_CDTI0LOC_LOC27 << 0)    /**< Shifted mode LOC27 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC28             (_TIMER_ROUTELOC2_CDTI0LOC_LOC28 << 0)    /**< Shifted mode LOC28 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC29             (_TIMER_ROUTELOC2_CDTI0LOC_LOC29 << 0)    /**< Shifted mode LOC29 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC30             (_TIMER_ROUTELOC2_CDTI0LOC_LOC30 << 0)    /**< Shifted mode LOC30 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC31             (_TIMER_ROUTELOC2_CDTI0LOC_LOC31 << 0)    /**< Shifted mode LOC31 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI1LOC_SHIFT            8                                         /**< Shift value for TIMER_CDTI1LOC */
+#define _TIMER_ROUTELOC2_CDTI1LOC_MASK             0x1F00UL                                  /**< Bit mask for TIMER_CDTI1LOC */
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC0             0x00000000UL                              /**< Mode LOC0 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI1LOC_DEFAULT          0x00000000UL                              /**< Mode DEFAULT for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC1             0x00000001UL                              /**< Mode LOC1 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC2             0x00000002UL                              /**< Mode LOC2 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC3             0x00000003UL                              /**< Mode LOC3 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC4             0x00000004UL                              /**< Mode LOC4 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC5             0x00000005UL                              /**< Mode LOC5 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC6             0x00000006UL                              /**< Mode LOC6 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC7             0x00000007UL                              /**< Mode LOC7 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC8             0x00000008UL                              /**< Mode LOC8 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC9             0x00000009UL                              /**< Mode LOC9 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC10            0x0000000AUL                              /**< Mode LOC10 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC11            0x0000000BUL                              /**< Mode LOC11 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC12            0x0000000CUL                              /**< Mode LOC12 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC13            0x0000000DUL                              /**< Mode LOC13 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC14            0x0000000EUL                              /**< Mode LOC14 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC15            0x0000000FUL                              /**< Mode LOC15 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC16            0x00000010UL                              /**< Mode LOC16 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC17            0x00000011UL                              /**< Mode LOC17 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC18            0x00000012UL                              /**< Mode LOC18 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC19            0x00000013UL                              /**< Mode LOC19 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC20            0x00000014UL                              /**< Mode LOC20 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC21            0x00000015UL                              /**< Mode LOC21 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC22            0x00000016UL                              /**< Mode LOC22 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC23            0x00000017UL                              /**< Mode LOC23 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC24            0x00000018UL                              /**< Mode LOC24 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC25            0x00000019UL                              /**< Mode LOC25 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC26            0x0000001AUL                              /**< Mode LOC26 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC27            0x0000001BUL                              /**< Mode LOC27 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC28            0x0000001CUL                              /**< Mode LOC28 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC29            0x0000001DUL                              /**< Mode LOC29 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC30            0x0000001EUL                              /**< Mode LOC30 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC31            0x0000001FUL                              /**< Mode LOC31 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC0              (_TIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8)     /**< Shifted mode LOC0 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI1LOC_DEFAULT           (_TIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8)  /**< Shifted mode DEFAULT for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC1              (_TIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8)     /**< Shifted mode LOC1 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC2              (_TIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8)     /**< Shifted mode LOC2 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC3              (_TIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8)     /**< Shifted mode LOC3 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC4              (_TIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8)     /**< Shifted mode LOC4 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC5              (_TIMER_ROUTELOC2_CDTI1LOC_LOC5 << 8)     /**< Shifted mode LOC5 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC6              (_TIMER_ROUTELOC2_CDTI1LOC_LOC6 << 8)     /**< Shifted mode LOC6 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC7              (_TIMER_ROUTELOC2_CDTI1LOC_LOC7 << 8)     /**< Shifted mode LOC7 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC8              (_TIMER_ROUTELOC2_CDTI1LOC_LOC8 << 8)     /**< Shifted mode LOC8 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC9              (_TIMER_ROUTELOC2_CDTI1LOC_LOC9 << 8)     /**< Shifted mode LOC9 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC10             (_TIMER_ROUTELOC2_CDTI1LOC_LOC10 << 8)    /**< Shifted mode LOC10 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC11             (_TIMER_ROUTELOC2_CDTI1LOC_LOC11 << 8)    /**< Shifted mode LOC11 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC12             (_TIMER_ROUTELOC2_CDTI1LOC_LOC12 << 8)    /**< Shifted mode LOC12 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC13             (_TIMER_ROUTELOC2_CDTI1LOC_LOC13 << 8)    /**< Shifted mode LOC13 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC14             (_TIMER_ROUTELOC2_CDTI1LOC_LOC14 << 8)    /**< Shifted mode LOC14 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC15             (_TIMER_ROUTELOC2_CDTI1LOC_LOC15 << 8)    /**< Shifted mode LOC15 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC16             (_TIMER_ROUTELOC2_CDTI1LOC_LOC16 << 8)    /**< Shifted mode LOC16 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC17             (_TIMER_ROUTELOC2_CDTI1LOC_LOC17 << 8)    /**< Shifted mode LOC17 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC18             (_TIMER_ROUTELOC2_CDTI1LOC_LOC18 << 8)    /**< Shifted mode LOC18 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC19             (_TIMER_ROUTELOC2_CDTI1LOC_LOC19 << 8)    /**< Shifted mode LOC19 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC20             (_TIMER_ROUTELOC2_CDTI1LOC_LOC20 << 8)    /**< Shifted mode LOC20 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC21             (_TIMER_ROUTELOC2_CDTI1LOC_LOC21 << 8)    /**< Shifted mode LOC21 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC22             (_TIMER_ROUTELOC2_CDTI1LOC_LOC22 << 8)    /**< Shifted mode LOC22 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC23             (_TIMER_ROUTELOC2_CDTI1LOC_LOC23 << 8)    /**< Shifted mode LOC23 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC24             (_TIMER_ROUTELOC2_CDTI1LOC_LOC24 << 8)    /**< Shifted mode LOC24 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC25             (_TIMER_ROUTELOC2_CDTI1LOC_LOC25 << 8)    /**< Shifted mode LOC25 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC26             (_TIMER_ROUTELOC2_CDTI1LOC_LOC26 << 8)    /**< Shifted mode LOC26 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC27             (_TIMER_ROUTELOC2_CDTI1LOC_LOC27 << 8)    /**< Shifted mode LOC27 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC28             (_TIMER_ROUTELOC2_CDTI1LOC_LOC28 << 8)    /**< Shifted mode LOC28 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC29             (_TIMER_ROUTELOC2_CDTI1LOC_LOC29 << 8)    /**< Shifted mode LOC29 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC30             (_TIMER_ROUTELOC2_CDTI1LOC_LOC30 << 8)    /**< Shifted mode LOC30 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC31             (_TIMER_ROUTELOC2_CDTI1LOC_LOC31 << 8)    /**< Shifted mode LOC31 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI2LOC_SHIFT            16                                        /**< Shift value for TIMER_CDTI2LOC */
+#define _TIMER_ROUTELOC2_CDTI2LOC_MASK             0x1F0000UL                                /**< Bit mask for TIMER_CDTI2LOC */
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC0             0x00000000UL                              /**< Mode LOC0 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI2LOC_DEFAULT          0x00000000UL                              /**< Mode DEFAULT for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC1             0x00000001UL                              /**< Mode LOC1 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC2             0x00000002UL                              /**< Mode LOC2 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC3             0x00000003UL                              /**< Mode LOC3 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC4             0x00000004UL                              /**< Mode LOC4 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC5             0x00000005UL                              /**< Mode LOC5 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC6             0x00000006UL                              /**< Mode LOC6 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC7             0x00000007UL                              /**< Mode LOC7 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC8             0x00000008UL                              /**< Mode LOC8 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC9             0x00000009UL                              /**< Mode LOC9 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC10            0x0000000AUL                              /**< Mode LOC10 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC11            0x0000000BUL                              /**< Mode LOC11 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC12            0x0000000CUL                              /**< Mode LOC12 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC13            0x0000000DUL                              /**< Mode LOC13 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC14            0x0000000EUL                              /**< Mode LOC14 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC15            0x0000000FUL                              /**< Mode LOC15 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC16            0x00000010UL                              /**< Mode LOC16 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC17            0x00000011UL                              /**< Mode LOC17 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC18            0x00000012UL                              /**< Mode LOC18 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC19            0x00000013UL                              /**< Mode LOC19 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC20            0x00000014UL                              /**< Mode LOC20 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC21            0x00000015UL                              /**< Mode LOC21 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC22            0x00000016UL                              /**< Mode LOC22 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC23            0x00000017UL                              /**< Mode LOC23 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC24            0x00000018UL                              /**< Mode LOC24 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC25            0x00000019UL                              /**< Mode LOC25 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC26            0x0000001AUL                              /**< Mode LOC26 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC27            0x0000001BUL                              /**< Mode LOC27 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC28            0x0000001CUL                              /**< Mode LOC28 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC29            0x0000001DUL                              /**< Mode LOC29 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC30            0x0000001EUL                              /**< Mode LOC30 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC31            0x0000001FUL                              /**< Mode LOC31 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC0              (_TIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16)    /**< Shifted mode LOC0 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI2LOC_DEFAULT           (_TIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC1              (_TIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16)    /**< Shifted mode LOC1 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC2              (_TIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16)    /**< Shifted mode LOC2 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC3              (_TIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16)    /**< Shifted mode LOC3 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC4              (_TIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16)    /**< Shifted mode LOC4 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC5              (_TIMER_ROUTELOC2_CDTI2LOC_LOC5 << 16)    /**< Shifted mode LOC5 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC6              (_TIMER_ROUTELOC2_CDTI2LOC_LOC6 << 16)    /**< Shifted mode LOC6 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC7              (_TIMER_ROUTELOC2_CDTI2LOC_LOC7 << 16)    /**< Shifted mode LOC7 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC8              (_TIMER_ROUTELOC2_CDTI2LOC_LOC8 << 16)    /**< Shifted mode LOC8 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC9              (_TIMER_ROUTELOC2_CDTI2LOC_LOC9 << 16)    /**< Shifted mode LOC9 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC10             (_TIMER_ROUTELOC2_CDTI2LOC_LOC10 << 16)   /**< Shifted mode LOC10 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC11             (_TIMER_ROUTELOC2_CDTI2LOC_LOC11 << 16)   /**< Shifted mode LOC11 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC12             (_TIMER_ROUTELOC2_CDTI2LOC_LOC12 << 16)   /**< Shifted mode LOC12 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC13             (_TIMER_ROUTELOC2_CDTI2LOC_LOC13 << 16)   /**< Shifted mode LOC13 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC14             (_TIMER_ROUTELOC2_CDTI2LOC_LOC14 << 16)   /**< Shifted mode LOC14 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC15             (_TIMER_ROUTELOC2_CDTI2LOC_LOC15 << 16)   /**< Shifted mode LOC15 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC16             (_TIMER_ROUTELOC2_CDTI2LOC_LOC16 << 16)   /**< Shifted mode LOC16 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC17             (_TIMER_ROUTELOC2_CDTI2LOC_LOC17 << 16)   /**< Shifted mode LOC17 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC18             (_TIMER_ROUTELOC2_CDTI2LOC_LOC18 << 16)   /**< Shifted mode LOC18 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC19             (_TIMER_ROUTELOC2_CDTI2LOC_LOC19 << 16)   /**< Shifted mode LOC19 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC20             (_TIMER_ROUTELOC2_CDTI2LOC_LOC20 << 16)   /**< Shifted mode LOC20 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC21             (_TIMER_ROUTELOC2_CDTI2LOC_LOC21 << 16)   /**< Shifted mode LOC21 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC22             (_TIMER_ROUTELOC2_CDTI2LOC_LOC22 << 16)   /**< Shifted mode LOC22 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC23             (_TIMER_ROUTELOC2_CDTI2LOC_LOC23 << 16)   /**< Shifted mode LOC23 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC24             (_TIMER_ROUTELOC2_CDTI2LOC_LOC24 << 16)   /**< Shifted mode LOC24 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC25             (_TIMER_ROUTELOC2_CDTI2LOC_LOC25 << 16)   /**< Shifted mode LOC25 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC26             (_TIMER_ROUTELOC2_CDTI2LOC_LOC26 << 16)   /**< Shifted mode LOC26 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC27             (_TIMER_ROUTELOC2_CDTI2LOC_LOC27 << 16)   /**< Shifted mode LOC27 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC28             (_TIMER_ROUTELOC2_CDTI2LOC_LOC28 << 16)   /**< Shifted mode LOC28 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC29             (_TIMER_ROUTELOC2_CDTI2LOC_LOC29 << 16)   /**< Shifted mode LOC29 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC30             (_TIMER_ROUTELOC2_CDTI2LOC_LOC30 << 16)   /**< Shifted mode LOC30 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC31             (_TIMER_ROUTELOC2_CDTI2LOC_LOC31 << 16)   /**< Shifted mode LOC31 for TIMER_ROUTELOC2 */
+
+/* Bit fields for TIMER CC_CTRL */
+#define _TIMER_CC_CTRL_RESETVALUE                  0x00000000UL                                    /**< Default value for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_MASK                        0x7F0F3F17UL                                    /**< Mask for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_MODE_SHIFT                  0                                               /**< Shift value for TIMER_MODE */
+#define _TIMER_CC_CTRL_MODE_MASK                   0x3UL                                           /**< Bit mask for TIMER_MODE */
+#define _TIMER_CC_CTRL_MODE_DEFAULT                0x00000000UL                                    /**< Mode DEFAULT for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_MODE_OFF                    0x00000000UL                                    /**< Mode OFF for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_MODE_INPUTCAPTURE           0x00000001UL                                    /**< Mode INPUTCAPTURE for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_MODE_OUTPUTCOMPARE          0x00000002UL                                    /**< Mode OUTPUTCOMPARE for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_MODE_PWM                    0x00000003UL                                    /**< Mode PWM for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_MODE_DEFAULT                 (_TIMER_CC_CTRL_MODE_DEFAULT << 0)              /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_MODE_OFF                     (_TIMER_CC_CTRL_MODE_OFF << 0)                  /**< Shifted mode OFF for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_MODE_INPUTCAPTURE            (_TIMER_CC_CTRL_MODE_INPUTCAPTURE << 0)         /**< Shifted mode INPUTCAPTURE for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_MODE_OUTPUTCOMPARE           (_TIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0)        /**< Shifted mode OUTPUTCOMPARE for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_MODE_PWM                     (_TIMER_CC_CTRL_MODE_PWM << 0)                  /**< Shifted mode PWM for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_OUTINV                       (0x1UL << 2)                                    /**< Output Invert */
+#define _TIMER_CC_CTRL_OUTINV_SHIFT                2                                               /**< Shift value for TIMER_OUTINV */
+#define _TIMER_CC_CTRL_OUTINV_MASK                 0x4UL                                           /**< Bit mask for TIMER_OUTINV */
+#define _TIMER_CC_CTRL_OUTINV_DEFAULT              0x00000000UL                                    /**< Mode DEFAULT for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_OUTINV_DEFAULT               (_TIMER_CC_CTRL_OUTINV_DEFAULT << 2)            /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_COIST                        (0x1UL << 4)                                    /**< Compare Output Initial State */
+#define _TIMER_CC_CTRL_COIST_SHIFT                 4                                               /**< Shift value for TIMER_COIST */
+#define _TIMER_CC_CTRL_COIST_MASK                  0x10UL                                          /**< Bit mask for TIMER_COIST */
+#define _TIMER_CC_CTRL_COIST_DEFAULT               0x00000000UL                                    /**< Mode DEFAULT for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_COIST_DEFAULT                (_TIMER_CC_CTRL_COIST_DEFAULT << 4)             /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_CMOA_SHIFT                  8                                               /**< Shift value for TIMER_CMOA */
+#define _TIMER_CC_CTRL_CMOA_MASK                   0x300UL                                         /**< Bit mask for TIMER_CMOA */
+#define _TIMER_CC_CTRL_CMOA_DEFAULT                0x00000000UL                                    /**< Mode DEFAULT for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_CMOA_NONE                   0x00000000UL                                    /**< Mode NONE for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_CMOA_TOGGLE                 0x00000001UL                                    /**< Mode TOGGLE for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_CMOA_CLEAR                  0x00000002UL                                    /**< Mode CLEAR for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_CMOA_SET                    0x00000003UL                                    /**< Mode SET for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_CMOA_DEFAULT                 (_TIMER_CC_CTRL_CMOA_DEFAULT << 8)              /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_CMOA_NONE                    (_TIMER_CC_CTRL_CMOA_NONE << 8)                 /**< Shifted mode NONE for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_CMOA_TOGGLE                  (_TIMER_CC_CTRL_CMOA_TOGGLE << 8)               /**< Shifted mode TOGGLE for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_CMOA_CLEAR                   (_TIMER_CC_CTRL_CMOA_CLEAR << 8)                /**< Shifted mode CLEAR for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_CMOA_SET                     (_TIMER_CC_CTRL_CMOA_SET << 8)                  /**< Shifted mode SET for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_COFOA_SHIFT                 10                                              /**< Shift value for TIMER_COFOA */
+#define _TIMER_CC_CTRL_COFOA_MASK                  0xC00UL                                         /**< Bit mask for TIMER_COFOA */
+#define _TIMER_CC_CTRL_COFOA_DEFAULT               0x00000000UL                                    /**< Mode DEFAULT for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_COFOA_NONE                  0x00000000UL                                    /**< Mode NONE for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_COFOA_TOGGLE                0x00000001UL                                    /**< Mode TOGGLE for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_COFOA_CLEAR                 0x00000002UL                                    /**< Mode CLEAR for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_COFOA_SET                   0x00000003UL                                    /**< Mode SET for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_COFOA_DEFAULT                (_TIMER_CC_CTRL_COFOA_DEFAULT << 10)            /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_COFOA_NONE                   (_TIMER_CC_CTRL_COFOA_NONE << 10)               /**< Shifted mode NONE for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_COFOA_TOGGLE                 (_TIMER_CC_CTRL_COFOA_TOGGLE << 10)             /**< Shifted mode TOGGLE for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_COFOA_CLEAR                  (_TIMER_CC_CTRL_COFOA_CLEAR << 10)              /**< Shifted mode CLEAR for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_COFOA_SET                    (_TIMER_CC_CTRL_COFOA_SET << 10)                /**< Shifted mode SET for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_CUFOA_SHIFT                 12                                              /**< Shift value for TIMER_CUFOA */
+#define _TIMER_CC_CTRL_CUFOA_MASK                  0x3000UL                                        /**< Bit mask for TIMER_CUFOA */
+#define _TIMER_CC_CTRL_CUFOA_DEFAULT               0x00000000UL                                    /**< Mode DEFAULT for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_CUFOA_NONE                  0x00000000UL                                    /**< Mode NONE for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_CUFOA_TOGGLE                0x00000001UL                                    /**< Mode TOGGLE for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_CUFOA_CLEAR                 0x00000002UL                                    /**< Mode CLEAR for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_CUFOA_SET                   0x00000003UL                                    /**< Mode SET for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_CUFOA_DEFAULT                (_TIMER_CC_CTRL_CUFOA_DEFAULT << 12)            /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_CUFOA_NONE                   (_TIMER_CC_CTRL_CUFOA_NONE << 12)               /**< Shifted mode NONE for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_CUFOA_TOGGLE                 (_TIMER_CC_CTRL_CUFOA_TOGGLE << 12)             /**< Shifted mode TOGGLE for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_CUFOA_CLEAR                  (_TIMER_CC_CTRL_CUFOA_CLEAR << 12)              /**< Shifted mode CLEAR for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_CUFOA_SET                    (_TIMER_CC_CTRL_CUFOA_SET << 12)                /**< Shifted mode SET for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_PRSSEL_SHIFT                16                                              /**< Shift value for TIMER_PRSSEL */
+#define _TIMER_CC_CTRL_PRSSEL_MASK                 0xF0000UL                                       /**< Bit mask for TIMER_PRSSEL */
+#define _TIMER_CC_CTRL_PRSSEL_DEFAULT              0x00000000UL                                    /**< Mode DEFAULT for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_PRSSEL_PRSCH0               0x00000000UL                                    /**< Mode PRSCH0 for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_PRSSEL_PRSCH1               0x00000001UL                                    /**< Mode PRSCH1 for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_PRSSEL_PRSCH2               0x00000002UL                                    /**< Mode PRSCH2 for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_PRSSEL_PRSCH3               0x00000003UL                                    /**< Mode PRSCH3 for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_PRSSEL_PRSCH4               0x00000004UL                                    /**< Mode PRSCH4 for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_PRSSEL_PRSCH5               0x00000005UL                                    /**< Mode PRSCH5 for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_PRSSEL_PRSCH6               0x00000006UL                                    /**< Mode PRSCH6 for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_PRSSEL_PRSCH7               0x00000007UL                                    /**< Mode PRSCH7 for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_PRSSEL_PRSCH8               0x00000008UL                                    /**< Mode PRSCH8 for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_PRSSEL_PRSCH9               0x00000009UL                                    /**< Mode PRSCH9 for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_PRSSEL_PRSCH10              0x0000000AUL                                    /**< Mode PRSCH10 for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_PRSSEL_PRSCH11              0x0000000BUL                                    /**< Mode PRSCH11 for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_PRSSEL_DEFAULT               (_TIMER_CC_CTRL_PRSSEL_DEFAULT << 16)           /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_PRSSEL_PRSCH0                (_TIMER_CC_CTRL_PRSSEL_PRSCH0 << 16)            /**< Shifted mode PRSCH0 for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_PRSSEL_PRSCH1                (_TIMER_CC_CTRL_PRSSEL_PRSCH1 << 16)            /**< Shifted mode PRSCH1 for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_PRSSEL_PRSCH2                (_TIMER_CC_CTRL_PRSSEL_PRSCH2 << 16)            /**< Shifted mode PRSCH2 for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_PRSSEL_PRSCH3                (_TIMER_CC_CTRL_PRSSEL_PRSCH3 << 16)            /**< Shifted mode PRSCH3 for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_PRSSEL_PRSCH4                (_TIMER_CC_CTRL_PRSSEL_PRSCH4 << 16)            /**< Shifted mode PRSCH4 for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_PRSSEL_PRSCH5                (_TIMER_CC_CTRL_PRSSEL_PRSCH5 << 16)            /**< Shifted mode PRSCH5 for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_PRSSEL_PRSCH6                (_TIMER_CC_CTRL_PRSSEL_PRSCH6 << 16)            /**< Shifted mode PRSCH6 for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_PRSSEL_PRSCH7                (_TIMER_CC_CTRL_PRSSEL_PRSCH7 << 16)            /**< Shifted mode PRSCH7 for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_PRSSEL_PRSCH8                (_TIMER_CC_CTRL_PRSSEL_PRSCH8 << 16)            /**< Shifted mode PRSCH8 for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_PRSSEL_PRSCH9                (_TIMER_CC_CTRL_PRSSEL_PRSCH9 << 16)            /**< Shifted mode PRSCH9 for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_PRSSEL_PRSCH10               (_TIMER_CC_CTRL_PRSSEL_PRSCH10 << 16)           /**< Shifted mode PRSCH10 for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_PRSSEL_PRSCH11               (_TIMER_CC_CTRL_PRSSEL_PRSCH11 << 16)           /**< Shifted mode PRSCH11 for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_ICEDGE_SHIFT                24                                              /**< Shift value for TIMER_ICEDGE */
+#define _TIMER_CC_CTRL_ICEDGE_MASK                 0x3000000UL                                     /**< Bit mask for TIMER_ICEDGE */
+#define _TIMER_CC_CTRL_ICEDGE_DEFAULT              0x00000000UL                                    /**< Mode DEFAULT for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_ICEDGE_RISING               0x00000000UL                                    /**< Mode RISING for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_ICEDGE_FALLING              0x00000001UL                                    /**< Mode FALLING for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_ICEDGE_BOTH                 0x00000002UL                                    /**< Mode BOTH for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_ICEDGE_NONE                 0x00000003UL                                    /**< Mode NONE for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_ICEDGE_DEFAULT               (_TIMER_CC_CTRL_ICEDGE_DEFAULT << 24)           /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_ICEDGE_RISING                (_TIMER_CC_CTRL_ICEDGE_RISING << 24)            /**< Shifted mode RISING for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_ICEDGE_FALLING               (_TIMER_CC_CTRL_ICEDGE_FALLING << 24)           /**< Shifted mode FALLING for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_ICEDGE_BOTH                  (_TIMER_CC_CTRL_ICEDGE_BOTH << 24)              /**< Shifted mode BOTH for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_ICEDGE_NONE                  (_TIMER_CC_CTRL_ICEDGE_NONE << 24)              /**< Shifted mode NONE for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_ICEVCTRL_SHIFT              26                                              /**< Shift value for TIMER_ICEVCTRL */
+#define _TIMER_CC_CTRL_ICEVCTRL_MASK               0xC000000UL                                     /**< Bit mask for TIMER_ICEVCTRL */
+#define _TIMER_CC_CTRL_ICEVCTRL_DEFAULT            0x00000000UL                                    /**< Mode DEFAULT for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE          0x00000000UL                                    /**< Mode EVERYEDGE for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE    0x00000001UL                                    /**< Mode EVERYSECONDEDGE for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_ICEVCTRL_RISING             0x00000002UL                                    /**< Mode RISING for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_ICEVCTRL_FALLING            0x00000003UL                                    /**< Mode FALLING for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_ICEVCTRL_DEFAULT             (_TIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26)         /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE           (_TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26)       /**< Shifted mode EVERYEDGE for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE     (_TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_ICEVCTRL_RISING              (_TIMER_CC_CTRL_ICEVCTRL_RISING << 26)          /**< Shifted mode RISING for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_ICEVCTRL_FALLING             (_TIMER_CC_CTRL_ICEVCTRL_FALLING << 26)         /**< Shifted mode FALLING for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_PRSCONF                      (0x1UL << 28)                                   /**< PRS Configuration */
+#define _TIMER_CC_CTRL_PRSCONF_SHIFT               28                                              /**< Shift value for TIMER_PRSCONF */
+#define _TIMER_CC_CTRL_PRSCONF_MASK                0x10000000UL                                    /**< Bit mask for TIMER_PRSCONF */
+#define _TIMER_CC_CTRL_PRSCONF_DEFAULT             0x00000000UL                                    /**< Mode DEFAULT for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_PRSCONF_PULSE               0x00000000UL                                    /**< Mode PULSE for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_PRSCONF_LEVEL               0x00000001UL                                    /**< Mode LEVEL for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_PRSCONF_DEFAULT              (_TIMER_CC_CTRL_PRSCONF_DEFAULT << 28)          /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_PRSCONF_PULSE                (_TIMER_CC_CTRL_PRSCONF_PULSE << 28)            /**< Shifted mode PULSE for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_PRSCONF_LEVEL                (_TIMER_CC_CTRL_PRSCONF_LEVEL << 28)            /**< Shifted mode LEVEL for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_INSEL                        (0x1UL << 29)                                   /**< Input Selection */
+#define _TIMER_CC_CTRL_INSEL_SHIFT                 29                                              /**< Shift value for TIMER_INSEL */
+#define _TIMER_CC_CTRL_INSEL_MASK                  0x20000000UL                                    /**< Bit mask for TIMER_INSEL */
+#define _TIMER_CC_CTRL_INSEL_DEFAULT               0x00000000UL                                    /**< Mode DEFAULT for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_INSEL_PIN                   0x00000000UL                                    /**< Mode PIN for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_INSEL_PRS                   0x00000001UL                                    /**< Mode PRS for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_INSEL_DEFAULT                (_TIMER_CC_CTRL_INSEL_DEFAULT << 29)            /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_INSEL_PIN                    (_TIMER_CC_CTRL_INSEL_PIN << 29)                /**< Shifted mode PIN for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_INSEL_PRS                    (_TIMER_CC_CTRL_INSEL_PRS << 29)                /**< Shifted mode PRS for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_FILT                         (0x1UL << 30)                                   /**< Digital Filter */
+#define _TIMER_CC_CTRL_FILT_SHIFT                  30                                              /**< Shift value for TIMER_FILT */
+#define _TIMER_CC_CTRL_FILT_MASK                   0x40000000UL                                    /**< Bit mask for TIMER_FILT */
+#define _TIMER_CC_CTRL_FILT_DEFAULT                0x00000000UL                                    /**< Mode DEFAULT for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_FILT_DISABLE                0x00000000UL                                    /**< Mode DISABLE for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_FILT_ENABLE                 0x00000001UL                                    /**< Mode ENABLE for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_FILT_DEFAULT                 (_TIMER_CC_CTRL_FILT_DEFAULT << 30)             /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_FILT_DISABLE                 (_TIMER_CC_CTRL_FILT_DISABLE << 30)             /**< Shifted mode DISABLE for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_FILT_ENABLE                  (_TIMER_CC_CTRL_FILT_ENABLE << 30)              /**< Shifted mode ENABLE for TIMER_CC_CTRL */
+
+/* Bit fields for TIMER CC_CCV */
+#define _TIMER_CC_CCV_RESETVALUE                   0x00000000UL                     /**< Default value for TIMER_CC_CCV */
+#define _TIMER_CC_CCV_MASK                         0x0000FFFFUL                     /**< Mask for TIMER_CC_CCV */
+#define _TIMER_CC_CCV_CCV_SHIFT                    0                                /**< Shift value for TIMER_CCV */
+#define _TIMER_CC_CCV_CCV_MASK                     0xFFFFUL                         /**< Bit mask for TIMER_CCV */
+#define _TIMER_CC_CCV_CCV_DEFAULT                  0x00000000UL                     /**< Mode DEFAULT for TIMER_CC_CCV */
+#define TIMER_CC_CCV_CCV_DEFAULT                   (_TIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CCV */
+
+/* Bit fields for TIMER CC_CCVP */
+#define _TIMER_CC_CCVP_RESETVALUE                  0x00000000UL                       /**< Default value for TIMER_CC_CCVP */
+#define _TIMER_CC_CCVP_MASK                        0x0000FFFFUL                       /**< Mask for TIMER_CC_CCVP */
+#define _TIMER_CC_CCVP_CCVP_SHIFT                  0                                  /**< Shift value for TIMER_CCVP */
+#define _TIMER_CC_CCVP_CCVP_MASK                   0xFFFFUL                           /**< Bit mask for TIMER_CCVP */
+#define _TIMER_CC_CCVP_CCVP_DEFAULT                0x00000000UL                       /**< Mode DEFAULT for TIMER_CC_CCVP */
+#define TIMER_CC_CCVP_CCVP_DEFAULT                 (_TIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CCVP */
+
+/* Bit fields for TIMER CC_CCVB */
+#define _TIMER_CC_CCVB_RESETVALUE                  0x00000000UL                       /**< Default value for TIMER_CC_CCVB */
+#define _TIMER_CC_CCVB_MASK                        0x0000FFFFUL                       /**< Mask for TIMER_CC_CCVB */
+#define _TIMER_CC_CCVB_CCVB_SHIFT                  0                                  /**< Shift value for TIMER_CCVB */
+#define _TIMER_CC_CCVB_CCVB_MASK                   0xFFFFUL                           /**< Bit mask for TIMER_CCVB */
+#define _TIMER_CC_CCVB_CCVB_DEFAULT                0x00000000UL                       /**< Mode DEFAULT for TIMER_CC_CCVB */
+#define TIMER_CC_CCVB_CCVB_DEFAULT                 (_TIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CCVB */
+
+/* Bit fields for TIMER DTCTRL */
+#define _TIMER_DTCTRL_RESETVALUE                   0x00000000UL                          /**< Default value for TIMER_DTCTRL */
+#define _TIMER_DTCTRL_MASK                         0x010006FFUL                          /**< Mask for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTEN                          (0x1UL << 0)                          /**< DTI Enable */
+#define _TIMER_DTCTRL_DTEN_SHIFT                   0                                     /**< Shift value for TIMER_DTEN */
+#define _TIMER_DTCTRL_DTEN_MASK                    0x1UL                                 /**< Bit mask for TIMER_DTEN */
+#define _TIMER_DTCTRL_DTEN_DEFAULT                 0x00000000UL                          /**< Mode DEFAULT for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTEN_DEFAULT                  (_TIMER_DTCTRL_DTEN_DEFAULT << 0)     /**< Shifted mode DEFAULT for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTDAS                         (0x1UL << 1)                          /**< DTI Automatic Start-up Functionality */
+#define _TIMER_DTCTRL_DTDAS_SHIFT                  1                                     /**< Shift value for TIMER_DTDAS */
+#define _TIMER_DTCTRL_DTDAS_MASK                   0x2UL                                 /**< Bit mask for TIMER_DTDAS */
+#define _TIMER_DTCTRL_DTDAS_DEFAULT                0x00000000UL                          /**< Mode DEFAULT for TIMER_DTCTRL */
+#define _TIMER_DTCTRL_DTDAS_NORESTART              0x00000000UL                          /**< Mode NORESTART for TIMER_DTCTRL */
+#define _TIMER_DTCTRL_DTDAS_RESTART                0x00000001UL                          /**< Mode RESTART for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTDAS_DEFAULT                 (_TIMER_DTCTRL_DTDAS_DEFAULT << 1)    /**< Shifted mode DEFAULT for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTDAS_NORESTART               (_TIMER_DTCTRL_DTDAS_NORESTART << 1)  /**< Shifted mode NORESTART for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTDAS_RESTART                 (_TIMER_DTCTRL_DTDAS_RESTART << 1)    /**< Shifted mode RESTART for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTIPOL                        (0x1UL << 2)                          /**< DTI Inactive Polarity */
+#define _TIMER_DTCTRL_DTIPOL_SHIFT                 2                                     /**< Shift value for TIMER_DTIPOL */
+#define _TIMER_DTCTRL_DTIPOL_MASK                  0x4UL                                 /**< Bit mask for TIMER_DTIPOL */
+#define _TIMER_DTCTRL_DTIPOL_DEFAULT               0x00000000UL                          /**< Mode DEFAULT for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTIPOL_DEFAULT                (_TIMER_DTCTRL_DTIPOL_DEFAULT << 2)   /**< Shifted mode DEFAULT for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTCINV                        (0x1UL << 3)                          /**< DTI Complementary Output Invert. */
+#define _TIMER_DTCTRL_DTCINV_SHIFT                 3                                     /**< Shift value for TIMER_DTCINV */
+#define _TIMER_DTCTRL_DTCINV_MASK                  0x8UL                                 /**< Bit mask for TIMER_DTCINV */
+#define _TIMER_DTCTRL_DTCINV_DEFAULT               0x00000000UL                          /**< Mode DEFAULT for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTCINV_DEFAULT                (_TIMER_DTCTRL_DTCINV_DEFAULT << 3)   /**< Shifted mode DEFAULT for TIMER_DTCTRL */
+#define _TIMER_DTCTRL_DTPRSSEL_SHIFT               4                                     /**< Shift value for TIMER_DTPRSSEL */
+#define _TIMER_DTCTRL_DTPRSSEL_MASK                0xF0UL                                /**< Bit mask for TIMER_DTPRSSEL */
+#define _TIMER_DTCTRL_DTPRSSEL_DEFAULT             0x00000000UL                          /**< Mode DEFAULT for TIMER_DTCTRL */
+#define _TIMER_DTCTRL_DTPRSSEL_PRSCH0              0x00000000UL                          /**< Mode PRSCH0 for TIMER_DTCTRL */
+#define _TIMER_DTCTRL_DTPRSSEL_PRSCH1              0x00000001UL                          /**< Mode PRSCH1 for TIMER_DTCTRL */
+#define _TIMER_DTCTRL_DTPRSSEL_PRSCH2              0x00000002UL                          /**< Mode PRSCH2 for TIMER_DTCTRL */
+#define _TIMER_DTCTRL_DTPRSSEL_PRSCH3              0x00000003UL                          /**< Mode PRSCH3 for TIMER_DTCTRL */
+#define _TIMER_DTCTRL_DTPRSSEL_PRSCH4              0x00000004UL                          /**< Mode PRSCH4 for TIMER_DTCTRL */
+#define _TIMER_DTCTRL_DTPRSSEL_PRSCH5              0x00000005UL                          /**< Mode PRSCH5 for TIMER_DTCTRL */
+#define _TIMER_DTCTRL_DTPRSSEL_PRSCH6              0x00000006UL                          /**< Mode PRSCH6 for TIMER_DTCTRL */
+#define _TIMER_DTCTRL_DTPRSSEL_PRSCH7              0x00000007UL                          /**< Mode PRSCH7 for TIMER_DTCTRL */
+#define _TIMER_DTCTRL_DTPRSSEL_PRSCH8              0x00000008UL                          /**< Mode PRSCH8 for TIMER_DTCTRL */
+#define _TIMER_DTCTRL_DTPRSSEL_PRSCH9              0x00000009UL                          /**< Mode PRSCH9 for TIMER_DTCTRL */
+#define _TIMER_DTCTRL_DTPRSSEL_PRSCH10             0x0000000AUL                          /**< Mode PRSCH10 for TIMER_DTCTRL */
+#define _TIMER_DTCTRL_DTPRSSEL_PRSCH11             0x0000000BUL                          /**< Mode PRSCH11 for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTPRSSEL_DEFAULT              (_TIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTPRSSEL_PRSCH0               (_TIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4)  /**< Shifted mode PRSCH0 for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTPRSSEL_PRSCH1               (_TIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4)  /**< Shifted mode PRSCH1 for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTPRSSEL_PRSCH2               (_TIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4)  /**< Shifted mode PRSCH2 for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTPRSSEL_PRSCH3               (_TIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4)  /**< Shifted mode PRSCH3 for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTPRSSEL_PRSCH4               (_TIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4)  /**< Shifted mode PRSCH4 for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTPRSSEL_PRSCH5               (_TIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4)  /**< Shifted mode PRSCH5 for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTPRSSEL_PRSCH6               (_TIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4)  /**< Shifted mode PRSCH6 for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTPRSSEL_PRSCH7               (_TIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4)  /**< Shifted mode PRSCH7 for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTPRSSEL_PRSCH8               (_TIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4)  /**< Shifted mode PRSCH8 for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTPRSSEL_PRSCH9               (_TIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4)  /**< Shifted mode PRSCH9 for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTPRSSEL_PRSCH10              (_TIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTPRSSEL_PRSCH11              (_TIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTAR                          (0x1UL << 9)                          /**< DTI Always Run */
+#define _TIMER_DTCTRL_DTAR_SHIFT                   9                                     /**< Shift value for TIMER_DTAR */
+#define _TIMER_DTCTRL_DTAR_MASK                    0x200UL                               /**< Bit mask for TIMER_DTAR */
+#define _TIMER_DTCTRL_DTAR_DEFAULT                 0x00000000UL                          /**< Mode DEFAULT for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTAR_DEFAULT                  (_TIMER_DTCTRL_DTAR_DEFAULT << 9)     /**< Shifted mode DEFAULT for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTFATS                        (0x1UL << 10)                         /**< DTI Fault Action on Timer Stop */
+#define _TIMER_DTCTRL_DTFATS_SHIFT                 10                                    /**< Shift value for TIMER_DTFATS */
+#define _TIMER_DTCTRL_DTFATS_MASK                  0x400UL                               /**< Bit mask for TIMER_DTFATS */
+#define _TIMER_DTCTRL_DTFATS_DEFAULT               0x00000000UL                          /**< Mode DEFAULT for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTFATS_DEFAULT                (_TIMER_DTCTRL_DTFATS_DEFAULT << 10)  /**< Shifted mode DEFAULT for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTPRSEN                       (0x1UL << 24)                         /**< DTI PRS Source Enable */
+#define _TIMER_DTCTRL_DTPRSEN_SHIFT                24                                    /**< Shift value for TIMER_DTPRSEN */
+#define _TIMER_DTCTRL_DTPRSEN_MASK                 0x1000000UL                           /**< Bit mask for TIMER_DTPRSEN */
+#define _TIMER_DTCTRL_DTPRSEN_DEFAULT              0x00000000UL                          /**< Mode DEFAULT for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTPRSEN_DEFAULT               (_TIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_DTCTRL */
+
+/* Bit fields for TIMER DTTIME */
+#define _TIMER_DTTIME_RESETVALUE                   0x00000000UL                          /**< Default value for TIMER_DTTIME */
+#define _TIMER_DTTIME_MASK                         0x003F3F0FUL                          /**< Mask for TIMER_DTTIME */
+#define _TIMER_DTTIME_DTPRESC_SHIFT                0                                     /**< Shift value for TIMER_DTPRESC */
+#define _TIMER_DTTIME_DTPRESC_MASK                 0xFUL                                 /**< Bit mask for TIMER_DTPRESC */
+#define _TIMER_DTTIME_DTPRESC_DEFAULT              0x00000000UL                          /**< Mode DEFAULT for TIMER_DTTIME */
+#define _TIMER_DTTIME_DTPRESC_DIV1                 0x00000000UL                          /**< Mode DIV1 for TIMER_DTTIME */
+#define _TIMER_DTTIME_DTPRESC_DIV2                 0x00000001UL                          /**< Mode DIV2 for TIMER_DTTIME */
+#define _TIMER_DTTIME_DTPRESC_DIV4                 0x00000002UL                          /**< Mode DIV4 for TIMER_DTTIME */
+#define _TIMER_DTTIME_DTPRESC_DIV8                 0x00000003UL                          /**< Mode DIV8 for TIMER_DTTIME */
+#define _TIMER_DTTIME_DTPRESC_DIV16                0x00000004UL                          /**< Mode DIV16 for TIMER_DTTIME */
+#define _TIMER_DTTIME_DTPRESC_DIV32                0x00000005UL                          /**< Mode DIV32 for TIMER_DTTIME */
+#define _TIMER_DTTIME_DTPRESC_DIV64                0x00000006UL                          /**< Mode DIV64 for TIMER_DTTIME */
+#define _TIMER_DTTIME_DTPRESC_DIV128               0x00000007UL                          /**< Mode DIV128 for TIMER_DTTIME */
+#define _TIMER_DTTIME_DTPRESC_DIV256               0x00000008UL                          /**< Mode DIV256 for TIMER_DTTIME */
+#define _TIMER_DTTIME_DTPRESC_DIV512               0x00000009UL                          /**< Mode DIV512 for TIMER_DTTIME */
+#define _TIMER_DTTIME_DTPRESC_DIV1024              0x0000000AUL                          /**< Mode DIV1024 for TIMER_DTTIME */
+#define TIMER_DTTIME_DTPRESC_DEFAULT               (_TIMER_DTTIME_DTPRESC_DEFAULT << 0)  /**< Shifted mode DEFAULT for TIMER_DTTIME */
+#define TIMER_DTTIME_DTPRESC_DIV1                  (_TIMER_DTTIME_DTPRESC_DIV1 << 0)     /**< Shifted mode DIV1 for TIMER_DTTIME */
+#define TIMER_DTTIME_DTPRESC_DIV2                  (_TIMER_DTTIME_DTPRESC_DIV2 << 0)     /**< Shifted mode DIV2 for TIMER_DTTIME */
+#define TIMER_DTTIME_DTPRESC_DIV4                  (_TIMER_DTTIME_DTPRESC_DIV4 << 0)     /**< Shifted mode DIV4 for TIMER_DTTIME */
+#define TIMER_DTTIME_DTPRESC_DIV8                  (_TIMER_DTTIME_DTPRESC_DIV8 << 0)     /**< Shifted mode DIV8 for TIMER_DTTIME */
+#define TIMER_DTTIME_DTPRESC_DIV16                 (_TIMER_DTTIME_DTPRESC_DIV16 << 0)    /**< Shifted mode DIV16 for TIMER_DTTIME */
+#define TIMER_DTTIME_DTPRESC_DIV32                 (_TIMER_DTTIME_DTPRESC_DIV32 << 0)    /**< Shifted mode DIV32 for TIMER_DTTIME */
+#define TIMER_DTTIME_DTPRESC_DIV64                 (_TIMER_DTTIME_DTPRESC_DIV64 << 0)    /**< Shifted mode DIV64 for TIMER_DTTIME */
+#define TIMER_DTTIME_DTPRESC_DIV128                (_TIMER_DTTIME_DTPRESC_DIV128 << 0)   /**< Shifted mode DIV128 for TIMER_DTTIME */
+#define TIMER_DTTIME_DTPRESC_DIV256                (_TIMER_DTTIME_DTPRESC_DIV256 << 0)   /**< Shifted mode DIV256 for TIMER_DTTIME */
+#define TIMER_DTTIME_DTPRESC_DIV512                (_TIMER_DTTIME_DTPRESC_DIV512 << 0)   /**< Shifted mode DIV512 for TIMER_DTTIME */
+#define TIMER_DTTIME_DTPRESC_DIV1024               (_TIMER_DTTIME_DTPRESC_DIV1024 << 0)  /**< Shifted mode DIV1024 for TIMER_DTTIME */
+#define _TIMER_DTTIME_DTRISET_SHIFT                8                                     /**< Shift value for TIMER_DTRISET */
+#define _TIMER_DTTIME_DTRISET_MASK                 0x3F00UL                              /**< Bit mask for TIMER_DTRISET */
+#define _TIMER_DTTIME_DTRISET_DEFAULT              0x00000000UL                          /**< Mode DEFAULT for TIMER_DTTIME */
+#define TIMER_DTTIME_DTRISET_DEFAULT               (_TIMER_DTTIME_DTRISET_DEFAULT << 8)  /**< Shifted mode DEFAULT for TIMER_DTTIME */
+#define _TIMER_DTTIME_DTFALLT_SHIFT                16                                    /**< Shift value for TIMER_DTFALLT */
+#define _TIMER_DTTIME_DTFALLT_MASK                 0x3F0000UL                            /**< Bit mask for TIMER_DTFALLT */
+#define _TIMER_DTTIME_DTFALLT_DEFAULT              0x00000000UL                          /**< Mode DEFAULT for TIMER_DTTIME */
+#define TIMER_DTTIME_DTFALLT_DEFAULT               (_TIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_DTTIME */
+
+/* Bit fields for TIMER DTFC */
+#define _TIMER_DTFC_RESETVALUE                     0x00000000UL                            /**< Default value for TIMER_DTFC */
+#define _TIMER_DTFC_MASK                           0x0F030F0FUL                            /**< Mask for TIMER_DTFC */
+#define _TIMER_DTFC_DTPRS0FSEL_SHIFT               0                                       /**< Shift value for TIMER_DTPRS0FSEL */
+#define _TIMER_DTFC_DTPRS0FSEL_MASK                0xFUL                                   /**< Bit mask for TIMER_DTPRS0FSEL */
+#define _TIMER_DTFC_DTPRS0FSEL_DEFAULT             0x00000000UL                            /**< Mode DEFAULT for TIMER_DTFC */
+#define _TIMER_DTFC_DTPRS0FSEL_PRSCH0              0x00000000UL                            /**< Mode PRSCH0 for TIMER_DTFC */
+#define _TIMER_DTFC_DTPRS0FSEL_PRSCH1              0x00000001UL                            /**< Mode PRSCH1 for TIMER_DTFC */
+#define _TIMER_DTFC_DTPRS0FSEL_PRSCH2              0x00000002UL                            /**< Mode PRSCH2 for TIMER_DTFC */
+#define _TIMER_DTFC_DTPRS0FSEL_PRSCH3              0x00000003UL                            /**< Mode PRSCH3 for TIMER_DTFC */
+#define _TIMER_DTFC_DTPRS0FSEL_PRSCH4              0x00000004UL                            /**< Mode PRSCH4 for TIMER_DTFC */
+#define _TIMER_DTFC_DTPRS0FSEL_PRSCH5              0x00000005UL                            /**< Mode PRSCH5 for TIMER_DTFC */
+#define _TIMER_DTFC_DTPRS0FSEL_PRSCH6              0x00000006UL                            /**< Mode PRSCH6 for TIMER_DTFC */
+#define _TIMER_DTFC_DTPRS0FSEL_PRSCH7              0x00000007UL                            /**< Mode PRSCH7 for TIMER_DTFC */
+#define _TIMER_DTFC_DTPRS0FSEL_PRSCH8              0x00000008UL                            /**< Mode PRSCH8 for TIMER_DTFC */
+#define _TIMER_DTFC_DTPRS0FSEL_PRSCH9              0x00000009UL                            /**< Mode PRSCH9 for TIMER_DTFC */
+#define _TIMER_DTFC_DTPRS0FSEL_PRSCH10             0x0000000AUL                            /**< Mode PRSCH10 for TIMER_DTFC */
+#define _TIMER_DTFC_DTPRS0FSEL_PRSCH11             0x0000000BUL                            /**< Mode PRSCH11 for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS0FSEL_DEFAULT              (_TIMER_DTFC_DTPRS0FSEL_DEFAULT << 0)   /**< Shifted mode DEFAULT for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS0FSEL_PRSCH0               (_TIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0)    /**< Shifted mode PRSCH0 for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS0FSEL_PRSCH1               (_TIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0)    /**< Shifted mode PRSCH1 for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS0FSEL_PRSCH2               (_TIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0)    /**< Shifted mode PRSCH2 for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS0FSEL_PRSCH3               (_TIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0)    /**< Shifted mode PRSCH3 for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS0FSEL_PRSCH4               (_TIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0)    /**< Shifted mode PRSCH4 for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS0FSEL_PRSCH5               (_TIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0)    /**< Shifted mode PRSCH5 for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS0FSEL_PRSCH6               (_TIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0)    /**< Shifted mode PRSCH6 for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS0FSEL_PRSCH7               (_TIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0)    /**< Shifted mode PRSCH7 for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS0FSEL_PRSCH8               (_TIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0)    /**< Shifted mode PRSCH8 for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS0FSEL_PRSCH9               (_TIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0)    /**< Shifted mode PRSCH9 for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS0FSEL_PRSCH10              (_TIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0)   /**< Shifted mode PRSCH10 for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS0FSEL_PRSCH11              (_TIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0)   /**< Shifted mode PRSCH11 for TIMER_DTFC */
+#define _TIMER_DTFC_DTPRS1FSEL_SHIFT               8                                       /**< Shift value for TIMER_DTPRS1FSEL */
+#define _TIMER_DTFC_DTPRS1FSEL_MASK                0xF00UL                                 /**< Bit mask for TIMER_DTPRS1FSEL */
+#define _TIMER_DTFC_DTPRS1FSEL_DEFAULT             0x00000000UL                            /**< Mode DEFAULT for TIMER_DTFC */
+#define _TIMER_DTFC_DTPRS1FSEL_PRSCH0              0x00000000UL                            /**< Mode PRSCH0 for TIMER_DTFC */
+#define _TIMER_DTFC_DTPRS1FSEL_PRSCH1              0x00000001UL                            /**< Mode PRSCH1 for TIMER_DTFC */
+#define _TIMER_DTFC_DTPRS1FSEL_PRSCH2              0x00000002UL                            /**< Mode PRSCH2 for TIMER_DTFC */
+#define _TIMER_DTFC_DTPRS1FSEL_PRSCH3              0x00000003UL                            /**< Mode PRSCH3 for TIMER_DTFC */
+#define _TIMER_DTFC_DTPRS1FSEL_PRSCH4              0x00000004UL                            /**< Mode PRSCH4 for TIMER_DTFC */
+#define _TIMER_DTFC_DTPRS1FSEL_PRSCH5              0x00000005UL                            /**< Mode PRSCH5 for TIMER_DTFC */
+#define _TIMER_DTFC_DTPRS1FSEL_PRSCH6              0x00000006UL                            /**< Mode PRSCH6 for TIMER_DTFC */
+#define _TIMER_DTFC_DTPRS1FSEL_PRSCH7              0x00000007UL                            /**< Mode PRSCH7 for TIMER_DTFC */
+#define _TIMER_DTFC_DTPRS1FSEL_PRSCH8              0x00000008UL                            /**< Mode PRSCH8 for TIMER_DTFC */
+#define _TIMER_DTFC_DTPRS1FSEL_PRSCH9              0x00000009UL                            /**< Mode PRSCH9 for TIMER_DTFC */
+#define _TIMER_DTFC_DTPRS1FSEL_PRSCH10             0x0000000AUL                            /**< Mode PRSCH10 for TIMER_DTFC */
+#define _TIMER_DTFC_DTPRS1FSEL_PRSCH11             0x0000000BUL                            /**< Mode PRSCH11 for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS1FSEL_DEFAULT              (_TIMER_DTFC_DTPRS1FSEL_DEFAULT << 8)   /**< Shifted mode DEFAULT for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS1FSEL_PRSCH0               (_TIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8)    /**< Shifted mode PRSCH0 for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS1FSEL_PRSCH1               (_TIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8)    /**< Shifted mode PRSCH1 for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS1FSEL_PRSCH2               (_TIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8)    /**< Shifted mode PRSCH2 for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS1FSEL_PRSCH3               (_TIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8)    /**< Shifted mode PRSCH3 for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS1FSEL_PRSCH4               (_TIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8)    /**< Shifted mode PRSCH4 for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS1FSEL_PRSCH5               (_TIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8)    /**< Shifted mode PRSCH5 for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS1FSEL_PRSCH6               (_TIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8)    /**< Shifted mode PRSCH6 for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS1FSEL_PRSCH7               (_TIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8)    /**< Shifted mode PRSCH7 for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS1FSEL_PRSCH8               (_TIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8)    /**< Shifted mode PRSCH8 for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS1FSEL_PRSCH9               (_TIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8)    /**< Shifted mode PRSCH9 for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS1FSEL_PRSCH10              (_TIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8)   /**< Shifted mode PRSCH10 for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS1FSEL_PRSCH11              (_TIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8)   /**< Shifted mode PRSCH11 for TIMER_DTFC */
+#define _TIMER_DTFC_DTFA_SHIFT                     16                                      /**< Shift value for TIMER_DTFA */
+#define _TIMER_DTFC_DTFA_MASK                      0x30000UL                               /**< Bit mask for TIMER_DTFA */
+#define _TIMER_DTFC_DTFA_DEFAULT                   0x00000000UL                            /**< Mode DEFAULT for TIMER_DTFC */
+#define _TIMER_DTFC_DTFA_NONE                      0x00000000UL                            /**< Mode NONE for TIMER_DTFC */
+#define _TIMER_DTFC_DTFA_INACTIVE                  0x00000001UL                            /**< Mode INACTIVE for TIMER_DTFC */
+#define _TIMER_DTFC_DTFA_CLEAR                     0x00000002UL                            /**< Mode CLEAR for TIMER_DTFC */
+#define _TIMER_DTFC_DTFA_TRISTATE                  0x00000003UL                            /**< Mode TRISTATE for TIMER_DTFC */
+#define TIMER_DTFC_DTFA_DEFAULT                    (_TIMER_DTFC_DTFA_DEFAULT << 16)        /**< Shifted mode DEFAULT for TIMER_DTFC */
+#define TIMER_DTFC_DTFA_NONE                       (_TIMER_DTFC_DTFA_NONE << 16)           /**< Shifted mode NONE for TIMER_DTFC */
+#define TIMER_DTFC_DTFA_INACTIVE                   (_TIMER_DTFC_DTFA_INACTIVE << 16)       /**< Shifted mode INACTIVE for TIMER_DTFC */
+#define TIMER_DTFC_DTFA_CLEAR                      (_TIMER_DTFC_DTFA_CLEAR << 16)          /**< Shifted mode CLEAR for TIMER_DTFC */
+#define TIMER_DTFC_DTFA_TRISTATE                   (_TIMER_DTFC_DTFA_TRISTATE << 16)       /**< Shifted mode TRISTATE for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS0FEN                       (0x1UL << 24)                           /**< DTI PRS 0 Fault Enable */
+#define _TIMER_DTFC_DTPRS0FEN_SHIFT                24                                      /**< Shift value for TIMER_DTPRS0FEN */
+#define _TIMER_DTFC_DTPRS0FEN_MASK                 0x1000000UL                             /**< Bit mask for TIMER_DTPRS0FEN */
+#define _TIMER_DTFC_DTPRS0FEN_DEFAULT              0x00000000UL                            /**< Mode DEFAULT for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS0FEN_DEFAULT               (_TIMER_DTFC_DTPRS0FEN_DEFAULT << 24)   /**< Shifted mode DEFAULT for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS1FEN                       (0x1UL << 25)                           /**< DTI PRS 1 Fault Enable */
+#define _TIMER_DTFC_DTPRS1FEN_SHIFT                25                                      /**< Shift value for TIMER_DTPRS1FEN */
+#define _TIMER_DTFC_DTPRS1FEN_MASK                 0x2000000UL                             /**< Bit mask for TIMER_DTPRS1FEN */
+#define _TIMER_DTFC_DTPRS1FEN_DEFAULT              0x00000000UL                            /**< Mode DEFAULT for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS1FEN_DEFAULT               (_TIMER_DTFC_DTPRS1FEN_DEFAULT << 25)   /**< Shifted mode DEFAULT for TIMER_DTFC */
+#define TIMER_DTFC_DTDBGFEN                        (0x1UL << 26)                           /**< DTI Debugger Fault Enable */
+#define _TIMER_DTFC_DTDBGFEN_SHIFT                 26                                      /**< Shift value for TIMER_DTDBGFEN */
+#define _TIMER_DTFC_DTDBGFEN_MASK                  0x4000000UL                             /**< Bit mask for TIMER_DTDBGFEN */
+#define _TIMER_DTFC_DTDBGFEN_DEFAULT               0x00000000UL                            /**< Mode DEFAULT for TIMER_DTFC */
+#define TIMER_DTFC_DTDBGFEN_DEFAULT                (_TIMER_DTFC_DTDBGFEN_DEFAULT << 26)    /**< Shifted mode DEFAULT for TIMER_DTFC */
+#define TIMER_DTFC_DTLOCKUPFEN                     (0x1UL << 27)                           /**< DTI Lockup Fault Enable */
+#define _TIMER_DTFC_DTLOCKUPFEN_SHIFT              27                                      /**< Shift value for TIMER_DTLOCKUPFEN */
+#define _TIMER_DTFC_DTLOCKUPFEN_MASK               0x8000000UL                             /**< Bit mask for TIMER_DTLOCKUPFEN */
+#define _TIMER_DTFC_DTLOCKUPFEN_DEFAULT            0x00000000UL                            /**< Mode DEFAULT for TIMER_DTFC */
+#define TIMER_DTFC_DTLOCKUPFEN_DEFAULT             (_TIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for TIMER_DTFC */
+
+/* Bit fields for TIMER DTOGEN */
+#define _TIMER_DTOGEN_RESETVALUE                   0x00000000UL                             /**< Default value for TIMER_DTOGEN */
+#define _TIMER_DTOGEN_MASK                         0x0000003FUL                             /**< Mask for TIMER_DTOGEN */
+#define TIMER_DTOGEN_DTOGCC0EN                     (0x1UL << 0)                             /**< DTI CC0 Output Generation Enable */
+#define _TIMER_DTOGEN_DTOGCC0EN_SHIFT              0                                        /**< Shift value for TIMER_DTOGCC0EN */
+#define _TIMER_DTOGEN_DTOGCC0EN_MASK               0x1UL                                    /**< Bit mask for TIMER_DTOGCC0EN */
+#define _TIMER_DTOGEN_DTOGCC0EN_DEFAULT            0x00000000UL                             /**< Mode DEFAULT for TIMER_DTOGEN */
+#define TIMER_DTOGEN_DTOGCC0EN_DEFAULT             (_TIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0)   /**< Shifted mode DEFAULT for TIMER_DTOGEN */
+#define TIMER_DTOGEN_DTOGCC1EN                     (0x1UL << 1)                             /**< DTI CC1 Output Generation Enable */
+#define _TIMER_DTOGEN_DTOGCC1EN_SHIFT              1                                        /**< Shift value for TIMER_DTOGCC1EN */
+#define _TIMER_DTOGEN_DTOGCC1EN_MASK               0x2UL                                    /**< Bit mask for TIMER_DTOGCC1EN */
+#define _TIMER_DTOGEN_DTOGCC1EN_DEFAULT            0x00000000UL                             /**< Mode DEFAULT for TIMER_DTOGEN */
+#define TIMER_DTOGEN_DTOGCC1EN_DEFAULT             (_TIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1)   /**< Shifted mode DEFAULT for TIMER_DTOGEN */
+#define TIMER_DTOGEN_DTOGCC2EN                     (0x1UL << 2)                             /**< DTI CC2 Output Generation Enable */
+#define _TIMER_DTOGEN_DTOGCC2EN_SHIFT              2                                        /**< Shift value for TIMER_DTOGCC2EN */
+#define _TIMER_DTOGEN_DTOGCC2EN_MASK               0x4UL                                    /**< Bit mask for TIMER_DTOGCC2EN */
+#define _TIMER_DTOGEN_DTOGCC2EN_DEFAULT            0x00000000UL                             /**< Mode DEFAULT for TIMER_DTOGEN */
+#define TIMER_DTOGEN_DTOGCC2EN_DEFAULT             (_TIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2)   /**< Shifted mode DEFAULT for TIMER_DTOGEN */
+#define TIMER_DTOGEN_DTOGCDTI0EN                   (0x1UL << 3)                             /**< DTI CDTI0 Output Generation Enable */
+#define _TIMER_DTOGEN_DTOGCDTI0EN_SHIFT            3                                        /**< Shift value for TIMER_DTOGCDTI0EN */
+#define _TIMER_DTOGEN_DTOGCDTI0EN_MASK             0x8UL                                    /**< Bit mask for TIMER_DTOGCDTI0EN */
+#define _TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT          0x00000000UL                             /**< Mode DEFAULT for TIMER_DTOGEN */
+#define TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT           (_TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTOGEN */
+#define TIMER_DTOGEN_DTOGCDTI1EN                   (0x1UL << 4)                             /**< DTI CDTI1 Output Generation Enable */
+#define _TIMER_DTOGEN_DTOGCDTI1EN_SHIFT            4                                        /**< Shift value for TIMER_DTOGCDTI1EN */
+#define _TIMER_DTOGEN_DTOGCDTI1EN_MASK             0x10UL                                   /**< Bit mask for TIMER_DTOGCDTI1EN */
+#define _TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT          0x00000000UL                             /**< Mode DEFAULT for TIMER_DTOGEN */
+#define TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT           (_TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTOGEN */
+#define TIMER_DTOGEN_DTOGCDTI2EN                   (0x1UL << 5)                             /**< DTI CDTI2 Output Generation Enable */
+#define _TIMER_DTOGEN_DTOGCDTI2EN_SHIFT            5                                        /**< Shift value for TIMER_DTOGCDTI2EN */
+#define _TIMER_DTOGEN_DTOGCDTI2EN_MASK             0x20UL                                   /**< Bit mask for TIMER_DTOGCDTI2EN */
+#define _TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT          0x00000000UL                             /**< Mode DEFAULT for TIMER_DTOGEN */
+#define TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT           (_TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_DTOGEN */
+
+/* Bit fields for TIMER DTFAULT */
+#define _TIMER_DTFAULT_RESETVALUE                  0x00000000UL                            /**< Default value for TIMER_DTFAULT */
+#define _TIMER_DTFAULT_MASK                        0x0000000FUL                            /**< Mask for TIMER_DTFAULT */
+#define TIMER_DTFAULT_DTPRS0F                      (0x1UL << 0)                            /**< DTI PRS 0 Fault */
+#define _TIMER_DTFAULT_DTPRS0F_SHIFT               0                                       /**< Shift value for TIMER_DTPRS0F */
+#define _TIMER_DTFAULT_DTPRS0F_MASK                0x1UL                                   /**< Bit mask for TIMER_DTPRS0F */
+#define _TIMER_DTFAULT_DTPRS0F_DEFAULT             0x00000000UL                            /**< Mode DEFAULT for TIMER_DTFAULT */
+#define TIMER_DTFAULT_DTPRS0F_DEFAULT              (_TIMER_DTFAULT_DTPRS0F_DEFAULT << 0)   /**< Shifted mode DEFAULT for TIMER_DTFAULT */
+#define TIMER_DTFAULT_DTPRS1F                      (0x1UL << 1)                            /**< DTI PRS 1 Fault */
+#define _TIMER_DTFAULT_DTPRS1F_SHIFT               1                                       /**< Shift value for TIMER_DTPRS1F */
+#define _TIMER_DTFAULT_DTPRS1F_MASK                0x2UL                                   /**< Bit mask for TIMER_DTPRS1F */
+#define _TIMER_DTFAULT_DTPRS1F_DEFAULT             0x00000000UL                            /**< Mode DEFAULT for TIMER_DTFAULT */
+#define TIMER_DTFAULT_DTPRS1F_DEFAULT              (_TIMER_DTFAULT_DTPRS1F_DEFAULT << 1)   /**< Shifted mode DEFAULT for TIMER_DTFAULT */
+#define TIMER_DTFAULT_DTDBGF                       (0x1UL << 2)                            /**< DTI Debugger Fault */
+#define _TIMER_DTFAULT_DTDBGF_SHIFT                2                                       /**< Shift value for TIMER_DTDBGF */
+#define _TIMER_DTFAULT_DTDBGF_MASK                 0x4UL                                   /**< Bit mask for TIMER_DTDBGF */
+#define _TIMER_DTFAULT_DTDBGF_DEFAULT              0x00000000UL                            /**< Mode DEFAULT for TIMER_DTFAULT */
+#define TIMER_DTFAULT_DTDBGF_DEFAULT               (_TIMER_DTFAULT_DTDBGF_DEFAULT << 2)    /**< Shifted mode DEFAULT for TIMER_DTFAULT */
+#define TIMER_DTFAULT_DTLOCKUPF                    (0x1UL << 3)                            /**< DTI Lockup Fault */
+#define _TIMER_DTFAULT_DTLOCKUPF_SHIFT             3                                       /**< Shift value for TIMER_DTLOCKUPF */
+#define _TIMER_DTFAULT_DTLOCKUPF_MASK              0x8UL                                   /**< Bit mask for TIMER_DTLOCKUPF */
+#define _TIMER_DTFAULT_DTLOCKUPF_DEFAULT           0x00000000UL                            /**< Mode DEFAULT for TIMER_DTFAULT */
+#define TIMER_DTFAULT_DTLOCKUPF_DEFAULT            (_TIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTFAULT */
+
+/* Bit fields for TIMER DTFAULTC */
+#define _TIMER_DTFAULTC_RESETVALUE                 0x00000000UL                             /**< Default value for TIMER_DTFAULTC */
+#define _TIMER_DTFAULTC_MASK                       0x0000000FUL                             /**< Mask for TIMER_DTFAULTC */
+#define TIMER_DTFAULTC_DTPRS0FC                    (0x1UL << 0)                             /**< DTI PRS0 Fault Clear */
+#define _TIMER_DTFAULTC_DTPRS0FC_SHIFT             0                                        /**< Shift value for TIMER_DTPRS0FC */
+#define _TIMER_DTFAULTC_DTPRS0FC_MASK              0x1UL                                    /**< Bit mask for TIMER_DTPRS0FC */
+#define _TIMER_DTFAULTC_DTPRS0FC_DEFAULT           0x00000000UL                             /**< Mode DEFAULT for TIMER_DTFAULTC */
+#define TIMER_DTFAULTC_DTPRS0FC_DEFAULT            (_TIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0)  /**< Shifted mode DEFAULT for TIMER_DTFAULTC */
+#define TIMER_DTFAULTC_DTPRS1FC                    (0x1UL << 1)                             /**< DTI PRS1 Fault Clear */
+#define _TIMER_DTFAULTC_DTPRS1FC_SHIFT             1                                        /**< Shift value for TIMER_DTPRS1FC */
+#define _TIMER_DTFAULTC_DTPRS1FC_MASK              0x2UL                                    /**< Bit mask for TIMER_DTPRS1FC */
+#define _TIMER_DTFAULTC_DTPRS1FC_DEFAULT           0x00000000UL                             /**< Mode DEFAULT for TIMER_DTFAULTC */
+#define TIMER_DTFAULTC_DTPRS1FC_DEFAULT            (_TIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1)  /**< Shifted mode DEFAULT for TIMER_DTFAULTC */
+#define TIMER_DTFAULTC_DTDBGFC                     (0x1UL << 2)                             /**< DTI Debugger Fault Clear */
+#define _TIMER_DTFAULTC_DTDBGFC_SHIFT              2                                        /**< Shift value for TIMER_DTDBGFC */
+#define _TIMER_DTFAULTC_DTDBGFC_MASK               0x4UL                                    /**< Bit mask for TIMER_DTDBGFC */
+#define _TIMER_DTFAULTC_DTDBGFC_DEFAULT            0x00000000UL                             /**< Mode DEFAULT for TIMER_DTFAULTC */
+#define TIMER_DTFAULTC_DTDBGFC_DEFAULT             (_TIMER_DTFAULTC_DTDBGFC_DEFAULT << 2)   /**< Shifted mode DEFAULT for TIMER_DTFAULTC */
+#define TIMER_DTFAULTC_TLOCKUPFC                   (0x1UL << 3)                             /**< DTI Lockup Fault Clear */
+#define _TIMER_DTFAULTC_TLOCKUPFC_SHIFT            3                                        /**< Shift value for TIMER_TLOCKUPFC */
+#define _TIMER_DTFAULTC_TLOCKUPFC_MASK             0x8UL                                    /**< Bit mask for TIMER_TLOCKUPFC */
+#define _TIMER_DTFAULTC_TLOCKUPFC_DEFAULT          0x00000000UL                             /**< Mode DEFAULT for TIMER_DTFAULTC */
+#define TIMER_DTFAULTC_TLOCKUPFC_DEFAULT           (_TIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */
+
+/* Bit fields for TIMER DTLOCK */
+#define _TIMER_DTLOCK_RESETVALUE                   0x00000000UL                          /**< Default value for TIMER_DTLOCK */
+#define _TIMER_DTLOCK_MASK                         0x0000FFFFUL                          /**< Mask for TIMER_DTLOCK */
+#define _TIMER_DTLOCK_LOCKKEY_SHIFT                0                                     /**< Shift value for TIMER_LOCKKEY */
+#define _TIMER_DTLOCK_LOCKKEY_MASK                 0xFFFFUL                              /**< Bit mask for TIMER_LOCKKEY */
+#define _TIMER_DTLOCK_LOCKKEY_DEFAULT              0x00000000UL                          /**< Mode DEFAULT for TIMER_DTLOCK */
+#define _TIMER_DTLOCK_LOCKKEY_LOCK                 0x00000000UL                          /**< Mode LOCK for TIMER_DTLOCK */
+#define _TIMER_DTLOCK_LOCKKEY_UNLOCKED             0x00000000UL                          /**< Mode UNLOCKED for TIMER_DTLOCK */
+#define _TIMER_DTLOCK_LOCKKEY_LOCKED               0x00000001UL                          /**< Mode LOCKED for TIMER_DTLOCK */
+#define _TIMER_DTLOCK_LOCKKEY_UNLOCK               0x0000CE80UL                          /**< Mode UNLOCK for TIMER_DTLOCK */
+#define TIMER_DTLOCK_LOCKKEY_DEFAULT               (_TIMER_DTLOCK_LOCKKEY_DEFAULT << 0)  /**< Shifted mode DEFAULT for TIMER_DTLOCK */
+#define TIMER_DTLOCK_LOCKKEY_LOCK                  (_TIMER_DTLOCK_LOCKKEY_LOCK << 0)     /**< Shifted mode LOCK for TIMER_DTLOCK */
+#define TIMER_DTLOCK_LOCKKEY_UNLOCKED              (_TIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for TIMER_DTLOCK */
+#define TIMER_DTLOCK_LOCKKEY_LOCKED                (_TIMER_DTLOCK_LOCKKEY_LOCKED << 0)   /**< Shifted mode LOCKED for TIMER_DTLOCK */
+#define TIMER_DTLOCK_LOCKKEY_UNLOCK                (_TIMER_DTLOCK_LOCKKEY_UNLOCK << 0)   /**< Shifted mode UNLOCK for TIMER_DTLOCK */
+
+/** @} End of group EFM32PG1B_TIMER */
+/** @} End of group Parts */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG_STK3401/efm32pg1b_timer_cc.h	Fri Jan 15 07:45:16 2016 +0000
@@ -0,0 +1,49 @@
+/**************************************************************************//**
+ * @file efm32pg1b_timer_cc.h
+ * @brief EFM32PG1B_TIMER_CC register and bit field definitions
+ * @version 4.2.0
+ ******************************************************************************
+ * @section License
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ ******************************************************************************
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software.@n
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.@n
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is
+ * providing the Software "AS IS", with no express or implied warranties of any
+ * kind, including, but not limited to, any implied warranties of
+ * merchantability or fitness for any particular purpose or warranties against
+ * infringement of any proprietary rights of a third party.
+ *
+ * Silicon Laboratories, Inc. will not be liable for any consequential,
+ * incidental, or special damages, or any other relief, or for any claim by
+ * any third party, arising from your use of this Software.
+ *
+ *****************************************************************************/
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @brief TIMER_CC EFM32PG1B TIMER CC
+ *****************************************************************************/
+typedef struct
+{
+  __IO uint32_t CTRL; /**< CC Channel Control Register  */
+  __IO uint32_t CCV;  /**< CC Channel Value Register  */
+  __I uint32_t  CCVP; /**< CC Channel Value Peek Register  */
+  __IO uint32_t CCVB; /**< CC Channel Buffer Register  */
+} TIMER_CC_TypeDef;
+
+/** @} End of group Parts */
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG_STK3401/efm32pg1b_usart.h	Fri Jan 15 07:45:16 2016 +0000
@@ -0,0 +1,1972 @@
+/**************************************************************************//**
+ * @file efm32pg1b_usart.h
+ * @brief EFM32PG1B_USART register and bit field definitions
+ * @version 4.2.0
+ ******************************************************************************
+ * @section License
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ ******************************************************************************
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software.@n
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.@n
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is
+ * providing the Software "AS IS", with no express or implied warranties of any
+ * kind, including, but not limited to, any implied warranties of
+ * merchantability or fitness for any particular purpose or warranties against
+ * infringement of any proprietary rights of a third party.
+ *
+ * Silicon Laboratories, Inc. will not be liable for any consequential,
+ * incidental, or special damages, or any other relief, or for any claim by
+ * any third party, arising from your use of this Software.
+ *
+ *****************************************************************************/
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFM32PG1B_USART
+ * @{
+ * @brief EFM32PG1B_USART Register Declaration
+ *****************************************************************************/
+typedef struct
+{
+  __IO uint32_t CTRL;         /**< Control Register  */
+  __IO uint32_t FRAME;        /**< USART Frame Format Register  */
+  __IO uint32_t TRIGCTRL;     /**< USART Trigger Control register  */
+  __IO uint32_t CMD;          /**< Command Register  */
+  __I uint32_t  STATUS;       /**< USART Status Register  */
+  __IO uint32_t CLKDIV;       /**< Clock Control Register  */
+  __I uint32_t  RXDATAX;      /**< RX Buffer Data Extended Register  */
+  __I uint32_t  RXDATA;       /**< RX Buffer Data Register  */
+  __I uint32_t  RXDOUBLEX;    /**< RX Buffer Double Data Extended Register  */
+  __I uint32_t  RXDOUBLE;     /**< RX FIFO Double Data Register  */
+  __I uint32_t  RXDATAXP;     /**< RX Buffer Data Extended Peek Register  */
+  __I uint32_t  RXDOUBLEXP;   /**< RX Buffer Double Data Extended Peek Register  */
+  __IO uint32_t TXDATAX;      /**< TX Buffer Data Extended Register  */
+  __IO uint32_t TXDATA;       /**< TX Buffer Data Register  */
+  __IO uint32_t TXDOUBLEX;    /**< TX Buffer Double Data Extended Register  */
+  __IO uint32_t TXDOUBLE;     /**< TX Buffer Double Data Register  */
+  __I uint32_t  IF;           /**< Interrupt Flag Register  */
+  __IO uint32_t IFS;          /**< Interrupt Flag Set Register  */
+  __IO uint32_t IFC;          /**< Interrupt Flag Clear Register  */
+  __IO uint32_t IEN;          /**< Interrupt Enable Register  */
+  __IO uint32_t IRCTRL;       /**< IrDA Control Register  */
+  uint32_t      RESERVED0[1]; /**< Reserved for future use **/
+  __IO uint32_t INPUT;        /**< USART Input Register  */
+  __IO uint32_t I2SCTRL;      /**< I2S Control Register  */
+  __IO uint32_t TIMING;       /**< Timing Register  */
+  __IO uint32_t CTRLX;        /**< Control Register Extended  */
+  __IO uint32_t TIMECMP0;     /**< Used to generate interrupts and various delays  */
+  __IO uint32_t TIMECMP1;     /**< Used to generate interrupts and various delays  */
+  __IO uint32_t TIMECMP2;     /**< Used to generate interrupts and various delays  */
+  __IO uint32_t ROUTEPEN;     /**< I/O Routing Pin Enable Register  */
+  __IO uint32_t ROUTELOC0;    /**< I/O Routing Location Register  */
+  __IO uint32_t ROUTELOC1;    /**< I/O Routing Location Register  */
+} USART_TypeDef;              /** @} */
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B_USART_BitFields
+ * @{
+ *****************************************************************************/
+
+/* Bit fields for USART CTRL */
+#define _USART_CTRL_RESETVALUE                  0x00000000UL                             /**< Default value for USART_CTRL */
+#define _USART_CTRL_MASK                        0xF3FFFF7FUL                             /**< Mask for USART_CTRL */
+#define USART_CTRL_SYNC                         (0x1UL << 0)                             /**< USART Synchronous Mode */
+#define _USART_CTRL_SYNC_SHIFT                  0                                        /**< Shift value for USART_SYNC */
+#define _USART_CTRL_SYNC_MASK                   0x1UL                                    /**< Bit mask for USART_SYNC */
+#define _USART_CTRL_SYNC_DEFAULT                0x00000000UL                             /**< Mode DEFAULT for USART_CTRL */
+#define USART_CTRL_SYNC_DEFAULT                 (_USART_CTRL_SYNC_DEFAULT << 0)          /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_LOOPBK                       (0x1UL << 1)                             /**< Loopback Enable */
+#define _USART_CTRL_LOOPBK_SHIFT                1                                        /**< Shift value for USART_LOOPBK */
+#define _USART_CTRL_LOOPBK_MASK                 0x2UL                                    /**< Bit mask for USART_LOOPBK */
+#define _USART_CTRL_LOOPBK_DEFAULT              0x00000000UL                             /**< Mode DEFAULT for USART_CTRL */
+#define USART_CTRL_LOOPBK_DEFAULT               (_USART_CTRL_LOOPBK_DEFAULT << 1)        /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_CCEN                         (0x1UL << 2)                             /**< Collision Check Enable */
+#define _USART_CTRL_CCEN_SHIFT                  2                                        /**< Shift value for USART_CCEN */
+#define _USART_CTRL_CCEN_MASK                   0x4UL                                    /**< Bit mask for USART_CCEN */
+#define _USART_CTRL_CCEN_DEFAULT                0x00000000UL                             /**< Mode DEFAULT for USART_CTRL */
+#define USART_CTRL_CCEN_DEFAULT                 (_USART_CTRL_CCEN_DEFAULT << 2)          /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_MPM                          (0x1UL << 3)                             /**< Multi-Processor Mode */
+#define _USART_CTRL_MPM_SHIFT                   3                                        /**< Shift value for USART_MPM */
+#define _USART_CTRL_MPM_MASK                    0x8UL                                    /**< Bit mask for USART_MPM */
+#define _USART_CTRL_MPM_DEFAULT                 0x00000000UL                             /**< Mode DEFAULT for USART_CTRL */
+#define USART_CTRL_MPM_DEFAULT                  (_USART_CTRL_MPM_DEFAULT << 3)           /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_MPAB                         (0x1UL << 4)                             /**< Multi-Processor Address-Bit */
+#define _USART_CTRL_MPAB_SHIFT                  4                                        /**< Shift value for USART_MPAB */
+#define _USART_CTRL_MPAB_MASK                   0x10UL                                   /**< Bit mask for USART_MPAB */
+#define _USART_CTRL_MPAB_DEFAULT                0x00000000UL                             /**< Mode DEFAULT for USART_CTRL */
+#define USART_CTRL_MPAB_DEFAULT                 (_USART_CTRL_MPAB_DEFAULT << 4)          /**< Shifted mode DEFAULT for USART_CTRL */
+#define _USART_CTRL_OVS_SHIFT                   5                                        /**< Shift value for USART_OVS */
+#define _USART_CTRL_OVS_MASK                    0x60UL                                   /**< Bit mask for USART_OVS */
+#define _USART_CTRL_OVS_DEFAULT                 0x00000000UL                             /**< Mode DEFAULT for USART_CTRL */
+#define _USART_CTRL_OVS_X16                     0x00000000UL                             /**< Mode X16 for USART_CTRL */
+#define _USART_CTRL_OVS_X8                      0x00000001UL                             /**< Mode X8 for USART_CTRL */
+#define _USART_CTRL_OVS_X6                      0x00000002UL                             /**< Mode X6 for USART_CTRL */
+#define _USART_CTRL_OVS_X4                      0x00000003UL                             /**< Mode X4 for USART_CTRL */
+#define USART_CTRL_OVS_DEFAULT                  (_USART_CTRL_OVS_DEFAULT << 5)           /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_OVS_X16                      (_USART_CTRL_OVS_X16 << 5)               /**< Shifted mode X16 for USART_CTRL */
+#define USART_CTRL_OVS_X8                       (_USART_CTRL_OVS_X8 << 5)                /**< Shifted mode X8 for USART_CTRL */
+#define USART_CTRL_OVS_X6                       (_USART_CTRL_OVS_X6 << 5)                /**< Shifted mode X6 for USART_CTRL */
+#define USART_CTRL_OVS_X4                       (_USART_CTRL_OVS_X4 << 5)                /**< Shifted mode X4 for USART_CTRL */
+#define USART_CTRL_CLKPOL                       (0x1UL << 8)                             /**< Clock Polarity */
+#define _USART_CTRL_CLKPOL_SHIFT                8                                        /**< Shift value for USART_CLKPOL */
+#define _USART_CTRL_CLKPOL_MASK                 0x100UL                                  /**< Bit mask for USART_CLKPOL */
+#define _USART_CTRL_CLKPOL_DEFAULT              0x00000000UL                             /**< Mode DEFAULT for USART_CTRL */
+#define _USART_CTRL_CLKPOL_IDLELOW              0x00000000UL                             /**< Mode IDLELOW for USART_CTRL */
+#define _USART_CTRL_CLKPOL_IDLEHIGH             0x00000001UL                             /**< Mode IDLEHIGH for USART_CTRL */
+#define USART_CTRL_CLKPOL_DEFAULT               (_USART_CTRL_CLKPOL_DEFAULT << 8)        /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_CLKPOL_IDLELOW               (_USART_CTRL_CLKPOL_IDLELOW << 8)        /**< Shifted mode IDLELOW for USART_CTRL */
+#define USART_CTRL_CLKPOL_IDLEHIGH              (_USART_CTRL_CLKPOL_IDLEHIGH << 8)       /**< Shifted mode IDLEHIGH for USART_CTRL */
+#define USART_CTRL_CLKPHA                       (0x1UL << 9)                             /**< Clock Edge For Setup/Sample */
+#define _USART_CTRL_CLKPHA_SHIFT                9                                        /**< Shift value for USART_CLKPHA */
+#define _USART_CTRL_CLKPHA_MASK                 0x200UL                                  /**< Bit mask for USART_CLKPHA */
+#define _USART_CTRL_CLKPHA_DEFAULT              0x00000000UL                             /**< Mode DEFAULT for USART_CTRL */
+#define _USART_CTRL_CLKPHA_SAMPLELEADING        0x00000000UL                             /**< Mode SAMPLELEADING for USART_CTRL */
+#define _USART_CTRL_CLKPHA_SAMPLETRAILING       0x00000001UL                             /**< Mode SAMPLETRAILING for USART_CTRL */
+#define USART_CTRL_CLKPHA_DEFAULT               (_USART_CTRL_CLKPHA_DEFAULT << 9)        /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_CLKPHA_SAMPLELEADING         (_USART_CTRL_CLKPHA_SAMPLELEADING << 9)  /**< Shifted mode SAMPLELEADING for USART_CTRL */
+#define USART_CTRL_CLKPHA_SAMPLETRAILING        (_USART_CTRL_CLKPHA_SAMPLETRAILING << 9) /**< Shifted mode SAMPLETRAILING for USART_CTRL */
+#define USART_CTRL_MSBF                         (0x1UL << 10)                            /**< Most Significant Bit First */
+#define _USART_CTRL_MSBF_SHIFT                  10                                       /**< Shift value for USART_MSBF */
+#define _USART_CTRL_MSBF_MASK                   0x400UL                                  /**< Bit mask for USART_MSBF */
+#define _USART_CTRL_MSBF_DEFAULT                0x00000000UL                             /**< Mode DEFAULT for USART_CTRL */
+#define USART_CTRL_MSBF_DEFAULT                 (_USART_CTRL_MSBF_DEFAULT << 10)         /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_CSMA                         (0x1UL << 11)                            /**< Action On Slave-Select In Master Mode */
+#define _USART_CTRL_CSMA_SHIFT                  11                                       /**< Shift value for USART_CSMA */
+#define _USART_CTRL_CSMA_MASK                   0x800UL                                  /**< Bit mask for USART_CSMA */
+#define _USART_CTRL_CSMA_DEFAULT                0x00000000UL                             /**< Mode DEFAULT for USART_CTRL */
+#define _USART_CTRL_CSMA_NOACTION               0x00000000UL                             /**< Mode NOACTION for USART_CTRL */
+#define _USART_CTRL_CSMA_GOTOSLAVEMODE          0x00000001UL                             /**< Mode GOTOSLAVEMODE for USART_CTRL */
+#define USART_CTRL_CSMA_DEFAULT                 (_USART_CTRL_CSMA_DEFAULT << 11)         /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_CSMA_NOACTION                (_USART_CTRL_CSMA_NOACTION << 11)        /**< Shifted mode NOACTION for USART_CTRL */
+#define USART_CTRL_CSMA_GOTOSLAVEMODE           (_USART_CTRL_CSMA_GOTOSLAVEMODE << 11)   /**< Shifted mode GOTOSLAVEMODE for USART_CTRL */
+#define USART_CTRL_TXBIL                        (0x1UL << 12)                            /**< TX Buffer Interrupt Level */
+#define _USART_CTRL_TXBIL_SHIFT                 12                                       /**< Shift value for USART_TXBIL */
+#define _USART_CTRL_TXBIL_MASK                  0x1000UL                                 /**< Bit mask for USART_TXBIL */
+#define _USART_CTRL_TXBIL_DEFAULT               0x00000000UL                             /**< Mode DEFAULT for USART_CTRL */
+#define _USART_CTRL_TXBIL_EMPTY                 0x00000000UL                             /**< Mode EMPTY for USART_CTRL */
+#define _USART_CTRL_TXBIL_HALFFULL              0x00000001UL                             /**< Mode HALFFULL for USART_CTRL */
+#define USART_CTRL_TXBIL_DEFAULT                (_USART_CTRL_TXBIL_DEFAULT << 12)        /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_TXBIL_EMPTY                  (_USART_CTRL_TXBIL_EMPTY << 12)          /**< Shifted mode EMPTY for USART_CTRL */
+#define USART_CTRL_TXBIL_HALFFULL               (_USART_CTRL_TXBIL_HALFFULL << 12)       /**< Shifted mode HALFFULL for USART_CTRL */
+#define USART_CTRL_RXINV                        (0x1UL << 13)                            /**< Receiver Input Invert */
+#define _USART_CTRL_RXINV_SHIFT                 13                                       /**< Shift value for USART_RXINV */
+#define _USART_CTRL_RXINV_MASK                  0x2000UL                                 /**< Bit mask for USART_RXINV */
+#define _USART_CTRL_RXINV_DEFAULT               0x00000000UL                             /**< Mode DEFAULT for USART_CTRL */
+#define USART_CTRL_RXINV_DEFAULT                (_USART_CTRL_RXINV_DEFAULT << 13)        /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_TXINV                        (0x1UL << 14)                            /**< Transmitter output Invert */
+#define _USART_CTRL_TXINV_SHIFT                 14                                       /**< Shift value for USART_TXINV */
+#define _USART_CTRL_TXINV_MASK                  0x4000UL                                 /**< Bit mask for USART_TXINV */
+#define _USART_CTRL_TXINV_DEFAULT               0x00000000UL                             /**< Mode DEFAULT for USART_CTRL */
+#define USART_CTRL_TXINV_DEFAULT                (_USART_CTRL_TXINV_DEFAULT << 14)        /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_CSINV                        (0x1UL << 15)                            /**< Chip Select Invert */
+#define _USART_CTRL_CSINV_SHIFT                 15                                       /**< Shift value for USART_CSINV */
+#define _USART_CTRL_CSINV_MASK                  0x8000UL                                 /**< Bit mask for USART_CSINV */
+#define _USART_CTRL_CSINV_DEFAULT               0x00000000UL                             /**< Mode DEFAULT for USART_CTRL */
+#define USART_CTRL_CSINV_DEFAULT                (_USART_CTRL_CSINV_DEFAULT << 15)        /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_AUTOCS                       (0x1UL << 16)                            /**< Automatic Chip Select */
+#define _USART_CTRL_AUTOCS_SHIFT                16                                       /**< Shift value for USART_AUTOCS */
+#define _USART_CTRL_AUTOCS_MASK                 0x10000UL                                /**< Bit mask for USART_AUTOCS */
+#define _USART_CTRL_AUTOCS_DEFAULT              0x00000000UL                             /**< Mode DEFAULT for USART_CTRL */
+#define USART_CTRL_AUTOCS_DEFAULT               (_USART_CTRL_AUTOCS_DEFAULT << 16)       /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_AUTOTRI                      (0x1UL << 17)                            /**< Automatic TX Tristate */
+#define _USART_CTRL_AUTOTRI_SHIFT               17                                       /**< Shift value for USART_AUTOTRI */
+#define _USART_CTRL_AUTOTRI_MASK                0x20000UL                                /**< Bit mask for USART_AUTOTRI */
+#define _USART_CTRL_AUTOTRI_DEFAULT             0x00000000UL                             /**< Mode DEFAULT for USART_CTRL */
+#define USART_CTRL_AUTOTRI_DEFAULT              (_USART_CTRL_AUTOTRI_DEFAULT << 17)      /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_SCMODE                       (0x1UL << 18)                            /**< SmartCard Mode */
+#define _USART_CTRL_SCMODE_SHIFT                18                                       /**< Shift value for USART_SCMODE */
+#define _USART_CTRL_SCMODE_MASK                 0x40000UL                                /**< Bit mask for USART_SCMODE */
+#define _USART_CTRL_SCMODE_DEFAULT              0x00000000UL                             /**< Mode DEFAULT for USART_CTRL */
+#define USART_CTRL_SCMODE_DEFAULT               (_USART_CTRL_SCMODE_DEFAULT << 18)       /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_SCRETRANS                    (0x1UL << 19)                            /**< SmartCard Retransmit */
+#define _USART_CTRL_SCRETRANS_SHIFT             19                                       /**< Shift value for USART_SCRETRANS */
+#define _USART_CTRL_SCRETRANS_MASK              0x80000UL                                /**< Bit mask for USART_SCRETRANS */
+#define _USART_CTRL_SCRETRANS_DEFAULT           0x00000000UL                             /**< Mode DEFAULT for USART_CTRL */
+#define USART_CTRL_SCRETRANS_DEFAULT            (_USART_CTRL_SCRETRANS_DEFAULT << 19)    /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_SKIPPERRF                    (0x1UL << 20)                            /**< Skip Parity Error Frames */
+#define _USART_CTRL_SKIPPERRF_SHIFT             20                                       /**< Shift value for USART_SKIPPERRF */
+#define _USART_CTRL_SKIPPERRF_MASK              0x100000UL                               /**< Bit mask for USART_SKIPPERRF */
+#define _USART_CTRL_SKIPPERRF_DEFAULT           0x00000000UL                             /**< Mode DEFAULT for USART_CTRL */
+#define USART_CTRL_SKIPPERRF_DEFAULT            (_USART_CTRL_SKIPPERRF_DEFAULT << 20)    /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_BIT8DV                       (0x1UL << 21)                            /**< Bit 8 Default Value */
+#define _USART_CTRL_BIT8DV_SHIFT                21                                       /**< Shift value for USART_BIT8DV */
+#define _USART_CTRL_BIT8DV_MASK                 0x200000UL                               /**< Bit mask for USART_BIT8DV */
+#define _USART_CTRL_BIT8DV_DEFAULT              0x00000000UL                             /**< Mode DEFAULT for USART_CTRL */
+#define USART_CTRL_BIT8DV_DEFAULT               (_USART_CTRL_BIT8DV_DEFAULT << 21)       /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_ERRSDMA                      (0x1UL << 22)                            /**< Halt DMA On Error */
+#define _USART_CTRL_ERRSDMA_SHIFT               22                                       /**< Shift value for USART_ERRSDMA */
+#define _USART_CTRL_ERRSDMA_MASK                0x400000UL                               /**< Bit mask for USART_ERRSDMA */
+#define _USART_CTRL_ERRSDMA_DEFAULT             0x00000000UL                             /**< Mode DEFAULT for USART_CTRL */
+#define USART_CTRL_ERRSDMA_DEFAULT              (_USART_CTRL_ERRSDMA_DEFAULT << 22)      /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_ERRSRX                       (0x1UL << 23)                            /**< Disable RX On Error */
+#define _USART_CTRL_ERRSRX_SHIFT                23                                       /**< Shift value for USART_ERRSRX */
+#define _USART_CTRL_ERRSRX_MASK                 0x800000UL                               /**< Bit mask for USART_ERRSRX */
+#define _USART_CTRL_ERRSRX_DEFAULT              0x00000000UL                             /**< Mode DEFAULT for USART_CTRL */
+#define USART_CTRL_ERRSRX_DEFAULT               (_USART_CTRL_ERRSRX_DEFAULT << 23)       /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_ERRSTX                       (0x1UL << 24)                            /**< Disable TX On Error */
+#define _USART_CTRL_ERRSTX_SHIFT                24                                       /**< Shift value for USART_ERRSTX */
+#define _USART_CTRL_ERRSTX_MASK                 0x1000000UL                              /**< Bit mask for USART_ERRSTX */
+#define _USART_CTRL_ERRSTX_DEFAULT              0x00000000UL                             /**< Mode DEFAULT for USART_CTRL */
+#define USART_CTRL_ERRSTX_DEFAULT               (_USART_CTRL_ERRSTX_DEFAULT << 24)       /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_SSSEARLY                     (0x1UL << 25)                            /**< Synchronous Slave Setup Early */
+#define _USART_CTRL_SSSEARLY_SHIFT              25                                       /**< Shift value for USART_SSSEARLY */
+#define _USART_CTRL_SSSEARLY_MASK               0x2000000UL                              /**< Bit mask for USART_SSSEARLY */
+#define _USART_CTRL_SSSEARLY_DEFAULT            0x00000000UL                             /**< Mode DEFAULT for USART_CTRL */
+#define USART_CTRL_SSSEARLY_DEFAULT             (_USART_CTRL_SSSEARLY_DEFAULT << 25)     /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_BYTESWAP                     (0x1UL << 28)                            /**< Byteswap In Double Accesses */
+#define _USART_CTRL_BYTESWAP_SHIFT              28                                       /**< Shift value for USART_BYTESWAP */
+#define _USART_CTRL_BYTESWAP_MASK               0x10000000UL                             /**< Bit mask for USART_BYTESWAP */
+#define _USART_CTRL_BYTESWAP_DEFAULT            0x00000000UL                             /**< Mode DEFAULT for USART_CTRL */
+#define USART_CTRL_BYTESWAP_DEFAULT             (_USART_CTRL_BYTESWAP_DEFAULT << 28)     /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_AUTOTX                       (0x1UL << 29)                            /**< Always Transmit When RX Not Full */
+#define _USART_CTRL_AUTOTX_SHIFT                29                                       /**< Shift value for USART_AUTOTX */
+#define _USART_CTRL_AUTOTX_MASK                 0x20000000UL                             /**< Bit mask for USART_AUTOTX */
+#define _USART_CTRL_AUTOTX_DEFAULT              0x00000000UL                             /**< Mode DEFAULT for USART_CTRL */
+#define USART_CTRL_AUTOTX_DEFAULT               (_USART_CTRL_AUTOTX_DEFAULT << 29)       /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_MVDIS                        (0x1UL << 30)                            /**< Majority Vote Disable */
+#define _USART_CTRL_MVDIS_SHIFT                 30                                       /**< Shift value for USART_MVDIS */
+#define _USART_CTRL_MVDIS_MASK                  0x40000000UL                             /**< Bit mask for USART_MVDIS */
+#define _USART_CTRL_MVDIS_DEFAULT               0x00000000UL                             /**< Mode DEFAULT for USART_CTRL */
+#define USART_CTRL_MVDIS_DEFAULT                (_USART_CTRL_MVDIS_DEFAULT << 30)        /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_SMSDELAY                     (0x1UL << 31)                            /**< Synchronous Master Sample Delay */
+#define _USART_CTRL_SMSDELAY_SHIFT              31                                       /**< Shift value for USART_SMSDELAY */
+#define _USART_CTRL_SMSDELAY_MASK               0x80000000UL                             /**< Bit mask for USART_SMSDELAY */
+#define _USART_CTRL_SMSDELAY_DEFAULT            0x00000000UL                             /**< Mode DEFAULT for USART_CTRL */
+#define USART_CTRL_SMSDELAY_DEFAULT             (_USART_CTRL_SMSDELAY_DEFAULT << 31)     /**< Shifted mode DEFAULT for USART_CTRL */
+
+/* Bit fields for USART FRAME */
+#define _USART_FRAME_RESETVALUE                 0x00001005UL                              /**< Default value for USART_FRAME */
+#define _USART_FRAME_MASK                       0x0000330FUL                              /**< Mask for USART_FRAME */
+#define _USART_FRAME_DATABITS_SHIFT             0                                         /**< Shift value for USART_DATABITS */
+#define _USART_FRAME_DATABITS_MASK              0xFUL                                     /**< Bit mask for USART_DATABITS */
+#define _USART_FRAME_DATABITS_FOUR              0x00000001UL                              /**< Mode FOUR for USART_FRAME */
+#define _USART_FRAME_DATABITS_FIVE              0x00000002UL                              /**< Mode FIVE for USART_FRAME */
+#define _USART_FRAME_DATABITS_SIX               0x00000003UL                              /**< Mode SIX for USART_FRAME */
+#define _USART_FRAME_DATABITS_SEVEN             0x00000004UL                              /**< Mode SEVEN for USART_FRAME */
+#define _USART_FRAME_DATABITS_DEFAULT           0x00000005UL                              /**< Mode DEFAULT for USART_FRAME */
+#define _USART_FRAME_DATABITS_EIGHT             0x00000005UL                              /**< Mode EIGHT for USART_FRAME */
+#define _USART_FRAME_DATABITS_NINE              0x00000006UL                              /**< Mode NINE for USART_FRAME */
+#define _USART_FRAME_DATABITS_TEN               0x00000007UL                              /**< Mode TEN for USART_FRAME */
+#define _USART_FRAME_DATABITS_ELEVEN            0x00000008UL                              /**< Mode ELEVEN for USART_FRAME */
+#define _USART_FRAME_DATABITS_TWELVE            0x00000009UL                              /**< Mode TWELVE for USART_FRAME */
+#define _USART_FRAME_DATABITS_THIRTEEN          0x0000000AUL                              /**< Mode THIRTEEN for USART_FRAME */
+#define _USART_FRAME_DATABITS_FOURTEEN          0x0000000BUL                              /**< Mode FOURTEEN for USART_FRAME */
+#define _USART_FRAME_DATABITS_FIFTEEN           0x0000000CUL                              /**< Mode FIFTEEN for USART_FRAME */
+#define _USART_FRAME_DATABITS_SIXTEEN           0x0000000DUL                              /**< Mode SIXTEEN for USART_FRAME */
+#define USART_FRAME_DATABITS_FOUR               (_USART_FRAME_DATABITS_FOUR << 0)         /**< Shifted mode FOUR for USART_FRAME */
+#define USART_FRAME_DATABITS_FIVE               (_USART_FRAME_DATABITS_FIVE << 0)         /**< Shifted mode FIVE for USART_FRAME */
+#define USART_FRAME_DATABITS_SIX                (_USART_FRAME_DATABITS_SIX << 0)          /**< Shifted mode SIX for USART_FRAME */
+#define USART_FRAME_DATABITS_SEVEN              (_USART_FRAME_DATABITS_SEVEN << 0)        /**< Shifted mode SEVEN for USART_FRAME */
+#define USART_FRAME_DATABITS_DEFAULT            (_USART_FRAME_DATABITS_DEFAULT << 0)      /**< Shifted mode DEFAULT for USART_FRAME */
+#define USART_FRAME_DATABITS_EIGHT              (_USART_FRAME_DATABITS_EIGHT << 0)        /**< Shifted mode EIGHT for USART_FRAME */
+#define USART_FRAME_DATABITS_NINE               (_USART_FRAME_DATABITS_NINE << 0)         /**< Shifted mode NINE for USART_FRAME */
+#define USART_FRAME_DATABITS_TEN                (_USART_FRAME_DATABITS_TEN << 0)          /**< Shifted mode TEN for USART_FRAME */
+#define USART_FRAME_DATABITS_ELEVEN             (_USART_FRAME_DATABITS_ELEVEN << 0)       /**< Shifted mode ELEVEN for USART_FRAME */
+#define USART_FRAME_DATABITS_TWELVE             (_USART_FRAME_DATABITS_TWELVE << 0)       /**< Shifted mode TWELVE for USART_FRAME */
+#define USART_FRAME_DATABITS_THIRTEEN           (_USART_FRAME_DATABITS_THIRTEEN << 0)     /**< Shifted mode THIRTEEN for USART_FRAME */
+#define USART_FRAME_DATABITS_FOURTEEN           (_USART_FRAME_DATABITS_FOURTEEN << 0)     /**< Shifted mode FOURTEEN for USART_FRAME */
+#define USART_FRAME_DATABITS_FIFTEEN            (_USART_FRAME_DATABITS_FIFTEEN << 0)      /**< Shifted mode FIFTEEN for USART_FRAME */
+#define USART_FRAME_DATABITS_SIXTEEN            (_USART_FRAME_DATABITS_SIXTEEN << 0)      /**< Shifted mode SIXTEEN for USART_FRAME */
+#define _USART_FRAME_PARITY_SHIFT               8                                         /**< Shift value for USART_PARITY */
+#define _USART_FRAME_PARITY_MASK                0x300UL                                   /**< Bit mask for USART_PARITY */
+#define _USART_FRAME_PARITY_DEFAULT             0x00000000UL                              /**< Mode DEFAULT for USART_FRAME */
+#define _USART_FRAME_PARITY_NONE                0x00000000UL                              /**< Mode NONE for USART_FRAME */
+#define _USART_FRAME_PARITY_EVEN                0x00000002UL                              /**< Mode EVEN for USART_FRAME */
+#define _USART_FRAME_PARITY_ODD                 0x00000003UL                              /**< Mode ODD for USART_FRAME */
+#define USART_FRAME_PARITY_DEFAULT              (_USART_FRAME_PARITY_DEFAULT << 8)        /**< Shifted mode DEFAULT for USART_FRAME */
+#define USART_FRAME_PARITY_NONE                 (_USART_FRAME_PARITY_NONE << 8)           /**< Shifted mode NONE for USART_FRAME */
+#define USART_FRAME_PARITY_EVEN                 (_USART_FRAME_PARITY_EVEN << 8)           /**< Shifted mode EVEN for USART_FRAME */
+#define USART_FRAME_PARITY_ODD                  (_USART_FRAME_PARITY_ODD << 8)            /**< Shifted mode ODD for USART_FRAME */
+#define _USART_FRAME_STOPBITS_SHIFT             12                                        /**< Shift value for USART_STOPBITS */
+#define _USART_FRAME_STOPBITS_MASK              0x3000UL                                  /**< Bit mask for USART_STOPBITS */
+#define _USART_FRAME_STOPBITS_HALF              0x00000000UL                              /**< Mode HALF for USART_FRAME */
+#define _USART_FRAME_STOPBITS_DEFAULT           0x00000001UL                              /**< Mode DEFAULT for USART_FRAME */
+#define _USART_FRAME_STOPBITS_ONE               0x00000001UL                              /**< Mode ONE for USART_FRAME */
+#define _USART_FRAME_STOPBITS_ONEANDAHALF       0x00000002UL                              /**< Mode ONEANDAHALF for USART_FRAME */
+#define _USART_FRAME_STOPBITS_TWO               0x00000003UL                              /**< Mode TWO for USART_FRAME */
+#define USART_FRAME_STOPBITS_HALF               (_USART_FRAME_STOPBITS_HALF << 12)        /**< Shifted mode HALF for USART_FRAME */
+#define USART_FRAME_STOPBITS_DEFAULT            (_USART_FRAME_STOPBITS_DEFAULT << 12)     /**< Shifted mode DEFAULT for USART_FRAME */
+#define USART_FRAME_STOPBITS_ONE                (_USART_FRAME_STOPBITS_ONE << 12)         /**< Shifted mode ONE for USART_FRAME */
+#define USART_FRAME_STOPBITS_ONEANDAHALF        (_USART_FRAME_STOPBITS_ONEANDAHALF << 12) /**< Shifted mode ONEANDAHALF for USART_FRAME */
+#define USART_FRAME_STOPBITS_TWO                (_USART_FRAME_STOPBITS_TWO << 12)         /**< Shifted mode TWO for USART_FRAME */
+
+/* Bit fields for USART TRIGCTRL */
+#define _USART_TRIGCTRL_RESETVALUE              0x00000000UL                             /**< Default value for USART_TRIGCTRL */
+#define _USART_TRIGCTRL_MASK                    0x000F1FF0UL                             /**< Mask for USART_TRIGCTRL */
+#define USART_TRIGCTRL_RXTEN                    (0x1UL << 4)                             /**< Receive Trigger Enable */
+#define _USART_TRIGCTRL_RXTEN_SHIFT             4                                        /**< Shift value for USART_RXTEN */
+#define _USART_TRIGCTRL_RXTEN_MASK              0x10UL                                   /**< Bit mask for USART_RXTEN */
+#define _USART_TRIGCTRL_RXTEN_DEFAULT           0x00000000UL                             /**< Mode DEFAULT for USART_TRIGCTRL */
+#define USART_TRIGCTRL_RXTEN_DEFAULT            (_USART_TRIGCTRL_RXTEN_DEFAULT << 4)     /**< Shifted mode DEFAULT for USART_TRIGCTRL */
+#define USART_TRIGCTRL_TXTEN                    (0x1UL << 5)                             /**< Transmit Trigger Enable */
+#define _USART_TRIGCTRL_TXTEN_SHIFT             5                                        /**< Shift value for USART_TXTEN */
+#define _USART_TRIGCTRL_TXTEN_MASK              0x20UL                                   /**< Bit mask for USART_TXTEN */
+#define _USART_TRIGCTRL_TXTEN_DEFAULT           0x00000000UL                             /**< Mode DEFAULT for USART_TRIGCTRL */
+#define USART_TRIGCTRL_TXTEN_DEFAULT            (_USART_TRIGCTRL_TXTEN_DEFAULT << 5)     /**< Shifted mode DEFAULT for USART_TRIGCTRL */
+#define USART_TRIGCTRL_AUTOTXTEN                (0x1UL << 6)                             /**< AUTOTX Trigger Enable */
+#define _USART_TRIGCTRL_AUTOTXTEN_SHIFT         6                                        /**< Shift value for USART_AUTOTXTEN */
+#define _USART_TRIGCTRL_AUTOTXTEN_MASK          0x40UL                                   /**< Bit mask for USART_AUTOTXTEN */
+#define _USART_TRIGCTRL_AUTOTXTEN_DEFAULT       0x00000000UL                             /**< Mode DEFAULT for USART_TRIGCTRL */
+#define USART_TRIGCTRL_AUTOTXTEN_DEFAULT        (_USART_TRIGCTRL_AUTOTXTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
+#define USART_TRIGCTRL_TXARX0EN                 (0x1UL << 7)                             /**< Enable Transmit Trigger after RX End of Frame plus TCMP0VAL */
+#define _USART_TRIGCTRL_TXARX0EN_SHIFT          7                                        /**< Shift value for USART_TXARX0EN */
+#define _USART_TRIGCTRL_TXARX0EN_MASK           0x80UL                                   /**< Bit mask for USART_TXARX0EN */
+#define _USART_TRIGCTRL_TXARX0EN_DEFAULT        0x00000000UL                             /**< Mode DEFAULT for USART_TRIGCTRL */
+#define USART_TRIGCTRL_TXARX0EN_DEFAULT         (_USART_TRIGCTRL_TXARX0EN_DEFAULT << 7)  /**< Shifted mode DEFAULT for USART_TRIGCTRL */
+#define USART_TRIGCTRL_TXARX1EN                 (0x1UL << 8)                             /**< Enable Transmit Trigger after RX End of Frame plus TCMP1VAL */
+#define _USART_TRIGCTRL_TXARX1EN_SHIFT          8                                        /**< Shift value for USART_TXARX1EN */
+#define _USART_TRIGCTRL_TXARX1EN_MASK           0x100UL                                  /**< Bit mask for USART_TXARX1EN */
+#define _USART_TRIGCTRL_TXARX1EN_DEFAULT        0x00000000UL                             /**< Mode DEFAULT for USART_TRIGCTRL */
+#define USART_TRIGCTRL_TXARX1EN_DEFAULT         (_USART_TRIGCTRL_TXARX1EN_DEFAULT << 8)  /**< Shifted mode DEFAULT for USART_TRIGCTRL */
+#define USART_TRIGCTRL_TXARX2EN                 (0x1UL << 9)                             /**< Enable Transmit Trigger after RX End of Frame plus TCMP2VAL */
+#define _USART_TRIGCTRL_TXARX2EN_SHIFT          9                                        /**< Shift value for USART_TXARX2EN */
+#define _USART_TRIGCTRL_TXARX2EN_MASK           0x200UL                                  /**< Bit mask for USART_TXARX2EN */
+#define _USART_TRIGCTRL_TXARX2EN_DEFAULT        0x00000000UL                             /**< Mode DEFAULT for USART_TRIGCTRL */
+#define USART_TRIGCTRL_TXARX2EN_DEFAULT         (_USART_TRIGCTRL_TXARX2EN_DEFAULT << 9)  /**< Shifted mode DEFAULT for USART_TRIGCTRL */
+#define USART_TRIGCTRL_RXATX0EN                 (0x1UL << 10)                            /**< Enable Receive Trigger after TX end of frame plus TCMPVAL0 baud-times */
+#define _USART_TRIGCTRL_RXATX0EN_SHIFT          10                                       /**< Shift value for USART_RXATX0EN */
+#define _USART_TRIGCTRL_RXATX0EN_MASK           0x400UL                                  /**< Bit mask for USART_RXATX0EN */
+#define _USART_TRIGCTRL_RXATX0EN_DEFAULT        0x00000000UL                             /**< Mode DEFAULT for USART_TRIGCTRL */
+#define USART_TRIGCTRL_RXATX0EN_DEFAULT         (_USART_TRIGCTRL_RXATX0EN_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
+#define USART_TRIGCTRL_RXATX1EN                 (0x1UL << 11)                            /**< Enable Receive Trigger after TX end of frame plus TCMPVAL1 baud-times */
+#define _USART_TRIGCTRL_RXATX1EN_SHIFT          11                                       /**< Shift value for USART_RXATX1EN */
+#define _USART_TRIGCTRL_RXATX1EN_MASK           0x800UL                                  /**< Bit mask for USART_RXATX1EN */
+#define _USART_TRIGCTRL_RXATX1EN_DEFAULT        0x00000000UL                             /**< Mode DEFAULT for USART_TRIGCTRL */
+#define USART_TRIGCTRL_RXATX1EN_DEFAULT         (_USART_TRIGCTRL_RXATX1EN_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
+#define USART_TRIGCTRL_RXATX2EN                 (0x1UL << 12)                            /**< Enable Receive Trigger after TX end of frame plus TCMPVAL2 baud-times */
+#define _USART_TRIGCTRL_RXATX2EN_SHIFT          12                                       /**< Shift value for USART_RXATX2EN */
+#define _USART_TRIGCTRL_RXATX2EN_MASK           0x1000UL                                 /**< Bit mask for USART_RXATX2EN */
+#define _USART_TRIGCTRL_RXATX2EN_DEFAULT        0x00000000UL                             /**< Mode DEFAULT for USART_TRIGCTRL */
+#define USART_TRIGCTRL_RXATX2EN_DEFAULT         (_USART_TRIGCTRL_RXATX2EN_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
+#define _USART_TRIGCTRL_TSEL_SHIFT              16                                       /**< Shift value for USART_TSEL */
+#define _USART_TRIGCTRL_TSEL_MASK               0xF0000UL                                /**< Bit mask for USART_TSEL */
+#define _USART_TRIGCTRL_TSEL_DEFAULT            0x00000000UL                             /**< Mode DEFAULT for USART_TRIGCTRL */
+#define _USART_TRIGCTRL_TSEL_PRSCH0             0x00000000UL                             /**< Mode PRSCH0 for USART_TRIGCTRL */
+#define _USART_TRIGCTRL_TSEL_PRSCH1             0x00000001UL                             /**< Mode PRSCH1 for USART_TRIGCTRL */
+#define _USART_TRIGCTRL_TSEL_PRSCH2             0x00000002UL                             /**< Mode PRSCH2 for USART_TRIGCTRL */
+#define _USART_TRIGCTRL_TSEL_PRSCH3             0x00000003UL                             /**< Mode PRSCH3 for USART_TRIGCTRL */
+#define _USART_TRIGCTRL_TSEL_PRSCH4             0x00000004UL                             /**< Mode PRSCH4 for USART_TRIGCTRL */
+#define _USART_TRIGCTRL_TSEL_PRSCH5             0x00000005UL                             /**< Mode PRSCH5 for USART_TRIGCTRL */
+#define _USART_TRIGCTRL_TSEL_PRSCH6             0x00000006UL                             /**< Mode PRSCH6 for USART_TRIGCTRL */
+#define _USART_TRIGCTRL_TSEL_PRSCH7             0x00000007UL                             /**< Mode PRSCH7 for USART_TRIGCTRL */
+#define _USART_TRIGCTRL_TSEL_PRSCH8             0x00000008UL                             /**< Mode PRSCH8 for USART_TRIGCTRL */
+#define _USART_TRIGCTRL_TSEL_PRSCH9             0x00000009UL                             /**< Mode PRSCH9 for USART_TRIGCTRL */
+#define _USART_TRIGCTRL_TSEL_PRSCH10            0x0000000AUL                             /**< Mode PRSCH10 for USART_TRIGCTRL */
+#define _USART_TRIGCTRL_TSEL_PRSCH11            0x0000000BUL                             /**< Mode PRSCH11 for USART_TRIGCTRL */
+#define USART_TRIGCTRL_TSEL_DEFAULT             (_USART_TRIGCTRL_TSEL_DEFAULT << 16)     /**< Shifted mode DEFAULT for USART_TRIGCTRL */
+#define USART_TRIGCTRL_TSEL_PRSCH0              (_USART_TRIGCTRL_TSEL_PRSCH0 << 16)      /**< Shifted mode PRSCH0 for USART_TRIGCTRL */
+#define USART_TRIGCTRL_TSEL_PRSCH1              (_USART_TRIGCTRL_TSEL_PRSCH1 << 16)      /**< Shifted mode PRSCH1 for USART_TRIGCTRL */
+#define USART_TRIGCTRL_TSEL_PRSCH2              (_USART_TRIGCTRL_TSEL_PRSCH2 << 16)      /**< Shifted mode PRSCH2 for USART_TRIGCTRL */
+#define USART_TRIGCTRL_TSEL_PRSCH3              (_USART_TRIGCTRL_TSEL_PRSCH3 << 16)      /**< Shifted mode PRSCH3 for USART_TRIGCTRL */
+#define USART_TRIGCTRL_TSEL_PRSCH4              (_USART_TRIGCTRL_TSEL_PRSCH4 << 16)      /**< Shifted mode PRSCH4 for USART_TRIGCTRL */
+#define USART_TRIGCTRL_TSEL_PRSCH5              (_USART_TRIGCTRL_TSEL_PRSCH5 << 16)      /**< Shifted mode PRSCH5 for USART_TRIGCTRL */
+#define USART_TRIGCTRL_TSEL_PRSCH6              (_USART_TRIGCTRL_TSEL_PRSCH6 << 16)      /**< Shifted mode PRSCH6 for USART_TRIGCTRL */
+#define USART_TRIGCTRL_TSEL_PRSCH7              (_USART_TRIGCTRL_TSEL_PRSCH7 << 16)      /**< Shifted mode PRSCH7 for USART_TRIGCTRL */
+#define USART_TRIGCTRL_TSEL_PRSCH8              (_USART_TRIGCTRL_TSEL_PRSCH8 << 16)      /**< Shifted mode PRSCH8 for USART_TRIGCTRL */
+#define USART_TRIGCTRL_TSEL_PRSCH9              (_USART_TRIGCTRL_TSEL_PRSCH9 << 16)      /**< Shifted mode PRSCH9 for USART_TRIGCTRL */
+#define USART_TRIGCTRL_TSEL_PRSCH10             (_USART_TRIGCTRL_TSEL_PRSCH10 << 16)     /**< Shifted mode PRSCH10 for USART_TRIGCTRL */
+#define USART_TRIGCTRL_TSEL_PRSCH11             (_USART_TRIGCTRL_TSEL_PRSCH11 << 16)     /**< Shifted mode PRSCH11 for USART_TRIGCTRL */
+
+/* Bit fields for USART CMD */
+#define _USART_CMD_RESETVALUE                   0x00000000UL                         /**< Default value for USART_CMD */
+#define _USART_CMD_MASK                         0x00000FFFUL                         /**< Mask for USART_CMD */
+#define USART_CMD_RXEN                          (0x1UL << 0)                         /**< Receiver Enable */
+#define _USART_CMD_RXEN_SHIFT                   0                                    /**< Shift value for USART_RXEN */
+#define _USART_CMD_RXEN_MASK                    0x1UL                                /**< Bit mask for USART_RXEN */
+#define _USART_CMD_RXEN_DEFAULT                 0x00000000UL                         /**< Mode DEFAULT for USART_CMD */
+#define USART_CMD_RXEN_DEFAULT                  (_USART_CMD_RXEN_DEFAULT << 0)       /**< Shifted mode DEFAULT for USART_CMD */
+#define USART_CMD_RXDIS                         (0x1UL << 1)                         /**< Receiver Disable */
+#define _USART_CMD_RXDIS_SHIFT                  1                                    /**< Shift value for USART_RXDIS */
+#define _USART_CMD_RXDIS_MASK                   0x2UL                                /**< Bit mask for USART_RXDIS */
+#define _USART_CMD_RXDIS_DEFAULT                0x00000000UL                         /**< Mode DEFAULT for USART_CMD */
+#define USART_CMD_RXDIS_DEFAULT                 (_USART_CMD_RXDIS_DEFAULT << 1)      /**< Shifted mode DEFAULT for USART_CMD */
+#define USART_CMD_TXEN                          (0x1UL << 2)                         /**< Transmitter Enable */
+#define _USART_CMD_TXEN_SHIFT                   2                                    /**< Shift value for USART_TXEN */
+#define _USART_CMD_TXEN_MASK                    0x4UL                                /**< Bit mask for USART_TXEN */
+#define _USART_CMD_TXEN_DEFAULT                 0x00000000UL                         /**< Mode DEFAULT for USART_CMD */
+#define USART_CMD_TXEN_DEFAULT                  (_USART_CMD_TXEN_DEFAULT << 2)       /**< Shifted mode DEFAULT for USART_CMD */
+#define USART_CMD_TXDIS                         (0x1UL << 3)                         /**< Transmitter Disable */
+#define _USART_CMD_TXDIS_SHIFT                  3                                    /**< Shift value for USART_TXDIS */
+#define _USART_CMD_TXDIS_MASK                   0x8UL                                /**< Bit mask for USART_TXDIS */
+#define _USART_CMD_TXDIS_DEFAULT                0x00000000UL                         /**< Mode DEFAULT for USART_CMD */
+#define USART_CMD_TXDIS_DEFAULT                 (_USART_CMD_TXDIS_DEFAULT << 3)      /**< Shifted mode DEFAULT for USART_CMD */
+#define USART_CMD_MASTEREN                      (0x1UL << 4)                         /**< Master Enable */
+#define _USART_CMD_MASTEREN_SHIFT               4                                    /**< Shift value for USART_MASTEREN */
+#define _USART_CMD_MASTEREN_MASK                0x10UL                               /**< Bit mask for USART_MASTEREN */
+#define _USART_CMD_MASTEREN_DEFAULT             0x00000000UL                         /**< Mode DEFAULT for USART_CMD */
+#define USART_CMD_MASTEREN_DEFAULT              (_USART_CMD_MASTEREN_DEFAULT << 4)   /**< Shifted mode DEFAULT for USART_CMD */
+#define USART_CMD_MASTERDIS                     (0x1UL << 5)                         /**< Master Disable */
+#define _USART_CMD_MASTERDIS_SHIFT              5                                    /**< Shift value for USART_MASTERDIS */
+#define _USART_CMD_MASTERDIS_MASK               0x20UL                               /**< Bit mask for USART_MASTERDIS */
+#define _USART_CMD_MASTERDIS_DEFAULT            0x00000000UL                         /**< Mode DEFAULT for USART_CMD */
+#define USART_CMD_MASTERDIS_DEFAULT             (_USART_CMD_MASTERDIS_DEFAULT << 5)  /**< Shifted mode DEFAULT for USART_CMD */
+#define USART_CMD_RXBLOCKEN                     (0x1UL << 6)                         /**< Receiver Block Enable */
+#define _USART_CMD_RXBLOCKEN_SHIFT              6                                    /**< Shift value for USART_RXBLOCKEN */
+#define _USART_CMD_RXBLOCKEN_MASK               0x40UL                               /**< Bit mask for USART_RXBLOCKEN */
+#define _USART_CMD_RXBLOCKEN_DEFAULT            0x00000000UL                         /**< Mode DEFAULT for USART_CMD */
+#define USART_CMD_RXBLOCKEN_DEFAULT             (_USART_CMD_RXBLOCKEN_DEFAULT << 6)  /**< Shifted mode DEFAULT for USART_CMD */
+#define USART_CMD_RXBLOCKDIS                    (0x1UL << 7)                         /**< Receiver Block Disable */
+#define _USART_CMD_RXBLOCKDIS_SHIFT             7                                    /**< Shift value for USART_RXBLOCKDIS */
+#define _USART_CMD_RXBLOCKDIS_MASK              0x80UL                               /**< Bit mask for USART_RXBLOCKDIS */
+#define _USART_CMD_RXBLOCKDIS_DEFAULT           0x00000000UL                         /**< Mode DEFAULT for USART_CMD */
+#define USART_CMD_RXBLOCKDIS_DEFAULT            (_USART_CMD_RXBLOCKDIS_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_CMD */
+#define USART_CMD_TXTRIEN                       (0x1UL << 8)                         /**< Transmitter Tristate Enable */
+#define _USART_CMD_TXTRIEN_SHIFT                8                                    /**< Shift value for USART_TXTRIEN */
+#define _USART_CMD_TXTRIEN_MASK                 0x100UL                              /**< Bit mask for USART_TXTRIEN */
+#define _USART_CMD_TXTRIEN_DEFAULT              0x00000000UL                         /**< Mode DEFAULT for USART_CMD */
+#define USART_CMD_TXTRIEN_DEFAULT               (_USART_CMD_TXTRIEN_DEFAULT << 8)    /**< Shifted mode DEFAULT for USART_CMD */
+#define USART_CMD_TXTRIDIS                      (0x1UL << 9)                         /**< Transmitter Tristate Disable */
+#define _USART_CMD_TXTRIDIS_SHIFT               9                                    /**< Shift value for USART_TXTRIDIS */
+#define _USART_CMD_TXTRIDIS_MASK                0x200UL                              /**< Bit mask for USART_TXTRIDIS */
+#define _USART_CMD_TXTRIDIS_DEFAULT             0x00000000UL                         /**< Mode DEFAULT for USART_CMD */
+#define USART_CMD_TXTRIDIS_DEFAULT              (_USART_CMD_TXTRIDIS_DEFAULT << 9)   /**< Shifted mode DEFAULT for USART_CMD */
+#define USART_CMD_CLEARTX                       (0x1UL << 10)                        /**< Clear TX */
+#define _USART_CMD_CLEARTX_SHIFT                10                                   /**< Shift value for USART_CLEARTX */
+#define _USART_CMD_CLEARTX_MASK                 0x400UL                              /**< Bit mask for USART_CLEARTX */
+#define _USART_CMD_CLEARTX_DEFAULT              0x00000000UL                         /**< Mode DEFAULT for USART_CMD */
+#define USART_CMD_CLEARTX_DEFAULT               (_USART_CMD_CLEARTX_DEFAULT << 10)   /**< Shifted mode DEFAULT for USART_CMD */
+#define USART_CMD_CLEARRX                       (0x1UL << 11)                        /**< Clear RX */
+#define _USART_CMD_CLEARRX_SHIFT                11                                   /**< Shift value for USART_CLEARRX */
+#define _USART_CMD_CLEARRX_MASK                 0x800UL                              /**< Bit mask for USART_CLEARRX */
+#define _USART_CMD_CLEARRX_DEFAULT              0x00000000UL                         /**< Mode DEFAULT for USART_CMD */
+#define USART_CMD_CLEARRX_DEFAULT               (_USART_CMD_CLEARRX_DEFAULT << 11)   /**< Shifted mode DEFAULT for USART_CMD */
+
+/* Bit fields for USART STATUS */
+#define _USART_STATUS_RESETVALUE                0x00002040UL                                 /**< Default value for USART_STATUS */
+#define _USART_STATUS_MASK                      0x00037FFFUL                                 /**< Mask for USART_STATUS */
+#define USART_STATUS_RXENS                      (0x1UL << 0)                                 /**< Receiver Enable Status */
+#define _USART_STATUS_RXENS_SHIFT               0                                            /**< Shift value for USART_RXENS */
+#define _USART_STATUS_RXENS_MASK                0x1UL                                        /**< Bit mask for USART_RXENS */
+#define _USART_STATUS_RXENS_DEFAULT             0x00000000UL                                 /**< Mode DEFAULT for USART_STATUS */
+#define USART_STATUS_RXENS_DEFAULT              (_USART_STATUS_RXENS_DEFAULT << 0)           /**< Shifted mode DEFAULT for USART_STATUS */
+#define USART_STATUS_TXENS                      (0x1UL << 1)                                 /**< Transmitter Enable Status */
+#define _USART_STATUS_TXENS_SHIFT               1                                            /**< Shift value for USART_TXENS */
+#define _USART_STATUS_TXENS_MASK                0x2UL                                        /**< Bit mask for USART_TXENS */
+#define _USART_STATUS_TXENS_DEFAULT             0x00000000UL                                 /**< Mode DEFAULT for USART_STATUS */
+#define USART_STATUS_TXENS_DEFAULT              (_USART_STATUS_TXENS_DEFAULT << 1)           /**< Shifted mode DEFAULT for USART_STATUS */
+#define USART_STATUS_MASTER                     (0x1UL << 2)                                 /**< SPI Master Mode */
+#define _USART_STATUS_MASTER_SHIFT              2                                            /**< Shift value for USART_MASTER */
+#define _USART_STATUS_MASTER_MASK               0x4UL                                        /**< Bit mask for USART_MASTER */
+#define _USART_STATUS_MASTER_DEFAULT            0x00000000UL                                 /**< Mode DEFAULT for USART_STATUS */
+#define USART_STATUS_MASTER_DEFAULT             (_USART_STATUS_MASTER_DEFAULT << 2)          /**< Shifted mode DEFAULT for USART_STATUS */
+#define USART_STATUS_RXBLOCK                    (0x1UL << 3)                                 /**< Block Incoming Data */
+#define _USART_STATUS_RXBLOCK_SHIFT             3                                            /**< Shift value for USART_RXBLOCK */
+#define _USART_STATUS_RXBLOCK_MASK              0x8UL                                        /**< Bit mask for USART_RXBLOCK */
+#define _USART_STATUS_RXBLOCK_DEFAULT           0x00000000UL                                 /**< Mode DEFAULT for USART_STATUS */
+#define USART_STATUS_RXBLOCK_DEFAULT            (_USART_STATUS_RXBLOCK_DEFAULT << 3)         /**< Shifted mode DEFAULT for USART_STATUS */
+#define USART_STATUS_TXTRI                      (0x1UL << 4)                                 /**< Transmitter Tristated */
+#define _USART_STATUS_TXTRI_SHIFT               4                                            /**< Shift value for USART_TXTRI */
+#define _USART_STATUS_TXTRI_MASK                0x10UL                                       /**< Bit mask for USART_TXTRI */
+#define _USART_STATUS_TXTRI_DEFAULT             0x00000000UL                                 /**< Mode DEFAULT for USART_STATUS */
+#define USART_STATUS_TXTRI_DEFAULT              (_USART_STATUS_TXTRI_DEFAULT << 4)           /**< Shifted mode DEFAULT for USART_STATUS */
+#define USART_STATUS_TXC                        (0x1UL << 5)                                 /**< TX Complete */
+#define _USART_STATUS_TXC_SHIFT                 5                                            /**< Shift value for USART_TXC */
+#define _USART_STATUS_TXC_MASK                  0x20UL                                       /**< Bit mask for USART_TXC */
+#define _USART_STATUS_TXC_DEFAULT               0x00000000UL                                 /**< Mode DEFAULT for USART_STATUS */
+#define USART_STATUS_TXC_DEFAULT                (_USART_STATUS_TXC_DEFAULT << 5)             /**< Shifted mode DEFAULT for USART_STATUS */
+#define USART_STATUS_TXBL                       (0x1UL << 6)                                 /**< TX Buffer Level */
+#define _USART_STATUS_TXBL_SHIFT                6                                            /**< Shift value for USART_TXBL */
+#define _USART_STATUS_TXBL_MASK                 0x40UL                                       /**< Bit mask for USART_TXBL */
+#define _USART_STATUS_TXBL_DEFAULT              0x00000001UL                                 /**< Mode DEFAULT for USART_STATUS */
+#define USART_STATUS_TXBL_DEFAULT               (_USART_STATUS_TXBL_DEFAULT << 6)            /**< Shifted mode DEFAULT for USART_STATUS */
+#define USART_STATUS_RXDATAV                    (0x1UL << 7)                                 /**< RX Data Valid */
+#define _USART_STATUS_RXDATAV_SHIFT             7                                            /**< Shift value for USART_RXDATAV */
+#define _USART_STATUS_RXDATAV_MASK              0x80UL                                       /**< Bit mask for USART_RXDATAV */
+#define _USART_STATUS_RXDATAV_DEFAULT           0x00000000UL                                 /**< Mode DEFAULT for USART_STATUS */
+#define USART_STATUS_RXDATAV_DEFAULT            (_USART_STATUS_RXDATAV_DEFAULT << 7)         /**< Shifted mode DEFAULT for USART_STATUS */
+#define USART_STATUS_RXFULL                     (0x1UL << 8)                                 /**< RX FIFO Full */
+#define _USART_STATUS_RXFULL_SHIFT              8                                            /**< Shift value for USART_RXFULL */
+#define _USART_STATUS_RXFULL_MASK               0x100UL                                      /**< Bit mask for USART_RXFULL */
+#define _USART_STATUS_RXFULL_DEFAULT            0x00000000UL                                 /**< Mode DEFAULT for USART_STATUS */
+#define USART_STATUS_RXFULL_DEFAULT             (_USART_STATUS_RXFULL_DEFAULT << 8)          /**< Shifted mode DEFAULT for USART_STATUS */
+#define USART_STATUS_TXBDRIGHT                  (0x1UL << 9)                                 /**< TX Buffer Expects Double Right Data */
+#define _USART_STATUS_TXBDRIGHT_SHIFT           9                                            /**< Shift value for USART_TXBDRIGHT */
+#define _USART_STATUS_TXBDRIGHT_MASK            0x200UL                                      /**< Bit mask for USART_TXBDRIGHT */
+#define _USART_STATUS_TXBDRIGHT_DEFAULT         0x00000000UL                                 /**< Mode DEFAULT for USART_STATUS */
+#define USART_STATUS_TXBDRIGHT_DEFAULT          (_USART_STATUS_TXBDRIGHT_DEFAULT << 9)       /**< Shifted mode DEFAULT for USART_STATUS */
+#define USART_STATUS_TXBSRIGHT                  (0x1UL << 10)                                /**< TX Buffer Expects Single Right Data */
+#define _USART_STATUS_TXBSRIGHT_SHIFT           10                                           /**< Shift value for USART_TXBSRIGHT */
+#define _USART_STATUS_TXBSRIGHT_MASK            0x400UL                                      /**< Bit mask for USART_TXBSRIGHT */
+#define _USART_STATUS_TXBSRIGHT_DEFAULT         0x00000000UL                                 /**< Mode DEFAULT for USART_STATUS */
+#define USART_STATUS_TXBSRIGHT_DEFAULT          (_USART_STATUS_TXBSRIGHT_DEFAULT << 10)      /**< Shifted mode DEFAULT for USART_STATUS */
+#define USART_STATUS_RXDATAVRIGHT               (0x1UL << 11)                                /**< RX Data Right */
+#define _USART_STATUS_RXDATAVRIGHT_SHIFT        11                                           /**< Shift value for USART_RXDATAVRIGHT */
+#define _USART_STATUS_RXDATAVRIGHT_MASK         0x800UL                                      /**< Bit mask for USART_RXDATAVRIGHT */
+#define _USART_STATUS_RXDATAVRIGHT_DEFAULT      0x00000000UL                                 /**< Mode DEFAULT for USART_STATUS */
+#define USART_STATUS_RXDATAVRIGHT_DEFAULT       (_USART_STATUS_RXDATAVRIGHT_DEFAULT << 11)   /**< Shifted mode DEFAULT for USART_STATUS */
+#define USART_STATUS_RXFULLRIGHT                (0x1UL << 12)                                /**< RX Full of Right Data */
+#define _USART_STATUS_RXFULLRIGHT_SHIFT         12                                           /**< Shift value for USART_RXFULLRIGHT */
+#define _USART_STATUS_RXFULLRIGHT_MASK          0x1000UL                                     /**< Bit mask for USART_RXFULLRIGHT */
+#define _USART_STATUS_RXFULLRIGHT_DEFAULT       0x00000000UL                                 /**< Mode DEFAULT for USART_STATUS */
+#define USART_STATUS_RXFULLRIGHT_DEFAULT        (_USART_STATUS_RXFULLRIGHT_DEFAULT << 12)    /**< Shifted mode DEFAULT for USART_STATUS */
+#define USART_STATUS_TXIDLE                     (0x1UL << 13)                                /**< TX Idle */
+#define _USART_STATUS_TXIDLE_SHIFT              13                                           /**< Shift value for USART_TXIDLE */
+#define _USART_STATUS_TXIDLE_MASK               0x2000UL                                     /**< Bit mask for USART_TXIDLE */
+#define _USART_STATUS_TXIDLE_DEFAULT            0x00000001UL                                 /**< Mode DEFAULT for USART_STATUS */
+#define USART_STATUS_TXIDLE_DEFAULT             (_USART_STATUS_TXIDLE_DEFAULT << 13)         /**< Shifted mode DEFAULT for USART_STATUS */
+#define USART_STATUS_TIMERRESTARTED             (0x1UL << 14)                                /**< The USART Timer restarted itself */
+#define _USART_STATUS_TIMERRESTARTED_SHIFT      14                                           /**< Shift value for USART_TIMERRESTARTED */
+#define _USART_STATUS_TIMERRESTARTED_MASK       0x4000UL                                     /**< Bit mask for USART_TIMERRESTARTED */
+#define _USART_STATUS_TIMERRESTARTED_DEFAULT    0x00000000UL                                 /**< Mode DEFAULT for USART_STATUS */
+#define USART_STATUS_TIMERRESTARTED_DEFAULT     (_USART_STATUS_TIMERRESTARTED_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_STATUS */
+#define _USART_STATUS_TXBUFCNT_SHIFT            16                                           /**< Shift value for USART_TXBUFCNT */
+#define _USART_STATUS_TXBUFCNT_MASK             0x30000UL                                    /**< Bit mask for USART_TXBUFCNT */
+#define _USART_STATUS_TXBUFCNT_DEFAULT          0x00000000UL                                 /**< Mode DEFAULT for USART_STATUS */
+#define USART_STATUS_TXBUFCNT_DEFAULT           (_USART_STATUS_TXBUFCNT_DEFAULT << 16)       /**< Shifted mode DEFAULT for USART_STATUS */
+
+/* Bit fields for USART CLKDIV */
+#define _USART_CLKDIV_RESETVALUE                0x00000000UL                             /**< Default value for USART_CLKDIV */
+#define _USART_CLKDIV_MASK                      0x807FFFF8UL                             /**< Mask for USART_CLKDIV */
+#define _USART_CLKDIV_DIV_SHIFT                 3                                        /**< Shift value for USART_DIV */
+#define _USART_CLKDIV_DIV_MASK                  0x7FFFF8UL                               /**< Bit mask for USART_DIV */
+#define _USART_CLKDIV_DIV_DEFAULT               0x00000000UL                             /**< Mode DEFAULT for USART_CLKDIV */
+#define USART_CLKDIV_DIV_DEFAULT                (_USART_CLKDIV_DIV_DEFAULT << 3)         /**< Shifted mode DEFAULT for USART_CLKDIV */
+#define USART_CLKDIV_AUTOBAUDEN                 (0x1UL << 31)                            /**< AUTOBAUD detection enable */
+#define _USART_CLKDIV_AUTOBAUDEN_SHIFT          31                                       /**< Shift value for USART_AUTOBAUDEN */
+#define _USART_CLKDIV_AUTOBAUDEN_MASK           0x80000000UL                             /**< Bit mask for USART_AUTOBAUDEN */
+#define _USART_CLKDIV_AUTOBAUDEN_DEFAULT        0x00000000UL                             /**< Mode DEFAULT for USART_CLKDIV */
+#define USART_CLKDIV_AUTOBAUDEN_DEFAULT         (_USART_CLKDIV_AUTOBAUDEN_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_CLKDIV */
+
+/* Bit fields for USART RXDATAX */
+#define _USART_RXDATAX_RESETVALUE               0x00000000UL                         /**< Default value for USART_RXDATAX */
+#define _USART_RXDATAX_MASK                     0x0000C1FFUL                         /**< Mask for USART_RXDATAX */
+#define _USART_RXDATAX_RXDATA_SHIFT             0                                    /**< Shift value for USART_RXDATA */
+#define _USART_RXDATAX_RXDATA_MASK              0x1FFUL                              /**< Bit mask for USART_RXDATA */
+#define _USART_RXDATAX_RXDATA_DEFAULT           0x00000000UL                         /**< Mode DEFAULT for USART_RXDATAX */
+#define USART_RXDATAX_RXDATA_DEFAULT            (_USART_RXDATAX_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATAX */
+#define USART_RXDATAX_PERR                      (0x1UL << 14)                        /**< Data Parity Error */
+#define _USART_RXDATAX_PERR_SHIFT               14                                   /**< Shift value for USART_PERR */
+#define _USART_RXDATAX_PERR_MASK                0x4000UL                             /**< Bit mask for USART_PERR */
+#define _USART_RXDATAX_PERR_DEFAULT             0x00000000UL                         /**< Mode DEFAULT for USART_RXDATAX */
+#define USART_RXDATAX_PERR_DEFAULT              (_USART_RXDATAX_PERR_DEFAULT << 14)  /**< Shifted mode DEFAULT for USART_RXDATAX */
+#define USART_RXDATAX_FERR                      (0x1UL << 15)                        /**< Data Framing Error */
+#define _USART_RXDATAX_FERR_SHIFT               15                                   /**< Shift value for USART_FERR */
+#define _USART_RXDATAX_FERR_MASK                0x8000UL                             /**< Bit mask for USART_FERR */
+#define _USART_RXDATAX_FERR_DEFAULT             0x00000000UL                         /**< Mode DEFAULT for USART_RXDATAX */
+#define USART_RXDATAX_FERR_DEFAULT              (_USART_RXDATAX_FERR_DEFAULT << 15)  /**< Shifted mode DEFAULT for USART_RXDATAX */
+
+/* Bit fields for USART RXDATA */
+#define _USART_RXDATA_RESETVALUE                0x00000000UL                        /**< Default value for USART_RXDATA */
+#define _USART_RXDATA_MASK                      0x000000FFUL                        /**< Mask for USART_RXDATA */
+#define _USART_RXDATA_RXDATA_SHIFT              0                                   /**< Shift value for USART_RXDATA */
+#define _USART_RXDATA_RXDATA_MASK               0xFFUL                              /**< Bit mask for USART_RXDATA */
+#define _USART_RXDATA_RXDATA_DEFAULT            0x00000000UL                        /**< Mode DEFAULT for USART_RXDATA */
+#define USART_RXDATA_RXDATA_DEFAULT             (_USART_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATA */
+
+/* Bit fields for USART RXDOUBLEX */
+#define _USART_RXDOUBLEX_RESETVALUE             0x00000000UL                             /**< Default value for USART_RXDOUBLEX */
+#define _USART_RXDOUBLEX_MASK                   0xC1FFC1FFUL                             /**< Mask for USART_RXDOUBLEX */
+#define _USART_RXDOUBLEX_RXDATA0_SHIFT          0                                        /**< Shift value for USART_RXDATA0 */
+#define _USART_RXDOUBLEX_RXDATA0_MASK           0x1FFUL                                  /**< Bit mask for USART_RXDATA0 */
+#define _USART_RXDOUBLEX_RXDATA0_DEFAULT        0x00000000UL                             /**< Mode DEFAULT for USART_RXDOUBLEX */
+#define USART_RXDOUBLEX_RXDATA0_DEFAULT         (_USART_RXDOUBLEX_RXDATA0_DEFAULT << 0)  /**< Shifted mode DEFAULT for USART_RXDOUBLEX */
+#define USART_RXDOUBLEX_PERR0                   (0x1UL << 14)                            /**< Data Parity Error 0 */
+#define _USART_RXDOUBLEX_PERR0_SHIFT            14                                       /**< Shift value for USART_PERR0 */
+#define _USART_RXDOUBLEX_PERR0_MASK             0x4000UL                                 /**< Bit mask for USART_PERR0 */
+#define _USART_RXDOUBLEX_PERR0_DEFAULT          0x00000000UL                             /**< Mode DEFAULT for USART_RXDOUBLEX */
+#define USART_RXDOUBLEX_PERR0_DEFAULT           (_USART_RXDOUBLEX_PERR0_DEFAULT << 14)   /**< Shifted mode DEFAULT for USART_RXDOUBLEX */
+#define USART_RXDOUBLEX_FERR0                   (0x1UL << 15)                            /**< Data Framing Error 0 */
+#define _USART_RXDOUBLEX_FERR0_SHIFT            15                                       /**< Shift value for USART_FERR0 */
+#define _USART_RXDOUBLEX_FERR0_MASK             0x8000UL                                 /**< Bit mask for USART_FERR0 */
+#define _USART_RXDOUBLEX_FERR0_DEFAULT          0x00000000UL                             /**< Mode DEFAULT for USART_RXDOUBLEX */
+#define USART_RXDOUBLEX_FERR0_DEFAULT           (_USART_RXDOUBLEX_FERR0_DEFAULT << 15)   /**< Shifted mode DEFAULT for USART_RXDOUBLEX */
+#define _USART_RXDOUBLEX_RXDATA1_SHIFT          16                                       /**< Shift value for USART_RXDATA1 */
+#define _USART_RXDOUBLEX_RXDATA1_MASK           0x1FF0000UL                              /**< Bit mask for USART_RXDATA1 */
+#define _USART_RXDOUBLEX_RXDATA1_DEFAULT        0x00000000UL                             /**< Mode DEFAULT for USART_RXDOUBLEX */
+#define USART_RXDOUBLEX_RXDATA1_DEFAULT         (_USART_RXDOUBLEX_RXDATA1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */
+#define USART_RXDOUBLEX_PERR1                   (0x1UL << 30)                            /**< Data Parity Error 1 */
+#define _USART_RXDOUBLEX_PERR1_SHIFT            30                                       /**< Shift value for USART_PERR1 */
+#define _USART_RXDOUBLEX_PERR1_MASK             0x40000000UL                             /**< Bit mask for USART_PERR1 */
+#define _USART_RXDOUBLEX_PERR1_DEFAULT          0x00000000UL                             /**< Mode DEFAULT for USART_RXDOUBLEX */
+#define USART_RXDOUBLEX_PERR1_DEFAULT           (_USART_RXDOUBLEX_PERR1_DEFAULT << 30)   /**< Shifted mode DEFAULT for USART_RXDOUBLEX */
+#define USART_RXDOUBLEX_FERR1                   (0x1UL << 31)                            /**< Data Framing Error 1 */
+#define _USART_RXDOUBLEX_FERR1_SHIFT            31                                       /**< Shift value for USART_FERR1 */
+#define _USART_RXDOUBLEX_FERR1_MASK             0x80000000UL                             /**< Bit mask for USART_FERR1 */
+#define _USART_RXDOUBLEX_FERR1_DEFAULT          0x00000000UL                             /**< Mode DEFAULT for USART_RXDOUBLEX */
+#define USART_RXDOUBLEX_FERR1_DEFAULT           (_USART_RXDOUBLEX_FERR1_DEFAULT << 31)   /**< Shifted mode DEFAULT for USART_RXDOUBLEX */
+
+/* Bit fields for USART RXDOUBLE */
+#define _USART_RXDOUBLE_RESETVALUE              0x00000000UL                           /**< Default value for USART_RXDOUBLE */
+#define _USART_RXDOUBLE_MASK                    0x0000FFFFUL                           /**< Mask for USART_RXDOUBLE */
+#define _USART_RXDOUBLE_RXDATA0_SHIFT           0                                      /**< Shift value for USART_RXDATA0 */
+#define _USART_RXDOUBLE_RXDATA0_MASK            0xFFUL                                 /**< Bit mask for USART_RXDATA0 */
+#define _USART_RXDOUBLE_RXDATA0_DEFAULT         0x00000000UL                           /**< Mode DEFAULT for USART_RXDOUBLE */
+#define USART_RXDOUBLE_RXDATA0_DEFAULT          (_USART_RXDOUBLE_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLE */
+#define _USART_RXDOUBLE_RXDATA1_SHIFT           8                                      /**< Shift value for USART_RXDATA1 */
+#define _USART_RXDOUBLE_RXDATA1_MASK            0xFF00UL                               /**< Bit mask for USART_RXDATA1 */
+#define _USART_RXDOUBLE_RXDATA1_DEFAULT         0x00000000UL                           /**< Mode DEFAULT for USART_RXDOUBLE */
+#define USART_RXDOUBLE_RXDATA1_DEFAULT          (_USART_RXDOUBLE_RXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_RXDOUBLE */
+
+/* Bit fields for USART RXDATAXP */
+#define _USART_RXDATAXP_RESETVALUE              0x00000000UL                           /**< Default value for USART_RXDATAXP */
+#define _USART_RXDATAXP_MASK                    0x0000C1FFUL                           /**< Mask for USART_RXDATAXP */
+#define _USART_RXDATAXP_RXDATAP_SHIFT           0                                      /**< Shift value for USART_RXDATAP */
+#define _USART_RXDATAXP_RXDATAP_MASK            0x1FFUL                                /**< Bit mask for USART_RXDATAP */
+#define _USART_RXDATAXP_RXDATAP_DEFAULT         0x00000000UL                           /**< Mode DEFAULT for USART_RXDATAXP */
+#define USART_RXDATAXP_RXDATAP_DEFAULT          (_USART_RXDATAXP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATAXP */
+#define USART_RXDATAXP_PERRP                    (0x1UL << 14)                          /**< Data Parity Error Peek */
+#define _USART_RXDATAXP_PERRP_SHIFT             14                                     /**< Shift value for USART_PERRP */
+#define _USART_RXDATAXP_PERRP_MASK              0x4000UL                               /**< Bit mask for USART_PERRP */
+#define _USART_RXDATAXP_PERRP_DEFAULT           0x00000000UL                           /**< Mode DEFAULT for USART_RXDATAXP */
+#define USART_RXDATAXP_PERRP_DEFAULT            (_USART_RXDATAXP_PERRP_DEFAULT << 14)  /**< Shifted mode DEFAULT for USART_RXDATAXP */
+#define USART_RXDATAXP_FERRP                    (0x1UL << 15)                          /**< Data Framing Error Peek */
+#define _USART_RXDATAXP_FERRP_SHIFT             15                                     /**< Shift value for USART_FERRP */
+#define _USART_RXDATAXP_FERRP_MASK              0x8000UL                               /**< Bit mask for USART_FERRP */
+#define _USART_RXDATAXP_FERRP_DEFAULT           0x00000000UL                           /**< Mode DEFAULT for USART_RXDATAXP */
+#define USART_RXDATAXP_FERRP_DEFAULT            (_USART_RXDATAXP_FERRP_DEFAULT << 15)  /**< Shifted mode DEFAULT for USART_RXDATAXP */
+
+/* Bit fields for USART RXDOUBLEXP */
+#define _USART_RXDOUBLEXP_RESETVALUE            0x00000000UL                               /**< Default value for USART_RXDOUBLEXP */
+#define _USART_RXDOUBLEXP_MASK                  0xC1FFC1FFUL                               /**< Mask for USART_RXDOUBLEXP */
+#define _USART_RXDOUBLEXP_RXDATAP0_SHIFT        0                                          /**< Shift value for USART_RXDATAP0 */
+#define _USART_RXDOUBLEXP_RXDATAP0_MASK         0x1FFUL                                    /**< Bit mask for USART_RXDATAP0 */
+#define _USART_RXDOUBLEXP_RXDATAP0_DEFAULT      0x00000000UL                               /**< Mode DEFAULT for USART_RXDOUBLEXP */
+#define USART_RXDOUBLEXP_RXDATAP0_DEFAULT       (_USART_RXDOUBLEXP_RXDATAP0_DEFAULT << 0)  /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */
+#define USART_RXDOUBLEXP_PERRP0                 (0x1UL << 14)                              /**< Data Parity Error 0 Peek */
+#define _USART_RXDOUBLEXP_PERRP0_SHIFT          14                                         /**< Shift value for USART_PERRP0 */
+#define _USART_RXDOUBLEXP_PERRP0_MASK           0x4000UL                                   /**< Bit mask for USART_PERRP0 */
+#define _USART_RXDOUBLEXP_PERRP0_DEFAULT        0x00000000UL                               /**< Mode DEFAULT for USART_RXDOUBLEXP */
+#define USART_RXDOUBLEXP_PERRP0_DEFAULT         (_USART_RXDOUBLEXP_PERRP0_DEFAULT << 14)   /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */
+#define USART_RXDOUBLEXP_FERRP0                 (0x1UL << 15)                              /**< Data Framing Error 0 Peek */
+#define _USART_RXDOUBLEXP_FERRP0_SHIFT          15                                         /**< Shift value for USART_FERRP0 */
+#define _USART_RXDOUBLEXP_FERRP0_MASK           0x8000UL                                   /**< Bit mask for USART_FERRP0 */
+#define _USART_RXDOUBLEXP_FERRP0_DEFAULT        0x00000000UL                               /**< Mode DEFAULT for USART_RXDOUBLEXP */
+#define USART_RXDOUBLEXP_FERRP0_DEFAULT         (_USART_RXDOUBLEXP_FERRP0_DEFAULT << 15)   /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */
+#define _USART_RXDOUBLEXP_RXDATAP1_SHIFT        16                                         /**< Shift value for USART_RXDATAP1 */
+#define _USART_RXDOUBLEXP_RXDATAP1_MASK         0x1FF0000UL                                /**< Bit mask for USART_RXDATAP1 */
+#define _USART_RXDOUBLEXP_RXDATAP1_DEFAULT      0x00000000UL                               /**< Mode DEFAULT for USART_RXDOUBLEXP */
+#define USART_RXDOUBLEXP_RXDATAP1_DEFAULT       (_USART_RXDOUBLEXP_RXDATAP1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */
+#define USART_RXDOUBLEXP_PERRP1                 (0x1UL << 30)                              /**< Data Parity Error 1 Peek */
+#define _USART_RXDOUBLEXP_PERRP1_SHIFT          30                                         /**< Shift value for USART_PERRP1 */
+#define _USART_RXDOUBLEXP_PERRP1_MASK           0x40000000UL                               /**< Bit mask for USART_PERRP1 */
+#define _USART_RXDOUBLEXP_PERRP1_DEFAULT        0x00000000UL                               /**< Mode DEFAULT for USART_RXDOUBLEXP */
+#define USART_RXDOUBLEXP_PERRP1_DEFAULT         (_USART_RXDOUBLEXP_PERRP1_DEFAULT << 30)   /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */
+#define USART_RXDOUBLEXP_FERRP1                 (0x1UL << 31)                              /**< Data Framing Error 1 Peek */
+#define _USART_RXDOUBLEXP_FERRP1_SHIFT          31                                         /**< Shift value for USART_FERRP1 */
+#define _USART_RXDOUBLEXP_FERRP1_MASK           0x80000000UL                               /**< Bit mask for USART_FERRP1 */
+#define _USART_RXDOUBLEXP_FERRP1_DEFAULT        0x00000000UL                               /**< Mode DEFAULT for USART_RXDOUBLEXP */
+#define USART_RXDOUBLEXP_FERRP1_DEFAULT         (_USART_RXDOUBLEXP_FERRP1_DEFAULT << 31)   /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */
+
+/* Bit fields for USART TXDATAX */
+#define _USART_TXDATAX_RESETVALUE               0x00000000UL                           /**< Default value for USART_TXDATAX */
+#define _USART_TXDATAX_MASK                     0x0000F9FFUL                           /**< Mask for USART_TXDATAX */
+#define _USART_TXDATAX_TXDATAX_SHIFT            0                                      /**< Shift value for USART_TXDATAX */
+#define _USART_TXDATAX_TXDATAX_MASK             0x1FFUL                                /**< Bit mask for USART_TXDATAX */
+#define _USART_TXDATAX_TXDATAX_DEFAULT          0x00000000UL                           /**< Mode DEFAULT for USART_TXDATAX */
+#define USART_TXDATAX_TXDATAX_DEFAULT           (_USART_TXDATAX_TXDATAX_DEFAULT << 0)  /**< Shifted mode DEFAULT for USART_TXDATAX */
+#define USART_TXDATAX_UBRXAT                    (0x1UL << 11)                          /**< Unblock RX After Transmission */
+#define _USART_TXDATAX_UBRXAT_SHIFT             11                                     /**< Shift value for USART_UBRXAT */
+#define _USART_TXDATAX_UBRXAT_MASK              0x800UL                                /**< Bit mask for USART_UBRXAT */
+#define _USART_TXDATAX_UBRXAT_DEFAULT           0x00000000UL                           /**< Mode DEFAULT for USART_TXDATAX */
+#define USART_TXDATAX_UBRXAT_DEFAULT            (_USART_TXDATAX_UBRXAT_DEFAULT << 11)  /**< Shifted mode DEFAULT for USART_TXDATAX */
+#define USART_TXDATAX_TXTRIAT                   (0x1UL << 12)                          /**< Set TXTRI After Transmission */
+#define _USART_TXDATAX_TXTRIAT_SHIFT            12                                     /**< Shift value for USART_TXTRIAT */
+#define _USART_TXDATAX_TXTRIAT_MASK             0x1000UL                               /**< Bit mask for USART_TXTRIAT */
+#define _USART_TXDATAX_TXTRIAT_DEFAULT          0x00000000UL                           /**< Mode DEFAULT for USART_TXDATAX */
+#define USART_TXDATAX_TXTRIAT_DEFAULT           (_USART_TXDATAX_TXTRIAT_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TXDATAX */
+#define USART_TXDATAX_TXBREAK                   (0x1UL << 13)                          /**< Transmit Data As Break */
+#define _USART_TXDATAX_TXBREAK_SHIFT            13                                     /**< Shift value for USART_TXBREAK */
+#define _USART_TXDATAX_TXBREAK_MASK             0x2000UL                               /**< Bit mask for USART_TXBREAK */
+#define _USART_TXDATAX_TXBREAK_DEFAULT          0x00000000UL                           /**< Mode DEFAULT for USART_TXDATAX */
+#define USART_TXDATAX_TXBREAK_DEFAULT           (_USART_TXDATAX_TXBREAK_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_TXDATAX */
+#define USART_TXDATAX_TXDISAT                   (0x1UL << 14)                          /**< Clear TXEN After Transmission */
+#define _USART_TXDATAX_TXDISAT_SHIFT            14                                     /**< Shift value for USART_TXDISAT */
+#define _USART_TXDATAX_TXDISAT_MASK             0x4000UL                               /**< Bit mask for USART_TXDISAT */
+#define _USART_TXDATAX_TXDISAT_DEFAULT          0x00000000UL                           /**< Mode DEFAULT for USART_TXDATAX */
+#define USART_TXDATAX_TXDISAT_DEFAULT           (_USART_TXDATAX_TXDISAT_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_TXDATAX */
+#define USART_TXDATAX_RXENAT                    (0x1UL << 15)                          /**< Enable RX After Transmission */
+#define _USART_TXDATAX_RXENAT_SHIFT             15                                     /**< Shift value for USART_RXENAT */
+#define _USART_TXDATAX_RXENAT_MASK              0x8000UL                               /**< Bit mask for USART_RXENAT */
+#define _USART_TXDATAX_RXENAT_DEFAULT           0x00000000UL                           /**< Mode DEFAULT for USART_TXDATAX */
+#define USART_TXDATAX_RXENAT_DEFAULT            (_USART_TXDATAX_RXENAT_DEFAULT << 15)  /**< Shifted mode DEFAULT for USART_TXDATAX */
+
+/* Bit fields for USART TXDATA */
+#define _USART_TXDATA_RESETVALUE                0x00000000UL                        /**< Default value for USART_TXDATA */
+#define _USART_TXDATA_MASK                      0x000000FFUL                        /**< Mask for USART_TXDATA */
+#define _USART_TXDATA_TXDATA_SHIFT              0                                   /**< Shift value for USART_TXDATA */
+#define _USART_TXDATA_TXDATA_MASK               0xFFUL                              /**< Bit mask for USART_TXDATA */
+#define _USART_TXDATA_TXDATA_DEFAULT            0x00000000UL                        /**< Mode DEFAULT for USART_TXDATA */
+#define USART_TXDATA_TXDATA_DEFAULT             (_USART_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDATA */
+
+/* Bit fields for USART TXDOUBLEX */
+#define _USART_TXDOUBLEX_RESETVALUE             0x00000000UL                              /**< Default value for USART_TXDOUBLEX */
+#define _USART_TXDOUBLEX_MASK                   0xF9FFF9FFUL                              /**< Mask for USART_TXDOUBLEX */
+#define _USART_TXDOUBLEX_TXDATA0_SHIFT          0                                         /**< Shift value for USART_TXDATA0 */
+#define _USART_TXDOUBLEX_TXDATA0_MASK           0x1FFUL                                   /**< Bit mask for USART_TXDATA0 */
+#define _USART_TXDOUBLEX_TXDATA0_DEFAULT        0x00000000UL                              /**< Mode DEFAULT for USART_TXDOUBLEX */
+#define USART_TXDOUBLEX_TXDATA0_DEFAULT         (_USART_TXDOUBLEX_TXDATA0_DEFAULT << 0)   /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
+#define USART_TXDOUBLEX_UBRXAT0                 (0x1UL << 11)                             /**< Unblock RX After Transmission */
+#define _USART_TXDOUBLEX_UBRXAT0_SHIFT          11                                        /**< Shift value for USART_UBRXAT0 */
+#define _USART_TXDOUBLEX_UBRXAT0_MASK           0x800UL                                   /**< Bit mask for USART_UBRXAT0 */
+#define _USART_TXDOUBLEX_UBRXAT0_DEFAULT        0x00000000UL                              /**< Mode DEFAULT for USART_TXDOUBLEX */
+#define USART_TXDOUBLEX_UBRXAT0_DEFAULT         (_USART_TXDOUBLEX_UBRXAT0_DEFAULT << 11)  /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
+#define USART_TXDOUBLEX_TXTRIAT0                (0x1UL << 12)                             /**< Set TXTRI After Transmission */
+#define _USART_TXDOUBLEX_TXTRIAT0_SHIFT         12                                        /**< Shift value for USART_TXTRIAT0 */
+#define _USART_TXDOUBLEX_TXTRIAT0_MASK          0x1000UL                                  /**< Bit mask for USART_TXTRIAT0 */
+#define _USART_TXDOUBLEX_TXTRIAT0_DEFAULT       0x00000000UL                              /**< Mode DEFAULT for USART_TXDOUBLEX */
+#define USART_TXDOUBLEX_TXTRIAT0_DEFAULT        (_USART_TXDOUBLEX_TXTRIAT0_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
+#define USART_TXDOUBLEX_TXBREAK0                (0x1UL << 13)                             /**< Transmit Data As Break */
+#define _USART_TXDOUBLEX_TXBREAK0_SHIFT         13                                        /**< Shift value for USART_TXBREAK0 */
+#define _USART_TXDOUBLEX_TXBREAK0_MASK          0x2000UL                                  /**< Bit mask for USART_TXBREAK0 */
+#define _USART_TXDOUBLEX_TXBREAK0_DEFAULT       0x00000000UL                              /**< Mode DEFAULT for USART_TXDOUBLEX */
+#define USART_TXDOUBLEX_TXBREAK0_DEFAULT        (_USART_TXDOUBLEX_TXBREAK0_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
+#define USART_TXDOUBLEX_TXDISAT0                (0x1UL << 14)                             /**< Clear TXEN After Transmission */
+#define _USART_TXDOUBLEX_TXDISAT0_SHIFT         14                                        /**< Shift value for USART_TXDISAT0 */
+#define _USART_TXDOUBLEX_TXDISAT0_MASK          0x4000UL                                  /**< Bit mask for USART_TXDISAT0 */
+#define _USART_TXDOUBLEX_TXDISAT0_DEFAULT       0x00000000UL                              /**< Mode DEFAULT for USART_TXDOUBLEX */
+#define USART_TXDOUBLEX_TXDISAT0_DEFAULT        (_USART_TXDOUBLEX_TXDISAT0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
+#define USART_TXDOUBLEX_RXENAT0                 (0x1UL << 15)                             /**< Enable RX After Transmission */
+#define _USART_TXDOUBLEX_RXENAT0_SHIFT          15                                        /**< Shift value for USART_RXENAT0 */
+#define _USART_TXDOUBLEX_RXENAT0_MASK           0x8000UL                                  /**< Bit mask for USART_RXENAT0 */
+#define _USART_TXDOUBLEX_RXENAT0_DEFAULT        0x00000000UL                              /**< Mode DEFAULT for USART_TXDOUBLEX */
+#define USART_TXDOUBLEX_RXENAT0_DEFAULT         (_USART_TXDOUBLEX_RXENAT0_DEFAULT << 15)  /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
+#define _USART_TXDOUBLEX_TXDATA1_SHIFT          16                                        /**< Shift value for USART_TXDATA1 */
+#define _USART_TXDOUBLEX_TXDATA1_MASK           0x1FF0000UL                               /**< Bit mask for USART_TXDATA1 */
+#define _USART_TXDOUBLEX_TXDATA1_DEFAULT        0x00000000UL                              /**< Mode DEFAULT for USART_TXDOUBLEX */
+#define USART_TXDOUBLEX_TXDATA1_DEFAULT         (_USART_TXDOUBLEX_TXDATA1_DEFAULT << 16)  /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
+#define USART_TXDOUBLEX_UBRXAT1                 (0x1UL << 27)                             /**< Unblock RX After Transmission */
+#define _USART_TXDOUBLEX_UBRXAT1_SHIFT          27                                        /**< Shift value for USART_UBRXAT1 */
+#define _USART_TXDOUBLEX_UBRXAT1_MASK           0x8000000UL                               /**< Bit mask for USART_UBRXAT1 */
+#define _USART_TXDOUBLEX_UBRXAT1_DEFAULT        0x00000000UL                              /**< Mode DEFAULT for USART_TXDOUBLEX */
+#define USART_TXDOUBLEX_UBRXAT1_DEFAULT         (_USART_TXDOUBLEX_UBRXAT1_DEFAULT << 27)  /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
+#define USART_TXDOUBLEX_TXTRIAT1                (0x1UL << 28)                             /**< Set TXTRI After Transmission */
+#define _USART_TXDOUBLEX_TXTRIAT1_SHIFT         28                                        /**< Shift value for USART_TXTRIAT1 */
+#define _USART_TXDOUBLEX_TXTRIAT1_MASK          0x10000000UL                              /**< Bit mask for USART_TXTRIAT1 */
+#define _USART_TXDOUBLEX_TXTRIAT1_DEFAULT       0x00000000UL                              /**< Mode DEFAULT for USART_TXDOUBLEX */
+#define USART_TXDOUBLEX_TXTRIAT1_DEFAULT        (_USART_TXDOUBLEX_TXTRIAT1_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
+#define USART_TXDOUBLEX_TXBREAK1                (0x1UL << 29)                             /**< Transmit Data As Break */
+#define _USART_TXDOUBLEX_TXBREAK1_SHIFT         29                                        /**< Shift value for USART_TXBREAK1 */
+#define _USART_TXDOUBLEX_TXBREAK1_MASK          0x20000000UL                              /**< Bit mask for USART_TXBREAK1 */
+#define _USART_TXDOUBLEX_TXBREAK1_DEFAULT       0x00000000UL                              /**< Mode DEFAULT for USART_TXDOUBLEX */
+#define USART_TXDOUBLEX_TXBREAK1_DEFAULT        (_USART_TXDOUBLEX_TXBREAK1_DEFAULT << 29) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
+#define USART_TXDOUBLEX_TXDISAT1                (0x1UL << 30)                             /**< Clear TXEN After Transmission */
+#define _USART_TXDOUBLEX_TXDISAT1_SHIFT         30                                        /**< Shift value for USART_TXDISAT1 */
+#define _USART_TXDOUBLEX_TXDISAT1_MASK          0x40000000UL                              /**< Bit mask for USART_TXDISAT1 */
+#define _USART_TXDOUBLEX_TXDISAT1_DEFAULT       0x00000000UL                              /**< Mode DEFAULT for USART_TXDOUBLEX */
+#define USART_TXDOUBLEX_TXDISAT1_DEFAULT        (_USART_TXDOUBLEX_TXDISAT1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
+#define USART_TXDOUBLEX_RXENAT1                 (0x1UL << 31)                             /**< Enable RX After Transmission */
+#define _USART_TXDOUBLEX_RXENAT1_SHIFT          31                                        /**< Shift value for USART_RXENAT1 */
+#define _USART_TXDOUBLEX_RXENAT1_MASK           0x80000000UL                              /**< Bit mask for USART_RXENAT1 */
+#define _USART_TXDOUBLEX_RXENAT1_DEFAULT        0x00000000UL                              /**< Mode DEFAULT for USART_TXDOUBLEX */
+#define USART_TXDOUBLEX_RXENAT1_DEFAULT         (_USART_TXDOUBLEX_RXENAT1_DEFAULT << 31)  /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
+
+/* Bit fields for USART TXDOUBLE */
+#define _USART_TXDOUBLE_RESETVALUE              0x00000000UL                           /**< Default value for USART_TXDOUBLE */
+#define _USART_TXDOUBLE_MASK                    0x0000FFFFUL                           /**< Mask for USART_TXDOUBLE */
+#define _USART_TXDOUBLE_TXDATA0_SHIFT           0                                      /**< Shift value for USART_TXDATA0 */
+#define _USART_TXDOUBLE_TXDATA0_MASK            0xFFUL                                 /**< Bit mask for USART_TXDATA0 */
+#define _USART_TXDOUBLE_TXDATA0_DEFAULT         0x00000000UL                           /**< Mode DEFAULT for USART_TXDOUBLE */
+#define USART_TXDOUBLE_TXDATA0_DEFAULT          (_USART_TXDOUBLE_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDOUBLE */
+#define _USART_TXDOUBLE_TXDATA1_SHIFT           8                                      /**< Shift value for USART_TXDATA1 */
+#define _USART_TXDOUBLE_TXDATA1_MASK            0xFF00UL                               /**< Bit mask for USART_TXDATA1 */
+#define _USART_TXDOUBLE_TXDATA1_DEFAULT         0x00000000UL                           /**< Mode DEFAULT for USART_TXDOUBLE */
+#define USART_TXDOUBLE_TXDATA1_DEFAULT          (_USART_TXDOUBLE_TXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_TXDOUBLE */
+
+/* Bit fields for USART IF */
+#define _USART_IF_RESETVALUE                    0x00000002UL                     /**< Default value for USART_IF */
+#define _USART_IF_MASK                          0x0001FFFFUL                     /**< Mask for USART_IF */
+#define USART_IF_TXC                            (0x1UL << 0)                     /**< TX Complete Interrupt Flag */
+#define _USART_IF_TXC_SHIFT                     0                                /**< Shift value for USART_TXC */
+#define _USART_IF_TXC_MASK                      0x1UL                            /**< Bit mask for USART_TXC */
+#define _USART_IF_TXC_DEFAULT                   0x00000000UL                     /**< Mode DEFAULT for USART_IF */
+#define USART_IF_TXC_DEFAULT                    (_USART_IF_TXC_DEFAULT << 0)     /**< Shifted mode DEFAULT for USART_IF */
+#define USART_IF_TXBL                           (0x1UL << 1)                     /**< TX Buffer Level Interrupt Flag */
+#define _USART_IF_TXBL_SHIFT                    1                                /**< Shift value for USART_TXBL */
+#define _USART_IF_TXBL_MASK                     0x2UL                            /**< Bit mask for USART_TXBL */
+#define _USART_IF_TXBL_DEFAULT                  0x00000001UL                     /**< Mode DEFAULT for USART_IF */
+#define USART_IF_TXBL_DEFAULT                   (_USART_IF_TXBL_DEFAULT << 1)    /**< Shifted mode DEFAULT for USART_IF */
+#define USART_IF_RXDATAV                        (0x1UL << 2)                     /**< RX Data Valid Interrupt Flag */
+#define _USART_IF_RXDATAV_SHIFT                 2                                /**< Shift value for USART_RXDATAV */
+#define _USART_IF_RXDATAV_MASK                  0x4UL                            /**< Bit mask for USART_RXDATAV */
+#define _USART_IF_RXDATAV_DEFAULT               0x00000000UL                     /**< Mode DEFAULT for USART_IF */
+#define USART_IF_RXDATAV_DEFAULT                (_USART_IF_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_IF */
+#define USART_IF_RXFULL                         (0x1UL << 3)                     /**< RX Buffer Full Interrupt Flag */
+#define _USART_IF_RXFULL_SHIFT                  3                                /**< Shift value for USART_RXFULL */
+#define _USART_IF_RXFULL_MASK                   0x8UL                            /**< Bit mask for USART_RXFULL */
+#define _USART_IF_RXFULL_DEFAULT                0x00000000UL                     /**< Mode DEFAULT for USART_IF */
+#define USART_IF_RXFULL_DEFAULT                 (_USART_IF_RXFULL_DEFAULT << 3)  /**< Shifted mode DEFAULT for USART_IF */
+#define USART_IF_RXOF                           (0x1UL << 4)                     /**< RX Overflow Interrupt Flag */
+#define _USART_IF_RXOF_SHIFT                    4                                /**< Shift value for USART_RXOF */
+#define _USART_IF_RXOF_MASK                     0x10UL                           /**< Bit mask for USART_RXOF */
+#define _USART_IF_RXOF_DEFAULT                  0x00000000UL                     /**< Mode DEFAULT for USART_IF */
+#define USART_IF_RXOF_DEFAULT                   (_USART_IF_RXOF_DEFAULT << 4)    /**< Shifted mode DEFAULT for USART_IF */
+#define USART_IF_RXUF                           (0x1UL << 5)                     /**< RX Underflow Interrupt Flag */
+#define _USART_IF_RXUF_SHIFT                    5                                /**< Shift value for USART_RXUF */
+#define _USART_IF_RXUF_MASK                     0x20UL                           /**< Bit mask for USART_RXUF */
+#define _USART_IF_RXUF_DEFAULT                  0x00000000UL                     /**< Mode DEFAULT for USART_IF */
+#define USART_IF_RXUF_DEFAULT                   (_USART_IF_RXUF_DEFAULT << 5)    /**< Shifted mode DEFAULT for USART_IF */
+#define USART_IF_TXOF                           (0x1UL << 6)                     /**< TX Overflow Interrupt Flag */
+#define _USART_IF_TXOF_SHIFT                    6                                /**< Shift value for USART_TXOF */
+#define _USART_IF_TXOF_MASK                     0x40UL                           /**< Bit mask for USART_TXOF */
+#define _USART_IF_TXOF_DEFAULT                  0x00000000UL                     /**< Mode DEFAULT for USART_IF */
+#define USART_IF_TXOF_DEFAULT                   (_USART_IF_TXOF_DEFAULT << 6)    /**< Shifted mode DEFAULT for USART_IF */
+#define USART_IF_TXUF                           (0x1UL << 7)                     /**< TX Underflow Interrupt Flag */
+#define _USART_IF_TXUF_SHIFT                    7                                /**< Shift value for USART_TXUF */
+#define _USART_IF_TXUF_MASK                     0x80UL                           /**< Bit mask for USART_TXUF */
+#define _USART_IF_TXUF_DEFAULT                  0x00000000UL                     /**< Mode DEFAULT for USART_IF */
+#define USART_IF_TXUF_DEFAULT                   (_USART_IF_TXUF_DEFAULT << 7)    /**< Shifted mode DEFAULT for USART_IF */
+#define USART_IF_PERR                           (0x1UL << 8)                     /**< Parity Error Interrupt Flag */
+#define _USART_IF_PERR_SHIFT                    8                                /**< Shift value for USART_PERR */
+#define _USART_IF_PERR_MASK                     0x100UL                          /**< Bit mask for USART_PERR */
+#define _USART_IF_PERR_DEFAULT                  0x00000000UL                     /**< Mode DEFAULT for USART_IF */
+#define USART_IF_PERR_DEFAULT                   (_USART_IF_PERR_DEFAULT << 8)    /**< Shifted mode DEFAULT for USART_IF */
+#define USART_IF_FERR                           (0x1UL << 9)                     /**< Framing Error Interrupt Flag */
+#define _USART_IF_FERR_SHIFT                    9                                /**< Shift value for USART_FERR */
+#define _USART_IF_FERR_MASK                     0x200UL                          /**< Bit mask for USART_FERR */
+#define _USART_IF_FERR_DEFAULT                  0x00000000UL                     /**< Mode DEFAULT for USART_IF */
+#define USART_IF_FERR_DEFAULT                   (_USART_IF_FERR_DEFAULT << 9)    /**< Shifted mode DEFAULT for USART_IF */
+#define USART_IF_MPAF                           (0x1UL << 10)                    /**< Multi-Processor Address Frame Interrupt Flag */
+#define _USART_IF_MPAF_SHIFT                    10                               /**< Shift value for USART_MPAF */
+#define _USART_IF_MPAF_MASK                     0x400UL                          /**< Bit mask for USART_MPAF */
+#define _USART_IF_MPAF_DEFAULT                  0x00000000UL                     /**< Mode DEFAULT for USART_IF */
+#define USART_IF_MPAF_DEFAULT                   (_USART_IF_MPAF_DEFAULT << 10)   /**< Shifted mode DEFAULT for USART_IF */
+#define USART_IF_SSM                            (0x1UL << 11)                    /**< Slave-Select In Master Mode Interrupt Flag */
+#define _USART_IF_SSM_SHIFT                     11                               /**< Shift value for USART_SSM */
+#define _USART_IF_SSM_MASK                      0x800UL                          /**< Bit mask for USART_SSM */
+#define _USART_IF_SSM_DEFAULT                   0x00000000UL                     /**< Mode DEFAULT for USART_IF */
+#define USART_IF_SSM_DEFAULT                    (_USART_IF_SSM_DEFAULT << 11)    /**< Shifted mode DEFAULT for USART_IF */
+#define USART_IF_CCF                            (0x1UL << 12)                    /**< Collision Check Fail Interrupt Flag */
+#define _USART_IF_CCF_SHIFT                     12                               /**< Shift value for USART_CCF */
+#define _USART_IF_CCF_MASK                      0x1000UL                         /**< Bit mask for USART_CCF */
+#define _USART_IF_CCF_DEFAULT                   0x00000000UL                     /**< Mode DEFAULT for USART_IF */
+#define USART_IF_CCF_DEFAULT                    (_USART_IF_CCF_DEFAULT << 12)    /**< Shifted mode DEFAULT for USART_IF */
+#define USART_IF_TXIDLE                         (0x1UL << 13)                    /**< TX Idle Interrupt Flag */
+#define _USART_IF_TXIDLE_SHIFT                  13                               /**< Shift value for USART_TXIDLE */
+#define _USART_IF_TXIDLE_MASK                   0x2000UL                         /**< Bit mask for USART_TXIDLE */
+#define _USART_IF_TXIDLE_DEFAULT                0x00000000UL                     /**< Mode DEFAULT for USART_IF */
+#define USART_IF_TXIDLE_DEFAULT                 (_USART_IF_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IF */
+#define USART_IF_TCMP0                          (0x1UL << 14)                    /**< Timer comparator 0 Interrupt Flag */
+#define _USART_IF_TCMP0_SHIFT                   14                               /**< Shift value for USART_TCMP0 */
+#define _USART_IF_TCMP0_MASK                    0x4000UL                         /**< Bit mask for USART_TCMP0 */
+#define _USART_IF_TCMP0_DEFAULT                 0x00000000UL                     /**< Mode DEFAULT for USART_IF */
+#define USART_IF_TCMP0_DEFAULT                  (_USART_IF_TCMP0_DEFAULT << 14)  /**< Shifted mode DEFAULT for USART_IF */
+#define USART_IF_TCMP1                          (0x1UL << 15)                    /**< Timer comparator 1 Interrupt Flag */
+#define _USART_IF_TCMP1_SHIFT                   15                               /**< Shift value for USART_TCMP1 */
+#define _USART_IF_TCMP1_MASK                    0x8000UL                         /**< Bit mask for USART_TCMP1 */
+#define _USART_IF_TCMP1_DEFAULT                 0x00000000UL                     /**< Mode DEFAULT for USART_IF */
+#define USART_IF_TCMP1_DEFAULT                  (_USART_IF_TCMP1_DEFAULT << 15)  /**< Shifted mode DEFAULT for USART_IF */
+#define USART_IF_TCMP2                          (0x1UL << 16)                    /**< Timer comparator 2 Interrupt Flag */
+#define _USART_IF_TCMP2_SHIFT                   16                               /**< Shift value for USART_TCMP2 */
+#define _USART_IF_TCMP2_MASK                    0x10000UL                        /**< Bit mask for USART_TCMP2 */
+#define _USART_IF_TCMP2_DEFAULT                 0x00000000UL                     /**< Mode DEFAULT for USART_IF */
+#define USART_IF_TCMP2_DEFAULT                  (_USART_IF_TCMP2_DEFAULT << 16)  /**< Shifted mode DEFAULT for USART_IF */
+
+/* Bit fields for USART IFS */
+#define _USART_IFS_RESETVALUE                   0x00000000UL                      /**< Default value for USART_IFS */
+#define _USART_IFS_MASK                         0x0001FFF9UL                      /**< Mask for USART_IFS */
+#define USART_IFS_TXC                           (0x1UL << 0)                      /**< Set TXC Interrupt Flag */
+#define _USART_IFS_TXC_SHIFT                    0                                 /**< Shift value for USART_TXC */
+#define _USART_IFS_TXC_MASK                     0x1UL                             /**< Bit mask for USART_TXC */
+#define _USART_IFS_TXC_DEFAULT                  0x00000000UL                      /**< Mode DEFAULT for USART_IFS */
+#define USART_IFS_TXC_DEFAULT                   (_USART_IFS_TXC_DEFAULT << 0)     /**< Shifted mode DEFAULT for USART_IFS */
+#define USART_IFS_RXFULL                        (0x1UL << 3)                      /**< Set RXFULL Interrupt Flag */
+#define _USART_IFS_RXFULL_SHIFT                 3                                 /**< Shift value for USART_RXFULL */
+#define _USART_IFS_RXFULL_MASK                  0x8UL                             /**< Bit mask for USART_RXFULL */
+#define _USART_IFS_RXFULL_DEFAULT               0x00000000UL                      /**< Mode DEFAULT for USART_IFS */
+#define USART_IFS_RXFULL_DEFAULT                (_USART_IFS_RXFULL_DEFAULT << 3)  /**< Shifted mode DEFAULT for USART_IFS */
+#define USART_IFS_RXOF                          (0x1UL << 4)                      /**< Set RXOF Interrupt Flag */
+#define _USART_IFS_RXOF_SHIFT                   4                                 /**< Shift value for USART_RXOF */
+#define _USART_IFS_RXOF_MASK                    0x10UL                            /**< Bit mask for USART_RXOF */
+#define _USART_IFS_RXOF_DEFAULT                 0x00000000UL                      /**< Mode DEFAULT for USART_IFS */
+#define USART_IFS_RXOF_DEFAULT                  (_USART_IFS_RXOF_DEFAULT << 4)    /**< Shifted mode DEFAULT for USART_IFS */
+#define USART_IFS_RXUF                          (0x1UL << 5)                      /**< Set RXUF Interrupt Flag */
+#define _USART_IFS_RXUF_SHIFT                   5                                 /**< Shift value for USART_RXUF */
+#define _USART_IFS_RXUF_MASK                    0x20UL                            /**< Bit mask for USART_RXUF */
+#define _USART_IFS_RXUF_DEFAULT                 0x00000000UL                      /**< Mode DEFAULT for USART_IFS */
+#define USART_IFS_RXUF_DEFAULT                  (_USART_IFS_RXUF_DEFAULT << 5)    /**< Shifted mode DEFAULT for USART_IFS */
+#define USART_IFS_TXOF                          (0x1UL << 6)                      /**< Set TXOF Interrupt Flag */
+#define _USART_IFS_TXOF_SHIFT                   6                                 /**< Shift value for USART_TXOF */
+#define _USART_IFS_TXOF_MASK                    0x40UL                            /**< Bit mask for USART_TXOF */
+#define _USART_IFS_TXOF_DEFAULT                 0x00000000UL                      /**< Mode DEFAULT for USART_IFS */
+#define USART_IFS_TXOF_DEFAULT                  (_USART_IFS_TXOF_DEFAULT << 6)    /**< Shifted mode DEFAULT for USART_IFS */
+#define USART_IFS_TXUF                          (0x1UL << 7)                      /**< Set TXUF Interrupt Flag */
+#define _USART_IFS_TXUF_SHIFT                   7                                 /**< Shift value for USART_TXUF */
+#define _USART_IFS_TXUF_MASK                    0x80UL                            /**< Bit mask for USART_TXUF */
+#define _USART_IFS_TXUF_DEFAULT                 0x00000000UL                      /**< Mode DEFAULT for USART_IFS */
+#define USART_IFS_TXUF_DEFAULT                  (_USART_IFS_TXUF_DEFAULT << 7)    /**< Shifted mode DEFAULT for USART_IFS */
+#define USART_IFS_PERR                          (0x1UL << 8)                      /**< Set PERR Interrupt Flag */
+#define _USART_IFS_PERR_SHIFT                   8                                 /**< Shift value for USART_PERR */
+#define _USART_IFS_PERR_MASK                    0x100UL                           /**< Bit mask for USART_PERR */
+#define _USART_IFS_PERR_DEFAULT                 0x00000000UL                      /**< Mode DEFAULT for USART_IFS */
+#define USART_IFS_PERR_DEFAULT                  (_USART_IFS_PERR_DEFAULT << 8)    /**< Shifted mode DEFAULT for USART_IFS */
+#define USART_IFS_FERR                          (0x1UL << 9)                      /**< Set FERR Interrupt Flag */
+#define _USART_IFS_FERR_SHIFT                   9                                 /**< Shift value for USART_FERR */
+#define _USART_IFS_FERR_MASK                    0x200UL                           /**< Bit mask for USART_FERR */
+#define _USART_IFS_FERR_DEFAULT                 0x00000000UL                      /**< Mode DEFAULT for USART_IFS */
+#define USART_IFS_FERR_DEFAULT                  (_USART_IFS_FERR_DEFAULT << 9)    /**< Shifted mode DEFAULT for USART_IFS */
+#define USART_IFS_MPAF                          (0x1UL << 10)                     /**< Set MPAF Interrupt Flag */
+#define _USART_IFS_MPAF_SHIFT                   10                                /**< Shift value for USART_MPAF */
+#define _USART_IFS_MPAF_MASK                    0x400UL                           /**< Bit mask for USART_MPAF */
+#define _USART_IFS_MPAF_DEFAULT                 0x00000000UL                      /**< Mode DEFAULT for USART_IFS */
+#define USART_IFS_MPAF_DEFAULT                  (_USART_IFS_MPAF_DEFAULT << 10)   /**< Shifted mode DEFAULT for USART_IFS */
+#define USART_IFS_SSM                           (0x1UL << 11)                     /**< Set SSM Interrupt Flag */
+#define _USART_IFS_SSM_SHIFT                    11                                /**< Shift value for USART_SSM */
+#define _USART_IFS_SSM_MASK                     0x800UL                           /**< Bit mask for USART_SSM */
+#define _USART_IFS_SSM_DEFAULT                  0x00000000UL                      /**< Mode DEFAULT for USART_IFS */
+#define USART_IFS_SSM_DEFAULT                   (_USART_IFS_SSM_DEFAULT << 11)    /**< Shifted mode DEFAULT for USART_IFS */
+#define USART_IFS_CCF                           (0x1UL << 12)                     /**< Set CCF Interrupt Flag */
+#define _USART_IFS_CCF_SHIFT                    12                                /**< Shift value for USART_CCF */
+#define _USART_IFS_CCF_MASK                     0x1000UL                          /**< Bit mask for USART_CCF */
+#define _USART_IFS_CCF_DEFAULT                  0x00000000UL                      /**< Mode DEFAULT for USART_IFS */
+#define USART_IFS_CCF_DEFAULT                   (_USART_IFS_CCF_DEFAULT << 12)    /**< Shifted mode DEFAULT for USART_IFS */
+#define USART_IFS_TXIDLE                        (0x1UL << 13)                     /**< Set TXIDLE Interrupt Flag */
+#define _USART_IFS_TXIDLE_SHIFT                 13                                /**< Shift value for USART_TXIDLE */
+#define _USART_IFS_TXIDLE_MASK                  0x2000UL                          /**< Bit mask for USART_TXIDLE */
+#define _USART_IFS_TXIDLE_DEFAULT               0x00000000UL                      /**< Mode DEFAULT for USART_IFS */
+#define USART_IFS_TXIDLE_DEFAULT                (_USART_IFS_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IFS */
+#define USART_IFS_TCMP0                         (0x1UL << 14)                     /**< Set TCMP0 Interrupt Flag */
+#define _USART_IFS_TCMP0_SHIFT                  14                                /**< Shift value for USART_TCMP0 */
+#define _USART_IFS_TCMP0_MASK                   0x4000UL                          /**< Bit mask for USART_TCMP0 */
+#define _USART_IFS_TCMP0_DEFAULT                0x00000000UL                      /**< Mode DEFAULT for USART_IFS */
+#define USART_IFS_TCMP0_DEFAULT                 (_USART_IFS_TCMP0_DEFAULT << 14)  /**< Shifted mode DEFAULT for USART_IFS */
+#define USART_IFS_TCMP1                         (0x1UL << 15)                     /**< Set TCMP1 Interrupt Flag */
+#define _USART_IFS_TCMP1_SHIFT                  15                                /**< Shift value for USART_TCMP1 */
+#define _USART_IFS_TCMP1_MASK                   0x8000UL                          /**< Bit mask for USART_TCMP1 */
+#define _USART_IFS_TCMP1_DEFAULT                0x00000000UL                      /**< Mode DEFAULT for USART_IFS */
+#define USART_IFS_TCMP1_DEFAULT                 (_USART_IFS_TCMP1_DEFAULT << 15)  /**< Shifted mode DEFAULT for USART_IFS */
+#define USART_IFS_TCMP2                         (0x1UL << 16)                     /**< Set TCMP2 Interrupt Flag */
+#define _USART_IFS_TCMP2_SHIFT                  16                                /**< Shift value for USART_TCMP2 */
+#define _USART_IFS_TCMP2_MASK                   0x10000UL                         /**< Bit mask for USART_TCMP2 */
+#define _USART_IFS_TCMP2_DEFAULT                0x00000000UL                      /**< Mode DEFAULT for USART_IFS */
+#define USART_IFS_TCMP2_DEFAULT                 (_USART_IFS_TCMP2_DEFAULT << 16)  /**< Shifted mode DEFAULT for USART_IFS */
+
+/* Bit fields for USART IFC */
+#define _USART_IFC_RESETVALUE                   0x00000000UL                      /**< Default value for USART_IFC */
+#define _USART_IFC_MASK                         0x0001FFF9UL                      /**< Mask for USART_IFC */
+#define USART_IFC_TXC                           (0x1UL << 0)                      /**< Clear TXC Interrupt Flag */
+#define _USART_IFC_TXC_SHIFT                    0                                 /**< Shift value for USART_TXC */
+#define _USART_IFC_TXC_MASK                     0x1UL                             /**< Bit mask for USART_TXC */
+#define _USART_IFC_TXC_DEFAULT                  0x00000000UL                      /**< Mode DEFAULT for USART_IFC */
+#define USART_IFC_TXC_DEFAULT                   (_USART_IFC_TXC_DEFAULT << 0)     /**< Shifted mode DEFAULT for USART_IFC */
+#define USART_IFC_RXFULL                        (0x1UL << 3)                      /**< Clear RXFULL Interrupt Flag */
+#define _USART_IFC_RXFULL_SHIFT                 3                                 /**< Shift value for USART_RXFULL */
+#define _USART_IFC_RXFULL_MASK                  0x8UL                             /**< Bit mask for USART_RXFULL */
+#define _USART_IFC_RXFULL_DEFAULT               0x00000000UL                      /**< Mode DEFAULT for USART_IFC */
+#define USART_IFC_RXFULL_DEFAULT                (_USART_IFC_RXFULL_DEFAULT << 3)  /**< Shifted mode DEFAULT for USART_IFC */
+#define USART_IFC_RXOF                          (0x1UL << 4)                      /**< Clear RXOF Interrupt Flag */
+#define _USART_IFC_RXOF_SHIFT                   4                                 /**< Shift value for USART_RXOF */
+#define _USART_IFC_RXOF_MASK                    0x10UL                            /**< Bit mask for USART_RXOF */
+#define _USART_IFC_RXOF_DEFAULT                 0x00000000UL                      /**< Mode DEFAULT for USART_IFC */
+#define USART_IFC_RXOF_DEFAULT                  (_USART_IFC_RXOF_DEFAULT << 4)    /**< Shifted mode DEFAULT for USART_IFC */
+#define USART_IFC_RXUF                          (0x1UL << 5)                      /**< Clear RXUF Interrupt Flag */
+#define _USART_IFC_RXUF_SHIFT                   5                                 /**< Shift value for USART_RXUF */
+#define _USART_IFC_RXUF_MASK                    0x20UL                            /**< Bit mask for USART_RXUF */
+#define _USART_IFC_RXUF_DEFAULT                 0x00000000UL                      /**< Mode DEFAULT for USART_IFC */
+#define USART_IFC_RXUF_DEFAULT                  (_USART_IFC_RXUF_DEFAULT << 5)    /**< Shifted mode DEFAULT for USART_IFC */
+#define USART_IFC_TXOF                          (0x1UL << 6)                      /**< Clear TXOF Interrupt Flag */
+#define _USART_IFC_TXOF_SHIFT                   6                                 /**< Shift value for USART_TXOF */
+#define _USART_IFC_TXOF_MASK                    0x40UL                            /**< Bit mask for USART_TXOF */
+#define _USART_IFC_TXOF_DEFAULT                 0x00000000UL                      /**< Mode DEFAULT for USART_IFC */
+#define USART_IFC_TXOF_DEFAULT                  (_USART_IFC_TXOF_DEFAULT << 6)    /**< Shifted mode DEFAULT for USART_IFC */
+#define USART_IFC_TXUF                          (0x1UL << 7)                      /**< Clear TXUF Interrupt Flag */
+#define _USART_IFC_TXUF_SHIFT                   7                                 /**< Shift value for USART_TXUF */
+#define _USART_IFC_TXUF_MASK                    0x80UL                            /**< Bit mask for USART_TXUF */
+#define _USART_IFC_TXUF_DEFAULT                 0x00000000UL                      /**< Mode DEFAULT for USART_IFC */
+#define USART_IFC_TXUF_DEFAULT                  (_USART_IFC_TXUF_DEFAULT << 7)    /**< Shifted mode DEFAULT for USART_IFC */
+#define USART_IFC_PERR                          (0x1UL << 8)                      /**< Clear PERR Interrupt Flag */
+#define _USART_IFC_PERR_SHIFT                   8                                 /**< Shift value for USART_PERR */
+#define _USART_IFC_PERR_MASK                    0x100UL                           /**< Bit mask for USART_PERR */
+#define _USART_IFC_PERR_DEFAULT                 0x00000000UL                      /**< Mode DEFAULT for USART_IFC */
+#define USART_IFC_PERR_DEFAULT                  (_USART_IFC_PERR_DEFAULT << 8)    /**< Shifted mode DEFAULT for USART_IFC */
+#define USART_IFC_FERR                          (0x1UL << 9)                      /**< Clear FERR Interrupt Flag */
+#define _USART_IFC_FERR_SHIFT                   9                                 /**< Shift value for USART_FERR */
+#define _USART_IFC_FERR_MASK                    0x200UL                           /**< Bit mask for USART_FERR */
+#define _USART_IFC_FERR_DEFAULT                 0x00000000UL                      /**< Mode DEFAULT for USART_IFC */
+#define USART_IFC_FERR_DEFAULT                  (_USART_IFC_FERR_DEFAULT << 9)    /**< Shifted mode DEFAULT for USART_IFC */
+#define USART_IFC_MPAF                          (0x1UL << 10)                     /**< Clear MPAF Interrupt Flag */
+#define _USART_IFC_MPAF_SHIFT                   10                                /**< Shift value for USART_MPAF */
+#define _USART_IFC_MPAF_MASK                    0x400UL                           /**< Bit mask for USART_MPAF */
+#define _USART_IFC_MPAF_DEFAULT                 0x00000000UL                      /**< Mode DEFAULT for USART_IFC */
+#define USART_IFC_MPAF_DEFAULT                  (_USART_IFC_MPAF_DEFAULT << 10)   /**< Shifted mode DEFAULT for USART_IFC */
+#define USART_IFC_SSM                           (0x1UL << 11)                     /**< Clear SSM Interrupt Flag */
+#define _USART_IFC_SSM_SHIFT                    11                                /**< Shift value for USART_SSM */
+#define _USART_IFC_SSM_MASK                     0x800UL                           /**< Bit mask for USART_SSM */
+#define _USART_IFC_SSM_DEFAULT                  0x00000000UL                      /**< Mode DEFAULT for USART_IFC */
+#define USART_IFC_SSM_DEFAULT                   (_USART_IFC_SSM_DEFAULT << 11)    /**< Shifted mode DEFAULT for USART_IFC */
+#define USART_IFC_CCF                           (0x1UL << 12)                     /**< Clear CCF Interrupt Flag */
+#define _USART_IFC_CCF_SHIFT                    12                                /**< Shift value for USART_CCF */
+#define _USART_IFC_CCF_MASK                     0x1000UL                          /**< Bit mask for USART_CCF */
+#define _USART_IFC_CCF_DEFAULT                  0x00000000UL                      /**< Mode DEFAULT for USART_IFC */
+#define USART_IFC_CCF_DEFAULT                   (_USART_IFC_CCF_DEFAULT << 12)    /**< Shifted mode DEFAULT for USART_IFC */
+#define USART_IFC_TXIDLE                        (0x1UL << 13)                     /**< Clear TXIDLE Interrupt Flag */
+#define _USART_IFC_TXIDLE_SHIFT                 13                                /**< Shift value for USART_TXIDLE */
+#define _USART_IFC_TXIDLE_MASK                  0x2000UL                          /**< Bit mask for USART_TXIDLE */
+#define _USART_IFC_TXIDLE_DEFAULT               0x00000000UL                      /**< Mode DEFAULT for USART_IFC */
+#define USART_IFC_TXIDLE_DEFAULT                (_USART_IFC_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IFC */
+#define USART_IFC_TCMP0                         (0x1UL << 14)                     /**< Clear TCMP0 Interrupt Flag */
+#define _USART_IFC_TCMP0_SHIFT                  14                                /**< Shift value for USART_TCMP0 */
+#define _USART_IFC_TCMP0_MASK                   0x4000UL                          /**< Bit mask for USART_TCMP0 */
+#define _USART_IFC_TCMP0_DEFAULT                0x00000000UL                      /**< Mode DEFAULT for USART_IFC */
+#define USART_IFC_TCMP0_DEFAULT                 (_USART_IFC_TCMP0_DEFAULT << 14)  /**< Shifted mode DEFAULT for USART_IFC */
+#define USART_IFC_TCMP1                         (0x1UL << 15)                     /**< Clear TCMP1 Interrupt Flag */
+#define _USART_IFC_TCMP1_SHIFT                  15                                /**< Shift value for USART_TCMP1 */
+#define _USART_IFC_TCMP1_MASK                   0x8000UL                          /**< Bit mask for USART_TCMP1 */
+#define _USART_IFC_TCMP1_DEFAULT                0x00000000UL                      /**< Mode DEFAULT for USART_IFC */
+#define USART_IFC_TCMP1_DEFAULT                 (_USART_IFC_TCMP1_DEFAULT << 15)  /**< Shifted mode DEFAULT for USART_IFC */
+#define USART_IFC_TCMP2                         (0x1UL << 16)                     /**< Clear TCMP2 Interrupt Flag */
+#define _USART_IFC_TCMP2_SHIFT                  16                                /**< Shift value for USART_TCMP2 */
+#define _USART_IFC_TCMP2_MASK                   0x10000UL                         /**< Bit mask for USART_TCMP2 */
+#define _USART_IFC_TCMP2_DEFAULT                0x00000000UL                      /**< Mode DEFAULT for USART_IFC */
+#define USART_IFC_TCMP2_DEFAULT                 (_USART_IFC_TCMP2_DEFAULT << 16)  /**< Shifted mode DEFAULT for USART_IFC */
+
+/* Bit fields for USART IEN */
+#define _USART_IEN_RESETVALUE                   0x00000000UL                      /**< Default value for USART_IEN */
+#define _USART_IEN_MASK                         0x0001FFFFUL                      /**< Mask for USART_IEN */
+#define USART_IEN_TXC                           (0x1UL << 0)                      /**< TXC Interrupt Enable */
+#define _USART_IEN_TXC_SHIFT                    0                                 /**< Shift value for USART_TXC */
+#define _USART_IEN_TXC_MASK                     0x1UL                             /**< Bit mask for USART_TXC */
+#define _USART_IEN_TXC_DEFAULT                  0x00000000UL                      /**< Mode DEFAULT for USART_IEN */
+#define USART_IEN_TXC_DEFAULT                   (_USART_IEN_TXC_DEFAULT << 0)     /**< Shifted mode DEFAULT for USART_IEN */
+#define USART_IEN_TXBL                          (0x1UL << 1)                      /**< TXBL Interrupt Enable */
+#define _USART_IEN_TXBL_SHIFT                   1                                 /**< Shift value for USART_TXBL */
+#define _USART_IEN_TXBL_MASK                    0x2UL                             /**< Bit mask for USART_TXBL */
+#define _USART_IEN_TXBL_DEFAULT                 0x00000000UL                      /**< Mode DEFAULT for USART_IEN */
+#define USART_IEN_TXBL_DEFAULT                  (_USART_IEN_TXBL_DEFAULT << 1)    /**< Shifted mode DEFAULT for USART_IEN */
+#define USART_IEN_RXDATAV                       (0x1UL << 2)                      /**< RXDATAV Interrupt Enable */
+#define _USART_IEN_RXDATAV_SHIFT                2                                 /**< Shift value for USART_RXDATAV */
+#define _USART_IEN_RXDATAV_MASK                 0x4UL                             /**< Bit mask for USART_RXDATAV */
+#define _USART_IEN_RXDATAV_DEFAULT              0x00000000UL                      /**< Mode DEFAULT for USART_IEN */
+#define USART_IEN_RXDATAV_DEFAULT               (_USART_IEN_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_IEN */
+#define USART_IEN_RXFULL                        (0x1UL << 3)                      /**< RXFULL Interrupt Enable */
+#define _USART_IEN_RXFULL_SHIFT                 3                                 /**< Shift value for USART_RXFULL */
+#define _USART_IEN_RXFULL_MASK                  0x8UL                             /**< Bit mask for USART_RXFULL */
+#define _USART_IEN_RXFULL_DEFAULT               0x00000000UL                      /**< Mode DEFAULT for USART_IEN */
+#define USART_IEN_RXFULL_DEFAULT                (_USART_IEN_RXFULL_DEFAULT << 3)  /**< Shifted mode DEFAULT for USART_IEN */
+#define USART_IEN_RXOF                          (0x1UL << 4)                      /**< RXOF Interrupt Enable */
+#define _USART_IEN_RXOF_SHIFT                   4                                 /**< Shift value for USART_RXOF */
+#define _USART_IEN_RXOF_MASK                    0x10UL                            /**< Bit mask for USART_RXOF */
+#define _USART_IEN_RXOF_DEFAULT                 0x00000000UL                      /**< Mode DEFAULT for USART_IEN */
+#define USART_IEN_RXOF_DEFAULT                  (_USART_IEN_RXOF_DEFAULT << 4)    /**< Shifted mode DEFAULT for USART_IEN */
+#define USART_IEN_RXUF                          (0x1UL << 5)                      /**< RXUF Interrupt Enable */
+#define _USART_IEN_RXUF_SHIFT                   5                                 /**< Shift value for USART_RXUF */
+#define _USART_IEN_RXUF_MASK                    0x20UL                            /**< Bit mask for USART_RXUF */
+#define _USART_IEN_RXUF_DEFAULT                 0x00000000UL                      /**< Mode DEFAULT for USART_IEN */
+#define USART_IEN_RXUF_DEFAULT                  (_USART_IEN_RXUF_DEFAULT << 5)    /**< Shifted mode DEFAULT for USART_IEN */
+#define USART_IEN_TXOF                          (0x1UL << 6)                      /**< TXOF Interrupt Enable */
+#define _USART_IEN_TXOF_SHIFT                   6                                 /**< Shift value for USART_TXOF */
+#define _USART_IEN_TXOF_MASK                    0x40UL                            /**< Bit mask for USART_TXOF */
+#define _USART_IEN_TXOF_DEFAULT                 0x00000000UL                      /**< Mode DEFAULT for USART_IEN */
+#define USART_IEN_TXOF_DEFAULT                  (_USART_IEN_TXOF_DEFAULT << 6)    /**< Shifted mode DEFAULT for USART_IEN */
+#define USART_IEN_TXUF                          (0x1UL << 7)                      /**< TXUF Interrupt Enable */
+#define _USART_IEN_TXUF_SHIFT                   7                                 /**< Shift value for USART_TXUF */
+#define _USART_IEN_TXUF_MASK                    0x80UL                            /**< Bit mask for USART_TXUF */
+#define _USART_IEN_TXUF_DEFAULT                 0x00000000UL                      /**< Mode DEFAULT for USART_IEN */
+#define USART_IEN_TXUF_DEFAULT                  (_USART_IEN_TXUF_DEFAULT << 7)    /**< Shifted mode DEFAULT for USART_IEN */
+#define USART_IEN_PERR                          (0x1UL << 8)                      /**< PERR Interrupt Enable */
+#define _USART_IEN_PERR_SHIFT                   8                                 /**< Shift value for USART_PERR */
+#define _USART_IEN_PERR_MASK                    0x100UL                           /**< Bit mask for USART_PERR */
+#define _USART_IEN_PERR_DEFAULT                 0x00000000UL                      /**< Mode DEFAULT for USART_IEN */
+#define USART_IEN_PERR_DEFAULT                  (_USART_IEN_PERR_DEFAULT << 8)    /**< Shifted mode DEFAULT for USART_IEN */
+#define USART_IEN_FERR                          (0x1UL << 9)                      /**< FERR Interrupt Enable */
+#define _USART_IEN_FERR_SHIFT                   9                                 /**< Shift value for USART_FERR */
+#define _USART_IEN_FERR_MASK                    0x200UL                           /**< Bit mask for USART_FERR */
+#define _USART_IEN_FERR_DEFAULT                 0x00000000UL                      /**< Mode DEFAULT for USART_IEN */
+#define USART_IEN_FERR_DEFAULT                  (_USART_IEN_FERR_DEFAULT << 9)    /**< Shifted mode DEFAULT for USART_IEN */
+#define USART_IEN_MPAF                          (0x1UL << 10)                     /**< MPAF Interrupt Enable */
+#define _USART_IEN_MPAF_SHIFT                   10                                /**< Shift value for USART_MPAF */
+#define _USART_IEN_MPAF_MASK                    0x400UL                           /**< Bit mask for USART_MPAF */
+#define _USART_IEN_MPAF_DEFAULT                 0x00000000UL                      /**< Mode DEFAULT for USART_IEN */
+#define USART_IEN_MPAF_DEFAULT                  (_USART_IEN_MPAF_DEFAULT << 10)   /**< Shifted mode DEFAULT for USART_IEN */
+#define USART_IEN_SSM                           (0x1UL << 11)                     /**< SSM Interrupt Enable */
+#define _USART_IEN_SSM_SHIFT                    11                                /**< Shift value for USART_SSM */
+#define _USART_IEN_SSM_MASK                     0x800UL                           /**< Bit mask for USART_SSM */
+#define _USART_IEN_SSM_DEFAULT                  0x00000000UL                      /**< Mode DEFAULT for USART_IEN */
+#define USART_IEN_SSM_DEFAULT                   (_USART_IEN_SSM_DEFAULT << 11)    /**< Shifted mode DEFAULT for USART_IEN */
+#define USART_IEN_CCF                           (0x1UL << 12)                     /**< CCF Interrupt Enable */
+#define _USART_IEN_CCF_SHIFT                    12                                /**< Shift value for USART_CCF */
+#define _USART_IEN_CCF_MASK                     0x1000UL                          /**< Bit mask for USART_CCF */
+#define _USART_IEN_CCF_DEFAULT                  0x00000000UL                      /**< Mode DEFAULT for USART_IEN */
+#define USART_IEN_CCF_DEFAULT                   (_USART_IEN_CCF_DEFAULT << 12)    /**< Shifted mode DEFAULT for USART_IEN */
+#define USART_IEN_TXIDLE                        (0x1UL << 13)                     /**< TXIDLE Interrupt Enable */
+#define _USART_IEN_TXIDLE_SHIFT                 13                                /**< Shift value for USART_TXIDLE */
+#define _USART_IEN_TXIDLE_MASK                  0x2000UL                          /**< Bit mask for USART_TXIDLE */
+#define _USART_IEN_TXIDLE_DEFAULT               0x00000000UL                      /**< Mode DEFAULT for USART_IEN */
+#define USART_IEN_TXIDLE_DEFAULT                (_USART_IEN_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IEN */
+#define USART_IEN_TCMP0                         (0x1UL << 14)                     /**< TCMP0 Interrupt Enable */
+#define _USART_IEN_TCMP0_SHIFT                  14                                /**< Shift value for USART_TCMP0 */
+#define _USART_IEN_TCMP0_MASK                   0x4000UL                          /**< Bit mask for USART_TCMP0 */
+#define _USART_IEN_TCMP0_DEFAULT                0x00000000UL                      /**< Mode DEFAULT for USART_IEN */
+#define USART_IEN_TCMP0_DEFAULT                 (_USART_IEN_TCMP0_DEFAULT << 14)  /**< Shifted mode DEFAULT for USART_IEN */
+#define USART_IEN_TCMP1                         (0x1UL << 15)                     /**< TCMP1 Interrupt Enable */
+#define _USART_IEN_TCMP1_SHIFT                  15                                /**< Shift value for USART_TCMP1 */
+#define _USART_IEN_TCMP1_MASK                   0x8000UL                          /**< Bit mask for USART_TCMP1 */
+#define _USART_IEN_TCMP1_DEFAULT                0x00000000UL                      /**< Mode DEFAULT for USART_IEN */
+#define USART_IEN_TCMP1_DEFAULT                 (_USART_IEN_TCMP1_DEFAULT << 15)  /**< Shifted mode DEFAULT for USART_IEN */
+#define USART_IEN_TCMP2                         (0x1UL << 16)                     /**< TCMP2 Interrupt Enable */
+#define _USART_IEN_TCMP2_SHIFT                  16                                /**< Shift value for USART_TCMP2 */
+#define _USART_IEN_TCMP2_MASK                   0x10000UL                         /**< Bit mask for USART_TCMP2 */
+#define _USART_IEN_TCMP2_DEFAULT                0x00000000UL                      /**< Mode DEFAULT for USART_IEN */
+#define USART_IEN_TCMP2_DEFAULT                 (_USART_IEN_TCMP2_DEFAULT << 16)  /**< Shifted mode DEFAULT for USART_IEN */
+
+/* Bit fields for USART IRCTRL */
+#define _USART_IRCTRL_RESETVALUE                0x00000000UL                          /**< Default value for USART_IRCTRL */
+#define _USART_IRCTRL_MASK                      0x00000F8FUL                          /**< Mask for USART_IRCTRL */
+#define USART_IRCTRL_IREN                       (0x1UL << 0)                          /**< Enable IrDA Module */
+#define _USART_IRCTRL_IREN_SHIFT                0                                     /**< Shift value for USART_IREN */
+#define _USART_IRCTRL_IREN_MASK                 0x1UL                                 /**< Bit mask for USART_IREN */
+#define _USART_IRCTRL_IREN_DEFAULT              0x00000000UL                          /**< Mode DEFAULT for USART_IRCTRL */
+#define USART_IRCTRL_IREN_DEFAULT               (_USART_IRCTRL_IREN_DEFAULT << 0)     /**< Shifted mode DEFAULT for USART_IRCTRL */
+#define _USART_IRCTRL_IRPW_SHIFT                1                                     /**< Shift value for USART_IRPW */
+#define _USART_IRCTRL_IRPW_MASK                 0x6UL                                 /**< Bit mask for USART_IRPW */
+#define _USART_IRCTRL_IRPW_DEFAULT              0x00000000UL                          /**< Mode DEFAULT for USART_IRCTRL */
+#define _USART_IRCTRL_IRPW_ONE                  0x00000000UL                          /**< Mode ONE for USART_IRCTRL */
+#define _USART_IRCTRL_IRPW_TWO                  0x00000001UL                          /**< Mode TWO for USART_IRCTRL */
+#define _USART_IRCTRL_IRPW_THREE                0x00000002UL                          /**< Mode THREE for USART_IRCTRL */
+#define _USART_IRCTRL_IRPW_FOUR                 0x00000003UL                          /**< Mode FOUR for USART_IRCTRL */
+#define USART_IRCTRL_IRPW_DEFAULT               (_USART_IRCTRL_IRPW_DEFAULT << 1)     /**< Shifted mode DEFAULT for USART_IRCTRL */
+#define USART_IRCTRL_IRPW_ONE                   (_USART_IRCTRL_IRPW_ONE << 1)         /**< Shifted mode ONE for USART_IRCTRL */
+#define USART_IRCTRL_IRPW_TWO                   (_USART_IRCTRL_IRPW_TWO << 1)         /**< Shifted mode TWO for USART_IRCTRL */
+#define USART_IRCTRL_IRPW_THREE                 (_USART_IRCTRL_IRPW_THREE << 1)       /**< Shifted mode THREE for USART_IRCTRL */
+#define USART_IRCTRL_IRPW_FOUR                  (_USART_IRCTRL_IRPW_FOUR << 1)        /**< Shifted mode FOUR for USART_IRCTRL */
+#define USART_IRCTRL_IRFILT                     (0x1UL << 3)                          /**< IrDA RX Filter */
+#define _USART_IRCTRL_IRFILT_SHIFT              3                                     /**< Shift value for USART_IRFILT */
+#define _USART_IRCTRL_IRFILT_MASK               0x8UL                                 /**< Bit mask for USART_IRFILT */
+#define _USART_IRCTRL_IRFILT_DEFAULT            0x00000000UL                          /**< Mode DEFAULT for USART_IRCTRL */
+#define USART_IRCTRL_IRFILT_DEFAULT             (_USART_IRCTRL_IRFILT_DEFAULT << 3)   /**< Shifted mode DEFAULT for USART_IRCTRL */
+#define USART_IRCTRL_IRPRSEN                    (0x1UL << 7)                          /**< IrDA PRS Channel Enable */
+#define _USART_IRCTRL_IRPRSEN_SHIFT             7                                     /**< Shift value for USART_IRPRSEN */
+#define _USART_IRCTRL_IRPRSEN_MASK              0x80UL                                /**< Bit mask for USART_IRPRSEN */
+#define _USART_IRCTRL_IRPRSEN_DEFAULT           0x00000000UL                          /**< Mode DEFAULT for USART_IRCTRL */
+#define USART_IRCTRL_IRPRSEN_DEFAULT            (_USART_IRCTRL_IRPRSEN_DEFAULT << 7)  /**< Shifted mode DEFAULT for USART_IRCTRL */
+#define _USART_IRCTRL_IRPRSSEL_SHIFT            8                                     /**< Shift value for USART_IRPRSSEL */
+#define _USART_IRCTRL_IRPRSSEL_MASK             0xF00UL                               /**< Bit mask for USART_IRPRSSEL */
+#define _USART_IRCTRL_IRPRSSEL_DEFAULT          0x00000000UL                          /**< Mode DEFAULT for USART_IRCTRL */
+#define _USART_IRCTRL_IRPRSSEL_PRSCH0           0x00000000UL                          /**< Mode PRSCH0 for USART_IRCTRL */
+#define _USART_IRCTRL_IRPRSSEL_PRSCH1           0x00000001UL                          /**< Mode PRSCH1 for USART_IRCTRL */
+#define _USART_IRCTRL_IRPRSSEL_PRSCH2           0x00000002UL                          /**< Mode PRSCH2 for USART_IRCTRL */
+#define _USART_IRCTRL_IRPRSSEL_PRSCH3           0x00000003UL                          /**< Mode PRSCH3 for USART_IRCTRL */
+#define _USART_IRCTRL_IRPRSSEL_PRSCH4           0x00000004UL                          /**< Mode PRSCH4 for USART_IRCTRL */
+#define _USART_IRCTRL_IRPRSSEL_PRSCH5           0x00000005UL                          /**< Mode PRSCH5 for USART_IRCTRL */
+#define _USART_IRCTRL_IRPRSSEL_PRSCH6           0x00000006UL                          /**< Mode PRSCH6 for USART_IRCTRL */
+#define _USART_IRCTRL_IRPRSSEL_PRSCH7           0x00000007UL                          /**< Mode PRSCH7 for USART_IRCTRL */
+#define _USART_IRCTRL_IRPRSSEL_PRSCH8           0x00000008UL                          /**< Mode PRSCH8 for USART_IRCTRL */
+#define _USART_IRCTRL_IRPRSSEL_PRSCH9           0x00000009UL                          /**< Mode PRSCH9 for USART_IRCTRL */
+#define _USART_IRCTRL_IRPRSSEL_PRSCH10          0x0000000AUL                          /**< Mode PRSCH10 for USART_IRCTRL */
+#define _USART_IRCTRL_IRPRSSEL_PRSCH11          0x0000000BUL                          /**< Mode PRSCH11 for USART_IRCTRL */
+#define USART_IRCTRL_IRPRSSEL_DEFAULT           (_USART_IRCTRL_IRPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IRCTRL */
+#define USART_IRCTRL_IRPRSSEL_PRSCH0            (_USART_IRCTRL_IRPRSSEL_PRSCH0 << 8)  /**< Shifted mode PRSCH0 for USART_IRCTRL */
+#define USART_IRCTRL_IRPRSSEL_PRSCH1            (_USART_IRCTRL_IRPRSSEL_PRSCH1 << 8)  /**< Shifted mode PRSCH1 for USART_IRCTRL */
+#define USART_IRCTRL_IRPRSSEL_PRSCH2            (_USART_IRCTRL_IRPRSSEL_PRSCH2 << 8)  /**< Shifted mode PRSCH2 for USART_IRCTRL */
+#define USART_IRCTRL_IRPRSSEL_PRSCH3            (_USART_IRCTRL_IRPRSSEL_PRSCH3 << 8)  /**< Shifted mode PRSCH3 for USART_IRCTRL */
+#define USART_IRCTRL_IRPRSSEL_PRSCH4            (_USART_IRCTRL_IRPRSSEL_PRSCH4 << 8)  /**< Shifted mode PRSCH4 for USART_IRCTRL */
+#define USART_IRCTRL_IRPRSSEL_PRSCH5            (_USART_IRCTRL_IRPRSSEL_PRSCH5 << 8)  /**< Shifted mode PRSCH5 for USART_IRCTRL */
+#define USART_IRCTRL_IRPRSSEL_PRSCH6            (_USART_IRCTRL_IRPRSSEL_PRSCH6 << 8)  /**< Shifted mode PRSCH6 for USART_IRCTRL */
+#define USART_IRCTRL_IRPRSSEL_PRSCH7            (_USART_IRCTRL_IRPRSSEL_PRSCH7 << 8)  /**< Shifted mode PRSCH7 for USART_IRCTRL */
+#define USART_IRCTRL_IRPRSSEL_PRSCH8            (_USART_IRCTRL_IRPRSSEL_PRSCH8 << 8)  /**< Shifted mode PRSCH8 for USART_IRCTRL */
+#define USART_IRCTRL_IRPRSSEL_PRSCH9            (_USART_IRCTRL_IRPRSSEL_PRSCH9 << 8)  /**< Shifted mode PRSCH9 for USART_IRCTRL */
+#define USART_IRCTRL_IRPRSSEL_PRSCH10           (_USART_IRCTRL_IRPRSSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for USART_IRCTRL */
+#define USART_IRCTRL_IRPRSSEL_PRSCH11           (_USART_IRCTRL_IRPRSSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for USART_IRCTRL */
+
+/* Bit fields for USART INPUT */
+#define _USART_INPUT_RESETVALUE                 0x00000000UL                          /**< Default value for USART_INPUT */
+#define _USART_INPUT_MASK                       0x00008F8FUL                          /**< Mask for USART_INPUT */
+#define _USART_INPUT_RXPRSSEL_SHIFT             0                                     /**< Shift value for USART_RXPRSSEL */
+#define _USART_INPUT_RXPRSSEL_MASK              0xFUL                                 /**< Bit mask for USART_RXPRSSEL */
+#define _USART_INPUT_RXPRSSEL_DEFAULT           0x00000000UL                          /**< Mode DEFAULT for USART_INPUT */
+#define _USART_INPUT_RXPRSSEL_PRSCH0            0x00000000UL                          /**< Mode PRSCH0 for USART_INPUT */
+#define _USART_INPUT_RXPRSSEL_PRSCH1            0x00000001UL                          /**< Mode PRSCH1 for USART_INPUT */
+#define _USART_INPUT_RXPRSSEL_PRSCH2            0x00000002UL                          /**< Mode PRSCH2 for USART_INPUT */
+#define _USART_INPUT_RXPRSSEL_PRSCH3            0x00000003UL                          /**< Mode PRSCH3 for USART_INPUT */
+#define _USART_INPUT_RXPRSSEL_PRSCH4            0x00000004UL                          /**< Mode PRSCH4 for USART_INPUT */
+#define _USART_INPUT_RXPRSSEL_PRSCH5            0x00000005UL                          /**< Mode PRSCH5 for USART_INPUT */
+#define _USART_INPUT_RXPRSSEL_PRSCH6            0x00000006UL                          /**< Mode PRSCH6 for USART_INPUT */
+#define _USART_INPUT_RXPRSSEL_PRSCH7            0x00000007UL                          /**< Mode PRSCH7 for USART_INPUT */
+#define _USART_INPUT_RXPRSSEL_PRSCH8            0x00000008UL                          /**< Mode PRSCH8 for USART_INPUT */
+#define _USART_INPUT_RXPRSSEL_PRSCH9            0x00000009UL                          /**< Mode PRSCH9 for USART_INPUT */
+#define _USART_INPUT_RXPRSSEL_PRSCH10           0x0000000AUL                          /**< Mode PRSCH10 for USART_INPUT */
+#define _USART_INPUT_RXPRSSEL_PRSCH11           0x0000000BUL                          /**< Mode PRSCH11 for USART_INPUT */
+#define USART_INPUT_RXPRSSEL_DEFAULT            (_USART_INPUT_RXPRSSEL_DEFAULT << 0)  /**< Shifted mode DEFAULT for USART_INPUT */
+#define USART_INPUT_RXPRSSEL_PRSCH0             (_USART_INPUT_RXPRSSEL_PRSCH0 << 0)   /**< Shifted mode PRSCH0 for USART_INPUT */
+#define USART_INPUT_RXPRSSEL_PRSCH1             (_USART_INPUT_RXPRSSEL_PRSCH1 << 0)   /**< Shifted mode PRSCH1 for USART_INPUT */
+#define USART_INPUT_RXPRSSEL_PRSCH2             (_USART_INPUT_RXPRSSEL_PRSCH2 << 0)   /**< Shifted mode PRSCH2 for USART_INPUT */
+#define USART_INPUT_RXPRSSEL_PRSCH3             (_USART_INPUT_RXPRSSEL_PRSCH3 << 0)   /**< Shifted mode PRSCH3 for USART_INPUT */
+#define USART_INPUT_RXPRSSEL_PRSCH4             (_USART_INPUT_RXPRSSEL_PRSCH4 << 0)   /**< Shifted mode PRSCH4 for USART_INPUT */
+#define USART_INPUT_RXPRSSEL_PRSCH5             (_USART_INPUT_RXPRSSEL_PRSCH5 << 0)   /**< Shifted mode PRSCH5 for USART_INPUT */
+#define USART_INPUT_RXPRSSEL_PRSCH6             (_USART_INPUT_RXPRSSEL_PRSCH6 << 0)   /**< Shifted mode PRSCH6 for USART_INPUT */
+#define USART_INPUT_RXPRSSEL_PRSCH7             (_USART_INPUT_RXPRSSEL_PRSCH7 << 0)   /**< Shifted mode PRSCH7 for USART_INPUT */
+#define USART_INPUT_RXPRSSEL_PRSCH8             (_USART_INPUT_RXPRSSEL_PRSCH8 << 0)   /**< Shifted mode PRSCH8 for USART_INPUT */
+#define USART_INPUT_RXPRSSEL_PRSCH9             (_USART_INPUT_RXPRSSEL_PRSCH9 << 0)   /**< Shifted mode PRSCH9 for USART_INPUT */
+#define USART_INPUT_RXPRSSEL_PRSCH10            (_USART_INPUT_RXPRSSEL_PRSCH10 << 0)  /**< Shifted mode PRSCH10 for USART_INPUT */
+#define USART_INPUT_RXPRSSEL_PRSCH11            (_USART_INPUT_RXPRSSEL_PRSCH11 << 0)  /**< Shifted mode PRSCH11 for USART_INPUT */
+#define USART_INPUT_RXPRS                       (0x1UL << 7)                          /**< PRS RX Enable */
+#define _USART_INPUT_RXPRS_SHIFT                7                                     /**< Shift value for USART_RXPRS */
+#define _USART_INPUT_RXPRS_MASK                 0x80UL                                /**< Bit mask for USART_RXPRS */
+#define _USART_INPUT_RXPRS_DEFAULT              0x00000000UL                          /**< Mode DEFAULT for USART_INPUT */
+#define USART_INPUT_RXPRS_DEFAULT               (_USART_INPUT_RXPRS_DEFAULT << 7)     /**< Shifted mode DEFAULT for USART_INPUT */
+#define _USART_INPUT_CLKPRSSEL_SHIFT            8                                     /**< Shift value for USART_CLKPRSSEL */
+#define _USART_INPUT_CLKPRSSEL_MASK             0xF00UL                               /**< Bit mask for USART_CLKPRSSEL */
+#define _USART_INPUT_CLKPRSSEL_DEFAULT          0x00000000UL                          /**< Mode DEFAULT for USART_INPUT */
+#define _USART_INPUT_CLKPRSSEL_PRSCH0           0x00000000UL                          /**< Mode PRSCH0 for USART_INPUT */
+#define _USART_INPUT_CLKPRSSEL_PRSCH1           0x00000001UL                          /**< Mode PRSCH1 for USART_INPUT */
+#define _USART_INPUT_CLKPRSSEL_PRSCH2           0x00000002UL                          /**< Mode PRSCH2 for USART_INPUT */
+#define _USART_INPUT_CLKPRSSEL_PRSCH3           0x00000003UL                          /**< Mode PRSCH3 for USART_INPUT */
+#define _USART_INPUT_CLKPRSSEL_PRSCH4           0x00000004UL                          /**< Mode PRSCH4 for USART_INPUT */
+#define _USART_INPUT_CLKPRSSEL_PRSCH5           0x00000005UL                          /**< Mode PRSCH5 for USART_INPUT */
+#define _USART_INPUT_CLKPRSSEL_PRSCH6           0x00000006UL                          /**< Mode PRSCH6 for USART_INPUT */
+#define _USART_INPUT_CLKPRSSEL_PRSCH7           0x00000007UL                          /**< Mode PRSCH7 for USART_INPUT */
+#define _USART_INPUT_CLKPRSSEL_PRSCH8           0x00000008UL                          /**< Mode PRSCH8 for USART_INPUT */
+#define _USART_INPUT_CLKPRSSEL_PRSCH9           0x00000009UL                          /**< Mode PRSCH9 for USART_INPUT */
+#define _USART_INPUT_CLKPRSSEL_PRSCH10          0x0000000AUL                          /**< Mode PRSCH10 for USART_INPUT */
+#define _USART_INPUT_CLKPRSSEL_PRSCH11          0x0000000BUL                          /**< Mode PRSCH11 for USART_INPUT */
+#define USART_INPUT_CLKPRSSEL_DEFAULT           (_USART_INPUT_CLKPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_INPUT */
+#define USART_INPUT_CLKPRSSEL_PRSCH0            (_USART_INPUT_CLKPRSSEL_PRSCH0 << 8)  /**< Shifted mode PRSCH0 for USART_INPUT */
+#define USART_INPUT_CLKPRSSEL_PRSCH1            (_USART_INPUT_CLKPRSSEL_PRSCH1 << 8)  /**< Shifted mode PRSCH1 for USART_INPUT */
+#define USART_INPUT_CLKPRSSEL_PRSCH2            (_USART_INPUT_CLKPRSSEL_PRSCH2 << 8)  /**< Shifted mode PRSCH2 for USART_INPUT */
+#define USART_INPUT_CLKPRSSEL_PRSCH3            (_USART_INPUT_CLKPRSSEL_PRSCH3 << 8)  /**< Shifted mode PRSCH3 for USART_INPUT */
+#define USART_INPUT_CLKPRSSEL_PRSCH4            (_USART_INPUT_CLKPRSSEL_PRSCH4 << 8)  /**< Shifted mode PRSCH4 for USART_INPUT */
+#define USART_INPUT_CLKPRSSEL_PRSCH5            (_USART_INPUT_CLKPRSSEL_PRSCH5 << 8)  /**< Shifted mode PRSCH5 for USART_INPUT */
+#define USART_INPUT_CLKPRSSEL_PRSCH6            (_USART_INPUT_CLKPRSSEL_PRSCH6 << 8)  /**< Shifted mode PRSCH6 for USART_INPUT */
+#define USART_INPUT_CLKPRSSEL_PRSCH7            (_USART_INPUT_CLKPRSSEL_PRSCH7 << 8)  /**< Shifted mode PRSCH7 for USART_INPUT */
+#define USART_INPUT_CLKPRSSEL_PRSCH8            (_USART_INPUT_CLKPRSSEL_PRSCH8 << 8)  /**< Shifted mode PRSCH8 for USART_INPUT */
+#define USART_INPUT_CLKPRSSEL_PRSCH9            (_USART_INPUT_CLKPRSSEL_PRSCH9 << 8)  /**< Shifted mode PRSCH9 for USART_INPUT */
+#define USART_INPUT_CLKPRSSEL_PRSCH10           (_USART_INPUT_CLKPRSSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for USART_INPUT */
+#define USART_INPUT_CLKPRSSEL_PRSCH11           (_USART_INPUT_CLKPRSSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for USART_INPUT */
+#define USART_INPUT_CLKPRS                      (0x1UL << 15)                         /**< PRS CLK Enable */
+#define _USART_INPUT_CLKPRS_SHIFT               15                                    /**< Shift value for USART_CLKPRS */
+#define _USART_INPUT_CLKPRS_MASK                0x8000UL                              /**< Bit mask for USART_CLKPRS */
+#define _USART_INPUT_CLKPRS_DEFAULT             0x00000000UL                          /**< Mode DEFAULT for USART_INPUT */
+#define USART_INPUT_CLKPRS_DEFAULT              (_USART_INPUT_CLKPRS_DEFAULT << 15)   /**< Shifted mode DEFAULT for USART_INPUT */
+
+/* Bit fields for USART I2SCTRL */
+#define _USART_I2SCTRL_RESETVALUE               0x00000000UL                           /**< Default value for USART_I2SCTRL */
+#define _USART_I2SCTRL_MASK                     0x0000071FUL                           /**< Mask for USART_I2SCTRL */
+#define USART_I2SCTRL_EN                        (0x1UL << 0)                           /**< Enable I2S Mode */
+#define _USART_I2SCTRL_EN_SHIFT                 0                                      /**< Shift value for USART_EN */
+#define _USART_I2SCTRL_EN_MASK                  0x1UL                                  /**< Bit mask for USART_EN */
+#define _USART_I2SCTRL_EN_DEFAULT               0x00000000UL                           /**< Mode DEFAULT for USART_I2SCTRL */
+#define USART_I2SCTRL_EN_DEFAULT                (_USART_I2SCTRL_EN_DEFAULT << 0)       /**< Shifted mode DEFAULT for USART_I2SCTRL */
+#define USART_I2SCTRL_MONO                      (0x1UL << 1)                           /**< Stero or Mono */
+#define _USART_I2SCTRL_MONO_SHIFT               1                                      /**< Shift value for USART_MONO */
+#define _USART_I2SCTRL_MONO_MASK                0x2UL                                  /**< Bit mask for USART_MONO */
+#define _USART_I2SCTRL_MONO_DEFAULT             0x00000000UL                           /**< Mode DEFAULT for USART_I2SCTRL */
+#define USART_I2SCTRL_MONO_DEFAULT              (_USART_I2SCTRL_MONO_DEFAULT << 1)     /**< Shifted mode DEFAULT for USART_I2SCTRL */
+#define USART_I2SCTRL_JUSTIFY                   (0x1UL << 2)                           /**< Justification of I2S Data */
+#define _USART_I2SCTRL_JUSTIFY_SHIFT            2                                      /**< Shift value for USART_JUSTIFY */
+#define _USART_I2SCTRL_JUSTIFY_MASK             0x4UL                                  /**< Bit mask for USART_JUSTIFY */
+#define _USART_I2SCTRL_JUSTIFY_DEFAULT          0x00000000UL                           /**< Mode DEFAULT for USART_I2SCTRL */
+#define _USART_I2SCTRL_JUSTIFY_LEFT             0x00000000UL                           /**< Mode LEFT for USART_I2SCTRL */
+#define _USART_I2SCTRL_JUSTIFY_RIGHT            0x00000001UL                           /**< Mode RIGHT for USART_I2SCTRL */
+#define USART_I2SCTRL_JUSTIFY_DEFAULT           (_USART_I2SCTRL_JUSTIFY_DEFAULT << 2)  /**< Shifted mode DEFAULT for USART_I2SCTRL */
+#define USART_I2SCTRL_JUSTIFY_LEFT              (_USART_I2SCTRL_JUSTIFY_LEFT << 2)     /**< Shifted mode LEFT for USART_I2SCTRL */
+#define USART_I2SCTRL_JUSTIFY_RIGHT             (_USART_I2SCTRL_JUSTIFY_RIGHT << 2)    /**< Shifted mode RIGHT for USART_I2SCTRL */
+#define USART_I2SCTRL_DMASPLIT                  (0x1UL << 3)                           /**< Separate DMA Request For Left/Right Data */
+#define _USART_I2SCTRL_DMASPLIT_SHIFT           3                                      /**< Shift value for USART_DMASPLIT */
+#define _USART_I2SCTRL_DMASPLIT_MASK            0x8UL                                  /**< Bit mask for USART_DMASPLIT */
+#define _USART_I2SCTRL_DMASPLIT_DEFAULT         0x00000000UL                           /**< Mode DEFAULT for USART_I2SCTRL */
+#define USART_I2SCTRL_DMASPLIT_DEFAULT          (_USART_I2SCTRL_DMASPLIT_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_I2SCTRL */
+#define USART_I2SCTRL_DELAY                     (0x1UL << 4)                           /**< Delay on I2S data */
+#define _USART_I2SCTRL_DELAY_SHIFT              4                                      /**< Shift value for USART_DELAY */
+#define _USART_I2SCTRL_DELAY_MASK               0x10UL                                 /**< Bit mask for USART_DELAY */
+#define _USART_I2SCTRL_DELAY_DEFAULT            0x00000000UL                           /**< Mode DEFAULT for USART_I2SCTRL */
+#define USART_I2SCTRL_DELAY_DEFAULT             (_USART_I2SCTRL_DELAY_DEFAULT << 4)    /**< Shifted mode DEFAULT for USART_I2SCTRL */
+#define _USART_I2SCTRL_FORMAT_SHIFT             8                                      /**< Shift value for USART_FORMAT */
+#define _USART_I2SCTRL_FORMAT_MASK              0x700UL                                /**< Bit mask for USART_FORMAT */
+#define _USART_I2SCTRL_FORMAT_DEFAULT           0x00000000UL                           /**< Mode DEFAULT for USART_I2SCTRL */
+#define _USART_I2SCTRL_FORMAT_W32D32            0x00000000UL                           /**< Mode W32D32 for USART_I2SCTRL */
+#define _USART_I2SCTRL_FORMAT_W32D24M           0x00000001UL                           /**< Mode W32D24M for USART_I2SCTRL */
+#define _USART_I2SCTRL_FORMAT_W32D24            0x00000002UL                           /**< Mode W32D24 for USART_I2SCTRL */
+#define _USART_I2SCTRL_FORMAT_W32D16            0x00000003UL                           /**< Mode W32D16 for USART_I2SCTRL */
+#define _USART_I2SCTRL_FORMAT_W32D8             0x00000004UL                           /**< Mode W32D8 for USART_I2SCTRL */
+#define _USART_I2SCTRL_FORMAT_W16D16            0x00000005UL                           /**< Mode W16D16 for USART_I2SCTRL */
+#define _USART_I2SCTRL_FORMAT_W16D8             0x00000006UL                           /**< Mode W16D8 for USART_I2SCTRL */
+#define _USART_I2SCTRL_FORMAT_W8D8              0x00000007UL                           /**< Mode W8D8 for USART_I2SCTRL */
+#define USART_I2SCTRL_FORMAT_DEFAULT            (_USART_I2SCTRL_FORMAT_DEFAULT << 8)   /**< Shifted mode DEFAULT for USART_I2SCTRL */
+#define USART_I2SCTRL_FORMAT_W32D32             (_USART_I2SCTRL_FORMAT_W32D32 << 8)    /**< Shifted mode W32D32 for USART_I2SCTRL */
+#define USART_I2SCTRL_FORMAT_W32D24M            (_USART_I2SCTRL_FORMAT_W32D24M << 8)   /**< Shifted mode W32D24M for USART_I2SCTRL */
+#define USART_I2SCTRL_FORMAT_W32D24             (_USART_I2SCTRL_FORMAT_W32D24 << 8)    /**< Shifted mode W32D24 for USART_I2SCTRL */
+#define USART_I2SCTRL_FORMAT_W32D16             (_USART_I2SCTRL_FORMAT_W32D16 << 8)    /**< Shifted mode W32D16 for USART_I2SCTRL */
+#define USART_I2SCTRL_FORMAT_W32D8              (_USART_I2SCTRL_FORMAT_W32D8 << 8)     /**< Shifted mode W32D8 for USART_I2SCTRL */
+#define USART_I2SCTRL_FORMAT_W16D16             (_USART_I2SCTRL_FORMAT_W16D16 << 8)    /**< Shifted mode W16D16 for USART_I2SCTRL */
+#define USART_I2SCTRL_FORMAT_W16D8              (_USART_I2SCTRL_FORMAT_W16D8 << 8)     /**< Shifted mode W16D8 for USART_I2SCTRL */
+#define USART_I2SCTRL_FORMAT_W8D8               (_USART_I2SCTRL_FORMAT_W8D8 << 8)      /**< Shifted mode W8D8 for USART_I2SCTRL */
+
+/* Bit fields for USART TIMING */
+#define _USART_TIMING_RESETVALUE                0x00000000UL                          /**< Default value for USART_TIMING */
+#define _USART_TIMING_MASK                      0x77770000UL                          /**< Mask for USART_TIMING */
+#define _USART_TIMING_TXDELAY_SHIFT             16                                    /**< Shift value for USART_TXDELAY */
+#define _USART_TIMING_TXDELAY_MASK              0x70000UL                             /**< Bit mask for USART_TXDELAY */
+#define _USART_TIMING_TXDELAY_DEFAULT           0x00000000UL                          /**< Mode DEFAULT for USART_TIMING */
+#define _USART_TIMING_TXDELAY_DISABLE           0x00000000UL                          /**< Mode DISABLE for USART_TIMING */
+#define _USART_TIMING_TXDELAY_ONE               0x00000001UL                          /**< Mode ONE for USART_TIMING */
+#define _USART_TIMING_TXDELAY_TWO               0x00000002UL                          /**< Mode TWO for USART_TIMING */
+#define _USART_TIMING_TXDELAY_THREE             0x00000003UL                          /**< Mode THREE for USART_TIMING */
+#define _USART_TIMING_TXDELAY_SEVEN             0x00000004UL                          /**< Mode SEVEN for USART_TIMING */
+#define _USART_TIMING_TXDELAY_TCMP0             0x00000005UL                          /**< Mode TCMP0 for USART_TIMING */
+#define _USART_TIMING_TXDELAY_TCMP1             0x00000006UL                          /**< Mode TCMP1 for USART_TIMING */
+#define _USART_TIMING_TXDELAY_TCMP2             0x00000007UL                          /**< Mode TCMP2 for USART_TIMING */
+#define USART_TIMING_TXDELAY_DEFAULT            (_USART_TIMING_TXDELAY_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMING */
+#define USART_TIMING_TXDELAY_DISABLE            (_USART_TIMING_TXDELAY_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMING */
+#define USART_TIMING_TXDELAY_ONE                (_USART_TIMING_TXDELAY_ONE << 16)     /**< Shifted mode ONE for USART_TIMING */
+#define USART_TIMING_TXDELAY_TWO                (_USART_TIMING_TXDELAY_TWO << 16)     /**< Shifted mode TWO for USART_TIMING */
+#define USART_TIMING_TXDELAY_THREE              (_USART_TIMING_TXDELAY_THREE << 16)   /**< Shifted mode THREE for USART_TIMING */
+#define USART_TIMING_TXDELAY_SEVEN              (_USART_TIMING_TXDELAY_SEVEN << 16)   /**< Shifted mode SEVEN for USART_TIMING */
+#define USART_TIMING_TXDELAY_TCMP0              (_USART_TIMING_TXDELAY_TCMP0 << 16)   /**< Shifted mode TCMP0 for USART_TIMING */
+#define USART_TIMING_TXDELAY_TCMP1              (_USART_TIMING_TXDELAY_TCMP1 << 16)   /**< Shifted mode TCMP1 for USART_TIMING */
+#define USART_TIMING_TXDELAY_TCMP2              (_USART_TIMING_TXDELAY_TCMP2 << 16)   /**< Shifted mode TCMP2 for USART_TIMING */
+#define _USART_TIMING_CSSETUP_SHIFT             20                                    /**< Shift value for USART_CSSETUP */
+#define _USART_TIMING_CSSETUP_MASK              0x700000UL                            /**< Bit mask for USART_CSSETUP */
+#define _USART_TIMING_CSSETUP_DEFAULT           0x00000000UL                          /**< Mode DEFAULT for USART_TIMING */
+#define _USART_TIMING_CSSETUP_ZERO              0x00000000UL                          /**< Mode ZERO for USART_TIMING */
+#define _USART_TIMING_CSSETUP_ONE               0x00000001UL                          /**< Mode ONE for USART_TIMING */
+#define _USART_TIMING_CSSETUP_TWO               0x00000002UL                          /**< Mode TWO for USART_TIMING */
+#define _USART_TIMING_CSSETUP_THREE             0x00000003UL                          /**< Mode THREE for USART_TIMING */
+#define _USART_TIMING_CSSETUP_SEVEN             0x00000004UL                          /**< Mode SEVEN for USART_TIMING */
+#define _USART_TIMING_CSSETUP_TCMP0             0x00000005UL                          /**< Mode TCMP0 for USART_TIMING */
+#define _USART_TIMING_CSSETUP_TCMP1             0x00000006UL                          /**< Mode TCMP1 for USART_TIMING */
+#define _USART_TIMING_CSSETUP_TCMP2             0x00000007UL                          /**< Mode TCMP2 for USART_TIMING */
+#define USART_TIMING_CSSETUP_DEFAULT            (_USART_TIMING_CSSETUP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMING */
+#define USART_TIMING_CSSETUP_ZERO               (_USART_TIMING_CSSETUP_ZERO << 20)    /**< Shifted mode ZERO for USART_TIMING */
+#define USART_TIMING_CSSETUP_ONE                (_USART_TIMING_CSSETUP_ONE << 20)     /**< Shifted mode ONE for USART_TIMING */
+#define USART_TIMING_CSSETUP_TWO                (_USART_TIMING_CSSETUP_TWO << 20)     /**< Shifted mode TWO for USART_TIMING */
+#define USART_TIMING_CSSETUP_THREE              (_USART_TIMING_CSSETUP_THREE << 20)   /**< Shifted mode THREE for USART_TIMING */
+#define USART_TIMING_CSSETUP_SEVEN              (_USART_TIMING_CSSETUP_SEVEN << 20)   /**< Shifted mode SEVEN for USART_TIMING */
+#define USART_TIMING_CSSETUP_TCMP0              (_USART_TIMING_CSSETUP_TCMP0 << 20)   /**< Shifted mode TCMP0 for USART_TIMING */
+#define USART_TIMING_CSSETUP_TCMP1              (_USART_TIMING_CSSETUP_TCMP1 << 20)   /**< Shifted mode TCMP1 for USART_TIMING */
+#define USART_TIMING_CSSETUP_TCMP2              (_USART_TIMING_CSSETUP_TCMP2 << 20)   /**< Shifted mode TCMP2 for USART_TIMING */
+#define _USART_TIMING_ICS_SHIFT                 24                                    /**< Shift value for USART_ICS */
+#define _USART_TIMING_ICS_MASK                  0x7000000UL                           /**< Bit mask for USART_ICS */
+#define _USART_TIMING_ICS_DEFAULT               0x00000000UL                          /**< Mode DEFAULT for USART_TIMING */
+#define _USART_TIMING_ICS_ZERO                  0x00000000UL                          /**< Mode ZERO for USART_TIMING */
+#define _USART_TIMING_ICS_ONE                   0x00000001UL                          /**< Mode ONE for USART_TIMING */
+#define _USART_TIMING_ICS_TWO                   0x00000002UL                          /**< Mode TWO for USART_TIMING */
+#define _USART_TIMING_ICS_THREE                 0x00000003UL                          /**< Mode THREE for USART_TIMING */
+#define _USART_TIMING_ICS_SEVEN                 0x00000004UL                          /**< Mode SEVEN for USART_TIMING */
+#define _USART_TIMING_ICS_TCMP0                 0x00000005UL                          /**< Mode TCMP0 for USART_TIMING */
+#define _USART_TIMING_ICS_TCMP1                 0x00000006UL                          /**< Mode TCMP1 for USART_TIMING */
+#define _USART_TIMING_ICS_TCMP2                 0x00000007UL                          /**< Mode TCMP2 for USART_TIMING */
+#define USART_TIMING_ICS_DEFAULT                (_USART_TIMING_ICS_DEFAULT << 24)     /**< Shifted mode DEFAULT for USART_TIMING */
+#define USART_TIMING_ICS_ZERO                   (_USART_TIMING_ICS_ZERO << 24)        /**< Shifted mode ZERO for USART_TIMING */
+#define USART_TIMING_ICS_ONE                    (_USART_TIMING_ICS_ONE << 24)         /**< Shifted mode ONE for USART_TIMING */
+#define USART_TIMING_ICS_TWO                    (_USART_TIMING_ICS_TWO << 24)         /**< Shifted mode TWO for USART_TIMING */
+#define USART_TIMING_ICS_THREE                  (_USART_TIMING_ICS_THREE << 24)       /**< Shifted mode THREE for USART_TIMING */
+#define USART_TIMING_ICS_SEVEN                  (_USART_TIMING_ICS_SEVEN << 24)       /**< Shifted mode SEVEN for USART_TIMING */
+#define USART_TIMING_ICS_TCMP0                  (_USART_TIMING_ICS_TCMP0 << 24)       /**< Shifted mode TCMP0 for USART_TIMING */
+#define USART_TIMING_ICS_TCMP1                  (_USART_TIMING_ICS_TCMP1 << 24)       /**< Shifted mode TCMP1 for USART_TIMING */
+#define USART_TIMING_ICS_TCMP2                  (_USART_TIMING_ICS_TCMP2 << 24)       /**< Shifted mode TCMP2 for USART_TIMING */
+#define _USART_TIMING_CSHOLD_SHIFT              28                                    /**< Shift value for USART_CSHOLD */
+#define _USART_TIMING_CSHOLD_MASK               0x70000000UL                          /**< Bit mask for USART_CSHOLD */
+#define _USART_TIMING_CSHOLD_DEFAULT            0x00000000UL                          /**< Mode DEFAULT for USART_TIMING */
+#define _USART_TIMING_CSHOLD_ZERO               0x00000000UL                          /**< Mode ZERO for USART_TIMING */
+#define _USART_TIMING_CSHOLD_ONE                0x00000001UL                          /**< Mode ONE for USART_TIMING */
+#define _USART_TIMING_CSHOLD_TWO                0x00000002UL                          /**< Mode TWO for USART_TIMING */
+#define _USART_TIMING_CSHOLD_THREE              0x00000003UL                          /**< Mode THREE for USART_TIMING */
+#define _USART_TIMING_CSHOLD_SEVEN              0x00000004UL                          /**< Mode SEVEN for USART_TIMING */
+#define _USART_TIMING_CSHOLD_TCMP0              0x00000005UL                          /**< Mode TCMP0 for USART_TIMING */
+#define _USART_TIMING_CSHOLD_TCMP1              0x00000006UL                          /**< Mode TCMP1 for USART_TIMING */
+#define _USART_TIMING_CSHOLD_TCMP2              0x00000007UL                          /**< Mode TCMP2 for USART_TIMING */
+#define USART_TIMING_CSHOLD_DEFAULT             (_USART_TIMING_CSHOLD_DEFAULT << 28)  /**< Shifted mode DEFAULT for USART_TIMING */
+#define USART_TIMING_CSHOLD_ZERO                (_USART_TIMING_CSHOLD_ZERO << 28)     /**< Shifted mode ZERO for USART_TIMING */
+#define USART_TIMING_CSHOLD_ONE                 (_USART_TIMING_CSHOLD_ONE << 28)      /**< Shifted mode ONE for USART_TIMING */
+#define USART_TIMING_CSHOLD_TWO                 (_USART_TIMING_CSHOLD_TWO << 28)      /**< Shifted mode TWO for USART_TIMING */
+#define USART_TIMING_CSHOLD_THREE               (_USART_TIMING_CSHOLD_THREE << 28)    /**< Shifted mode THREE for USART_TIMING */
+#define USART_TIMING_CSHOLD_SEVEN               (_USART_TIMING_CSHOLD_SEVEN << 28)    /**< Shifted mode SEVEN for USART_TIMING */
+#define USART_TIMING_CSHOLD_TCMP0               (_USART_TIMING_CSHOLD_TCMP0 << 28)    /**< Shifted mode TCMP0 for USART_TIMING */
+#define USART_TIMING_CSHOLD_TCMP1               (_USART_TIMING_CSHOLD_TCMP1 << 28)    /**< Shifted mode TCMP1 for USART_TIMING */
+#define USART_TIMING_CSHOLD_TCMP2               (_USART_TIMING_CSHOLD_TCMP2 << 28)    /**< Shifted mode TCMP2 for USART_TIMING */
+
+/* Bit fields for USART CTRLX */
+#define _USART_CTRLX_RESETVALUE                 0x00000000UL                        /**< Default value for USART_CTRLX */
+#define _USART_CTRLX_MASK                       0x0000000FUL                        /**< Mask for USART_CTRLX */
+#define USART_CTRLX_DBGHALT                     (0x1UL << 0)                        /**< Debug halt */
+#define _USART_CTRLX_DBGHALT_SHIFT              0                                   /**< Shift value for USART_DBGHALT */
+#define _USART_CTRLX_DBGHALT_MASK               0x1UL                               /**< Bit mask for USART_DBGHALT */
+#define _USART_CTRLX_DBGHALT_DEFAULT            0x00000000UL                        /**< Mode DEFAULT for USART_CTRLX */
+#define USART_CTRLX_DBGHALT_DEFAULT             (_USART_CTRLX_DBGHALT_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CTRLX */
+#define USART_CTRLX_CTSINV                      (0x1UL << 1)                        /**< CTS Pin Inversion */
+#define _USART_CTRLX_CTSINV_SHIFT               1                                   /**< Shift value for USART_CTSINV */
+#define _USART_CTRLX_CTSINV_MASK                0x2UL                               /**< Bit mask for USART_CTSINV */
+#define _USART_CTRLX_CTSINV_DEFAULT             0x00000000UL                        /**< Mode DEFAULT for USART_CTRLX */
+#define USART_CTRLX_CTSINV_DEFAULT              (_USART_CTRLX_CTSINV_DEFAULT << 1)  /**< Shifted mode DEFAULT for USART_CTRLX */
+#define USART_CTRLX_CTSEN                       (0x1UL << 2)                        /**< CTS Function enabled */
+#define _USART_CTRLX_CTSEN_SHIFT                2                                   /**< Shift value for USART_CTSEN */
+#define _USART_CTRLX_CTSEN_MASK                 0x4UL                               /**< Bit mask for USART_CTSEN */
+#define _USART_CTRLX_CTSEN_DEFAULT              0x00000000UL                        /**< Mode DEFAULT for USART_CTRLX */
+#define USART_CTRLX_CTSEN_DEFAULT               (_USART_CTRLX_CTSEN_DEFAULT << 2)   /**< Shifted mode DEFAULT for USART_CTRLX */
+#define USART_CTRLX_RTSINV                      (0x1UL << 3)                        /**< RTS Pin Inversion */
+#define _USART_CTRLX_RTSINV_SHIFT               3                                   /**< Shift value for USART_RTSINV */
+#define _USART_CTRLX_RTSINV_MASK                0x8UL                               /**< Bit mask for USART_RTSINV */
+#define _USART_CTRLX_RTSINV_DEFAULT             0x00000000UL                        /**< Mode DEFAULT for USART_CTRLX */
+#define USART_CTRLX_RTSINV_DEFAULT              (_USART_CTRLX_RTSINV_DEFAULT << 3)  /**< Shifted mode DEFAULT for USART_CTRLX */
+
+/* Bit fields for USART TIMECMP0 */
+#define _USART_TIMECMP0_RESETVALUE              0x00000000UL                              /**< Default value for USART_TIMECMP0 */
+#define _USART_TIMECMP0_MASK                    0x017700FFUL                              /**< Mask for USART_TIMECMP0 */
+#define _USART_TIMECMP0_TCMPVAL_SHIFT           0                                         /**< Shift value for USART_TCMPVAL */
+#define _USART_TIMECMP0_TCMPVAL_MASK            0xFFUL                                    /**< Bit mask for USART_TCMPVAL */
+#define _USART_TIMECMP0_TCMPVAL_DEFAULT         0x00000000UL                              /**< Mode DEFAULT for USART_TIMECMP0 */
+#define USART_TIMECMP0_TCMPVAL_DEFAULT          (_USART_TIMECMP0_TCMPVAL_DEFAULT << 0)    /**< Shifted mode DEFAULT for USART_TIMECMP0 */
+#define _USART_TIMECMP0_TSTART_SHIFT            16                                        /**< Shift value for USART_TSTART */
+#define _USART_TIMECMP0_TSTART_MASK             0x70000UL                                 /**< Bit mask for USART_TSTART */
+#define _USART_TIMECMP0_TSTART_DEFAULT          0x00000000UL                              /**< Mode DEFAULT for USART_TIMECMP0 */
+#define _USART_TIMECMP0_TSTART_DISABLE          0x00000000UL                              /**< Mode DISABLE for USART_TIMECMP0 */
+#define _USART_TIMECMP0_TSTART_TXEOF            0x00000001UL                              /**< Mode TXEOF for USART_TIMECMP0 */
+#define _USART_TIMECMP0_TSTART_TXC              0x00000002UL                              /**< Mode TXC for USART_TIMECMP0 */
+#define _USART_TIMECMP0_TSTART_RXACT            0x00000003UL                              /**< Mode RXACT for USART_TIMECMP0 */
+#define _USART_TIMECMP0_TSTART_RXEOF            0x00000004UL                              /**< Mode RXEOF for USART_TIMECMP0 */
+#define USART_TIMECMP0_TSTART_DEFAULT           (_USART_TIMECMP0_TSTART_DEFAULT << 16)    /**< Shifted mode DEFAULT for USART_TIMECMP0 */
+#define USART_TIMECMP0_TSTART_DISABLE           (_USART_TIMECMP0_TSTART_DISABLE << 16)    /**< Shifted mode DISABLE for USART_TIMECMP0 */
+#define USART_TIMECMP0_TSTART_TXEOF             (_USART_TIMECMP0_TSTART_TXEOF << 16)      /**< Shifted mode TXEOF for USART_TIMECMP0 */
+#define USART_TIMECMP0_TSTART_TXC               (_USART_TIMECMP0_TSTART_TXC << 16)        /**< Shifted mode TXC for USART_TIMECMP0 */
+#define USART_TIMECMP0_TSTART_RXACT             (_USART_TIMECMP0_TSTART_RXACT << 16)      /**< Shifted mode RXACT for USART_TIMECMP0 */
+#define USART_TIMECMP0_TSTART_RXEOF             (_USART_TIMECMP0_TSTART_RXEOF << 16)      /**< Shifted mode RXEOF for USART_TIMECMP0 */
+#define _USART_TIMECMP0_TSTOP_SHIFT             20                                        /**< Shift value for USART_TSTOP */
+#define _USART_TIMECMP0_TSTOP_MASK              0x700000UL                                /**< Bit mask for USART_TSTOP */
+#define _USART_TIMECMP0_TSTOP_DEFAULT           0x00000000UL                              /**< Mode DEFAULT for USART_TIMECMP0 */
+#define _USART_TIMECMP0_TSTOP_TCMP0             0x00000000UL                              /**< Mode TCMP0 for USART_TIMECMP0 */
+#define _USART_TIMECMP0_TSTOP_TXST              0x00000001UL                              /**< Mode TXST for USART_TIMECMP0 */
+#define _USART_TIMECMP0_TSTOP_RXACT             0x00000002UL                              /**< Mode RXACT for USART_TIMECMP0 */
+#define _USART_TIMECMP0_TSTOP_RXACTN            0x00000003UL                              /**< Mode RXACTN for USART_TIMECMP0 */
+#define USART_TIMECMP0_TSTOP_DEFAULT            (_USART_TIMECMP0_TSTOP_DEFAULT << 20)     /**< Shifted mode DEFAULT for USART_TIMECMP0 */
+#define USART_TIMECMP0_TSTOP_TCMP0              (_USART_TIMECMP0_TSTOP_TCMP0 << 20)       /**< Shifted mode TCMP0 for USART_TIMECMP0 */
+#define USART_TIMECMP0_TSTOP_TXST               (_USART_TIMECMP0_TSTOP_TXST << 20)        /**< Shifted mode TXST for USART_TIMECMP0 */
+#define USART_TIMECMP0_TSTOP_RXACT              (_USART_TIMECMP0_TSTOP_RXACT << 20)       /**< Shifted mode RXACT for USART_TIMECMP0 */
+#define USART_TIMECMP0_TSTOP_RXACTN             (_USART_TIMECMP0_TSTOP_RXACTN << 20)      /**< Shifted mode RXACTN for USART_TIMECMP0 */
+#define USART_TIMECMP0_RESTARTEN                (0x1UL << 24)                             /**< Restart Timer on TCMP0 */
+#define _USART_TIMECMP0_RESTARTEN_SHIFT         24                                        /**< Shift value for USART_RESTARTEN */
+#define _USART_TIMECMP0_RESTARTEN_MASK          0x1000000UL                               /**< Bit mask for USART_RESTARTEN */
+#define _USART_TIMECMP0_RESTARTEN_DEFAULT       0x00000000UL                              /**< Mode DEFAULT for USART_TIMECMP0 */
+#define USART_TIMECMP0_RESTARTEN_DEFAULT        (_USART_TIMECMP0_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP0 */
+
+/* Bit fields for USART TIMECMP1 */
+#define _USART_TIMECMP1_RESETVALUE              0x00000000UL                              /**< Default value for USART_TIMECMP1 */
+#define _USART_TIMECMP1_MASK                    0x017700FFUL                              /**< Mask for USART_TIMECMP1 */
+#define _USART_TIMECMP1_TCMPVAL_SHIFT           0                                         /**< Shift value for USART_TCMPVAL */
+#define _USART_TIMECMP1_TCMPVAL_MASK            0xFFUL                                    /**< Bit mask for USART_TCMPVAL */
+#define _USART_TIMECMP1_TCMPVAL_DEFAULT         0x00000000UL                              /**< Mode DEFAULT for USART_TIMECMP1 */
+#define USART_TIMECMP1_TCMPVAL_DEFAULT          (_USART_TIMECMP1_TCMPVAL_DEFAULT << 0)    /**< Shifted mode DEFAULT for USART_TIMECMP1 */
+#define _USART_TIMECMP1_TSTART_SHIFT            16                                        /**< Shift value for USART_TSTART */
+#define _USART_TIMECMP1_TSTART_MASK             0x70000UL                                 /**< Bit mask for USART_TSTART */
+#define _USART_TIMECMP1_TSTART_DEFAULT          0x00000000UL                              /**< Mode DEFAULT for USART_TIMECMP1 */
+#define _USART_TIMECMP1_TSTART_DISABLE          0x00000000UL                              /**< Mode DISABLE for USART_TIMECMP1 */
+#define _USART_TIMECMP1_TSTART_TXEOF            0x00000001UL                              /**< Mode TXEOF for USART_TIMECMP1 */
+#define _USART_TIMECMP1_TSTART_TXC              0x00000002UL                              /**< Mode TXC for USART_TIMECMP1 */
+#define _USART_TIMECMP1_TSTART_RXACT            0x00000003UL                              /**< Mode RXACT for USART_TIMECMP1 */
+#define _USART_TIMECMP1_TSTART_RXEOF            0x00000004UL                              /**< Mode RXEOF for USART_TIMECMP1 */
+#define USART_TIMECMP1_TSTART_DEFAULT           (_USART_TIMECMP1_TSTART_DEFAULT << 16)    /**< Shifted mode DEFAULT for USART_TIMECMP1 */
+#define USART_TIMECMP1_TSTART_DISABLE           (_USART_TIMECMP1_TSTART_DISABLE << 16)    /**< Shifted mode DISABLE for USART_TIMECMP1 */
+#define USART_TIMECMP1_TSTART_TXEOF             (_USART_TIMECMP1_TSTART_TXEOF << 16)      /**< Shifted mode TXEOF for USART_TIMECMP1 */
+#define USART_TIMECMP1_TSTART_TXC               (_USART_TIMECMP1_TSTART_TXC << 16)        /**< Shifted mode TXC for USART_TIMECMP1 */
+#define USART_TIMECMP1_TSTART_RXACT             (_USART_TIMECMP1_TSTART_RXACT << 16)      /**< Shifted mode RXACT for USART_TIMECMP1 */
+#define USART_TIMECMP1_TSTART_RXEOF             (_USART_TIMECMP1_TSTART_RXEOF << 16)      /**< Shifted mode RXEOF for USART_TIMECMP1 */
+#define _USART_TIMECMP1_TSTOP_SHIFT             20                                        /**< Shift value for USART_TSTOP */
+#define _USART_TIMECMP1_TSTOP_MASK              0x700000UL                                /**< Bit mask for USART_TSTOP */
+#define _USART_TIMECMP1_TSTOP_DEFAULT           0x00000000UL                              /**< Mode DEFAULT for USART_TIMECMP1 */
+#define _USART_TIMECMP1_TSTOP_TCMP1             0x00000000UL                              /**< Mode TCMP1 for USART_TIMECMP1 */
+#define _USART_TIMECMP1_TSTOP_TXST              0x00000001UL                              /**< Mode TXST for USART_TIMECMP1 */
+#define _USART_TIMECMP1_TSTOP_RXACT             0x00000002UL                              /**< Mode RXACT for USART_TIMECMP1 */
+#define _USART_TIMECMP1_TSTOP_RXACTN            0x00000003UL                              /**< Mode RXACTN for USART_TIMECMP1 */
+#define USART_TIMECMP1_TSTOP_DEFAULT            (_USART_TIMECMP1_TSTOP_DEFAULT << 20)     /**< Shifted mode DEFAULT for USART_TIMECMP1 */
+#define USART_TIMECMP1_TSTOP_TCMP1              (_USART_TIMECMP1_TSTOP_TCMP1 << 20)       /**< Shifted mode TCMP1 for USART_TIMECMP1 */
+#define USART_TIMECMP1_TSTOP_TXST               (_USART_TIMECMP1_TSTOP_TXST << 20)        /**< Shifted mode TXST for USART_TIMECMP1 */
+#define USART_TIMECMP1_TSTOP_RXACT              (_USART_TIMECMP1_TSTOP_RXACT << 20)       /**< Shifted mode RXACT for USART_TIMECMP1 */
+#define USART_TIMECMP1_TSTOP_RXACTN             (_USART_TIMECMP1_TSTOP_RXACTN << 20)      /**< Shifted mode RXACTN for USART_TIMECMP1 */
+#define USART_TIMECMP1_RESTARTEN                (0x1UL << 24)                             /**< Restart Timer on TCMP1 */
+#define _USART_TIMECMP1_RESTARTEN_SHIFT         24                                        /**< Shift value for USART_RESTARTEN */
+#define _USART_TIMECMP1_RESTARTEN_MASK          0x1000000UL                               /**< Bit mask for USART_RESTARTEN */
+#define _USART_TIMECMP1_RESTARTEN_DEFAULT       0x00000000UL                              /**< Mode DEFAULT for USART_TIMECMP1 */
+#define USART_TIMECMP1_RESTARTEN_DEFAULT        (_USART_TIMECMP1_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP1 */
+
+/* Bit fields for USART TIMECMP2 */
+#define _USART_TIMECMP2_RESETVALUE              0x00000000UL                              /**< Default value for USART_TIMECMP2 */
+#define _USART_TIMECMP2_MASK                    0x017700FFUL                              /**< Mask for USART_TIMECMP2 */
+#define _USART_TIMECMP2_TCMPVAL_SHIFT           0                                         /**< Shift value for USART_TCMPVAL */
+#define _USART_TIMECMP2_TCMPVAL_MASK            0xFFUL                                    /**< Bit mask for USART_TCMPVAL */
+#define _USART_TIMECMP2_TCMPVAL_DEFAULT         0x00000000UL                              /**< Mode DEFAULT for USART_TIMECMP2 */
+#define USART_TIMECMP2_TCMPVAL_DEFAULT          (_USART_TIMECMP2_TCMPVAL_DEFAULT << 0)    /**< Shifted mode DEFAULT for USART_TIMECMP2 */
+#define _USART_TIMECMP2_TSTART_SHIFT            16                                        /**< Shift value for USART_TSTART */
+#define _USART_TIMECMP2_TSTART_MASK             0x70000UL                                 /**< Bit mask for USART_TSTART */
+#define _USART_TIMECMP2_TSTART_DEFAULT          0x00000000UL                              /**< Mode DEFAULT for USART_TIMECMP2 */
+#define _USART_TIMECMP2_TSTART_DISABLE          0x00000000UL                              /**< Mode DISABLE for USART_TIMECMP2 */
+#define _USART_TIMECMP2_TSTART_TXEOF            0x00000001UL                              /**< Mode TXEOF for USART_TIMECMP2 */
+#define _USART_TIMECMP2_TSTART_TXC              0x00000002UL                              /**< Mode TXC for USART_TIMECMP2 */
+#define _USART_TIMECMP2_TSTART_RXACT            0x00000003UL                              /**< Mode RXACT for USART_TIMECMP2 */
+#define _USART_TIMECMP2_TSTART_RXEOF            0x00000004UL                              /**< Mode RXEOF for USART_TIMECMP2 */
+#define USART_TIMECMP2_TSTART_DEFAULT           (_USART_TIMECMP2_TSTART_DEFAULT << 16)    /**< Shifted mode DEFAULT for USART_TIMECMP2 */
+#define USART_TIMECMP2_TSTART_DISABLE           (_USART_TIMECMP2_TSTART_DISABLE << 16)    /**< Shifted mode DISABLE for USART_TIMECMP2 */
+#define USART_TIMECMP2_TSTART_TXEOF             (_USART_TIMECMP2_TSTART_TXEOF << 16)      /**< Shifted mode TXEOF for USART_TIMECMP2 */
+#define USART_TIMECMP2_TSTART_TXC               (_USART_TIMECMP2_TSTART_TXC << 16)        /**< Shifted mode TXC for USART_TIMECMP2 */
+#define USART_TIMECMP2_TSTART_RXACT             (_USART_TIMECMP2_TSTART_RXACT << 16)      /**< Shifted mode RXACT for USART_TIMECMP2 */
+#define USART_TIMECMP2_TSTART_RXEOF             (_USART_TIMECMP2_TSTART_RXEOF << 16)      /**< Shifted mode RXEOF for USART_TIMECMP2 */
+#define _USART_TIMECMP2_TSTOP_SHIFT             20                                        /**< Shift value for USART_TSTOP */
+#define _USART_TIMECMP2_TSTOP_MASK              0x700000UL                                /**< Bit mask for USART_TSTOP */
+#define _USART_TIMECMP2_TSTOP_DEFAULT           0x00000000UL                              /**< Mode DEFAULT for USART_TIMECMP2 */
+#define _USART_TIMECMP2_TSTOP_TCMP2             0x00000000UL                              /**< Mode TCMP2 for USART_TIMECMP2 */
+#define _USART_TIMECMP2_TSTOP_TXST              0x00000001UL                              /**< Mode TXST for USART_TIMECMP2 */
+#define _USART_TIMECMP2_TSTOP_RXACT             0x00000002UL                              /**< Mode RXACT for USART_TIMECMP2 */
+#define _USART_TIMECMP2_TSTOP_RXACTN            0x00000003UL                              /**< Mode RXACTN for USART_TIMECMP2 */
+#define USART_TIMECMP2_TSTOP_DEFAULT            (_USART_TIMECMP2_TSTOP_DEFAULT << 20)     /**< Shifted mode DEFAULT for USART_TIMECMP2 */
+#define USART_TIMECMP2_TSTOP_TCMP2              (_USART_TIMECMP2_TSTOP_TCMP2 << 20)       /**< Shifted mode TCMP2 for USART_TIMECMP2 */
+#define USART_TIMECMP2_TSTOP_TXST               (_USART_TIMECMP2_TSTOP_TXST << 20)        /**< Shifted mode TXST for USART_TIMECMP2 */
+#define USART_TIMECMP2_TSTOP_RXACT              (_USART_TIMECMP2_TSTOP_RXACT << 20)       /**< Shifted mode RXACT for USART_TIMECMP2 */
+#define USART_TIMECMP2_TSTOP_RXACTN             (_USART_TIMECMP2_TSTOP_RXACTN << 20)      /**< Shifted mode RXACTN for USART_TIMECMP2 */
+#define USART_TIMECMP2_RESTARTEN                (0x1UL << 24)                             /**< Restart Timer on TCMP2 */
+#define _USART_TIMECMP2_RESTARTEN_SHIFT         24                                        /**< Shift value for USART_RESTARTEN */
+#define _USART_TIMECMP2_RESTARTEN_MASK          0x1000000UL                               /**< Bit mask for USART_RESTARTEN */
+#define _USART_TIMECMP2_RESTARTEN_DEFAULT       0x00000000UL                              /**< Mode DEFAULT for USART_TIMECMP2 */
+#define USART_TIMECMP2_RESTARTEN_DEFAULT        (_USART_TIMECMP2_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP2 */
+
+/* Bit fields for USART ROUTEPEN */
+#define _USART_ROUTEPEN_RESETVALUE              0x00000000UL                          /**< Default value for USART_ROUTEPEN */
+#define _USART_ROUTEPEN_MASK                    0x0000003FUL                          /**< Mask for USART_ROUTEPEN */
+#define USART_ROUTEPEN_RXPEN                    (0x1UL << 0)                          /**< RX Pin Enable */
+#define _USART_ROUTEPEN_RXPEN_SHIFT             0                                     /**< Shift value for USART_RXPEN */
+#define _USART_ROUTEPEN_RXPEN_MASK              0x1UL                                 /**< Bit mask for USART_RXPEN */
+#define _USART_ROUTEPEN_RXPEN_DEFAULT           0x00000000UL                          /**< Mode DEFAULT for USART_ROUTEPEN */
+#define USART_ROUTEPEN_RXPEN_DEFAULT            (_USART_ROUTEPEN_RXPEN_DEFAULT << 0)  /**< Shifted mode DEFAULT for USART_ROUTEPEN */
+#define USART_ROUTEPEN_TXPEN                    (0x1UL << 1)                          /**< TX Pin Enable */
+#define _USART_ROUTEPEN_TXPEN_SHIFT             1                                     /**< Shift value for USART_TXPEN */
+#define _USART_ROUTEPEN_TXPEN_MASK              0x2UL                                 /**< Bit mask for USART_TXPEN */
+#define _USART_ROUTEPEN_TXPEN_DEFAULT           0x00000000UL                          /**< Mode DEFAULT for USART_ROUTEPEN */
+#define USART_ROUTEPEN_TXPEN_DEFAULT            (_USART_ROUTEPEN_TXPEN_DEFAULT << 1)  /**< Shifted mode DEFAULT for USART_ROUTEPEN */
+#define USART_ROUTEPEN_CSPEN                    (0x1UL << 2)                          /**< CS Pin Enable */
+#define _USART_ROUTEPEN_CSPEN_SHIFT             2                                     /**< Shift value for USART_CSPEN */
+#define _USART_ROUTEPEN_CSPEN_MASK              0x4UL                                 /**< Bit mask for USART_CSPEN */
+#define _USART_ROUTEPEN_CSPEN_DEFAULT           0x00000000UL                          /**< Mode DEFAULT for USART_ROUTEPEN */
+#define USART_ROUTEPEN_CSPEN_DEFAULT            (_USART_ROUTEPEN_CSPEN_DEFAULT << 2)  /**< Shifted mode DEFAULT for USART_ROUTEPEN */
+#define USART_ROUTEPEN_CLKPEN                   (0x1UL << 3)                          /**< CLK Pin Enable */
+#define _USART_ROUTEPEN_CLKPEN_SHIFT            3                                     /**< Shift value for USART_CLKPEN */
+#define _USART_ROUTEPEN_CLKPEN_MASK             0x8UL                                 /**< Bit mask for USART_CLKPEN */
+#define _USART_ROUTEPEN_CLKPEN_DEFAULT          0x00000000UL                          /**< Mode DEFAULT for USART_ROUTEPEN */
+#define USART_ROUTEPEN_CLKPEN_DEFAULT           (_USART_ROUTEPEN_CLKPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_ROUTEPEN */
+#define USART_ROUTEPEN_CTSPEN                   (0x1UL << 4)                          /**< CTS Pin Enable */
+#define _USART_ROUTEPEN_CTSPEN_SHIFT            4                                     /**< Shift value for USART_CTSPEN */
+#define _USART_ROUTEPEN_CTSPEN_MASK             0x10UL                                /**< Bit mask for USART_CTSPEN */
+#define _USART_ROUTEPEN_CTSPEN_DEFAULT          0x00000000UL                          /**< Mode DEFAULT for USART_ROUTEPEN */
+#define USART_ROUTEPEN_CTSPEN_DEFAULT           (_USART_ROUTEPEN_CTSPEN_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_ROUTEPEN */
+#define USART_ROUTEPEN_RTSPEN                   (0x1UL << 5)                          /**< RTS Pin Enable */
+#define _USART_ROUTEPEN_RTSPEN_SHIFT            5                                     /**< Shift value for USART_RTSPEN */
+#define _USART_ROUTEPEN_RTSPEN_MASK             0x20UL                                /**< Bit mask for USART_RTSPEN */
+#define _USART_ROUTEPEN_RTSPEN_DEFAULT          0x00000000UL                          /**< Mode DEFAULT for USART_ROUTEPEN */
+#define USART_ROUTEPEN_RTSPEN_DEFAULT           (_USART_ROUTEPEN_RTSPEN_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_ROUTEPEN */
+
+/* Bit fields for USART ROUTELOC0 */
+#define _USART_ROUTELOC0_RESETVALUE             0x00000000UL                            /**< Default value for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_MASK                   0x1F1F1F1FUL                            /**< Mask for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_RXLOC_SHIFT            0                                       /**< Shift value for USART_RXLOC */
+#define _USART_ROUTELOC0_RXLOC_MASK             0x1FUL                                  /**< Bit mask for USART_RXLOC */
+#define _USART_ROUTELOC0_RXLOC_LOC0             0x00000000UL                            /**< Mode LOC0 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_RXLOC_DEFAULT          0x00000000UL                            /**< Mode DEFAULT for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_RXLOC_LOC1             0x00000001UL                            /**< Mode LOC1 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_RXLOC_LOC2             0x00000002UL                            /**< Mode LOC2 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_RXLOC_LOC3             0x00000003UL                            /**< Mode LOC3 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_RXLOC_LOC4             0x00000004UL                            /**< Mode LOC4 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_RXLOC_LOC5             0x00000005UL                            /**< Mode LOC5 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_RXLOC_LOC6             0x00000006UL                            /**< Mode LOC6 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_RXLOC_LOC7             0x00000007UL                            /**< Mode LOC7 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_RXLOC_LOC8             0x00000008UL                            /**< Mode LOC8 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_RXLOC_LOC9             0x00000009UL                            /**< Mode LOC9 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_RXLOC_LOC10            0x0000000AUL                            /**< Mode LOC10 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_RXLOC_LOC11            0x0000000BUL                            /**< Mode LOC11 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_RXLOC_LOC12            0x0000000CUL                            /**< Mode LOC12 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_RXLOC_LOC13            0x0000000DUL                            /**< Mode LOC13 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_RXLOC_LOC14            0x0000000EUL                            /**< Mode LOC14 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_RXLOC_LOC15            0x0000000FUL                            /**< Mode LOC15 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_RXLOC_LOC16            0x00000010UL                            /**< Mode LOC16 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_RXLOC_LOC17            0x00000011UL                            /**< Mode LOC17 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_RXLOC_LOC18            0x00000012UL                            /**< Mode LOC18 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_RXLOC_LOC19            0x00000013UL                            /**< Mode LOC19 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_RXLOC_LOC20            0x00000014UL                            /**< Mode LOC20 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_RXLOC_LOC21            0x00000015UL                            /**< Mode LOC21 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_RXLOC_LOC22            0x00000016UL                            /**< Mode LOC22 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_RXLOC_LOC23            0x00000017UL                            /**< Mode LOC23 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_RXLOC_LOC24            0x00000018UL                            /**< Mode LOC24 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_RXLOC_LOC25            0x00000019UL                            /**< Mode LOC25 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_RXLOC_LOC26            0x0000001AUL                            /**< Mode LOC26 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_RXLOC_LOC27            0x0000001BUL                            /**< Mode LOC27 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_RXLOC_LOC28            0x0000001CUL                            /**< Mode LOC28 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_RXLOC_LOC29            0x0000001DUL                            /**< Mode LOC29 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_RXLOC_LOC30            0x0000001EUL                            /**< Mode LOC30 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_RXLOC_LOC31            0x0000001FUL                            /**< Mode LOC31 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_RXLOC_LOC0              (_USART_ROUTELOC0_RXLOC_LOC0 << 0)      /**< Shifted mode LOC0 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_RXLOC_DEFAULT           (_USART_ROUTELOC0_RXLOC_DEFAULT << 0)   /**< Shifted mode DEFAULT for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_RXLOC_LOC1              (_USART_ROUTELOC0_RXLOC_LOC1 << 0)      /**< Shifted mode LOC1 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_RXLOC_LOC2              (_USART_ROUTELOC0_RXLOC_LOC2 << 0)      /**< Shifted mode LOC2 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_RXLOC_LOC3              (_USART_ROUTELOC0_RXLOC_LOC3 << 0)      /**< Shifted mode LOC3 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_RXLOC_LOC4              (_USART_ROUTELOC0_RXLOC_LOC4 << 0)      /**< Shifted mode LOC4 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_RXLOC_LOC5              (_USART_ROUTELOC0_RXLOC_LOC5 << 0)      /**< Shifted mode LOC5 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_RXLOC_LOC6              (_USART_ROUTELOC0_RXLOC_LOC6 << 0)      /**< Shifted mode LOC6 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_RXLOC_LOC7              (_USART_ROUTELOC0_RXLOC_LOC7 << 0)      /**< Shifted mode LOC7 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_RXLOC_LOC8              (_USART_ROUTELOC0_RXLOC_LOC8 << 0)      /**< Shifted mode LOC8 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_RXLOC_LOC9              (_USART_ROUTELOC0_RXLOC_LOC9 << 0)      /**< Shifted mode LOC9 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_RXLOC_LOC10             (_USART_ROUTELOC0_RXLOC_LOC10 << 0)     /**< Shifted mode LOC10 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_RXLOC_LOC11             (_USART_ROUTELOC0_RXLOC_LOC11 << 0)     /**< Shifted mode LOC11 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_RXLOC_LOC12             (_USART_ROUTELOC0_RXLOC_LOC12 << 0)     /**< Shifted mode LOC12 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_RXLOC_LOC13             (_USART_ROUTELOC0_RXLOC_LOC13 << 0)     /**< Shifted mode LOC13 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_RXLOC_LOC14             (_USART_ROUTELOC0_RXLOC_LOC14 << 0)     /**< Shifted mode LOC14 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_RXLOC_LOC15             (_USART_ROUTELOC0_RXLOC_LOC15 << 0)     /**< Shifted mode LOC15 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_RXLOC_LOC16             (_USART_ROUTELOC0_RXLOC_LOC16 << 0)     /**< Shifted mode LOC16 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_RXLOC_LOC17             (_USART_ROUTELOC0_RXLOC_LOC17 << 0)     /**< Shifted mode LOC17 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_RXLOC_LOC18             (_USART_ROUTELOC0_RXLOC_LOC18 << 0)     /**< Shifted mode LOC18 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_RXLOC_LOC19             (_USART_ROUTELOC0_RXLOC_LOC19 << 0)     /**< Shifted mode LOC19 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_RXLOC_LOC20             (_USART_ROUTELOC0_RXLOC_LOC20 << 0)     /**< Shifted mode LOC20 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_RXLOC_LOC21             (_USART_ROUTELOC0_RXLOC_LOC21 << 0)     /**< Shifted mode LOC21 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_RXLOC_LOC22             (_USART_ROUTELOC0_RXLOC_LOC22 << 0)     /**< Shifted mode LOC22 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_RXLOC_LOC23             (_USART_ROUTELOC0_RXLOC_LOC23 << 0)     /**< Shifted mode LOC23 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_RXLOC_LOC24             (_USART_ROUTELOC0_RXLOC_LOC24 << 0)     /**< Shifted mode LOC24 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_RXLOC_LOC25             (_USART_ROUTELOC0_RXLOC_LOC25 << 0)     /**< Shifted mode LOC25 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_RXLOC_LOC26             (_USART_ROUTELOC0_RXLOC_LOC26 << 0)     /**< Shifted mode LOC26 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_RXLOC_LOC27             (_USART_ROUTELOC0_RXLOC_LOC27 << 0)     /**< Shifted mode LOC27 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_RXLOC_LOC28             (_USART_ROUTELOC0_RXLOC_LOC28 << 0)     /**< Shifted mode LOC28 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_RXLOC_LOC29             (_USART_ROUTELOC0_RXLOC_LOC29 << 0)     /**< Shifted mode LOC29 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_RXLOC_LOC30             (_USART_ROUTELOC0_RXLOC_LOC30 << 0)     /**< Shifted mode LOC30 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_RXLOC_LOC31             (_USART_ROUTELOC0_RXLOC_LOC31 << 0)     /**< Shifted mode LOC31 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_TXLOC_SHIFT            8                                       /**< Shift value for USART_TXLOC */
+#define _USART_ROUTELOC0_TXLOC_MASK             0x1F00UL                                /**< Bit mask for USART_TXLOC */
+#define _USART_ROUTELOC0_TXLOC_LOC0             0x00000000UL                            /**< Mode LOC0 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_TXLOC_DEFAULT          0x00000000UL                            /**< Mode DEFAULT for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_TXLOC_LOC1             0x00000001UL                            /**< Mode LOC1 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_TXLOC_LOC2             0x00000002UL                            /**< Mode LOC2 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_TXLOC_LOC3             0x00000003UL                            /**< Mode LOC3 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_TXLOC_LOC4             0x00000004UL                            /**< Mode LOC4 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_TXLOC_LOC5             0x00000005UL                            /**< Mode LOC5 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_TXLOC_LOC6             0x00000006UL                            /**< Mode LOC6 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_TXLOC_LOC7             0x00000007UL                            /**< Mode LOC7 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_TXLOC_LOC8             0x00000008UL                            /**< Mode LOC8 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_TXLOC_LOC9             0x00000009UL                            /**< Mode LOC9 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_TXLOC_LOC10            0x0000000AUL                            /**< Mode LOC10 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_TXLOC_LOC11            0x0000000BUL                            /**< Mode LOC11 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_TXLOC_LOC12            0x0000000CUL                            /**< Mode LOC12 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_TXLOC_LOC13            0x0000000DUL                            /**< Mode LOC13 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_TXLOC_LOC14            0x0000000EUL                            /**< Mode LOC14 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_TXLOC_LOC15            0x0000000FUL                            /**< Mode LOC15 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_TXLOC_LOC16            0x00000010UL                            /**< Mode LOC16 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_TXLOC_LOC17            0x00000011UL                            /**< Mode LOC17 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_TXLOC_LOC18            0x00000012UL                            /**< Mode LOC18 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_TXLOC_LOC19            0x00000013UL                            /**< Mode LOC19 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_TXLOC_LOC20            0x00000014UL                            /**< Mode LOC20 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_TXLOC_LOC21            0x00000015UL                            /**< Mode LOC21 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_TXLOC_LOC22            0x00000016UL                            /**< Mode LOC22 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_TXLOC_LOC23            0x00000017UL                            /**< Mode LOC23 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_TXLOC_LOC24            0x00000018UL                            /**< Mode LOC24 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_TXLOC_LOC25            0x00000019UL                            /**< Mode LOC25 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_TXLOC_LOC26            0x0000001AUL                            /**< Mode LOC26 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_TXLOC_LOC27            0x0000001BUL                            /**< Mode LOC27 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_TXLOC_LOC28            0x0000001CUL                            /**< Mode LOC28 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_TXLOC_LOC29            0x0000001DUL                            /**< Mode LOC29 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_TXLOC_LOC30            0x0000001EUL                            /**< Mode LOC30 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_TXLOC_LOC31            0x0000001FUL                            /**< Mode LOC31 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_TXLOC_LOC0              (_USART_ROUTELOC0_TXLOC_LOC0 << 8)      /**< Shifted mode LOC0 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_TXLOC_DEFAULT           (_USART_ROUTELOC0_TXLOC_DEFAULT << 8)   /**< Shifted mode DEFAULT for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_TXLOC_LOC1              (_USART_ROUTELOC0_TXLOC_LOC1 << 8)      /**< Shifted mode LOC1 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_TXLOC_LOC2              (_USART_ROUTELOC0_TXLOC_LOC2 << 8)      /**< Shifted mode LOC2 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_TXLOC_LOC3              (_USART_ROUTELOC0_TXLOC_LOC3 << 8)      /**< Shifted mode LOC3 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_TXLOC_LOC4              (_USART_ROUTELOC0_TXLOC_LOC4 << 8)      /**< Shifted mode LOC4 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_TXLOC_LOC5              (_USART_ROUTELOC0_TXLOC_LOC5 << 8)      /**< Shifted mode LOC5 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_TXLOC_LOC6              (_USART_ROUTELOC0_TXLOC_LOC6 << 8)      /**< Shifted mode LOC6 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_TXLOC_LOC7              (_USART_ROUTELOC0_TXLOC_LOC7 << 8)      /**< Shifted mode LOC7 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_TXLOC_LOC8              (_USART_ROUTELOC0_TXLOC_LOC8 << 8)      /**< Shifted mode LOC8 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_TXLOC_LOC9              (_USART_ROUTELOC0_TXLOC_LOC9 << 8)      /**< Shifted mode LOC9 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_TXLOC_LOC10             (_USART_ROUTELOC0_TXLOC_LOC10 << 8)     /**< Shifted mode LOC10 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_TXLOC_LOC11             (_USART_ROUTELOC0_TXLOC_LOC11 << 8)     /**< Shifted mode LOC11 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_TXLOC_LOC12             (_USART_ROUTELOC0_TXLOC_LOC12 << 8)     /**< Shifted mode LOC12 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_TXLOC_LOC13             (_USART_ROUTELOC0_TXLOC_LOC13 << 8)     /**< Shifted mode LOC13 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_TXLOC_LOC14             (_USART_ROUTELOC0_TXLOC_LOC14 << 8)     /**< Shifted mode LOC14 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_TXLOC_LOC15             (_USART_ROUTELOC0_TXLOC_LOC15 << 8)     /**< Shifted mode LOC15 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_TXLOC_LOC16             (_USART_ROUTELOC0_TXLOC_LOC16 << 8)     /**< Shifted mode LOC16 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_TXLOC_LOC17             (_USART_ROUTELOC0_TXLOC_LOC17 << 8)     /**< Shifted mode LOC17 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_TXLOC_LOC18             (_USART_ROUTELOC0_TXLOC_LOC18 << 8)     /**< Shifted mode LOC18 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_TXLOC_LOC19             (_USART_ROUTELOC0_TXLOC_LOC19 << 8)     /**< Shifted mode LOC19 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_TXLOC_LOC20             (_USART_ROUTELOC0_TXLOC_LOC20 << 8)     /**< Shifted mode LOC20 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_TXLOC_LOC21             (_USART_ROUTELOC0_TXLOC_LOC21 << 8)     /**< Shifted mode LOC21 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_TXLOC_LOC22             (_USART_ROUTELOC0_TXLOC_LOC22 << 8)     /**< Shifted mode LOC22 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_TXLOC_LOC23             (_USART_ROUTELOC0_TXLOC_LOC23 << 8)     /**< Shifted mode LOC23 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_TXLOC_LOC24             (_USART_ROUTELOC0_TXLOC_LOC24 << 8)     /**< Shifted mode LOC24 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_TXLOC_LOC25             (_USART_ROUTELOC0_TXLOC_LOC25 << 8)     /**< Shifted mode LOC25 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_TXLOC_LOC26             (_USART_ROUTELOC0_TXLOC_LOC26 << 8)     /**< Shifted mode LOC26 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_TXLOC_LOC27             (_USART_ROUTELOC0_TXLOC_LOC27 << 8)     /**< Shifted mode LOC27 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_TXLOC_LOC28             (_USART_ROUTELOC0_TXLOC_LOC28 << 8)     /**< Shifted mode LOC28 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_TXLOC_LOC29             (_USART_ROUTELOC0_TXLOC_LOC29 << 8)     /**< Shifted mode LOC29 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_TXLOC_LOC30             (_USART_ROUTELOC0_TXLOC_LOC30 << 8)     /**< Shifted mode LOC30 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_TXLOC_LOC31             (_USART_ROUTELOC0_TXLOC_LOC31 << 8)     /**< Shifted mode LOC31 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CSLOC_SHIFT            16                                      /**< Shift value for USART_CSLOC */
+#define _USART_ROUTELOC0_CSLOC_MASK             0x1F0000UL                              /**< Bit mask for USART_CSLOC */
+#define _USART_ROUTELOC0_CSLOC_LOC0             0x00000000UL                            /**< Mode LOC0 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CSLOC_DEFAULT          0x00000000UL                            /**< Mode DEFAULT for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CSLOC_LOC1             0x00000001UL                            /**< Mode LOC1 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CSLOC_LOC2             0x00000002UL                            /**< Mode LOC2 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CSLOC_LOC3             0x00000003UL                            /**< Mode LOC3 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CSLOC_LOC4             0x00000004UL                            /**< Mode LOC4 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CSLOC_LOC5             0x00000005UL                            /**< Mode LOC5 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CSLOC_LOC6             0x00000006UL                            /**< Mode LOC6 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CSLOC_LOC7             0x00000007UL                            /**< Mode LOC7 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CSLOC_LOC8             0x00000008UL                            /**< Mode LOC8 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CSLOC_LOC9             0x00000009UL                            /**< Mode LOC9 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CSLOC_LOC10            0x0000000AUL                            /**< Mode LOC10 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CSLOC_LOC11            0x0000000BUL                            /**< Mode LOC11 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CSLOC_LOC12            0x0000000CUL                            /**< Mode LOC12 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CSLOC_LOC13            0x0000000DUL                            /**< Mode LOC13 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CSLOC_LOC14            0x0000000EUL                            /**< Mode LOC14 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CSLOC_LOC15            0x0000000FUL                            /**< Mode LOC15 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CSLOC_LOC16            0x00000010UL                            /**< Mode LOC16 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CSLOC_LOC17            0x00000011UL                            /**< Mode LOC17 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CSLOC_LOC18            0x00000012UL                            /**< Mode LOC18 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CSLOC_LOC19            0x00000013UL                            /**< Mode LOC19 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CSLOC_LOC20            0x00000014UL                            /**< Mode LOC20 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CSLOC_LOC21            0x00000015UL                            /**< Mode LOC21 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CSLOC_LOC22            0x00000016UL                            /**< Mode LOC22 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CSLOC_LOC23            0x00000017UL                            /**< Mode LOC23 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CSLOC_LOC24            0x00000018UL                            /**< Mode LOC24 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CSLOC_LOC25            0x00000019UL                            /**< Mode LOC25 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CSLOC_LOC26            0x0000001AUL                            /**< Mode LOC26 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CSLOC_LOC27            0x0000001BUL                            /**< Mode LOC27 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CSLOC_LOC28            0x0000001CUL                            /**< Mode LOC28 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CSLOC_LOC29            0x0000001DUL                            /**< Mode LOC29 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CSLOC_LOC30            0x0000001EUL                            /**< Mode LOC30 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CSLOC_LOC31            0x0000001FUL                            /**< Mode LOC31 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CSLOC_LOC0              (_USART_ROUTELOC0_CSLOC_LOC0 << 16)     /**< Shifted mode LOC0 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CSLOC_DEFAULT           (_USART_ROUTELOC0_CSLOC_DEFAULT << 16)  /**< Shifted mode DEFAULT for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CSLOC_LOC1              (_USART_ROUTELOC0_CSLOC_LOC1 << 16)     /**< Shifted mode LOC1 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CSLOC_LOC2              (_USART_ROUTELOC0_CSLOC_LOC2 << 16)     /**< Shifted mode LOC2 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CSLOC_LOC3              (_USART_ROUTELOC0_CSLOC_LOC3 << 16)     /**< Shifted mode LOC3 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CSLOC_LOC4              (_USART_ROUTELOC0_CSLOC_LOC4 << 16)     /**< Shifted mode LOC4 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CSLOC_LOC5              (_USART_ROUTELOC0_CSLOC_LOC5 << 16)     /**< Shifted mode LOC5 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CSLOC_LOC6              (_USART_ROUTELOC0_CSLOC_LOC6 << 16)     /**< Shifted mode LOC6 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CSLOC_LOC7              (_USART_ROUTELOC0_CSLOC_LOC7 << 16)     /**< Shifted mode LOC7 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CSLOC_LOC8              (_USART_ROUTELOC0_CSLOC_LOC8 << 16)     /**< Shifted mode LOC8 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CSLOC_LOC9              (_USART_ROUTELOC0_CSLOC_LOC9 << 16)     /**< Shifted mode LOC9 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CSLOC_LOC10             (_USART_ROUTELOC0_CSLOC_LOC10 << 16)    /**< Shifted mode LOC10 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CSLOC_LOC11             (_USART_ROUTELOC0_CSLOC_LOC11 << 16)    /**< Shifted mode LOC11 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CSLOC_LOC12             (_USART_ROUTELOC0_CSLOC_LOC12 << 16)    /**< Shifted mode LOC12 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CSLOC_LOC13             (_USART_ROUTELOC0_CSLOC_LOC13 << 16)    /**< Shifted mode LOC13 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CSLOC_LOC14             (_USART_ROUTELOC0_CSLOC_LOC14 << 16)    /**< Shifted mode LOC14 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CSLOC_LOC15             (_USART_ROUTELOC0_CSLOC_LOC15 << 16)    /**< Shifted mode LOC15 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CSLOC_LOC16             (_USART_ROUTELOC0_CSLOC_LOC16 << 16)    /**< Shifted mode LOC16 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CSLOC_LOC17             (_USART_ROUTELOC0_CSLOC_LOC17 << 16)    /**< Shifted mode LOC17 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CSLOC_LOC18             (_USART_ROUTELOC0_CSLOC_LOC18 << 16)    /**< Shifted mode LOC18 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CSLOC_LOC19             (_USART_ROUTELOC0_CSLOC_LOC19 << 16)    /**< Shifted mode LOC19 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CSLOC_LOC20             (_USART_ROUTELOC0_CSLOC_LOC20 << 16)    /**< Shifted mode LOC20 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CSLOC_LOC21             (_USART_ROUTELOC0_CSLOC_LOC21 << 16)    /**< Shifted mode LOC21 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CSLOC_LOC22             (_USART_ROUTELOC0_CSLOC_LOC22 << 16)    /**< Shifted mode LOC22 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CSLOC_LOC23             (_USART_ROUTELOC0_CSLOC_LOC23 << 16)    /**< Shifted mode LOC23 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CSLOC_LOC24             (_USART_ROUTELOC0_CSLOC_LOC24 << 16)    /**< Shifted mode LOC24 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CSLOC_LOC25             (_USART_ROUTELOC0_CSLOC_LOC25 << 16)    /**< Shifted mode LOC25 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CSLOC_LOC26             (_USART_ROUTELOC0_CSLOC_LOC26 << 16)    /**< Shifted mode LOC26 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CSLOC_LOC27             (_USART_ROUTELOC0_CSLOC_LOC27 << 16)    /**< Shifted mode LOC27 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CSLOC_LOC28             (_USART_ROUTELOC0_CSLOC_LOC28 << 16)    /**< Shifted mode LOC28 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CSLOC_LOC29             (_USART_ROUTELOC0_CSLOC_LOC29 << 16)    /**< Shifted mode LOC29 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CSLOC_LOC30             (_USART_ROUTELOC0_CSLOC_LOC30 << 16)    /**< Shifted mode LOC30 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CSLOC_LOC31             (_USART_ROUTELOC0_CSLOC_LOC31 << 16)    /**< Shifted mode LOC31 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CLKLOC_SHIFT           24                                      /**< Shift value for USART_CLKLOC */
+#define _USART_ROUTELOC0_CLKLOC_MASK            0x1F000000UL                            /**< Bit mask for USART_CLKLOC */
+#define _USART_ROUTELOC0_CLKLOC_LOC0            0x00000000UL                            /**< Mode LOC0 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CLKLOC_DEFAULT         0x00000000UL                            /**< Mode DEFAULT for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CLKLOC_LOC1            0x00000001UL                            /**< Mode LOC1 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CLKLOC_LOC2            0x00000002UL                            /**< Mode LOC2 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CLKLOC_LOC3            0x00000003UL                            /**< Mode LOC3 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CLKLOC_LOC4            0x00000004UL                            /**< Mode LOC4 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CLKLOC_LOC5            0x00000005UL                            /**< Mode LOC5 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CLKLOC_LOC6            0x00000006UL                            /**< Mode LOC6 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CLKLOC_LOC7            0x00000007UL                            /**< Mode LOC7 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CLKLOC_LOC8            0x00000008UL                            /**< Mode LOC8 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CLKLOC_LOC9            0x00000009UL                            /**< Mode LOC9 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CLKLOC_LOC10           0x0000000AUL                            /**< Mode LOC10 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CLKLOC_LOC11           0x0000000BUL                            /**< Mode LOC11 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CLKLOC_LOC12           0x0000000CUL                            /**< Mode LOC12 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CLKLOC_LOC13           0x0000000DUL                            /**< Mode LOC13 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CLKLOC_LOC14           0x0000000EUL                            /**< Mode LOC14 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CLKLOC_LOC15           0x0000000FUL                            /**< Mode LOC15 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CLKLOC_LOC16           0x00000010UL                            /**< Mode LOC16 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CLKLOC_LOC17           0x00000011UL                            /**< Mode LOC17 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CLKLOC_LOC18           0x00000012UL                            /**< Mode LOC18 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CLKLOC_LOC19           0x00000013UL                            /**< Mode LOC19 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CLKLOC_LOC20           0x00000014UL                            /**< Mode LOC20 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CLKLOC_LOC21           0x00000015UL                            /**< Mode LOC21 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CLKLOC_LOC22           0x00000016UL                            /**< Mode LOC22 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CLKLOC_LOC23           0x00000017UL                            /**< Mode LOC23 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CLKLOC_LOC24           0x00000018UL                            /**< Mode LOC24 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CLKLOC_LOC25           0x00000019UL                            /**< Mode LOC25 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CLKLOC_LOC26           0x0000001AUL                            /**< Mode LOC26 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CLKLOC_LOC27           0x0000001BUL                            /**< Mode LOC27 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CLKLOC_LOC28           0x0000001CUL                            /**< Mode LOC28 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CLKLOC_LOC29           0x0000001DUL                            /**< Mode LOC29 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CLKLOC_LOC30           0x0000001EUL                            /**< Mode LOC30 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CLKLOC_LOC31           0x0000001FUL                            /**< Mode LOC31 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CLKLOC_LOC0             (_USART_ROUTELOC0_CLKLOC_LOC0 << 24)    /**< Shifted mode LOC0 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CLKLOC_DEFAULT          (_USART_ROUTELOC0_CLKLOC_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CLKLOC_LOC1             (_USART_ROUTELOC0_CLKLOC_LOC1 << 24)    /**< Shifted mode LOC1 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CLKLOC_LOC2             (_USART_ROUTELOC0_CLKLOC_LOC2 << 24)    /**< Shifted mode LOC2 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CLKLOC_LOC3             (_USART_ROUTELOC0_CLKLOC_LOC3 << 24)    /**< Shifted mode LOC3 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CLKLOC_LOC4             (_USART_ROUTELOC0_CLKLOC_LOC4 << 24)    /**< Shifted mode LOC4 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CLKLOC_LOC5             (_USART_ROUTELOC0_CLKLOC_LOC5 << 24)    /**< Shifted mode LOC5 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CLKLOC_LOC6             (_USART_ROUTELOC0_CLKLOC_LOC6 << 24)    /**< Shifted mode LOC6 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CLKLOC_LOC7             (_USART_ROUTELOC0_CLKLOC_LOC7 << 24)    /**< Shifted mode LOC7 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CLKLOC_LOC8             (_USART_ROUTELOC0_CLKLOC_LOC8 << 24)    /**< Shifted mode LOC8 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CLKLOC_LOC9             (_USART_ROUTELOC0_CLKLOC_LOC9 << 24)    /**< Shifted mode LOC9 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CLKLOC_LOC10            (_USART_ROUTELOC0_CLKLOC_LOC10 << 24)   /**< Shifted mode LOC10 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CLKLOC_LOC11            (_USART_ROUTELOC0_CLKLOC_LOC11 << 24)   /**< Shifted mode LOC11 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CLKLOC_LOC12            (_USART_ROUTELOC0_CLKLOC_LOC12 << 24)   /**< Shifted mode LOC12 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CLKLOC_LOC13            (_USART_ROUTELOC0_CLKLOC_LOC13 << 24)   /**< Shifted mode LOC13 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CLKLOC_LOC14            (_USART_ROUTELOC0_CLKLOC_LOC14 << 24)   /**< Shifted mode LOC14 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CLKLOC_LOC15            (_USART_ROUTELOC0_CLKLOC_LOC15 << 24)   /**< Shifted mode LOC15 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CLKLOC_LOC16            (_USART_ROUTELOC0_CLKLOC_LOC16 << 24)   /**< Shifted mode LOC16 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CLKLOC_LOC17            (_USART_ROUTELOC0_CLKLOC_LOC17 << 24)   /**< Shifted mode LOC17 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CLKLOC_LOC18            (_USART_ROUTELOC0_CLKLOC_LOC18 << 24)   /**< Shifted mode LOC18 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CLKLOC_LOC19            (_USART_ROUTELOC0_CLKLOC_LOC19 << 24)   /**< Shifted mode LOC19 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CLKLOC_LOC20            (_USART_ROUTELOC0_CLKLOC_LOC20 << 24)   /**< Shifted mode LOC20 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CLKLOC_LOC21            (_USART_ROUTELOC0_CLKLOC_LOC21 << 24)   /**< Shifted mode LOC21 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CLKLOC_LOC22            (_USART_ROUTELOC0_CLKLOC_LOC22 << 24)   /**< Shifted mode LOC22 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CLKLOC_LOC23            (_USART_ROUTELOC0_CLKLOC_LOC23 << 24)   /**< Shifted mode LOC23 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CLKLOC_LOC24            (_USART_ROUTELOC0_CLKLOC_LOC24 << 24)   /**< Shifted mode LOC24 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CLKLOC_LOC25            (_USART_ROUTELOC0_CLKLOC_LOC25 << 24)   /**< Shifted mode LOC25 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CLKLOC_LOC26            (_USART_ROUTELOC0_CLKLOC_LOC26 << 24)   /**< Shifted mode LOC26 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CLKLOC_LOC27            (_USART_ROUTELOC0_CLKLOC_LOC27 << 24)   /**< Shifted mode LOC27 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CLKLOC_LOC28            (_USART_ROUTELOC0_CLKLOC_LOC28 << 24)   /**< Shifted mode LOC28 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CLKLOC_LOC29            (_USART_ROUTELOC0_CLKLOC_LOC29 << 24)   /**< Shifted mode LOC29 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CLKLOC_LOC30            (_USART_ROUTELOC0_CLKLOC_LOC30 << 24)   /**< Shifted mode LOC30 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CLKLOC_LOC31            (_USART_ROUTELOC0_CLKLOC_LOC31 << 24)   /**< Shifted mode LOC31 for USART_ROUTELOC0 */
+
+/* Bit fields for USART ROUTELOC1 */
+#define _USART_ROUTELOC1_RESETVALUE             0x00000000UL                           /**< Default value for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_MASK                   0x00001F1FUL                           /**< Mask for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_CTSLOC_SHIFT           0                                      /**< Shift value for USART_CTSLOC */
+#define _USART_ROUTELOC1_CTSLOC_MASK            0x1FUL                                 /**< Bit mask for USART_CTSLOC */
+#define _USART_ROUTELOC1_CTSLOC_LOC0            0x00000000UL                           /**< Mode LOC0 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_CTSLOC_DEFAULT         0x00000000UL                           /**< Mode DEFAULT for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_CTSLOC_LOC1            0x00000001UL                           /**< Mode LOC1 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_CTSLOC_LOC2            0x00000002UL                           /**< Mode LOC2 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_CTSLOC_LOC3            0x00000003UL                           /**< Mode LOC3 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_CTSLOC_LOC4            0x00000004UL                           /**< Mode LOC4 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_CTSLOC_LOC5            0x00000005UL                           /**< Mode LOC5 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_CTSLOC_LOC6            0x00000006UL                           /**< Mode LOC6 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_CTSLOC_LOC7            0x00000007UL                           /**< Mode LOC7 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_CTSLOC_LOC8            0x00000008UL                           /**< Mode LOC8 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_CTSLOC_LOC9            0x00000009UL                           /**< Mode LOC9 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_CTSLOC_LOC10           0x0000000AUL                           /**< Mode LOC10 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_CTSLOC_LOC11           0x0000000BUL                           /**< Mode LOC11 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_CTSLOC_LOC12           0x0000000CUL                           /**< Mode LOC12 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_CTSLOC_LOC13           0x0000000DUL                           /**< Mode LOC13 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_CTSLOC_LOC14           0x0000000EUL                           /**< Mode LOC14 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_CTSLOC_LOC15           0x0000000FUL                           /**< Mode LOC15 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_CTSLOC_LOC16           0x00000010UL                           /**< Mode LOC16 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_CTSLOC_LOC17           0x00000011UL                           /**< Mode LOC17 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_CTSLOC_LOC18           0x00000012UL                           /**< Mode LOC18 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_CTSLOC_LOC19           0x00000013UL                           /**< Mode LOC19 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_CTSLOC_LOC20           0x00000014UL                           /**< Mode LOC20 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_CTSLOC_LOC21           0x00000015UL                           /**< Mode LOC21 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_CTSLOC_LOC22           0x00000016UL                           /**< Mode LOC22 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_CTSLOC_LOC23           0x00000017UL                           /**< Mode LOC23 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_CTSLOC_LOC24           0x00000018UL                           /**< Mode LOC24 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_CTSLOC_LOC25           0x00000019UL                           /**< Mode LOC25 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_CTSLOC_LOC26           0x0000001AUL                           /**< Mode LOC26 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_CTSLOC_LOC27           0x0000001BUL                           /**< Mode LOC27 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_CTSLOC_LOC28           0x0000001CUL                           /**< Mode LOC28 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_CTSLOC_LOC29           0x0000001DUL                           /**< Mode LOC29 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_CTSLOC_LOC30           0x0000001EUL                           /**< Mode LOC30 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_CTSLOC_LOC31           0x0000001FUL                           /**< Mode LOC31 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_CTSLOC_LOC0             (_USART_ROUTELOC1_CTSLOC_LOC0 << 0)    /**< Shifted mode LOC0 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_CTSLOC_DEFAULT          (_USART_ROUTELOC1_CTSLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_CTSLOC_LOC1             (_USART_ROUTELOC1_CTSLOC_LOC1 << 0)    /**< Shifted mode LOC1 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_CTSLOC_LOC2             (_USART_ROUTELOC1_CTSLOC_LOC2 << 0)    /**< Shifted mode LOC2 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_CTSLOC_LOC3             (_USART_ROUTELOC1_CTSLOC_LOC3 << 0)    /**< Shifted mode LOC3 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_CTSLOC_LOC4             (_USART_ROUTELOC1_CTSLOC_LOC4 << 0)    /**< Shifted mode LOC4 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_CTSLOC_LOC5             (_USART_ROUTELOC1_CTSLOC_LOC5 << 0)    /**< Shifted mode LOC5 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_CTSLOC_LOC6             (_USART_ROUTELOC1_CTSLOC_LOC6 << 0)    /**< Shifted mode LOC6 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_CTSLOC_LOC7             (_USART_ROUTELOC1_CTSLOC_LOC7 << 0)    /**< Shifted mode LOC7 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_CTSLOC_LOC8             (_USART_ROUTELOC1_CTSLOC_LOC8 << 0)    /**< Shifted mode LOC8 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_CTSLOC_LOC9             (_USART_ROUTELOC1_CTSLOC_LOC9 << 0)    /**< Shifted mode LOC9 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_CTSLOC_LOC10            (_USART_ROUTELOC1_CTSLOC_LOC10 << 0)   /**< Shifted mode LOC10 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_CTSLOC_LOC11            (_USART_ROUTELOC1_CTSLOC_LOC11 << 0)   /**< Shifted mode LOC11 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_CTSLOC_LOC12            (_USART_ROUTELOC1_CTSLOC_LOC12 << 0)   /**< Shifted mode LOC12 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_CTSLOC_LOC13            (_USART_ROUTELOC1_CTSLOC_LOC13 << 0)   /**< Shifted mode LOC13 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_CTSLOC_LOC14            (_USART_ROUTELOC1_CTSLOC_LOC14 << 0)   /**< Shifted mode LOC14 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_CTSLOC_LOC15            (_USART_ROUTELOC1_CTSLOC_LOC15 << 0)   /**< Shifted mode LOC15 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_CTSLOC_LOC16            (_USART_ROUTELOC1_CTSLOC_LOC16 << 0)   /**< Shifted mode LOC16 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_CTSLOC_LOC17            (_USART_ROUTELOC1_CTSLOC_LOC17 << 0)   /**< Shifted mode LOC17 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_CTSLOC_LOC18            (_USART_ROUTELOC1_CTSLOC_LOC18 << 0)   /**< Shifted mode LOC18 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_CTSLOC_LOC19            (_USART_ROUTELOC1_CTSLOC_LOC19 << 0)   /**< Shifted mode LOC19 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_CTSLOC_LOC20            (_USART_ROUTELOC1_CTSLOC_LOC20 << 0)   /**< Shifted mode LOC20 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_CTSLOC_LOC21            (_USART_ROUTELOC1_CTSLOC_LOC21 << 0)   /**< Shifted mode LOC21 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_CTSLOC_LOC22            (_USART_ROUTELOC1_CTSLOC_LOC22 << 0)   /**< Shifted mode LOC22 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_CTSLOC_LOC23            (_USART_ROUTELOC1_CTSLOC_LOC23 << 0)   /**< Shifted mode LOC23 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_CTSLOC_LOC24            (_USART_ROUTELOC1_CTSLOC_LOC24 << 0)   /**< Shifted mode LOC24 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_CTSLOC_LOC25            (_USART_ROUTELOC1_CTSLOC_LOC25 << 0)   /**< Shifted mode LOC25 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_CTSLOC_LOC26            (_USART_ROUTELOC1_CTSLOC_LOC26 << 0)   /**< Shifted mode LOC26 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_CTSLOC_LOC27            (_USART_ROUTELOC1_CTSLOC_LOC27 << 0)   /**< Shifted mode LOC27 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_CTSLOC_LOC28            (_USART_ROUTELOC1_CTSLOC_LOC28 << 0)   /**< Shifted mode LOC28 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_CTSLOC_LOC29            (_USART_ROUTELOC1_CTSLOC_LOC29 << 0)   /**< Shifted mode LOC29 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_CTSLOC_LOC30            (_USART_ROUTELOC1_CTSLOC_LOC30 << 0)   /**< Shifted mode LOC30 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_CTSLOC_LOC31            (_USART_ROUTELOC1_CTSLOC_LOC31 << 0)   /**< Shifted mode LOC31 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_RTSLOC_SHIFT           8                                      /**< Shift value for USART_RTSLOC */
+#define _USART_ROUTELOC1_RTSLOC_MASK            0x1F00UL                               /**< Bit mask for USART_RTSLOC */
+#define _USART_ROUTELOC1_RTSLOC_LOC0            0x00000000UL                           /**< Mode LOC0 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_RTSLOC_DEFAULT         0x00000000UL                           /**< Mode DEFAULT for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_RTSLOC_LOC1            0x00000001UL                           /**< Mode LOC1 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_RTSLOC_LOC2            0x00000002UL                           /**< Mode LOC2 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_RTSLOC_LOC3            0x00000003UL                           /**< Mode LOC3 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_RTSLOC_LOC4            0x00000004UL                           /**< Mode LOC4 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_RTSLOC_LOC5            0x00000005UL                           /**< Mode LOC5 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_RTSLOC_LOC6            0x00000006UL                           /**< Mode LOC6 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_RTSLOC_LOC7            0x00000007UL                           /**< Mode LOC7 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_RTSLOC_LOC8            0x00000008UL                           /**< Mode LOC8 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_RTSLOC_LOC9            0x00000009UL                           /**< Mode LOC9 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_RTSLOC_LOC10           0x0000000AUL                           /**< Mode LOC10 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_RTSLOC_LOC11           0x0000000BUL                           /**< Mode LOC11 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_RTSLOC_LOC12           0x0000000CUL                           /**< Mode LOC12 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_RTSLOC_LOC13           0x0000000DUL                           /**< Mode LOC13 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_RTSLOC_LOC14           0x0000000EUL                           /**< Mode LOC14 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_RTSLOC_LOC15           0x0000000FUL                           /**< Mode LOC15 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_RTSLOC_LOC16           0x00000010UL                           /**< Mode LOC16 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_RTSLOC_LOC17           0x00000011UL                           /**< Mode LOC17 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_RTSLOC_LOC18           0x00000012UL                           /**< Mode LOC18 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_RTSLOC_LOC19           0x00000013UL                           /**< Mode LOC19 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_RTSLOC_LOC20           0x00000014UL                           /**< Mode LOC20 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_RTSLOC_LOC21           0x00000015UL                           /**< Mode LOC21 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_RTSLOC_LOC22           0x00000016UL                           /**< Mode LOC22 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_RTSLOC_LOC23           0x00000017UL                           /**< Mode LOC23 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_RTSLOC_LOC24           0x00000018UL                           /**< Mode LOC24 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_RTSLOC_LOC25           0x00000019UL                           /**< Mode LOC25 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_RTSLOC_LOC26           0x0000001AUL                           /**< Mode LOC26 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_RTSLOC_LOC27           0x0000001BUL                           /**< Mode LOC27 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_RTSLOC_LOC28           0x0000001CUL                           /**< Mode LOC28 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_RTSLOC_LOC29           0x0000001DUL                           /**< Mode LOC29 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_RTSLOC_LOC30           0x0000001EUL                           /**< Mode LOC30 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_RTSLOC_LOC31           0x0000001FUL                           /**< Mode LOC31 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_RTSLOC_LOC0             (_USART_ROUTELOC1_RTSLOC_LOC0 << 8)    /**< Shifted mode LOC0 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_RTSLOC_DEFAULT          (_USART_ROUTELOC1_RTSLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_RTSLOC_LOC1             (_USART_ROUTELOC1_RTSLOC_LOC1 << 8)    /**< Shifted mode LOC1 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_RTSLOC_LOC2             (_USART_ROUTELOC1_RTSLOC_LOC2 << 8)    /**< Shifted mode LOC2 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_RTSLOC_LOC3             (_USART_ROUTELOC1_RTSLOC_LOC3 << 8)    /**< Shifted mode LOC3 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_RTSLOC_LOC4             (_USART_ROUTELOC1_RTSLOC_LOC4 << 8)    /**< Shifted mode LOC4 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_RTSLOC_LOC5             (_USART_ROUTELOC1_RTSLOC_LOC5 << 8)    /**< Shifted mode LOC5 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_RTSLOC_LOC6             (_USART_ROUTELOC1_RTSLOC_LOC6 << 8)    /**< Shifted mode LOC6 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_RTSLOC_LOC7             (_USART_ROUTELOC1_RTSLOC_LOC7 << 8)    /**< Shifted mode LOC7 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_RTSLOC_LOC8             (_USART_ROUTELOC1_RTSLOC_LOC8 << 8)    /**< Shifted mode LOC8 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_RTSLOC_LOC9             (_USART_ROUTELOC1_RTSLOC_LOC9 << 8)    /**< Shifted mode LOC9 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_RTSLOC_LOC10            (_USART_ROUTELOC1_RTSLOC_LOC10 << 8)   /**< Shifted mode LOC10 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_RTSLOC_LOC11            (_USART_ROUTELOC1_RTSLOC_LOC11 << 8)   /**< Shifted mode LOC11 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_RTSLOC_LOC12            (_USART_ROUTELOC1_RTSLOC_LOC12 << 8)   /**< Shifted mode LOC12 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_RTSLOC_LOC13            (_USART_ROUTELOC1_RTSLOC_LOC13 << 8)   /**< Shifted mode LOC13 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_RTSLOC_LOC14            (_USART_ROUTELOC1_RTSLOC_LOC14 << 8)   /**< Shifted mode LOC14 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_RTSLOC_LOC15            (_USART_ROUTELOC1_RTSLOC_LOC15 << 8)   /**< Shifted mode LOC15 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_RTSLOC_LOC16            (_USART_ROUTELOC1_RTSLOC_LOC16 << 8)   /**< Shifted mode LOC16 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_RTSLOC_LOC17            (_USART_ROUTELOC1_RTSLOC_LOC17 << 8)   /**< Shifted mode LOC17 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_RTSLOC_LOC18            (_USART_ROUTELOC1_RTSLOC_LOC18 << 8)   /**< Shifted mode LOC18 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_RTSLOC_LOC19            (_USART_ROUTELOC1_RTSLOC_LOC19 << 8)   /**< Shifted mode LOC19 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_RTSLOC_LOC20            (_USART_ROUTELOC1_RTSLOC_LOC20 << 8)   /**< Shifted mode LOC20 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_RTSLOC_LOC21            (_USART_ROUTELOC1_RTSLOC_LOC21 << 8)   /**< Shifted mode LOC21 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_RTSLOC_LOC22            (_USART_ROUTELOC1_RTSLOC_LOC22 << 8)   /**< Shifted mode LOC22 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_RTSLOC_LOC23            (_USART_ROUTELOC1_RTSLOC_LOC23 << 8)   /**< Shifted mode LOC23 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_RTSLOC_LOC24            (_USART_ROUTELOC1_RTSLOC_LOC24 << 8)   /**< Shifted mode LOC24 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_RTSLOC_LOC25            (_USART_ROUTELOC1_RTSLOC_LOC25 << 8)   /**< Shifted mode LOC25 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_RTSLOC_LOC26            (_USART_ROUTELOC1_RTSLOC_LOC26 << 8)   /**< Shifted mode LOC26 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_RTSLOC_LOC27            (_USART_ROUTELOC1_RTSLOC_LOC27 << 8)   /**< Shifted mode LOC27 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_RTSLOC_LOC28            (_USART_ROUTELOC1_RTSLOC_LOC28 << 8)   /**< Shifted mode LOC28 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_RTSLOC_LOC29            (_USART_ROUTELOC1_RTSLOC_LOC29 << 8)   /**< Shifted mode LOC29 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_RTSLOC_LOC30            (_USART_ROUTELOC1_RTSLOC_LOC30 << 8)   /**< Shifted mode LOC30 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_RTSLOC_LOC31            (_USART_ROUTELOC1_RTSLOC_LOC31 << 8)   /**< Shifted mode LOC31 for USART_ROUTELOC1 */
+
+/** @} End of group EFM32PG1B_USART */
+/** @} End of group Parts */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG_STK3401/efm32pg1b_wdog.h	Fri Jan 15 07:45:16 2016 +0000
@@ -0,0 +1,333 @@
+/**************************************************************************//**
+ * @file efm32pg1b_wdog.h
+ * @brief EFM32PG1B_WDOG register and bit field definitions
+ * @version 4.2.0
+ ******************************************************************************
+ * @section License
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ ******************************************************************************
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software.@n
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.@n
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is
+ * providing the Software "AS IS", with no express or implied warranties of any
+ * kind, including, but not limited to, any implied warranties of
+ * merchantability or fitness for any particular purpose or warranties against
+ * infringement of any proprietary rights of a third party.
+ *
+ * Silicon Laboratories, Inc. will not be liable for any consequential,
+ * incidental, or special damages, or any other relief, or for any claim by
+ * any third party, arising from your use of this Software.
+ *
+ *****************************************************************************/
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFM32PG1B_WDOG
+ * @{
+ * @brief EFM32PG1B_WDOG Register Declaration
+ *****************************************************************************/
+typedef struct
+{
+  __IO uint32_t    CTRL;         /**< Control Register  */
+  __IO uint32_t    CMD;          /**< Command Register  */
+
+  __I uint32_t     SYNCBUSY;     /**< Synchronization Busy Register  */
+
+  WDOG_PCH_TypeDef PCH[2];       /**< PCH */
+
+  uint32_t         RESERVED0[2]; /**< Reserved for future use **/
+  __I uint32_t     IF;           /**< Watchdog Interrupt Flags  */
+  __IO uint32_t    IFS;          /**< Interrupt Flag Set Register  */
+  __IO uint32_t    IFC;          /**< Interrupt Flag Clear Register  */
+  __IO uint32_t    IEN;          /**< Interrupt Enable Register  */
+} WDOG_TypeDef;                  /** @} */
+
+/**************************************************************************//**
+ * @defgroup EFM32PG1B_WDOG_BitFields
+ * @{
+ *****************************************************************************/
+
+/* Bit fields for WDOG CTRL */
+#define _WDOG_CTRL_RESETVALUE                     0x00000F00UL                          /**< Default value for WDOG_CTRL */
+#define _WDOG_CTRL_MASK                           0xC7033F7FUL                          /**< Mask for WDOG_CTRL */
+#define WDOG_CTRL_EN                              (0x1UL << 0)                          /**< Watchdog Timer Enable */
+#define _WDOG_CTRL_EN_SHIFT                       0                                     /**< Shift value for WDOG_EN */
+#define _WDOG_CTRL_EN_MASK                        0x1UL                                 /**< Bit mask for WDOG_EN */
+#define _WDOG_CTRL_EN_DEFAULT                     0x00000000UL                          /**< Mode DEFAULT for WDOG_CTRL */
+#define WDOG_CTRL_EN_DEFAULT                      (_WDOG_CTRL_EN_DEFAULT << 0)          /**< Shifted mode DEFAULT for WDOG_CTRL */
+#define WDOG_CTRL_DEBUGRUN                        (0x1UL << 1)                          /**< Debug Mode Run Enable */
+#define _WDOG_CTRL_DEBUGRUN_SHIFT                 1                                     /**< Shift value for WDOG_DEBUGRUN */
+#define _WDOG_CTRL_DEBUGRUN_MASK                  0x2UL                                 /**< Bit mask for WDOG_DEBUGRUN */
+#define _WDOG_CTRL_DEBUGRUN_DEFAULT               0x00000000UL                          /**< Mode DEFAULT for WDOG_CTRL */
+#define WDOG_CTRL_DEBUGRUN_DEFAULT                (_WDOG_CTRL_DEBUGRUN_DEFAULT << 1)    /**< Shifted mode DEFAULT for WDOG_CTRL */
+#define WDOG_CTRL_EM2RUN                          (0x1UL << 2)                          /**< Energy Mode 2 Run Enable */
+#define _WDOG_CTRL_EM2RUN_SHIFT                   2                                     /**< Shift value for WDOG_EM2RUN */
+#define _WDOG_CTRL_EM2RUN_MASK                    0x4UL                                 /**< Bit mask for WDOG_EM2RUN */
+#define _WDOG_CTRL_EM2RUN_DEFAULT                 0x00000000UL                          /**< Mode DEFAULT for WDOG_CTRL */
+#define WDOG_CTRL_EM2RUN_DEFAULT                  (_WDOG_CTRL_EM2RUN_DEFAULT << 2)      /**< Shifted mode DEFAULT for WDOG_CTRL */
+#define WDOG_CTRL_EM3RUN                          (0x1UL << 3)                          /**< Energy Mode 3 Run Enable */
+#define _WDOG_CTRL_EM3RUN_SHIFT                   3                                     /**< Shift value for WDOG_EM3RUN */
+#define _WDOG_CTRL_EM3RUN_MASK                    0x8UL                                 /**< Bit mask for WDOG_EM3RUN */
+#define _WDOG_CTRL_EM3RUN_DEFAULT                 0x00000000UL                          /**< Mode DEFAULT for WDOG_CTRL */
+#define WDOG_CTRL_EM3RUN_DEFAULT                  (_WDOG_CTRL_EM3RUN_DEFAULT << 3)      /**< Shifted mode DEFAULT for WDOG_CTRL */
+#define WDOG_CTRL_LOCK                            (0x1UL << 4)                          /**< Configuration lock */
+#define _WDOG_CTRL_LOCK_SHIFT                     4                                     /**< Shift value for WDOG_LOCK */
+#define _WDOG_CTRL_LOCK_MASK                      0x10UL                                /**< Bit mask for WDOG_LOCK */
+#define _WDOG_CTRL_LOCK_DEFAULT                   0x00000000UL                          /**< Mode DEFAULT for WDOG_CTRL */
+#define WDOG_CTRL_LOCK_DEFAULT                    (_WDOG_CTRL_LOCK_DEFAULT << 4)        /**< Shifted mode DEFAULT for WDOG_CTRL */
+#define WDOG_CTRL_EM4BLOCK                        (0x1UL << 5)                          /**< Energy Mode 4 Block */
+#define _WDOG_CTRL_EM4BLOCK_SHIFT                 5                                     /**< Shift value for WDOG_EM4BLOCK */
+#define _WDOG_CTRL_EM4BLOCK_MASK                  0x20UL                                /**< Bit mask for WDOG_EM4BLOCK */
+#define _WDOG_CTRL_EM4BLOCK_DEFAULT               0x00000000UL                          /**< Mode DEFAULT for WDOG_CTRL */
+#define WDOG_CTRL_EM4BLOCK_DEFAULT                (_WDOG_CTRL_EM4BLOCK_DEFAULT << 5)    /**< Shifted mode DEFAULT for WDOG_CTRL */
+#define WDOG_CTRL_SWOSCBLOCK                      (0x1UL << 6)                          /**< Software Oscillator Disable Block */
+#define _WDOG_CTRL_SWOSCBLOCK_SHIFT               6                                     /**< Shift value for WDOG_SWOSCBLOCK */
+#define _WDOG_CTRL_SWOSCBLOCK_MASK                0x40UL                                /**< Bit mask for WDOG_SWOSCBLOCK */
+#define _WDOG_CTRL_SWOSCBLOCK_DEFAULT             0x00000000UL                          /**< Mode DEFAULT for WDOG_CTRL */
+#define WDOG_CTRL_SWOSCBLOCK_DEFAULT              (_WDOG_CTRL_SWOSCBLOCK_DEFAULT << 6)  /**< Shifted mode DEFAULT for WDOG_CTRL */
+#define _WDOG_CTRL_PERSEL_SHIFT                   8                                     /**< Shift value for WDOG_PERSEL */
+#define _WDOG_CTRL_PERSEL_MASK                    0xF00UL                               /**< Bit mask for WDOG_PERSEL */
+#define _WDOG_CTRL_PERSEL_DEFAULT                 0x0000000FUL                          /**< Mode DEFAULT for WDOG_CTRL */
+#define WDOG_CTRL_PERSEL_DEFAULT                  (_WDOG_CTRL_PERSEL_DEFAULT << 8)      /**< Shifted mode DEFAULT for WDOG_CTRL */
+#define _WDOG_CTRL_CLKSEL_SHIFT                   12                                    /**< Shift value for WDOG_CLKSEL */
+#define _WDOG_CTRL_CLKSEL_MASK                    0x3000UL                              /**< Bit mask for WDOG_CLKSEL */
+#define _WDOG_CTRL_CLKSEL_DEFAULT                 0x00000000UL                          /**< Mode DEFAULT for WDOG_CTRL */
+#define _WDOG_CTRL_CLKSEL_ULFRCO                  0x00000000UL                          /**< Mode ULFRCO for WDOG_CTRL */
+#define _WDOG_CTRL_CLKSEL_LFRCO                   0x00000001UL                          /**< Mode LFRCO for WDOG_CTRL */
+#define _WDOG_CTRL_CLKSEL_LFXO                    0x00000002UL                          /**< Mode LFXO for WDOG_CTRL */
+#define WDOG_CTRL_CLKSEL_DEFAULT                  (_WDOG_CTRL_CLKSEL_DEFAULT << 12)     /**< Shifted mode DEFAULT for WDOG_CTRL */
+#define WDOG_CTRL_CLKSEL_ULFRCO                   (_WDOG_CTRL_CLKSEL_ULFRCO << 12)      /**< Shifted mode ULFRCO for WDOG_CTRL */
+#define WDOG_CTRL_CLKSEL_LFRCO                    (_WDOG_CTRL_CLKSEL_LFRCO << 12)       /**< Shifted mode LFRCO for WDOG_CTRL */
+#define WDOG_CTRL_CLKSEL_LFXO                     (_WDOG_CTRL_CLKSEL_LFXO << 12)        /**< Shifted mode LFXO for WDOG_CTRL */
+#define _WDOG_CTRL_WARNSEL_SHIFT                  16                                    /**< Shift value for WDOG_WARNSEL */
+#define _WDOG_CTRL_WARNSEL_MASK                   0x30000UL                             /**< Bit mask for WDOG_WARNSEL */
+#define _WDOG_CTRL_WARNSEL_DEFAULT                0x00000000UL                          /**< Mode DEFAULT for WDOG_CTRL */
+#define WDOG_CTRL_WARNSEL_DEFAULT                 (_WDOG_CTRL_WARNSEL_DEFAULT << 16)    /**< Shifted mode DEFAULT for WDOG_CTRL */
+#define _WDOG_CTRL_WINSEL_SHIFT                   24                                    /**< Shift value for WDOG_WINSEL */
+#define _WDOG_CTRL_WINSEL_MASK                    0x7000000UL                           /**< Bit mask for WDOG_WINSEL */
+#define _WDOG_CTRL_WINSEL_DEFAULT                 0x00000000UL                          /**< Mode DEFAULT for WDOG_CTRL */
+#define WDOG_CTRL_WINSEL_DEFAULT                  (_WDOG_CTRL_WINSEL_DEFAULT << 24)     /**< Shifted mode DEFAULT for WDOG_CTRL */
+#define WDOG_CTRL_CLRSRC                          (0x1UL << 30)                         /**< Watchdog Clear Source */
+#define _WDOG_CTRL_CLRSRC_SHIFT                   30                                    /**< Shift value for WDOG_CLRSRC */
+#define _WDOG_CTRL_CLRSRC_MASK                    0x40000000UL                          /**< Bit mask for WDOG_CLRSRC */
+#define _WDOG_CTRL_CLRSRC_DEFAULT                 0x00000000UL                          /**< Mode DEFAULT for WDOG_CTRL */
+#define _WDOG_CTRL_CLRSRC_SW                      0x00000000UL                          /**< Mode SW for WDOG_CTRL */
+#define _WDOG_CTRL_CLRSRC_PCH0                    0x00000001UL                          /**< Mode PCH0 for WDOG_CTRL */
+#define WDOG_CTRL_CLRSRC_DEFAULT                  (_WDOG_CTRL_CLRSRC_DEFAULT << 30)     /**< Shifted mode DEFAULT for WDOG_CTRL */
+#define WDOG_CTRL_CLRSRC_SW                       (_WDOG_CTRL_CLRSRC_SW << 30)          /**< Shifted mode SW for WDOG_CTRL */
+#define WDOG_CTRL_CLRSRC_PCH0                     (_WDOG_CTRL_CLRSRC_PCH0 << 30)        /**< Shifted mode PCH0 for WDOG_CTRL */
+#define WDOG_CTRL_WDOGRSTDIS                      (0x1UL << 31)                         /**< Watchdog Reset Disable */
+#define _WDOG_CTRL_WDOGRSTDIS_SHIFT               31                                    /**< Shift value for WDOG_WDOGRSTDIS */
+#define _WDOG_CTRL_WDOGRSTDIS_MASK                0x80000000UL                          /**< Bit mask for WDOG_WDOGRSTDIS */
+#define _WDOG_CTRL_WDOGRSTDIS_DEFAULT             0x00000000UL                          /**< Mode DEFAULT for WDOG_CTRL */
+#define _WDOG_CTRL_WDOGRSTDIS_EN                  0x00000000UL                          /**< Mode EN for WDOG_CTRL */
+#define _WDOG_CTRL_WDOGRSTDIS_DIS                 0x00000001UL                          /**< Mode DIS for WDOG_CTRL */
+#define WDOG_CTRL_WDOGRSTDIS_DEFAULT              (_WDOG_CTRL_WDOGRSTDIS_DEFAULT << 31) /**< Shifted mode DEFAULT for WDOG_CTRL */
+#define WDOG_CTRL_WDOGRSTDIS_EN                   (_WDOG_CTRL_WDOGRSTDIS_EN << 31)      /**< Shifted mode EN for WDOG_CTRL */
+#define WDOG_CTRL_WDOGRSTDIS_DIS                  (_WDOG_CTRL_WDOGRSTDIS_DIS << 31)     /**< Shifted mode DIS for WDOG_CTRL */
+
+/* Bit fields for WDOG CMD */
+#define _WDOG_CMD_RESETVALUE                      0x00000000UL                     /**< Default value for WDOG_CMD */
+#define _WDOG_CMD_MASK                            0x00000001UL                     /**< Mask for WDOG_CMD */
+#define WDOG_CMD_CLEAR                            (0x1UL << 0)                     /**< Watchdog Timer Clear */
+#define _WDOG_CMD_CLEAR_SHIFT                     0                                /**< Shift value for WDOG_CLEAR */
+#define _WDOG_CMD_CLEAR_MASK                      0x1UL                            /**< Bit mask for WDOG_CLEAR */
+#define _WDOG_CMD_CLEAR_DEFAULT                   0x00000000UL                     /**< Mode DEFAULT for WDOG_CMD */
+#define _WDOG_CMD_CLEAR_UNCHANGED                 0x00000000UL                     /**< Mode UNCHANGED for WDOG_CMD */
+#define _WDOG_CMD_CLEAR_CLEARED                   0x00000001UL                     /**< Mode CLEARED for WDOG_CMD */
+#define WDOG_CMD_CLEAR_DEFAULT                    (_WDOG_CMD_CLEAR_DEFAULT << 0)   /**< Shifted mode DEFAULT for WDOG_CMD */
+#define WDOG_CMD_CLEAR_UNCHANGED                  (_WDOG_CMD_CLEAR_UNCHANGED << 0) /**< Shifted mode UNCHANGED for WDOG_CMD */
+#define WDOG_CMD_CLEAR_CLEARED                    (_WDOG_CMD_CLEAR_CLEARED << 0)   /**< Shifted mode CLEARED for WDOG_CMD */
+
+/* Bit fields for WDOG SYNCBUSY */
+#define _WDOG_SYNCBUSY_RESETVALUE                 0x00000000UL                               /**< Default value for WDOG_SYNCBUSY */
+#define _WDOG_SYNCBUSY_MASK                       0x0000000FUL                               /**< Mask for WDOG_SYNCBUSY */
+#define WDOG_SYNCBUSY_CTRL                        (0x1UL << 0)                               /**< CTRL Register Busy */
+#define _WDOG_SYNCBUSY_CTRL_SHIFT                 0                                          /**< Shift value for WDOG_CTRL */
+#define _WDOG_SYNCBUSY_CTRL_MASK                  0x1UL                                      /**< Bit mask for WDOG_CTRL */
+#define _WDOG_SYNCBUSY_CTRL_DEFAULT               0x00000000UL                               /**< Mode DEFAULT for WDOG_SYNCBUSY */
+#define WDOG_SYNCBUSY_CTRL_DEFAULT                (_WDOG_SYNCBUSY_CTRL_DEFAULT << 0)         /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */
+#define WDOG_SYNCBUSY_CMD                         (0x1UL << 1)                               /**< CMD Register Busy */
+#define _WDOG_SYNCBUSY_CMD_SHIFT                  1                                          /**< Shift value for WDOG_CMD */
+#define _WDOG_SYNCBUSY_CMD_MASK                   0x2UL                                      /**< Bit mask for WDOG_CMD */
+#define _WDOG_SYNCBUSY_CMD_DEFAULT                0x00000000UL                               /**< Mode DEFAULT for WDOG_SYNCBUSY */
+#define WDOG_SYNCBUSY_CMD_DEFAULT                 (_WDOG_SYNCBUSY_CMD_DEFAULT << 1)          /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */
+#define WDOG_SYNCBUSY_PCH0_PRSCTRL                (0x1UL << 2)                               /**< PCH0_PRSCTRL Register Busy */
+#define _WDOG_SYNCBUSY_PCH0_PRSCTRL_SHIFT         2                                          /**< Shift value for WDOG_PCH0_PRSCTRL */
+#define _WDOG_SYNCBUSY_PCH0_PRSCTRL_MASK          0x4UL                                      /**< Bit mask for WDOG_PCH0_PRSCTRL */
+#define _WDOG_SYNCBUSY_PCH0_PRSCTRL_DEFAULT       0x00000000UL                               /**< Mode DEFAULT for WDOG_SYNCBUSY */
+#define WDOG_SYNCBUSY_PCH0_PRSCTRL_DEFAULT        (_WDOG_SYNCBUSY_PCH0_PRSCTRL_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */
+#define WDOG_SYNCBUSY_PCH1_PRSCTRL                (0x1UL << 3)                               /**< PCH1_PRSCTRL Register Busy */
+#define _WDOG_SYNCBUSY_PCH1_PRSCTRL_SHIFT         3                                          /**< Shift value for WDOG_PCH1_PRSCTRL */
+#define _WDOG_SYNCBUSY_PCH1_PRSCTRL_MASK          0x8UL                                      /**< Bit mask for WDOG_PCH1_PRSCTRL */
+#define _WDOG_SYNCBUSY_PCH1_PRSCTRL_DEFAULT       0x00000000UL                               /**< Mode DEFAULT for WDOG_SYNCBUSY */
+#define WDOG_SYNCBUSY_PCH1_PRSCTRL_DEFAULT        (_WDOG_SYNCBUSY_PCH1_PRSCTRL_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */
+
+/* Bit fields for WDOG PCH_PRSCTRL */
+#define _WDOG_PCH_PRSCTRL_RESETVALUE              0x00000000UL                                  /**< Default value for WDOG_PCH_PRSCTRL */
+#define _WDOG_PCH_PRSCTRL_MASK                    0x0000010FUL                                  /**< Mask for WDOG_PCH_PRSCTRL */
+#define _WDOG_PCH_PRSCTRL_PRSSEL_SHIFT            0                                             /**< Shift value for WDOG_PRSSEL */
+#define _WDOG_PCH_PRSCTRL_PRSSEL_MASK             0xFUL                                         /**< Bit mask for WDOG_PRSSEL */
+#define _WDOG_PCH_PRSCTRL_PRSSEL_DEFAULT          0x00000000UL                                  /**< Mode DEFAULT for WDOG_PCH_PRSCTRL */
+#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH0           0x00000000UL                                  /**< Mode PRSCH0 for WDOG_PCH_PRSCTRL */
+#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH1           0x00000001UL                                  /**< Mode PRSCH1 for WDOG_PCH_PRSCTRL */
+#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH2           0x00000002UL                                  /**< Mode PRSCH2 for WDOG_PCH_PRSCTRL */
+#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH3           0x00000003UL                                  /**< Mode PRSCH3 for WDOG_PCH_PRSCTRL */
+#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH4           0x00000004UL                                  /**< Mode PRSCH4 for WDOG_PCH_PRSCTRL */
+#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH5           0x00000005UL                                  /**< Mode PRSCH5 for WDOG_PCH_PRSCTRL */
+#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH6           0x00000006UL                                  /**< Mode PRSCH6 for WDOG_PCH_PRSCTRL */
+#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH7           0x00000007UL                                  /**< Mode PRSCH7 for WDOG_PCH_PRSCTRL */
+#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH8           0x00000008UL                                  /**< Mode PRSCH8 for WDOG_PCH_PRSCTRL */
+#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH9           0x00000009UL                                  /**< Mode PRSCH9 for WDOG_PCH_PRSCTRL */
+#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH10          0x0000000AUL                                  /**< Mode PRSCH10 for WDOG_PCH_PRSCTRL */
+#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH11          0x0000000BUL                                  /**< Mode PRSCH11 for WDOG_PCH_PRSCTRL */
+#define WDOG_PCH_PRSCTRL_PRSSEL_DEFAULT           (_WDOG_PCH_PRSCTRL_PRSSEL_DEFAULT << 0)       /**< Shifted mode DEFAULT for WDOG_PCH_PRSCTRL */
+#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH0            (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH0 << 0)        /**< Shifted mode PRSCH0 for WDOG_PCH_PRSCTRL */
+#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH1            (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH1 << 0)        /**< Shifted mode PRSCH1 for WDOG_PCH_PRSCTRL */
+#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH2            (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH2 << 0)        /**< Shifted mode PRSCH2 for WDOG_PCH_PRSCTRL */
+#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH3            (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH3 << 0)        /**< Shifted mode PRSCH3 for WDOG_PCH_PRSCTRL */
+#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH4            (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH4 << 0)        /**< Shifted mode PRSCH4 for WDOG_PCH_PRSCTRL */
+#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH5            (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH5 << 0)        /**< Shifted mode PRSCH5 for WDOG_PCH_PRSCTRL */
+#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH6            (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH6 << 0)        /**< Shifted mode PRSCH6 for WDOG_PCH_PRSCTRL */
+#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH7            (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH7 << 0)        /**< Shifted mode PRSCH7 for WDOG_PCH_PRSCTRL */
+#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH8            (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH8 << 0)        /**< Shifted mode PRSCH8 for WDOG_PCH_PRSCTRL */
+#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH9            (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH9 << 0)        /**< Shifted mode PRSCH9 for WDOG_PCH_PRSCTRL */
+#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH10           (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH10 << 0)       /**< Shifted mode PRSCH10 for WDOG_PCH_PRSCTRL */
+#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH11           (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH11 << 0)       /**< Shifted mode PRSCH11 for WDOG_PCH_PRSCTRL */
+#define WDOG_PCH_PRSCTRL_PRSMISSRSTEN             (0x1UL << 8)                                  /**< PRS missing event will trigger a watchdog reset */
+#define _WDOG_PCH_PRSCTRL_PRSMISSRSTEN_SHIFT      8                                             /**< Shift value for WDOG_PRSMISSRSTEN */
+#define _WDOG_PCH_PRSCTRL_PRSMISSRSTEN_MASK       0x100UL                                       /**< Bit mask for WDOG_PRSMISSRSTEN */
+#define _WDOG_PCH_PRSCTRL_PRSMISSRSTEN_DEFAULT    0x00000000UL                                  /**< Mode DEFAULT for WDOG_PCH_PRSCTRL */
+#define WDOG_PCH_PRSCTRL_PRSMISSRSTEN_DEFAULT     (_WDOG_PCH_PRSCTRL_PRSMISSRSTEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WDOG_PCH_PRSCTRL */
+
+/* Bit fields for WDOG IF */
+#define _WDOG_IF_RESETVALUE                       0x00000000UL                 /**< Default value for WDOG_IF */
+#define _WDOG_IF_MASK                             0x0000001FUL                 /**< Mask for WDOG_IF */
+#define WDOG_IF_TOUT                              (0x1UL << 0)                 /**< Wdog Timeout Interrupt Flag */
+#define _WDOG_IF_TOUT_SHIFT                       0                            /**< Shift value for WDOG_TOUT */
+#define _WDOG_IF_TOUT_MASK                        0x1UL                        /**< Bit mask for WDOG_TOUT */
+#define _WDOG_IF_TOUT_DEFAULT                     0x00000000UL                 /**< Mode DEFAULT for WDOG_IF */
+#define WDOG_IF_TOUT_DEFAULT                      (_WDOG_IF_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IF */
+#define WDOG_IF_WARN                              (0x1UL << 1)                 /**< Wdog Warning Timeout Interrupt Flag */
+#define _WDOG_IF_WARN_SHIFT                       1                            /**< Shift value for WDOG_WARN */
+#define _WDOG_IF_WARN_MASK                        0x2UL                        /**< Bit mask for WDOG_WARN */
+#define _WDOG_IF_WARN_DEFAULT                     0x00000000UL                 /**< Mode DEFAULT for WDOG_IF */
+#define WDOG_IF_WARN_DEFAULT                      (_WDOG_IF_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IF */
+#define WDOG_IF_WIN                               (0x1UL << 2)                 /**< Wdog Window Interrupt Flag */
+#define _WDOG_IF_WIN_SHIFT                        2                            /**< Shift value for WDOG_WIN */
+#define _WDOG_IF_WIN_MASK                         0x4UL                        /**< Bit mask for WDOG_WIN */
+#define _WDOG_IF_WIN_DEFAULT                      0x00000000UL                 /**< Mode DEFAULT for WDOG_IF */
+#define WDOG_IF_WIN_DEFAULT                       (_WDOG_IF_WIN_DEFAULT << 2)  /**< Shifted mode DEFAULT for WDOG_IF */
+#define WDOG_IF_PEM0                              (0x1UL << 3)                 /**< PRS Channel Zero Event Missing Interrupt Flag */
+#define _WDOG_IF_PEM0_SHIFT                       3                            /**< Shift value for WDOG_PEM0 */
+#define _WDOG_IF_PEM0_MASK                        0x8UL                        /**< Bit mask for WDOG_PEM0 */
+#define _WDOG_IF_PEM0_DEFAULT                     0x00000000UL                 /**< Mode DEFAULT for WDOG_IF */
+#define WDOG_IF_PEM0_DEFAULT                      (_WDOG_IF_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IF */
+#define WDOG_IF_PEM1                              (0x1UL << 4)                 /**< PRS Channel One Event Missing Interrupt Flag */
+#define _WDOG_IF_PEM1_SHIFT                       4                            /**< Shift value for WDOG_PEM1 */
+#define _WDOG_IF_PEM1_MASK                        0x10UL                       /**< Bit mask for WDOG_PEM1 */
+#define _WDOG_IF_PEM1_DEFAULT                     0x00000000UL                 /**< Mode DEFAULT for WDOG_IF */
+#define WDOG_IF_PEM1_DEFAULT                      (_WDOG_IF_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IF */
+
+/* Bit fields for WDOG IFS */
+#define _WDOG_IFS_RESETVALUE                      0x00000000UL                  /**< Default value for WDOG_IFS */
+#define _WDOG_IFS_MASK                            0x0000001FUL                  /**< Mask for WDOG_IFS */
+#define WDOG_IFS_TOUT                             (0x1UL << 0)                  /**< Set TOUT Interrupt Flag */
+#define _WDOG_IFS_TOUT_SHIFT                      0                             /**< Shift value for WDOG_TOUT */
+#define _WDOG_IFS_TOUT_MASK                       0x1UL                         /**< Bit mask for WDOG_TOUT */
+#define _WDOG_IFS_TOUT_DEFAULT                    0x00000000UL                  /**< Mode DEFAULT for WDOG_IFS */
+#define WDOG_IFS_TOUT_DEFAULT                     (_WDOG_IFS_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IFS */
+#define WDOG_IFS_WARN                             (0x1UL << 1)                  /**< Set WARN Interrupt Flag */
+#define _WDOG_IFS_WARN_SHIFT                      1                             /**< Shift value for WDOG_WARN */
+#define _WDOG_IFS_WARN_MASK                       0x2UL                         /**< Bit mask for WDOG_WARN */
+#define _WDOG_IFS_WARN_DEFAULT                    0x00000000UL                  /**< Mode DEFAULT for WDOG_IFS */
+#define WDOG_IFS_WARN_DEFAULT                     (_WDOG_IFS_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IFS */
+#define WDOG_IFS_WIN                              (0x1UL << 2)                  /**< Set WIN Interrupt Flag */
+#define _WDOG_IFS_WIN_SHIFT                       2                             /**< Shift value for WDOG_WIN */
+#define _WDOG_IFS_WIN_MASK                        0x4UL                         /**< Bit mask for WDOG_WIN */
+#define _WDOG_IFS_WIN_DEFAULT                     0x00000000UL                  /**< Mode DEFAULT for WDOG_IFS */
+#define WDOG_IFS_WIN_DEFAULT                      (_WDOG_IFS_WIN_DEFAULT << 2)  /**< Shifted mode DEFAULT for WDOG_IFS */
+#define WDOG_IFS_PEM0                             (0x1UL << 3)                  /**< Set PEM0 Interrupt Flag */
+#define _WDOG_IFS_PEM0_SHIFT                      3                             /**< Shift value for WDOG_PEM0 */
+#define _WDOG_IFS_PEM0_MASK                       0x8UL                         /**< Bit mask for WDOG_PEM0 */
+#define _WDOG_IFS_PEM0_DEFAULT                    0x00000000UL                  /**< Mode DEFAULT for WDOG_IFS */
+#define WDOG_IFS_PEM0_DEFAULT                     (_WDOG_IFS_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IFS */
+#define WDOG_IFS_PEM1                             (0x1UL << 4)                  /**< Set PEM1 Interrupt Flag */
+#define _WDOG_IFS_PEM1_SHIFT                      4                             /**< Shift value for WDOG_PEM1 */
+#define _WDOG_IFS_PEM1_MASK                       0x10UL                        /**< Bit mask for WDOG_PEM1 */
+#define _WDOG_IFS_PEM1_DEFAULT                    0x00000000UL                  /**< Mode DEFAULT for WDOG_IFS */
+#define WDOG_IFS_PEM1_DEFAULT                     (_WDOG_IFS_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IFS */
+
+/* Bit fields for WDOG IFC */
+#define _WDOG_IFC_RESETVALUE                      0x00000000UL                  /**< Default value for WDOG_IFC */
+#define _WDOG_IFC_MASK                            0x0000001FUL                  /**< Mask for WDOG_IFC */
+#define WDOG_IFC_TOUT                             (0x1UL << 0)                  /**< Clear TOUT Interrupt Flag */
+#define _WDOG_IFC_TOUT_SHIFT                      0                             /**< Shift value for WDOG_TOUT */
+#define _WDOG_IFC_TOUT_MASK                       0x1UL                         /**< Bit mask for WDOG_TOUT */
+#define _WDOG_IFC_TOUT_DEFAULT                    0x00000000UL                  /**< Mode DEFAULT for WDOG_IFC */
+#define WDOG_IFC_TOUT_DEFAULT                     (_WDOG_IFC_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IFC */
+#define WDOG_IFC_WARN                             (0x1UL << 1)                  /**< Clear WARN Interrupt Flag */
+#define _WDOG_IFC_WARN_SHIFT                      1                             /**< Shift value for WDOG_WARN */
+#define _WDOG_IFC_WARN_MASK                       0x2UL                         /**< Bit mask for WDOG_WARN */
+#define _WDOG_IFC_WARN_DEFAULT                    0x00000000UL                  /**< Mode DEFAULT for WDOG_IFC */
+#define WDOG_IFC_WARN_DEFAULT                     (_WDOG_IFC_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IFC */
+#define WDOG_IFC_WIN                              (0x1UL << 2)                  /**< Clear WIN Interrupt Flag */
+#define _WDOG_IFC_WIN_SHIFT                       2                             /**< Shift value for WDOG_WIN */
+#define _WDOG_IFC_WIN_MASK                        0x4UL                         /**< Bit mask for WDOG_WIN */
+#define _WDOG_IFC_WIN_DEFAULT                     0x00000000UL                  /**< Mode DEFAULT for WDOG_IFC */
+#define WDOG_IFC_WIN_DEFAULT                      (_WDOG_IFC_WIN_DEFAULT << 2)  /**< Shifted mode DEFAULT for WDOG_IFC */
+#define WDOG_IFC_PEM0                             (0x1UL << 3)                  /**< Clear PEM0 Interrupt Flag */
+#define _WDOG_IFC_PEM0_SHIFT                      3                             /**< Shift value for WDOG_PEM0 */
+#define _WDOG_IFC_PEM0_MASK                       0x8UL                         /**< Bit mask for WDOG_PEM0 */
+#define _WDOG_IFC_PEM0_DEFAULT                    0x00000000UL                  /**< Mode DEFAULT for WDOG_IFC */
+#define WDOG_IFC_PEM0_DEFAULT                     (_WDOG_IFC_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IFC */
+#define WDOG_IFC_PEM1                             (0x1UL << 4)                  /**< Clear PEM1 Interrupt Flag */
+#define _WDOG_IFC_PEM1_SHIFT                      4                             /**< Shift value for WDOG_PEM1 */
+#define _WDOG_IFC_PEM1_MASK                       0x10UL                        /**< Bit mask for WDOG_PEM1 */
+#define _WDOG_IFC_PEM1_DEFAULT                    0x00000000UL                  /**< Mode DEFAULT for WDOG_IFC */
+#define WDOG_IFC_PEM1_DEFAULT                     (_WDOG_IFC_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IFC */
+
+/* Bit fields for WDOG IEN */
+#define _WDOG_IEN_RESETVALUE                      0x00000000UL                  /**< Default value for WDOG_IEN */
+#define _WDOG_IEN_MASK                            0x0000001FUL                  /**< Mask for WDOG_IEN */
+#define WDOG_IEN_TOUT                             (0x1UL << 0)                  /**< TOUT Interrupt Enable */
+#define _WDOG_IEN_TOUT_SHIFT                      0                             /**< Shift value for WDOG_TOUT */
+#define _WDOG_IEN_TOUT_MASK                       0x1UL                         /**< Bit mask for WDOG_TOUT */
+#define _WDOG_IEN_TOUT_DEFAULT                    0x00000000UL                  /**< Mode DEFAULT for WDOG_IEN */
+#define WDOG_IEN_TOUT_DEFAULT                     (_WDOG_IEN_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IEN */
+#define WDOG_IEN_WARN                             (0x1UL << 1)                  /**< WARN Interrupt Enable */
+#define _WDOG_IEN_WARN_SHIFT                      1                             /**< Shift value for WDOG_WARN */
+#define _WDOG_IEN_WARN_MASK                       0x2UL                         /**< Bit mask for WDOG_WARN */
+#define _WDOG_IEN_WARN_DEFAULT                    0x00000000UL                  /**< Mode DEFAULT for WDOG_IEN */
+#define WDOG_IEN_WARN_DEFAULT                     (_WDOG_IEN_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IEN */
+#define WDOG_IEN_WIN                              (0x1UL << 2)                  /**< WIN Interrupt Enable */
+#define _WDOG_IEN_WIN_SHIFT                       2                             /**< Shift value for WDOG_WIN */
+#define _WDOG_IEN_WIN_MASK                        0x4UL                         /**< Bit mask for WDOG_WIN */
+#define _WDOG_IEN_WIN_DEFAULT                     0x00000000UL                  /**< Mode DEFAULT for WDOG_IEN */
+#define WDOG_IEN_WIN_DEFAULT                      (_WDOG_IEN_WIN_DEFAULT << 2)  /**< Shifted mode DEFAULT for WDOG_IEN */
+#define WDOG_IEN_PEM0                             (0x1UL << 3)                  /**< PEM0 Interrupt Enable */
+#define _WDOG_IEN_PEM0_SHIFT                      3                             /**< Shift value for WDOG_PEM0 */
+#define _WDOG_IEN_PEM0_MASK                       0x8UL                         /**< Bit mask for WDOG_PEM0 */
+#define _WDOG_IEN_PEM0_DEFAULT                    0x00000000UL                  /**< Mode DEFAULT for WDOG_IEN */
+#define WDOG_IEN_PEM0_DEFAULT                     (_WDOG_IEN_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IEN */
+#define WDOG_IEN_PEM1                             (0x1UL << 4)                  /**< PEM1 Interrupt Enable */
+#define _WDOG_IEN_PEM1_SHIFT                      4                             /**< Shift value for WDOG_PEM1 */
+#define _WDOG_IEN_PEM1_MASK                       0x10UL                        /**< Bit mask for WDOG_PEM1 */
+#define _WDOG_IEN_PEM1_DEFAULT                    0x00000000UL                  /**< Mode DEFAULT for WDOG_IEN */
+#define WDOG_IEN_PEM1_DEFAULT                     (_WDOG_IEN_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IEN */
+
+/** @} End of group EFM32PG1B_WDOG */
+/** @} End of group Parts */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG_STK3401/efm32pg1b_wdog_pch.h	Fri Jan 15 07:45:16 2016 +0000
@@ -0,0 +1,46 @@
+/**************************************************************************//**
+ * @file efm32pg1b_wdog_pch.h
+ * @brief EFM32PG1B_WDOG_PCH register and bit field definitions
+ * @version 4.2.0
+ ******************************************************************************
+ * @section License
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ ******************************************************************************
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software.@n
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.@n
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is
+ * providing the Software "AS IS", with no express or implied warranties of any
+ * kind, including, but not limited to, any implied warranties of
+ * merchantability or fitness for any particular purpose or warranties against
+ * infringement of any proprietary rights of a third party.
+ *
+ * Silicon Laboratories, Inc. will not be liable for any consequential,
+ * incidental, or special damages, or any other relief, or for any claim by
+ * any third party, arising from your use of this Software.
+ *
+ *****************************************************************************/
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @brief WDOG_PCH EFM32PG1B WDOG PCH
+ *****************************************************************************/
+typedef struct
+{
+  __IO uint32_t PRSCTRL; /**< PRS Control Register  */
+} WDOG_PCH_TypeDef;
+
+/** @} End of group Parts */
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG_STK3401/em_device.h	Fri Jan 15 07:45:16 2016 +0000
@@ -0,0 +1,68 @@
+/**************************************************************************//**
+ * @file em_device.h
+ * @brief CMSIS Cortex-M Peripheral Access Layer for Silicon Laboratories
+ *        microcontroller devices
+ *
+ * This is a convenience header file for defining the part number on the
+ * build command line, instead of specifying the part specific header file.
+ *
+ * @verbatim
+ * Example: Add "-DEFM32G890F128" to your build options, to define part
+ *          Add "#include "em_device.h" to your source files
+ *
+ *
+ * @endverbatim
+ * @version 4.2.0
+ ******************************************************************************
+ * @section License
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ ******************************************************************************
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software.@n
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.@n
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is
+ * providing the Software "AS IS", with no express or implied warranties of any
+ * kind, including, but not limited to, any implied warranties of
+ * merchantability or fitness for any particular purpose or warranties against
+ * infringement of any proprietary rights of a third party.
+ *
+ * Silicon Laboratories, Inc. will not be liable for any consequential,
+ * incidental, or special damages, or any other relief, or for any claim by
+ * any third party, arising from your use of this Software.
+ *
+ *****************************************************************************/
+
+#ifndef EM_DEVICE_H
+#define EM_DEVICE_H
+
+#if defined(EFM32PG1B100F128GM32)
+#include "efm32pg1b100f128gm32.h"
+
+#elif defined(EFM32PG1B100F256GM32)
+#include "efm32pg1b100f256gm32.h"
+
+#elif defined(EFM32PG1B200F128GM32)
+#include "efm32pg1b200f128gm32.h"
+
+#elif defined(EFM32PG1B200F128GM48)
+#include "efm32pg1b200f128gm48.h"
+
+#elif defined(EFM32PG1B200F256GM32)
+#include "efm32pg1b200f256gm32.h"
+
+#elif defined(EFM32PG1B200F256GM48)
+#include "efm32pg1b200f256gm48.h"
+
+#else
+#error "em_device.h: PART NUMBER undefined"
+#endif
+#endif /* EM_DEVICE_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG_STK3401/system_efm32pg1b.c	Fri Jan 15 07:45:16 2016 +0000
@@ -0,0 +1,383 @@
+/***************************************************************************//**
+ * @file system_efm32pg1b.c
+ * @brief CMSIS Cortex-M3/M4 System Layer for EFM32 devices.
+ * @version 4.2.0
+ ******************************************************************************
+ * @section License
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ ******************************************************************************
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software.@n
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.@n
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is
+ * providing the Software "AS IS", with no express or implied warranties of any
+ * kind, including, but not limited to, any implied warranties of
+ * merchantability or fitness for any particular purpose or warranties against
+ * infringement of any proprietary rights of a third party.
+ *
+ * Silicon Laboratories, Inc. will not be liable for any consequential,
+ * incidental, or special damages, or any other relief, or for any claim by
+ * any third party, arising from your use of this Software.
+ *
+ *****************************************************************************/
+
+#include <stdint.h>
+#include "em_device.h"
+
+/*******************************************************************************
+ ******************************   DEFINES   ************************************
+ ******************************************************************************/
+
+/** LFRCO frequency, tuned to below frequency during manufacturing. */
+#define EFM32_LFRCO_FREQ  (32768UL)
+#define EFM32_ULFRCO_FREQ (1000UL)
+
+/*******************************************************************************
+ **************************   LOCAL VARIABLES   ********************************
+ ******************************************************************************/
+
+/* System oscillator frequencies. These frequencies are normally constant */
+/* for a target, but they are made configurable in order to allow run-time */
+/* handling of different boards. The crystal oscillator clocks can be set */
+/* compile time to a non-default value by defining respective EFM_nFXO_FREQ */
+/* values according to board design. By defining the EFM_nFXO_FREQ to 0, */
+/* one indicates that the oscillator is not present, in order to save some */
+/* SW footprint. */
+
+#ifndef EFM32_HFRCO_MAX_FREQ
+#define EFM32_HFRCO_MAX_FREQ            (38000000UL)
+#endif
+
+#ifndef EFM32_HFXO_FREQ
+#define EFM32_HFXO_FREQ                 (40000000UL)
+#endif
+
+#ifndef EFM32_HFRCO_STARTUP_FREQ
+#define EFM32_HFRCO_STARTUP_FREQ        (19000000UL)
+#endif
+
+
+/* Do not define variable if HF crystal oscillator not present */
+#if (EFM32_HFXO_FREQ > 0UL)
+/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
+/** System HFXO clock. */
+static uint32_t SystemHFXOClock = EFM32_HFXO_FREQ;
+/** @endcond (DO_NOT_INCLUDE_WITH_DOXYGEN) */
+#endif
+
+#ifndef EFM32_LFXO_FREQ
+#define EFM32_LFXO_FREQ (EFM32_LFRCO_FREQ)
+#endif
+/* Do not define variable if LF crystal oscillator not present */
+#if (EFM32_LFXO_FREQ > 0UL)
+/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
+/** System LFXO clock. */
+static uint32_t SystemLFXOClock = 32768UL;
+/** @endcond (DO_NOT_INCLUDE_WITH_DOXYGEN) */
+#endif
+
+
+/*******************************************************************************
+ **************************   GLOBAL VARIABLES   *******************************
+ ******************************************************************************/
+
+/**
+ * @brief
+ *   System System Clock Frequency (Core Clock).
+ *
+ * @details
+ *   Required CMSIS global variable that must be kept up-to-date.
+ */
+uint32_t SystemCoreClock;
+
+
+/**
+ * @brief
+ *   System HFRCO frequency
+ *
+ * @note
+ *   This is an EFM32 proprietary variable, not part of the CMSIS definition.
+ *
+ * @details
+ *   Frequency of the system HFRCO oscillator
+ */
+uint32_t SystemHfrcoFreq = EFM32_HFRCO_STARTUP_FREQ;
+
+
+/*******************************************************************************
+ **************************   GLOBAL FUNCTIONS   *******************************
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * @brief
+ *   Get the current core clock frequency.
+ *
+ * @details
+ *   Calculate and get the current core clock frequency based on the current
+ *   configuration. Assuming that the SystemCoreClock global variable is
+ *   maintained, the core clock frequency is stored in that variable as well.
+ *   This function will however calculate the core clock based on actual HW
+ *   configuration. It will also update the SystemCoreClock global variable.
+ *
+ * @note
+ *   This is an EFM32 proprietary function, not part of the CMSIS definition.
+ *
+ * @return
+ *   The current core clock frequency in Hz.
+ ******************************************************************************/
+uint32_t SystemCoreClockGet(void)
+{
+  uint32_t ret;
+  uint32_t presc;
+
+  ret   = SystemHFClockGet();
+  presc = (CMU->HFCOREPRESC & _CMU_HFCOREPRESC_PRESC_MASK) >>
+          _CMU_HFCOREPRESC_PRESC_SHIFT;
+  ret  /= (presc + 1);
+
+  /* Keep CMSIS system clock variable up-to-date */
+  SystemCoreClock = ret;
+
+  return ret;
+}
+
+
+/***************************************************************************//**
+ * @brief
+ *   Get the maximum core clock frequency.
+ *
+ * @note
+ *   This is an EFM32 proprietary function, not part of the CMSIS definition.
+ *
+ * @return
+ *   The maximum core clock frequency in Hz.
+ ******************************************************************************/
+uint32_t SystemMaxCoreClockGet(void)
+{
+  return (EFM32_HFRCO_MAX_FREQ > EFM32_HFXO_FREQ ? \
+          EFM32_HFRCO_MAX_FREQ : EFM32_HFXO_FREQ);
+}
+
+
+/***************************************************************************//**
+ * @brief
+ *   Get the current HFCLK frequency.
+ *
+ * @note
+ *   This is an EFM32 proprietary function, not part of the CMSIS definition.
+ *
+ * @return
+ *   The current HFCLK frequency in Hz.
+ ******************************************************************************/
+uint32_t SystemHFClockGet(void)
+{
+  uint32_t ret;
+
+  switch (CMU->HFCLKSTATUS & _CMU_HFCLKSTATUS_SELECTED_MASK)
+  {
+    case CMU_HFCLKSTATUS_SELECTED_LFXO:
+#if (EFM32_LFXO_FREQ > 0)
+      ret = SystemLFXOClock;
+#else
+      /* We should not get here, since core should not be clocked. May */
+      /* be caused by a misconfiguration though. */
+      ret = 0;
+#endif
+      break;
+
+    case CMU_HFCLKSTATUS_SELECTED_LFRCO:
+      ret = EFM32_LFRCO_FREQ;
+      break;
+
+    case CMU_HFCLKSTATUS_SELECTED_HFXO:
+#if (EFM32_HFXO_FREQ > 0)
+      ret = SystemHFXOClock;
+#else
+      /* We should not get here, since core should not be clocked. May */
+      /* be caused by a misconfiguration though. */
+      ret = 0;
+#endif
+      break;
+
+    default: /* CMU_HFCLKSTATUS_SELECTED_HFRCO */
+      ret = SystemHfrcoFreq;
+      break;
+  }
+
+  return ret;
+}
+
+
+/**************************************************************************//**
+ * @brief
+ *   Get high frequency crystal oscillator clock frequency for target system.
+ *
+ * @note
+ *   This is an EFM32 proprietary function, not part of the CMSIS definition.
+ *
+ * @return
+ *   HFXO frequency in Hz.
+ *****************************************************************************/
+uint32_t SystemHFXOClockGet(void)
+{
+  /* External crystal oscillator present? */
+#if (EFM32_HFXO_FREQ > 0)
+  return SystemHFXOClock;
+#else
+  return 0;
+#endif
+}
+
+
+/**************************************************************************//**
+ * @brief
+ *   Set high frequency crystal oscillator clock frequency for target system.
+ *
+ * @note
+ *   This function is mainly provided for being able to handle target systems
+ *   with different HF crystal oscillator frequencies run-time. If used, it
+ *   should probably only be used once during system startup.
+ *
+ * @note
+ *   This is an EFM32 proprietary function, not part of the CMSIS definition.
+ *
+ * @param[in] freq
+ *   HFXO frequency in Hz used for target.
+ *****************************************************************************/
+void SystemHFXOClockSet(uint32_t freq)
+{
+  /* External crystal oscillator present? */
+#if (EFM32_HFXO_FREQ > 0)
+  SystemHFXOClock = freq;
+
+  /* Update core clock frequency if HFXO is used to clock core */
+  if ((CMU->HFCLKSTATUS & _CMU_HFCLKSTATUS_SELECTED_MASK) == CMU_HFCLKSTATUS_SELECTED_HFXO)
+  {
+    /* The function will update the global variable */
+    SystemCoreClockGet();
+  }
+#else
+  (void)freq; /* Unused parameter */
+#endif
+}
+
+
+/**************************************************************************//**
+ * @brief
+ *   Initialize the system.
+ *
+ * @details
+ *   Do required generic HW system init.
+ *
+ * @note
+ *   This function is invoked during system init, before the main() routine
+ *   and any data has been initialized. For this reason, it cannot do any
+ *   initialization of variables etc.
+ *****************************************************************************/
+void SystemInit(void)
+{
+#if (__FPU_PRESENT == 1)
+  /* Set floating point coprosessor access mode. */
+  SCB->CPACR |= ((3UL << 10 * 2) |      /* set CP10 Full Access */
+                 (3UL << 11 * 2));      /* set CP11 Full Access */
+#endif
+}
+
+
+/**************************************************************************//**
+ * @brief
+ *   Get low frequency RC oscillator clock frequency for target system.
+ *
+ * @note
+ *   This is an EFM32 proprietary function, not part of the CMSIS definition.
+ *
+ * @return
+ *   LFRCO frequency in Hz.
+ *****************************************************************************/
+uint32_t SystemLFRCOClockGet(void)
+{
+  /* Currently we assume that this frequency is properly tuned during */
+  /* manufacturing and is not changed after reset. If future requirements */
+  /* for re-tuning by user, we can add support for that. */
+  return EFM32_LFRCO_FREQ;
+}
+
+
+/**************************************************************************//**
+ * @brief
+ *   Get ultra low frequency RC oscillator clock frequency for target system.
+ *
+ * @note
+ *   This is an EFM32 proprietary function, not part of the CMSIS definition.
+ *
+ * @return
+ *   ULFRCO frequency in Hz.
+ *****************************************************************************/
+uint32_t SystemULFRCOClockGet(void)
+{
+  /* The ULFRCO frequency is not tuned, and can be very inaccurate */
+  return EFM32_ULFRCO_FREQ;
+}
+
+
+/**************************************************************************//**
+ * @brief
+ *   Get low frequency crystal oscillator clock frequency for target system.
+ *
+ * @note
+ *   This is an EFM32 proprietary function, not part of the CMSIS definition.
+ *
+ * @return
+ *   LFXO frequency in Hz.
+ *****************************************************************************/
+uint32_t SystemLFXOClockGet(void)
+{
+  /* External crystal oscillator present? */
+#if (EFM32_LFXO_FREQ > 0)
+  return SystemLFXOClock;
+#else
+  return 0;
+#endif
+}
+
+
+/**************************************************************************//**
+ * @brief
+ *   Set low frequency crystal oscillator clock frequency for target system.
+ *
+ * @note
+ *   This function is mainly provided for being able to handle target systems
+ *   with different HF crystal oscillator frequencies run-time. If used, it
+ *   should probably only be used once during system startup.
+ *
+ * @note
+ *   This is an EFM32 proprietary function, not part of the CMSIS definition.
+ *
+ * @param[in] freq
+ *   LFXO frequency in Hz used for target.
+ *****************************************************************************/
+void SystemLFXOClockSet(uint32_t freq)
+{
+  /* External crystal oscillator present? */
+#if (EFM32_LFXO_FREQ > 0)
+  SystemLFXOClock = freq;
+
+  /* Update core clock frequency if LFXO is used to clock core */
+  if ((CMU->HFCLKSTATUS & _CMU_HFCLKSTATUS_SELECTED_MASK) == CMU_HFCLKSTATUS_SELECTED_LFXO)
+  {
+    /* The function will update the global variable */
+    SystemCoreClockGet();
+  }
+#else
+  (void)freq; /* Unused parameter */
+#endif
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG_STK3401/system_efm32pg1b.h	Fri Jan 15 07:45:16 2016 +0000
@@ -0,0 +1,129 @@
+/***************************************************************************//**
+ * @file system_efm32pg1b.h
+ * @brief CMSIS Cortex-M3/M4 System Layer for EFM32 devices.
+ * @version 4.2.0
+ ******************************************************************************
+ * @section License
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ ******************************************************************************
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software.@n
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.@n
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is
+ * providing the Software "AS IS", with no express or implied warranties of any
+ * kind, including, but not limited to, any implied warranties of
+ * merchantability or fitness for any particular purpose or warranties against
+ * infringement of any proprietary rights of a third party.
+ *
+ * Silicon Laboratories, Inc. will not be liable for any consequential,
+ * incidental, or special damages, or any other relief, or for any claim by
+ * any third party, arising from your use of this Software.
+ *
+ *****************************************************************************/
+
+#ifndef SYSTEM_EFM32_H
+#define SYSTEM_EFM32_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/*******************************************************************************
+ **************************   GLOBAL VARIABLES   *******************************
+ ******************************************************************************/
+
+extern uint32_t SystemCoreClock;        /**< System Clock Frequency (Core Clock) */
+extern uint32_t SystemHfrcoFreq;        /**< System HFRCO frequency */
+
+/*******************************************************************************
+ *****************************   PROTOTYPES   **********************************
+ ******************************************************************************/
+
+void Reset_Handler(void);
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+
+void EMU_IRQHandler(void);
+void WDOG_IRQHandler(void);
+void LDMA_IRQHandler(void);
+void GPIO_EVEN_IRQHandler(void);
+void TIMER0_IRQHandler(void);
+void USART0_RX_IRQHandler(void);
+void USART0_TX_IRQHandler(void);
+void ACMP0_IRQHandler(void);
+void ADC0_IRQHandler(void);
+void IDAC0_IRQHandler(void);
+void I2C0_IRQHandler(void);
+void GPIO_ODD_IRQHandler(void);
+void TIMER1_IRQHandler(void);
+void USART1_RX_IRQHandler(void);
+void USART1_TX_IRQHandler(void);
+void LEUART0_IRQHandler(void);
+void PCNT0_IRQHandler(void);
+void CMU_IRQHandler(void);
+void MSC_IRQHandler(void);
+void LETIMER0_IRQHandler(void);
+void RTCC_IRQHandler(void);
+void CRYOTIMER_IRQHandler(void);
+
+#if (__FPU_PRESENT == 1)
+void FPUEH_IRQHandler(void);
+#endif
+
+uint32_t SystemCoreClockGet(void);
+
+/**************************************************************************//**
+ * @brief
+ *   Update CMSIS SystemCoreClock variable.
+ *
+ * @details
+ *   CMSIS defines a global variable SystemCoreClock that shall hold the
+ *   core frequency in Hz. If the core frequency is dynamically changed, the
+ *   variable must be kept updated in order to be CMSIS compliant.
+ *
+ *   Notice that only if changing the core clock frequency through the EFM CMU
+ *   API, this variable will be kept updated. This function is only provided
+ *   for CMSIS compliance and if a user modifies the the core clock outside
+ *   the CMU API.
+ *****************************************************************************/
+static __INLINE void SystemCoreClockUpdate(void)
+{
+  SystemCoreClockGet();
+}
+
+uint32_t SystemMaxCoreClockGet(void);
+
+void SystemInit(void);
+uint32_t SystemHFClockGet(void);
+
+uint32_t SystemHFXOClockGet(void);
+void SystemHFXOClockSet(uint32_t freq);
+
+uint32_t SystemLFRCOClockGet(void);
+uint32_t SystemULFRCOClockGet(void);
+
+uint32_t SystemLFXOClockGet(void);
+void SystemLFXOClockSet(uint32_t freq);
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* SYSTEM_EFM32_H */

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/TOOLCHAIN_ARM_MICRO/startup_efm32wg.S	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/TOOLCHAIN_ARM_MICRO/startup_efm32wg.S	Fri Jan 15 07:45:16 2016 +0000
@@ -2,7 +2,7 @@
 ; * @file startup_efm32wg.s
 ; * @brief    CMSIS Core Device Startup File for
 ; *           Silicon Labs EFM32WG Device Series
-; * @version 3.20.6
+; * @version 4.2.1
 ; * @date     03. February 2012
 ; *
 ; * @note
@@ -265,10 +265,7 @@
 EBI_IRQHandler
 EMU_IRQHandler
 FPUEH_IRQHandler
-
-
                 B       .
-
                 ENDP
 
                 ALIGN

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/TOOLCHAIN_ARM_STD/startup_efm32wg.S	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/TOOLCHAIN_ARM_STD/startup_efm32wg.S	Fri Jan 15 07:45:16 2016 +0000
@@ -2,7 +2,7 @@
 ; * @file startup_efm32wg.s
 ; * @brief    CMSIS Core Device Startup File for
 ; *           Silicon Labs EFM32WG Device Series
-; * @version 3.20.6
+; * @version 4.2.1
 ; * @date     03. February 2012
 ; *
 ; * @note
@@ -265,24 +265,13 @@
 EBI_IRQHandler
 EMU_IRQHandler
 FPUEH_IRQHandler
-
-
                 B       .
-
                 ENDP
 
                 ALIGN
 
 ; User Initial Stack & Heap
 
-                IF      :DEF:__MICROLIB
-
-                EXPORT  __initial_sp
-                EXPORT  __heap_base
-                EXPORT  __heap_limit
-
-                ELSE
-
                 IMPORT  __use_two_region_memory
                 EXPORT  __user_initial_stackheap
 
@@ -296,6 +285,4 @@
 
                 ALIGN
 
-                ENDIF
-
                 END

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/TOOLCHAIN_GCC_ARM/efm32wg.ld	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/TOOLCHAIN_GCC_ARM/efm32wg.ld	Fri Jan 15 07:45:16 2016 +0000
@@ -4,25 +4,34 @@
 /* CMSIS END USER LICENSE AGREEMENT.pdf, governing the use of       */
 /* Example Code.                                                    */
 /*                                                                  */
-/* Silicon Laboratories, Inc. 2014                                  */
+/* Silicon Laboratories, Inc. 2015                                  */
+/*                                                                  */
+/* Version 4.2.0 */
+/*                                                                  */
+
 MEMORY
 {
   FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 262144
   RAM (rwx)  : ORIGIN = 0x20000000, LENGTH = 32768
 }
+
 /* MBED: mbed needs to be able to dynamically set the interrupt vector table.
  * We make room for the table at the very beginning of RAM, i.e. at
- * 0x20000000. We need (16+39) * sizeof(uint32_t) = 220 bytes for EFM32WG */
+ * 0x20000000. We need (16+40) * sizeof(uint32_t) = 224 bytes for EFM32WG */
 __vector_size = 0xE0;
 
 /* Linker script to place sections and symbol values. Should be used together
  * with other linker script that defines memory regions FLASH and RAM.
  * It references following symbols, which must be defined in code:
  *   Reset_Handler : Entry of reset handler
- * 
+ *
  * It defines following symbols, which code can use without definition:
  *   __exidx_start
  *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
  *   __etext
  *   __data_start__
  *   __preinit_array_start
@@ -40,6 +49,8 @@
  *   __StackLimit
  *   __StackTop
  *   __stack
+ *   __Vectors_End
+ *   __Vectors_Size
  */
 ENTRY(Reset_Handler)
 
@@ -47,7 +58,11 @@
 {
   .text :
   {
-    KEEP(*(.isr_vector))
+    KEEP(*(.vectors))
+    __Vectors_End = .;
+    __Vectors_Size = __Vectors_End - __Vectors;
+    __end__ = .;
+
     *(.text*)
 
     KEEP(*(.init))
@@ -72,7 +87,7 @@
     KEEP(*(.eh_frame*))
   } > FLASH
 
-  .ARM.extab : 
+  .ARM.extab :
   {
     *(.ARM.extab* .gnu.linkonce.armextab.*)
   } > FLASH
@@ -84,15 +99,49 @@
   } > FLASH
   __exidx_end = .;
 
+  /* To copy multiple ROM to RAM sections,
+   * uncomment .copy.table section and,
+   * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+  /*
+  .copy.table :
+  {
+    . = ALIGN(4);
+    __copy_table_start__ = .;
+    LONG (__etext)
+    LONG (__data_start__)
+    LONG (__data_end__ - __data_start__)
+    LONG (__etext2)
+    LONG (__data2_start__)
+    LONG (__data2_end__ - __data2_start__)
+    __copy_table_end__ = .;
+  } > FLASH
+  */
+
+  /* To clear multiple BSS sections,
+   * uncomment .zero.table section and,
+   * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+  /*
+  .zero.table :
+  {
+    . = ALIGN(4);
+    __zero_table_start__ = .;
+    LONG (__bss_start__)
+    LONG (__bss_end__ - __bss_start__)
+    LONG (__bss2_start__)
+    LONG (__bss2_end__ - __bss2_start__)
+    __zero_table_end__ = .;
+  } > FLASH
+  */
+
   __etext = .;
-  
+
   .data : AT (__etext)
   {
     __data_start__ = .;
     *("dma")
     PROVIDE( __start_vector_table__ = .);
-  	. += __vector_size;
-  	PROVIDE( __end_vector_table__ = .);
+    . += __vector_size;
+    PROVIDE( __end_vector_table__ = .);
     *(vtable)
     *(.data*)
     . = ALIGN (4);
@@ -118,6 +167,7 @@
     KEEP(*(.fini_array))
     PROVIDE_HIDDEN (__fini_array_end = .);
 
+    KEEP(*(.jcr*))
     . = ALIGN(4);
     /* All data end */
     __data_end__ = .;
@@ -126,27 +176,30 @@
 
   .bss :
   {
+    . = ALIGN(4);
     __bss_start__ = .;
     *(.bss*)
     *(COMMON)
+    . = ALIGN(4);
     __bss_end__ = .;
   } > RAM
 
-  .heap :
+  .heap (COPY):
   {
+    __HeapBase = .;
     __end__ = .;
     end = __end__;
     _end = __end__;
-    *(.heap*)
+    KEEP(*(.heap*))
     __HeapLimit = .;
   } > RAM
 
   /* .stack_dummy section doesn't contains any symbols. It is only
    * used for linker to calculate size of stack sections, and assign
    * values to stack symbols later */
-  .stack_dummy :
+  .stack_dummy (COPY):
   {
-    *(.stack)
+    KEEP(*(.stack*))
   } > RAM
 
   /* Set stack top to end of RAM, and stack limit move down by
@@ -157,4 +210,7 @@
 
   /* Check if data + heap + stack exceeds RAM limit */
   ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+
+  /* Check if FLASH usage exceeds FLASH size */
+  ASSERT( LENGTH(FLASH) >= (__etext + SIZEOF(.data)), "FLASH memory overflowed !")
 }

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/TOOLCHAIN_GCC_ARM/startup_efm32wg.S	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/TOOLCHAIN_GCC_ARM/startup_efm32wg.S	Fri Jan 15 07:45:16 2016 +0000
@@ -1,235 +1,340 @@
 /* @file startup_efm32wg.S
  * @brief startup file for Silicon Labs EFM32WG devices.
  *        For use with GCC for ARM Embedded Processors
- * @version 3.20.6
- * Date: 08 Feb 2012
- *
- * Copyright (c) 2012, ARM Limited
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
-    * Redistributions of source code must retain the above copyright
-      notice, this list of conditions and the following disclaimer.
-    * Redistributions in binary form must reproduce the above copyright
-      notice, this list of conditions and the following disclaimer in the
-      documentation and/or other materials provided with the distribution.
-    * Neither the name of the ARM Limited nor the
-      names of its contributors may be used to endorse or promote products
-      derived from this software without specific prior written permission.
+ * @version 4.2.1
+ * Date:    12 June 2014
  *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
-    .syntax unified
-    .arch armv7-m
+/* Copyright (c) 2011 - 2014 ARM LIMITED
 
-    .section .stack
-    .align 3
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+    .syntax     unified
+    .arch       armv7-m
+    .section    .stack
+    .align      3
 #ifdef __STACK_SIZE
-    .equ    Stack_Size, __STACK_SIZE
+    .equ        Stack_Size, __STACK_SIZE
 #else
-    .equ    Stack_Size, 0x400
+    .equ        Stack_Size, 0x00000400
 #endif
-    .globl    __StackTop
-    .globl    __StackLimit
+    .globl      __StackTop
+    .globl      __StackLimit
 __StackLimit:
-    .space    Stack_Size
-    .size __StackLimit, . - __StackLimit
+    .space      Stack_Size
+    .size       __StackLimit, . - __StackLimit
 __StackTop:
-    .size __StackTop, . - __StackTop
+    .size       __StackTop, . - __StackTop
 
-    .section .heap
-    .align 3
+    .section    .heap
+    .align      3
 #ifdef __HEAP_SIZE
-    .equ    Heap_Size, __HEAP_SIZE
+    .equ        Heap_Size, __HEAP_SIZE
 #else
-    .equ    Heap_Size, 0xC00
+    .equ        Heap_Size, 0x00000C00
 #endif
-    .globl    __HeapBase
-    .globl    __HeapLimit
+    .globl      __HeapBase
+    .globl      __HeapLimit
 __HeapBase:
-    .if    Heap_Size
-    .space    Heap_Size
+    .if Heap_Size
+    .space      Heap_Size
     .endif
-    .size __HeapBase, . - __HeapBase
+    .size       __HeapBase, . - __HeapBase
 __HeapLimit:
-    .size __HeapLimit, . - __HeapLimit
+    .size       __HeapLimit, . - __HeapLimit
 
-    .section .isr_vector
-    .align 8
-    .globl __isr_vector
-__isr_vector:
-    .long    __StackTop            /* Top of Stack */
-    .long    Reset_Handler         /* Reset Handler */
-    .long    NMI_Handler           /* NMI Handler */
-    .long    HardFault_Handler     /* Hard Fault Handler */
-    .long    MemManage_Handler     /* MPU Fault Handler */
-    .long    BusFault_Handler      /* Bus Fault Handler */
-    .long    UsageFault_Handler    /* Usage Fault Handler */
-    .long    Default_Handler       /* Reserved */
-    .long    Default_Handler       /* Reserved */
-    .long    Default_Handler       /* Reserved */
-    .long    Default_Handler       /* Reserved */
-    .long    SVC_Handler           /* SVCall Handler */
-    .long    DebugMon_Handler      /* Debug Monitor Handler */
-    .long    Default_Handler       /* Reserved */
-    .long    PendSV_Handler        /* PendSV Handler */
-    .long    SysTick_Handler       /* SysTick Handler */
+    .section    .vectors
+    .align      2
+    .globl      __Vectors
+__Vectors:
+    .long       __StackTop            /* Top of Stack */
+    .long       Reset_Handler         /* Reset Handler */
+    .long       NMI_Handler           /* NMI Handler */
+    .long       HardFault_Handler     /* Hard Fault Handler */
+    .long       MemManage_Handler     /* MPU Fault Handler */
+    .long       BusFault_Handler      /* Bus Fault Handler */
+    .long       UsageFault_Handler    /* Usage Fault Handler */
+    .long       Default_Handler       /* Reserved */
+    .long       Default_Handler       /* Reserved */
+    .long       Default_Handler       /* Reserved */
+    .long       Default_Handler       /* Reserved */
+    .long       SVC_Handler           /* SVCall Handler */
+    .long       DebugMon_Handler      /* Debug Monitor Handler */
+    .long       Default_Handler       /* Reserved */
+    .long       PendSV_Handler        /* PendSV Handler */
+    .long       SysTick_Handler       /* SysTick Handler */
 
     /* External interrupts */
-    .long    DMA_IRQHandler    /* 0 - DMA */
-    .long    GPIO_EVEN_IRQHandler    /* 1 - GPIO_EVEN */
-    .long    TIMER0_IRQHandler    /* 2 - TIMER0 */
-    .long    USART0_RX_IRQHandler    /* 3 - USART0_RX */
-    .long    USART0_TX_IRQHandler    /* 4 - USART0_TX */
-    .long    USB_IRQHandler    /* 5 - USB */
-    .long    ACMP0_IRQHandler    /* 6 - ACMP0 */
-    .long    ADC0_IRQHandler    /* 7 - ADC0 */
-    .long    DAC0_IRQHandler    /* 8 - DAC0 */
-    .long    I2C0_IRQHandler    /* 9 - I2C0 */
-    .long    I2C1_IRQHandler    /* 10 - I2C1 */
-    .long    GPIO_ODD_IRQHandler    /* 11 - GPIO_ODD */
-    .long    TIMER1_IRQHandler    /* 12 - TIMER1 */
-    .long    TIMER2_IRQHandler    /* 13 - TIMER2 */
-    .long    TIMER3_IRQHandler    /* 14 - TIMER3 */
-    .long    USART1_RX_IRQHandler    /* 15 - USART1_RX */
-    .long    USART1_TX_IRQHandler    /* 16 - USART1_TX */
-    .long    LESENSE_IRQHandler    /* 17 - LESENSE */
-    .long    USART2_RX_IRQHandler    /* 18 - USART2_RX */
-    .long    USART2_TX_IRQHandler    /* 19 - USART2_TX */
-    .long    UART0_RX_IRQHandler    /* 20 - UART0_RX */
-    .long    UART0_TX_IRQHandler    /* 21 - UART0_TX */
-    .long    UART1_RX_IRQHandler    /* 22 - UART1_RX */
-    .long    UART1_TX_IRQHandler    /* 23 - UART1_TX */
-    .long    LEUART0_IRQHandler    /* 24 - LEUART0 */
-    .long    LEUART1_IRQHandler    /* 25 - LEUART1 */
-    .long    LETIMER0_IRQHandler    /* 26 - LETIMER0 */
-    .long    PCNT0_IRQHandler    /* 27 - PCNT0 */
-    .long    PCNT1_IRQHandler    /* 28 - PCNT1 */
-    .long    PCNT2_IRQHandler    /* 29 - PCNT2 */
-    .long    RTC_IRQHandler    /* 30 - RTC */
-    .long    BURTC_IRQHandler    /* 31 - BURTC */
-    .long    CMU_IRQHandler    /* 32 - CMU */
-    .long    VCMP_IRQHandler    /* 33 - VCMP */
-    .long    LCD_IRQHandler    /* 34 - LCD */
-    .long    MSC_IRQHandler    /* 35 - MSC */
-    .long    AES_IRQHandler    /* 36 - AES */
-    .long    EBI_IRQHandler    /* 37 - EBI */
-    .long    EMU_IRQHandler    /* 38 - EMU */
-    .long    FPUEH_IRQHandler    /* 39 - FPUEH */
+
+    .long       DMA_IRQHandler    /* 0 - DMA */
+    .long       GPIO_EVEN_IRQHandler    /* 1 - GPIO_EVEN */
+    .long       TIMER0_IRQHandler    /* 2 - TIMER0 */
+    .long       USART0_RX_IRQHandler    /* 3 - USART0_RX */
+    .long       USART0_TX_IRQHandler    /* 4 - USART0_TX */
+    .long       USB_IRQHandler    /* 5 - USB */
+    .long       ACMP0_IRQHandler    /* 6 - ACMP0 */
+    .long       ADC0_IRQHandler    /* 7 - ADC0 */
+    .long       DAC0_IRQHandler    /* 8 - DAC0 */
+    .long       I2C0_IRQHandler    /* 9 - I2C0 */
+    .long       I2C1_IRQHandler    /* 10 - I2C1 */
+    .long       GPIO_ODD_IRQHandler    /* 11 - GPIO_ODD */
+    .long       TIMER1_IRQHandler    /* 12 - TIMER1 */
+    .long       TIMER2_IRQHandler    /* 13 - TIMER2 */
+    .long       TIMER3_IRQHandler    /* 14 - TIMER3 */
+    .long       USART1_RX_IRQHandler    /* 15 - USART1_RX */
+    .long       USART1_TX_IRQHandler    /* 16 - USART1_TX */
+    .long       LESENSE_IRQHandler    /* 17 - LESENSE */
+    .long       USART2_RX_IRQHandler    /* 18 - USART2_RX */
+    .long       USART2_TX_IRQHandler    /* 19 - USART2_TX */
+    .long       UART0_RX_IRQHandler    /* 20 - UART0_RX */
+    .long       UART0_TX_IRQHandler    /* 21 - UART0_TX */
+    .long       UART1_RX_IRQHandler    /* 22 - UART1_RX */
+    .long       UART1_TX_IRQHandler    /* 23 - UART1_TX */
+    .long       LEUART0_IRQHandler    /* 24 - LEUART0 */
+    .long       LEUART1_IRQHandler    /* 25 - LEUART1 */
+    .long       LETIMER0_IRQHandler    /* 26 - LETIMER0 */
+    .long       PCNT0_IRQHandler    /* 27 - PCNT0 */
+    .long       PCNT1_IRQHandler    /* 28 - PCNT1 */
+    .long       PCNT2_IRQHandler    /* 29 - PCNT2 */
+    .long       RTC_IRQHandler    /* 30 - RTC */
+    .long       BURTC_IRQHandler    /* 31 - BURTC */
+    .long       CMU_IRQHandler    /* 32 - CMU */
+    .long       VCMP_IRQHandler    /* 33 - VCMP */
+    .long       LCD_IRQHandler    /* 34 - LCD */
+    .long       MSC_IRQHandler    /* 35 - MSC */
+    .long       AES_IRQHandler    /* 36 - AES */
+    .long       EBI_IRQHandler    /* 37 - EBI */
+    .long       EMU_IRQHandler    /* 38 - EMU */
+    .long       FPUEH_IRQHandler    /* 39 - FPUEH */
 
 
-    .size    __isr_vector, . - __isr_vector
+    .size       __Vectors, . - __Vectors
 
     .text
     .thumb
     .thumb_func
-    .align 2
-    .globl    Reset_Handler
-    .type    Reset_Handler, %function
+    .align      2
+    .globl      Reset_Handler
+    .type       Reset_Handler, %function
 Reset_Handler:
-/*     Loop to copy data from read only memory to RAM. The ranges
- *      of copy from/to are specified by following symbols evaluated in
- *      linker script.
- *      __etext: End of code section, i.e., begin of data sections to copy from.
- *      __data_start__/__data_end__: RAM address range that data should be
- *      copied to. Both must be aligned to 4 bytes boundary.  */
 #ifndef __NO_SYSTEM_INIT
-    ldr    r0, =SystemInit
-    blx    r0
+    ldr     r0, =SystemInit
+    blx     r0
 #endif
-    ldr    r1, =__etext
-    ldr    r2, =__data_start__
-    ldr    r3, =__data_end__
+
+/*  Firstly it copies data from read only memory to RAM. There are two schemes
+ *  to copy. One can copy more than one sections. Another can only copy
+ *  one section.  The former scheme needs more instructions and read-only
+ *  data to implement than the latter.
+ *  Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.  */
+
+#ifdef __STARTUP_COPY_MULTIPLE
+/*  Multiple sections scheme.
+ *
+ *  Between symbol address __copy_table_start__ and __copy_table_end__,
+ *  there are array of triplets, each of which specify:
+ *    offset 0: LMA of start of a section to copy from
+ *    offset 4: VMA of start of a section to copy to
+ *    offset 8: size of the section to copy. Must be multiply of 4
+ *
+ *  All addresses must be aligned to 4 bytes boundary.
+ */
+    ldr     r4, =__copy_table_start__
+    ldr     r5, =__copy_table_end__
+
+.L_loop0:
+    cmp     r4, r5
+    bge     .L_loop0_done
+    ldr     r1, [r4]
+    ldr     r2, [r4, #4]
+    ldr     r3, [r4, #8]
+
+.L_loop0_0:
+    subs    r3, #4
+    ittt    ge
+    ldrge   r0, [r1, r3]
+    strge   r0, [r2, r3]
+    bge     .L_loop0_0
+
+    adds    r4, #12
+    b       .L_loop0
+
+.L_loop0_done:
+#else
+/*  Single section scheme.
+ *
+ *  The ranges of copy from/to are specified by following symbols
+ *    __etext: LMA of start of the section to copy from. Usually end of text
+ *    __data_start__: VMA of start of the section to copy to
+ *    __data_end__: VMA of end of the section to copy to
+ *
+ *  All addresses must be aligned to 4 bytes boundary.
+ */
+    ldr     r1, =__etext
+    ldr     r2, =__data_start__
+    ldr     r3, =__data_end__
+
+.L_loop1:
+    cmp     r2, r3
+    ittt    lt
+    ldrlt   r0, [r1], #4
+    strlt   r0, [r2], #4
+    blt     .L_loop1
+#endif /*__STARTUP_COPY_MULTIPLE */
 
-    subs   r3, r2
-    ble    .flash_to_ram_loop_end
-.flash_to_ram_loop:
-    subs   r3, #4
-    ldr    r0, [r1, r3]
-    str    r0, [r2, r3]
-    bgt    .flash_to_ram_loop
-.flash_to_ram_loop_end:
+/*  This part of work usually is done in C library startup code. Otherwise,
+ *  define this macro to enable it in this startup.
+ *
+ *  There are two schemes too. One can clear multiple BSS sections. Another
+ *  can only clear one section. The former is more size expensive than the
+ *  latter.
+ *
+ *  Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ *  Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ */
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
+/*  Multiple sections scheme.
+ *
+ *  Between symbol address __copy_table_start__ and __copy_table_end__,
+ *  there are array of tuples specifying:
+ *    offset 0: Start of a BSS section
+ *    offset 4: Size of this BSS section. Must be multiply of 4
+ */
+    ldr     r3, =__zero_table_start__
+    ldr     r4, =__zero_table_end__
+
+.L_loop2:
+    cmp     r3, r4
+    bge     .L_loop2_done
+    ldr     r1, [r3]
+    ldr     r2, [r3, #4]
+    movs    r0, 0
 
-    ldr    r0, =_start
-    bx     r0
+.L_loop2_0:
+    subs    r2, #4
+    itt     ge
+    strge   r0, [r1, r2]
+    bge     .L_loop2_0
+    adds    r3, #8
+    b       .L_loop2
+.L_loop2_done:
+#elif defined (__STARTUP_CLEAR_BSS)
+/*  Single BSS section scheme.
+ *
+ *  The BSS section is specified by following symbols
+ *    __bss_start__: start of the BSS section.
+ *    __bss_end__: end of the BSS section.
+ *
+ *  Both addresses must be aligned to 4 bytes boundary.
+ */
+    ldr     r1, =__bss_start__
+    ldr     r2, =__bss_end__
+
+    movs    r0, 0
+.L_loop3:
+    cmp     r1, r2
+    itt     lt
+    strlt   r0, [r1], #4
+    blt     .L_loop3
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
+
+#ifndef __START
+#define __START _start
+#endif
+    bl      __START
+
     .pool
-    .size Reset_Handler, . - Reset_Handler
+    .size   Reset_Handler, . - Reset_Handler
+
+    .align  1
+    .thumb_func
+    .weak   Default_Handler
+    .type   Default_Handler, %function
+Default_Handler:
+    b       .
+    .size   Default_Handler, . - Default_Handler
 
 /*    Macro to define default handlers. Default handler
  *    will be weak symbol and just dead loops. They can be
  *    overwritten by other handlers */
-    .macro    def_irq_handler    handler_name
-    .align 1
-    .thumb_func
-    .weak    \handler_name
-    .type    \handler_name, %function
-\handler_name:
-    b    .
-    .size    \handler_name, . - \handler_name
+    .macro  def_irq_handler	handler_name
+    .weak   \handler_name
+    .set    \handler_name, Default_Handler
     .endm
 
-    def_irq_handler    Default_Handler
-
-    def_irq_handler    NMI_Handler
-    def_irq_handler    HardFault_Handler
-    def_irq_handler    MemManage_Handler
-    def_irq_handler    BusFault_Handler
-    def_irq_handler    UsageFault_Handler
-    def_irq_handler    SVC_Handler
-    def_irq_handler    DebugMon_Handler
-    def_irq_handler    PendSV_Handler
-    def_irq_handler    SysTick_Handler
+    def_irq_handler     NMI_Handler
+    def_irq_handler     HardFault_Handler
+    def_irq_handler     MemManage_Handler
+    def_irq_handler     BusFault_Handler
+    def_irq_handler     UsageFault_Handler
+    def_irq_handler     SVC_Handler
+    def_irq_handler     DebugMon_Handler
+    def_irq_handler     PendSV_Handler
+    def_irq_handler     SysTick_Handler
 
-    def_irq_handler    DMA_IRQHandler
-    def_irq_handler    GPIO_EVEN_IRQHandler
-    def_irq_handler    TIMER0_IRQHandler
-    def_irq_handler    USART0_RX_IRQHandler
-    def_irq_handler    USART0_TX_IRQHandler
-    def_irq_handler    USB_IRQHandler
-    def_irq_handler    ACMP0_IRQHandler
-    def_irq_handler    ADC0_IRQHandler
-    def_irq_handler    DAC0_IRQHandler
-    def_irq_handler    I2C0_IRQHandler
-    def_irq_handler    I2C1_IRQHandler
-    def_irq_handler    GPIO_ODD_IRQHandler
-    def_irq_handler    TIMER1_IRQHandler
-    def_irq_handler    TIMER2_IRQHandler
-    def_irq_handler    TIMER3_IRQHandler
-    def_irq_handler    USART1_RX_IRQHandler
-    def_irq_handler    USART1_TX_IRQHandler
-    def_irq_handler    LESENSE_IRQHandler
-    def_irq_handler    USART2_RX_IRQHandler
-    def_irq_handler    USART2_TX_IRQHandler
-    def_irq_handler    UART0_RX_IRQHandler
-    def_irq_handler    UART0_TX_IRQHandler
-    def_irq_handler    UART1_RX_IRQHandler
-    def_irq_handler    UART1_TX_IRQHandler
-    def_irq_handler    LEUART0_IRQHandler
-    def_irq_handler    LEUART1_IRQHandler
-    def_irq_handler    LETIMER0_IRQHandler
-    def_irq_handler    PCNT0_IRQHandler
-    def_irq_handler    PCNT1_IRQHandler
-    def_irq_handler    PCNT2_IRQHandler
-    def_irq_handler    RTC_IRQHandler
-    def_irq_handler    BURTC_IRQHandler
-    def_irq_handler    CMU_IRQHandler
-    def_irq_handler    VCMP_IRQHandler
-    def_irq_handler    LCD_IRQHandler
-    def_irq_handler    MSC_IRQHandler
-    def_irq_handler    AES_IRQHandler
-    def_irq_handler    EBI_IRQHandler
-    def_irq_handler    EMU_IRQHandler
-    def_irq_handler    FPUEH_IRQHandler
+    def_irq_handler     DMA_IRQHandler
+    def_irq_handler     GPIO_EVEN_IRQHandler
+    def_irq_handler     TIMER0_IRQHandler
+    def_irq_handler     USART0_RX_IRQHandler
+    def_irq_handler     USART0_TX_IRQHandler
+    def_irq_handler     USB_IRQHandler
+    def_irq_handler     ACMP0_IRQHandler
+    def_irq_handler     ADC0_IRQHandler
+    def_irq_handler     DAC0_IRQHandler
+    def_irq_handler     I2C0_IRQHandler
+    def_irq_handler     I2C1_IRQHandler
+    def_irq_handler     GPIO_ODD_IRQHandler
+    def_irq_handler     TIMER1_IRQHandler
+    def_irq_handler     TIMER2_IRQHandler
+    def_irq_handler     TIMER3_IRQHandler
+    def_irq_handler     USART1_RX_IRQHandler
+    def_irq_handler     USART1_TX_IRQHandler
+    def_irq_handler     LESENSE_IRQHandler
+    def_irq_handler     USART2_RX_IRQHandler
+    def_irq_handler     USART2_TX_IRQHandler
+    def_irq_handler     UART0_RX_IRQHandler
+    def_irq_handler     UART0_TX_IRQHandler
+    def_irq_handler     UART1_RX_IRQHandler
+    def_irq_handler     UART1_TX_IRQHandler
+    def_irq_handler     LEUART0_IRQHandler
+    def_irq_handler     LEUART1_IRQHandler
+    def_irq_handler     LETIMER0_IRQHandler
+    def_irq_handler     PCNT0_IRQHandler
+    def_irq_handler     PCNT1_IRQHandler
+    def_irq_handler     PCNT2_IRQHandler
+    def_irq_handler     RTC_IRQHandler
+    def_irq_handler     BURTC_IRQHandler
+    def_irq_handler     CMU_IRQHandler
+    def_irq_handler     VCMP_IRQHandler
+    def_irq_handler     LCD_IRQHandler
+    def_irq_handler     MSC_IRQHandler
+    def_irq_handler     AES_IRQHandler
+    def_irq_handler     EBI_IRQHandler
+    def_irq_handler     EMU_IRQHandler
+    def_irq_handler     FPUEH_IRQHandler
 
 
     .end

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/cmsis_nvic.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/cmsis_nvic.h	Fri Jan 15 07:45:16 2016 +0000
@@ -2,14 +2,14 @@
  * Copyright (c) 2009-2011 ARM Limited. All rights reserved.
  *
  * CMSIS-style functionality to support dynamic vectors
- */ 
+ */
 
 #ifndef MBED_CMSIS_NVIC_H
 #define MBED_CMSIS_NVIC_H
 
 #include "cmsis.h"
 
-#define NVIC_NUM_VECTORS      (16 + 39)   // CORE + MCU Peripherals
+#define NVIC_NUM_VECTORS      (16 + 40)   // CORE + MCU Peripherals
 #define NVIC_USER_IRQ_OFFSET  16
 
 #ifdef __cplusplus

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg990f256.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg990f256.h	Fri Jan 15 07:45:16 2016 +0000
@@ -2,10 +2,10 @@
  * @file efm32wg990f256.h
  * @brief CMSIS Cortex-M Peripheral Access Layer Header File
  *        for EFM32WG990F256
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -31,8 +31,8 @@
  *
  *****************************************************************************/
 
-#ifndef __EFM32WG990F256_H
-#define __EFM32WG990F256_H
+#ifndef EFM32WG990F256_H
+#define EFM32WG990F256_H
 
 #ifdef __cplusplus
 extern "C" {
@@ -52,7 +52,7 @@
 typedef enum IRQn
 {
 /******  Cortex-M4 Processor Exceptions Numbers *******************************************/
-  NonMaskableInt_IRQn   = -14,              /*!< 2 Non Maskable Interrupt                 */
+  NonMaskableInt_IRQn   = -14,              /*!< 2 Cortex-M4 Non Maskable Interrupt       */
   HardFault_IRQn        = -13,              /*!< 3 Cortex-M4 Hard Fault Interrupt         */
   MemoryManagement_IRQn = -12,              /*!< 4 Cortex-M4 Memory Management Interrupt  */
   BusFault_IRQn         = -11,              /*!< 5 Cortex-M4 Bus Fault Interrupt          */
@@ -123,8 +123,10 @@
 ******************************************************************************/
 
 /** Part family */
-#define _EFM32_WONDER_FAMILY    1 /**< Wonder Gecko EFM32WG MCU Family */
-#define _EFM_DEVICE               /**< Silicon Labs EFM-type microcontroller */
+#define _EFM32_WONDER_FAMILY            1 /**< Wonder Gecko EFM32WG MCU Family */
+#define _EFM_DEVICE                       /**< Silicon Labs EFM-type microcontroller */
+#define _SILICON_LABS_32B_PLATFORM_1      /**< Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM      1 /**< Silicon Labs platform name */
 
 /* If part number is not defined as compiler option, define it */
 #if !defined(EFM32WG990F256)
@@ -189,80 +191,81 @@
 #define AFACHAN_MAX          53
 
 /* Part number capabilities */
-#define USART_PRESENT          /**< USART is available in this part */
-#define USART_COUNT          3 /**< 3 USARTs available  */
-#define UART_PRESENT           /**< UART is available in this part */
-#define UART_COUNT           2 /**< 2 UARTs available  */
-#define TIMER_PRESENT          /**< TIMER is available in this part */
-#define TIMER_COUNT          4 /**< 4 TIMERs available  */
-#define ACMP_PRESENT           /**< ACMP is available in this part */
-#define ACMP_COUNT           2 /**< 2 ACMPs available  */
-#define LEUART_PRESENT         /**< LEUART is available in this part */
-#define LEUART_COUNT         2 /**< 2 LEUARTs available  */
-#define LETIMER_PRESENT        /**< LETIMER is available in this part */
-#define LETIMER_COUNT        1 /**< 1 LETIMERs available  */
-#define PCNT_PRESENT           /**< PCNT is available in this part */
-#define PCNT_COUNT           3 /**< 3 PCNTs available  */
-#define I2C_PRESENT            /**< I2C is available in this part */
-#define I2C_COUNT            2 /**< 2 I2Cs available  */
-#define ADC_PRESENT            /**< ADC is available in this part */
-#define ADC_COUNT            1 /**< 1 ADCs available  */
-#define DAC_PRESENT            /**< DAC is available in this part */
-#define DAC_COUNT            1 /**< 1 DACs available  */
+
+#define USART_PRESENT         /**< USART is available in this part */
+#define USART_COUNT         3 /**< 3 USARTs available  */
+#define UART_PRESENT          /**< UART is available in this part */
+#define UART_COUNT          2 /**< 2 UARTs available  */
+#define TIMER_PRESENT         /**< TIMER is available in this part */
+#define TIMER_COUNT         4 /**< 4 TIMERs available  */
+#define ACMP_PRESENT          /**< ACMP is available in this part */
+#define ACMP_COUNT          2 /**< 2 ACMPs available  */
+#define LEUART_PRESENT        /**< LEUART is available in this part */
+#define LEUART_COUNT        2 /**< 2 LEUARTs available  */
+#define LETIMER_PRESENT       /**< LETIMER is available in this part */
+#define LETIMER_COUNT       1 /**< 1 LETIMERs available  */
+#define PCNT_PRESENT          /**< PCNT is available in this part */
+#define PCNT_COUNT          3 /**< 3 PCNTs available  */
+#define I2C_PRESENT           /**< I2C is available in this part */
+#define I2C_COUNT           2 /**< 2 I2Cs available  */
+#define ADC_PRESENT           /**< ADC is available in this part */
+#define ADC_COUNT           1 /**< 1 ADCs available  */
+#define DAC_PRESENT           /**< DAC is available in this part */
+#define DAC_COUNT           1 /**< 1 DACs available  */
 #define DMA_PRESENT
-#define DMA_COUNT            1
+#define DMA_COUNT           1
 #define AES_PRESENT
-#define AES_COUNT            1
+#define AES_COUNT           1
 #define USBC_PRESENT
-#define USBC_COUNT           1
+#define USBC_COUNT          1
 #define USB_PRESENT
-#define USB_COUNT            1
+#define USB_COUNT           1
 #define LE_PRESENT
-#define LE_COUNT             1
+#define LE_COUNT            1
 #define MSC_PRESENT
-#define MSC_COUNT            1
+#define MSC_COUNT           1
 #define EMU_PRESENT
-#define EMU_COUNT            1
+#define EMU_COUNT           1
 #define RMU_PRESENT
-#define RMU_COUNT            1
+#define RMU_COUNT           1
 #define CMU_PRESENT
-#define CMU_COUNT            1
+#define CMU_COUNT           1
 #define LESENSE_PRESENT
-#define LESENSE_COUNT        1
+#define LESENSE_COUNT       1
 #define EBI_PRESENT
-#define EBI_COUNT            1
+#define EBI_COUNT           1
 #define FPUEH_PRESENT
-#define FPUEH_COUNT          1
+#define FPUEH_COUNT         1
 #define RTC_PRESENT
-#define RTC_COUNT            1
+#define RTC_COUNT           1
 #define GPIO_PRESENT
-#define GPIO_COUNT           1
+#define GPIO_COUNT          1
 #define VCMP_PRESENT
-#define VCMP_COUNT           1
+#define VCMP_COUNT          1
 #define PRS_PRESENT
-#define PRS_COUNT            1
+#define PRS_COUNT           1
 #define OPAMP_PRESENT
-#define OPAMP_COUNT          1
+#define OPAMP_COUNT         1
 #define BU_PRESENT
-#define BU_COUNT             1
+#define BU_COUNT            1
 #define LCD_PRESENT
-#define LCD_COUNT            1
+#define LCD_COUNT           1
 #define BURTC_PRESENT
-#define BURTC_COUNT          1
+#define BURTC_COUNT         1
 #define HFXTAL_PRESENT
-#define HFXTAL_COUNT         1
+#define HFXTAL_COUNT        1
 #define LFXTAL_PRESENT
-#define LFXTAL_COUNT         1
+#define LFXTAL_COUNT        1
 #define WDOG_PRESENT
-#define WDOG_COUNT           1
+#define WDOG_COUNT          1
 #define DBG_PRESENT
-#define DBG_COUNT            1
+#define DBG_COUNT           1
 #define ETM_PRESENT
-#define ETM_COUNT            1
+#define ETM_COUNT           1
 #define BOOTLOADER_PRESENT
-#define BOOTLOADER_COUNT     1
+#define BOOTLOADER_COUNT    1
 #define ANALOG_PRESENT
-#define ANALOG_COUNT         1
+#define ANALOG_COUNT        1
 
 #include "core_cm4.h"       /* Cortex-M4 processor and core peripherals */
 #include "system_efm32wg.h" /* System Header */
@@ -480,4 +483,4 @@
 #ifdef __cplusplus
 }
 #endif
-#endif /* __EFM32WG990F256_H */
+#endif /* EFM32WG990F256_H */

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_acmp.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_acmp.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32wg_acmp.h
  * @brief EFM32WG_ACMP register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32WG_ACMP
  * @{
  * @brief EFM32WG_ACMP Register Declaration
@@ -327,5 +331,5 @@
 #define ACMP_ROUTE_LOCATION_LOC2           (_ACMP_ROUTE_LOCATION_LOC2 << 8)    /**< Shifted mode LOC2 for ACMP_ROUTE */
 
 /** @} End of group EFM32WG_ACMP */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_adc.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_adc.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32wg_adc.h
  * @brief EFM32WG_ADC register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32WG_ADC
  * @{
  * @brief EFM32WG_ADC Register Declaration
@@ -666,5 +670,5 @@
 #define ADC_BIASPROG_COMPBIAS_DEFAULT           (_ADC_BIASPROG_COMPBIAS_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_BIASPROG */
 
 /** @} End of group EFM32WG_ADC */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_aes.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_aes.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32wg_aes.h
  * @brief EFM32WG_AES register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32WG_AES
  * @{
  * @brief EFM32WG_AES Register Declaration
@@ -235,5 +239,5 @@
 #define AES_KEYHD_KEYHD_DEFAULT         (_AES_KEYHD_KEYHD_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYHD */
 
 /** @} End of group EFM32WG_AES */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_af_pins.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_af_pins.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32wg_af_pins.h
  * @brief EFM32WG_AF_PINS register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32WG_AF_Pins
  * @{
  *****************************************************************************/
@@ -200,5 +204,5 @@
 #define AF_ETM_TD3_PIN(i)           ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 5 :  -1)
 
 /** @} End of group EFM32WG_AF_Pins */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_af_ports.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_af_ports.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32wg_af_ports.h
  * @brief EFM32WG_AF_PORTS register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32WG_AF_Ports
  * @{
  *****************************************************************************/
@@ -200,5 +204,5 @@
 #define AF_ETM_TD3_PORT(i)           ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 0 :  -1)
 
 /** @} End of group EFM32WG_AF_Ports */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_burtc.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_burtc.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32wg_burtc.h
  * @brief EFM32WG_BURTC register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32WG_BURTC
  * @{
  * @brief EFM32WG_BURTC Register Declaration
@@ -55,7 +59,6 @@
   __I uint32_t      SYNCBUSY;      /**< Synchronization Busy Register  */
 
   uint32_t          RESERVED0[48]; /**< Reserved registers */
-
   BURTC_RET_TypeDef RET[128];      /**< RetentionReg */
 } BURTC_TypeDef;                   /** @} */
 
@@ -373,5 +376,5 @@
 #define BURTC_RET_REG_REG_DEFAULT             (_BURTC_RET_REG_REG_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_RET_REG */
 
 /** @} End of group EFM32WG_BURTC */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_burtc_ret.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_burtc_ret.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32wg_burtc_ret.h
  * @brief EFM32WG_BURTC_RET register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @brief BURTC_RET EFM32WG BURTC RET
  *****************************************************************************/
 typedef struct
@@ -37,3 +41,6 @@
   __IO uint32_t REG; /**< Retention Register  */
 } BURTC_RET_TypeDef;
 
+/** @} End of group Parts */
+
+

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_calibrate.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_calibrate.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32wg_calibrate.h
  * @brief EFM32WG_CALIBRATE register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32WG_CALIBRATE
  * @{
  *****************************************************************************/
@@ -41,3 +45,6 @@
   __I uint32_t VALUE;   /**< Default value for calibration register */
 } CALIBRATE_TypeDef;    /** @} */
 
+/** @} End of group Parts */
+
+

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_cmu.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_cmu.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32wg_cmu.h
  * @brief EFM32WG_CMU register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32WG_CMU
  * @{
  * @brief EFM32WG_CMU Register Declaration
@@ -60,6 +64,7 @@
   __IO uint32_t LFACLKEN0;    /**< Low Frequency A Clock Enable Register 0  (Async Reg)  */
   uint32_t      RESERVED1[1]; /**< Reserved for future use **/
   __IO uint32_t LFBCLKEN0;    /**< Low Frequency B Clock Enable Register 0 (Async Reg)  */
+
   uint32_t      RESERVED2[1]; /**< Reserved for future use **/
   __IO uint32_t LFAPRESC0;    /**< Low Frequency A Prescaler Register 0 (Async Reg)  */
   uint32_t      RESERVED3[1]; /**< Reserved for future use **/
@@ -78,7 +83,7 @@
 
 /* Bit fields for CMU CTRL */
 #define _CMU_CTRL_RESETVALUE                        0x000C262CUL                                /**< Default value for CMU_CTRL */
-#define _CMU_CTRL_MASK                              0x53FFFEEFUL                                /**< Mask for CMU_CTRL */
+#define _CMU_CTRL_MASK                              0x57FFFEEFUL                                /**< Mask for CMU_CTRL */
 #define _CMU_CTRL_HFXOMODE_SHIFT                    0                                           /**< Shift value for CMU_HFXOMODE */
 #define _CMU_CTRL_HFXOMODE_MASK                     0x3UL                                       /**< Bit mask for CMU_HFXOMODE */
 #define _CMU_CTRL_HFXOMODE_DEFAULT                  0x00000000UL                                /**< Mode DEFAULT for CMU_CTRL */
@@ -187,7 +192,7 @@
 #define CMU_CTRL_CLKOUTSEL0_ULFRCO                  (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20)         /**< Shifted mode ULFRCO for CMU_CTRL */
 #define CMU_CTRL_CLKOUTSEL0_AUXHFRCO                (_CMU_CTRL_CLKOUTSEL0_AUXHFRCO << 20)       /**< Shifted mode AUXHFRCO for CMU_CTRL */
 #define _CMU_CTRL_CLKOUTSEL1_SHIFT                  23                                          /**< Shift value for CMU_CLKOUTSEL1 */
-#define _CMU_CTRL_CLKOUTSEL1_MASK                   0x3800000UL                                 /**< Bit mask for CMU_CLKOUTSEL1 */
+#define _CMU_CTRL_CLKOUTSEL1_MASK                   0x7800000UL                                 /**< Bit mask for CMU_CLKOUTSEL1 */
 #define _CMU_CTRL_CLKOUTSEL1_DEFAULT                0x00000000UL                                /**< Mode DEFAULT for CMU_CTRL */
 #define _CMU_CTRL_CLKOUTSEL1_LFRCO                  0x00000000UL                                /**< Mode LFRCO for CMU_CTRL */
 #define _CMU_CTRL_CLKOUTSEL1_LFXO                   0x00000001UL                                /**< Mode LFXO for CMU_CTRL */
@@ -454,7 +459,7 @@
 
 /* Bit fields for CMU CMD */
 #define _CMU_CMD_RESETVALUE                         0x00000000UL                          /**< Default value for CMU_CMD */
-#define _CMU_CMD_MASK                               0x0000007FUL                          /**< Mask for CMU_CMD */
+#define _CMU_CMD_MASK                               0x000000FFUL                          /**< Mask for CMU_CMD */
 #define _CMU_CMD_HFCLKSEL_SHIFT                     0                                     /**< Shift value for CMU_HFCLKSEL */
 #define _CMU_CMD_HFCLKSEL_MASK                      0x7UL                                 /**< Bit mask for CMU_HFCLKSEL */
 #define _CMU_CMD_HFCLKSEL_DEFAULT                   0x00000000UL                          /**< Mode DEFAULT for CMU_CMD */
@@ -478,7 +483,7 @@
 #define _CMU_CMD_CALSTOP_DEFAULT                    0x00000000UL                          /**< Mode DEFAULT for CMU_CMD */
 #define CMU_CMD_CALSTOP_DEFAULT                     (_CMU_CMD_CALSTOP_DEFAULT << 4)       /**< Shifted mode DEFAULT for CMU_CMD */
 #define _CMU_CMD_USBCCLKSEL_SHIFT                   5                                     /**< Shift value for CMU_USBCCLKSEL */
-#define _CMU_CMD_USBCCLKSEL_MASK                    0x60UL                                /**< Bit mask for CMU_USBCCLKSEL */
+#define _CMU_CMD_USBCCLKSEL_MASK                    0xE0UL                                /**< Bit mask for CMU_USBCCLKSEL */
 #define _CMU_CMD_USBCCLKSEL_DEFAULT                 0x00000000UL                          /**< Mode DEFAULT for CMU_CMD */
 #define _CMU_CMD_USBCCLKSEL_HFCLKNODIV              0x00000001UL                          /**< Mode HFCLKNODIV for CMU_CMD */
 #define _CMU_CMD_USBCCLKSEL_LFXO                    0x00000002UL                          /**< Mode LFXO for CMU_CMD */
@@ -1243,5 +1248,5 @@
 #define CMU_LOCK_LOCKKEY_UNLOCK                     (_CMU_LOCK_LOCKKEY_UNLOCK << 0)   /**< Shifted mode UNLOCK for CMU_LOCK */
 
 /** @} End of group EFM32WG_CMU */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_dac.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_dac.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32wg_dac.h
  * @brief EFM32WG_DAC register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32WG_DAC
  * @{
  * @brief EFM32WG_DAC Register Declaration
@@ -788,5 +792,5 @@
 #define DAC_OPA2MUX_RESSEL_RES7               (_DAC_OPA2MUX_RESSEL_RES7 << 28)     /**< Shifted mode RES7 for DAC_OPA2MUX */
 
 /** @} End of group EFM32WG_DAC */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_devinfo.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_devinfo.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32wg_devinfo.h
  * @brief EFM32WG_DEVINFO register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32WG_DEVINFO
  * @{
  *****************************************************************************/
@@ -140,15 +144,28 @@
 #define _DEVINFO_PART_PROD_REV_SHIFT               24           /**< Bit position for production revision */
 #define _DEVINFO_PART_DEVICE_FAMILY_MASK           0x00FF0000UL /**< Device Family, 0x47 for Gecko */
 #define _DEVINFO_PART_DEVICE_FAMILY_SHIFT          16           /**< Bit position for device family */
+/* Legacy family #defines */
 #define _DEVINFO_PART_DEVICE_FAMILY_G              71           /**< Gecko Device Family */
 #define _DEVINFO_PART_DEVICE_FAMILY_GG             72           /**< Giant Gecko Device Family */
 #define _DEVINFO_PART_DEVICE_FAMILY_TG             73           /**< Tiny Gecko Device Family */
 #define _DEVINFO_PART_DEVICE_FAMILY_LG             74           /**< Leopard Gecko Device Family */
 #define _DEVINFO_PART_DEVICE_FAMILY_WG             75           /**< Wonder Gecko Device Family */
 #define _DEVINFO_PART_DEVICE_FAMILY_ZG             76           /**< Zero Gecko Device Family */
+#define _DEVINFO_PART_DEVICE_FAMILY_HG             77           /**< Happy Gecko Device Family */
+/* New style family #defines */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFM32G         71           /**< Gecko Device Family */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFM32GG        72           /**< Giant Gecko Device Family */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFM32TG        73           /**< Tiny Gecko Device Family */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFM32LG        74           /**< Leopard Gecko Device Family */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFM32WG        75           /**< Wonder Gecko Device Family */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFM32ZG        76           /**< Zero Gecko Device Family */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFM32HG        77           /**< Happy Gecko Device Family */
+#define _DEVINFO_PART_DEVICE_FAMILY_EZR32WG        120          /**< EZR Wonder Gecko Device Family */
+#define _DEVINFO_PART_DEVICE_FAMILY_EZR32LG        121          /**< EZR Leopard Gecko Device Family */
+#define _DEVINFO_PART_DEVICE_FAMILY_EZR32HG        122          /**< EZR Happy Gecko Device Family */
 #define _DEVINFO_PART_DEVICE_NUMBER_MASK           0x0000FFFFUL /**< Device number */
 #define _DEVINFO_PART_DEVICE_NUMBER_SHIFT          0            /**< Bit position for device number */
 
 /** @} End of group EFM32WG_DEVINFO */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_dma.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_dma.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32wg_dma.h
  * @brief EFM32WG_DMA register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32WG_DMA
  * @{
  * @brief EFM32WG_DMA Register Declaration
@@ -75,7 +79,6 @@
   __IO uint32_t  RECT0;          /**< Channel 0 Rectangle Register  */
 
   uint32_t       RESERVED6[39];  /**< Reserved registers */
-
   DMA_CH_TypeDef CH[12];         /**< Channel registers */
 } DMA_TypeDef;                   /** @} */
 
@@ -1625,5 +1628,5 @@
 #define DMA_CH_CTRL_SOURCESEL_EBI                       (_DMA_CH_CTRL_SOURCESEL_EBI << 16)            /**< Shifted mode EBI for DMA_CH_CTRL */
 
 /** @} End of group EFM32WG_DMA */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_dma_ch.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_dma_ch.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32wg_dma_ch.h
  * @brief EFM32WG_DMA_CH register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @brief DMA_CH EFM32WG DMA CH
  *****************************************************************************/
 typedef struct
@@ -37,3 +41,6 @@
   __IO uint32_t CTRL; /**< Channel Control Register  */
 } DMA_CH_TypeDef;
 
+/** @} End of group Parts */
+
+

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_dma_descriptor.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_dma_descriptor.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32wg_dma_descriptor.h
  * @brief EFM32WG_DMA_DESCRIPTOR register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32WG_DMA_DESCRIPTOR
  * @{
  *****************************************************************************/
@@ -43,3 +47,6 @@
   __IO uint32_t    USER;       /**< DMA padding register, available for user */
 } DMA_DESCRIPTOR_TypeDef;      /** @} */
 
+/** @} End of group Parts */
+
+

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_dmactrl.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_dmactrl.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32wg_dmactrl.h
  * @brief EFM32WG_DMACTRL register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -29,6 +29,10 @@
  * any third party, arising from your use of this Software.
  *
  *****************************************************************************/
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
 
 /**************************************************************************//**
  * @defgroup EFM32WG_DMACTRL_BitFields
@@ -77,11 +81,11 @@
 #define _DMA_CTRL_DST_PROT_CTRL_MASK                   0x00E00000UL  /**< Protection flag for destination, bit mask */
 #define _DMA_CTRL_DST_PROT_CTRL_SHIFT                  21            /**< Protection flag for destination, shift value */
 #define DMA_CTRL_DST_PROT_PRIVILEGED                   0x00200000UL  /**< Privileged mode for destination */
-#define DMA_CTRL_DST_PROT_NON_PRIVILEGED               0x00000000UL  /**< Non-privileged mode for estination */
+#define DMA_CTRL_DST_PROT_NON_PRIVILEGED               0x00000000UL  /**< Non-privileged mode for destination */
 #define _DMA_CTRL_SRC_PROT_CTRL_MASK                   0x001C0000UL  /**< Protection flag for source, bit mask */
 #define _DMA_CTRL_SRC_PROT_CTRL_SHIFT                  18            /**< Protection flag for source, shift value */
 #define DMA_CTRL_SRC_PROT_PRIVILEGED                   0x00040000UL  /**< Privileged mode for destination */
-#define DMA_CTRL_SRC_PROT_NON_PRIVILEGED               0x00000000UL  /**< Non-privileged mode for estination */
+#define DMA_CTRL_SRC_PROT_NON_PRIVILEGED               0x00000000UL  /**< Non-privileged mode for destination */
 #define _DMA_CTRL_PROT_NON_PRIVILEGED                  0x00          /**< Protection bits to indicate non-privileged access */
 #define _DMA_CTRL_PROT_PRIVILEGED                      0x01          /**< Protection bits to indicate privileged access */
 #define _DMA_CTRL_R_POWER_MASK                         0x0003C000UL  /**< DMA arbitration mask */
@@ -132,5 +136,5 @@
 #define DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER_ALT     0x000000007UL /**< Peripheral scatter gather cycle type using alternate structure */
 
 /** @} End of group EFM32WG_DMA */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_dmareq.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_dmareq.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32wg_dmareq.h
  * @brief EFM32WG_DMAREQ register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -29,6 +29,10 @@
  * any third party, arising from your use of this Software.
  *
  *****************************************************************************/
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
 
 /**************************************************************************//**
  * @defgroup EFM32WG_DMAREQ_BitFields
@@ -95,5 +99,5 @@
 #define DMAREQ_EBI_DDEMPTY            ((51 << 16) + 3) /**< DMA channel select for EBI_DDEMPTY */
 
 /** @} End of group EFM32WG_DMAREQ */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_ebi.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_ebi.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32wg_ebi.h
  * @brief EFM32WG_EBI register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32WG_EBI
  * @{
  * @brief EFM32WG_EBI Register Declaration
@@ -1456,5 +1460,5 @@
 #define EBI_IEN_DDJIT_DEFAULT                     (_EBI_IEN_DDJIT_DEFAULT << 5)   /**< Shifted mode DEFAULT for EBI_IEN */
 
 /** @} End of group EFM32WG_EBI */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_emu.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_emu.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32wg_emu.h
  * @brief EFM32WG_EMU register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32WG_EMU
  * @{
  * @brief EFM32WG_EMU Register Declaration
@@ -340,5 +344,5 @@
 #define EMU_BUBODUNREGCAL_RANGE_DEFAULT     (_EMU_BUBODUNREGCAL_RANGE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_BUBODUNREGCAL */
 
 /** @} End of group EFM32WG_EMU */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_etm.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_etm.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32wg_etm.h
  * @brief EFM32WG_ETM register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32WG_ETM
  * @{
  * @brief EFM32WG_ETM Register Declaration
@@ -778,5 +782,5 @@
 #define ETM_ETMCIDR3_PREAMB_DEFAULT                   (_ETM_ETMCIDR3_PREAMB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCIDR3 */
 
 /** @} End of group EFM32WG_ETM */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_fpueh.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_fpueh.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32wg_fpueh.h
  * @brief EFM32WG_FPUEH register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32WG_FPUEH
  * @{
  * @brief EFM32WG_FPUEH Register Declaration
@@ -184,5 +188,5 @@
 #define FPUEH_IEN_FPIXC_DEFAULT     (_FPUEH_IEN_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IEN */
 
 /** @} End of group EFM32WG_FPUEH */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_gpio.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_gpio.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32wg_gpio.h
  * @brief EFM32WG_GPIO register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32WG_GPIO
  * @{
  * @brief EFM32WG_GPIO Register Declaration
@@ -1200,5 +1204,5 @@
 #define GPIO_EM4WUCAUSE_EM4WUCAUSE_E13                    (_GPIO_EM4WUCAUSE_EM4WUCAUSE_E13 << 0)     /**< Shifted mode E13 for GPIO_EM4WUCAUSE */
 
 /** @} End of group EFM32WG_GPIO */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_gpio_p.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_gpio_p.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32wg_gpio_p.h
  * @brief EFM32WG_GPIO_P register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @brief GPIO_P EFM32WG GPIO P
  *****************************************************************************/
 typedef struct
@@ -45,3 +49,6 @@
   __IO uint32_t PINLOCKN; /**< Port Unlocked Pins Register  */
 } GPIO_P_TypeDef;
 
+/** @} End of group Parts */
+
+

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_i2c.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_i2c.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32wg_i2c.h
  * @brief EFM32WG_I2C register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32WG_I2C
  * @{
  * @brief EFM32WG_I2C Register Declaration
@@ -697,5 +701,5 @@
 #define I2C_ROUTE_LOCATION_LOC6           (_I2C_ROUTE_LOCATION_LOC6 << 8)    /**< Shifted mode LOC6 for I2C_ROUTE */
 
 /** @} End of group EFM32WG_I2C */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_lcd.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_lcd.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32wg_lcd.h
  * @brief EFM32WG_LCD register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32WG_LCD
  * @{
  * @brief EFM32WG_LCD Register Declaration
@@ -591,5 +595,5 @@
 #define LCD_SEGD7L_SEGD7L_DEFAULT          (_LCD_SEGD7L_SEGD7L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD7L */
 
 /** @} End of group EFM32WG_LCD */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_lesense.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_lesense.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32wg_lesense.h
  * @brief EFM32WG_LESENSE register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32WG_LESENSE
  * @{
  * @brief EFM32WG_LESENSE Register Declaration
@@ -61,9 +65,10 @@
   __IO uint32_t       POWERDOWN;      /**< LESENSE RAM power-down register  */
 
   uint32_t            RESERVED0[105]; /**< Reserved registers */
+  LESENSE_ST_TypeDef  ST[16];         /**< Decoding states */
 
-  LESENSE_ST_TypeDef  ST[16];         /**< Decoding states */
   LESENSE_BUF_TypeDef BUF[16];        /**< Scanresult */
+
   LESENSE_CH_TypeDef  CH[16];         /**< Scanconfig */
 } LESENSE_TypeDef;                    /** @} */
 
@@ -1921,5 +1926,5 @@
 #define LESENSE_CH_EVAL_SCANRESINV_DEFAULT             (_LESENSE_CH_EVAL_SCANRESINV_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_CH_EVAL */
 
 /** @} End of group EFM32WG_LESENSE */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_lesense_buf.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_lesense_buf.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32wg_lesense_buf.h
  * @brief EFM32WG_LESENSE_BUF register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @brief LESENSE_BUF EFM32WG LESENSE BUF
  *****************************************************************************/
 typedef struct
@@ -37,3 +41,6 @@
   __IO uint32_t DATA; /**< Scan results  */
 } LESENSE_BUF_TypeDef;
 
+/** @} End of group Parts */
+
+

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_lesense_ch.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_lesense_ch.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32wg_lesense_ch.h
  * @brief EFM32WG_LESENSE_CH register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @brief LESENSE_CH EFM32WG LESENSE CH
  *****************************************************************************/
 typedef struct
@@ -37,7 +41,9 @@
   __IO uint32_t TIMING;       /**< Scan configuration  */
   __IO uint32_t INTERACT;     /**< Scan configuration  */
   __IO uint32_t EVAL;         /**< Scan configuration  */
-
   uint32_t      RESERVED0[1]; /**< Reserved future */
 } LESENSE_CH_TypeDef;
 
+/** @} End of group Parts */
+
+

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_lesense_st.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_lesense_st.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32wg_lesense_st.h
  * @brief EFM32WG_LESENSE_ST register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @brief LESENSE_ST EFM32WG LESENSE ST
  *****************************************************************************/
 typedef struct
@@ -38,3 +42,6 @@
   __IO uint32_t TCONFB; /**< State transition configuration B  */
 } LESENSE_ST_TypeDef;
 
+/** @} End of group Parts */
+
+

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_letimer.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_letimer.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32wg_letimer.h
  * @brief EFM32WG_LETIMER register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32WG_LETIMER
  * @{
  * @brief EFM32WG_LETIMER Register Declaration
@@ -404,5 +408,5 @@
 #define LETIMER_ROUTE_LOCATION_LOC3          (_LETIMER_ROUTE_LOCATION_LOC3 << 8)    /**< Shifted mode LOC3 for LETIMER_ROUTE */
 
 /** @} End of group EFM32WG_LETIMER */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_leuart.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_leuart.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32wg_leuart.h
  * @brief EFM32WG_LEUART register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32WG_LEUART
  * @{
  * @brief EFM32WG_LEUART Register Declaration
@@ -695,5 +699,5 @@
 #define LEUART_INPUT_RXPRS_DEFAULT               (_LEUART_INPUT_RXPRS_DEFAULT << 4)    /**< Shifted mode DEFAULT for LEUART_INPUT */
 
 /** @} End of group EFM32WG_LEUART */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_msc.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_msc.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32wg_msc.h
  * @brief EFM32WG_MSC register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32WG_MSC
  * @{
  * @brief EFM32WG_MSC Register Declaration
@@ -429,5 +433,5 @@
 #define MSC_MASSLOCK_LOCKKEY_UNLOCK             (_MSC_MASSLOCK_LOCKKEY_UNLOCK << 0)   /**< Shifted mode UNLOCK for MSC_MASSLOCK */
 
 /** @} End of group EFM32WG_MSC */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_pcnt.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_pcnt.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32wg_pcnt.h
  * @brief EFM32WG_PCNT register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32WG_PCNT
  * @{
  * @brief EFM32WG_PCNT Register Declaration
@@ -413,5 +417,5 @@
 #define PCNT_INPUT_S1PRSEN_DEFAULT        (_PCNT_INPUT_S1PRSEN_DEFAULT << 10) /**< Shifted mode DEFAULT for PCNT_INPUT */
 
 /** @} End of group EFM32WG_PCNT */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_prs.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_prs.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32wg_prs.h
  * @brief EFM32WG_PRS register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32WG_PRS
  * @{
  * @brief EFM32WG_PRS Register Declaration
@@ -41,7 +45,6 @@
   __IO uint32_t  ROUTE;        /**< I/O Routing Register  */
 
   uint32_t       RESERVED0[1]; /**< Reserved registers */
-
   PRS_CH_TypeDef CH[12];       /**< Channel registers */
 } PRS_TypeDef;                 /** @} */
 
@@ -448,5 +451,5 @@
 #define PRS_CH_CTRL_ASYNC_DEFAULT               (_PRS_CH_CTRL_ASYNC_DEFAULT << 28)          /**< Shifted mode DEFAULT for PRS_CH_CTRL */
 
 /** @} End of group EFM32WG_PRS */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_prs_ch.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_prs_ch.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32wg_prs_ch.h
  * @brief EFM32WG_PRS_CH register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @brief PRS_CH EFM32WG PRS CH
  *****************************************************************************/
 typedef struct
@@ -37,3 +41,6 @@
   __IO uint32_t CTRL; /**< Channel Control Register  */
 } PRS_CH_TypeDef;
 
+/** @} End of group Parts */
+
+

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_prs_signals.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_prs_signals.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32wg_prs_signals.h
  * @brief EFM32WG_PRS_SIGNALS register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @addtogroup EFM32WG_PRS_Signals
  * @{
  * @brief PRS Signal names
@@ -118,5 +122,5 @@
 #define PRS_LESENSE_DEC2         ((59 << 16) + 2) /**< PRS LESENSE Decoder PRS out 2 */
 
 /** @} End of group EFM32WG_PRS */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_rmu.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_rmu.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32wg_rmu.h
  * @brief EFM32WG_RMU register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32WG_RMU
  * @{
  * @brief EFM32WG_RMU Register Declaration
@@ -154,5 +158,5 @@
 #define RMU_CMD_RCCLR_DEFAULT                 (_RMU_CMD_RCCLR_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_CMD */
 
 /** @} End of group EFM32WG_RMU */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_romtable.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_romtable.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32wg_romtable.h
  * @brief EFM32WG_ROMTABLE register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32WG_ROMTABLE
  * @{
  * @brief Chip Information, Revision numbers
@@ -64,5 +68,5 @@
 #define _ROMTABLE_PID3_REVMINORLSB_SHIFT    4            /**< Least Significant Bits [3:0] of CHIP MINOR revision, shift */
 
 /** @} End of group EFM32WG_ROMTABLE */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_rtc.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_rtc.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32wg_rtc.h
  * @brief EFM32WG_RTC register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32WG_RTC
  * @{
  * @brief EFM32WG_RTC Register Declaration
@@ -210,5 +214,5 @@
 #define RTC_SYNCBUSY_COMP1_DEFAULT       (_RTC_SYNCBUSY_COMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_SYNCBUSY */
 
 /** @} End of group EFM32WG_RTC */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_timer.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_timer.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32wg_timer.h
  * @brief EFM32WG_TIMER register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32WG_TIMER
  * @{
  * @brief EFM32WG_TIMER Register Declaration
@@ -49,7 +53,6 @@
   __IO uint32_t    ROUTE;        /**< I/O Routing Register  */
 
   uint32_t         RESERVED0[1]; /**< Reserved registers */
-
   TIMER_CC_TypeDef CC[3];        /**< Compare/Capture Channel */
 
   uint32_t         RESERVED1[4]; /**< Reserved for future use **/
@@ -181,7 +184,7 @@
 #define _TIMER_CTRL_ATI_MASK                       0x10000000UL                             /**< Bit mask for TIMER_ATI */
 #define _TIMER_CTRL_ATI_DEFAULT                    0x00000000UL                             /**< Mode DEFAULT for TIMER_CTRL */
 #define TIMER_CTRL_ATI_DEFAULT                     (_TIMER_CTRL_ATI_DEFAULT << 28)          /**< Shifted mode DEFAULT for TIMER_CTRL */
-#define TIMER_CTRL_RSSCOIST                        (0x1UL << 29)                            /**< Reload-Start Sets Compare Ouptut initial State */
+#define TIMER_CTRL_RSSCOIST                        (0x1UL << 29)                            /**< Reload-Start Sets Compare Output initial State */
 #define _TIMER_CTRL_RSSCOIST_SHIFT                 29                                       /**< Shift value for TIMER_RSSCOIST */
 #define _TIMER_CTRL_RSSCOIST_MASK                  0x20000000UL                             /**< Bit mask for TIMER_RSSCOIST */
 #define _TIMER_CTRL_RSSCOIST_DEFAULT               0x00000000UL                             /**< Mode DEFAULT for TIMER_CTRL */
@@ -516,15 +519,15 @@
 #define TIMER_ROUTE_CDTI2PEN_DEFAULT               (_TIMER_ROUTE_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_ROUTE */
 #define _TIMER_ROUTE_LOCATION_SHIFT                16                                    /**< Shift value for TIMER_LOCATION */
 #define _TIMER_ROUTE_LOCATION_MASK                 0x70000UL                             /**< Bit mask for TIMER_LOCATION */
+#define _TIMER_ROUTE_LOCATION_LOC0                 0x00000000UL                          /**< Mode LOC0 for TIMER_ROUTE */
 #define _TIMER_ROUTE_LOCATION_DEFAULT              0x00000000UL                          /**< Mode DEFAULT for TIMER_ROUTE */
-#define _TIMER_ROUTE_LOCATION_LOC0                 0x00000000UL                          /**< Mode LOC0 for TIMER_ROUTE */
 #define _TIMER_ROUTE_LOCATION_LOC1                 0x00000001UL                          /**< Mode LOC1 for TIMER_ROUTE */
 #define _TIMER_ROUTE_LOCATION_LOC2                 0x00000002UL                          /**< Mode LOC2 for TIMER_ROUTE */
 #define _TIMER_ROUTE_LOCATION_LOC3                 0x00000003UL                          /**< Mode LOC3 for TIMER_ROUTE */
 #define _TIMER_ROUTE_LOCATION_LOC4                 0x00000004UL                          /**< Mode LOC4 for TIMER_ROUTE */
 #define _TIMER_ROUTE_LOCATION_LOC5                 0x00000005UL                          /**< Mode LOC5 for TIMER_ROUTE */
+#define TIMER_ROUTE_LOCATION_LOC0                  (_TIMER_ROUTE_LOCATION_LOC0 << 16)    /**< Shifted mode LOC0 for TIMER_ROUTE */
 #define TIMER_ROUTE_LOCATION_DEFAULT               (_TIMER_ROUTE_LOCATION_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_ROUTE */
-#define TIMER_ROUTE_LOCATION_LOC0                  (_TIMER_ROUTE_LOCATION_LOC0 << 16)    /**< Shifted mode LOC0 for TIMER_ROUTE */
 #define TIMER_ROUTE_LOCATION_LOC1                  (_TIMER_ROUTE_LOCATION_LOC1 << 16)    /**< Shifted mode LOC1 for TIMER_ROUTE */
 #define TIMER_ROUTE_LOCATION_LOC2                  (_TIMER_ROUTE_LOCATION_LOC2 << 16)    /**< Shifted mode LOC2 for TIMER_ROUTE */
 #define TIMER_ROUTE_LOCATION_LOC3                  (_TIMER_ROUTE_LOCATION_LOC3 << 16)    /**< Shifted mode LOC3 for TIMER_ROUTE */
@@ -961,5 +964,5 @@
 #define TIMER_DTLOCK_LOCKKEY_UNLOCK                (_TIMER_DTLOCK_LOCKKEY_UNLOCK << 0)   /**< Shifted mode UNLOCK for TIMER_DTLOCK */
 
 /** @} End of group EFM32WG_TIMER */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_timer_cc.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_timer_cc.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32wg_timer_cc.h
  * @brief EFM32WG_TIMER_CC register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @brief TIMER_CC EFM32WG TIMER CC
  *****************************************************************************/
 typedef struct
@@ -40,3 +44,6 @@
   __IO uint32_t CCVB; /**< CC Channel Buffer Register  */
 } TIMER_CC_TypeDef;
 
+/** @} End of group Parts */
+
+

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_uart.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_uart.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32wg_uart.h
  * @brief EFM32WG_UART register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -29,6 +29,10 @@
  * any third party, arising from your use of this Software.
  *
  *****************************************************************************/
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
 
 /**************************************************************************//**
  * @defgroup EFM32WG_UART_BitFields
@@ -1123,5 +1127,5 @@
 #define UART_I2SCTRL_FORMAT_W8D8             (_UART_I2SCTRL_FORMAT_W8D8 << 8)      /**< Shifted mode W8D8 for UART_I2SCTRL */
 
 /** @} End of group EFM32WG_UART */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_usart.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_usart.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32wg_usart.h
  * @brief EFM32WG_USART register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32WG_USART
  * @{
  * @brief EFM32WG_USART Register Declaration
@@ -1155,5 +1159,5 @@
 #define USART_I2SCTRL_FORMAT_W8D8             (_USART_I2SCTRL_FORMAT_W8D8 << 8)      /**< Shifted mode W8D8 for USART_I2SCTRL */
 
 /** @} End of group EFM32WG_USART */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_usb.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_usb.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32wg_usb.h
  * @brief EFM32WG_USB register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32WG_USB
  * @{
  * @brief EFM32WG_USB Register Declaration
@@ -81,7 +85,6 @@
   __IO uint32_t    HPRT;              /**< Host Port Control and Status Register  */
 
   uint32_t         RESERVED6[47];     /**< Reserved registers */
-
   USB_HC_TypeDef   HC[14];            /**< Host Channel Registers */
 
   uint32_t         RESERVED7[80];     /**< Reserved for future use **/
@@ -110,7 +113,6 @@
   __I uint32_t     DIEP0TXFSTS;       /**< Device IN Endpoint 0 Transmit FIFO Status Register  */
 
   uint32_t         RESERVED14[1];     /**< Reserved registers */
-
   USB_DIEP_TypeDef DIEP[6];           /**< Device IN Endpoint x+1 Registers */
 
   uint32_t         RESERVED15[72];    /**< Reserved for future use **/
@@ -122,70 +124,54 @@
   __IO uint32_t    DOEP0DMAADDR;      /**< Device OUT Endpoint 0 DMA Address Register  */
 
   uint32_t         RESERVED18[2];     /**< Reserved registers */
-
   USB_DOEP_TypeDef DOEP[6];           /**< Device OUT Endpoint x+1 Registers */
 
   uint32_t         RESERVED19[136];   /**< Reserved for future use **/
   __IO uint32_t    PCGCCTL;           /**< Power and Clock Gating Control Register  */
 
   uint32_t         RESERVED20[127];   /**< Reserved registers */
-
   __IO uint32_t    FIFO0D[512];       /**< Device EP 0/Host Channel 0 FIFO  */
 
   uint32_t         RESERVED21[512];   /**< Reserved registers */
-
   __IO uint32_t    FIFO1D[512];       /**< Device EP 1/Host Channel 1 FIFO  */
 
   uint32_t         RESERVED22[512];   /**< Reserved registers */
-
   __IO uint32_t    FIFO2D[512];       /**< Device EP 2/Host Channel 2 FIFO  */
 
   uint32_t         RESERVED23[512];   /**< Reserved registers */
-
   __IO uint32_t    FIFO3D[512];       /**< Device EP 3/Host Channel 3 FIFO  */
 
   uint32_t         RESERVED24[512];   /**< Reserved registers */
-
   __IO uint32_t    FIFO4D[512];       /**< Device EP 4/Host Channel 4 FIFO  */
 
   uint32_t         RESERVED25[512];   /**< Reserved registers */
-
   __IO uint32_t    FIFO5D[512];       /**< Device EP 5/Host Channel 5 FIFO  */
 
   uint32_t         RESERVED26[512];   /**< Reserved registers */
-
   __IO uint32_t    FIFO6D[512];       /**< Device EP 6/Host Channel 6 FIFO  */
 
   uint32_t         RESERVED27[512];   /**< Reserved registers */
-
   __IO uint32_t    FIFO7D[512];       /**< Host Channel 7 FIFO  */
 
   uint32_t         RESERVED28[512];   /**< Reserved registers */
-
   __IO uint32_t    FIFO8D[512];       /**< Host Channel 8 FIFO  */
 
   uint32_t         RESERVED29[512];   /**< Reserved registers */
-
   __IO uint32_t    FIFO9D[512];       /**< Host Channel 9 FIFO  */
 
   uint32_t         RESERVED30[512];   /**< Reserved registers */
-
   __IO uint32_t    FIFO10D[512];      /**< Host Channel 10 FIFO  */
 
   uint32_t         RESERVED31[512];   /**< Reserved registers */
-
   __IO uint32_t    FIFO11D[512];      /**< Host Channel 11 FIFO  */
 
   uint32_t         RESERVED32[512];   /**< Reserved registers */
-
   __IO uint32_t    FIFO12D[512];      /**< Host Channel 12 FIFO  */
 
   uint32_t         RESERVED33[512];   /**< Reserved registers */
-
   __IO uint32_t    FIFO13D[512];      /**< Host Channel 13 FIFO  */
 
   uint32_t         RESERVED34[17920]; /**< Reserved registers */
-
   __IO uint32_t    FIFORAM[512];      /**< Direct Access to Data FIFO RAM for Debugging (2 KB)  */
 } USB_TypeDef;                        /** @} */
 
@@ -321,12 +307,12 @@
 /* Bit fields for USB GOTGCTL */
 #define _USB_GOTGCTL_RESETVALUE                    0x00010000UL                             /**< Default value for USB_GOTGCTL */
 #define _USB_GOTGCTL_MASK                          0x001F0FFFUL                             /**< Mask for USB_GOTGCTL */
-#define USB_GOTGCTL_SESREQSCS                      (0x1UL << 0)                             /**< Session Request Success (device only) */
+#define USB_GOTGCTL_SESREQSCS                      (0x1UL << 0)                             /**< Session Request Success device only */
 #define _USB_GOTGCTL_SESREQSCS_SHIFT               0                                        /**< Shift value for USB_SESREQSCS */
 #define _USB_GOTGCTL_SESREQSCS_MASK                0x1UL                                    /**< Bit mask for USB_SESREQSCS */
 #define _USB_GOTGCTL_SESREQSCS_DEFAULT             0x00000000UL                             /**< Mode DEFAULT for USB_GOTGCTL */
 #define USB_GOTGCTL_SESREQSCS_DEFAULT              (_USB_GOTGCTL_SESREQSCS_DEFAULT << 0)    /**< Shifted mode DEFAULT for USB_GOTGCTL */
-#define USB_GOTGCTL_SESREQ                         (0x1UL << 1)                             /**< Session Request (device only) */
+#define USB_GOTGCTL_SESREQ                         (0x1UL << 1)                             /**< Session Request device only */
 #define _USB_GOTGCTL_SESREQ_SHIFT                  1                                        /**< Shift value for USB_SESREQ */
 #define _USB_GOTGCTL_SESREQ_MASK                   0x2UL                                    /**< Bit mask for USB_SESREQ */
 #define _USB_GOTGCTL_SESREQ_DEFAULT                0x00000000UL                             /**< Mode DEFAULT for USB_GOTGCTL */
@@ -361,27 +347,27 @@
 #define _USB_GOTGCTL_AVALIDOVVAL_MASK              0x80UL                                   /**< Bit mask for USB_AVALIDOVVAL */
 #define _USB_GOTGCTL_AVALIDOVVAL_DEFAULT           0x00000000UL                             /**< Mode DEFAULT for USB_GOTGCTL */
 #define USB_GOTGCTL_AVALIDOVVAL_DEFAULT            (_USB_GOTGCTL_AVALIDOVVAL_DEFAULT << 7)  /**< Shifted mode DEFAULT for USB_GOTGCTL */
-#define USB_GOTGCTL_HSTNEGSCS                      (0x1UL << 8)                             /**< Host Negotiation Success (device only) */
+#define USB_GOTGCTL_HSTNEGSCS                      (0x1UL << 8)                             /**< Host Negotiation Success device only */
 #define _USB_GOTGCTL_HSTNEGSCS_SHIFT               8                                        /**< Shift value for USB_HSTNEGSCS */
 #define _USB_GOTGCTL_HSTNEGSCS_MASK                0x100UL                                  /**< Bit mask for USB_HSTNEGSCS */
 #define _USB_GOTGCTL_HSTNEGSCS_DEFAULT             0x00000000UL                             /**< Mode DEFAULT for USB_GOTGCTL */
 #define USB_GOTGCTL_HSTNEGSCS_DEFAULT              (_USB_GOTGCTL_HSTNEGSCS_DEFAULT << 8)    /**< Shifted mode DEFAULT for USB_GOTGCTL */
-#define USB_GOTGCTL_HNPREQ                         (0x1UL << 9)                             /**< HNP Request (device only) */
+#define USB_GOTGCTL_HNPREQ                         (0x1UL << 9)                             /**< HNP Request device only */
 #define _USB_GOTGCTL_HNPREQ_SHIFT                  9                                        /**< Shift value for USB_HNPREQ */
 #define _USB_GOTGCTL_HNPREQ_MASK                   0x200UL                                  /**< Bit mask for USB_HNPREQ */
 #define _USB_GOTGCTL_HNPREQ_DEFAULT                0x00000000UL                             /**< Mode DEFAULT for USB_GOTGCTL */
 #define USB_GOTGCTL_HNPREQ_DEFAULT                 (_USB_GOTGCTL_HNPREQ_DEFAULT << 9)       /**< Shifted mode DEFAULT for USB_GOTGCTL */
-#define USB_GOTGCTL_HSTSETHNPEN                    (0x1UL << 10)                            /**< Host Set HNP Enable (host only) */
+#define USB_GOTGCTL_HSTSETHNPEN                    (0x1UL << 10)                            /**< Host Set HNP Enable host only */
 #define _USB_GOTGCTL_HSTSETHNPEN_SHIFT             10                                       /**< Shift value for USB_HSTSETHNPEN */
 #define _USB_GOTGCTL_HSTSETHNPEN_MASK              0x400UL                                  /**< Bit mask for USB_HSTSETHNPEN */
 #define _USB_GOTGCTL_HSTSETHNPEN_DEFAULT           0x00000000UL                             /**< Mode DEFAULT for USB_GOTGCTL */
 #define USB_GOTGCTL_HSTSETHNPEN_DEFAULT            (_USB_GOTGCTL_HSTSETHNPEN_DEFAULT << 10) /**< Shifted mode DEFAULT for USB_GOTGCTL */
-#define USB_GOTGCTL_DEVHNPEN                       (0x1UL << 11)                            /**< Device HNP Enabled (device only) */
+#define USB_GOTGCTL_DEVHNPEN                       (0x1UL << 11)                            /**< Device HNP Enabled device only */
 #define _USB_GOTGCTL_DEVHNPEN_SHIFT                11                                       /**< Shift value for USB_DEVHNPEN */
 #define _USB_GOTGCTL_DEVHNPEN_MASK                 0x800UL                                  /**< Bit mask for USB_DEVHNPEN */
 #define _USB_GOTGCTL_DEVHNPEN_DEFAULT              0x00000000UL                             /**< Mode DEFAULT for USB_GOTGCTL */
 #define USB_GOTGCTL_DEVHNPEN_DEFAULT               (_USB_GOTGCTL_DEVHNPEN_DEFAULT << 11)    /**< Shifted mode DEFAULT for USB_GOTGCTL */
-#define USB_GOTGCTL_CONIDSTS                       (0x1UL << 16)                            /**< Connector ID Status (host and device) */
+#define USB_GOTGCTL_CONIDSTS                       (0x1UL << 16)                            /**< Connector ID Status host and device */
 #define _USB_GOTGCTL_CONIDSTS_SHIFT                16                                       /**< Shift value for USB_CONIDSTS */
 #define _USB_GOTGCTL_CONIDSTS_MASK                 0x10000UL                                /**< Bit mask for USB_CONIDSTS */
 #define _USB_GOTGCTL_CONIDSTS_A                    0x00000000UL                             /**< Mode A for USB_GOTGCTL */
@@ -390,7 +376,7 @@
 #define USB_GOTGCTL_CONIDSTS_A                     (_USB_GOTGCTL_CONIDSTS_A << 16)          /**< Shifted mode A for USB_GOTGCTL */
 #define USB_GOTGCTL_CONIDSTS_DEFAULT               (_USB_GOTGCTL_CONIDSTS_DEFAULT << 16)    /**< Shifted mode DEFAULT for USB_GOTGCTL */
 #define USB_GOTGCTL_CONIDSTS_B                     (_USB_GOTGCTL_CONIDSTS_B << 16)          /**< Shifted mode B for USB_GOTGCTL */
-#define USB_GOTGCTL_DBNCTIME                       (0x1UL << 17)                            /**< Long/Short Debounce Time (host only) */
+#define USB_GOTGCTL_DBNCTIME                       (0x1UL << 17)                            /**< Long/Short Debounce Time host only */
 #define _USB_GOTGCTL_DBNCTIME_SHIFT                17                                       /**< Shift value for USB_DBNCTIME */
 #define _USB_GOTGCTL_DBNCTIME_MASK                 0x20000UL                                /**< Bit mask for USB_DBNCTIME */
 #define _USB_GOTGCTL_DBNCTIME_DEFAULT              0x00000000UL                             /**< Mode DEFAULT for USB_GOTGCTL */
@@ -399,12 +385,12 @@
 #define USB_GOTGCTL_DBNCTIME_DEFAULT               (_USB_GOTGCTL_DBNCTIME_DEFAULT << 17)    /**< Shifted mode DEFAULT for USB_GOTGCTL */
 #define USB_GOTGCTL_DBNCTIME_LONG                  (_USB_GOTGCTL_DBNCTIME_LONG << 17)       /**< Shifted mode LONG for USB_GOTGCTL */
 #define USB_GOTGCTL_DBNCTIME_SHORT                 (_USB_GOTGCTL_DBNCTIME_SHORT << 17)      /**< Shifted mode SHORT for USB_GOTGCTL */
-#define USB_GOTGCTL_ASESVLD                        (0x1UL << 18)                            /**< A-Session Valid (host only) */
+#define USB_GOTGCTL_ASESVLD                        (0x1UL << 18)                            /**< A-Session Valid host only */
 #define _USB_GOTGCTL_ASESVLD_SHIFT                 18                                       /**< Shift value for USB_ASESVLD */
 #define _USB_GOTGCTL_ASESVLD_MASK                  0x40000UL                                /**< Bit mask for USB_ASESVLD */
 #define _USB_GOTGCTL_ASESVLD_DEFAULT               0x00000000UL                             /**< Mode DEFAULT for USB_GOTGCTL */
 #define USB_GOTGCTL_ASESVLD_DEFAULT                (_USB_GOTGCTL_ASESVLD_DEFAULT << 18)     /**< Shifted mode DEFAULT for USB_GOTGCTL */
-#define USB_GOTGCTL_BSESVLD                        (0x1UL << 19)                            /**< B-Session Valid (device only) */
+#define USB_GOTGCTL_BSESVLD                        (0x1UL << 19)                            /**< B-Session Valid device only */
 #define _USB_GOTGCTL_BSESVLD_SHIFT                 19                                       /**< Shift value for USB_BSESVLD */
 #define _USB_GOTGCTL_BSESVLD_MASK                  0x80000UL                                /**< Bit mask for USB_BSESVLD */
 #define _USB_GOTGCTL_BSESVLD_DEFAULT               0x00000000UL                             /**< Mode DEFAULT for USB_GOTGCTL */
@@ -422,32 +408,32 @@
 /* Bit fields for USB GOTGINT */
 #define _USB_GOTGINT_RESETVALUE                    0x00000000UL                                 /**< Default value for USB_GOTGINT */
 #define _USB_GOTGINT_MASK                          0x000E0304UL                                 /**< Mask for USB_GOTGINT */
-#define USB_GOTGINT_SESENDDET                      (0x1UL << 2)                                 /**< Session End Detected (host and device) */
+#define USB_GOTGINT_SESENDDET                      (0x1UL << 2)                                 /**< Session End Detected host and device */
 #define _USB_GOTGINT_SESENDDET_SHIFT               2                                            /**< Shift value for USB_SESENDDET */
 #define _USB_GOTGINT_SESENDDET_MASK                0x4UL                                        /**< Bit mask for USB_SESENDDET */
 #define _USB_GOTGINT_SESENDDET_DEFAULT             0x00000000UL                                 /**< Mode DEFAULT for USB_GOTGINT */
 #define USB_GOTGINT_SESENDDET_DEFAULT              (_USB_GOTGINT_SESENDDET_DEFAULT << 2)        /**< Shifted mode DEFAULT for USB_GOTGINT */
-#define USB_GOTGINT_SESREQSUCSTSCHNG               (0x1UL << 8)                                 /**< Session Request Success Status Change (host and device) */
+#define USB_GOTGINT_SESREQSUCSTSCHNG               (0x1UL << 8)                                 /**< Session Request Success Status Change host and device */
 #define _USB_GOTGINT_SESREQSUCSTSCHNG_SHIFT        8                                            /**< Shift value for USB_SESREQSUCSTSCHNG */
 #define _USB_GOTGINT_SESREQSUCSTSCHNG_MASK         0x100UL                                      /**< Bit mask for USB_SESREQSUCSTSCHNG */
 #define _USB_GOTGINT_SESREQSUCSTSCHNG_DEFAULT      0x00000000UL                                 /**< Mode DEFAULT for USB_GOTGINT */
 #define USB_GOTGINT_SESREQSUCSTSCHNG_DEFAULT       (_USB_GOTGINT_SESREQSUCSTSCHNG_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_GOTGINT */
-#define USB_GOTGINT_HSTNEGSUCSTSCHNG               (0x1UL << 9)                                 /**< Host Negotiation Success Status Change (host and device) */
+#define USB_GOTGINT_HSTNEGSUCSTSCHNG               (0x1UL << 9)                                 /**< Host Negotiation Success Status Change host and device */
 #define _USB_GOTGINT_HSTNEGSUCSTSCHNG_SHIFT        9                                            /**< Shift value for USB_HSTNEGSUCSTSCHNG */
 #define _USB_GOTGINT_HSTNEGSUCSTSCHNG_MASK         0x200UL                                      /**< Bit mask for USB_HSTNEGSUCSTSCHNG */
 #define _USB_GOTGINT_HSTNEGSUCSTSCHNG_DEFAULT      0x00000000UL                                 /**< Mode DEFAULT for USB_GOTGINT */
 #define USB_GOTGINT_HSTNEGSUCSTSCHNG_DEFAULT       (_USB_GOTGINT_HSTNEGSUCSTSCHNG_DEFAULT << 9) /**< Shifted mode DEFAULT for USB_GOTGINT */
-#define USB_GOTGINT_HSTNEGDET                      (0x1UL << 17)                                /**< Host Negotiation Detected (host and device) */
+#define USB_GOTGINT_HSTNEGDET                      (0x1UL << 17)                                /**< Host Negotiation Detected host and device */
 #define _USB_GOTGINT_HSTNEGDET_SHIFT               17                                           /**< Shift value for USB_HSTNEGDET */
 #define _USB_GOTGINT_HSTNEGDET_MASK                0x20000UL                                    /**< Bit mask for USB_HSTNEGDET */
 #define _USB_GOTGINT_HSTNEGDET_DEFAULT             0x00000000UL                                 /**< Mode DEFAULT for USB_GOTGINT */
 #define USB_GOTGINT_HSTNEGDET_DEFAULT              (_USB_GOTGINT_HSTNEGDET_DEFAULT << 17)       /**< Shifted mode DEFAULT for USB_GOTGINT */
-#define USB_GOTGINT_ADEVTOUTCHG                    (0x1UL << 18)                                /**< A-Device Timeout Change (host and device) */
+#define USB_GOTGINT_ADEVTOUTCHG                    (0x1UL << 18)                                /**< A-Device Timeout Change host and device */
 #define _USB_GOTGINT_ADEVTOUTCHG_SHIFT             18                                           /**< Shift value for USB_ADEVTOUTCHG */
 #define _USB_GOTGINT_ADEVTOUTCHG_MASK              0x40000UL                                    /**< Bit mask for USB_ADEVTOUTCHG */
 #define _USB_GOTGINT_ADEVTOUTCHG_DEFAULT           0x00000000UL                                 /**< Mode DEFAULT for USB_GOTGINT */
 #define USB_GOTGINT_ADEVTOUTCHG_DEFAULT            (_USB_GOTGINT_ADEVTOUTCHG_DEFAULT << 18)     /**< Shifted mode DEFAULT for USB_GOTGINT */
-#define USB_GOTGINT_DBNCEDONE                      (0x1UL << 19)                                /**< Debounce Done (host only) */
+#define USB_GOTGINT_DBNCEDONE                      (0x1UL << 19)                                /**< Debounce Done host only */
 #define _USB_GOTGINT_DBNCEDONE_SHIFT               19                                           /**< Shift value for USB_DBNCEDONE */
 #define _USB_GOTGINT_DBNCEDONE_MASK                0x80000UL                                    /**< Bit mask for USB_DBNCEDONE */
 #define _USB_GOTGINT_DBNCEDONE_DEFAULT             0x00000000UL                                 /**< Mode DEFAULT for USB_GOTGINT */
@@ -456,7 +442,7 @@
 /* Bit fields for USB GAHBCFG */
 #define _USB_GAHBCFG_RESETVALUE                    0x00000000UL                                /**< Default value for USB_GAHBCFG */
 #define _USB_GAHBCFG_MASK                          0x006001BFUL                                /**< Mask for USB_GAHBCFG */
-#define USB_GAHBCFG_GLBLINTRMSK                    (0x1UL << 0)                                /**< Global Interrupt Mask (host and device) */
+#define USB_GAHBCFG_GLBLINTRMSK                    (0x1UL << 0)                                /**< Global Interrupt Mask host and device */
 #define _USB_GAHBCFG_GLBLINTRMSK_SHIFT             0                                           /**< Shift value for USB_GLBLINTRMSK */
 #define _USB_GAHBCFG_GLBLINTRMSK_MASK              0x1UL                                       /**< Bit mask for USB_GLBLINTRMSK */
 #define _USB_GAHBCFG_GLBLINTRMSK_DEFAULT           0x00000000UL                                /**< Mode DEFAULT for USB_GAHBCFG */
@@ -475,12 +461,12 @@
 #define USB_GAHBCFG_HBSTLEN_INCR4                  (_USB_GAHBCFG_HBSTLEN_INCR4 << 1)           /**< Shifted mode INCR4 for USB_GAHBCFG */
 #define USB_GAHBCFG_HBSTLEN_INCR8                  (_USB_GAHBCFG_HBSTLEN_INCR8 << 1)           /**< Shifted mode INCR8 for USB_GAHBCFG */
 #define USB_GAHBCFG_HBSTLEN_INCR16                 (_USB_GAHBCFG_HBSTLEN_INCR16 << 1)          /**< Shifted mode INCR16 for USB_GAHBCFG */
-#define USB_GAHBCFG_DMAEN                          (0x1UL << 5)                                /**< DMA Enable (host and device) */
+#define USB_GAHBCFG_DMAEN                          (0x1UL << 5)                                /**< DMA Enable host and device */
 #define _USB_GAHBCFG_DMAEN_SHIFT                   5                                           /**< Shift value for USB_DMAEN */
 #define _USB_GAHBCFG_DMAEN_MASK                    0x20UL                                      /**< Bit mask for USB_DMAEN */
 #define _USB_GAHBCFG_DMAEN_DEFAULT                 0x00000000UL                                /**< Mode DEFAULT for USB_GAHBCFG */
 #define USB_GAHBCFG_DMAEN_DEFAULT                  (_USB_GAHBCFG_DMAEN_DEFAULT << 5)           /**< Shifted mode DEFAULT for USB_GAHBCFG */
-#define USB_GAHBCFG_NPTXFEMPLVL                    (0x1UL << 7)                                /**< Non-Periodic TxFIFO Empty Level (host and device) */
+#define USB_GAHBCFG_NPTXFEMPLVL                    (0x1UL << 7)                                /**< Non-Periodic TxFIFO Empty Level host and device */
 #define _USB_GAHBCFG_NPTXFEMPLVL_SHIFT             7                                           /**< Shift value for USB_NPTXFEMPLVL */
 #define _USB_GAHBCFG_NPTXFEMPLVL_MASK              0x80UL                                      /**< Bit mask for USB_NPTXFEMPLVL */
 #define _USB_GAHBCFG_NPTXFEMPLVL_DEFAULT           0x00000000UL                                /**< Mode DEFAULT for USB_GAHBCFG */
@@ -489,7 +475,7 @@
 #define USB_GAHBCFG_NPTXFEMPLVL_DEFAULT            (_USB_GAHBCFG_NPTXFEMPLVL_DEFAULT << 7)     /**< Shifted mode DEFAULT for USB_GAHBCFG */
 #define USB_GAHBCFG_NPTXFEMPLVL_HALFEMPTY          (_USB_GAHBCFG_NPTXFEMPLVL_HALFEMPTY << 7)   /**< Shifted mode HALFEMPTY for USB_GAHBCFG */
 #define USB_GAHBCFG_NPTXFEMPLVL_EMPTY              (_USB_GAHBCFG_NPTXFEMPLVL_EMPTY << 7)       /**< Shifted mode EMPTY for USB_GAHBCFG */
-#define USB_GAHBCFG_PTXFEMPLVL                     (0x1UL << 8)                                /**< Periodic TxFIFO Empty Level (host only) */
+#define USB_GAHBCFG_PTXFEMPLVL                     (0x1UL << 8)                                /**< Periodic TxFIFO Empty Level host only */
 #define _USB_GAHBCFG_PTXFEMPLVL_SHIFT              8                                           /**< Shift value for USB_PTXFEMPLVL */
 #define _USB_GAHBCFG_PTXFEMPLVL_MASK               0x100UL                                     /**< Bit mask for USB_PTXFEMPLVL */
 #define _USB_GAHBCFG_PTXFEMPLVL_DEFAULT            0x00000000UL                                /**< Mode DEFAULT for USB_GAHBCFG */
@@ -516,17 +502,17 @@
 #define _USB_GUSBCFG_TOUTCAL_MASK                  0x7UL                                       /**< Bit mask for USB_TOUTCAL */
 #define _USB_GUSBCFG_TOUTCAL_DEFAULT               0x00000000UL                                /**< Mode DEFAULT for USB_GUSBCFG */
 #define USB_GUSBCFG_TOUTCAL_DEFAULT                (_USB_GUSBCFG_TOUTCAL_DEFAULT << 0)         /**< Shifted mode DEFAULT for USB_GUSBCFG */
-#define USB_GUSBCFG_FSINTF                         (0x1UL << 5)                                /**< Full-Speed Serial Interface Select (host and device) */
+#define USB_GUSBCFG_FSINTF                         (0x1UL << 5)                                /**< Full-Speed Serial Interface Select host and device */
 #define _USB_GUSBCFG_FSINTF_SHIFT                  5                                           /**< Shift value for USB_FSINTF */
 #define _USB_GUSBCFG_FSINTF_MASK                   0x20UL                                      /**< Bit mask for USB_FSINTF */
 #define _USB_GUSBCFG_FSINTF_DEFAULT                0x00000000UL                                /**< Mode DEFAULT for USB_GUSBCFG */
 #define USB_GUSBCFG_FSINTF_DEFAULT                 (_USB_GUSBCFG_FSINTF_DEFAULT << 5)          /**< Shifted mode DEFAULT for USB_GUSBCFG */
-#define USB_GUSBCFG_SRPCAP                         (0x1UL << 8)                                /**< SRP-Capable (host and device) */
+#define USB_GUSBCFG_SRPCAP                         (0x1UL << 8)                                /**< SRP-Capable host and device */
 #define _USB_GUSBCFG_SRPCAP_SHIFT                  8                                           /**< Shift value for USB_SRPCAP */
 #define _USB_GUSBCFG_SRPCAP_MASK                   0x100UL                                     /**< Bit mask for USB_SRPCAP */
 #define _USB_GUSBCFG_SRPCAP_DEFAULT                0x00000000UL                                /**< Mode DEFAULT for USB_GUSBCFG */
 #define USB_GUSBCFG_SRPCAP_DEFAULT                 (_USB_GUSBCFG_SRPCAP_DEFAULT << 8)          /**< Shifted mode DEFAULT for USB_GUSBCFG */
-#define USB_GUSBCFG_HNPCAP                         (0x1UL << 9)                                /**< HNP-Capable (host and device) */
+#define USB_GUSBCFG_HNPCAP                         (0x1UL << 9)                                /**< HNP-Capable host and device */
 #define _USB_GUSBCFG_HNPCAP_SHIFT                  9                                           /**< Shift value for USB_HNPCAP */
 #define _USB_GUSBCFG_HNPCAP_MASK                   0x200UL                                     /**< Bit mask for USB_HNPCAP */
 #define _USB_GUSBCFG_HNPCAP_DEFAULT                0x00000000UL                                /**< Mode DEFAULT for USB_GUSBCFG */
@@ -535,7 +521,7 @@
 #define _USB_GUSBCFG_USBTRDTIM_MASK                0x3C00UL                                    /**< Bit mask for USB_USBTRDTIM */
 #define _USB_GUSBCFG_USBTRDTIM_DEFAULT             0x00000005UL                                /**< Mode DEFAULT for USB_GUSBCFG */
 #define USB_GUSBCFG_USBTRDTIM_DEFAULT              (_USB_GUSBCFG_USBTRDTIM_DEFAULT << 10)      /**< Shifted mode DEFAULT for USB_GUSBCFG */
-#define USB_GUSBCFG_TERMSELDLPULSE                 (0x1UL << 22)                               /**< TermSel DLine Pulsing Selection (device only) */
+#define USB_GUSBCFG_TERMSELDLPULSE                 (0x1UL << 22)                               /**< TermSel DLine Pulsing Selection device only */
 #define _USB_GUSBCFG_TERMSELDLPULSE_SHIFT          22                                          /**< Shift value for USB_TERMSELDLPULSE */
 #define _USB_GUSBCFG_TERMSELDLPULSE_MASK           0x400000UL                                  /**< Bit mask for USB_TERMSELDLPULSE */
 #define _USB_GUSBCFG_TERMSELDLPULSE_DEFAULT        0x00000000UL                                /**< Mode DEFAULT for USB_GUSBCFG */
@@ -544,22 +530,22 @@
 #define USB_GUSBCFG_TERMSELDLPULSE_DEFAULT         (_USB_GUSBCFG_TERMSELDLPULSE_DEFAULT << 22) /**< Shifted mode DEFAULT for USB_GUSBCFG */
 #define USB_GUSBCFG_TERMSELDLPULSE_TXVALID         (_USB_GUSBCFG_TERMSELDLPULSE_TXVALID << 22) /**< Shifted mode TXVALID for USB_GUSBCFG */
 #define USB_GUSBCFG_TERMSELDLPULSE_TERMSEL         (_USB_GUSBCFG_TERMSELDLPULSE_TERMSEL << 22) /**< Shifted mode TERMSEL for USB_GUSBCFG */
-#define USB_GUSBCFG_TXENDDELAY                     (0x1UL << 28)                               /**< Tx End Delay (device only) */
+#define USB_GUSBCFG_TXENDDELAY                     (0x1UL << 28)                               /**< Tx End Delay device only */
 #define _USB_GUSBCFG_TXENDDELAY_SHIFT              28                                          /**< Shift value for USB_TXENDDELAY */
 #define _USB_GUSBCFG_TXENDDELAY_MASK               0x10000000UL                                /**< Bit mask for USB_TXENDDELAY */
 #define _USB_GUSBCFG_TXENDDELAY_DEFAULT            0x00000000UL                                /**< Mode DEFAULT for USB_GUSBCFG */
 #define USB_GUSBCFG_TXENDDELAY_DEFAULT             (_USB_GUSBCFG_TXENDDELAY_DEFAULT << 28)     /**< Shifted mode DEFAULT for USB_GUSBCFG */
-#define USB_GUSBCFG_FORCEHSTMODE                   (0x1UL << 29)                               /**< Force Host Mode (host and device) */
+#define USB_GUSBCFG_FORCEHSTMODE                   (0x1UL << 29)                               /**< Force Host Mode host and device */
 #define _USB_GUSBCFG_FORCEHSTMODE_SHIFT            29                                          /**< Shift value for USB_FORCEHSTMODE */
 #define _USB_GUSBCFG_FORCEHSTMODE_MASK             0x20000000UL                                /**< Bit mask for USB_FORCEHSTMODE */
 #define _USB_GUSBCFG_FORCEHSTMODE_DEFAULT          0x00000000UL                                /**< Mode DEFAULT for USB_GUSBCFG */
 #define USB_GUSBCFG_FORCEHSTMODE_DEFAULT           (_USB_GUSBCFG_FORCEHSTMODE_DEFAULT << 29)   /**< Shifted mode DEFAULT for USB_GUSBCFG */
-#define USB_GUSBCFG_FORCEDEVMODE                   (0x1UL << 30)                               /**< Force Device Mode (host and device) */
+#define USB_GUSBCFG_FORCEDEVMODE                   (0x1UL << 30)                               /**< Force Device Mode host and device */
 #define _USB_GUSBCFG_FORCEDEVMODE_SHIFT            30                                          /**< Shift value for USB_FORCEDEVMODE */
 #define _USB_GUSBCFG_FORCEDEVMODE_MASK             0x40000000UL                                /**< Bit mask for USB_FORCEDEVMODE */
 #define _USB_GUSBCFG_FORCEDEVMODE_DEFAULT          0x00000000UL                                /**< Mode DEFAULT for USB_GUSBCFG */
 #define USB_GUSBCFG_FORCEDEVMODE_DEFAULT           (_USB_GUSBCFG_FORCEDEVMODE_DEFAULT << 30)   /**< Shifted mode DEFAULT for USB_GUSBCFG */
-#define USB_GUSBCFG_CORRUPTTXPKT                   (0x1UL << 31)                               /**< Corrupt Tx packet (host and device) */
+#define USB_GUSBCFG_CORRUPTTXPKT                   (0x1UL << 31)                               /**< Corrupt Tx packet host and device */
 #define _USB_GUSBCFG_CORRUPTTXPKT_SHIFT            31                                          /**< Shift value for USB_CORRUPTTXPKT */
 #define _USB_GUSBCFG_CORRUPTTXPKT_MASK             0x80000000UL                                /**< Bit mask for USB_CORRUPTTXPKT */
 #define _USB_GUSBCFG_CORRUPTTXPKT_DEFAULT          0x00000000UL                                /**< Mode DEFAULT for USB_GUSBCFG */
@@ -568,22 +554,22 @@
 /* Bit fields for USB GRSTCTL */
 #define _USB_GRSTCTL_RESETVALUE                    0x80000000UL                           /**< Default value for USB_GRSTCTL */
 #define _USB_GRSTCTL_MASK                          0xC00007F5UL                           /**< Mask for USB_GRSTCTL */
-#define USB_GRSTCTL_CSFTRST                        (0x1UL << 0)                           /**< Core Soft Reset (host and device) */
+#define USB_GRSTCTL_CSFTRST                        (0x1UL << 0)                           /**< Core Soft Reset host and device */
 #define _USB_GRSTCTL_CSFTRST_SHIFT                 0                                      /**< Shift value for USB_CSFTRST */
 #define _USB_GRSTCTL_CSFTRST_MASK                  0x1UL                                  /**< Bit mask for USB_CSFTRST */
 #define _USB_GRSTCTL_CSFTRST_DEFAULT               0x00000000UL                           /**< Mode DEFAULT for USB_GRSTCTL */
 #define USB_GRSTCTL_CSFTRST_DEFAULT                (_USB_GRSTCTL_CSFTRST_DEFAULT << 0)    /**< Shifted mode DEFAULT for USB_GRSTCTL */
-#define USB_GRSTCTL_FRMCNTRRST                     (0x1UL << 2)                           /**< Host Frame Counter Reset (host only) */
+#define USB_GRSTCTL_FRMCNTRRST                     (0x1UL << 2)                           /**< Host Frame Counter Reset host only */
 #define _USB_GRSTCTL_FRMCNTRRST_SHIFT              2                                      /**< Shift value for USB_FRMCNTRRST */
 #define _USB_GRSTCTL_FRMCNTRRST_MASK               0x4UL                                  /**< Bit mask for USB_FRMCNTRRST */
 #define _USB_GRSTCTL_FRMCNTRRST_DEFAULT            0x00000000UL                           /**< Mode DEFAULT for USB_GRSTCTL */
 #define USB_GRSTCTL_FRMCNTRRST_DEFAULT             (_USB_GRSTCTL_FRMCNTRRST_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_GRSTCTL */
-#define USB_GRSTCTL_RXFFLSH                        (0x1UL << 4)                           /**< RxFIFO Flush (host and device) */
+#define USB_GRSTCTL_RXFFLSH                        (0x1UL << 4)                           /**< RxFIFO Flush host and device */
 #define _USB_GRSTCTL_RXFFLSH_SHIFT                 4                                      /**< Shift value for USB_RXFFLSH */
 #define _USB_GRSTCTL_RXFFLSH_MASK                  0x10UL                                 /**< Bit mask for USB_RXFFLSH */
 #define _USB_GRSTCTL_RXFFLSH_DEFAULT               0x00000000UL                           /**< Mode DEFAULT for USB_GRSTCTL */
 #define USB_GRSTCTL_RXFFLSH_DEFAULT                (_USB_GRSTCTL_RXFFLSH_DEFAULT << 4)    /**< Shifted mode DEFAULT for USB_GRSTCTL */
-#define USB_GRSTCTL_TXFFLSH                        (0x1UL << 5)                           /**< TxFIFO Flush (host and device) */
+#define USB_GRSTCTL_TXFFLSH                        (0x1UL << 5)                           /**< TxFIFO Flush host and device */
 #define _USB_GRSTCTL_TXFFLSH_SHIFT                 5                                      /**< Shift value for USB_TXFFLSH */
 #define _USB_GRSTCTL_TXFFLSH_MASK                  0x20UL                                 /**< Bit mask for USB_TXFFLSH */
 #define _USB_GRSTCTL_TXFFLSH_DEFAULT               0x00000000UL                           /**< Mode DEFAULT for USB_GRSTCTL */
@@ -608,12 +594,12 @@
 #define USB_GRSTCTL_TXFNUM_F5                      (_USB_GRSTCTL_TXFNUM_F5 << 6)          /**< Shifted mode F5 for USB_GRSTCTL */
 #define USB_GRSTCTL_TXFNUM_F6                      (_USB_GRSTCTL_TXFNUM_F6 << 6)          /**< Shifted mode F6 for USB_GRSTCTL */
 #define USB_GRSTCTL_TXFNUM_FALL                    (_USB_GRSTCTL_TXFNUM_FALL << 6)        /**< Shifted mode FALL for USB_GRSTCTL */
-#define USB_GRSTCTL_DMAREQ                         (0x1UL << 30)                          /**< DMA Request Signal (host and device) */
+#define USB_GRSTCTL_DMAREQ                         (0x1UL << 30)                          /**< DMA Request Signal host and device */
 #define _USB_GRSTCTL_DMAREQ_SHIFT                  30                                     /**< Shift value for USB_DMAREQ */
 #define _USB_GRSTCTL_DMAREQ_MASK                   0x40000000UL                           /**< Bit mask for USB_DMAREQ */
 #define _USB_GRSTCTL_DMAREQ_DEFAULT                0x00000000UL                           /**< Mode DEFAULT for USB_GRSTCTL */
 #define USB_GRSTCTL_DMAREQ_DEFAULT                 (_USB_GRSTCTL_DMAREQ_DEFAULT << 30)    /**< Shifted mode DEFAULT for USB_GRSTCTL */
-#define USB_GRSTCTL_AHBIDLE                        (0x1UL << 31)                          /**< AHB Master Idle (host and device) */
+#define USB_GRSTCTL_AHBIDLE                        (0x1UL << 31)                          /**< AHB Master Idle host and device */
 #define _USB_GRSTCTL_AHBIDLE_SHIFT                 31                                     /**< Shift value for USB_AHBIDLE */
 #define _USB_GRSTCTL_AHBIDLE_MASK                  0x80000000UL                           /**< Bit mask for USB_AHBIDLE */
 #define _USB_GRSTCTL_AHBIDLE_DEFAULT               0x00000001UL                           /**< Mode DEFAULT for USB_GRSTCTL */
@@ -621,8 +607,8 @@
 
 /* Bit fields for USB GINTSTS */
 #define _USB_GINTSTS_RESETVALUE                    0x14000020UL                              /**< Default value for USB_GINTSTS */
-#define _USB_GINTSTS_MASK                          0xF7FC7CFFUL                              /**< Mask for USB_GINTSTS */
-#define USB_GINTSTS_CURMOD                         (0x1UL << 0)                              /**< Current Mode of Operation (host and device) */
+#define _USB_GINTSTS_MASK                          0xF7FCFCFFUL                              /**< Mask for USB_GINTSTS */
+#define USB_GINTSTS_CURMOD                         (0x1UL << 0)                              /**< Current Mode of Operation host and device */
 #define _USB_GINTSTS_CURMOD_SHIFT                  0                                         /**< Shift value for USB_CURMOD */
 #define _USB_GINTSTS_CURMOD_MASK                   0x1UL                                     /**< Bit mask for USB_CURMOD */
 #define _USB_GINTSTS_CURMOD_DEFAULT                0x00000000UL                              /**< Mode DEFAULT for USB_GINTSTS */
@@ -631,127 +617,132 @@
 #define USB_GINTSTS_CURMOD_DEFAULT                 (_USB_GINTSTS_CURMOD_DEFAULT << 0)        /**< Shifted mode DEFAULT for USB_GINTSTS */
 #define USB_GINTSTS_CURMOD_DEVICE                  (_USB_GINTSTS_CURMOD_DEVICE << 0)         /**< Shifted mode DEVICE for USB_GINTSTS */
 #define USB_GINTSTS_CURMOD_HOST                    (_USB_GINTSTS_CURMOD_HOST << 0)           /**< Shifted mode HOST for USB_GINTSTS */
-#define USB_GINTSTS_MODEMIS                        (0x1UL << 1)                              /**< Mode Mismatch Interrupt (host and device) */
+#define USB_GINTSTS_MODEMIS                        (0x1UL << 1)                              /**< Mode Mismatch Interrupt host and device */
 #define _USB_GINTSTS_MODEMIS_SHIFT                 1                                         /**< Shift value for USB_MODEMIS */
 #define _USB_GINTSTS_MODEMIS_MASK                  0x2UL                                     /**< Bit mask for USB_MODEMIS */
 #define _USB_GINTSTS_MODEMIS_DEFAULT               0x00000000UL                              /**< Mode DEFAULT for USB_GINTSTS */
 #define USB_GINTSTS_MODEMIS_DEFAULT                (_USB_GINTSTS_MODEMIS_DEFAULT << 1)       /**< Shifted mode DEFAULT for USB_GINTSTS */
-#define USB_GINTSTS_OTGINT                         (0x1UL << 2)                              /**< OTG Interrupt (host and device) */
+#define USB_GINTSTS_OTGINT                         (0x1UL << 2)                              /**< OTG Interrupt host and device */
 #define _USB_GINTSTS_OTGINT_SHIFT                  2                                         /**< Shift value for USB_OTGINT */
 #define _USB_GINTSTS_OTGINT_MASK                   0x4UL                                     /**< Bit mask for USB_OTGINT */
 #define _USB_GINTSTS_OTGINT_DEFAULT                0x00000000UL                              /**< Mode DEFAULT for USB_GINTSTS */
 #define USB_GINTSTS_OTGINT_DEFAULT                 (_USB_GINTSTS_OTGINT_DEFAULT << 2)        /**< Shifted mode DEFAULT for USB_GINTSTS */
-#define USB_GINTSTS_SOF                            (0x1UL << 3)                              /**< Start of Frame (host and device) */
+#define USB_GINTSTS_SOF                            (0x1UL << 3)                              /**< Start of Frame host and device */
 #define _USB_GINTSTS_SOF_SHIFT                     3                                         /**< Shift value for USB_SOF */
 #define _USB_GINTSTS_SOF_MASK                      0x8UL                                     /**< Bit mask for USB_SOF */
 #define _USB_GINTSTS_SOF_DEFAULT                   0x00000000UL                              /**< Mode DEFAULT for USB_GINTSTS */
 #define USB_GINTSTS_SOF_DEFAULT                    (_USB_GINTSTS_SOF_DEFAULT << 3)           /**< Shifted mode DEFAULT for USB_GINTSTS */
-#define USB_GINTSTS_RXFLVL                         (0x1UL << 4)                              /**< RxFIFO Non-Empty (host and device) */
+#define USB_GINTSTS_RXFLVL                         (0x1UL << 4)                              /**< RxFIFO Non-Empty host and device */
 #define _USB_GINTSTS_RXFLVL_SHIFT                  4                                         /**< Shift value for USB_RXFLVL */
 #define _USB_GINTSTS_RXFLVL_MASK                   0x10UL                                    /**< Bit mask for USB_RXFLVL */
 #define _USB_GINTSTS_RXFLVL_DEFAULT                0x00000000UL                              /**< Mode DEFAULT for USB_GINTSTS */
 #define USB_GINTSTS_RXFLVL_DEFAULT                 (_USB_GINTSTS_RXFLVL_DEFAULT << 4)        /**< Shifted mode DEFAULT for USB_GINTSTS */
-#define USB_GINTSTS_NPTXFEMP                       (0x1UL << 5)                              /**< Non-Periodic TxFIFO Empty (host only) */
+#define USB_GINTSTS_NPTXFEMP                       (0x1UL << 5)                              /**< Non-Periodic TxFIFO Empty host only */
 #define _USB_GINTSTS_NPTXFEMP_SHIFT                5                                         /**< Shift value for USB_NPTXFEMP */
 #define _USB_GINTSTS_NPTXFEMP_MASK                 0x20UL                                    /**< Bit mask for USB_NPTXFEMP */
 #define _USB_GINTSTS_NPTXFEMP_DEFAULT              0x00000001UL                              /**< Mode DEFAULT for USB_GINTSTS */
 #define USB_GINTSTS_NPTXFEMP_DEFAULT               (_USB_GINTSTS_NPTXFEMP_DEFAULT << 5)      /**< Shifted mode DEFAULT for USB_GINTSTS */
-#define USB_GINTSTS_GINNAKEFF                      (0x1UL << 6)                              /**< Global IN Non-periodic NAK Effective (device only) */
+#define USB_GINTSTS_GINNAKEFF                      (0x1UL << 6)                              /**< Global IN Non-periodic NAK Effective device only */
 #define _USB_GINTSTS_GINNAKEFF_SHIFT               6                                         /**< Shift value for USB_GINNAKEFF */
 #define _USB_GINTSTS_GINNAKEFF_MASK                0x40UL                                    /**< Bit mask for USB_GINNAKEFF */
 #define _USB_GINTSTS_GINNAKEFF_DEFAULT             0x00000000UL                              /**< Mode DEFAULT for USB_GINTSTS */
 #define USB_GINTSTS_GINNAKEFF_DEFAULT              (_USB_GINTSTS_GINNAKEFF_DEFAULT << 6)     /**< Shifted mode DEFAULT for USB_GINTSTS */
-#define USB_GINTSTS_GOUTNAKEFF                     (0x1UL << 7)                              /**< Global OUT NAK Effective (device only) */
+#define USB_GINTSTS_GOUTNAKEFF                     (0x1UL << 7)                              /**< Global OUT NAK Effective device only */
 #define _USB_GINTSTS_GOUTNAKEFF_SHIFT              7                                         /**< Shift value for USB_GOUTNAKEFF */
 #define _USB_GINTSTS_GOUTNAKEFF_MASK               0x80UL                                    /**< Bit mask for USB_GOUTNAKEFF */
 #define _USB_GINTSTS_GOUTNAKEFF_DEFAULT            0x00000000UL                              /**< Mode DEFAULT for USB_GINTSTS */
 #define USB_GINTSTS_GOUTNAKEFF_DEFAULT             (_USB_GINTSTS_GOUTNAKEFF_DEFAULT << 7)    /**< Shifted mode DEFAULT for USB_GINTSTS */
-#define USB_GINTSTS_ERLYSUSP                       (0x1UL << 10)                             /**< Early Suspend (device only) */
+#define USB_GINTSTS_ERLYSUSP                       (0x1UL << 10)                             /**< Early Suspend device only */
 #define _USB_GINTSTS_ERLYSUSP_SHIFT                10                                        /**< Shift value for USB_ERLYSUSP */
 #define _USB_GINTSTS_ERLYSUSP_MASK                 0x400UL                                   /**< Bit mask for USB_ERLYSUSP */
 #define _USB_GINTSTS_ERLYSUSP_DEFAULT              0x00000000UL                              /**< Mode DEFAULT for USB_GINTSTS */
 #define USB_GINTSTS_ERLYSUSP_DEFAULT               (_USB_GINTSTS_ERLYSUSP_DEFAULT << 10)     /**< Shifted mode DEFAULT for USB_GINTSTS */
-#define USB_GINTSTS_USBSUSP                        (0x1UL << 11)                             /**< USB Suspend (device only) */
+#define USB_GINTSTS_USBSUSP                        (0x1UL << 11)                             /**< USB Suspend device only */
 #define _USB_GINTSTS_USBSUSP_SHIFT                 11                                        /**< Shift value for USB_USBSUSP */
 #define _USB_GINTSTS_USBSUSP_MASK                  0x800UL                                   /**< Bit mask for USB_USBSUSP */
 #define _USB_GINTSTS_USBSUSP_DEFAULT               0x00000000UL                              /**< Mode DEFAULT for USB_GINTSTS */
 #define USB_GINTSTS_USBSUSP_DEFAULT                (_USB_GINTSTS_USBSUSP_DEFAULT << 11)      /**< Shifted mode DEFAULT for USB_GINTSTS */
-#define USB_GINTSTS_USBRST                         (0x1UL << 12)                             /**< USB Reset (device only) */
+#define USB_GINTSTS_USBRST                         (0x1UL << 12)                             /**< USB Reset device only */
 #define _USB_GINTSTS_USBRST_SHIFT                  12                                        /**< Shift value for USB_USBRST */
 #define _USB_GINTSTS_USBRST_MASK                   0x1000UL                                  /**< Bit mask for USB_USBRST */
 #define _USB_GINTSTS_USBRST_DEFAULT                0x00000000UL                              /**< Mode DEFAULT for USB_GINTSTS */
 #define USB_GINTSTS_USBRST_DEFAULT                 (_USB_GINTSTS_USBRST_DEFAULT << 12)       /**< Shifted mode DEFAULT for USB_GINTSTS */
-#define USB_GINTSTS_ENUMDONE                       (0x1UL << 13)                             /**< Enumeration Done (device only) */
+#define USB_GINTSTS_ENUMDONE                       (0x1UL << 13)                             /**< Enumeration Done device only */
 #define _USB_GINTSTS_ENUMDONE_SHIFT                13                                        /**< Shift value for USB_ENUMDONE */
 #define _USB_GINTSTS_ENUMDONE_MASK                 0x2000UL                                  /**< Bit mask for USB_ENUMDONE */
 #define _USB_GINTSTS_ENUMDONE_DEFAULT              0x00000000UL                              /**< Mode DEFAULT for USB_GINTSTS */
 #define USB_GINTSTS_ENUMDONE_DEFAULT               (_USB_GINTSTS_ENUMDONE_DEFAULT << 13)     /**< Shifted mode DEFAULT for USB_GINTSTS */
-#define USB_GINTSTS_ISOOUTDROP                     (0x1UL << 14)                             /**< Isochronous OUT Packet Dropped Interrupt (device only) */
+#define USB_GINTSTS_ISOOUTDROP                     (0x1UL << 14)                             /**< Isochronous OUT Packet Dropped Interrupt device only */
 #define _USB_GINTSTS_ISOOUTDROP_SHIFT              14                                        /**< Shift value for USB_ISOOUTDROP */
 #define _USB_GINTSTS_ISOOUTDROP_MASK               0x4000UL                                  /**< Bit mask for USB_ISOOUTDROP */
 #define _USB_GINTSTS_ISOOUTDROP_DEFAULT            0x00000000UL                              /**< Mode DEFAULT for USB_GINTSTS */
 #define USB_GINTSTS_ISOOUTDROP_DEFAULT             (_USB_GINTSTS_ISOOUTDROP_DEFAULT << 14)   /**< Shifted mode DEFAULT for USB_GINTSTS */
-#define USB_GINTSTS_IEPINT                         (0x1UL << 18)                             /**< IN Endpoints Interrupt (device only) */
+#define USB_GINTSTS_EOPF                           (0x1UL << 15)                             /**< End of Periodic Frame Interrupt */
+#define _USB_GINTSTS_EOPF_SHIFT                    15                                        /**< Shift value for USB_EOPF */
+#define _USB_GINTSTS_EOPF_MASK                     0x8000UL                                  /**< Bit mask for USB_EOPF */
+#define _USB_GINTSTS_EOPF_DEFAULT                  0x00000000UL                              /**< Mode DEFAULT for USB_GINTSTS */
+#define USB_GINTSTS_EOPF_DEFAULT                   (_USB_GINTSTS_EOPF_DEFAULT << 15)         /**< Shifted mode DEFAULT for USB_GINTSTS */
+#define USB_GINTSTS_IEPINT                         (0x1UL << 18)                             /**< IN Endpoints Interrupt device only */
 #define _USB_GINTSTS_IEPINT_SHIFT                  18                                        /**< Shift value for USB_IEPINT */
 #define _USB_GINTSTS_IEPINT_MASK                   0x40000UL                                 /**< Bit mask for USB_IEPINT */
 #define _USB_GINTSTS_IEPINT_DEFAULT                0x00000000UL                              /**< Mode DEFAULT for USB_GINTSTS */
 #define USB_GINTSTS_IEPINT_DEFAULT                 (_USB_GINTSTS_IEPINT_DEFAULT << 18)       /**< Shifted mode DEFAULT for USB_GINTSTS */
-#define USB_GINTSTS_OEPINT                         (0x1UL << 19)                             /**< OUT Endpoints Interrupt (device only) */
+#define USB_GINTSTS_OEPINT                         (0x1UL << 19)                             /**< OUT Endpoints Interrupt device only */
 #define _USB_GINTSTS_OEPINT_SHIFT                  19                                        /**< Shift value for USB_OEPINT */
 #define _USB_GINTSTS_OEPINT_MASK                   0x80000UL                                 /**< Bit mask for USB_OEPINT */
 #define _USB_GINTSTS_OEPINT_DEFAULT                0x00000000UL                              /**< Mode DEFAULT for USB_GINTSTS */
 #define USB_GINTSTS_OEPINT_DEFAULT                 (_USB_GINTSTS_OEPINT_DEFAULT << 19)       /**< Shifted mode DEFAULT for USB_GINTSTS */
-#define USB_GINTSTS_INCOMPISOIN                    (0x1UL << 20)                             /**< Incomplete Isochronous IN Transfer (device only) */
+#define USB_GINTSTS_INCOMPISOIN                    (0x1UL << 20)                             /**< Incomplete Isochronous IN Transfer device only */
 #define _USB_GINTSTS_INCOMPISOIN_SHIFT             20                                        /**< Shift value for USB_INCOMPISOIN */
 #define _USB_GINTSTS_INCOMPISOIN_MASK              0x100000UL                                /**< Bit mask for USB_INCOMPISOIN */
 #define _USB_GINTSTS_INCOMPISOIN_DEFAULT           0x00000000UL                              /**< Mode DEFAULT for USB_GINTSTS */
 #define USB_GINTSTS_INCOMPISOIN_DEFAULT            (_USB_GINTSTS_INCOMPISOIN_DEFAULT << 20)  /**< Shifted mode DEFAULT for USB_GINTSTS */
-#define USB_GINTSTS_INCOMPLP                       (0x1UL << 21)                             /**< Incomplete Periodic Transfer (device only) */
+#define USB_GINTSTS_INCOMPLP                       (0x1UL << 21)                             /**< Incomplete Periodic Transfer host and device */
 #define _USB_GINTSTS_INCOMPLP_SHIFT                21                                        /**< Shift value for USB_INCOMPLP */
 #define _USB_GINTSTS_INCOMPLP_MASK                 0x200000UL                                /**< Bit mask for USB_INCOMPLP */
 #define _USB_GINTSTS_INCOMPLP_DEFAULT              0x00000000UL                              /**< Mode DEFAULT for USB_GINTSTS */
 #define USB_GINTSTS_INCOMPLP_DEFAULT               (_USB_GINTSTS_INCOMPLP_DEFAULT << 21)     /**< Shifted mode DEFAULT for USB_GINTSTS */
-#define USB_GINTSTS_FETSUSP                        (0x1UL << 22)                             /**< Data Fetch Suspended (device only) */
+#define USB_GINTSTS_FETSUSP                        (0x1UL << 22)                             /**< Data Fetch Suspended device only */
 #define _USB_GINTSTS_FETSUSP_SHIFT                 22                                        /**< Shift value for USB_FETSUSP */
 #define _USB_GINTSTS_FETSUSP_MASK                  0x400000UL                                /**< Bit mask for USB_FETSUSP */
 #define _USB_GINTSTS_FETSUSP_DEFAULT               0x00000000UL                              /**< Mode DEFAULT for USB_GINTSTS */
 #define USB_GINTSTS_FETSUSP_DEFAULT                (_USB_GINTSTS_FETSUSP_DEFAULT << 22)      /**< Shifted mode DEFAULT for USB_GINTSTS */
-#define USB_GINTSTS_RESETDET                       (0x1UL << 23)                             /**< Reset detected Interrupt (device only) */
+#define USB_GINTSTS_RESETDET                       (0x1UL << 23)                             /**< Reset detected Interrupt device only */
 #define _USB_GINTSTS_RESETDET_SHIFT                23                                        /**< Shift value for USB_RESETDET */
 #define _USB_GINTSTS_RESETDET_MASK                 0x800000UL                                /**< Bit mask for USB_RESETDET */
 #define _USB_GINTSTS_RESETDET_DEFAULT              0x00000000UL                              /**< Mode DEFAULT for USB_GINTSTS */
 #define USB_GINTSTS_RESETDET_DEFAULT               (_USB_GINTSTS_RESETDET_DEFAULT << 23)     /**< Shifted mode DEFAULT for USB_GINTSTS */
-#define USB_GINTSTS_PRTINT                         (0x1UL << 24)                             /**< Host Port Interrupt (host only) */
+#define USB_GINTSTS_PRTINT                         (0x1UL << 24)                             /**< Host Port Interrupt host only */
 #define _USB_GINTSTS_PRTINT_SHIFT                  24                                        /**< Shift value for USB_PRTINT */
 #define _USB_GINTSTS_PRTINT_MASK                   0x1000000UL                               /**< Bit mask for USB_PRTINT */
 #define _USB_GINTSTS_PRTINT_DEFAULT                0x00000000UL                              /**< Mode DEFAULT for USB_GINTSTS */
 #define USB_GINTSTS_PRTINT_DEFAULT                 (_USB_GINTSTS_PRTINT_DEFAULT << 24)       /**< Shifted mode DEFAULT for USB_GINTSTS */
-#define USB_GINTSTS_HCHINT                         (0x1UL << 25)                             /**< Host Channels Interrupt (host only) */
+#define USB_GINTSTS_HCHINT                         (0x1UL << 25)                             /**< Host Channels Interrupt host only */
 #define _USB_GINTSTS_HCHINT_SHIFT                  25                                        /**< Shift value for USB_HCHINT */
 #define _USB_GINTSTS_HCHINT_MASK                   0x2000000UL                               /**< Bit mask for USB_HCHINT */
 #define _USB_GINTSTS_HCHINT_DEFAULT                0x00000000UL                              /**< Mode DEFAULT for USB_GINTSTS */
 #define USB_GINTSTS_HCHINT_DEFAULT                 (_USB_GINTSTS_HCHINT_DEFAULT << 25)       /**< Shifted mode DEFAULT for USB_GINTSTS */
-#define USB_GINTSTS_PTXFEMP                        (0x1UL << 26)                             /**< Periodic TxFIFO Empty (host only) */
+#define USB_GINTSTS_PTXFEMP                        (0x1UL << 26)                             /**< Periodic TxFIFO Empty host only */
 #define _USB_GINTSTS_PTXFEMP_SHIFT                 26                                        /**< Shift value for USB_PTXFEMP */
 #define _USB_GINTSTS_PTXFEMP_MASK                  0x4000000UL                               /**< Bit mask for USB_PTXFEMP */
 #define _USB_GINTSTS_PTXFEMP_DEFAULT               0x00000001UL                              /**< Mode DEFAULT for USB_GINTSTS */
 #define USB_GINTSTS_PTXFEMP_DEFAULT                (_USB_GINTSTS_PTXFEMP_DEFAULT << 26)      /**< Shifted mode DEFAULT for USB_GINTSTS */
-#define USB_GINTSTS_CONIDSTSCHNG                   (0x1UL << 28)                             /**< Connector ID Status Change (host and device) */
+#define USB_GINTSTS_CONIDSTSCHNG                   (0x1UL << 28)                             /**< Connector ID Status Change host and device */
 #define _USB_GINTSTS_CONIDSTSCHNG_SHIFT            28                                        /**< Shift value for USB_CONIDSTSCHNG */
 #define _USB_GINTSTS_CONIDSTSCHNG_MASK             0x10000000UL                              /**< Bit mask for USB_CONIDSTSCHNG */
 #define _USB_GINTSTS_CONIDSTSCHNG_DEFAULT          0x00000001UL                              /**< Mode DEFAULT for USB_GINTSTS */
 #define USB_GINTSTS_CONIDSTSCHNG_DEFAULT           (_USB_GINTSTS_CONIDSTSCHNG_DEFAULT << 28) /**< Shifted mode DEFAULT for USB_GINTSTS */
-#define USB_GINTSTS_DISCONNINT                     (0x1UL << 29)                             /**< Disconnect Detected Interrupt (host only) */
+#define USB_GINTSTS_DISCONNINT                     (0x1UL << 29)                             /**< Disconnect Detected Interrupt host only */
 #define _USB_GINTSTS_DISCONNINT_SHIFT              29                                        /**< Shift value for USB_DISCONNINT */
 #define _USB_GINTSTS_DISCONNINT_MASK               0x20000000UL                              /**< Bit mask for USB_DISCONNINT */
 #define _USB_GINTSTS_DISCONNINT_DEFAULT            0x00000000UL                              /**< Mode DEFAULT for USB_GINTSTS */
 #define USB_GINTSTS_DISCONNINT_DEFAULT             (_USB_GINTSTS_DISCONNINT_DEFAULT << 29)   /**< Shifted mode DEFAULT for USB_GINTSTS */
-#define USB_GINTSTS_SESSREQINT                     (0x1UL << 30)                             /**< Session Request/New Session Detected Interrupt (host and device) */
+#define USB_GINTSTS_SESSREQINT                     (0x1UL << 30)                             /**< Session Request/New Session Detected Interrupt host and device */
 #define _USB_GINTSTS_SESSREQINT_SHIFT              30                                        /**< Shift value for USB_SESSREQINT */
 #define _USB_GINTSTS_SESSREQINT_MASK               0x40000000UL                              /**< Bit mask for USB_SESSREQINT */
 #define _USB_GINTSTS_SESSREQINT_DEFAULT            0x00000000UL                              /**< Mode DEFAULT for USB_GINTSTS */
 #define USB_GINTSTS_SESSREQINT_DEFAULT             (_USB_GINTSTS_SESSREQINT_DEFAULT << 30)   /**< Shifted mode DEFAULT for USB_GINTSTS */
-#define USB_GINTSTS_WKUPINT                        (0x1UL << 31)                             /**< Resume/Remote Wakeup Detected Interrupt (host and device) */
+#define USB_GINTSTS_WKUPINT                        (0x1UL << 31)                             /**< Resume/Remote Wakeup Detected Interrupt host and device */
 #define _USB_GINTSTS_WKUPINT_SHIFT                 31                                        /**< Shift value for USB_WKUPINT */
 #define _USB_GINTSTS_WKUPINT_MASK                  0x80000000UL                              /**< Bit mask for USB_WKUPINT */
 #define _USB_GINTSTS_WKUPINT_DEFAULT               0x00000000UL                              /**< Mode DEFAULT for USB_GINTSTS */
@@ -759,128 +750,133 @@
 
 /* Bit fields for USB GINTMSK */
 #define _USB_GINTMSK_RESETVALUE                    0x00000000UL                                 /**< Default value for USB_GINTMSK */
-#define _USB_GINTMSK_MASK                          0xF7FC7CFEUL                                 /**< Mask for USB_GINTMSK */
-#define USB_GINTMSK_MODEMISMSK                     (0x1UL << 1)                                 /**< Mode Mismatch Interrupt Mask (host and device) */
+#define _USB_GINTMSK_MASK                          0xF7FCFCFEUL                                 /**< Mask for USB_GINTMSK */
+#define USB_GINTMSK_MODEMISMSK                     (0x1UL << 1)                                 /**< Mode Mismatch Interrupt Mask host and device */
 #define _USB_GINTMSK_MODEMISMSK_SHIFT              1                                            /**< Shift value for USB_MODEMISMSK */
 #define _USB_GINTMSK_MODEMISMSK_MASK               0x2UL                                        /**< Bit mask for USB_MODEMISMSK */
 #define _USB_GINTMSK_MODEMISMSK_DEFAULT            0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
 #define USB_GINTMSK_MODEMISMSK_DEFAULT             (_USB_GINTMSK_MODEMISMSK_DEFAULT << 1)       /**< Shifted mode DEFAULT for USB_GINTMSK */
-#define USB_GINTMSK_OTGINTMSK                      (0x1UL << 2)                                 /**< OTG Interrupt Mask (host and device) */
+#define USB_GINTMSK_OTGINTMSK                      (0x1UL << 2)                                 /**< OTG Interrupt Mask host and device */
 #define _USB_GINTMSK_OTGINTMSK_SHIFT               2                                            /**< Shift value for USB_OTGINTMSK */
 #define _USB_GINTMSK_OTGINTMSK_MASK                0x4UL                                        /**< Bit mask for USB_OTGINTMSK */
 #define _USB_GINTMSK_OTGINTMSK_DEFAULT             0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
 #define USB_GINTMSK_OTGINTMSK_DEFAULT              (_USB_GINTMSK_OTGINTMSK_DEFAULT << 2)        /**< Shifted mode DEFAULT for USB_GINTMSK */
-#define USB_GINTMSK_SOFMSK                         (0x1UL << 3)                                 /**< Start of Frame Mask (host and device) */
+#define USB_GINTMSK_SOFMSK                         (0x1UL << 3)                                 /**< Start of Frame Mask host and device */
 #define _USB_GINTMSK_SOFMSK_SHIFT                  3                                            /**< Shift value for USB_SOFMSK */
 #define _USB_GINTMSK_SOFMSK_MASK                   0x8UL                                        /**< Bit mask for USB_SOFMSK */
 #define _USB_GINTMSK_SOFMSK_DEFAULT                0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
 #define USB_GINTMSK_SOFMSK_DEFAULT                 (_USB_GINTMSK_SOFMSK_DEFAULT << 3)           /**< Shifted mode DEFAULT for USB_GINTMSK */
-#define USB_GINTMSK_RXFLVLMSK                      (0x1UL << 4)                                 /**< Receive FIFO Non-Empty Mask (host and device) */
+#define USB_GINTMSK_RXFLVLMSK                      (0x1UL << 4)                                 /**< Receive FIFO Non-Empty Mask host and device */
 #define _USB_GINTMSK_RXFLVLMSK_SHIFT               4                                            /**< Shift value for USB_RXFLVLMSK */
 #define _USB_GINTMSK_RXFLVLMSK_MASK                0x10UL                                       /**< Bit mask for USB_RXFLVLMSK */
 #define _USB_GINTMSK_RXFLVLMSK_DEFAULT             0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
 #define USB_GINTMSK_RXFLVLMSK_DEFAULT              (_USB_GINTMSK_RXFLVLMSK_DEFAULT << 4)        /**< Shifted mode DEFAULT for USB_GINTMSK */
-#define USB_GINTMSK_NPTXFEMPMSK                    (0x1UL << 5)                                 /**< Non-Periodic TxFIFO Empty Mask (host only) */
+#define USB_GINTMSK_NPTXFEMPMSK                    (0x1UL << 5)                                 /**< Non-Periodic TxFIFO Empty Mask host only */
 #define _USB_GINTMSK_NPTXFEMPMSK_SHIFT             5                                            /**< Shift value for USB_NPTXFEMPMSK */
 #define _USB_GINTMSK_NPTXFEMPMSK_MASK              0x20UL                                       /**< Bit mask for USB_NPTXFEMPMSK */
 #define _USB_GINTMSK_NPTXFEMPMSK_DEFAULT           0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
 #define USB_GINTMSK_NPTXFEMPMSK_DEFAULT            (_USB_GINTMSK_NPTXFEMPMSK_DEFAULT << 5)      /**< Shifted mode DEFAULT for USB_GINTMSK */
-#define USB_GINTMSK_GINNAKEFFMSK                   (0x1UL << 6)                                 /**< Global Non-periodic IN NAK Effective Mask (device only) */
+#define USB_GINTMSK_GINNAKEFFMSK                   (0x1UL << 6)                                 /**< Global Non-periodic IN NAK Effective Mask device only */
 #define _USB_GINTMSK_GINNAKEFFMSK_SHIFT            6                                            /**< Shift value for USB_GINNAKEFFMSK */
 #define _USB_GINTMSK_GINNAKEFFMSK_MASK             0x40UL                                       /**< Bit mask for USB_GINNAKEFFMSK */
 #define _USB_GINTMSK_GINNAKEFFMSK_DEFAULT          0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
 #define USB_GINTMSK_GINNAKEFFMSK_DEFAULT           (_USB_GINTMSK_GINNAKEFFMSK_DEFAULT << 6)     /**< Shifted mode DEFAULT for USB_GINTMSK */
-#define USB_GINTMSK_GOUTNAKEFFMSK                  (0x1UL << 7)                                 /**< Global OUT NAK Effective Mask (device only) */
+#define USB_GINTMSK_GOUTNAKEFFMSK                  (0x1UL << 7)                                 /**< Global OUT NAK Effective Mask device only */
 #define _USB_GINTMSK_GOUTNAKEFFMSK_SHIFT           7                                            /**< Shift value for USB_GOUTNAKEFFMSK */
 #define _USB_GINTMSK_GOUTNAKEFFMSK_MASK            0x80UL                                       /**< Bit mask for USB_GOUTNAKEFFMSK */
 #define _USB_GINTMSK_GOUTNAKEFFMSK_DEFAULT         0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
 #define USB_GINTMSK_GOUTNAKEFFMSK_DEFAULT          (_USB_GINTMSK_GOUTNAKEFFMSK_DEFAULT << 7)    /**< Shifted mode DEFAULT for USB_GINTMSK */
-#define USB_GINTMSK_ERLYSUSPMSK                    (0x1UL << 10)                                /**< Early Suspend Mask (device only) */
+#define USB_GINTMSK_ERLYSUSPMSK                    (0x1UL << 10)                                /**< Early Suspend Mask device only */
 #define _USB_GINTMSK_ERLYSUSPMSK_SHIFT             10                                           /**< Shift value for USB_ERLYSUSPMSK */
 #define _USB_GINTMSK_ERLYSUSPMSK_MASK              0x400UL                                      /**< Bit mask for USB_ERLYSUSPMSK */
 #define _USB_GINTMSK_ERLYSUSPMSK_DEFAULT           0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
 #define USB_GINTMSK_ERLYSUSPMSK_DEFAULT            (_USB_GINTMSK_ERLYSUSPMSK_DEFAULT << 10)     /**< Shifted mode DEFAULT for USB_GINTMSK */
-#define USB_GINTMSK_USBSUSPMSK                     (0x1UL << 11)                                /**< USB Suspend Mask (device only) */
+#define USB_GINTMSK_USBSUSPMSK                     (0x1UL << 11)                                /**< USB Suspend Mask device only */
 #define _USB_GINTMSK_USBSUSPMSK_SHIFT              11                                           /**< Shift value for USB_USBSUSPMSK */
 #define _USB_GINTMSK_USBSUSPMSK_MASK               0x800UL                                      /**< Bit mask for USB_USBSUSPMSK */
 #define _USB_GINTMSK_USBSUSPMSK_DEFAULT            0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
 #define USB_GINTMSK_USBSUSPMSK_DEFAULT             (_USB_GINTMSK_USBSUSPMSK_DEFAULT << 11)      /**< Shifted mode DEFAULT for USB_GINTMSK */
-#define USB_GINTMSK_USBRSTMSK                      (0x1UL << 12)                                /**< USB Reset Mask (device only) */
+#define USB_GINTMSK_USBRSTMSK                      (0x1UL << 12)                                /**< USB Reset Mask device only */
 #define _USB_GINTMSK_USBRSTMSK_SHIFT               12                                           /**< Shift value for USB_USBRSTMSK */
 #define _USB_GINTMSK_USBRSTMSK_MASK                0x1000UL                                     /**< Bit mask for USB_USBRSTMSK */
 #define _USB_GINTMSK_USBRSTMSK_DEFAULT             0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
 #define USB_GINTMSK_USBRSTMSK_DEFAULT              (_USB_GINTMSK_USBRSTMSK_DEFAULT << 12)       /**< Shifted mode DEFAULT for USB_GINTMSK */
-#define USB_GINTMSK_ENUMDONEMSK                    (0x1UL << 13)                                /**< Enumeration Done Mask (device only) */
+#define USB_GINTMSK_ENUMDONEMSK                    (0x1UL << 13)                                /**< Enumeration Done Mask device only */
 #define _USB_GINTMSK_ENUMDONEMSK_SHIFT             13                                           /**< Shift value for USB_ENUMDONEMSK */
 #define _USB_GINTMSK_ENUMDONEMSK_MASK              0x2000UL                                     /**< Bit mask for USB_ENUMDONEMSK */
 #define _USB_GINTMSK_ENUMDONEMSK_DEFAULT           0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
 #define USB_GINTMSK_ENUMDONEMSK_DEFAULT            (_USB_GINTMSK_ENUMDONEMSK_DEFAULT << 13)     /**< Shifted mode DEFAULT for USB_GINTMSK */
-#define USB_GINTMSK_ISOOUTDROPMSK                  (0x1UL << 14)                                /**< Isochronous OUT Packet Dropped Interrupt Mask (device only) */
+#define USB_GINTMSK_ISOOUTDROPMSK                  (0x1UL << 14)                                /**< Isochronous OUT Packet Dropped Interrupt Mask device only */
 #define _USB_GINTMSK_ISOOUTDROPMSK_SHIFT           14                                           /**< Shift value for USB_ISOOUTDROPMSK */
 #define _USB_GINTMSK_ISOOUTDROPMSK_MASK            0x4000UL                                     /**< Bit mask for USB_ISOOUTDROPMSK */
 #define _USB_GINTMSK_ISOOUTDROPMSK_DEFAULT         0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
 #define USB_GINTMSK_ISOOUTDROPMSK_DEFAULT          (_USB_GINTMSK_ISOOUTDROPMSK_DEFAULT << 14)   /**< Shifted mode DEFAULT for USB_GINTMSK */
-#define USB_GINTMSK_IEPINTMSK                      (0x1UL << 18)                                /**< IN Endpoints Interrupt Mask (device only) */
+#define USB_GINTMSK_EOPFMSK                        (0x1UL << 15)                                /**< End of Periodic Frame Interrupt Mask device only */
+#define _USB_GINTMSK_EOPFMSK_SHIFT                 15                                           /**< Shift value for USB_EOPFMSK */
+#define _USB_GINTMSK_EOPFMSK_MASK                  0x8000UL                                     /**< Bit mask for USB_EOPFMSK */
+#define _USB_GINTMSK_EOPFMSK_DEFAULT               0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
+#define USB_GINTMSK_EOPFMSK_DEFAULT                (_USB_GINTMSK_EOPFMSK_DEFAULT << 15)         /**< Shifted mode DEFAULT for USB_GINTMSK */
+#define USB_GINTMSK_IEPINTMSK                      (0x1UL << 18)                                /**< IN Endpoints Interrupt Mask device only */
 #define _USB_GINTMSK_IEPINTMSK_SHIFT               18                                           /**< Shift value for USB_IEPINTMSK */
 #define _USB_GINTMSK_IEPINTMSK_MASK                0x40000UL                                    /**< Bit mask for USB_IEPINTMSK */
 #define _USB_GINTMSK_IEPINTMSK_DEFAULT             0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
 #define USB_GINTMSK_IEPINTMSK_DEFAULT              (_USB_GINTMSK_IEPINTMSK_DEFAULT << 18)       /**< Shifted mode DEFAULT for USB_GINTMSK */
-#define USB_GINTMSK_OEPINTMSK                      (0x1UL << 19)                                /**< OUT Endpoints Interrupt Mask (device only) */
+#define USB_GINTMSK_OEPINTMSK                      (0x1UL << 19)                                /**< OUT Endpoints Interrupt Mask device only */
 #define _USB_GINTMSK_OEPINTMSK_SHIFT               19                                           /**< Shift value for USB_OEPINTMSK */
 #define _USB_GINTMSK_OEPINTMSK_MASK                0x80000UL                                    /**< Bit mask for USB_OEPINTMSK */
 #define _USB_GINTMSK_OEPINTMSK_DEFAULT             0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
 #define USB_GINTMSK_OEPINTMSK_DEFAULT              (_USB_GINTMSK_OEPINTMSK_DEFAULT << 19)       /**< Shifted mode DEFAULT for USB_GINTMSK */
-#define USB_GINTMSK_INCOMPISOINMSK                 (0x1UL << 20)                                /**< Incomplete Isochronous IN Transfer Mask (device only) */
+#define USB_GINTMSK_INCOMPISOINMSK                 (0x1UL << 20)                                /**< Incomplete Isochronous IN Transfer Mask device only */
 #define _USB_GINTMSK_INCOMPISOINMSK_SHIFT          20                                           /**< Shift value for USB_INCOMPISOINMSK */
 #define _USB_GINTMSK_INCOMPISOINMSK_MASK           0x100000UL                                   /**< Bit mask for USB_INCOMPISOINMSK */
 #define _USB_GINTMSK_INCOMPISOINMSK_DEFAULT        0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
 #define USB_GINTMSK_INCOMPISOINMSK_DEFAULT         (_USB_GINTMSK_INCOMPISOINMSK_DEFAULT << 20)  /**< Shifted mode DEFAULT for USB_GINTMSK */
-#define USB_GINTMSK_INCOMPLPMSK                    (0x1UL << 21)                                /**< Incomplete Periodic Transfer Mask (host only) */
+#define USB_GINTMSK_INCOMPLPMSK                    (0x1UL << 21)                                /**< Incomplete Periodic Transfer Mask host and device */
 #define _USB_GINTMSK_INCOMPLPMSK_SHIFT             21                                           /**< Shift value for USB_INCOMPLPMSK */
 #define _USB_GINTMSK_INCOMPLPMSK_MASK              0x200000UL                                   /**< Bit mask for USB_INCOMPLPMSK */
 #define _USB_GINTMSK_INCOMPLPMSK_DEFAULT           0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
 #define USB_GINTMSK_INCOMPLPMSK_DEFAULT            (_USB_GINTMSK_INCOMPLPMSK_DEFAULT << 21)     /**< Shifted mode DEFAULT for USB_GINTMSK */
-#define USB_GINTMSK_FETSUSPMSK                     (0x1UL << 22)                                /**< Data Fetch Suspended Mask (device only) */
+#define USB_GINTMSK_FETSUSPMSK                     (0x1UL << 22)                                /**< Data Fetch Suspended Mask device only */
 #define _USB_GINTMSK_FETSUSPMSK_SHIFT              22                                           /**< Shift value for USB_FETSUSPMSK */
 #define _USB_GINTMSK_FETSUSPMSK_MASK               0x400000UL                                   /**< Bit mask for USB_FETSUSPMSK */
 #define _USB_GINTMSK_FETSUSPMSK_DEFAULT            0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
 #define USB_GINTMSK_FETSUSPMSK_DEFAULT             (_USB_GINTMSK_FETSUSPMSK_DEFAULT << 22)      /**< Shifted mode DEFAULT for USB_GINTMSK */
-#define USB_GINTMSK_RESETDETMSK                    (0x1UL << 23)                                /**< Reset detected Interrupt Mask (device only) */
+#define USB_GINTMSK_RESETDETMSK                    (0x1UL << 23)                                /**< Reset detected Interrupt Mask device only */
 #define _USB_GINTMSK_RESETDETMSK_SHIFT             23                                           /**< Shift value for USB_RESETDETMSK */
 #define _USB_GINTMSK_RESETDETMSK_MASK              0x800000UL                                   /**< Bit mask for USB_RESETDETMSK */
 #define _USB_GINTMSK_RESETDETMSK_DEFAULT           0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
 #define USB_GINTMSK_RESETDETMSK_DEFAULT            (_USB_GINTMSK_RESETDETMSK_DEFAULT << 23)     /**< Shifted mode DEFAULT for USB_GINTMSK */
-#define USB_GINTMSK_PRTINTMSK                      (0x1UL << 24)                                /**< Host Port Interrupt Mask (host only) */
+#define USB_GINTMSK_PRTINTMSK                      (0x1UL << 24)                                /**< Host Port Interrupt Mask host only */
 #define _USB_GINTMSK_PRTINTMSK_SHIFT               24                                           /**< Shift value for USB_PRTINTMSK */
 #define _USB_GINTMSK_PRTINTMSK_MASK                0x1000000UL                                  /**< Bit mask for USB_PRTINTMSK */
 #define _USB_GINTMSK_PRTINTMSK_DEFAULT             0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
 #define USB_GINTMSK_PRTINTMSK_DEFAULT              (_USB_GINTMSK_PRTINTMSK_DEFAULT << 24)       /**< Shifted mode DEFAULT for USB_GINTMSK */
-#define USB_GINTMSK_HCHINTMSK                      (0x1UL << 25)                                /**< Host Channels Interrupt Mask (host only) */
+#define USB_GINTMSK_HCHINTMSK                      (0x1UL << 25)                                /**< Host Channels Interrupt Mask host only */
 #define _USB_GINTMSK_HCHINTMSK_SHIFT               25                                           /**< Shift value for USB_HCHINTMSK */
 #define _USB_GINTMSK_HCHINTMSK_MASK                0x2000000UL                                  /**< Bit mask for USB_HCHINTMSK */
 #define _USB_GINTMSK_HCHINTMSK_DEFAULT             0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
 #define USB_GINTMSK_HCHINTMSK_DEFAULT              (_USB_GINTMSK_HCHINTMSK_DEFAULT << 25)       /**< Shifted mode DEFAULT for USB_GINTMSK */
-#define USB_GINTMSK_PTXFEMPMSK                     (0x1UL << 26)                                /**< Periodic TxFIFO Empty Mask (host only) */
+#define USB_GINTMSK_PTXFEMPMSK                     (0x1UL << 26)                                /**< Periodic TxFIFO Empty Mask host only */
 #define _USB_GINTMSK_PTXFEMPMSK_SHIFT              26                                           /**< Shift value for USB_PTXFEMPMSK */
 #define _USB_GINTMSK_PTXFEMPMSK_MASK               0x4000000UL                                  /**< Bit mask for USB_PTXFEMPMSK */
 #define _USB_GINTMSK_PTXFEMPMSK_DEFAULT            0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
 #define USB_GINTMSK_PTXFEMPMSK_DEFAULT             (_USB_GINTMSK_PTXFEMPMSK_DEFAULT << 26)      /**< Shifted mode DEFAULT for USB_GINTMSK */
-#define USB_GINTMSK_CONIDSTSCHNGMSK                (0x1UL << 28)                                /**< Connector ID Status Change Mask (host and device) */
+#define USB_GINTMSK_CONIDSTSCHNGMSK                (0x1UL << 28)                                /**< Connector ID Status Change Mask host and device */
 #define _USB_GINTMSK_CONIDSTSCHNGMSK_SHIFT         28                                           /**< Shift value for USB_CONIDSTSCHNGMSK */
 #define _USB_GINTMSK_CONIDSTSCHNGMSK_MASK          0x10000000UL                                 /**< Bit mask for USB_CONIDSTSCHNGMSK */
 #define _USB_GINTMSK_CONIDSTSCHNGMSK_DEFAULT       0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
 #define USB_GINTMSK_CONIDSTSCHNGMSK_DEFAULT        (_USB_GINTMSK_CONIDSTSCHNGMSK_DEFAULT << 28) /**< Shifted mode DEFAULT for USB_GINTMSK */
-#define USB_GINTMSK_DISCONNINTMSK                  (0x1UL << 29)                                /**< Disconnect Detected Interrupt Mask (host and device) */
+#define USB_GINTMSK_DISCONNINTMSK                  (0x1UL << 29)                                /**< Disconnect Detected Interrupt Mask host and device */
 #define _USB_GINTMSK_DISCONNINTMSK_SHIFT           29                                           /**< Shift value for USB_DISCONNINTMSK */
 #define _USB_GINTMSK_DISCONNINTMSK_MASK            0x20000000UL                                 /**< Bit mask for USB_DISCONNINTMSK */
 #define _USB_GINTMSK_DISCONNINTMSK_DEFAULT         0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
 #define USB_GINTMSK_DISCONNINTMSK_DEFAULT          (_USB_GINTMSK_DISCONNINTMSK_DEFAULT << 29)   /**< Shifted mode DEFAULT for USB_GINTMSK */
-#define USB_GINTMSK_SESSREQINTMSK                  (0x1UL << 30)                                /**< Session Request/New Session Detected Interrupt Mask (host and device) */
+#define USB_GINTMSK_SESSREQINTMSK                  (0x1UL << 30)                                /**< Session Request/New Session Detected Interrupt Mask host and device */
 #define _USB_GINTMSK_SESSREQINTMSK_SHIFT           30                                           /**< Shift value for USB_SESSREQINTMSK */
 #define _USB_GINTMSK_SESSREQINTMSK_MASK            0x40000000UL                                 /**< Bit mask for USB_SESSREQINTMSK */
 #define _USB_GINTMSK_SESSREQINTMSK_DEFAULT         0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
 #define USB_GINTMSK_SESSREQINTMSK_DEFAULT          (_USB_GINTMSK_SESSREQINTMSK_DEFAULT << 30)   /**< Shifted mode DEFAULT for USB_GINTMSK */
-#define USB_GINTMSK_WKUPINTMSK                     (0x1UL << 31)                                /**< Resume/Remote Wakeup Detected Interrupt Mask (host and device) */
+#define USB_GINTMSK_WKUPINTMSK                     (0x1UL << 31)                                /**< Resume/Remote Wakeup Detected Interrupt Mask host and device */
 #define _USB_GINTMSK_WKUPINTMSK_SHIFT              31                                           /**< Shift value for USB_WKUPINTMSK */
 #define _USB_GINTMSK_WKUPINTMSK_MASK               0x80000000UL                                 /**< Bit mask for USB_WKUPINTMSK */
 #define _USB_GINTMSK_WKUPINTMSK_DEFAULT            0x00000000UL                                 /**< Mode DEFAULT for USB_GINTMSK */
@@ -2657,5 +2653,5 @@
 #define USB_FIFORAM_FIFORAM_DEFAULT                (_USB_FIFORAM_FIFORAM_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_FIFORAM */
 
 /** @} End of group EFM32WG_USB */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_usb_diep.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_usb_diep.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32wg_usb_diep.h
  * @brief EFM32WG_USB_DIEP register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @brief USB_DIEP EFM32WG USB DIEP
  *****************************************************************************/
 typedef struct
@@ -41,7 +45,9 @@
   __IO uint32_t TSIZ;         /**< Device IN Endpoint x+1 Transfer Size Register  */
   __IO uint32_t DMAADDR;      /**< Device IN Endpoint x+1 DMA Address Register  */
   __I uint32_t  TXFSTS;       /**< Device IN Endpoint x+1 Transmit FIFO Status Register  */
-
   uint32_t      RESERVED2[1]; /**< Reserved future */
 } USB_DIEP_TypeDef;
 
+/** @} End of group Parts */
+
+

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_usb_doep.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_usb_doep.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32wg_usb_doep.h
  * @brief EFM32WG_USB_DOEP register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @brief USB_DOEP EFM32WG USB DOEP
  *****************************************************************************/
 typedef struct
@@ -40,7 +44,9 @@
   uint32_t      RESERVED1[1]; /**< Reserved for future use **/
   __IO uint32_t TSIZ;         /**< Device OUT Endpoint x+1 Transfer Size Register  */
   __IO uint32_t DMAADDR;      /**< Device OUT Endpoint x+1 DMA Address Register  */
-
   uint32_t      RESERVED2[2]; /**< Reserved future */
 } USB_DOEP_TypeDef;
 
+/** @} End of group Parts */
+
+

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_usb_hc.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_usb_hc.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32wg_usb_hc.h
  * @brief EFM32WG_USB_HC register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @brief USB_HC EFM32WG USB HC
  *****************************************************************************/
 typedef struct
@@ -40,7 +44,9 @@
   __IO uint32_t INTMSK;       /**< Host Channel x Interrupt Mask Register  */
   __IO uint32_t TSIZ;         /**< Host Channel x Transfer Size Register  */
   __IO uint32_t DMAADDR;      /**< Host Channel x DMA Address Register  */
-
   uint32_t      RESERVED1[2]; /**< Reserved future */
 } USB_HC_TypeDef;
 
+/** @} End of group Parts */
+
+

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_vcmp.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_vcmp.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32wg_vcmp.h
  * @brief EFM32WG_VCMP register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32WG_VCMP
  * @{
  * @brief EFM32WG_VCMP Register Declaration
@@ -192,5 +196,5 @@
 #define VCMP_IFC_WARMUP_DEFAULT             (_VCMP_IFC_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for VCMP_IFC */
 
 /** @} End of group EFM32WG_VCMP */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_wdog.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_wdog.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32wg_wdog.h
  * @brief EFM32WG_WDOG register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32WG_WDOG
  * @{
  * @brief EFM32WG_WDOG Register Declaration
@@ -128,5 +132,5 @@
 #define WDOG_SYNCBUSY_CMD_DEFAULT        (_WDOG_SYNCBUSY_CMD_DEFAULT << 1)  /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */
 
 /** @} End of group EFM32WG_WDOG */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/em_device.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/em_device.h	Fri Jan 15 07:45:16 2016 +0000
@@ -9,11 +9,13 @@
  * @verbatim
  * Example: Add "-DEFM32G890F128" to your build options, to define part
  *          Add "#include "em_device.h" to your source files
+ *
+ *
  * @endverbatim
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -29,19 +31,18 @@
  * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
  * has no obligation to support this Software. Silicon Laboratories, Inc. is
  * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of 
+ * kind, including, but not limited to, any implied warranties of
  * merchantability or fitness for any particular purpose or warranties against
  * infringement of any proprietary rights of a third party.
  *
- * Silicon Laboratories, Inc. will not be liable for any consequential, 
- * incidental, or special damages, or any other relief, or for any claim by 
+ * Silicon Laboratories, Inc. will not be liable for any consequential,
+ * incidental, or special damages, or any other relief, or for any claim by
  * any third party, arising from your use of this Software.
  *
  *****************************************************************************/
 
-#ifndef __EM_DEVICE_H
-#define __EM_DEVICE_H
-
+#ifndef EM_DEVICE_H
+#define EM_DEVICE_H
 
 #if defined(EFM32WG230F128)
 #include "efm32wg230f128.h"
@@ -106,6 +107,15 @@
 #elif defined(EFM32WG332F64)
 #include "efm32wg332f64.h"
 
+#elif defined(EFM32WG360F128)
+#include "efm32wg360f128.h"
+
+#elif defined(EFM32WG360F256)
+#include "efm32wg360f256.h"
+
+#elif defined(EFM32WG360F64)
+#include "efm32wg360f64.h"
+
 #elif defined(EFM32WG380F128)
 #include "efm32wg380f128.h"
 
@@ -178,6 +188,9 @@
 #elif defined(EFM32WG895F64)
 #include "efm32wg895f64.h"
 
+#elif defined(EFM32WG900F256)
+#include "efm32wg900f256.h"
+
 #elif defined(EFM32WG940F128)
 #include "efm32wg940f128.h"
 
@@ -223,9 +236,7 @@
 #elif defined(EFM32WG995F64)
 #include "efm32wg995f64.h"
 
-
 #else
 #error "em_device.h: PART NUMBER undefined"
 #endif
-
-#endif
+#endif /* EM_DEVICE_H */

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/system_efm32wg.c	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/system_efm32wg.c	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /***************************************************************************//**
  * @file system_efm32wg.c
  * @brief CMSIS Cortex-M4 System Layer for EFM32WG devices.
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -20,12 +20,12 @@
  * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
  * has no obligation to support this Software. Silicon Laboratories, Inc. is
  * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of 
+ * kind, including, but not limited to, any implied warranties of
  * merchantability or fitness for any particular purpose or warranties against
  * infringement of any proprietary rights of a third party.
  *
- * Silicon Laboratories, Inc. will not be liable for any consequential, 
- * incidental, or special damages, or any other relief, or for any claim by 
+ * Silicon Laboratories, Inc. will not be liable for any consequential,
+ * incidental, or special damages, or any other relief, or for any claim by
  * any third party, arising from your use of this Software.
  *
  *****************************************************************************/
@@ -54,27 +54,27 @@
 /* SW footprint. */
 
 #ifndef EFM32_HFXO_FREQ
-#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
-#define EFM32_HFXO_FREQ (48000000UL)        
-#else
-#define EFM32_HFXO_FREQ (32000000UL)
+#define EFM32_HFXO_FREQ (48000000UL)
 #endif
-#endif
+
+#define EFM32_HFRCO_MAX_FREQ (28000000UL)
+
 /* Do not define variable if HF crystal oscillator not present */
 #if (EFM32_HFXO_FREQ > 0)
 /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
-/** System HFXO clock. */ 
+/** System HFXO clock. */
 static uint32_t SystemHFXOClock = EFM32_HFXO_FREQ;
 /** @endcond (DO_NOT_INCLUDE_WITH_DOXYGEN) */
 #endif
 
-#ifndef EFM32_LFXO_FREQ 
+#ifndef EFM32_LFXO_FREQ
 #define EFM32_LFXO_FREQ (EFM32_LFRCO_FREQ)
 #endif
+
 /* Do not define variable if LF crystal oscillator not present */
 #if (EFM32_LFXO_FREQ > 0)
 /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
-/** System LFXO clock. */ 
+/** System LFXO clock. */
 static uint32_t SystemLFXOClock = EFM32_LFXO_FREQ;
 /** @endcond (DO_NOT_INCLUDE_WITH_DOXYGEN) */
 #endif
@@ -123,13 +123,11 @@
 uint32_t SystemCoreClockGet(void)
 {
   uint32_t ret;
-  
+
   ret = SystemHFClockGet();
-#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
   /* Leopard/Giant/Wonder Gecko has an additional divider */
   ret =  ret / (1 + ((CMU->CTRL & _CMU_CTRL_HFCLKDIV_MASK)>>_CMU_CTRL_HFCLKDIV_SHIFT));
-#endif
-  ret >>= (CMU->HFCORECLKDIV & _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK) >> 
+  ret >>= (CMU->HFCORECLKDIV & _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK) >>
           _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT;
 
   /* Keep CMSIS variable up-to-date just in case */
@@ -141,6 +139,23 @@
 
 /***************************************************************************//**
  * @brief
+ *   Get the maximum core clock frequency.
+ *
+ * @note
+ *   This is an EFR32 proprietary function, not part of the CMSIS definition.
+ *
+ * @return
+ *   The maximum core clock frequency in Hz.
+ ******************************************************************************/
+uint32_t SystemMaxCoreClockGet(void)
+{
+  return (EFM32_HFRCO_MAX_FREQ > EFM32_HFXO_FREQ ? \
+          EFM32_HFRCO_MAX_FREQ : EFM32_HFXO_FREQ);
+}
+
+
+/***************************************************************************//**
+ * @brief
  *   Get the current HFCLK frequency.
  *
  * @note
@@ -152,7 +167,7 @@
 uint32_t SystemHFClockGet(void)
 {
   uint32_t ret;
-  
+
   switch (CMU->STATUS & (CMU_STATUS_HFRCOSEL | CMU_STATUS_HFXOSEL |
                          CMU_STATUS_LFRCOSEL | CMU_STATUS_LFXOSEL))
   {
@@ -165,11 +180,11 @@
       ret = 0;
 #endif
       break;
-      
+
     case CMU_STATUS_LFRCOSEL:
       ret = EFM32_LFRCO_FREQ;
       break;
-      
+
     case CMU_STATUS_HFXOSEL:
 #if (EFM32_HFXO_FREQ > 0)
       ret = SystemHFXOClock;
@@ -179,7 +194,7 @@
       ret = 0;
 #endif
       break;
-      
+
     default: /* CMU_STATUS_HFRCOSEL */
       switch (CMU->HFRCOCTRL & _CMU_HFRCOCTRL_BAND_MASK)
       {

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/system_efm32wg.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/system_efm32wg.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /***************************************************************************//**
  * @file system_efm32wg.h
  * @brief CMSIS Cortex-M4 System Layer for EFM32WG devices.
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,8 +30,8 @@
  *
  *****************************************************************************/
 
-#ifndef __SYSTEM_EFM32WG_H
-#define __SYSTEM_EFM32WG_H
+#ifndef SYSTEM_EFM32WG_H
+#define SYSTEM_EFM32WG_H
 
 #ifdef __cplusplus
 extern "C" {
@@ -50,7 +50,6 @@
  ******************************************************************************/
 
 /* Interrupt routines - prototypes */
-#if defined(_EFM32_WONDER_FAMILY)
 void Reset_Handler(void);
 void NMI_Handler(void);
 void HardFault_Handler(void);
@@ -61,6 +60,7 @@
 void DebugMon_Handler(void);
 void PendSV_Handler(void);
 void SysTick_Handler(void);
+
 void DMA_IRQHandler(void);
 void GPIO_EVEN_IRQHandler(void);
 void TIMER0_IRQHandler(void);
@@ -101,9 +101,9 @@
 void EBI_IRQHandler(void);
 void EMU_IRQHandler(void);
 void FPUEH_IRQHandler(void);
-#endif
 
 uint32_t SystemCoreClockGet(void);
+uint32_t SystemMaxCoreClockGet(void);
 
 /**************************************************************************//**
  * @brief
@@ -136,4 +136,4 @@
 #ifdef __cplusplus
 }
 #endif
-#endif /* __SYSTEM_EFM32WG_H */
+#endif /* SYSTEM_EFM32WG_H */

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/TOOLCHAIN_ARM_MICRO/efm32zg.sct	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/TOOLCHAIN_ARM_MICRO/efm32zg.sct	Fri Jan 15 07:45:16 2016 +0000
@@ -8,7 +8,7 @@
    *(InRoot$$Sections)
    .ANY (+RO)
   }
-  RW_IRAM1 0x20000080 0x00000F80  {  ; RW data
+  RW_IRAM1 0x2000008C 0x00000F74  {  ; RW data
    .ANY (+RW +ZI)
   }
 }

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/TOOLCHAIN_ARM_MICRO/startup_efm32zg.S	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/TOOLCHAIN_ARM_MICRO/startup_efm32zg.S	Fri Jan 15 07:45:16 2016 +0000
@@ -2,7 +2,7 @@
 ; * @file startup_efm32zg.s
 ; * @brief    CMSIS Core Device Startup File for
 ; *           Silicon Labs EFM32ZG Device Series
-; * @version 3.20.6
+; * @version 4.2.1
 ; * @date     03. February 2012
 ; *
 ; * @note
@@ -29,7 +29,7 @@
 ;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
 ; </h>
 
-Stack_Size      EQU     0x00000200
+Stack_Size      EQU     0x00000400
 
                 AREA    STACK, NOINIT, READWRITE, ALIGN=3
 Stack_Mem       SPACE   Stack_Size
@@ -95,6 +95,8 @@
                 DCD     VCMP_IRQHandler        ; 14: VCMP Interrupt
                 DCD     MSC_IRQHandler        ; 15: MSC Interrupt
                 DCD     AES_IRQHandler        ; 16: AES Interrupt
+                DCD     0                         ; 17: Reserved
+                DCD     0                         ; 18: Reserved
 
 __Vectors_End
 __Vectors_Size  EQU     __Vectors_End - __Vectors
@@ -177,9 +179,7 @@
 MSC_IRQHandler
 AES_IRQHandler
 
-
                 B       .
-
                 ENDP
 
                 ALIGN

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/TOOLCHAIN_GCC_ARM/efm32zg.ld	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/TOOLCHAIN_GCC_ARM/efm32zg.ld	Fri Jan 15 07:45:16 2016 +0000
@@ -4,25 +4,34 @@
 /* CMSIS END USER LICENSE AGREEMENT.pdf, governing the use of       */
 /* Example Code.                                                    */
 /*                                                                  */
-/* Silicon Laboratories, Inc. 2014                                  */
+/* Silicon Laboratories, Inc. 2015                                  */
+/*                                                                  */
+/* Version 4.2.0 */
+/*                                                                  */
+
 MEMORY
 {
   FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32768
   RAM (rwx)  : ORIGIN = 0x20000000, LENGTH = 4096
 }
+
 /* MBED: mbed needs to be able to dynamically set the interrupt vector table.
  * We make room for the table at the very beginning of RAM, i.e. at
- * 0x20000000. We need (16+16) * sizeof(uint32_t) = 128 bytes for EFM32ZG */
-__vector_size = 0x80;
+ * 0x20000000. We need (16+19) * sizeof(uint32_t) = 140 bytes for EFM32ZG */
+__vector_size = 0x8C;
 
 /* Linker script to place sections and symbol values. Should be used together
  * with other linker script that defines memory regions FLASH and RAM.
  * It references following symbols, which must be defined in code:
  *   Reset_Handler : Entry of reset handler
- * 
+ *
  * It defines following symbols, which code can use without definition:
  *   __exidx_start
  *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
  *   __etext
  *   __data_start__
  *   __preinit_array_start
@@ -40,6 +49,8 @@
  *   __StackLimit
  *   __StackTop
  *   __stack
+ *   __Vectors_End
+ *   __Vectors_Size
  */
 ENTRY(Reset_Handler)
 
@@ -47,7 +58,11 @@
 {
   .text :
   {
-    KEEP(*(.isr_vector))
+    KEEP(*(.vectors))
+    __Vectors_End = .;
+    __Vectors_Size = __Vectors_End - __Vectors;
+    __end__ = .;
+
     *(.text*)
 
     KEEP(*(.init))
@@ -72,7 +87,7 @@
     KEEP(*(.eh_frame*))
   } > FLASH
 
-  .ARM.extab : 
+  .ARM.extab :
   {
     *(.ARM.extab* .gnu.linkonce.armextab.*)
   } > FLASH
@@ -84,15 +99,49 @@
   } > FLASH
   __exidx_end = .;
 
+  /* To copy multiple ROM to RAM sections,
+   * uncomment .copy.table section and,
+   * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+  /*
+  .copy.table :
+  {
+    . = ALIGN(4);
+    __copy_table_start__ = .;
+    LONG (__etext)
+    LONG (__data_start__)
+    LONG (__data_end__ - __data_start__)
+    LONG (__etext2)
+    LONG (__data2_start__)
+    LONG (__data2_end__ - __data2_start__)
+    __copy_table_end__ = .;
+  } > FLASH
+  */
+
+  /* To clear multiple BSS sections,
+   * uncomment .zero.table section and,
+   * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+  /*
+  .zero.table :
+  {
+    . = ALIGN(4);
+    __zero_table_start__ = .;
+    LONG (__bss_start__)
+    LONG (__bss_end__ - __bss_start__)
+    LONG (__bss2_start__)
+    LONG (__bss2_end__ - __bss2_start__)
+    __zero_table_end__ = .;
+  } > FLASH
+  */
+
   __etext = .;
-  
+
   .data : AT (__etext)
   {
     __data_start__ = .;
     *("dma")
     PROVIDE( __start_vector_table__ = .);
-  	. += __vector_size;
-  	PROVIDE( __end_vector_table__ = .);
+    . += __vector_size;
+    PROVIDE( __end_vector_table__ = .);
     *(vtable)
     *(.data*)
     . = ALIGN (4);
@@ -118,6 +167,7 @@
     KEEP(*(.fini_array))
     PROVIDE_HIDDEN (__fini_array_end = .);
 
+    KEEP(*(.jcr*))
     . = ALIGN(4);
     /* All data end */
     __data_end__ = .;
@@ -126,27 +176,30 @@
 
   .bss :
   {
+    . = ALIGN(4);
     __bss_start__ = .;
     *(.bss*)
     *(COMMON)
+    . = ALIGN(4);
     __bss_end__ = .;
   } > RAM
 
-  .heap :
+  .heap (COPY):
   {
+    __HeapBase = .;
     __end__ = .;
     end = __end__;
     _end = __end__;
-    *(.heap*)
+    KEEP(*(.heap*))
     __HeapLimit = .;
   } > RAM
 
   /* .stack_dummy section doesn't contains any symbols. It is only
    * used for linker to calculate size of stack sections, and assign
    * values to stack symbols later */
-  .stack_dummy :
+  .stack_dummy (COPY):
   {
-    *(.stack)
+    KEEP(*(.stack*))
   } > RAM
 
   /* Set stack top to end of RAM, and stack limit move down by
@@ -157,4 +210,7 @@
 
   /* Check if data + heap + stack exceeds RAM limit */
   ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+
+  /* Check if FLASH usage exceeds FLASH size */
+  ASSERT( LENGTH(FLASH) >= (__etext + SIZEOF(.data)), "FLASH memory overflowed !")
 }

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/TOOLCHAIN_GCC_ARM/startup_efm32zg.S	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/TOOLCHAIN_GCC_ARM/startup_efm32zg.S	Fri Jan 15 07:45:16 2016 +0000
@@ -1,185 +1,303 @@
 /* @file startup_efm32zg.S
  * @brief startup file for Silicon Labs EFM32ZG devices.
  *        For use with GCC for ARM Embedded Processors
- * @version 3.20.6
- * Date: 08 Feb 2012
- *
- * Copyright (c) 2012, ARM Limited
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
-    * Redistributions of source code must retain the above copyright
-      notice, this list of conditions and the following disclaimer.
-    * Redistributions in binary form must reproduce the above copyright
-      notice, this list of conditions and the following disclaimer in the
-      documentation and/or other materials provided with the distribution.
-    * Neither the name of the ARM Limited nor the
-      names of its contributors may be used to endorse or promote products
-      derived from this software without specific prior written permission.
+ * @version 4.2.1
+ * Date:    12 June 2014
  *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
-    .syntax unified
-    .arch armv6-m
+/* Copyright (c) 2011 - 2014 ARM LIMITED
 
-    .section .stack
-    .align 3
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+    .syntax     unified
+    .arch       armv6-m
+
+    .section    .stack
+    .align      3
 #ifdef __STACK_SIZE
-    .equ    Stack_Size, __STACK_SIZE
+    .equ        Stack_Size, __STACK_SIZE
 #else
-    .equ    Stack_Size, 0x200
+    .equ        Stack_Size, 0x00000400
 #endif
-    .globl    __StackTop
-    .globl    __StackLimit
+    .globl      __StackTop
+    .globl      __StackLimit
 __StackLimit:
-    .space    Stack_Size
-    .size __StackLimit, . - __StackLimit
+    .space      Stack_Size
+    .size       __StackLimit, . - __StackLimit
 __StackTop:
-    .size __StackTop, . - __StackTop
+    .size       __StackTop, . - __StackTop
 
-    .section .heap
-    .align 3
+    .section    .heap
+    .align      3
 #ifdef __HEAP_SIZE
-    .equ    Heap_Size, __HEAP_SIZE
+    .equ        Heap_Size, __HEAP_SIZE
 #else
-    .equ    Heap_Size, 0x0
+    .equ        Heap_Size, 0x00000000
 #endif
-    .globl    __HeapBase
-    .globl    __HeapLimit
+    .globl      __HeapBase
+    .globl      __HeapLimit
 __HeapBase:
-    .if    Heap_Size
-    .space    Heap_Size
+    .if Heap_Size
+    .space      Heap_Size
     .endif
-    .size __HeapBase, . - __HeapBase
+    .size       __HeapBase, . - __HeapBase
 __HeapLimit:
-    .size __HeapLimit, . - __HeapLimit
+    .size       __HeapLimit, . - __HeapLimit
 
-    .section .isr_vector
-    .align 8
-    .globl __isr_vector
-__isr_vector:
-    .long    __StackTop            /* Top of Stack */
-    .long    Reset_Handler         /* Reset Handler */
-    .long    NMI_Handler           /* NMI Handler */
-    .long    HardFault_Handler     /* Hard Fault Handler */
-    .long    Default_Handler       /* Reserved */
-    .long    Default_Handler       /* Reserved */
-    .long    Default_Handler       /* Reserved */
-    .long    Default_Handler       /* Reserved */
-    .long    Default_Handler       /* Reserved */
-    .long    Default_Handler       /* Reserved */
-    .long    Default_Handler       /* Reserved */
-    .long    SVC_Handler           /* SVCall Handler */
-    .long    Default_Handler       /* Reserved */
-    .long    Default_Handler       /* Reserved */
-    .long    PendSV_Handler        /* PendSV Handler */
-    .long    SysTick_Handler       /* SysTick Handler */
+    .section    .vectors
+    .align      2
+    .globl      __Vectors
+__Vectors:
+    .long       __StackTop            /* Top of Stack */
+    .long       Reset_Handler         /* Reset Handler */
+    .long       NMI_Handler           /* NMI Handler */
+    .long       HardFault_Handler     /* Hard Fault Handler */
+    .long       Default_Handler       /* Reserved */
+    .long       Default_Handler       /* Reserved */
+    .long       Default_Handler       /* Reserved */
+    .long       Default_Handler       /* Reserved */
+    .long       Default_Handler       /* Reserved */
+    .long       Default_Handler       /* Reserved */
+    .long       Default_Handler       /* Reserved */
+    .long       SVC_Handler           /* SVCall Handler */
+    .long       Default_Handler       /* Reserved */
+    .long       Default_Handler       /* Reserved */
+    .long       PendSV_Handler        /* PendSV Handler */
+    .long       SysTick_Handler       /* SysTick Handler */
 
     /* External interrupts */
-    .long    DMA_IRQHandler    /* 0 - DMA */
-    .long    GPIO_EVEN_IRQHandler    /* 1 - GPIO_EVEN */
-    .long    TIMER0_IRQHandler    /* 2 - TIMER0 */
-    .long    ACMP0_IRQHandler    /* 3 - ACMP0 */
-    .long    ADC0_IRQHandler    /* 4 - ADC0 */
-    .long    I2C0_IRQHandler    /* 5 - I2C0 */
-    .long    GPIO_ODD_IRQHandler    /* 6 - GPIO_ODD */
-    .long    TIMER1_IRQHandler    /* 7 - TIMER1 */
-    .long    USART1_RX_IRQHandler    /* 8 - USART1_RX */
-    .long    USART1_TX_IRQHandler    /* 9 - USART1_TX */
-    .long    LEUART0_IRQHandler    /* 10 - LEUART0 */
-    .long    PCNT0_IRQHandler    /* 11 - PCNT0 */
-    .long    RTC_IRQHandler    /* 12 - RTC */
-    .long    CMU_IRQHandler    /* 13 - CMU */
-    .long    VCMP_IRQHandler    /* 14 - VCMP */
-    .long    MSC_IRQHandler    /* 15 - MSC */
-    .long    AES_IRQHandler    /* 16 - AES */
+
+    .long       DMA_IRQHandler    /* 0 - DMA */
+    .long       GPIO_EVEN_IRQHandler    /* 1 - GPIO_EVEN */
+    .long       TIMER0_IRQHandler    /* 2 - TIMER0 */
+    .long       ACMP0_IRQHandler    /* 3 - ACMP0 */
+    .long       ADC0_IRQHandler    /* 4 - ADC0 */
+    .long       I2C0_IRQHandler    /* 5 - I2C0 */
+    .long       GPIO_ODD_IRQHandler    /* 6 - GPIO_ODD */
+    .long       TIMER1_IRQHandler    /* 7 - TIMER1 */
+    .long       USART1_RX_IRQHandler    /* 8 - USART1_RX */
+    .long       USART1_TX_IRQHandler    /* 9 - USART1_TX */
+    .long       LEUART0_IRQHandler    /* 10 - LEUART0 */
+    .long       PCNT0_IRQHandler    /* 11 - PCNT0 */
+    .long       RTC_IRQHandler    /* 12 - RTC */
+    .long       CMU_IRQHandler    /* 13 - CMU */
+    .long       VCMP_IRQHandler    /* 14 - VCMP */
+    .long       MSC_IRQHandler    /* 15 - MSC */
+    .long       AES_IRQHandler    /* 16 - AES */
+    .long       Default_Handler    /* 17 - Reserved */
+    .long       Default_Handler    /* 18 - Reserved */
 
 
-    .size    __isr_vector, . - __isr_vector
+    .size       __Vectors, . - __Vectors
 
     .text
     .thumb
     .thumb_func
-    .align 2
-    .globl    Reset_Handler
-    .type    Reset_Handler, %function
+    .align      2
+    .globl      Reset_Handler
+    .type       Reset_Handler, %function
 Reset_Handler:
-/*     Loop to copy data from read only memory to RAM. The ranges
- *      of copy from/to are specified by following symbols evaluated in
- *      linker script.
- *      __etext: End of code section, i.e., begin of data sections to copy from.
- *      __data_start__/__data_end__: RAM address range that data should be
- *      copied to. Both must be aligned to 4 bytes boundary.  */
 #ifndef __NO_SYSTEM_INIT
-    ldr    r0, =SystemInit
-    blx    r0
+    ldr     r0, =SystemInit
+    blx     r0
 #endif
-    ldr    r1, =__etext
-    ldr    r2, =__data_start__
-    ldr    r3, =__data_end__
+
+/*  Firstly it copies data from read only memory to RAM. There are two schemes
+ *  to copy. One can copy more than one sections. Another can only copy
+ *  one section.  The former scheme needs more instructions and read-only
+ *  data to implement than the latter.
+ *  Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.  */
+
+#ifdef __STARTUP_COPY_MULTIPLE
+/*  Multiple sections scheme.
+ *
+ *  Between symbol address __copy_table_start__ and __copy_table_end__,
+ *  there are array of triplets, each of which specify:
+ *    offset 0: LMA of start of a section to copy from
+ *    offset 4: VMA of start of a section to copy to
+ *    offset 8: size of the section to copy. Must be multiply of 4
+ *
+ *  All addresses must be aligned to 4 bytes boundary.
+ */
+    ldr     r4, =__copy_table_start__
+    ldr     r5, =__copy_table_end__
+
+.L_loop0:
+    cmp     r4, r5
+    bge     .L_loop0_done
+    ldr     r1, [r4]
+    ldr     r2, [r4, #4]
+    ldr     r3, [r4, #8]
+
+.L_loop0_0:
+    subs    r3, #4
+    blt     .L_loop0_0_done
+    ldr     r0, [r1, r3]
+    str     r0, [r2, r3]
+    b       .L_loop0_0
+
+.L_loop0_0_done:
+    adds    r4, #12
+    b       .L_loop0
+
+.L_loop0_done:
+#else
+/*  Single section scheme.
+ *
+ *  The ranges of copy from/to are specified by following symbols
+ *    __etext: LMA of start of the section to copy from. Usually end of text
+ *    __data_start__: VMA of start of the section to copy to
+ *    __data_end__: VMA of end of the section to copy to
+ *
+ *  All addresses must be aligned to 4 bytes boundary.
+ */
+    ldr     r1, =__etext
+    ldr     r2, =__data_start__
+    ldr     r3, =__data_end__
+
+    subs    r3, r2
+    ble     .L_loop1_done
+
+.L_loop1:
+    subs    r3, #4
+    ldr     r0, [r1,r3]
+    str     r0, [r2,r3]
+    bgt     .L_loop1
+
+.L_loop1_done:
+#endif /*__STARTUP_COPY_MULTIPLE */
 
-    subs   r3, r2
-    ble    .flash_to_ram_loop_end
-.flash_to_ram_loop:
-    subs   r3, #4
-    ldr    r0, [r1, r3]
-    str    r0, [r2, r3]
-    bgt    .flash_to_ram_loop
-.flash_to_ram_loop_end:
+/*  This part of work usually is done in C library startup code. Otherwise,
+ *  define this macro to enable it in this startup.
+ *
+ *  There are two schemes too. One can clear multiple BSS sections. Another
+ *  can only clear one section. The former is more size expensive than the
+ *  latter.
+ *
+ *  Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ *  Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ */
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
+/*  Multiple sections scheme.
+ *
+ *  Between symbol address __copy_table_start__ and __copy_table_end__,
+ *  there are array of tuples specifying:
+ *    offset 0: Start of a BSS section
+ *    offset 4: Size of this BSS section. Must be multiply of 4
+ */
+    ldr     r3, =__zero_table_start__
+    ldr     r4, =__zero_table_end__
+
+.L_loop2:
+    cmp     r3, r4
+    bge     .L_loop2_done
+    ldr     r1, [r3]
+    ldr     r2, [r3, #4]
+    movs    r0, 0
+
+.L_loop2_0:
+    subs    r2, #4
+    blt     .L_loop2_0_done
+    str     r0, [r1, r2]
+    b       .L_loop2_0
+.L_loop2_0_done:
 
-    ldr    r0, =_start
-    bx     r0
+    adds    r3, #8
+    b       .L_loop2
+.L_loop2_done:
+#elif defined (__STARTUP_CLEAR_BSS)
+/*  Single BSS section scheme.
+ *
+ *  The BSS section is specified by following symbols
+ *    __bss_start__: start of the BSS section.
+ *    __bss_end__: end of the BSS section.
+ *
+ *  Both addresses must be aligned to 4 bytes boundary.
+ */
+    ldr     r1, =__bss_start__
+    ldr     r2, =__bss_end__
+
+    movs    r0, 0
+    subs    r2, r1
+    ble     .L_loop3_done
+
+.L_loop3:
+    subs    r2, #4
+    str     r0, [r1, r2]
+    bgt     .L_loop3
+.L_loop3_done:
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
+
+#ifndef __START
+#define __START _start
+#endif
+    bl      __START
+
     .pool
-    .size Reset_Handler, . - Reset_Handler
+    .size   Reset_Handler, . - Reset_Handler
+
+    .align  1
+    .thumb_func
+    .weak   Default_Handler
+    .type   Default_Handler, %function
+Default_Handler:
+    b       .
+    .size   Default_Handler, . - Default_Handler
 
 /*    Macro to define default handlers. Default handler
  *    will be weak symbol and just dead loops. They can be
  *    overwritten by other handlers */
-    .macro    def_irq_handler    handler_name
-    .align 1
-    .thumb_func
-    .weak    \handler_name
-    .type    \handler_name, %function
-\handler_name:
-    b    .
-    .size    \handler_name, . - \handler_name
+    .macro  def_irq_handler	handler_name
+    .weak   \handler_name
+    .set    \handler_name, Default_Handler
     .endm
 
-    def_irq_handler    Default_Handler
-
-    def_irq_handler    NMI_Handler
-    def_irq_handler    HardFault_Handler
-    def_irq_handler    SVC_Handler
-    def_irq_handler    PendSV_Handler
-    def_irq_handler    SysTick_Handler
+    def_irq_handler     NMI_Handler
+    def_irq_handler     HardFault_Handler
+    def_irq_handler     SVC_Handler
+    def_irq_handler     PendSV_Handler
+    def_irq_handler     SysTick_Handler
 
-    def_irq_handler    DMA_IRQHandler
-    def_irq_handler    GPIO_EVEN_IRQHandler
-    def_irq_handler    TIMER0_IRQHandler
-    def_irq_handler    ACMP0_IRQHandler
-    def_irq_handler    ADC0_IRQHandler
-    def_irq_handler    I2C0_IRQHandler
-    def_irq_handler    GPIO_ODD_IRQHandler
-    def_irq_handler    TIMER1_IRQHandler
-    def_irq_handler    USART1_RX_IRQHandler
-    def_irq_handler    USART1_TX_IRQHandler
-    def_irq_handler    LEUART0_IRQHandler
-    def_irq_handler    PCNT0_IRQHandler
-    def_irq_handler    RTC_IRQHandler
-    def_irq_handler    CMU_IRQHandler
-    def_irq_handler    VCMP_IRQHandler
-    def_irq_handler    MSC_IRQHandler
-    def_irq_handler    AES_IRQHandler
+    def_irq_handler     DMA_IRQHandler
+    def_irq_handler     GPIO_EVEN_IRQHandler
+    def_irq_handler     TIMER0_IRQHandler
+    def_irq_handler     ACMP0_IRQHandler
+    def_irq_handler     ADC0_IRQHandler
+    def_irq_handler     I2C0_IRQHandler
+    def_irq_handler     GPIO_ODD_IRQHandler
+    def_irq_handler     TIMER1_IRQHandler
+    def_irq_handler     USART1_RX_IRQHandler
+    def_irq_handler     USART1_TX_IRQHandler
+    def_irq_handler     LEUART0_IRQHandler
+    def_irq_handler     PCNT0_IRQHandler
+    def_irq_handler     RTC_IRQHandler
+    def_irq_handler     CMU_IRQHandler
+    def_irq_handler     VCMP_IRQHandler
+    def_irq_handler     MSC_IRQHandler
+    def_irq_handler     AES_IRQHandler
 
 
     .end

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/cmsis_nvic.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/cmsis_nvic.h	Fri Jan 15 07:45:16 2016 +0000
@@ -2,14 +2,14 @@
  * Copyright (c) 2009-2011 ARM Limited. All rights reserved.
  *
  * CMSIS-style functionality to support dynamic vectors
- */ 
+ */
 
 #ifndef MBED_CMSIS_NVIC_H
 #define MBED_CMSIS_NVIC_H
 
 #include "cmsis.h"
 
-#define NVIC_NUM_VECTORS      (16 + 16)   // CORE + MCU Peripherals
+#define NVIC_NUM_VECTORS      (16 + 19)   // CORE + MCU Peripherals
 #define NVIC_USER_IRQ_OFFSET  16
 
 #ifdef __cplusplus

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg222f32.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg222f32.h	Fri Jan 15 07:45:16 2016 +0000
@@ -2,10 +2,10 @@
  * @file efm32zg222f32.h
  * @brief CMSIS Cortex-M Peripheral Access Layer Header File
  *        for EFM32ZG222F32
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -31,8 +31,8 @@
  *
  *****************************************************************************/
 
-#ifndef __EFM32ZG222F32_H
-#define __EFM32ZG222F32_H
+#ifndef EFM32ZG222F32_H
+#define EFM32ZG222F32_H
 
 #ifdef __cplusplus
 extern "C" {
@@ -52,7 +52,7 @@
 typedef enum IRQn
 {
 /******  Cortex-M0+ Processor Exceptions Numbers *****************************************/
-  NonMaskableInt_IRQn = -14,                /*!< 2 Non Maskable Interrupt                */
+  NonMaskableInt_IRQn = -14,                /*!< 2 Cortex-M0+ Non Maskable Interrupt     */
   HardFault_IRQn      = -13,                /*!< 3 Cortex-M0+ Hard Fault Interrupt       */
   SVCall_IRQn         = -5,                 /*!< 11 Cortex-M0+ SV Call Interrupt         */
   PendSV_IRQn         = -2,                 /*!< 14 Cortex-M0+ Pend SV Interrupt         */
@@ -96,8 +96,10 @@
 ******************************************************************************/
 
 /** Part family */
-#define _EFM32_ZERO_FAMILY    1 /**< Zero Gecko EFM32ZG MCU Family */
-#define _EFM_DEVICE             /**< Silicon Labs EFM-type microcontroller */
+#define _EFM32_ZERO_FAMILY              1 /**< Zero Gecko EFM32ZG MCU Family */
+#define _EFM_DEVICE                       /**< Silicon Labs EFM-type microcontroller */
+#define _SILICON_LABS_32B_PLATFORM_1      /**< Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM      1 /**< Silicon Labs platform name */
 
 /* If part number is not defined as compiler option, define it */
 #if !defined(EFM32ZG222F32)
@@ -138,6 +140,7 @@
 #define __CM0PLUS_REV        0x001          /**< Cortex-M0+ Core revision r0p1 */
 #define PRS_CHAN_COUNT       4              /**< Number of PRS channels */
 #define DMA_CHAN_COUNT       4              /**< Number of DMA channels */
+
 /** AF channels connect the different on-chip peripherals with the af-mux */
 #define AFCHAN_MAX           33
 #define AFCHANLOC_MAX        7
@@ -198,7 +201,9 @@
 #define ANALOG_COUNT        1
 
 /** @} End of group EFM32ZG222F32_Part */
-
+#ifndef ARM_MATH_CM0PLUS
+#define ARM_MATH_CM0PLUS
+#endif
 #include "arm_math.h"       /* To get __CLZ definitions etc. */
 #include "core_cm0plus.h"   /* Cortex-M0+ processor and core peripherals */
 #include "system_efm32zg.h" /* System Header */
@@ -359,4 +364,4 @@
 #ifdef __cplusplus
 }
 #endif
-#endif /* __EFM32ZG222F32_H */
+#endif /* EFM32ZG222F32_H */

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_acmp.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_acmp.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32zg_acmp.h
  * @brief EFM32ZG_ACMP register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32ZG_ACMP
  * @{
  * @brief EFM32ZG_ACMP Register Declaration
@@ -323,5 +327,5 @@
 #define ACMP_ROUTE_LOCATION_LOC2           (_ACMP_ROUTE_LOCATION_LOC2 << 8)    /**< Shifted mode LOC2 for ACMP_ROUTE */
 
 /** @} End of group EFM32ZG_ACMP */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_adc.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_adc.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32zg_adc.h
  * @brief EFM32ZG_ADC register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32ZG_ADC
  * @{
  * @brief EFM32ZG_ADC Register Declaration
@@ -643,5 +647,5 @@
 #define ADC_BIASPROG_COMPBIAS_DEFAULT           (_ADC_BIASPROG_COMPBIAS_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_BIASPROG */
 
 /** @} End of group EFM32ZG_ADC */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_aes.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_aes.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32zg_aes.h
  * @brief EFM32ZG_AES register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32ZG_AES
  * @{
  * @brief EFM32ZG_AES Register Declaration
@@ -189,5 +193,5 @@
 #define AES_KEYLD_KEYLD_DEFAULT         (_AES_KEYLD_KEYLD_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYLD */
 
 /** @} End of group EFM32ZG_AES */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_af_pins.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_af_pins.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32zg_af_pins.h
  * @brief EFM32ZG_AF_PINS register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32ZG_AF_Pins
  * @{
  *****************************************************************************/
@@ -68,5 +72,5 @@
 #define AF_DBG_SWCLK_PIN(i)       ((i) == 0 ? 0 :  -1)
 
 /** @} End of group EFM32ZG_AF_Pins */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_af_ports.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_af_ports.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32zg_af_ports.h
  * @brief EFM32ZG_AF_PORTS register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32ZG_AF_Ports
  * @{
  *****************************************************************************/
@@ -68,5 +72,5 @@
 #define AF_DBG_SWCLK_PORT(i)       ((i) == 0 ? 5 :  -1)
 
 /** @} End of group EFM32ZG_AF_Ports */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_calibrate.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_calibrate.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32zg_calibrate.h
  * @brief EFM32ZG_CALIBRATE register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32ZG_CALIBRATE
  * @{
  *****************************************************************************/
@@ -41,3 +45,6 @@
   __I uint32_t VALUE;   /**< Default value for calibration register */
 } CALIBRATE_TypeDef;    /** @} */
 
+/** @} End of group Parts */
+
+

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_cmu.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_cmu.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32zg_cmu.h
  * @brief EFM32ZG_CMU register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32ZG_CMU
  * @{
  * @brief EFM32ZG_CMU Register Declaration
@@ -60,6 +64,7 @@
   __IO uint32_t LFACLKEN0;    /**< Low Frequency A Clock Enable Register 0  (Async Reg)  */
   uint32_t      RESERVED1[1]; /**< Reserved for future use **/
   __IO uint32_t LFBCLKEN0;    /**< Low Frequency B Clock Enable Register 0 (Async Reg)  */
+
   uint32_t      RESERVED2[1]; /**< Reserved for future use **/
   __IO uint32_t LFAPRESC0;    /**< Low Frequency A Prescaler Register 0 (Async Reg)  */
   uint32_t      RESERVED3[1]; /**< Reserved for future use **/
@@ -79,7 +84,7 @@
 
 /* Bit fields for CMU CTRL */
 #define _CMU_CTRL_RESETVALUE                        0x000C262CUL                             /**< Default value for CMU_CTRL */
-#define _CMU_CTRL_MASK                              0x03FE3EEFUL                             /**< Mask for CMU_CTRL */
+#define _CMU_CTRL_MASK                              0x07FE3EEFUL                             /**< Mask for CMU_CTRL */
 #define _CMU_CTRL_HFXOMODE_SHIFT                    0                                        /**< Shift value for CMU_HFXOMODE */
 #define _CMU_CTRL_HFXOMODE_MASK                     0x3UL                                    /**< Bit mask for CMU_HFXOMODE */
 #define _CMU_CTRL_HFXOMODE_DEFAULT                  0x00000000UL                             /**< Mode DEFAULT for CMU_CTRL */
@@ -180,7 +185,7 @@
 #define CMU_CTRL_CLKOUTSEL0_ULFRCO                  (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20)      /**< Shifted mode ULFRCO for CMU_CTRL */
 #define CMU_CTRL_CLKOUTSEL0_AUXHFRCO                (_CMU_CTRL_CLKOUTSEL0_AUXHFRCO << 20)    /**< Shifted mode AUXHFRCO for CMU_CTRL */
 #define _CMU_CTRL_CLKOUTSEL1_SHIFT                  23                                       /**< Shift value for CMU_CLKOUTSEL1 */
-#define _CMU_CTRL_CLKOUTSEL1_MASK                   0x3800000UL                              /**< Bit mask for CMU_CLKOUTSEL1 */
+#define _CMU_CTRL_CLKOUTSEL1_MASK                   0x7800000UL                              /**< Bit mask for CMU_CLKOUTSEL1 */
 #define _CMU_CTRL_CLKOUTSEL1_DEFAULT                0x00000000UL                             /**< Mode DEFAULT for CMU_CTRL */
 #define _CMU_CTRL_CLKOUTSEL1_LFRCO                  0x00000000UL                             /**< Mode LFRCO for CMU_CTRL */
 #define _CMU_CTRL_CLKOUTSEL1_LFXO                   0x00000001UL                             /**< Mode LFXO for CMU_CTRL */
@@ -973,5 +978,5 @@
 #define CMU_LOCK_LOCKKEY_UNLOCK                     (_CMU_LOCK_LOCKKEY_UNLOCK << 0)   /**< Shifted mode UNLOCK for CMU_LOCK */
 
 /** @} End of group EFM32ZG_CMU */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_devinfo.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_devinfo.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32zg_devinfo.h
  * @brief EFM32ZG_DEVINFO register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32ZG_DEVINFO
  * @{
  *****************************************************************************/
@@ -125,15 +129,28 @@
 #define _DEVINFO_PART_PROD_REV_SHIFT               24           /**< Bit position for production revision */
 #define _DEVINFO_PART_DEVICE_FAMILY_MASK           0x00FF0000UL /**< Device Family, 0x47 for Gecko */
 #define _DEVINFO_PART_DEVICE_FAMILY_SHIFT          16           /**< Bit position for device family */
+/* Legacy family #defines */
 #define _DEVINFO_PART_DEVICE_FAMILY_G              71           /**< Gecko Device Family */
 #define _DEVINFO_PART_DEVICE_FAMILY_GG             72           /**< Giant Gecko Device Family */
 #define _DEVINFO_PART_DEVICE_FAMILY_TG             73           /**< Tiny Gecko Device Family */
 #define _DEVINFO_PART_DEVICE_FAMILY_LG             74           /**< Leopard Gecko Device Family */
 #define _DEVINFO_PART_DEVICE_FAMILY_WG             75           /**< Wonder Gecko Device Family */
 #define _DEVINFO_PART_DEVICE_FAMILY_ZG             76           /**< Zero Gecko Device Family */
+#define _DEVINFO_PART_DEVICE_FAMILY_HG             77           /**< Happy Gecko Device Family */
+/* New style family #defines */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFM32G         71           /**< Gecko Device Family */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFM32GG        72           /**< Giant Gecko Device Family */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFM32TG        73           /**< Tiny Gecko Device Family */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFM32LG        74           /**< Leopard Gecko Device Family */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFM32WG        75           /**< Wonder Gecko Device Family */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFM32ZG        76           /**< Zero Gecko Device Family */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFM32HG        77           /**< Happy Gecko Device Family */
+#define _DEVINFO_PART_DEVICE_FAMILY_EZR32WG        120          /**< EZR Wonder Gecko Device Family */
+#define _DEVINFO_PART_DEVICE_FAMILY_EZR32LG        121          /**< EZR Leopard Gecko Device Family */
+#define _DEVINFO_PART_DEVICE_FAMILY_EZR32HG        122          /**< EZR Happy Gecko Device Family */
 #define _DEVINFO_PART_DEVICE_NUMBER_MASK           0x0000FFFFUL /**< Device number */
 #define _DEVINFO_PART_DEVICE_NUMBER_SHIFT          0            /**< Bit position for device number */
 
 /** @} End of group EFM32ZG_DEVINFO */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_dma.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_dma.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32zg_dma.h
  * @brief EFM32ZG_DMA register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32ZG_DMA
  * @{
  * @brief EFM32ZG_DMA Register Declaration
@@ -67,7 +71,6 @@
   __IO uint32_t  IEN;            /**< Interrupt Enable register  */
 
   uint32_t       RESERVED4[60];  /**< Reserved registers */
-
   DMA_CH_TypeDef CH[4];          /**< Channel registers */
 } DMA_TypeDef;                   /** @} */
 
@@ -687,5 +690,5 @@
 #define DMA_CH_CTRL_SOURCESEL_AES                       (_DMA_CH_CTRL_SOURCESEL_AES << 16)            /**< Shifted mode AES for DMA_CH_CTRL */
 
 /** @} End of group EFM32ZG_DMA */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_dma_ch.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_dma_ch.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32zg_dma_ch.h
  * @brief EFM32ZG_DMA_CH register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @brief DMA_CH EFM32ZG DMA CH
  *****************************************************************************/
 typedef struct
@@ -37,3 +41,6 @@
   __IO uint32_t CTRL; /**< Channel Control Register  */
 } DMA_CH_TypeDef;
 
+/** @} End of group Parts */
+
+

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_dma_descriptor.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_dma_descriptor.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32zg_dma_descriptor.h
  * @brief EFM32ZG_DMA_DESCRIPTOR register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32ZG_DMA_DESCRIPTOR
  * @{
  *****************************************************************************/
@@ -43,3 +47,6 @@
   __IO uint32_t    USER;       /**< DMA padding register, available for user */
 } DMA_DESCRIPTOR_TypeDef;      /** @} */
 
+/** @} End of group Parts */
+
+

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_dmactrl.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_dmactrl.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32zg_dmactrl.h
  * @brief EFM32ZG_DMACTRL register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -29,6 +29,10 @@
  * any third party, arising from your use of this Software.
  *
  *****************************************************************************/
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
 
 /**************************************************************************//**
  * @defgroup EFM32ZG_DMACTRL_BitFields
@@ -132,5 +136,5 @@
 #define DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER_ALT     0x000000007UL /**< Peripheral scatter gather cycle type using alternate structure */
 
 /** @} End of group EFM32ZG_DMA */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_dmareq.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_dmareq.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32zg_dmareq.h
  * @brief EFM32ZG_DMAREQ register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -29,6 +29,10 @@
  * any third party, arising from your use of this Software.
  *
  *****************************************************************************/
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
 
 /**************************************************************************//**
  * @defgroup EFM32ZG_DMAREQ_BitFields
@@ -61,5 +65,5 @@
 #define DMAREQ_AES_KEYWR              ((49 << 16) + 3) /**< DMA channel select for AES_KEYWR */
 
 /** @} End of group EFM32ZG_DMAREQ */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_emu.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_emu.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32zg_emu.h
  * @brief EFM32ZG_EMU register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32ZG_EMU
  * @{
  * @brief EFM32ZG_EMU Register Declaration
@@ -98,5 +102,5 @@
 #define EMU_AUXCTRL_HRCCLR_DEFAULT     (_EMU_AUXCTRL_HRCCLR_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_AUXCTRL */
 
 /** @} End of group EFM32ZG_EMU */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_gpio.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_gpio.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32zg_gpio.h
  * @brief EFM32ZG_GPIO register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32ZG_GPIO
  * @{
  * @brief EFM32ZG_GPIO Register Declaration
@@ -1140,5 +1144,5 @@
 #define GPIO_EM4WUCAUSE_EM4WUCAUSE_E13                    (_GPIO_EM4WUCAUSE_EM4WUCAUSE_E13 << 0)     /**< Shifted mode E13 for GPIO_EM4WUCAUSE */
 
 /** @} End of group EFM32ZG_GPIO */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_gpio_p.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_gpio_p.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32zg_gpio_p.h
  * @brief EFM32ZG_GPIO_P register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @brief GPIO_P EFM32ZG GPIO P
  *****************************************************************************/
 typedef struct
@@ -45,3 +49,6 @@
   __IO uint32_t PINLOCKN; /**< Port Unlocked Pins Register  */
 } GPIO_P_TypeDef;
 
+/** @} End of group Parts */
+
+

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_i2c.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_i2c.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32zg_i2c.h
  * @brief EFM32ZG_I2C register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32ZG_I2C
  * @{
  * @brief EFM32ZG_I2C Register Declaration
@@ -697,5 +701,5 @@
 #define I2C_ROUTE_LOCATION_LOC6           (_I2C_ROUTE_LOCATION_LOC6 << 8)    /**< Shifted mode LOC6 for I2C_ROUTE */
 
 /** @} End of group EFM32ZG_I2C */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_idac.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_idac.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32zg_idac.h
  * @brief EFM32ZG_IDAC register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32ZG_IDAC
  * @{
  * @brief EFM32ZG_IDAC Register Declaration
@@ -140,5 +144,5 @@
 #define IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_DEFAULT     (_IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_DUTYCONFIG */
 
 /** @} End of group EFM32ZG_IDAC */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_leuart.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_leuart.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32zg_leuart.h
  * @brief EFM32ZG_LEUART register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32ZG_LEUART
  * @{
  * @brief EFM32ZG_LEUART Register Declaration
@@ -679,5 +683,5 @@
 #define LEUART_INPUT_RXPRS_DEFAULT               (_LEUART_INPUT_RXPRS_DEFAULT << 4)    /**< Shifted mode DEFAULT for LEUART_INPUT */
 
 /** @} End of group EFM32ZG_LEUART */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_msc.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_msc.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32zg_msc.h
  * @brief EFM32ZG_MSC register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32ZG_MSC
  * @{
  * @brief EFM32ZG_MSC Register Declaration
@@ -408,5 +412,5 @@
 #define MSC_IRQLATENCY_IRQLATENCY_DEFAULT       (_MSC_IRQLATENCY_IRQLATENCY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IRQLATENCY */
 
 /** @} End of group EFM32ZG_MSC */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_pcnt.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_pcnt.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32zg_pcnt.h
  * @brief EFM32ZG_PCNT register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32ZG_PCNT
  * @{
  * @brief EFM32ZG_PCNT Register Declaration
@@ -464,5 +468,5 @@
 #define PCNT_INPUT_S1PRSEN_DEFAULT        (_PCNT_INPUT_S1PRSEN_DEFAULT << 10) /**< Shifted mode DEFAULT for PCNT_INPUT */
 
 /** @} End of group EFM32ZG_PCNT */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_prs.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_prs.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32zg_prs.h
  * @brief EFM32ZG_PRS register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32ZG_PRS
  * @{
  * @brief EFM32ZG_PRS Register Declaration
@@ -41,7 +45,6 @@
   __IO uint32_t  ROUTE;        /**< I/O Routing Register  */
 
   uint32_t       RESERVED0[1]; /**< Reserved registers */
-
   PRS_CH_TypeDef CH[4];        /**< Channel registers */
 } PRS_TypeDef;                 /** @} */
 
@@ -254,5 +257,5 @@
 #define PRS_CH_CTRL_ASYNC_DEFAULT            (_PRS_CH_CTRL_ASYNC_DEFAULT << 28)       /**< Shifted mode DEFAULT for PRS_CH_CTRL */
 
 /** @} End of group EFM32ZG_PRS */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_prs_ch.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_prs_ch.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32zg_prs_ch.h
  * @brief EFM32ZG_PRS_CH register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @brief PRS_CH EFM32ZG PRS CH
  *****************************************************************************/
 typedef struct
@@ -37,3 +41,6 @@
   __IO uint32_t CTRL; /**< Channel Control Register  */
 } PRS_CH_TypeDef;
 
+/** @} End of group Parts */
+
+

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_prs_signals.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_prs_signals.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32zg_prs_signals.h
  * @brief EFM32ZG_PRS_SIGNALS register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,11 +30,14 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @addtogroup EFM32ZG_PRS_Signals
  * @{
  * @brief PRS Signal names
  *****************************************************************************/
-
 #define PRS_VCMP_OUT          ((1 << 16) + 0)  /**< PRS Voltage comparator output */
 #define PRS_ACMP0_OUT         ((2 << 16) + 0)  /**< PRS Analog comparator output */
 #define PRS_ADC0_SINGLE       ((8 << 16) + 0)  /**< PRS ADC single conversion done */
@@ -74,5 +77,5 @@
 #define PRS_PCNT0_TCC         ((54 << 16) + 0) /**< PRS Triggered compare match */
 
 /** @} End of group EFM32ZG_PRS */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_rmu.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_rmu.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32zg_rmu.h
  * @brief EFM32ZG_RMU register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32ZG_RMU
  * @{
  * @brief EFM32ZG_RMU Register Declaration
@@ -124,5 +128,5 @@
 #define RMU_CMD_RCCLR_DEFAULT                (_RMU_CMD_RCCLR_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_CMD */
 
 /** @} End of group EFM32ZG_RMU */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_romtable.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_romtable.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32zg_romtable.h
  * @brief EFM32ZG_ROMTABLE register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32ZG_ROMTABLE
  * @{
  * @brief Chip Information, Revision numbers
@@ -64,5 +68,5 @@
 #define _ROMTABLE_PID3_REVMINORLSB_SHIFT    4            /**< Least Significant Bits [3:0] of CHIP MINOR revision, shift */
 
 /** @} End of group EFM32ZG_ROMTABLE */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_rtc.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_rtc.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32zg_rtc.h
  * @brief EFM32ZG_RTC register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32ZG_RTC
  * @{
  * @brief EFM32ZG_RTC Register Declaration
@@ -210,5 +214,5 @@
 #define RTC_SYNCBUSY_COMP1_DEFAULT       (_RTC_SYNCBUSY_COMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_SYNCBUSY */
 
 /** @} End of group EFM32ZG_RTC */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_timer.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_timer.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32zg_timer.h
  * @brief EFM32ZG_TIMER register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32ZG_TIMER
  * @{
  * @brief EFM32ZG_TIMER Register Declaration
@@ -49,7 +53,6 @@
   __IO uint32_t    ROUTE;        /**< I/O Routing Register  */
 
   uint32_t         RESERVED0[1]; /**< Reserved registers */
-
   TIMER_CC_TypeDef CC[3];        /**< Compare/Capture Channel */
 } TIMER_TypeDef;                 /** @} */
 
@@ -172,7 +175,7 @@
 #define _TIMER_CTRL_ATI_MASK                       0x10000000UL                             /**< Bit mask for TIMER_ATI */
 #define _TIMER_CTRL_ATI_DEFAULT                    0x00000000UL                             /**< Mode DEFAULT for TIMER_CTRL */
 #define TIMER_CTRL_ATI_DEFAULT                     (_TIMER_CTRL_ATI_DEFAULT << 28)          /**< Shifted mode DEFAULT for TIMER_CTRL */
-#define TIMER_CTRL_RSSCOIST                        (0x1UL << 29)                            /**< Reload-Start Sets Compare Ouptut initial State */
+#define TIMER_CTRL_RSSCOIST                        (0x1UL << 29)                            /**< Reload-Start Sets Compare Output initial State */
 #define _TIMER_CTRL_RSSCOIST_SHIFT                 29                                       /**< Shift value for TIMER_RSSCOIST */
 #define _TIMER_CTRL_RSSCOIST_MASK                  0x20000000UL                             /**< Bit mask for TIMER_RSSCOIST */
 #define _TIMER_CTRL_RSSCOIST_DEFAULT               0x00000000UL                             /**< Mode DEFAULT for TIMER_CTRL */
@@ -492,15 +495,15 @@
 #define TIMER_ROUTE_CC2PEN_DEFAULT                 (_TIMER_ROUTE_CC2PEN_DEFAULT << 2)    /**< Shifted mode DEFAULT for TIMER_ROUTE */
 #define _TIMER_ROUTE_LOCATION_SHIFT                16                                    /**< Shift value for TIMER_LOCATION */
 #define _TIMER_ROUTE_LOCATION_MASK                 0x70000UL                             /**< Bit mask for TIMER_LOCATION */
+#define _TIMER_ROUTE_LOCATION_LOC0                 0x00000000UL                          /**< Mode LOC0 for TIMER_ROUTE */
 #define _TIMER_ROUTE_LOCATION_DEFAULT              0x00000000UL                          /**< Mode DEFAULT for TIMER_ROUTE */
-#define _TIMER_ROUTE_LOCATION_LOC0                 0x00000000UL                          /**< Mode LOC0 for TIMER_ROUTE */
 #define _TIMER_ROUTE_LOCATION_LOC1                 0x00000001UL                          /**< Mode LOC1 for TIMER_ROUTE */
 #define _TIMER_ROUTE_LOCATION_LOC2                 0x00000002UL                          /**< Mode LOC2 for TIMER_ROUTE */
 #define _TIMER_ROUTE_LOCATION_LOC3                 0x00000003UL                          /**< Mode LOC3 for TIMER_ROUTE */
 #define _TIMER_ROUTE_LOCATION_LOC4                 0x00000004UL                          /**< Mode LOC4 for TIMER_ROUTE */
 #define _TIMER_ROUTE_LOCATION_LOC5                 0x00000005UL                          /**< Mode LOC5 for TIMER_ROUTE */
+#define TIMER_ROUTE_LOCATION_LOC0                  (_TIMER_ROUTE_LOCATION_LOC0 << 16)    /**< Shifted mode LOC0 for TIMER_ROUTE */
 #define TIMER_ROUTE_LOCATION_DEFAULT               (_TIMER_ROUTE_LOCATION_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_ROUTE */
-#define TIMER_ROUTE_LOCATION_LOC0                  (_TIMER_ROUTE_LOCATION_LOC0 << 16)    /**< Shifted mode LOC0 for TIMER_ROUTE */
 #define TIMER_ROUTE_LOCATION_LOC1                  (_TIMER_ROUTE_LOCATION_LOC1 << 16)    /**< Shifted mode LOC1 for TIMER_ROUTE */
 #define TIMER_ROUTE_LOCATION_LOC2                  (_TIMER_ROUTE_LOCATION_LOC2 << 16)    /**< Shifted mode LOC2 for TIMER_ROUTE */
 #define TIMER_ROUTE_LOCATION_LOC3                  (_TIMER_ROUTE_LOCATION_LOC3 << 16)    /**< Shifted mode LOC3 for TIMER_ROUTE */
@@ -657,5 +660,5 @@
 #define TIMER_CC_CCVB_CCVB_DEFAULT                 (_TIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CCVB */
 
 /** @} End of group EFM32ZG_TIMER */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_timer_cc.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_timer_cc.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32zg_timer_cc.h
  * @brief EFM32ZG_TIMER_CC register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @brief TIMER_CC EFM32ZG TIMER CC
  *****************************************************************************/
 typedef struct
@@ -40,3 +44,6 @@
   __IO uint32_t CCVB; /**< CC Channel Buffer Register  */
 } TIMER_CC_TypeDef;
 
+/** @} End of group Parts */
+
+

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_usart.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_usart.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32zg_usart.h
  * @brief EFM32ZG_USART register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32ZG_USART
  * @{
  * @brief EFM32ZG_USART Register Declaration
@@ -1119,5 +1123,5 @@
 #define USART_I2SCTRL_FORMAT_W8D8             (_USART_I2SCTRL_FORMAT_W8D8 << 8)      /**< Shifted mode W8D8 for USART_I2SCTRL */
 
 /** @} End of group EFM32ZG_USART */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_vcmp.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_vcmp.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32zg_vcmp.h
  * @brief EFM32ZG_VCMP register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32ZG_VCMP
  * @{
  * @brief EFM32ZG_VCMP Register Declaration
@@ -192,5 +196,5 @@
 #define VCMP_IFC_WARMUP_DEFAULT             (_VCMP_IFC_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for VCMP_IFC */
 
 /** @} End of group EFM32ZG_VCMP */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_wdog.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_wdog.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file efm32zg_wdog.h
  * @brief EFM32ZG_WDOG register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
  *
  *****************************************************************************/
 /**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
  * @defgroup EFM32ZG_WDOG
  * @{
  * @brief EFM32ZG_WDOG Register Declaration
@@ -128,5 +132,5 @@
 #define WDOG_SYNCBUSY_CMD_DEFAULT        (_WDOG_SYNCBUSY_CMD_DEFAULT << 1)  /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */
 
 /** @} End of group EFM32ZG_WDOG */
+/** @} End of group Parts */
 
-

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/em_device.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/em_device.h	Fri Jan 15 07:45:16 2016 +0000
@@ -9,11 +9,13 @@
  * @verbatim
  * Example: Add "-DEFM32G890F128" to your build options, to define part
  *          Add "#include "em_device.h" to your source files
+ *
+ *
  * @endverbatim
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -29,19 +31,18 @@
  * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
  * has no obligation to support this Software. Silicon Laboratories, Inc. is
  * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of 
+ * kind, including, but not limited to, any implied warranties of
  * merchantability or fitness for any particular purpose or warranties against
  * infringement of any proprietary rights of a third party.
  *
- * Silicon Laboratories, Inc. will not be liable for any consequential, 
- * incidental, or special damages, or any other relief, or for any claim by 
+ * Silicon Laboratories, Inc. will not be liable for any consequential,
+ * incidental, or special damages, or any other relief, or for any claim by
  * any third party, arising from your use of this Software.
  *
  *****************************************************************************/
 
-#ifndef __EM_DEVICE_H
-#define __EM_DEVICE_H
-
+#ifndef EM_DEVICE_H
+#define EM_DEVICE_H
 
 #if defined(EFM32ZG108F16)
 #include "efm32zg108f16.h"
@@ -91,9 +92,7 @@
 #elif defined(EFM32ZG222F8)
 #include "efm32zg222f8.h"
 
-
 #else
 #error "em_device.h: PART NUMBER undefined"
 #endif
-
-#endif
+#endif /* EM_DEVICE_H */

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/system_efm32zg.c	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/system_efm32zg.c	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /***************************************************************************//**
- * @file system_efm32zg.c 
+ * @file system_efm32zg.c
  * @brief CMSIS Cortex-M0+ System Layer for EFM32ZG devices.
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -20,12 +20,12 @@
  * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
  * has no obligation to support this Software. Silicon Laboratories, Inc. is
  * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of 
+ * kind, including, but not limited to, any implied warranties of
  * merchantability or fitness for any particular purpose or warranties against
  * infringement of any proprietary rights of a third party.
  *
- * Silicon Laboratories, Inc. will not be liable for any consequential, 
- * incidental, or special damages, or any other relief, or for any claim by 
+ * Silicon Laboratories, Inc. will not be liable for any consequential,
+ * incidental, or special damages, or any other relief, or for any claim by
  * any third party, arising from your use of this Software.
  *
  *****************************************************************************/
@@ -56,6 +56,9 @@
 #ifndef EFM32_HFXO_FREQ
 #define EFM32_HFXO_FREQ (24000000UL)
 #endif
+
+#define EFM32_HFRCO_MAX_FREQ    (21000000UL)
+
 /* Do not define variable if HF crystal oscillator not present */
 #if (EFM32_HFXO_FREQ > 0)
 /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
@@ -67,6 +70,7 @@
 #ifndef EFM32_LFXO_FREQ
 #define EFM32_LFXO_FREQ (EFM32_LFRCO_FREQ)
 #endif
+
 /* Do not define variable if LF crystal oscillator not present */
 #if (EFM32_LFXO_FREQ > 0)
 /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
@@ -112,7 +116,7 @@
 uint32_t SystemCoreClockGet(void)
 {
   uint32_t ret;
-  
+
   ret = SystemHFClockGet();
   ret >>= (CMU->HFCORECLKDIV & _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK) >>
           _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT;
@@ -126,6 +130,23 @@
 
 /***************************************************************************//**
  * @brief
+ *   Get the maximum core clock frequency.
+ *
+ * @note
+ *   This is an EFR32 proprietary function, not part of the CMSIS definition.
+ *
+ * @return
+ *   The maximum core clock frequency in Hz.
+ ******************************************************************************/
+uint32_t SystemMaxCoreClockGet(void)
+{
+  return (EFM32_HFRCO_MAX_FREQ > EFM32_HFXO_FREQ ? \
+          EFM32_HFRCO_MAX_FREQ : EFM32_HFXO_FREQ);
+}
+
+
+/***************************************************************************//**
+ * @brief
  *   Get the current HFCLK frequency.
  *
  * @note
@@ -137,7 +158,7 @@
 uint32_t SystemHFClockGet(void)
 {
   uint32_t ret;
-  
+
   switch (CMU->STATUS & (CMU_STATUS_HFRCOSEL | CMU_STATUS_HFXOSEL |
                          CMU_STATUS_LFRCOSEL | CMU_STATUS_LFXOSEL))
   {
@@ -150,11 +171,11 @@
       ret = 0;
 #endif
       break;
-      
+
     case CMU_STATUS_LFRCOSEL:
       ret = EFM32_LFRCO_FREQ;
       break;
-      
+
     case CMU_STATUS_HFXOSEL:
 #if (EFM32_HFXO_FREQ > 0)
       ret = SystemHFXOClock;
@@ -164,7 +185,7 @@
       ret = 0;
 #endif
       break;
-      
+
     default: /* CMU_STATUS_HFRCOSEL */
       switch (CMU->HFRCOCTRL & _CMU_HFRCOCTRL_BAND_MASK)
       {

--- a/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/system_efm32zg.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/system_efm32zg.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file system_efm32zg.h
  * @brief CMSIS Cortex-M System Layer for EFM32 devices.
- * @version 3.20.6
+ * @version 4.2.0
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,8 +30,8 @@
  *
  *****************************************************************************/
 
-#ifndef __SYSTEM_EFM32ZG_H
-#define __SYSTEM_EFM32ZG_H
+#ifndef SYSTEM_EFM32ZG_H
+#define SYSTEM_EFM32ZG_H
 
 #ifdef __cplusplus
 extern "C" {
@@ -76,6 +76,7 @@
 void AES_IRQHandler(void);
 
 uint32_t SystemCoreClockGet(void);
+uint32_t SystemMaxCoreClockGet(void);
 
 /**************************************************************************//**
  * @brief
@@ -108,4 +109,4 @@
 #ifdef __cplusplus
 }
 #endif
-#endif /* __SYSTEM_EFM32ZG_H */
+#endif /* SYSTEM_EFM32ZG_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG_STK3401/Modules.h	Fri Jan 15 07:45:16 2016 +0000
@@ -0,0 +1,42 @@
+/***************************************************************************//**
+ * @file Modules.h
+ *******************************************************************************
+ * @section License
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
+ *******************************************************************************
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
+ * obligation to support this Software. Silicon Labs is providing the
+ * Software "AS IS", with no express or implied warranties of any kind,
+ * including, but not limited to, any implied warranties of merchantability
+ * or fitness for any particular purpose or warranties against infringement
+ * of any proprietary rights of a third party.
+ *
+ * Silicon Labs will not be liable for any consequential, incidental, or
+ * special damages, or any other relief, or for any claim by any third party,
+ * arising from your use of this Software.
+ *
+ ******************************************************************************/
+#ifndef MBED_MODULES_H
+#define MBED_MODULES_H
+
+#define MODULES_SIZE_ANALOGIN  1
+#define MODULES_SIZE_ANALOGOUT 0
+#define MODULES_SIZE_GPIO      1
+#define MODULES_SIZE_SPI       2
+#define MODULES_SIZE_I2C       1
+#define MODULES_SIZE_PWMOUT    1
+#define MODULES_SIZE_SERIAL    3
+#define TRANSACTION_QUEUE_SIZE_SPI   4
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG_STK3401/PeripheralNames.h	Fri Jan 15 07:45:16 2016 +0000
@@ -0,0 +1,75 @@
+/***************************************************************************//**
+ * @file PeripheralNames.h
+ *******************************************************************************
+ * @section License
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
+ *******************************************************************************
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
+ * obligation to support this Software. Silicon Labs is providing the
+ * Software "AS IS", with no express or implied warranties of any kind,
+ * including, but not limited to, any implied warranties of merchantability
+ * or fitness for any particular purpose or warranties against infringement
+ * of any proprietary rights of a third party.
+ *
+ * Silicon Labs will not be liable for any consequential, incidental, or
+ * special damages, or any other relief, or for any claim by any third party,
+ * arising from your use of this Software.
+ *
+ ******************************************************************************/
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "em_adc.h"
+#include "em_usart.h"
+#include "em_i2c.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    ADC_0 = ADC0_BASE
+} ADCName;
+
+typedef enum {
+    I2C_0 = I2C0_BASE,
+} I2CName;
+
+typedef enum {
+    PWM_CH0 = 0,
+    PWM_CH1 = 1,
+    PWM_CH2 = 2,
+    PWM_CH3 = 3
+} PWMName;
+
+typedef enum {
+    USART_0 = USART0_BASE,
+    USART_1 = USART1_BASE,
+    LEUART_0 = LEUART0_BASE,
+} UARTName;
+
+#define STDIO_UART_TX     USBTX
+#define STDIO_UART_RX     USBRX
+#define STDIO_UART        USART0
+
+typedef enum {
+    SPI_0 = USART0_BASE,
+    SPI_1 = USART1_BASE,
+} SPIName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG_STK3401/PeripheralPins.c	Fri Jan 15 07:45:16 2016 +0000
@@ -0,0 +1,434 @@
+/***************************************************************************//**
+ * @file PeripheralPins.c
+ *******************************************************************************
+ * @section License
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
+ *******************************************************************************
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
+ * obligation to support this Software. Silicon Labs is providing the
+ * Software "AS IS", with no express or implied warranties of any kind,
+ * including, but not limited to, any implied warranties of merchantability
+ * or fitness for any particular purpose or warranties against infringement
+ * of any proprietary rights of a third particularty.
+ *
+ * Silicon Labs will not be liable for any consequential, incidental, or
+ * special damages, or any other relief, or for any claim by any third party,
+ * arising from your use of this Software.
+ *
+ ******************************************************************************/
+
+#include "PeripheralPins.h"
+
+/************ADC***************/
+/* The third "function" value is used to select the correct ADC channel */
+const PinMap PinMap_ADC[] = {
+    {PA0,  ADC_0, adcPosSelAPORT3XCH8},
+    {PA1,  ADC_0, adcPosSelAPORT4XCH9},
+    {PA2,  ADC_0, adcPosSelAPORT3XCH10},
+    {PA3,  ADC_0, adcPosSelAPORT4XCH11},
+    {PA4,  ADC_0, adcPosSelAPORT3XCH12},
+    {PA5,  ADC_0, adcPosSelAPORT4XCH13},
+    
+    {PB11, ADC_0, adcPosSelAPORT4XCH27},
+    {PB12, ADC_0, adcPosSelAPORT3XCH28},
+    {PB14, ADC_0, adcPosSelAPORT3XCH30},
+    {PB15, ADC_0, adcPosSelAPORT4XCH31},
+    
+    {PC6,  ADC_0, adcPosSelAPORT1XCH6},
+    {PC7,  ADC_0, adcPosSelAPORT2XCH7},
+    {PC8,  ADC_0, adcPosSelAPORT1XCH8},
+    {PC9,  ADC_0, adcPosSelAPORT2XCH9},
+    {PC10, ADC_0, adcPosSelAPORT1XCH10},
+    {PC11, ADC_0, adcPosSelAPORT2XCH11},
+    
+    {PD9,  ADC_0, adcPosSelAPORT4XCH1},
+    {PD10, ADC_0, adcPosSelAPORT3XCH2},
+    {PD11, ADC_0, adcPosSelAPORT3YCH3},
+    {PD12, ADC_0, adcPosSelAPORT3XCH4},
+    {PD13, ADC_0, adcPosSelAPORT3YCH5},
+    {PD14, ADC_0, adcPosSelAPORT3XCH6},
+    {PD15, ADC_0, adcPosSelAPORT4XCH7},
+    
+    {PF0,  ADC_0, adcPosSelAPORT1XCH16},
+    {PF1,  ADC_0, adcPosSelAPORT2XCH17},
+    {PF2,  ADC_0, adcPosSelAPORT1XCH18},
+    {PF3,  ADC_0, adcPosSelAPORT2XCH19},
+    {PF4,  ADC_0, adcPosSelAPORT1XCH20},
+    {PF5,  ADC_0, adcPosSelAPORT2XCH21},
+    {PF6,  ADC_0, adcPosSelAPORT1XCH22},
+    {PF7,  ADC_0, adcPosSelAPORT2XCH23},
+    {NC ,  NC   , NC}
+};
+
+/************I2C SCL***********/
+const PinMap PinMap_I2C_SCL[] = {
+    /* I2C0 */
+    {PA1,  I2C_0,  0},
+    {PA2,  I2C_0,  1},
+    {PA3,  I2C_0,  2},
+    {PA4,  I2C_0,  3},
+    {PA5,  I2C_0,  4},
+    {PB11, I2C_0,  5},
+    {PB12, I2C_0,  6},
+    {PB13, I2C_0,  7},
+    {PB14, I2C_0,  8},
+    {PB15, I2C_0,  9},
+    {PC6,  I2C_0, 10},
+    {PC7,  I2C_0, 11},
+    {PC8,  I2C_0, 12},
+    {PC9,  I2C_0, 13},
+    {PC10, I2C_0, 14},
+    {PC11, I2C_0, 15},
+    {PD9,  I2C_0, 16},
+    {PD10, I2C_0, 17},
+    {PD11, I2C_0, 18},
+    {PD12, I2C_0, 19},
+    {PD13, I2C_0, 20},
+    {PD14, I2C_0, 21},
+    {PD15, I2C_0, 22},
+    {PF0,  I2C_0, 23},
+    {PF1,  I2C_0, 24},
+    {PF2,  I2C_0, 25},
+    {PF3,  I2C_0, 26},
+    {PF4,  I2C_0, 27},
+    {PF5,  I2C_0, 28},
+    {PF6,  I2C_0, 29},
+    {PF7,  I2C_0, 30},
+    {PA0,  I2C_0, 31},
+
+    {NC  , NC   , NC}
+};
+
+/************I2C SDA***********/
+const PinMap PinMap_I2C_SDA[] = {
+    /* I2C0 */
+    {PA0,  I2C_0,  0},
+    {PA1,  I2C_0,  1},
+    {PA2,  I2C_0,  2},
+    {PA3,  I2C_0,  3},
+    {PA4,  I2C_0,  4},
+    {PA5,  I2C_0,  5},
+    {PB11, I2C_0,  6},
+    {PB12, I2C_0,  7},
+    {PB13, I2C_0,  8},
+    {PB14, I2C_0,  9},
+    {PB15, I2C_0, 10},
+    {PC6,  I2C_0, 11},
+    {PC7,  I2C_0, 12},
+    {PC8,  I2C_0, 13},
+    {PC9,  I2C_0, 14},
+    {PC10, I2C_0, 15},
+    {PC11, I2C_0, 16},
+    {PD9,  I2C_0, 17},
+    {PD10, I2C_0, 18},
+    {PD11, I2C_0, 19},
+    {PD12, I2C_0, 20},
+    {PD13, I2C_0, 21},
+    {PD14, I2C_0, 22},
+    {PD15, I2C_0, 23},
+    {PF0,  I2C_0, 24},
+    {PF1,  I2C_0, 25},
+    {PF2,  I2C_0, 26},
+    {PF3,  I2C_0, 27},
+    {PF4,  I2C_0, 28},
+    {PF5,  I2C_0, 29},
+    {PF6,  I2C_0, 30},
+    {PF7,  I2C_0, 31},
+
+    /* Not connected */
+    {NC  , NC   , NC}
+};
+
+/************PWM***************/
+const PinMap PinMap_PWM[] = {
+    {PA0,  PWM_CH0,  0},
+    {PA1,  PWM_CH1,  0},
+    {PA2,  PWM_CH2,  0},
+    {PA3,  PWM_CH3,  0},
+    {PA4,  PWM_CH2,  2},
+    {PA5,  PWM_CH3,  2},
+    {PB11, PWM_CH1,  5},
+    {PB12, PWM_CH2,  5},
+    {PB13, PWM_CH3,  5},
+    {PB14, PWM_CH0,  9},
+    {PB15, PWM_CH0, 10},
+    {PC6,  PWM_CH0, 11},
+    {PC7,  PWM_CH1, 11},
+    {PC8,  PWM_CH2, 11},
+    {PC9,  PWM_CH3, 11},
+    {PC10, PWM_CH2, 13},
+    {PC11, PWM_CH3, 13},
+    {PD9,  PWM_CH3, 14},
+    {PD10, PWM_CH0, 18},
+    {PD11, PWM_CH1, 18},
+    {PD12, PWM_CH2, 18},
+    {PD13, PWM_CH3, 18},
+    {PD14, PWM_CH0, 22},
+    {PD15, PWM_CH1, 22},
+    {PF0,  PWM_CH0, 24},
+    {PF1,  PWM_CH1, 24},
+    {PF2,  PWM_CH2, 24},
+    {PF3,  PWM_CH3, 24},
+    {PF4,  PWM_CH0, 28},
+    {PF5,  PWM_CH1, 28},
+    {PF6,  PWM_CH2, 28},
+    {PF7,  PWM_CH3, 28},
+
+    {NC  , NC     , NC}
+};
+
+/*************SPI**************/
+const PinMap PinMap_SPI_MOSI[] = {
+
+    /* USART0 */
+    {PA0,  SPI_0,  0},
+    {PA1,  SPI_0,  1},
+    {PA2,  SPI_0,  2},
+    {PA3,  SPI_0,  3},
+    {PA4,  SPI_0,  4},
+    {PA5,  SPI_0,  5},
+    {PB11, SPI_0,  6},
+    {PB12, SPI_0,  7},
+    {PB13, SPI_0,  8},
+    {PB14, SPI_0,  9},
+    {PB15, SPI_0, 10},
+    {PD9,  SPI_0, 17},
+    {PD10, SPI_0, 18},
+    {PD11, SPI_0, 19},
+    {PD12, SPI_0, 20},
+    {PD13, SPI_0, 21},
+    {PD14, SPI_0, 22},
+    {PD15, SPI_0, 23},
+
+    /* USART1 */
+    {PC6,  SPI_1, 11},
+    {PC7,  SPI_1, 12},
+    {PC8,  SPI_1, 13},
+    {PC9,  SPI_1, 14},
+    {PC10, SPI_1, 15},
+    {PC11, SPI_1, 16},
+    {PF0,  SPI_1, 24},
+    {PF1,  SPI_1, 25},
+    {PF2,  SPI_1, 26},
+    {PF3,  SPI_1, 27},
+    {PF4,  SPI_1, 28},
+    {PF5,  SPI_1, 29},
+    {PF6,  SPI_1, 30},
+    {PF7,  SPI_1, 31},
+
+    {NC  , NC   , NC}
+};
+
+const PinMap PinMap_SPI_MISO[] = {
+
+    /* USART0 */
+    {PA0,  SPI_0, 31},
+    {PA1,  SPI_0,  0},
+    {PA2,  SPI_0,  1},
+    {PA3,  SPI_0,  2},
+    {PA4,  SPI_0,  3},
+    {PA5,  SPI_0,  4},
+    {PB11, SPI_0,  5},
+    {PB12, SPI_0,  6},
+    {PB13, SPI_0,  7},
+    {PB14, SPI_0,  8},
+    {PB15, SPI_0,  9},
+    {PD9,  SPI_0, 16},
+    {PD10, SPI_0, 17},
+    {PD11, SPI_0, 18},
+    {PD12, SPI_0, 19},
+    {PD13, SPI_0, 20},
+    {PD14, SPI_0, 21},
+    {PD15, SPI_0, 22},
+
+    /* USART1 */
+    {PC6,  SPI_1, 10},
+    {PC7,  SPI_1, 11},
+    {PC8,  SPI_1, 12},
+    {PC9,  SPI_1, 13},
+    {PC10, SPI_1, 14},
+    {PC11, SPI_1, 15},
+    {PF0,  SPI_1, 23},
+    {PF1,  SPI_1, 24},
+    {PF2,  SPI_1, 25},
+    {PF3,  SPI_1, 26},
+    {PF4,  SPI_1, 27},
+    {PF5,  SPI_1, 28},
+    {PF6,  SPI_1, 29},
+    {PF7,  SPI_1, 30},
+    {PA0,  SPI_1, 31},
+
+    {NC  , NC   , NC}
+};
+
+const PinMap PinMap_SPI_CLK[] = {
+
+    /* USART0 */
+    {PA0,  SPI_0, 30},
+    {PA1,  SPI_0, 31},
+    {PA2,  SPI_0,  0},
+    {PA3,  SPI_0,  1},
+    {PA4,  SPI_0,  2},
+    {PA5,  SPI_0,  3},
+    {PB11, SPI_0,  4},
+    {PB12, SPI_0,  5},
+    {PB13, SPI_0,  6},
+    {PB14, SPI_0,  7},
+    {PB15, SPI_0,  8},
+    {PD9,  SPI_0, 15},
+    {PD10, SPI_0, 16},
+    {PD11, SPI_0, 17},
+    {PD12, SPI_0, 18},
+    {PD13, SPI_0, 19},
+    {PD14, SPI_0, 20},
+    {PD15, SPI_0, 21},
+
+    /* USART1 */
+    {PC6,  SPI_1,  9},
+    {PC7,  SPI_1, 10},
+    {PC8,  SPI_1, 11},
+    {PC9,  SPI_1, 12},
+    {PC10, SPI_1, 13},
+    {PC11, SPI_1, 14},
+    {PF0,  SPI_1, 22},
+    {PF1,  SPI_1, 23},
+    {PF2,  SPI_1, 24},
+    {PF3,  SPI_1, 25},
+    {PF4,  SPI_1, 26},
+    {PF5,  SPI_1, 27},
+    {PF6,  SPI_1, 28},
+    {PF7,  SPI_1, 29},
+    {PA0,  SPI_1, 30},
+    {PA1,  SPI_1, 31},
+
+    {NC  , NC   , NC}
+};
+
+const PinMap PinMap_SPI_CS[] = {
+
+    /* USART0 */
+    {PA0,  SPI_0,  29},
+    {PA1,  SPI_0,  30},
+    {PA2,  SPI_0,  31},
+    {PA3,  SPI_0,  0},
+    {PA4,  SPI_0,  1},
+    {PA5,  SPI_0,  2},
+    {PB11, SPI_0,  3},
+    {PB12, SPI_0,  4},
+    {PB13, SPI_0,  5},
+    {PB14, SPI_0,  6},
+    {PB15, SPI_0,  7},
+    {PD9,  SPI_0, 14},
+    {PD10, SPI_0, 15},
+    {PD11, SPI_0, 16},
+    {PD12, SPI_0, 17},
+    {PD13, SPI_0, 18},
+    {PD14, SPI_0, 19},
+    {PD15, SPI_0, 20},
+
+    /* USART1 */
+    {PC6,  SPI_1,  8},
+    {PC7,  SPI_1,  9},
+    {PC8,  SPI_1, 10},
+    {PC9,  SPI_1, 11},
+    {PC10, SPI_1, 12},
+    {PC11, SPI_1, 13},
+    {PF0,  SPI_1, 21},
+    {PF1,  SPI_1, 22},
+    {PF2,  SPI_1, 23},
+    {PF3,  SPI_1, 24},
+    {PF4,  SPI_1, 25},
+    {PF5,  SPI_1, 26},
+    {PF6,  SPI_1, 27},
+    {PF7,  SPI_1, 28},
+
+    {NC  , NC   , NC}
+};
+
+/************UART**************/
+const PinMap PinMap_UART_TX[] = {
+    {PA0,  USART_0,  0},
+    {PA1,  USART_0,  1},
+    {PA2,  USART_0,  2},
+    {PA3,  USART_0,  3},
+    {PA4,  USART_0,  4},
+    {PA5,  USART_0,  5},
+    {PB11, USART_0,  6},
+    {PB12, USART_0,  7},
+    {PB13, USART_0,  8},
+    {PB14, USART_0,  9},
+    {PB15, USART_0, 10},
+    {PD9,  LEUART_0, 17},
+    {PD10, LEUART_0, 18},
+    {PD11, LEUART_0, 19},
+    {PD12, LEUART_0, 20},
+    {PD13, LEUART_0, 21},
+    {PD14, LEUART_0, 22},
+    {PD15, LEUART_0, 23},
+
+    {PC6,  USART_1, 11},
+    {PC7,  USART_1, 12},
+    {PC8,  USART_1, 13},
+    {PC9,  USART_1, 14},
+    {PC10, USART_1, 15},
+    {PC11, USART_1, 16},
+    {PF0,  USART_1, 24},
+    {PF1,  USART_1, 25},
+    {PF2,  USART_1, 26},
+    {PF3,  USART_1, 27},
+    {PF4,  USART_1, 28},
+    {PF5,  USART_1, 29},
+    {PF6,  USART_1, 30},
+    {PF7,  USART_1, 31},
+
+    {NC  , NC   , NC}
+};
+
+const PinMap PinMap_UART_RX[] = {
+    {PA0,  USART_0, 31},
+    {PA1,  USART_0,  0},
+    {PA2,  USART_0,  1},
+    {PA3,  USART_0,  2},
+    {PA4,  USART_0,  3},
+    {PA5,  USART_0,  4},
+    {PB11, USART_0,  5},
+    {PB12, USART_0,  6},
+    {PB13, USART_0,  7},
+    {PB14, USART_0,  8},
+    {PB15, USART_0,  9},
+    {PD9,  LEUART_0, 16},
+    {PD10, LEUART_0, 17},
+    {PD11, LEUART_0, 18},
+    {PD12, LEUART_0, 19},
+    {PD13, LEUART_0, 20},
+    {PD14, LEUART_0, 21},
+    {PD15, LEUART_0, 22},
+
+    {PC6,  USART_1, 10},
+    {PC7,  USART_1, 11},
+    {PC8,  USART_1, 12},
+    {PC9,  USART_1, 13},
+    {PC10, USART_1, 14},
+    {PC11, USART_1, 15},
+    {PF0,  USART_1, 23},
+    {PF1,  USART_1, 24},
+    {PF2,  USART_1, 25},
+    {PF3,  USART_1, 26},
+    {PF4,  USART_1, 27},
+    {PF5,  USART_1, 28},
+    {PF6,  USART_1, 29},
+    {PF7,  USART_1, 30},
+
+    {NC  , NC   , NC}
+};

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG_STK3401/PeripheralPins.h	Fri Jan 15 07:45:16 2016 +0000
@@ -0,0 +1,60 @@
+/***************************************************************************//**
+ * @file PeripheralPins.h
+ *******************************************************************************
+ * @section License
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
+ *******************************************************************************
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
+ * obligation to support this Software. Silicon Labs is providing the
+ * Software "AS IS", with no express or implied warranties of any kind,
+ * including, but not limited to, any implied warranties of merchantability
+ * or fitness for any particular purpose or warranties against infringement
+ * of any proprietary rights of a third party.
+ *
+ * Silicon Labs will not be liable for any consequential, incidental, or
+ * special damages, or any other relief, or for any claim by any third party,
+ * arising from your use of this Software.
+ *
+ ******************************************************************************/
+
+#ifndef MBED_PERIPHERALPINS_H
+#define MBED_PERIPHERALPINS_H
+
+#include "pinmap.h"
+#include "PeripheralNames.h"
+
+/************ADC***************/
+extern const PinMap PinMap_ADC[];
+
+/************I2C SCL***********/
+extern const PinMap PinMap_I2C_SCL[];
+
+/************I2C SDA***********/
+extern const PinMap PinMap_I2C_SDA[];
+
+/************PWM***************/
+extern const PinMap PinMap_PWM[];
+
+/************SPI***************/
+extern const PinMap PinMap_SPI_MOSI[];
+extern const PinMap PinMap_SPI_MISO[];
+extern const PinMap PinMap_SPI_CLK[];
+extern const PinMap PinMap_SPI_CS[];
+
+/************UART**************/
+extern const PinMap PinMap_UART_TX[];
+extern const PinMap PinMap_UART_RX[];
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG_STK3401/PinNames.h	Fri Jan 15 07:45:16 2016 +0000
@@ -0,0 +1,123 @@
+/***************************************************************************//**
+ * @file PinNames.h
+ *******************************************************************************
+ * @section License
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
+ *******************************************************************************
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
+ * obligation to support this Software. Silicon Labs is providing the
+ * Software "AS IS", with no express or implied warranties of any kind,
+ * including, but not limited to, any implied warranties of merchantability
+ * or fitness for any particular purpose or warranties against infringement
+ * of any proprietary rights of a third party.
+ *
+ * Silicon Labs will not be liable for any consequential, incidental, or
+ * special damages, or any other relief, or for any claim by any third party,
+ * arising from your use of this Software.
+ *
+ ******************************************************************************/
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+#include "em_gpio.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    PIN_INPUT = 0,
+    PIN_OUTPUT = 1
+} PinDirection;
+
+typedef enum {
+    /* EFM32 Pin Names
+     * First 4 bits represent pin number, the remaining
+     * bits represent port number (A = 0, B = 1, ...)
+     */
+    PA0 = 0 << 4, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15,
+    PB0 = 1 << 4, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15,
+    PC0 = 2 << 4, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15,
+    PD0 = 3 << 4, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15,
+    PE0 = 4 << 4, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15,
+    PF0 = 5 << 4, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15,
+
+    /* Starter Kit says LED0 and LED1, but mbed expects 1 and 2. This way using 1 and 2 or 0 and 1 will work. */
+    LED0 = PF4,
+    LED1 = PF5,
+    LED2 = LED0,
+    LED3 = LED0,
+    LED4 = LED1,
+
+    /* Push Buttons */
+    SW0 = PF6,
+    SW1 = PF7,
+    BTN0 = SW0,
+    BTN1 = SW1,
+
+    /* Serial (just some usable pins) */
+    SERIAL_TX   = PD10,
+    SERIAL_RX   = PD11,
+
+    /* Board Controller UART (USB) + enable pin */
+    USBTX       = PA0,
+    USBRX       = PA1,
+    EFM_BC_EN   = PA5,
+
+    /* Not connected */
+    NC = (int) 0xFFFFFFFF
+} PinName;
+
+
+/* 0x10 represents setting the DOUT register (see efm32 modes in ref. manual) */
+typedef enum {
+    /* EFM32 pin modes */
+    Disabled             = gpioModeDisabled,
+    DisabledPullUp       = gpioModeDisabled | 0x10,
+    Input                = gpioModeInput,
+    InputFilter          = gpioModeInput | 0x10,
+    InputPullDown        = gpioModeInputPull,
+    InputPullUp          = gpioModeInputPull | 0x10,
+    InputPullFilterDown  = gpioModeInputPullFilter,
+    InputPullFilterUp    = gpioModeInputPullFilter | 0x10,
+    PushPull             = gpioModePushPull,
+    WiredOr              = gpioModeWiredOr,
+    WiredOrPullDown      = gpioModeWiredOrPullDown,
+    WiredAnd             = gpioModeWiredAnd,
+    WiredAndFilter       = gpioModeWiredAndFilter,
+    WiredAndPullUp       = gpioModeWiredAndPullUp,
+    WiredAndPullUpFilter = gpioModeWiredAndPullUpFilter,
+
+    /* mbed modes:
+     * PullUp, PullDown, PullNone, OpenDrain
+     *
+     * mbed default digital input mode:
+     * PullDefault
+     *
+     * mbed default digital output mode:
+     * PullNone
+     */
+    PullUp = InputPullUp,
+    PullDown = InputPullDown,
+    OpenDrain = WiredAnd,
+    PullNone = PushPull,
+    PullDefault = PushPull
+} PinMode;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG_STK3401/PortNames.h	Fri Jan 15 07:45:16 2016 +0000
@@ -0,0 +1,50 @@
+/***************************************************************************//**
+ * @file PortNames.h
+ *******************************************************************************
+ * @section License
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
+ *******************************************************************************
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
+ * obligation to support this Software. Silicon Labs is providing the
+ * Software "AS IS", with no express or implied warranties of any kind,
+ * including, but not limited to, any implied warranties of merchantability
+ * or fitness for any particular purpose or warranties against infringement
+ * of any proprietary rights of a third party.
+ *
+ * Silicon Labs will not be liable for any consequential, incidental, or
+ * special damages, or any other relief, or for any claim by any third party,
+ * arising from your use of this Software.
+ *
+ ******************************************************************************/
+#ifndef MBED_PORTNAMES_H
+#define MBED_PORTNAMES_H
+
+#include "em_gpio.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    PortA = gpioPortA, /**< Port A */
+    PortB = gpioPortB, /**< Port B */
+    PortC = gpioPortC, /**< Port C */
+    PortD = gpioPortD, /**< Port D */
+    PortF = gpioPortF  /**< Port F */
+} PortName;
+
+#ifdef __cplusplus
+}
+#endif
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG_STK3401/device.h	Fri Jan 15 07:45:16 2016 +0000
@@ -0,0 +1,73 @@
+/***************************************************************************//**
+ * @file device.h
+ *******************************************************************************
+ * @section License
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
+ *******************************************************************************
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
+ * obligation to support this Software. Silicon Labs is providing the
+ * Software "AS IS", with no express or implied warranties of any kind,
+ * including, but not limited to, any implied warranties of merchantability
+ * or fitness for any particular purpose or warranties against infringement
+ * of any proprietary rights of a third party.
+ *
+ * Silicon Labs will not be liable for any consequential, incidental, or
+ * special damages, or any other relief, or for any claim by any third party,
+ * arising from your use of this Software.
+ *
+ ******************************************************************************/
+#ifndef MBED_DEVICE_H
+#define MBED_DEVICE_H
+
+#define DEVICE_PORTIN           1
+#define DEVICE_PORTOUT          1
+#define DEVICE_PORTINOUT        1
+
+#define DEVICE_INTERRUPTIN      1
+
+#define DEVICE_ANALOGIN         1
+#define DEVICE_ANALOGOUT        0
+
+#define DEVICE_SERIAL           1
+#define DEVICE_SERIAL_ASYNCH    1
+
+#define DEVICE_I2C              1
+#define DEVICE_I2CSLAVE         1
+#define DEVICE_I2C_ASYNCH       1
+
+#define DEVICE_SPI              1
+#define DEVICE_SPISLAVE         1
+#define DEVICE_SPI_ASYNCH       1
+
+#define DEVICE_CAN              0
+
+#define DEVICE_RTC              1
+
+#define DEVICE_ETHERNET         0
+
+#define DEVICE_PWMOUT           1
+
+#define DEVICE_SLEEP            1
+
+#define DEVICE_STDIO_MESSAGES   1
+
+#define DEVICE_LOWPOWERTIMER    1
+
+#define DEVICE_ERROR_PATTERN    1
+
+#include "objects.h"
+#include "Modules.h"
+#include "device_peripherals.h"
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG_STK3401/device_peripherals.h	Fri Jan 15 07:45:16 2016 +0000
@@ -0,0 +1,84 @@
+/***************************************************************************//**
+ * @file device_peripherals.h
+ *******************************************************************************
+ * @section License
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
+ *******************************************************************************
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
+ * obligation to support this Software. Silicon Labs is providing the
+ * Software "AS IS", with no express or implied warranties of any kind,
+ * including, but not limited to, any implied warranties of merchantability
+ * or fitness for any particular purpose or warranties against infringement
+ * of any proprietary rights of a third party.
+ *
+ * Silicon Labs will not be liable for any consequential, incidental, or
+ * special damages, or any other relief, or for any claim by any third party,
+ * arising from your use of this Software.
+ *
+ ******************************************************************************/
+#ifndef MBED_DEVICE_PERIPHERALS_H
+#define MBED_DEVICE_PERIPHERALS_H
+
+/* us ticker */
+#define US_TICKER_TIMER         TIMER0
+#define US_TICKER_TIMER_CLOCK	cmuClock_TIMER0
+#define US_TICKER_TIMER_IRQ     TIMER0_IRQn
+
+/* PWM */
+#define PWM_TIMER        TIMER1
+#define PWM_TIMER_CLOCK  cmuClock_TIMER1
+#define PWM_ROUTE        TIMER_ROUTE_LOCATION_LOC1
+
+/* Clocks */
+
+/* Clock definitions */
+#define LFXO    0
+#define HFXO    1
+#define LFRCO   2
+#define HFRCO   3
+#define ULFRCO  4
+
+
+/* Low Energy peripheral clock source.
+ * Options:
+ * 	* LFXO: external crystal, please define frequency.
+ * 	* LFRCO: internal RC oscillator (32.768kHz)
+ * 	* ULFRCO: internal ultra-low power RC oscillator (available down to EM3) (1kHz)
+ */
+#define LOW_ENERGY_CLOCK_SOURCE		LFXO
+
+/** Core clock source.
+ * Options:
+ * 	* HFXO: external crystal, please define frequency.
+ * 	* HFRCO: High-frequency internal RC oscillator. Please select frequency as well.
+ */
+#define CORE_CLOCK_SOURCE		HFXO
+
+#define HFRCO_FREQUENCY_ENUM            cmuHFRCOFreq_19M0Hz
+#define HFRCO_FREQUENCY                 19000000
+
+#define LFXO_FREQUENCY			32768
+#define HFXO_FREQUENCY			40000000
+
+#if (LOW_ENERGY_CLOCK_SOURCE == LFXO)
+#define LOW_ENERGY_CLOCK_FREQUENCY	LFXO_FREQUENCY
+#elif (LOW_ENERGY_CLOCK_SOURCE == LFRCO)
+#define LOW_ENERGY_CLOCK_FREQUENCY	32768
+#elif (LOW_ENERGY_CLOCK_SOURCE == ULFRCO)
+#define LOW_ENERGY_CLOCK_FREQUENCY	1000
+#else
+#error "Unknown Low Energy Clock selection"
+#endif
+
+#endif

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/analogin_api.c	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/analogin_api.c	Fri Jan 15 07:45:16 2016 +0000
@@ -41,26 +41,16 @@
 #include "em_adc.h"
 #include "em_cmu.h"
 
-uint8_t analogin_get_index(analogin_t *obj)
+void analogin_init(analogin_t *obj, PinName pin)
 {
-    return 0; //only one module availalbe
-}
+    static uint8_t adc_initialized = 0;
 
-void analogin_preinit(analogin_t *obj, PinName pin)
-{
+    /* Init structure */
     obj->adc = (ADC_TypeDef *) pinmap_peripheral(pin, PinMap_ADC);
     MBED_ASSERT((int) obj->adc != NC);
 
     obj->channel = pin_location(pin, PinMap_ADC);
     MBED_ASSERT((int) obj->channel != NC);
-}
-
-void analogin_init(analogin_t *obj, PinName pin)
-{
-    static uint8_t adc_initialized = 0;
-
-    /* Init structure */
-    analogin_preinit(obj, pin);
 
     /* Only initialize the ADC once */
     if (!adc_initialized) {
@@ -86,31 +76,6 @@
     }
 }
 
-void analogin_enable(analogin_t *obj, uint8_t enable)
-{
-    //not avail for EFM32
-}
-
-void analogin_enable_pins(analogin_t *obj, uint8_t enable)
-{
-    //not avail for EFM32
-}
-
-void analogin_enable_interrupt(analogin_t *obj, uint32_t address, uint8_t enable)
-{
-    NVIC_SetVector(ADC0_IRQn, address);
-    if (enable) {
-        // enable end of conversion interrupt
-        ADC_IntEnable(obj->adc, ADC_IEN_SCAN);
-        ADC_IntSet(obj->adc, ADC_IF_SCAN);
-        NVIC_EnableIRQ(ADC0_IRQn);
-    } else {
-        ADC_IntDisable(obj->adc, ADC_IEN_SCAN);
-        ADC_IntClear(obj->adc, ADC_IF_SCAN);
-        NVIC_DisableIRQ(ADC0_IRQn);
-    }
-}
-
 uint16_t analogin_read_u16(analogin_t *obj)
 {
     ADC_TypeDef *adc = obj->adc;
@@ -120,7 +85,11 @@
     adc->CMD = ADC_CMD_SINGLESTOP;
 
     // Make sure we are checking the correct channel
+#if defined _ADC_SINGLECTRL_INPUTSEL_MASK
     adc->SINGLECTRL = (adc->SINGLECTRL & ~_ADC_SINGLECTRL_INPUTSEL_MASK) | obj->channel;
+#elif _ADC_SINGLECTRL_POSSEL_MASK
+    adc->SINGLECTRL = (adc->SINGLECTRL & ~_ADC_SINGLECTRL_POSSEL_MASK) | obj->channel << _ADC_SINGLECTRL_POSSEL_SHIFT;
+#endif
 
     ADC_Start(adc, adcStartSingle);
 

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/analogout_api.c	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/analogout_api.c	Fri Jan 15 07:45:16 2016 +0000
@@ -42,26 +42,18 @@
 #include "em_dac.h"
 #include "em_cmu.h"
 
-uint8_t analogout_get_index(dac_t *obj)
+static uint8_t dac_initialized = 0;
+
+void analogout_init(dac_t *obj, PinName pin)
 {
-    return 0;
-}
-
-void analogout_preinit(dac_t *obj, PinName pin)
-{
+    /* init in-memory structure */
     obj->dac = (DAC_TypeDef *) pinmap_peripheral(pin, PinMap_DAC);
     MBED_ASSERT((int) obj->dac != NC);
 
     obj->channel = pin_location(pin, PinMap_DAC);
     MBED_ASSERT((int) obj->channel != NC);
-}
-
-void analogout_init(dac_t *obj, PinName pin)
-{
-    static uint8_t dac_initialized = 0;
-
-    /* init in-memory structure */
-    analogout_preinit(obj, pin);
+    
+    pin_mode(pin, Disabled);
 
     if (!dac_initialized) {
         /* Initialize the DAC. Will disable both DAC channels, so should only be done once */
@@ -83,19 +75,22 @@
     }
     /* Use default channel settings */
     DAC_InitChannel_TypeDef initChannel = DAC_INITCHANNEL_DEFAULT;
+    initChannel.enable = true;
     DAC_InitChannel(obj->dac, &initChannel, obj->channel);
-
-
 }
 
-void analogout_enable(dac_t *obj, uint8_t enable)
+void analogout_free(dac_t *obj)
 {
-    DAC_Enable(obj->dac, obj->channel, enable);
-}
-
-void analogout_pins_enable(dac_t *obj, uint8_t enable)
-{
-    //not avail for EFM32
+    //Reset channel by re-initializing
+    DAC_InitChannel_TypeDef initChannel = DAC_INITCHANNEL_DEFAULT;
+    initChannel.enable = false;
+    DAC_InitChannel(obj->dac, &initChannel, obj->channel);
+    
+    //Check all channels to see if we can disable the DAC completely
+    if((DAC0->CH0CTRL & DAC_CH0CTRL_EN) == 0 && (DAC0->CH1CTRL & DAC_CH1CTRL_EN) == 0) {
+        CMU_ClockEnable(cmuClock_DAC0, false);
+        dac_initialized = 0;
+    }
 }
 
 static inline void dac_write(dac_t *obj, int value)

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/clocking.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/clocking.h	Fri Jan 15 07:45:16 2016 +0000
@@ -32,37 +32,45 @@
 #include "device_peripherals.h"
 
 #if( CORE_CLOCK_SOURCE == HFXO)
-#define REFERENCE_FREQUENCY HFXO_FREQUENCY
+# define REFERENCE_FREQUENCY HFXO_FREQUENCY
 #elif( CORE_CLOCK_SOURCE == HFRCO)
-#if( HFRCO_FREQUENCY == CMU_HFRCOCTRL_BAND_1MHZ)
-#define REFERENCE_FREQUENCY 1000000
-#elif(HFRCO_FREQUENCY == CMU_HFRCOCTRL_BAND_7MHZ)
-#define REFERENCE_FREQUENCY 7000000
-#elif(HFRCO_FREQUENCY == CMU_HFRCOCTRL_BAND_11MHZ)
-#define REFERENCE_FREQUENCY 7000000
-#elif(HFRCO_FREQUENCY == CMU_HFRCOCTRL_BAND_14MHZ)
-#define REFERENCE_FREQUENCY 14000000
-#elif(HFRCO_FREQUENCY == CMU_HFRCOCTRL_BAND_21MHZ)
-#define REFERENCE_FREQUENCY 21000000
-#elif(HFRCO_FREQUENCY == CMU_HFRCOCTRL_BAND_28MHZ)
-#define REFERENCE_FREQUENCY 28000000
-#else
-#define REFERENCE_FREQUENCY 14000000
-#endif
+
+# if defined _CMU_HFRCOCTRL_BAND_MASK
+#  if( HFRCO_FREQUENCY == CMU_HFRCOCTRL_BAND_1MHZ)
+#   define REFERENCE_FREQUENCY 1000000
+#  elif(HFRCO_FREQUENCY == CMU_HFRCOCTRL_BAND_7MHZ)
+#   define REFERENCE_FREQUENCY 7000000
+#  elif(HFRCO_FREQUENCY == CMU_HFRCOCTRL_BAND_11MHZ)
+#   define REFERENCE_FREQUENCY 7000000
+#  elif(HFRCO_FREQUENCY == CMU_HFRCOCTRL_BAND_14MHZ)
+#   define REFERENCE_FREQUENCY 14000000
+#  elif(HFRCO_FREQUENCY == CMU_HFRCOCTRL_BAND_21MHZ)
+#   define REFERENCE_FREQUENCY 21000000
+#  elif(HFRCO_FREQUENCY == CMU_HFRCOCTRL_BAND_28MHZ)
+#   define REFERENCE_FREQUENCY 28000000
+#  else
+#   define REFERENCE_FREQUENCY 14000000
+#  endif
+# elif defined _CMU_HFRCOCTRL_FREQRANGE_MASK
+#  define REFERENCE_FREQUENCY HFRCO_FREQUENCY
+# else
+#  error "HFRCO frequency not defined"
+# endif
 #endif
 
 #if ( LOW_ENERGY_CLOCK_SOURCE == LFXO )
-#define LEUART_USING_LFXO
-#if ( defined(CMU_CTRL_HFLE) && (REFERENCE_FREQUENCY > 24000000) )
-#define LEUART_HF_REF_FREQ (REFERENCE_FREQUENCY / 4)
+# define LEUART_USING_LFXO
+# if ( (defined(CMU_CTRL_HFLE) || defined(CMU_CTRL_WSHFLE) ) && (REFERENCE_FREQUENCY > 24000000) )
+#  define LEUART_HF_REF_FREQ (REFERENCE_FREQUENCY / 4)
+# else
+#  define LEUART_HF_REF_FREQ (REFERENCE_FREQUENCY / 2)
+# endif
+# define LEUART_LF_REF_FREQ LFXO_FREQUENCY
 #else
-#define LEUART_HF_REF_FREQ (REFERENCE_FREQUENCY / 2)
+# if ( (defined(CMU_CTRL_HFLE) || defined(CMU_CTRL_WSHFLE) ) && (REFERENCE_FREQUENCY > 24000000) )
+#  define LEUART_REF_FREQ (REFERENCE_FREQUENCY / 4)
+# else
+#  define LEUART_REF_FREQ (REFERENCE_FREQUENCY / 2)
+# endif
 #endif
-#define LEUART_LF_REF_FREQ LFXO_FREQUENCY
-#else
-#if ( defined(CMU_CTRL_HFLE) && (REFERENCE_FREQUENCY > 24000000) )
-#define LEUART_REF_FREQ (REFERENCE_FREQUENCY / 4)
-#else
-#define LEUART_REF_FREQ (REFERENCE_FREQUENCY / 2)
-#endif
-#endif
+

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/dma_api.c	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/dma_api.c	Fri Jan 15 07:45:16 2016 +0000
@@ -30,10 +30,20 @@
 
 #include <stdint.h>
 #include "dma_api_HAL.h"
+#include "em_device.h"
+#include "em_cmu.h"
+#include "em_int.h"
+
+#ifdef DMA_PRESENT
 #include "em_dma.h"
-#include "em_cmu.h"
+#endif
+
+#ifdef LDMA_PRESENT
+#include "em_ldma.h"
+#endif
 
 /** DMA control block array, requires proper alignment. */
+#ifdef DMA_PRESENT
 #if defined (__ICCARM__)
 #pragma data_alignment=DMACTRL_ALIGNMENT
 DMA_DESCRIPTOR_TypeDef dmaControlBlock[DMACTRL_CH_CNT * 2];
@@ -47,6 +57,7 @@
 #else
 #error Undefined toolkit, need to define alignment
 #endif
+#endif /* DMA_PRESENT */
 
 uint32_t channels = 0; // Bit vector of taken channels
 bool enabled = false;
@@ -54,15 +65,32 @@
 void dma_init(void)
 {
     if (enabled) return;
+
+#if defined DMA_PRESENT
+    CMU_ClockEnable(cmuClock_DMA, true);
+    CMU_ClockEnable(cmuClock_HFPER, true); // FIXME: DMA is clocked via HFCORECLK, why HFPERCLK?
+
     DMA_Init_TypeDef   dmaInit;
 
-    CMU_ClockEnable(cmuClock_DMA, true);
-    CMU_ClockEnable(cmuClock_HFPER, true);
-
-    /* Configure general DMA issues */
     dmaInit.hprot        = 0;
     dmaInit.controlBlock = dmaControlBlock;
     DMA_Init(&dmaInit);
+
+#elif defined LDMA_PRESENT
+    CMU_ClockEnable(cmuClock_LDMA, true);
+
+    LDMA_Init_t ldmaInit;
+
+    ldmaInit.ldmaInitCtrlNumFixed = 0;     /* All channels round-robin */
+    ldmaInit.ldmaInitCtrlSyncPrsClrEn = 0; /* Do not allow PRS to clear SYNCTRIG */
+    ldmaInit.ldmaInitCtrlSyncPrsSetEn = 0; /* Do not allow PRS to set SYNCTRIG */
+    ldmaInit.ldmaInitIrqPriority = 2;      /* IRQ Priority */
+
+    LDMA_Init(&ldmaInit);
+#else
+#error "Unrecognized DMA peripheral"
+#endif
+
     enabled = true;
 }
 
@@ -97,7 +125,87 @@
 
 int dma_channel_free(int channelid)
 {
-    channels &= ~(1 << channelid);
+    if( channelid >= 0 ) {
+        channels &= ~(1 << channelid);
+    }
+
     return 0;
 }
 
+#ifdef LDMA_PRESENT
+
+/* LDMA emlib API extensions */
+
+typedef struct {
+    LDMAx_CBFunc_t callback;
+    void *userdata;
+} LDMA_InternCallback_t;
+
+static LDMA_InternCallback_t ldmaCallback[DMA_CHAN_COUNT];
+
+void LDMAx_StartTransfer(  int ch,
+                           LDMA_TransferCfg_t *transfer,
+                           LDMA_Descriptor_t  *descriptor,
+                           LDMAx_CBFunc_t cbFunc,
+                           void *userData )
+{
+    ldmaCallback[ch].callback = cbFunc;
+    ldmaCallback[ch].userdata = userData;
+
+    LDMA_StartTransfer(ch, transfer, descriptor);
+}
+
+void LDMA_IRQHandler( void )
+{
+    uint32_t pending, chnum, chmask;
+
+    /* Get all pending and enabled interrupts */
+    pending  = LDMA->IF;
+    pending &= LDMA->IEN;
+
+    /* Check for LDMA error */
+    if ( pending & LDMA_IF_ERROR )
+    {
+        /* Loop here to enable the debugger to see what has happened */
+        while (1)
+            ;
+    }
+
+    /* Iterate over all LDMA channels. */
+    for ( chnum = 0,                chmask = 1;
+          chnum < DMA_CHAN_COUNT;
+          chnum++,                  chmask <<= 1 )
+    {
+        if ( pending & chmask )
+        {
+            /* Clear interrupt flag. */
+            LDMA->IFC = chmask;
+
+            /* Do more stuff here, execute callbacks etc. */
+            if ( ldmaCallback[chnum].callback )
+            {
+                ldmaCallback[chnum].callback(chnum, false, ldmaCallback[chnum].userdata);
+            }
+        }
+    }
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Check if LDMA channel is enabled.
+ *
+ * @param[in] ch
+ *   LDMA channel to check.
+ *
+ * @return
+ *   true if channel is enabled, false if not.
+ ******************************************************************************/
+bool LDMAx_ChannelEnabled( int ch )
+{
+    EFM_ASSERT(ch < DMA_CHAN_COUNT);
+    uint32_t chMask = 1 << ch;
+    return (bool)(LDMA->CHEN & chMask);
+    INT_Disable();
+}
+
+#endif /* LDMA_PRESENT */

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/dma_api_HAL.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/dma_api_HAL.h	Fri Jan 15 07:45:16 2016 +0000
@@ -33,7 +33,15 @@
 
 #include <stdint.h>
 #include "dma_api.h"
+#include "em_device.h"
+
+#ifdef DMA_PRESENT
 #include "em_dma.h"
+#endif
+
+#ifdef LDMA_PRESENT
+#include "em_ldma.h"
+#endif
 
 #ifdef __cplusplus
 extern "C" {
@@ -60,10 +68,31 @@
 #error "Unsupported DMA channel count (dma_api.c)."
 #endif
 
+#ifdef LDMA_PRESENT
+typedef void (*LDMAx_CBFunc_t)(unsigned int channel, bool primary, void *user);
+
+typedef struct
+{
+    LDMAx_CBFunc_t cbFunc;
+    void *userPtr;
+} LDMAx_Callback_t;
+
+void LDMAx_StartTransfer(  int ch,
+                           LDMA_TransferCfg_t *transfer,
+                           LDMA_Descriptor_t  *descriptor,
+                           LDMAx_CBFunc_t cbFunc,
+                           void *userData );
+bool LDMAx_ChannelEnabled( int ch );
+#endif
+
 typedef struct {
     DMAUsage dmaUsageState;
     int dmaChannel;
+#ifndef LDMA_PRESENT
     DMA_CB_TypeDef dmaCallback;
+#else
+    LDMAx_Callback_t dmaCallback;
+#endif
 } DMA_OPTIONS_t;
 
 typedef void (*DMACallback)(void);

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/Changes_emlib.txt	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/Changes_emlib.txt	Fri Jan 15 07:45:16 2016 +0000
@@ -1,6 +1,65 @@
 ================ Revision history ============================================
+4.2.1:
+ - Added errata fix for an issue that may cause BOD resets in EM2 when using
+   DCDC-to-DVDD mode. The fix is implemented in EMU_DCDCInit().
+ - Added function EMU_DCDCPowerOff() for boards with physically disconnected DCDC.
+ - Current consumption is optimized for DCDC bypass mode. This update is
+   implemented in EMU_DCDCInit().
+
+4.2.0:
+ - Updated I2C clock divider equation for platform 2 parts. Added constraints
+   to HFPER clock frequency in I2C_BusFreqSet().
+ - EMU EMU_EM23VregMode_TypeDef replaced with a bool.
+ - Added support for GPIO alternate drive strength and alternate control modes.
+ - DCDC setup is simplified. More tuning and optimization settings added to
+   EMU_DCDCInit().
+ - Added member pinRetentionMode to EMU_EM4Init_TypeDef.
+ - Added function EMU_UnlatchPinRetention() to support unlatching of pin
+   retention in EM4H/S.
+ - Fixed bug in ADC_InitScan() which caused a overwrite of single conversion
+   mode calibration values.
+ - Added support for CRYPTO module on Pearl and Jade Geckos (em_crypto.c/h)
+
+4.1.1:
+ - EMU_DCDCInit() updated with new parameters for EM2 and 3. Current consumption
+   with DCDC at expected levels for EFR32 and EFM32PG revA1, A2 and B0.
+ - EMU_DCDCInit_TypeDef updated with more parameters. EMU_DcdcLpcmpBiasMode_TypeDef
+   is removed.
+ - More assertions added to EMU_DCDCInit().
+ - HFXO default parameters updated.
+ - ADC defaults updated.
+ - RMU pin mode set fixed.
+ - Added missing define for cmuSelect_ULFRCO.
+ - Added missing functions for handling peripheral interrupts.
+ - Added support for VMON.
+
+4.1.0:
+ - The typedef EMU_EM23Init_TypeDef which is a parameter to EMU_EM23Init()
+   has got a new definition.
+ - Initial support _SILICON_LABS_32B_PLATFORM_2 devices added
+
+4.0.0:
+ - Use ARM CMSIS version 4.2.0.
+ - New style version macros in em_version.h.
+
+3.20.14:
+ - USB release only.
+
+3.20.13:
+ - Added new style family #defines in em_system.h, including EZR32 families.
+ - Fixed I2C_FREQ_STANDARD_MAX macros.
+ - Fixed bug in MSC_WriteWord which called internal functions that were linked
+   to flash for armgcc. All subsequent calls of MSC_WriteWord should now be
+   linked to RAM for all supported compilers. The internals of MSC_WriteWord
+   will check the global variable SystemCoreClock in order to make sure the
+   frequency is high enough for flash operations. If the core clock frequency
+   is changed, software is responsible for calling MSC_Init or
+   SystemCoreClockGet in order to set the SystemCoreClock variable to the
+   correct value.
+ - Added errata fix IDAC_101.
+
 3.20.12:
- - Added errata fix EMU_108 and IDAC101.
+ - Added errata fix EMU_108.
  - #ifdef's now use register defines instead of a mix of register and family defines.
  - Added a case for when there are only 4 DMA channels available:
    Alignment was (correctly) defined at 7 bit, but got asserted for 8 bit, leading

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/ReadMe_emlib.txt	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/ReadMe_emlib.txt	Fri Jan 15 07:45:16 2016 +0000
@@ -1,11 +1,8 @@
 ================ Silicon Labs Peripheral Library ============================
 
 This directory, "emlib", contains the Silicon Labs Peripheral Support
-library for the EFM32 series of microcontrollers and EFR4 series for RF
-transceivers and System-On-Chip devices.
-
-The "emlib" SW is designed to support all Silicon Labs EFM and EFR devices,
-from Gecko revision B and forward.
+library for the EFM32 and EZR32 series of microcontrollers and System-On-Chip
+devices.
 
 Some design guidelines for this library:
 
@@ -26,19 +23,19 @@
 
 ================ About CMSIS ================================================
 
-These APIs are based on EFM32_CMSIS "Device" header file structure.
+These APIs are based on EM_CMSIS "Device" header file structure.
 
 As a result of this, the library requires basic C99-support. You might have
 to enable C99 support in your compiler. Comments are in doxygen compatible
 format.
 
-The EFM32_CMSIS library contains all peripheral module registers and bit field
+The EM_CMSIS library contains all peripheral module registers and bit field
 descriptors.
 
-To download EFM32_CMSIS, go to
-    http://www.silabs.com/support/pages/software-downloads.aspx
+To download EM_CMSIS, go to
+    http://www.silabs.com/support/pages/document-library.aspx?p=MCUs--32-bit
 
-For more information about CMSIS see 
+For more information about CMSIS see
     http://www.onarm.com
     http://www.arm.com/products/CPUs/CMSIS.html
 
@@ -59,8 +56,8 @@
 ================ Software updates ============================================
 
 Silicon Labs continually works to provide updated and improved emlib, example
-code and other software of use for Silicon Labs customers. Please check the 
-download section of Silicon Labs's web site at 
+code and other software of use for Silicon Labs customers. Please check the
+download section of Silicon Labs's web site at
 
         http://www.silabs.com
 
@@ -68,5 +65,4 @@
 Simplicity Studio application, you will be notified about updates when
 available.
 
-
-(C) Copyright Silicon Labs, 2014
+(C) Copyright Silicon Labs, 2015

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_acmp.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_acmp.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /***************************************************************************//**
  * @file em_acmp.h
  * @brief Analog Comparator (ACMP) peripheral API
- * @version 3.20.12
+ * @version 4.2.1
  *******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
  *******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,9 +30,8 @@
  *
  ******************************************************************************/
 
-
-#ifndef __SILICON_LABS_EM_ACMP_H_
-#define __SILICON_LABS_EM_ACMP_H_
+#ifndef __SILICON_LABS_EM_ACMP_H__
+#define __SILICON_LABS_EM_ACMP_H__
 
 #include "em_device.h"
 #if defined(ACMP_COUNT) && (ACMP_COUNT > 0)
@@ -58,34 +57,57 @@
  ********************************   ENUMS   ************************************
  ******************************************************************************/
 
-/** Resistor values used for capacative sense. See the datasheet for your
- *  device for details on each resistor value. */
+/** Resistor values used for the internal capacative sense resistor. See the
+ *  datasheet for your device for details on each resistor value. */
 typedef enum
 {
-  /** resistor value 0 */
-  acmpResistor0 = _ACMP_INPUTSEL_CSRESSEL_RES0,
-  /** resistor value 1 */
-  acmpResistor1 = _ACMP_INPUTSEL_CSRESSEL_RES1,
-  /** resistor value 2 */
-  acmpResistor2 = _ACMP_INPUTSEL_CSRESSEL_RES2,
-  /** resistor value 3 */
-  acmpResistor3 = _ACMP_INPUTSEL_CSRESSEL_RES3
+  acmpResistor0 = _ACMP_INPUTSEL_CSRESSEL_RES0,   /**< Resistor value 0 */
+  acmpResistor1 = _ACMP_INPUTSEL_CSRESSEL_RES1,   /**< Resistor value 1 */
+  acmpResistor2 = _ACMP_INPUTSEL_CSRESSEL_RES2,   /**< Resistor value 2 */
+  acmpResistor3 = _ACMP_INPUTSEL_CSRESSEL_RES3,   /**< Resistor value 3 */
+#if defined(_ACMP_INPUTSEL_CSRESSEL_RES4)
+  acmpResistor4 = _ACMP_INPUTSEL_CSRESSEL_RES4,   /**< Resistor value 4 */
+  acmpResistor5 = _ACMP_INPUTSEL_CSRESSEL_RES5,   /**< Resistor value 5 */
+  acmpResistor6 = _ACMP_INPUTSEL_CSRESSEL_RES6,   /**< Resistor value 6 */
+  acmpResistor7 = _ACMP_INPUTSEL_CSRESSEL_RES7,   /**< Resistor value 7 */
+#endif
 } ACMP_CapsenseResistor_TypeDef;
 
 /** Hysteresis level. See datasheet for your device for details on each
  *  level. */
 typedef enum
 {
-  acmpHysteresisLevel0 = _ACMP_CTRL_HYSTSEL_HYST0, /**< Hysteresis level 0 */
-  acmpHysteresisLevel1 = _ACMP_CTRL_HYSTSEL_HYST1, /**< Hysteresis level 1 */
-  acmpHysteresisLevel2 = _ACMP_CTRL_HYSTSEL_HYST2, /**< Hysteresis level 2 */
-  acmpHysteresisLevel3 = _ACMP_CTRL_HYSTSEL_HYST3, /**< Hysteresis level 3 */
-  acmpHysteresisLevel4 = _ACMP_CTRL_HYSTSEL_HYST4, /**< Hysteresis level 4 */
-  acmpHysteresisLevel5 = _ACMP_CTRL_HYSTSEL_HYST5, /**< Hysteresis level 5 */
-  acmpHysteresisLevel6 = _ACMP_CTRL_HYSTSEL_HYST6, /**< Hysteresis level 6 */
-  acmpHysteresisLevel7 = _ACMP_CTRL_HYSTSEL_HYST7  /**< Hysteresis level 7 */
+#if defined(_ACMP_CTRL_HYSTSEL_MASK)
+  acmpHysteresisLevel0 = _ACMP_CTRL_HYSTSEL_HYST0,       /**< Hysteresis level 0 */
+  acmpHysteresisLevel1 = _ACMP_CTRL_HYSTSEL_HYST1,       /**< Hysteresis level 1 */
+  acmpHysteresisLevel2 = _ACMP_CTRL_HYSTSEL_HYST2,       /**< Hysteresis level 2 */
+  acmpHysteresisLevel3 = _ACMP_CTRL_HYSTSEL_HYST3,       /**< Hysteresis level 3 */
+  acmpHysteresisLevel4 = _ACMP_CTRL_HYSTSEL_HYST4,       /**< Hysteresis level 4 */
+  acmpHysteresisLevel5 = _ACMP_CTRL_HYSTSEL_HYST5,       /**< Hysteresis level 5 */
+  acmpHysteresisLevel6 = _ACMP_CTRL_HYSTSEL_HYST6,       /**< Hysteresis level 6 */
+  acmpHysteresisLevel7 = _ACMP_CTRL_HYSTSEL_HYST7        /**< Hysteresis level 7 */
+#endif
+#if defined(_ACMP_HYSTERESIS0_HYST_MASK)
+  acmpHysteresisLevel0 = _ACMP_HYSTERESIS0_HYST_HYST0,   /**< Hysteresis level 0 */
+  acmpHysteresisLevel1 = _ACMP_HYSTERESIS0_HYST_HYST1,   /**< Hysteresis level 1 */
+  acmpHysteresisLevel2 = _ACMP_HYSTERESIS0_HYST_HYST2,   /**< Hysteresis level 2 */
+  acmpHysteresisLevel3 = _ACMP_HYSTERESIS0_HYST_HYST3,   /**< Hysteresis level 3 */
+  acmpHysteresisLevel4 = _ACMP_HYSTERESIS0_HYST_HYST4,   /**< Hysteresis level 4 */
+  acmpHysteresisLevel5 = _ACMP_HYSTERESIS0_HYST_HYST5,   /**< Hysteresis level 5 */
+  acmpHysteresisLevel6 = _ACMP_HYSTERESIS0_HYST_HYST6,   /**< Hysteresis level 6 */
+  acmpHysteresisLevel7 = _ACMP_HYSTERESIS0_HYST_HYST7,   /**< Hysteresis level 7 */
+  acmpHysteresisLevel8 = _ACMP_HYSTERESIS0_HYST_HYST8,   /**< Hysteresis level 8 */
+  acmpHysteresisLevel9 = _ACMP_HYSTERESIS0_HYST_HYST9,   /**< Hysteresis level 9 */
+  acmpHysteresisLevel10 = _ACMP_HYSTERESIS0_HYST_HYST10, /**< Hysteresis level 10 */
+  acmpHysteresisLevel11 = _ACMP_HYSTERESIS0_HYST_HYST11, /**< Hysteresis level 11 */
+  acmpHysteresisLevel12 = _ACMP_HYSTERESIS0_HYST_HYST12, /**< Hysteresis level 12 */
+  acmpHysteresisLevel13 = _ACMP_HYSTERESIS0_HYST_HYST13, /**< Hysteresis level 13 */
+  acmpHysteresisLevel14 = _ACMP_HYSTERESIS0_HYST_HYST14, /**< Hysteresis level 14 */
+  acmpHysteresisLevel15 = _ACMP_HYSTERESIS0_HYST_HYST15, /**< Hysteresis level 15 */
+#endif
 } ACMP_HysteresisLevel_TypeDef;
 
+#if defined(_ACMP_CTRL_WARMTIME_MASK)
 /** ACMP warmup time. The delay is measured in HFPERCLK cycles and should
  *  be at least 10 us. */
 typedef enum
@@ -107,7 +129,297 @@
   /** 512 HFPERCLK cycles warmup */
   acmpWarmTime512 = _ACMP_CTRL_WARMTIME_512CYCLES
 } ACMP_WarmTime_TypeDef;
+#endif
 
+#if defined(_ACMP_CTRL_INPUTRANGE_MASK)
+/**
+ * Adjust performance of the ACMP for a given input voltage range
+ */
+typedef enum
+{
+  acmpInputRangeFull = _ACMP_CTRL_INPUTRANGE_FULL,      /**< Input can be from 0 to Vdd */
+  acmpInputRangeHigh = _ACMP_CTRL_INPUTRANGE_GTVDDDIV2, /**< Input will always be greater than Vdd/2 */
+  acmpInputRangeLow  = _ACMP_CTRL_INPUTRANGE_LTVDDDIV2  /**< Input will always be less than Vdd/2 */
+} ACMP_InputRange_TypeDef;
+#endif
+
+#if defined(_ACMP_CTRL_PWRSEL_MASK)
+/**
+ * ACMP Power source.
+ */
+typedef enum
+{
+  acmpPowerSourceAvdd    = _ACMP_CTRL_PWRSEL_AVDD,    /**< Power the ACMP using the AVDD supply */
+  acmpPowerSourceVddVreg = _ACMP_CTRL_PWRSEL_VREGVDD, /**< Power the ACMP using the VREGVDD supply */
+  acmpPowerSourceIOVdd0  = _ACMP_CTRL_PWRSEL_IOVDD0,  /**< Power the ACMP using the IOVDD/IOVDD0 supply */
+  acmpPowerSourceIOVdd1  = _ACMP_CTRL_PWRSEL_IOVDD1,  /**< Power the ACMP using the IOVDD1 supply (if part has two I/O voltages) */
+} ACMP_PowerSource_TypeDef;
+#endif
+
+#if defined(_ACMP_CTRL_ACCURACY_MASK)
+/**
+ * ACMP accuracy mode.
+ */
+typedef enum
+{
+  acmpAccuracyLow = _ACMP_CTRL_ACCURACY_LOW,   /**< Low-accuracy mode but consume less current */
+  acmpAccuracyHigh = _ACMP_CTRL_ACCURACY_HIGH  /**< High-accuracy mode but consume more current */
+} ACMP_Accuracy_TypeDef;
+#endif
+
+#if defined(_ACMP_INPUTSEL_VASEL_MASK)
+/** ACMP Input to the VA divider. This enum is used to select the input for
+ *  the VA Divider */
+typedef enum
+{
+  acmpVAInputVDD       = _ACMP_INPUTSEL_VASEL_VDD,
+  acmpVAInputAPORT2YCH0  = _ACMP_INPUTSEL_VASEL_APORT2YCH0,
+  acmpVAInputAPORT2YCH2  = _ACMP_INPUTSEL_VASEL_APORT2YCH2,
+  acmpVAInputAPORT2YCH4  = _ACMP_INPUTSEL_VASEL_APORT2YCH4,
+  acmpVAInputAPORT2YCH6  = _ACMP_INPUTSEL_VASEL_APORT2YCH6,
+  acmpVAInputAPORT2YCH8  = _ACMP_INPUTSEL_VASEL_APORT2YCH8,
+  acmpVAInputAPORT2YCH10 = _ACMP_INPUTSEL_VASEL_APORT2YCH10,
+  acmpVAInputAPORT2YCH12 = _ACMP_INPUTSEL_VASEL_APORT2YCH12,
+  acmpVAInputAPORT2YCH14 = _ACMP_INPUTSEL_VASEL_APORT2YCH14,
+  acmpVAInputAPORT2YCH16 = _ACMP_INPUTSEL_VASEL_APORT2YCH16,
+  acmpVAInputAPORT2YCH18 = _ACMP_INPUTSEL_VASEL_APORT2YCH18,
+  acmpVAInputAPORT2YCH20 = _ACMP_INPUTSEL_VASEL_APORT2YCH20,
+  acmpVAInputAPORT2YCH22 = _ACMP_INPUTSEL_VASEL_APORT2YCH22,
+  acmpVAInputAPORT2YCH24 = _ACMP_INPUTSEL_VASEL_APORT2YCH24,
+  acmpVAInputAPORT2YCH26 = _ACMP_INPUTSEL_VASEL_APORT2YCH26,
+  acmpVAInputAPORT2YCH28 = _ACMP_INPUTSEL_VASEL_APORT2YCH28,
+  acmpVAInputAPORT2YCH30 = _ACMP_INPUTSEL_VASEL_APORT2YCH30,
+  acmpVAInputAPORT1XCH0  = _ACMP_INPUTSEL_VASEL_APORT1XCH0,
+  acmpVAInputAPORT1YCH1  = _ACMP_INPUTSEL_VASEL_APORT1YCH1,
+  acmpVAInputAPORT1XCH2  = _ACMP_INPUTSEL_VASEL_APORT1XCH2,
+  acmpVAInputAPORT1YCH3  = _ACMP_INPUTSEL_VASEL_APORT1YCH3,
+  acmpVAInputAPORT1XCH4  = _ACMP_INPUTSEL_VASEL_APORT1XCH4,
+  acmpVAInputAPORT1YCH5  = _ACMP_INPUTSEL_VASEL_APORT1YCH5,
+  acmpVAInputAPORT1XCH6  = _ACMP_INPUTSEL_VASEL_APORT1XCH6,
+  acmpVAInputAPORT1YCH7  = _ACMP_INPUTSEL_VASEL_APORT1YCH7,
+  acmpVAInputAPORT1XCH8  = _ACMP_INPUTSEL_VASEL_APORT1XCH8,
+  acmpVAInputAPORT1YCH9  = _ACMP_INPUTSEL_VASEL_APORT1YCH9,
+  acmpVAInputAPORT1XCH10 = _ACMP_INPUTSEL_VASEL_APORT1XCH10,
+  acmpVAInputAPORT1YCH11 = _ACMP_INPUTSEL_VASEL_APORT1YCH11,
+  acmpVAInputAPORT1XCH12 = _ACMP_INPUTSEL_VASEL_APORT1XCH12,
+  acmpVAInputAPORT1YCH13 = _ACMP_INPUTSEL_VASEL_APORT1YCH13,
+  acmpVAInputAPORT1XCH14 = _ACMP_INPUTSEL_VASEL_APORT1XCH14,
+  acmpVAInputAPORT1YCH15 = _ACMP_INPUTSEL_VASEL_APORT1YCH15,
+  acmpVAInputAPORT1XCH16 = _ACMP_INPUTSEL_VASEL_APORT1XCH16,
+  acmpVAInputAPORT1YCH17 = _ACMP_INPUTSEL_VASEL_APORT1YCH17,
+  acmpVAInputAPORT1XCH18 = _ACMP_INPUTSEL_VASEL_APORT1XCH18,
+  acmpVAInputAPORT1YCH19 = _ACMP_INPUTSEL_VASEL_APORT1YCH19,
+  acmpVAInputAPORT1XCH20 = _ACMP_INPUTSEL_VASEL_APORT1XCH20,
+  acmpVAInputAPORT1YCH21 = _ACMP_INPUTSEL_VASEL_APORT1YCH21,
+  acmpVAInputAPORT1XCH22 = _ACMP_INPUTSEL_VASEL_APORT1XCH22,
+  acmpVAInputAPORT1YCH23 = _ACMP_INPUTSEL_VASEL_APORT1YCH23,
+  acmpVAInputAPORT1XCH24 = _ACMP_INPUTSEL_VASEL_APORT1XCH24,
+  acmpVAInputAPORT1YCH25 = _ACMP_INPUTSEL_VASEL_APORT1YCH25,
+  acmpVAInputAPORT1XCH26 = _ACMP_INPUTSEL_VASEL_APORT1XCH26,
+  acmpVAInputAPORT1YCH27 = _ACMP_INPUTSEL_VASEL_APORT1YCH27,
+  acmpVAInputAPORT1XCH28 = _ACMP_INPUTSEL_VASEL_APORT1XCH28,
+  acmpVAInputAPORT1YCH29 = _ACMP_INPUTSEL_VASEL_APORT1YCH29,
+  acmpVAInputAPORT1XCH30 = _ACMP_INPUTSEL_VASEL_APORT1XCH30,
+  acmpVAInputAPORT1YCH31 = _ACMP_INPUTSEL_VASEL_APORT1YCH31
+} ACMP_VAInput_TypeDef;
+#endif
+
+#if defined(_ACMP_INPUTSEL_VBSEL_MASK)
+/**
+ * ACMP Input to the VB divider. This enum is used to select the input for
+ * the VB divider.
+ */
+typedef enum
+{
+  acmpVBInput1V25 = _ACMP_INPUTSEL_VBSEL_1V25,
+  acmpVBInput2V5  = _ACMP_INPUTSEL_VBSEL_2V5
+} ACMP_VBInput_TypeDef;
+#endif
+
+#if defined(_ACMP_INPUTSEL_VLPSEL_MASK)
+/**
+ * ACMP Low-Power Input Selection.
+ */
+typedef enum
+{
+  acmpVLPInputVADIV = _ACMP_INPUTSEL_VLPSEL_VADIV,
+  acmpVLPInputVBDIV = _ACMP_INPUTSEL_VLPSEL_VBDIV
+} ACMP_VLPInput_Typedef;
+#endif
+
+#if defined(_SILICON_LABS_32B_PLATFORM_2)
+/** ACMP Input Selection */
+typedef enum
+{
+  acmpInputAPORT0XCH0  = _ACMP_INPUTSEL_POSSEL_APORT0XCH0,
+  acmpInputAPORT0XCH1  = _ACMP_INPUTSEL_POSSEL_APORT0XCH1,
+  acmpInputAPORT0XCH2  = _ACMP_INPUTSEL_POSSEL_APORT0XCH2,
+  acmpInputAPORT0XCH3  = _ACMP_INPUTSEL_POSSEL_APORT0XCH3,
+  acmpInputAPORT0XCH4  = _ACMP_INPUTSEL_POSSEL_APORT0XCH4,
+  acmpInputAPORT0XCH5  = _ACMP_INPUTSEL_POSSEL_APORT0XCH5,
+  acmpInputAPORT0XCH6  = _ACMP_INPUTSEL_POSSEL_APORT0XCH6,
+  acmpInputAPORT0XCH7  = _ACMP_INPUTSEL_POSSEL_APORT0XCH7,
+  acmpInputAPORT0XCH8  = _ACMP_INPUTSEL_POSSEL_APORT0XCH8,
+  acmpInputAPORT0XCH9  = _ACMP_INPUTSEL_POSSEL_APORT0XCH9,
+  acmpInputAPORT0XCH10 = _ACMP_INPUTSEL_POSSEL_APORT0XCH10,
+  acmpInputAPORT0XCH11 = _ACMP_INPUTSEL_POSSEL_APORT0XCH11,
+  acmpInputAPORT0XCH12 = _ACMP_INPUTSEL_POSSEL_APORT0XCH12,
+  acmpInputAPORT0XCH13 = _ACMP_INPUTSEL_POSSEL_APORT0XCH13,
+  acmpInputAPORT0XCH14 = _ACMP_INPUTSEL_POSSEL_APORT0XCH14,
+  acmpInputAPORT0XCH15 = _ACMP_INPUTSEL_POSSEL_APORT0XCH15,
+  acmpInputAPORT0YCH0  = _ACMP_INPUTSEL_POSSEL_APORT0YCH0,
+  acmpInputAPORT0YCH1  = _ACMP_INPUTSEL_POSSEL_APORT0YCH1,
+  acmpInputAPORT0YCH2  = _ACMP_INPUTSEL_POSSEL_APORT0YCH2,
+  acmpInputAPORT0YCH3  = _ACMP_INPUTSEL_POSSEL_APORT0YCH3,
+  acmpInputAPORT0YCH4  = _ACMP_INPUTSEL_POSSEL_APORT0YCH4,
+  acmpInputAPORT0YCH5  = _ACMP_INPUTSEL_POSSEL_APORT0YCH5,
+  acmpInputAPORT0YCH6  = _ACMP_INPUTSEL_POSSEL_APORT0YCH6,
+  acmpInputAPORT0YCH7  = _ACMP_INPUTSEL_POSSEL_APORT0YCH7,
+  acmpInputAPORT0YCH8  = _ACMP_INPUTSEL_POSSEL_APORT0YCH8,
+  acmpInputAPORT0YCH9  = _ACMP_INPUTSEL_POSSEL_APORT0YCH9,
+  acmpInputAPORT0YCH10 = _ACMP_INPUTSEL_POSSEL_APORT0YCH10,
+  acmpInputAPORT0YCH11 = _ACMP_INPUTSEL_POSSEL_APORT0YCH11,
+  acmpInputAPORT0YCH12 = _ACMP_INPUTSEL_POSSEL_APORT0YCH12,
+  acmpInputAPORT0YCH13 = _ACMP_INPUTSEL_POSSEL_APORT0YCH13,
+  acmpInputAPORT0YCH14 = _ACMP_INPUTSEL_POSSEL_APORT0YCH14,
+  acmpInputAPORT0YCH15 = _ACMP_INPUTSEL_POSSEL_APORT0YCH15,
+  acmpInputAPORT1XCH0  = _ACMP_INPUTSEL_POSSEL_APORT1XCH0,
+  acmpInputAPORT1YCH1  = _ACMP_INPUTSEL_POSSEL_APORT1YCH1,
+  acmpInputAPORT1XCH2  = _ACMP_INPUTSEL_POSSEL_APORT1XCH2,
+  acmpInputAPORT1YCH3  = _ACMP_INPUTSEL_POSSEL_APORT1YCH3,
+  acmpInputAPORT1XCH4  = _ACMP_INPUTSEL_POSSEL_APORT1XCH4,
+  acmpInputAPORT1YCH5  = _ACMP_INPUTSEL_POSSEL_APORT1YCH5,
+  acmpInputAPORT1XCH6  = _ACMP_INPUTSEL_POSSEL_APORT1XCH6,
+  acmpInputAPORT1YCH7  = _ACMP_INPUTSEL_POSSEL_APORT1YCH7,
+  acmpInputAPORT1XCH8  = _ACMP_INPUTSEL_POSSEL_APORT1XCH8,
+  acmpInputAPORT1YCH9  = _ACMP_INPUTSEL_POSSEL_APORT1YCH9,
+  acmpInputAPORT1XCH10 = _ACMP_INPUTSEL_POSSEL_APORT1XCH10,
+  acmpInputAPORT1YCH11 = _ACMP_INPUTSEL_POSSEL_APORT1YCH11,
+  acmpInputAPORT1XCH12 = _ACMP_INPUTSEL_POSSEL_APORT1XCH12,
+  acmpInputAPORT1YCH13 = _ACMP_INPUTSEL_POSSEL_APORT1YCH13,
+  acmpInputAPORT1XCH14 = _ACMP_INPUTSEL_POSSEL_APORT1XCH14,
+  acmpInputAPORT1YCH15 = _ACMP_INPUTSEL_POSSEL_APORT1YCH15,
+  acmpInputAPORT1XCH16 = _ACMP_INPUTSEL_POSSEL_APORT1XCH16,
+  acmpInputAPORT1YCH17 = _ACMP_INPUTSEL_POSSEL_APORT1YCH17,
+  acmpInputAPORT1XCH18 = _ACMP_INPUTSEL_POSSEL_APORT1XCH18,
+  acmpInputAPORT1YCH19 = _ACMP_INPUTSEL_POSSEL_APORT1YCH19,
+  acmpInputAPORT1XCH20 = _ACMP_INPUTSEL_POSSEL_APORT1XCH20,
+  acmpInputAPORT1YCH21 = _ACMP_INPUTSEL_POSSEL_APORT1YCH21,
+  acmpInputAPORT1XCH22 = _ACMP_INPUTSEL_POSSEL_APORT1XCH22,
+  acmpInputAPORT1YCH23 = _ACMP_INPUTSEL_POSSEL_APORT1YCH23,
+  acmpInputAPORT1XCH24 = _ACMP_INPUTSEL_POSSEL_APORT1XCH24,
+  acmpInputAPORT1YCH25 = _ACMP_INPUTSEL_POSSEL_APORT1YCH25,
+  acmpInputAPORT1XCH26 = _ACMP_INPUTSEL_POSSEL_APORT1XCH26,
+  acmpInputAPORT1YCH27 = _ACMP_INPUTSEL_POSSEL_APORT1YCH27,
+  acmpInputAPORT1XCH28 = _ACMP_INPUTSEL_POSSEL_APORT1XCH28,
+  acmpInputAPORT1YCH29 = _ACMP_INPUTSEL_POSSEL_APORT1YCH29,
+  acmpInputAPORT1XCH30 = _ACMP_INPUTSEL_POSSEL_APORT1XCH30,
+  acmpInputAPORT1YCH31 = _ACMP_INPUTSEL_POSSEL_APORT1YCH31,
+  acmpInputAPORT2YCH0  = _ACMP_INPUTSEL_POSSEL_APORT2YCH0,
+  acmpInputAPORT2XCH1  = _ACMP_INPUTSEL_POSSEL_APORT2XCH1,
+  acmpInputAPORT2YCH2  = _ACMP_INPUTSEL_POSSEL_APORT2YCH2,
+  acmpInputAPORT2XCH3  = _ACMP_INPUTSEL_POSSEL_APORT2XCH3,
+  acmpInputAPORT2YCH4  = _ACMP_INPUTSEL_POSSEL_APORT2YCH4,
+  acmpInputAPORT2XCH5  = _ACMP_INPUTSEL_POSSEL_APORT2XCH5,
+  acmpInputAPORT2YCH6  = _ACMP_INPUTSEL_POSSEL_APORT2YCH6,
+  acmpInputAPORT2XCH7  = _ACMP_INPUTSEL_POSSEL_APORT2XCH7,
+  acmpInputAPORT2YCH8  = _ACMP_INPUTSEL_POSSEL_APORT2YCH8,
+  acmpInputAPORT2XCH9  = _ACMP_INPUTSEL_POSSEL_APORT2XCH9,
+  acmpInputAPORT2YCH10 = _ACMP_INPUTSEL_POSSEL_APORT2YCH10,
+  acmpInputAPORT2XCH11 = _ACMP_INPUTSEL_POSSEL_APORT2XCH11,
+  acmpInputAPORT2YCH12 = _ACMP_INPUTSEL_POSSEL_APORT2YCH12,
+  acmpInputAPORT2XCH13 = _ACMP_INPUTSEL_POSSEL_APORT2XCH13,
+  acmpInputAPORT2YCH14 = _ACMP_INPUTSEL_POSSEL_APORT2YCH14,
+  acmpInputAPORT2XCH15 = _ACMP_INPUTSEL_POSSEL_APORT2XCH15,
+  acmpInputAPORT2YCH16 = _ACMP_INPUTSEL_POSSEL_APORT2YCH16,
+  acmpInputAPORT2XCH17 = _ACMP_INPUTSEL_POSSEL_APORT2XCH17,
+  acmpInputAPORT2YCH18 = _ACMP_INPUTSEL_POSSEL_APORT2YCH18,
+  acmpInputAPORT2XCH19 = _ACMP_INPUTSEL_POSSEL_APORT2XCH19,
+  acmpInputAPORT2YCH20 = _ACMP_INPUTSEL_POSSEL_APORT2YCH20,
+  acmpInputAPORT2XCH21 = _ACMP_INPUTSEL_POSSEL_APORT2XCH21,
+  acmpInputAPORT2YCH22 = _ACMP_INPUTSEL_POSSEL_APORT2YCH22,
+  acmpInputAPORT2XCH23 = _ACMP_INPUTSEL_POSSEL_APORT2XCH23,
+  acmpInputAPORT2YCH24 = _ACMP_INPUTSEL_POSSEL_APORT2YCH24,
+  acmpInputAPORT2XCH25 = _ACMP_INPUTSEL_POSSEL_APORT2XCH25,
+  acmpInputAPORT2YCH26 = _ACMP_INPUTSEL_POSSEL_APORT2YCH26,
+  acmpInputAPORT2XCH27 = _ACMP_INPUTSEL_POSSEL_APORT2XCH27,
+  acmpInputAPORT2YCH28 = _ACMP_INPUTSEL_POSSEL_APORT2YCH28,
+  acmpInputAPORT2XCH29 = _ACMP_INPUTSEL_POSSEL_APORT2XCH29,
+  acmpInputAPORT2YCH30 = _ACMP_INPUTSEL_POSSEL_APORT2YCH30,
+  acmpInputAPORT2XCH31 = _ACMP_INPUTSEL_POSSEL_APORT2XCH31,
+  acmpInputAPORT3XCH0  = _ACMP_INPUTSEL_POSSEL_APORT3XCH0,
+  acmpInputAPORT3YCH1  = _ACMP_INPUTSEL_POSSEL_APORT3YCH1,
+  acmpInputAPORT3XCH2  = _ACMP_INPUTSEL_POSSEL_APORT3XCH2,
+  acmpInputAPORT3YCH3  = _ACMP_INPUTSEL_POSSEL_APORT3YCH3,
+  acmpInputAPORT3XCH4  = _ACMP_INPUTSEL_POSSEL_APORT3XCH4,
+  acmpInputAPORT3YCH5  = _ACMP_INPUTSEL_POSSEL_APORT3YCH5,
+  acmpInputAPORT3XCH6  = _ACMP_INPUTSEL_POSSEL_APORT3XCH6,
+  acmpInputAPORT3YCH7  = _ACMP_INPUTSEL_POSSEL_APORT3YCH7,
+  acmpInputAPORT3XCH8  = _ACMP_INPUTSEL_POSSEL_APORT3XCH8,
+  acmpInputAPORT3YCH9  = _ACMP_INPUTSEL_POSSEL_APORT3YCH9,
+  acmpInputAPORT3XCH10 = _ACMP_INPUTSEL_POSSEL_APORT3XCH10,
+  acmpInputAPORT3YCH11 = _ACMP_INPUTSEL_POSSEL_APORT3YCH11,
+  acmpInputAPORT3XCH12 = _ACMP_INPUTSEL_POSSEL_APORT3XCH12,
+  acmpInputAPORT3YCH13 = _ACMP_INPUTSEL_POSSEL_APORT3YCH13,
+  acmpInputAPORT3XCH14 = _ACMP_INPUTSEL_POSSEL_APORT3XCH14,
+  acmpInputAPORT3YCH15 = _ACMP_INPUTSEL_POSSEL_APORT3YCH15,
+  acmpInputAPORT3XCH16 = _ACMP_INPUTSEL_POSSEL_APORT3XCH16,
+  acmpInputAPORT3YCH17 = _ACMP_INPUTSEL_POSSEL_APORT3YCH17,
+  acmpInputAPORT3XCH18 = _ACMP_INPUTSEL_POSSEL_APORT3XCH18,
+  acmpInputAPORT3YCH19 = _ACMP_INPUTSEL_POSSEL_APORT3YCH19,
+  acmpInputAPORT3XCH20 = _ACMP_INPUTSEL_POSSEL_APORT3XCH20,
+  acmpInputAPORT3YCH21 = _ACMP_INPUTSEL_POSSEL_APORT3YCH21,
+  acmpInputAPORT3XCH22 = _ACMP_INPUTSEL_POSSEL_APORT3XCH22,
+  acmpInputAPORT3YCH23 = _ACMP_INPUTSEL_POSSEL_APORT3YCH23,
+  acmpInputAPORT3XCH24 = _ACMP_INPUTSEL_POSSEL_APORT3XCH24,
+  acmpInputAPORT3YCH25 = _ACMP_INPUTSEL_POSSEL_APORT3YCH25,
+  acmpInputAPORT3XCH26 = _ACMP_INPUTSEL_POSSEL_APORT3XCH26,
+  acmpInputAPORT3YCH27 = _ACMP_INPUTSEL_POSSEL_APORT3YCH27,
+  acmpInputAPORT3XCH28 = _ACMP_INPUTSEL_POSSEL_APORT3XCH28,
+  acmpInputAPORT3YCH29 = _ACMP_INPUTSEL_POSSEL_APORT3YCH29,
+  acmpInputAPORT3XCH30 = _ACMP_INPUTSEL_POSSEL_APORT3XCH30,
+  acmpInputAPORT3YCH31 = _ACMP_INPUTSEL_POSSEL_APORT3YCH31,
+  acmpInputAPORT4YCH0  = _ACMP_INPUTSEL_POSSEL_APORT4YCH0,
+  acmpInputAPORT4XCH1  = _ACMP_INPUTSEL_POSSEL_APORT4XCH1,
+  acmpInputAPORT4YCH2  = _ACMP_INPUTSEL_POSSEL_APORT4YCH2,
+  acmpInputAPORT4XCH3  = _ACMP_INPUTSEL_POSSEL_APORT4XCH3,
+  acmpInputAPORT4YCH4  = _ACMP_INPUTSEL_POSSEL_APORT4YCH4,
+  acmpInputAPORT4XCH5  = _ACMP_INPUTSEL_POSSEL_APORT4XCH5,
+  acmpInputAPORT4YCH6  = _ACMP_INPUTSEL_POSSEL_APORT4YCH6,
+  acmpInputAPORT4XCH7  = _ACMP_INPUTSEL_POSSEL_APORT4XCH7,
+  acmpInputAPORT4YCH8  = _ACMP_INPUTSEL_POSSEL_APORT4YCH8,
+  acmpInputAPORT4XCH9  = _ACMP_INPUTSEL_POSSEL_APORT4XCH9,
+  acmpInputAPORT4YCH10 = _ACMP_INPUTSEL_POSSEL_APORT4YCH10,
+  acmpInputAPORT4XCH11 = _ACMP_INPUTSEL_POSSEL_APORT4XCH11,
+  acmpInputAPORT4YCH12 = _ACMP_INPUTSEL_POSSEL_APORT4YCH12,
+  acmpInputAPORT4XCH13 = _ACMP_INPUTSEL_POSSEL_APORT4XCH13,
+  acmpInputAPORT4YCH16 = _ACMP_INPUTSEL_POSSEL_APORT4YCH16,
+  acmpInputAPORT4XCH17 = _ACMP_INPUTSEL_POSSEL_APORT4XCH17,
+  acmpInputAPORT4YCH18 = _ACMP_INPUTSEL_POSSEL_APORT4YCH18,
+  acmpInputAPORT4XCH19 = _ACMP_INPUTSEL_POSSEL_APORT4XCH19,
+  acmpInputAPORT4YCH20 = _ACMP_INPUTSEL_POSSEL_APORT4YCH20,
+  acmpInputAPORT4XCH21 = _ACMP_INPUTSEL_POSSEL_APORT4XCH21,
+  acmpInputAPORT4YCH22 = _ACMP_INPUTSEL_POSSEL_APORT4YCH22,
+  acmpInputAPORT4XCH23 = _ACMP_INPUTSEL_POSSEL_APORT4XCH23,
+  acmpInputAPORT4YCH24 = _ACMP_INPUTSEL_POSSEL_APORT4YCH24,
+  acmpInputAPORT4XCH25 = _ACMP_INPUTSEL_POSSEL_APORT4XCH25,
+  acmpInputAPORT4YCH26 = _ACMP_INPUTSEL_POSSEL_APORT4YCH26,
+  acmpInputAPORT4XCH27 = _ACMP_INPUTSEL_POSSEL_APORT4XCH27,
+  acmpInputAPORT4YCH28 = _ACMP_INPUTSEL_POSSEL_APORT4YCH28,
+  acmpInputAPORT4XCH29 = _ACMP_INPUTSEL_POSSEL_APORT4XCH29,
+  acmpInputAPORT4YCH30 = _ACMP_INPUTSEL_POSSEL_APORT4YCH30,
+  acmpInputAPORT4YCH14 = _ACMP_INPUTSEL_POSSEL_APORT4YCH14,
+  acmpInputAPORT4XCH15 = _ACMP_INPUTSEL_POSSEL_APORT4XCH15,
+  acmpInputAPORT4XCH31 = _ACMP_INPUTSEL_POSSEL_APORT4XCH31,
+  acmpInputDACOUT0   = _ACMP_INPUTSEL_POSSEL_DACOUT0,
+  acmpInputDACOUT1   = _ACMP_INPUTSEL_POSSEL_DACOUT1,
+  acmpInputVLP       = _ACMP_INPUTSEL_POSSEL_VLP,
+  acmpInputVBDIV     = _ACMP_INPUTSEL_POSSEL_VBDIV,
+  acmpInputVADIV     = _ACMP_INPUTSEL_POSSEL_VADIV,
+  acmpInputVDD       = _ACMP_INPUTSEL_POSSEL_VDD,
+  acmpInputVSS       = _ACMP_INPUTSEL_POSSEL_VSS,
+} ACMP_Channel_TypeDef;
+#else
 /** ACMP inputs. Note that scaled VDD and bandgap references can only be used
  *  as negative inputs. */
 typedef enum
@@ -135,21 +447,22 @@
   /** Scaled VDD reference */
   acmpChannelVDD  = _ACMP_INPUTSEL_NEGSEL_VDD,
 
-#if defined( _ACMP_INPUTSEL_NEGSEL_DAC0CH0 )
+#if defined(_ACMP_INPUTSEL_NEGSEL_DAC0CH0)
   /** DAC0 channel 0 */
   acmpChannelDAC0Ch0 = _ACMP_INPUTSEL_NEGSEL_DAC0CH0,
 #endif
 
-#if defined( _ACMP_INPUTSEL_NEGSEL_DAC0CH1 )
+#if defined(_ACMP_INPUTSEL_NEGSEL_DAC0CH1)
   /** DAC0 channel 1 */
   acmpChannelDAC0Ch1 = _ACMP_INPUTSEL_NEGSEL_DAC0CH1,
 #endif
 
-#if defined( _ACMP_INPUTSEL_NEGSEL_CAPSENSE )
+#if defined(_ACMP_INPUTSEL_NEGSEL_CAPSENSE)
   /** Capacitive sense mode */
   acmpChannelCapSense = _ACMP_INPUTSEL_NEGSEL_CAPSENSE,
 #endif
 } ACMP_Channel_TypeDef;
+#endif
 
 /*******************************************************************************
  ******************************   STRUCTS   ************************************
@@ -162,49 +475,110 @@
    *  the reference manual for details. */
   bool                          fullBias;
 
+#if defined(_ACMP_CTRL_HALFBIAS_MASK)
   /** Half bias current. See the ACMP chapter about bias and response time in
    *  the reference manual for details. */
   bool                          halfBias;
+#endif
 
   /** Bias current. See the ACMP chapter about bias and response time in the
-   *  reference manual for details. Valid values are in the range 0-7. */
+   *  reference manual for details. */
   uint32_t                      biasProg;
 
+#if defined(_ACMP_CTRL_WARMTIME_MASK)
   /** Warmup time. This is measured in HFPERCLK cycles and should be
    *  about 10us in wall clock time. */
   ACMP_WarmTime_TypeDef         warmTime;
+#endif
 
+#if defined(_ACMP_CTRL_HYSTSEL_MASK)
   /** Hysteresis level */
   ACMP_HysteresisLevel_TypeDef  hysteresisLevel;
+#else
+  /** Hysteresis level when ACMP output is 0 */
+  ACMP_HysteresisLevel_TypeDef  hysteresisLevel_0;
+
+  /** Hysteresis level when ACMP output is 1 */
+  ACMP_HysteresisLevel_TypeDef  hysteresisLevel_1;
+#endif
 
   /** Resistor used in the capacative sensing circuit. For values see
    *  your device datasheet. */
   ACMP_CapsenseResistor_TypeDef resistor;
 
+#if defined(_ACMP_INPUTSEL_LPREF_MASK)
   /** Low power reference enabled. This setting, if enabled, reduces the
    *  power used by the VDD and bandgap references. */
   bool                          lowPowerReferenceEnabled;
+#endif
 
-  /** Vdd reference value. VDD_SCALED = VDD × VDDLEVEL × 50mV/3.8V.
+#if defined(_ACMP_INPUTSEL_VDDLEVEL_MASK)
+  /** Vdd reference value. VDD_SCALED = (Vdd * VDDLEVEL) / 63.
    *  Valid values are in the range 0-63. */
   uint32_t                      vddLevel;
+#else
+  /**
+   * This value configures the upper voltage threshold of the capsense
+   * oscillation rail.
+   *
+   * The voltage threshold is calculated as
+   *   Vdd * (vddLevelHigh + 1) / 64
+   */
+  uint32_t                      vddLevelHigh;
+
+  /**
+   * This value configures the lower voltage threshold of the capsense
+   * oscillation rail.
+   *
+   * The voltage threshold is calculated as
+   *   Vdd * (vddLevelLow + 1) / 64
+   */
+  uint32_t                      vddLevelLow;
+#endif
 
   /** If true, ACMP is being enabled after configuration. */
   bool                          enable;
 } ACMP_CapsenseInit_TypeDef;
 
 /** Default config for capacitive sense mode initialization. */
-#define ACMP_CAPSENSE_INIT_DEFAULT                        \
-  { false,              /* fullBias */                    \
-    false,              /* halfBias */                    \
-    0x7,                /* biasProg */                    \
-    acmpWarmTime512,    /* 512 cycle warmup to be safe */ \
-    acmpHysteresisLevel5,                                 \
-    acmpResistor3,                                        \
-    false,              /* low power reference */         \
-    0x3D,               /* VDD level */                   \
-    true                /* Enable after init. */          \
-  }
+#if defined(_ACMP_HYSTERESIS0_HYST_MASK)
+#define ACMP_CAPSENSE_INIT_DEFAULT                                          \
+{                                                                           \
+  false,                /* Don't use fullBias to lower power consumption */ \
+  0x20,                 /* Using biasProg value of 0x20 (32) */             \
+  acmpHysteresisLevel8, /* Use hysteresis level 8 when ACMP output is 0 */  \
+  acmpHysteresisLevel8, /* Use hysteresis level 8 when ACMP output is 1 */  \
+  acmpResistor5,        /* Use internal resistor value 5 */                 \
+  0x30,                 /* VDD level high */                                \
+  0x10,                 /* VDD level low */                                 \
+  true                  /* Enable after init. */                            \
+}
+#elif defined(_ACMP_CTRL_WARMTIME_MASK)
+#define ACMP_CAPSENSE_INIT_DEFAULT                      \
+{                                                       \
+  false,              /* fullBias */                    \
+  false,              /* halfBias */                    \
+  0x7,                /* biasProg */                    \
+  acmpWarmTime512,    /* 512 cycle warmup to be safe */ \
+  acmpHysteresisLevel5,                                 \
+  acmpResistor3,                                        \
+  false,              /* low power reference */         \
+  0x3D,               /* VDD level */                   \
+  true                /* Enable after init. */          \
+}
+#else
+#define ACMP_CAPSENSE_INIT_DEFAULT                      \
+{                                                       \
+  false,              /* fullBias */                    \
+  false,              /* halfBias */                    \
+  0x7,                /* biasProg */                    \
+  acmpHysteresisLevel5,                                 \
+  acmpResistor3,                                        \
+  false,              /* low power reference */         \
+  0x3D,               /* VDD level */                   \
+  true                /* Enable after init. */          \
+}
+#endif
 
 /** ACMP initialization structure. */
 typedef struct
@@ -213,9 +587,11 @@
    *  the reference manual for details. */
   bool                         fullBias;
 
+#if defined(_ACMP_CTRL_HALFBIAS_MASK)
   /** Half bias current. See the ACMP chapter about bias and response time in
    *  the reference manual for details. */
   bool                         halfBias;
+#endif
 
   /** Bias current. See the ACMP chapter about bias and response time in the
    *  reference manual for details. Valid values are in the range 0-7. */
@@ -227,43 +603,181 @@
   /** Enable setting the interrupt flag on rising edge */
   bool                         interruptOnRisingEdge;
 
+#if defined(_ACMP_CTRL_INPUTRANGE_MASK)
+  /** Input range. Adjust this setting to optimize the performance for a
+   *  given input voltage range.  */
+  ACMP_InputRange_TypeDef      inputRange;
+#endif
+
+#if defined(_ACMP_CTRL_ACCURACY_MASK)
+  /** ACMP accuracy mode. Select the accuracy mode that matches the
+   *  required current usage and accuracy requirement. Low accuracy
+   *  consumes less current while high accuracy consumes more current. */
+  ACMP_Accuracy_TypeDef        accuracy;
+#endif
+
+#if defined(_ACMP_CTRL_PWRSEL_MASK)
+  /** Select the power source for the ACMP. */
+  ACMP_PowerSource_TypeDef     powerSource;
+#endif
+
+#if defined(_ACMP_CTRL_WARMTIME_MASK)
   /** Warmup time. This is measured in HFPERCLK cycles and should be
    *  about 10us in wall clock time. */
   ACMP_WarmTime_TypeDef        warmTime;
+#endif
 
+#if defined(_ACMP_CTRL_HYSTSEL_MASK)
   /** Hysteresis level */
   ACMP_HysteresisLevel_TypeDef hysteresisLevel;
+#else
+  /** Hysteresis when ACMP output is 0 */
+  ACMP_HysteresisLevel_TypeDef  hysteresisLevel_0;
+
+  /** Hysteresis when ACMP output is 1 */
+  ACMP_HysteresisLevel_TypeDef  hysteresisLevel_1;
+#endif
+
+#if defined(_ACMP_INPUTSEL_VLPSEL_MASK)
+  /** VLP Input source. Select between using VADIV or VBDIV as the VLP
+   *  source. */
+  ACMP_VLPInput_Typedef        vlpInput;
+#endif
 
   /** Inactive value emitted by the ACMP during warmup */
   bool                         inactiveValue;
 
+#if defined(_ACMP_INPUTSEL_LPREF_MASK)
   /** Low power reference enabled. This setting, if enabled, reduces the
    *  power used by the VDD and bandgap references. */
   bool                         lowPowerReferenceEnabled;
+#endif
 
-  /** Vdd reference value. VDD_SCALED = VDD × VDDLEVEL × 50mV/3.8V.
+#if defined(_ACMP_INPUTSEL_VDDLEVEL_MASK)
+  /** Vdd reference value. VDD_SCALED = VDD * VDDLEVEL * 50mV/3.8V.
    *  Valid values are in the range 0-63. */
   uint32_t                     vddLevel;
+#endif
 
   /** If true, ACMP is being enabled after configuration. */
   bool                         enable;
 } ACMP_Init_TypeDef;
 
 /** Default config for ACMP regular initialization. */
-#define ACMP_INIT_DEFAULT                                                     \
-  { false,              /* fullBias */                                        \
-    false,              /* halfBias */                                        \
-    0x7,                /* biasProg */                                        \
-    false,              /* No interrupt on falling edge. */                   \
-    false,              /* No interrupt on rising edge. */                    \
-    acmpWarmTime512,    /* 512 cycle warmup to be safe */                     \
-    acmpHysteresisLevel5,                                                     \
-    false,              /* Disabled emitting inactive value during warmup. */ \
-    false,              /* low power reference */                             \
-    0x3D,               /* VDD level */                                       \
-    true                /* Enable after init. */                              \
-  }
+#if defined(_ACMP_HYSTERESIS0_HYST_MASK)
+#define ACMP_INIT_DEFAULT                                                   \
+{                                                                           \
+  false,                      /* fullBias */                                \
+  0x7,                        /* biasProg */                                \
+  false,                      /* No interrupt on falling edge. */           \
+  false,                      /* No interrupt on rising edge. */            \
+  acmpInputRangeFull,         /* Input range from 0 to Vdd. */              \
+  acmpAccuracyLow,            /* Low accuracy, less current usage. */       \
+  acmpPowerSourceAvdd,        /* Use the AVDD supply. */                    \
+  acmpHysteresisLevel5,       /* Use hysteresis level 5 when output is 0 */ \
+  acmpHysteresisLevel5,       /* Use hysteresis level 5 when output is 1 */ \
+  acmpVLPInputVADIV,          /* Use VADIV as the VLP input source. */      \
+  false,                      /* Output 0 when ACMP is inactive. */         \
+  true                        /* Enable after init. */                      \
+}
+#elif defined(_ACMP_CTRL_WARMTIME_MASK)
+#define ACMP_INIT_DEFAULT                                                   \
+{                                                                           \
+  false,              /* fullBias */                                        \
+  false,              /* halfBias */                                        \
+  0x7,                /* biasProg */                                        \
+  false,              /* No interrupt on falling edge. */                   \
+  false,              /* No interrupt on rising edge. */                    \
+  acmpWarmTime512,    /* 512 cycle warmup to be safe */                     \
+  acmpHysteresisLevel5,                                                     \
+  false,              /* Disabled emitting inactive value during warmup. */ \
+  false,              /* low power reference */                             \
+  0x3D,               /* VDD level */                                       \
+  true                /* Enable after init. */                              \
+}
+#else
+#define ACMP_INIT_DEFAULT                                                   \
+{                                                                           \
+  false,              /* fullBias */                                        \
+  false,              /* halfBias */                                        \
+  0x7,                /* biasProg */                                        \
+  false,              /* No interrupt on falling edge. */                   \
+  false,              /* No interrupt on rising edge. */                    \
+  acmpHysteresisLevel5,                                                     \
+  false,              /* Disabled emitting inactive value during warmup. */ \
+  false,              /* low power reference */                             \
+  0x3D,               /* VDD level */                                       \
+  true                /* Enable after init. */                              \
+}
+#endif
+
+#if defined(_ACMP_INPUTSEL_VASEL_MASK)
+/** VA Configuration structure. This struct is used to configure the
+ *  VA voltage input source and it's dividers. */
+typedef struct
+{
+  ACMP_VAInput_TypeDef input; /**< VA voltage input source */
 
+  /**
+   * Divider for VA voltage input source when ACMP output is 0. This value is
+   * used to divide the VA voltage input source by a specific value. The valid
+   * range is between 0 and 63.
+   *
+   *  VA divided = VA input * (div0 + 1) / 64
+   */
+  uint32_t             div0;
+
+  /**
+   * Divider for VA voltage input source when ACMP output is 1. This value is
+   * used to divide the VA voltage input source by a specific value. The valid
+   * range is between 0 and 63.
+   *
+   *  VA divided = VA input * (div1 + 1) / 64
+   */
+  uint32_t             div1;
+} ACMP_VAConfig_TypeDef;
+
+#define ACMP_VACONFIG_DEFAULT                                               \
+{                                                                           \
+  acmpVAInputVDD, /* Use Vdd as VA voltage input source */                  \
+  63,             /* No division of the VA source when ACMP output is 0 */  \
+  63,             /* No division of the VA source when ACMP output is 1 */  \
+}
+#endif
+
+#if defined(_ACMP_INPUTSEL_VBSEL_MASK)
+/** VB Configuration structure. This struct is used to configure the
+ *  VB voltage input source and it's dividers. */
+typedef struct
+{
+  ACMP_VBInput_TypeDef input; /**< VB Voltage input source */
+
+  /**
+   * Divider for VB voltage input source when ACMP output is 0. This value is
+   * used to divide the VB voltage input source by a specific value. The valid
+   * range is between 0 and 63.
+   *
+   *  VB divided = VB input * (div0 + 1) / 64
+   */
+  uint32_t             div0;
+
+  /**
+   * Divider for VB voltage input source when ACMP output is 1. This value is
+   * used to divide the VB voltage input source by a specific value. The valid
+   * range is between 0 and 63.
+   *
+   *  VB divided = VB input * (div1 + 1) / 64
+   */
+  uint32_t             div1;
+} ACMP_VBConfig_TypeDef;
+
+#define ACMP_VBCONFIG_DEFAULT                                               \
+{                                                                           \
+  acmpVBInput1V25, /* Use 1.25 V as VB voltage input source */              \
+  63,              /* No division of the VB source when ACMP output is 0 */ \
+  63,              /* No division of the VB source when ACMP output is 1 */ \
+}
+#endif
 
 /*******************************************************************************
  *****************************   PROTOTYPES   **********************************
@@ -277,6 +791,12 @@
 void ACMP_GPIOSetup(ACMP_TypeDef *acmp, uint32_t location, bool enable, bool invert);
 void ACMP_Init(ACMP_TypeDef *acmp, const ACMP_Init_TypeDef *init);
 void ACMP_Reset(ACMP_TypeDef *acmp);
+#if defined(_ACMP_INPUTSEL_VASEL_MASK)
+void ACMP_VASetup(ACMP_TypeDef *acmp, const ACMP_VAConfig_TypeDef *vaconfig);
+#endif
+#if defined(_ACMP_INPUTSEL_VBSEL_MASK)
+void ACMP_VBSetup(ACMP_TypeDef *acmp, const ACMP_VBConfig_TypeDef *vbconfig);
+#endif
 
 /***************************************************************************//**
  * @brief
@@ -350,7 +870,7 @@
  ******************************************************************************/
 __STATIC_INLINE uint32_t ACMP_IntGet(ACMP_TypeDef *acmp)
 {
-  return(acmp->IF);
+  return acmp->IF;
 }
 
 
@@ -410,4 +930,4 @@
 #endif
 
 #endif /* defined(ACMP_COUNT) && (ACMP_COUNT > 0) */
-#endif /* __SILICON_LABS_EM_ACMP_H_ */
+#endif /* __SILICON_LABS_EM_ACMP_H__ */

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_adc.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_adc.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /***************************************************************************//**
  * @file em_adc.h
  * @brief Analog to Digital Converter (ADC) peripheral API
- * @version 3.20.12
+ * @version 4.2.1
  *******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
  *******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,12 +30,11 @@
  *
  ******************************************************************************/
 
-
-#ifndef __SILICON_LABS_EM_ADC_H_
-#define __SILICON_LABS_EM_ADC_H_
+#ifndef __SILICON_LABS_EM_ADC_H__
+#define __SILICON_LABS_EM_ADC_H__
 
 #include "em_device.h"
-#if defined(ADC_COUNT) && (ADC_COUNT > 0)
+#if defined( ADC_COUNT ) && ( ADC_COUNT > 0 )
 
 #include <stdbool.h>
 
@@ -71,7 +70,7 @@
   adcAcqTime256 = _ADC_SINGLECTRL_AT_256CYCLES  /**< 256 clock cycles. */
 } ADC_AcqTime_TypeDef;
 
-
+#if defined( _ADC_CTRL_LPFMODE_MASK )
 /** Lowpass filter mode. */
 typedef enum
 {
@@ -84,7 +83,7 @@
   /** On-chip decoupling capacitor. */
   adcLPFilterDeCap  = _ADC_CTRL_LPFMODE_DECAP
 } ADC_LPFilter_TypeDef;
-
+#endif
 
 /** Oversample rate select. */
 typedef enum
@@ -130,6 +129,7 @@
 /** Peripheral Reflex System signal used to trigger single sample. */
 typedef enum
 {
+#if defined( _ADC_SINGLECTRL_PRSSEL_MASK )
   adcPRSSELCh0 = _ADC_SINGLECTRL_PRSSEL_PRSCH0, /**< PRS channel 0. */
   adcPRSSELCh1 = _ADC_SINGLECTRL_PRSSEL_PRSCH1, /**< PRS channel 1. */
   adcPRSSELCh2 = _ADC_SINGLECTRL_PRSSEL_PRSCH2, /**< PRS channel 2. */
@@ -158,10 +158,34 @@
 #if defined( _ADC_SINGLECTRL_PRSSEL_PRSCH11 )
   adcPRSSELCh11 = _ADC_SINGLECTRL_PRSSEL_PRSCH11, /**< PRS channel 11. */
 #endif
+#elif defined(_ADC_SINGLECTRLX_PRSSEL_MASK)
+  adcPRSSELCh0 = _ADC_SINGLECTRLX_PRSSEL_PRSCH0, /**< PRS channel 0. */
+  adcPRSSELCh1 = _ADC_SINGLECTRLX_PRSSEL_PRSCH1, /**< PRS channel 1. */
+  adcPRSSELCh2 = _ADC_SINGLECTRLX_PRSSEL_PRSCH2, /**< PRS channel 2. */
+  adcPRSSELCh3 = _ADC_SINGLECTRLX_PRSSEL_PRSCH3, /**< PRS channel 3. */
+  adcPRSSELCh4 = _ADC_SINGLECTRLX_PRSSEL_PRSCH4, /**< PRS channel 4. */
+  adcPRSSELCh5 = _ADC_SINGLECTRLX_PRSSEL_PRSCH5, /**< PRS channel 5. */
+  adcPRSSELCh6 = _ADC_SINGLECTRLX_PRSSEL_PRSCH6, /**< PRS channel 6. */
+  adcPRSSELCh7 = _ADC_SINGLECTRLX_PRSSEL_PRSCH7,  /**< PRS channel 7. */
+  adcPRSSELCh8 = _ADC_SINGLECTRLX_PRSSEL_PRSCH8,  /**< PRS channel 8. */
+  adcPRSSELCh9 = _ADC_SINGLECTRLX_PRSSEL_PRSCH9,  /**< PRS channel 9. */
+  adcPRSSELCh10 = _ADC_SINGLECTRLX_PRSSEL_PRSCH10,  /**< PRS channel 10. */
+  adcPRSSELCh11 = _ADC_SINGLECTRLX_PRSSEL_PRSCH11,  /**< PRS channel 11. */
+#if defined( _ADC_SINGLECTRLX_PRSSEL_PRSCH12 )
+  adcPRSSELCh12 = _ADC_SINGLECTRLX_PRSSEL_PRSCH12,  /**< PRS channel 12. */
+  adcPRSSELCh13 = _ADC_SINGLECTRLX_PRSSEL_PRSCH13,  /**< PRS channel 13. */
+  adcPRSSELCh14 = _ADC_SINGLECTRLX_PRSSEL_PRSCH14,  /**< PRS channel 14. */
+  adcPRSSELCh15 = _ADC_SINGLECTRLX_PRSSEL_PRSCH15,  /**< PRS channel 15. */
+#endif
+#endif
 } ADC_PRSSEL_TypeDef;
 
 
-/** Reference to ADC sample. */
+/** Single and scan mode voltage references. Using unshifted enums and or
+    in ADC_CTRLX_VREFSEL_REG to select the extension register CTRLX_VREFSEL. */
+#if defined( _ADC_SCANCTRLX_VREFSEL_MASK )
+#define ADC_CTRLX_VREFSEL_REG     0x80
+#endif
 typedef enum
 {
   /** Internal 1.25V reference. */
@@ -176,14 +200,52 @@
   /** Internal differential 5V reference. */
   adcRef5VDIFF    = _ADC_SINGLECTRL_REF_5VDIFF,
 
-  /** Single ended ext. ref. from pin 6. */
+  /** Single ended external reference from pin 6. */
   adcRefExtSingle = _ADC_SINGLECTRL_REF_EXTSINGLE,
 
-  /** Differential ext. ref. from pin 6 and 7. */
+  /** Differential external reference from pin 6 and 7. */
   adcRef2xExtDiff = _ADC_SINGLECTRL_REF_2XEXTDIFF,
 
   /** Unbuffered 2xVDD. */
-  adcRef2xVDD     = _ADC_SINGLECTRL_REF_2XVDD
+  adcRef2xVDD     = _ADC_SINGLECTRL_REF_2XVDD,
+
+#if defined( _ADC_SINGLECTRLX_VREFSEL_VBGR )
+  /** Custom VFS: Internal Bandgap reference */
+  adcRefVBGR      = _ADC_SINGLECTRLX_VREFSEL_VBGR | ADC_CTRLX_VREFSEL_REG,
+#endif
+
+#if defined( _ADC_SINGLECTRLX_VREFSEL_VDDXWATT )
+  /** Custom VFS: Scaled AVDD: AVDD * VREFATT */
+  adcRefVddxAtt   = _ADC_SINGLECTRLX_VREFSEL_VDDXWATT | ADC_CTRLX_VREFSEL_REG,
+#endif
+
+#if defined( _ADC_SINGLECTRLX_VREFSEL_VREFPWATT )
+  /** Custom VFS: Scaled singled ended external reference from pin 6:
+      VREFP * VREFATT */
+  adcRefVPxAtt    = _ADC_SINGLECTRLX_VREFSEL_VREFPWATT | ADC_CTRLX_VREFSEL_REG,
+#endif
+
+#if defined( _ADC_SINGLECTRLX_VREFSEL_VREFP )
+  /** Custom VFS: Raw single ended external reference from pin 6. */
+  adcRefP         = _ADC_SINGLECTRLX_VREFSEL_VREFP | ADC_CTRLX_VREFSEL_REG,
+#endif
+
+#if defined( _ADC_SINGLECTRLX_VREFSEL_VENTROPY )
+  /** Custom VFS: Special mode for entropy generation */
+  adcRefVEntropy = _ADC_SINGLECTRLX_VREFSEL_VENTROPY | ADC_CTRLX_VREFSEL_REG,
+#endif
+
+#if defined( _ADC_SINGLECTRLX_VREFSEL_VREFPNWATT )
+  /** Custom VFS: Scaled differential external Vref from pin 6 and 7:
+      (VREFP - VREFN) * VREFATT */
+  adcRefVPNxAtt  = _ADC_SINGLECTRLX_VREFSEL_VREFPNWATT | ADC_CTRLX_VREFSEL_REG,
+#endif
+
+#if defined( _ADC_SINGLECTRLX_VREFSEL_VREFPN )
+  /** Custom VFS: Raw differential external Vref from pin 6 and 7:
+      VREFP - VREFN */
+  adcRefPN       = _ADC_SINGLECTRLX_VREFSEL_VREFPN | ADC_CTRLX_VREFSEL_REG,
+#endif
 } ADC_Ref_TypeDef;
 
 
@@ -197,37 +259,446 @@
 } ADC_Res_TypeDef;
 
 
+#if defined( _ADC_SINGLECTRL_INPUTSEL_MASK )
 /** Single sample input selection. */
 typedef enum
 {
   /* Differential mode disabled */
-  adcSingleInpCh0      = _ADC_SINGLECTRL_INPUTSEL_CH0,      /**< Channel 0. */
-  adcSingleInpCh1      = _ADC_SINGLECTRL_INPUTSEL_CH1,      /**< Channel 1. */
-  adcSingleInpCh2      = _ADC_SINGLECTRL_INPUTSEL_CH2,      /**< Channel 2. */
-  adcSingleInpCh3      = _ADC_SINGLECTRL_INPUTSEL_CH3,      /**< Channel 3. */
-  adcSingleInpCh4      = _ADC_SINGLECTRL_INPUTSEL_CH4,      /**< Channel 4. */
-  adcSingleInpCh5      = _ADC_SINGLECTRL_INPUTSEL_CH5,      /**< Channel 5. */
-  adcSingleInpCh6      = _ADC_SINGLECTRL_INPUTSEL_CH6,      /**< Channel 6. */
-  adcSingleInpCh7      = _ADC_SINGLECTRL_INPUTSEL_CH7,      /**< Channel 7. */
-  adcSingleInpTemp     = _ADC_SINGLECTRL_INPUTSEL_TEMP,     /**< Temperature reference. */
-  adcSingleInpVDDDiv3  = _ADC_SINGLECTRL_INPUTSEL_VDDDIV3,  /**< VDD divided by 3. */
-  adcSingleInpVDD      = _ADC_SINGLECTRL_INPUTSEL_VDD,      /**< VDD. */
-  adcSingleInpVSS      = _ADC_SINGLECTRL_INPUTSEL_VSS,      /**< VSS. */
-  adcSingleInpVrefDiv2 = _ADC_SINGLECTRL_INPUTSEL_VREFDIV2, /**< Vref divided by 2. */
-  adcSingleInpDACOut0  = _ADC_SINGLECTRL_INPUTSEL_DAC0OUT0, /**< DAC output 0. */
-  adcSingleInpDACOut1  = _ADC_SINGLECTRL_INPUTSEL_DAC0OUT1, /**< DAC output 1. */
+  adcSingleInputCh0      = _ADC_SINGLECTRL_INPUTSEL_CH0,      /**< Channel 0. */
+  adcSingleInputCh1      = _ADC_SINGLECTRL_INPUTSEL_CH1,      /**< Channel 1. */
+  adcSingleInputCh2      = _ADC_SINGLECTRL_INPUTSEL_CH2,      /**< Channel 2. */
+  adcSingleInputCh3      = _ADC_SINGLECTRL_INPUTSEL_CH3,      /**< Channel 3. */
+  adcSingleInputCh4      = _ADC_SINGLECTRL_INPUTSEL_CH4,      /**< Channel 4. */
+  adcSingleInputCh5      = _ADC_SINGLECTRL_INPUTSEL_CH5,      /**< Channel 5. */
+  adcSingleInputCh6      = _ADC_SINGLECTRL_INPUTSEL_CH6,      /**< Channel 6. */
+  adcSingleInputCh7      = _ADC_SINGLECTRL_INPUTSEL_CH7,      /**< Channel 7. */
+  adcSingleInputTemp     = _ADC_SINGLECTRL_INPUTSEL_TEMP,     /**< Temperature reference. */
+  adcSingleInputVDDDiv3  = _ADC_SINGLECTRL_INPUTSEL_VDDDIV3,  /**< VDD divided by 3. */
+  adcSingleInputVDD      = _ADC_SINGLECTRL_INPUTSEL_VDD,      /**< VDD. */
+  adcSingleInputVSS      = _ADC_SINGLECTRL_INPUTSEL_VSS,      /**< VSS. */
+  adcSingleInputVrefDiv2 = _ADC_SINGLECTRL_INPUTSEL_VREFDIV2, /**< Vref divided by 2. */
+  adcSingleInputDACOut0  = _ADC_SINGLECTRL_INPUTSEL_DAC0OUT0, /**< DAC output 0. */
+  adcSingleInputDACOut1  = _ADC_SINGLECTRL_INPUTSEL_DAC0OUT1, /**< DAC output 1. */
   /* TBD: Use define when available */
-  adcSingleInpATEST    = 15,                                /**< ATEST. */
+  adcSingleInputATEST    = 15,                                /**< ATEST. */
 
   /* Differential mode enabled */
-  adcSingleInpCh0Ch1   = _ADC_SINGLECTRL_INPUTSEL_CH0CH1,   /**< Positive Ch0, negative Ch1. */
-  adcSingleInpCh2Ch3   = _ADC_SINGLECTRL_INPUTSEL_CH2CH3,   /**< Positive Ch2, negative Ch3. */
-  adcSingleInpCh4Ch5   = _ADC_SINGLECTRL_INPUTSEL_CH4CH5,   /**< Positive Ch4, negative Ch5. */
-  adcSingleInpCh6Ch7   = _ADC_SINGLECTRL_INPUTSEL_CH6CH7,   /**< Positive Ch6, negative Ch7. */
+  adcSingleInputCh0Ch1   = _ADC_SINGLECTRL_INPUTSEL_CH0CH1,   /**< Positive Ch0, negative Ch1. */
+  adcSingleInputCh2Ch3   = _ADC_SINGLECTRL_INPUTSEL_CH2CH3,   /**< Positive Ch2, negative Ch3. */
+  adcSingleInputCh4Ch5   = _ADC_SINGLECTRL_INPUTSEL_CH4CH5,   /**< Positive Ch4, negative Ch5. */
+  adcSingleInputCh6Ch7   = _ADC_SINGLECTRL_INPUTSEL_CH6CH7,   /**< Positive Ch6, negative Ch7. */
   /* TBD: Use define when available */
-  adcSingleInpDiff0    = 4                                  /**< Differential 0. */
+  adcSingleInputDiff0    = 4                                  /**< Differential 0. */
 } ADC_SingleInput_TypeDef;
 
+/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
+/* Legacy enum names */
+#define adcSingleInpCh0       adcSingleInputCh0
+#define adcSingleInpCh1       adcSingleInputCh1
+#define adcSingleInpCh2       adcSingleInputCh2
+#define adcSingleInpCh3       adcSingleInputCh3
+#define adcSingleInpCh4       adcSingleInputCh4
+#define adcSingleInpCh5       adcSingleInputCh5
+#define adcSingleInpCh6       adcSingleInputCh6
+#define adcSingleInpCh7       adcSingleInputCh7
+#define adcSingleInpTemp      adcSingleInputTemp
+#define adcSingleInpVDDDiv3   adcSingleInputVDDDiv3
+#define adcSingleInpVDD       adcSingleInputVDD
+#define adcSingleInpVSS       adcSingleInputVSS
+#define adcSingleInpVrefDiv2  adcSingleInputVrefDiv2
+#define adcSingleInpDACOut0   adcSingleInputDACOut0
+#define adcSingleInpDACOut1   adcSingleInputDACOut1
+#define adcSingleInpATEST     adcSingleInputATEST
+#define adcSingleInpCh0Ch1    adcSingleInputCh0Ch1
+#define adcSingleInpCh2Ch3    adcSingleInputCh2Ch3
+#define adcSingleInpCh4Ch5    adcSingleInputCh4Ch5
+#define adcSingleInpCh6Ch7    adcSingleInputCh6Ch7
+#define adcSingleInpDiff0     adcSingleInputDiff0
+/** @endcond */
+#endif
+
+#if defined( _ADC_SINGLECTRL_POSSEL_MASK )
+/** Positive input selection for single and scan coversion. */
+typedef enum
+{
+  adcPosSelAPORT0XCH0  = _ADC_SINGLECTRL_POSSEL_APORT0XCH0,
+  adcPosSelAPORT0XCH1  = _ADC_SINGLECTRL_POSSEL_APORT0XCH1,
+  adcPosSelAPORT0XCH2  = _ADC_SINGLECTRL_POSSEL_APORT0XCH2,
+  adcPosSelAPORT0XCH3  = _ADC_SINGLECTRL_POSSEL_APORT0XCH3,
+  adcPosSelAPORT0XCH4  = _ADC_SINGLECTRL_POSSEL_APORT0XCH4,
+  adcPosSelAPORT0XCH5  = _ADC_SINGLECTRL_POSSEL_APORT0XCH5,
+  adcPosSelAPORT0XCH6  = _ADC_SINGLECTRL_POSSEL_APORT0XCH6,
+  adcPosSelAPORT0XCH7  = _ADC_SINGLECTRL_POSSEL_APORT0XCH7,
+  adcPosSelAPORT0XCH8  = _ADC_SINGLECTRL_POSSEL_APORT0XCH8,
+  adcPosSelAPORT0XCH9  = _ADC_SINGLECTRL_POSSEL_APORT0XCH9,
+  adcPosSelAPORT0XCH10 = _ADC_SINGLECTRL_POSSEL_APORT0XCH10,
+  adcPosSelAPORT0XCH11 = _ADC_SINGLECTRL_POSSEL_APORT0XCH11,
+  adcPosSelAPORT0XCH12 = _ADC_SINGLECTRL_POSSEL_APORT0XCH12,
+  adcPosSelAPORT0XCH13 = _ADC_SINGLECTRL_POSSEL_APORT0XCH13,
+  adcPosSelAPORT0XCH14 = _ADC_SINGLECTRL_POSSEL_APORT0XCH14,
+  adcPosSelAPORT0XCH15 = _ADC_SINGLECTRL_POSSEL_APORT0XCH15,
+  adcPosSelAPORT0YCH0  = _ADC_SINGLECTRL_POSSEL_APORT0YCH0,
+  adcPosSelAPORT0YCH1  = _ADC_SINGLECTRL_POSSEL_APORT0YCH1,
+  adcPosSelAPORT0YCH2  = _ADC_SINGLECTRL_POSSEL_APORT0YCH2,
+  adcPosSelAPORT0YCH3  = _ADC_SINGLECTRL_POSSEL_APORT0YCH3,
+  adcPosSelAPORT0YCH4  = _ADC_SINGLECTRL_POSSEL_APORT0YCH4,
+  adcPosSelAPORT0YCH5  = _ADC_SINGLECTRL_POSSEL_APORT0YCH5,
+  adcPosSelAPORT0YCH6  = _ADC_SINGLECTRL_POSSEL_APORT0YCH6,
+  adcPosSelAPORT0YCH7  = _ADC_SINGLECTRL_POSSEL_APORT0YCH7,
+  adcPosSelAPORT0YCH8  = _ADC_SINGLECTRL_POSSEL_APORT0YCH8,
+  adcPosSelAPORT0YCH9  = _ADC_SINGLECTRL_POSSEL_APORT0YCH9,
+  adcPosSelAPORT0YCH10 = _ADC_SINGLECTRL_POSSEL_APORT0YCH10,
+  adcPosSelAPORT0YCH11 = _ADC_SINGLECTRL_POSSEL_APORT0YCH11,
+  adcPosSelAPORT0YCH12 = _ADC_SINGLECTRL_POSSEL_APORT0YCH12,
+  adcPosSelAPORT0YCH13 = _ADC_SINGLECTRL_POSSEL_APORT0YCH13,
+  adcPosSelAPORT0YCH14 = _ADC_SINGLECTRL_POSSEL_APORT0YCH14,
+  adcPosSelAPORT0YCH15 = _ADC_SINGLECTRL_POSSEL_APORT0YCH15,
+  adcPosSelAPORT1XCH0  = _ADC_SINGLECTRL_POSSEL_APORT1XCH0,
+  adcPosSelAPORT1YCH1  = _ADC_SINGLECTRL_POSSEL_APORT1YCH1,
+  adcPosSelAPORT1XCH2  = _ADC_SINGLECTRL_POSSEL_APORT1XCH2,
+  adcPosSelAPORT1YCH3  = _ADC_SINGLECTRL_POSSEL_APORT1YCH3,
+  adcPosSelAPORT1XCH4  = _ADC_SINGLECTRL_POSSEL_APORT1XCH4,
+  adcPosSelAPORT1YCH5  = _ADC_SINGLECTRL_POSSEL_APORT1YCH5,
+  adcPosSelAPORT1XCH6  = _ADC_SINGLECTRL_POSSEL_APORT1XCH6,
+  adcPosSelAPORT1YCH7  = _ADC_SINGLECTRL_POSSEL_APORT1YCH7,
+  adcPosSelAPORT1XCH8  = _ADC_SINGLECTRL_POSSEL_APORT1XCH8,
+  adcPosSelAPORT1YCH9  = _ADC_SINGLECTRL_POSSEL_APORT1YCH9,
+  adcPosSelAPORT1XCH10 = _ADC_SINGLECTRL_POSSEL_APORT1XCH10,
+  adcPosSelAPORT1YCH11 = _ADC_SINGLECTRL_POSSEL_APORT1YCH11,
+  adcPosSelAPORT1XCH12 = _ADC_SINGLECTRL_POSSEL_APORT1XCH12,
+  adcPosSelAPORT1YCH13 = _ADC_SINGLECTRL_POSSEL_APORT1YCH13,
+  adcPosSelAPORT1XCH14 = _ADC_SINGLECTRL_POSSEL_APORT1XCH14,
+  adcPosSelAPORT1YCH15 = _ADC_SINGLECTRL_POSSEL_APORT1YCH15,
+  adcPosSelAPORT1XCH16 = _ADC_SINGLECTRL_POSSEL_APORT1XCH16,
+  adcPosSelAPORT1YCH17 = _ADC_SINGLECTRL_POSSEL_APORT1YCH17,
+  adcPosSelAPORT1XCH18 = _ADC_SINGLECTRL_POSSEL_APORT1XCH18,
+  adcPosSelAPORT1YCH19 = _ADC_SINGLECTRL_POSSEL_APORT1YCH19,
+  adcPosSelAPORT1XCH20 = _ADC_SINGLECTRL_POSSEL_APORT1XCH20,
+  adcPosSelAPORT1YCH21 = _ADC_SINGLECTRL_POSSEL_APORT1YCH21,
+  adcPosSelAPORT1XCH22 = _ADC_SINGLECTRL_POSSEL_APORT1XCH22,
+  adcPosSelAPORT1YCH23 = _ADC_SINGLECTRL_POSSEL_APORT1YCH23,
+  adcPosSelAPORT1XCH24 = _ADC_SINGLECTRL_POSSEL_APORT1XCH24,
+  adcPosSelAPORT1YCH25 = _ADC_SINGLECTRL_POSSEL_APORT1YCH25,
+  adcPosSelAPORT1XCH26 = _ADC_SINGLECTRL_POSSEL_APORT1XCH26,
+  adcPosSelAPORT1YCH27 = _ADC_SINGLECTRL_POSSEL_APORT1YCH27,
+  adcPosSelAPORT1XCH28 = _ADC_SINGLECTRL_POSSEL_APORT1XCH28,
+  adcPosSelAPORT1YCH29 = _ADC_SINGLECTRL_POSSEL_APORT1YCH29,
+  adcPosSelAPORT1XCH30 = _ADC_SINGLECTRL_POSSEL_APORT1XCH30,
+  adcPosSelAPORT1YCH31 = _ADC_SINGLECTRL_POSSEL_APORT1YCH31,
+  adcPosSelAPORT2YCH0  = _ADC_SINGLECTRL_POSSEL_APORT2YCH0,
+  adcPosSelAPORT2XCH1  = _ADC_SINGLECTRL_POSSEL_APORT2XCH1,
+  adcPosSelAPORT2YCH2  = _ADC_SINGLECTRL_POSSEL_APORT2YCH2,
+  adcPosSelAPORT2XCH3  = _ADC_SINGLECTRL_POSSEL_APORT2XCH3,
+  adcPosSelAPORT2YCH4  = _ADC_SINGLECTRL_POSSEL_APORT2YCH4,
+  adcPosSelAPORT2XCH5  = _ADC_SINGLECTRL_POSSEL_APORT2XCH5,
+  adcPosSelAPORT2YCH6  = _ADC_SINGLECTRL_POSSEL_APORT2YCH6,
+  adcPosSelAPORT2XCH7  = _ADC_SINGLECTRL_POSSEL_APORT2XCH7,
+  adcPosSelAPORT2YCH8  = _ADC_SINGLECTRL_POSSEL_APORT2YCH8,
+  adcPosSelAPORT2XCH9  = _ADC_SINGLECTRL_POSSEL_APORT2XCH9,
+  adcPosSelAPORT2YCH10 = _ADC_SINGLECTRL_POSSEL_APORT2YCH10,
+  adcPosSelAPORT2XCH11 = _ADC_SINGLECTRL_POSSEL_APORT2XCH11,
+  adcPosSelAPORT2YCH12 = _ADC_SINGLECTRL_POSSEL_APORT2YCH12,
+  adcPosSelAPORT2XCH13 = _ADC_SINGLECTRL_POSSEL_APORT2XCH13,
+  adcPosSelAPORT2YCH14 = _ADC_SINGLECTRL_POSSEL_APORT2YCH14,
+  adcPosSelAPORT2XCH15 = _ADC_SINGLECTRL_POSSEL_APORT2XCH15,
+  adcPosSelAPORT2YCH16 = _ADC_SINGLECTRL_POSSEL_APORT2YCH16,
+  adcPosSelAPORT2XCH17 = _ADC_SINGLECTRL_POSSEL_APORT2XCH17,
+  adcPosSelAPORT2YCH18 = _ADC_SINGLECTRL_POSSEL_APORT2YCH18,
+  adcPosSelAPORT2XCH19 = _ADC_SINGLECTRL_POSSEL_APORT2XCH19,
+  adcPosSelAPORT2YCH20 = _ADC_SINGLECTRL_POSSEL_APORT2YCH20,
+  adcPosSelAPORT2XCH21 = _ADC_SINGLECTRL_POSSEL_APORT2XCH21,
+  adcPosSelAPORT2YCH22 = _ADC_SINGLECTRL_POSSEL_APORT2YCH22,
+  adcPosSelAPORT2XCH23 = _ADC_SINGLECTRL_POSSEL_APORT2XCH23,
+  adcPosSelAPORT2YCH24 = _ADC_SINGLECTRL_POSSEL_APORT2YCH24,
+  adcPosSelAPORT2XCH25 = _ADC_SINGLECTRL_POSSEL_APORT2XCH25,
+  adcPosSelAPORT2YCH26 = _ADC_SINGLECTRL_POSSEL_APORT2YCH26,
+  adcPosSelAPORT2XCH27 = _ADC_SINGLECTRL_POSSEL_APORT2XCH27,
+  adcPosSelAPORT2YCH28 = _ADC_SINGLECTRL_POSSEL_APORT2YCH28,
+  adcPosSelAPORT2XCH29 = _ADC_SINGLECTRL_POSSEL_APORT2XCH29,
+  adcPosSelAPORT2YCH30 = _ADC_SINGLECTRL_POSSEL_APORT2YCH30,
+  adcPosSelAPORT2XCH31 = _ADC_SINGLECTRL_POSSEL_APORT2XCH31,
+  adcPosSelAPORT3XCH0  = _ADC_SINGLECTRL_POSSEL_APORT3XCH0,
+  adcPosSelAPORT3YCH1  = _ADC_SINGLECTRL_POSSEL_APORT3YCH1,
+  adcPosSelAPORT3XCH2  = _ADC_SINGLECTRL_POSSEL_APORT3XCH2,
+  adcPosSelAPORT3YCH3  = _ADC_SINGLECTRL_POSSEL_APORT3YCH3,
+  adcPosSelAPORT3XCH4  = _ADC_SINGLECTRL_POSSEL_APORT3XCH4,
+  adcPosSelAPORT3YCH5  = _ADC_SINGLECTRL_POSSEL_APORT3YCH5,
+  adcPosSelAPORT3XCH6  = _ADC_SINGLECTRL_POSSEL_APORT3XCH6,
+  adcPosSelAPORT3YCH7  = _ADC_SINGLECTRL_POSSEL_APORT3YCH7,
+  adcPosSelAPORT3XCH8  = _ADC_SINGLECTRL_POSSEL_APORT3XCH8,
+  adcPosSelAPORT3YCH9  = _ADC_SINGLECTRL_POSSEL_APORT3YCH9,
+  adcPosSelAPORT3XCH10 = _ADC_SINGLECTRL_POSSEL_APORT3XCH10,
+  adcPosSelAPORT3YCH11 = _ADC_SINGLECTRL_POSSEL_APORT3YCH11,
+  adcPosSelAPORT3XCH12 = _ADC_SINGLECTRL_POSSEL_APORT3XCH12,
+  adcPosSelAPORT3YCH13 = _ADC_SINGLECTRL_POSSEL_APORT3YCH13,
+  adcPosSelAPORT3XCH14 = _ADC_SINGLECTRL_POSSEL_APORT3XCH14,
+  adcPosSelAPORT3YCH15 = _ADC_SINGLECTRL_POSSEL_APORT3YCH15,
+  adcPosSelAPORT3XCH16 = _ADC_SINGLECTRL_POSSEL_APORT3XCH16,
+  adcPosSelAPORT3YCH17 = _ADC_SINGLECTRL_POSSEL_APORT3YCH17,
+  adcPosSelAPORT3XCH18 = _ADC_SINGLECTRL_POSSEL_APORT3XCH18,
+  adcPosSelAPORT3YCH19 = _ADC_SINGLECTRL_POSSEL_APORT3YCH19,
+  adcPosSelAPORT3XCH20 = _ADC_SINGLECTRL_POSSEL_APORT3XCH20,
+  adcPosSelAPORT3YCH21 = _ADC_SINGLECTRL_POSSEL_APORT3YCH21,
+  adcPosSelAPORT3XCH22 = _ADC_SINGLECTRL_POSSEL_APORT3XCH22,
+  adcPosSelAPORT3YCH23 = _ADC_SINGLECTRL_POSSEL_APORT3YCH23,
+  adcPosSelAPORT3XCH24 = _ADC_SINGLECTRL_POSSEL_APORT3XCH24,
+  adcPosSelAPORT3YCH25 = _ADC_SINGLECTRL_POSSEL_APORT3YCH25,
+  adcPosSelAPORT3XCH26 = _ADC_SINGLECTRL_POSSEL_APORT3XCH26,
+  adcPosSelAPORT3YCH27 = _ADC_SINGLECTRL_POSSEL_APORT3YCH27,
+  adcPosSelAPORT3XCH28 = _ADC_SINGLECTRL_POSSEL_APORT3XCH28,
+  adcPosSelAPORT3YCH29 = _ADC_SINGLECTRL_POSSEL_APORT3YCH29,
+  adcPosSelAPORT3XCH30 = _ADC_SINGLECTRL_POSSEL_APORT3XCH30,
+  adcPosSelAPORT3YCH31 = _ADC_SINGLECTRL_POSSEL_APORT3YCH31,
+  adcPosSelAPORT4YCH0  = _ADC_SINGLECTRL_POSSEL_APORT4YCH0,
+  adcPosSelAPORT4XCH1  = _ADC_SINGLECTRL_POSSEL_APORT4XCH1,
+  adcPosSelAPORT4YCH2  = _ADC_SINGLECTRL_POSSEL_APORT4YCH2,
+  adcPosSelAPORT4XCH3  = _ADC_SINGLECTRL_POSSEL_APORT4XCH3,
+  adcPosSelAPORT4YCH4  = _ADC_SINGLECTRL_POSSEL_APORT4YCH4,
+  adcPosSelAPORT4XCH5  = _ADC_SINGLECTRL_POSSEL_APORT4XCH5,
+  adcPosSelAPORT4YCH6  = _ADC_SINGLECTRL_POSSEL_APORT4YCH6,
+  adcPosSelAPORT4XCH7  = _ADC_SINGLECTRL_POSSEL_APORT4XCH7,
+  adcPosSelAPORT4YCH8  = _ADC_SINGLECTRL_POSSEL_APORT4YCH8,
+  adcPosSelAPORT4XCH9  = _ADC_SINGLECTRL_POSSEL_APORT4XCH9,
+  adcPosSelAPORT4YCH10 = _ADC_SINGLECTRL_POSSEL_APORT4YCH10,
+  adcPosSelAPORT4XCH11 = _ADC_SINGLECTRL_POSSEL_APORT4XCH11,
+  adcPosSelAPORT4YCH12 = _ADC_SINGLECTRL_POSSEL_APORT4YCH12,
+  adcPosSelAPORT4XCH13 = _ADC_SINGLECTRL_POSSEL_APORT4XCH13,
+  adcPosSelAPORT4YCH14 = _ADC_SINGLECTRL_POSSEL_APORT4YCH14,
+  adcPosSelAPORT4XCH15 = _ADC_SINGLECTRL_POSSEL_APORT4XCH15,
+  adcPosSelAPORT4YCH16 = _ADC_SINGLECTRL_POSSEL_APORT4YCH16,
+  adcPosSelAPORT4XCH17 = _ADC_SINGLECTRL_POSSEL_APORT4XCH17,
+  adcPosSelAPORT4YCH18 = _ADC_SINGLECTRL_POSSEL_APORT4YCH18,
+  adcPosSelAPORT4XCH19 = _ADC_SINGLECTRL_POSSEL_APORT4XCH19,
+  adcPosSelAPORT4YCH20 = _ADC_SINGLECTRL_POSSEL_APORT4YCH20,
+  adcPosSelAPORT4XCH21 = _ADC_SINGLECTRL_POSSEL_APORT4XCH21,
+  adcPosSelAPORT4YCH22 = _ADC_SINGLECTRL_POSSEL_APORT4YCH22,
+  adcPosSelAPORT4XCH23 = _ADC_SINGLECTRL_POSSEL_APORT4XCH23,
+  adcPosSelAPORT4YCH24 = _ADC_SINGLECTRL_POSSEL_APORT4YCH24,
+  adcPosSelAPORT4XCH25 = _ADC_SINGLECTRL_POSSEL_APORT4XCH25,
+  adcPosSelAPORT4YCH26 = _ADC_SINGLECTRL_POSSEL_APORT4YCH26,
+  adcPosSelAPORT4XCH27 = _ADC_SINGLECTRL_POSSEL_APORT4XCH27,
+  adcPosSelAPORT4YCH28 = _ADC_SINGLECTRL_POSSEL_APORT4YCH28,
+  adcPosSelAPORT4XCH29 = _ADC_SINGLECTRL_POSSEL_APORT4XCH29,
+  adcPosSelAPORT4YCH30 = _ADC_SINGLECTRL_POSSEL_APORT4YCH30,
+  adcPosSelAPORT4XCH31 = _ADC_SINGLECTRL_POSSEL_APORT4XCH31,
+  adcPosSelAVDD        = _ADC_SINGLECTRL_POSSEL_AVDD,
+  adcPosSelBU          = _ADC_SINGLECTRL_POSSEL_BU,
+  adcPosSelAREG        = _ADC_SINGLECTRL_POSSEL_AREG,
+  adcPosSelVREGOUTPA   = _ADC_SINGLECTRL_POSSEL_VREGOUTPA,
+  adcPosSelPDBU        = _ADC_SINGLECTRL_POSSEL_PDBU,
+  adcPosSelIO0         = _ADC_SINGLECTRL_POSSEL_IO0,
+  adcPosSelIO1         = _ADC_SINGLECTRL_POSSEL_IO1,
+  adcPosSelVSP         = _ADC_SINGLECTRL_POSSEL_VSP,
+  adcPosSelSP0         = _ADC_SINGLECTRL_POSSEL_SP0,
+  adcPosSelTEMP        = _ADC_SINGLECTRL_POSSEL_TEMP,
+  adcPosSelDAC0OUT0    = _ADC_SINGLECTRL_POSSEL_DAC0OUT0,
+  adcPosSelTESTP       = _ADC_SINGLECTRL_POSSEL_TESTP,
+  adcPosSelSP1         = _ADC_SINGLECTRL_POSSEL_SP1,
+  adcPosSelSP2         = _ADC_SINGLECTRL_POSSEL_SP2,
+  adcPosSelDAC0OUT1    = _ADC_SINGLECTRL_POSSEL_DAC0OUT1,
+  adcPosSelSUBLSB      = _ADC_SINGLECTRL_POSSEL_SUBLSB,
+  adcPosSelDEFAULT     = _ADC_SINGLECTRL_POSSEL_DEFAULT,
+  adcPosSelVSS         = _ADC_SINGLECTRL_POSSEL_VSS
+} ADC_PosSel_TypeDef;
+#endif
+
+
+#if defined( _ADC_SINGLECTRL_NEGSEL_MASK )
+/** Negative input selection for single and scan coversion. */
+typedef enum
+{
+  adcNegSelAPORT0XCH0  = _ADC_SINGLECTRL_NEGSEL_APORT0XCH0,
+  adcNegSelAPORT0XCH1  = _ADC_SINGLECTRL_NEGSEL_APORT0XCH1,
+  adcNegSelAPORT0XCH2  = _ADC_SINGLECTRL_NEGSEL_APORT0XCH2,
+  adcNegSelAPORT0XCH3  = _ADC_SINGLECTRL_NEGSEL_APORT0XCH3,
+  adcNegSelAPORT0XCH4  = _ADC_SINGLECTRL_NEGSEL_APORT0XCH4,
+  adcNegSelAPORT0XCH5  = _ADC_SINGLECTRL_NEGSEL_APORT0XCH5,
+  adcNegSelAPORT0XCH6  = _ADC_SINGLECTRL_NEGSEL_APORT0XCH6,
+  adcNegSelAPORT0XCH7  = _ADC_SINGLECTRL_NEGSEL_APORT0XCH7,
+  adcNegSelAPORT0XCH8  = _ADC_SINGLECTRL_NEGSEL_APORT0XCH8,
+  adcNegSelAPORT0XCH9  = _ADC_SINGLECTRL_NEGSEL_APORT0XCH9,
+  adcNegSelAPORT0XCH10 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH10,
+  adcNegSelAPORT0XCH11 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH11,
+  adcNegSelAPORT0XCH12 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH12,
+  adcNegSelAPORT0XCH13 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH13,
+  adcNegSelAPORT0XCH14 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH14,
+  adcNegSelAPORT0XCH15 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH15,
+  adcNegSelAPORT0YCH0  = _ADC_SINGLECTRL_NEGSEL_APORT0YCH0,
+  adcNegSelAPORT0YCH1  = _ADC_SINGLECTRL_NEGSEL_APORT0YCH1,
+  adcNegSelAPORT0YCH2  = _ADC_SINGLECTRL_NEGSEL_APORT0YCH2,
+  adcNegSelAPORT0YCH3  = _ADC_SINGLECTRL_NEGSEL_APORT0YCH3,
+  adcNegSelAPORT0YCH4  = _ADC_SINGLECTRL_NEGSEL_APORT0YCH4,
+  adcNegSelAPORT0YCH5  = _ADC_SINGLECTRL_NEGSEL_APORT0YCH5,
+  adcNegSelAPORT0YCH6  = _ADC_SINGLECTRL_NEGSEL_APORT0YCH6,
+  adcNegSelAPORT0YCH7  = _ADC_SINGLECTRL_NEGSEL_APORT0YCH7,
+  adcNegSelAPORT0YCH8  = _ADC_SINGLECTRL_NEGSEL_APORT0YCH8,
+  adcNegSelAPORT0YCH9  = _ADC_SINGLECTRL_NEGSEL_APORT0YCH9,
+  adcNegSelAPORT0YCH10 = _ADC_SINGLECTRL_NEGSEL_APORT0YCH10,
+  adcNegSelAPORT0YCH11 = _ADC_SINGLECTRL_NEGSEL_APORT0YCH11,
+  adcNegSelAPORT0YCH12 = _ADC_SINGLECTRL_NEGSEL_APORT0YCH12,
+  adcNegSelAPORT0YCH13 = _ADC_SINGLECTRL_NEGSEL_APORT0YCH13,
+  adcNegSelAPORT0YCH14 = _ADC_SINGLECTRL_NEGSEL_APORT0YCH14,
+  adcNegSelAPORT0YCH15 = _ADC_SINGLECTRL_NEGSEL_APORT0YCH15,
+  adcNegSelAPORT1XCH0  = _ADC_SINGLECTRL_NEGSEL_APORT1XCH0,
+  adcNegSelAPORT1YCH1  = _ADC_SINGLECTRL_NEGSEL_APORT1YCH1,
+  adcNegSelAPORT1XCH2  = _ADC_SINGLECTRL_NEGSEL_APORT1XCH2,
+  adcNegSelAPORT1YCH3  = _ADC_SINGLECTRL_NEGSEL_APORT1YCH3,
+  adcNegSelAPORT1XCH4  = _ADC_SINGLECTRL_NEGSEL_APORT1XCH4,
+  adcNegSelAPORT1YCH5  = _ADC_SINGLECTRL_NEGSEL_APORT1YCH5,
+  adcNegSelAPORT1XCH6  = _ADC_SINGLECTRL_NEGSEL_APORT1XCH6,
+  adcNegSelAPORT1YCH7  = _ADC_SINGLECTRL_NEGSEL_APORT1YCH7,
+  adcNegSelAPORT1XCH8  = _ADC_SINGLECTRL_NEGSEL_APORT1XCH8,
+  adcNegSelAPORT1YCH9  = _ADC_SINGLECTRL_NEGSEL_APORT1YCH9,
+  adcNegSelAPORT1XCH10 = _ADC_SINGLECTRL_NEGSEL_APORT1XCH10,
+  adcNegSelAPORT1YCH11 = _ADC_SINGLECTRL_NEGSEL_APORT1YCH11,
+  adcNegSelAPORT1XCH12 = _ADC_SINGLECTRL_NEGSEL_APORT1XCH12,
+  adcNegSelAPORT1YCH13 = _ADC_SINGLECTRL_NEGSEL_APORT1YCH13,
+  adcNegSelAPORT1XCH14 = _ADC_SINGLECTRL_NEGSEL_APORT1XCH14,
+  adcNegSelAPORT1YCH15 = _ADC_SINGLECTRL_NEGSEL_APORT1YCH15,
+  adcNegSelAPORT1XCH16 = _ADC_SINGLECTRL_NEGSEL_APORT1XCH16,
+  adcNegSelAPORT1YCH17 = _ADC_SINGLECTRL_NEGSEL_APORT1YCH17,
+  adcNegSelAPORT1XCH18 = _ADC_SINGLECTRL_NEGSEL_APORT1XCH18,
+  adcNegSelAPORT1YCH19 = _ADC_SINGLECTRL_NEGSEL_APORT1YCH19,
+  adcNegSelAPORT1XCH20 = _ADC_SINGLECTRL_NEGSEL_APORT1XCH20,
+  adcNegSelAPORT1YCH21 = _ADC_SINGLECTRL_NEGSEL_APORT1YCH21,
+  adcNegSelAPORT1XCH22 = _ADC_SINGLECTRL_NEGSEL_APORT1XCH22,
+  adcNegSelAPORT1YCH23 = _ADC_SINGLECTRL_NEGSEL_APORT1YCH23,
+  adcNegSelAPORT1XCH24 = _ADC_SINGLECTRL_NEGSEL_APORT1XCH24,
+  adcNegSelAPORT1YCH25 = _ADC_SINGLECTRL_NEGSEL_APORT1YCH25,
+  adcNegSelAPORT1XCH26 = _ADC_SINGLECTRL_NEGSEL_APORT1XCH26,
+  adcNegSelAPORT1YCH27 = _ADC_SINGLECTRL_NEGSEL_APORT1YCH27,
+  adcNegSelAPORT1XCH28 = _ADC_SINGLECTRL_NEGSEL_APORT1XCH28,
+  adcNegSelAPORT1YCH29 = _ADC_SINGLECTRL_NEGSEL_APORT1YCH29,
+  adcNegSelAPORT1XCH30 = _ADC_SINGLECTRL_NEGSEL_APORT1XCH30,
+  adcNegSelAPORT1YCH31 = _ADC_SINGLECTRL_NEGSEL_APORT1YCH31,
+  adcNegSelAPORT2YCH0  = _ADC_SINGLECTRL_NEGSEL_APORT2YCH0,
+  adcNegSelAPORT2XCH1  = _ADC_SINGLECTRL_NEGSEL_APORT2XCH1,
+  adcNegSelAPORT2YCH2  = _ADC_SINGLECTRL_NEGSEL_APORT2YCH2,
+  adcNegSelAPORT2XCH3  = _ADC_SINGLECTRL_NEGSEL_APORT2XCH3,
+  adcNegSelAPORT2YCH4  = _ADC_SINGLECTRL_NEGSEL_APORT2YCH4,
+  adcNegSelAPORT2XCH5  = _ADC_SINGLECTRL_NEGSEL_APORT2XCH5,
+  adcNegSelAPORT2YCH6  = _ADC_SINGLECTRL_NEGSEL_APORT2YCH6,
+  adcNegSelAPORT2XCH7  = _ADC_SINGLECTRL_NEGSEL_APORT2XCH7,
+  adcNegSelAPORT2YCH8  = _ADC_SINGLECTRL_NEGSEL_APORT2YCH8,
+  adcNegSelAPORT2XCH9  = _ADC_SINGLECTRL_NEGSEL_APORT2XCH9,
+  adcNegSelAPORT2YCH10 = _ADC_SINGLECTRL_NEGSEL_APORT2YCH10,
+  adcNegSelAPORT2XCH11 = _ADC_SINGLECTRL_NEGSEL_APORT2XCH11,
+  adcNegSelAPORT2YCH12 = _ADC_SINGLECTRL_NEGSEL_APORT2YCH12,
+  adcNegSelAPORT2XCH13 = _ADC_SINGLECTRL_NEGSEL_APORT2XCH13,
+  adcNegSelAPORT2YCH14 = _ADC_SINGLECTRL_NEGSEL_APORT2YCH14,
+  adcNegSelAPORT2XCH15 = _ADC_SINGLECTRL_NEGSEL_APORT2XCH15,
+  adcNegSelAPORT2YCH16 = _ADC_SINGLECTRL_NEGSEL_APORT2YCH16,
+  adcNegSelAPORT2XCH17 = _ADC_SINGLECTRL_NEGSEL_APORT2XCH17,
+  adcNegSelAPORT2YCH18 = _ADC_SINGLECTRL_NEGSEL_APORT2YCH18,
+  adcNegSelAPORT2XCH19 = _ADC_SINGLECTRL_NEGSEL_APORT2XCH19,
+  adcNegSelAPORT2YCH20 = _ADC_SINGLECTRL_NEGSEL_APORT2YCH20,
+  adcNegSelAPORT2XCH21 = _ADC_SINGLECTRL_NEGSEL_APORT2XCH21,
+  adcNegSelAPORT2YCH22 = _ADC_SINGLECTRL_NEGSEL_APORT2YCH22,
+  adcNegSelAPORT2XCH23 = _ADC_SINGLECTRL_NEGSEL_APORT2XCH23,
+  adcNegSelAPORT2YCH24 = _ADC_SINGLECTRL_NEGSEL_APORT2YCH24,
+  adcNegSelAPORT2XCH25 = _ADC_SINGLECTRL_NEGSEL_APORT2XCH25,
+  adcNegSelAPORT2YCH26 = _ADC_SINGLECTRL_NEGSEL_APORT2YCH26,
+  adcNegSelAPORT2XCH27 = _ADC_SINGLECTRL_NEGSEL_APORT2XCH27,
+  adcNegSelAPORT2YCH28 = _ADC_SINGLECTRL_NEGSEL_APORT2YCH28,
+  adcNegSelAPORT2XCH29 = _ADC_SINGLECTRL_NEGSEL_APORT2XCH29,
+  adcNegSelAPORT2YCH30 = _ADC_SINGLECTRL_NEGSEL_APORT2YCH30,
+  adcNegSelAPORT2XCH31 = _ADC_SINGLECTRL_NEGSEL_APORT2XCH31,
+  adcNegSelAPORT3XCH0  = _ADC_SINGLECTRL_NEGSEL_APORT3XCH0,
+  adcNegSelAPORT3YCH1  = _ADC_SINGLECTRL_NEGSEL_APORT3YCH1,
+  adcNegSelAPORT3XCH2  = _ADC_SINGLECTRL_NEGSEL_APORT3XCH2,
+  adcNegSelAPORT3YCH3  = _ADC_SINGLECTRL_NEGSEL_APORT3YCH3,
+  adcNegSelAPORT3XCH4  = _ADC_SINGLECTRL_NEGSEL_APORT3XCH4,
+  adcNegSelAPORT3YCH5  = _ADC_SINGLECTRL_NEGSEL_APORT3YCH5,
+  adcNegSelAPORT3XCH6  = _ADC_SINGLECTRL_NEGSEL_APORT3XCH6,
+  adcNegSelAPORT3YCH7  = _ADC_SINGLECTRL_NEGSEL_APORT3YCH7,
+  adcNegSelAPORT3XCH8  = _ADC_SINGLECTRL_NEGSEL_APORT3XCH8,
+  adcNegSelAPORT3YCH9  = _ADC_SINGLECTRL_NEGSEL_APORT3YCH9,
+  adcNegSelAPORT3XCH10 = _ADC_SINGLECTRL_NEGSEL_APORT3XCH10,
+  adcNegSelAPORT3YCH11 = _ADC_SINGLECTRL_NEGSEL_APORT3YCH11,
+  adcNegSelAPORT3XCH12 = _ADC_SINGLECTRL_NEGSEL_APORT3XCH12,
+  adcNegSelAPORT3YCH13 = _ADC_SINGLECTRL_NEGSEL_APORT3YCH13,
+  adcNegSelAPORT3XCH14 = _ADC_SINGLECTRL_NEGSEL_APORT3XCH14,
+  adcNegSelAPORT3YCH15 = _ADC_SINGLECTRL_NEGSEL_APORT3YCH15,
+  adcNegSelAPORT3XCH16 = _ADC_SINGLECTRL_NEGSEL_APORT3XCH16,
+  adcNegSelAPORT3YCH17 = _ADC_SINGLECTRL_NEGSEL_APORT3YCH17,
+  adcNegSelAPORT3XCH18 = _ADC_SINGLECTRL_NEGSEL_APORT3XCH18,
+  adcNegSelAPORT3YCH19 = _ADC_SINGLECTRL_NEGSEL_APORT3YCH19,
+  adcNegSelAPORT3XCH20 = _ADC_SINGLECTRL_NEGSEL_APORT3XCH20,
+  adcNegSelAPORT3YCH21 = _ADC_SINGLECTRL_NEGSEL_APORT3YCH21,
+  adcNegSelAPORT3XCH22 = _ADC_SINGLECTRL_NEGSEL_APORT3XCH22,
+  adcNegSelAPORT3YCH23 = _ADC_SINGLECTRL_NEGSEL_APORT3YCH23,
+  adcNegSelAPORT3XCH24 = _ADC_SINGLECTRL_NEGSEL_APORT3XCH24,
+  adcNegSelAPORT3YCH25 = _ADC_SINGLECTRL_NEGSEL_APORT3YCH25,
+  adcNegSelAPORT3XCH26 = _ADC_SINGLECTRL_NEGSEL_APORT3XCH26,
+  adcNegSelAPORT3YCH27 = _ADC_SINGLECTRL_NEGSEL_APORT3YCH27,
+  adcNegSelAPORT3XCH28 = _ADC_SINGLECTRL_NEGSEL_APORT3XCH28,
+  adcNegSelAPORT3YCH29 = _ADC_SINGLECTRL_NEGSEL_APORT3YCH29,
+  adcNegSelAPORT3XCH30 = _ADC_SINGLECTRL_NEGSEL_APORT3XCH30,
+  adcNegSelAPORT3YCH31 = _ADC_SINGLECTRL_NEGSEL_APORT3YCH31,
+  adcNegSelAPORT4YCH0  = _ADC_SINGLECTRL_NEGSEL_APORT4YCH0,
+  adcNegSelAPORT4XCH1  = _ADC_SINGLECTRL_NEGSEL_APORT4XCH1,
+  adcNegSelAPORT4YCH2  = _ADC_SINGLECTRL_NEGSEL_APORT4YCH2,
+  adcNegSelAPORT4XCH3  = _ADC_SINGLECTRL_NEGSEL_APORT4XCH3,
+  adcNegSelAPORT4YCH4  = _ADC_SINGLECTRL_NEGSEL_APORT4YCH4,
+  adcNegSelAPORT4XCH5  = _ADC_SINGLECTRL_NEGSEL_APORT4XCH5,
+  adcNegSelAPORT4YCH6  = _ADC_SINGLECTRL_NEGSEL_APORT4YCH6,
+  adcNegSelAPORT4XCH7  = _ADC_SINGLECTRL_NEGSEL_APORT4XCH7,
+  adcNegSelAPORT4YCH8  = _ADC_SINGLECTRL_NEGSEL_APORT4YCH8,
+  adcNegSelAPORT4XCH9  = _ADC_SINGLECTRL_NEGSEL_APORT4XCH9,
+  adcNegSelAPORT4YCH10 = _ADC_SINGLECTRL_NEGSEL_APORT4YCH10,
+  adcNegSelAPORT4XCH11 = _ADC_SINGLECTRL_NEGSEL_APORT4XCH11,
+  adcNegSelAPORT4YCH12 = _ADC_SINGLECTRL_NEGSEL_APORT4YCH12,
+  adcNegSelAPORT4XCH13 = _ADC_SINGLECTRL_NEGSEL_APORT4XCH13,
+  adcNegSelAPORT4YCH14 = _ADC_SINGLECTRL_NEGSEL_APORT4YCH14,
+  adcNegSelAPORT4XCH15 = _ADC_SINGLECTRL_NEGSEL_APORT4XCH15,
+  adcNegSelAPORT4YCH16 = _ADC_SINGLECTRL_NEGSEL_APORT4YCH16,
+  adcNegSelAPORT4XCH17 = _ADC_SINGLECTRL_NEGSEL_APORT4XCH17,
+  adcNegSelAPORT4YCH18 = _ADC_SINGLECTRL_NEGSEL_APORT4YCH18,
+  adcNegSelAPORT4XCH19 = _ADC_SINGLECTRL_NEGSEL_APORT4XCH19,
+  adcNegSelAPORT4YCH20 = _ADC_SINGLECTRL_NEGSEL_APORT4YCH20,
+  adcNegSelAPORT4XCH21 = _ADC_SINGLECTRL_NEGSEL_APORT4XCH21,
+  adcNegSelAPORT4YCH22 = _ADC_SINGLECTRL_NEGSEL_APORT4YCH22,
+  adcNegSelAPORT4XCH23 = _ADC_SINGLECTRL_NEGSEL_APORT4XCH23,
+  adcNegSelAPORT4YCH24 = _ADC_SINGLECTRL_NEGSEL_APORT4YCH24,
+  adcNegSelAPORT4XCH25 = _ADC_SINGLECTRL_NEGSEL_APORT4XCH25,
+  adcNegSelAPORT4YCH26 = _ADC_SINGLECTRL_NEGSEL_APORT4YCH26,
+  adcNegSelAPORT4XCH27 = _ADC_SINGLECTRL_NEGSEL_APORT4XCH27,
+  adcNegSelAPORT4YCH28 = _ADC_SINGLECTRL_NEGSEL_APORT4YCH28,
+  adcNegSelAPORT4XCH29 = _ADC_SINGLECTRL_NEGSEL_APORT4XCH29,
+  adcNegSelAPORT4YCH30 = _ADC_SINGLECTRL_NEGSEL_APORT4YCH30,
+  adcNegSelAPORT4XCH31 = _ADC_SINGLECTRL_NEGSEL_APORT4XCH31,
+  adcNegSelTESTN       = _ADC_SINGLECTRL_NEGSEL_TESTN,
+  adcNegSelDEFAULT     = _ADC_SINGLECTRL_NEGSEL_DEFAULT,
+  adcNegSelVSS         = _ADC_SINGLECTRL_NEGSEL_VSS
+} ADC_NegSel_TypeDef;
+#endif
+
+
+#if defined( _ADC_SCANINPUTSEL_MASK )
+  /* ADC scan input groups */
+typedef enum
+{
+  adcScanInputGroup0 = 0,
+  adcScanInputGroup1 = 1,
+  adcScanInputGroup2 = 2,
+  adcScanInputGroup3 = 3,
+} ADC_ScanInputGroup_TypeDef;
+
+  /* ADC scan alternative negative inputs */
+typedef enum
+{
+  adcScanNegInput1  = 1,
+  adcScanNegInput3  = 3,
+  adcScanNegInput5  = 5,
+  adcScanNegInput7  = 7,
+  adcScanNegInput8  = 8,
+  adcScanNegInput10 = 10,
+  adcScanNegInput12 = 12,
+  adcScanNegInput14 = 14,
+  adcScanNegInputDefault = 0xFF,
+} ADC_ScanNegInput_TypeDef;
+#endif
+
 
 /** ADC Start command. */
 typedef enum
@@ -252,17 +723,46 @@
   /** ADC shutdown after each conversion. */
   adcWarmupNormal          = _ADC_CTRL_WARMUPMODE_NORMAL,
 
+#if defined( _ADC_CTRL_WARMUPMODE_FASTBG )
   /** Do not warm-up bandgap references. */
   adcWarmupFastBG          = _ADC_CTRL_WARMUPMODE_FASTBG,
+#endif
 
+#if defined( _ADC_CTRL_WARMUPMODE_KEEPSCANREFWARM )
   /** Reference selected for scan mode kept warm.*/
   adcWarmupKeepScanRefWarm = _ADC_CTRL_WARMUPMODE_KEEPSCANREFWARM,
+#endif
 
-  /** ADC and reference selected for scan mode kept warm.*/
-  adcWarmupKeepADCWarm     = _ADC_CTRL_WARMUPMODE_KEEPADCWARM
+#if defined( _ADC_CTRL_WARMUPMODE_KEEPINSTANDBY )
+  /** ADC is kept in standby mode between conversion. 1us warmup time needed
+      before next conversion. */
+  adcWarmupKeepInStandby   = _ADC_CTRL_WARMUPMODE_KEEPINSTANDBY,
+#endif
+
+#if defined( _ADC_CTRL_WARMUPMODE_KEEPINSLOWACC )
+  /** ADC is kept in slow acquisition mode between conversions. 1us warmup
+      time needed before next conversion. */
+  adcWarmupKeepInSlowAcq   = _ADC_CTRL_WARMUPMODE_KEEPINSLOWACC,
+#endif
+
+  /** ADC and reference selected for scan mode kept warmup, allowing
+      continuous conversion. */
+  adcWarmupKeepADCWarm     = _ADC_CTRL_WARMUPMODE_KEEPADCWARM,
+
 } ADC_Warmup_TypeDef;
 
 
+#if defined( _ADC_CTRL_ADCCLKMODE_MASK )
+  /** ADC EM2 clock configuration */
+typedef enum
+{
+  adcEm2Disabled           = 0,
+  adcEm2ClockOnDemand      = _ADC_CTRL_ADCCLKMODE_ASYNC | _ADC_CTRL_ASYNCCLKEN_ASNEEDED,
+  adcEm2ClockAlwaysOn      = _ADC_CTRL_ADCCLKMODE_ASYNC | _ADC_CTRL_ASYNCCLKEN_ALWAYSON,
+} ADC_EM2ClockConfig_TypeDef;
+#endif
+
+
 /*******************************************************************************
  *******************************   STRUCTS   ***********************************
  ******************************************************************************/
@@ -274,13 +774,15 @@
    * Oversampling rate select. In order to have any effect, oversampling must
    * be enabled for single/scan mode.
    */
-  ADC_OvsRateSel_TypeDef ovsRateSel;
+  ADC_OvsRateSel_TypeDef        ovsRateSel;
 
+#if defined( _ADC_CTRL_LPFMODE_MASK )
   /** Lowpass or decoupling capacitor filter to use. */
-  ADC_LPFilter_TypeDef   lpfMode;
+  ADC_LPFilter_TypeDef          lpfMode;
+#endif
 
   /** Warm-up mode to use for ADC. */
-  ADC_Warmup_TypeDef     warmUpMode;
+  ADC_Warmup_TypeDef            warmUpMode;
 
   /**
    * Timebase used for ADC warm up. Select N to give (N+1)HFPERCLK cycles.
@@ -289,24 +791,66 @@
    * is at least 1 us. See ADC_TimebaseCalc() for a way to obtain
    * a suggested timebase of at least 1 us.
    */
-  uint8_t                timebase;
+  uint8_t                       timebase;
 
   /** Clock division factor N, ADC clock =  HFPERCLK / (N + 1). */
-  uint8_t                prescale;
+  uint8_t                       prescale;
 
   /** Enable/disable conversion tailgating. */
-  bool                   tailgate;
+  bool                          tailgate;
+
+  /** ADC EM2 clock configuration */
+#if defined( _ADC_CTRL_ADCCLKMODE_MASK )
+  ADC_EM2ClockConfig_TypeDef    em2ClockConfig;
+#endif
 } ADC_Init_TypeDef;
 
+
 /** Default config for ADC init structure. */
-#define ADC_INIT_DEFAULT                                                     \
-  { adcOvsRateSel2,                /* 2x oversampling (if enabled). */       \
-    adcLPFilterBypass,             /* No input filter selected. */           \
-    adcWarmupNormal,               /* ADC shutdown after each conversion. */ \
-    _ADC_CTRL_TIMEBASE_DEFAULT,    /* Use HW default value. */               \
-    _ADC_CTRL_PRESC_DEFAULT,       /* Use HW default value. */               \
-    false                          /* Do not use tailgate. */                \
-  }
+#if defined( _ADC_CTRL_LPFMODE_MASK ) && (!defined( _ADC_CTRL_ADCCLKMODE_MASK ))
+#define ADC_INIT_DEFAULT                                                      \
+{                                                                             \
+  adcOvsRateSel2,                /* 2x oversampling (if enabled). */          \
+  adcLPFilterBypass,             /* No input filter selected. */              \
+  adcWarmupNormal,               /* ADC shutdown after each conversion. */    \
+  _ADC_CTRL_TIMEBASE_DEFAULT,    /* Use HW default value. */                  \
+  _ADC_CTRL_PRESC_DEFAULT,       /* Use HW default value. */                  \
+  false                          /* Do not use tailgate. */                   \
+}
+#elif (!defined( _ADC_CTRL_LPFMODE_MASK )) && (!defined( _ADC_CTRL_ADCCLKMODE_MASK ))
+#define ADC_INIT_DEFAULT                                                      \
+{                                                                             \
+  adcOvsRateSel2,                /* 2x oversampling (if enabled). */          \
+  adcWarmupNormal,               /* ADC shutdown after each conversion. */    \
+  _ADC_CTRL_TIMEBASE_DEFAULT,    /* Use HW default value. */                  \
+  _ADC_CTRL_PRESC_DEFAULT,       /* Use HW default value. */                  \
+  false                          /* Do not use tailgate. */                   \
+}
+#elif (!defined( _ADC_CTRL_LPFMODE_MASK )) && defined( _ADC_CTRL_ADCCLKMODE_MASK )
+#define ADC_INIT_DEFAULT                                                      \
+{                                                                             \
+  adcOvsRateSel2,                /* 2x oversampling (if enabled). */          \
+  adcWarmupNormal,               /* ADC shutdown after each conversion. */    \
+  _ADC_CTRL_TIMEBASE_DEFAULT,    /* Use HW default value. */                  \
+  _ADC_CTRL_PRESC_DEFAULT,       /* Use HW default value. */                  \
+  false,                         /* Do not use tailgate. */                   \
+  adcEm2Disabled                 /* ADC disabled in EM2 */                    \
+}
+#endif
+
+
+/** Scan input configuration */
+typedef struct
+{
+  /** Input range select to be applied to ADC_SCANCHCONF. */
+  int32_t             scanInputSel;
+
+  /** Input enable mask */
+  uint32_t            scanInputEn;
+
+  /** Alternative negative input */
+  uint32_t            scanNegSel;
+} ADC_InitScanInput_TypeDef;
 
 
 /** Scan sequence init structure. */
@@ -330,13 +874,23 @@
   /** Sample resolution. */
   ADC_Res_TypeDef     resolution;
 
+#if defined( _ADC_SCANCTRL_INPUTMASK_MASK )
   /**
-   * Input scan selection. If single ended (@p diff is false), use logical
+   * Scan input selection. If single ended (@p diff is false), use logical
    * combination of ADC_SCANCTRL_INPUTMASK_CHx defines. If differential input
    * (@p diff is true), use logical combination of ADC_SCANCTRL_INPUTMASK_CHxCHy
    * defines. (Notice underscore prefix for defines used.)
    */
   uint32_t            input;
+#endif
+
+#if defined( _ADC_SCANINPUTSEL_MASK )
+  /**
+   * Scan input configuration. Use ADC_ScanSingleEndedInit() or ADC_ScanDifferentialInit()
+   * to write this struct. Note that the diff variable is included in ADC_InitScanInput_TypeDef.
+   */
+  ADC_InitScanInput_TypeDef scanInputConfig;
+#endif
 
   /** Select if single ended or differential input. */
   bool                diff;
@@ -349,20 +903,53 @@
 
   /** Select if continuous conversion until explicit stop. */
   bool                rep;
+
+  /** When true, DMA is available in EM2 for scan conversion */
+#if defined( _ADC_CTRL_SCANDMAWU_MASK )
+  bool                scanDmaEm2Wu;
+#endif
+
+#if defined( _ADC_SCANCTRLX_FIFOOFACT_MASK )
+  /** When true, the FIFO overwrites old data when full. If false, then the FIFO discards new data.
+      The SINGLEOF IRQ is triggered in both cases. */
+  bool                fifoOverwrite;
+#endif
 } ADC_InitScan_TypeDef;
 
 /** Default config for ADC scan init structure. */
-#define ADC_INITSCAN_DEFAULT                                                        \
-  { adcPRSSELCh0,              /* PRS ch0 (if enabled). */                          \
-    adcAcqTime1,               /* 1 ADC_CLK cycle acquisition time. */              \
-    adcRef1V25,                /* 1.25V internal reference. */                      \
-    adcRes12Bit,               /* 12 bit resolution. */                             \
-    0,                         /* No input selected. */                             \
-    false,                     /* Single ended input. */                            \
-    false,                     /* PRS disabled. */                                  \
-    false,                     /* Right adjust. */                                  \
-    false                      /* Deactivate conversion after one scan sequence. */ \
-  }
+#if defined( _ADC_SCANCTRL_INPUTMASK_MASK )
+#define ADC_INITSCAN_DEFAULT                                                      \
+{                                                                                 \
+  adcPRSSELCh0,              /* PRS ch0 (if enabled). */                          \
+  adcAcqTime1,               /* 1 ADC_CLK cycle acquisition time. */              \
+  adcRef1V25,                /* 1.25V internal reference. */                      \
+  adcRes12Bit,               /* 12 bit resolution. */                             \
+  0,                         /* No input selected. */                             \
+  false,                     /* Single-ended input. */                            \
+  false,                     /* PRS disabled. */                                  \
+  false,                     /* Right adjust. */                                  \
+  false,                     /* Deactivate conversion after one scan sequence. */ \
+}
+#endif
+
+#if defined( _ADC_SCANINPUTSEL_MASK )
+#define ADC_INITSCAN_DEFAULT                                                      \
+{                                                                                 \
+  adcPRSSELCh0,              /* PRS ch0 (if enabled). */                          \
+  adcAcqTime1,               /* 1 ADC_CLK cycle acquisition time. */              \
+  adcRef1V25,                /* 1.25V internal reference. */                      \
+  adcRes12Bit,               /* 12 bit resolution. */                             \
+  0,                         /* Default ADC inputs */                             \
+  0,                         /* Default input mask (all off) */                   \
+  _ADC_SCANNEGSEL_RESETVALUE,/* Default negative select for positive ternimal */  \
+  false,                     /* Single-ended input. */                            \
+  false,                     /* PRS disabled. */                                  \
+  false,                     /* Right adjust. */                                  \
+  false,                     /* Deactivate conversion after one scan sequence. */ \
+  false,                     /* No EM2 DMA wakeup from scan FIFO DVL */           \
+  false                      /* Discard new data on full FIFO. */                 \
+}
+#endif
 
 
 /** Single conversion init structure. */
@@ -372,52 +959,94 @@
    * Peripheral reflex system trigger selection. Only applicable if @p prsEnable
    * is enabled.
    */
-  ADC_PRSSEL_TypeDef      prsSel;
+  ADC_PRSSEL_TypeDef       prsSel;
 
   /** Acquisition time (in ADC clock cycles). */
-  ADC_AcqTime_TypeDef     acqTime;
+  ADC_AcqTime_TypeDef      acqTime;
 
   /**
    * Sample reference selection. Notice that for external references, the
    * ADC calibration register must be set explicitly.
    */
-  ADC_Ref_TypeDef         reference;
+  ADC_Ref_TypeDef          reference;
 
   /** Sample resolution. */
-  ADC_Res_TypeDef         resolution;
+  ADC_Res_TypeDef          resolution;
 
+#if defined( _ADC_SINGLECTRL_INPUTSEL_MASK )
   /**
    * Sample input selection, use single ended or differential input according
    * to setting of @p diff.
    */
-  ADC_SingleInput_TypeDef input;
+  ADC_SingleInput_TypeDef  input;
+#endif
+
+#if defined( _ADC_SINGLECTRL_POSSEL_MASK )
+  /** Select positive input for for single channel conversion mode. */
+  ADC_PosSel_TypeDef posSel;
+#endif
+
+#if defined( _ADC_SINGLECTRL_NEGSEL_MASK )
+  /** Select negative input for single channel conversion mode. Negative input is grounded
+      for single ended (non-differential) converison.  */
+  ADC_NegSel_TypeDef negSel;
+#endif
 
   /** Select if single ended or differential input. */
-  bool                    diff;
+  bool                     diff;
 
   /** Peripheral reflex system trigger enable. */
-  bool                    prsEnable;
+  bool                     prsEnable;
 
   /** Select if left adjustment should be done. */
-  bool                    leftAdjust;
+  bool                     leftAdjust;
 
   /** Select if continuous conversion until explicit stop. */
-  bool                    rep;
+  bool                     rep;
+
+#if defined( _ADC_CTRL_SINGLEDMAWU_MASK )
+  /** When true, DMA is available in EM2 for single conversion */
+  bool                    singleDmaEm2Wu;
+#endif
+
+#if defined( _ADC_SINGLECTRLX_FIFOOFACT_MASK )
+  /** When true, the FIFO overwrites old data when full. If false, then the FIFO discards new data.
+      The SCANOF IRQ is triggered in both cases. */
+  bool                    fifoOverwrite;
+#endif
 } ADC_InitSingle_TypeDef;
 
 /** Default config for ADC single conversion init structure. */
-#define ADC_INITSINGLE_DEFAULT                                                      \
-  { adcPRSSELCh0,              /* PRS ch0 (if enabled). */                          \
-    adcAcqTime1,               /* 1 ADC_CLK cycle acquisition time. */              \
-    adcRef1V25,                /* 1.25V internal reference. */                      \
-    adcRes12Bit,               /* 12 bit resolution. */                             \
-    adcSingleInpCh0,           /* CH0 input selected. */                            \
-    false,                     /* Single ended input. */                            \
-    false,                     /* PRS disabled. */                                  \
-    false,                     /* Right adjust. */                                  \
-    false                      /* Deactivate conversion after one scan sequence. */ \
-  }
-
+#if defined( _ADC_SINGLECTRL_INPUTSEL_MASK )
+#define ADC_INITSINGLE_DEFAULT                                                    \
+{                                                                                 \
+  adcPRSSELCh0,              /* PRS ch0 (if enabled). */                          \
+  adcAcqTime1,               /* 1 ADC_CLK cycle acquisition time. */              \
+  adcRef1V25,                /* 1.25V internal reference. */                      \
+  adcRes12Bit,               /* 12 bit resolution. */                             \
+  adcSingleInpCh0,           /* CH0 input selected. */                            \
+  false,                     /* Single ended input. */                            \
+  false,                     /* PRS disabled. */                                  \
+  false,                     /* Right adjust. */                                  \
+  false                      /* Deactivate conversion after one scan sequence. */ \
+}
+#else
+#define ADC_INITSINGLE_DEFAULT                                                    \
+{                                                                                 \
+  adcPRSSELCh0,              /* PRS ch0 (if enabled). */                          \
+  adcAcqTime1,               /* 1 ADC_CLK cycle acquisition time. */              \
+  adcRef1V25,                /* 1.25V internal reference. */                      \
+  adcRes12Bit,               /* 12 bit resolution. */                             \
+  adcPosSelAPORT0XCH0,         /* Select node BUS0XCH0 as posSel */                 \
+  adcNegSelAPORT0XCH1,         /* Select node BUS0XCH1 as negSel */                 \
+  false,                     /* Single ended input. */                            \
+  false,                     /* PRS disabled. */                                  \
+  false,                     /* Right adjust. */                                  \
+  false,                     /* Deactivate conversion after one scan sequence. */ \
+  false,                     /* No EM2 DMA wakeup from single FIFO DVL */         \
+  false                      /* Discard new data on full FIFO. */                 \
+}
+#endif
 
 /*******************************************************************************
  *****************************   PROTOTYPES   **********************************
@@ -428,17 +1057,36 @@
  *   Get single conversion result.
  *
  * @note
- *   Do only use if single conversion data valid.
+ *   Check data valid flag before calling this function.
  *
  * @param[in] adc
  *   Pointer to ADC peripheral register block.
  *
  * @return
- *
+ *   Single conversion data.
  ******************************************************************************/
 __STATIC_INLINE uint32_t ADC_DataSingleGet(ADC_TypeDef *adc)
 {
-  return(adc->SINGLEDATA);
+  return adc->SINGLEDATA;
+}
+
+
+/***************************************************************************//**
+ * @brief
+ *   Peek single conversion result.
+ *
+ * @note
+ *   Check data valid flag before calling this function.
+ *
+ * @param[in] adc
+ *   Pointer to ADC peripheral register block.
+ *
+ * @return
+ *   Single conversion data.
+ ******************************************************************************/
+__STATIC_INLINE uint32_t ADC_DataSinglePeek(ADC_TypeDef *adc)
+{
+  return adc->SINGLEDATAP;
 }
 
 
@@ -447,20 +1095,62 @@
  *   Get scan result.
  *
  * @note
- *   Do only use if scan data valid.
+ *   Check data valid flag before calling this function.
  *
  * @param[in] adc
  *   Pointer to ADC peripheral register block.
+ *
+ * @return
+ *   Scan conversion data.
  ******************************************************************************/
 __STATIC_INLINE uint32_t ADC_DataScanGet(ADC_TypeDef *adc)
 {
-  return(adc->SCANDATA);
+  return adc->SCANDATA;
+}
+
+
+/***************************************************************************//**
+ * @brief
+ *   Peek scan result.
+ *
+ * @note
+ *   Check data valid flag before calling this function.
+ *
+ * @param[in] adc
+ *   Pointer to ADC peripheral register block.
+ *
+ * @return
+ *   Scan conversion data.
+ ******************************************************************************/
+__STATIC_INLINE uint32_t ADC_DataScanPeek(ADC_TypeDef *adc)
+{
+  return adc->SCANDATAP;
 }
 
 
+#if defined( _ADC_SCANDATAX_MASK )
+uint32_t ADC_DataIdScanGet(ADC_TypeDef *adc, uint32_t *scanId);
+#endif
+
 void ADC_Init(ADC_TypeDef *adc, const ADC_Init_TypeDef *init);
+void ADC_Reset(ADC_TypeDef *adc);
 void ADC_InitScan(ADC_TypeDef *adc, const ADC_InitScan_TypeDef *init);
+
+#if defined( _ADC_SCANINPUTSEL_MASK )
+void ADC_ScanInputClear(ADC_InitScan_TypeDef *scanInit);
+uint32_t ADC_ScanSingleEndedInputAdd(ADC_InitScan_TypeDef *scanInit,
+                                     ADC_ScanInputGroup_TypeDef inputGroup,
+                                     ADC_PosSel_TypeDef singleEndedSel);
+uint32_t ADC_ScanDifferentialInputAdd(ADC_InitScan_TypeDef *scanInit,
+                                      ADC_ScanInputGroup_TypeDef inputGroup,
+                                      ADC_PosSel_TypeDef posSel,
+                                      ADC_ScanNegInput_TypeDef adcScanNegInput);
+#endif
+
 void ADC_InitSingle(ADC_TypeDef *adc, const ADC_InitSingle_TypeDef *init);
+uint8_t ADC_TimebaseCalc(uint32_t hfperFreq);
+uint8_t ADC_PrescaleCalc(uint32_t adcFreq, uint32_t hfperFreq);
+
 
 /***************************************************************************//**
  * @brief
@@ -492,7 +1182,7 @@
  ******************************************************************************/
 __STATIC_INLINE void ADC_IntDisable(ADC_TypeDef *adc, uint32_t flags)
 {
-  adc->IEN &= ~(flags);
+  adc->IEN &= ~flags;
 }
 
 
@@ -534,7 +1224,39 @@
  ******************************************************************************/
 __STATIC_INLINE uint32_t ADC_IntGet(ADC_TypeDef *adc)
 {
-  return(adc->IF);
+  return adc->IF;
+}
+
+
+/***************************************************************************//**
+ * @brief
+ *   Get enabled and pending ADC interrupt flags.
+ *   Useful for handling more interrupt sources in the same interrupt handler.
+ *
+ * @param[in] adc
+ *   Pointer to ADC peripheral register block.
+ *
+ * @note
+ *   Interrupt flags are not cleared by the use of this function.
+ *
+ * @return
+ *   Pending and enabled ADC interrupt sources.
+ *   The return value is the bitwise AND combination of
+ *   - the OR combination of enabled interrupt sources in ADCx_IEN_nnn
+ *     register (ADCx_IEN_nnn) and
+ *   - the OR combination of valid interrupt flags of the ADC module
+ *     (ADCx_IF_nnn).
+ ******************************************************************************/
+__STATIC_INLINE uint32_t ADC_IntGetEnabled(ADC_TypeDef *adc)
+{
+  uint32_t ien;
+
+  /* Store ADCx->IEN in temporary variable in order to define explicit order
+   * of volatile accesses. */
+  ien = adc->IEN;
+
+  /* Bitwise AND of pending and enabled interrupts */
+  return adc->IF & ien;
 }
 
 
@@ -554,8 +1276,6 @@
   adc->IFS = flags;
 }
 
-uint8_t ADC_PrescaleCalc(uint32_t adcFreq, uint32_t hfperFreq);
-
 
 /***************************************************************************//**
  * @brief
@@ -572,8 +1292,6 @@
   adc->CMD = (uint32_t)cmd;
 }
 
-void ADC_Reset(ADC_TypeDef *adc);
-uint8_t ADC_TimebaseCalc(uint32_t hfperFreq);
 
 /** @} (end addtogroup ADC) */
 /** @} (end addtogroup EM_Library) */
@@ -583,4 +1301,4 @@
 #endif
 
 #endif /* defined(ADC_COUNT) && (ADC_COUNT > 0) */
-#endif /* __SILICON_LABS_EM_ADC_H_ */
+#endif /* __SILICON_LABS_EM_ADC_H__ */

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_aes.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_aes.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,11 +1,10 @@
 /***************************************************************************//**
  * @file em_aes.h
- * @brief Advanced encryption standard (AES) accelerator peripheral API for
- *   EFM32.
- * @version 3.20.12
+ * @brief Advanced encryption standard (AES) accelerator peripheral API.
+ * @version 4.2.1
  *******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
  *******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -31,9 +30,8 @@
  *
  ******************************************************************************/
 
-
-#ifndef __SILICON_LABS_EM_AES_H_
-#define __SILICON_LABS_EM_AES_H_
+#ifndef __SILICON_LABS_EM_AES_H__
+#define __SILICON_LABS_EM_AES_H__
 
 #include "em_device.h"
 #if defined(AES_COUNT) && (AES_COUNT > 0)
@@ -201,7 +199,30 @@
  ******************************************************************************/
 __STATIC_INLINE uint32_t AES_IntGet(void)
 {
-  return(AES->IF);
+  return AES->IF;
+}
+
+
+/***************************************************************************//**
+ * @brief
+ *   Get enabled and pending AES interrupt flags.
+ *   Useful for handling more interrupt sources in the same interrupt handler.
+ *
+ * @note
+ *   Interrupt flags are not cleared by the use of this function.
+ *
+ * @return
+ *   Pending and enabled AES interrupt sources
+ *   The return value is the bitwise AND of
+ *   - the enabled interrupt sources in AES_IEN and
+ *   - the pending interrupt flags AES_IF
+ ******************************************************************************/
+__STATIC_INLINE uint32_t AES_IntGetEnabled(void)
+{
+  uint32_t ien;
+
+  ien = AES->IEN;
+  return AES->IF & ien;
 }
 
 
@@ -242,6 +263,6 @@
 #endif
 
 #endif /* defined(AES_COUNT) && (AES_COUNT > 0) */
-#endif /* __SILICON_LABS_EM_AES_H_ */
+#endif /* __SILICON_LABS_EM_AES_H__ */
 
 

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_assert.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_assert.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,28 +1,28 @@
 /***************************************************************************//**
  * @file em_assert.h
- * @brief EFM32 peripheral API "assert" implementation.
- * @version 3.20.12
+ * @brief Emlib peripheral API "assert" implementation.
+ * @version 4.2.1
  *
  * @details
- * By default, EFM32 library assert usage is not included in order to reduce
- * footprint and processing overhead. Further, EFM32 assert usage is decoupled
+ * By default, emlib library assert usage is not included in order to reduce
+ * footprint and processing overhead. Further, emlib assert usage is decoupled
  * from ISO C assert handling (NDEBUG usage), to allow a user to use ISO C
- * assert without including EFM32 assert statements.
+ * assert without including emlib assert statements.
  *
- * Below are available defines for controlling EFM32 assert inclusion. The defines
+ * Below are available defines for controlling emlib assert inclusion. The defines
  * are typically defined for a project to be used by the preprocessor.
  *
- * @li If DEBUG_EFM is defined, the internal EFM32 library assert handling will
+ * @li If DEBUG_EFM is defined, the internal emlib library assert handling will
  * be used, which may be a quite rudimentary implementation.
  *
- * @li If DEBUG_EFM_USER is defined instead, the user must provide its own EFM32
+ * @li If DEBUG_EFM_USER is defined instead, the user must provide their own
  * assert handling routine (assertEFM()).
  *
- * As indicated above, if none of the above defines are used, EFM32 assert
+ * As indicated above, if none of the above defines are used, emlib assert
  * statements are not compiled.
  *******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
  *******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -48,9 +48,8 @@
  *
  ******************************************************************************/
 
-
-#ifndef __SILICON_LABS_EM_ASSERT_H_
-#define __SILICON_LABS_EM_ASSERT_H_
+#ifndef __SILICON_LABS_EM_ASSERT_H__
+#define __SILICON_LABS_EM_ASSERT_H__
 
 #ifdef __cplusplus
 extern "C" {
@@ -77,4 +76,4 @@
 }
 #endif
 
-#endif /* __SILICON_LABS_EM_ASSERT_H_ */
+#endif /* __SILICON_LABS_EM_ASSERT_H__ */

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_bitband.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_bitband.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /***************************************************************************//**
  * @file em_bitband.h
  * @brief Bitband Peripheral API
- * @version 3.20.12
+ * @version 4.2.1
  *******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
  *******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,11 +30,11 @@
  *
  ******************************************************************************/
 
+#ifndef __SILICON_LABS_EM_BITBAND_H__
+#define __SILICON_LABS_EM_BITBAND_H__
 
-#ifndef __SILICON_LABS_EM_BITBAND_H_
-#define __SILICON_LABS_EM_BITBAND_H_
+#include "em_bus.h"
 
-#include "em_device.h"
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -46,7 +46,7 @@
 
 /***************************************************************************//**
  * @addtogroup BITBAND
- * @brief BITBAND Peripheral API
+ * @brief BITBAND Peripheral API (deprecated - use em_bus.h)
  * @{
  ******************************************************************************/
 
@@ -68,22 +68,7 @@
  *
  * @param[in] val Value to set bit to, 0 or 1.
  ******************************************************************************/
-__STATIC_INLINE void BITBAND_Peripheral(volatile uint32_t *addr,
-                                        uint32_t bit,
-                                        uint32_t val)
-{
-#if defined(BITBAND_PER_BASE)
-  uint32_t tmp =
-    BITBAND_PER_BASE + (((uint32_t)addr - PER_MEM_BASE) * 32) + (bit * 4);
-
-  *((volatile uint32_t *)tmp) = (uint32_t)val;
-#else
-  uint32_t tmp = *addr;
-  /* Make sure val is not more than 1, because we only want to set one bit. */
-  val &= 0x1;
-  *addr = (tmp & ~(1 << bit)) | (val << bit);
-#endif /* defined(BITBAND_PER_BASE) */
-}
+#define BITBAND_Peripheral(addr, bit, val) BUS_RegBitWrite(addr, bit, val)
 
 
 /***************************************************************************//**
@@ -102,18 +87,7 @@
  *
  * @return           Value of the requested bit.
  ******************************************************************************/
-__STATIC_INLINE uint32_t BITBAND_PeripheralRead(volatile uint32_t *addr,
-                                                uint32_t bit)
-{
-#if defined(BITBAND_PER_BASE)
-  uint32_t tmp =
-    BITBAND_PER_BASE + (((uint32_t)addr - PER_MEM_BASE) * 32) + (bit * 4);
-
-  return *((volatile uint32_t *)tmp);
-#else
-  return ((*addr) >> bit) & 1;
-#endif /* defined(BITBAND_PER_BASE) */
-}
+#define BITBAND_PeripheralRead(addr, bit) BUS_RegBitRead(addr, bit)
 
 
 /***************************************************************************//**
@@ -134,20 +108,7 @@
  *
  * @param[in] val Value to set bit to, 0 or 1.
  ******************************************************************************/
-__STATIC_INLINE void BITBAND_SRAM(uint32_t *addr, uint32_t bit, uint32_t val)
-{
-#if defined(BITBAND_RAM_BASE)
-  uint32_t tmp =
-    BITBAND_RAM_BASE + (((uint32_t)addr - RAM_MEM_BASE) * 32) + (bit * 4);
-
-  *((volatile uint32_t *)tmp) = (uint32_t)val;
-#else
-  uint32_t tmp = *addr;
-  /* Make sure val is not more than 1, because we only want to set one bit. */
-  val &= 0x1;
-  *addr = (tmp & ~(1 << bit)) | (val << bit);
-#endif /* defined(BITBAND_RAM_BASE) */
-}
+#define BITBAND_SRAM(addr, bit, val) BUS_RamBitWrite(addr, bit, val)
 
 
 /***************************************************************************//**
@@ -166,17 +127,7 @@
  *
  * @return            Value of the requested bit.
  ******************************************************************************/
-__STATIC_INLINE uint32_t BITBAND_SRAMRead(uint32_t *addr, uint32_t bit)
-{
-#if defined(BITBAND_RAM_BASE)
-  uint32_t tmp =
-    BITBAND_RAM_BASE + (((uint32_t)addr - RAM_MEM_BASE) * 32) + (bit * 4);
-
-  return *((volatile uint32_t *)tmp);
-#else
-  return ((*addr) >> bit) & 1;
-#endif /* defined(BITBAND_RAM_BASE) */
-}
+#define BITBAND_SRAMRead(addr, bit) BUS_RamBitRead(addr, bit)
 
 /** @} (end addtogroup BITBAND) */
 /** @} (end addtogroup EM_Library) */
@@ -185,4 +136,4 @@
 }
 #endif
 
-#endif /* __SILICON_LABS_EM_BITBAND_H_ */
+#endif /* __SILICON_LABS_EM_BITBAND_H__ */

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_burtc.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_burtc.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /***************************************************************************//**
  * @file em_burtc.h
  * @brief Backup Real Time Counter (BURTC) peripheral API
- * @version 3.20.12
+ * @version 4.2.1
  *******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
  *******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,17 +30,15 @@
  *
  ******************************************************************************/
 
+#ifndef __SILICON_LABS_EM_BURTC_H__
+#define __SILICON_LABS_EM_BURTC_H__
 
-#ifndef __SILICON_LABS_EM_BURTC_H_
-#define __SILICON_LABS_EM_BURTC_H_
+#include "em_device.h"
+#if defined(BURTC_PRESENT)
 
 #include <stdbool.h>
-#include "em_device.h"
-
-#if defined(BURTC_PRESENT)
-
 #include "em_assert.h"
-#include "em_bitband.h"
+#include "em_bus.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -133,17 +131,18 @@
 } BURTC_Init_TypeDef;
 
 /** Default configuration for BURTC init structure */
-#define BURTC_INIT_DEFAULT \
-  { true,                  \
-    burtcModeEM2,          \
-    false,                 \
-    burtcClkSelULFRCO,     \
-    burtcClkDiv_1,         \
-    0,                     \
-    true,                  \
-    false,                 \
-    burtcLPDisable,        \
-  }
+#define BURTC_INIT_DEFAULT  \
+{                           \
+  true,                     \
+  burtcModeEM2,             \
+  false,                    \
+  burtcClkSelULFRCO,        \
+  burtcClkDiv_1,            \
+  0,                        \
+  true,                     \
+  false,                    \
+  burtcLPDisable,           \
+}
 
 /*******************************************************************************
  *****************************   PROTOTYPES   **********************************
@@ -286,15 +285,17 @@
 __STATIC_INLINE void BURTC_Enable(bool enable)
 {
   /* Note! If mode is disabled, BURTC counter will not start */
-  EFM_ASSERT(((enable == true) && ((BURTC->CTRL & _BURTC_CTRL_MODE_MASK) != BURTC_CTRL_MODE_DISABLE))
+  EFM_ASSERT(((enable == true)
+              && ((BURTC->CTRL & _BURTC_CTRL_MODE_MASK)
+                  != BURTC_CTRL_MODE_DISABLE))
              || (enable == false));
   if (enable)
   {
-    BITBAND_Peripheral(&BURTC->CTRL, _BURTC_CTRL_RSTEN_SHIFT, 0);
+    BUS_RegBitWrite(&BURTC->CTRL, _BURTC_CTRL_RSTEN_SHIFT, 0);
   }
   else
   {
-    BITBAND_Peripheral(&BURTC->CTRL, _BURTC_CTRL_RSTEN_SHIFT, 1);
+    BUS_RegBitWrite(&BURTC->CTRL, _BURTC_CTRL_RSTEN_SHIFT, 1);
   }
 }
 
@@ -329,7 +330,7 @@
  ******************************************************************************/
 __STATIC_INLINE void BURTC_FreezeEnable(bool enable)
 {
-  BITBAND_Peripheral(&BURTC->FREEZE, _BURTC_FREEZE_REGFREEZE_SHIFT, enable);
+  BUS_RegBitWrite(&BURTC->FREEZE, _BURTC_FREEZE_REGFREEZE_SHIFT, enable);
 }
 
 
@@ -343,7 +344,7 @@
  ******************************************************************************/
 __STATIC_INLINE void BURTC_Powerdown(bool enable)
 {
-  BITBAND_Peripheral(&BURTC->POWERDOWN, _BURTC_POWERDOWN_RAM_SHIFT, enable);
+  BUS_RegBitWrite(&BURTC->POWERDOWN, _BURTC_POWERDOWN_RAM_SHIFT, enable);
 }
 
 
@@ -415,4 +416,4 @@
 #endif
 
 #endif /* BURTC_PRESENT */
-#endif /* __SILICON_LABS_EM_BURTC_H_ */
+#endif /* __SILICON_LABS_EM_BURTC_H__ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_bus.h	Fri Jan 15 07:45:16 2016 +0000
@@ -0,0 +1,327 @@
+/***************************************************************************//**
+ * @file em_bus.h
+ * @brief RAM and peripheral bit-field set and clear API
+ * @version 4.2.1
+ *******************************************************************************
+ * @section License
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
+ *******************************************************************************
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
+ * obligation to support this Software. Silicon Labs is providing the
+ * Software "AS IS", with no express or implied warranties of any kind,
+ * including, but not limited to, any implied warranties of merchantability
+ * or fitness for any particular purpose or warranties against infringement
+ * of any proprietary rights of a third party.
+ *
+ * Silicon Labs will not be liable for any consequential, incidental, or
+ * special damages, or any other relief, or for any claim by any third party,
+ * arising from your use of this Software.
+ *
+ ******************************************************************************/
+
+#ifndef __SILICON_LABS_EM_BUS__
+#define __SILICON_LABS_EM_BUS__
+
+#include "em_device.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************************************************************//**
+ * @addtogroup EM_Library
+ * @{
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * @addtogroup BUS
+ * @brief BUS RAM and register bit/field read/write API
+ * @{
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * @brief
+ *   Perform a single-bit write operation on a 32-bit word in RAM
+ *
+ * @details
+ *   This function uses Cortex-M bit-banding hardware to perform an atomic
+ *   read-modify-write operation on a single bit write on a 32-bit word in RAM.
+ *   Please refer to the reference manual for further details about bit-banding.
+ *
+ * @note
+ *   This function is atomic on Cortex-M cores with bit-banding support. Bit-
+ *   banding is a multicycle read-modify-write bus operation. RAM bit-banding is
+ *   performed using the memory alias region at BITBAND_RAM_BASE.
+ *
+ * @param[in] addr Address of 32-bit word in RAM
+ *
+ * @param[in] bit Bit position to write, 0-31
+ *
+ * @param[in] val Value to set bit to, 0 or 1
+ ******************************************************************************/
+__STATIC_INLINE void BUS_RamBitWrite(volatile uint32_t *addr,
+                                     unsigned int bit,
+                                     unsigned int val)
+{
+#if defined( BITBAND_RAM_BASE )
+  uint32_t aliasAddr =
+    BITBAND_RAM_BASE + (((uint32_t)addr - SRAM_BASE) * 32) + (bit * 4);
+
+  *(volatile uint32_t *)aliasAddr = (uint32_t)val;
+#else
+  uint32_t tmp = *addr;
+
+  /* Make sure val is not more than 1, because we only want to set one bit. */
+  *addr = (tmp & ~(1 << bit)) | ((val & 1) << bit);
+#endif
+}
+
+
+/***************************************************************************//**
+ * @brief
+ *   Perform a single-bit read operation on a 32-bit word in RAM
+ *
+ * @details
+ *   This function uses Cortex-M bit-banding hardware to perform an atomic
+ *   read operation on a single register bit. Please refer to the
+ *   reference manual for further details about bit-banding.
+ *
+ * @note
+ *   This function is atomic on Cortex-M cores with bit-banding support.
+ *   RAM bit-banding is performed using the memory alias region
+ *   at BITBAND_RAM_BASE.
+ *
+ * @param[in] addr RAM address
+ *
+ * @param[in] bit Bit position to read, 0-31
+ *
+ * @return
+ *     The requested bit shifted to bit position 0 in the return value
+ ******************************************************************************/
+__STATIC_INLINE unsigned int BUS_RamBitRead(volatile const uint32_t *addr,
+                                            unsigned int bit)
+{
+#if defined( BITBAND_RAM_BASE )
+  uint32_t aliasAddr =
+    BITBAND_RAM_BASE + (((uint32_t)addr - SRAM_BASE) * 32) + (bit * 4);
+
+  return *(volatile uint32_t *)aliasAddr;
+#else
+  return ((*addr) >> bit) & 1;
+#endif
+}
+
+
+/***************************************************************************//**
+ * @brief
+ *   Perform a single-bit write operation on a peripheral register
+ *
+ * @details
+ *   This function uses Cortex-M bit-banding hardware to perform an atomic
+ *   read-modify-write operation on a single register bit. Please refer to the
+ *   reference manual for further details about bit-banding.
+ *
+ * @note
+ *   This function is atomic on Cortex-M cores with bit-banding support. Bit-
+ *   banding is a multicycle read-modify-write bus operation. Peripheral register
+ *   bit-banding is performed using the memory alias region at BITBAND_PER_BASE.
+ *
+ * @param[in] addr Peripheral register address
+ *
+ * @param[in] bit Bit position to write, 0-31
+ *
+ * @param[in] val Value to set bit to, 0 or 1
+ ******************************************************************************/
+__STATIC_INLINE void BUS_RegBitWrite(volatile uint32_t *addr,
+                                     unsigned int bit,
+                                     unsigned int val)
+{
+#if defined( BITBAND_PER_BASE )
+  uint32_t aliasAddr =
+    BITBAND_PER_BASE + (((uint32_t)addr - PER_MEM_BASE) * 32) + (bit * 4);
+
+  *(volatile uint32_t *)aliasAddr = (uint32_t)val;
+#else
+  uint32_t tmp = *addr;
+
+  /* Make sure val is not more than 1, because we only want to set one bit. */
+  *addr = (tmp & ~(1 << bit)) | ((val & 1) << bit);
+#endif
+}
+
+
+/***************************************************************************//**
+ * @brief
+ *   Perform a single-bit read operation on a peripheral register
+ *
+ * @details
+ *   This function uses Cortex-M bit-banding hardware to perform an atomic
+ *   read operation on a single register bit. Please refer to the
+ *   reference manual for further details about bit-banding.
+ *
+ * @note
+ *   This function is atomic on Cortex-M cores with bit-banding support.
+ *   Peripheral register bit-banding is performed using the memory alias
+ *   region at BITBAND_PER_BASE.
+ *
+ * @param[in] addr Peripheral register address
+ *
+ * @param[in] bit Bit position to read, 0-31
+ *
+ * @return
+ *     The requested bit shifted to bit position 0 in the return value
+ ******************************************************************************/
+__STATIC_INLINE unsigned int BUS_RegBitRead(volatile const uint32_t *addr,
+                                            unsigned int bit)
+{
+#if defined( BITBAND_PER_BASE )
+  uint32_t aliasAddr =
+    BITBAND_PER_BASE + (((uint32_t)addr - PER_MEM_BASE) * 32) + (bit * 4);
+
+  return *(volatile uint32_t *)aliasAddr;
+#else
+  return ((*addr) >> bit) & 1;
+#endif
+}
+
+
+/***************************************************************************//**
+ * @brief
+ *   Perform a masked set operation on peripheral register address.
+ *
+ * @details
+ *   Peripheral register masked set provides a single-cycle and atomic set
+ *   operation of a bit-mask in a peripheral register. All 1's in the mask are
+ *   set to 1 in the register. All 0's in the mask are not changed in the
+ *   register.
+ *   RAMs and special peripherals are not supported. Please refer to the
+ *   reference manual for further details about peripheral register field set.
+ *
+ * @note
+ *   This function is single-cycle and atomic on cores with peripheral bit set
+ *   and clear support. It uses the memory alias region at PER_BITSET_MEM_BASE.
+ *
+ * @param[in] addr Peripheral register address
+ *
+ * @param[in] mask Mask to set
+ ******************************************************************************/
+__STATIC_INLINE void BUS_RegMaskedSet(volatile uint32_t *addr,
+                                      uint32_t mask)
+{
+#if defined( PER_BITSET_MEM_BASE )
+  uint32_t aliasAddr = PER_BITSET_MEM_BASE + ((uint32_t)addr - PER_MEM_BASE);
+  *(volatile uint32_t *)aliasAddr = mask;
+#else
+  *addr |= mask;
+#endif
+}
+
+
+/***************************************************************************//**
+ * @brief
+ *   Perform a masked clear operation on peripheral register address.
+ *
+ * @details
+ *   Peripheral register masked clear provides a single-cycle and atomic clear
+ *   operation of a bit-mask in a peripheral register. All 1's in the mask are
+ *   set to 0 in the register.
+ *   All 0's in the mask are not changed in the register.
+ *   RAMs and special peripherals are not supported. Please refer to the
+ *   reference manual for further details about peripheral register field clear.
+ *
+ * @note
+ *   This function is single-cycle and atomic on cores with peripheral bit set
+ *   and clear support. It uses the memory alias region at PER_BITCLR_MEM_BASE.
+ *
+ * @param[in] addr Peripheral register address
+ *
+ * @param[in] mask Mask to clear
+ ******************************************************************************/
+__STATIC_INLINE void BUS_RegMaskedClear(volatile uint32_t *addr,
+                                        uint32_t mask)
+{
+#if defined( PER_BITCLR_MEM_BASE )
+  uint32_t aliasAddr = PER_BITCLR_MEM_BASE + ((uint32_t)addr - PER_MEM_BASE);
+  *(volatile uint32_t *)aliasAddr = mask;
+#else
+  *addr &= ~mask;
+#endif
+}
+
+
+/***************************************************************************//**
+ * @brief
+ *   Perform peripheral register masked clear and value write.
+ *
+ * @details
+ *   This function first clears the mask in the peripheral register, then
+ *   writes the value. Typically the mask is a bit-field in the register, and
+ *   the value val is within the mask.
+ *
+ * @note
+ *   This operation is not atomic. Note that the mask is first set to 0 before
+ *   the val is set.
+ *
+ * @param[in] addr Peripheral register address
+ *
+ * @param[in] mask Peripheral register mask
+ *
+ * @param[in] val Peripheral register value. The value must be shifted to the
+                  correct bit position in the register.
+ ******************************************************************************/
+__STATIC_INLINE void BUS_RegMaskedWrite(volatile uint32_t *addr,
+                                        uint32_t mask,
+                                        uint32_t val)
+{
+#if defined( PER_BITCLR_MEM_BASE )
+  BUS_RegMaskedClear(addr, mask);
+  BUS_RegMaskedSet(addr, val);
+#else
+  *addr = (*addr & ~mask) | val;
+#endif
+}
+
+
+/***************************************************************************//**
+ * @brief
+ *   Perform a peripheral register masked read
+ *
+ * @details
+ *   Read an unshifted and masked value from a peripheral register.
+ *
+ * @note
+ *   This operation is not hardware accelerated.
+ *
+ * @param[in] addr Peripheral register address
+ *
+ * @param[in] mask Peripheral register mask
+ *
+ * @return
+ *   Unshifted and masked register value
+ ******************************************************************************/
+__STATIC_INLINE uint32_t BUS_RegMaskedRead(volatile const uint32_t *addr,
+                                           uint32_t mask)
+{
+  return *addr & mask;
+}
+
+
+/** @} (end addtogroup BUS) */
+/** @} (end addtogroup EM_Library) */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SILICON_LABS_EM_BUS__ */

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_chip.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_chip.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /***************************************************************************//**
  * @file em_chip.h
  * @brief Chip Initialization API
- * @version 3.20.12
+ * @version 4.2.1
  *******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
  *******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,9 +30,8 @@
  *
  ******************************************************************************/
 
-
-#ifndef __SILICON_LABS_EM_CHIP_H_
-#define __SILICON_LABS_EM_CHIP_H_
+#ifndef __SILICON_LABS_EM_CHIP_H__
+#define __SILICON_LABS_EM_CHIP_H__
 
 #include "em_device.h"
 #include "em_system.h"
@@ -56,7 +55,7 @@
  * @brief
  *   Chip initialization routine for revision errata workarounds
  *
- * This init function will configure the EFM32 device to a state where it is
+ * This init function will configure the device to a state where it is
  * as similar as later revisions as possible, to improve software compatibility
  * with newer parts. See the device specific errata for details.
  *****************************************************************************/
@@ -172,12 +171,12 @@
 #if defined(_EFM32_HAPPY_FAMILY)
   uint32_t rev;
   rev = *(volatile uint32_t *)(0x0FE081FC);
-  
+
   if ((rev >> 24) <= 129)
   {
     /* This fixes a mistaken internal connection between PC0 and PC4 */
     /* This disables an internal pulldown on PC4 */
-    *(volatile uint32_t*)(0x400C6018) = (1 << 26) | (5 << 0); 
+    *(volatile uint32_t*)(0x400C6018) = (1 << 26) | (5 << 0);
     /* This disables an internal LDO test signal driving PC4 */
     *(volatile uint32_t*)(0x400C80E4) &= ~(1 << 24);
   }
@@ -191,4 +190,4 @@
 }
 #endif
 
-#endif /* __SILICON_LABS_EM_CHIP_H_ */
+#endif /* __SILICON_LABS_EM_CHIP_H__ */

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_cmu.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_cmu.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /***************************************************************************//**
  * @file em_cmu.h
  * @brief Clock management unit (CMU) API
- * @version 3.20.12
+ * @version 4.2.1
  *******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
  *******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -29,16 +29,15 @@
  * arising from your use of this Software.
  *
  ******************************************************************************/
-
-
-#ifndef __SILICON_LABS_EM_CMU_H_
-#define __SILICON_LABS_EM_CMU_H_
+#ifndef __SILICON_LABS_EM_CMU_H__
+#define __SILICON_LABS_EM_CMU_H__
 
 #include "em_device.h"
 #if defined( CMU_PRESENT )
 
 #include <stdbool.h>
-#include "em_bitband.h"
+#include "em_assert.h"
+#include "em_bus.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -56,71 +55,85 @@
 
 /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
 
-/* Select register ids, for internal use */
+/* Select register id's, for internal use. */
 #define CMU_NOSEL_REG              0
 #define CMU_HFCLKSEL_REG           1
 #define CMU_LFACLKSEL_REG          2
 #define CMU_LFBCLKSEL_REG          3
-#define CMU_DBGCLKSEL_REG          4
-#if defined( _CMU_CMD_USBCCLKSEL_MASK )
-#define CMU_USBCCLKSEL_REG         5
-#endif
-#if defined( _CMU_LFCLKSEL_LFC_MASK )
-#define CMU_LFCCLKSEL_REG          6
-#endif
+#define CMU_LFCCLKSEL_REG          4
+#define CMU_LFECLKSEL_REG          5
+#define CMU_DBGCLKSEL_REG          6
+#define CMU_USBCCLKSEL_REG         7
 
 #define CMU_SEL_REG_POS            0
 #define CMU_SEL_REG_MASK           0xf
 
-/* Divisor register ids, for internal use */
+/* Divisor/prescaler register id's, for internal use. */
 #define CMU_NODIV_REG              0
-#define CMU_HFPERCLKDIV_REG        1
-#define CMU_HFCORECLKDIV_REG       2
-#define CMU_LFAPRESC0_REG          3
-#define CMU_LFBPRESC0_REG          4
-#if defined( _CMU_CTRL_HFCLKDIV_MASK )
-#define CMU_HFCLKDIV_REG           5
-#endif
-#define CMU_DIV_REG_POS            4
-#define CMU_DIV_REG_MASK           0xf
+#define CMU_NOPRESC_REG            0
+#define CMU_HFPRESC_REG            1
+#define CMU_HFCLKDIV_REG           1
+#define CMU_HFEXPPRESC_REG         2
+#define CMU_HFCLKLEPRESC_REG       3
+#define CMU_HFPERPRESC_REG         4
+#define CMU_HFPERCLKDIV_REG        4
+#define CMU_HFCOREPRESC_REG        5
+#define CMU_HFCORECLKDIV_REG       5
+#define CMU_HFRADIOPRESC_REG       6
+#define CMU_LFAPRESC0_REG          7
+#define CMU_LFBPRESC0_REG          8
+#define CMU_LFEPRESC0_REG          9
 
-/* Enable register ids, for internal use */
+#define CMU_PRESC_REG_POS          4
+#define CMU_DIV_REG_POS            CMU_PRESC_REG_POS
+#define CMU_PRESC_REG_MASK         0xf
+#define CMU_DIV_REG_MASK           CMU_PRESC_REG_MASK
+
+/* Enable register id's, for internal use. */
 #define CMU_NO_EN_REG              0
+#define CMU_CTRL_EN_REG            1
 #define CMU_HFPERCLKDIV_EN_REG     1
 #define CMU_HFPERCLKEN0_EN_REG     2
 #define CMU_HFCORECLKEN0_EN_REG    3
-#define CMU_LFACLKEN0_EN_REG       4
-#define CMU_LFBCLKEN0_EN_REG       5
-#define CMU_PCNT_EN_REG            6
-#if defined( _CMU_LFCCLKEN0_MASK )
-#define CMU_LFCCLKEN0_EN_REG       7
-#endif
+#define CMU_HFRADIOCLKEN0_EN_REG   4
+#define CMU_HFBUSCLKEN0_EN_REG     5
+#define CMU_LFACLKEN0_EN_REG       6
+#define CMU_LFBCLKEN0_EN_REG       7
+#define CMU_LFCCLKEN0_EN_REG       8
+#define CMU_LFECLKEN0_EN_REG       9
+#define CMU_PCNT_EN_REG            10
 
 #define CMU_EN_REG_POS             8
 #define CMU_EN_REG_MASK            0xf
 
-/* Enable register bit position, for internal use */
+/* Enable register bit positions, for internal use. */
 #define CMU_EN_BIT_POS             12
 #define CMU_EN_BIT_MASK            0x1f
 
-/* Clock branch bitfield position, for internal use */
+/* Clock branch bitfield positions, for internal use. */
 #define CMU_HF_CLK_BRANCH          0
-#define CMU_HFPER_CLK_BRANCH       1
-#define CMU_HFCORE_CLK_BRANCH      2
-#define CMU_LFA_CLK_BRANCH         3
-#define CMU_RTC_CLK_BRANCH         4
-#define CMU_LETIMER_CLK_BRANCH     5
-#define CMU_LCDPRE_CLK_BRANCH      6
-#define CMU_LCD_CLK_BRANCH         7
-#define CMU_LESENSE_CLK_BRANCH     8
-#define CMU_LFB_CLK_BRANCH         9
+#define CMU_HFCORE_CLK_BRANCH      1
+#define CMU_HFPER_CLK_BRANCH       2
+#define CMU_HFRADIO_CLK_BRANCH     3
+#define CMU_HFBUS_CLK_BRANCH       4
+#define CMU_HFEXP_CLK_BRANCH       5
+#define CMU_DBG_CLK_BRANCH         6
+#define CMU_AUX_CLK_BRANCH         7
+#define CMU_RTC_CLK_BRANCH         8
+#define CMU_RTCC_CLK_BRANCH        8
+#define CMU_LETIMER_CLK_BRANCH     9
+#define CMU_LETIMER0_CLK_BRANCH    9
 #define CMU_LEUART0_CLK_BRANCH     10
 #define CMU_LEUART1_CLK_BRANCH     11
-#define CMU_DBG_CLK_BRANCH         12
-#define CMU_AUX_CLK_BRANCH         13
-#define CMU_USBC_CLK_BRANCH        14
-#define CMU_LFC_CLK_BRANCH         15
-#define CMU_USBLE_CLK_BRANCH       16
+#define CMU_LFA_CLK_BRANCH         12
+#define CMU_LFB_CLK_BRANCH         13
+#define CMU_LFC_CLK_BRANCH         14
+#define CMU_LFE_CLK_BRANCH         15
+#define CMU_USBC_CLK_BRANCH        16
+#define CMU_USBLE_CLK_BRANCH       17
+#define CMU_LCDPRE_CLK_BRANCH      18
+#define CMU_LCD_CLK_BRANCH         19
+#define CMU_LESENSE_CLK_BRANCH     20
 
 #define CMU_CLK_BRANCH_POS         17
 #define CMU_CLK_BRANCH_MASK        0x1f
@@ -152,43 +165,37 @@
 /** Clock divider configuration */
 typedef uint32_t CMU_ClkDiv_TypeDef;
 
-/** High frequency RC bands. */
+#if defined( _SILICON_LABS_32B_PLATFORM_2 )
+/** Clockprescaler configuration */
+typedef uint32_t CMU_ClkPresc_TypeDef;
+#endif
+
+#if defined( _CMU_HFRCOCTRL_BAND_MASK )
+/** High frequency system RCO bands */
 typedef enum
 {
-  /** 1MHz RC band. */
-  cmuHFRCOBand_1MHz  = _CMU_HFRCOCTRL_BAND_1MHZ,
-  /** 7MHz RC band. */
-  cmuHFRCOBand_7MHz  = _CMU_HFRCOCTRL_BAND_7MHZ,
-  /** 11MHz RC band. */
-  cmuHFRCOBand_11MHz = _CMU_HFRCOCTRL_BAND_11MHZ,
-  /** 14MHz RC band. */
-  cmuHFRCOBand_14MHz = _CMU_HFRCOCTRL_BAND_14MHZ,
-  /** 21MHz RC band. */
-  cmuHFRCOBand_21MHz = _CMU_HFRCOCTRL_BAND_21MHZ,
-#if defined( _CMU_HFRCOCTRL_BAND_28MHZ )
-  /** 28MHz RC band. */
-  cmuHFRCOBand_28MHz = _CMU_HFRCOCTRL_BAND_28MHZ
+  cmuHFRCOBand_1MHz  = _CMU_HFRCOCTRL_BAND_1MHZ,      /**< 1MHz HFRCO band  */
+  cmuHFRCOBand_7MHz  = _CMU_HFRCOCTRL_BAND_7MHZ,      /**< 7MHz HFRCO band  */
+  cmuHFRCOBand_11MHz = _CMU_HFRCOCTRL_BAND_11MHZ,     /**< 11MHz HFRCO band */
+  cmuHFRCOBand_14MHz = _CMU_HFRCOCTRL_BAND_14MHZ,     /**< 14MHz HFRCO band */
+  cmuHFRCOBand_21MHz = _CMU_HFRCOCTRL_BAND_21MHZ,     /**< 21MHz HFRCO band */
+#if defined( CMU_HFRCOCTRL_BAND_28MHZ )
+  cmuHFRCOBand_28MHz = _CMU_HFRCOCTRL_BAND_28MHZ,     /**< 28MHz HFRCO band */
 #endif
 } CMU_HFRCOBand_TypeDef;
-
+#endif /* _CMU_HFRCOCTRL_BAND_MASK */
 
 #if defined( _CMU_AUXHFRCOCTRL_BAND_MASK )
-/** AUX High frequency RC bands. */
+/** AUX High frequency RCO bands */
 typedef enum
 {
-  /** 1MHz RC band. */
-  cmuAUXHFRCOBand_1MHz  = _CMU_AUXHFRCOCTRL_BAND_1MHZ,
-  /** 7MHz RC band. */
-  cmuAUXHFRCOBand_7MHz  = _CMU_AUXHFRCOCTRL_BAND_7MHZ,
-  /** 11MHz RC band. */
-  cmuAUXHFRCOBand_11MHz = _CMU_AUXHFRCOCTRL_BAND_11MHZ,
-  /** 14MHz RC band. */
-  cmuAUXHFRCOBand_14MHz = _CMU_AUXHFRCOCTRL_BAND_14MHZ,
-  /** 21MHz RC band. */
-  cmuAUXHFRCOBand_21MHz = _CMU_AUXHFRCOCTRL_BAND_21MHZ,
-#if defined( _CMU_AUXHFRCOCTRL_BAND_28MHZ )
-  /** 28MHz RC band. */
-  cmuAUXHFRCOBand_28MHz = _CMU_AUXHFRCOCTRL_BAND_28MHZ
+  cmuAUXHFRCOBand_1MHz  = _CMU_AUXHFRCOCTRL_BAND_1MHZ,  /**< 1MHz RC band  */
+  cmuAUXHFRCOBand_7MHz  = _CMU_AUXHFRCOCTRL_BAND_7MHZ,  /**< 7MHz RC band  */
+  cmuAUXHFRCOBand_11MHz = _CMU_AUXHFRCOCTRL_BAND_11MHZ, /**< 11MHz RC band */
+  cmuAUXHFRCOBand_14MHz = _CMU_AUXHFRCOCTRL_BAND_14MHZ, /**< 14MHz RC band */
+  cmuAUXHFRCOBand_21MHz = _CMU_AUXHFRCOCTRL_BAND_21MHZ, /**< 21MHz RC band */
+#if defined( CMU_AUXHFRCOCTRL_BAND_28MHZ )
+  cmuAUXHFRCOBand_28MHz = _CMU_AUXHFRCOCTRL_BAND_28MHZ, /**< 28MHz RC band */
 #endif
 } CMU_AUXHFRCOBand_TypeDef;
 #endif
@@ -204,6 +211,46 @@
 } CMU_USHFRCOBand_TypeDef;
 #endif
 
+#if defined( _CMU_HFRCOCTRL_FREQRANGE_MASK )
+/** High frequency system RCO bands */
+typedef enum
+{
+  cmuHFRCOFreq_1M0Hz            = 1000000U,             /**< 1MHz RC band   */
+  cmuHFRCOFreq_2M0Hz            = 2000000U,             /**< 2MHz RC band   */
+  cmuHFRCOFreq_4M0Hz            = 4000000U,             /**< 4MHz RC band   */
+  cmuHFRCOFreq_7M0Hz            = 7000000U,             /**< 7MHz RC band   */
+  cmuHFRCOFreq_13M0Hz           = 13000000U,            /**< 13MHz RC band  */
+  cmuHFRCOFreq_16M0Hz           = 16000000U,            /**< 16MHz RC band  */
+  cmuHFRCOFreq_19M0Hz           = 19000000U,            /**< 19MHz RC band  */
+  cmuHFRCOFreq_26M0Hz           = 26000000U,            /**< 26MHz RC band  */
+  cmuHFRCOFreq_32M0Hz           = 32000000U,            /**< 32MHz RC band  */
+  cmuHFRCOFreq_38M0Hz           = 38000000U,            /**< 38MHz RC band  */
+  cmuHFRCOFreq_UserDefined      = 0,
+} CMU_HFRCOFreq_TypeDef;
+#define CMU_HFRCO_MIN           cmuHFRCOFreq_1M0Hz
+#define CMU_HFRCO_MAX           cmuHFRCOFreq_38M0Hz
+#endif
+
+#if defined( _CMU_AUXHFRCOCTRL_FREQRANGE_MASK )
+/** AUX High frequency RCO bands */
+typedef enum
+{
+  cmuAUXHFRCOFreq_1M0Hz         = 1000000U,             /**< 1MHz RC band   */
+  cmuAUXHFRCOFreq_2M0Hz         = 2000000U,             /**< 2MHz RC band   */
+  cmuAUXHFRCOFreq_4M0Hz         = 4000000U,             /**< 4MHz RC band   */
+  cmuAUXHFRCOFreq_7M0Hz         = 7000000U,             /**< 7MHz RC band   */
+  cmuAUXHFRCOFreq_13M0Hz        = 13000000U,            /**< 13MHz RC band  */
+  cmuAUXHFRCOFreq_16M0Hz        = 16000000U,            /**< 16MHz RC band  */
+  cmuAUXHFRCOFreq_19M0Hz        = 19000000U,            /**< 19MHz RC band  */
+  cmuAUXHFRCOFreq_26M0Hz        = 26000000U,            /**< 26MHz RC band  */
+  cmuAUXHFRCOFreq_32M0Hz        = 32000000U,            /**< 32MHz RC band  */
+  cmuAUXHFRCOFreq_38M0Hz        = 38000000U,            /**< 38MHz RC band  */
+  cmuAUXHFRCOFreq_UserDefined   = 0,
+} CMU_AUXHFRCOFreq_TypeDef;
+#define CMU_AUXHFRCO_MIN        cmuAUXHFRCOFreq_1M0Hz
+#define CMU_AUXHFRCO_MAX        cmuAUXHFRCOFreq_38M0Hz
+#endif
+
 
 /** Clock points in CMU. Please refer to CMU overview in reference manual. */
 typedef enum
@@ -213,223 +260,365 @@
   /*******************/
 
   /** High frequency clock */
-#if defined( _CMU_CTRL_HFCLKDIV_MASK )
-  cmuClock_HF = (CMU_HFCLKDIV_REG << CMU_DIV_REG_POS) |
-                (CMU_HFCLKSEL_REG << CMU_SEL_REG_POS) |
-                (CMU_NO_EN_REG << CMU_EN_REG_POS) |
-                (0 << CMU_EN_BIT_POS) |
-                (CMU_HF_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+#if defined( _CMU_CTRL_HFCLKDIV_MASK ) \
+    || defined( _CMU_HFPRESC_MASK )
+  cmuClock_HF = (CMU_HFCLKDIV_REG << CMU_DIV_REG_POS)
+                | (CMU_HFCLKSEL_REG << CMU_SEL_REG_POS)
+                | (CMU_NO_EN_REG << CMU_EN_REG_POS)
+                | (0 << CMU_EN_BIT_POS)
+                | (CMU_HF_CLK_BRANCH << CMU_CLK_BRANCH_POS),
 #else
-  cmuClock_HF = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
-                (CMU_HFCLKSEL_REG << CMU_SEL_REG_POS) |
-                (CMU_NO_EN_REG << CMU_EN_REG_POS) |
-                (0 << CMU_EN_BIT_POS) |
-                (CMU_HF_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+  cmuClock_HF = (CMU_NODIV_REG << CMU_DIV_REG_POS)
+                | (CMU_HFCLKSEL_REG << CMU_SEL_REG_POS)
+                | (CMU_NO_EN_REG << CMU_EN_REG_POS)
+                | (0 << CMU_EN_BIT_POS)
+                | (CMU_HF_CLK_BRANCH << CMU_CLK_BRANCH_POS),
 #endif
 
   /** Debug clock */
-  cmuClock_DBG = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
-                 (CMU_DBGCLKSEL_REG << CMU_SEL_REG_POS) |
-                 (CMU_NO_EN_REG << CMU_EN_REG_POS) |
-                 (0 << CMU_EN_BIT_POS) |
-                 (CMU_DBG_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+  cmuClock_DBG = (CMU_NODIV_REG << CMU_DIV_REG_POS)
+                 | (CMU_DBGCLKSEL_REG << CMU_SEL_REG_POS)
+                 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
+                 | (0 << CMU_EN_BIT_POS)
+                 | (CMU_DBG_CLK_BRANCH << CMU_CLK_BRANCH_POS),
 
   /** AUX clock */
-  cmuClock_AUX = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
-                 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
-                 (CMU_NO_EN_REG << CMU_EN_REG_POS) |
-                 (0 << CMU_EN_BIT_POS) |
-                 (CMU_AUX_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+  cmuClock_AUX = (CMU_NODIV_REG << CMU_DIV_REG_POS)
+                 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+                 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
+                 | (0 << CMU_EN_BIT_POS)
+                 | (CMU_AUX_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+
+#if defined( _CMU_HFEXPPRESC_MASK )
+  /**********************/
+  /* HF export sub-branch */
+  /**********************/
+
+  /** Export clock */
+  cmuClock_EXPORT = (CMU_HFEXPPRESC_REG << CMU_PRESC_REG_POS)
+                    | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+                    | (CMU_NO_EN_REG << CMU_EN_REG_POS)
+                    | (0 << CMU_EN_BIT_POS)
+                    | (CMU_HFEXP_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+#endif
+
+#if defined( _CMU_HFBUSCLKEN0_MASK )
+/**********************************/
+  /* HF bus clock sub-branch */
+  /**********************************/
+
+  /** High frequency bus clock. */
+  cmuClock_BUS = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
+                 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+                 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
+                 | (0 << CMU_EN_BIT_POS)
+                 | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+
+#if defined( CMU_HFBUSCLKEN0_CRYPTO )
+  /** Cryptography accelerator clock. */
+  cmuClock_CRYPTO = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
+                    | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+                    | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
+                    | (_CMU_HFBUSCLKEN0_CRYPTO_SHIFT << CMU_EN_BIT_POS)
+                    | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+#endif
+
+#if defined( CMU_HFBUSCLKEN0_LDMA )
+  /** Direct memory access controller clock. */
+  cmuClock_LDMA = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
+                  | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+                  | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
+                  | (_CMU_HFBUSCLKEN0_LDMA_SHIFT << CMU_EN_BIT_POS)
+                  | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+#endif
+
+#if defined( CMU_HFBUSCLKEN0_GPCRC )
+  /** General purpose cyclic redundancy checksum clock. */
+  cmuClock_GPCRC = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
+                   | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+                   | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
+                   | (_CMU_HFBUSCLKEN0_GPCRC_SHIFT << CMU_EN_BIT_POS)
+                   | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+#endif
+
+#if defined( CMU_HFBUSCLKEN0_GPIO )
+  /** General purpose input/output clock. */
+  cmuClock_GPIO = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
+                  | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+                  | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
+                  | (_CMU_HFBUSCLKEN0_GPIO_SHIFT << CMU_EN_BIT_POS)
+                  | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+#endif
+
+  /** Low energy clocking module clock. */
+  cmuClock_CORELE = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
+                    | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+                    | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
+                    | (_CMU_HFBUSCLKEN0_LE_SHIFT << CMU_EN_BIT_POS)
+                    | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+
+#if defined( CMU_HFBUSCLKEN0_PRS )
+  /** Peripheral reflex system clock. */
+  cmuClock_PRS = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
+                 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+                 | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
+                 | (_CMU_HFBUSCLKEN0_PRS_SHIFT << CMU_EN_BIT_POS)
+                 | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+#endif
+#endif
 
   /**********************************/
   /* HF peripheral clock sub-branch */
   /**********************************/
 
   /** High frequency peripheral clock */
-  cmuClock_HFPER = (CMU_HFPERCLKDIV_REG << CMU_DIV_REG_POS) |
-                   (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
-                   (CMU_HFPERCLKDIV_EN_REG << CMU_EN_REG_POS) |
-                   (_CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT << CMU_EN_BIT_POS) |
-                   (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+#if defined( _CMU_HFPRESC_MASK )
+  cmuClock_HFPER = (CMU_HFPERPRESC_REG << CMU_PRESC_REG_POS)
+                   | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+                   | (CMU_CTRL_EN_REG << CMU_EN_REG_POS)
+                   | (_CMU_CTRL_HFPERCLKEN_SHIFT << CMU_EN_BIT_POS)
+                   | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+#else
+  cmuClock_HFPER = (CMU_HFPERCLKDIV_REG << CMU_DIV_REG_POS)
+                   | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+                   | (CMU_HFPERCLKDIV_EN_REG << CMU_EN_REG_POS)
+                   | (_CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT << CMU_EN_BIT_POS)
+                   | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+#endif
 
-#if defined(_CMU_HFPERCLKEN0_USART0_MASK)
+#if defined( CMU_HFPERCLKEN0_USART0 )
   /** Universal sync/async receiver/transmitter 0 clock. */
-  cmuClock_USART0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
-                    (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
-                    (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
-                    (_CMU_HFPERCLKEN0_USART0_SHIFT << CMU_EN_BIT_POS) |
-                    (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+  cmuClock_USART0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
+                    | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+                    | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
+                    | (_CMU_HFPERCLKEN0_USART0_SHIFT << CMU_EN_BIT_POS)
+                    | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
 #endif
 
-#if defined(_CMU_HFPERCLKEN0_USARTRF0_MASK)
+#if defined( CMU_HFPERCLKEN0_USARTRF0 )
   /** Universal sync/async receiver/transmitter 0 clock. */
-  cmuClock_USARTRF0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
-                    (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
-                    (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
-                    (_CMU_HFPERCLKEN0_USARTRF0_SHIFT << CMU_EN_BIT_POS) |
-                    (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+  cmuClock_USARTRF0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
+                      | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+                      | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
+                      | (_CMU_HFPERCLKEN0_USARTRF0_SHIFT << CMU_EN_BIT_POS)
+                      | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
 #endif
 
-#if defined(_CMU_HFPERCLKEN0_USART1_MASK)
-  /** Universal sync/async receiver/transmitter 1 clock. */
-  cmuClock_USART1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
-                    (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
-                    (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
-                    (_CMU_HFPERCLKEN0_USART1_SHIFT << CMU_EN_BIT_POS) |
-                    (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+#if defined( CMU_HFPERCLKEN0_USARTRF1 )
+  /** Universal sync/async receiver/transmitter 0 clock. */
+  cmuClock_USARTRF1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
+                      | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+                      | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
+                      | (_CMU_HFPERCLKEN0_USARTRF1_SHIFT << CMU_EN_BIT_POS)
+                      | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
 #endif
 
-#if defined(_CMU_HFPERCLKEN0_USART2_MASK)
+#if defined( CMU_HFPERCLKEN0_USART1 )
+  /** Universal sync/async receiver/transmitter 1 clock. */
+  cmuClock_USART1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
+                    | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+                    | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
+                    | (_CMU_HFPERCLKEN0_USART1_SHIFT << CMU_EN_BIT_POS)
+                    | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+#endif
+
+#if defined( CMU_HFPERCLKEN0_USART2 )
   /** Universal sync/async receiver/transmitter 2 clock. */
-  cmuClock_USART2 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
-                    (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
-                    (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
-                    (_CMU_HFPERCLKEN0_USART2_SHIFT << CMU_EN_BIT_POS) |
-                    (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+  cmuClock_USART2 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
+                    | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+                    | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
+                    | (_CMU_HFPERCLKEN0_USART2_SHIFT << CMU_EN_BIT_POS)
+                    | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
 #endif
 
-#if defined(_CMU_HFPERCLKEN0_UART0_MASK)
-  /** Universal async receiver/transmitter 0 clock. */
-  cmuClock_UART0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
-                   (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
-                   (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
-                   (_CMU_HFPERCLKEN0_UART0_SHIFT << CMU_EN_BIT_POS) |
-                   (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+#if defined( CMU_HFPERCLKEN0_USART3 )
+  /** Universal sync/async receiver/transmitter 3 clock. */
+  cmuClock_USART3 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
+                    | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+                    | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
+                    | (_CMU_HFPERCLKEN0_USART3_SHIFT << CMU_EN_BIT_POS)
+                    | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
 #endif
 
-#if defined(_CMU_HFPERCLKEN0_UART1_MASK)
-  /** Universal async receiver/transmitter 1 clock. */
-  cmuClock_UART1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
-                   (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
-                   (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
-                   (_CMU_HFPERCLKEN0_UART1_SHIFT << CMU_EN_BIT_POS) |
-                   (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+#if defined( CMU_HFPERCLKEN0_USART4 )
+  /** Universal sync/async receiver/transmitter 4 clock. */
+  cmuClock_USART4 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
+                    | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+                    | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
+                    | (_CMU_HFPERCLKEN0_USART4_SHIFT << CMU_EN_BIT_POS)
+                    | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+#endif
+
+#if defined( CMU_HFPERCLKEN0_USART5 )
+  /** Universal sync/async receiver/transmitter 5 clock. */
+  cmuClock_USART5 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
+                    | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+                    | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
+                    | (_CMU_HFPERCLKEN0_USART5_SHIFT << CMU_EN_BIT_POS)
+                    | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
 #endif
 
-#if defined(_CMU_HFPERCLKEN0_TIMER0_MASK)
-  /** Timer 0 clock. */
-  cmuClock_TIMER0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
-                    (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
-                    (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
-                    (_CMU_HFPERCLKEN0_TIMER0_SHIFT << CMU_EN_BIT_POS) |
-                    (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+
+#if defined( CMU_HFPERCLKEN0_UART0 )
+  /** Universal async receiver/transmitter 0 clock. */
+  cmuClock_UART0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
+                   | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+                   | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
+                   | (_CMU_HFPERCLKEN0_UART0_SHIFT << CMU_EN_BIT_POS)
+                   | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
 #endif
 
-#if defined(_CMU_HFPERCLKEN0_TIMER1_MASK)
-  /** Timer 1 clock. */
-  cmuClock_TIMER1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
-                    (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
-                    (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
-                    (_CMU_HFPERCLKEN0_TIMER1_SHIFT << CMU_EN_BIT_POS) |
-                    (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+#if defined( CMU_HFPERCLKEN0_UART1 )
+  /** Universal async receiver/transmitter 1 clock. */
+  cmuClock_UART1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
+                   | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+                   | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
+                   | (_CMU_HFPERCLKEN0_UART1_SHIFT << CMU_EN_BIT_POS)
+                   | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
 #endif
 
-#if defined(_CMU_HFPERCLKEN0_TIMER2_MASK)
-  /** Timer 2 clock. */
-  cmuClock_TIMER2 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
-                    (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
-                    (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
-                    (_CMU_HFPERCLKEN0_TIMER2_SHIFT << CMU_EN_BIT_POS) |
-                    (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+#if defined( CMU_HFPERCLKEN0_TIMER0 )
+  /** Timer 0 clock. */
+  cmuClock_TIMER0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
+                    | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+                    | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
+                    | (_CMU_HFPERCLKEN0_TIMER0_SHIFT << CMU_EN_BIT_POS)
+                    | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+#endif
+
+#if defined( CMU_HFPERCLKEN0_TIMER1 )
+  /** Timer 1 clock. */
+  cmuClock_TIMER1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
+                    | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+                    | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
+                    | (_CMU_HFPERCLKEN0_TIMER1_SHIFT << CMU_EN_BIT_POS)
+                    | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
 #endif
 
-#if defined(_CMU_HFPERCLKEN0_TIMER3_MASK)
-  /** Timer 3 clock. */
-  cmuClock_TIMER3 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
-                    (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
-                    (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
-                    (_CMU_HFPERCLKEN0_TIMER3_SHIFT << CMU_EN_BIT_POS) |
-                    (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+#if defined( CMU_HFPERCLKEN0_TIMER2 )
+  /** Timer 2 clock. */
+  cmuClock_TIMER2 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
+                    | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+                    | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
+                    | (_CMU_HFPERCLKEN0_TIMER2_SHIFT << CMU_EN_BIT_POS)
+                    | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
 #endif
 
-#if defined(_CMU_HFPERCLKEN0_ACMP0_MASK)
-  /** Analog comparator 0 clock. */
-  cmuClock_ACMP0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
-                   (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
-                   (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
-                   (_CMU_HFPERCLKEN0_ACMP0_SHIFT << CMU_EN_BIT_POS) |
-                   (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+#if defined( CMU_HFPERCLKEN0_TIMER3 )
+  /** Timer 3 clock. */
+  cmuClock_TIMER3 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
+                    | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+                    | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
+                    | (_CMU_HFPERCLKEN0_TIMER3_SHIFT << CMU_EN_BIT_POS)
+                    | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
 #endif
 
-#if defined(_CMU_HFPERCLKEN0_ACMP1_MASK)
-  /** Analog comparator 1 clock. */
-  cmuClock_ACMP1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
-                   (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
-                   (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
-                   (_CMU_HFPERCLKEN0_ACMP1_SHIFT << CMU_EN_BIT_POS) |
-                   (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+#if defined( CMU_HFPERCLKEN0_CRYOTIMER )
+  /** CRYOtimer clock. */
+  cmuClock_CRYOTIMER = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
+                       | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+                       | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
+                       | (_CMU_HFPERCLKEN0_CRYOTIMER_SHIFT << CMU_EN_BIT_POS)
+                       | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
 #endif
 
-#if defined(_CMU_HFPERCLKEN0_PRS_MASK)
-  /** Peripheral reflex system clock. */
-  cmuClock_PRS = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
-                 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
-                 (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
-                 (_CMU_HFPERCLKEN0_PRS_SHIFT << CMU_EN_BIT_POS) |
-                 (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+#if defined( CMU_HFPERCLKEN0_ACMP0 )
+  /** Analog comparator 0 clock. */
+  cmuClock_ACMP0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
+                   | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+                   | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
+                   | (_CMU_HFPERCLKEN0_ACMP0_SHIFT << CMU_EN_BIT_POS)
+                   | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
 #endif
 
-#if defined(_CMU_HFPERCLKEN0_DAC0_MASK)
-  /** Digital to analog converter 0 clock. */
-  cmuClock_DAC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
-                  (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
-                  (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
-                  (_CMU_HFPERCLKEN0_DAC0_SHIFT << CMU_EN_BIT_POS) |
-                  (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+#if defined( CMU_HFPERCLKEN0_ACMP1 )
+  /** Analog comparator 1 clock. */
+  cmuClock_ACMP1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
+                   | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+                   | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
+                   | (_CMU_HFPERCLKEN0_ACMP1_SHIFT << CMU_EN_BIT_POS)
+                   | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+#endif
+
+#if defined( CMU_HFPERCLKEN0_PRS )
+  /** Peripheral reflex system clock. */
+  cmuClock_PRS = (CMU_NODIV_REG << CMU_DIV_REG_POS)
+                 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+                 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
+                 | (_CMU_HFPERCLKEN0_PRS_SHIFT << CMU_EN_BIT_POS)
+                 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
 #endif
 
-#if defined(_CMU_HFPERCLKEN0_IDAC0_MASK)
+#if defined( CMU_HFPERCLKEN0_DAC0 )
   /** Digital to analog converter 0 clock. */
-  cmuClock_IDAC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
-                  (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
-                  (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
-                  (_CMU_HFPERCLKEN0_IDAC0_SHIFT << CMU_EN_BIT_POS) |
-                  (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+  cmuClock_DAC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
+                  | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+                  | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
+                  | (_CMU_HFPERCLKEN0_DAC0_SHIFT << CMU_EN_BIT_POS)
+                  | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
 #endif
 
-#if defined(GPIO_PRESENT)
+#if defined( CMU_HFPERCLKEN0_IDAC0 )
+  /** Digital to analog converter 0 clock. */
+  cmuClock_IDAC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
+                   | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+                   | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
+                   | (_CMU_HFPERCLKEN0_IDAC0_SHIFT << CMU_EN_BIT_POS)
+                   | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+#endif
+
+#if defined( CMU_HFPERCLKEN0_GPIO )
   /** General purpose input/output clock. */
-  cmuClock_GPIO = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
-                  (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
-                  (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
-                  (_CMU_HFPERCLKEN0_GPIO_SHIFT << CMU_EN_BIT_POS) |
-                  (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+  cmuClock_GPIO = (CMU_NODIV_REG << CMU_DIV_REG_POS)
+                  | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+                  | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
+                  | (_CMU_HFPERCLKEN0_GPIO_SHIFT << CMU_EN_BIT_POS)
+                  | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
 #endif
 
-#if defined(VCMP_PRESENT)
+#if defined( CMU_HFPERCLKEN0_VCMP )
   /** Voltage comparator clock. */
-  cmuClock_VCMP = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
-                  (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
-                  (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
-                  (_CMU_HFPERCLKEN0_VCMP_SHIFT << CMU_EN_BIT_POS) |
-                  (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+  cmuClock_VCMP = (CMU_NODIV_REG << CMU_DIV_REG_POS)
+                  | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+                  | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
+                  | (_CMU_HFPERCLKEN0_VCMP_SHIFT << CMU_EN_BIT_POS)
+                  | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+#endif
+
+#if defined( CMU_HFPERCLKEN0_ADC0 )
+  /** Analog to digital converter 0 clock. */
+  cmuClock_ADC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
+                  | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+                  | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
+                  | (_CMU_HFPERCLKEN0_ADC0_SHIFT << CMU_EN_BIT_POS)
+                  | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
 #endif
 
-#if defined(_CMU_HFPERCLKEN0_ADC0_MASK)
-  /** Analog to digital converter 0 clock. */
-  cmuClock_ADC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
-                  (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
-                  (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
-                  (_CMU_HFPERCLKEN0_ADC0_SHIFT << CMU_EN_BIT_POS) |
-                  (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+#if defined( CMU_HFPERCLKEN0_I2C0 )
+  /** I2C 0 clock. */
+  cmuClock_I2C0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
+                  | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+                  | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
+                  | (_CMU_HFPERCLKEN0_I2C0_SHIFT << CMU_EN_BIT_POS)
+                  | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
 #endif
 
-#if defined(_CMU_HFPERCLKEN0_I2C0_MASK)
-  /** I2C 0 clock. */
-  cmuClock_I2C0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
-                  (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
-                  (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
-                  (_CMU_HFPERCLKEN0_I2C0_SHIFT << CMU_EN_BIT_POS) |
-                  (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+#if defined( CMU_HFPERCLKEN0_I2C1 )
+  /** I2C 1 clock. */
+  cmuClock_I2C1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
+                  | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+                  | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
+                  | (_CMU_HFPERCLKEN0_I2C1_SHIFT << CMU_EN_BIT_POS)
+                  | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
 #endif
 
-#if defined(_CMU_HFPERCLKEN0_I2C1_MASK)
-  /** I2C 1 clock. */
-  cmuClock_I2C1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
-                  (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
-                  (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
-                  (_CMU_HFPERCLKEN0_I2C1_SHIFT << CMU_EN_BIT_POS) |
-                  (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+#if defined( CMU_HFPERCLKEN0_I2C2 )
+  /** I2C 2 clock. */
+  cmuClock_I2C2 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
+                  | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+                  | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
+                  | (_CMU_HFPERCLKEN0_I2C2_SHIFT << CMU_EN_BIT_POS)
+                  | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
 #endif
 
   /**********************/
@@ -437,62 +626,150 @@
   /**********************/
 
   /** Core clock */
-  cmuClock_CORE = (CMU_HFCORECLKDIV_REG << CMU_DIV_REG_POS) |
-                  (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
-                  (CMU_NO_EN_REG << CMU_EN_REG_POS) |
-                  (0 << CMU_EN_BIT_POS) |
-                  (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+  cmuClock_CORE = (CMU_HFCORECLKDIV_REG << CMU_DIV_REG_POS)
+                  | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+                  | (CMU_NO_EN_REG << CMU_EN_REG_POS)
+                  | (0 << CMU_EN_BIT_POS)
+                  | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
 
-#if defined(AES_PRESENT)
+#if defined( CMU_HFCORECLKEN0_AES )
   /** Advanced encryption standard accelerator clock. */
-  cmuClock_AES = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
-                 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
-                 (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) |
-                 (_CMU_HFCORECLKEN0_AES_SHIFT << CMU_EN_BIT_POS) |
-                 (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+  cmuClock_AES = (CMU_NODIV_REG << CMU_DIV_REG_POS)
+                 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+                 | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS)
+                 | (_CMU_HFCORECLKEN0_AES_SHIFT << CMU_EN_BIT_POS)
+                 | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+#endif
+
+#if defined( CMU_HFCORECLKEN0_DMA )
+  /** Direct memory access controller clock. */
+  cmuClock_DMA = (CMU_NODIV_REG << CMU_DIV_REG_POS)
+                 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+                 | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS)
+                 | (_CMU_HFCORECLKEN0_DMA_SHIFT << CMU_EN_BIT_POS)
+                 | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
 #endif
 
-#if defined(DMA_PRESENT)
-  /** Direct memory access controller clock. */
-  cmuClock_DMA = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
-                 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
-                 (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) |
-                 (_CMU_HFCORECLKEN0_DMA_SHIFT << CMU_EN_BIT_POS) |
-                 (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
-#endif
-  /** Low energy clocking module clock. */
-  cmuClock_CORELE = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
-                    (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
-                    (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) |
-                    (_CMU_HFCORECLKEN0_LE_SHIFT << CMU_EN_BIT_POS) |
-                    (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
-
-#if defined(EBI_PRESENT)
-  /** External bus interface clock. */
-  cmuClock_EBI = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
-                 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
-                 (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) |
-                 (_CMU_HFCORECLKEN0_EBI_SHIFT << CMU_EN_BIT_POS) |
-                 (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+#if defined( CMU_HFCORECLKEN0_LE )
+/** Low energy clocking module clock. */
+  cmuClock_CORELE = (CMU_NODIV_REG << CMU_DIV_REG_POS)
+                    | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+                    | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS)
+                    | (_CMU_HFCORECLKEN0_LE_SHIFT << CMU_EN_BIT_POS)
+                    | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
 #endif
 
-#if defined(USB_PRESENT)
+#if defined( CMU_HFCORECLKEN0_EBI )
+  /** External bus interface clock. */
+  cmuClock_EBI = (CMU_NODIV_REG << CMU_DIV_REG_POS)
+                 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+                 | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS)
+                 | (_CMU_HFCORECLKEN0_EBI_SHIFT << CMU_EN_BIT_POS)
+                 | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+#endif
+
+#if defined( CMU_HFCORECLKEN0_USBC )
   /** USB Core clock. */
-  cmuClock_USBC = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
-                  (CMU_USBCCLKSEL_REG << CMU_SEL_REG_POS) |
-                  (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) |
-                  (_CMU_HFCORECLKEN0_USBC_SHIFT << CMU_EN_BIT_POS) |
-                  (CMU_USBC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+  cmuClock_USBC = (CMU_NODIV_REG << CMU_DIV_REG_POS)
+                  | (CMU_USBCCLKSEL_REG << CMU_SEL_REG_POS)
+                  | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS)
+                  | (_CMU_HFCORECLKEN0_USBC_SHIFT << CMU_EN_BIT_POS)
+                  | (CMU_USBC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
 
 #endif
 
-#if defined(USB_PRESENT)
+#if defined( CMU_HFCORECLKEN0_USB )
   /** USB clock. */
-  cmuClock_USB = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
-                 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
-                 (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) |
-                 (_CMU_HFCORECLKEN0_USB_SHIFT << CMU_EN_BIT_POS) |
-                 (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+  cmuClock_USB = (CMU_NODIV_REG << CMU_DIV_REG_POS)
+                 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+                 | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS)
+                 | (_CMU_HFCORECLKEN0_USB_SHIFT << CMU_EN_BIT_POS)
+                 | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+#endif
+
+#if defined( CMU_CTRL_HFRADIOCLKEN )
+  /**********************************/
+  /* HF radio clock sub-branch */
+  /**********************************/
+
+  /** High frequency radio clock. */
+  cmuClock_RADIO = (CMU_HFRADIOPRESC_REG << CMU_PRESC_REG_POS)
+                   | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+                   | (CMU_CTRL_EN_REG << CMU_EN_REG_POS)
+                   | (_CMU_CTRL_HFRADIOCLKEN_SHIFT << CMU_EN_BIT_POS)
+                   | (CMU_HFRADIO_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+
+#if defined( CMU_HFRADIOCLKEN0_MODEM )
+  /** Modulator/demodulator clock. */
+  cmuClock_MODEM = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
+                   | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+                   | (CMU_HFRADIOCLKEN0_EN_REG << CMU_EN_REG_POS)
+                   | (_CMU_HFRADIOCLKEN0_MODEM_SHIFT << CMU_EN_BIT_POS)
+                   | (CMU_HFRADIO_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+#endif
+
+#if defined( CMU_HFRADIOCLKEN0_PROTIMER )
+  /** Protocol timer clock. */
+  cmuClock_PROTIMER = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
+                      | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+                      | (CMU_HFRADIOCLKEN0_EN_REG << CMU_EN_REG_POS)
+                      | (_CMU_HFRADIOCLKEN0_PROTIMER_SHIFT << CMU_EN_BIT_POS)
+                      | (CMU_HFRADIO_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+#endif
+
+#if defined( CMU_HFRADIOCLKEN0_CRC )
+  /** Cyclic Redundancy Check clock. */
+  cmuClock_CRC = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
+                 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+                 | (CMU_HFRADIOCLKEN0_EN_REG << CMU_EN_REG_POS)
+                 | (_CMU_HFRADIOCLKEN0_CRC_SHIFT << CMU_EN_BIT_POS)
+                 | (CMU_HFRADIO_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+#endif
+
+#if defined( CMU_HFRADIOCLKEN0_AGC )
+  /** Automatic Gain Control clock. */
+  cmuClock_AGC = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
+                 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+                 | (CMU_HFRADIOCLKEN0_EN_REG << CMU_EN_REG_POS)
+                 | (_CMU_HFRADIOCLKEN0_AGC_SHIFT << CMU_EN_BIT_POS)
+                 | (CMU_HFRADIO_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+#endif
+
+#if defined( CMU_HFRADIOCLKEN0_FRC )
+  /** Frame Controller clock. */
+  cmuClock_FRC = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
+                 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+                 | (CMU_HFRADIOCLKEN0_EN_REG << CMU_EN_REG_POS)
+                 | (_CMU_HFRADIOCLKEN0_FRC_SHIFT << CMU_EN_BIT_POS)
+                 | (CMU_HFRADIO_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+#endif
+
+#if defined( CMU_HFRADIOCLKEN0_SYNTH )
+  /** Frequency Synthesizer clock. */
+  cmuClock_SYNTH = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
+                   | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+                   | (CMU_HFRADIOCLKEN0_EN_REG << CMU_EN_REG_POS)
+                   | (_CMU_HFRADIOCLKEN0_SYNTH_SHIFT << CMU_EN_BIT_POS)
+                   | (CMU_HFRADIO_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+#endif
+
+#if defined( CMU_HFRADIOCLKEN0_BUFC )
+  /** Buffer Controller Check clock. */
+  cmuClock_BUFC = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
+                  | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+                  | (CMU_HFRADIOCLKEN0_EN_REG << CMU_EN_REG_POS)
+                  | (_CMU_HFRADIOCLKEN0_BUFC_SHIFT << CMU_EN_BIT_POS)
+                  | (CMU_HFRADIO_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+#endif
+
+#if defined( CMU_HFRADIOCLKEN0_RAC )
+  /** Radio Controller clock. */
+  cmuClock_RAC = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
+                 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+                 | (CMU_HFRADIOCLKEN0_EN_REG << CMU_EN_REG_POS)
+                 | (_CMU_HFRADIOCLKEN0_RAC_SHIFT << CMU_EN_BIT_POS)
+                 | (CMU_HFRADIO_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+#endif
 #endif
 
   /***************/
@@ -500,80 +777,80 @@
   /***************/
 
   /** Low frequency A clock */
-  cmuClock_LFA = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
-                 (CMU_LFACLKSEL_REG << CMU_SEL_REG_POS) |
-                 (CMU_NO_EN_REG << CMU_EN_REG_POS) |
-                 (0 << CMU_EN_BIT_POS) |
-                 (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+  cmuClock_LFA = (CMU_NODIV_REG << CMU_DIV_REG_POS)
+                 | (CMU_LFACLKSEL_REG << CMU_SEL_REG_POS)
+                 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
+                 | (0 << CMU_EN_BIT_POS)
+                 | (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS),
 
-#if defined(RTC_PRESENT)
+#if defined( CMU_LFACLKEN0_RTC )
   /** Real time counter clock. */
-  cmuClock_RTC = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS) |
-                 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
-                 (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS) |
-                 (_CMU_LFACLKEN0_RTC_SHIFT << CMU_EN_BIT_POS) |
-                 (CMU_RTC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+  cmuClock_RTC = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS)
+                 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+                 | (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS)
+                 | (_CMU_LFACLKEN0_RTC_SHIFT << CMU_EN_BIT_POS)
+                 | (CMU_RTC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
 #endif
 
-#if defined(_CMU_LFACLKEN0_LETIMER0_MASK)
+#if defined( CMU_LFACLKEN0_LETIMER0 )
   /** Low energy timer 0 clock. */
-  cmuClock_LETIMER0 = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS) |
-                      (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
-                      (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS) |
-                      (_CMU_LFACLKEN0_LETIMER0_SHIFT << CMU_EN_BIT_POS) |
-                      (CMU_LETIMER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+  cmuClock_LETIMER0 = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS)
+                      | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+                      | (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS)
+                      | (_CMU_LFACLKEN0_LETIMER0_SHIFT << CMU_EN_BIT_POS)
+                      | (CMU_LETIMER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
 #endif
 
-#if defined(_CMU_LFACLKEN0_LCD_MASK)
+#if defined( CMU_LFACLKEN0_LCD )
   /** Liquid crystal display, pre FDIV clock. */
-  cmuClock_LCDpre = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS) |
-                    (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
-                    (CMU_NO_EN_REG << CMU_EN_REG_POS) |
-                    (0 << CMU_EN_BIT_POS) |
-                    (CMU_LCDPRE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+  cmuClock_LCDpre = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS)
+                    | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+                    | (CMU_NO_EN_REG << CMU_EN_REG_POS)
+                    | (0 << CMU_EN_BIT_POS)
+                    | (CMU_LCDPRE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
 
   /** Liquid crystal display clock. Please notice that FDIV prescaler
    * must be set by special API. */
-  cmuClock_LCD = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
-                 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
-                 (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS) |
-                 (_CMU_LFACLKEN0_LCD_SHIFT << CMU_EN_BIT_POS) |
-                 (CMU_LCD_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+  cmuClock_LCD = (CMU_NODIV_REG << CMU_DIV_REG_POS)
+                 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+                 | (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS)
+                 | (_CMU_LFACLKEN0_LCD_SHIFT << CMU_EN_BIT_POS)
+                 | (CMU_LCD_CLK_BRANCH << CMU_CLK_BRANCH_POS),
 #endif
 
-#if defined(_CMU_PCNTCTRL_PCNT0CLKEN_MASK)
+#if defined( CMU_PCNTCTRL_PCNT0CLKEN )
   /** Pulse counter 0 clock. */
-  cmuClock_PCNT0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
-                   (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
-                   (CMU_PCNT_EN_REG << CMU_EN_REG_POS) |
-                   (_CMU_PCNTCTRL_PCNT0CLKEN_SHIFT << CMU_EN_BIT_POS) |
-                   (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+  cmuClock_PCNT0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
+                   | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+                   | (CMU_PCNT_EN_REG << CMU_EN_REG_POS)
+                   | (_CMU_PCNTCTRL_PCNT0CLKEN_SHIFT << CMU_EN_BIT_POS)
+                   | (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS),
 #endif
 
-#if defined(_CMU_PCNTCTRL_PCNT1CLKEN_MASK)
+#if defined( CMU_PCNTCTRL_PCNT1CLKEN )
   /** Pulse counter 1 clock. */
-  cmuClock_PCNT1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
-                   (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
-                   (CMU_PCNT_EN_REG << CMU_EN_REG_POS) |
-                   (_CMU_PCNTCTRL_PCNT1CLKEN_SHIFT << CMU_EN_BIT_POS) |
-                   (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+  cmuClock_PCNT1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
+                   | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+                   | (CMU_PCNT_EN_REG << CMU_EN_REG_POS)
+                   | (_CMU_PCNTCTRL_PCNT1CLKEN_SHIFT << CMU_EN_BIT_POS)
+                   | (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS),
 #endif
 
-#if defined(_CMU_PCNTCTRL_PCNT2CLKEN_MASK)
+#if defined( CMU_PCNTCTRL_PCNT2CLKEN )
   /** Pulse counter 2 clock. */
-  cmuClock_PCNT2 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
-                   (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
-                   (CMU_PCNT_EN_REG << CMU_EN_REG_POS) |
-                   (_CMU_PCNTCTRL_PCNT2CLKEN_SHIFT << CMU_EN_BIT_POS) |
-                   (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+  cmuClock_PCNT2 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
+                   | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+                   | (CMU_PCNT_EN_REG << CMU_EN_REG_POS)
+                   | (_CMU_PCNTCTRL_PCNT2CLKEN_SHIFT << CMU_EN_BIT_POS)
+                   | (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS),
 #endif
-#if defined(_CMU_LFACLKEN0_LESENSE_MASK)
+#if defined( CMU_LFACLKEN0_LESENSE )
   /** LESENSE clock. */
-  cmuClock_LESENSE = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS) |
-                     (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
-                     (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS) |
-                     (_CMU_LFACLKEN0_LESENSE_SHIFT << CMU_EN_BIT_POS) |
-                     (CMU_LESENSE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+  cmuClock_LESENSE = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS)
+                     | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+                     | (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS)
+                     | (_CMU_LFACLKEN0_LESENSE_SHIFT << CMU_EN_BIT_POS)
+                     | (CMU_LESENSE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
 #endif
 
   /***************/
@@ -581,50 +858,72 @@
   /***************/
 
   /** Low frequency B clock */
-  cmuClock_LFB = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
-                 (CMU_LFBCLKSEL_REG << CMU_SEL_REG_POS) |
-                 (CMU_NO_EN_REG << CMU_EN_REG_POS) |
-                 (0 << CMU_EN_BIT_POS) |
-                 (CMU_LFB_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+  cmuClock_LFB = (CMU_NODIV_REG << CMU_DIV_REG_POS)
+                 | (CMU_LFBCLKSEL_REG << CMU_SEL_REG_POS)
+                 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
+                 | (0 << CMU_EN_BIT_POS)
+                 | (CMU_LFB_CLK_BRANCH << CMU_CLK_BRANCH_POS),
 
-#if defined(_CMU_LFBCLKEN0_LEUART0_MASK)
+#if defined( CMU_LFBCLKEN0_LEUART0 )
   /** Low energy universal asynchronous receiver/transmitter 0 clock. */
-  cmuClock_LEUART0 = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS) |
-                     (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
-                     (CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS) |
-                     (_CMU_LFBCLKEN0_LEUART0_SHIFT << CMU_EN_BIT_POS) |
-                     (CMU_LEUART0_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+  cmuClock_LEUART0 = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS)
+                     | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+                     | (CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS)
+                     | (_CMU_LFBCLKEN0_LEUART0_SHIFT << CMU_EN_BIT_POS)
+                     | (CMU_LEUART0_CLK_BRANCH << CMU_CLK_BRANCH_POS),
 #endif
 
-#if defined(_CMU_LFBCLKEN0_LEUART1_MASK)
+#if defined( CMU_LFBCLKEN0_LEUART1 )
   /** Low energy universal asynchronous receiver/transmitter 1 clock. */
-  cmuClock_LEUART1 = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS) |
-                     (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
-                     (CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS) |
-                     (_CMU_LFBCLKEN0_LEUART1_SHIFT << CMU_EN_BIT_POS) |
-                     (CMU_LEUART1_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+  cmuClock_LEUART1 = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS)
+                     | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+                     | (CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS)
+                     | (_CMU_LFBCLKEN0_LEUART1_SHIFT << CMU_EN_BIT_POS)
+                     | (CMU_LEUART1_CLK_BRANCH << CMU_CLK_BRANCH_POS),
 #endif
 
+#if defined( _CMU_LFCCLKEN0_MASK )
   /***************/
   /* LF C branch */
   /***************/
 
   /** Low frequency C clock */
-#if defined( _CMU_LFCLKSEL_LFC_MASK )
-  cmuClock_LFC = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
-                 (CMU_LFCCLKSEL_REG << CMU_SEL_REG_POS) |
-                 (CMU_NO_EN_REG << CMU_EN_REG_POS) |
-                 (0 << CMU_EN_BIT_POS) |
-                 (CMU_LFC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+  cmuClock_LFC = (CMU_NODIV_REG << CMU_DIV_REG_POS)
+                 | (CMU_LFCCLKSEL_REG << CMU_SEL_REG_POS)
+                 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
+                 | (0 << CMU_EN_BIT_POS)
+                 | (CMU_LFC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+
+#if defined( CMU_LFCCLKEN0_USBLE )
+  /** USB LE clock. */
+  cmuClock_USBLE = (CMU_NODIV_REG << CMU_DIV_REG_POS)
+                   | (CMU_LFCCLKSEL_REG << CMU_SEL_REG_POS)
+                   | (CMU_LFCCLKEN0_EN_REG << CMU_EN_REG_POS)
+                   | (_CMU_LFCCLKEN0_USBLE_SHIFT << CMU_EN_BIT_POS)
+                   | (CMU_USBLE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+#endif
 #endif
 
-#if defined(_CMU_LFCCLKEN0_USBLE_MASK)
-  /** USB LE clock. */
-  cmuClock_USBLE = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
-                   (CMU_LFCCLKSEL_REG << CMU_SEL_REG_POS) |
-                   (CMU_LFCCLKEN0_EN_REG << CMU_EN_REG_POS) |
-                   (_CMU_LFCCLKEN0_USBLE_SHIFT << CMU_EN_BIT_POS) |
-                   (CMU_USBLE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+#if defined( _CMU_LFECLKEN0_MASK )
+  /***************/
+  /* LF E branch */
+  /***************/
+
+  /** Low frequency A clock */
+  cmuClock_LFE = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
+                 | (CMU_LFECLKSEL_REG << CMU_SEL_REG_POS)
+                 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
+                 | (0 << CMU_EN_BIT_POS)
+                 | (CMU_LFE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+
+  /** Real time counter and calendar clock. */
+#if defined ( CMU_LFECLKEN0_RTCC )
+  cmuClock_RTCC = (CMU_LFEPRESC0_REG << CMU_PRESC_REG_POS)
+                  | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+                  | (CMU_LFECLKEN0_EN_REG << CMU_EN_REG_POS)
+                  | (_CMU_LFECLKEN0_RTCC_SHIFT << CMU_EN_BIT_POS)
+                  | (CMU_RTCC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+#endif
 #endif
 
 } CMU_Clock_TypeDef;
@@ -641,7 +940,7 @@
 #if defined( _CMU_STATUS_USHFRCOENS_MASK )
   cmuOsc_USHFRCO,  /**< USB high frequency RC oscillator */
 #endif
-#if defined( _CMU_LFCLKSEL_LFAE_ULFRCO )
+#if defined( CMU_LFCLKSEL_LFAE_ULFRCO ) || defined( CMU_LFACLKSEL_LFA_ULFRCO )
   cmuOsc_ULFRCO    /**< Ultra low frequency RC oscillator. */
 #endif
 } CMU_Osc_TypeDef;
@@ -656,65 +955,257 @@
   cmuSelect_LFRCO,      /**< Low frequency RC oscillator. */
   cmuSelect_HFXO,       /**< High frequency crystal oscillator. */
   cmuSelect_HFRCO,      /**< High frequency RC oscillator. */
+#if defined( CMU_LFACLKSEL_LFA_HFCLKLE ) || defined( CMU_LFBCLKSEL_LFB_HFCLKLE )
+  cmuSelect_HFCLKLE,    /**< High frequency clock to LE divided by 2 or 4. */
+#endif
   cmuSelect_CORELEDIV2, /**< Core low energy clock divided by 2. */
   cmuSelect_AUXHFRCO,   /**< Auxilliary clock source can be used for debug clock */
   cmuSelect_HFCLK,      /**< Divided HFCLK on Giant for debug clock, undivided on Tiny Gecko and for USBC (not used on Gecko) */
-#if defined( _CMU_STATUS_USHFRCOENS_MASK )
+#if defined( CMU_STATUS_USHFRCOENS )
   cmuSelect_USHFRCO,    /**< USB high frequency RC oscillator */
 #endif
-#if defined( _CMU_CMD_HFCLKSEL_USHFRCODIV2 )
+#if defined( CMU_CMD_HFCLKSEL_USHFRCODIV2 )
   cmuSelect_USHFRCODIV2,/**< USB high frequency RC oscillator */
 #endif
-#if defined( _CMU_LFCLKSEL_LFAE_ULFRCO )
+#if defined( CMU_LFCLKSEL_LFAE_ULFRCO ) || defined( CMU_LFACLKSEL_LFA_ULFRCO )
   cmuSelect_ULFRCO,     /**< Ultra low frequency RC oscillator. */
 #endif
 } CMU_Select_TypeDef;
 
 
 /*******************************************************************************
+ *******************************   STRUCTS   ***********************************
+ ******************************************************************************/
+
+#if defined( _CMU_LFXOCTRL_MASK )
+/** LFXO initialization structure. Init values should be obtained from a configuration tool,
+    app note or xtal datasheet  */
+typedef struct
+{
+  uint8_t ctune;                        /**< CTUNE (load capacitance) value */
+  uint8_t gain;                         /**< Gain / max startup margin */
+  uint8_t timeout;                      /**< Startup delay */
+} CMU_LFXOInit_TypeDef;
+
+/** Default LFXO initialization */
+#define CMU_LFXOINIT_DEFAULT            \
+  {                                     \
+    _CMU_LFXOCTRL_TUNING_DEFAULT,       \
+    _CMU_LFXOCTRL_GAIN_DEFAULT,         \
+    _CMU_LFXOCTRL_TIMEOUT_DEFAULT,      \
+  }
+#endif
+
+#if defined( _CMU_HFXOCTRL_MASK )
+/** HFXO initialization structure. Init values should be obtained from a configuration tool,
+    app note or xtal datasheet  */
+typedef struct
+{
+  bool lowPowerMode;                    /**< Enable low-power mode */
+  bool autoStartEm01;                   /**< Enable auto-start on entry to EM0/1 */
+  bool autoSelEm01;                     /**< Enable auto-select on entry to EM0/1 */
+  bool autoStartSelOnRacWakeup;         /**< Enable auto-start and select on RAC wakeup */
+  uint16_t ctuneStartup;                /**< Startup phase CTUNE (load capacitance) value */
+  uint16_t ctuneSteadyState;            /**< Steady-state phase CTUNE (load capacitance) value */
+  uint8_t regIshStartup;                /**< Shunt startup current */
+  uint8_t regIshSteadyState;            /**< Shunt steady-state current */
+  uint8_t xoCoreBiasTrimStartup;        /**< Startup XO core bias current trim */
+  uint8_t xoCoreBiasTrimSteadyState;    /**< Steady-state XO core bias current trim */
+  uint8_t thresholdPeakDetect;          /**< Peak detection threshold */
+  uint8_t timeoutShuntOptimization;     /**< Timeout - shunt optimization */
+  uint8_t timeoutPeakDetect;            /**< Timeout - peak detection */
+  uint8_t timeoutWarmSteady;            /**< Timeout - warmup */
+  uint8_t timeoutSteady;                /**< Timeout - steady-state */
+  uint8_t timeoutStartup;               /**< Timeout - startup */
+} CMU_HFXOInit_TypeDef;
+
+/** Default HFXO initialization */
+#if defined( _EFR_DEVICE )
+#define CMU_HFXOINIT_DEFAULT                                                    \
+{                                                                               \
+  false,        /* Low-noise mode for EFR32 */                                  \
+  false,        /* Disable auto-start on EM0/1 entry */                         \
+  false,        /* Disable auto-select on EM0/1 entry */                        \
+  false,        /* Disable auto-start and select on RAC wakeup */               \
+  _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT,                                           \
+  _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT,                                       \
+  _CMU_HFXOSTARTUPCTRL_REGISHWARM_DEFAULT,                                      \
+  _CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT,                                      \
+  _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT,                                    \
+  0x7,          /* Recommended steady-state XO core bias current */             \
+  0x6,          /* Recommended peak detection threshold */                      \
+  _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT,                                 \
+  0xA,          /* Recommended peak detection timeout  */                       \
+  _CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_DEFAULT,                               \
+  _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT,                                   \
+  _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT,                                  \
+}
+/* EFM32 device */
+#else
+#define CMU_HFXOINIT_DEFAULT                                                    \
+{                                                                               \
+  true,         /* Low-power mode for EFM32 */                                  \
+  false,        /* Disable auto-start on EM0/1 entry */                         \
+  false,        /* Disable auto-select on EM0/1 entry */                        \
+  false,        /* Disable auto-start and select on RAC wakeup */               \
+  _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT,                                           \
+  _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT,                                       \
+  _CMU_HFXOSTARTUPCTRL_REGISHWARM_DEFAULT,                                      \
+  _CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT,                                      \
+  _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT,                                    \
+  0x7,          /* Recommended steady-state osc core bias current */            \
+  0x6,          /* Recommended peak detection threshold */                      \
+  _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT,                                 \
+  0xA,          /* Recommended peak detection timeout  */                       \
+  _CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_DEFAULT,                               \
+  _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT,                                   \
+  _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT,                                  \
+}
+#endif
+#endif /* _CMU_HFXOCTRL_MASK */
+
+
+/*******************************************************************************
  *****************************   PROTOTYPES   **********************************
  ******************************************************************************/
 
-void CMU_ClockEnable(CMU_Clock_TypeDef clock, bool enable);
-uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock);
-CMU_ClkDiv_TypeDef CMU_ClockDivGet(CMU_Clock_TypeDef clock);
-CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock);
-void CMU_ClockDivSet(CMU_Clock_TypeDef clock, CMU_ClkDiv_TypeDef div);
-void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref);
+#if defined( _CMU_AUXHFRCOCTRL_BAND_MASK )
+CMU_AUXHFRCOBand_TypeDef  CMU_AUXHFRCOBandGet(void);
+void                      CMU_AUXHFRCOBandSet(CMU_AUXHFRCOBand_TypeDef band);
+
+#elif defined( _CMU_AUXHFRCOCTRL_FREQRANGE_MASK )
+CMU_AUXHFRCOFreq_TypeDef  CMU_AUXHFRCOFreqGet(void);
+void                      CMU_AUXHFRCOFreqSet(CMU_AUXHFRCOFreq_TypeDef freqEnum);
+#endif
+
+uint32_t              CMU_Calibrate(uint32_t HFCycles, CMU_Osc_TypeDef reference);
 
-CMU_HFRCOBand_TypeDef CMU_HFRCOBandGet(void);
-void CMU_HFRCOBandSet(CMU_HFRCOBand_TypeDef band);
+#if defined( _CMU_CALCTRL_UPSEL_MASK ) && defined( _CMU_CALCTRL_DOWNSEL_MASK )
+void                  CMU_CalibrateConfig(uint32_t downCycles, CMU_Osc_TypeDef downSel,
+                                          CMU_Osc_TypeDef upSel);
+#endif
 
-#if defined( _CMU_AUXHFRCOCTRL_BAND_MASK )
-CMU_AUXHFRCOBand_TypeDef CMU_AUXHFRCOBandGet(void);
-void CMU_AUXHFRCOBandSet(CMU_AUXHFRCOBand_TypeDef band);
+uint32_t              CMU_CalibrateCountGet(void);
+void                  CMU_ClockEnable(CMU_Clock_TypeDef clock, bool enable);
+CMU_ClkDiv_TypeDef    CMU_ClockDivGet(CMU_Clock_TypeDef clock);
+void                  CMU_ClockDivSet(CMU_Clock_TypeDef clock, CMU_ClkDiv_TypeDef div);
+uint32_t              CMU_ClockFreqGet(CMU_Clock_TypeDef clock);
+
+#if defined( _SILICON_LABS_32B_PLATFORM_2 )
+void                  CMU_ClockPrescSet(CMU_Clock_TypeDef clock, uint32_t presc);
+uint32_t              CMU_ClockPrescGet(CMU_Clock_TypeDef clock);
 #endif
 
-#if defined( _CMU_USHFRCOCONF_BAND_MASK )
-CMU_USHFRCOBand_TypeDef CMU_USHFRCOBandGet(void);
-void CMU_USHFRCOBandSet(CMU_USHFRCOBand_TypeDef band);
+void                  CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref);
+CMU_Select_TypeDef    CMU_ClockSelectGet(CMU_Clock_TypeDef clock);
+void                  CMU_FreezeEnable(bool enable);
+
+#if defined( _CMU_HFRCOCTRL_BAND_MASK )
+CMU_HFRCOBand_TypeDef CMU_HFRCOBandGet(void);
+void                  CMU_HFRCOBandSet(CMU_HFRCOBand_TypeDef band);
+
+#elif defined( _CMU_HFRCOCTRL_FREQRANGE_MASK )
+CMU_HFRCOFreq_TypeDef CMU_HFRCOFreqGet(void);
+void                  CMU_HFRCOFreqSet(CMU_HFRCOFreq_TypeDef freqEnum);
+#endif
+
+uint32_t              CMU_HFRCOStartupDelayGet(void);
+void                  CMU_HFRCOStartupDelaySet(uint32_t delay);
+
+#if defined( _CMU_HFXOCTRL_AUTOSTARTRDYSELRAC_MASK )
+void                  CMU_HFXOAutostartEnable(bool enRACStartSel,
+                                              bool enEM0EM1Start,
+                                              bool enEM0EM1StartSel);
+#endif
+
+#if defined( _CMU_HFXOCTRL_MASK )
+void                  CMU_HFXOInit(CMU_HFXOInit_TypeDef *hfxoInit);
+#endif
+
+
+uint32_t              CMU_LCDClkFDIVGet(void);
+void                  CMU_LCDClkFDIVSet(uint32_t div);
+
+#if defined( _CMU_LFXOCTRL_MASK )
+void                  CMU_LFXOInit(CMU_LFXOInit_TypeDef *lfxoInit);
 #endif
 
-void CMU_HFRCOStartupDelaySet(uint32_t delay);
-uint32_t CMU_HFRCOStartupDelayGet(void);
+void                  CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait);
+uint32_t              CMU_OscillatorTuningGet(CMU_Osc_TypeDef osc);
+void                  CMU_OscillatorTuningSet(CMU_Osc_TypeDef osc, uint32_t val);
+bool                  CMU_PCNTClockExternalGet(unsigned int instance);
+void                  CMU_PCNTClockExternalSet(unsigned int instance, bool external);
+
+#if defined( _CMU_USHFRCOCONF_BAND_MASK )
+CMU_USHFRCOBand_TypeDef   CMU_USHFRCOBandGet(void);
+void                      CMU_USHFRCOBandSet(CMU_USHFRCOBand_TypeDef band);
+#endif
+
 
-void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait);
-uint32_t CMU_OscillatorTuningGet(CMU_Osc_TypeDef osc);
-void CMU_OscillatorTuningSet(CMU_Osc_TypeDef osc, uint32_t val);
+#if defined( CMU_CALCTRL_CONT )
+/***************************************************************************//**
+ * @brief
+ *   Configures continuous calibration mode
+ * @param[in] enable
+ *   If true, enables continuous calibration, if false disables continuous
+ *   calibrartion
+ ******************************************************************************/
+__STATIC_INLINE void CMU_CalibrateCont(bool enable)
+{
+  BUS_RegBitWrite(&(CMU->CALCTRL), _CMU_CALCTRL_CONT_SHIFT, enable);
+}
+#endif
 
-bool CMU_PCNTClockExternalGet(unsigned int inst);
-void CMU_PCNTClockExternalSet(unsigned int inst, bool external);
 
-uint32_t CMU_LCDClkFDIVGet(void);
-void CMU_LCDClkFDIVSet(uint32_t div);
+/***************************************************************************//**
+ * @brief
+ *   Starts calibration
+ * @note
+ *   This call is usually invoked after CMU_CalibrateConfig() and possibly
+ *   CMU_CalibrateCont()
+ ******************************************************************************/
+__STATIC_INLINE void CMU_CalibrateStart(void)
+{
+  CMU->CMD = CMU_CMD_CALSTART;
+}
+
+
+#if defined( CMU_CMD_CALSTOP )
+/***************************************************************************//**
+ * @brief
+ *   Stop the calibration counters
+ ******************************************************************************/
+__STATIC_INLINE void CMU_CalibrateStop(void)
+{
+  CMU->CMD = CMU_CMD_CALSTOP;
+}
+#endif
+
 
-void CMU_FreezeEnable(bool enable);
-uint32_t CMU_Calibrate(uint32_t HFCycles, CMU_Osc_TypeDef reference);
+/***************************************************************************//**
+ * @brief
+ *   Convert dividend to logarithmic value. Only works for even
+ *   numbers equal to 2^n.
+ *
+ * @param[in] div
+ *   Unscaled dividend.
+ *
+ * @return
+ *   Logarithm of 2, as used by fixed prescalers.
+ ******************************************************************************/
+__STATIC_INLINE uint32_t CMU_DivToLog2(CMU_ClkDiv_TypeDef div)
+{
+  uint32_t log2;
 
-#if defined( _CMU_CALCTRL_UPSEL_MASK ) && defined( _CMU_CALCTRL_DOWNSEL_MASK )
-void CMU_CalibrateConfig(uint32_t downCycles, CMU_Osc_TypeDef downSel,
-                         CMU_Osc_TypeDef upSel);
-#endif
+  /* Fixed 2^n prescalers take argument of 32768 or less. */
+  EFM_ASSERT((div > 0U) && (div <= 32768U));
+
+  /* Count leading zeroes and "reverse" result */
+  log2 = (31U - __CLZ(div));
+
+  return log2;
+}
+
 
 /***************************************************************************//**
  * @brief
@@ -784,30 +1275,23 @@
  *   The event bits are not cleared by the use of this function.
  *
  * @return
- *   Pending and enabled CMU interrupt sources.
- *   The return value is the bitwise AND combination of
- *   - the OR combination of enabled interrupt sources in CMU_IEN_nnn
- *   register (CMU_IEN_nnn) and
- *   - the OR combination of valid interrupt flags of the CMU module
- *   (CMU_IF_nnn).
+ *   Pending and enabled CMU interrupt sources
+ *   The return value is the bitwise AND of
+ *   - the enabled interrupt sources in CMU_IEN and
+ *   - the pending interrupt flags CMU_IF
  ******************************************************************************/
 __STATIC_INLINE uint32_t CMU_IntGetEnabled(void)
 {
-  uint32_t tmp = 0U;
-
+  uint32_t ien;
 
-  /* Store LESENSE->IEN in temporary variable in order to define explicit order
-   * of volatile accesses. */
-  tmp = CMU->IEN;
-
-  /* Bitwise AND of pending and enabled interrupts */
-  return CMU->IF & tmp;
+  ien = CMU->IEN;
+  return CMU->IF & ien;
 }
 
 
 /**************************************************************************//**
  * @brief
- *   Set one or more pending CMU interrupts from SW.
+ *   Set one or more pending CMU interrupts.
  *
  * @param[in] flags
  *   CMU interrupt sources to set to pending.
@@ -839,6 +1323,52 @@
 
 /***************************************************************************//**
  * @brief
+ *   Convert logarithm of 2 prescaler to division factor.
+ *
+ * @param[in] log2
+ *   Logarithm of 2, as used by fixed prescalers.
+ *
+ * @return
+ *   Dividend.
+ ******************************************************************************/
+__STATIC_INLINE uint32_t CMU_Log2ToDiv(uint32_t log2)
+{
+  return 1 << log2;
+}
+
+
+#if defined( _SILICON_LABS_32B_PLATFORM_2 )
+/***************************************************************************//**
+ * @brief
+ *   Convert prescaler dividend to logarithmic value. Only works for even
+ *   numbers equal to 2^n.
+ *
+ * @param[in] presc
+ *   Unscaled dividend (dividend = presc + 1).
+ *
+ * @return
+ *   Logarithm of 2, as used by fixed 2^n prescalers.
+ ******************************************************************************/
+__STATIC_INLINE uint32_t CMU_PrescToLog2(CMU_ClkPresc_TypeDef presc)
+{
+  uint32_t log2;
+
+  /* Integer prescalers take argument less than 32768. */
+  EFM_ASSERT(presc < 32768U);
+
+  /* Count leading zeroes and "reverse" result */
+  log2 = (31U - __CLZ(presc + 1));
+
+  /* Check that presc is a 2^n number */
+  EFM_ASSERT(presc == (CMU_Log2ToDiv(log2) - 1));
+
+  return log2;
+}
+#endif
+
+
+/***************************************************************************//**
+ * @brief
  *   Unlock the CMU so that writing to locked registers again is possible.
  ******************************************************************************/
 __STATIC_INLINE void CMU_Unlock(void)
@@ -846,77 +1376,6 @@
   CMU->LOCK = CMU_LOCK_LOCKKEY_UNLOCK;
 }
 
-
-/***************************************************************************//**
- * @brief
- *    Get calibration count register
- * @note
- *    If continuous calibrartion mode is active, calibration busy will allmost
- *    always be on, and we just need to read the value, where the normal case
- *    would be that this function call has been triggered by the CALRDY
- *    interrupt flag.
- * @return
- *    Calibration count, the number of UPSEL clocks (see CMU_CalibrateConfig)
- *    in the period of DOWNSEL oscillator clock cycles configured by a previous
- *    write operation to CMU->CALCNT
- ******************************************************************************/
-__STATIC_INLINE uint32_t CMU_CalibrateCountGet(void)
-{
-  /* Wait until calibration completes, UNLESS continuous calibration mode is  */
-  /* active */
-#if defined( CMU_CALCTRL_CONT )
-  if (!(CMU->CALCTRL & CMU_CALCTRL_CONT))
-  {
-    while (CMU->STATUS & CMU_STATUS_CALBSY)
-      ;
-  }
-#else
-  while (CMU->STATUS & CMU_STATUS_CALBSY)
-      ;
-#endif
-  return CMU->CALCNT;
-}
-
-
-/***************************************************************************//**
- * @brief
- *   Starts calibration
- * @note
- *   This call is usually invoked after CMU_CalibrateConfig() and possibly
- *   CMU_CalibrateCont()
- ******************************************************************************/
-__STATIC_INLINE void CMU_CalibrateStart(void)
-{
-  CMU->CMD = CMU_CMD_CALSTART;
-}
-
-
-#if defined( CMU_CMD_CALSTOP )
-/***************************************************************************//**
- * @brief
- *   Stop the calibration counters
- ******************************************************************************/
-__STATIC_INLINE void CMU_CalibrateStop(void)
-{
-  CMU->CMD = CMU_CMD_CALSTOP;
-}
-#endif
-
-
-#if defined( CMU_CALCTRL_CONT )
-/***************************************************************************//**
- * @brief
- *   Configures continuous calibration mode
- * @param[in] enable
- *   If true, enables continuous calibration, if false disables continuous
- *   calibrartion
- ******************************************************************************/
-__STATIC_INLINE void CMU_CalibrateCont(bool enable)
-{
-  BITBAND_Peripheral(&(CMU->CALCTRL), _CMU_CALCTRL_CONT_SHIFT, enable);
-}
-#endif
-
 /** @} (end addtogroup CMU) */
 /** @} (end addtogroup EM_Library) */
 
@@ -925,4 +1384,4 @@
 #endif
 
 #endif /* defined( CMU_PRESENT ) */
-#endif /* __SILICON_LABS_EM_CMU_H_ */
+#endif /* __SILICON_LABS_EM_CMU_H__ */

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_common.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_common.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /***************************************************************************//**
  * @file em_common.h
- * @brief EFM32 general purpose utilities.
- * @version 3.20.12
+ * @brief Emlib general purpose utilities.
+ * @version 4.2.1
  *******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
  *******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,14 +30,12 @@
  *
  ******************************************************************************/
 
-
-#ifndef __SILICON_LABS_EM_COMMON_H_
-#define __SILICON_LABS_EM_COMMON_H_
+#ifndef __SILICON_LABS_EM_COMMON_H__
+#define __SILICON_LABS_EM_COMMON_H__
 
-#include <stdint.h>
+#include "em_device.h"
 #include <stdbool.h>
 
-
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -49,7 +47,7 @@
 
 /***************************************************************************//**
  * @addtogroup COMMON
- * @brief EFM32 general purpose utilities.
+ * @brief Emlib general purpose utilities.
  * @{
  ******************************************************************************/
 
@@ -75,7 +73,7 @@
 #define EFM32_ALIGN(X) _Pragma( STRINGIZE( data_alignment=X ) )
 #endif
 
-#else
+#else // !defined(__GNUC__)
 
 /** Macro for getting minimum value. No sideeffects, a and b are evaluated once only. */
 #define EFM32_MIN(a, b)    ({ __typeof__(a) _a = (a); __typeof__(b) _b = (b); _a < _b ? _a : _b; })
@@ -104,7 +102,33 @@
  */
 #define EFM32_ALIGN(X)
 
+#endif // !defined(__GNUC__)
+
+/***************************************************************************//**
+ * @brief
+ *   Count trailing number of zero's.
+ *
+ * @note
+ *   Disabling SWDClk will disable the debug interface, which may result in
+ *   a lockout if done early in startup (before debugger is able to halt core).
+ *
+ * @param[in] value
+ *   Data value to check for number of trailing zero bits.
+ *
+ * @return
+ *   Number of trailing zero's in value.
+ ******************************************************************************/
+__STATIC_INLINE uint32_t EFM32_CTZ(uint32_t value)
+{
+#if (__CORTEX_M >= 3)
+  return __CLZ(__RBIT(value));
+
+#else
+  uint32_t zeros;
+  for(zeros=0; (zeros<32) && ((value&0x1) == 0); zeros++, value>>=1);
+  return zeros;
 #endif
+}
 
 /** @} (end addtogroup COMMON) */
 /** @} (end addtogroup EM_Library) */
@@ -113,4 +137,4 @@
 }
 #endif
 
-#endif /* __SILICON_LABS_EM_COMMON_H_ */
+#endif /* __SILICON_LABS_EM_COMMON_H__ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_crc.h	Fri Jan 15 07:45:16 2016 +0000
@@ -0,0 +1,294 @@
+/***************************************************************************//**
+ * @file
+ * @brief Cyclic Redundancy Check (CRC) API.
+ * @version 4.2.1
+ *******************************************************************************
+ * @section License
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
+ *******************************************************************************
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
+ * obligation to support this Software. Silicon Labs is providing the
+ * Software "AS IS", with no express or implied warranties of any kind,
+ * including, but not limited to, any implied warranties of merchantability
+ * or fitness for any particular purpose or warranties against infringement
+ * of any proprietary rights of a third party.
+ *
+ * Silicon Labs will not be liable for any consequential, incidental, or
+ * special damages, or any other relief, or for any claim by any third party,
+ * arising from your use of this Software.
+ *
+ ******************************************************************************/
+
+#ifndef __SILICON_LABS_EM_CRC_H__
+#define __SILICON_LABS_EM_CRC_H__
+
+#include "em_device.h"
+#if defined(CRC_COUNT) && (CRC_COUNT > 0)
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************************************************************//**
+ * @addtogroup EM_Library
+ * @{
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * @addtogroup CRC
+ * @{
+ ******************************************************************************/
+
+/*******************************************************************************
+ ********************************   ENUMS   ************************************
+ ******************************************************************************/
+
+/** CRC width values. */
+typedef enum
+{
+  /** 8 bit (1 byte) CRC code. */
+  crcWidth8 = CRC_CTRL_CRCWIDTH_CRCWIDTH8,
+
+  /** 16 bit (2 byte) CRC code. */
+  crcWidth16 = CRC_CTRL_CRCWIDTH_CRCWIDTH16,
+
+  /** 24 bit (3 byte) CRC code. */
+  crcWidth24 = CRC_CTRL_CRCWIDTH_CRCWIDTH24,
+
+  /** 32 bit (4 byte) CRC code. */
+  crcWidth32 = CRC_CTRL_CRCWIDTH_CRCWIDTH32
+} CRC_Width_TypeDef;
+
+
+/** CRC byte reverse values. */
+typedef enum
+{
+  /** Most significant CRC bytes are transferred first over air via the Frame
+   *  Controller (FRC). */
+  crcByteOrderNormal = CRC_CTRL_BYTEREVERSE_NORMAL,
+
+  /** Least significant CRC bytes are transferred first over air via the Frame
+   *  Controller (FRC). */
+  crcByteOrderReversed = CRC_CTRL_BYTEREVERSE_REVERSED
+} CRC_ByteOrder_TypeDef;
+
+
+/** CRC bit order values. */
+typedef enum
+{
+  /** Least significant data bit (LSB) is fed first to the CRC generator. */
+  crcBitOrderLSBFirst = CRC_CTRL_INPUTBITORDER_LSBFIRST,
+
+  /** Most significant data bit (MSB) is fed first to the CRC generator. */
+  crcBitOrderMSBFirst = CRC_CTRL_INPUTBITORDER_MSBFIRST
+} CRC_BitOrder_TypeDef;
+
+
+/** CRC bit reverse values. */
+typedef enum
+{
+  /** The bit ordering of CRC data is the same as defined by the BITORDER field
+   *  in the Frame Controller. */
+  crcBitReverseNormal = CRC_CTRL_BITREVERSE_NORMAL,
+
+  /** The bit ordering of CRC data is the opposite as defined by the BITORDER
+   *  field in the Frame Controller. */
+  crcBitReverseReversed = CRC_CTRL_BITREVERSE_REVERSED
+} CRC_BitReverse_TypeDef;
+
+
+/*******************************************************************************
+ *******************************   STRUCTS   ***********************************
+ ******************************************************************************/
+
+/** CRC initialization structure. */
+typedef struct
+{
+  /** Width of the CRC code. */
+  CRC_Width_TypeDef         crcWidth;
+
+  /** CRC polynomial value. This value defines POLY[31:0], which is used as the
+   *  polynomial (in reversed order) during the CRC calculation. If the CRC
+   *  width is less than 32 bits, the most significant part of this register
+   *  remains unused.
+   *  - Set the bit to 1 in the register to get the corresponding degree term
+   *  appear in the polynomial with a coefficient of 1.
+   *  - Set the bit to 0 in the register to get the corresponding degree term
+   *  appear in the polynomial with a coefficient of 0.
+   *  Note: If a CRC polynomial of size less than 32 bits is to be used, the
+   *  polynomial value must be shifted so that the highest degree term is
+   *  located in DATA[0]!
+   *  Please refer to the CRC sub-chapter "CRC Polynomial" in the documentation
+   *  for more details! */
+  uint32_t                   crcPoly;
+
+  /** CRC initialization value. Loaded into the CRC_DATA register upon issuing
+   *  the INIT command by calling CRC_InitCommand(), or when the Frame
+   *  Controller (FRC) uses the CRC for automatic CRC calculation and
+   *  verification. */
+  uint32_t                   initValue;
+
+  /** Number of bits per input word. This value defines the number of valid
+   *  input bits in the CRC_INPUTDATA register, or in data coming from the Frame
+   *  Controller (FRC). The number of bits in each word equals to
+   *  (BITSPERWORD + EXTRABITSPERWORD + 1), where EXTRABITSPERWORD is taken from
+   *  the currently active Frame Control Descriptor (FCD). */
+  uint8_t                    bitsPerWord;
+
+  /** If true, the byte order is reversed and the least significant CRC bytes
+   *  are transferred first over the air. (description TBD) */
+  CRC_ByteOrder_TypeDef      byteReverse;
+
+  /** Bit order. Defines the order in which bits are fed to the CRC generator.
+   *  This setting applies both to data written to the CRC_INPUTDATA register,
+   *  and data coming from the Frame Controller (FRC). */
+  CRC_BitOrder_TypeDef       inputBitOrder;
+
+  /** Output bit reverse. In most cases, the bit ordering of the CRC value
+   *  corresponds to the bit ordering of other data transmitted over air. When
+   *  set, the BITREVERSE field has the possibility to reverse this bit ordering
+   *  to comply with some protocols. Note that this field does not affect the
+   *  way the CRC value is calculated, only how it is transmitted over air. */
+  CRC_BitReverse_TypeDef     bitReverse;
+
+  /** Enable/disable CRC input data padding. When set, CRC input data is zero-
+   *  padded, such that the number of bytes over which the CRC value is
+   *  calculated at least equals the length of the calculated CRC value. If not
+   *  set, no zero-padding of CRC input data is applied. */
+  bool                       inputPadding;
+
+  /** If true, CRC input is inverted. */
+  bool                       invInput;
+
+  /** If true, CRC output to the Frame Controller (FRC) is inverted. */
+  bool                       invOutput;
+} CRC_Init_TypeDef;
+
+/** Default configuration for CRC_Init_TypeDef structure. */
+#define CRC_INIT_DEFAULT                                              \
+{                                                                     \
+  crcWidth16,           /* CRC width is 16 bits. */                   \
+  0x00008408UL,         /* Polynomial value of IEEE 802.15.4-2006. */ \
+  0x00000000UL,         /* Initialization value. */                   \
+  8U,                   /* 8 bits per word. */                        \
+  crcByteOrderNormal,   /* Byte order is normal. */                   \
+  crcBitOrderLSBFirst,  /* Bit order (TBD). */                        \
+  crcBitReverseNormal,  /* Bit order is not reversed on output. */    \
+  false,                /* No zero-padding. */                        \
+  false,                /* Input is not inverted. */                  \
+  false                 /* Output is not inverted. */                 \
+}
+
+
+/*******************************************************************************
+ ******************************   PROTOTYPES   *********************************
+ ******************************************************************************/
+
+void CRC_Init(CRC_Init_TypeDef const *init);
+void CRC_Reset(void);
+
+/***************************************************************************//**
+ * @brief
+ *   Issues a command to initialize the CRC calculation.
+ *
+ * @details
+ *   This function issues the command INITIALIZE in CRC_CMD that initializes the
+ *   CRC calculation by writing the initial values to the DATA register.
+ *
+ * @note
+ *   Internal notes:
+ *   Initialize in CRC_CMD
+ *   Conclude on reference of parameters. Register names or config struct members?
+ ******************************************************************************/
+__STATIC_INLINE void CRC_InitCommand(void)
+{
+  CRC->CMD = CRC_CMD_INITIALIZE;
+}
+
+
+/***************************************************************************//**
+ * @brief
+ *   Set the initialization value of the CRC.
+ ******************************************************************************/
+__STATIC_INLINE void CRC_InitValueSet(uint32_t initValue)
+{
+  CRC->INIT = initValue;
+}
+
+
+/***************************************************************************//**
+ * @brief
+ *   Writes data to the input data register of the CRC.
+ *
+ * @details
+ *   Use this function to write input data to the CRC when the FRC is not being
+ *   used for automatic handling of the CRC. The CRC calculation is based on
+ *   the provided input data using the configured CRC polynomial.
+ *
+ * @param[in] data
+ *   Data to be written to the input data register.
+ ******************************************************************************/
+__STATIC_INLINE void CRC_InputDataWrite(uint16_t data)
+{
+  CRC->INPUTDATA = (uint32_t)data;
+}
+
+
+/***************************************************************************//**
+ * @brief
+ *   Reads the data register of the CRC.
+ *
+ * @details
+ *   Use this function to read the calculated CRC value.
+ *
+ * @return
+ *   Content of the CRC data register.
+ ******************************************************************************/
+__STATIC_INLINE uint32_t CRC_DataRead(void)
+{
+  return CRC->DATA;
+}
+
+
+/***************************************************************************//**
+ * @brief
+ *   Gets if the CRC is busy.
+ *
+ * @details
+ *   Returns true when the CRC module is busy, false otherwise.
+ *
+ * @return
+ *   CRC busy flag.
+ *   @li true - CRC module is busy.
+ *   @li false - CRC module is not busy.
+ ******************************************************************************/
+__STATIC_INLINE bool CRC_BusyGet(void)
+{
+  return (bool)((CRC->STATUS & _CRC_STATUS_BUSY_MASK)
+                >> _CRC_STATUS_BUSY_SHIFT);
+}
+
+
+/** @} (end addtogroup CRC) */
+/** @} (end addtogroup EM_Library) */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* defined(CRC_COUNT) && (CRC_COUNT > 0) */
+#endif /* __SILICON_LABS_EM_CRC_H__ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_cryotimer.h	Fri Jan 15 07:45:16 2016 +0000
@@ -0,0 +1,357 @@
+/***************************************************************************//**
+ * @file em_cryotimer.h
+ * @brief Ultra Low Energy Timer/Counter (CRYOTIMER) peripheral API
+ * @version 4.2.1
+ *******************************************************************************
+ * @section License
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
+ *******************************************************************************
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software.@n
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.@n
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
+ * obligation to support this Software. Silicon Labs is providing the
+ * Software "AS IS", with no express or implied warranties of any kind,
+ * including, but not limited to, any implied warranties of merchantability
+ * or fitness for any particular purpose or warranties against infringement
+ * of any proprietary rights of a third party.
+ *
+ * Silicon Labs will not be liable for any consequential, incidental, or
+ * special damages, or any other relief, or for any claim by any third party,
+ * arising from your use of this Software.
+ *
+ ******************************************************************************/
+
+#ifndef EM_CRYOTIMER_H__
+#define EM_CRYOTIMER_H__
+
+#include <stdbool.h>
+#include "em_device.h"
+#include "em_bus.h"
+
+#if defined(CRYOTIMER_PRESENT) && (CRYOTIMER_COUNT == 1)
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************************************************************//**
+ * @addtogroup EM_Library
+ * @{
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * @addtogroup CRYOTIMER
+ * @brief Ultra Low Energy Timer/Counter (CRYOTIMER) Peripheral API
+ *
+ * @details
+ *   The user is responsible for choosing which oscillator to use for the
+ *   CRYOTIMER. The oscillator that is choosen must be enabled and ready before
+ *   calling this @ref CRYOTIMER_Init function. See @ref CMU_OscillatorEnable
+ *   for details of how to enable and wait for an oscillator to become ready.
+ *   Note that ULFRCO is always ready while LFRCO and LFXO must be enable by
+ *   the user.
+ *
+ * @details
+ *   Note that the only oscillator which is running in EM3 is ULFRCO. Keep this
+ *   in mind when choosing which oscillator to use for the CRYOTIMER.
+ *
+ * @details
+ *   Special care must be taken if the user wants the CRYOTIMER to run during
+ *   EM4. All the low frequency oscillators can be used in EM4, however the
+ *   oscillator that is used must be be configured to be retained when going
+ *   into EM4. This can be configured by using functions in the @ref EMU module.
+ *   See @ref EMU_EM4Init and @ref EMU_EM4Init_TypeDef. If an oscillator is
+ *   retained in EM4 the user is also responsible for unlatching the retained
+ *   configuration on a wakeup from EM4.
+ *
+ * @{
+ ******************************************************************************/
+
+/*******************************************************************************
+ *********************************   ENUM   ************************************
+ ******************************************************************************/
+
+/** Prescaler selection. */
+typedef enum
+{
+  cryotimerPresc_1     = _CRYOTIMER_CTRL_PRESC_DIV1,      /**< Divide clock by 1. */
+  cryotimerPresc_2     = _CRYOTIMER_CTRL_PRESC_DIV2,      /**< Divide clock by 2. */
+  cryotimerPresc_4     = _CRYOTIMER_CTRL_PRESC_DIV4,      /**< Divide clock by 4. */
+  cryotimerPresc_8     = _CRYOTIMER_CTRL_PRESC_DIV8,      /**< Divide clock by 8. */
+  cryotimerPresc_16    = _CRYOTIMER_CTRL_PRESC_DIV16,     /**< Divide clock by 16. */
+  cryotimerPresc_32    = _CRYOTIMER_CTRL_PRESC_DIV32,     /**< Divide clock by 32. */
+  cryotimerPresc_64    = _CRYOTIMER_CTRL_PRESC_DIV64,     /**< Divide clock by 64. */
+  cryotimerPresc_128   = _CRYOTIMER_CTRL_PRESC_DIV128,    /**< Divide clock by 128. */
+} CRYOTIMER_Presc_TypeDef;
+
+/** Low frequency oscillator selection. */
+typedef enum 
+{
+  cryotimerOscLFRCO   = _CRYOTIMER_CTRL_OSCSEL_LFRCO,  /**< Select Low Frequency RC Oscillator. */
+  cryotimerOscLFXO    = _CRYOTIMER_CTRL_OSCSEL_LFXO,   /**< Select Low Frequency Crystal Oscillator. */
+  cryotimerOscULFRCO  = _CRYOTIMER_CTRL_OSCSEL_ULFRCO, /**< Select Ultra Low Frequency RC Oscillator. */
+} CRYOTIMER_Osc_TypeDef;
+
+/** Period selection value */
+typedef enum
+{
+  cryotimerPeriod_1     = 0,    /**< Wakeup event after every Pre-scaled clock cycle. */
+  cryotimerPeriod_2     = 1,    /**< Wakeup event after 2 Pre-scaled clock cycles. */
+  cryotimerPeriod_4     = 2,    /**< Wakeup event after 4 Pre-scaled clock cycles. */
+  cryotimerPeriod_8     = 3,    /**< Wakeup event after 8 Pre-scaled clock cycles. */
+  cryotimerPeriod_16    = 4,    /**< Wakeup event after 16 Pre-scaled clock cycles. */
+  cryotimerPeriod_32    = 5,    /**< Wakeup event after 32 Pre-scaled clock cycles. */
+  cryotimerPeriod_64    = 6,    /**< Wakeup event after 64 Pre-scaled clock cycles. */
+  cryotimerPeriod_128   = 7,    /**< Wakeup event after 128 Pre-scaled clock cycles. */
+  cryotimerPeriod_256   = 8,    /**< Wakeup event after 256 Pre-scaled clock cycles. */
+  cryotimerPeriod_512   = 9,    /**< Wakeup event after 512 Pre-scaled clock cycles. */
+  cryotimerPeriod_1k    = 10,   /**< Wakeup event after 1k Pre-scaled clock cycles. */
+  cryotimerPeriod_2k    = 11,   /**< Wakeup event after 2k Pre-scaled clock cycles. */
+  cryotimerPeriod_4k    = 12,   /**< Wakeup event after 4k Pre-scaled clock cycles. */
+  cryotimerPeriod_8k    = 13,   /**< Wakeup event after 8k Pre-scaled clock cycles. */
+  cryotimerPeriod_16k   = 14,   /**< Wakeup event after 16k Pre-scaled clock cycles. */
+  cryotimerPeriod_32k   = 15,   /**< Wakeup event after 32k Pre-scaled clock cycles. */
+  cryotimerPeriod_64k   = 16,   /**< Wakeup event after 64k Pre-scaled clock cycles. */
+  cryotimerPeriod_128k  = 17,   /**< Wakeup event after 128k Pre-scaled clock cycles. */
+  cryotimerPeriod_256k  = 18,   /**< Wakeup event after 256k Pre-scaled clock cycles. */
+  cryotimerPeriod_512k  = 19,   /**< Wakeup event after 512k Pre-scaled clock cycles. */
+  cryotimerPeriod_1m    = 20,   /**< Wakeup event after 1m Pre-scaled clock cycles. */
+  cryotimerPeriod_2m    = 21,   /**< Wakeup event after 2m Pre-scaled clock cycles. */
+  cryotimerPeriod_4m    = 22,   /**< Wakeup event after 4m Pre-scaled clock cycles. */
+  cryotimerPeriod_8m    = 23,   /**< Wakeup event after 8m Pre-scaled clock cycles. */
+  cryotimerPeriod_16m   = 24,   /**< Wakeup event after 16m Pre-scaled clock cycles. */
+  cryotimerPeriod_32m   = 25,   /**< Wakeup event after 32m Pre-scaled clock cycles. */
+  cryotimerPeriod_64m   = 26,   /**< Wakeup event after 64m Pre-scaled clock cycles. */
+  cryotimerPeriod_128m  = 27,   /**< Wakeup event after 128m Pre-scaled clock cycles. */
+  cryotimerPeriod_256m  = 28,   /**< Wakeup event after 256m Pre-scaled clock cycles. */
+  cryotimerPeriod_512m  = 29,   /**< Wakeup event after 512m Pre-scaled clock cycles. */
+  cryotimerPeriod_1024m = 30,   /**< Wakeup event after 1024m Pre-scaled clock cycles. */
+  cryotimerPeriod_2048m = 31,   /**< Wakeup event after 2048m Pre-scaled clock cycles. */
+  cryotimerPeriod_4096m = 32,   /**< Wakeup event after 4096m Pre-scaled clock cycles. */
+} CRYOTIMER_Period_TypeDef;
+
+/*******************************************************************************
+ *******************************   STRUCTS   ***********************************
+ ******************************************************************************/
+
+/** CRYOTIMER initialization structure. */
+typedef struct
+{
+  /** Enable/disable counting when initialization is completed. */
+  bool                      enable;
+
+  /** Enable/disable timer counting during debug halt. */
+  bool                      debugRun;
+
+  /** Enable/disable EM4 Wakeup. */
+  bool                      em4Wakeup;
+
+  /** Select the oscillator for the CRYOTIMER. */
+  CRYOTIMER_Osc_TypeDef     osc;
+
+  /** Prescaler. */
+  CRYOTIMER_Presc_TypeDef   presc;
+
+  /** Period between wakeup event/interrupt. */
+  CRYOTIMER_Period_TypeDef  period;
+} CRYOTIMER_Init_TypeDef;
+
+/*******************************************************************************
+ *******************************   DEFINES   ***********************************
+ ******************************************************************************/
+
+/** Default CRYOTIMER init structure. */
+#define CRYOTIMER_INIT_DEFAULT                                                   \
+{                                                                                \
+  true,                  /* Start counting when init done.                    */ \
+  false,                 /* Disable CRYOTIMER during debug halt.              */ \
+  false,                 /* Disable EM4 wakeup.                               */ \
+  cryotimerOscLFRCO,     /* Select Low Frequency RC Oscillator.               */ \
+  cryotimerPresc_1,      /* LF Oscillator frequency undivided.                */ \
+  cryotimerPeriod_4096m, /* Wakeup event after 4096M pre-scaled clock cycles. */ \
+}
+
+/*******************************************************************************
+ *****************************   PROTOTYPES   **********************************
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * @brief
+ *   Clear the CRYOTIMER period interrupt.
+ *
+ * @param[in] flags
+ *   CRYOTIMER interrupt sources to clear. Use CRYOTIMER_IFC_PERIOD
+ ******************************************************************************/
+__STATIC_INLINE void CRYOTIMER_IntClear(uint32_t flags)
+{
+  CRYOTIMER->IFC = flags & _CRYOTIMER_IFC_MASK;
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Get the CRYOTIMER interrupt flag.
+ * 
+ * @note
+ *   The event bits are not cleared by the use of this function.
+ *
+ * @return
+ *   Pending CRYOTIMER interrupt sources.
+ ******************************************************************************/
+__STATIC_INLINE uint32_t CRYOTIMER_IntGet(void)
+{
+  return CRYOTIMER->IF;
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Get enabled and pending CRYOTIMER interrupt flags.
+ *   Useful for handling more interrupt sources in the same interrupt handler.
+ *
+ * @note
+ *   Interrupt flags are not cleared by the use of this function.
+ *
+ * @return
+ *   Pending and enabled CRYOTIMER interrupt sources
+ *   The return value is the bitwise AND of
+ *   - the enabled interrupt sources in CRYOTIMER_IEN and
+ *   - the pending interrupt flags CRYOTIMER_IF
+ ******************************************************************************/
+__STATIC_INLINE uint32_t CRYOTIMER_IntGetEnabled(void)
+{
+  uint32_t ien;
+
+  ien = CRYOTIMER->IEN & _CRYOTIMER_IEN_MASK;
+  return CRYOTIMER->IF & ien;
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Enable one or more CRYOTIMER interrupts.
+ *
+ * @param[in] flags
+ *   CRYOTIMER interrupt sources to enable. Use CRYOTIMER_IEN_PERIOD.
+ ******************************************************************************/
+__STATIC_INLINE void CRYOTIMER_IntEnable(uint32_t flags)
+{
+  CRYOTIMER->IEN |= (flags & _CRYOTIMER_IEN_MASK);
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Disable one or more CRYOTIMER interrupts.
+ *
+ * @param[in] flags
+ *   CRYOTIMER interrupt sources to disable. Use CRYOTIMER_IEN_PERIOD.
+ ******************************************************************************/
+__STATIC_INLINE void CRYOTIMER_IntDisable(uint32_t flags)
+{
+  CRYOTIMER->IEN &= ~(flags & _CRYOTIMER_IEN_MASK);
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Set the CRYOTIMER period interrupt flag.
+ *
+ * @note
+ *   Writes 1 to the interrupt flag set register.
+ *
+ * @param[in] flags
+ *   CRYOTIMER interrupt sources to set to pending. Use CRYOTIMER_IFS_PERIOD.
+ ******************************************************************************/
+__STATIC_INLINE void CRYOTIMER_IntSet(uint32_t flags)
+{
+  CRYOTIMER->IFS = flags & _CRYOTIMER_IFS_MASK;
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Set the CRYOTIMER period select
+ *
+ * @note
+ *   Sets the duration between the Interrupts/Wakeup events based on 
+ *   the pre-scaled clock.
+ *
+ * @param[in] period
+ *   2^period is the number of clock cycles before a wakeup event or 
+ *   interrupt is triggered. The CRYOTIMER_Periodsel_TypeDef enum can 
+ *   be used a convenience type when calling this function.
+ ******************************************************************************/
+__STATIC_INLINE void CRYOTIMER_PeriodSet(uint32_t period)
+{
+  CRYOTIMER->PERIODSEL = period & _CRYOTIMER_PERIODSEL_MASK;
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Get the CRYOTIMER period select value
+ *
+ * @note
+ *   Gets the duration between the Interrupts/Wakeup events in the 
+ *   CRYOTIMER.
+ *
+ * @return
+ *   Duration between the interrupts/wakeup events. Returns the value
+ *   of the PERIODSEL register. The number of clock cycles can be calculated
+ *   as the 2^n where n is the return value of this function.
+ ******************************************************************************/
+__STATIC_INLINE uint32_t CRYOTIMER_PeriodGet(void)
+{
+  return CRYOTIMER->PERIODSEL;
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Get the CRYOTIMER counter value
+ *
+ * @return
+ *   Returns the current CRYOTIMER counter value.
+ ******************************************************************************/
+__STATIC_INLINE uint32_t CRYOTIMER_CounterGet(void)
+{
+  return CRYOTIMER->CNT;
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Enable/disable EM4 wakeup capability.
+ *
+ * @param[in] enable
+ *   True to enable EM4 wakeup, false to disable.
+ ******************************************************************************/
+__STATIC_INLINE void CRYOTIMER_EM4WakeupEnable(bool enable)
+{
+  BUS_RegBitWrite((&CRYOTIMER->EM4WUEN), _CRYOTIMER_EM4WUEN_EM4WU_SHIFT, enable);
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Enable/disable the CRYOTIMER.
+ *
+ * @param[in] enable
+ *   True to enable the CRYOTIMER, false to disable.
+ ******************************************************************************/
+__STATIC_INLINE void CRYOTIMER_Enable(bool enable)
+{
+  BUS_RegBitWrite((&CRYOTIMER->CTRL), _CRYOTIMER_CTRL_EN_SHIFT, enable);
+}
+
+void CRYOTIMER_Init(const CRYOTIMER_Init_TypeDef *init);
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} (end addtogroup CRYOTIMER) */
+/** @} (end addtogroup EM_Library) */
+
+#endif /* defined(CRYOTIMER_PRESENT) && (CRYOTIMER_COUNT == 1) */
+#endif /* EM_CRYOTIMER_H__ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_crypto.h	Fri Jan 15 07:45:16 2016 +0000
@@ -0,0 +1,1334 @@
+/***************************************************************************//**
+ * @file em_crypto.h
+ * @brief Cryptography accelerator peripheral API
+ * @version 4.2.1
+ *******************************************************************************
+ * @section License
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
+ *******************************************************************************
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
+ * obligation to support this Software. Silicon Labs is providing the
+ * Software "AS IS", with no express or implied warranties of any kind,
+ * including, but not limited to, any implied warranties of merchantability
+ * or fitness for any particular purpose or warranties against infringement
+ * of any proprietary rights of a third party.
+ *
+ * Silicon Labs will not be liable for any consequential, incidental, or
+ * special damages, or any other relief, or for any claim by any third party,
+ * arising from your use of this Software.
+ *
+ ******************************************************************************/
+#ifndef __SILICON_LABS_EM_CRYPTO_H__
+#define __SILICON_LABS_EM_CRYPTO_H__
+
+#include "em_device.h"
+
+#if defined(CRYPTO_COUNT) && (CRYPTO_COUNT > 0)
+
+#include "em_bus.h"
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************************************************************//**
+ * @addtogroup EM_Library
+ * @{
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * @addtogroup CRYPTO
+ * @{
+ ******************************************************************************/
+
+ /*******************************************************************************
+ ******************************   DEFINES    ***********************************
+ ******************************************************************************/
+
+/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
+/** Data sizes used by CRYPTO operations. */
+#define CRYPTO_DATA_SIZE_IN_BITS           (128)
+#define CRYPTO_DATA_SIZE_IN_BYTES          (CRYPTO_DATA_SIZE_IN_BITS/8)
+#define CRYPTO_DATA_SIZE_IN_32BIT_WORDS    (CRYPTO_DATA_SIZE_IN_BYTES/sizeof(uint32_t))
+
+#define CRYPTO_KEYBUF_SIZE_IN_BITS         (256)
+#define CRYPTO_KEYBUF_SIZE_IN_BYTES        (CRYPTO_DDATA_SIZE_IN_BITS/8)
+#define CRYPTO_KEYBUF_SIZE_IN_32BIT_WORDS  (CRYPTO_DDATA_SIZE_IN_BYTES/sizeof(uint32_t))
+
+#define CRYPTO_DDATA_SIZE_IN_BITS          (256)
+#define CRYPTO_DDATA_SIZE_IN_BYTES         (CRYPTO_DDATA_SIZE_IN_BITS/8)
+#define CRYPTO_DDATA_SIZE_IN_32BIT_WORDS   (CRYPTO_DDATA_SIZE_IN_BYTES/sizeof(uint32_t))
+
+#define CRYPTO_QDATA_SIZE_IN_BITS          (512)
+#define CRYPTO_QDATA_SIZE_IN_BYTES         (CRYPTO_QDATA_SIZE_IN_BITS/8)
+#define CRYPTO_QDATA_SIZE_IN_32BIT_WORDS   (CRYPTO_QDATA_SIZE_IN_BYTES/sizeof(uint32_t))
+
+#define CRYPTO_DATA260_SIZE_IN_32BIT_WORDS (9)
+
+/** SHA-1 digest sizes */
+#define CRYPTO_SHA1_DIGEST_SIZE_IN_BITS    (160)
+#define CRYPTO_SHA1_DIGEST_SIZE_IN_BYTES   (CRYPTO_SHA1_DIGEST_SIZE_IN_BITS/8)
+
+/** SHA-256 digest sizes */
+#define CRYPTO_SHA256_DIGEST_SIZE_IN_BITS  (256)
+#define CRYPTO_SHA256_DIGEST_SIZE_IN_BYTES (CRYPTO_SHA256_DIGEST_SIZE_IN_BITS/8)
+
+/**
+ * Read and write all 260 bits of DDATA0 when in 260 bit mode.
+ */
+#define CRYPTO_DDATA0_260_BITS_READ(bigint260)  CRYPTO_DData0Read260(bigint260)
+#define CRYPTO_DDATA0_260_BITS_WRITE(bigint260) CRYPTO_DData0Write260(bigint260)
+/** @endcond */
+
+/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
+/**
+ * Instruction sequence load macros CRYPTO_SEQ_LOAD_X (where X is in the range
+ * 1-20). E.g. @ref CRYPTO_SEQ_LOAD_20.
+ * Use these macros in order for faster execution than the function API.
+ */
+#define CRYPTO_SEQ_LOAD_1(a1) { \
+    CRYPTO->SEQ0 =  a1 |  (CRYPTO_CMD_INSTR_END<<8);}
+#define CRYPTO_SEQ_LOAD_2(a1, a2) { \
+    CRYPTO->SEQ0 =  a1 |  (a2<<8) |  (CRYPTO_CMD_INSTR_END<<16);}
+#define CRYPTO_SEQ_LOAD_3(a1, a2, a3) { \
+    CRYPTO->SEQ0 =  a1 |  (a2<<8) |  (a3<<16) | (CRYPTO_CMD_INSTR_END<<24);}
+#define CRYPTO_SEQ_LOAD_4(a1, a2, a3, a4) { \
+    CRYPTO->SEQ0 =  a1 |  (a2<<8) |  (a3<<16) |  (a4<<24);              \
+    CRYPTO->SEQ1 =  CRYPTO_CMD_INSTR_END;}
+#define CRYPTO_SEQ_LOAD_5(a1, a2, a3, a4, a5) { \
+    CRYPTO->SEQ0 =  a1 |  (a2<<8) |  (a3<<16) |  (a4<<24);              \
+    CRYPTO->SEQ1 =  a5 |  (CRYPTO_CMD_INSTR_END<<8);}
+#define CRYPTO_SEQ_LOAD_6(a1, a2, a3, a4, a5, a6) { \
+    CRYPTO->SEQ0 =  a1 |  (a2<<8) |  (a3<<16) |  (a4<<24);              \
+    CRYPTO->SEQ1 =  a5 |  (a6<<8) |  (CRYPTO_CMD_INSTR_END<<16);}
+#define CRYPTO_SEQ_LOAD_7(a1, a2, a3, a4, a5, a6, a7) { \
+    CRYPTO->SEQ0 =  a1 |  (a2<<8) |  (a3<<16) |  (a4<<24);              \
+    CRYPTO->SEQ1 =  a5 |  (a6<<8) |  (a7<<16) |  (CRYPTO_CMD_INSTR_END<<24);}
+#define CRYPTO_SEQ_LOAD_8(a1, a2, a3, a4, a5, a6, a7, a8) { \
+    CRYPTO->SEQ0 =  a1 |  (a2<<8) |  (a3<<16) |  (a4<<24);              \
+    CRYPTO->SEQ1 =  a5 |  (a6<<8) |  (a7<<16) |  (a8<<24);              \
+    CRYPTO->SEQ2 =  CRYPTO_CMD_INSTR_END;}
+#define CRYPTO_SEQ_LOAD_9(a1, a2, a3, a4, a5, a6, a7, a8, a9) { \
+    CRYPTO->SEQ0 =  a1 |  (a2<<8) |  (a3<<16) |  (a4<<24);              \
+    CRYPTO->SEQ1 =  a5 |  (a6<<8) |  (a7<<16) |  (a8<<24);              \
+    CRYPTO->SEQ2 =  a9 | (CRYPTO_CMD_INSTR_END<<8);}
+#define CRYPTO_SEQ_LOAD_10(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10) { \
+    CRYPTO->SEQ0 =  a1 |  (a2<<8) |  (a3<<16) |  (a4<<24);              \
+    CRYPTO->SEQ1 =  a5 |  (a6<<8) |  (a7<<16) |  (a8<<24);              \
+    CRYPTO->SEQ2 =  a9 | (a10<<8) | (CRYPTO_CMD_INSTR_END<<16);}
+#define CRYPTO_SEQ_LOAD_11(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11) { \
+    CRYPTO->SEQ0 =  a1 |  (a2<<8) |  (a3<<16) |  (a4<<24);              \
+    CRYPTO->SEQ1 =  a5 |  (a6<<8) |  (a7<<16) |  (a8<<24);              \
+    CRYPTO->SEQ2 =  a9 | (a10<<8) | (a11<<16) | (CRYPTO_CMD_INSTR_END<<24);}
+#define CRYPTO_SEQ_LOAD_12(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12) { \
+    CRYPTO->SEQ0 =  a1 |  (a2<<8) |  (a3<<16) |  (a4<<24);              \
+    CRYPTO->SEQ1 =  a5 |  (a6<<8) |  (a7<<16) |  (a8<<24);              \
+    CRYPTO->SEQ2 =  a9 | (a10<<8) | (a11<<16) | (a12<<24);              \
+    CRYPTO->SEQ3 = CRYPTO_CMD_INSTR_END;}
+#define CRYPTO_SEQ_LOAD_13(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13) { \
+    CRYPTO->SEQ0 =  a1 |  (a2<<8) |  (a3<<16) |  (a4<<24);              \
+    CRYPTO->SEQ1 =  a5 |  (a6<<8) |  (a7<<16) |  (a8<<24);              \
+    CRYPTO->SEQ2 =  a9 | (a10<<8) | (a11<<16) | (a12<<24);              \
+    CRYPTO->SEQ3 = a13 | (CRYPTO_CMD_INSTR_END<<8);}
+#define CRYPTO_SEQ_LOAD_14(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14) { \
+    CRYPTO->SEQ0 =  a1 |  (a2<<8) |  (a3<<16) |  (a4<<24);              \
+    CRYPTO->SEQ1 =  a5 |  (a6<<8) |  (a7<<16) |  (a8<<24);              \
+    CRYPTO->SEQ2 =  a9 | (a10<<8) | (a11<<16) | (a12<<24);              \
+    CRYPTO->SEQ3 = a13 | (a14<<8) | (CRYPTO_CMD_INSTR_END<<16);}
+#define CRYPTO_SEQ_LOAD_15(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15) { \
+    CRYPTO->SEQ0 =  a1 |  (a2<<8) |  (a3<<16) |  (a4<<24);              \
+    CRYPTO->SEQ1 =  a5 |  (a6<<8) |  (a7<<16) |  (a8<<24);              \
+    CRYPTO->SEQ2 =  a9 | (a10<<8) | (a11<<16) | (a12<<24);              \
+    CRYPTO->SEQ3 = a13 | (a14<<8) | (a15<<16) | (CRYPTO_CMD_INSTR_END<<24);}
+#define CRYPTO_SEQ_LOAD_16(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16) { \
+    CRYPTO->SEQ0 =  a1 |  (a2<<8) |  (a3<<16) |  (a4<<24);              \
+    CRYPTO->SEQ1 =  a5 |  (a6<<8) |  (a7<<16) |  (a8<<24);              \
+    CRYPTO->SEQ2 =  a9 | (a10<<8) | (a11<<16) | (a12<<24);              \
+    CRYPTO->SEQ3 = a13 | (a14<<8) | (a15<<16) | (a16<<24);              \
+    CRYPTO->SEQ4 = CRYPTO_CMD_INSTR_END;}
+#define CRYPTO_SEQ_LOAD_17(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16, a17) { \
+    CRYPTO->SEQ0 =  a1 |  (a2<<8) |  (a3<<16) |  (a4<<24);              \
+    CRYPTO->SEQ1 =  a5 |  (a6<<8) |  (a7<<16) |  (a8<<24);              \
+    CRYPTO->SEQ2 =  a9 | (a10<<8) | (a11<<16) | (a12<<24);              \
+    CRYPTO->SEQ3 = a13 | (a14<<8) | (a15<<16) | (a16<<24);              \
+    CRYPTO->SEQ4 = a17 | (CRYPTO_CMD_INSTR_END<<8);}
+#define CRYPTO_SEQ_LOAD_18(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16, a17, a18) { \
+    CRYPTO->SEQ0 =  a1 |  (a2<<8) |  (a3<<16) |  (a4<<24);              \
+    CRYPTO->SEQ1 =  a5 |  (a6<<8) |  (a7<<16) |  (a8<<24);              \
+    CRYPTO->SEQ2 =  a9 | (a10<<8) | (a11<<16) | (a12<<24);              \
+    CRYPTO->SEQ3 = a13 | (a14<<8) | (a15<<16) | (a16<<24);              \
+    CRYPTO->SEQ4 = a17 | (a18<<8) | (CRYPTO_CMD_INSTR_END<<16);}
+#define CRYPTO_SEQ_LOAD_19(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16, a17, a18, a19) { \
+    CRYPTO->SEQ0 =  a1 |  (a2<<8) |  (a3<<16) |  (a4<<24);              \
+    CRYPTO->SEQ1 =  a5 |  (a6<<8) |  (a7<<16) |  (a8<<24);              \
+    CRYPTO->SEQ2 =  a9 | (a10<<8) | (a11<<16) | (a12<<24);              \
+    CRYPTO->SEQ3 = a13 | (a14<<8) | (a15<<16) | (a16<<24);              \
+    CRYPTO->SEQ4 = a17 | (a18<<8) | (a19<<16) | (CRYPTO_CMD_INSTR_END<<24);}
+#define CRYPTO_SEQ_LOAD_20(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16, a17, a18, a19, a20) { \
+    CRYPTO->SEQ0 =  a1 |  (a2<<8) |  (a3<<16) |  (a4<<24);              \
+    CRYPTO->SEQ1 =  a5 |  (a6<<8) |  (a7<<16) |  (a8<<24);              \
+    CRYPTO->SEQ2 =  a9 | (a10<<8) | (a11<<16) | (a12<<24);              \
+    CRYPTO->SEQ3 = a13 | (a14<<8) | (a15<<16) | (a16<<24);              \
+    CRYPTO->SEQ4 = a17 | (a18<<8) | (a19<<16) | (a20<<24);}
+/** @endcond */
+
+/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
+/**
+ * Instruction sequence execution macros CRYPTO_EXECUTE_X (where X is in the range
+ * 1-20). E.g. @ref CRYPTO_EXECUTE_19.
+ * Use these macros in order for faster execution than the function API.
+ */
+#define CRYPTO_EXECUTE_1(a1) {                                          \
+    CRYPTO->SEQ0 = a1 | (CRYPTO_CMD_INSTR_EXEC<<8);                    }
+#define CRYPTO_EXECUTE_2(a1, a2) {                                      \
+    CRYPTO->SEQ0 = a1 | (a2<<8) | (CRYPTO_CMD_INSTR_EXEC<<16);         }
+#define CRYPTO_EXECUTE_3(a1, a2, a3) {                                  \
+    CRYPTO->SEQ0 = a1 | (a2<<8) | (a3<<16) | (CRYPTO_CMD_INSTR_EXEC<<24); }
+#define CRYPTO_EXECUTE_4(a1, a2, a3, a4) {                              \
+    CRYPTO->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24);                  \
+    CRYPTO->SEQ1 = CRYPTO_CMD_INSTR_EXEC;                              }
+#define CRYPTO_EXECUTE_5(a1, a2, a3, a4, a5) {                          \
+    CRYPTO->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24);                  \
+    CRYPTO->SEQ1 = a5 | (CRYPTO_CMD_INSTR_EXEC<<8);                    }
+#define CRYPTO_EXECUTE_6(a1, a2, a3, a4, a5, a6) {                      \
+    CRYPTO->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24);                  \
+    CRYPTO->SEQ1 = a5 | (a6<<8) | (CRYPTO_CMD_INSTR_EXEC<<16);         }
+#define CRYPTO_EXECUTE_7(a1, a2, a3, a4, a5, a6, a7) {                  \
+    CRYPTO->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24);                  \
+    CRYPTO->SEQ1 = a5 | (a6<<8) | (a7<<16) | (CRYPTO_CMD_INSTR_EXEC<<24); }
+#define CRYPTO_EXECUTE_8(a1, a2, a3, a4, a5, a6, a7, a8) {              \
+    CRYPTO->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24);                  \
+    CRYPTO->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24);                  \
+    CRYPTO->SEQ2 = CRYPTO_CMD_INSTR_EXEC;                              }
+#define CRYPTO_EXECUTE_9(a1, a2, a3, a4, a5, a6, a7, a8, a9) {          \
+    CRYPTO->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24);                  \
+    CRYPTO->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24);                  \
+    CRYPTO->SEQ2 = a9 | (CRYPTO_CMD_INSTR_EXEC<<8);                    }
+#define CRYPTO_EXECUTE_10(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10) {    \
+    CRYPTO->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24);                  \
+    CRYPTO->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24);                  \
+    CRYPTO->SEQ2 = a9 | (a10<<8) | (CRYPTO_CMD_INSTR_EXEC<<16);        }
+#define CRYPTO_EXECUTE_11(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11) { \
+    CRYPTO->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24);                  \
+    CRYPTO->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24);                  \
+    CRYPTO->SEQ2 = a9 | (a10<<8) | (a11<<16) | (CRYPTO_CMD_INSTR_EXEC<<24); }
+#define CRYPTO_EXECUTE_12(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12) { \
+    CRYPTO->SEQ0 = a1 |  (a2<<8) |  (a3<<16) | (a4<<24);                \
+    CRYPTO->SEQ1 = a5 |  (a6<<8) |  (a7<<16) | (a8<<24);                \
+    CRYPTO->SEQ2 = a9 | (a10<<8) | (a11<<16) | (a12<<24);               \
+    CRYPTO->SEQ3 = CRYPTO_CMD_INSTR_EXEC;                              }
+#define CRYPTO_EXECUTE_13(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13) { \
+    CRYPTO->SEQ0 = a1  | (a2<<8)  | (a3<<16)  | (a4<<24);               \
+    CRYPTO->SEQ1 = a5  | (a6<<8)  | (a7<<16)  | (a8<<24);               \
+    CRYPTO->SEQ2 = a9  | (a10<<8) | (a11<<16) | (a12<<24);              \
+    CRYPTO->SEQ3 = a13 | (CRYPTO_CMD_INSTR_EXEC<<8);                   }
+#define CRYPTO_EXECUTE_14(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14) { \
+    CRYPTO->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24);                  \
+    CRYPTO->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24);                  \
+    CRYPTO->SEQ2 = a9 | (a10<<8) | (a11<<16) | (a12<<24);               \
+    CRYPTO->SEQ3 = a13 | (a14<<8) | (CRYPTO_CMD_INSTR_EXEC<<16);       }
+#define CRYPTO_EXECUTE_15(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15) { \
+    CRYPTO->SEQ0 =  a1 |  (a2<<8) |  (a3<<16) |  (a4<<24);              \
+    CRYPTO->SEQ1 =  a5 |  (a6<<8) |  (a7<<16) |  (a8<<24);              \
+    CRYPTO->SEQ2 =  a9 | (a10<<8) | (a11<<16) | (a12<<24);              \
+    CRYPTO->SEQ3 = a13 | (a14<<8) | (a15<<16) | (CRYPTO_CMD_INSTR_EXEC<<24); }
+#define CRYPTO_EXECUTE_16(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16) { \
+    CRYPTO->SEQ0 =  a1 |  (a2<<8) |  (a3<<16) |  (a4<<24);              \
+    CRYPTO->SEQ1 =  a5 |  (a6<<8) |  (a7<<16) |  (a8<<24);              \
+    CRYPTO->SEQ2 =  a9 | (a10<<8) | (a11<<16) | (a12<<24);              \
+    CRYPTO->SEQ3 = a13 | (a14<<8) | (a15<<16) | (a16<<24);              \
+    CRYPTO->SEQ4 = CRYPTO_CMD_INSTR_EXEC;                              }
+#define CRYPTO_EXECUTE_17(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16, a17) { \
+    CRYPTO->SEQ0 =  a1 |  (a2<<8) |  (a3<<16) | (a4<<24);               \
+    CRYPTO->SEQ1 =  a5 |  (a6<<8) |  (a7<<16) | (a8<<24);               \
+    CRYPTO->SEQ2 =  a9 | (a10<<8) | (a11<<16) | (a12<<24);              \
+    CRYPTO->SEQ3 = a13 | (a14<<8) | (a15<<16) | (a16<<24);              \
+    CRYPTO->SEQ4 = a17 | (CRYPTO_CMD_INSTR_EXEC<<8);                   }
+#define CRYPTO_EXECUTE_18(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16, a17, a18) { \
+    CRYPTO->SEQ0 =  a1 |  (a2<<8) |  (a3<<16) |  (a4<<24);              \
+    CRYPTO->SEQ1 =  a5 |  (a6<<8) |  (a7<<16) |  (a8<<24);              \
+    CRYPTO->SEQ2 =  a9 | (a10<<8) | (a11<<16) | (a12<<24);              \
+    CRYPTO->SEQ3 = a13 | (a14<<8) | (a15<<16) | (a16<<24);              \
+    CRYPTO->SEQ4 = a17 | (a18<<8) | (CRYPTO_CMD_INSTR_EXEC<<16);       }
+#define CRYPTO_EXECUTE_19(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16, a17, a18, a19) { \
+    CRYPTO->SEQ0 =  a1 |  (a2<<8) |  (a3<<16) |  (a4<<24);              \
+    CRYPTO->SEQ1 =  a5 |  (a6<<8) |  (a7<<16) |  (a8<<24);              \
+    CRYPTO->SEQ2 =  a9 | (a10<<8) | (a11<<16) | (a12<<24);              \
+    CRYPTO->SEQ3 = a13 | (a14<<8) | (a15<<16) | (a16<<24);              \
+    CRYPTO->SEQ4 = a17 | (a18<<8) | (a19<<16) | (CRYPTO_CMD_INSTR_EXEC<<24); }
+#define CRYPTO_EXECUTE_20(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16, a17, a18, a19, a20) { \
+    CRYPTO->SEQ0 =  a1 |  (a2<<8) |  (a3<<16) |  (a4<<24);              \
+    CRYPTO->SEQ1 =  a5 |  (a6<<8) |  (a7<<16) |  (a8<<24);              \
+    CRYPTO->SEQ2 =  a9 | (a10<<8) | (a11<<16) | (a12<<24);              \
+    CRYPTO->SEQ3 = a13 | (a14<<8) | (a15<<16) | (a16<<24);              \
+    CRYPTO->SEQ4 = a17 | (a18<<8) | (a19<<16) | (a20<<24);              \
+    CRYPTO_InstructionSequenceExecute();}
+/** @endcond */
+
+/*******************************************************************************
+ ******************************   TYPEDEFS   ***********************************
+ ******************************************************************************/
+
+/**
+ * CRYPTO data types used for data load functions. This data type is
+ * capable of storing a 128 bits value as used in the crypto DATA
+ * registers
+ */
+typedef uint32_t CRYPTO_Data_TypeDef[CRYPTO_DATA_SIZE_IN_32BIT_WORDS];
+
+/**
+ * CRYPTO data type used for data load functions. This data type
+ * is capable of storing a 256 bits value as used in the crypto DDATA
+ * registers
+ */
+typedef uint32_t CRYPTO_DData_TypeDef[CRYPTO_DDATA_SIZE_IN_32BIT_WORDS];
+
+/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
+typedef uint32_t* CRYPTO_DDataPtr_TypeDef;
+/** @endcond */
+
+/**
+ * CRYPTO data type used for data load functions. This data type is
+ * capable of storing a 512 bits value as used in the crypto QDATA
+ * registers
+ */
+typedef uint32_t CRYPTO_QData_TypeDef[CRYPTO_QDATA_SIZE_IN_32BIT_WORDS];
+
+/**
+ * CRYPTO data type used for data load functions. This data type is
+ * capable of storing a 260 bits value as used by the @ref CRYPTO_DData0Write260
+ * function.
+ *
+ * Note that this data type is multiple of 32 bit words, so the
+ * actual storage used by this type is 32x9=288 bits.
+ */
+typedef uint32_t CRYPTO_Data260_TypeDef[CRYPTO_DATA260_SIZE_IN_32BIT_WORDS];
+
+/**
+ * CRYPTO data type used for data load functions. This data type is
+ * capable of storing 256 bits as used in the crypto KEYBUF register.
+ */
+typedef uint32_t CRYPTO_KeyBuf_TypeDef[CRYPTO_KEYBUF_SIZE_IN_32BIT_WORDS];
+
+/**
+ * CRYPTO Data registers. These register are used to load 128 bit values as
+ * input and output data for cryptographic and big integer arithmetic
+ * functions of the CRYPTO module.
+ */
+typedef enum
+{
+  cryptoRegDATA0    = (uint32_t) &CRYPTO->DATA0,    /**< 128 bit DATA0 register */
+  cryptoRegDATA1    = (uint32_t) &CRYPTO->DATA1,    /**< 128 bit DATA1 register */
+  cryptoRegDATA2    = (uint32_t) &CRYPTO->DATA2,    /**< 128 bit DATA2 register */
+  cryptoRegDATA3    = (uint32_t) &CRYPTO->DATA3,    /**< 128 bit DATA3 register */
+  cryptoRegDATA0XOR = (uint32_t) &CRYPTO->DATA0XOR, /**< 128 bit DATA0XOR register */
+} CRYPTO_DataReg_TypeDef;
+
+/**
+ * CRYPTO DData (Double Data) registers. These registers are used to load
+ * 256 bit values as input and output data for cryptographic and big integer
+ * arithmetic functions of the CRYPTO module.
+ */
+typedef enum
+{
+  cryptoRegDDATA0    = (uint32_t) &CRYPTO->DDATA0,    /**< 256 bit DDATA0 register */
+  cryptoRegDDATA1    = (uint32_t) &CRYPTO->DDATA1,    /**< 256 bit DDATA1 register */
+  cryptoRegDDATA2    = (uint32_t) &CRYPTO->DDATA2,    /**< 256 bit DDATA2 register */
+  cryptoRegDDATA3    = (uint32_t) &CRYPTO->DDATA3,    /**< 256 bit DDATA3 register */
+  cryptoRegDDATA4    = (uint32_t) &CRYPTO->DDATA4,    /**< 256 bit DDATA4 register */
+  cryptoRegDDATA0BIG = (uint32_t) &CRYPTO->DDATA0BIG, /**< 256 bit DDATA0BIG register, big endian access to DDATA0 */
+} CRYPTO_DDataReg_TypeDef;
+
+/**
+ * CRYPTO QData (Quad data) registers. These registers are used to load 512 bit
+ * values as input and output data for cryptographic and big integer arithmetic
+ * functions of the CRYPTO module.
+ */
+typedef enum
+{
+  cryptoRegQDATA0    = (uint32_t) &CRYPTO->QDATA0,    /**< 512 bit QDATA0 register */
+  cryptoRegQDATA1    = (uint32_t) &CRYPTO->QDATA1,    /**< 512 bit QDATA1 register */
+  cryptoRegQDATA1BIG = (uint32_t) &CRYPTO->QDATA1BIG, /**< 512 bit QDATA1BIG register, big-endian access to QDATA1 */
+} CRYPTO_QDataReg_TypeDef;
+
+/** CRYPTO modulus types. */
+typedef enum
+{
+  cryptoModulusBin256        = CRYPTO_WAC_MODULUS_BIN256,       /**< Generic 256 bit modulus 2^256 */
+  cryptoModulusBin128        = CRYPTO_WAC_MODULUS_BIN128,       /**< Generic 128 bit modulus 2^128 */
+  cryptoModulusGcmBin128     = CRYPTO_WAC_MODULUS_GCMBIN128,    /**< GCM 128 bit modulus = 2^128 + 2^7 + 2^2 + 2 + 1 */
+  cryptoModulusEccB233       = CRYPTO_WAC_MODULUS_ECCBIN233P,   /**< ECC B233 prime modulus = 2^233 + 2^74 + 1   */
+  cryptoModulusEccB163       = CRYPTO_WAC_MODULUS_ECCBIN163P,   /**< ECC B163 prime modulus = 2^163 + 2^7 + 2^6 + 2^3 + 1 */
+  cryptoModulusEccP256       = CRYPTO_WAC_MODULUS_ECCPRIME256P, /**< ECC P256 prime modulus = 2^256 - 2^224 + 2^192 + 2^96 - 1 */
+  cryptoModulusEccP224       = CRYPTO_WAC_MODULUS_ECCPRIME224P, /**< ECC P224 prime modulus = 2^224 - 2^96 - 1 */
+  cryptoModulusEccP192       = CRYPTO_WAC_MODULUS_ECCPRIME192P, /**< ECC P192 prime modulus = 2^192 - 2^64 - 1 */
+  cryptoModulusEccB233Order  = CRYPTO_WAC_MODULUS_ECCBIN233N,   /**< ECC B233 order modulus   */
+  cryptoModulusEccB233KOrder = CRYPTO_WAC_MODULUS_ECCBIN233KN,  /**< ECC B233K order modulus */
+  cryptoModulusEccB163Order  = CRYPTO_WAC_MODULUS_ECCBIN163N,   /**< ECC B163 order modulus */
+  cryptoModulusEccB163KOrder = CRYPTO_WAC_MODULUS_ECCBIN163KN,  /**< ECC B163K order modulus */
+  cryptoModulusEccP256Order  = CRYPTO_WAC_MODULUS_ECCPRIME256N, /**< ECC P256 order modulus */
+  cryptoModulusEccP224Order  = CRYPTO_WAC_MODULUS_ECCPRIME224N, /**< ECC P224 order modulus */
+  cryptoModulusEccP192Order  = CRYPTO_WAC_MODULUS_ECCPRIME192N  /**< ECC P192 order modulus */
+} CRYPTO_ModulusType_TypeDef;
+
+/** CRYPTO multiplication widths for wide arithmetic operations. */
+typedef enum
+{
+  cryptoMulOperand256Bits     = CRYPTO_WAC_MULWIDTH_MUL256, /**< 256 bits operands */
+  cryptoMulOperand128Bits     = CRYPTO_WAC_MULWIDTH_MUL128, /**< 128 bits operands */
+  cryptoMulOperandModulusBits = CRYPTO_WAC_MULWIDTH_MULMOD  /**< MUL operand width
+                                                                 is specified by the
+                                                                 modulus type.*/
+} CRYPTO_MulOperandWidth_TypeDef;
+
+/** CRYPTO result widths for MUL operations. */
+typedef enum
+{
+  cryptoResult128Bits = CRYPTO_WAC_RESULTWIDTH_128BIT, /**< Multiplication result width is 128 bits*/
+  cryptoResult256Bits = CRYPTO_WAC_RESULTWIDTH_256BIT, /**< Multiplication result width is 256 bits*/
+  cryptoResult260Bits = CRYPTO_WAC_RESULTWIDTH_260BIT  /**< Multiplication result width is 260 bits*/
+} CRYPTO_ResultWidth_TypeDef;
+
+/** CRYPTO result widths for MUL operations. */
+typedef enum
+{
+  cryptoInc1byte = CRYPTO_CTRL_INCWIDTH_INCWIDTH1, /**< inc width is 1 byte*/
+  cryptoInc2byte = CRYPTO_CTRL_INCWIDTH_INCWIDTH2, /**< inc width is 2 byte*/
+  cryptoInc3byte = CRYPTO_CTRL_INCWIDTH_INCWIDTH3, /**< inc width is 3 byte*/
+  cryptoInc4byte = CRYPTO_CTRL_INCWIDTH_INCWIDTH4  /**< inc width is 4 byte*/
+} CRYPTO_IncWidth_TypeDef;
+
+/** CRYPTO key width. */
+typedef enum
+{
+  cryptoKey128Bits = 8,     /**< Key width is 128 bits*/
+  cryptoKey256Bits = 16,    /**< Key width is 256 bits*/
+} CRYPTO_KeyWidth_TypeDef;
+
+/**
+ * The max number of crypto instructions in an instruction sequence
+ */
+#define CRYPTO_MAX_SEQUENCE_INSTRUCTIONS (20)
+
+/**
+ * Instruction sequence type.
+ * The user should fill in the desired operations from step1, then step2 etc.
+ * The CRYPTO_CMD_INSTR_END marks the end of the sequence.
+ * Bit fields are used to format the memory layout of the struct equal to the
+ * sequence registers in the CRYPTO module.
+ */
+typedef uint8_t CRYPTO_InstructionSequence_TypeDef[CRYPTO_MAX_SEQUENCE_INSTRUCTIONS];
+
+/** Default instruction sequence consisting of all ENDs. The user can
+    initialize the instruction sequence with this default value set, and fill
+    in the desired operations from step 1. The first END instruction marks
+    the end of the sequence. */
+#define CRYPTO_INSTRUCTIONSEQUENSE_DEFAULT                             \
+  {CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, \
+   CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, \
+   CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, \
+   CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, \
+   CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, \
+   CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, \
+   CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END}
+
+/** SHA-1 Digest type. */
+typedef uint8_t CRYPTO_SHA1_Digest_TypeDef[CRYPTO_SHA1_DIGEST_SIZE_IN_BYTES];
+
+/** SHA-256 Digest type. */
+typedef uint8_t CRYPTO_SHA256_Digest_TypeDef[CRYPTO_SHA256_DIGEST_SIZE_IN_BYTES];
+
+/**
+ * @brief
+ *   AES counter modification function pointer.
+ *
+ * @note
+ *   This is defined in order for backwards compatibility with EFM32 em_aes.h.
+ *   The CRYPTO implementation of Counter mode does not support counter update
+ *   callbacks.
+ *   
+ * @param[in]  ctr   Counter value to be modified.
+ */
+typedef void (*CRYPTO_AES_CtrFuncPtr_TypeDef)(uint8_t * ctr);
+
+/*******************************************************************************
+ *****************************   PROTOTYPES   **********************************
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * @brief
+ *   Set the modulus type used for wide arithmetic operations.
+ *
+ * @details
+ *   This function sets the modulus type to be used by the Modulus instructions
+ *   of the CRYPTO module.
+ *
+ * @param[in]  modType  Modulus type.
+ ******************************************************************************/
+void CRYPTO_ModulusSet(CRYPTO_ModulusType_TypeDef modType);
+
+/***************************************************************************//**
+ * @brief
+ *   Set the number of bits in the operands of the MUL instruction.
+ *
+ * @details
+ *   This function sets the number of bits to be used in the operands of
+ *   the MUL instruction.
+ *
+ * @param[in]  mulOperandWidth  Multiplication width in bits.
+ ******************************************************************************/
+__STATIC_INLINE void CRYPTO_MulOperandWidthSet(CRYPTO_MulOperandWidth_TypeDef mulOperandWidth)
+{
+  uint32_t temp = CRYPTO->WAC & (~_CRYPTO_WAC_MULWIDTH_MASK);
+  CRYPTO->WAC = temp | mulOperandWidth;
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Set the width of the results of the non-modulus instructions.
+ *
+ * @details
+ *   This function sets the result width of the non-modulus instructions.
+ *
+ * @param[in]  resultWidth  Result width of non-modulus instructions.
+ ******************************************************************************/
+__STATIC_INLINE void CRYPTO_ResultWidthSet(CRYPTO_ResultWidth_TypeDef resultWidth)
+{
+  uint32_t temp = CRYPTO->WAC & (~_CRYPTO_WAC_RESULTWIDTH_MASK);
+  CRYPTO->WAC = temp | resultWidth;
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Set the width of the DATA1 increment instruction DATA1INC.
+ *
+ * @details
+ *   This function sets the width of the DATA1 increment instruction
+ *   @ref CRYPTO_CMD_INSTR_DATA1INC.
+ *
+ * @param[in]  incWidth  incrementation width.
+ ******************************************************************************/
+__STATIC_INLINE void CRYPTO_IncWidthSet(CRYPTO_IncWidth_TypeDef incWidth)
+{
+  uint32_t temp = CRYPTO->CTRL & (~_CRYPTO_CTRL_INCWIDTH_MASK);
+  CRYPTO->CTRL = temp | incWidth;
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Write a 128 bit value into a crypto register.
+ *
+ * @note
+ *   This function provide a low-level api for writing to the multi-word
+ *   registers in the crypto peripheral. Applications should prefer to use
+ *   @ref CRYPTO_DataWrite, @ref CRYPTO_DDataWrite or @ref CRYPTO_QDataWrite
+ *   for writing to the DATA, DDATA and QDATA registers.
+ *
+ * @param[in]  reg
+ *   Pointer to the crypto register.
+ *
+ * @param[in]  val
+ *   This is a pointer to 4 32 bit integers that contains the 128 bit value
+ *   which will be written to the crypto register.
+ ******************************************************************************/
+__STATIC_INLINE void CRYPTO_BurstToCrypto(volatile uint32_t * reg, const uint32_t * val)
+{
+  /* Load data from memory into local registers. */
+  register uint32_t v0 = val[0];
+  register uint32_t v1 = val[1];
+  register uint32_t v2 = val[2];
+  register uint32_t v3 = val[3];
+  /* Store data to CRYPTO */
+  *reg = v0;
+  *reg = v1;
+  *reg = v2;
+  *reg = v3;
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Read a 128 bit value from a crypto register.
+ *
+ * @note
+ *   This function provide a low-level api for reading one of the multi-word
+ *   registers in the crypto peripheral. Applications should prefer to use
+ *   @ref CRYPTO_DataRead, @ref CRYPTO_DDataRead or @ref CRYPTO_QDataRead
+ *   for reading the value of the DATA, DDATA and QDATA registers.
+ *
+ * @param[in]  reg
+ *   Pointer to the crypto register.
+ *
+ * @param[out]  val
+ *   This is a pointer to an array that is capable of holding 4 32 bit integers
+ *   that will be filled with the 128 bit value from the crypto register.
+ ******************************************************************************/
+__STATIC_INLINE void CRYPTO_BurstFromCrypto(volatile uint32_t * reg, uint32_t * val)
+{
+  /* Load data from CRYPTO into local registers. */
+  register uint32_t v0 = *reg;
+  register uint32_t v1 = *reg;
+  register uint32_t v2 = *reg;
+  register uint32_t v3 = *reg;
+  /* Store data to memory */
+  val[0] = v0;
+  val[1] = v1;
+  val[2] = v2;
+  val[3] = v3;
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Write 128 bits of data to a DATAX register in the CRYPTO module.
+ *
+ * @details
+ *   Write 128 bits of data to a DATAX register in the crypto module. The data
+ *   value is typically input to a big integer operation (see crypto
+ *   instructions).
+ *
+ * @param[in]  dataReg    The 128 bit DATA register.
+ * @param[in]  val        Value of the data to write to the DATA register.
+ ******************************************************************************/
+__STATIC_INLINE void CRYPTO_DataWrite(CRYPTO_DataReg_TypeDef dataReg,
+                                      const CRYPTO_Data_TypeDef val)
+{
+  CRYPTO_BurstToCrypto((volatile uint32_t *)dataReg, val);
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Read 128 bits of data from a DATAX register in the CRYPTO module.
+ *
+ * @details
+ *   Read 128 bits of data from a DATAX register in the crypto module. The data
+ *   value is typically output from a big integer operation (see crypto
+ *   instructions)
+ *
+ * @param[in]  dataReg   The 128 bit DATA register.
+ * @param[out] val       Location where to store the value in memory.
+ ******************************************************************************/
+__STATIC_INLINE void CRYPTO_DataRead(CRYPTO_DataReg_TypeDef  dataReg,
+                                     CRYPTO_Data_TypeDef     val)
+{
+  CRYPTO_BurstFromCrypto((volatile uint32_t *)dataReg, val);
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Write 256 bits of data to a DDATAX register in the CRYPTO module.
+ *
+ * @details
+ *   Write 256 bits of data into a DDATAX (Double Data) register in the crypto
+ *   module. The data value is typically input to a big integer operation (see
+ *   crypto instructions).
+ *
+ * @param[in]  ddataReg   The 256 bit DDATA register.
+ * @param[in]  val        Value of the data to write to the DDATA register.
+ ******************************************************************************/
+__STATIC_INLINE void CRYPTO_DDataWrite(CRYPTO_DDataReg_TypeDef ddataReg,
+                                       const CRYPTO_DData_TypeDef val)
+{
+  CRYPTO_BurstToCrypto((volatile uint32_t *)ddataReg, &val[0]);
+  CRYPTO_BurstToCrypto((volatile uint32_t *)ddataReg, &val[4]);
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Read 256 bits of data from a DDATAX register in the CRYPTO module.
+ *
+ * @details
+ *   Read 256 bits of data from a DDATAX (Double Data) register in the crypto
+ *   module. The data value is typically output from a big integer operation
+ *   (see crypto instructions).
+ *
+ * @param[in]  ddataReg   The 256 bit DDATA register.
+ * @param[out] val        Location where to store the value in memory.
+ ******************************************************************************/
+__STATIC_INLINE void CRYPTO_DDataRead(CRYPTO_DDataReg_TypeDef ddataReg,
+                                      CRYPTO_DData_TypeDef    val)
+{
+  CRYPTO_BurstFromCrypto((volatile uint32_t *)ddataReg, &val[0]);
+  CRYPTO_BurstFromCrypto((volatile uint32_t *)ddataReg, &val[4]);
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Write 512 bits of data to a QDATAX register in the CRYPTO module.
+ *
+ * @details
+ *   Write 512 bits of data into a QDATAX (Quad Data) register in the crypto module
+ *   The data value is typically input to a big integer operation (see crypto
+ *   instructions).
+ *
+ * @param[in]  qdataReg   The 512 bits QDATA register.
+ * @param[in]  val        Value of the data to write to the QDATA register.
+ ******************************************************************************/
+__STATIC_INLINE void CRYPTO_QDataWrite(CRYPTO_QDataReg_TypeDef qdataReg,
+                                       CRYPTO_QData_TypeDef    val)
+{
+  CRYPTO_BurstToCrypto((volatile uint32_t *)qdataReg, &val[0]);
+  CRYPTO_BurstToCrypto((volatile uint32_t *)qdataReg, &val[4]);
+  CRYPTO_BurstToCrypto((volatile uint32_t *)qdataReg, &val[8]);
+  CRYPTO_BurstToCrypto((volatile uint32_t *)qdataReg, &val[12]);
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Read 512 bits of data from a QDATAX register in the CRYPTO module.
+ *
+ * @details
+ * Read 512 bits of data from a QDATAX register in the crypto module. The data
+ * value is typically input to a big integer operation (see crypto
+ * instructions).
+ *
+ * @param[in]  qdataReg   The 512 bits QDATA register.
+ * @param[in]  val        Value of the data to write to the QDATA register.
+ ******************************************************************************/
+__STATIC_INLINE void CRYPTO_QDataRead(CRYPTO_QDataReg_TypeDef qdataReg,
+                                      CRYPTO_QData_TypeDef    val)
+{
+  CRYPTO_BurstFromCrypto((volatile uint32_t *)qdataReg, &val[0]);
+  CRYPTO_BurstFromCrypto((volatile uint32_t *)qdataReg, &val[4]);
+  CRYPTO_BurstFromCrypto((volatile uint32_t *)qdataReg, &val[8]);
+  CRYPTO_BurstFromCrypto((volatile uint32_t *)qdataReg, &val[12]);
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Set the key value to be used by the CRYPTO module.
+ *
+ * @details
+ *   Write 128 or 256 bit key to the KEYBUF register in the crypto module.
+ *
+ * @param[in]  val     Value of the data to write to the KEYBUF register.
+ * @param[in]  keyWidth Key width - 128 or 256 bits
+ ******************************************************************************/
+__STATIC_INLINE void CRYPTO_KeyBufWrite(CRYPTO_KeyBuf_TypeDef    val,
+                                        CRYPTO_KeyWidth_TypeDef  keyWidth)
+{
+  if (keyWidth == cryptoKey256Bits)
+  {
+    /* Set AES-256 mode */
+    BUS_RegBitWrite(&CRYPTO->CTRL, _CRYPTO_CTRL_AES_SHIFT, _CRYPTO_CTRL_AES_AES256);
+    /* Load key in KEYBUF register (= DDATA4) */
+    CRYPTO_DDataWrite(cryptoRegDDATA4, (uint32_t *)val);
+  }
+  else
+  {
+    /* Set AES-128 mode */
+    BUS_RegBitWrite(&CRYPTO->CTRL, _CRYPTO_CTRL_AES_SHIFT, _CRYPTO_CTRL_AES_AES128);
+    CRYPTO_BurstToCrypto(&CRYPTO->KEYBUF, &val[0]);
+  }
+}
+
+void CRYPTO_KeyRead(CRYPTO_KeyBuf_TypeDef   val,
+                    CRYPTO_KeyWidth_TypeDef keyWidth);
+
+/***************************************************************************//**
+ * @brief
+ *   Quick write 128 bit key to the CRYPTO module.
+ *
+ * @details
+ *   Quick write 128 bit key to the KEYBUF register in the CRYPTO module.
+ *
+ *  @param[in]  val    Value of the data to write to the KEYBUF register.
+ ******************************************************************************/
+__STATIC_INLINE void CRYPTO_KeyBuf128Write(const uint32_t * val)
+{
+  CRYPTO_BurstToCrypto(&CRYPTO->KEYBUF, val);
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Quick read access of the Carry bit from arithmetic operations.
+ *
+ * @details
+ *   This function reads the carry bit of the CRYPTO ALU.
+ *
+ * @return
+ *   Returns 'true' if carry is 1, and 'false' if carry is 0.
+ ******************************************************************************/
+__STATIC_INLINE bool CRYPTO_CarryIsSet(void)
+{
+  return (CRYPTO->DSTATUS & _CRYPTO_DSTATUS_CARRY_MASK)
+    >> _CRYPTO_DSTATUS_CARRY_SHIFT;
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Quick read access of the 4 LSbits of the DDATA0 register.
+ *
+ * @details
+ *   This function quickly retrieves the 4 least significant bits of the
+ *   DDATA0 register via the DDATA0LSBS bit field in the DSTATUS register.
+ *
+ * @return
+ *   Returns the 4 LSbits of DDATA0.
+ ******************************************************************************/
+__STATIC_INLINE uint8_t CRYPTO_DData0_4LSBitsRead(void)
+{
+  return (CRYPTO->DSTATUS & _CRYPTO_DSTATUS_DDATA0LSBS_MASK)
+    >> _CRYPTO_DSTATUS_DDATA0LSBS_SHIFT;
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Read 260 bits from the DDATA0 register.
+ *
+ * @details
+ *   This functions reads 260 bits from the DDATA0 register in the CRYPTO
+ *   module. The data value is typically output from a big integer operation
+ *   (see crypto instructions) when the result width is set to 260 bits by
+ *   calling @ref CRYPTO_ResultWidthSet(cryptoResult260Bits);
+ *
+ * @param[out] val        Location where to store the value in memory.
+ ******************************************************************************/
+__STATIC_INLINE void CRYPTO_DData0Read260(CRYPTO_Data260_TypeDef val)
+{    
+  CRYPTO_DDataRead(cryptoRegDDATA0, val);
+  val[8] = (CRYPTO->DSTATUS & _CRYPTO_DSTATUS_DDATA0MSBS_MASK)
+        >> _CRYPTO_DSTATUS_DDATA0MSBS_SHIFT;
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Write 260 bits to the DDATA0 register.
+ *
+ * @details
+ *   This functions writes 260 bits to the DDATA0 register in the CRYPTO
+ *   module. The data value is typically input to a big integer operation
+ *   (see crypto instructions) when the result width is set to 260 bits by
+ *   calling @ref CRYPTO_ResultWidthSet(cryptoResult260Bits);
+ *
+ * @param[out] val        Location where of the value in memory.
+ ******************************************************************************/
+__STATIC_INLINE void CRYPTO_DData0Write260(const CRYPTO_Data260_TypeDef val)
+{
+  CRYPTO_DDataWrite(cryptoRegDDATA0, val);
+  CRYPTO->DDATA0BYTE32 = val[8] & _CRYPTO_DDATA0BYTE32_DDATA0BYTE32_MASK;
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Quick read the MSbit of the DDATA1 register.
+ *
+ * @details
+ *   This function reads the most significant bit (bit 255) of the DDATA1
+ *   register via the DDATA1MSB bit field in the DSTATUS register. This can
+ *   be used to quickly check the signedness of a big integer resident in the
+ *   CRYPTO module.
+ *
+ * @return
+ *   Returns 'true' if MSbit is 1, and 'false' if MSbit is 0.
+ ******************************************************************************/
+__STATIC_INLINE bool CRYPTO_DData1_MSBitRead(void)
+{
+  return (CRYPTO->DSTATUS & _CRYPTO_DSTATUS_DDATA1MSB_MASK)
+    >> _CRYPTO_DSTATUS_DDATA1MSB_SHIFT;
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Load a sequence of instructions to be executed on the current values in
+ *   the data registers.
+ *
+ * @details
+ *   This function loads a sequence of instructions to the crypto module. The
+ *   instructions will be executed when the CRYPTO_InstructionSequenceExecute
+ *   function is called. The first END marks the end of the sequence.
+ *
+ * @param[in]  instructionSequence  Instruction sequence to load.
+ ******************************************************************************/
+__STATIC_INLINE void CRYPTO_InstructionSequenceLoad(const CRYPTO_InstructionSequence_TypeDef instructionSequence)
+{
+  const uint32_t * pas = (const uint32_t *) instructionSequence;
+
+  CRYPTO->SEQ0 = pas[0];
+  CRYPTO->SEQ1 = pas[1];
+  CRYPTO->SEQ2 = pas[2];
+  CRYPTO->SEQ3 = pas[3];
+  CRYPTO->SEQ4 = pas[4];
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Execute the current programmed instruction sequence.
+ *
+ * @details
+ *   This function starts the execution of the current instruction sequence
+ *   in the CRYPTO module.
+ ******************************************************************************/
+__STATIC_INLINE void CRYPTO_InstructionSequenceExecute(void)
+{
+  /* Start the command sequence. */
+  CRYPTO->CMD = CRYPTO_CMD_SEQSTART;
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Check whether the execution of an instruction sequence has completed.
+ *
+ * @details
+ *   This function checks whether an instruction sequence has completed.
+ *
+ * @return
+ *   Returns 'true' if the instruction sequence is done, and 'false' if not.
+ ******************************************************************************/
+__STATIC_INLINE bool CRYPTO_InstructionSequenceDone(void)
+{
+  /* Return true if operation has completed. */
+  return !(CRYPTO->STATUS
+           & (CRYPTO_STATUS_INSTRRUNNING | CRYPTO_STATUS_SEQRUNNING));
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Wait for completion of the current sequence of instructions.
+ *
+ * @details
+ *   This function "busy"-waits until the execution of the ongoing instruction
+ *   sequence has completed.
+ ******************************************************************************/
+__STATIC_INLINE void CRYPTO_InstructionSequenceWait(void)
+{
+  while (!CRYPTO_InstructionSequenceDone())
+    ;
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Wait for completion of the current command.
+ *
+ * @details
+ *   This function "busy"-waits until the execution of the ongoing instruction
+ *   has completed.
+ ******************************************************************************/
+__STATIC_INLINE void CRYPTO_InstructionWait(void)
+{
+  /* Wait for completion */
+  while (!(CRYPTO->IF & CRYPTO_IF_INSTRDONE))
+    ;
+  CRYPTO->IFC = CRYPTO_IF_INSTRDONE;
+}
+
+void CRYPTO_SHA_1(const uint8_t *              msg,
+                  uint64_t                     msgLen,
+                  CRYPTO_SHA1_Digest_TypeDef   digest);
+
+void CRYPTO_SHA_256(const uint8_t *              msg,
+                    uint64_t                     msgLen,
+                    CRYPTO_SHA256_Digest_TypeDef digest);
+
+void CRYPTO_Mul(uint32_t * A, int aSize,
+                uint32_t * B, int bSize,
+                uint32_t * R, int rSize);
+
+void CRYPTO_AES_CBC128(uint8_t * out,
+                       const uint8_t * in,
+                       unsigned int len,
+                       const uint8_t * key,
+                       const uint8_t * iv,
+                       bool encrypt);
+
+void CRYPTO_AES_CBC256(uint8_t * out,
+                       const uint8_t * in,
+                       unsigned int len,
+                       const uint8_t * key,
+                       const uint8_t * iv,
+                       bool encrypt);
+
+void CRYPTO_AES_CFB128(uint8_t * out,
+                       const uint8_t * in,
+                       unsigned int len,
+                       const uint8_t * key,
+                       const uint8_t * iv,
+                       bool encrypt);
+
+void CRYPTO_AES_CFB256(uint8_t * out,
+                       const uint8_t * in,
+                       unsigned int len,
+                       const uint8_t * key,
+                       const uint8_t * iv,
+                       bool encrypt);
+
+void CRYPTO_AES_CTR128(uint8_t * out,
+                       const uint8_t * in,
+                       unsigned int len,
+                       const uint8_t * key,
+                       uint8_t * ctr,
+                       CRYPTO_AES_CtrFuncPtr_TypeDef ctrFunc);
+
+void CRYPTO_AES_CTR256(uint8_t * out,
+                       const uint8_t * in,
+                       unsigned int len,
+                       const uint8_t * key,
+                       uint8_t * ctr,
+                       CRYPTO_AES_CtrFuncPtr_TypeDef ctrFunc);
+
+void CRYPTO_AES_CTRUpdate32Bit(uint8_t * ctr);
+void CRYPTO_AES_DecryptKey128(uint8_t * out, const uint8_t * in);
+void CRYPTO_AES_DecryptKey256(uint8_t * out, const uint8_t * in);
+
+void CRYPTO_AES_ECB128(uint8_t * out,
+                       const uint8_t * in,
+                       unsigned int len,
+                       const uint8_t * key,
+                       bool encrypt);
+
+void CRYPTO_AES_ECB256(uint8_t * out,
+                       const uint8_t * in,
+                       unsigned int len,
+                       const uint8_t * key,
+                       bool encrypt);
+
+void CRYPTO_AES_OFB128(uint8_t * out,
+                       const uint8_t * in,
+                       unsigned int len,
+                       const uint8_t * key,
+                       const uint8_t * iv);
+
+void CRYPTO_AES_OFB256(uint8_t * out,
+                       const uint8_t * in,
+                       unsigned int len,
+                       const uint8_t * key,
+                       const uint8_t * iv);
+
+/***************************************************************************//**
+ * @brief
+ *   Clear one or more pending CRYPTO interrupts.
+ *
+ * @param[in] flags
+ *   Pending CRYPTO interrupt source to clear. Use a bitwise logic OR combination of
+ *   valid interrupt flags for the CRYPTO module (CRYPTO_IF_nnn).
+ ******************************************************************************/
+__STATIC_INLINE void CRYPTO_IntClear(uint32_t flags)
+{
+  CRYPTO->IFC = flags;
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Disable one or more CRYPTO interrupts.
+ *
+ * @param[in] flags
+ *   CRYPTO interrupt sources to disable. Use a bitwise logic OR combination of
+ *   valid interrupt flags for the CRYPTO module (CRYPTO_IF_nnn).
+ ******************************************************************************/
+__STATIC_INLINE void CRYPTO_IntDisable(uint32_t flags)
+{
+  CRYPTO->IEN &= ~(flags);
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Enable one or more CRYPTO interrupts.
+ *
+ * @note
+ *   Depending on the use, a pending interrupt may already be set prior to
+ *   enabling the interrupt. Consider using CRYPTO_IntClear() prior to enabling
+ *   if such a pending interrupt should be ignored.
+ *
+ * @param[in] flags
+ *   CRYPTO interrupt sources to enable. Use a bitwise logic OR combination of
+ *   valid interrupt flags for the CRYPTO module (CRYPTO_IF_nnn).
+ ******************************************************************************/
+__STATIC_INLINE void CRYPTO_IntEnable(uint32_t flags)
+{
+  CRYPTO->IEN |= flags;
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Get pending CRYPTO interrupt flags.
+ *
+ * @note
+ *   The event bits are not cleared by the use of this function.
+ *
+ * @return
+ *   CRYPTO interrupt sources pending. A bitwise logic OR combination of valid
+ *   interrupt flags for the CRYPTO module (CRYPTO_IF_nnn).
+ ******************************************************************************/
+__STATIC_INLINE uint32_t CRYPTO_IntGet(void)
+{
+  return CRYPTO->IF;
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Get enabled and pending CRYPTO interrupt flags.
+ *   Useful for handling more interrupt sources in the same interrupt handler.
+ *
+ * @note
+ *   Interrupt flags are not cleared by the use of this function.
+ *
+ * @return
+ *   Pending and enabled CRYPTO interrupt sources
+ *   The return value is the bitwise AND of
+ *   - the enabled interrupt sources in CRYPTO_IEN and
+ *   - the pending interrupt flags CRYPTO_IF
+ ******************************************************************************/
+__STATIC_INLINE uint32_t CRYPTO_IntGetEnabled(void)
+{
+  return CRYPTO->IF & CRYPTO->IEN;
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Set one or more pending CRYPTO interrupts from SW.
+ *
+ * @param[in] flags
+ *   CRYPTO interrupt sources to set to pending. Use a bitwise logic OR combination
+ *   of valid interrupt flags for the CRYPTO module (CRYPTO_IF_nnn).
+ ******************************************************************************/
+__STATIC_INLINE void CRYPTO_IntSet(uint32_t flags)
+{
+  CRYPTO->IFS = flags;
+}
+
+/*******************************************************************************
+ *****    Static inline wrappers for CRYPTO AES functions in order to      *****
+ *****    preserve backwards compatibility with AES module API functions.  *****
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * @brief
+ *   AES Cipher-block chaining (CBC) cipher mode encryption/decryption,
+ *   128 bit key.
+ *
+ * @deprecated
+ *   This function is present to preserve backwards compatibility. Use
+ *   @ref CRYPTO_AES_CBC128 instead.
+ ******************************************************************************/
+__STATIC_INLINE void AES_CBC128(uint8_t * out,
+                       const uint8_t * in,
+                       unsigned int len,
+                       const uint8_t * key,
+                       const uint8_t * iv,
+                       bool encrypt)
+{
+  CRYPTO_AES_CBC128(out, in, len, key, iv, encrypt);
+}
+
+/***************************************************************************//**
+ * @brief
+ *   AES Cipher-block chaining (CBC) cipher mode encryption/decryption, 256 bit
+ *   key.
+ *
+ * @deprecated
+ *   This function is present to preserve backwards compatibility. Use
+ *   @ref CRYPTO_AES_CBC256 instead.
+ ******************************************************************************/
+__STATIC_INLINE void AES_CBC256(uint8_t * out,
+                       const uint8_t * in,
+                       unsigned int len,
+                       const uint8_t * key,
+                       const uint8_t * iv,
+                       bool encrypt)
+{
+  CRYPTO_AES_CBC256(out, in, len, key, iv, encrypt);
+}
+
+/***************************************************************************//**
+ * @brief
+ *   AES Cipher feedback (CFB) cipher mode encryption/decryption, 128 bit key.
+ *
+ * @deprecated
+ *   This function is present to preserve backwards compatibility. Use
+ *   @ref CRYPTO_AES_CFB128 instead.
+ ******************************************************************************/
+__STATIC_INLINE void AES_CFB128(uint8_t * out,
+                       const uint8_t * in,
+                       unsigned int len,
+                       const uint8_t * key,
+                       const uint8_t * iv,
+                       bool encrypt)
+{
+  CRYPTO_AES_CFB128(out, in, len, key, iv, encrypt);
+}
+
+/***************************************************************************//**
+ * @brief
+ *   AES Cipher feedback (CFB) cipher mode encryption/decryption, 256 bit key.
+ *
+ * @deprecated
+ *   This function is present to preserve backwards compatibility. Use
+ *   @ref CRYPTO_AES_CFB256 instead.
+ ******************************************************************************/
+__STATIC_INLINE void AES_CFB256(uint8_t * out,
+                       const uint8_t * in,
+                       unsigned int len,
+                       const uint8_t * key,
+                       const uint8_t * iv,
+                       bool encrypt)
+{
+  CRYPTO_AES_CFB256(out, in, len, key, iv, encrypt);
+}
+
+/***************************************************************************//**
+ * @brief
+ *   AES Counter (CTR) cipher mode encryption/decryption, 128 bit key.
+ *
+ * @deprecated
+ *   This function is present to preserve backwards compatibility. Use
+ *   @ref CRYPTO_AES_CTR128 instead.
+ ******************************************************************************/
+__STATIC_INLINE void AES_CTR128(uint8_t * out,
+                       const uint8_t * in,
+                       unsigned int len,
+                       const uint8_t * key,
+                       uint8_t * ctr,
+                       CRYPTO_AES_CtrFuncPtr_TypeDef ctrFunc)
+{
+  CRYPTO_AES_CTR128(out, in, len, key, ctr, ctrFunc);
+}
+
+/***************************************************************************//**
+ * @brief
+ *   AES Counter (CTR) cipher mode encryption/decryption, 256 bit key.
+ *
+ * @deprecated
+ *   This function is present to preserve backwards compatibility. Use
+ *   @ref CRYPTO_AES_CTR256 instead.
+ ******************************************************************************/
+__STATIC_INLINE void AES_CTR256(uint8_t * out,
+                       const uint8_t * in,
+                       unsigned int len,
+                       const uint8_t * key,
+                       uint8_t * ctr,
+                       CRYPTO_AES_CtrFuncPtr_TypeDef ctrFunc)
+{
+  CRYPTO_AES_CTR256(out, in, len, key, ctr, ctrFunc);
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Update last 32 bits of 128 bit counter, by incrementing with 1.
+ *
+ * @deprecated
+ *   This function is present to preserve backwards compatibility. Use
+ *   @ref CRYPTO_AES_CTRUpdate32Bit instead.
+ ******************************************************************************/
+__STATIC_INLINE void AES_CTRUpdate32Bit(uint8_t * ctr)
+{
+  CRYPTO_AES_CTRUpdate32Bit(ctr);
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Generate 128 bit AES decryption key from 128 bit encryption key. The
+ *   decryption key is used for some cipher modes when decrypting.
+ *
+ * @deprecated
+ *   This function is present to preserve backwards compatibility. Use
+ *   @ref CRYPTO_AES_DecryptKey128 instead.
+ ******************************************************************************/
+__STATIC_INLINE void AES_DecryptKey128(uint8_t * out, const uint8_t * in)
+{
+  CRYPTO_AES_DecryptKey128(out, in);
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Generate 256 bit AES decryption key from 256 bit encryption key. The
+ *   decryption key is used for some cipher modes when decrypting.
+ *
+ * @deprecated
+ *   This function is present to preserve backwards compatibility. Use
+ *   @ref CRYPTO_AES_DecryptKey256 instead.
+ ******************************************************************************/
+__STATIC_INLINE void AES_DecryptKey256(uint8_t * out, const uint8_t * in)
+{
+  CRYPTO_AES_DecryptKey256(out, in);
+}
+
+/***************************************************************************//**
+ * @brief
+ *   AES Electronic Codebook (ECB) cipher mode encryption/decryption,
+ *   128 bit key.
+ *
+ * @deprecated
+ *   This function is present to preserve backwards compatibility. Use
+ *   @ref CRYPTO_AES_ECB128 instead.
+ ******************************************************************************/
+__STATIC_INLINE void AES_ECB128(uint8_t * out,
+                                const uint8_t * in,
+                                unsigned int len,
+                                const uint8_t * key,
+                                bool encrypt)
+{
+  CRYPTO_AES_ECB128(out, in, len, key, encrypt);
+}
+
+/***************************************************************************//**
+ * @brief
+ *   AES Electronic Codebook (ECB) cipher mode encryption/decryption,
+ *   256 bit key.
+ *
+ * @deprecated
+ *   This function is present to preserve backwards compatibility. Use
+ *   @ref CRYPTO_AES_ECB256 instead.
+ ******************************************************************************/
+__STATIC_INLINE void AES_ECB256(uint8_t * out,
+                                const uint8_t * in,
+                                unsigned int len,
+                                const uint8_t * key,
+                                bool encrypt)
+{
+  CRYPTO_AES_ECB256(out, in, len, key, encrypt);
+}
+
+/***************************************************************************//**
+ * @brief
+ *   AES Output feedback (OFB) cipher mode encryption/decryption, 128 bit key.
+ *
+ * @deprecated
+ *   This function is present to preserve backwards compatibility. Use
+ *   @ref CRYPTO_AES_OFB128 instead.
+ ******************************************************************************/
+__STATIC_INLINE void AES_OFB128(uint8_t * out,
+                                const uint8_t * in,
+                                unsigned int len,
+                                const uint8_t * key,
+                                const uint8_t * iv)
+{
+  CRYPTO_AES_OFB128(out, in, len, key, iv);
+}
+
+/***************************************************************************//**
+ * @brief
+ *   AES Output feedback (OFB) cipher mode encryption/decryption, 256 bit key.
+ *
+ * @deprecated
+ *   This function is present to preserve backwards compatibility. Use
+ *   @ref CRYPTO_AES_OFB256 instead.
+ ******************************************************************************/
+__STATIC_INLINE void AES_OFB256(uint8_t * out,
+                                const uint8_t * in,
+                                unsigned int len,
+                                const uint8_t * key,
+                                const uint8_t * iv)
+{
+  CRYPTO_AES_OFB256(out, in, len, key, iv);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} (end addtogroup CRYPTO) */
+/** @} (end addtogroup EM_Library) */
+
+#endif /* defined(CRYPTO_COUNT) && (CRYPTO_COUNT > 0) */
+
+#endif /* __SILICON_LABS_EM_CRYPTO_H__ */

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_dac.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_dac.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /***************************************************************************//**
  * @file em_dac.h
  * @brief Digital to Analog Converter (DAC) peripheral API
- * @version 3.20.12
+ * @version 4.2.1
  *******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
  *******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,15 +30,14 @@
  *
  ******************************************************************************/
 
-
-#ifndef __EM_DAC_H
-#define __EM_DAC_H
+#ifndef __SILICON_LABS_EM_DAC_H__
+#define __SILICON_LABS_EM_DAC_H__
 
 #include "em_device.h"
-#include "em_assert.h"
 
 #if defined(DAC_COUNT) && (DAC_COUNT > 0)
 
+#include "em_assert.h"
 #include <stdbool.h>
 
 #ifdef __cplusplus
@@ -180,18 +179,19 @@
 } DAC_Init_TypeDef;
 
 /** Default config for DAC init structure. */
-#define DAC_INIT_DEFAULT                                                 \
-  { dacRefresh8,              /* Refresh every 8 prescaled cycles. */    \
-    dacRef1V25,               /* 1.25V internal reference. */            \
-    dacOutputPin,             /* Output to pin only. */                  \
-    dacConvModeContinuous,    /* Continuous mode. */                     \
-    0,                        /* No prescaling. */                       \
-    false,                    /* Do not enable low pass filter. */       \
-    false,                    /* Do not reset prescaler on ch0 start. */ \
-    false,                    /* DAC output enable always on. */         \
-    false,                    /* Disable sine mode. */                   \
-    false                     /* Single ended mode. */                   \
-  }
+#define DAC_INIT_DEFAULT                                               \
+{                                                                      \
+  dacRefresh8,              /* Refresh every 8 prescaled cycles. */    \
+  dacRef1V25,               /* 1.25V internal reference. */            \
+  dacOutputPin,             /* Output to pin only. */                  \
+  dacConvModeContinuous,    /* Continuous mode. */                     \
+  0,                        /* No prescaling. */                       \
+  false,                    /* Do not enable low pass filter. */       \
+  false,                    /* Do not reset prescaler on ch0 start. */ \
+  false,                    /* DAC output enable always on. */         \
+  false,                    /* Disable sine mode. */                   \
+  false                     /* Single ended mode. */                   \
+}
 
 
 /** DAC channel init structure. */
@@ -220,12 +220,13 @@
 } DAC_InitChannel_TypeDef;
 
 /** Default config for DAC channel init structure. */
-#define DAC_INITCHANNEL_DEFAULT                                           \
-  { false,              /* Leave channel disabled when init done. */      \
-    false,              /* Disable PRS triggering. */                     \
-    false,              /* Channel not refreshed automatically. */        \
-    dacPRSSELCh0        /* Select PRS ch0 (if PRS triggering enabled). */ \
-  }
+#define DAC_INITCHANNEL_DEFAULT                                         \
+{                                                                       \
+  false,              /* Leave channel disabled when init done. */      \
+  false,              /* Disable PRS triggering. */                     \
+  false,              /* Channel not refreshed automatically. */        \
+  dacPRSSELCh0        /* Select PRS ch0 (if PRS triggering enabled). */ \
+}
 
 
 /*******************************************************************************
@@ -315,7 +316,7 @@
  ******************************************************************************/
 __STATIC_INLINE void DAC_IntDisable(DAC_TypeDef *dac, uint32_t flags)
 {
-  dac->IEN &= ~(flags);
+  dac->IEN &= ~flags;
 }
 
 
@@ -357,7 +358,39 @@
  ******************************************************************************/
 __STATIC_INLINE uint32_t DAC_IntGet(DAC_TypeDef *dac)
 {
-  return(dac->IF);
+  return dac->IF;
+}
+
+
+/***************************************************************************//**
+ * @brief
+ *   Get enabled and pending DAC interrupt flags.
+ *   Useful for handling more interrupt sources in the same interrupt handler.
+ *
+ * @param[in] dac
+ *   Pointer to DAC peripheral register block.
+ *
+ * @note
+ *   Interrupt flags are not cleared by the use of this function.
+ *
+ * @return
+ *   Pending and enabled DAC interrupt sources.
+ *   The return value is the bitwise AND combination of
+ *   - the OR combination of enabled interrupt sources in DACx_IEN_nnn
+ *     register (DACx_IEN_nnn) and
+ *   - the OR combination of valid interrupt flags of the DAC module
+ *     (DACx_IF_nnn).
+ ******************************************************************************/
+__STATIC_INLINE uint32_t DAC_IntGetEnabled(DAC_TypeDef *dac)
+{
+  uint32_t ien;
+
+  /* Store DAC->IEN in temporary variable in order to define explicit order
+   * of volatile accesses. */
+  ien = dac->IEN;
+
+  /* Bitwise AND of pending and enabled interrupts */
+  return dac->IF & ien;
 }
 
 
@@ -388,5 +421,4 @@
 #endif
 
 #endif /* defined(DAC_COUNT) && (DAC_COUNT > 0) */
-
-#endif /* __EM_DAC_H */
+#endif /* __SILICON_LABS_EM_DAC_H__ */

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_dbg.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_dbg.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /***************************************************************************//**
  * @file em_dbg.h
  * @brief Debug (DBG) API
- * @version 3.20.12
+ * @version 4.2.1
  *******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
  *******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -31,13 +31,13 @@
  ******************************************************************************/
 
 
-#ifndef __SILICON_LABS_EM_DBG_H_
-#define __SILICON_LABS_EM_DBG_H_
+#ifndef __SILICON_LABS_EM_DBG_H__
+#define __SILICON_LABS_EM_DBG_H__
 
 #include <stdbool.h>
 #include "em_device.h"
 
-#if defined ( CoreDebug_DHCSR_C_DEBUGEN_Msk )
+#if defined( CoreDebug_DHCSR_C_DEBUGEN_Msk )
 
 #ifdef __cplusplus
 extern "C" {
@@ -57,7 +57,7 @@
  *****************************   PROTOTYPES   **********************************
  ******************************************************************************/
 
-#if defined( GPIO_ROUTE_SWCLKPEN )
+#if defined( GPIO_ROUTE_SWCLKPEN ) || defined( GPIO_ROUTEPEN_SWCLKTCKPEN )
 /***************************************************************************//**
  * @brief
  *   Check if a debugger is connected (and debug session activated)
@@ -72,12 +72,12 @@
  ******************************************************************************/
 __STATIC_INLINE bool DBG_Connected(void)
 {
-  return ((CoreDebug->DHCSR & CoreDebug_DHCSR_C_DEBUGEN_Msk) ? true : false);
+  return (CoreDebug->DHCSR & CoreDebug_DHCSR_C_DEBUGEN_Msk) ? true : false;
 }
 #endif
 
 
-#if defined( GPIO_ROUTE_SWOPEN )
+#if defined( GPIO_ROUTE_SWOPEN ) || defined( GPIO_ROUTEPEN_SWVPEN )
 void DBG_SWOEnable(unsigned int location);
 #endif
 
@@ -88,6 +88,6 @@
 }
 #endif
 
-#endif /* defined ( CoreDebug_DHCSR_C_DEBUGEN_Msk ) */
+#endif /* defined( CoreDebug_DHCSR_C_DEBUGEN_Msk ) */
 
-#endif /* __SILICON_LABS_EM_DBG_H_ */
+#endif /* __SILICON_LABS_EM_DBG_H__ */

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_dma.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_dma.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /***************************************************************************//**
  * @file em_dma.h
  * @brief Direct memory access (DMA) API
- * @version 3.20.12
+ * @version 4.2.1
  *******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
  *******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,10 +30,8 @@
  *
  ******************************************************************************/
 
-
-
-#ifndef __SILICON_LABS_EM_DMA_H_
-#define __SILICON_LABS_EM_DMA_H_
+#ifndef __SILICON_LABS_EM_DMA_H__
+#define __SILICON_LABS_EM_DMA_H__
 
 #include "em_device.h"
 #if defined( DMA_PRESENT )
@@ -407,14 +405,14 @@
   /* Clean loop copy operation */
   switch(channel)
   {
-  case 0:
-    DMA->LOOP0 = _DMA_LOOP0_RESETVALUE;
-    break;
-  case 1:
-    DMA->LOOP1 = _DMA_LOOP1_RESETVALUE;
-    break;
-  default:
-    break;
+    case 0:
+      DMA->LOOP0 = _DMA_LOOP0_RESETVALUE;
+      break;
+    case 1:
+      DMA->LOOP1 = _DMA_LOOP1_RESETVALUE;
+      break;
+    default:
+      break;
   }
 }
 #endif
@@ -452,6 +450,106 @@
                          bool last);
 void DMA_Reset(void);
 
+/***************************************************************************//**
+ * @brief
+ *   Clear one or more pending DMA interrupts.
+ *
+ * @param[in] flags
+ *   Pending DMA interrupt sources to clear. Use one or more valid
+ *   interrupt flags for the DMA module (DMA_IFC_nnn).
+ ******************************************************************************/
+__STATIC_INLINE void DMA_IntClear(uint32_t flags)
+{
+  DMA->IFC = flags;
+}
+
+
+/***************************************************************************//**
+ * @brief
+ *   Disable one or more DMA interrupts.
+ *
+ * @param[in] flags
+ *   DMA interrupt sources to disable. Use one or more valid
+ *   interrupt flags for the DMA module (DMA_IEN_nnn).
+ ******************************************************************************/
+__STATIC_INLINE void DMA_IntDisable(uint32_t flags)
+{
+  DMA->IEN &= ~flags;
+}
+
+
+/***************************************************************************//**
+ * @brief
+ *   Enable one or more DMA interrupts.
+ *
+ * @note
+ *   Depending on the use, a pending interrupt may already be set prior to
+ *   enabling the interrupt. Consider using DMA_IntClear() prior to enabling
+ *   if such a pending interrupt should be ignored.
+ *
+ * @param[in] flags
+ *   DMA interrupt sources to enable. Use one or more valid
+ *   interrupt flags for the DMA module (DMA_IEN_nnn).
+ ******************************************************************************/
+__STATIC_INLINE void DMA_IntEnable(uint32_t flags)
+{
+  DMA->IEN |= flags;
+}
+
+
+/***************************************************************************//**
+ * @brief
+ *   Get pending DMA interrupt flags.
+ *
+ * @note
+ *   The event bits are not cleared by the use of this function.
+ *
+ * @return
+ *   DMA interrupt sources pending. Returns one or more valid
+ *   interrupt flags for the DMA module (DMA_IF_nnn).
+ ******************************************************************************/
+__STATIC_INLINE uint32_t DMA_IntGet(void)
+{
+  return DMA->IF;
+}
+
+
+/***************************************************************************//**
+ * @brief
+ *   Get enabled and pending DMA interrupt flags.
+ *   Useful for handling more interrupt sources in the same interrupt handler.
+ *
+ * @note
+ *   Interrupt flags are not cleared by the use of this function.
+ *
+ * @return
+ *   Pending and enabled DMA interrupt sources
+ *   The return value is the bitwise AND of
+ *   - the enabled interrupt sources in DMA_IEN and
+ *   - the pending interrupt flags DMA_IF
+ ******************************************************************************/
+__STATIC_INLINE uint32_t DMA_IntGetEnabled(void)
+{
+  uint32_t ien;
+
+  ien = DMA->IEN;
+  return DMA->IF & ien;
+}
+
+
+/***************************************************************************//**
+ * @brief
+ *   Set one or more pending DMA interrupts
+ *
+ * @param[in] flags
+ *   DMA interrupt sources to set to pending. Use one or more valid
+ *   interrupt flags for the DMA module (DMA_IFS_nnn).
+ ******************************************************************************/
+__STATIC_INLINE void DMA_IntSet(uint32_t flags)
+{
+  DMA->IFS = flags;
+}
+
 /** @} (end addtogroup DMA) */
 /** @} (end addtogroup EM_Library) */
 
@@ -460,4 +558,4 @@
 #endif
 
 #endif /* defined( DMA_PRESENT ) */
-#endif /* __SILICON_LABS_EM_DMA_H_ */
+#endif /* __SILICON_LABS_EM_DMA_H__ */

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_ebi.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_ebi.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /***************************************************************************//**
  * @file em_ebi.h
  * @brief External Bus Iterface (EBI) peripheral API
- * @version 3.20.12
+ * @version 4.2.1
  *******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
  *******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,17 +30,15 @@
  *
  ******************************************************************************/
 
-
-#ifndef __SILICON_LABS_EM_EBI_H_
-#define __SILICON_LABS_EM_EBI_H_
+#ifndef __SILICON_LABS_EM_EBI_H__
+#define __SILICON_LABS_EM_EBI_H__
 
 #include "em_device.h"
-
 #if defined(EBI_COUNT) && (EBI_COUNT > 0)
-#include "em_assert.h"
 
 #include <stdint.h>
 #include <stdbool.h>
+#include "em_assert.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -60,9 +58,9 @@
  * @verbatim
  *
  * ---------               ---------
- * |  EBI  |  /|       |\  | Ext.  |
- * |       | / --------- \ | Async |
- * |(EFM32)| \ --------- / | Device|
+ * |       |  /|       |\  | Ext.  |
+ * |  EBI  | / --------- \ | Async |
+ * |       | \ --------- / | Device|
  * |       |  \|       |/  |       |
  * ---------               ---------
  *         Parallel interface
@@ -389,61 +387,63 @@
 
 /** Default config for EBI init structures */
 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
-#define EBI_INIT_DEFAULT                                 \
-  {   ebiModeD8A8,      /* 8 bit address, 8 bit data */  \
-      ebiActiveLow,     /* ARDY polarity */              \
-      ebiActiveLow,     /* ALE polarity */               \
-      ebiActiveLow,     /* WE polarity */                \
-      ebiActiveLow,     /* RE polarity */                \
-      ebiActiveLow,     /* CS polarity */                \
-      ebiActiveLow,     /* BL polarity */                \
-      false,            /* enable BL */                  \
-      false,            /* enable NOIDLE */              \
-      false,            /* enable ARDY */                \
-      false,            /* don't disable ARDY timeout */ \
-      EBI_BANK0,        /* enable bank 0 */              \
-      EBI_CS0,          /* enable chip select 0 */       \
-      0,                /* addr setup cycles */          \
-      1,                /* addr hold cycles */           \
-      false,            /* do not enable half cycle ALE strobe */ \
-      0,                /* read setup cycles */          \
-      0,                /* read strobe cycles */         \
-      0,                /* read hold cycles */           \
-      false,            /* disable page mode */          \
-      false,            /* disable prefetch */           \
-      false,            /* do not enable half cycle REn strobe */ \
-      0,                /* write setup cycles */         \
-      0,                /* write strobe cycles */        \
-      1,                /* write hold cycles */          \
-      false,            /* do not disable the write buffer */ \
-      false,            /* do not enable halc cycle WEn strobe */ \
-      ebiALowA0,        /* ALB - Low bound, address lines */ \
-      ebiAHighA0,       /* APEN - High bound, address lines */   \
-      ebiLocation0,     /* Use Location 0 */             \
-      true,             /* enable EBI */                 \
-  }
+#define EBI_INIT_DEFAULT                                      \
+{                                                             \
+  ebiModeD8A8,      /* 8 bit address, 8 bit data */           \
+  ebiActiveLow,     /* ARDY polarity */                       \
+  ebiActiveLow,     /* ALE polarity */                        \
+  ebiActiveLow,     /* WE polarity */                         \
+  ebiActiveLow,     /* RE polarity */                         \
+  ebiActiveLow,     /* CS polarity */                         \
+  ebiActiveLow,     /* BL polarity */                         \
+  false,            /* enable BL */                           \
+  false,            /* enable NOIDLE */                       \
+  false,            /* enable ARDY */                         \
+  false,            /* don't disable ARDY timeout */          \
+  EBI_BANK0,        /* enable bank 0 */                       \
+  EBI_CS0,          /* enable chip select 0 */                \
+  0,                /* addr setup cycles */                   \
+  1,                /* addr hold cycles */                    \
+  false,            /* do not enable half cycle ALE strobe */ \
+  0,                /* read setup cycles */                   \
+  0,                /* read strobe cycles */                  \
+  0,                /* read hold cycles */                    \
+  false,            /* disable page mode */                   \
+  false,            /* disable prefetch */                    \
+  false,            /* do not enable half cycle REn strobe */ \
+  0,                /* write setup cycles */                  \
+  0,                /* write strobe cycles */                 \
+  1,                /* write hold cycles */                   \
+  false,            /* do not disable the write buffer */     \
+  false,            /* do not enable halc cycle WEn strobe */ \
+  ebiALowA0,        /* ALB - Low bound, address lines */      \
+  ebiAHighA0,       /* APEN - High bound, address lines */    \
+  ebiLocation0,     /* Use Location 0 */                      \
+  true,             /* enable EBI */                          \
+}
 #else
-#define EBI_INIT_DEFAULT                                 \
-  { ebiModeD8A8,        /* 8 bit address, 8 bit data */  \
-    ebiActiveLow,       /* ARDY polarity */              \
-    ebiActiveLow,       /* ALE polarity */               \
-    ebiActiveLow,       /* WE polarity */                \
-    ebiActiveLow,       /* RE polarity */                \
-    ebiActiveLow,       /* CS polarity */                \
-    false,              /* enable ARDY */                \
-    false,              /* don't disable ARDY timeout */ \
-    EBI_BANK0,          /* enable bank 0 */              \
-    EBI_CS0,            /* enable chip select 0 */       \
-    0,                  /* addr setup cycles */          \
-    1,                  /* addr hold cycles */           \
-    0,                  /* read setup cycles */          \
-    0,                  /* read strobe cycles */         \
-    0,                  /* read hold cycles */           \
-    0,                  /* write setup cycles */         \
-    0,                  /* write strobe cycles */        \
-    1,                  /* write hold cycles */          \
-    true,               /* enable EBI */                 \
-  }
+#define EBI_INIT_DEFAULT                               \
+{                                                      \
+  ebiModeD8A8,        /* 8 bit address, 8 bit data */  \
+  ebiActiveLow,       /* ARDY polarity */              \
+  ebiActiveLow,       /* ALE polarity */               \
+  ebiActiveLow,       /* WE polarity */                \
+  ebiActiveLow,       /* RE polarity */                \
+  ebiActiveLow,       /* CS polarity */                \
+  false,              /* enable ARDY */                \
+  false,              /* don't disable ARDY timeout */ \
+  EBI_BANK0,          /* enable bank 0 */              \
+  EBI_CS0,            /* enable chip select 0 */       \
+  0,                  /* addr setup cycles */          \
+  1,                  /* addr hold cycles */           \
+  0,                  /* read setup cycles */          \
+  0,                  /* read strobe cycles */         \
+  0,                  /* read hold cycles */           \
+  0,                  /* write setup cycles */         \
+  0,                  /* write strobe cycles */        \
+  1,                  /* write hold cycles */          \
+  true,               /* enable EBI */                 \
+}
 #endif
 
 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
@@ -506,34 +506,35 @@
 } EBI_TFTInit_TypeDef;
 
 /** Default configuration for EBI TFT init structure */
-#define EBI_TFTINIT_DEFAULT                                                           \
-  { ebiTFTBank0,                /* Select EBI Bank 0 */                               \
-    ebiTFTWidthHalfWord,        /* Select 2-byte increments */                        \
-    ebiTFTColorSrcMem,          /* Use memory as source for mask/blending */          \
-    ebiTFTInterleaveUnlimited,  /* Unlimited interleaved accesses */                  \
-    ebiTFTFrameBufTriggerVSync, /* VSYNC as frame buffer update trigger */            \
-    false,                      /* Drive DCLK from negative edge of internal clock */ \
-    ebiTFTMBDisabled,           /* No masking and alpha blending enabled */           \
-    ebiTFTDDModeExternal,       /* Drive from external memory */                      \
-    ebiActiveLow,               /* CS Active Low polarity */                          \
-    ebiActiveLow,               /* DCLK Active Low polarity */                        \
-    ebiActiveLow,               /* DATAEN Active Low polarity */                      \
-    ebiActiveLow,               /* HSYNC Active Low polarity */                       \
-    ebiActiveLow,               /* VSYNC Active Low polarity */                       \
-    320,                        /* Horizontal size in pixels */                       \
-    1,                          /* Horizontal Front Porch */                          \
-    29,                         /* Horizontal Back Porch */                           \
-    2,                          /* Horizontal Synchronization Pulse Width */          \
-    240,                        /* Vertical size in pixels */                         \
-    1,                          /* Vertical Front Porch */                            \
-    4,                          /* Vertical Back Porch */                             \
-    2,                          /* Vertical Synchronization Pulse Width */            \
-    0x0000,                     /* Address offset to EBI memory base */               \
-    5,                          /* DCLK Period */                                     \
-    2,                          /* DCLK Start */                                      \
-    1,                          /* DCLK Setup cycles */                               \
-    1,                          /* DCLK Hold cycles */                                \
-  }
+#define EBI_TFTINIT_DEFAULT                                                         \
+{                                                                                   \
+  ebiTFTBank0,                /* Select EBI Bank 0 */                               \
+  ebiTFTWidthHalfWord,        /* Select 2-byte increments */                        \
+  ebiTFTColorSrcMem,          /* Use memory as source for mask/blending */          \
+  ebiTFTInterleaveUnlimited,  /* Unlimited interleaved accesses */                  \
+  ebiTFTFrameBufTriggerVSync, /* VSYNC as frame buffer update trigger */            \
+  false,                      /* Drive DCLK from negative edge of internal clock */ \
+  ebiTFTMBDisabled,           /* No masking and alpha blending enabled */           \
+  ebiTFTDDModeExternal,       /* Drive from external memory */                      \
+  ebiActiveLow,               /* CS Active Low polarity */                          \
+  ebiActiveLow,               /* DCLK Active Low polarity */                        \
+  ebiActiveLow,               /* DATAEN Active Low polarity */                      \
+  ebiActiveLow,               /* HSYNC Active Low polarity */                       \
+  ebiActiveLow,               /* VSYNC Active Low polarity */                       \
+  320,                        /* Horizontal size in pixels */                       \
+  1,                          /* Horizontal Front Porch */                          \
+  29,                         /* Horizontal Back Porch */                           \
+  2,                          /* Horizontal Synchronization Pulse Width */          \
+  240,                        /* Vertical size in pixels */                         \
+  1,                          /* Vertical Front Porch */                            \
+  4,                          /* Vertical Back Porch */                             \
+  2,                          /* Vertical Synchronization Pulse Width */            \
+  0x0000,                     /* Address offset to EBI memory base */               \
+  5,                          /* DCLK Period */                                     \
+  2,                          /* DCLK Start */                                      \
+  1,                          /* DCLK Setup cycles */                               \
+  1,                          /* DCLK Hold cycles */                                \
+}
 
 #endif
 /*******************************************************************************
@@ -721,7 +722,7 @@
 
 /***************************************************************************//**
  * @brief
- *   Set one or more pending EBI interrupts from SW.
+ *   Set one or more pending EBI interrupts.
  *
  * @param[in] flags
  *   EBI interrupt sources to set to pending. Use a logical OR combination of
@@ -735,7 +736,7 @@
 
 /***************************************************************************//**
  * @brief
- *   Disable one or more EBI interrupts
+ *   Disable one or more EBI interrupts.
  *
  * @param[in] flags
  *   EBI interrupt sources to disable. Use logical OR combination of valid
@@ -749,7 +750,7 @@
 
 /***************************************************************************//**
  * @brief
- *   Enable one or more EBI interrupts
+ *   Enable one or more EBI interrupts.
  *
  * @param[in] flags
  *   EBI interrupt sources to enable. Use logical OR combination of valid
@@ -763,7 +764,7 @@
 
 /***************************************************************************//**
  * @brief
- *   Get pending EBI interrupt flags
+ *   Get pending EBI interrupt flags.
  *
  * @note
  *   The event bits are not cleared by the use of this function
@@ -774,7 +775,30 @@
  ******************************************************************************/
 __STATIC_INLINE uint32_t EBI_IntGet(void)
 {
-  return(EBI->IF);
+  return EBI->IF;
+}
+
+
+/***************************************************************************//**
+ * @brief
+ *   Get enabled and pending EBI interrupt flags.
+ *   Useful for handling more interrupt sources in the same interrupt handler.
+ *
+ * @note
+ *   Interrupt flags are not cleared by the use of this function.
+ *
+ * @return
+ *   Pending and enabled EBI interrupt sources
+ *   The return value is the bitwise AND of
+ *   - the enabled interrupt sources in EBI_IEN and
+ *   - the pending interrupt flags EBI_IF
+ ******************************************************************************/
+__STATIC_INLINE uint32_t EBI_IntGetEnabled(void)
+{
+  uint32_t ien;
+
+  ien = EBI->IEN;
+  return EBI->IF & ien;
 }
 
 
@@ -817,4 +841,4 @@
 
 #endif /* defined(EBI_COUNT) && (EBI_COUNT > 0) */
 
-#endif /* __SILICON_LABS_EM_EBI_H_ */
+#endif /* __SILICON_LABS_EM_EBI_H__ */

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_emu.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_emu.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /***************************************************************************//**
  * @file em_emu.h
  * @brief Energy management unit (EMU) peripheral API
- * @version 3.20.12
+ * @version 4.2.1
  *******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
  *******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,7 +30,6 @@
  *
  ******************************************************************************/
 
-
 #ifndef __SILICON_LABS_EM_EMU_H__
 #define __SILICON_LABS_EM_EMU_H__
 
@@ -38,7 +37,7 @@
 #if defined( EMU_PRESENT )
 
 #include <stdbool.h>
-#include "em_bitband.h"
+#include "em_bus.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -58,22 +57,6 @@
  ********************************   ENUMS   ************************************
  ******************************************************************************/
 
-typedef enum
-{
-  /** Enable EM2 and 3 voltage regulator reduced drive strength (reduced leakage current) */
-#if defined( _EMU_CTRL_EM23VREG_MASK )
-  emuEM23Vreg_REDUCED = EMU_CTRL_EM23VREG_REDUCED,
-#elif defined( _EMU_CTRL_EMVREG_MASK )
-  emuEM23Vreg_REDUCED = EMU_CTRL_EMVREG_REDUCED,
-#endif
-  /** Enable EM2 and 3 voltage regulator full drive strength (faster startup) */
-#if defined( _EMU_CTRL_EM23VREG_MASK )
-  emuEM23Vreg_FULL = EMU_CTRL_EM23VREG_FULL,
-#elif defined( _EMU_CTRL_EMVREG_MASK )
-  emuEM23Vreg_FULL = EMU_CTRL_EMVREG_FULL,
-#endif
-} EMU_EM23VregMode;
-
 #if defined( _EMU_EM4CONF_OSC_MASK )
 /** EM4 duty oscillator */
 typedef enum
@@ -143,8 +126,111 @@
   emuBODMode_Inactive,
 } EMU_BODMode_TypeDef;
 
+#if defined( _EMU_EM4CTRL_EM4STATE_MASK )
+/** EM4 modes */
+typedef enum
+{
+  /** EM4 Hibernate */
+  emuEM4Hibernate = EMU_EM4CTRL_EM4STATE_EM4H,
+  /** EM4 Shutoff */
+  emuEM4Shutoff = EMU_EM4CTRL_EM4STATE_EM4S,
+} EMU_EM4State_TypeDef;
+#endif
 
 
+#if defined( _EMU_EM4CTRL_EM4IORETMODE_MASK )
+typedef enum
+{
+  /** No Retention: Pads enter reset state when entering EM4 */
+  emuPinRetentionDisable = EMU_EM4CTRL_EM4IORETMODE_DISABLE,
+  /** Retention through EM4: Pads enter reset state when exiting EM4 */
+  emuPinRetentionEm4Exit = EMU_EM4CTRL_EM4IORETMODE_EM4EXIT,
+  /** Retention through EM4 and wakeup: call EMU_UnlatchPinRetention() to
+      release pins from retention after EM4 wakeup */
+  emuPinRetentionLatch   = EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH,
+} EMU_EM4PinRetention_TypeDef;
+#endif
+
+
+#if defined( _EMU_PWRCFG_MASK )
+/** Power configurations */
+typedef enum
+{
+  /** DCDC is connected to DVDD */
+  emuPowerConfig_DcdcToDvdd = EMU_PWRCFG_PWRCFG_DCDCTODVDD,
+} EMU_PowerConfig_TypeDef;
+#endif
+
+#if defined( _EMU_DCDCCTRL_MASK )
+/** DCDC operating modes */
+typedef enum
+{
+  /** DCDC regulator bypass */
+  emuDcdcMode_Bypass = EMU_DCDCCTRL_DCDCMODE_BYPASS,
+  /** DCDC low-noise mode */
+  emuDcdcMode_LowNoise = EMU_DCDCCTRL_DCDCMODE_LOWNOISE,
+} EMU_DcdcMode_TypeDef;
+#endif
+
+#if defined( _EMU_PWRCTRL_MASK )
+/** DCDC to DVDD mode analog peripheral power supply select */
+typedef enum
+{
+  /** Select AVDD as analog power supply. Typically lower noise, but less energy efficient. */
+  emuDcdcAnaPeripheralPower_AVDD = EMU_PWRCTRL_ANASW_AVDD,
+  /** Select DCDC (DVDD) as analog power supply. Typically more energy efficient, but more noise. */
+  emuDcdcAnaPeripheralPower_DCDC = EMU_PWRCTRL_ANASW_DVDD
+} EMU_DcdcAnaPeripheralPower_TypeDef;
+#endif
+
+#if defined( _EMU_DCDCMISCCTRL_MASK )
+/** DCDC Low-noise efficiency mode */
+typedef enum
+{
+#if defined( _EFM_DEVICE )
+  /** High efficiency mode */
+  emuDcdcLnHighEfficiency = 0,
+#endif
+  /** Fast transient response mode */
+  emuDcdcLnFastTransient = EMU_DCDCMISCCTRL_LNFORCECCM,
+} EMU_DcdcLnTransientMode_TypeDef;
+#endif
+
+#if defined( _EMU_DCDCCTRL_MASK )
+/** DCDC Low-noise RCO band select */
+typedef enum
+{
+  /** Set RCO to 3MHz */
+  EMU_DcdcLnRcoBand_3MHz = 0,
+  /** Set RCO to 4MHz */
+  EMU_DcdcLnRcoBand_4MHz = 1,
+  /** Set RCO to 5MHz */
+  EMU_DcdcLnRcoBand_5MHz = 2,
+  /** Set RCO to 6MHz */
+  EMU_DcdcLnRcoBand_6MHz = 3,
+  /** Set RCO to 7MHz */
+  EMU_DcdcLnRcoBand_7MHz = 4,
+  /** Set RCO to 8MHz */
+  EMU_DcdcLnRcoBand_8MHz = 5,
+  /** Set RCO to 9MHz */
+  EMU_DcdcLnRcoBand_9MHz = 6,
+  /** Set RCO to 10MHz */
+  EMU_DcdcLnRcoBand_10MHz = 7,
+} EMU_DcdcLnRcoBand_TypeDef;
+
+#endif
+
+#if defined( EMU_STATUS_VMONRDY )
+/** VMON channels */
+typedef enum
+{
+  emuVmonChannel_AVDD,
+  emuVmonChannel_ALTAVDD,
+  emuVmonChannel_DVDD,
+  emuVmonChannel_IOVDD0
+} EMU_VmonChannel_TypeDef;
+#endif /* EMU_STATUS_VMONRDY */
+
 /*******************************************************************************
  *******************************   STRUCTS   ***********************************
  ******************************************************************************/
@@ -152,44 +238,58 @@
 /** Energy Mode 2 and 3 initialization structure  */
 typedef struct
 {
-  bool em23Vreg;
+  bool em23VregFullEn;                  /**< Enable full VREG drive strength in EM2/3 */
 } EMU_EM23Init_TypeDef;
 
 /** Default initialization of EM2 and 3 configuration */
 #define EMU_EM23INIT_DEFAULT    \
-  { false }     /* Reduced voltage regulator drive strength in EM2 and EM3 */
+{ false }                               /* Reduced voltage regulator drive strength in EM2 and EM3 */
 
 
+#if defined( _EMU_EM4CONF_MASK ) || defined( _EMU_EM4CTRL_MASK )
 /** Energy Mode 4 initialization structure  */
 typedef struct
 {
+#if defined( _EMU_EM4CONF_MASK )
   /* Init parameters for platforms with EMU->EM4CONF register */
-#if defined( _EMU_EM4CONF_MASK )
-  bool                  lockConfig;     /** Lock configuration of regulator, BOD and oscillator */
-  bool                  buBodRstDis;    /** When set, no reset will be asserted due to Brownout when in EM4 */
-  EMU_EM4Osc_TypeDef    osc;            /** EM4 duty oscillator */
-  bool                  buRtcWakeup;    /** Wake up on EM4 BURTC interrupt */
-  bool                  vreg;           /** Enable EM4 voltage regulator */
-#else
-  bool                  reserved;       /** Placeholder for empty structs */
+  bool                  lockConfig;     /**< Lock configuration of regulator, BOD and oscillator */
+  bool                  buBodRstDis;    /**< When set, no reset will be asserted due to Brownout when in EM4 */
+  EMU_EM4Osc_TypeDef    osc;            /**< EM4 duty oscillator */
+  bool                  buRtcWakeup;    /**< Wake up on EM4 BURTC interrupt */
+  bool                  vreg;           /**< Enable EM4 voltage regulator */
+
+#elif defined( _EMU_EM4CTRL_MASK )
+  /* Init parameters for platforms with EMU->EM4CTRL register */
+  bool                        retainLfxo;       /**< Disable the LFXO upon EM4 entry */
+  bool                        retainLfrco;      /**< Disable the LFRCO upon EM4 entry */
+  bool                        retainUlfrco;     /**< Disable the ULFRCO upon EM4 entry */
+  EMU_EM4State_TypeDef        em4State;         /**< Hibernate or shutoff EM4 state */
+  EMU_EM4PinRetention_TypeDef pinRetentionMode; /**< EM4 pin retention mode */
 #endif
 } EMU_EM4Init_TypeDef;
+#endif
 
 /** Default initialization of EM4 configuration */
 #if defined( _EMU_EM4CONF_MASK )
-#define EMU_EM4INIT_DEFAULT    \
-  { false,             /* Dont't lock configuration after it's been set */ \
-    false,             /* No reset will be asserted due to Brownout when in EM4 */ \
-    emuEM4Osc_ULFRCO,  /* Use default ULFRCO oscillator  */ \
-    true,              /* Wake up on EM4 BURTC interrupt */ \
-    true,              /* Enable VREG */ \
-  }
-#else
- #define EMU_EM4INIT_DEFAULT    \
-  { false,             /* Placeholder default value */ \
-  }
+#define EMU_EM4INIT_DEFAULT                                                                \
+{                                                                                          \
+  false,                              /* Dont't lock configuration after it's been set */  \
+  false,                              /* No reset will be asserted due to Brownout when in EM4 */ \
+  emuEM4Osc_ULFRCO,                   /* Use default ULFRCO oscillator  */                 \
+  true,                               /* Wake up on EM4 BURTC interrupt */                 \
+  true,                               /* Enable VREG */                                    \
+}
 #endif
-
+#if defined( _EMU_EM4CTRL_MASK )
+#define EMU_EM4INIT_DEFAULT                                                                \
+{                                                                                          \
+  false,                             /* Retain LFXO configuration upon EM4 entry */        \
+  false,                             /* Retain LFRCO configuration upon EM4 entry */       \
+  false,                             /* Retain ULFRCO configuration upon EM4 entry */      \
+  emuEM4Shutoff,                     /* Use EM4 shutoff state */                           \
+  emuPinRetentionDisable,            /* Do not retain pins in EM4 */                       \
+}
+#endif
 
 #if defined( BU_PRESENT )
 /** Backup Power Domain Initialization structure */
@@ -221,23 +321,121 @@
   bool                  enable;
 } EMU_BUPDInit_TypeDef;
 
-/** Default */
-#define EMU_BUPDINIT_DEFAULT                                                \
-  { emuProbe_Disable, /* Do not enable voltage probe */                     \
-    false,            /* Disable BOD calibration mode */                    \
-    false,            /* Disable BU_STAT pin for backup mode indication */  \
-                                                                            \
-    emuRes_Res0,      /* RES0 series resistance between main and backup power */ \
-    false,            /* Don't enable strong switch */                           \
-    false,            /* Don't enable medium switch */                           \
-    false,            /* Don't enable weak switch */                             \
-                                                                                 \
-    emuPower_None,    /* No connection between main and backup power (inactive mode) */  \
-    emuPower_None,    /* No connection between main and backup power (active mode) */    \
-    true              /* Enable BUPD enter on BOD, enable BU_VIN pin, release BU reset  */  \
-  }
+/** Default Backup Power Domain configuration */
+#define EMU_BUPDINIT_DEFAULT                                              \
+{                                                                         \
+  emuProbe_Disable, /* Do not enable voltage probe */                     \
+  false,            /* Disable BOD calibration mode */                    \
+  false,            /* Disable BU_STAT pin for backup mode indication */  \
+                                                                          \
+  emuRes_Res0,      /* RES0 series resistance between main and backup power */ \
+  false,            /* Don't enable strong switch */                           \
+  false,            /* Don't enable medium switch */                           \
+  false,            /* Don't enable weak switch */                             \
+                                                                               \
+  emuPower_None,    /* No connection between main and backup power (inactive mode) */     \
+  emuPower_None,    /* No connection between main and backup power (active mode) */       \
+  true              /* Enable BUPD enter on BOD, enable BU_VIN pin, release BU reset  */  \
+}
 #endif
 
+#if defined( _EMU_DCDCCTRL_MASK )
+/** DCDC initialization structure */
+typedef struct
+{
+  EMU_PowerConfig_TypeDef powerConfig;                  /**< Device external power configuration */
+  EMU_DcdcMode_TypeDef dcdcMode;                        /**< DCDC regulator operating mode in EM0 */
+  uint16_t mVout;                                       /**< Target output voltage (mV) */
+  uint16_t em01LoadCurrent_mA;                          /**< Estimated average load current in EM0 (mA).
+                                                             This estimate is also used for EM1 optimization,
+                                                             so if EM1 current is expected to be higher than EM0,
+                                                             then this parameter should hold the higher EM1 current. */
+  uint16_t em234LoadCurrent_uA;                         /**< Estimated average load current in EM2 (uA).
+                                                             This estimate is also used for EM3 and 4 optimization,
+                                                             so if EM3 or 4 current is expected to be higher than EM2,
+                                                             then this parameter should hold the higher EM3 or 4 current. */
+  uint16_t maxCurrent_mA;                               /**< Maximum peak DCDC output current (mA).
+                                                             This can be set to the maximum for the power source,
+                                                             for example the maximum for a battery. */
+  EMU_DcdcAnaPeripheralPower_TypeDef anaPeripheralPower;/**< Select analog peripheral power in DCDC-to-DVDD mode */
+  EMU_DcdcLnTransientMode_TypeDef lnTransientMode;      /**< Low-noise transient mode */
+
+} EMU_DCDCInit_TypeDef;
+
+/** Default DCDC initialization */
+#if defined( _EFM_DEVICE )
+#define EMU_DCDCINIT_DEFAULT                                                                                    \
+{                                                                                                               \
+  emuPowerConfig_DcdcToDvdd,     /* DCDC to DVDD */                                                             \
+  emuDcdcMode_LowNoise,          /* Low-niose mode in EM0 (can be set to LowPower on EFM32PG revB0) */          \
+  1800,                          /* Nominal output voltage for DVDD mode, 1.8V  */                              \
+  5,                             /* Nominal EM0 load current of less than 5mA */                                \
+  10,                            /* Nominal EM2/3 load current less than 10uA  */                               \
+  160,                           /* Maximum peak current of 160mA */                                            \
+  emuDcdcAnaPeripheralPower_DCDC,/* Select DCDC as analog power supply (lower power) */                         \
+  emuDcdcLnHighEfficiency,       /* Use low-noise high-efficiency mode (ignored if emuDcdcMode_LowPower) */     \
+}
+#else /* EFR32 device */
+#define EMU_DCDCINIT_DEFAULT                                                                                    \
+{                                                                                                               \
+  emuPowerConfig_DcdcToDvdd,     /* DCDC to DVDD */                                                             \
+  emuDcdcMode_LowNoise,          /* Low-niose mode in EM0 */                                                    \
+  1800,                          /* Nominal output voltage for DVDD mode, 1.8V  */                              \
+  15,                             /* Nominal EM0 load current of less than 5mA */                               \
+  10,                            /* Nominal EM2/3 load current less than 10uA  */                               \
+  160,                           /* Maximum peak current of 160mA */                                            \
+  emuDcdcAnaPeripheralPower_AVDD,/* Select AVDD as analog power supply (less noise) */                          \
+  emuDcdcLnFastTransient,        /* Use low-noise fast-transient mode */                                        \
+}
+#endif
+
+#endif
+
+#if defined( EMU_STATUS_VMONRDY )
+/** VMON initialization structure */
+typedef struct
+{
+  EMU_VmonChannel_TypeDef channel;                 /**< VMON channel to configure */
+  int threshold;                                   /**< Trigger threshold (mV) */
+  bool riseWakeup;                                 /**< Wake up from EM4H on rising edge */
+  bool fallWakeup;                                 /**< Wake up from EM4H on falling edge */
+  bool enable;                                     /**< Enable VMON channel */
+  bool retDisable;                                 /**< Disable IO0 retention when voltage drops below threshold (IOVDD only) */
+} EMU_VmonInit_TypeDef;
+
+/** Default VMON initialization structure */
+#define EMU_VMONINIT_DEFAULT                                               \
+{                                                                          \
+  emuVmonChannel_AVDD,          /* AVDD VMON channel */                    \
+  3200,                         /* 3.2 V threshold */                      \
+  false,                        /* Don't wake from EM4H on rising edge */  \
+  false,                        /* Don't wake from EM4H on falling edge */ \
+  true,                         /* Enable VMON channel */                  \
+  false                         /* Don't disable IO0 retention */          \
+}
+
+/** VMON Hysteresis initialization structure */
+typedef struct
+{
+  EMU_VmonChannel_TypeDef channel;                     /**< VMON channel to configure */
+  int riseThreshold;                                   /**< Rising threshold (mV) */
+  int fallThreshold;                                   /**< Falling threshold (mV) */
+  bool riseWakeup;                                     /**< Wake up from EM4H on rising edge */
+  bool fallWakeup;                                     /**< Wake up from EM4H on falling edge */
+  bool enable;                                         /**< Enable VMON channel */
+} EMU_VmonHystInit_TypeDef;
+
+/** Default VMON Hysteresis initialization structure */
+#define EMU_VMONHYSTINIT_DEFAULT                                           \
+{                                                                          \
+  emuVmonChannel_AVDD,          /* AVDD VMON channel */                    \
+  3200,                         /* 3.2 V rise threshold */                 \
+  3200,                         /* 3.2 V fall threshold */                 \
+  false,                        /* Don't wake from EM4H on rising edge */  \
+  false,                        /* Don't wake from EM4H on falling edge */ \
+  true                          /* Enable VMON channel */                  \
+}
+#endif /* EMU_STATUS_VMONRDY */
 
 /*******************************************************************************
  *****************************   PROTOTYPES   **********************************
@@ -249,13 +447,13 @@
  ******************************************************************************/
 __STATIC_INLINE void EMU_EnterEM1(void)
 {
-  /* Just enter Cortex-M3 sleep mode */
+  /* Enter sleep mode */
   SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
   __WFI();
 }
 
 void EMU_EM23Init(EMU_EM23Init_TypeDef *em23Init);
-#if defined( _EMU_EM4CONF_MASK )
+#if defined( _EMU_EM4CONF_MASK ) || defined( _EMU_EM4CTRL_MASK )
 void EMU_EM4Init(EMU_EM4Init_TypeDef *em4Init);
 #endif
 void EMU_EnterEM2(bool restore);
@@ -268,7 +466,33 @@
 void EMU_BUThresholdSet(EMU_BODMode_TypeDef mode, uint32_t value);
 void EMU_BUThresRangeSet(EMU_BODMode_TypeDef mode, uint32_t value);
 #endif
+#if defined( _EMU_DCDCCTRL_MASK )
+bool EMU_DCDCInit(EMU_DCDCInit_TypeDef *dcdcInit);
+void EMU_DCDCModeSet(EMU_DcdcMode_TypeDef dcdcMode);
+bool EMU_DCDCOutputVoltageSet(uint32_t mV, bool setLpVoltage, bool setLnVoltage);
+void EMU_DCDCOptimizeSlice(uint32_t mALoadCurrent);
+void EMU_DCDCLnRcoBandSet(EMU_DcdcLnRcoBand_TypeDef band);
+bool EMU_DCDCPowerOff(void);
+#endif
+#if defined( EMU_STATUS_VMONRDY )
+void EMU_VmonInit(EMU_VmonInit_TypeDef *vmonInit);
+void EMU_VmonHystInit(EMU_VmonHystInit_TypeDef *vmonInit);
+void EMU_VmonEnable(EMU_VmonChannel_TypeDef channel, bool enable);
+bool EMU_VmonChannelStatusGet(EMU_VmonChannel_TypeDef channel);
 
+/***************************************************************************//**
+ * @brief
+ *   Get the status of the voltage monitor (VMON).
+ *
+ * @return
+ *   Status of the VMON. True if all the enabled channels are ready, false if
+ *   one or more of the enabled channels are not ready.
+ ******************************************************************************/
+__STATIC_INLINE bool EMU_VmonStatusGet(void)
+{
+  return BUS_RegBitRead(&EMU->STATUS, _EMU_STATUS_VMONRDY_SHIFT);
+}
+#endif /* EMU_STATUS_VMONRDY */
 
 #if defined( _EMU_IF_MASK )
 /***************************************************************************//**
@@ -295,7 +519,7 @@
  ******************************************************************************/
 __STATIC_INLINE void EMU_IntDisable(uint32_t flags)
 {
-  EMU->IEN &= ~(flags);
+  EMU->IEN &= ~flags;
 }
 
 
@@ -382,11 +606,10 @@
  ******************************************************************************/
 __STATIC_INLINE void EMU_EM4Lock(bool enable)
 {
-  BITBAND_Peripheral(&(EMU->EM4CONF), _EMU_EM4CONF_LOCKCONF_SHIFT, enable);
+  BUS_RegBitWrite(&(EMU->EM4CONF), _EMU_EM4CONF_LOCKCONF_SHIFT, enable);
 }
 #endif
 
-
 #if defined( _EMU_STATUS_BURDY_MASK )
 /***************************************************************************//**
  * @brief
@@ -394,11 +617,11 @@
  ******************************************************************************/
 __STATIC_INLINE void EMU_BUReady(void)
 {
-  while(!(EMU->STATUS & EMU_STATUS_BURDY));
+  while(!(EMU->STATUS & EMU_STATUS_BURDY))
+    ;
 }
 #endif
 
-
 #if defined( _EMU_ROUTE_BUVINPEN_MASK )
 /***************************************************************************//**
  * @brief
@@ -408,21 +631,21 @@
  ******************************************************************************/
 __STATIC_INLINE void EMU_BUPinEnable(bool enable)
 {
-  BITBAND_Peripheral(&(EMU->ROUTE), _EMU_ROUTE_BUVINPEN_SHIFT, enable);
+  BUS_RegBitWrite(&(EMU->ROUTE), _EMU_ROUTE_BUVINPEN_SHIFT, enable);
 }
 #endif
 
-
 /***************************************************************************//**
  * @brief
- *   Lock the EMU in order to protect all its registers against unintended
+ *   Lock the EMU in order to protect its registers against unintended
  *   modification.
  *
  * @note
  *   If locking the EMU registers, they must be unlocked prior to using any
- *   EMU API functions modifying EMU registers. An exception to this is the
- *   energy mode entering API (EMU_EnterEMn()), which can be used when the
- *   EMU registers are locked.
+ *   EMU API functions modifying EMU registers, excluding interrupt control
+ *   and regulator control if the architecture has a EMU_PWRCTRL register.
+ *   An exception to this is the energy mode entering API (EMU_EnterEMn()),
+ *   which can be used when the EMU registers are locked.
  ******************************************************************************/
 __STATIC_INLINE void EMU_Lock(void)
 {
@@ -439,25 +662,63 @@
   EMU->LOCK = EMU_LOCK_LOCKKEY_UNLOCK;
 }
 
+
+#if defined( _EMU_PWRLOCK_MASK )
+/***************************************************************************//**
+ * @brief
+ *   Lock the EMU regulator control registers in order to protect against
+ *   unintended modification.
+ ******************************************************************************/
+__STATIC_INLINE void EMU_PowerLock(void)
+{
+  EMU->PWRLOCK = EMU_PWRLOCK_LOCKKEY_LOCK;
+}
+
+
+/***************************************************************************//**
+ * @brief
+ *   Unlock the EMU power control registers so that writing to
+ *   locked registers again is possible.
+ ******************************************************************************/
+__STATIC_INLINE void EMU_PowerUnlock(void)
+{
+  EMU->PWRLOCK = EMU_PWRLOCK_LOCKKEY_UNLOCK;
+}
+#endif
+
+
 /***************************************************************************//**
  * @brief
  *   Block entering EM2 or higher number energy modes.
  ******************************************************************************/
 __STATIC_INLINE void EMU_EM2Block(void)
 {
-  BITBAND_Peripheral(&(EMU->CTRL), _EMU_CTRL_EM2BLOCK_SHIFT, 1U);
+  BUS_RegBitWrite(&(EMU->CTRL), _EMU_CTRL_EM2BLOCK_SHIFT, 1U);
 }
 
-
 /***************************************************************************//**
  * @brief
  *   Unblock entering EM2 or higher number energy modes.
  ******************************************************************************/
 __STATIC_INLINE void EMU_EM2UnBlock(void)
 {
-  BITBAND_Peripheral(&(EMU->CTRL), _EMU_CTRL_EM2BLOCK_SHIFT, 0U);
+  BUS_RegBitWrite(&(EMU->CTRL), _EMU_CTRL_EM2BLOCK_SHIFT, 0U);
 }
 
+#if defined( _EMU_EM4CTRL_EM4IORETMODE_MASK )
+/***************************************************************************//**
+ * @brief
+ *   When EM4 pin retention is set to emuPinRetentionLatch, then pins are retained
+ *   through EM4 entry and wakeup. The pin state is released by calling this function.
+ *   The feature allows peripherals or GPIO to be re-initialized after EM4 exit (reset),
+ *   and when the initialization is done, this function can release pins and return control
+ *   to the peripherals or GPIO.
+ ******************************************************************************/
+__STATIC_INLINE void EMU_UnlatchPinRetention(void)
+{
+  EMU->CMD = EMU_CMD_EM4UNLATCH;
+}
+#endif
 
 /** @} (end addtogroup EMU) */
 /** @} (end addtogroup EM_Library) */
@@ -467,4 +728,4 @@
 #endif
 
 #endif /* defined( EMU_PRESENT ) */
-#endif /* __EM_EMU_H */
+#endif /* __SILICON_LABS_EM_EMU_H__ */

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_gpio.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_gpio.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /***************************************************************************//**
  * @file em_gpio.h
  * @brief General Purpose IO (GPIO) peripheral API
- * @version 3.20.12
+ * @version 4.2.1
  *******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
  *******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -31,14 +31,14 @@
  ******************************************************************************/
 
 
-#ifndef __SILICON_LABS_EM_GPIO_H_
-#define __SILICON_LABS_EM_GPIO_H_
+#ifndef __SILICON_LABS_EM_GPIO_H__
+#define __SILICON_LABS_EM_GPIO_H__
 
 #include "em_device.h"
 #if defined(GPIO_COUNT) && (GPIO_COUNT > 0)
 
 #include <stdbool.h>
-#include "em_bitband.h"
+#include "em_bus.h"
 #include "em_assert.h"
 
 #ifdef __cplusplus
@@ -56,20 +56,208 @@
  ******************************************************************************/
 
 /*******************************************************************************
+ *******************************   DEFINES   ***********************************
+ ******************************************************************************/
+
+/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
+#if defined( _EFM32_TINY_FAMILY ) || defined( _EFM32_ZERO_FAMILY )
+
+#define _GPIO_PORT_A_PIN_COUNT 14
+#define _GPIO_PORT_B_PIN_COUNT 10
+#define _GPIO_PORT_C_PIN_COUNT 16
+#define _GPIO_PORT_D_PIN_COUNT 9
+#define _GPIO_PORT_E_PIN_COUNT 12
+#define _GPIO_PORT_F_PIN_COUNT 6
+
+#define _GPIO_PORT_A_PIN_MASK 0xF77F
+#define _GPIO_PORT_B_PIN_MASK 0x79F8
+#define _GPIO_PORT_C_PIN_MASK 0xFFFF
+#define _GPIO_PORT_D_PIN_MASK 0x01FF
+#define _GPIO_PORT_E_PIN_MASK 0xFFF0
+#define _GPIO_PORT_F_PIN_MASK 0x003F
+
+#elif defined( _EFM32_HAPPY_FAMILY )
+
+#define _GPIO_PORT_A_PIN_COUNT 6
+#define _GPIO_PORT_B_PIN_COUNT 5
+#define _GPIO_PORT_C_PIN_COUNT 12
+#define _GPIO_PORT_D_PIN_COUNT 4
+#define _GPIO_PORT_E_PIN_COUNT 4
+#define _GPIO_PORT_F_PIN_COUNT 6
+
+#define _GPIO_PORT_A_PIN_MASK 0x0707
+#define _GPIO_PORT_B_PIN_MASK 0x6980
+#define _GPIO_PORT_C_PIN_MASK 0xEF1F
+#define _GPIO_PORT_D_PIN_MASK 0x00F0
+#define _GPIO_PORT_E_PIN_MASK 0x3C00
+#define _GPIO_PORT_F_PIN_MASK 0x003F
+
+#elif defined( _EFM32_GIANT_FAMILY ) \
+      || defined( _EFM32_WONDER_FAMILY )
+
+#define _GPIO_PORT_A_PIN_COUNT 16
+#define _GPIO_PORT_B_PIN_COUNT 16
+#define _GPIO_PORT_C_PIN_COUNT 16
+#define _GPIO_PORT_D_PIN_COUNT 16
+#define _GPIO_PORT_E_PIN_COUNT 16
+#define _GPIO_PORT_F_PIN_COUNT 13
+
+#define _GPIO_PORT_A_PIN_MASK 0xFFFF
+#define _GPIO_PORT_B_PIN_MASK 0xFFFF
+#define _GPIO_PORT_C_PIN_MASK 0xFFFF
+#define _GPIO_PORT_D_PIN_MASK 0xFFFF
+#define _GPIO_PORT_E_PIN_MASK 0xFFFF
+#define _GPIO_PORT_F_PIN_MASK 0x1FFF
+
+#elif defined( _EFM32_GECKO_FAMILY )
+
+#define _GPIO_PORT_A_PIN_COUNT 16
+#define _GPIO_PORT_B_PIN_COUNT 16
+#define _GPIO_PORT_C_PIN_COUNT 16
+#define _GPIO_PORT_D_PIN_COUNT 16
+#define _GPIO_PORT_E_PIN_COUNT 16
+#define _GPIO_PORT_F_PIN_COUNT 10
+
+#define _GPIO_PORT_A_PIN_MASK 0xFFFF
+#define _GPIO_PORT_B_PIN_MASK 0xFFFF
+#define _GPIO_PORT_C_PIN_MASK 0xFFFF
+#define _GPIO_PORT_D_PIN_MASK 0xFFFF
+#define _GPIO_PORT_E_PIN_MASK 0xFFFF
+#define _GPIO_PORT_F_PIN_MASK 0x03FF
+
+#elif defined( _EFR32_MIGHTY_FAMILY )    \
+      || defined( _EFR32_BLUE_FAMILY )   \
+      || defined( _EFR32_FLEX_FAMILY )   \
+      || defined( _EFR32_ZAPPY_FAMILY )
+
+#define _GPIO_PORT_A_PIN_COUNT 6
+#define _GPIO_PORT_B_PIN_COUNT 5
+#define _GPIO_PORT_C_PIN_COUNT 6
+#define _GPIO_PORT_D_PIN_COUNT 3
+#define _GPIO_PORT_E_PIN_COUNT 0
+#define _GPIO_PORT_F_PIN_COUNT 8
+
+#define _GPIO_PORT_A_PIN_MASK 0x003F
+#define _GPIO_PORT_B_PIN_MASK 0xF800
+#define _GPIO_PORT_C_PIN_MASK 0x0FC0
+#define _GPIO_PORT_D_PIN_MASK 0xE000
+#define _GPIO_PORT_E_PIN_MASK 0x0000
+#define _GPIO_PORT_F_PIN_MASK 0x00FF
+
+#elif defined( _EFM32_PEARL_FAMILY )    \
+      || defined( _EFM32_JADE_FAMILY )
+
+#define _GPIO_PORT_A_PIN_COUNT 6
+#define _GPIO_PORT_B_PIN_COUNT 5
+#define _GPIO_PORT_C_PIN_COUNT 6
+#define _GPIO_PORT_D_PIN_COUNT 7
+#define _GPIO_PORT_E_PIN_COUNT 0
+#define _GPIO_PORT_F_PIN_COUNT 8
+
+#define _GPIO_PORT_A_PIN_MASK 0x003F
+#define _GPIO_PORT_B_PIN_MASK 0xF800
+#define _GPIO_PORT_C_PIN_MASK 0x0FC0
+#define _GPIO_PORT_D_PIN_MASK 0xFE00
+#define _GPIO_PORT_E_PIN_MASK 0x0000
+#define _GPIO_PORT_F_PIN_MASK 0x00FF
+
+#else
+#warning "Port and pin masks are not defined for this family."
+#endif
+
+#if defined( _GPIO_PORT_G_PIN_COUNT ) && defined( _GPIO_PORT_H_PIN_COUNT )
+#define _GPIO_PORT_SIZE(port) (                \
+        (port) == 0 ? _GPIO_PORT_A_PIN_COUNT : \
+        (port) == 1 ? _GPIO_PORT_B_PIN_COUNT : \
+        (port) == 2 ? _GPIO_PORT_C_PIN_COUNT : \
+        (port) == 3 ? _GPIO_PORT_D_PIN_COUNT : \
+        (port) == 4 ? _GPIO_PORT_E_PIN_COUNT : \
+        (port) == 5 ? _GPIO_PORT_F_PIN_COUNT : \
+        (port) == 6 ? _GPIO_PORT_G_PIN_COUNT : \
+        (port) == 7 ? _GPIO_PORT_H_PIN_COUNT : \
+        0)
+#else
+#define _GPIO_PORT_SIZE(port) (                \
+        (port) == 0 ? _GPIO_PORT_A_PIN_COUNT : \
+        (port) == 1 ? _GPIO_PORT_B_PIN_COUNT : \
+        (port) == 2 ? _GPIO_PORT_C_PIN_COUNT : \
+        (port) == 3 ? _GPIO_PORT_D_PIN_COUNT : \
+        (port) == 4 ? _GPIO_PORT_E_PIN_COUNT : \
+        (port) == 5 ? _GPIO_PORT_F_PIN_COUNT : \
+        0)
+#endif
+
+#if defined( _GPIO_PORT_G_PIN_MASK ) && defined( _GPIO_PORT_H_PIN_MASK )
+#define _GPIO_PORT_MASK(port) ( \
+        (port) == 0 ? _GPIO_PORT_A_PIN_MASK : \
+        (port) == 1 ? _GPIO_PORT_B_PIN_MASK : \
+        (port) == 2 ? _GPIO_PORT_C_PIN_MASK : \
+        (port) == 3 ? _GPIO_PORT_D_PIN_MASK : \
+        (port) == 4 ? _GPIO_PORT_E_PIN_MASK : \
+        (port) == 5 ? _GPIO_PORT_F_PIN_MASK : \
+        (port) == 6 ? _GPIO_PORT_G_PIN_MASK : \
+        (port) == 7 ? _GPIO_PORT_H_PIN_MASK : \
+        0)
+#else
+#define _GPIO_PORT_MASK(port) ( \
+        (port) == 0 ? _GPIO_PORT_A_PIN_MASK : \
+        (port) == 1 ? _GPIO_PORT_B_PIN_MASK : \
+        (port) == 2 ? _GPIO_PORT_C_PIN_MASK : \
+        (port) == 3 ? _GPIO_PORT_D_PIN_MASK : \
+        (port) == 4 ? _GPIO_PORT_E_PIN_MASK : \
+        (port) == 5 ? _GPIO_PORT_F_PIN_MASK : \
+        0)
+#endif
+
+/** Validation of port and pin */
+#define GPIO_PORT_VALID(port)          ( _GPIO_PORT_MASK(port) )
+#define GPIO_PORT_PIN_VALID(port, pin) ((( _GPIO_PORT_MASK(port)) >> (pin)) & 0x1 )
+
+/** Highest GPIO pin number */
+#define GPIO_PIN_MAX  15
+
+/** Highest GPIO port number */
+#if defined( _GPIO_PORT_G_PIN_COUNT ) && defined( _GPIO_PORT_H_PIN_COUNT )
+#define GPIO_PORT_MAX  7
+#else
+#define GPIO_PORT_MAX  5
+#endif
+/** @endcond */
+
+/*******************************************************************************
  ********************************   ENUMS   ************************************
  ******************************************************************************/
 
-/** GPIO ports identificator. */
+/** GPIO ports ids. */
 typedef enum
 {
-  gpioPortA = 0, /**< Port A */
-  gpioPortB = 1, /**< Port B */
-  gpioPortC = 2, /**< Port C */
-  gpioPortD = 3, /**< Port D */
-  gpioPortE = 4, /**< Port E */
-  gpioPortF = 5  /**< Port F */
+#if ( _GPIO_PORT_A_PIN_COUNT > 0 )
+  gpioPortA = 0,
+#endif
+#if ( _GPIO_PORT_B_PIN_COUNT > 0 )
+  gpioPortB = 1,
+#endif
+#if ( _GPIO_PORT_C_PIN_COUNT > 0 )
+  gpioPortC = 2,
+#endif
+#if ( _GPIO_PORT_D_PIN_COUNT > 0 )
+  gpioPortD = 3,
+#endif
+#if ( _GPIO_PORT_E_PIN_COUNT > 0 )
+  gpioPortE = 4,
+#endif
+#if ( _GPIO_PORT_F_PIN_COUNT > 0 )
+  gpioPortF = 5
+#endif
+#if defined( _GPIO_PORT_G_PIN_COUNT ) && ( _GPIO_PORT_G_PIN_COUNT > 0 )
+  gpioPortG = 6
+#endif
+#if defined( _GPIO_PORT_H_PIN_COUNT ) && ( _GPIO_PORT_H_PIN_COUNT > 0 )
+  gpioPortH = 7
+#endif
 } GPIO_Port_TypeDef;
 
+#if defined( _GPIO_P_CTRL_DRIVEMODE_MASK )
 /** GPIO drive mode. */
 typedef enum
 {
@@ -82,8 +270,30 @@
   /** 2 mA */
   gpioDriveModeLow      = GPIO_P_CTRL_DRIVEMODE_LOW
 } GPIO_DriveMode_TypeDef;
+#endif
 
-/** Pin mode. For more details on each mode, please refer to the EFM32
+#if defined( _GPIO_P_CTRL_DRIVESTRENGTH_MASK ) && defined( _GPIO_P_CTRL_DRIVESTRENGTHALT_MASK )
+/** GPIO drive strength. */
+typedef enum
+{
+  /** GPIO weak 1mA and alternate function weak 1mA */
+  gpioDriveStrengthWeakAlternateWeak     = GPIO_P_CTRL_DRIVESTRENGTH_WEAK | GPIO_P_CTRL_DRIVESTRENGTHALT_WEAK,
+
+  /** GPIO weak 1mA and alternate function strong 10mA */
+  gpioDriveStrengthWeakAlternateStrong   = GPIO_P_CTRL_DRIVESTRENGTH_WEAK | GPIO_P_CTRL_DRIVESTRENGTHALT_STRONG,
+
+    /** GPIO strong 10mA and alternate function weak 1mA */
+  gpioDriveStrengthStrongAlternateWeak   = GPIO_P_CTRL_DRIVESTRENGTH_STRONG | GPIO_P_CTRL_DRIVESTRENGTHALT_WEAK,
+
+  /** GPIO strong 10mA and alternate function strong 10mA */
+  gpioDriveStrengthStrongAlternateStrong = GPIO_P_CTRL_DRIVESTRENGTH_STRONG | GPIO_P_CTRL_DRIVESTRENGTHALT_STRONG,
+} GPIO_DriveStrength_TypeDef;
+/* For legacy support */
+#define gpioDriveStrengthStrong   gpioDriveStrengthStrongAlternateStrong
+#define gpioDriveStrengthWeak     gpioDriveStrengthWeakAlternateWeak
+#endif
+
+/** Pin mode. For more details on each mode, please refer to the
  * reference manual. */
 typedef enum
 {
@@ -97,46 +307,48 @@
   gpioModeInputPullFilter           = _GPIO_P_MODEL_MODE0_INPUTPULLFILTER,
   /** Push-pull output */
   gpioModePushPull                  = _GPIO_P_MODEL_MODE0_PUSHPULL,
+#if defined( _GPIO_P_MODEL_MODE0_PUSHPULLDRIVE )
   /** Push-pull output with drive-strength set by DRIVEMODE */
   gpioModePushPullDrive             = _GPIO_P_MODEL_MODE0_PUSHPULLDRIVE,
+#endif
+#if defined( _GPIO_P_MODEL_MODE0_PUSHPULLALT )
+  /** Push-pull using alternate control */
+  gpioModePushPullAlternate       = _GPIO_P_MODEL_MODE0_PUSHPULLALT,
+#endif
   /** Wired-or output */
-  gpioModeWiredOr                   = _GPIO_P_MODEL_MODE0_WIREDOR,
+  gpioModeWiredOr                       = _GPIO_P_MODEL_MODE0_WIREDOR,
   /** Wired-or output with pull-down */
-  gpioModeWiredOrPullDown           = _GPIO_P_MODEL_MODE0_WIREDORPULLDOWN,
+  gpioModeWiredOrPullDown               = _GPIO_P_MODEL_MODE0_WIREDORPULLDOWN,
   /** Open-drain output */
-  gpioModeWiredAnd                  = _GPIO_P_MODEL_MODE0_WIREDAND,
+  gpioModeWiredAnd                      = _GPIO_P_MODEL_MODE0_WIREDAND,
   /** Open-drain output with filter */
-  gpioModeWiredAndFilter            = _GPIO_P_MODEL_MODE0_WIREDANDFILTER,
+  gpioModeWiredAndFilter                = _GPIO_P_MODEL_MODE0_WIREDANDFILTER,
   /** Open-drain output with pullup */
-  gpioModeWiredAndPullUp            = _GPIO_P_MODEL_MODE0_WIREDANDPULLUP,
+  gpioModeWiredAndPullUp                = _GPIO_P_MODEL_MODE0_WIREDANDPULLUP,
   /** Open-drain output with filter and pullup */
-  gpioModeWiredAndPullUpFilter      = _GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER,
+  gpioModeWiredAndPullUpFilter          = _GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER,
+#if defined( _GPIO_P_MODEL_MODE0_WIREDANDDRIVE )
   /** Open-drain output with drive-strength set by DRIVEMODE */
-  gpioModeWiredAndDrive             = _GPIO_P_MODEL_MODE0_WIREDANDDRIVE,
+  gpioModeWiredAndDrive                 = _GPIO_P_MODEL_MODE0_WIREDANDDRIVE,
   /** Open-drain output with filter and drive-strength set by DRIVEMODE */
-  gpioModeWiredAndDriveFilter       = _GPIO_P_MODEL_MODE0_WIREDANDDRIVEFILTER,
+  gpioModeWiredAndDriveFilter           = _GPIO_P_MODEL_MODE0_WIREDANDDRIVEFILTER,
   /** Open-drain output with pullup and drive-strength set by DRIVEMODE */
-  gpioModeWiredAndDrivePullUp       = _GPIO_P_MODEL_MODE0_WIREDANDDRIVEPULLUP,
+  gpioModeWiredAndDrivePullUp           = _GPIO_P_MODEL_MODE0_WIREDANDDRIVEPULLUP,
   /** Open-drain output with filter, pullup and drive-strength set by DRIVEMODE */
-  gpioModeWiredAndDrivePullUpFilter = _GPIO_P_MODEL_MODE0_WIREDANDDRIVEPULLUPFILTER
+  gpioModeWiredAndDrivePullUpFilter     = _GPIO_P_MODEL_MODE0_WIREDANDDRIVEPULLUPFILTER
+#endif
+#if defined( _GPIO_P_MODEL_MODE0_WIREDANDALT )
+  /** Open-drain output using alternate control */
+  gpioModeWiredAndAlternate             = _GPIO_P_MODEL_MODE0_WIREDANDALT,
+  /** Open-drain output using alternate control with filter */
+  gpioModeWiredAndAlternateFilter       = _GPIO_P_MODEL_MODE0_WIREDANDALTFILTER,
+  /** Open-drain output using alternate control with pullup */
+  gpioModeWiredAndAlternatePullUp       = _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP,
+  /** Open-drain output uisng alternate control with filter and pullup */
+  gpioModeWiredAndAlternatePullUpFilter = _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER,
+#endif
 } GPIO_Mode_TypeDef;
 
-
-/*******************************************************************************
- *******************************   DEFINES   ***********************************
- ******************************************************************************/
-
-/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
-
-/** Validation of pin typically usable in assert statements. */
-#define GPIO_PIN_VALID(pin)           ((pin) < 16)
-
-/** Validation of port typically usable in assert statements. */
-#define GPIO_PORT_VALID(port)         ((port) <= gpioPortF)
-
-/** @endcond */
-
-
 /*******************************************************************************
  *****************************   PROTOTYPES   **********************************
  ******************************************************************************/
@@ -154,8 +366,8 @@
                      GPIO_Mode_TypeDef mode,
                      unsigned int out);
 
-# if defined( GPIO_CTRL_EM4RET )
-__STATIC_INLINE void GPIO_EM4SetPinRetention(bool enable);
+# if defined( _GPIO_EM4WUEN_MASK )
+void GPIO_EM4EnablePinWakeup(uint32_t pinmask, uint32_t polaritymask);
 #endif
 
 /***************************************************************************//**
@@ -172,13 +384,19 @@
  ******************************************************************************/
 __STATIC_INLINE void GPIO_DbgSWDClkEnable(bool enable)
 {
-  BITBAND_Peripheral(&(GPIO->ROUTE), _GPIO_ROUTE_SWCLKPEN_SHIFT, (unsigned int)enable);
+#if defined( _GPIO_ROUTE_SWCLKPEN_MASK )
+  BUS_RegBitWrite(&(GPIO->ROUTE), _GPIO_ROUTE_SWCLKPEN_SHIFT, enable);
+#elif defined( _GPIO_ROUTEPEN_SWCLKTCKPEN_MASK )
+  BUS_RegBitWrite(&(GPIO->ROUTEPEN), _GPIO_ROUTEPEN_SWCLKTCKPEN_SHIFT, enable);
+#else
+#warning "ROUTE enable for SWCLK pin is not defined."
+#endif
 }
 
 
 /***************************************************************************//**
  * @brief
- *   Enable/disable serial wire data pin.
+ *   Enable/disable serial wire data I/O pin.
  *
  * @note
  *   Disabling SWDClk will disable the debug interface, which may result in
@@ -190,11 +408,17 @@
  ******************************************************************************/
 __STATIC_INLINE void GPIO_DbgSWDIOEnable(bool enable)
 {
-  BITBAND_Peripheral(&(GPIO->ROUTE), _GPIO_ROUTE_SWDIOPEN_SHIFT, (unsigned int)enable);
+#if defined( _GPIO_ROUTE_SWDIOPEN_MASK )
+  BUS_RegBitWrite(&(GPIO->ROUTE), _GPIO_ROUTE_SWDIOPEN_SHIFT, enable);
+#elif defined( _GPIO_ROUTEPEN_SWDIOTMSPEN_MASK )
+  BUS_RegBitWrite(&(GPIO->ROUTEPEN), _GPIO_ROUTEPEN_SWDIOTMSPEN_SHIFT, enable);
+#else
+#warning "ROUTE enable for SWDIO pin is not defined."
+#endif
 }
 
 
-#if defined( GPIO_ROUTE_SWOPEN )
+#if defined( _GPIO_ROUTE_SWOPEN_MASK ) || defined( _GPIO_ROUTEPEN_SWVPEN_MASK )
 /***************************************************************************//**
  * @brief
  *   Enable/Disable serial wire output pin.
@@ -210,12 +434,23 @@
  ******************************************************************************/
 __STATIC_INLINE void GPIO_DbgSWOEnable(bool enable)
 {
-  BITBAND_Peripheral(&(GPIO->ROUTE), _GPIO_ROUTE_SWOPEN_SHIFT, (unsigned int)enable);
+#if defined( _GPIO_ROUTE_SWOPEN_MASK )
+  BUS_RegBitWrite(&(GPIO->ROUTE), _GPIO_ROUTE_SWOPEN_SHIFT, enable);
+#elif defined( _GPIO_ROUTEPEN_SWVPEN_MASK )
+  BUS_RegBitWrite(&(GPIO->ROUTEPEN), _GPIO_ROUTEPEN_SWVPEN_SHIFT, enable);
+#else
+#warning "ROUTE enable for SWO/SWV pin is not defined."
+#endif
 }
 #endif
 
+#if defined (_GPIO_P_CTRL_DRIVEMODE_MASK)
 void GPIO_DriveModeSet(GPIO_Port_TypeDef port, GPIO_DriveMode_TypeDef mode);
+#endif
 
+#if defined( _GPIO_P_CTRL_DRIVESTRENGTH_MASK )
+void GPIO_DriveStrengthSet(GPIO_Port_TypeDef port, GPIO_DriveStrength_TypeDef strength);
+#endif
 
 # if defined( _GPIO_EM4WUEN_MASK )
 /**************************************************************************//**
@@ -235,40 +470,7 @@
 #endif
 
 
-# if defined( _GPIO_EM4WUEN_MASK )
-/**************************************************************************//**
- * @brief
- *   Enable GPIO pin wake-up from EM4. When the function exits,
- *   EM4 mode can be safely entered.
- *
- * @note
- *   It is assumed that the GPIO pin modes are set correctly.
- *   Valid modes are @ref gpioModeInput and @ref gpioModeInputPull.
- *
- * @param[in] pinmask
- *   Bitmask containing the bitwise logic OR of which GPIO pin(s) to enable.
- *   Refer to Reference Manuals for pinmask to GPIO port/pin mapping.
- * @param[in] polaritymask
- *   Bitmask containing the bitwise logic OR of GPIO pin(s) wake-up polarity.
- *   Refer to Reference Manuals for pinmask to GPIO port/pin mapping.
- *****************************************************************************/
-__STATIC_INLINE void GPIO_EM4EnablePinWakeup(uint32_t pinmask,
-                                             uint32_t polaritymask)
-{
-  EFM_ASSERT((pinmask & ~_GPIO_EM4WUEN_MASK) == 0);
-  EFM_ASSERT((polaritymask & ~_GPIO_EM4WUPOL_MASK) == 0);
-
-  GPIO->EM4WUPOL &= ~pinmask;               /* Set wakeup polarity */
-  GPIO->EM4WUPOL |= pinmask & polaritymask;
-  GPIO->EM4WUEN  |= pinmask;                /* Enable wakeup */
-
-  GPIO_EM4SetPinRetention(true);            /* Enable pin retention */
-
-  GPIO->CMD = GPIO_CMD_EM4WUCLR;            /* Clear wake-up logic */
-}
-#endif
-
-#if defined( _GPIO_EM4WUCAUSE_MASK )
+#if defined( _GPIO_EM4WUCAUSE_MASK ) || defined( _RMU_RSTCAUSE_EM4RST_MASK )
 /**************************************************************************//**
  * @brief
  *   Check which GPIO pin(s) that caused a wake-up from EM4.
@@ -279,16 +481,25 @@
  *****************************************************************************/
 __STATIC_INLINE uint32_t GPIO_EM4GetPinWakeupCause(void)
 {
+#if defined( _GPIO_EM4WUCAUSE_MASK )
   return GPIO->EM4WUCAUSE & _GPIO_EM4WUCAUSE_MASK;
+#else
+  return RMU->RSTCAUSE & _RMU_RSTCAUSE_EM4RST_MASK;
+#endif
 }
 #endif
 
 
-# if defined( GPIO_CTRL_EM4RET )
+#if defined( GPIO_CTRL_EM4RET ) || defined( _EMU_EM4CTRL_EM4IORETMODE_MASK )
 /**************************************************************************//**
  * @brief
  *   Enable GPIO pin retention of output enable, output value, pull enable and
  *   pull direction in EM4.
+ * 
+ * @note
+ *   For platform 2 parts, EMU_EM4Init() and EMU_UnlatchPinRetention() offers 
+ *   more pin retention features. This function implements the EM4EXIT retention
+ *   mode on platform 2.
  *
  * @param[in] enable
  *   @li true - enable EM4 pin retention.
@@ -298,11 +509,21 @@
 {
   if (enable)
   {
+#if defined( GPIO_CTRL_EM4RET )
     GPIO->CTRL |= GPIO_CTRL_EM4RET;
+#else
+    EMU->EM4CTRL = (EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4IORETMODE_MASK)
+                   | EMU_EM4CTRL_EM4IORETMODE_EM4EXIT;
+#endif
   }
   else
   {
+#if defined( GPIO_CTRL_EM4RET )
     GPIO->CTRL &= ~GPIO_CTRL_EM4RET;
+#else
+    EMU->EM4CTRL = (EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4IORETMODE_MASK)
+                   | EMU_EM4CTRL_EM4IORETMODE_DISABLE;
+#endif
   }
 }
 #endif
@@ -321,8 +542,8 @@
  *   @li GPIO_INSENSE_PRS - peripheral reflex system input sensing.
  *
  * @param[in] mask
- *   Mask containing bitwise logic OR of bits similar as for @p val used to indicate
- *   which input sense options to disable/enable.
+ *   Mask containing bitwise logic OR of bits similar as for @p val used to
+ *   indicate which input sense options to disable/enable.
  ******************************************************************************/
 __STATIC_INLINE void GPIO_InputSenseSet(uint32_t val, uint32_t mask)
 {
@@ -383,7 +604,7 @@
  ******************************************************************************/
 __STATIC_INLINE uint32_t GPIO_IntGet(void)
 {
-  return(GPIO->IF);
+  return GPIO->IF;
 }
 
 
@@ -451,11 +672,11 @@
  * @return
  *   The pin value, 0 or 1.
  ******************************************************************************/
-__STATIC_INLINE unsigned int GPIO_PinInGet(GPIO_Port_TypeDef port, unsigned int pin)
+__STATIC_INLINE unsigned int GPIO_PinInGet(GPIO_Port_TypeDef port,
+                                           unsigned int pin)
 {
-  EFM_ASSERT(GPIO_PORT_VALID(port) && GPIO_PIN_VALID(pin));
-
-  return((unsigned int)((GPIO->P[port].DIN >> pin) & 0x1));
+  EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin));
+  return BUS_RegBitRead(&GPIO->P[port].DIN, pin);
 }
 
 
@@ -476,9 +697,12 @@
  ******************************************************************************/
 __STATIC_INLINE void GPIO_PinOutClear(GPIO_Port_TypeDef port, unsigned int pin)
 {
-  EFM_ASSERT(GPIO_PORT_VALID(port) && GPIO_PIN_VALID(pin));
-
+  EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin));
+#if defined( _GPIO_P_DOUTCLR_MASK )
   GPIO->P[port].DOUTCLR = 1 << pin;
+#else
+  BUS_RegBitWrite(&GPIO->P[port].DOUT, pin, 0);
+#endif
 }
 
 
@@ -495,11 +719,11 @@
  * @return
  *   The DOUT setting for the requested pin, 0 or 1.
  ******************************************************************************/
-__STATIC_INLINE unsigned int GPIO_PinOutGet(GPIO_Port_TypeDef port, unsigned int pin)
+__STATIC_INLINE unsigned int GPIO_PinOutGet(GPIO_Port_TypeDef port,
+                                            unsigned int pin)
 {
-  EFM_ASSERT(GPIO_PORT_VALID(port) && GPIO_PIN_VALID(pin));
-
-  return((unsigned int)((GPIO->P[port].DOUT >> pin) & 0x1));
+  EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin));
+  return BUS_RegBitRead(&GPIO->P[port].DOUT, pin);
 }
 
 
@@ -520,9 +744,12 @@
  ******************************************************************************/
 __STATIC_INLINE void GPIO_PinOutSet(GPIO_Port_TypeDef port, unsigned int pin)
 {
-  EFM_ASSERT(GPIO_PORT_VALID(port) && GPIO_PIN_VALID(pin));
-
+  EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin));
+#if defined( _GPIO_P_DOUTSET_MASK )
   GPIO->P[port].DOUTSET = 1 << pin;
+#else
+  BUS_RegBitWrite(&GPIO->P[port].DOUT, pin, 1);
+#endif
 }
 
 
@@ -543,7 +770,7 @@
  ******************************************************************************/
 __STATIC_INLINE void GPIO_PinOutToggle(GPIO_Port_TypeDef port, unsigned int pin)
 {
-  EFM_ASSERT(GPIO_PORT_VALID(port) && GPIO_PIN_VALID(pin));
+  EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin));
 
   GPIO->P[port].DOUTTGL = 1 << pin;
 }
@@ -560,7 +787,7 @@
 {
   EFM_ASSERT(GPIO_PORT_VALID(port));
 
-  return(GPIO->P[port].DIN & _GPIO_P_DIN_DIN_MASK);
+  return GPIO->P[port].DIN;
 }
 
 
@@ -582,8 +809,11 @@
 __STATIC_INLINE void GPIO_PortOutClear(GPIO_Port_TypeDef port, uint32_t pins)
 {
   EFM_ASSERT(GPIO_PORT_VALID(port));
-
-  GPIO->P[port].DOUTCLR = pins & _GPIO_P_DOUTCLR_DOUTCLR_MASK;
+#if defined( _GPIO_P_DOUTCLR_MASK )
+  GPIO->P[port].DOUTCLR = pins;
+#else
+  BUS_RegMaskedClear(&GPIO->P[port].DOUT, pins);
+#endif
 }
 
 
@@ -601,7 +831,7 @@
 {
   EFM_ASSERT(GPIO_PORT_VALID(port));
 
-  return(GPIO->P[port].DOUT & _GPIO_P_DOUT_DOUT_MASK);
+  return GPIO->P[port].DOUT;
 }
 
 
@@ -623,8 +853,11 @@
 __STATIC_INLINE void GPIO_PortOutSet(GPIO_Port_TypeDef port, uint32_t pins)
 {
   EFM_ASSERT(GPIO_PORT_VALID(port));
-
-  GPIO->P[port].DOUTSET = pins & _GPIO_P_DOUTSET_DOUTSET_MASK;
+#if defined( _GPIO_P_DOUTSET_MASK )
+  GPIO->P[port].DOUTSET = pins;
+#else
+  BUS_RegMaskedSet(&GPIO->P[port].DOUT, pins);
+#endif
 }
 
 
@@ -646,7 +879,9 @@
  * @param[in] mask
  *   Mask indicating which bits to modify.
  ******************************************************************************/
-__STATIC_INLINE void GPIO_PortOutSetVal(GPIO_Port_TypeDef port, uint32_t val, uint32_t mask)
+__STATIC_INLINE void GPIO_PortOutSetVal(GPIO_Port_TypeDef port,
+                                        uint32_t val,
+                                        uint32_t mask)
 {
   EFM_ASSERT(GPIO_PORT_VALID(port));
 
@@ -656,7 +891,7 @@
 
 /***************************************************************************//**
  * @brief
- *   Toggle a single pin in GPIO port data out register.
+ *   Toggle pins in GPIO port data out register.
  *
  * @note
  *   In order for the setting to take effect on the output pad, the pin must
@@ -673,7 +908,7 @@
 {
   EFM_ASSERT(GPIO_PORT_VALID(port));
 
-  GPIO->P[port].DOUTTGL = pins & _GPIO_P_DOUTTGL_DOUTTGL_MASK;
+  GPIO->P[port].DOUTTGL = pins;
 }
 
 
@@ -686,7 +921,6 @@
   GPIO->LOCK = GPIO_LOCK_LOCKKEY_UNLOCK;
 }
 
-
 /** @} (end addtogroup GPIO) */
 /** @} (end addtogroup EM_Library) */
 
@@ -695,4 +929,4 @@
 #endif
 
 #endif /* defined(GPIO_COUNT) && (GPIO_COUNT > 0) */
-#endif /* __SILICON_LABS_EM_GPIO_H_ */
+#endif /* __SILICON_LABS_EM_GPIO_H__ */

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_i2c.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_i2c.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /***************************************************************************//**
  * @file em_i2c.h
  * @brief Inter-intergrated circuit (I2C) peripheral API
- * @version 3.20.12
+ * @version 4.2.1
  *******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
  *******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,9 +30,8 @@
  *
  ******************************************************************************/
 
-
-#ifndef __SILICON_LABS_EM_I2C_H_
-#define __SILICON_LABS_EM_I2C_H_
+#ifndef __SILICON_LABS_EM_I2C_H__
+#define __SILICON_LABS_EM_I2C_H__
 
 #include "em_device.h"
 #if defined(I2C_COUNT) && (I2C_COUNT > 0)
@@ -66,8 +65,21 @@
  *   worst case value of Tlow or Thigh as base.
  *
  *   1/(Tlow + Thigh + 1us + 0.3us) = 1/(4.7 + 4.7 + 1.3)us = 93458Hz
+ * @note
+ *   Due to chip characteristics, the max value is somewhat reduced.
  */
-#define I2C_FREQ_STANDARD_MAX    93500
+#if defined(_EFM32_GECKO_FAMILY) || defined(_EFM32_TINY_FAMILY) \
+    || defined(_EFM32_ZERO_FAMILY) || defined(_EFM32_HAPPY_FAMILY)
+#define I2C_FREQ_STANDARD_MAX    93000
+#elif defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
+#define I2C_FREQ_STANDARD_MAX    92000
+#elif defined(_SILICON_LABS_32B_PLATFORM_2)
+// None of the chips on this platform has been characterized on this parameter.
+// Use same value as on Wonder until further notice.
+#define I2C_FREQ_STANDARD_MAX    92000
+#else
+#error "Unknown device family."
+#endif
 
 /**
  * @brief
@@ -79,7 +91,7 @@
  *
  *   1/(Tlow + Thigh + 0.3us + 0.3us) = 1/(1.3 + 0.65 + 0.6)us = 392157Hz
  */
-#define I2C_FREQ_FAST_MAX        392500
+#define I2C_FREQ_FAST_MAX        392157
 
 
 /**
@@ -87,12 +99,12 @@
  *   Fast mode+ max frequency assuming using 11:6 ratio for Nlow:Nhigh.
  * @details
  *   From I2C specification: Min Tlow = 0.5us, min Thigh = 0.26us,
- *   max Trise=0.012us, max Tfall=0.12us. Since ratio is 11:6, have to use
+ *   max Trise=0.12us, max Tfall=0.12us. Since ratio is 11:6, have to use
  *   worst case value of Tlow or (11/6)xThigh as base.
  *
  *   1/(Tlow + Thigh + 0.12us + 0.12us) = 1/(0.5 + 0.273 + 0.24)us = 987167Hz
  */
-#define I2C_FREQ_FASTPLUS_MAX    987500
+#define I2C_FREQ_FASTPLUS_MAX    987167
 
 
 /**
@@ -207,14 +219,15 @@
 } I2C_Init_TypeDef;
 
 /** Suggested default config for I2C init structure. */
-#define I2C_INIT_DEFAULT                                                    \
-  { true,                    /* Enable when init done */                    \
-    true,                    /* Set to master mode */                       \
-    0,                       /* Use currently configured reference clock */ \
-    I2C_FREQ_STANDARD_MAX,   /* Set to standard rate assuring being */      \
-                             /* within I2C spec */                          \
-    i2cClockHLRStandard      /* Set to use 4:4 low/high duty cycle */       \
-  }
+#define I2C_INIT_DEFAULT                                                  \
+{                                                                         \
+  true,                    /* Enable when init done */                    \
+  true,                    /* Set to master mode */                       \
+  0,                       /* Use currently configured reference clock */ \
+  I2C_FREQ_STANDARD_MAX,   /* Set to standard rate assuring being */      \
+                           /* within I2C spec */                          \
+  i2cClockHLRStandard      /* Set to use 4:4 low/high duty cycle */       \
+}
 
 
 /**
@@ -273,9 +286,9 @@
 
 uint32_t I2C_BusFreqGet(I2C_TypeDef *i2c);
 void I2C_BusFreqSet(I2C_TypeDef *i2c,
-                    uint32_t refFreq,
-                    uint32_t freq,
-                    I2C_ClockHLR_TypeDef type);
+                    uint32_t freqRef,
+                    uint32_t freqScl,
+                    I2C_ClockHLR_TypeDef i2cMode);
 void I2C_Enable(I2C_TypeDef *i2c, bool enable);
 void I2C_Init(I2C_TypeDef *i2c, const I2C_Init_TypeDef *init);
 
@@ -351,7 +364,33 @@
  ******************************************************************************/
 __STATIC_INLINE uint32_t I2C_IntGet(I2C_TypeDef *i2c)
 {
-  return(i2c->IF);
+  return i2c->IF;
+}
+
+
+/***************************************************************************//**
+ * @brief
+ *   Get enabled and pending I2C interrupt flags.
+ *   Useful for handling more interrupt sources in the same interrupt handler.
+ *
+ * @note
+ *   Interrupt flags are not cleared by the use of this function.
+ *
+ * @param[in] i2c
+ *   Pointer to I2C peripheral register block.
+ *
+ * @return
+ *   Pending and enabled I2C interrupt sources
+ *   The return value is the bitwise AND of
+ *   - the enabled interrupt sources in I2Cn_IEN and
+ *   - the pending interrupt flags I2Cn_IF
+ ******************************************************************************/
+__STATIC_INLINE uint32_t I2C_IntGetEnabled(I2C_TypeDef *i2c)
+{
+  uint32_t ien;
+
+  ien = i2c->IEN;
+  return i2c->IF & ien;
 }
 
 
@@ -392,7 +431,7 @@
  ******************************************************************************/
 __STATIC_INLINE uint8_t I2C_SlaveAddressGet(I2C_TypeDef *i2c)
 {
-  return((uint8_t)(i2c->SADDR));
+  return ((uint8_t)(i2c->SADDR));
 }
 
 
@@ -444,7 +483,7 @@
  ******************************************************************************/
 __STATIC_INLINE uint8_t I2C_SlaveAddressMaskGet(I2C_TypeDef *i2c)
 {
-  return((uint8_t)(i2c->SADDRMASK));
+  return ((uint8_t)(i2c->SADDRMASK));
 }
 
 
@@ -489,4 +528,4 @@
 #endif
 
 #endif /* defined(I2C_COUNT) && (I2C_COUNT > 0) */
-#endif /* __SILICON_LABS_EM_I2C_H_ */
+#endif /* __SILICON_LABS_EM_I2C_H__ */

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_idac.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_idac.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /***************************************************************************//**
  * @file em_idac.h
  * @brief Current Digital to Analog Converter (IDAC) peripheral API
- * @version 3.20.12
+ * @version 4.2.1
  *******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
  *******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,9 +30,8 @@
  *
  ******************************************************************************/
 
-
-#ifndef __SILICON_LABS_EM_IDAC_H_
-#define __SILICON_LABS_EM_IDAC_H_
+#ifndef __SILICON_LABS_EM_IDAC_H__
+#define __SILICON_LABS_EM_IDAC_H__
 
 #include "em_device.h"
 
@@ -67,8 +66,43 @@
 /** Output mode. */
 typedef enum
 {
+#if defined( _IDAC_CTRL_OUTMODE_MASK )
   idacOutputPin     = IDAC_CTRL_OUTMODE_PIN,     /**< Output to IDAC OUT pin */
   idacOutputADC     = IDAC_CTRL_OUTMODE_ADC      /**< Output to ADC */
+#elif ( _IDAC_CTRL_APORTOUTSEL_MASK )
+  idacOutputAPORT1XCH0 = IDAC_CTRL_APORTOUTSEL_APORT1XCH0, /**< Output to APORT 1X CH0 */
+  idacOutputAPORT1YCH1 = IDAC_CTRL_APORTOUTSEL_APORT1YCH1, /**< Output to APORT 1Y CH1 */
+  idacOutputAPORT1XCH2 = IDAC_CTRL_APORTOUTSEL_APORT1XCH2, /**< Output to APORT 1X CH2 */
+  idacOutputAPORT1YCH3 = IDAC_CTRL_APORTOUTSEL_APORT1YCH3, /**< Output to APORT 1Y CH3 */
+  idacOutputAPORT1XCH4 = IDAC_CTRL_APORTOUTSEL_APORT1XCH4, /**< Output to APORT 1X CH4 */
+  idacOutputAPORT1YCH5 = IDAC_CTRL_APORTOUTSEL_APORT1YCH5, /**< Output to APORT 1Y CH5 */
+  idacOutputAPORT1XCH6 = IDAC_CTRL_APORTOUTSEL_APORT1XCH6, /**< Output to APORT 1X CH6 */
+  idacOutputAPORT1YCH7 = IDAC_CTRL_APORTOUTSEL_APORT1YCH7, /**< Output to APORT 1Y CH7 */
+  idacOutputAPORT1XCH8 = IDAC_CTRL_APORTOUTSEL_APORT1XCH8, /**< Output to APORT 1X CH8 */
+  idacOutputAPORT1YCH9 = IDAC_CTRL_APORTOUTSEL_APORT1YCH9, /**< Output to APORT 1Y CH9 */
+  idacOutputAPORT1XCH10 = IDAC_CTRL_APORTOUTSEL_APORT1XCH10, /**< Output to APORT 1X CH10 */
+  idacOutputAPORT1YCH11 = IDAC_CTRL_APORTOUTSEL_APORT1YCH11, /**< Output to APORT 1Y CH11 */
+  idacOutputAPORT1XCH12 = IDAC_CTRL_APORTOUTSEL_APORT1XCH12, /**< Output to APORT 1X CH12 */
+  idacOutputAPORT1YCH13 = IDAC_CTRL_APORTOUTSEL_APORT1YCH13, /**< Output to APORT 1Y CH13 */
+  idacOutputAPORT1XCH14 = IDAC_CTRL_APORTOUTSEL_APORT1XCH14, /**< Output to APORT 1X CH14 */
+  idacOutputAPORT1YCH15 = IDAC_CTRL_APORTOUTSEL_APORT1YCH15, /**< Output to APORT 1Y CH15 */
+  idacOutputAPORT1XCH16 = IDAC_CTRL_APORTOUTSEL_APORT1XCH16, /**< Output to APORT 1X CH16 */
+  idacOutputAPORT1YCH17 = IDAC_CTRL_APORTOUTSEL_APORT1YCH17, /**< Output to APORT 1Y CH17 */
+  idacOutputAPORT1XCH18 = IDAC_CTRL_APORTOUTSEL_APORT1XCH18, /**< Output to APORT 1X CH18 */
+  idacOutputAPORT1YCH19 = IDAC_CTRL_APORTOUTSEL_APORT1YCH19, /**< Output to APORT 1Y CH19 */
+  idacOutputAPORT1XCH20 = IDAC_CTRL_APORTOUTSEL_APORT1XCH20, /**< Output to APORT 1X CH20 */
+  idacOutputAPORT1YCH21 = IDAC_CTRL_APORTOUTSEL_APORT1YCH21, /**< Output to APORT 1Y CH21 */
+  idacOutputAPORT1XCH22 = IDAC_CTRL_APORTOUTSEL_APORT1XCH22, /**< Output to APORT 1X CH22 */
+  idacOutputAPORT1YCH23 = IDAC_CTRL_APORTOUTSEL_APORT1YCH23, /**< Output to APORT 1Y CH23 */
+  idacOutputAPORT1XCH24 = IDAC_CTRL_APORTOUTSEL_APORT1XCH24, /**< Output to APORT 1X CH24 */
+  idacOutputAPORT1YCH25 = IDAC_CTRL_APORTOUTSEL_APORT1YCH25, /**< Output to APORT 1Y CH25 */
+  idacOutputAPORT1XCH26 = IDAC_CTRL_APORTOUTSEL_APORT1XCH26, /**< Output to APORT 1X CH26 */
+  idacOutputAPORT1YCH27 = IDAC_CTRL_APORTOUTSEL_APORT1YCH27, /**< Output to APORT 1Y CH27 */
+  idacOutputAPORT1XCH28 = IDAC_CTRL_APORTOUTSEL_APORT1XCH28, /**< Output to APORT 1X CH28 */
+  idacOutputAPORT1YCH29 = IDAC_CTRL_APORTOUTSEL_APORT1YCH29, /**< Output to APORT 1Y CH29 */
+  idacOutputAPORT1XCH30 = IDAC_CTRL_APORTOUTSEL_APORT1XCH30, /**< Output to APORT 1X CH30 */
+  idacOutputAPORT1YCH31 = IDAC_CTRL_APORTOUTSEL_APORT1YCH31, /**< Output to APORT 1Y CH31 */
+#endif
 } IDAC_OutMode_TypeDef;
 
 
@@ -80,28 +114,16 @@
   idacPRSSELCh1 = IDAC_CTRL_PRSSEL_PRSCH1,      /**< PRS channel 1. */
   idacPRSSELCh2 = IDAC_CTRL_PRSSEL_PRSCH2,      /**< PRS channel 2. */
   idacPRSSELCh3 = IDAC_CTRL_PRSSEL_PRSCH3,      /**< PRS channel 3. */
-#if  defined( IDAC_CTRL_PRSSEL_PRSCH4 )
+#if defined( IDAC_CTRL_PRSSEL_PRSCH4 )
   idacPRSSELCh4 = IDAC_CTRL_PRSSEL_PRSCH4,      /**< PRS channel 4. */
-#endif
-#if  defined( IDAC_CTRL_PRSSEL_PRSCH5 )
   idacPRSSELCh5 = IDAC_CTRL_PRSSEL_PRSCH5,      /**< PRS channel 5. */
 #endif
-#if  defined( IDAC_CTRL_PRSSEL_PRSCH6 )
+#if defined( IDAC_CTRL_PRSSEL_PRSCH6 )
   idacPRSSELCh6 = IDAC_CTRL_PRSSEL_PRSCH6,      /**< PRS channel 6. */
-#endif
-#if  defined( IDAC_CTRL_PRSSEL_PRSCH7 )
   idacPRSSELCh7 = IDAC_CTRL_PRSSEL_PRSCH7,      /**< PRS channel 7. */
-#endif
-#if  defined( IDAC_CTRL_PRSSEL_PRSCH8 )
   idacPRSSELCh8 = IDAC_CTRL_PRSSEL_PRSCH8,      /**< PRS channel 8. */
-#endif
-#if  defined( IDAC_CTRL_PRSSEL_PRSCH9 )
   idacPRSSELCh9 = IDAC_CTRL_PRSSEL_PRSCH9,      /**< PRS channel 9. */
-#endif
-#if  defined( IDAC_CTRL_PRSSEL_PRSCH10 )
   idacPRSSELCh10 = IDAC_CTRL_PRSSEL_PRSCH10,    /**< PRS channel 10 */
-#endif
-#if  defined( IDAC_CTRL_PRSSEL_PRSCH11 )
   idacPRSSELCh11 = IDAC_CTRL_PRSSEL_PRSCH11,    /**< PRS channel 11 */
 #endif
 } IDAC_PRSSEL_TypeDef;
@@ -148,13 +170,25 @@
 } IDAC_Init_TypeDef;
 
 /** Default config for IDAC init structure. */
-#define IDAC_INIT_DEFAULT                                             \
-  { false,          /* Leave IDAC disabled when init done. */         \
-    idacOutputPin,   /* Output to IDAC OUT pin. */                     \
-    false,          /* Disable PRS triggering. */                     \
-    idacPRSSELCh0,  /* Select PRS ch0 (if PRS triggering enabled). */ \
-    false           /* Disable current sink mode. */                  \
-  }
+#if defined( _IDAC_CTRL_OUTMODE_MASK )
+#define IDAC_INIT_DEFAULT                                              \
+{                                                                      \
+  false,          /**< Leave IDAC disabled when init done. */          \
+  idacOutputPin,  /**< Output to IDAC output pin. */                   \
+  false,          /**< Disable PRS triggering. */                      \
+  idacPRSSELCh0,  /**< Select PRS ch0 (if PRS triggering enabled). */  \
+  false           /**< Disable current sink mode. */                   \
+}
+#elif ( _IDAC_CTRL_APORTOUTSEL_MASK )
+#define IDAC_INIT_DEFAULT                                              \
+{                                                                      \
+  false,          /**< Leave IDAC disabled when init done. */          \
+  idacOutputAPORT1XCH0, /**< Output to APORT. */                       \
+  false,          /**< Disable PRS triggering. */                      \
+  idacPRSSELCh0,  /**< Select PRS ch0 (if PRS triggering enabled). */  \
+  false           /**< Disable current sink mode. */                   \
+}
+#endif
 
 
 /*******************************************************************************
@@ -262,6 +296,133 @@
 void IDAC_OutEnable(IDAC_TypeDef *idac, bool enable);
 
 
+#if defined( _IDAC_IEN_MASK )
+/***************************************************************************//**
+ * @brief
+ *   Clear one or more pending IDAC interrupts.
+ *
+ * @param[in] IDAC
+ *   Pointer to IDAC peripheral register block.
+ *
+ * @param[in] flags
+ *   Pending IDAC interrupt source(s) to clear. Use one or more valid
+ *   interrupt flags for the IDAC module (IDAC_IF_nnn) OR'ed together.
+ ******************************************************************************/
+__STATIC_INLINE void IDAC_IntClear(IDAC_TypeDef *idac, uint32_t flags)
+{
+  idac->IFC = flags;
+}
+
+
+/***************************************************************************//**
+ * @brief
+ *   Disable one or more IDAC interrupts.
+ *
+ * @param[in] IDAC
+ *   Pointer to IDAC peripheral register block.
+ *
+ * @param[in] flags
+ *   IDAC interrupt source(s) to disable. Use one or more valid
+ *   interrupt flags for the IDAC module (IDAC_IF_nnn) OR'ed together.
+ ******************************************************************************/
+__STATIC_INLINE void IDAC_IntDisable(IDAC_TypeDef *idac, uint32_t flags)
+{
+  idac->IEN &= ~flags;
+}
+
+
+/***************************************************************************//**
+ * @brief
+ *   Enable one or more IDAC interrupts.
+ *
+ * @note
+ *   Depending on the use, a pending interrupt may already be set prior to
+ *   enabling the interrupt. Consider using IDAC_IntClear() prior to enabling
+ *   if such a pending interrupt should be ignored.
+ *
+ * @param[in] IDAC
+ *   Pointer to IDAC peripheral register block.
+ *
+ * @param[in] flags
+ *   IDAC interrupt source(s) to enable. Use one or more valid
+ *   interrupt flags for the IDAC module (IDAC_IF_nnn) OR'ed together.
+ ******************************************************************************/
+__STATIC_INLINE void IDAC_IntEnable(IDAC_TypeDef *idac, uint32_t flags)
+{
+  idac->IEN |= flags;
+}
+
+
+/***************************************************************************//**
+ * @brief
+ *   Get pending IDAC interrupt flags.
+ *
+ * @note
+ *   The event bits are not cleared by the use of this function.
+ *
+ * @param[in] IDAC
+ *   Pointer to IDAC peripheral register block.
+ *
+ * @return
+ *   IDAC interrupt source(s) pending. Returns one or more valid
+ *   interrupt flags for the IDAC module (IDAC_IF_nnn) OR'ed together.
+ ******************************************************************************/
+__STATIC_INLINE uint32_t IDAC_IntGet(IDAC_TypeDef *idac)
+{
+  return idac->IF;
+}
+
+
+/***************************************************************************//**
+ * @brief
+ *   Get enabled and pending IDAC interrupt flags.
+ *   Useful for handling more interrupt sources in the same interrupt handler.
+ *
+ * @param[in] IDAC
+ *   Pointer to IDAC peripheral register block.
+ *
+ * @note
+ *   Interrupt flags are not cleared by the use of this function.
+ *
+ * @return
+ *   Pending and enabled IDAC interrupt sources.
+ *   The return value is the bitwise AND combination of
+ *   - the OR combination of enabled interrupt sources in IDACx_IEN_nnn
+ *     register (IDACx_IEN_nnn) and
+ *   - the OR combination of valid interrupt flags of the IDAC module
+ *     (IDACx_IF_nnn).
+ ******************************************************************************/
+__STATIC_INLINE uint32_t IDAC_IntGetEnabled(IDAC_TypeDef *idac)
+{
+  uint32_t ien;
+
+  /* Store flags in temporary variable in order to define explicit order
+   * of volatile accesses. */
+  ien = idac->IEN;
+
+  /* Bitwise AND of pending and enabled interrupts */
+  return idac->IF & ien;
+}
+
+
+/***************************************************************************//**
+ * @brief
+ *   Set one or more pending IDAC interrupts from SW.
+ *
+ * @param[in] IDAC
+ *   Pointer to IDAC peripheral register block.
+ *
+ * @param[in] flags
+ *   IDAC interrupt source(s) to set to pending. Use one or more valid
+ *   interrupt flags for the IDAC module (IDAC_IF_nnn) OR'ed together.
+ ******************************************************************************/
+__STATIC_INLINE void IDAC_IntSet(IDAC_TypeDef *idac, uint32_t flags)
+{
+  idac->IFS = flags;
+}
+#endif
+
+
 /** @} (end addtogroup IDAC) */
 /** @} (end addtogroup EM_Library) */
 
@@ -271,4 +432,4 @@
 
 #endif /* defined(IDAC_COUNT) && (IDAC_COUNT > 0) */
 
-#endif /* __SILICON_LABS_EM_IDAC_H_ */
+#endif /* __SILICON_LABS_EM_IDAC_H__ */

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_int.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_int.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /***************************************************************************//**
  * @file em_int.h
  * @brief Interrupt enable/disable unit API
- * @version 3.20.12
+ * @version 4.2.1
  *******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
  *******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,9 +30,8 @@
  *
  ******************************************************************************/
 
-
-#ifndef __SILICON_LABS_EM_INT_H_
-#define __SILICON_LABS_EM_INT_H_
+#ifndef __SILICON_LABS_EM_INT_H__
+#define __SILICON_LABS_EM_INT_H__
 
 #include "em_device.h"
 
@@ -66,7 +65,7 @@
  *   Disable interrupts and increment lock level counter.
  *
  * @return
- *   The resulting interrupt nesting level.
+ *   The resulting interrupt disable nesting level.
  *
  ******************************************************************************/
 __STATIC_INLINE uint32_t INT_Disable(void)
@@ -85,7 +84,7 @@
  *   Enable interrupts.
  *
  * @return
- *   The resulting interrupt nesting level.
+ *   The resulting interrupt disable nesting level.
  *
  * @details
  *   Decrement interrupt lock level counter and enable interrupts if counter
@@ -119,4 +118,4 @@
 }
 #endif
 
-#endif /* __SILICON_LABS_EM_INT_H_ */
+#endif /* __SILICON_LABS_EM_INT_H__ */

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_lcd.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_lcd.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /***************************************************************************//**
  * @file em_lcd.h
  * @brief Liquid Crystal Display (LCD) peripheral API
- * @version 3.20.12
+ * @version 4.2.1
  *******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
  *******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,9 +30,8 @@
  *
  ******************************************************************************/
 
-
-#ifndef __SILICON_LABS_EM_LCD_H_
-#define __SILICON_LABS_EM_LCD_H_
+#ifndef __SILICON_LABS_EM_LCD_H__
+#define __SILICON_LABS_EM_LCD_H__
 
 #include "em_device.h"
 
@@ -69,7 +68,7 @@
   lcdMuxTriplex    = LCD_DISPCTRL_MUX_TRIPLEX,
   /** Quadruplex / 1/4 Duty cycle (segments can be multiplexed with LCD_COM[0:3]) */
   lcdMuxQuadruplex = LCD_DISPCTRL_MUX_QUADRUPLEX,
-#if defined(_EFM32_TINY_FAMILY) || defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
+#if defined(LCD_DISPCTRL_MUXE_MUXE)
   /** Sextaplex / 1/6 Duty cycle (segments can be multiplexed with LCD_COM[0:5]) */
   lcdMuxSextaplex  = LCD_DISPCTRL_MUXE_MUXE | LCD_DISPCTRL_MUX_DUPLEX,
   /** Octaplex / 1/6 Duty cycle (segments can be multiplexed with LCD_COM[0:5]) */
@@ -86,7 +85,7 @@
   lcdBiasOneHalf   = LCD_DISPCTRL_BIAS_ONEHALF,
   /** 1/3 Bias (4 levels) */
   lcdBiasOneThird  = LCD_DISPCTRL_BIAS_ONETHIRD,
-#if defined(_EFM32_TINY_FAMILY) || defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
+#if defined(LCD_DISPCTRL_BIAS_ONEFOURTH)
   /** 1/4 Bias (5 levels) */
   lcdBiasOneFourth = LCD_DISPCTRL_BIAS_ONEFOURTH,
 #endif
@@ -160,11 +159,10 @@
   lcdSegment16_19 = (1 << 4),
   /** Select segment lines 20 to 23 */
   lcdSegment20_23 = (1 << 5),
-#if defined(_EFM32_TINY_FAMILY)
+#if defined(_LCD_SEGD0L_MASK) && (_LCD_SEGD0L_MASK == 0x00FFFFFFUL)
   /** Select all segment lines */
   lcdSegmentAll   = (0x003f)
-#endif
-#if defined(_EFM32_GECKO_FAMILY) || defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
+#elif defined(_LCD_SEGD0H_MASK) && (_LCD_SEGD0H_MASK == 0x000000FFUL)
   /** Select segment lines 24 to 27 */
   lcdSegment24_27 = (1 << 6),
   /** Select segment lines 28 to 31 */
@@ -229,7 +227,7 @@
   LCD_AnimShift_TypeDef BShift;
   /** A and B Logical Operation to use for mixing and outputting resulting segments */
   LCD_AnimLogic_TypeDef animLogic;
-#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
+#if defined(LCD_BACTRL_ALOC)
   /** Number of first segment to animate. Options are 0 or 8 for Giant/Leopard. End is startSeg+7 */
   int                   startSeg;
 #endif
@@ -265,13 +263,14 @@
 
 /** Default config for LCD init structure, enables 160 segments  */
 #define LCD_INIT_DEFAULT \
-  { true,                \
-    lcdMuxQuadruplex,    \
-    lcdBiasOneThird,     \
-    lcdWaveLowPower,     \
-    lcdVLCDSelVDD,       \
-    lcdConConfVLCD       \
-  }
+{                        \
+  true,                  \
+  lcdMuxQuadruplex,      \
+  lcdBiasOneThird,       \
+  lcdWaveLowPower,       \
+  lcdVLCDSelVDD,         \
+  lcdConConfVLCD         \
+}
 
 /*******************************************************************************
  *****************************   PROTOTYPES   **********************************
@@ -286,37 +285,17 @@
 void LCD_SegmentRangeEnable(LCD_SegmentRange_TypeDef segment, bool enable);
 void LCD_SegmentSet(int com, int bit, bool enable);
 void LCD_SegmentSetLow(int com, uint32_t mask, uint32_t bits);
-#if defined(_EFM32_GECKO_FAMILY) || defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
+#if defined(_LCD_SEGD0H_MASK)
 void LCD_SegmentSetHigh(int com, uint32_t mask, uint32_t bits);
 #endif
 void LCD_ContrastSet(int level);
 void LCD_VBoostSet(LCD_VBoostLevel_TypeDef vboost);
 
-#if defined(_EFM32_TINY_FAMILY) || defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
+#if defined(LCD_CTRL_DSC)
 void LCD_BiasSegmentSet(int segment, int biasLevel);
 void LCD_BiasComSet(int com, int biasLevel);
 #endif
 
-__STATIC_INLINE void LCD_Enable(bool enable);
-__STATIC_INLINE void LCD_AnimEnable(bool enable);
-__STATIC_INLINE void LCD_BlinkEnable(bool enable);
-__STATIC_INLINE void LCD_BlankEnable(bool enable);
-__STATIC_INLINE void LCD_FrameCountEnable(bool enable);
-__STATIC_INLINE int LCD_AnimState(void);
-__STATIC_INLINE int LCD_BlinkState(void);
-__STATIC_INLINE void LCD_FreezeEnable(bool enable);
-__STATIC_INLINE uint32_t LCD_SyncBusyGet(void);
-__STATIC_INLINE void LCD_SyncBusyDelay(uint32_t flags);
-__STATIC_INLINE uint32_t LCD_IntGet(void);
-__STATIC_INLINE uint32_t LCD_IntGetEnabled(void);
-__STATIC_INLINE void LCD_IntSet(uint32_t flags);
-__STATIC_INLINE void LCD_IntEnable(uint32_t flags);
-__STATIC_INLINE void LCD_IntDisable(uint32_t flags);
-__STATIC_INLINE void LCD_IntClear(uint32_t flags);
-#if defined(_EFM32_TINY_FAMILY) || defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
-__STATIC_INLINE void LCD_DSCEnable(bool enable);
-#endif
-
 /***************************************************************************//**
  * @brief
  *   Enable or disable LCD controller
@@ -334,7 +313,7 @@
   }
   else
   {
-    LCD->CTRL &= ~(LCD_CTRL_EN);
+    LCD->CTRL &= ~LCD_CTRL_EN;
   }
 }
 
@@ -354,7 +333,7 @@
   }
   else
   {
-    LCD->BACTRL &= ~(LCD_BACTRL_AEN);
+    LCD->BACTRL &= ~LCD_BACTRL_AEN;
   }
 }
 
@@ -374,7 +353,7 @@
   }
   else
   {
-    LCD->BACTRL &= ~(LCD_BACTRL_BLINKEN);
+    LCD->BACTRL &= ~LCD_BACTRL_BLINKEN;
   }
 }
 
@@ -394,7 +373,7 @@
   }
   else
   {
-    LCD->BACTRL &= ~(LCD_BACTRL_BLANK);
+    LCD->BACTRL &= ~LCD_BACTRL_BLANK;
   }
 }
 
@@ -414,7 +393,7 @@
   }
   else
   {
-    LCD->BACTRL &= ~(LCD_BACTRL_FCEN);
+    LCD->BACTRL &= ~LCD_BACTRL_FCEN;
   }
 }
 
@@ -475,7 +454,7 @@
  ******************************************************************************/
 __STATIC_INLINE uint32_t LCD_SyncBusyGet(void)
 {
-  return(LCD->SYNCBUSY);
+  return LCD->SYNCBUSY;
 }
 
 
@@ -503,7 +482,7 @@
  ******************************************************************************/
 __STATIC_INLINE uint32_t LCD_IntGet(void)
 {
-  return(LCD->IF);
+  return LCD->IF;
 }
 
 
@@ -527,14 +506,14 @@
  ******************************************************************************/
 __STATIC_INLINE uint32_t LCD_IntGetEnabled(void)
 {
-  uint32_t tmp = 0U;
+  uint32_t ien;
 
   /* Store LCD->IEN in temporary variable in order to define explicit order
    * of volatile accesses. */
-  tmp = LCD->IEN;
+  ien = LCD->IEN;
 
   /* Bitwise AND of pending and enabled interrupts */
-  return LCD->IF & tmp;
+  return LCD->IF & ien;
 }
 
 
@@ -579,7 +558,7 @@
  ******************************************************************************/
 __STATIC_INLINE void LCD_IntDisable(uint32_t flags)
 {
-  LCD->IEN &= ~(flags);
+  LCD->IEN &= ~flags;
 }
 
 
@@ -598,7 +577,7 @@
 }
 
 
-#if defined(_EFM32_TINY_FAMILY) || defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
+#if defined(LCD_CTRL_DSC)
 /***************************************************************************//**
  * @brief
  *   Enable or disable LCD Direct Segment Control
@@ -616,7 +595,7 @@
   }
   else
   {
-    LCD->CTRL &= ~(LCD_CTRL_DSC);
+    LCD->CTRL &= ~LCD_CTRL_DSC;
   }
 }
 #endif
@@ -630,4 +609,4 @@
 
 #endif /* defined(LCD_COUNT) && (LCD_COUNT > 0) */
 
-#endif /* __SILICON_LABS_EM_LCD_H_ */
+#endif /* __SILICON_LABS_EM_LCD_H__ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_ldma.h	Fri Jan 15 07:45:16 2016 +0000
@@ -0,0 +1,1330 @@
+/***************************************************************************//**
+ * @file em_ldma.h
+ * @brief Direct memory access (LDMA) API
+ * @version 4.2.1
+ *******************************************************************************
+ * @section License
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
+ *******************************************************************************
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software.@n
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.@n
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
+ * obligation to support this Software. Silicon Labs is providing the
+ * Software "AS IS", with no express or implied warranties of any kind,
+ * including, but not limited to, any implied warranties of merchantability
+ * or fitness for any particular purpose or warranties against infringement
+ * of any proprietary rights of a third party.
+ *
+ * Silicon Labs will not be liable for any consequential, incidental, or
+ * special damages, or any other relief, or for any claim by any third party,
+ * arising from your use of this Software.
+ *
+ ******************************************************************************/
+
+#ifndef __SILICON_LABS_EM_LDMA_H__
+#define __SILICON_LABS_EM_LDMA_H__
+
+#include "em_device.h"
+
+#if defined( LDMA_PRESENT ) && ( LDMA_COUNT == 1 )
+
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/***************************************************************************//**
+ * @addtogroup EM_Library
+ * @{
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * @addtogroup LDMA
+ * @{
+ ******************************************************************************/
+
+/*******************************************************************************
+ ********************************   ENUMS   ************************************
+ ******************************************************************************/
+
+/**
+ * This value controls the number of unit data transfers per arbitration
+ * cycle, providing a means to balance DMA channels' load on the controller.
+ */
+typedef enum
+{
+  ldmaCtrlBlockSizeUnit1    = _LDMA_CH_CTRL_BLOCKSIZE_UNIT1,    /**< One transfer per arbitration.     */
+  ldmaCtrlBlockSizeUnit2    = _LDMA_CH_CTRL_BLOCKSIZE_UNIT2,    /**< Two transfers per arbitration.    */
+  ldmaCtrlBlockSizeUnit3    = _LDMA_CH_CTRL_BLOCKSIZE_UNIT3,    /**< Three transfers per arbitration.  */
+  ldmaCtrlBlockSizeUnit4    = _LDMA_CH_CTRL_BLOCKSIZE_UNIT4,    /**< Four transfers per arbitration.   */
+  ldmaCtrlBlockSizeUnit6    = _LDMA_CH_CTRL_BLOCKSIZE_UNIT6,    /**< Six transfers per arbitration.    */
+  ldmaCtrlBlockSizeUnit8    = _LDMA_CH_CTRL_BLOCKSIZE_UNIT8,    /**< Eight transfers per arbitration.  */
+  ldmaCtrlBlockSizeUnit16   = _LDMA_CH_CTRL_BLOCKSIZE_UNIT16,   /**< 16 transfers per arbitration.     */
+  ldmaCtrlBlockSizeUnit32   = _LDMA_CH_CTRL_BLOCKSIZE_UNIT32,   /**< 32 transfers per arbitration.     */
+  ldmaCtrlBlockSizeUnit64   = _LDMA_CH_CTRL_BLOCKSIZE_UNIT64,   /**< 64 transfers per arbitration.     */
+  ldmaCtrlBlockSizeUnit128  = _LDMA_CH_CTRL_BLOCKSIZE_UNIT128,  /**< 128 transfers per arbitration.    */
+  ldmaCtrlBlockSizeUnit256  = _LDMA_CH_CTRL_BLOCKSIZE_UNIT256,  /**< 256 transfers per arbitration.    */
+  ldmaCtrlBlockSizeUnit512  = _LDMA_CH_CTRL_BLOCKSIZE_UNIT512,  /**< 512 transfers per arbitration.    */
+  ldmaCtrlBlockSizeUnit1024 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT1024, /**< 1024 transfers per arbitration.   */
+  ldmaCtrlBlockSizeAll      = _LDMA_CH_CTRL_BLOCKSIZE_ALL       /**< Lock arbitration during transfer. */
+} LDMA_CtrlBlockSize_t;
+
+/** DMA structure type. */
+typedef enum
+{
+  ldmaCtrlStructTypeXfer  = _LDMA_CH_CTRL_STRUCTTYPE_TRANSFER,    /**< TRANSFER transfer type.    */
+  ldmaCtrlStructTypeSync  = _LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE, /**< SYNCHRONIZE transfer type. */
+  ldmaCtrlStructTypeWrite = _LDMA_CH_CTRL_STRUCTTYPE_WRITE        /**< WRITE transfer type.       */
+} LDMA_CtrlStructType_t;
+
+/** DMA transfer block or cycle selector. */
+typedef enum
+{
+  ldmaCtrlReqModeBlock = _LDMA_CH_CTRL_REQMODE_BLOCK, /**< Each DMA request trigger transfer of one block.     */
+  ldmaCtrlReqModeAll   = _LDMA_CH_CTRL_REQMODE_ALL    /**< A DMA request trigger transfer of a complete cycle. */
+} LDMA_CtrlReqMode_t;
+
+/** Source address increment unit size. */
+typedef enum
+{
+  ldmaCtrlSrcIncOne  = _LDMA_CH_CTRL_SRCINC_ONE,  /**< Increment source address by one unit data size.   */
+  ldmaCtrlSrcIncTwo  = _LDMA_CH_CTRL_SRCINC_TWO,  /**< Increment source address by two unit data sizes.  */
+  ldmaCtrlSrcIncFour = _LDMA_CH_CTRL_SRCINC_FOUR, /**< Increment source address by four unit data sizes. */
+  ldmaCtrlSrcIncNone = _LDMA_CH_CTRL_SRCINC_NONE  /**< Do not increment the source address.              */
+} LDMA_CtrlSrcInc_t;
+
+/** DMA transfer unit size. */
+typedef enum
+{
+  ldmaCtrlSizeByte = _LDMA_CH_CTRL_SIZE_BYTE,     /**< Each unit transfer is a byte.      */
+  ldmaCtrlSizeHalf = _LDMA_CH_CTRL_SIZE_HALFWORD, /**< Each unit transfer is a half-word. */
+  ldmaCtrlSizeWord = _LDMA_CH_CTRL_SIZE_WORD      /**< Each unit transfer is a word.      */
+} LDMA_CtrlSize_t;
+
+/** Destination address increment unit size. */
+typedef enum
+{
+  ldmaCtrlDstIncOne  = _LDMA_CH_CTRL_DSTINC_ONE,  /**< Increment destination address by one unit data size.   */
+  ldmaCtrlDstIncTwo  = _LDMA_CH_CTRL_DSTINC_TWO,  /**< Increment destination address by two unit data sizes.  */
+  ldmaCtrlDstIncFour = _LDMA_CH_CTRL_DSTINC_FOUR, /**< Increment destination address by four unit data sizes. */
+  ldmaCtrlDstIncNone = _LDMA_CH_CTRL_DSTINC_NONE  /**< Do not increment the destination address.              */
+} LDMA_CtrlDstInc_t;
+
+/** Source addressing mode. */
+typedef enum
+{
+  ldmaCtrlSrcAddrModeAbs = _LDMA_CH_CTRL_SRCMODE_ABSOLUTE, /**< Address fetched from a linked structure is absolute.  */
+  ldmaCtrlSrcAddrModeRel = _LDMA_CH_CTRL_SRCMODE_RELATIVE  /**< Address fetched from a linked structure is relative.  */
+} LDMA_CtrlSrcAddrMode_t;
+
+/** Destination addressing mode. */
+typedef enum
+{
+  ldmaCtrlDstAddrModeAbs = _LDMA_CH_CTRL_DSTMODE_ABSOLUTE, /**< Address fetched from a linked structure is absolute.  */
+  ldmaCtrlDstAddrModeRel = _LDMA_CH_CTRL_DSTMODE_RELATIVE  /**< Address fetched from a linked structure is relative.  */
+} LDMA_CtrlDstAddrMode_t;
+
+/** DMA linkload address mode. */
+typedef enum
+{
+  ldmaLinkModeAbs = _LDMA_CH_LINK_LINKMODE_ABSOLUTE, /**< Link address is an absolute address value.            */
+  ldmaLinkModeRel = _LDMA_CH_LINK_LINKMODE_RELATIVE  /**< Link address is a two's complement releative address. */
+} LDMA_LinkMode_t;
+
+/** Insert extra arbitration slots to increase channel arbitration priority. */
+typedef enum
+{
+  ldmaCfgArbSlotsAs1 = _LDMA_CH_CFG_ARBSLOTS_ONE,  /**< One arbitration slot selected.    */
+  ldmaCfgArbSlotsAs2 = _LDMA_CH_CFG_ARBSLOTS_TWO,  /**< Two arbitration slots selected.   */
+  ldmaCfgArbSlotsAs4 = _LDMA_CH_CFG_ARBSLOTS_FOUR, /**< Four arbitration slots selected.  */
+  ldmaCfgArbSlotsAs8 = _LDMA_CH_CFG_ARBSLOTS_EIGHT /**< Eight arbitration slots selected. */
+} LDMA_CfgArbSlots_t;
+
+/** Source address increment sign. */
+typedef enum
+{
+  ldmaCfgSrcIncSignPos = _LDMA_CH_CFG_SRCINCSIGN_POSITIVE, /**< Increment source address. */
+  ldmaCfgSrcIncSignNeg = _LDMA_CH_CFG_SRCINCSIGN_NEGATIVE  /**< Decrement source address. */
+} LDMA_CfgSrcIncSign_t;
+
+/** Destination address increment sign. */
+typedef enum
+{
+  ldmaCfgDstIncSignPos = _LDMA_CH_CFG_DSTINCSIGN_POSITIVE, /**< Increment destination address. */
+  ldmaCfgDstIncSignNeg = _LDMA_CH_CFG_DSTINCSIGN_NEGATIVE  /**< Decrement destination address. */
+} LDMA_CfgDstIncSign_t;
+
+/** Peripherals that can trigger LDMA transfers. */
+typedef enum
+{
+  ldmaPeripheralSignal_NONE = LDMA_CH_REQSEL_SOURCESEL_NONE,                                                                ///< No peripheral selected for DMA triggering.
+  #if defined( LDMA_CH_REQSEL_SIGSEL_ADC0SCAN )
+  ldmaPeripheralSignal_ADC0_SCAN = LDMA_CH_REQSEL_SIGSEL_ADC0SCAN | LDMA_CH_REQSEL_SOURCESEL_ADC0,                          ///< Trig on ADC0_SCAN.
+  #endif
+  #if defined( LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE )
+  ldmaPeripheralSignal_ADC0_SINGLE = LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE | LDMA_CH_REQSEL_SOURCESEL_ADC0,                      ///< Trig on ADC0_SINGLE.
+  #endif
+  #if defined( LDMA_CH_REQSEL_SIGSEL_AGCRSSI )
+  ldmaPeripheralSignal_AGC_RSSI = LDMA_CH_REQSEL_SIGSEL_AGCRSSI | LDMA_CH_REQSEL_SOURCESEL_AGC,                             ///< Trig on AGC_RSSI.
+  #endif
+  #if defined( LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0RD )
+  ldmaPeripheralSignal_CRYPTO_DATA0RD = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO,              ///< Trig on CRYPTO_DATA0RD.
+  #endif
+  #if defined( LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0WR )
+  ldmaPeripheralSignal_CRYPTO_DATA0WR = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO,              ///< Trig on CRYPTO_DATA0WR.
+  #endif
+  #if defined( LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0XWR )
+  ldmaPeripheralSignal_CRYPTO_DATA0XWR = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0XWR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO,            ///< Trig on CRYPTO_DATA0XWR.
+  #endif
+  #if defined( LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1RD )
+  ldmaPeripheralSignal_CRYPTO_DATA1RD = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO,              ///< Trig on CRYPTO_DATA1RD.
+  #endif
+  #if defined( LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1WR )
+  ldmaPeripheralSignal_CRYPTO_DATA1WR = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO,              ///< Trig on CRYPTO_DATA1WR.
+  #endif
+  #if defined( LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV )
+  ldmaPeripheralSignal_I2C0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_I2C0,                    ///< Trig on I2C0_RXDATAV.
+  #endif
+  #if defined( LDMA_CH_REQSEL_SIGSEL_I2C0TXBL )
+  ldmaPeripheralSignal_I2C0_TXBL = LDMA_CH_REQSEL_SIGSEL_I2C0TXBL | LDMA_CH_REQSEL_SOURCESEL_I2C0,                          ///< Trig on I2C0_TXBL.
+  #endif
+  #if defined( LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV )
+  ldmaPeripheralSignal_LEUART0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_LEUART0,           ///< Trig on LEUART0_RXDATAV.
+  #endif
+  #if defined( LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL )
+  ldmaPeripheralSignal_LEUART0_TXBL = LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL | LDMA_CH_REQSEL_SOURCESEL_LEUART0,                 ///< Trig on LEUART0_TXBL.
+  #endif
+  #if defined( LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY )
+  ldmaPeripheralSignal_LEUART0_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_LEUART0,           ///< Trig on LEUART0_TXEMPTY.
+  #endif
+  #if defined( LDMA_CH_REQSEL_SIGSEL_MODEMDEBUG )
+  ldmaPeripheralSignal_MODEM_DEBUG = LDMA_CH_REQSEL_SIGSEL_MODEMDEBUG | LDMA_CH_REQSEL_SOURCESEL_MODEM,                     ///< Trig on MODEM_DEBUG.
+  #endif
+  #if defined( LDMA_CH_REQSEL_SIGSEL_MSCWDATA )
+  ldmaPeripheralSignal_MSC_WDATA = LDMA_CH_REQSEL_SIGSEL_MSCWDATA | LDMA_CH_REQSEL_SOURCESEL_MSC,                           ///< Trig on MSC_WDATA.
+  #endif
+  #if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERBOF )
+  ldmaPeripheralSignal_PROTIMER_BOF = LDMA_CH_REQSEL_SIGSEL_PROTIMERBOF | LDMA_CH_REQSEL_SOURCESEL_PROTIMER,                ///< Trig on PROTIMER_BOF.
+  #endif
+  #if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERCC0 )
+  ldmaPeripheralSignal_PROTIMER_CC0 = LDMA_CH_REQSEL_SIGSEL_PROTIMERCC0 | LDMA_CH_REQSEL_SOURCESEL_PROTIMER,                ///< Trig on PROTIMER_CC0.
+  #endif
+  #if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERCC1 )
+  ldmaPeripheralSignal_PROTIMER_CC1 = LDMA_CH_REQSEL_SIGSEL_PROTIMERCC1 | LDMA_CH_REQSEL_SOURCESEL_PROTIMER,                ///< Trig on PROTIMER_CC1.
+  #endif
+  #if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERCC2 )
+  ldmaPeripheralSignal_PROTIMER_CC2 = LDMA_CH_REQSEL_SIGSEL_PROTIMERCC2 | LDMA_CH_REQSEL_SOURCESEL_PROTIMER,                ///< Trig on PROTIMER_CC2.
+  #endif
+  #if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERCC3 )
+  ldmaPeripheralSignal_PROTIMER_CC3 = LDMA_CH_REQSEL_SIGSEL_PROTIMERCC3 | LDMA_CH_REQSEL_SOURCESEL_PROTIMER,                ///< Trig on PROTIMER_CC3.
+  #endif
+  #if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERCC4 )
+  ldmaPeripheralSignal_PROTIMER_CC4 = LDMA_CH_REQSEL_SIGSEL_PROTIMERCC4 | LDMA_CH_REQSEL_SOURCESEL_PROTIMER,                ///< Trig on PROTIMER_CC4.
+  #endif
+  #if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERPOF )
+  ldmaPeripheralSignal_PROTIMER_POF = LDMA_CH_REQSEL_SIGSEL_PROTIMERPOF | LDMA_CH_REQSEL_SOURCESEL_PROTIMER,                ///< Trig on PROTIMER_POF.
+  #endif
+  #if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERWOF )
+  ldmaPeripheralSignal_PROTIMER_WOF = LDMA_CH_REQSEL_SIGSEL_PROTIMERWOF | LDMA_CH_REQSEL_SOURCESEL_PROTIMER,                ///< Trig on PROTIMER_WOF.
+  #endif
+  #if defined( LDMA_CH_REQSEL_SIGSEL_PRSREQ0 )
+  ldmaPeripheralSignal_PRS_REQ0 = LDMA_CH_REQSEL_SIGSEL_PRSREQ0 | LDMA_CH_REQSEL_SOURCESEL_PRS,                             ///< Trig on PRS_REQ0.
+  #endif
+  #if defined( LDMA_CH_REQSEL_SIGSEL_PRSREQ1 )
+  ldmaPeripheralSignal_PRS_REQ1 = LDMA_CH_REQSEL_SIGSEL_PRSREQ1 | LDMA_CH_REQSEL_SOURCESEL_PRS,                             ///< Trig on PRS_REQ1.
+  #endif
+  #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 )
+  ldmaPeripheralSignal_TIMER0_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER0,                      ///< Trig on TIMER0_CC0.
+  #endif
+  #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 )
+  ldmaPeripheralSignal_TIMER0_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER0,                      ///< Trig on TIMER0_CC1.
+  #endif
+  #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 )
+  ldmaPeripheralSignal_TIMER0_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER0,                      ///< Trig on TIMER0_CC2.
+  #endif
+  #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF )
+  ldmaPeripheralSignal_TIMER0_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER0,                    ///< Trig on TIMER0_UFOF.
+  #endif
+  #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 )
+  ldmaPeripheralSignal_TIMER1_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER1,                      ///< Trig on TIMER1_CC0.
+  #endif
+  #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 )
+  ldmaPeripheralSignal_TIMER1_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER1,                      ///< Trig on TIMER1_CC1.
+  #endif
+  #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 )
+  ldmaPeripheralSignal_TIMER1_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER1,                      ///< Trig on TIMER1_CC2.
+  #endif
+  #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 )
+  ldmaPeripheralSignal_TIMER1_CC3 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 | LDMA_CH_REQSEL_SOURCESEL_TIMER1,                      ///< Trig on TIMER1_CC3.
+  #endif
+  #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF )
+  ldmaPeripheralSignal_TIMER1_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER1,                    ///< Trig on TIMER1_UFOF.
+  #endif
+  #if defined( LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV )
+  ldmaPeripheralSignal_USART0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART0,              ///< Trig on USART0_RXDATAV.
+  #endif
+  #if defined( LDMA_CH_REQSEL_SIGSEL_USART0TXBL )
+  ldmaPeripheralSignal_USART0_TXBL = LDMA_CH_REQSEL_SIGSEL_USART0TXBL | LDMA_CH_REQSEL_SOURCESEL_USART0,                    ///< Trig on USART0_TXBL.
+  #endif
+  #if defined( LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY )
+  ldmaPeripheralSignal_USART0_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART0,              ///< Trig on USART0_TXEMPTY.
+  #endif
+  #if defined( LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV )
+  ldmaPeripheralSignal_USART1_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART1,              ///< Trig on USART1_RXDATAV.
+  #endif
+  #if defined( LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT )
+  ldmaPeripheralSignal_USART1_RXDATAVRIGHT = LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART1,    ///< Trig on USART1_RXDATAVRIGHT.
+  #endif
+  #if defined( LDMA_CH_REQSEL_SIGSEL_USART1TXBL )
+  ldmaPeripheralSignal_USART1_TXBL = LDMA_CH_REQSEL_SIGSEL_USART1TXBL | LDMA_CH_REQSEL_SOURCESEL_USART1,                    ///< Trig on USART1_TXBL.
+  #endif
+  #if defined( LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT )
+  ldmaPeripheralSignal_USART1_TXBLRIGHT = LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART1,          ///< Trig on USART1_TXBLRIGHT.
+  #endif
+  #if defined( LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY )
+  ldmaPeripheralSignal_USART1_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART1               ///< Trig on USART1_TXEMPTY.
+  #endif
+} LDMA_PeripheralSignal_t;
+
+
+/*******************************************************************************
+ *******************************   STRUCTS   ***********************************
+ ******************************************************************************/
+
+/**
+ * @brief
+ *   DMA descriptor.
+ * @details
+ *   The LDMA DMA controller supports three different DMA descriptors. Each
+ *   consist of four WORD's which map directly onto hw control registers for a
+ *   given DMA channel. The three descriptor types are XFER, SYNC and WRI.
+ *   Refer to the reference manual for further information.
+ */
+typedef union
+{
+  /**
+   *  TRANSFER DMA descriptor, this is the only descriptor type which can be
+   *  used to start a DMA transfer.
+   */
+  struct
+  {
+    uint32_t  structType : 2;   /**< Set to 0 to select XFER descriptor type. */
+    uint32_t  reserved0  : 1;
+    uint32_t  structReq  : 1;   /**< DMA transfer trigger during LINKLOAD.    */
+    uint32_t  xferCnt    : 11;  /**< Transfer count minus one.                */
+    uint32_t  byteSwap   : 1;   /**< Enable byte swapping transfers.          */
+    uint32_t  blockSize  : 4;   /**< Number of unit transfers per arb. cycle. */
+    uint32_t  doneIfs    : 1;   /**< Generate interrupt when done.            */
+    uint32_t  reqMode    : 1;   /**< Block or cycle transfer selector.        */
+    uint32_t  decLoopCnt : 1;   /**< Enable looped transfers.                 */
+    uint32_t  ignoreSrec : 1;   /**< Ignore single requests.                  */
+    uint32_t  srcInc     : 2;   /**< Source address increment unit size.      */
+    uint32_t  size       : 2;   /**< DMA transfer unit size.                  */
+    uint32_t  dstInc     : 2;   /**< Destination address increment unit size. */
+    uint32_t  srcAddrMode: 1;   /**< Source addressing mode.                  */
+    uint32_t  dstAddrMode: 1;   /**< Destination addressing mode.             */
+
+    uint32_t  srcAddr;          /**< DMA source address.                      */
+    uint32_t  dstAddr;          /**< DMA destination address.                 */
+
+    uint32_t  linkMode   : 1;   /**< Select absolute or relative link address.*/
+    uint32_t  link       : 1;   /**< Enable LINKLOAD when transfer is done.   */
+    int32_t   linkAddr   : 30;  /**< Address of next (linked) descriptor.     */
+  } xfer;
+
+  /** SYNCHRONIZE DMA descriptor, used for intra channel transfer
+  *   syncronization.
+  */
+  struct
+  {
+    uint32_t  structType : 2;   /**< Set to 1 to select SYNC descriptor type. */
+    uint32_t  reserved0  : 1;
+    uint32_t  structReq  : 1;   /**< DMA transfer trigger during LINKLOAD.    */
+    uint32_t  xferCnt    : 11;  /**< Transfer count minus one.                */
+    uint32_t  byteSwap   : 1;   /**< Enable byte swapping transfers.          */
+    uint32_t  blockSize  : 4;   /**< Number of unit transfers per arb. cycle. */
+    uint32_t  doneIfs    : 1;   /**< Generate interrupt when done.            */
+    uint32_t  reqMode    : 1;   /**< Block or cycle transfer selector.        */
+    uint32_t  decLoopCnt : 1;   /**< Enable looped transfers.                 */
+    uint32_t  ignoreSrec : 1;   /**< Ignore single requests.                  */
+    uint32_t  srcInc     : 2;   /**< Source address increment unit size.      */
+    uint32_t  size       : 2;   /**< DMA transfer unit size.                  */
+    uint32_t  dstInc     : 2;   /**< Destination address increment unit size. */
+    uint32_t  srcAddrMode: 1;   /**< Source addressing mode.                  */
+    uint32_t  dstAddrMode: 1;   /**< Destination addressing mode.             */
+
+    uint32_t  syncSet    : 8;   /**< Set bits in LDMA_CTRL.SYNCTRIG register. */
+    uint32_t  syncClr    : 8;   /**< Clear bits in LDMA_CTRL.SYNCTRIG register*/
+    uint32_t  reserved3  : 16;
+    uint32_t  matchVal   : 8;   /**< Sync trig match value.                   */
+    uint32_t  matchEn    : 8;   /**< Sync trig match enable.                  */
+    uint32_t  reserved4  : 16;
+
+    uint32_t  linkMode   : 1;   /**< Select absolute or relative link address.*/
+    uint32_t  link       : 1;   /**< Enable LINKLOAD when transfer is done.   */
+    int32_t   linkAddr   : 30;  /**< Address of next (linked) descriptor.     */
+  } sync;
+
+  /** WRITE DMA descriptor, used for write immediate operations.              */
+  struct
+  {
+    uint32_t  structType : 2;   /**< Set to 2 to select WRITE descriptor type.*/
+    uint32_t  reserved0  : 1;
+    uint32_t  structReq  : 1;   /**< DMA transfer trigger during LINKLOAD.    */
+    uint32_t  xferCnt    : 11;  /**< Transfer count minus one.                */
+    uint32_t  byteSwap   : 1;   /**< Enable byte swapping transfers.          */
+    uint32_t  blockSize  : 4;   /**< Number of unit transfers per arb. cycle. */
+    uint32_t  doneIfs    : 1;   /**< Generate interrupt when done.            */
+    uint32_t  reqMode    : 1;   /**< Block or cycle transfer selector.        */
+    uint32_t  decLoopCnt : 1;   /**< Enable looped transfers.                 */
+    uint32_t  ignoreSrec : 1;   /**< Ignore single requests.                  */
+    uint32_t  srcInc     : 2;   /**< Source address increment unit size.      */
+    uint32_t  size       : 2;   /**< DMA transfer unit size.                  */
+    uint32_t  dstInc     : 2;   /**< Destination address increment unit size. */
+    uint32_t  srcAddrMode: 1;   /**< Source addressing mode.                  */
+    uint32_t  dstAddrMode: 1;   /**< Destination addressing mode.             */
+
+    uint32_t  immVal;           /**< Data to be written at dstAddr.           */
+    uint32_t  dstAddr;          /**< DMA write destination address.           */
+
+    uint32_t  linkMode   : 1;   /**< Select absolute or relative link address.*/
+    uint32_t  link       : 1;   /**< Enable LINKLOAD when transfer is done.   */
+    int32_t   linkAddr   : 30;  /**< Address of next (linked) descriptor.     */
+  } wri;
+} LDMA_Descriptor_t;
+
+/** @brief LDMA initialization configuration structure. */
+typedef struct
+{
+  uint8_t               ldmaInitCtrlNumFixed;     /**< Arbitration mode separator.*/
+  uint8_t               ldmaInitCtrlSyncPrsClrEn; /**< PRS Synctrig clear enable. */
+  uint8_t               ldmaInitCtrlSyncPrsSetEn; /**< PRS Synctrig set enable.   */
+  uint8_t               ldmaInitIrqPriority;      /**< LDMA IRQ priority (0..7).  */
+} LDMA_Init_t;
+
+/**
+ * @brief
+ *   DMA transfer configuration structure.
+ * @details
+ *   This struct configures all aspects of a DMA transfer.
+ */
+typedef struct
+{
+  uint32_t              ldmaReqSel;            /**< Selects DMA trigger source.          */
+  uint8_t               ldmaCtrlSyncPrsClrOff; /**< PRS Synctrig clear enables to clear. */
+  uint8_t               ldmaCtrlSyncPrsClrOn;  /**< PRS Synctrig clear enables to set.   */
+  uint8_t               ldmaCtrlSyncPrsSetOff; /**< PRS Synctrig set enables to clear.   */
+  uint8_t               ldmaCtrlSyncPrsSetOn;  /**< PRS Synctrig set enables to set.     */
+  bool                  ldmaReqDis;            /**< Mask the PRS trigger input.          */
+  bool                  ldmaDbgHalt;           /**< Dis. DMA trig when cpu is halted.    */
+  uint8_t               ldmaCfgArbSlots;       /**< Arbitration slot number.             */
+  uint8_t               ldmaCfgSrcIncSign;     /**< Source addr. increment sign.         */
+  uint8_t               ldmaCfgDstIncSign;     /**< Dest. addr. increment sign.          */
+  uint8_t               ldmaLoopCnt;           /**< Counter for looped transfers.        */
+} LDMA_TransferCfg_t;
+
+
+/*******************************************************************************
+ **************************   STRUCT INITIALIZERS   ****************************
+ ******************************************************************************/
+
+
+/** @brief Default DMA initialization structure. */
+#define LDMA_INIT_DEFAULT                                                                   \
+{                                                                                           \
+  .ldmaInitCtrlNumFixed     = _LDMA_CTRL_NUMFIXED_DEFAULT, /* Fixed priority arbitration. */ \
+  .ldmaInitCtrlSyncPrsClrEn = 0,                           /* No PRS Synctrig clear enable*/ \
+  .ldmaInitCtrlSyncPrsSetEn = 0,                           /* No PRS Synctrig set enable. */ \
+  .ldmaInitIrqPriority      = 3                            /* IRQ priority level 3.       */ \
+}
+
+/**
+ * @brief
+ *   Generic DMA transfer configuration for memory to memory transfers.
+ */
+#define LDMA_TRANSFER_CFG_MEMORY()              \
+{                                               \
+  0, 0, 0, 0, 0,                                \
+  false, false, ldmaCfgArbSlotsAs1,             \
+  ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, 0 \
+}
+
+/**
+ * @brief
+ *   Generic DMA transfer configuration for looped memory to memory transfers.
+ */
+#define LDMA_TRANSFER_CFG_MEMORY_LOOP( loopCnt) \
+{                                               \
+  0, 0, 0, 0, 0,                                \
+  false, false, ldmaCfgArbSlotsAs1,             \
+  ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos,   \
+  loopCnt                                       \
+}
+
+/**
+ * @brief
+ *   Generic DMA transfer configuration for memory to/from peripheral transfers.
+ */
+#define LDMA_TRANSFER_CFG_PERIPHERAL( signal )  \
+{                                               \
+  signal, 0, 0, 0, 0,                           \
+  false, false, ldmaCfgArbSlotsAs1,             \
+  ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, 0 \
+}
+
+/**
+ * @brief
+ *   Generic DMA transfer configuration for looped memory to/from peripheral transfers.
+ */
+#define LDMA_TRANSFER_CFG_PERIPHERAL_LOOP( signal, loopCnt )  \
+{                                                             \
+  signal, 0, 0, 0, 0,                                         \
+  false, false, ldmaCfgArbSlotsAs1,                           \
+  ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, loopCnt         \
+}
+
+/**
+ * @brief
+ *   DMA descriptor initializer for single memory to memory word transfer.
+ * @param[in] src       Source data address.
+ * @param[in] dest      Destination data address.
+ * @param[in] count     Number of words to transfer.
+ */
+#define LDMA_DESCRIPTOR_SINGLE_M2M_WORD( src, dest, count ) \
+{                                                           \
+  .xfer =                                                   \
+  {                                                         \
+    .structType   = ldmaCtrlStructTypeXfer,                 \
+    .structReq    = 1,                                      \
+    .xferCnt      = ( count ) - 1,                          \
+    .byteSwap     = 0,                                      \
+    .blockSize    = ldmaCtrlBlockSizeUnit1,                 \
+    .doneIfs      = 1,                                      \
+    .reqMode      = ldmaCtrlReqModeAll,                     \
+    .decLoopCnt   = 0,                                      \
+    .ignoreSrec   = 0,                                      \
+    .srcInc       = ldmaCtrlSrcIncOne,                      \
+    .size         = ldmaCtrlSizeWord,                       \
+    .dstInc       = ldmaCtrlDstIncOne,                      \
+    .srcAddrMode  = ldmaCtrlSrcAddrModeAbs,                 \
+    .dstAddrMode  = ldmaCtrlDstAddrModeAbs,                 \
+    .srcAddr      = (uint32_t)(src),                        \
+    .dstAddr      = (uint32_t)(dest),                       \
+    .linkMode     = 0,                                      \
+    .link         = 0,                                      \
+    .linkAddr     = 0                                       \
+  }                                                         \
+}
+
+/**
+ * @brief
+ *   DMA descriptor initializer for single memory to memory half-word transfer.
+ * @param[in] src       Source data address.
+ * @param[in] dest      Destination data address.
+ * @param[in] count     Number of half-words to transfer.
+ */
+#define LDMA_DESCRIPTOR_SINGLE_M2M_HALF( src, dest, count ) \
+{                                                           \
+  .xfer =                                                   \
+  {                                                         \
+    .structType   = ldmaCtrlStructTypeXfer,                 \
+    .structReq    = 1,                                      \
+    .xferCnt      = ( count ) - 1,                          \
+    .byteSwap     = 0,                                      \
+    .blockSize    = ldmaCtrlBlockSizeUnit1,                 \
+    .doneIfs      = 1,                                      \
+    .reqMode      = ldmaCtrlReqModeAll,                     \
+    .decLoopCnt   = 0,                                      \
+    .ignoreSrec   = 0,                                      \
+    .srcInc       = ldmaCtrlSrcIncOne,                      \
+    .size         = ldmaCtrlSizeHalf,                       \
+    .dstInc       = ldmaCtrlDstIncOne,                      \
+    .srcAddrMode  = ldmaCtrlSrcAddrModeAbs,                 \
+    .dstAddrMode  = ldmaCtrlDstAddrModeAbs,                 \
+    .srcAddr      = (uint32_t)(src),                        \
+    .dstAddr      = (uint32_t)(dest),                       \
+    .linkMode     = 0,                                      \
+    .link         = 0,                                      \
+    .linkAddr     = 0                                       \
+  }                                                         \
+}
+
+/**
+ * @brief
+ *   DMA descriptor initializer for single memory to memory byte transfer.
+ * @param[in] src       Source data address.
+ * @param[in] dest      Destination data address.
+ * @param[in] count     Number of bytes to transfer.
+ */
+#define LDMA_DESCRIPTOR_SINGLE_M2M_BYTE( src, dest, count ) \
+{                                                           \
+  .xfer =                                                   \
+  {                                                         \
+    .structType   = ldmaCtrlStructTypeXfer,                 \
+    .structReq    = 1,                                      \
+    .xferCnt      = ( count ) - 1,                          \
+    .byteSwap     = 0,                                      \
+    .blockSize    = ldmaCtrlBlockSizeUnit1,                 \
+    .doneIfs      = 1,                                      \
+    .reqMode      = ldmaCtrlReqModeAll,                     \
+    .decLoopCnt   = 0,                                      \
+    .ignoreSrec   = 0,                                      \
+    .srcInc       = ldmaCtrlSrcIncOne,                      \
+    .size         = ldmaCtrlSizeByte,                       \
+    .dstInc       = ldmaCtrlDstIncOne,                      \
+    .srcAddrMode  = ldmaCtrlSrcAddrModeAbs,                 \
+    .dstAddrMode  = ldmaCtrlDstAddrModeAbs,                 \
+    .srcAddr      = (uint32_t)(src),                        \
+    .dstAddr      = (uint32_t)(dest),                       \
+    .linkMode     = 0,                                      \
+    .link         = 0,                                      \
+    .linkAddr     = 0                                       \
+  }                                                         \
+}
+
+/**
+ * @brief
+ *   DMA descriptor initializer for linked memory to memory word transfer.
+ *
+ *   The link address must be an absolute address.
+ * @note
+ *   The linkAddr member of the transfer descriptor is not
+ *   initialized.
+ * @param[in] src       Source data address.
+ * @param[in] dest      Destination data address.
+ * @param[in] count     Number of words to transfer.
+ */
+#define LDMA_DESCRIPTOR_LINKABS_M2M_WORD( src, dest, count ) \
+{                                                            \
+  .xfer =                                                    \
+  {                                                          \
+    .structType   = ldmaCtrlStructTypeXfer,                  \
+    .structReq    = 1,                                       \
+    .xferCnt      = ( count ) - 1,                           \
+    .byteSwap     = 0,                                       \
+    .blockSize    = ldmaCtrlBlockSizeUnit1,                  \
+    .doneIfs      = 0,                                       \
+    .reqMode      = ldmaCtrlReqModeAll,                      \
+    .decLoopCnt   = 0,                                       \
+    .ignoreSrec   = 0,                                       \
+    .srcInc       = ldmaCtrlSrcIncOne,                       \
+    .size         = ldmaCtrlSizeWord,                        \
+    .dstInc       = ldmaCtrlDstIncOne,                       \
+    .srcAddrMode  = ldmaCtrlSrcAddrModeAbs,                  \
+    .dstAddrMode  = ldmaCtrlDstAddrModeAbs,                  \
+    .srcAddr      = (uint32_t)(src),                         \
+    .dstAddr      = (uint32_t)(dest),                        \
+    .linkMode     = ldmaLinkModeAbs,                         \
+    .link         = 1,                                       \
+    .linkAddr     = 0   /* Must be set runtime ! */          \
+  }                                                          \
+}
+
+/**
+ * @brief
+ *   DMA descriptor initializer for linked memory to memory half-word transfer.
+ *
+ *   The link address must be an absolute address.
+ * @note
+ *   The linkAddr member of the transfer descriptor is not
+ *   initialized.
+ * @param[in] src       Source data address.
+ * @param[in] dest      Destination data address.
+ * @param[in] count     Number of half-words to transfer.
+ */
+#define LDMA_DESCRIPTOR_LINKABS_M2M_HALF( src, dest, count ) \
+{                                                            \
+  .xfer =                                                    \
+  {                                                          \
+    .structType   = ldmaCtrlStructTypeXfer,                  \
+    .structReq    = 1,                                       \
+    .xferCnt      = ( count ) - 1,                           \
+    .byteSwap     = 0,                                       \
+    .blockSize    = ldmaCtrlBlockSizeUnit1,                  \
+    .doneIfs      = 0,                                       \
+    .reqMode      = ldmaCtrlReqModeAll,                      \
+    .decLoopCnt   = 0,                                       \
+    .ignoreSrec   = 0,                                       \
+    .srcInc       = ldmaCtrlSrcIncOne,                       \
+    .size         = ldmaCtrlSizeHalf,                        \
+    .dstInc       = ldmaCtrlDstIncOne,                       \
+    .srcAddrMode  = ldmaCtrlSrcAddrModeAbs,                  \
+    .dstAddrMode  = ldmaCtrlDstAddrModeAbs,                  \
+    .srcAddr      = (uint32_t)(src),                         \
+    .dstAddr      = (uint32_t)(dest),                        \
+    .linkMode     = ldmaLinkModeAbs,                         \
+    .link         = 1,                                       \
+    .linkAddr     = 0   /* Must be set runtime ! */          \
+  }                                                          \
+}
+
+/**
+ * @brief
+ *   DMA descriptor initializer for linked memory to memory byte transfer.
+ *
+ *   The link address must be an absolute address.
+ * @note
+ *   The linkAddr member of the transfer descriptor is not
+ *   initialized.
+ * @param[in] src       Source data address.
+ * @param[in] dest      Destination data address.
+ * @param[in] count     Number of bytes to transfer.
+ */
+#define LDMA_DESCRIPTOR_LINKABS_M2M_BYTE( src, dest, count ) \
+{                                                            \
+  .xfer =                                                    \
+  {                                                          \
+    .structType   = ldmaCtrlStructTypeXfer,                  \
+    .structReq    = 1,                                       \
+    .xferCnt      = ( count ) - 1,                           \
+    .byteSwap     = 0,                                       \
+    .blockSize    = ldmaCtrlBlockSizeUnit1,                  \
+    .doneIfs      = 0,                                       \
+    .reqMode      = ldmaCtrlReqModeAll,                      \
+    .decLoopCnt   = 0,                                       \
+    .ignoreSrec   = 0,                                       \
+    .srcInc       = ldmaCtrlSrcIncOne,                       \
+    .size         = ldmaCtrlSizeByte,                        \
+    .dstInc       = ldmaCtrlDstIncOne,                       \
+    .srcAddrMode  = ldmaCtrlSrcAddrModeAbs,                  \
+    .dstAddrMode  = ldmaCtrlDstAddrModeAbs,                  \
+    .srcAddr      = (uint32_t)(src),                         \
+    .dstAddr      = (uint32_t)(dest),                        \
+    .linkMode     = ldmaLinkModeAbs,                         \
+    .link         = 1,                                       \
+    .linkAddr     = 0   /* Must be set runtime ! */          \
+  }                                                          \
+}
+
+/**
+ * @brief
+ *   DMA descriptor initializer for linked memory to memory word transfer.
+ *
+ *   The link address is a relative address.
+ * @note
+ *   The linkAddr member of the transfer descriptor is
+ *   initialized to 4, assuming that the next descriptor immediately follows
+ *   this descriptor (in memory).
+ * @param[in] src       Source data address.
+ * @param[in] dest      Destination data address.
+ * @param[in] count     Number of words to transfer.
+ * @param[in] linkjmp   Address of descriptor to link to expressed as a
+ *                      signed number of descriptors from "here".
+ *                      1=one descriptor forward in memory,
+ *                      0=one this descriptor,
+ *                      -1=one descriptor back in memory.
+ */
+#define LDMA_DESCRIPTOR_LINKREL_M2M_WORD( src, dest, count, linkjmp ) \
+{                                                                     \
+  .xfer =                                                             \
+  {                                                                   \
+    .structType   = ldmaCtrlStructTypeXfer,                           \
+    .structReq    = 1,                                                \
+    .xferCnt      = ( count ) - 1,                                    \
+    .byteSwap     = 0,                                                \
+    .blockSize    = ldmaCtrlBlockSizeUnit1,                           \
+    .doneIfs      = 0,                                                \
+    .reqMode      = ldmaCtrlReqModeAll,                               \
+    .decLoopCnt   = 0,                                                \
+    .ignoreSrec   = 0,                                                \
+    .srcInc       = ldmaCtrlSrcIncOne,                                \
+    .size         = ldmaCtrlSizeWord,                                 \
+    .dstInc       = ldmaCtrlDstIncOne,                                \
+    .srcAddrMode  = ldmaCtrlSrcAddrModeAbs,                           \
+    .dstAddrMode  = ldmaCtrlDstAddrModeAbs,                           \
+    .srcAddr      = (uint32_t)(src),                                  \
+    .dstAddr      = (uint32_t)(dest),                                 \
+    .linkMode     = ldmaLinkModeRel,                                  \
+    .link         = 1,                                                \
+    .linkAddr     = ( linkjmp ) * 4                                   \
+  }                                                                   \
+}
+
+/**
+ * @brief
+ *   DMA descriptor initializer for linked memory to memory half-word transfer.
+ *
+ *   The link address is a relative address.
+ * @note
+ *   The linkAddr member of the transfer descriptor is
+ *   initialized to 4, assuming that the next descriptor immediately follows
+ *   this descriptor (in memory).
+ * @param[in] src       Source data address.
+ * @param[in] dest      Destination data address.
+ * @param[in] count     Number of half-words to transfer.
+ * @param[in] linkjmp   Address of descriptor to link to expressed as a
+ *                      signed number of descriptors from "here".
+ *                      1=one descriptor forward in memory,
+ *                      0=one this descriptor,
+ *                      -1=one descriptor back in memory.
+ */
+#define LDMA_DESCRIPTOR_LINKREL_M2M_HALF( src, dest, count, linkjmp ) \
+{                                                                     \
+  .xfer =                                                             \
+  {                                                                   \
+    .structType   = ldmaCtrlStructTypeXfer,                           \
+    .structReq    = 1,                                                \
+    .xferCnt      = ( count ) - 1,                                    \
+    .byteSwap     = 0,                                                \
+    .blockSize    = ldmaCtrlBlockSizeUnit1,                           \
+    .doneIfs      = 0,                                                \
+    .reqMode      = ldmaCtrlReqModeAll,                               \
+    .decLoopCnt   = 0,                                                \
+    .ignoreSrec   = 0,                                                \
+    .srcInc       = ldmaCtrlSrcIncOne,                                \
+    .size         = ldmaCtrlSizeHalf,                                 \
+    .dstInc       = ldmaCtrlDstIncOne,                                \
+    .srcAddrMode  = ldmaCtrlSrcAddrModeAbs,                           \
+    .dstAddrMode  = ldmaCtrlDstAddrModeAbs,                           \
+    .srcAddr      = (uint32_t)(src),                                  \
+    .dstAddr      = (uint32_t)(dest),                                 \
+    .linkMode     = ldmaLinkModeRel,                                  \
+    .link         = 1,                                                \
+    .linkAddr     = ( linkjmp ) * 4                                   \
+  }                                                                   \
+}
+
+/**
+ * @brief
+ *   DMA descriptor initializer for linked memory to memory byte transfer.
+ *
+ *   The link address is a relative address.
+ * @note
+ *   The linkAddr member of the transfer descriptor is
+ *   initialized to 4, assuming that the next descriptor immediately follows
+ *   this descriptor (in memory).
+ * @param[in] src       Source data address.
+ * @param[in] dest      Destination data address.
+ * @param[in] count     Number of bytes to transfer.
+ * @param[in] linkjmp   Address of descriptor to link to expressed as a
+ *                      signed number of descriptors from "here".
+ *                      1=one descriptor forward in memory,
+ *                      0=one this descriptor,
+ *                      -1=one descriptor back in memory.
+ */
+#define LDMA_DESCRIPTOR_LINKREL_M2M_BYTE( src, dest, count, linkjmp ) \
+{                                                                     \
+  .xfer =                                                             \
+  {                                                                   \
+    .structType   = ldmaCtrlStructTypeXfer,                           \
+    .structReq    = 1,                                                \
+    .xferCnt      = ( count ) - 1,                                    \
+    .byteSwap     = 0,                                                \
+    .blockSize    = ldmaCtrlBlockSizeUnit1,                           \
+    .doneIfs      = 0,                                                \
+    .reqMode      = ldmaCtrlReqModeAll,                               \
+    .decLoopCnt   = 0,                                                \
+    .ignoreSrec   = 0,                                                \
+    .srcInc       = ldmaCtrlSrcIncOne,                                \
+    .size         = ldmaCtrlSizeByte,                                 \
+    .dstInc       = ldmaCtrlDstIncOne,                                \
+    .srcAddrMode  = ldmaCtrlSrcAddrModeAbs,                           \
+    .dstAddrMode  = ldmaCtrlDstAddrModeAbs,                           \
+    .srcAddr      = (uint32_t)(src),                                  \
+    .dstAddr      = (uint32_t)(dest),                                 \
+    .linkMode     = ldmaLinkModeRel,                                  \
+    .link         = 1,                                                \
+    .linkAddr     = ( linkjmp ) * 4                                   \
+  }                                                                   \
+}
+
+/**
+ * @brief
+ *   DMA descriptor initializer for byte transfers from a peripheral to memory.
+ * @param[in] src       Peripheral data source register address.
+ * @param[in] dest      Destination data address.
+ * @param[in] count     Number of bytes to transfer.
+ */
+#define LDMA_DESCRIPTOR_SINGLE_P2M_BYTE( src, dest, count ) \
+{                                                           \
+  .xfer =                                                   \
+  {                                                         \
+    .structType   = ldmaCtrlStructTypeXfer,                 \
+    .structReq    = 0,                                      \
+    .xferCnt      = ( count ) - 1,                          \
+    .byteSwap     = 0,                                      \
+    .blockSize    = ldmaCtrlBlockSizeUnit1,                 \
+    .doneIfs      = 1,                                      \
+    .reqMode      = ldmaCtrlReqModeBlock,                   \
+    .decLoopCnt   = 0,                                      \
+    .ignoreSrec   = 0,                                      \
+    .srcInc       = ldmaCtrlSrcIncNone,                     \
+    .size         = ldmaCtrlSizeByte,                       \
+    .dstInc       = ldmaCtrlDstIncOne,                      \
+    .srcAddrMode  = ldmaCtrlSrcAddrModeAbs,                 \
+    .dstAddrMode  = ldmaCtrlDstAddrModeAbs,                 \
+    .srcAddr      = (uint32_t)(src),                        \
+    .dstAddr      = (uint32_t)(dest),                       \
+    .linkMode     = 0,                                      \
+    .link         = 0,                                      \
+    .linkAddr     = 0                                       \
+  }                                                         \
+}
+
+/**
+ * @brief
+ *   DMA descriptor initializer for byte transfers from memory to a peripheral
+ * @param[in] src       Source data address.
+ * @param[in] dest      Peripheral data register destination address.
+ * @param[in] count     Number of bytes to transfer.
+ */
+#define LDMA_DESCRIPTOR_SINGLE_M2P_BYTE( src, dest, count ) \
+{                                                           \
+  .xfer =                                                   \
+  {                                                         \
+    .structType   = ldmaCtrlStructTypeXfer,                 \
+    .structReq    = 0,                                      \
+    .xferCnt      = ( count ) - 1,                          \
+    .byteSwap     = 0,                                      \
+    .blockSize    = ldmaCtrlBlockSizeUnit1,                 \
+    .doneIfs      = 1,                                      \
+    .reqMode      = ldmaCtrlReqModeBlock,                   \
+    .decLoopCnt   = 0,                                      \
+    .ignoreSrec   = 0,                                      \
+    .srcInc       = ldmaCtrlSrcIncOne,                      \
+    .size         = ldmaCtrlSizeByte,                       \
+    .dstInc       = ldmaCtrlDstIncNone,                     \
+    .srcAddrMode  = ldmaCtrlSrcAddrModeAbs,                 \
+    .dstAddrMode  = ldmaCtrlDstAddrModeAbs,                 \
+    .srcAddr      = (uint32_t)(src),                        \
+    .dstAddr      = (uint32_t)(dest),                       \
+    .linkMode     = 0,                                      \
+    .link         = 0,                                      \
+    .linkAddr     = 0                                       \
+  }                                                         \
+}
+
+/**
+ * @brief
+ *   DMA descriptor initializer for byte transfers from a peripheral to memory.
+ * @param[in] src       Peripheral data source register address.
+ * @param[in] dest      Destination data address.
+ * @param[in] count     Number of bytes to transfer.
+ * @param[in] linkjmp   Address of descriptor to link to expressed as a
+ *                      signed number of descriptors from "here".
+ *                      1=one descriptor forward in memory,
+ *                      0=one this descriptor,
+ *                      -1=one descriptor back in memory.
+ */
+#define LDMA_DESCRIPTOR_LINKREL_P2M_BYTE( src, dest, count, linkjmp ) \
+{                                                                     \
+  .xfer =                                                             \
+  {                                                                   \
+    .structType   = ldmaCtrlStructTypeXfer,                           \
+    .structReq    = 0,                                                \
+    .xferCnt      = ( count ) - 1,                                    \
+    .byteSwap     = 0,                                                \
+    .blockSize    = ldmaCtrlBlockSizeUnit1,                           \
+    .doneIfs      = 1,                                                \
+    .reqMode      = ldmaCtrlReqModeBlock,                             \
+    .decLoopCnt   = 0,                                                \
+    .ignoreSrec   = 0,                                                \
+    .srcInc       = ldmaCtrlSrcIncNone,                               \
+    .size         = ldmaCtrlSizeByte,                                 \
+    .dstInc       = ldmaCtrlDstIncOne,                                \
+    .srcAddrMode  = ldmaCtrlSrcAddrModeAbs,                           \
+    .dstAddrMode  = ldmaCtrlDstAddrModeAbs,                           \
+    .srcAddr      = (uint32_t)(src),                                  \
+    .dstAddr      = (uint32_t)(dest),                                 \
+    .linkMode     = ldmaLinkModeRel,                                  \
+    .link         = 1,                                                \
+    .linkAddr     = ( linkjmp ) * 4                                   \
+  }                                                                   \
+}
+
+/**
+ * @brief
+ *   DMA descriptor initializer for byte transfers from memory to a peripheral
+ * @param[in] src       Source data address.
+ * @param[in] dest      Peripheral data register destination address.
+ * @param[in] count     Number of bytes to transfer.
+ * @param[in] linkjmp   Address of descriptor to link to expressed as a
+ *                      signed number of descriptors from "here".
+ *                      1=one descriptor forward in memory,
+ *                      0=one this descriptor,
+ *                      -1=one descriptor back in memory.
+ */
+#define LDMA_DESCRIPTOR_LINKREL_M2P_BYTE( src, dest, count, linkjmp ) \
+{                                                                     \
+  .xfer =                                                             \
+  {                                                                   \
+    .structType   = ldmaCtrlStructTypeXfer,                           \
+    .structReq    = 0,                                                \
+    .xferCnt      = ( count ) - 1,                                    \
+    .byteSwap     = 0,                                                \
+    .blockSize    = ldmaCtrlBlockSizeUnit1,                           \
+    .doneIfs      = 1,                                                \
+    .reqMode      = ldmaCtrlReqModeBlock,                             \
+    .decLoopCnt   = 0,                                                \
+    .ignoreSrec   = 0,                                                \
+    .srcInc       = ldmaCtrlSrcIncOne,                                \
+    .size         = ldmaCtrlSizeByte,                                 \
+    .dstInc       = ldmaCtrlDstIncNone,                               \
+    .srcAddrMode  = ldmaCtrlSrcAddrModeAbs,                           \
+    .dstAddrMode  = ldmaCtrlDstAddrModeAbs,                           \
+    .srcAddr      = (uint32_t)(src),                                  \
+    .dstAddr      = (uint32_t)(dest),                                 \
+    .linkMode     = ldmaLinkModeRel,                                  \
+    .link         = 1,                                                \
+    .linkAddr     = ( linkjmp ) * 4                                   \
+  }                                                                   \
+}
+
+/**
+ * @brief
+ *   DMA descriptor initializer for Immediate WRITE transfer
+ * @param[in] value     Immediate value to write.
+ * @param[in] address   Write sddress.
+ */
+#define LDMA_DESCRIPTOR_SINGLE_WRITE( value, address )  \
+{                                                       \
+  .wri =                                                \
+  {                                                     \
+    .structType   = ldmaCtrlStructTypeWrite,            \
+    .structReq    = 1,                                  \
+    .xferCnt      = 0,                                  \
+    .byteSwap     = 0,                                  \
+    .blockSize    = 0,                                  \
+    .doneIfs      = 1,                                  \
+    .reqMode      = 0,                                  \
+    .decLoopCnt   = 0,                                  \
+    .ignoreSrec   = 0,                                  \
+    .srcInc       = 0,                                  \
+    .size         = 0,                                  \
+    .dstInc       = 0,                                  \
+    .srcAddrMode  = 0,                                  \
+    .dstAddrMode  = 0,                                  \
+    .immVal       = (value),                            \
+    .dstAddr      = (uint32_t)(address),                \
+    .linkMode     = 0,                                  \
+    .link         = 0,                                  \
+    .linkAddr     = 0                                   \
+  }                                                     \
+}
+
+/**
+ * @brief
+ *   DMA descriptor initializer for Immediate WRITE transfer
+ *
+ *   The link address must be an absolute address.
+ * @note
+ *   The linkAddr member of the transfer descriptor is not
+ *   initialized.
+ * @param[in] value     Immediate value to write.
+ * @param[in] address   Write sddress.
+ */
+#define LDMA_DESCRIPTOR_LINKABS_WRITE( value, address )  \
+{                                                        \
+  .wri =                                                 \
+  {                                                      \
+    .structType   = ldmaCtrlStructTypeWrite,             \
+    .structReq    = 1,                                   \
+    .xferCnt      = 0,                                   \
+    .byteSwap     = 0,                                   \
+    .blockSize    = 0,                                   \
+    .doneIfs      = 0,                                   \
+    .reqMode      = 0,                                   \
+    .decLoopCnt   = 0,                                   \
+    .ignoreSrec   = 0,                                   \
+    .srcInc       = 0,                                   \
+    .size         = 0,                                   \
+    .dstInc       = 0,                                   \
+    .srcAddrMode  = 0,                                   \
+    .dstAddrMode  = 0,                                   \
+    .immVal       = (value),                             \
+    .dstAddr      = (uint32_t)(address),                 \
+    .linkMode     = ldmaLinkModeAbs,                     \
+    .link         = 1,                                   \
+    .linkAddr     = 0   /* Must be set runtime ! */      \
+  }                                                      \
+}
+
+/**
+ * @brief
+ *   DMA descriptor initializer for Immediate WRITE transfer
+ * @param[in] value     Immediate value to write.
+ * @param[in] address   Write sddress.
+ * @param[in] linkjmp   Address of descriptor to link to expressed as a
+ *                      signed number of descriptors from "here".
+ *                      1=one descriptor forward in memory,
+ *                      0=one this descriptor,
+ *                      -1=one descriptor back in memory.
+ */
+#define LDMA_DESCRIPTOR_LINKREL_WRITE( value, address, linkjmp )  \
+{                                                                 \
+  .wri =                                                          \
+  {                                                               \
+    .structType   = ldmaCtrlStructTypeWrite,                      \
+    .structReq    = 1,                                            \
+    .xferCnt      = 0,                                            \
+    .byteSwap     = 0,                                            \
+    .blockSize    = 0,                                            \
+    .doneIfs      = 0,                                            \
+    .reqMode      = 0,                                            \
+    .decLoopCnt   = 0,                                            \
+    .ignoreSrec   = 0,                                            \
+    .srcInc       = 0,                                            \
+    .size         = 0,                                            \
+    .dstInc       = 0,                                            \
+    .srcAddrMode  = 0,                                            \
+    .dstAddrMode  = 0,                                            \
+    .immVal       = (value),                                      \
+    .dstAddr      = (uint32_t)(address),                          \
+    .linkMode     = ldmaLinkModeRel,                              \
+    .link         = 1,                                            \
+    .linkAddr     = ( linkjmp ) * 4                               \
+  }                                                               \
+}
+
+/**
+ * @brief
+ *   DMA descriptor initializer for SYNC transfer
+ * @param[in] set          Sync pattern bits to set.
+ * @param[in] clr          Sync pattern bits to clear.
+ * @param[in] matchValue   Sync pattern to match.
+ * @param[in] matchEnable  Sync pattern bits to enable for match.
+ */
+#define LDMA_DESCRIPTOR_SINGLE_SYNC( set, clr, matchValue, matchEnable )  \
+{                                                                         \
+  .sync =                                                                 \
+  {                                                                       \
+    .structType   = ldmaCtrlStructTypeSync,                               \
+    .structReq    = 1,                                                    \
+    .xferCnt      = 0,                                                    \
+    .byteSwap     = 0,                                                    \
+    .blockSize    = 0,                                                    \
+    .doneIfs      = 1,                                                    \
+    .reqMode      = 0,                                                    \
+    .decLoopCnt   = 0,                                                    \
+    .ignoreSrec   = 0,                                                    \
+    .srcInc       = 0,                                                    \
+    .size         = 0,                                                    \
+    .dstInc       = 0,                                                    \
+    .srcAddrMode  = 0,                                                    \
+    .dstAddrMode  = 0,                                                    \
+    .syncSet      = (set),                                                \
+    .syncClr      = (clr),                                                \
+    .matchVal     = (matchValue),                                         \
+    .matchEn      = (matchEnable),                                        \
+    .linkMode     = 0,                                                    \
+    .link         = 0,                                                    \
+    .linkAddr     = 0                                                     \
+  }                                                                       \
+}
+
+/**
+ * @brief
+ *   DMA descriptor initializer for SYNC transfer
+ *
+ *   The link address must be an absolute address.
+ * @note
+ *   The linkAddr member of the transfer descriptor is not
+ *   initialized.
+ * @param[in] set          Sync pattern bits to set.
+ * @param[in] clr          Sync pattern bits to clear.
+ * @param[in] matchValue   Sync pattern to match.
+ * @param[in] matchEnable  Sync pattern bits to enable for match.
+ */
+#define LDMA_DESCRIPTOR_LINKABS_SYNC( set, clr, matchValue, matchEnable ) \
+{                                                                         \
+  .sync =                                                                 \
+  {                                                                       \
+    .structType   = ldmaCtrlStructTypeSync,                               \
+    .structReq    = 1,                                                    \
+    .xferCnt      = 0,                                                    \
+    .byteSwap     = 0,                                                    \
+    .blockSize    = 0,                                                    \
+    .doneIfs      = 0,                                                    \
+    .reqMode      = 0,                                                    \
+    .decLoopCnt   = 0,                                                    \
+    .ignoreSrec   = 0,                                                    \
+    .srcInc       = 0,                                                    \
+    .size         = 0,                                                    \
+    .dstInc       = 0,                                                    \
+    .srcAddrMode  = 0,                                                    \
+    .dstAddrMode  = 0,                                                    \
+    .syncSet      = (set),                                                \
+    .syncClr      = (clr),                                                \
+    .matchVal     = (matchValue),                                         \
+    .matchEn      = (matchEnable),                                        \
+    .linkMode     = ldmaLinkModeAbs,                                      \
+    .link         = 1,                                                    \
+    .linkAddr     = 0   /* Must be set runtime ! */                       \
+  }                                                                       \
+}
+
+/**
+ * @brief
+ *   DMA descriptor initializer for SYNC transfer
+ * @param[in] set          Sync pattern bits to set.
+ * @param[in] clr          Sync pattern bits to clear.
+ * @param[in] matchValue   Sync pattern to match.
+ * @param[in] matchEnable  Sync pattern bits to enable for match.
+ * @param[in] linkjmp   Address of descriptor to link to expressed as a
+ *                      signed number of descriptors from "here".
+ *                      1=one descriptor forward in memory,
+ *                      0=one this descriptor,
+ *                      -1=one descriptor back in memory.
+ */
+#define LDMA_DESCRIPTOR_LINKREL_SYNC( set, clr, matchValue, matchEnable, linkjmp ) \
+{                                                                         \
+  .sync =                                                                 \
+  {                                                                       \
+    .structType   = ldmaCtrlStructTypeSync,                               \
+    .structReq    = 1,                                                    \
+    .xferCnt      = 0,                                                    \
+    .byteSwap     = 0,                                                    \
+    .blockSize    = 0,                                                    \
+    .doneIfs      = 0,                                                    \
+    .reqMode      = 0,                                                    \
+    .decLoopCnt   = 0,                                                    \
+    .ignoreSrec   = 0,                                                    \
+    .srcInc       = 0,                                                    \
+    .size         = 0,                                                    \
+    .dstInc       = 0,                                                    \
+    .srcAddrMode  = 0,                                                    \
+    .dstAddrMode  = 0,                                                    \
+    .syncSet      = (set),                                                \
+    .syncClr      = (clr),                                                \
+    .matchVal     = (matchValue),                                         \
+    .matchEn      = (matchEnable),                                        \
+    .linkMode     = ldmaLinkModeRel,                                      \
+    .link         = 1,                                                    \
+    .linkAddr     = ( linkjmp ) * 4                                       \
+  }                                                                       \
+}
+
+/*******************************************************************************
+ *****************************   PROTOTYPES   **********************************
+ ******************************************************************************/
+
+void LDMA_DeInit( void );
+void LDMA_Init( LDMA_Init_t *init );
+void LDMA_StartTransfer(  int ch,
+                          LDMA_TransferCfg_t *transfer,
+                          LDMA_Descriptor_t  *descriptor );
+void LDMA_StopTransfer( int ch );
+bool LDMA_TransferDone( int ch );
+uint32_t LDMA_TransferRemainingCount( int ch );
+
+
+/***************************************************************************//**
+ * @brief
+ *   Clear one or more pending LDMA interrupts.
+ *
+ * @param[in] flags
+ *   Pending LDMA interrupt sources to clear. Use one or more valid
+ *   interrupt flags for the LDMA module (LDMA_IFC_nnn).
+ ******************************************************************************/
+__STATIC_INLINE void LDMA_IntClear(uint32_t flags)
+{
+  LDMA->IFC = flags;
+}
+
+
+/***************************************************************************//**
+ * @brief
+ *   Disable one or more LDMA interrupts.
+ *
+ * @param[in] flags
+ *   LDMA interrupt sources to disable. Use one or more valid
+ *   interrupt flags for the LDMA module (LDMA_IEN_nnn).
+ ******************************************************************************/
+__STATIC_INLINE void LDMA_IntDisable(uint32_t flags)
+{
+  LDMA->IEN &= ~flags;
+}
+
+
+/***************************************************************************//**
+ * @brief
+ *   Enable one or more LDMA interrupts.
+ *
+ * @note
+ *   Depending on the use, a pending interrupt may already be set prior to
+ *   enabling the interrupt. Consider using LDMA_IntClear() prior to enabling
+ *   if such a pending interrupt should be ignored.
+ *
+ * @param[in] flags
+ *   LDMA interrupt sources to enable. Use one or more valid
+ *   interrupt flags for the LDMA module (LDMA_IEN_nnn).
+ ******************************************************************************/
+__STATIC_INLINE void LDMA_IntEnable(uint32_t flags)
+{
+  LDMA->IEN |= flags;
+}
+
+
+/***************************************************************************//**
+ * @brief
+ *   Get pending LDMA interrupt flags.
+ *
+ * @note
+ *   The event bits are not cleared by the use of this function.
+ *
+ * @return
+ *   LDMA interrupt sources pending. Returns one or more valid
+ *   interrupt flags for the LDMA module (LDMA_IF_nnn).
+ ******************************************************************************/
+__STATIC_INLINE uint32_t LDMA_IntGet(void)
+{
+  return LDMA->IF;
+}
+
+
+/***************************************************************************//**
+ * @brief
+ *   Get enabled and pending LDMA interrupt flags.
+ *   Useful for handling more interrupt sources in the same interrupt handler.
+ *
+ * @note
+ *   Interrupt flags are not cleared by the use of this function.
+ *
+ * @return
+ *   Pending and enabled LDMA interrupt sources
+ *   The return value is the bitwise AND of
+ *   - the enabled interrupt sources in LDMA_IEN and
+ *   - the pending interrupt flags LDMA_IF
+ ******************************************************************************/
+__STATIC_INLINE uint32_t LDMA_IntGetEnabled(void)
+{
+  uint32_t ien;
+
+  ien = LDMA->IEN;
+  return LDMA->IF & ien;
+}
+
+
+/***************************************************************************//**
+ * @brief
+ *   Set one or more pending LDMA interrupts
+ *
+ * @param[in] flags
+ *   LDMA interrupt sources to set to pending. Use one or more valid
+ *   interrupt flags for the LDMA module (LDMA_IFS_nnn).
+ ******************************************************************************/
+__STATIC_INLINE void LDMA_IntSet(uint32_t flags)
+{
+  LDMA->IFS = flags;
+}
+
+/** @} (end addtogroup LDMA) */
+/** @} (end addtogroup EM_Library) */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* defined( LDMA_PRESENT ) && ( LDMA_COUNT == 1 ) */
+#endif /* __SILICON_LABS_EM_LDMA_H__ */

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_lesense.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_lesense.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /***************************************************************************//**
  * @file em_lesense.h
  * @brief Low Energy Sensor (LESENSE) peripheral API
- * @version 3.20.12
+ * @version 4.2.1
  *******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
  *******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,9 +30,8 @@
  *
  ******************************************************************************/
 
-
-#ifndef __SILICON_LABS_EM_LESENSE_H_
-#define __SILICON_LABS_EM_LESENSE_H_
+#ifndef __SILICON_LABS_EM_LESENSE_H__
+#define __SILICON_LABS_EM_LESENSE_H__
 
 #include "em_device.h"
 
@@ -516,21 +515,21 @@
 } LESENSE_CoreCtrlDesc_TypeDef;
 
 /** Default configuration for LESENSE_CtrlDesc_TypeDef structure. */
-#define LESENSE_CORECTRL_DESC_DEFAULT                                                                 \
-  {                                                                                                   \
-    lesenseScanStartPeriodic,  /* Start new scan each time the period counter overflows. */           \
-    lesensePRSCh0,             /* Default PRS channel is selected. */                                 \
-    lesenseScanConfDirMap,     /* Direct mapping SCANCONF register usage strategy. */                 \
-    false,                     /* Don't invert ACMP0 output. */                                       \
-    false,                     /* Don't invert ACMP1 output. */                                       \
-    false,                     /* Disable dual sampling. */                                           \
-    true,                      /* Store scan result after each scan. */                               \
-    true,                      /* Overwrite result buffer register even if it is full. */             \
-    lesenseBufTrigHalf,        /* Trigger interrupt and DMA request if result buffer is half full. */ \
-    lesenseDMAWakeUpDisable,   /* Don't wake up on DMA from EM2. */                                   \
-    lesenseBiasModeDontTouch,  /* Don't touch bias configuration. */                                  \
-    true                       /* Keep LESENSE running in debug mode. */                              \
-  }
+#define LESENSE_CORECTRL_DESC_DEFAULT                                                               \
+{                                                                                                   \
+  lesenseScanStartPeriodic,  /* Start new scan each time the period counter overflows. */           \
+  lesensePRSCh0,             /* Default PRS channel is selected. */                                 \
+  lesenseScanConfDirMap,     /* Direct mapping SCANCONF register usage strategy. */                 \
+  false,                     /* Don't invert ACMP0 output. */                                       \
+  false,                     /* Don't invert ACMP1 output. */                                       \
+  false,                     /* Disable dual sampling. */                                           \
+  true,                      /* Store scan result after each scan. */                               \
+  true,                      /* Overwrite result buffer register even if it is full. */             \
+  lesenseBufTrigHalf,        /* Trigger interrupt and DMA request if result buffer is half full. */ \
+  lesenseDMAWakeUpDisable,   /* Don't wake up on DMA from EM2. */                                   \
+  lesenseBiasModeDontTouch,  /* Don't touch bias configuration. */                                  \
+  true                       /* Keep LESENSE running in debug mode. */                              \
+}
 
 
 /** LESENSE timing control descriptor structure. */
@@ -542,10 +541,10 @@
 } LESENSE_TimeCtrlDesc_TypeDef;
 
 /** Default configuration for LESENSE_TimeCtrlDesc_TypeDef structure. */
-#define LESENSE_TIMECTRL_DESC_DEFAULT     \
-  {                                       \
-    0U /* No sensor interaction delay. */ \
-  }
+#define LESENSE_TIMECTRL_DESC_DEFAULT   \
+{                                       \
+  0U /* No sensor interaction delay. */ \
+}
 
 
 /** LESENSE peripheral control descriptor structure. */
@@ -588,20 +587,20 @@
 } LESENSE_PerCtrlDesc_TypeDef;
 
 /** Default configuration for LESENSE_PerCtrl_TypeDef structure. */
-#define LESENSE_PERCTRL_DESC_DEFAULT \
-  {                                  \
-    lesenseDACIfData,          /**/  \
-    lesenseDACConvModeDisable, /**/  \
-    lesenseDACOutModeDisable,  /**/  \
-    lesenseDACIfData,          /**/  \
-    lesenseDACConvModeDisable, /**/  \
-    lesenseDACOutModeDisable,  /**/  \
-    0U,                        /**/  \
-    lesenseDACRefVdd,          /**/  \
-    lesenseACMPModeMuxThres,   /**/  \
-    lesenseACMPModeMuxThres,   /**/  \
-    lesenseWarmupModeKeepWarm, /**/  \
-  }
+#define LESENSE_PERCTRL_DESC_DEFAULT  \
+{                                     \
+  lesenseDACIfData,          /**/     \
+  lesenseDACConvModeDisable, /**/     \
+  lesenseDACOutModeDisable,  /**/     \
+  lesenseDACIfData,          /**/     \
+  lesenseDACConvModeDisable, /**/     \
+  lesenseDACOutModeDisable,  /**/     \
+  0U,                        /**/     \
+  lesenseDACRefVdd,          /**/     \
+  lesenseACMPModeMuxThres,   /**/     \
+  lesenseACMPModeMuxThres,   /**/     \
+  lesenseWarmupModeKeepWarm, /**/     \
+}
 
 
 /** LESENSE decoder control descriptor structure. */
@@ -655,22 +654,22 @@
 } LESENSE_DecCtrlDesc_TypeDef;
 
 /** Default configuration for LESENSE_PerCtrl_TypeDef structure. */
-#define LESENSE_DECCTRL_DESC_DEFAULT \
-  {                                  \
-    lesenseDecInputSensorSt, /**/    \
-    0U,                      /**/    \
-    false,                   /**/    \
-    true,                    /**/    \
-    true,                    /**/    \
-    true,                    /**/    \
-    true,                    /**/    \
-    true,                    /**/    \
-    false,                   /**/    \
-    lesensePRSCh0,           /**/    \
-    lesensePRSCh1,           /**/    \
-    lesensePRSCh2,           /**/    \
-    lesensePRSCh3,           /**/    \
-  }
+#define LESENSE_DECCTRL_DESC_DEFAULT  \
+{                                     \
+  lesenseDecInputSensorSt, /**/       \
+  0U,                      /**/       \
+  false,                   /**/       \
+  true,                    /**/       \
+  true,                    /**/       \
+  true,                    /**/       \
+  true,                    /**/       \
+  true,                    /**/       \
+  false,                   /**/       \
+  lesensePRSCh0,           /**/       \
+  lesensePRSCh1,           /**/       \
+  lesensePRSCh2,           /**/       \
+  lesensePRSCh3,           /**/       \
+}
 
 
 /** LESENSE module initialization structure. */
@@ -690,13 +689,13 @@
 } LESENSE_Init_TypeDef;
 
 /** Default configuration for LESENSE_Init_TypeDef structure. */
-#define LESENSE_INIT_DEFAULT                        \
-  {                                                 \
-    .coreCtrl = LESENSE_CORECTRL_DESC_DEFAULT, /* Default core control parameters. */ \
-    .timeCtrl = LESENSE_TIMECTRL_DESC_DEFAULT, /* Default time control parameters. */ \
-    .perCtrl  = LESENSE_PERCTRL_DESC_DEFAULT,  /* Default peripheral control parameters. */ \
-    .decCtrl  = LESENSE_DECCTRL_DESC_DEFAULT   /* Default decoder control parameters. */ \
-  }
+#define LESENSE_INIT_DEFAULT                                                              \
+{                                                                                         \
+  .coreCtrl = LESENSE_CORECTRL_DESC_DEFAULT, /* Default core control parameters. */       \
+  .timeCtrl = LESENSE_TIMECTRL_DESC_DEFAULT, /* Default time control parameters. */       \
+  .perCtrl  = LESENSE_PERCTRL_DESC_DEFAULT,  /* Default peripheral control parameters. */ \
+  .decCtrl  = LESENSE_DECCTRL_DESC_DEFAULT   /* Default decoder control parameters. */    \
+}
 
 
 /** Channel descriptor structure. */
@@ -785,51 +784,51 @@
 } LESENSE_ChAll_TypeDef;
 
 /** Default configuration for scan channel. */
-#define LESENSE_CH_CONF_DEFAULT                                                                       \
-  {                                                                                                   \
-    true,                  /* Enable scan channel. */                                                 \
-    true,                  /* Enable the assigned pin on scan channel. */                             \
-    true,                  /* Enable interrupts on channel. */                                        \
-    lesenseChPinExHigh,    /* Channel pin is high during the excitation period. */                    \
-    lesenseChPinIdleLow,   /* Channel pin is low during the idle period. */                           \
-    false,                 /* Don't use alternate excitation pins for excitation. */                  \
-    false,                 /* Disabled to shift results from this channel to the decoder register. */ \
-    false,                 /* Disabled to invert the scan result bit. */                              \
-    false,                 /* Disabled to store counter value in the result buffer. */                \
-    lesenseClkLF,          /* Use the LF clock for excitation timing. */                              \
-    lesenseClkLF,          /* Use the LF clock for sample timing. */                                  \
-    0x03U,                 /* Excitation time is set to 3(+1) excitation clock cycles. */             \
-    0x09U,                 /* Sample delay is set to 9(+1) sample clock cycles. */                    \
-    0x06U,                 /* Measure delay is set to 6 excitation clock cycles.*/                    \
-    0x00U,                 /* ACMP threshold has been set to 0. */                                    \
-    lesenseSampleModeACMP, /* ACMP output will be used in comparison. */                              \
-    lesenseSetIntNone,     /* No interrupt is generated by the channel. */                            \
-    0xFFU,                 /* Counter threshold has bee set to 0xFF. */                               \
-    lesenseCompModeLess    /* Compare mode has been set to trigger interrupt on "less". */            \
-  }
+#define LESENSE_CH_CONF_DEFAULT                                                                     \
+{                                                                                                   \
+  true,                  /* Enable scan channel. */                                                 \
+  true,                  /* Enable the assigned pin on scan channel. */                             \
+  true,                  /* Enable interrupts on channel. */                                        \
+  lesenseChPinExHigh,    /* Channel pin is high during the excitation period. */                    \
+  lesenseChPinIdleLow,   /* Channel pin is low during the idle period. */                           \
+  false,                 /* Don't use alternate excitation pins for excitation. */                  \
+  false,                 /* Disabled to shift results from this channel to the decoder register. */ \
+  false,                 /* Disabled to invert the scan result bit. */                              \
+  false,                 /* Disabled to store counter value in the result buffer. */                \
+  lesenseClkLF,          /* Use the LF clock for excitation timing. */                              \
+  lesenseClkLF,          /* Use the LF clock for sample timing. */                                  \
+  0x03U,                 /* Excitation time is set to 3(+1) excitation clock cycles. */             \
+  0x09U,                 /* Sample delay is set to 9(+1) sample clock cycles. */                    \
+  0x06U,                 /* Measure delay is set to 6 excitation clock cycles.*/                    \
+  0x00U,                 /* ACMP threshold has been set to 0. */                                    \
+  lesenseSampleModeACMP, /* ACMP output will be used in comparison. */                              \
+  lesenseSetIntNone,     /* No interrupt is generated by the channel. */                            \
+  0xFFU,                 /* Counter threshold has bee set to 0xFF. */                               \
+  lesenseCompModeLess    /* Compare mode has been set to trigger interrupt on "less". */            \
+}
 
 /** Default configuration for all sensor channels. */
-#define LESENSE_SCAN_CONF_DEFAULT                     \
-  {                                                   \
-    {                                                 \
-      LESENSE_CH_CONF_DEFAULT, /* Scan channel 0. */  \
-      LESENSE_CH_CONF_DEFAULT, /* Scan channel 1. */  \
-      LESENSE_CH_CONF_DEFAULT, /* Scan channel 2. */  \
-      LESENSE_CH_CONF_DEFAULT, /* Scan channel 3. */  \
-      LESENSE_CH_CONF_DEFAULT, /* Scan channel 4. */  \
-      LESENSE_CH_CONF_DEFAULT, /* Scan channel 5. */  \
-      LESENSE_CH_CONF_DEFAULT, /* Scan channel 6. */  \
-      LESENSE_CH_CONF_DEFAULT, /* Scan channel 7. */  \
-      LESENSE_CH_CONF_DEFAULT, /* Scan channel 8. */  \
-      LESENSE_CH_CONF_DEFAULT, /* Scan channel 9. */  \
-      LESENSE_CH_CONF_DEFAULT, /* Scan channel 10. */ \
-      LESENSE_CH_CONF_DEFAULT, /* Scan channel 11. */ \
-      LESENSE_CH_CONF_DEFAULT, /* Scan channel 12. */ \
-      LESENSE_CH_CONF_DEFAULT, /* Scan channel 13. */ \
-      LESENSE_CH_CONF_DEFAULT, /* Scan channel 14. */ \
-      LESENSE_CH_CONF_DEFAULT, /* Scan channel 15. */ \
-    }                                                 \
-  }
+#define LESENSE_SCAN_CONF_DEFAULT                   \
+{                                                   \
+  {                                                 \
+    LESENSE_CH_CONF_DEFAULT, /* Scan channel 0. */  \
+    LESENSE_CH_CONF_DEFAULT, /* Scan channel 1. */  \
+    LESENSE_CH_CONF_DEFAULT, /* Scan channel 2. */  \
+    LESENSE_CH_CONF_DEFAULT, /* Scan channel 3. */  \
+    LESENSE_CH_CONF_DEFAULT, /* Scan channel 4. */  \
+    LESENSE_CH_CONF_DEFAULT, /* Scan channel 5. */  \
+    LESENSE_CH_CONF_DEFAULT, /* Scan channel 6. */  \
+    LESENSE_CH_CONF_DEFAULT, /* Scan channel 7. */  \
+    LESENSE_CH_CONF_DEFAULT, /* Scan channel 8. */  \
+    LESENSE_CH_CONF_DEFAULT, /* Scan channel 9. */  \
+    LESENSE_CH_CONF_DEFAULT, /* Scan channel 10. */ \
+    LESENSE_CH_CONF_DEFAULT, /* Scan channel 11. */ \
+    LESENSE_CH_CONF_DEFAULT, /* Scan channel 12. */ \
+    LESENSE_CH_CONF_DEFAULT, /* Scan channel 13. */ \
+    LESENSE_CH_CONF_DEFAULT, /* Scan channel 14. */ \
+    LESENSE_CH_CONF_DEFAULT, /* Scan channel 15. */ \
+  }                                                 \
+}
 
 
 /** Alternate excitation descriptor structure. */
@@ -878,36 +877,36 @@
 
 
 /** Default configuration for alternate excitation channel. */
-#define LESENSE_ALTEX_CH_CONF_DEFAULT                                          \
-  {                                                                            \
-    true,                  /* Alternate excitation enabled.*/                  \
-    lesenseAltExPinIdleDis,/* Alternate excitation pin is disabled in idle. */ \
-    false                  /* Excite only for corresponding channel. */        \
-  }
+#define LESENSE_ALTEX_CH_CONF_DEFAULT                                        \
+{                                                                            \
+  true,                  /* Alternate excitation enabled.*/                  \
+  lesenseAltExPinIdleDis,/* Alternate excitation pin is disabled in idle. */ \
+  false                  /* Excite only for corresponding channel. */        \
+}
 
 /** Default configuration for all alternate excitation channels. */
-#define LESENSE_ALTEX_CONF_DEFAULT                                         \
-  {                                                                        \
-    lesenseAltExMapACMP,                                                   \
-    {                                                                      \
-      LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 0. */ \
-      LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 1. */ \
-      LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 2. */ \
-      LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 3. */ \
-      LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 4. */ \
-      LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 5. */ \
-      LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 6. */ \
-      LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 7. */ \
-      LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 8. */ \
-      LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 9. */ \
-      LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 10. */ \
-      LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 11. */ \
-      LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 12. */ \
-      LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 13. */ \
-      LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 14. */ \
-      LESENSE_ALTEX_CH_CONF_DEFAULT  /* Alternate excitation channel 15. */ \
-    }                                                                      \
-  }
+#define LESENSE_ALTEX_CONF_DEFAULT                                        \
+{                                                                         \
+  lesenseAltExMapACMP,                                                    \
+  {                                                                       \
+    LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 0. */  \
+    LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 1. */  \
+    LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 2. */  \
+    LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 3. */  \
+    LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 4. */  \
+    LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 5. */  \
+    LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 6. */  \
+    LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 7. */  \
+    LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 8. */  \
+    LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 9. */  \
+    LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 10. */ \
+    LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 11. */ \
+    LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 12. */ \
+    LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 13. */ \
+    LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 14. */ \
+    LESENSE_ALTEX_CH_CONF_DEFAULT  /* Alternate excitation channel 15. */ \
+  }                                                                       \
+}
 
 
 /** Decoder state condition descriptor structure. */
@@ -935,14 +934,14 @@
 } LESENSE_DecStCond_TypeDef;
 
 /** Default configuration for decoder state condition. */
-#define LESENSE_ST_CONF_DEFAULT                                          \
-  {                                                                      \
-    0x0FU,               /* Compare value set to 0x0F. */                \
-    0x00U,               /* All decoder inputs masked. */                \
-    0U,                  /* Next state is state 0. */                    \
-    lesenseTransActNone, /* No PRS action performed on compare match. */ \
-    false                /* No interrupt triggered on compare match. */  \
-  }
+#define LESENSE_ST_CONF_DEFAULT                                        \
+{                                                                      \
+  0x0FU,               /* Compare value set to 0x0F. */                \
+  0x00U,               /* All decoder inputs masked. */                \
+  0U,                  /* Next state is state 0. */                    \
+  lesenseTransActNone, /* No PRS action performed on compare match. */ \
+  false                /* No interrupt triggered on compare match. */  \
+}
 
 
 /** Decoder state x configuration structure. */
@@ -970,27 +969,27 @@
 } LESENSE_DecStAll_TypeDef;
 
 /** Default configuration for all decoder states. */
-#define LESENSE_DECODER_CONF_DEFAULT                                                                                 \
-  {  /* chain |   Descriptor A         |   Descriptor B   */ \
-    {                                                                                                                \
-      { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 0. */                            \
-      { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 1. */                            \
-      { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 2. */                            \
-      { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 3. */                            \
-      { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 4. */                            \
-      { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 5. */                            \
-      { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 6. */                            \
-      { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 7. */                            \
-      { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 8. */                            \
-      { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 9. */                            \
-      { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 10. */                           \
-      { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 11. */                           \
-      { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 12. */                           \
-      { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 13. */                           \
-      { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 14. */                           \
-      { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT } /* Decoder state 15. */                            \
-    }                                                                                                                \
-  }
+#define LESENSE_DECODER_CONF_DEFAULT                                                     \
+{  /* chain |   Descriptor A         |   Descriptor B   */                               \
+  {                                                                                      \
+    { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 0. */  \
+    { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 1. */  \
+    { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 2. */  \
+    { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 3. */  \
+    { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 4. */  \
+    { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 5. */  \
+    { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 6. */  \
+    { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 7. */  \
+    { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 8. */  \
+    { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 9. */  \
+    { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 10. */ \
+    { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 11. */ \
+    { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 12. */ \
+    { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 13. */ \
+    { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 14. */ \
+    { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }  /* Decoder state 15. */ \
+  }                                                                                      \
+}
 
 /*******************************************************************************
  *****************************   PROTOTYPES   **********************************
@@ -1035,23 +1034,6 @@
 void LESENSE_DecoderStart(void);
 void LESENSE_ResultBufferClear(void);
 
-__STATIC_INLINE void LESENSE_DecoderStop(void);
-__STATIC_INLINE uint32_t LESENSE_StatusGet(void);
-__STATIC_INLINE void LESENSE_StatusWait(uint32_t flag);
-__STATIC_INLINE uint32_t LESENSE_ChannelActiveGet(void);
-__STATIC_INLINE uint32_t LESENSE_ScanResultGet(void);
-__STATIC_INLINE uint32_t LESENSE_ScanResultDataGet(void);
-__STATIC_INLINE uint32_t LESENSE_ScanResultDataBufferGet(uint32_t idx);
-__STATIC_INLINE uint32_t LESENSE_SensorStateGet(void);
-__STATIC_INLINE void LESENSE_RAMPowerDown(void);
-
-__STATIC_INLINE void LESENSE_IntClear(uint32_t flags);
-__STATIC_INLINE void LESENSE_IntEnable(uint32_t flags);
-__STATIC_INLINE void LESENSE_IntDisable(uint32_t flags);
-__STATIC_INLINE void LESENSE_IntSet(uint32_t flags);
-__STATIC_INLINE uint32_t LESENSE_IntGet(void);
-__STATIC_INLINE uint32_t LESENSE_IntGetEnabled(void);
-
 
 /***************************************************************************//**
  * @brief
@@ -1206,7 +1188,7 @@
  *
  * @details
  *   This function shuts off the LESENSE RAM in order to decrease the leakage
- *   current of EFM32 if LESENSE is not used in your application.
+ *   current of the mcu if LESENSE is not used in your application.
  *
  * @note
  *   Warning! Once the LESENSE RAM is powered down, it cannot be powered up
@@ -1260,7 +1242,7 @@
  ******************************************************************************/
 __STATIC_INLINE void LESENSE_IntDisable(uint32_t flags)
 {
-  LESENSE->IEN &= ~(flags);
+  LESENSE->IEN &= ~flags;
 }
 
 
@@ -1336,4 +1318,4 @@
 
 #endif /* defined(LESENSE_COUNT) && (LESENSE_COUNT > 0) */
 
-#endif /* __SILICON_LABS_EM_LESENSE_H_ */
+#endif /* __SILICON_LABS_EM_LESENSE_H__ */

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_letimer.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_letimer.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /***************************************************************************//**
  * @file em_letimer.h
  * @brief Low Energy Timer (LETIMER) peripheral API
- * @version 3.20.12
+ * @version 4.2.1
  *******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
  *******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,9 +30,8 @@
  *
  ******************************************************************************/
 
-
-#ifndef __SILICON_LABS_EM_LETIMER_H_
-#define __SILICON_LABS_EM_LETIMER_H_
+#ifndef __SILICON_LABS_EM_LETIMER_H__
+#define __SILICON_LABS_EM_LETIMER_H__
 
 #include <stdbool.h>
 #include "em_device.h"
@@ -98,8 +97,10 @@
 {
   bool                       enable;         /**< Start counting when init completed. */
   bool                       debugRun;       /**< Counter shall keep running during debug halt. */
+#if defined(LETIMER_CTRL_RTCC0TEN)
   bool                       rtcComp0Enable; /**< Start counting on RTC COMP0 match. */
   bool                       rtcComp1Enable; /**< Start counting on RTC COMP1 match. */
+#endif
   bool                       comp0Top;       /**< Load COMP0 register into CNT when counter underflows. */
   bool                       bufTop;         /**< Load COMP1 into COMP0 when REP0 reaches 0. */
   uint8_t                    out0Pol;        /**< Idle value for output 0. */
@@ -110,20 +111,35 @@
 } LETIMER_Init_TypeDef;
 
 /** Default config for LETIMER init structure. */
-#define LETIMER_INIT_DEFAULT                                                    \
-  { true,               /* Enable timer when init complete. */                  \
-    false,              /* Stop counter during debug halt. */                   \
-    false,              /* Do not start counting on RTC COMP0 match. */         \
-    false,              /* Do not start counting on RTC COMP1 match. */         \
-    false,              /* Do not load COMP0 into CNT on underflow. */          \
-    false,              /* Do not load COMP1 into COMP0 when REP0 reaches 0. */ \
-    0,                  /* Idle value 0 for output 0. */                        \
-    0,                  /* Idle value 0 for output 1. */                        \
-    letimerUFOANone,    /* No action on underflow on output 0. */               \
-    letimerUFOANone,    /* No action on underflow on output 1. */               \
-    letimerRepeatFree   /* Count until stopped by SW. */                        \
-  }
-
+#if defined(LETIMER_CTRL_RTCC0TEN)
+#define LETIMER_INIT_DEFAULT                                                  \
+{                                                                             \
+  true,               /* Enable timer when init complete. */                  \
+  false,              /* Stop counter during debug halt. */                   \
+  false,              /* Do not start counting on RTC COMP0 match. */         \
+  false,              /* Do not start counting on RTC COMP1 match. */         \
+  false,              /* Do not load COMP0 into CNT on underflow. */          \
+  false,              /* Do not load COMP1 into COMP0 when REP0 reaches 0. */ \
+  0,                  /* Idle value 0 for output 0. */                        \
+  0,                  /* Idle value 0 for output 1. */                        \
+  letimerUFOANone,    /* No action on underflow on output 0. */               \
+  letimerUFOANone,    /* No action on underflow on output 1. */               \
+  letimerRepeatFree   /* Count until stopped by SW. */                        \
+}
+#else
+#define LETIMER_INIT_DEFAULT                                                  \
+{                                                                             \
+  true,               /* Enable timer when init complete. */                  \
+  false,              /* Stop counter during debug halt. */                   \
+  false,              /* Do not load COMP0 into CNT on underflow. */          \
+  false,              /* Do not load COMP1 into COMP0 when REP0 reaches 0. */ \
+  0,                  /* Idle value 0 for output 0. */                        \
+  0,                  /* Idle value 0 for output 1. */                        \
+  letimerUFOANone,    /* No action on underflow on output 0. */               \
+  letimerUFOANone,    /* No action on underflow on output 1. */               \
+  letimerRepeatFree   /* Count until stopped by SW. */                        \
+}
+#endif
 
 /*******************************************************************************
  *****************************   PROTOTYPES   **********************************
@@ -152,7 +168,9 @@
 
 
 void LETIMER_Enable(LETIMER_TypeDef *letimer, bool enable);
+#if defined(_LETIMER_FREEZE_MASK)
 void LETIMER_FreezeEnable(LETIMER_TypeDef *letimer, bool enable);
+#endif
 void LETIMER_Init(LETIMER_TypeDef *letimer, const LETIMER_Init_TypeDef *init);
 
 
@@ -187,7 +205,7 @@
  ******************************************************************************/
 __STATIC_INLINE void LETIMER_IntDisable(LETIMER_TypeDef *letimer, uint32_t flags)
 {
-  letimer->IEN &= ~(flags);
+  letimer->IEN &= ~flags;
 }
 
 
@@ -229,7 +247,42 @@
  ******************************************************************************/
 __STATIC_INLINE uint32_t LETIMER_IntGet(LETIMER_TypeDef *letimer)
 {
-  return(letimer->IF);
+  return letimer->IF;
+}
+
+
+/***************************************************************************//**
+ * @brief
+ *   Get enabled and pending LETIMER interrupt flags.
+ *
+ * @details
+ *   Useful for handling more interrupt sources in the same interrupt handler.
+ *
+ * @note
+ *   The event bits are not cleared by the use of this function.
+ *
+ * @param[in] letimer
+ *   Pointer to LETIMER peripheral register block.
+ *
+ * @return
+ *   Pending and enabled LETIMER interrupt sources.
+ *   The return value is the bitwise AND combination of
+ *   - the OR combination of enabled interrupt sources in LETIMER_IEN_nnn
+ *   register (LETIMER_IEN_nnn) and
+ *   - the OR combination of valid interrupt flags of the LETIMER module
+ *   (LETIMER_IF_nnn).
+ ******************************************************************************/
+__STATIC_INLINE uint32_t LETIMER_IntGetEnabled(LETIMER_TypeDef *letimer)
+{
+  uint32_t ien;
+
+
+  /* Store flags in temporary variable in order to define explicit order
+   * of volatile accesses. */
+  ien = letimer->IEN;
+
+  /* Bitwise AND of pending and enabled interrupts */
+  return letimer->IF & ien;
 }
 
 
@@ -249,6 +302,7 @@
   letimer->IFS = flags;
 }
 
+
 uint32_t LETIMER_RepeatGet(LETIMER_TypeDef *letimer, unsigned int rep);
 void LETIMER_RepeatSet(LETIMER_TypeDef *letimer,
                        unsigned int rep,
@@ -264,5 +318,4 @@
 #endif
 
 #endif /* defined(LETIMER_COUNT) && (LETIMER_COUNT > 0) */
-
-#endif /* __SILICON_LABS_EM_LETIMER_H_ */
+#endif /* __SILICON_LABS_EM_LETIMER_H__ */

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_leuart.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_leuart.h	Fri Jan 15 07:45:16 2016 +0000
@@ -2,10 +2,10 @@
  * @file em_leuart.h
  * @brief Low Energy Universal Asynchronous Receiver/Transmitter (LEUART)
  *   peripheral API
- * @version 3.20.12
+ * @version 4.2.1
  *******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
  *******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -31,9 +31,8 @@
  *
  ******************************************************************************/
 
-
-#ifndef __SILICON_LABS_EM_LEUART_H_
-#define __SILICON_LABS_EM_LEUART_H_
+#ifndef __SILICON_LABS_EM_LEUART_H__
+#define __SILICON_LABS_EM_LEUART_H__
 
 #include "em_device.h"
 #if defined(LEUART_COUNT) && (LEUART_COUNT > 0)
@@ -130,14 +129,15 @@
 } LEUART_Init_TypeDef;
 
 /** Default config for LEUART init structure. */
-#define LEUART_INIT_DEFAULT                                                                   \
-  { leuartEnable,      /* Enable RX/TX when init completed. */                                \
-    0,                 /* Use current configured reference clock for configuring baudrate. */ \
-    9600,              /* 9600 bits/s. */                                                     \
-    leuartDatabits8,   /* 8 databits. */                                                      \
-    leuartNoParity,    /* No parity. */                                                       \
-    leuartStopbits1    /* 1 stopbit. */                                                       \
-  }
+#define LEUART_INIT_DEFAULT                                                                 \
+{                                                                                           \
+  leuartEnable,      /* Enable RX/TX when init completed. */                                \
+  0,                 /* Use current configured reference clock for configuring baudrate. */ \
+  9600,              /* 9600 bits/s. */                                                     \
+  leuartDatabits8,   /* 8 databits. */                                                      \
+  leuartNoParity,    /* No parity. */                                                       \
+  leuartStopbits1    /* 1 stopbit. */                                                       \
+}
 
 
 /*******************************************************************************
@@ -185,7 +185,7 @@
  ******************************************************************************/
 __STATIC_INLINE void LEUART_IntDisable(LEUART_TypeDef *leuart, uint32_t flags)
 {
-  leuart->IEN &= ~(flags);
+  leuart->IEN &= ~flags;
 }
 
 
@@ -227,7 +227,39 @@
  ******************************************************************************/
 __STATIC_INLINE uint32_t LEUART_IntGet(LEUART_TypeDef *leuart)
 {
-  return(leuart->IF);
+  return leuart->IF;
+}
+
+
+/***************************************************************************//**
+ * @brief
+ *   Get enabled and pending LEUART interrupt flags.
+ *   Useful for handling more interrupt sources in the same interrupt handler.
+ *
+ * @param[in] leuart
+ *   Pointer to LEUART peripheral register block.
+ *
+ * @note
+ *   Interrupt flags are not cleared by the use of this function.
+ *
+ * @return
+ *   Pending and enabled LEUART interrupt sources.
+ *   The return value is the bitwise AND combination of
+ *   - the OR combination of enabled interrupt sources in LEUARTx_IEN_nnn
+ *     register (LEUARTx_IEN_nnn) and
+ *   - the OR combination of valid interrupt flags of the LEUART module
+ *     (LEUARTx_IF_nnn).
+ ******************************************************************************/
+__STATIC_INLINE uint32_t LEUART_IntGetEnabled(LEUART_TypeDef *leuart)
+{
+  uint32_t tmp;
+
+  /* Store LEUARTx->IEN in temporary variable in order to define explicit order
+   * of volatile accesses. */
+  tmp = leuart->IEN;
+
+  /* Bitwise AND of pending and enabled interrupts */
+  return leuart->IF & tmp;
 }
 
 
@@ -247,21 +279,23 @@
   leuart->IFS = flags;
 }
 
+
+/***************************************************************************//**
+ * @brief
+ *   Get LEUART STATUS register.
+ *
+ * @param[in] leuart
+ *   Pointer to LEUART peripheral register block.
+ *
+ * @return
+ *  STATUS register value.
+ *
+ ******************************************************************************/
 __STATIC_INLINE uint32_t LEUART_StatusGet(LEUART_TypeDef *leuart)
 {
   return leuart->STATUS;
 }
 
-__STATIC_INLINE uint8_t LEUART_RxDataGet(LEUART_TypeDef *leuart)
-{
-  return (uint8_t)(leuart->RXDATA & 0xFF);
-}
-
-__STATIC_INLINE uint32_t LEUART_IntGetEnabled(LEUART_TypeDef *leuart)
-{
-  return(leuart->IF & leuart->IEN);
-}
-
 void LEUART_Reset(LEUART_TypeDef *leuart);
 uint8_t LEUART_Rx(LEUART_TypeDef *leuart);
 uint16_t LEUART_RxExt(LEUART_TypeDef *leuart);
@@ -269,6 +303,74 @@
 void LEUART_TxExt(LEUART_TypeDef *leuart, uint16_t data);
 
 
+/***************************************************************************//**
+ * @brief
+ *   Receive one 8 bit frame, (or part of a 9 bit frame).
+ *
+ * @details
+ *   This function is used to quickly receive one 8 bit frame by reading the
+ *   RXDATA register directly, without checking the STATUS register for the
+ *   RXDATAV flag. This can be useful from the RXDATAV interrupt handler,
+ *   i.e. waiting is superfluous, in order to quickly read the received data.
+ *   Please refer to @ref LEUART_RxDataXGet() for reception of 9 bit frames.
+ *
+ * @note
+ *   Since this function does not check whether the RXDATA register actually
+ *   holds valid data, it should only be used in situations when it is certain
+ *   that there is valid data, ensured by some external program routine, e.g.
+ *   like when handling an RXDATAV interrupt. The @ref LEUART_Rx() is normally a
+ *   better choice if the validity of the RXDATA register is not certain.
+ *
+ * @note
+ *   Notice that possible parity/stop bits are not
+ *   considered part of specified frame bit length.
+ *
+ * @param[in] leuart
+ *   Pointer to LEUART peripheral register block.
+ *
+ * @return
+ *   Data received.
+ ******************************************************************************/
+__STATIC_INLINE uint8_t LEUART_RxDataGet(LEUART_TypeDef *leuart)
+{
+  return (uint8_t)leuart->RXDATA;
+}
+
+
+/***************************************************************************//**
+ * @brief
+ *   Receive one 8-9 bit frame, with extended information.
+ *
+ * @details
+ *   This function is used to quickly receive one 8-9 bit frame with extended
+ *   information by reading the RXDATAX register directly, without checking the
+ *   STATUS register for the RXDATAV flag. This can be useful from the RXDATAV
+ *   interrupt handler, i.e. waiting is superfluous, in order to quickly read
+ *   the received data.
+ *
+ * @note
+ *   Since this function does not check whether the RXDATAX register actually
+ *   holds valid data, it should only be used in situations when it is certain
+ *   that there is valid data, ensured by some external program routine, e.g.
+ *   like when handling an RXDATAV interrupt. The @ref LEUART_RxExt() is normally
+ *   a better choice if the validity of the RXDATAX register is not certain.
+ *
+ * @note
+ *   Notice that possible parity/stop bits are not
+ *   considered part of specified frame bit length.
+ *
+ * @param[in] leuart
+ *   Pointer to LEUART peripheral register block.
+ *
+ * @return
+ *   Data received.
+ ******************************************************************************/
+__STATIC_INLINE uint16_t LEUART_RxDataXGet(LEUART_TypeDef *leuart)
+{
+  return (uint16_t)leuart->RXDATAX;
+}
+
+
 /** @} (end addtogroup LEUART) */
 /** @} (end addtogroup EM_Library) */
 
@@ -277,5 +379,4 @@
 #endif
 
 #endif /* defined(LEUART_COUNT) && (LEUART_COUNT > 0) */
-
-#endif /* __SILICON_LABS_EM_LEUART_H_ */
+#endif /* __SILICON_LABS_EM_LEUART_H__ */

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_mpu.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_mpu.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /***************************************************************************//**
  * @file em_mpu.h
  * @brief Memory protection unit (MPU) peripheral API
- * @version 3.20.12
+ * @version 4.2.1
  *******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
  *******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,9 +30,8 @@
  *
  ******************************************************************************/
 
-
-#ifndef __SILICON_LABS_EM_MPU_H_
-#define __SILICON_LABS_EM_MPU_H_
+#ifndef __SILICON_LABS_EM_MPU_H__
+#define __SILICON_LABS_EM_MPU_H__
 
 #include "em_device.h"
 
@@ -139,54 +138,54 @@
 } MPU_RegionInit_TypeDef;
 
 /** Default configuration of MPU region init structure for flash memory.     */
-#define MPU_INIT_FLASH_DEFAULT                                  \
-  {                                                             \
-    true,                   /* Enable MPU region.            */ \
-    0,                      /* MPU Region number.            */ \
-    FLASH_MEM_BASE,         /* Flash base address.           */ \
-    mpuRegionSize1Mb,       /* Size - Set to max. */ \
-    mpuRegionApFullAccess,  /* Access permissions.           */ \
-    false,                  /* Execution allowed.            */ \
-    false,                  /* Not shareable.                */ \
-    true,                   /* Cacheable.                    */ \
-    false,                  /* Not bufferable.               */ \
-    0,                      /* No subregions.                */ \
-    0                       /* No TEX attributes.            */ \
-  }
+#define MPU_INIT_FLASH_DEFAULT                                \
+{                                                             \
+  true,                   /* Enable MPU region.            */ \
+  0,                      /* MPU Region number.            */ \
+  FLASH_MEM_BASE,         /* Flash base address.           */ \
+  mpuRegionSize1Mb,       /* Size - Set to max. */            \
+  mpuRegionApFullAccess,  /* Access permissions.           */ \
+  false,                  /* Execution allowed.            */ \
+  false,                  /* Not shareable.                */ \
+  true,                   /* Cacheable.                    */ \
+  false,                  /* Not bufferable.               */ \
+  0,                      /* No subregions.                */ \
+  0                       /* No TEX attributes.            */ \
+}
 
 
 /** Default configuration of MPU region init structure for sram memory.      */
-#define MPU_INIT_SRAM_DEFAULT                                   \
-  {                                                             \
-    true,                   /* Enable MPU region.            */ \
-    1,                      /* MPU Region number.            */ \
-    RAM_MEM_BASE,           /* SRAM base address.            */ \
-    mpuRegionSize128Kb,     /* Size - Set to max. */ \
-    mpuRegionApFullAccess,  /* Access permissions.           */ \
-    false,                  /* Execution allowed.            */ \
-    true,                   /* Shareable.                    */ \
-    true,                   /* Cacheable.                    */ \
-    false,                  /* Not bufferable.               */ \
-    0,                      /* No subregions.                */ \
-    0                       /* No TEX attributes.            */ \
-  }
+#define MPU_INIT_SRAM_DEFAULT                                 \
+{                                                             \
+  true,                   /* Enable MPU region.            */ \
+  1,                      /* MPU Region number.            */ \
+  RAM_MEM_BASE,           /* SRAM base address.            */ \
+  mpuRegionSize128Kb,     /* Size - Set to max. */            \
+  mpuRegionApFullAccess,  /* Access permissions.           */ \
+  false,                  /* Execution allowed.            */ \
+  true,                   /* Shareable.                    */ \
+  true,                   /* Cacheable.                    */ \
+  false,                  /* Not bufferable.               */ \
+  0,                      /* No subregions.                */ \
+  0                       /* No TEX attributes.            */ \
+}
 
 
 /** Default configuration of MPU region init structure for onchip peripherals.*/
-#define MPU_INIT_PERIPHERAL_DEFAULT                             \
-  {                                                             \
-    true,                   /* Enable MPU region.            */ \
-    0,                      /* MPU Region number.            */ \
-    0,                      /* Region base address.          */ \
-    mpuRegionSize32b,       /* Size - Set to minimum         */ \
-    mpuRegionApFullAccess,  /* Access permissions.           */ \
-    true,                   /* Execution not allowed.        */ \
-    true,                   /* Shareable.                    */ \
-    false,                  /* Not cacheable.                */ \
-    true,                   /* Bufferable.                   */ \
-    0,                      /* No subregions.                */ \
-    0                       /* No TEX attributes.            */ \
-  }
+#define MPU_INIT_PERIPHERAL_DEFAULT                           \
+{                                                             \
+  true,                   /* Enable MPU region.            */ \
+  0,                      /* MPU Region number.            */ \
+  0,                      /* Region base address.          */ \
+  mpuRegionSize32b,       /* Size - Set to minimum         */ \
+  mpuRegionApFullAccess,  /* Access permissions.           */ \
+  true,                   /* Execution not allowed.        */ \
+  true,                   /* Shareable.                    */ \
+  false,                  /* Not cacheable.                */ \
+  true,                   /* Bufferable.                   */ \
+  0,                      /* No subregions.                */ \
+  0                       /* No TEX attributes.            */ \
+}
 
 
 /*******************************************************************************
@@ -221,9 +220,9 @@
  ******************************************************************************/
 __STATIC_INLINE void MPU_Enable(uint32_t flags)
 {
-  EFM_ASSERT(!(flags & ~(MPU_CTRL_PRIVDEFENA_Msk |
-                         MPU_CTRL_HFNMIENA_Msk |
-                         MPU_CTRL_ENABLE_Msk)));
+  EFM_ASSERT(!(flags & ~(MPU_CTRL_PRIVDEFENA_Msk
+                         | MPU_CTRL_HFNMIENA_Msk
+                         | MPU_CTRL_ENABLE_Msk)));
 
   MPU->CTRL   = flags | MPU_CTRL_ENABLE_Msk;     /* Enable the MPU */
   SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;       /* Enable fault exceptions */
@@ -239,4 +238,4 @@
 
 #endif /* defined(__MPU_PRESENT) && (__MPU_PRESENT == 1) */
 
-#endif /* __SILICON_LABS_EM_MPU_H_ */
+#endif /* __SILICON_LABS_EM_MPU_H__ */

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_msc.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_msc.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /***************************************************************************//**
  * @file em_msc.h
  * @brief Flash controller module (MSC) peripheral API
- * @version 3.20.12
+ * @version 4.2.1
  *******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
  *******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -38,7 +38,7 @@
 
 #include <stdint.h>
 #include <stdbool.h>
-#include "em_bitband.h"
+#include "em_bus.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -71,6 +71,24 @@
  */
 #define MSC_PROGRAM_TIMEOUT    10000000ul
 
+/**
+ * @brief
+ *    By compiling with the define EM_MSC_RUN_FROM_FLASH the Flash
+ *    controller (MSC) peripheral will remain in and execute from flash.
+ *    This is useful for targets that don't want to allocate RAM space to
+ *    hold the flash functions.  Without this define the MSC peripheral
+ *    functions will be copied into and run out of RAM.
+ * @note
+ *    This define is commented out by default so the MSC controller API
+ *    will run from RAM by default.
+ *
+ */
+#if defined( DOXY_DOC_ONLY )
+#define EM_MSC_RUN_FROM_FLASH
+#else
+//#define EM_MSC_RUN_FROM_FLASH
+#endif
+
 /*******************************************************************************
  *************************   TYPEDEFS   ****************************************
  ******************************************************************************/
@@ -88,7 +106,8 @@
 
 #if defined( _MSC_READCTRL_BUSSTRATEGY_MASK )
 /** Strategy for prioritized bus access */
-typedef enum {
+typedef enum
+{
   mscBusStrategyCPU = MSC_READCTRL_BUSSTRATEGY_CPU,       /**< Prioritize CPU bus accesses */
   mscBusStrategyDMA = MSC_READCTRL_BUSSTRATEGY_DMA,       /**< Prioritize DMA bus accesses */
   mscBusStrategyDMAEM1 = MSC_READCTRL_BUSSTRATEGY_DMAEM1, /**< Prioritize DMAEM1 for bus accesses */
@@ -96,6 +115,28 @@
 } MSC_BusStrategy_Typedef;
 #endif
 
+/** Code execution configuration */
+typedef struct
+{
+  bool scbtEn;          /**< Enable Suppressed Conditional Branch Target Prefetch */
+  bool prefetchEn;      /**< Enable MSC prefetching */
+  bool ifcDis;          /**< Disable instruction cache */
+  bool aiDis;           /**< Disable automatic cache invalidation on write or erase */
+  bool iccDis;          /**< Disable automatic caching of fetches in interrupt context */
+  bool useHprot;        /**< Use ahb_hprot to determine if the instruction is cacheable or not */
+} MSC_ExecConfig_TypeDef;
+
+/** Default MSC ExecConfig initialization */
+#define MSC_EXECCONFIG_DEFAULT  \
+{                               \
+  false,                        \
+  true,                         \
+  false,                        \
+  false,                        \
+  false,                        \
+  false,                        \
+}
+
 /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
 /* Legacy type names */
 #define mscBusStrategy_Typedef MSC_BusStrategy_Typedef
@@ -108,6 +149,9 @@
 
 void MSC_Init(void);
 void MSC_Deinit(void);
+#if !defined( _EFM32_GECKO_FAMILY )
+void MSC_ExecConfigSet(MSC_ExecConfig_TypeDef *execConfig);
+#endif
 
 /***************************************************************************//**
  * @brief
@@ -328,7 +372,7 @@
  ******************************************************************************/
 __STATIC_INLINE void MSC_EnableCache(bool enable)
 {
-  BITBAND_Peripheral(&(MSC->READCTRL), _MSC_READCTRL_IFCDIS_SHIFT, ~enable);
+  BUS_RegBitWrite(&(MSC->READCTRL), _MSC_READCTRL_IFCDIS_SHIFT, !enable);
 }
 
 
@@ -341,7 +385,7 @@
  ******************************************************************************/
 __STATIC_INLINE void MSC_EnableCacheIRQs(bool enable)
 {
-  BITBAND_Peripheral(&(MSC->READCTRL), _MSC_READCTRL_ICCDIS_SHIFT, ~enable);
+  BUS_RegBitWrite(&(MSC->READCTRL), _MSC_READCTRL_ICCDIS_SHIFT, !enable);
 }
 #endif
 
@@ -354,7 +398,7 @@
  ******************************************************************************/
 __STATIC_INLINE void MSC_EnableAutoCacheFlush(bool enable)
 {
-  BITBAND_Peripheral(&(MSC->READCTRL), _MSC_READCTRL_AIDIS_SHIFT, ~enable);
+  BUS_RegBitWrite(&(MSC->READCTRL), _MSC_READCTRL_AIDIS_SHIFT, !enable);
 }
 #endif /* defined( MSC_IF_CHOF ) && defined( MSC_IF_CMOF ) */
 
@@ -372,57 +416,44 @@
 }
 #endif
 
-
-#ifdef __CC_ARM  /* MDK-ARM compiler */
-MSC_Status_TypeDef MSC_WriteWord(uint32_t *address, void const *data, uint32_t numBytes);
-#if !defined( _EFM32_GECKO_FAMILY )
-MSC_Status_TypeDef MSC_WriteWordFast(uint32_t *address, void const *data, uint32_t numBytes);
+#if defined(EM_MSC_RUN_FROM_FLASH)
+#define MSC_FUNC_PREFIX
+#define MSC_FUNC_POSTFIX
+#elif defined(__CC_ARM)
+#define MSC_FUNC_PREFIX
+#define MSC_FUNC_POSTFIX
+#elif defined(__ICCARM__)
+#define MSC_FUNC_PREFIX   __ramfunc
+#define MSC_FUNC_POSTFIX
+#elif defined(__GNUC__) && defined(__CROSSWORKS_ARM)
+#define MSC_FUNC_PREFIX
+#define MSC_FUNC_POSTFIX  __attribute__ ((section(".fast")))
+#elif defined(__GNUC__)
+#define MSC_FUNC_PREFIX
+#define MSC_FUNC_POSTFIX  __attribute__ ((section(".ram")))
 #endif
-MSC_Status_TypeDef MSC_ErasePage(uint32_t *startAddress);
 
-#if defined( _MSC_MASSLOCK_MASK )
-MSC_Status_TypeDef MSC_MassErase(void);
-#endif
-#endif /* __CC_ARM */
+
+MSC_FUNC_PREFIX MSC_Status_TypeDef
+  MSC_WriteWord(uint32_t *address,
+                void const *data,
+                uint32_t numBytes) MSC_FUNC_POSTFIX;
 
-#ifdef __ICCARM__ /* IAR compiler */
-__ramfunc MSC_Status_TypeDef MSC_WriteWord(uint32_t *address, void const *data, uint32_t numBytes);
 #if !defined( _EFM32_GECKO_FAMILY )
-__ramfunc MSC_Status_TypeDef MSC_WriteWordFast(uint32_t *address, void const *data, uint32_t numBytes);
+MSC_FUNC_PREFIX MSC_Status_TypeDef
+  MSC_WriteWordFast(uint32_t *address,
+                    void const *data,
+                    uint32_t numBytes) MSC_FUNC_POSTFIX;
+
 #endif
-__ramfunc MSC_Status_TypeDef MSC_ErasePage(uint32_t *startAddress);
+
+MSC_FUNC_PREFIX MSC_Status_TypeDef
+  MSC_ErasePage(uint32_t *startAddress) MSC_FUNC_POSTFIX;
 
 #if defined( _MSC_MASSLOCK_MASK )
-__ramfunc MSC_Status_TypeDef MSC_MassErase(void);
-#endif
-#endif /* __ICCARM__ */
-
-#ifdef __GNUC__  /* GCC based compilers */
-#ifdef __CROSSWORKS_ARM  /* Rowley Crossworks (GCC based) */
-MSC_Status_TypeDef MSC_WriteWord(uint32_t *address, void const *data, uint32_t numBytes) __attribute__ ((section(".fast")));
-#if !defined( _EFM32_GECKO_FAMILY )
-MSC_Status_TypeDef MSC_WriteWordFast(uint32_t *address, void const *data, uint32_t numBytes) __attribute__ ((section(".fast")));
-#endif
-MSC_Status_TypeDef MSC_ErasePage(uint32_t *startAddress) __attribute__ ((section(".fast")));
-
-#if defined( _MSC_MASSLOCK_MASK )
-MSC_Status_TypeDef MSC_MassErase(void) __attribute__ ((section(".fast")));
+MSC_FUNC_PREFIX MSC_Status_TypeDef MSC_MassErase(void) MSC_FUNC_POSTFIX;
 #endif
 
-#else /* GCC */
-MSC_Status_TypeDef MSC_WriteWord(uint32_t *address, void const *data, uint32_t numBytes) __attribute__ ((section(".ram")));
-#if !defined( _EFM32_GECKO_FAMILY )
-MSC_Status_TypeDef MSC_WriteWordFast(uint32_t *address, void const *data, uint32_t numBytes) __attribute__ ((section(".ram")));
-#endif
-MSC_Status_TypeDef MSC_ErasePage(uint32_t *startAddress) __attribute__ ((section(".ram")));
-
-#if defined( _MSC_MASSLOCK_MASK )
-MSC_Status_TypeDef MSC_MassErase(void) __attribute__ ((section(".ram")));
-#endif
-
-#endif /* __GNUC__ */
-#endif /* __CROSSWORKS_ARM */
-
 /** @} (end addtogroup MSC) */
 /** @} (end addtogroup EM_Library) */
 

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_opamp.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_opamp.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file em_opamp.h
  * @brief Operational Amplifier (OPAMP) peripheral API
- * @version 3.20.12
+ * @version 4.2.1
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
  *******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,9 +30,8 @@
  *
  ******************************************************************************/
 
-
-#ifndef __SILICON_LABS_EM_OPAMP_H_
-#define __SILICON_LABS_EM_OPAMP_H_
+#ifndef __SILICON_LABS_EM_OPAMP_H__
+#define __SILICON_LABS_EM_OPAMP_H__
 
 #include "em_device.h"
 #if defined(OPAMP_PRESENT) && (OPAMP_COUNT == 1)
@@ -178,379 +177,379 @@
   uint32_t               offset;              /**< Opamp offset value when @ref defaultOffset is false.*/
 } OPAMP_Init_TypeDef;
 
-/** Configuration of OPA0/1 in unity gain voltage follower mode.       */
-#define OPA_INIT_UNITY_GAIN                                                       \
-  {                                                                               \
-    opaNegSelUnityGain,             /* Unity gain.                             */ \
-    opaPosSelPosPad,                /* Pos input from pad.                     */ \
-    opaOutModeMain,                 /* Main output enabled.                    */ \
-    opaResSelDefault,               /* Resistor ladder is not used.            */ \
-    opaResInMuxDisable,             /* Resistor ladder disabled.               */ \
-    0,                              /* No alternate outputs enabled.           */ \
-    _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting.             */       \
-    _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting.        */       \
-    false,                          /* No low pass filter on pos pad.          */ \
-    false,                          /* No low pass filter on neg pad.          */ \
-    false,                          /* No nextout output enabled.              */ \
-    false,                          /* Neg pad disabled.                       */ \
-    true,                           /* Pos pad enabled, used as signal input.  */ \
-    false,                          /* No shorting of inputs.                  */ \
-    false,                          /* Rail-to-rail input enabled.             */ \
-    true,                           /* Use factory calibrated opamp offset.    */ \
-    0                               /* Opamp offset value (not used).          */ \
-  }
+/** Configuration of OPA0/1 in unity gain voltage follower mode. */
+#define OPA_INIT_UNITY_GAIN                                                     \
+{                                                                               \
+  opaNegSelUnityGain,             /* Unity gain.                             */ \
+  opaPosSelPosPad,                /* Pos input from pad.                     */ \
+  opaOutModeMain,                 /* Main output enabled.                    */ \
+  opaResSelDefault,               /* Resistor ladder is not used.            */ \
+  opaResInMuxDisable,             /* Resistor ladder disabled.               */ \
+  0,                              /* No alternate outputs enabled.           */ \
+  _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting.                   */ \
+  _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting.              */ \
+  false,                          /* No low pass filter on pos pad.          */ \
+  false,                          /* No low pass filter on neg pad.          */ \
+  false,                          /* No nextout output enabled.              */ \
+  false,                          /* Neg pad disabled.                       */ \
+  true,                           /* Pos pad enabled, used as signal input.  */ \
+  false,                          /* No shorting of inputs.                  */ \
+  false,                          /* Rail-to-rail input enabled.             */ \
+  true,                           /* Use factory calibrated opamp offset.    */ \
+  0                               /* Opamp offset value (not used).          */ \
+}
 
-/** Configuration of OPA2 in unity gain voltage follower mode.         */
-#define OPA_INIT_UNITY_GAIN_OPA2                                                  \
-  {                                                                               \
-    opaNegSelUnityGain,             /* Unity gain.                             */ \
-    opaPosSelPosPad,                /* Pos input from pad.                     */ \
-    opaOutModeMain,                 /* Main output enabled.                    */ \
-    opaResSelDefault,               /* Resistor ladder is not used.            */ \
-    opaResInMuxDisable,             /* Resistor ladder disabled.               */ \
-    DAC_OPA0MUX_OUTPEN_OUT0,        /* Alternate output 0 enabled.             */ \
-    _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting.             */       \
-    _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting.        */       \
-    false,                          /* No low pass filter on pos pad.          */ \
-    false,                          /* No low pass filter on neg pad.          */ \
-    false,                          /* No nextout output enabled.              */ \
-    false,                          /* Neg pad disabled.                       */ \
-    true,                           /* Pos pad enabled, used as signal input.  */ \
-    false,                          /* No shorting of inputs.                  */ \
-    false,                          /* Rail-to-rail input enabled.             */ \
-    true,                           /* Use factory calibrated opamp offset.    */ \
-    0                               /* Opamp offset value (not used).          */ \
-  }
+/** Configuration of OPA2 in unity gain voltage follower mode. */
+#define OPA_INIT_UNITY_GAIN_OPA2                                                \
+{                                                                               \
+  opaNegSelUnityGain,             /* Unity gain.                             */ \
+  opaPosSelPosPad,                /* Pos input from pad.                     */ \
+  opaOutModeMain,                 /* Main output enabled.                    */ \
+  opaResSelDefault,               /* Resistor ladder is not used.            */ \
+  opaResInMuxDisable,             /* Resistor ladder disabled.               */ \
+  DAC_OPA0MUX_OUTPEN_OUT0,        /* Alternate output 0 enabled.             */ \
+  _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting.                   */ \
+  _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting.              */ \
+  false,                          /* No low pass filter on pos pad.          */ \
+  false,                          /* No low pass filter on neg pad.          */ \
+  false,                          /* No nextout output enabled.              */ \
+  false,                          /* Neg pad disabled.                       */ \
+  true,                           /* Pos pad enabled, used as signal input.  */ \
+  false,                          /* No shorting of inputs.                  */ \
+  false,                          /* Rail-to-rail input enabled.             */ \
+  true,                           /* Use factory calibrated opamp offset.    */ \
+  0                               /* Opamp offset value (not used).          */ \
+}
 
 /** Configuration of OPA0/1 in non-inverting amplifier mode.           */
-#define OPA_INIT_NON_INVERTING                                                    \
-  {                                                                               \
-    opaNegSelResTap,                /* Neg input from resistor ladder tap.     */ \
-    opaPosSelPosPad,                /* Pos input from pad.                     */ \
-    opaOutModeMain,                 /* Main output enabled.                    */ \
-    opaResSelR2eq0_33R1,            /* R2 = 1/3 R1                             */ \
-    opaResInMuxNegPad,              /* Resistor ladder input from neg pad.     */ \
-    0,                              /* No alternate outputs enabled.           */ \
-    _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting.             */       \
-    _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting.        */       \
-    false,                          /* No low pass filter on pos pad.          */ \
-    false,                          /* No low pass filter on neg pad.          */ \
-    false,                          /* No nextout output enabled.              */ \
-    true,                           /* Neg pad enabled, used as signal ground. */ \
-    true,                           /* Pos pad enabled, used as signal input.  */ \
-    false,                          /* No shorting of inputs.                  */ \
-    false,                          /* Rail-to-rail input enabled.             */ \
-    true,                           /* Use factory calibrated opamp offset.    */ \
-    0                               /* Opamp offset value (not used).          */ \
-  }
+#define OPA_INIT_NON_INVERTING                                                  \
+{                                                                               \
+  opaNegSelResTap,                /* Neg input from resistor ladder tap.     */ \
+  opaPosSelPosPad,                /* Pos input from pad.                     */ \
+  opaOutModeMain,                 /* Main output enabled.                    */ \
+  opaResSelR2eq0_33R1,            /* R2 = 1/3 R1                             */ \
+  opaResInMuxNegPad,              /* Resistor ladder input from neg pad.     */ \
+  0,                              /* No alternate outputs enabled.           */ \
+  _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting.                   */ \
+  _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting.              */ \
+  false,                          /* No low pass filter on pos pad.          */ \
+  false,                          /* No low pass filter on neg pad.          */ \
+  false,                          /* No nextout output enabled.              */ \
+  true,                           /* Neg pad enabled, used as signal ground. */ \
+  true,                           /* Pos pad enabled, used as signal input.  */ \
+  false,                          /* No shorting of inputs.                  */ \
+  false,                          /* Rail-to-rail input enabled.             */ \
+  true,                           /* Use factory calibrated opamp offset.    */ \
+  0                               /* Opamp offset value (not used).          */ \
+}
 
-/** Configuration of OPA2 in non-inverting amplifier mode.             */
-#define OPA_INIT_NON_INVERTING_OPA2                                               \
-  {                                                                               \
-    opaNegSelResTap,                /* Neg input from resistor ladder tap.     */ \
-    opaPosSelPosPad,                /* Pos input from pad.                     */ \
-    opaOutModeMain,                 /* Main output enabled.                    */ \
-    opaResSelR2eq0_33R1,            /* R2 = 1/3 R1                             */ \
-    opaResInMuxNegPad,              /* Resistor ladder input from neg pad.     */ \
-    DAC_OPA0MUX_OUTPEN_OUT0,        /* Alternate output 0 enabled.             */ \
-    _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting.             */       \
-    _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting.        */       \
-    false,                          /* No low pass filter on pos pad.          */ \
-    false,                          /* No low pass filter on neg pad.          */ \
-    false,                          /* No nextout output enabled.              */ \
-    true,                           /* Neg pad enabled, used as signal ground. */ \
-    true,                           /* Pos pad enabled, used as signal input.  */ \
-    false,                          /* No shorting of inputs.                  */ \
-    false,                          /* Rail-to-rail input enabled.             */ \
-    true,                           /* Use factory calibrated opamp offset.    */ \
-    0                               /* Opamp offset value (not used).          */ \
-  }
+/** Configuration of OPA2 in non-inverting amplifier mode. */
+#define OPA_INIT_NON_INVERTING_OPA2                                             \
+{                                                                               \
+  opaNegSelResTap,                /* Neg input from resistor ladder tap.     */ \
+  opaPosSelPosPad,                /* Pos input from pad.                     */ \
+  opaOutModeMain,                 /* Main output enabled.                    */ \
+  opaResSelR2eq0_33R1,            /* R2 = 1/3 R1                             */ \
+  opaResInMuxNegPad,              /* Resistor ladder input from neg pad.     */ \
+  DAC_OPA0MUX_OUTPEN_OUT0,        /* Alternate output 0 enabled.             */ \
+  _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting.                   */ \
+  _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting.              */ \
+  false,                          /* No low pass filter on pos pad.          */ \
+  false,                          /* No low pass filter on neg pad.          */ \
+  false,                          /* No nextout output enabled.              */ \
+  true,                           /* Neg pad enabled, used as signal ground. */ \
+  true,                           /* Pos pad enabled, used as signal input.  */ \
+  false,                          /* No shorting of inputs.                  */ \
+  false,                          /* Rail-to-rail input enabled.             */ \
+  true,                           /* Use factory calibrated opamp offset.    */ \
+  0                               /* Opamp offset value (not used).          */ \
+}
 
-/** Configuration of OPA0/1 in inverting amplifier mode.               */
-#define OPA_INIT_INVERTING                                                        \
-  {                                                                               \
-    opaNegSelResTap,                /* Neg input from resistor ladder tap.     */ \
-    opaPosSelPosPad,                /* Pos input from pad.                     */ \
-    opaOutModeMain,                 /* Main output enabled.                    */ \
-    opaResSelR2eqR1,                /* R2 = R1                                 */ \
-    opaResInMuxNegPad,              /* Resistor ladder input from neg pad.     */ \
-    0,                              /* No alternate outputs enabled.           */ \
-    _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting.             */       \
-    _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting.        */       \
-    false,                          /* No low pass filter on pos pad.          */ \
-    false,                          /* No low pass filter on neg pad.          */ \
-    false,                          /* No nextout output enabled.              */ \
-    true,                           /* Neg pad enabled, used as signal input.  */ \
-    true,                           /* Pos pad enabled, used as signal ground. */ \
-    false,                          /* No shorting of inputs.                  */ \
-    false,                          /* Rail-to-rail input enabled.             */ \
-    true,                           /* Use factory calibrated opamp offset.    */ \
-    0                               /* Opamp offset value (not used).          */ \
-  }
+/** Configuration of OPA0/1 in inverting amplifier mode. */
+#define OPA_INIT_INVERTING                                                      \
+{                                                                               \
+  opaNegSelResTap,                /* Neg input from resistor ladder tap.     */ \
+  opaPosSelPosPad,                /* Pos input from pad.                     */ \
+  opaOutModeMain,                 /* Main output enabled.                    */ \
+  opaResSelR2eqR1,                /* R2 = R1                                 */ \
+  opaResInMuxNegPad,              /* Resistor ladder input from neg pad.     */ \
+  0,                              /* No alternate outputs enabled.           */ \
+  _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting.                   */ \
+  _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting.              */ \
+  false,                          /* No low pass filter on pos pad.          */ \
+  false,                          /* No low pass filter on neg pad.          */ \
+  false,                          /* No nextout output enabled.              */ \
+  true,                           /* Neg pad enabled, used as signal input.  */ \
+  true,                           /* Pos pad enabled, used as signal ground. */ \
+  false,                          /* No shorting of inputs.                  */ \
+  false,                          /* Rail-to-rail input enabled.             */ \
+  true,                           /* Use factory calibrated opamp offset.    */ \
+  0                               /* Opamp offset value (not used).          */ \
+}
 
-/** Configuration of OPA2 in inverting amplifier mode.                 */
-#define OPA_INIT_INVERTING_OPA2                                                   \
-  {                                                                               \
-    opaNegSelResTap,                /* Neg input from resistor ladder tap.     */ \
-    opaPosSelPosPad,                /* Pos input from pad.                     */ \
-    opaOutModeMain,                 /* Main output enabled.                    */ \
-    opaResSelR2eqR1,                /* R2 = R1                                 */ \
-    opaResInMuxNegPad,              /* Resistor ladder input from neg pad.     */ \
-    DAC_OPA0MUX_OUTPEN_OUT0,        /* Alternate output 0 enabled.             */ \
-    _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting.             */       \
-    _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting.        */       \
-    false,                          /* No low pass filter on pos pad.          */ \
-    false,                          /* No low pass filter on neg pad.          */ \
-    false,                          /* No nextout output enabled.              */ \
-    true,                           /* Neg pad enabled, used as signal input.  */ \
-    true,                           /* Pos pad enabled, used as signal ground. */ \
-    false,                          /* No shorting of inputs.                  */ \
-    false,                          /* Rail-to-rail input enabled.             */ \
-    true,                           /* Use factory calibrated opamp offset.    */ \
-    0                               /* Opamp offset value (not used).          */ \
-  }
+/** Configuration of OPA2 in inverting amplifier mode. */
+#define OPA_INIT_INVERTING_OPA2                                                 \
+{                                                                               \
+  opaNegSelResTap,                /* Neg input from resistor ladder tap.     */ \
+  opaPosSelPosPad,                /* Pos input from pad.                     */ \
+  opaOutModeMain,                 /* Main output enabled.                    */ \
+  opaResSelR2eqR1,                /* R2 = R1                                 */ \
+  opaResInMuxNegPad,              /* Resistor ladder input from neg pad.     */ \
+  DAC_OPA0MUX_OUTPEN_OUT0,        /* Alternate output 0 enabled.             */ \
+  _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting.                   */ \
+  _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting.              */ \
+  false,                          /* No low pass filter on pos pad.          */ \
+  false,                          /* No low pass filter on neg pad.          */ \
+  false,                          /* No nextout output enabled.              */ \
+  true,                           /* Neg pad enabled, used as signal input.  */ \
+  true,                           /* Pos pad enabled, used as signal ground. */ \
+  false,                          /* No shorting of inputs.                  */ \
+  false,                          /* Rail-to-rail input enabled.             */ \
+  true,                           /* Use factory calibrated opamp offset.    */ \
+  0                               /* Opamp offset value (not used).          */ \
+}
 
-/** Configuration of OPA0 in cascaded non-inverting amplifier mode.    */
-#define OPA_INIT_CASCADED_NON_INVERTING_OPA0                                      \
-  {                                                                               \
-    opaNegSelResTap,                /* Neg input from resistor ladder tap.     */ \
-    opaPosSelPosPad,                /* Pos input from pad.                     */ \
-    opaOutModeAll,                  /* Both main and alternate outputs.        */ \
-    opaResSelR2eq0_33R1,            /* R2 = 1/3 R1                             */ \
-    opaResInMuxNegPad,              /* Resistor ladder input from neg pad.     */ \
-    0,                              /* No alternate outputs enabled.           */ \
-    _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting.             */       \
-    _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting.        */       \
-    false,                          /* No low pass filter on pos pad.          */ \
-    false,                          /* No low pass filter on neg pad.          */ \
-    true,                           /* Pass output to next stage (OPA1).       */ \
-    true,                           /* Neg pad enabled, used as signal ground. */ \
-    true,                           /* Pos pad enabled, used as signal input.  */ \
-    false,                          /* No shorting of inputs.                  */ \
-    false,                          /* Rail-to-rail input enabled.             */ \
-    true,                           /* Use factory calibrated opamp offset.    */ \
-    0                               /* Opamp offset value (not used).          */ \
-  }
+/** Configuration of OPA0 in cascaded non-inverting amplifier mode. */
+#define OPA_INIT_CASCADED_NON_INVERTING_OPA0                                    \
+{                                                                               \
+  opaNegSelResTap,                /* Neg input from resistor ladder tap.     */ \
+  opaPosSelPosPad,                /* Pos input from pad.                     */ \
+  opaOutModeAll,                  /* Both main and alternate outputs.        */ \
+  opaResSelR2eq0_33R1,            /* R2 = 1/3 R1                             */ \
+  opaResInMuxNegPad,              /* Resistor ladder input from neg pad.     */ \
+  0,                              /* No alternate outputs enabled.           */ \
+  _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting.                   */ \
+  _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting.              */ \
+  false,                          /* No low pass filter on pos pad.          */ \
+  false,                          /* No low pass filter on neg pad.          */ \
+  true,                           /* Pass output to next stage (OPA1).       */ \
+  true,                           /* Neg pad enabled, used as signal ground. */ \
+  true,                           /* Pos pad enabled, used as signal input.  */ \
+  false,                          /* No shorting of inputs.                  */ \
+  false,                          /* Rail-to-rail input enabled.             */ \
+  true,                           /* Use factory calibrated opamp offset.    */ \
+  0                               /* Opamp offset value (not used).          */ \
+}
 
-/** Configuration of OPA1 in cascaded non-inverting amplifier mode.    */
-#define OPA_INIT_CASCADED_NON_INVERTING_OPA1                                      \
-  {                                                                               \
-    opaNegSelResTap,                /* Neg input from resistor ladder tap.     */ \
-    opaPosSelOpaIn,                 /* Pos input from OPA0 output.             */ \
-    opaOutModeAll,                  /* Both main and alternate outputs.        */ \
-    opaResSelR2eq0_33R1,            /* R2 = 1/3 R1                             */ \
-    opaResInMuxNegPad,              /* Resistor ladder input from neg pad.     */ \
-    0,                              /* No alternate outputs enabled.           */ \
-    _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting.             */       \
-    _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting.        */       \
-    false,                          /* No low pass filter on pos pad.          */ \
-    false,                          /* No low pass filter on neg pad.          */ \
-    true,                           /* Pass output to next stage (OPA2).       */ \
-    true,                           /* Neg pad enabled, used as signal ground. */ \
-    false,                          /* Pos pad disabled.                       */ \
-    false,                          /* No shorting of inputs.                  */ \
-    false,                          /* Rail-to-rail input enabled.             */ \
-    true,                           /* Use factory calibrated opamp offset.    */ \
-    0                               /* Opamp offset value (not used).          */ \
-  }
+/** Configuration of OPA1 in cascaded non-inverting amplifier mode. */
+#define OPA_INIT_CASCADED_NON_INVERTING_OPA1                                    \
+{                                                                               \
+  opaNegSelResTap,                /* Neg input from resistor ladder tap.     */ \
+  opaPosSelOpaIn,                 /* Pos input from OPA0 output.             */ \
+  opaOutModeAll,                  /* Both main and alternate outputs.        */ \
+  opaResSelR2eq0_33R1,            /* R2 = 1/3 R1                             */ \
+  opaResInMuxNegPad,              /* Resistor ladder input from neg pad.     */ \
+  0,                              /* No alternate outputs enabled.           */ \
+  _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting.                   */ \
+  _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting.              */ \
+  false,                          /* No low pass filter on pos pad.          */ \
+  false,                          /* No low pass filter on neg pad.          */ \
+  true,                           /* Pass output to next stage (OPA2).       */ \
+  true,                           /* Neg pad enabled, used as signal ground. */ \
+  false,                          /* Pos pad disabled.                       */ \
+  false,                          /* No shorting of inputs.                  */ \
+  false,                          /* Rail-to-rail input enabled.             */ \
+  true,                           /* Use factory calibrated opamp offset.    */ \
+  0                               /* Opamp offset value (not used).          */ \
+}
 
-/** Configuration of OPA2 in cascaded non-inverting amplifier mode.    */
-#define OPA_INIT_CASCADED_NON_INVERTING_OPA2                                      \
-  {                                                                               \
-    opaNegSelResTap,                /* Neg input from resistor ladder tap.     */ \
-    opaPosSelOpaIn,                 /* Pos input from OPA1 output.             */ \
-    opaOutModeMain,                 /* Main output enabled.                    */ \
-    opaResSelR2eq0_33R1,            /* R2 = 1/3 R1                             */ \
-    opaResInMuxNegPad,              /* Resistor ladder input from neg pad.     */ \
-    DAC_OPA0MUX_OUTPEN_OUT0,        /* Alternate output 0 enabled.             */ \
-    _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting.             */       \
-    _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting.        */       \
-    false,                          /* No low pass filter on pos pad.          */ \
-    false,                          /* No low pass filter on neg pad.          */ \
-    false,                          /* No nextout output enabled.              */ \
-    true,                           /* Neg pad enabled, used as signal ground. */ \
-    false,                          /* Pos pad disabled.                       */ \
-    false,                          /* No shorting of inputs.                  */ \
-    false,                          /* Rail-to-rail input enabled.             */ \
-    true,                           /* Use factory calibrated opamp offset.    */ \
-    0                               /* Opamp offset value (not used).          */ \
-  }
+/** Configuration of OPA2 in cascaded non-inverting amplifier mode. */
+#define OPA_INIT_CASCADED_NON_INVERTING_OPA2                                    \
+{                                                                               \
+  opaNegSelResTap,                /* Neg input from resistor ladder tap.     */ \
+  opaPosSelOpaIn,                 /* Pos input from OPA1 output.             */ \
+  opaOutModeMain,                 /* Main output enabled.                    */ \
+  opaResSelR2eq0_33R1,            /* R2 = 1/3 R1                             */ \
+  opaResInMuxNegPad,              /* Resistor ladder input from neg pad.     */ \
+  DAC_OPA0MUX_OUTPEN_OUT0,        /* Alternate output 0 enabled.             */ \
+  _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting.                   */ \
+  _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting.              */ \
+  false,                          /* No low pass filter on pos pad.          */ \
+  false,                          /* No low pass filter on neg pad.          */ \
+  false,                          /* No nextout output enabled.              */ \
+  true,                           /* Neg pad enabled, used as signal ground. */ \
+  false,                          /* Pos pad disabled.                       */ \
+  false,                          /* No shorting of inputs.                  */ \
+  false,                          /* Rail-to-rail input enabled.             */ \
+  true,                           /* Use factory calibrated opamp offset.    */ \
+  0                               /* Opamp offset value (not used).          */ \
+}
 
-/** Configuration of OPA0 in cascaded inverting amplifier mode.        */
-#define OPA_INIT_CASCADED_INVERTING_OPA0                                          \
-  {                                                                               \
-    opaNegSelResTap,                /* Neg input from resistor ladder tap.     */ \
-    opaPosSelPosPad,                /* Pos input from pad.                     */ \
-    opaOutModeAll,                  /* Both main and alternate outputs.        */ \
-    opaResSelR2eqR1,                /* R2 = R1                                 */ \
-    opaResInMuxNegPad,              /* Resistor ladder input from neg pad.     */ \
-    0,                              /* No alternate outputs enabled.           */ \
-    _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting.             */       \
-    _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting.        */       \
-    false,                          /* No low pass filter on pos pad.          */ \
-    false,                          /* No low pass filter on neg pad.          */ \
-    true,                           /* Pass output to next stage (OPA1).       */ \
-    true,                           /* Neg pad enabled, used as signal input.  */ \
-    true,                           /* Pos pad enabled, used as signal ground. */ \
-    false,                          /* No shorting of inputs.                  */ \
-    false,                          /* Rail-to-rail input enabled.             */ \
-    true,                           /* Use factory calibrated opamp offset.    */ \
-    0                               /* Opamp offset value (not used).          */ \
-  }
+/** Configuration of OPA0 in cascaded inverting amplifier mode. */
+#define OPA_INIT_CASCADED_INVERTING_OPA0                                        \
+{                                                                               \
+  opaNegSelResTap,                /* Neg input from resistor ladder tap.     */ \
+  opaPosSelPosPad,                /* Pos input from pad.                     */ \
+  opaOutModeAll,                  /* Both main and alternate outputs.        */ \
+  opaResSelR2eqR1,                /* R2 = R1                                 */ \
+  opaResInMuxNegPad,              /* Resistor ladder input from neg pad.     */ \
+  0,                              /* No alternate outputs enabled.           */ \
+  _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting.                   */ \
+  _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting.              */ \
+  false,                          /* No low pass filter on pos pad.          */ \
+  false,                          /* No low pass filter on neg pad.          */ \
+  true,                           /* Pass output to next stage (OPA1).       */ \
+  true,                           /* Neg pad enabled, used as signal input.  */ \
+  true,                           /* Pos pad enabled, used as signal ground. */ \
+  false,                          /* No shorting of inputs.                  */ \
+  false,                          /* Rail-to-rail input enabled.             */ \
+  true,                           /* Use factory calibrated opamp offset.    */ \
+  0                               /* Opamp offset value (not used).          */ \
+}
 
-/** Configuration of OPA1 in cascaded inverting amplifier mode.        */
-#define OPA_INIT_CASCADED_INVERTING_OPA1                                          \
-  {                                                                               \
-    opaNegSelResTap,                /* Neg input from resistor ladder tap.     */ \
-    opaPosSelPosPad,                /* Pos input from pad.                     */ \
-    opaOutModeAll,                  /* Both main and alternate outputs.        */ \
-    opaResSelR2eqR1,                /* R2 = R1                                 */ \
-    opaResInMuxOpaIn,               /* Resistor ladder input from OPA0.        */ \
-    0,                              /* No alternate outputs enabled.           */ \
-    _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting.             */       \
-    _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting.        */       \
-    false,                          /* No low pass filter on pos pad.          */ \
-    false,                          /* No low pass filter on neg pad.          */ \
-    true,                           /* Pass output to next stage (OPA2).       */ \
-    false,                          /* Neg pad disabled.                       */ \
-    true,                           /* Pos pad enabled, used as signal ground. */ \
-    false,                          /* No shorting of inputs.                  */ \
-    false,                          /* Rail-to-rail input enabled.             */ \
-    true,                           /* Use factory calibrated opamp offset.    */ \
-    0                               /* Opamp offset value (not used).          */ \
-  }
+/** Configuration of OPA1 in cascaded inverting amplifier mode. */
+#define OPA_INIT_CASCADED_INVERTING_OPA1                                        \
+{                                                                               \
+  opaNegSelResTap,                /* Neg input from resistor ladder tap.     */ \
+  opaPosSelPosPad,                /* Pos input from pad.                     */ \
+  opaOutModeAll,                  /* Both main and alternate outputs.        */ \
+  opaResSelR2eqR1,                /* R2 = R1                                 */ \
+  opaResInMuxOpaIn,               /* Resistor ladder input from OPA0.        */ \
+  0,                              /* No alternate outputs enabled.           */ \
+  _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting.                   */ \
+  _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting.              */ \
+  false,                          /* No low pass filter on pos pad.          */ \
+  false,                          /* No low pass filter on neg pad.          */ \
+  true,                           /* Pass output to next stage (OPA2).       */ \
+  false,                          /* Neg pad disabled.                       */ \
+  true,                           /* Pos pad enabled, used as signal ground. */ \
+  false,                          /* No shorting of inputs.                  */ \
+  false,                          /* Rail-to-rail input enabled.             */ \
+  true,                           /* Use factory calibrated opamp offset.    */ \
+  0                               /* Opamp offset value (not used).          */ \
+}
 
-/** Configuration of OPA2 in cascaded inverting amplifier mode.        */
-#define OPA_INIT_CASCADED_INVERTING_OPA2                                          \
-  {                                                                               \
-    opaNegSelResTap,                /* Neg input from resistor ladder tap.     */ \
-    opaPosSelPosPad,                /* Pos input from pad.                     */ \
-    opaOutModeMain,                 /* Main output enabled.                    */ \
-    opaResSelR2eqR1,                /* R2 = R1                                 */ \
-    opaResInMuxOpaIn,               /* Resistor ladder input from OPA1.        */ \
-    DAC_OPA0MUX_OUTPEN_OUT0,        /* Alternate output 0 enabled.             */ \
-    _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting.             */       \
-    _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting.        */       \
-    false,                          /* No low pass filter on pos pad.          */ \
-    false,                          /* No low pass filter on neg pad.          */ \
-    false,                          /* No nextout output enabled.              */ \
-    false,                          /* Neg pad disabled.                       */ \
-    true,                           /* Pos pad enabled, used as signal ground. */ \
-    false,                          /* No shorting of inputs.                  */ \
-    false,                          /* Rail-to-rail input enabled.             */ \
-    true,                           /* Use factory calibrated opamp offset.    */ \
-    0                               /* Opamp offset value (not used).          */ \
-  }
+/** Configuration of OPA2 in cascaded inverting amplifier mode. */
+#define OPA_INIT_CASCADED_INVERTING_OPA2                                        \
+{                                                                               \
+  opaNegSelResTap,                /* Neg input from resistor ladder tap.     */ \
+  opaPosSelPosPad,                /* Pos input from pad.                     */ \
+  opaOutModeMain,                 /* Main output enabled.                    */ \
+  opaResSelR2eqR1,                /* R2 = R1                                 */ \
+  opaResInMuxOpaIn,               /* Resistor ladder input from OPA1.        */ \
+  DAC_OPA0MUX_OUTPEN_OUT0,        /* Alternate output 0 enabled.             */ \
+  _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting.                   */ \
+  _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting.              */ \
+  false,                          /* No low pass filter on pos pad.          */ \
+  false,                          /* No low pass filter on neg pad.          */ \
+  false,                          /* No nextout output enabled.              */ \
+  false,                          /* Neg pad disabled.                       */ \
+  true,                           /* Pos pad enabled, used as signal ground. */ \
+  false,                          /* No shorting of inputs.                  */ \
+  false,                          /* Rail-to-rail input enabled.             */ \
+  true,                           /* Use factory calibrated opamp offset.    */ \
+  0                               /* Opamp offset value (not used).          */ \
+}
 
-/** Configuration of OPA0 in two-opamp differential driver mode.       */
-#define OPA_INIT_DIFF_DRIVER_OPA0                                                 \
-  {                                                                               \
-    opaNegSelUnityGain,             /* Unity gain.                             */ \
-    opaPosSelPosPad,                /* Pos input from pad.                     */ \
-    opaOutModeAll,                  /* Both main and alternate outputs.        */ \
-    opaResSelDefault,               /* Resistor ladder is not used.            */ \
-    opaResInMuxDisable,             /* Resistor ladder disabled.               */ \
-    0,                              /* No alternate outputs enabled.           */ \
-    _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting.             */       \
-    _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting.        */       \
-    false,                          /* No low pass filter on pos pad.          */ \
-    false,                          /* No low pass filter on neg pad.          */ \
-    true,                           /* Pass output to next stage (OPA1).       */ \
-    false,                          /* Neg pad disabled.                       */ \
-    true,                           /* Pos pad enabled, used as signal input.  */ \
-    false,                          /* No shorting of inputs.                  */ \
-    false,                          /* Rail-to-rail input enabled.             */ \
-    true,                           /* Use factory calibrated opamp offset.    */ \
-    0                               /* Opamp offset value (not used).          */ \
-  }
+/** Configuration of OPA0 in two-opamp differential driver mode. */
+#define OPA_INIT_DIFF_DRIVER_OPA0                                               \
+{                                                                               \
+  opaNegSelUnityGain,             /* Unity gain.                             */ \
+  opaPosSelPosPad,                /* Pos input from pad.                     */ \
+  opaOutModeAll,                  /* Both main and alternate outputs.        */ \
+  opaResSelDefault,               /* Resistor ladder is not used.            */ \
+  opaResInMuxDisable,             /* Resistor ladder disabled.               */ \
+  0,                              /* No alternate outputs enabled.           */ \
+  _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting.                   */ \
+  _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting.              */ \
+  false,                          /* No low pass filter on pos pad.          */ \
+  false,                          /* No low pass filter on neg pad.          */ \
+  true,                           /* Pass output to next stage (OPA1).       */ \
+  false,                          /* Neg pad disabled.                       */ \
+  true,                           /* Pos pad enabled, used as signal input.  */ \
+  false,                          /* No shorting of inputs.                  */ \
+  false,                          /* Rail-to-rail input enabled.             */ \
+  true,                           /* Use factory calibrated opamp offset.    */ \
+  0                               /* Opamp offset value (not used).          */ \
+}
 
-/** Configuration of OPA1 in two-opamp differential driver mode.       */
-#define OPA_INIT_DIFF_DRIVER_OPA1                                                 \
-  {                                                                               \
-    opaNegSelResTap,                /* Neg input from resistor ladder tap.     */ \
-    opaPosSelPosPad,                /* Pos input from pad.                     */ \
-    opaOutModeMain,                 /* Main output enabled.                    */ \
-    opaResSelR2eqR1,                /* R2 = R1                                 */ \
-    opaResInMuxOpaIn,               /* Resistor ladder input from OPA0.        */ \
-    0,                              /* No alternate outputs enabled.           */ \
-    _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting.             */       \
-    _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting.        */       \
-    false,                          /* No low pass filter on pos pad.          */ \
-    false,                          /* No low pass filter on neg pad.          */ \
-    false,                          /* No nextout output enabled.              */ \
-    false,                          /* Neg pad disabled.                       */ \
-    true,                           /* Pos pad enabled, used as signal ground. */ \
-    false,                          /* No shorting of inputs.                  */ \
-    false,                          /* Rail-to-rail input enabled.             */ \
-    true,                           /* Use factory calibrated opamp offset.    */ \
-    0                               /* Opamp offset value (not used).          */ \
-  }
+/** Configuration of OPA1 in two-opamp differential driver mode. */
+#define OPA_INIT_DIFF_DRIVER_OPA1                                               \
+{                                                                               \
+  opaNegSelResTap,                /* Neg input from resistor ladder tap.     */ \
+  opaPosSelPosPad,                /* Pos input from pad.                     */ \
+  opaOutModeMain,                 /* Main output enabled.                    */ \
+  opaResSelR2eqR1,                /* R2 = R1                                 */ \
+  opaResInMuxOpaIn,               /* Resistor ladder input from OPA0.        */ \
+  0,                              /* No alternate outputs enabled.           */ \
+  _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting.                   */ \
+  _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting.              */ \
+  false,                          /* No low pass filter on pos pad.          */ \
+  false,                          /* No low pass filter on neg pad.          */ \
+  false,                          /* No nextout output enabled.              */ \
+  false,                          /* Neg pad disabled.                       */ \
+  true,                           /* Pos pad enabled, used as signal ground. */ \
+  false,                          /* No shorting of inputs.                  */ \
+  false,                          /* Rail-to-rail input enabled.             */ \
+  true,                           /* Use factory calibrated opamp offset.    */ \
+  0                               /* Opamp offset value (not used).          */ \
+}
 
-/** Configuration of OPA0 in three-opamp differential receiver mode.   */
-#define OPA_INIT_DIFF_RECEIVER_OPA0                                               \
-  {                                                                               \
-    opaNegSelUnityGain,             /* Unity gain.                             */ \
-    opaPosSelPosPad,                /* Pos input from pad.                     */ \
-    opaOutModeAll,                  /* Both main and alternate outputs.        */ \
-    opaResSelR2eqR1,                /* R2 = R1                                 */ \
-    opaResInMuxNegPad,              /* Resistor ladder input from neg pad.     */ \
-    0,                              /* No alternate outputs enabled.           */ \
-    _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting.             */       \
-    _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting.        */       \
-    false,                          /* No low pass filter on pos pad.          */ \
-    false,                          /* No low pass filter on neg pad.          */ \
-    true,                           /* Pass output to next stage (OPA2).       */ \
-    true,                           /* Neg pad enabled, used as signal ground. */ \
-    true,                           /* Pos pad enabled, used as signal input.  */ \
-    false,                          /* No shorting of inputs.                  */ \
-    false,                          /* Rail-to-rail input enabled.             */ \
-    true,                           /* Use factory calibrated opamp offset.    */ \
-    0                               /* Opamp offset value (not used).          */ \
-  }
+/** Configuration of OPA0 in three-opamp differential receiver mode. */
+#define OPA_INIT_DIFF_RECEIVER_OPA0                                             \
+{                                                                               \
+  opaNegSelUnityGain,             /* Unity gain.                             */ \
+  opaPosSelPosPad,                /* Pos input from pad.                     */ \
+  opaOutModeAll,                  /* Both main and alternate outputs.        */ \
+  opaResSelR2eqR1,                /* R2 = R1                                 */ \
+  opaResInMuxNegPad,              /* Resistor ladder input from neg pad.     */ \
+  0,                              /* No alternate outputs enabled.           */ \
+  _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting.                   */ \
+  _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting.              */ \
+  false,                          /* No low pass filter on pos pad.          */ \
+  false,                          /* No low pass filter on neg pad.          */ \
+  true,                           /* Pass output to next stage (OPA2).       */ \
+  true,                           /* Neg pad enabled, used as signal ground. */ \
+  true,                           /* Pos pad enabled, used as signal input.  */ \
+  false,                          /* No shorting of inputs.                  */ \
+  false,                          /* Rail-to-rail input enabled.             */ \
+  true,                           /* Use factory calibrated opamp offset.    */ \
+  0                               /* Opamp offset value (not used).          */ \
+}
 
-/** Configuration of OPA1 in three-opamp differential receiver mode.   */
-#define OPA_INIT_DIFF_RECEIVER_OPA1                                               \
-  {                                                                               \
-    opaNegSelUnityGain,             /* Unity gain.                             */ \
-    opaPosSelPosPad,                /* Pos input from pad.                     */ \
-    opaOutModeAll,                  /* Both main and alternate outputs.        */ \
-    opaResSelDefault,               /* Resistor ladder is not used.            */ \
-    opaResInMuxDisable,             /* Disable resistor ladder.                */ \
-    0,                              /* No alternate outputs enabled.           */ \
-    _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting.             */       \
-    _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting.        */       \
-    false,                          /* No low pass filter on pos pad.          */ \
-    false,                          /* No low pass filter on neg pad.          */ \
-    true,                           /* Pass output to next stage (OPA2).       */ \
-    false,                          /* Neg pad disabled.                       */ \
-    true,                           /* Pos pad enabled, used as signal input.  */ \
-    false,                          /* No shorting of inputs.                  */ \
-    false,                          /* Rail-to-rail input enabled.             */ \
-    true,                           /* Use factory calibrated opamp offset.    */ \
-    0                               /* Opamp offset value (not used).          */ \
-  }
+/** Configuration of OPA1 in three-opamp differential receiver mode. */
+#define OPA_INIT_DIFF_RECEIVER_OPA1                                             \
+{                                                                               \
+  opaNegSelUnityGain,             /* Unity gain.                             */ \
+  opaPosSelPosPad,                /* Pos input from pad.                     */ \
+  opaOutModeAll,                  /* Both main and alternate outputs.        */ \
+  opaResSelDefault,               /* Resistor ladder is not used.            */ \
+  opaResInMuxDisable,             /* Disable resistor ladder.                */ \
+  0,                              /* No alternate outputs enabled.           */ \
+  _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting.                   */ \
+  _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting.              */ \
+  false,                          /* No low pass filter on pos pad.          */ \
+  false,                          /* No low pass filter on neg pad.          */ \
+  true,                           /* Pass output to next stage (OPA2).       */ \
+  false,                          /* Neg pad disabled.                       */ \
+  true,                           /* Pos pad enabled, used as signal input.  */ \
+  false,                          /* No shorting of inputs.                  */ \
+  false,                          /* Rail-to-rail input enabled.             */ \
+  true,                           /* Use factory calibrated opamp offset.    */ \
+  0                               /* Opamp offset value (not used).          */ \
+}
 
-/** Configuration of OPA2 in three-opamp differential receiver mode.   */
-#define OPA_INIT_DIFF_RECEIVER_OPA2                                               \
-  {                                                                               \
-    opaNegSelResTap,                /* Input from resistor ladder tap.         */ \
-    opaPosSelResTapOpa0,            /* Input from OPA0 resistor ladder tap.    */ \
-    opaOutModeMain,                 /* Main output enabled.                    */ \
-    opaResSelR2eqR1,                /* R2 = R1                                 */ \
-    opaResInMuxOpaIn,               /* Resistor ladder input from OPA1.        */ \
-    DAC_OPA0MUX_OUTPEN_OUT0,        /* Enable alternate output 0.              */ \
-    _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting.             */       \
-    _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting.        */       \
-    false,                          /* No low pass filter on pos pad.          */ \
-    false,                          /* No low pass filter on neg pad.          */ \
-    false,                          /* No nextout output enabled.              */ \
-    false,                          /* Neg pad disabled.                       */ \
-    false,                          /* Pos pad disabled.                       */ \
-    false,                          /* No shorting of inputs.                  */ \
-    false,                          /* Rail-to-rail input enabled.             */ \
-    true,                           /* Use factory calibrated opamp offset.    */ \
-    0                               /* Opamp offset value (not used).          */ \
-  }
+/** Configuration of OPA2 in three-opamp differential receiver mode. */
+#define OPA_INIT_DIFF_RECEIVER_OPA2                                             \
+{                                                                               \
+  opaNegSelResTap,                /* Input from resistor ladder tap.         */ \
+  opaPosSelResTapOpa0,            /* Input from OPA0 resistor ladder tap.    */ \
+  opaOutModeMain,                 /* Main output enabled.                    */ \
+  opaResSelR2eqR1,                /* R2 = R1                                 */ \
+  opaResInMuxOpaIn,               /* Resistor ladder input from OPA1.        */ \
+  DAC_OPA0MUX_OUTPEN_OUT0,        /* Enable alternate output 0.              */ \
+  _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting.                   */ \
+  _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting.              */ \
+  false,                          /* No low pass filter on pos pad.          */ \
+  false,                          /* No low pass filter on neg pad.          */ \
+  false,                          /* No nextout output enabled.              */ \
+  false,                          /* Neg pad disabled.                       */ \
+  false,                          /* Pos pad disabled.                       */ \
+  false,                          /* No shorting of inputs.                  */ \
+  false,                          /* Rail-to-rail input enabled.             */ \
+  true,                           /* Use factory calibrated opamp offset.    */ \
+  0                               /* Opamp offset value (not used).          */ \
+}
 
 /*******************************************************************************
  *****************************   PROTOTYPES   **********************************
@@ -567,4 +566,4 @@
 #endif
 
 #endif /* defined( OPAMP_PRESENT ) && ( OPAMP_COUNT == 1 ) */
-#endif /* __SILICON_LABS_EM_OPAMP_H_ */
+#endif /* __SILICON_LABS_EM_OPAMP_H__ */

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_part.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_part.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /***************************************************************************//**
  * @file em_part.h
  * @brief Verify that part specific main header files are supported and included
- * @version 3.20.12
+ * @version 4.2.1
  *******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
  *******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,12 +30,12 @@
  *
  ******************************************************************************/
 
-
-#ifndef __SILICON_LABS_EM_PART_H_
-#define __SILICON_LABS_EM_PART_H_
+#ifndef __SILICON_LABS_EM_PART_H__
+#define __SILICON_LABS_EM_PART_H__
 
 /* This file is kept for backwards compatibility. */
+#warning "Using em_part.h is deprecated. Please use em_device.h instead."
 
 #include "em_device.h"
 
-#endif /* __SILICON_LABS_EM_PART_H_ */
+#endif /* __SILICON_LABS_EM_PART_H__ */

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_pcnt.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_pcnt.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /***************************************************************************//**
  * @file em_pcnt.h
  * @brief Pulse Counter (PCNT) peripheral API
- * @version 3.20.12
+ * @version 4.2.1
  *******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
  *******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,9 +30,8 @@
  *
  ******************************************************************************/
 
-
-#ifndef __SILICON_LABS_EM_PCNT_H_
-#define __SILICON_LABS_EM_PCNT_H_
+#ifndef __SILICON_LABS_EM_PCNT_H__
+#define __SILICON_LABS_EM_PCNT_H__
 
 #include "em_device.h"
 #if defined(PCNT_COUNT) && (PCNT_COUNT > 0)
@@ -56,17 +55,21 @@
 /*******************************************************************************
  *******************************   DEFINES   ***********************************
  ******************************************************************************/
-/** PCNT Counter register sizes. */
-#if defined _EFM32_GECKO_FAMILY
-#define PCNT0_CNT_SIZE    (8)   /** PCNT0 counter is  8 bits. */
+/** PCNT0 Counter register size. */
+#if defined(_EFM32_GECKO_FAMILY)
+#define PCNT0_CNT_SIZE    (8)   /* PCNT0 counter is  8 bits. */
 #else
-#define PCNT0_CNT_SIZE   (16)   /** PCNT0 counter is 16 bits. */
+#define PCNT0_CNT_SIZE   (16)   /* PCNT0 counter is 16 bits. */
 #endif
+
 #ifdef PCNT1
-#define PCNT1_CNT_SIZE    (8)   /** PCNT1 counter is  8 bits. */
+/** PCNT1 Counter register size. */
+#define PCNT1_CNT_SIZE    (8)   /* PCNT1 counter is  8 bits. */
 #endif
+
 #ifdef PCNT2
-#define PCNT2_CNT_SIZE    (8)   /** PCNT2 counter is  8 bits. */
+/** PCNT2 Counter register size. */
+#define PCNT2_CNT_SIZE    (8)   /* PCNT2 counter is  8 bits. */
 #endif
 
 
@@ -87,11 +90,22 @@
   pcntModeExtSingle = _PCNT_CTRL_MODE_EXTCLKSINGLE,
 
   /** Externally clocked quadrature decoder mode (available in EM0-EM3). */
-  pcntModeExtQuad   = _PCNT_CTRL_MODE_EXTCLKQUAD
+  pcntModeExtQuad   = _PCNT_CTRL_MODE_EXTCLKQUAD,
+  
+#if defined(_PCNT_CTRL_MODE_OVSQUAD1X)
+  /** LFACLK oversampling quadrature decoder 1X mode (available in EM0-EM2). */
+  pcntModeOvsQuad1  = _PCNT_CTRL_MODE_OVSQUAD1X,
+  
+  /** LFACLK oversampling quadrature decoder 2X mode (available in EM0-EM2). */
+  pcntModeOvsQuad2  = _PCNT_CTRL_MODE_OVSQUAD2X,
+  
+  /** LFACLK oversampling quadrature decoder 4X mode (available in EM0-EM2). */
+  pcntModeOvsQuad4  = _PCNT_CTRL_MODE_OVSQUAD4X,
+#endif
 } PCNT_Mode_TypeDef;
 
 
-#if defined( _PCNT_CTRL_CNTEV_MASK)
+#if defined(_PCNT_CTRL_CNTEV_MASK)
 /** Counter event selection.
  *  Note: unshifted values are being used for enumeration because multiple
  *  configuration structure members use this type definition. */
@@ -112,7 +126,7 @@
 #endif
 
 
-#if defined( _PCNT_INPUT_MASK )
+#if defined(_PCNT_INPUT_MASK)
 /** PRS sources for @p s0PRS and @p s1PRS. */
 typedef enum
 {
@@ -120,28 +134,28 @@
   pcntPRSCh1 = 1,     /**< PRS channel 1. */
   pcntPRSCh2 = 2,     /**< PRS channel 2. */
   pcntPRSCh3 = 3,     /**< PRS channel 3. */
-#if defined( PCNT_INPUT_S0PRSSEL_PRSCH4 )
+#if defined(PCNT_INPUT_S0PRSSEL_PRSCH4)
   pcntPRSCh4 = 4,     /**< PRS channel 4. */
 #endif
-#if defined( PCNT_INPUT_S0PRSSEL_PRSCH5 )
+#if defined(PCNT_INPUT_S0PRSSEL_PRSCH5)
   pcntPRSCh5 = 5,     /**< PRS channel 5. */
 #endif
-#if defined( PCNT_INPUT_S0PRSSEL_PRSCH6 )
+#if defined(PCNT_INPUT_S0PRSSEL_PRSCH6)
   pcntPRSCh6 = 6,     /**< PRS channel 6. */
 #endif
-#if defined( PCNT_INPUT_S0PRSSEL_PRSCH7 )
+#if defined(PCNT_INPUT_S0PRSSEL_PRSCH7)
   pcntPRSCh7 = 7,     /**< PRS channel 7. */
 #endif
-#if defined( PCNT_INPUT_S0PRSSEL_PRSCH8 )
+#if defined(PCNT_INPUT_S0PRSSEL_PRSCH8)
   pcntPRSCh8 = 8,     /**< PRS channel 8. */
 #endif
-#if defined( PCNT_INPUT_S0PRSSEL_PRSCH9 )
+#if defined(PCNT_INPUT_S0PRSSEL_PRSCH9)
   pcntPRSCh9 = 9,     /**< PRS channel 9. */
 #endif
-#if defined( PCNT_INPUT_S0PRSSEL_PRSCH10 )
+#if defined(PCNT_INPUT_S0PRSSEL_PRSCH10)
   pcntPRSCh10 = 10,   /**< PRS channel 10. */
 #endif
-#if defined( PCNT_INPUT_S0PRSSEL_PRSCH11 )
+#if defined(PCNT_INPUT_S0PRSSEL_PRSCH11)
   pcntPRSCh11 = 11    /**< PRS channel 11. */
 #endif
 } PCNT_PRSSel_TypeDef;
@@ -187,17 +201,17 @@
   /** Counting direction, only applicable for #pcntModeOvsSingle and
    * #pcntModeExtSingle modes. */
   bool                  countDown;
-
-  /** Enable filter, only available in #pcntModeOvsSingle mode. */
+  
+  /** Enable filter, only available in #pcntModeOvs* modes. */
   bool                  filter;
 
-#if defined( PCNT_CTRL_HYST )
+#if defined(PCNT_CTRL_HYST)
   /** Set to true to enable hysteresis. When its enabled, the PCNT will always
    *  overflow and underflow to TOP/2. */
   bool                  hyst;
 
   /** Set to true to enable S1 to determine the direction of counting in
-   *  OVSSINGLE or EXTCLKSINGLE modes.
+   *  OVSSINGLE or EXTCLKSINGLE modes. @n
    *  When S1 is high, the count direction is given by CNTDIR, and when S1 is
    *  low, the count direction is the opposite. */
   bool                  s1CntDir;
@@ -218,34 +232,141 @@
 #endif
 } PCNT_Init_TypeDef;
 
-#if !defined ( PCNT_CTRL_HYST )
+#if !defined(PCNT_CTRL_HYST)
 /** Default config for PCNT init structure. */
-#define PCNT_INIT_DEFAULT                                                           \
-  { pcntModeDisable,                          /* Disabled by default. */            \
-    _PCNT_CNT_RESETVALUE,                     /* Default counter HW reset value. */ \
-    _PCNT_TOP_RESETVALUE,                     /* Default counter HW reset value. */ \
-    false,                                    /* Use positive edge. */              \
-    false,                                    /* Up-counting. */                    \
-    false                                     /* Filter disabled. */                \
-  }
+#define PCNT_INIT_DEFAULT                                                         \
+{                                                                                 \
+  pcntModeDisable,                          /* Disabled by default. */            \
+  _PCNT_CNT_RESETVALUE,                     /* Default counter HW reset value. */ \
+  _PCNT_TOP_RESETVALUE,                     /* Default counter HW reset value. */ \
+  false,                                    /* Use positive edge. */              \
+  false,                                    /* Up-counting. */                    \
+  false                                     /* Filter disabled. */                \
+}
 #else
 /** Default config for PCNT init structure. */
-#define PCNT_INIT_DEFAULT                                                                        \
-  { pcntModeDisable,                          /* Disabled by default. */                         \
-    _PCNT_CNT_RESETVALUE,                     /* Default counter HW reset value. */              \
-    _PCNT_TOP_RESETVALUE,                     /* Default counter HW reset value. */              \
-    false,                                    /* Use positive edge. */                           \
-    false,                                    /* Up-counting. */                                 \
-    false,                                    /* Filter disabled. */                             \
-    false,                                    /* Hysteresis disabled. */                         \
-    true,                                     /* Counter direction is given by CNTDIR. */        \
-    pcntCntEventUp,                           /* Regular counter counts up on upcount events. */ \
-    pcntCntEventNone,                         /* Auxiliary counter doesn't respond to events. */ \
-    pcntPRSCh0,                               /* PRS channel 0 selected as S0IN. */              \
-    pcntPRSCh0                                /* PRS channel 0 selected as S1IN. */              \
-  }
+#define PCNT_INIT_DEFAULT                                                                      \
+{                                                                                              \
+  pcntModeDisable,                          /* Disabled by default. */                         \
+  _PCNT_CNT_RESETVALUE,                     /* Default counter HW reset value. */              \
+  _PCNT_TOP_RESETVALUE,                     /* Default counter HW reset value. */              \
+  false,                                    /* Use positive edge. */                           \
+  false,                                    /* Up-counting. */                                 \
+  false,                                    /* Filter disabled. */                             \
+  false,                                    /* Hysteresis disabled. */                         \
+  true,                                     /* Counter direction is given by CNTDIR. */        \
+  pcntCntEventUp,                           /* Regular counter counts up on upcount events. */ \
+  pcntCntEventNone,                         /* Auxiliary counter doesn't respond to events. */ \
+  pcntPRSCh0,                               /* PRS channel 0 selected as S0IN. */              \
+  pcntPRSCh0                                /* PRS channel 0 selected as S1IN. */              \
+}
+#endif
+
+#if defined(PCNT_OVSCFG_FILTLEN_DEFAULT)
+/** Filter initialization structure */
+typedef struct 
+{
+  /** Used only in OVSINGLE and OVSQUAD1X-4X modes. To use this, enable the filter through
+   *  setting filter to true during PCNT_Init(). Filter length = (filtLen + 5) LFACLK cycles. */
+  uint8_t               filtLen;
+  
+  /** When set, removes flutter from Quaddecoder inputs S0IN and S1IN. 
+   *  Available only in OVSQUAD1X-4X modes. */
+  bool                  flutterrm;
+} PCNT_Filter_TypeDef;
+#endif
+
+/** Default config for PCNT init structure. */
+#if defined(PCNT_OVSCFG_FILTLEN_DEFAULT)
+#define PCNT_FILTER_DEFAULT                                                                     \
+{                                                                                               \
+  0,                                        /* Default length is 5 LFACLK cycles */             \
+  false                                     /* No flutter removal */                            \
+}                                                                                             
 #endif
 
+#if defined(PCNT_CTRL_TCCMODE_DEFAULT)
+
+/** Modes for Triggered Compare and Clear module */
+typedef enum 
+{
+  /** Triggered compare and clear not enabled. */
+  tccModeDisabled       = _PCNT_CTRL_TCCMODE_DISABLED,
+  
+  /** Compare and clear performed on each (optionally prescaled) LFA clock cycle. */
+  tccModeLFA            = _PCNT_CTRL_TCCMODE_LFA,
+  
+  /** Compare and clear performed on PRS edges. Polarity defined by prsPolarity. */
+  tccModePRS            = _PCNT_CTRL_TCCMODE_PRS
+} PCNT_TCCMode_TypeDef;
+
+/** Prescaler values for LFA compare and clear events. Only has effect when TCC mode is LFA. */
+typedef enum 
+{
+  /** Compare and clear event each LFA cycle. */
+  tccPrescDiv1          = _PCNT_CTRL_TCCPRESC_DIV1,
+  
+  /** Compare and clear event every other LFA cycle. */
+  tccPrescDiv2          = _PCNT_CTRL_TCCPRESC_DIV2,
+  
+  /** Compare and clear event every 4th LFA cycle. */
+  tccPrescDiv4          = _PCNT_CTRL_TCCPRESC_DIV4,
+  
+  /** Compare and clear event every 8th LFA cycle. */
+  tccPrescDiv8          = _PCNT_CTRL_TCCPRESC_DIV8
+} PCNT_TCCPresc_Typedef;
+
+/** Compare modes for TCC module */
+typedef enum 
+{
+  /** Compare match if PCNT_CNT is less than, or equal to PCNT_TOP. */
+  tccCompLTOE           = _PCNT_CTRL_TCCCOMP_LTOE,
+  
+  /** Compare match if PCNT_CNT is greater than or equal to PCNT_TOP. */
+  tccCompGTOE           = _PCNT_CTRL_TCCCOMP_GTOE,
+  
+  /** Compare match if PCNT_CNT is less than, or equal to PCNT_TOP[15:8]], and greater
+   *  than, or equal to PCNT_TOP[7:0]. */
+  tccCompRange          = _PCNT_CTRL_TCCCOMP_RANGE
+} PCNT_TCCComp_Typedef;
+
+/** TCC initialization structure */
+typedef struct 
+{
+  /** Mode to operate in. */
+  PCNT_TCCMode_TypeDef      mode;
+  
+  /** Prescaler value for LFACLK in LFA mode */
+  PCNT_TCCPresc_Typedef     prescaler;
+  
+  /** Choose the event that will trigger a clear */
+  PCNT_TCCComp_Typedef      compare;
+  
+  /** PRS input to TCC module, either for gating the PCNT clock, triggering the TCC comparison, or both. */
+  PCNT_PRSSel_TypeDef       tccPRS;
+
+  /** TCC PRS input polarity. @n
+   *  False = Rising edge for comparison trigger, and PCNT clock gated when the PRS signal is high. @n
+   *  True = Falling edge for comparison trigger, and PCNT clock gated when the PRS signal is low. */
+  bool                      prsPolarity;
+  
+  /** Enable gating PCNT input clock through TCC PRS signal. 
+   *  Polarity selection is done through prsPolarity. */
+  bool                      prsGateEnable;
+} PCNT_TCC_TypeDef;
+
+#define PCNT_TCC_DEFAULT                                                                            \
+{                                                                                                   \
+  tccModeDisabled,                              /* Disabled by default */                           \
+  tccPrescDiv1,                                 /* Do not prescale LFA clock in LFA mode */         \
+  tccCompLTOE,                                  /* Clear when CNT <= TOP */                         \
+  pcntPRSCh0,                                   /* Select PRS channel 0 as input to TCC */          \
+  false,                                        /* PRS polarity is rising edge, and gate when 1 */  \
+  false                                         /* Do not gate the PCNT counter input */            \
+}
+
+#endif 
+/* defined(PCNT_CTRL_TCCMODE_DEFAULT) */
 
 /*******************************************************************************
  *****************************   PROTOTYPES   **********************************
@@ -266,8 +387,7 @@
   return pcnt->CNT;
 }
 
-
-#if defined( _PCNT_AUXCNT_MASK )
+#if defined(_PCNT_AUXCNT_MASK)
 /***************************************************************************//**
  * @brief
  *   Get auxiliary counter value.
@@ -284,11 +404,9 @@
 }
 #endif
 
-
 void PCNT_CounterReset(PCNT_TypeDef *pcnt);
 void PCNT_CounterTopSet(PCNT_TypeDef *pcnt, uint32_t count, uint32_t top);
 
-
 /***************************************************************************//**
  * @brief
  *   Set counter value.
@@ -315,18 +433,23 @@
   PCNT_CounterTopSet(pcnt, count, pcnt->TOP);
 }
 
-
 void PCNT_Enable(PCNT_TypeDef *pcnt, PCNT_Mode_TypeDef mode);
 void PCNT_FreezeEnable(PCNT_TypeDef *pcnt, bool enable);
 void PCNT_Init(PCNT_TypeDef *pcnt, const PCNT_Init_TypeDef *init);
 
-#if defined( _PCNT_INPUT_MASK )
+#if defined(PCNT_OVSCFG_FILTLEN_DEFAULT)
+void PCNT_FilterConfiguration(PCNT_TypeDef *pcnt, const PCNT_Filter_TypeDef *config, bool enable);
+#endif
+
+#if defined(_PCNT_INPUT_MASK)
 void PCNT_PRSInputEnable(PCNT_TypeDef *pcnt,
                          PCNT_PRSInput_TypeDef prsInput,
                          bool enable);
 #endif
 
-
+#if defined(PCNT_CTRL_TCCMODE_DEFAULT)
+void PCNT_TCCConfiguration(PCNT_TypeDef *pcnt, const PCNT_TCC_TypeDef *config);
+#endif
 /***************************************************************************//**
  * @brief
  *   Clear one or more pending PCNT interrupts.
@@ -343,7 +466,6 @@
   pcnt->IFC = flags;
 }
 
-
 /***************************************************************************//**
  * @brief
  *   Disable one or more PCNT interrupts.
@@ -357,10 +479,9 @@
  ******************************************************************************/
 __STATIC_INLINE void PCNT_IntDisable(PCNT_TypeDef *pcnt, uint32_t flags)
 {
-  pcnt->IEN &= ~(flags);
+  pcnt->IEN &= ~flags;
 }
 
-
 /***************************************************************************//**
  * @brief
  *   Enable one or more PCNT interrupts.
@@ -382,7 +503,6 @@
   pcnt->IEN |= flags;
 }
 
-
 /***************************************************************************//**
  * @brief
  *   Get pending PCNT interrupt flags.
@@ -402,7 +522,6 @@
   return pcnt->IF;
 }
 
-
 /***************************************************************************//**
  * @brief
  *   Get enabled and pending PCNT interrupt flags.
@@ -426,18 +545,17 @@
  ******************************************************************************/
 __STATIC_INLINE uint32_t PCNT_IntGetEnabled(PCNT_TypeDef *pcnt)
 {
-  uint32_t tmp = 0U;
+  uint32_t ien;
 
 
   /* Store pcnt->IEN in temporary variable in order to define explicit order
    * of volatile accesses. */
-  tmp = pcnt->IEN;
+  ien = pcnt->IEN;
 
   /* Bitwise AND of pending and enabled interrupts */
-  return pcnt->IF & tmp;
+  return pcnt->IF & ien;
 }
 
-
 /***************************************************************************//**
  * @brief
  *   Set one or more pending PCNT interrupts from SW.
@@ -456,7 +574,6 @@
 
 void PCNT_Reset(PCNT_TypeDef *pcnt);
 
-
 /***************************************************************************//**
  * @brief
  *   Get pulse counter top buffer value.
@@ -491,7 +608,6 @@
 
 void PCNT_TopSet(PCNT_TypeDef *pcnt, uint32_t val);
 
-
 /** @} (end addtogroup PCNT) */
 /** @} (end addtogroup EM_Library) */
 
@@ -500,4 +616,4 @@
 #endif
 
 #endif /* defined(PCNT_COUNT) && (PCNT_COUNT > 0) */
-#endif /* __SILICON_LABS_EM_PCNT_H_ */
+#endif /* __SILICON_LABS_EM_PCNT_H__ */

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_prs.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_prs.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /***************************************************************************//**
  * @file em_prs.h
  * @brief Peripheral Reflex System (PRS) peripheral API
- * @version 3.20.12
+ * @version 4.2.1
  *******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
  *******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,9 +30,8 @@
  *
  ******************************************************************************/
 
-
-#ifndef __SILICON_LABS_EM_PRS_H_
-#define __SILICON_LABS_EM_PRS_H_
+#ifndef __SILICON_LABS_EM_PRS_H__
+#define __SILICON_LABS_EM_PRS_H__
 
 #include "em_device.h"
 #if defined(PRS_COUNT) && (PRS_COUNT > 0)
@@ -128,4 +127,4 @@
 #endif
 
 #endif /* defined(PRS_COUNT) && (PRS_COUNT > 0) */
-#endif /* __SILICON_LABS_EM_PRS_H_ */
+#endif /* __SILICON_LABS_EM_PRS_H__ */

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_rmu.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_rmu.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /***************************************************************************//**
  * @file em_rmu.h
  * @brief Reset Management Unit (RMU) peripheral API
- * @version 3.20.12
+ * @version 4.2.1
  *******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
  *******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,12 +30,12 @@
  *
  ******************************************************************************/
 
-
-#ifndef __SILICON_LABS_EM_RMU_H_
-#define __SILICON_LABS_EM_RMU_H_
+#ifndef __SILICON_LABS_EM_RMU_H__
+#define __SILICON_LABS_EM_RMU_H__
 
 #include "em_device.h"
 #if defined(RMU_COUNT) && (RMU_COUNT > 0)
+#include "em_assert.h"
 
 #include <stdbool.h>
 
@@ -57,15 +57,43 @@
  ********************************   ENUMS   ************************************
  ******************************************************************************/
 
+/** RMU reset modes */
+typedef enum
+{
+#if defined(_RMU_CTRL_PINRMODE_MASK)
+  rmuResetModeDisabled = _RMU_CTRL_PINRMODE_DISABLED,
+  rmuResetModeLimited  = _RMU_CTRL_PINRMODE_LIMITED,
+  rmuResetModeExtended = _RMU_CTRL_PINRMODE_EXTENDED,
+  rmuResetModeFull     = _RMU_CTRL_PINRMODE_FULL,
+#else
+  rmuResetModeClear    = 0,
+  rmuResetModeSet      = 1,
+#endif
+} RMU_ResetMode_TypeDef;
+
 /** RMU controlled peripheral reset control and reset source control */
 typedef enum
 {
-#if defined( RMU_CTRL_BURSTEN )
-  /** Reset control over Backup Power Domain */
-  rmuResetBU = _RMU_CTRL_BURSTEN_SHIFT,
+#if defined(RMU_CTRL_BURSTEN)
+  rmuResetBU = _RMU_CTRL_BURSTEN_MASK,              /**< Reset control over Backup Power domain select */
+#endif
+#if defined(RMU_CTRL_LOCKUPRDIS)
+  rmuResetLockUp = _RMU_CTRL_LOCKUPRDIS_MASK,       /**< Cortex lockup reset select */
+#elif defined(_RMU_CTRL_LOCKUPRMODE_MASK)
+  rmuResetLockUp = _RMU_CTRL_LOCKUPRMODE_MASK,      /**< Cortex lockup reset select */
 #endif
-  /** Allow Cortex-M3 lock up signal */
-  rmuResetLockUp = _RMU_CTRL_LOCKUPRDIS_SHIFT
+#if defined(_RMU_CTRL_WDOGRMODE_MASK)
+  rmuResetWdog = _RMU_CTRL_WDOGRMODE_MASK,          /**< WDOG reset select */
+#endif
+#if defined(_RMU_CTRL_LOCKUPRMODE_MASK)
+  rmuResetCoreLockup = _RMU_CTRL_LOCKUPRMODE_MASK,  /**< Cortex lockup reset select */
+#endif
+#if defined(_RMU_CTRL_SYSRMODE_MASK)
+  rmuResetSys = _RMU_CTRL_SYSRMODE_MASK,            /**< SYSRESET select */
+#endif
+#if defined(_RMU_CTRL_PINRMODE_MASK)
+  rmuResetPin = _RMU_CTRL_PINRMODE_MASK,            /**< Pin reset select */
+#endif
 } RMU_Reset_TypeDef;
 
 /*******************************************************************************
@@ -75,10 +103,42 @@
 /** RMU_LockupResetDisable kept for backwards compatibility */
 #define RMU_LockupResetDisable(A) RMU_ResetControl(rmuResetLockUp, A)
 
-void RMU_ResetControl(RMU_Reset_TypeDef reset, bool enable);
+void RMU_ResetControl(RMU_Reset_TypeDef reset, RMU_ResetMode_TypeDef mode);
 void RMU_ResetCauseClear(void);
 uint32_t RMU_ResetCauseGet(void);
 
+#if defined(_RMU_CTRL_RESETSTATE_MASK)
+/***************************************************************************//**
+ * @brief
+ *   Set user reset state. This state is reset only by a Power-on-reset and a
+ *   pin reset.
+ *
+ * @param[in] userState User state to set
+ ******************************************************************************/
+__STATIC_INLINE void RMU_UserResetStateSet(uint32_t userState)
+{
+  EFM_ASSERT(!(userState
+               & ~(_RMU_CTRL_RESETSTATE_MASK >> _RMU_CTRL_RESETSTATE_SHIFT)));
+  RMU->CTRL = (RMU->CTRL & ~_RMU_CTRL_RESETSTATE_MASK)
+              | (userState << _RMU_CTRL_RESETSTATE_SHIFT);
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Get user reset state. This state is reset only by a Power-on-reset and a
+ *   pin reset.
+ *
+ * @return
+ *   Reset surviving user state
+ ******************************************************************************/
+__STATIC_INLINE uint32_t RMU_UserResetStateGet(void)
+{
+  uint32_t userState = (RMU->CTRL & _RMU_CTRL_RESETSTATE_MASK)
+                       >> _RMU_CTRL_RESETSTATE_SHIFT;
+  return userState;
+}
+#endif
+
 /** @} (end addtogroup RMU) */
 /** @} (end addtogroup EM_Library) */
 
@@ -87,4 +147,4 @@
 #endif
 
 #endif /* defined(RMU_COUNT) && (RMU_COUNT > 0) */
-#endif /* __SILICON_LABS_EM_RMU_H_ */
+#endif /* __SILICON_LABS_EM_RMU_H__ */

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_rtc.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_rtc.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /***************************************************************************//**
  * @file em_rtc.h
  * @brief Real Time Counter (RTC) peripheral API
- * @version 3.20.12
+ * @version 4.2.1
  *******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
  *******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,9 +30,8 @@
  *
  ******************************************************************************/
 
-
-#ifndef __SILICON_LABS_EM_RTC_H_
-#define __SILICON_LABS_EM_RTC_H_
+#ifndef __SILICON_LABS_EM_RTC_H__
+#define __SILICON_LABS_EM_RTC_H__
 
 #include "em_device.h"
 #if defined(RTC_COUNT) && (RTC_COUNT > 0)
@@ -66,11 +65,12 @@
 } RTC_Init_TypeDef;
 
 /** Suggested default config for RTC init structure. */
-#define RTC_INIT_DEFAULT                                       \
-  { true,    /* Start counting when init done */               \
-    false,   /* Disable updating during debug halt */          \
-    true     /* Restart counting from 0 when reaching COMP0 */ \
-  }
+#define RTC_INIT_DEFAULT                                     \
+{                                                            \
+  true,    /* Start counting when init done */               \
+  false,   /* Disable updating during debug halt */          \
+  true     /* Restart counting from 0 when reaching COMP0 */ \
+}
 
 
 /*******************************************************************************
@@ -89,7 +89,7 @@
  ******************************************************************************/
 __STATIC_INLINE uint32_t RTC_CounterGet(void)
 {
-  return(RTC->CNT);
+  return RTC->CNT;
 }
 
 void RTC_CounterReset(void);
@@ -123,7 +123,7 @@
  ******************************************************************************/
 __STATIC_INLINE void RTC_IntDisable(uint32_t flags)
 {
-  RTC->IEN &= ~(flags);
+  RTC->IEN &= ~flags;
 }
 
 
@@ -160,7 +160,30 @@
  ******************************************************************************/
 __STATIC_INLINE uint32_t RTC_IntGet(void)
 {
-  return(RTC->IF);
+  return RTC->IF;
+}
+
+
+/***************************************************************************//**
+ * @brief
+ *   Get enabled and pending RTC interrupt flags.
+ *   Useful for handling more interrupt sources in the same interrupt handler.
+ *
+ * @note
+ *   Interrupt flags are not cleared by the use of this function.
+ *
+ * @return
+ *   Pending and enabled RTC interrupt sources
+ *   The return value is the bitwise AND of
+ *   - the enabled interrupt sources in RTC_IEN and
+ *   - the pending interrupt flags RTC_IF
+ ******************************************************************************/
+__STATIC_INLINE uint32_t RTC_IntGetEnabled(void)
+{
+  uint32_t ien;
+
+  ien = RTC->IEN;
+  return RTC->IF & ien;
 }
 
 
@@ -188,4 +211,4 @@
 #endif
 
 #endif /* defined(RTC_COUNT) && (RTC_COUNT > 0) */
-#endif /* __SILICON_LABS_EM_RTC_H_ */
+#endif /* __SILICON_LABS_EM_RTC_H__ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_rtcc.h	Fri Jan 15 07:45:16 2016 +0000
@@ -0,0 +1,696 @@
+/***************************************************************************//**
+ * @file
+ * @brief Real Time Counter (RTCC) peripheral API.
+ * @version 4.2.1
+ *******************************************************************************
+ * @section License
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
+ *******************************************************************************
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
+ * obligation to support this Software. Silicon Labs is providing the
+ * Software "AS IS", with no express or implied warranties of any kind,
+ * including, but not limited to, any implied warranties of merchantability
+ * or fitness for any particular purpose or warranties against infringement
+ * of any proprietary rights of a third party.
+ *
+ * Silicon Labs will not be liable for any consequential, incidental, or
+ * special damages, or any other relief, or for any claim by any third party,
+ * arising from your use of this Software.
+ *
+ ******************************************************************************/
+
+#ifndef __SILICON_LABS_EM_RTCC_H__
+#define __SILICON_LABS_EM_RTCC_H__
+
+#include "em_device.h"
+#if defined( RTCC_COUNT ) && ( RTCC_COUNT == 1 )
+
+#include <stdbool.h>
+#include "em_assert.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************************************************************//**
+ * @addtogroup EM_Library
+ * @{
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * @addtogroup RTCC
+ * @{
+ ******************************************************************************/
+
+/*******************************************************************************
+ *********************************   ENUM   ************************************
+ ******************************************************************************/
+
+/** Operational mode of the counter. */
+typedef enum
+{
+  /** Normal counter mode. The counter is incremented by 1 for each tick. */
+  rtccCntModeNormal = _RTCC_CTRL_CNTTICK_PRESC,
+
+  /** Calendar mode. Refer to the RTCC chapter of the Reference Manual for more
+   *  details on the calendar mode. */
+  rtccCntModeCalendar = _RTCC_CTRL_CNTTICK_CCV0MATCH
+} RTCC_CntMode_TypeDef;
+
+/** Counter prescaler selection. */
+typedef enum
+{
+  rtccCntPresc_1     = _RTCC_CTRL_CNTPRESC_DIV1,      /**< Divide clock by 1. */
+  rtccCntPresc_2     = _RTCC_CTRL_CNTPRESC_DIV2,      /**< Divide clock by 2. */
+  rtccCntPresc_4     = _RTCC_CTRL_CNTPRESC_DIV4,      /**< Divide clock by 4. */
+  rtccCntPresc_8     = _RTCC_CTRL_CNTPRESC_DIV8,      /**< Divide clock by 8. */
+  rtccCntPresc_16    = _RTCC_CTRL_CNTPRESC_DIV16,     /**< Divide clock by 16. */
+  rtccCntPresc_32    = _RTCC_CTRL_CNTPRESC_DIV32,     /**< Divide clock by 32. */
+  rtccCntPresc_64    = _RTCC_CTRL_CNTPRESC_DIV64,     /**< Divide clock by 64. */
+  rtccCntPresc_128   = _RTCC_CTRL_CNTPRESC_DIV128,    /**< Divide clock by 128. */
+  rtccCntPresc_256   = _RTCC_CTRL_CNTPRESC_DIV256,    /**< Divide clock by 256. */
+  rtccCntPresc_512   = _RTCC_CTRL_CNTPRESC_DIV512,    /**< Divide clock by 512. */
+  rtccCntPresc_1024  = _RTCC_CTRL_CNTPRESC_DIV1024,   /**< Divide clock by 1024. */
+  rtccCntPresc_2048  = _RTCC_CTRL_CNTPRESC_DIV2048,   /**< Divide clock by 2048. */
+  rtccCntPresc_4096  = _RTCC_CTRL_CNTPRESC_DIV4096,   /**< Divide clock by 4096. */
+  rtccCntPresc_8192  = _RTCC_CTRL_CNTPRESC_DIV8192,   /**< Divide clock by 8192. */
+  rtccCntPresc_16384 = _RTCC_CTRL_CNTPRESC_DIV16384,  /**< Divide clock by 16384. */
+  rtccCntPresc_32768 = _RTCC_CTRL_CNTPRESC_DIV32768   /**< Divide clock by 32768. */
+} RTCC_CntPresc_TypeDef;
+
+
+/** Prescaler mode of the RTCC counter. */
+typedef enum
+{
+  /** CNT register ticks according to the prescaler value. */
+  rtccCntTickPresc = _RTCC_CTRL_CNTTICK_PRESC,
+
+  /** CNT register ticks when PRECNT matches the 15 least significant bits of
+   *  ch. 0 CCV register. */
+  rtccCntTickCCV0Match = _RTCC_CTRL_CNTTICK_CCV0MATCH
+} RTCC_PrescMode_TypeDef;
+
+
+/** Capture/Compare channel mode. */
+typedef enum
+{
+  rtccCapComChModeOff     = _RTCC_CC_CTRL_MODE_OFF,           /**< Capture/Compare channel turned off. */
+  rtccCapComChModeCapture = _RTCC_CC_CTRL_MODE_INPUTCAPTURE,  /**< Capture mode. */
+  rtccCapComChModeCompare = _RTCC_CC_CTRL_MODE_OUTPUTCOMPARE, /**< Compare mode. */
+} RTCC_CapComChMode_TypeDef;
+
+/** Compare match output action mode. */
+typedef enum
+{
+  rtccCompMatchOutActionPulse  = _RTCC_CC_CTRL_CMOA_PULSE,  /**< Generate a pulse. */
+  rtccCompMatchOutActionToggle = _RTCC_CC_CTRL_CMOA_TOGGLE, /**< Toggle output. */
+  rtccCompMatchOutActionClear  = _RTCC_CC_CTRL_CMOA_CLEAR,  /**< Clear output. */
+  rtccCompMatchOutActionSet    = _RTCC_CC_CTRL_CMOA_SET     /**< Set output. */
+} RTCC_CompMatchOutAction_TypeDef;
+
+
+/** PRS input sources. */
+typedef enum
+{
+  rtccPRSCh0 = _RTCC_CC_CTRL_PRSSEL_PRSCH0,   /**< PRS channel 0. */
+  rtccPRSCh1 = _RTCC_CC_CTRL_PRSSEL_PRSCH1,   /**< PRS channel 1. */
+  rtccPRSCh2 = _RTCC_CC_CTRL_PRSSEL_PRSCH2,   /**< PRS channel 2. */
+  rtccPRSCh3 = _RTCC_CC_CTRL_PRSSEL_PRSCH3,   /**< PRS channel 3. */
+  rtccPRSCh4 = _RTCC_CC_CTRL_PRSSEL_PRSCH4,   /**< PRS channel 4. */
+  rtccPRSCh5 = _RTCC_CC_CTRL_PRSSEL_PRSCH5,   /**< PRS channel 5. */
+  rtccPRSCh6 = _RTCC_CC_CTRL_PRSSEL_PRSCH6,   /**< PRS channel 6. */
+  rtccPRSCh7 = _RTCC_CC_CTRL_PRSSEL_PRSCH7,   /**< PRS channel 7. */
+  rtccPRSCh8 = _RTCC_CC_CTRL_PRSSEL_PRSCH8,   /**< PRS channel 8. */
+  rtccPRSCh9 = _RTCC_CC_CTRL_PRSSEL_PRSCH9,   /**< PRS channel 9. */
+  rtccPRSCh10 = _RTCC_CC_CTRL_PRSSEL_PRSCH10, /**< PRS channel 10. */
+  rtccPRSCh11 = _RTCC_CC_CTRL_PRSSEL_PRSCH11  /**< PRS channel 11. */
+} RTCC_PRSSel_TypeDef;
+
+
+/** Input edge select. */
+typedef enum
+{
+  rtccInEdgeRising  = _RTCC_CC_CTRL_ICEDGE_RISING,  /**< Rising edges detected. */
+  rtccInEdgeFalling = _RTCC_CC_CTRL_ICEDGE_FALLING, /**< Falling edges detected. */
+  rtccInEdgeBoth    = _RTCC_CC_CTRL_ICEDGE_BOTH,    /**< Both edges detected. */
+  rtccInEdgeNone    = _RTCC_CC_CTRL_ICEDGE_NONE     /**< No edge detection, signal is left as is. */
+} RTCC_InEdgeSel_TypeDef;
+
+
+/** Capture/Compare channel compare mode. */
+typedef enum
+{
+  /** CCVx is compared with the CNT register. */
+  rtccCompBaseCnt = _RTCC_CC_CTRL_COMPBASE_CNT,
+
+  /** CCVx is compared with a CNT[16:0] and PRECNT[14:0]. */
+  rtccCompBasePreCnt = _RTCC_CC_CTRL_COMPBASE_PRECNT
+} RTCC_CompBase_TypeDef;
+
+  /** Day compare mode. */
+typedef enum
+{
+  rtccDayCompareModeMonth = _RTCC_CC_CTRL_DAYCC_MONTH,  /**< Day of month is selected for Capture/Compare. */
+  rtccDayCompareModeWeek  = _RTCC_CC_CTRL_DAYCC_WEEK    /**< Day of week is selected for Capture/Compare. */
+} RTCC_DayCompareMode_TypeDef;
+
+/*******************************************************************************
+ *******************************   STRUCTS   ***********************************
+ ******************************************************************************/
+
+/** RTCC initialization structure. */
+typedef struct
+{
+  /** Enable/disable counting when initialization is completed. */
+  bool                   enable;
+
+  /** Enable/disable timer counting during debug halt. */
+  bool                   debugRun;
+
+  /** Enable/disable precounter wrap on ch. 0 CCV value. */
+  bool                   precntWrapOnCCV0;
+
+  /** Enable/disable counter wrap on ch. 1 CCV value. */
+  bool                   cntWrapOnCCV1;
+
+  /** Counter prescaler. */
+  RTCC_CntPresc_TypeDef  presc;
+
+  /** Prescaler mode. */
+  RTCC_PrescMode_TypeDef prescMode;
+
+#if defined(_RTCC_CTRL_BUMODETSEN_MASK)
+  /** Enable/disable storing RTCC counter value in RTCC_CCV2 upon backup mode
+   *  entry. */
+  bool                   enaBackupModeSet;
+#endif
+
+  /** Enable/disable the check that sets the OSCFFAIL interrupt flag if no
+   *  LFCLK-RTCC ticks are detected within one ULFRCO cycles. */
+  bool                   enaOSCFailDetect;
+
+  /** Select the operational mode of the counter. */
+  RTCC_CntMode_TypeDef   cntMode;
+
+  /** Disable leap year correction for the calendar mode. When this parameter is
+   *  set to false, February has 29 days if (year % 4 == 0). If true, February
+   *  always has 28 days. */
+  bool                   disLeapYearCorr;
+} RTCC_Init_TypeDef;
+
+
+/** RTCC capture/compare channel configuration structure. */
+typedef struct
+{
+  /** Select the mode of the Capture/Compare channel. */
+  RTCC_CapComChMode_TypeDef        chMode;
+
+  /** Compare mode channel match output action. */
+  RTCC_CompMatchOutAction_TypeDef  compMatchOutAction;
+
+  /** Capture mode channel PRS input channel selection. */
+  RTCC_PRSSel_TypeDef              prsSel;
+
+  /** Capture mode channel input edge selection. */
+  RTCC_InEdgeSel_TypeDef           inputEdgeSel;
+
+  /** Comparison base of the channel in compare mode. */
+  RTCC_CompBase_TypeDef            compBase;
+
+  /** The COMPMASK (5 bit) most significant bits of the compare value will not
+   *  be subject to comparison.  */
+  uint8_t                          compMask;
+
+  /** Day compare mode. */
+  RTCC_DayCompareMode_TypeDef      dayCompMode;
+} RTCC_CCChConf_TypeDef;
+
+
+/*******************************************************************************
+ *******************************   DEFINES   ***********************************
+ ******************************************************************************/
+
+/** Default RTCC init structure. */
+#if defined(_RTCC_CTRL_BUMODETSEN_MASK)
+#define RTCC_INIT_DEFAULT                                                   \
+{                                                                           \
+  true,     /* Start counting when init done.                           */  \
+  false,    /* Disable RTCC during debug halt.                          */  \
+  false,    /* Disable precounter wrap on ch. 0 CCV value.              */  \
+  false,    /* Disable counter wrap on ch. 1 CCV value.                 */  \
+  rtccCntPresc_32, /* 977 us per tick.                                  */  \
+  rtccCntTickPresc, /* Counter increments according to prescaler value. */  \
+  false,    /* No RTCC storage on backup mode entry.                    */  \
+  false,    /* No RTCC oscillator failure detection.                    */  \
+  rtccCntModeNormal, /* Normal RTCC mode.                               */  \
+  false,    /* No leap year correction.                                 */  \
+}
+#else
+#define RTCC_INIT_DEFAULT                                                   \
+{                                                                           \
+  true,     /* Start counting when init done.                           */  \
+  false,    /* Disable RTCC during debug halt.                          */  \
+  false,    /* Disable precounter wrap on ch. 0 CCV value.              */  \
+  false,    /* Disable counter wrap on ch. 1 CCV value.                 */  \
+  rtccCntPresc_32, /* 977 us per tick.                                  */  \
+  rtccCntTickPresc, /* Counter increments according to prescaler value. */  \
+  false,    /* No RTCC oscillator failure detection.                    */  \
+  rtccCntModeNormal, /* Normal RTCC mode.                               */  \
+  false,    /* No leap year correction.                                 */  \
+}
+#endif
+
+/** Default RTCC channel output compare init structure. */
+#define RTCC_CH_INIT_COMPARE_DEFAULT                                        \
+{                                                                           \
+  rtccCapComChModeCompare,     /* Select output compare mode.     */        \
+  rtccCompMatchOutActionPulse, /* Create pulse on compare match.  */        \
+  rtccPRSCh0,                  /* PRS channel 0 (not used).       */        \
+  rtccInEdgeNone,              /* No edge detection.              */        \
+  rtccCompBaseCnt,             /* Counter comparison base.        */        \
+  0,                           /* No compare mask bits set.       */        \
+  rtccDayCompareModeMonth      /* Don't care */                             \
+}
+
+/** Default RTCC channel input capture init structure. */
+#define RTCC_CH_INIT_CAPTURE_DEFAULT                                        \
+{                                                                           \
+  rtccCapComChModeCapture,     /* Select input capture mode.      */        \
+  rtccCompMatchOutActionPulse, /* Create pulse on capture.        */        \
+  rtccPRSCh0,                  /* PRS channel 0.                  */        \
+  rtccInEdgeRising,            /* Rising edge detection.          */        \
+  rtccCompBaseCnt,             /* Don't care.                     */        \
+  0,                           /* Don't care.                     */        \
+  rtccDayCompareModeMonth      /* Don't care                      */        \
+}
+
+/** Validation of valid RTCC channel for assert statements. */
+#define RTCC_CH_VALID( ch )    ( ( ch ) < 3 )
+
+/*******************************************************************************
+ *****************************   PROTOTYPES   **********************************
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * @brief
+ *   Get RTCC capture/compare register value (CCV) for selected channel.
+ *
+ * @param[in] ch
+ *   Channel selector.
+ *
+ * @return
+ *   Capture/compare register value.
+ ******************************************************************************/
+__STATIC_INLINE uint32_t RTCC_ChannelCCVGet( int ch )
+{
+  EFM_ASSERT( RTCC_CH_VALID( ch ) );
+  return RTCC->CC[ ch ].CCV;
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Set RTCC capture/compare register value (CCV) for selected channel.
+ *
+ * @param[in] ch
+ *   Channel selector.
+ *
+ * @param[in] value
+ *   CCV value.
+ ******************************************************************************/
+__STATIC_INLINE void RTCC_ChannelCCVSet( int ch, uint32_t value )
+{
+  EFM_ASSERT( RTCC_CH_VALID( ch ) );
+  RTCC->CC[ ch ].CCV = value;
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Get the calendar DATE register content for selected channel.
+ *
+ * @param[in] ch
+ *   Channel selector.
+ *
+ * @return
+ *   DATE register value.
+ ******************************************************************************/
+__STATIC_INLINE uint32_t RTCC_ChannelDateGet( int ch )
+{
+  EFM_ASSERT( RTCC_CH_VALID( ch ) );
+  return RTCC->CC[ ch ].DATE;
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Set the calendar DATE register for selected channel.
+ *
+ * @param[in] ch
+ *   Channel selector.
+ *
+ * @param[in] date
+ *   DATE value.
+ ******************************************************************************/
+__STATIC_INLINE void RTCC_ChannelDateSet( int ch, uint32_t date )
+{
+  EFM_ASSERT( RTCC_CH_VALID( ch ) );
+  RTCC->CC[ ch ].DATE = date;
+}
+
+void RTCC_ChannelInit( int ch, RTCC_CCChConf_TypeDef const *confPtr );
+
+/***************************************************************************//**
+ * @brief
+ *   Get the calendar TIME register content for selected channel.
+ *
+ * @param[in] ch
+ *   Channel selector.
+ *
+ * @return
+ *   TIME register value.
+ ******************************************************************************/
+__STATIC_INLINE uint32_t RTCC_ChannelTimeGet( int ch )
+{
+  EFM_ASSERT( RTCC_CH_VALID( ch ) );
+  return RTCC->CC[ ch ].TIME;
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Set the calendar TIME register for selected channel.
+ *
+ * @param[in] ch
+ *   Channel selector.
+ *
+ * @param[in] time
+ *   TIME value.
+ ******************************************************************************/
+__STATIC_INLINE void RTCC_ChannelTimeSet( int ch, uint32_t time )
+{
+  EFM_ASSERT( RTCC_CH_VALID( ch ) );
+  RTCC->CC[ ch ].TIME = time;
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Get the combined CNT/PRECNT register content.
+ *
+ * @return
+ *   CNT/PRECNT register value.
+ ******************************************************************************/
+__STATIC_INLINE uint32_t RTCC_CombinedCounterGet( void )
+{
+  return RTCC->COMBCNT;
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Get RTCC counter value.
+ *
+ * @return
+ *   Current RTCC counter value.
+ ******************************************************************************/
+__STATIC_INLINE uint32_t RTCC_CounterGet( void )
+{
+  return RTCC->CNT;
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Set RTCC CNT counter.
+ *
+ * @param[in] value
+ *   CNT value.
+ ******************************************************************************/
+__STATIC_INLINE void RTCC_CounterSet( uint32_t value )
+{
+  RTCC->CNT = value;
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Get DATE register value.
+ *
+ * @return
+ *   Current DATE register value.
+ ******************************************************************************/
+__STATIC_INLINE uint32_t RTCC_DateGet( void )
+{
+  return RTCC->DATE;
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Set RTCC DATE register.
+ *
+ * @param[in] date
+ *   DATE value.
+ ******************************************************************************/
+__STATIC_INLINE void RTCC_DateSet( uint32_t date )
+{
+  RTCC->DATE = date;
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Enable/disable EM4 wakeup capability.
+ *
+ * @param[in] enable
+ *   True to enable EM4 wakeup, false to disable.
+ ******************************************************************************/
+__STATIC_INLINE void RTCC_EM4WakeupEnable( bool enable )
+{
+  if ( enable )
+  {
+    RTCC->EM4WUEN = RTCC_EM4WUEN_EM4WU;
+  }
+  else
+  {
+    RTCC->EM4WUEN = 0;
+  }
+}
+
+void RTCC_Enable( bool enable );
+
+void RTCC_Init( const RTCC_Init_TypeDef *init );
+
+/***************************************************************************//**
+ * @brief
+ *   Clear one or more pending RTCC interrupts.
+ *
+ * @param[in] flags
+ *   RTCC interrupt sources to clear. Use a set of interrupt flags OR-ed
+ *   together to clear multiple interrupt sources.
+ ******************************************************************************/
+__STATIC_INLINE void RTCC_IntClear( uint32_t flags )
+{
+  RTCC->IFC = flags;
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Disable one or more RTCC interrupts.
+ *
+ * @param[in] flags
+ *   RTCC interrupt sources to disable. Use a set of interrupt flags OR-ed
+ *   together to disable multiple interrupt.
+ ******************************************************************************/
+__STATIC_INLINE void RTCC_IntDisable( uint32_t flags )
+{
+  RTCC->IEN &= ~flags;
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Enable one or more RTCC interrupts.
+ *
+ * @note
+ *   Depending on the use, a pending interrupt may already be set prior to
+ *   enabling the interrupt. Consider using RTCC_IntClear() prior to enabling
+ *   if such a pending interrupt should be ignored.
+ *
+ * @param[in] flags
+ *   RTCC interrupt sources to enable. Use a set of interrupt flags OR-ed
+ *   together to set multiple interrupt.
+ ******************************************************************************/
+__STATIC_INLINE void RTCC_IntEnable( uint32_t flags )
+{
+  RTCC->IEN |= flags;
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Get pending RTCC interrupt flags.
+ *
+ * @note
+ *   The event bits are not cleared by the use of this function.
+ *
+ * @return
+ *   Pending RTCC interrupt sources. Returns a set of interrupt flags OR-ed
+ *   together for the interrupt sources set.
+ ******************************************************************************/
+__STATIC_INLINE uint32_t RTCC_IntGet( void )
+{
+  return RTCC->IF;
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Get enabled and pending RTCC interrupt flags.
+ *
+ * @details
+ *   Useful for handling more interrupt sources in the same interrupt handler.
+ *
+ * @return
+ *   Pending and enabled RTCC interrupt sources. Returns a set of interrupt
+ *   flags OR-ed together for the interrupt sources set.
+ ******************************************************************************/
+__STATIC_INLINE uint32_t RTCC_IntGetEnabled( void )
+{
+  uint32_t tmp;
+
+  tmp = RTCC->IEN;
+
+  /* Bitwise AND of pending and enabled interrupt flags. */
+  return RTCC->IF & tmp;
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Set one or more pending RTCC interrupts from SW.
+ *
+ * @param[in] flags
+ *   RTCC interrupt sources to set to pending. Use a set of interrupt flags
+ *   (RTCC_IFS_nnn).
+ ******************************************************************************/
+__STATIC_INLINE void RTCC_IntSet( uint32_t flags )
+{
+  RTCC->IFS = flags;
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Lock RTCC registers.
+ *
+ * @note
+ *   When RTCC registers are locked, RTCC_CTRL, RTCC_PRECNT, RTCC_CNT,
+ *   RTCC_TIME, RTCC_DATE, RTCC_IEN, RTCC_POWERDOWN and RTCC_CCx_XXX registers
+ *   can not be written to.
+ ******************************************************************************/
+__STATIC_INLINE void RTCC_Lock( void )
+{
+  RTCC->LOCK = RTCC_LOCK_LOCKKEY_LOCK;
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Get RTCC pre-counter value.
+ *
+ * @return
+ *   Current RTCC pre-counter value.
+ ******************************************************************************/
+__STATIC_INLINE uint32_t RTCC_PreCounterGet( void )
+{
+  return RTCC->PRECNT;
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Set RTCC pre-counter value.
+ *
+ * @param[in] preCntVal
+ *   RTCC pre-counter value to be set.
+ ******************************************************************************/
+__STATIC_INLINE void RTCC_PreCounterSet( uint32_t preCntVal )
+{
+  RTCC->PRECNT = preCntVal;
+}
+
+void RTCC_Reset( void );
+
+/***************************************************************************//**
+ * @brief
+ *   Power down the retention ram.
+ *
+ * @note
+ *   Once retention ram is powered down, it cannot be powered up again.
+ ******************************************************************************/
+__STATIC_INLINE void RTCC_RetentionRamPowerDown( void )
+{
+  RTCC->POWERDOWN = RTCC_POWERDOWN_RAM;
+}
+
+void RTCC_StatusClear( void );
+
+/***************************************************************************//**
+ * @brief
+ *   Get STATUS register value.
+ *
+ * @return
+ *   Current STATUS register value.
+ ******************************************************************************/
+__STATIC_INLINE uint32_t RTCC_StatusGet( void )
+{
+  while ( RTCC->SYNCBUSY & RTCC_SYNCBUSY_CMD )
+  {
+    // Wait for syncronization.
+  }
+  return RTCC->STATUS;
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Get TIME register value.
+ *
+ * @return
+ *   Current TIME register value.
+ ******************************************************************************/
+__STATIC_INLINE uint32_t RTCC_TimeGet( void )
+{
+  return RTCC->TIME;
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Set RTCC TIME register.
+ *
+ * @param[in] time
+ *   TIME value.
+ ******************************************************************************/
+__STATIC_INLINE void RTCC_TimeSet( uint32_t time )
+{
+  RTCC->TIME = time;
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Unlock RTCC registers.
+ *
+ * @note
+ *   When RTCC registers are locked, RTCC_CTRL, RTCC_PRECNT, RTCC_CNT,
+ *   RTCC_TIME, RTCC_DATE, RTCC_IEN, RTCC_POWERDOWN and RTCC_CCx_XXX registers
+ *   can not be written to.
+ ******************************************************************************/
+__STATIC_INLINE void RTCC_Unlock( void )
+{
+  RTCC->LOCK = RTCC_LOCK_LOCKKEY_UNLOCK;
+}
+
+/** @} (end addtogroup RTCC) */
+/** @} (end addtogroup EM_Library) */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* defined( RTCC_COUNT ) && ( RTC_COUNT == 1 ) */
+#endif /* __SILICON_LABS_EM_RTCC_H__ */

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_system.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_system.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /***************************************************************************//**
  * @file em_system.h
  * @brief System API
- * @version 3.20.12
+ * @version 4.2.1
  *******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
  *******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,9 +30,8 @@
  *
  ******************************************************************************/
 
-
-#ifndef __SILICON_LABS_EM_SYSTEM_H_
-#define __SILICON_LABS_EM_SYSTEM_H_
+#ifndef __SILICON_LABS_EM_SYSTEM_H__
+#define __SILICON_LABS_EM_SYSTEM_H__
 
 #include <stdbool.h>
 #include "em_device.h"
@@ -55,28 +54,102 @@
  ********************************   ENUMS   ************************************
  ******************************************************************************/
 
-/** EFM32 part family identifiers. */
+/** Family identifiers. */
 typedef enum
 {
-#if defined( _DEVINFO_PART_DEVICE_FAMILY_G )
+/* New style family #defines */
+#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32G)
+  systemPartFamilyEfm32Gecko   = _DEVINFO_PART_DEVICE_FAMILY_EFM32G,      /**< EFM32 Gecko Device Family */
+#endif
+#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32GG)
+  systemPartFamilyEfm32Giant   = _DEVINFO_PART_DEVICE_FAMILY_EFM32GG,     /**< EFM32 Giant Gecko Device Family */
+#endif
+#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32TG)
+  systemPartFamilyEfm32Tiny    = _DEVINFO_PART_DEVICE_FAMILY_EFM32TG,     /**< EFM32 Tiny Gecko Device Family */
+#endif
+#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32LG)
+  systemPartFamilyEfm32Leopard = _DEVINFO_PART_DEVICE_FAMILY_EFM32LG,     /**< EFM32 Leopard Gecko Device Family */
+#endif
+#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32WG)
+  systemPartFamilyEfm32Wonder  = _DEVINFO_PART_DEVICE_FAMILY_EFM32WG,     /**< EFM32 Wonder Gecko Device Family */
+#endif
+#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32ZG)
+  systemPartFamilyEfm32Zero    = _DEVINFO_PART_DEVICE_FAMILY_EFM32ZG,     /**< EFM32 Zero Gecko Device Family */
+#endif
+#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32HG)
+  systemPartFamilyEfm32Happy   = _DEVINFO_PART_DEVICE_FAMILY_EFM32HG,     /**< EFM32 Happy Gecko Device Family */
+#endif
+#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B)
+  systemPartFamilyEfm32Pearl1B = _DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B,   /**< EFM32 Pearl Gecko Gen1 Basic Device Family */
+#endif
+#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B)
+  systemPartFamilyEfm32Jade1B  = _DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B,   /**< EFM32 Jade Gecko Gen1 Basic Device Family */
+#endif
+#if defined(_DEVINFO_PART_DEVICE_FAMILY_EZR32WG)
+  systemPartFamilyEzr32Wonder  = _DEVINFO_PART_DEVICE_FAMILY_EZR32WG,     /**< EZR32 Wonder Device Family */
+#endif
+#if defined(_DEVINFO_PART_DEVICE_FAMILY_EZR32LG)
+  systemPartFamilyEzr32Leopard = _DEVINFO_PART_DEVICE_FAMILY_EZR32LG,     /**< EZR32 Leopard Device Family */
+#endif
+#if defined(_DEVINFO_PART_DEVICE_FAMILY_EZR32HG)
+  systemPartFamilyEzr32Happy   = _DEVINFO_PART_DEVICE_FAMILY_EZR32HG,     /**< EZR32 Happy Device Family */
+#endif
+#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P)
+  systemPartFamilyMighty1P = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P,       /**< EFR32 Mighty Gecko Gen1 Premium Device Family */
+#endif
+#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B)
+  systemPartFamilyMighty1B = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B,       /**< EFR32 Mighty Gecko Gen1 Basic Device Family */
+#endif
+#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V)
+  systemPartFamilyMighty1V = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V,       /**< EFR32 Mighty Gecko Gen1 Value Device Family */
+#endif
+#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P)
+  systemPartFamilyBlue1P   = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P,       /**< EFR32 Blue Gecko Gen1 Premium Device Family */
+#endif
+#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B)
+  systemPartFamilyBlue1B   = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B,       /**< EFR32 Blue Gecko Gen1 Basic Device Family */
+#endif
+#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V)
+  systemPartFamilyBlue1V   = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V,       /**< EFR32 Blue Gecko Gen1 Value Device Family */
+#endif
+#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32SG1P)
+  systemPartFamilySnappy1P = _DEVINFO_PART_DEVICE_FAMILY_EFR32SG1P,       /**< EFR32 Snappy Gecko Gen1 Premium Device Family */
+#endif
+#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32SG1B)
+  systemPartFamilySnappy1B = _DEVINFO_PART_DEVICE_FAMILY_EFR32SG1B,       /**< EFR32 Snappy Gecko Gen1 Basic Device Family */
+#endif
+#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32SG1V)
+  systemPartFamilySnappy1V = _DEVINFO_PART_DEVICE_FAMILY_EFR32SG1V,       /**< EFR32 Snappy Gecko Gen1 Value Device Family */
+#endif
+#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P)
+  systemPartFamilyFlex1P   = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P,       /**< EFR32 Flex Gecko Gen1 Premium Device Family */
+#endif
+#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B)
+  systemPartFamilyFlex1B   = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B,       /**< EFR32 Flex Gecko Gen1 Basic Device Family */
+#endif
+#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V)
+  systemPartFamilyFlex1V   = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V,       /**< EFR32 Flex Gecko Gen1 Value Device Family */
+#endif
+/* Legacy family #defines */
+#if defined(_DEVINFO_PART_DEVICE_FAMILY_G)
   systemPartFamilyGecko   = _DEVINFO_PART_DEVICE_FAMILY_G,   /**< Gecko Device Family */
 #endif
-#if defined( _DEVINFO_PART_DEVICE_FAMILY_GG )
+#if defined(_DEVINFO_PART_DEVICE_FAMILY_GG)
   systemPartFamilyGiant   = _DEVINFO_PART_DEVICE_FAMILY_GG,  /**< Giant Gecko Device Family */
 #endif
-#if defined( _DEVINFO_PART_DEVICE_FAMILY_TG )
+#if defined(_DEVINFO_PART_DEVICE_FAMILY_TG)
   systemPartFamilyTiny    = _DEVINFO_PART_DEVICE_FAMILY_TG,  /**< Tiny Gecko Device Family */
 #endif
-#if defined( _DEVINFO_PART_DEVICE_FAMILY_LG )
+#if defined(_DEVINFO_PART_DEVICE_FAMILY_LG)
   systemPartFamilyLeopard = _DEVINFO_PART_DEVICE_FAMILY_LG,  /**< Leopard Gecko Device Family */
 #endif
-#if defined( _DEVINFO_PART_DEVICE_FAMILY_WG )
+#if defined(_DEVINFO_PART_DEVICE_FAMILY_WG)
   systemPartFamilyWonder  = _DEVINFO_PART_DEVICE_FAMILY_WG,  /**< Wonder Gecko Device Family */
 #endif
-#if defined( _DEVINFO_PART_DEVICE_FAMILY_ZG )
+#if defined(_DEVINFO_PART_DEVICE_FAMILY_ZG)
   systemPartFamilyZero    = _DEVINFO_PART_DEVICE_FAMILY_ZG,  /**< Zero Gecko Device Family */
 #endif
-#if defined( _DEVINFO_PART_DEVICE_FAMILY_HG )
+#if defined(_DEVINFO_PART_DEVICE_FAMILY_HG)
   systemPartFamilyHappy   = _DEVINFO_PART_DEVICE_FAMILY_HG,  /**< Happy Gecko Device Family */
 #endif
   systemPartFamilyUnknown = 0xFF                             /**< Unknown Device Family.
@@ -97,7 +170,7 @@
   uint8_t family;/**< Device family number  */
 } SYSTEM_ChipRevision_TypeDef;
 
-#if defined( __FPU_PRESENT ) && ( __FPU_PRESENT == 1 )
+#if defined(__FPU_PRESENT) && (__FPU_PRESENT == 1)
 /** Floating point coprocessor access modes. */
 typedef enum
 {
@@ -115,7 +188,7 @@
 void     SYSTEM_ChipRevisionGet(SYSTEM_ChipRevision_TypeDef *rev);
 uint32_t SYSTEM_GetCalibrationValue(volatile uint32_t *regAddress);
 
-#if defined( __FPU_PRESENT ) && ( __FPU_PRESENT == 1 )
+#if defined(__FPU_PRESENT) && (__FPU_PRESENT == 1)
 /***************************************************************************//**
  * @brief
  *   Set floating point coprocessor (FPU) access mode.
@@ -139,7 +212,7 @@
  ******************************************************************************/
 __STATIC_INLINE uint64_t SYSTEM_GetUnique(void)
 {
-  return ((uint64_t) ((uint64_t) DEVINFO->UNIQUEH << 32) | (uint64_t) DEVINFO->UNIQUEL);
+  return (uint64_t)((uint64_t)DEVINFO->UNIQUEH << 32) | (uint64_t)DEVINFO->UNIQUEL;
 }
 
 /***************************************************************************//**
@@ -151,8 +224,8 @@
  ******************************************************************************/
 __STATIC_INLINE uint8_t SYSTEM_GetProdRev(void)
 {
-  return ((DEVINFO->PART & _DEVINFO_PART_PROD_REV_MASK)
-                         >> _DEVINFO_PART_PROD_REV_SHIFT);
+  return (DEVINFO->PART & _DEVINFO_PART_PROD_REV_MASK)
+         >> _DEVINFO_PART_PROD_REV_SHIFT;
 }
 
 /***************************************************************************//**
@@ -174,11 +247,11 @@
   if (SYSTEM_GetProdRev() < 5)
   {
     return (DEVINFO->MSIZE & _DEVINFO_MSIZE_FLASH_MASK)
-                           >> _DEVINFO_MSIZE_FLASH_SHIFT;
+           >> _DEVINFO_MSIZE_FLASH_SHIFT;
   }
 #endif
   return (DEVINFO->MSIZE & _DEVINFO_MSIZE_SRAM_MASK)
-                         >> _DEVINFO_MSIZE_SRAM_SHIFT;
+         >> _DEVINFO_MSIZE_SRAM_SHIFT;
 }
 
 /***************************************************************************//**
@@ -200,11 +273,11 @@
   if (SYSTEM_GetProdRev() < 5)
   {
     return (DEVINFO->MSIZE & _DEVINFO_MSIZE_SRAM_MASK)
-                           >> _DEVINFO_MSIZE_SRAM_SHIFT;
+           >> _DEVINFO_MSIZE_SRAM_SHIFT;
   }
 #endif
   return (DEVINFO->MSIZE & _DEVINFO_MSIZE_FLASH_MASK)
-                         >> _DEVINFO_MSIZE_FLASH_SHIFT;
+         >> _DEVINFO_MSIZE_FLASH_SHIFT;
 }
 
 
@@ -224,28 +297,43 @@
 {
   uint32_t tmp;
 
-#if defined( _EFM32_GIANT_FAMILY )
-  tmp = SYSTEM_GetProdRev();
-  if (tmp < 18)
+#if defined(_EFM32_GIANT_FAMILY)
+  if (SYSTEM_GetProdRev() < 18)
   {
     /* Early Giant/Leopard devices did not have MEMINFO in DEVINFO. */
     return FLASH_PAGE_SIZE;
   }
-#elif defined( _EFM32_ZERO_FAMILY )
-  tmp = SYSTEM_GetProdRev();
-  if (tmp < 24)
+#elif defined(_EFM32_ZERO_FAMILY)
+  if (SYSTEM_GetProdRev() < 24)
   {
     /* Early Zero devices have an incorrect DEVINFO flash page size */
     return FLASH_PAGE_SIZE;
   }
 #endif
+
   tmp = (DEVINFO->MEMINFO & _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_MASK)
-                 >> _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_SHIFT;
+        >> _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_SHIFT;
 
   return 1 << ((tmp + 10) & 0xFF);
 }
 
 
+#if defined( _DEVINFO_DEVINFOREV_DEVINFOREV_MASK )
+/***************************************************************************//**
+ * @brief
+ *   Get DEVINFO revision.
+ *
+ * @return
+ *   Revision of the DEVINFO contents.
+ ******************************************************************************/
+__STATIC_INLINE uint8_t SYSTEM_GetDevinfoRev(void)
+{
+  return (DEVINFO->DEVINFOREV & _DEVINFO_DEVINFOREV_DEVINFOREV_MASK)
+          >> _DEVINFO_DEVINFOREV_DEVINFOREV_SHIFT;
+}
+#endif
+
+
 /***************************************************************************//**
  * @brief
  *   Get part number of the MCU.
@@ -256,7 +344,7 @@
 __STATIC_INLINE uint16_t SYSTEM_GetPartNumber(void)
 {
   return (DEVINFO->PART & _DEVINFO_PART_DEVICE_NUMBER_MASK)
-                        >> _DEVINFO_PART_DEVICE_NUMBER_SHIFT;
+         >> _DEVINFO_PART_DEVICE_NUMBER_SHIFT;
 }
 
 /***************************************************************************//**
@@ -276,8 +364,8 @@
 __STATIC_INLINE SYSTEM_PartFamily_TypeDef SYSTEM_GetFamily(void)
 {
   return (SYSTEM_PartFamily_TypeDef)
-    ((DEVINFO->PART & _DEVINFO_PART_DEVICE_FAMILY_MASK)
-     >> _DEVINFO_PART_DEVICE_FAMILY_SHIFT);
+         ((DEVINFO->PART & _DEVINFO_PART_DEVICE_FAMILY_MASK)
+          >> _DEVINFO_PART_DEVICE_FAMILY_SHIFT);
 }
 
 
@@ -291,7 +379,7 @@
 __STATIC_INLINE uint8_t SYSTEM_GetCalibrationTemperature(void)
 {
   return (DEVINFO->CAL & _DEVINFO_CAL_TEMP_MASK)
-                       >> _DEVINFO_CAL_TEMP_SHIFT;
+         >> _DEVINFO_CAL_TEMP_SHIFT;
 }
 
 /** @} (end addtogroup SYSTEM) */
@@ -301,4 +389,4 @@
 }
 #endif
 
-#endif /* __SILICON_LABS_EM_SYSTEM_H_ */
+#endif /* __SILICON_LABS_EM_SYSTEM_H__ */

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_timer.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_timer.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /***************************************************************************//**
  * @file em_timer.h
  * @brief Timer/counter (TIMER) peripheral API
- * @version 3.20.12
+ * @version 4.2.1
  *******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
  *******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,9 +30,8 @@
  *
  ******************************************************************************/
 
-
-#ifndef __SILICON_LABS_EM_TIMER_H_
-#define __SILICON_LABS_EM_TIMER_H_
+#ifndef __SILICON_LABS_EM_TIMER_H__
+#define __SILICON_LABS_EM_TIMER_H__
 
 #include "em_device.h"
 #if defined(TIMER_COUNT) && (TIMER_COUNT > 0)
@@ -67,20 +66,26 @@
 #elif (TIMER_COUNT == 2)
 #define TIMER_REF_VALID(ref)    (((ref) == TIMER0) || ((ref) == TIMER1))
 #elif (TIMER_COUNT == 3)
-#define TIMER_REF_VALID(ref)    (((ref) == TIMER0) || \
-                                 ((ref) == TIMER1) || \
-                                 ((ref) == TIMER2))
+#define TIMER_REF_VALID(ref)    (((ref) == TIMER0)    \
+                                 || ((ref) == TIMER1) \
+                                 || ((ref) == TIMER2))
 #elif (TIMER_COUNT == 4)
-#define TIMER_REF_VALID(ref)    (((ref) == TIMER0) || \
-                                 ((ref) == TIMER1) || \
-                                 ((ref) == TIMER2) || \
-                                 ((ref) == TIMER3))
+#define TIMER_REF_VALID(ref)    (((ref) == TIMER0)    \
+                                 || ((ref) == TIMER1) \
+                                 || ((ref) == TIMER2) \
+                                 || ((ref) == TIMER3))
 #else
-#error Undefined number of timers.
+#error "Undefined number of timers."
 #endif
 
 /** Validation of TIMER compare/capture channel number */
+#if defined(_SILICON_LABS_32B_PLATFORM_1)
 #define TIMER_CH_VALID(ch)    ((ch) < 3)
+#elif defined(_SILICON_LABS_32B_PLATFORM_2)
+#define TIMER_CH_VALID(ch)    ((ch) < 4)
+#else
+#error "Unknown platform. Undefined number of channels."
+#endif
 
 /** @endcond */
 
@@ -220,33 +225,33 @@
   timerPRSSELCh1 = _TIMER_CC_CTRL_PRSSEL_PRSCH1,        /**< PRS channel 1. */
   timerPRSSELCh2 = _TIMER_CC_CTRL_PRSSEL_PRSCH2,        /**< PRS channel 2. */
   timerPRSSELCh3 = _TIMER_CC_CTRL_PRSSEL_PRSCH3,        /**< PRS channel 3. */
-#if defined( _TIMER_CC_CTRL_PRSSEL_PRSCH4 )
+#if defined(_TIMER_CC_CTRL_PRSSEL_PRSCH4)
   timerPRSSELCh4 = _TIMER_CC_CTRL_PRSSEL_PRSCH4,        /**< PRS channel 4. */
 #endif
-#if defined( _TIMER_CC_CTRL_PRSSEL_PRSCH5 )
+#if defined(_TIMER_CC_CTRL_PRSSEL_PRSCH5)
   timerPRSSELCh5 = _TIMER_CC_CTRL_PRSSEL_PRSCH5,        /**< PRS channel 5. */
 #endif
-#if defined( _TIMER_CC_CTRL_PRSSEL_PRSCH6 )
+#if defined(_TIMER_CC_CTRL_PRSSEL_PRSCH6)
   timerPRSSELCh6 = _TIMER_CC_CTRL_PRSSEL_PRSCH6,        /**< PRS channel 6. */
 #endif
-#if defined( _TIMER_CC_CTRL_PRSSEL_PRSCH7 )
+#if defined(_TIMER_CC_CTRL_PRSSEL_PRSCH7)
   timerPRSSELCh7 = _TIMER_CC_CTRL_PRSSEL_PRSCH7,        /**< PRS channel 7. */
 #endif
-#if defined( _TIMER_CC_CTRL_PRSSEL_PRSCH8 )
+#if defined(_TIMER_CC_CTRL_PRSSEL_PRSCH8)
   timerPRSSELCh8  = _TIMER_CC_CTRL_PRSSEL_PRSCH8,       /**< PRS channel 8. */
 #endif
-#if defined( _TIMER_CC_CTRL_PRSSEL_PRSCH9 )
+#if defined(_TIMER_CC_CTRL_PRSSEL_PRSCH9)
   timerPRSSELCh9  = _TIMER_CC_CTRL_PRSSEL_PRSCH9,       /**< PRS channel 9. */
 #endif
-#if defined( _TIMER_CC_CTRL_PRSSEL_PRSCH10 )
+#if defined(_TIMER_CC_CTRL_PRSSEL_PRSCH10)
   timerPRSSELCh10 = _TIMER_CC_CTRL_PRSSEL_PRSCH10,      /**< PRS channel 10. */
 #endif
-#if defined( _TIMER_CC_CTRL_PRSSEL_PRSCH11 )
+#if defined(_TIMER_CC_CTRL_PRSSEL_PRSCH11)
   timerPRSSELCh11 = _TIMER_CC_CTRL_PRSSEL_PRSCH11,      /**< PRS channel 11. */
 #endif
 } TIMER_PRSSEL_TypeDef;
 
-#ifdef _TIMER_DTFC_DTFA_NONE
+#if defined(_TIMER_DTFC_DTFA_NONE)
 /** DT (Dead Time) Fault Actions. */
 typedef enum
 {
@@ -276,7 +281,7 @@
   /** Clock selection. */
   TIMER_ClkSel_TypeDef      clkSel;
 
-#if defined( TIMER_CTRL_X2CNT ) && defined( TIMER_CTRL_ATI )
+#if defined(TIMER_CTRL_X2CNT) && defined(TIMER_CTRL_ATI)
   /** 2x Count mode, counter increments/decrements by 2, meant for PWN mode. */
   bool                      count2x;
 
@@ -308,36 +313,38 @@
 } TIMER_Init_TypeDef;
 
 /** Default config for TIMER init structure. */
-#if defined( TIMER_CTRL_X2CNT ) && defined( TIMER_CTRL_ATI )
-#define TIMER_INIT_DEFAULT                                                              \
-  { true,                   /* Enable timer when init complete. */                      \
-    false,                  /* Stop counter during debug halt. */                       \
-    timerPrescale1,         /* No prescaling. */                                        \
-    timerClkSelHFPerClk,    /* Select HFPER clock. */                                   \
-    false,                  /* Not 2x count mode. */                                    \
-    false,                  /* No ATI. */                                               \
-    timerInputActionNone,   /* No action on falling input edge. */                      \
-    timerInputActionNone,   /* No action on rising input edge. */                       \
-    timerModeUp,            /* Up-counting. */                                          \
-    false,                  /* Do not clear DMA requests when DMA channel is active. */ \
-    false,                  /* Select X2 quadrature decode mode (if used). */           \
-    false,                  /* Disable one shot. */                                     \
-    false                   /* Not started/stopped/reloaded by other timers. */         \
-  }
+#if defined(TIMER_CTRL_X2CNT) && defined(TIMER_CTRL_ATI)
+#define TIMER_INIT_DEFAULT                                                            \
+{                                                                                     \
+  true,                   /* Enable timer when init complete. */                      \
+  false,                  /* Stop counter during debug halt. */                       \
+  timerPrescale1,         /* No prescaling. */                                        \
+  timerClkSelHFPerClk,    /* Select HFPER clock. */                                   \
+  false,                  /* Not 2x count mode. */                                    \
+  false,                  /* No ATI. */                                               \
+  timerInputActionNone,   /* No action on falling input edge. */                      \
+  timerInputActionNone,   /* No action on rising input edge. */                       \
+  timerModeUp,            /* Up-counting. */                                          \
+  false,                  /* Do not clear DMA requests when DMA channel is active. */ \
+  false,                  /* Select X2 quadrature decode mode (if used). */           \
+  false,                  /* Disable one shot. */                                     \
+  false                   /* Not started/stopped/reloaded by other timers. */         \
+}
 #else
-#define TIMER_INIT_DEFAULT                                                              \
-  { true,                   /* Enable timer when init complete. */                      \
-    false,                  /* Stop counter during debug halt. */                       \
-    timerPrescale1,         /* No prescaling. */                                        \
-    timerClkSelHFPerClk,    /* Select HFPER clock. */                                   \
-    timerInputActionNone,   /* No action on falling input edge. */                      \
-    timerInputActionNone,   /* No action on rising input edge. */                       \
-    timerModeUp,            /* Up-counting. */                                          \
-    false,                  /* Do not clear DMA requests when DMA channel is active. */ \
-    false,                  /* Select X2 quadrature decode mode (if used). */           \
-    false,                  /* Disable one shot. */                                     \
-    false                   /* Not started/stopped/reloaded by other timers. */         \
-  }
+#define TIMER_INIT_DEFAULT                                                            \
+{                                                                                     \
+  true,                   /* Enable timer when init complete. */                      \
+  false,                  /* Stop counter during debug halt. */                       \
+  timerPrescale1,         /* No prescaling. */                                        \
+  timerClkSelHFPerClk,    /* Select HFPER clock. */                                   \
+  timerInputActionNone,   /* No action on falling input edge. */                      \
+  timerInputActionNone,   /* No action on rising input edge. */                       \
+  timerModeUp,            /* Up-counting. */                                          \
+  false,                  /* Do not clear DMA requests when DMA channel is active. */ \
+  false,                  /* Select X2 quadrature decode mode (if used). */           \
+  false,                  /* Disable one shot. */                                     \
+  false                   /* Not started/stopped/reloaded by other timers. */         \
+}
 #endif
 
 /** TIMER compare/capture initialization structure. */
@@ -387,21 +394,22 @@
 } TIMER_InitCC_TypeDef;
 
 /** Default config for TIMER compare/capture init structure. */
-#define TIMER_INITCC_DEFAULT                                                   \
-  { timerEventEveryEdge,      /* Event on every capture. */                    \
-    timerEdgeRising,          /* Input capture edge on rising edge. */         \
-    timerPRSSELCh0,           /* Not used by default, select PRS channel 0. */ \
-    timerOutputActionNone,    /* No action on underflow. */                    \
-    timerOutputActionNone,    /* No action on overflow. */                     \
-    timerOutputActionNone,    /* No action on match. */                        \
-    timerCCModeOff,           /* Disable compare/capture channel. */           \
-    false,                    /* Disable filter. */                            \
-    false,                    /* Select TIMERnCCx input. */                    \
-    false,                    /* Clear output when countre disabled. */        \
-    false                     /* Do not invert output. */                      \
-  }
+#define TIMER_INITCC_DEFAULT                                                 \
+{                                                                            \
+  timerEventEveryEdge,      /* Event on every capture. */                    \
+  timerEdgeRising,          /* Input capture edge on rising edge. */         \
+  timerPRSSELCh0,           /* Not used by default, select PRS channel 0. */ \
+  timerOutputActionNone,    /* No action on underflow. */                    \
+  timerOutputActionNone,    /* No action on overflow. */                     \
+  timerOutputActionNone,    /* No action on match. */                        \
+  timerCCModeOff,           /* Disable compare/capture channel. */           \
+  false,                    /* Disable filter. */                            \
+  false,                    /* Select TIMERnCCx input. */                    \
+  false,                    /* Clear output when counter disabled. */        \
+  false                     /* Do not invert output. */                      \
+}
 
-#ifdef _TIMER_DTCTRL_MASK
+#if defined(_TIMER_DTCTRL_MASK)
 /** TIMER Dead Time Insertion (DTI) initialization structure. */
 typedef struct
 {
@@ -464,25 +472,26 @@
 
 
   /** Default config for TIMER DTI init structure. */
-#define TIMER_INITDTI_DEFAULT                                                  \
-  { true,                     /* Enable the DTI. */                            \
-    false,                    /* CC[0|1|2] outputs are active high. */         \
-    false,                    /* CDTI[0|1|2] outputs are not inverted. */      \
-    false,                    /* No auto restart when debugger exits. */       \
-    false,                    /* No PRS source selected. */                    \
-    timerPRSSELCh0,           /* Not used by default, select PRS channel 0. */ \
-    timerPrescale1,           /* No prescaling.  */                            \
-    0,                        /* No rise time. */                              \
-    0,                        /* No fall time. */                              \
-    TIMER_DTOGEN_DTOGCC0EN|TIMER_DTOGEN_DTOGCDTI0EN, /* Enable CC0 and CDTI0 */\
-    true,                     /* Enable core lockup as fault source */         \
-    true,                     /* Enable debugger as fault source */            \
-    false,                    /* Disable PRS fault source 0 */                 \
-    timerPRSSELCh0,           /* Not used by default, select PRS channel 0. */ \
-    false,                    /* Disable PRS fault source 1 */                 \
-    timerPRSSELCh0,           /* Not used by default, select PRS channel 0. */ \
-    timerDtiFaultActionInactive, /* No fault action. */                        \
-  }
+#define TIMER_INITDTI_DEFAULT                                                \
+{                                                                            \
+  true,                     /* Enable the DTI. */                            \
+  false,                    /* CC[0|1|2] outputs are active high. */         \
+  false,                    /* CDTI[0|1|2] outputs are not inverted. */      \
+  false,                    /* No auto restart when debugger exits. */       \
+  false,                    /* No PRS source selected. */                    \
+  timerPRSSELCh0,           /* Not used by default, select PRS channel 0. */ \
+  timerPrescale1,           /* No prescaling.  */                            \
+  0,                        /* No rise time. */                              \
+  0,                        /* No fall time. */                              \
+  TIMER_DTOGEN_DTOGCC0EN|TIMER_DTOGEN_DTOGCDTI0EN, /* Enable CC0 and CDTI0 */\
+  true,                     /* Enable core lockup as fault source */         \
+  true,                     /* Enable debugger as fault source */            \
+  false,                    /* Disable PRS fault source 0 */                 \
+  timerPRSSELCh0,           /* Not used by default, select PRS channel 0. */ \
+  false,                    /* Disable PRS fault source 1 */                 \
+  timerPRSSELCh0,           /* Not used by default, select PRS channel 0. */ \
+  timerDtiFaultActionInactive, /* No fault action. */                        \
+}
 #endif /* _TIMER_DTCTRL_MASK */
 
 
@@ -506,7 +515,7 @@
  ******************************************************************************/
 __STATIC_INLINE uint32_t TIMER_CaptureGet(TIMER_TypeDef *timer, unsigned int ch)
 {
-  return(timer->CC[ch].CCV);
+  return timer->CC[ch].CCV;
 }
 
 
@@ -571,7 +580,7 @@
  ******************************************************************************/
 __STATIC_INLINE uint32_t TIMER_CounterGet(TIMER_TypeDef *timer)
 {
-  return(timer->CNT);
+  return timer->CNT;
 }
 
 
@@ -621,7 +630,7 @@
                   unsigned int ch,
                   const TIMER_InitCC_TypeDef *init);
 
-#ifdef _TIMER_DTCTRL_MASK
+#if defined(_TIMER_DTCTRL_MASK)
 void TIMER_InitDTI(TIMER_TypeDef *timer, const TIMER_InitDTI_TypeDef *init);
 
 /***************************************************************************//**
@@ -666,7 +675,7 @@
 __STATIC_INLINE uint32_t TIMER_GetDTIFault(TIMER_TypeDef *timer)
 {
   EFM_ASSERT(TIMER0 == timer);
-  return(timer->DTFAULT);
+  return timer->DTFAULT;
 }
 
 
@@ -720,7 +729,7 @@
  ******************************************************************************/
 __STATIC_INLINE void TIMER_IntDisable(TIMER_TypeDef *timer, uint32_t flags)
 {
-  timer->IEN &= ~(flags);
+  timer->IEN &= ~flags;
 }
 
 
@@ -762,7 +771,7 @@
  ******************************************************************************/
 __STATIC_INLINE uint32_t TIMER_IntGet(TIMER_TypeDef *timer)
 {
-  return(timer->IF);
+  return timer->IF;
 }
 
 
@@ -787,14 +796,14 @@
  ******************************************************************************/
 __STATIC_INLINE uint32_t TIMER_IntGetEnabled(TIMER_TypeDef *timer)
 {
-  uint32_t tmp;
+  uint32_t ien;
 
   /* Store TIMER->IEN in temporary variable in order to define explicit order
    * of volatile accesses. */
-  tmp = timer->IEN;
+  ien = timer->IEN;
 
   /* Bitwise AND of pending and enabled interrupts */
-  return timer->IF & tmp;
+  return timer->IF & ien;
 }
 
 
@@ -814,7 +823,7 @@
   timer->IFS = flags;
 }
 
-#ifdef TIMER_DTLOCK_LOCKKEY_LOCK
+#if defined(_TIMER_DTLOCK_LOCKKEY_LOCK)
 /***************************************************************************//**
  * @brief
  *   Lock some of the TIMER registers in order to protect them from being
@@ -874,7 +883,7 @@
  ******************************************************************************/
 __STATIC_INLINE uint32_t TIMER_TopGet(TIMER_TypeDef *timer)
 {
-  return(timer->TOP);
+  return timer->TOP;
 }
 
 
@@ -894,7 +903,7 @@
 }
 
 
-#ifdef TIMER_DTLOCK_LOCKKEY_UNLOCK
+#if defined(TIMER_DTLOCK_LOCKKEY_UNLOCK)
 /***************************************************************************//**
  * @brief
  *   Unlock the TIMER so that writing to locked registers again is possible.
@@ -919,4 +928,4 @@
 #endif
 
 #endif /* defined(TIMER_COUNT) && (TIMER_COUNT > 0) */
-#endif /* __SILICON_LABS_EM_TIMER_H_ */
+#endif /* __SILICON_LABS_EM_TIMER_H__ */

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_usart.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_usart.h	Fri Jan 15 07:45:16 2016 +0000
@@ -2,10 +2,10 @@
  * @file em_usart.h
  * @brief Universal synchronous/asynchronous receiver/transmitter (USART/UART)
  *   peripheral API
- * @version 3.20.12
+ * @version 4.2.1
  *******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
  *******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -32,8 +32,8 @@
  ******************************************************************************/
 
 
-#ifndef __SILICON_LABS_EM_USART_H_
-#define __SILICON_LABS_EM_USART_H_
+#ifndef __SILICON_LABS_EM_USART_H__
+#define __SILICON_LABS_EM_USART_H__
 
 #include "em_device.h"
 #if defined(USART_COUNT) && (USART_COUNT > 0)
@@ -165,21 +165,21 @@
   usartIrDAPrsCh1 = USART_IRCTRL_IRPRSSEL_PRSCH1,       /**< PRS channel 1 */
   usartIrDAPrsCh2 = USART_IRCTRL_IRPRSSEL_PRSCH2,       /**< PRS channel 2 */
   usartIrDAPrsCh3 = USART_IRCTRL_IRPRSSEL_PRSCH3,       /**< PRS channel 3 */
-#if defined( USART_IRCTRL_IRPRSSEL_PRSCH4 )
+#if defined(USART_IRCTRL_IRPRSSEL_PRSCH4)
   usartIrDAPrsCh4 = USART_IRCTRL_IRPRSSEL_PRSCH4,       /**< PRS channel 4 */
 #endif
-#if defined( USART_IRCTRL_IRPRSSEL_PRSCH5 )
+#if defined(USART_IRCTRL_IRPRSSEL_PRSCH5)
   usartIrDAPrsCh5 = USART_IRCTRL_IRPRSSEL_PRSCH5,       /**< PRS channel 5 */
 #endif
-#if defined( USART_IRCTRL_IRPRSSEL_PRSCH6 )
+#if defined(USART_IRCTRL_IRPRSSEL_PRSCH6)
   usartIrDAPrsCh6 = USART_IRCTRL_IRPRSSEL_PRSCH6,       /**< PRS channel 6 */
 #endif
-#if defined( USART_IRCTRL_IRPRSSEL_PRSCH7 )
+#if defined(USART_IRCTRL_IRPRSSEL_PRSCH7)
   usartIrDAPrsCh7 = USART_IRCTRL_IRPRSSEL_PRSCH7,       /**< PRS channel 7 */
 #endif
 } USART_IrDAPrsSel_Typedef;
 
-#if defined( _USART_I2SCTRL_MASK )
+#if defined(_USART_I2SCTRL_MASK)
 /** I2S format selection. */
 typedef enum
 {
@@ -201,7 +201,7 @@
 } USART_I2sJustify_TypeDef;
 #endif
 
-#if defined( _USART_INPUT_MASK )
+#if defined(_USART_INPUT_MASK)
 /** USART Rx input PRS selection. */
 typedef enum
 {
@@ -210,14 +210,14 @@
   usartPrsRxCh2  = USART_INPUT_RXPRSSEL_PRSCH2,    /**< PRSCH2  selected as USART_INPUT */
   usartPrsRxCh3  = USART_INPUT_RXPRSSEL_PRSCH3,    /**< PRSCH3  selected as USART_INPUT */
 
-#if defined( USART_INPUT_RXPRSSEL_PRSCH7 )
+#if defined(USART_INPUT_RXPRSSEL_PRSCH7)
   usartPrsRxCh4  = USART_INPUT_RXPRSSEL_PRSCH4,    /**< PRSCH4  selected as USART_INPUT */
   usartPrsRxCh5  = USART_INPUT_RXPRSSEL_PRSCH5,    /**< PRSCH5  selected as USART_INPUT */
   usartPrsRxCh6  = USART_INPUT_RXPRSSEL_PRSCH6,    /**< PRSCH6  selected as USART_INPUT */
   usartPrsRxCh7  = USART_INPUT_RXPRSSEL_PRSCH7,    /**< PRSCH7  selected as USART_INPUT */
 #endif
 
-#if defined( USART_INPUT_RXPRSSEL_PRSCH11 )
+#if defined(USART_INPUT_RXPRSSEL_PRSCH11)
   usartPrsRxCh8  = USART_INPUT_RXPRSSEL_PRSCH8,    /**< PRSCH8  selected as USART_INPUT */
   usartPrsRxCh9  = USART_INPUT_RXPRSSEL_PRSCH9,    /**< PRSCH9  selected as USART_INPUT */
   usartPrsRxCh10 = USART_INPUT_RXPRSSEL_PRSCH10,   /**< PRSCH10 selected as USART_INPUT */
@@ -234,7 +234,7 @@
   usartPrsTriggerCh2 = USART_TRIGCTRL_TSEL_PRSCH2, /**< PRSCH0 selected as USART Trigger */
   usartPrsTriggerCh3 = USART_TRIGCTRL_TSEL_PRSCH3, /**< PRSCH0 selected as USART Trigger */
 
-#if defined( USART_TRIGCTRL_TSEL_PRSCH7 )
+#if defined(USART_TRIGCTRL_TSEL_PRSCH7)
   usartPrsTriggerCh4 = USART_TRIGCTRL_TSEL_PRSCH4, /**< PRSCH0 selected as USART Trigger */
   usartPrsTriggerCh5 = USART_TRIGCTRL_TSEL_PRSCH5, /**< PRSCH0 selected as USART Trigger */
   usartPrsTriggerCh6 = USART_TRIGCTRL_TSEL_PRSCH6, /**< PRSCH0 selected as USART Trigger */
@@ -274,7 +274,7 @@
   /** Number of stopbits to use. */
   USART_Stopbits_TypeDef stopbits;
 
-#if defined( USART_INPUT_RXPRS ) && defined( USART_CTRL_MVDIS )
+#if defined(USART_INPUT_RXPRS) && defined(USART_CTRL_MVDIS)
   /** Majority Vote Disable for 16x, 8x and 6x oversampling modes. */
   bool                   mvdis;
 
@@ -284,12 +284,20 @@
   /** Select PRS channel for USART Rx. (Only valid if prsRxEnable is true). */
   USART_PrsRxCh_TypeDef  prsRxCh;
 #endif
+#if defined(_USART_TIMING_CSHOLD_MASK)
+  /** Auto CS enabling */
+  bool autoCsEnable;
+  /** Auto CS hold time in baud cycles */
+  uint8_t autoCsHold;
+  /** Auto CS setup time in baud cycles */
+  uint8_t autoCsSetup;
+#endif
 } USART_InitAsync_TypeDef;
 
 /** USART PRS trigger enable */
 typedef struct
 {
-#if defined( USART_TRIGCTRL_AUTOTXTEN )
+#if defined(USART_TRIGCTRL_AUTOTXTEN)
   /** Enable AUTOTX */
   bool autoTxTriggerEnable;
 #endif
@@ -302,45 +310,66 @@
 } USART_PrsTriggerInit_TypeDef;
 
 /** Default config for USART async init structure. */
-#if defined( USART_INPUT_RXPRS ) && defined( USART_CTRL_MVDIS )
-#define USART_INITASYNC_DEFAULT                                                              \
-  { usartEnable,      /* Enable RX/TX when init completed. */                                \
-    0,                /* Use current configured reference clock for configuring baudrate. */ \
-    115200,           /* 115200 bits/s. */                                                   \
-    usartOVS16,       /* 16x oversampling. */                                                \
-    usartDatabits8,   /* 8 databits. */                                                      \
-    usartNoParity,    /* No parity. */                                                       \
-    usartStopbits1,   /* 1 stopbit. */                                                       \
-    false,            /* Do not disable majority vote. */                                    \
-    false,            /* Not USART PRS input mode. */                                        \
-    usartPrsRxCh0     /* PRS channel 0. */                                                   \
-  }
+#if defined(_USART_TIMING_CSHOLD_MASK) && defined(USART_CTRL_MVDIS)
+#define USART_INITASYNC_DEFAULT                                                            \
+{                                                                                          \
+  usartEnable,      /* Enable RX/TX when init completed. */                                \
+  0,                /* Use current configured reference clock for configuring baudrate. */ \
+  115200,           /* 115200 bits/s. */                                                   \
+  usartOVS16,       /* 16x oversampling. */                                                \
+  usartDatabits8,   /* 8 databits. */                                                      \
+  usartNoParity,    /* No parity. */                                                       \
+  usartStopbits1,   /* 1 stopbit. */                                                       \
+  false,            /* Do not disable majority vote. */                                    \
+  false,            /* Not USART PRS input mode. */                                        \
+  usartPrsRxCh0,    /* PRS channel 0. */                                                   \
+  false,            /* Auto CS functionality enable/disable switch */                      \
+  0,                /* Auto CS Hold cycles */                                              \
+  0                 /* Auto CS Setup cycles */                                             \
+}
+#elif defined(USART_INPUT_RXPRS) && defined(USART_CTRL_MVDIS)
+#define USART_INITASYNC_DEFAULT                                                            \
+{                                                                                          \
+  usartEnable,      /* Enable RX/TX when init completed. */                                \
+  0,                /* Use current configured reference clock for configuring baudrate. */ \
+  115200,           /* 115200 bits/s. */                                                   \
+  usartOVS16,       /* 16x oversampling. */                                                \
+  usartDatabits8,   /* 8 databits. */                                                      \
+  usartNoParity,    /* No parity. */                                                       \
+  usartStopbits1,   /* 1 stopbit. */                                                       \
+  false,            /* Do not disable majority vote. */                                    \
+  false,            /* Not USART PRS input mode. */                                        \
+  usartPrsRxCh0     /* PRS channel 0. */                                                   \
+}
 #else
-#define USART_INITASYNC_DEFAULT                                                              \
-  { usartEnable,      /* Enable RX/TX when init completed. */                                \
-    0,                /* Use current configured reference clock for configuring baudrate. */ \
-    115200,           /* 115200 bits/s. */                                                   \
-    usartOVS16,       /* 16x oversampling. */                                                \
-    usartDatabits8,   /* 8 databits. */                                                      \
-    usartNoParity,    /* No parity. */                                                       \
-    usartStopbits1    /* 1 stopbit. */                                                       \
-  }
+#define USART_INITASYNC_DEFAULT                                                            \
+{                                                                                          \
+  usartEnable,      /* Enable RX/TX when init completed. */                                \
+  0,                /* Use current configured reference clock for configuring baudrate. */ \
+  115200,           /* 115200 bits/s. */                                                   \
+  usartOVS16,       /* 16x oversampling. */                                                \
+  usartDatabits8,   /* 8 databits. */                                                      \
+  usartNoParity,    /* No parity. */                                                       \
+  usartStopbits1    /* 1 stopbit. */                                                       \
+}
 #endif
 
 /** Default config for USART PRS triggering structure. */
-#if defined ( USART_TRIGCTRL_AUTOTXTEN )
-#define USART_INITPRSTRIGGER_DEFAULT                                                         \
-  { false,              /* Do not enable autoTX triggering. */                               \
-    false,              /* Do not enable receive triggering. */                              \
-    false,              /* Do not enable transmit triggering. */                             \
-    usartPrsTriggerCh0  /* Set default channel to zero. */                                   \
-  }
+#if defined(USART_TRIGCTRL_AUTOTXTEN)
+#define USART_INITPRSTRIGGER_DEFAULT                                                       \
+{                                                                                          \
+  false,              /* Do not enable autoTX triggering. */                               \
+  false,              /* Do not enable receive triggering. */                              \
+  false,              /* Do not enable transmit triggering. */                             \
+  usartPrsTriggerCh0  /* Set default channel to zero. */                                   \
+}
 #else
-#define USART_INITPRSTRIGGER_DEFAULT                                                         \
-  { false,              /* Do not enable receive triggering. */                              \
-    false,              /* Do not enable transmit triggering. */                             \
-    usartPrsTriggerCh0  /* Set default channel to zero. */                                   \
-  }
+#define USART_INITPRSTRIGGER_DEFAULT                                                       \
+{                                                                                          \
+  false,              /* Do not enable receive triggering. */                              \
+  false,              /* Do not enable transmit triggering. */                             \
+  usartPrsTriggerCh0  /* Set default channel to zero. */                                   \
+}
 #endif
 
 /** Synchronous mode init structure. */
@@ -370,7 +399,7 @@
   /** Clock polarity/phase mode. */
   USART_ClockMode_TypeDef clockMode;
 
-#if defined( USART_INPUT_RXPRS ) && defined( USART_TRIGCTRL_AUTOTXTEN )
+#if defined(USART_INPUT_RXPRS) && defined(USART_TRIGCTRL_AUTOTXTEN)
   /** Enable USART Rx via PRS. */
   bool                    prsRxEnable;
 
@@ -381,32 +410,59 @@
    *  If TX is empty, underflows are generated. */
   bool                    autoTx;
 #endif
+#if defined(_USART_TIMING_CSHOLD_MASK)
+  /** Auto CS enabling */
+  bool autoCsEnable;
+  /** Auto CS hold time in baud cycles */
+  uint8_t autoCsHold;
+  /** Auto CS setup time in baud cycles */
+  uint8_t autoCsSetup;
+#endif
 } USART_InitSync_TypeDef;
 
 /** Default config for USART sync init structure. */
-#if defined( USART_INPUT_RXPRS ) && defined( USART_TRIGCTRL_AUTOTXTEN )
-#define USART_INITSYNC_DEFAULT                                                                \
-  { usartEnable,       /* Enable RX/TX when init completed. */                                \
-    0,                 /* Use current configured reference clock for configuring baudrate. */ \
-    1000000,           /* 1 Mbits/s. */                                                       \
-    usartDatabits8,    /* 8 databits. */                                                      \
-    true,              /* Master mode. */                                                     \
-    false,             /* Send least significant bit first. */                                \
-    usartClockMode0,   /* Clock idle low, sample on rising edge. */                           \
-    false,             /* Not USART PRS input mode. */                                        \
-    usartPrsRxCh0,     /* PRS channel 0. */                                                   \
-    false              /* No AUTOTX mode. */                                                  \
-  }
+#if defined(_USART_TIMING_CSHOLD_MASK)
+#define USART_INITSYNC_DEFAULT                                                              \
+{                                                                                           \
+  usartEnable,       /* Enable RX/TX when init completed. */                                \
+  0,                 /* Use current configured reference clock for configuring baudrate. */ \
+  1000000,           /* 1 Mbits/s. */                                                       \
+  usartDatabits8,    /* 8 databits. */                                                      \
+  true,              /* Master mode. */                                                     \
+  false,             /* Send least significant bit first. */                                \
+  usartClockMode0,   /* Clock idle low, sample on rising edge. */                           \
+  false,             /* Not USART PRS input mode. */                                        \
+  usartPrsRxCh0,     /* PRS channel 0. */                                                   \
+  false,             /* No AUTOTX mode. */                                                  \
+  false,             /* No AUTOCS mode */                                                   \
+  0,                 /* Auto CS Hold cycles */                                              \
+  0                  /* Auto CS Setup cycles */                                             \
+}
+#elif defined(USART_INPUT_RXPRS) && defined(USART_TRIGCTRL_AUTOTXTEN)
+#define USART_INITSYNC_DEFAULT                                                              \
+{                                                                                           \
+  usartEnable,       /* Enable RX/TX when init completed. */                                \
+  0,                 /* Use current configured reference clock for configuring baudrate. */ \
+  1000000,           /* 1 Mbits/s. */                                                       \
+  usartDatabits8,    /* 8 databits. */                                                      \
+  true,              /* Master mode. */                                                     \
+  false,             /* Send least significant bit first. */                                \
+  usartClockMode0,   /* Clock idle low, sample on rising edge. */                           \
+  false,             /* Not USART PRS input mode. */                                        \
+  usartPrsRxCh0,     /* PRS channel 0. */                                                   \
+  false              /* No AUTOTX mode. */                                                  \
+}
 #else
-#define USART_INITSYNC_DEFAULT                                                                \
-  { usartEnable,       /* Enable RX/TX when init completed. */                                \
-    0,                 /* Use current configured reference clock for configuring baudrate. */ \
-    1000000,           /* 1 Mbits/s. */                                                       \
-    usartDatabits8,    /* 8 databits. */                                                      \
-    true,              /* Master mode. */                                                     \
-    false,             /* Send least significant bit first. */                                \
-    usartClockMode0    /* Clock idle low, sample on rising edge. */                           \
-  }
+#define USART_INITSYNC_DEFAULT                                                              \
+{                                                                                           \
+  usartEnable,       /* Enable RX/TX when init completed. */                                \
+  0,                 /* Use current configured reference clock for configuring baudrate. */ \
+  1000000,           /* 1 Mbits/s. */                                                       \
+  usartDatabits8,    /* 8 databits. */                                                      \
+  true,              /* Master mode. */                                                     \
+  false,             /* Send least significant bit first. */                                \
+  usartClockMode0    /* Clock idle low, sample on rising edge. */                           \
+}
 #endif
 
 
@@ -437,25 +493,26 @@
 
 
 /** Default config for IrDA mode init structure. */
-#define USART_INITIRDA_DEFAULT                                                                \
-  {                                                                                           \
-    { usartEnable,     /* Enable RX/TX when init completed. */                                \
-      0,               /* Use current configured reference clock for configuring baudrate. */ \
-      115200,          /* 115200 bits/s. */                                                   \
-      usartOVS16,      /* 16x oversampling. */                                                \
-      usartDatabits8,  /* 8 databits. */                                                      \
-      usartEvenParity, /* Even parity. */                                                     \
-      usartStopbits1   /* 1 stopbit. */                                                       \
-    },                                                                                        \
-    false,             /* Rx invert disabled. */                                              \
-    false,             /* Filtering disabled. */                                              \
-    usartIrDAPwTHREE,  /* Pulse width is set to ONE. */                                       \
-    false,             /* Routing to PRS is disabled. */                                      \
-    usartIrDAPrsCh0    /* PRS channel 0. */                                                   \
-  }
+#define USART_INITIRDA_DEFAULT                                                              \
+{                                                                                           \
+  {                                                                                         \
+    usartEnable,     /* Enable RX/TX when init completed. */                                \
+    0,               /* Use current configured reference clock for configuring baudrate. */ \
+    115200,          /* 115200 bits/s. */                                                   \
+    usartOVS16,      /* 16x oversampling. */                                                \
+    usartDatabits8,  /* 8 databits. */                                                      \
+    usartEvenParity, /* Even parity. */                                                     \
+    usartStopbits1   /* 1 stopbit. */                                                       \
+  },                                                                                        \
+  false,             /* Rx invert disabled. */                                              \
+  false,             /* Filtering disabled. */                                              \
+  usartIrDAPwTHREE,  /* Pulse width is set to ONE. */                                       \
+  false,             /* Routing to PRS is disabled. */                                      \
+  usartIrDAPrsCh0    /* PRS channel 0. */                                                   \
+}
 
 
-#if defined( _USART_I2SCTRL_MASK )
+#if defined(_USART_I2SCTRL_MASK)
 /** I2S mode init structure. Inherited from synchronous mode init structure */
 typedef struct
 {
@@ -482,25 +539,26 @@
 
 
 /** Default config for I2S mode init structure. */
-#define USART_INITI2S_DEFAULT                                                                    \
-  {                                                                                              \
-    { usartEnableTx,      /* Enable TX when init completed. */                                   \
-      0,                  /* Use current configured reference clock for configuring baudrate. */ \
-      1000000,            /* Baudrate 1M bits/s. */                                              \
-      usartDatabits16,    /* 16 databits. */                                                     \
-      true,               /* Operate as I2S master. */                                           \
-      true,               /* Most significant bit first. */                                      \
-      usartClockMode0,    /* Clock idle low, sample on rising edge. */                           \
-      false,              /* Don't enable USARTRx via PRS. */                                    \
-      usartPrsRxCh0,      /* PRS channel selection (dummy). */                                   \
-      false               /* Disable AUTOTX mode. */                                             \
-    },                                                                                           \
-    usartI2sFormatW16D16, /* 16-bit word, 16-bit data */                                         \
-    true,                 /* Delay on I2S data. */                                               \
-    false,                /* No DMA split. */                                                    \
-    usartI2sJustifyLeft,  /* Data is left-justified within the frame */                          \
-    false                 /* Stereo mode. */                                                     \
-  }
+#define USART_INITI2S_DEFAULT                                                                  \
+{                                                                                              \
+  {                                                                                            \
+    usartEnableTx,      /* Enable TX when init completed. */                                   \
+    0,                  /* Use current configured reference clock for configuring baudrate. */ \
+    1000000,            /* Baudrate 1M bits/s. */                                              \
+    usartDatabits16,    /* 16 databits. */                                                     \
+    true,               /* Operate as I2S master. */                                           \
+    true,               /* Most significant bit first. */                                      \
+    usartClockMode0,    /* Clock idle low, sample on rising edge. */                           \
+    false,              /* Don't enable USARTRx via PRS. */                                    \
+    usartPrsRxCh0,      /* PRS channel selection (dummy). */                                   \
+    false               /* Disable AUTOTX mode. */                                             \
+  },                                                                                           \
+  usartI2sFormatW16D16, /* 16-bit word, 16-bit data */                                         \
+  true,                 /* Delay on I2S data. */                                               \
+  false,                /* No DMA split. */                                                    \
+  usartI2sJustifyLeft,  /* Data is left-justified within the frame */                          \
+  false                 /* Stereo mode. */                                                     \
+}
 #endif
 
 /*******************************************************************************
@@ -523,11 +581,11 @@
 
 void USART_InitAsync(USART_TypeDef *usart, const USART_InitAsync_TypeDef *init);
 void USART_InitSync(USART_TypeDef *usart, const USART_InitSync_TypeDef *init);
-#if defined(USART0) || ( (USART_COUNT == 1) && defined( USART1 ) )
+#if defined(USART0) || ((USART_COUNT == 1) && defined(USART1))
 void USART_InitIrDA(const USART_InitIrDA_TypeDef *init);
 #endif
 
-#if defined( _USART_I2SCTRL_MASK )
+#if defined(_USART_I2SCTRL_MASK)
 void USART_InitI2s(USART_TypeDef *usart, USART_InitI2s_TypeDef *init);
 #endif
 void USART_InitPrsTrigger(USART_TypeDef *usart, const USART_PrsTriggerInit_TypeDef *init);
@@ -563,7 +621,7 @@
  ******************************************************************************/
 __STATIC_INLINE void USART_IntDisable(USART_TypeDef *usart, uint32_t flags)
 {
-  usart->IEN &= ~(flags);
+  usart->IEN &= ~flags;
 }
 
 
@@ -630,14 +688,14 @@
  ******************************************************************************/
 __STATIC_INLINE uint32_t USART_IntGetEnabled(USART_TypeDef *usart)
 {
-  uint32_t tmp;
+  uint32_t ien;
 
   /* Store USARTx->IEN in temporary variable in order to define explicit order
    * of volatile accesses. */
-  tmp = usart->IEN;
+  ien = usart->IEN;
 
   /* Bitwise AND of pending and enabled interrupts */
-  return usart->IF & tmp;
+  return usart->IF & ien;
 }
 
 
@@ -669,7 +727,7 @@
  *  STATUS register value.
  *
  ******************************************************************************/
-static __INLINE uint32_t USART_StatusGet(USART_TypeDef *usart)
+__STATIC_INLINE uint32_t USART_StatusGet(USART_TypeDef *usart)
 {
   return usart->STATUS;
 }
@@ -709,9 +767,9 @@
  * @return
  *   Data received.
  ******************************************************************************/
-static __INLINE uint8_t USART_RxDataGet(USART_TypeDef *usart)
+__STATIC_INLINE uint8_t USART_RxDataGet(USART_TypeDef *usart)
 {
-  return (uint8_t) (usart->RXDATA);
+  return (uint8_t)usart->RXDATA;
 }
 
 
@@ -747,9 +805,9 @@
  * @return
  *   Data received.
  ******************************************************************************/
-static __INLINE uint16_t USART_RxDoubleGet(USART_TypeDef *usart)
+__STATIC_INLINE uint16_t USART_RxDoubleGet(USART_TypeDef *usart)
 {
-  return (uint16_t) (usart->RXDOUBLE);
+  return (uint16_t)usart->RXDOUBLE;
 }
 
 
@@ -783,7 +841,7 @@
  * @return
  *   Data received.
  ******************************************************************************/
-static __INLINE uint32_t USART_RxDoubleXGet(USART_TypeDef *usart)
+__STATIC_INLINE uint32_t USART_RxDoubleXGet(USART_TypeDef *usart)
 {
   return usart->RXDOUBLEX;
 }
@@ -818,9 +876,9 @@
  * @return
  *   Data received.
  ******************************************************************************/
-static __INLINE uint16_t USART_RxDataXGet(USART_TypeDef *usart)
+__STATIC_INLINE uint16_t USART_RxDataXGet(USART_TypeDef *usart)
 {
-  return (uint16_t) (usart->RXDATAX);
+  return (uint16_t)usart->RXDATAX;
 }
 
 uint8_t USART_SpiTransfer(USART_TypeDef *usart, uint8_t data);
@@ -838,4 +896,4 @@
 #endif
 
 #endif /* defined(USART_COUNT) && (USART_COUNT > 0) */
-#endif /* __SILICON_LABS_EM_USART_H_ */
+#endif /* __SILICON_LABS_EM_USART_H__ */

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_vcmp.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_vcmp.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /***************************************************************************//**
  * @file em_vcmp.h
  * @brief Voltage Comparator (VCMP) peripheral API
- * @version 3.20.12
+ * @version 4.2.1
  *******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
  *******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,9 +30,8 @@
  *
  ******************************************************************************/
 
-
-#ifndef __SILICON_LABS_EM_VCMP_H_
-#define __SILICON_LABS_EM_VCMP_H_
+#ifndef __SILICON_LABS_EM_VCMP_H__
+#define __SILICON_LABS_EM_VCMP_H__
 
 #include "em_device.h"
 #if defined(VCMP_COUNT) && (VCMP_COUNT > 0)
@@ -121,39 +120,28 @@
 } VCMP_Init_TypeDef;
 
 /** Default VCMP initialization structure */
-#define VCMP_INIT_DEFAULT                                                  \
-  { true,                /** Half Bias enabled */                          \
-    0x7,                 /** Bias curernt 0.7 uA when half bias enabled */ \
-    false,               /** Falling edge sense not enabled */             \
-    false,               /** Rising edge sense not enabled */              \
-    vcmpWarmTime4Cycles, /** 4 clock cycles warm-up time */                \
-    vcmpHystNone,        /** No hysteresis */                              \
-    0,                   /** 0 in digital ouput when inactive */           \
-    true,                /** Do not use low power reference */             \
-    39,                  /** Trigger level just below 3V */                \
-    true,                /** Enable after init */                          \
-  }
+#define VCMP_INIT_DEFAULT                                                \
+{                                                                        \
+  true,                /** Half Bias enabled */                          \
+  0x7,                 /** Bias curernt 0.7 uA when half bias enabled */ \
+  false,               /** Falling edge sense not enabled */             \
+  false,               /** Rising edge sense not enabled */              \
+  vcmpWarmTime4Cycles, /** 4 clock cycles warm-up time */                \
+  vcmpHystNone,        /** No hysteresis */                              \
+  0,                   /** 0 in digital ouput when inactive */           \
+  true,                /** Do not use low power reference */             \
+  39,                  /** Trigger level just below 3V */                \
+  true,                /** Enable after init */                          \
+}
 
 /*******************************************************************************
  *****************************   PROTOTYPES   **********************************
  ******************************************************************************/
+
 void VCMP_Init(const VCMP_Init_TypeDef *vcmpInit);
 void VCMP_LowPowerRefSet(bool enable);
 void VCMP_TriggerSet(int level);
 
-__STATIC_INLINE void VCMP_Enable(void);
-__STATIC_INLINE void VCMP_Disable(void);
-__STATIC_INLINE uint32_t VCMP_VoltageToLevel(float v);
-__STATIC_INLINE bool VCMP_VDDLower(void);
-__STATIC_INLINE bool VCMP_VDDHigher(void);
-__STATIC_INLINE bool VCMP_Ready(void);
-__STATIC_INLINE void VCMP_IntClear(uint32_t flags);
-__STATIC_INLINE void VCMP_IntSet(uint32_t flags);
-__STATIC_INLINE void VCMP_IntDisable(uint32_t flags);
-__STATIC_INLINE void VCMP_IntEnable(uint32_t flags);
-__STATIC_INLINE uint32_t VCMP_IntGet(void);
-__STATIC_INLINE uint32_t VCMP_IntGetEnabled(void);
-
 /***************************************************************************//**
  * @brief
  *   Enable Voltage Comparator
@@ -170,7 +158,7 @@
  ******************************************************************************/
 __STATIC_INLINE void VCMP_Disable(void)
 {
-  VCMP->CTRL &= ~(VCMP_CTRL_EN);
+  VCMP->CTRL &= ~VCMP_CTRL_EN;
 }
 
 
@@ -284,7 +272,7 @@
  ******************************************************************************/
 __STATIC_INLINE void VCMP_IntDisable(uint32_t flags)
 {
-  VCMP->IEN &= ~(flags);
+  VCMP->IEN &= ~flags;
 }
 
 
@@ -316,7 +304,7 @@
  ******************************************************************************/
 __STATIC_INLINE uint32_t VCMP_IntGet(void)
 {
-  return(VCMP->IF);
+  return VCMP->IF;
 }
 
 
@@ -358,4 +346,4 @@
 #endif
 
 #endif /* defined(VCMP_COUNT) && (VCMP_COUNT > 0) */
-#endif /* __SILICON_LABS_EM_VCMP_H_ */
+#endif /* __SILICON_LABS_EM_VCMP_H__ */

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_version.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_version.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /***************************************************************************//**
  * @file em_version.h
  * @brief Assign correct part number for include file
- * @version 3.20.12
+ * @version 4.2.1
  *******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
  *******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,9 +30,8 @@
  *
  ******************************************************************************/
 
-
-#ifndef __SILICON_LABS_EM_VERSION_H_
-#define __SILICON_LABS_EM_VERSION_H_
+#ifndef __SILICON_LABS_EM_VERSION_H__
+#define __SILICON_LABS_EM_VERSION_H__
 
 #include "em_device.h"
 
@@ -46,18 +45,36 @@
  ******************************************************************************/
 
 /***************************************************************************//**
- * @addtogroup Version
+ * @addtogroup VERSION
  * @{
  ******************************************************************************/
 
-/** Version number of emlib peripheral API */
-#define _EMLIB_VERSION 3.20.12
-/** Major version of emlib */
-#define _EMLIB_VERSION_MAJOR 3
-/** Minor version of emlib */
-#define _EMLIB_VERSION_MINOR 20
-/** Patch revision of emlib */
-#define _EMLIB_VERSION_PATCH 12
+/** Version number of emlib peripheral API. */
+#define _EMLIB_VERSION 4.2.1
+
+/** Major version of emlib. Bumped when incompatible API changes introduced. */
+#define _EMLIB_VERSION_MAJOR 4
+
+/** Minor version of emlib. Bumped when functionality is added in a backwards-
+    compatible manner. */
+#define _EMLIB_VERSION_MINOR 2
+
+/** Patch revision of emlib. Bumped when adding backwards-compatible bug
+    fixes.*/
+#define _EMLIB_VERSION_PATCH 1
+
+
+/** Version number of targeted CMSIS package. */
+#define _CMSIS_VERSION 4.2.0
+
+/** Major version of CMSIS. */
+#define _CMSIS_VERSION_MAJOR 4
+
+/** Minor version of CMSIS. */
+#define _CMSIS_VERSION_MINOR 2
+
+/** Patch revision of CMSIS. */
+#define _CMSIS_VERSION_PATCH 0
 
 /** @} (end addtogroup Version) */
 /** @} (end addtogroup EM_Library) */
@@ -66,4 +83,4 @@
 }
 #endif
 
-#endif /* __SILICON_LABS_EM_VERSION_H_ */
+#endif /* __SILICON_LABS_EM_VERSION_H__ */

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_wdog.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_wdog.h	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /***************************************************************************//**
  * @file em_wdog.h
  * @brief Watchdog (WDOG) peripheral API
- * @version 3.20.12
+ * @version 4.2.1
  *******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
  *******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -31,8 +31,8 @@
  ******************************************************************************/
 
 
-#ifndef __SILICON_LABS_EM_WDOG_H_
-#define __SILICON_LABS_EM_WDOG_H_
+#ifndef __SILICON_LABS_EM_WDOG_H__
+#define __SILICON_LABS_EM_WDOG_H__
 
 #include "em_device.h"
 #if defined(WDOG_COUNT) && (WDOG_COUNT > 0)
@@ -122,17 +122,18 @@
 } WDOG_Init_TypeDef;
 
 /** Suggested default config for WDOG init structure. */
-#define WDOG_INIT_DEFAULT                                                                        \
-  { true,               /* Start watchdog when init done */                                      \
-    false,              /* WDOG not counting during debug halt */                                \
-    false,              /* WDOG not counting when in EM2 */                                      \
-    false,              /* WDOG not counting when in EM3 */                                      \
-    false,              /* EM4 can be entered */                                                 \
-    false,              /* Do not block disabling LFRCO/LFXO in CMU */                           \
-    false,              /* Do not lock WDOG configuration (if locked, reset needed to unlock) */ \
-    wdogClkSelULFRCO,   /* Select 1kHZ WDOG oscillator */                                        \
-    wdogPeriod_256k     /* Set longest possible timeout period */                                \
-  }
+#define WDOG_INIT_DEFAULT                                                                      \
+{                                                                                              \
+  true,               /* Start watchdog when init done */                                      \
+  false,              /* WDOG not counting during debug halt */                                \
+  false,              /* WDOG not counting when in EM2 */                                      \
+  false,              /* WDOG not counting when in EM3 */                                      \
+  false,              /* EM4 can be entered */                                                 \
+  false,              /* Do not block disabling LFRCO/LFXO in CMU */                           \
+  false,              /* Do not lock WDOG configuration (if locked, reset needed to unlock) */ \
+  wdogClkSelULFRCO,   /* Select 1kHZ WDOG oscillator */                                        \
+  wdogPeriod_256k     /* Set longest possible timeout period */                                \
+}
 
 
 /*******************************************************************************
@@ -152,4 +153,4 @@
 #endif
 
 #endif /* defined(WDOG_COUNT) && (WDOG_COUNT > 0) */
-#endif /* __SILICON_LABS_EM_WDOG_H_ */
+#endif /* __SILICON_LABS_EM_WDOG_H__ */

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_acmp.c	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_acmp.c	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /***************************************************************************//**
  * @file em_acmp.c
  * @brief Analog Comparator (ACMP) Peripheral API
- * @version 3.20.12
+ * @version 4.2.1
  *******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
  *******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -35,7 +35,7 @@
 #if defined(ACMP_COUNT) && (ACMP_COUNT > 0)
 
 #include <stdbool.h>
-#include "em_bitband.h"
+#include "em_bus.h"
 #include "em_assert.h"
 
 /***************************************************************************//**
@@ -66,6 +66,20 @@
 #error Undefined number of analog comparators (ACMP).
 #endif
 
+/** The maximum value that can be inserted in the route location register
+ *  for the specific device. */
+#if defined(_ACMP_ROUTE_LOCATION_LOC3)
+#define _ACMP_ROUTE_LOCATION_MAX     _ACMP_ROUTE_LOCATION_LOC3
+#elif defined(_ACMP_ROUTE_LOCATION_LOC2)
+#define _ACMP_ROUTE_LOCATION_MAX     _ACMP_ROUTE_LOCATION_LOC2
+#elif defined(_ACMP_ROUTE_LOCATION_LOC1)
+#define _ACMP_ROUTE_LOCATION_MAX     _ACMP_ROUTE_LOCATION_LOC1
+#elif defined(_ACMP_ROUTELOC0_OUTLOC_LOC31)
+#define _ACMP_ROUTE_LOCATION_MAX     _ACMP_ROUTELOC0_OUTLOC_LOC31
+#else
+#error Undefined max route locations
+#endif
+
 /** @endcond */
 
 /*******************************************************************************
@@ -99,31 +113,60 @@
   EFM_ASSERT(ACMP_REF_VALID(acmp));
 
   /* Make sure that vddLevel is within bounds */
+#if defined(_ACMP_INPUTSEL_VDDLEVEL_MASK)
   EFM_ASSERT(init->vddLevel < 64);
+#else
+  EFM_ASSERT(init->vddLevelLow < 64);
+  EFM_ASSERT(init->vddLevelHigh < 64);
+#endif
 
   /* Make sure biasprog is within bounds */
-  EFM_ASSERT(init->biasProg < 16);
+  EFM_ASSERT(init->biasProg <=
+      (_ACMP_CTRL_BIASPROG_MASK >> _ACMP_CTRL_BIASPROG_SHIFT));
 
   /* Set control register. No need to set interrupt modes */
   acmp->CTRL = (init->fullBias << _ACMP_CTRL_FULLBIAS_SHIFT)
+#if defined(_ACMP_CTRL_HALFBIAS_MASK)
                | (init->halfBias << _ACMP_CTRL_HALFBIAS_SHIFT)
+#endif
                | (init->biasProg << _ACMP_CTRL_BIASPROG_SHIFT)
+#if defined(_ACMP_CTRL_WARMTIME_MASK)
                | (init->warmTime << _ACMP_CTRL_WARMTIME_SHIFT)
-               | (init->hysteresisLevel << _ACMP_CTRL_HYSTSEL_SHIFT);
+#endif
+#if defined(_ACMP_CTRL_HYSTSEL_MASK)
+               | (init->hysteresisLevel << _ACMP_CTRL_HYSTSEL_SHIFT)
+#endif
+#if defined(_ACMP_CTRL_ACCURACY_MASK)
+               | ACMP_CTRL_ACCURACY_HIGH
+#endif
+               ;
+
+#if defined(_ACMP_HYSTERESIS0_MASK)
+  acmp->HYSTERESIS0 = (init->vddLevelHigh      << _ACMP_HYSTERESIS0_DIVVA_SHIFT)
+                      | (init->hysteresisLevel_0 << _ACMP_HYSTERESIS0_HYST_SHIFT);
+  acmp->HYSTERESIS1 = (init->vddLevelLow       << _ACMP_HYSTERESIS1_DIVVA_SHIFT)
+                      | (init->hysteresisLevel_1 << _ACMP_HYSTERESIS1_HYST_SHIFT);
+#endif
 
   /* Select capacative sensing mode by selecting a resistor and enabling it */
   acmp->INPUTSEL = (init->resistor << _ACMP_INPUTSEL_CSRESSEL_SHIFT)
                    | ACMP_INPUTSEL_CSRESEN
+#if defined(_ACMP_INPUTSEL_LPREF_MASK)
                    | (init->lowPowerReferenceEnabled << _ACMP_INPUTSEL_LPREF_SHIFT)
+#endif
+#if defined(_ACMP_INPUTSEL_VDDLEVEL_MASK)
                    | (init->vddLevel << _ACMP_INPUTSEL_VDDLEVEL_SHIFT)
-                   | ACMP_INPUTSEL_NEGSEL_CAPSENSE;
+#endif
+#if defined(ACMP_INPUTSEL_NEGSEL_CAPSENSE)
+                   | ACMP_INPUTSEL_NEGSEL_CAPSENSE
+#else
+                   | ACMP_INPUTSEL_VASEL_VDD
+                   | ACMP_INPUTSEL_NEGSEL_VADIV
+#endif
+                   ;
 
-  /* Enable ACMP if requested.
-   * Note: BITBAND_Peripheral() function is used for setting/clearing single
-   * bit peripheral register bitfields. */
-  BITBAND_Peripheral(&(acmp->CTRL),
-                     (uint32_t)_ACMP_CTRL_EN_SHIFT,
-                     (uint32_t)init->enable);
+  /* Enable ACMP if requested. */
+  BUS_RegBitWrite(&(acmp->CTRL), _ACMP_CTRL_EN_SHIFT, init->enable);
 }
 
 /***************************************************************************//**
@@ -142,12 +185,20 @@
  ******************************************************************************/
 void ACMP_CapsenseChannelSet(ACMP_TypeDef *acmp, ACMP_Channel_TypeDef channel)
 {
+  /* Make sure the module exists on the selected chip */
+  EFM_ASSERT(ACMP_REF_VALID(acmp));
+
+#if defined(_ACMP_INPUTSEL_POSSEL_CH7)
   /* Make sure that only external channels are used */
   EFM_ASSERT(channel <= _ACMP_INPUTSEL_POSSEL_CH7);
+#elif defined(_ACMP_INPUTSEL_POSSEL_BUS4XCH31)
+  /* Make sure that only external channels are used */
+  EFM_ASSERT(channel <= _ACMP_INPUTSEL_POSSEL_BUS4XCH31);
+#endif
 
   /* Set channel as positive channel in ACMP */
-  SET_BIT_FIELD(acmp->INPUTSEL, _ACMP_INPUTSEL_POSSEL_MASK, channel,
-                _ACMP_INPUTSEL_POSSEL_SHIFT);
+  BUS_RegMaskedWrite(&acmp->INPUTSEL, _ACMP_INPUTSEL_POSSEL_MASK,
+      channel << _ACMP_INPUTSEL_POSSEL_SHIFT);
 }
 
 /***************************************************************************//**
@@ -159,6 +210,9 @@
  ******************************************************************************/
 void ACMP_Disable(ACMP_TypeDef *acmp)
 {
+  /* Make sure the module exists on the selected chip */
+  EFM_ASSERT(ACMP_REF_VALID(acmp));
+
   acmp->CTRL &= ~ACMP_CTRL_EN;
 }
 
@@ -171,6 +225,9 @@
  ******************************************************************************/
 void ACMP_Enable(ACMP_TypeDef *acmp)
 {
+  /* Make sure the module exists on the selected chip */
+  EFM_ASSERT(ACMP_REF_VALID(acmp));
+
   acmp->CTRL |= ACMP_CTRL_EN;
 }
 
@@ -190,10 +247,14 @@
   /* Make sure the module exists on the selected chip */
   EFM_ASSERT(ACMP_REF_VALID(acmp));
 
-  acmp->CTRL     = _ACMP_CTRL_RESETVALUE;
-  acmp->INPUTSEL = _ACMP_INPUTSEL_RESETVALUE;
-  acmp->IEN      = _ACMP_IEN_RESETVALUE;
-  acmp->IFC      = _ACMP_IF_MASK;
+  acmp->CTRL        = _ACMP_CTRL_RESETVALUE;
+  acmp->INPUTSEL    = _ACMP_INPUTSEL_RESETVALUE;
+#if defined(_ACMP_HYSTERESIS0_HYST_MASK)
+  acmp->HYSTERESIS0 = _ACMP_HYSTERESIS0_RESETVALUE;
+  acmp->HYSTERESIS1 = _ACMP_HYSTERESIS1_RESETVALUE;
+#endif
+  acmp->IEN         = _ACMP_IEN_RESETVALUE;
+  acmp->IFC         = _ACMP_IF_MASK;
 }
 
 /***************************************************************************//**
@@ -218,27 +279,24 @@
  ******************************************************************************/
 void ACMP_GPIOSetup(ACMP_TypeDef *acmp, uint32_t location, bool enable, bool invert)
 {
-  /* Sanity checking of location */
-#if defined( _ACMP_ROUTE_LOCATION_LOC3 )
-  EFM_ASSERT(location <= _ACMP_ROUTE_LOCATION_LOC3);
-
-#elif defined( _ACMP_ROUTE_LOCATION_LOC2 )
-  EFM_ASSERT(location <= _ACMP_ROUTE_LOCATION_LOC2);
+  /* Make sure the module exists on the selected chip */
+  EFM_ASSERT(ACMP_REF_VALID(acmp));
 
-#elif defined( _ACMP_ROUTE_LOCATION_LOC1 )
-  EFM_ASSERT(location <= _ACMP_ROUTE_LOCATION_LOC1);
-
-#else
-#error Illegal pin location (ACMP).
-#endif
-
+  /* Sanity checking of location */
+  EFM_ASSERT(location <= _ACMP_ROUTE_LOCATION_MAX);
 
   /* Set GPIO inversion */
-  SET_BIT_FIELD(acmp->CTRL, _ACMP_CTRL_GPIOINV_MASK, invert,
-                _ACMP_CTRL_GPIOINV_SHIFT);
+  BUS_RegMaskedWrite(&acmp->CTRL, _ACMP_CTRL_GPIOINV_MASK,
+      invert << _ACMP_CTRL_GPIOINV_SHIFT);
 
+#if defined(_ACMP_ROUTE_MASK)
   acmp->ROUTE = (location << _ACMP_ROUTE_LOCATION_SHIFT)
                 | (enable << _ACMP_ROUTE_ACMPPEN_SHIFT);
+#endif
+#if defined(_ACMP_ROUTELOC0_MASK)
+  acmp->ROUTELOC0 = location << _ACMP_ROUTELOC0_OUTLOC_SHIFT;
+  acmp->ROUTEPEN  = enable ? ACMP_ROUTEPEN_OUTPEN : 0;
+#endif
 }
 
 /***************************************************************************//**
@@ -257,26 +315,29 @@
 void ACMP_ChannelSet(ACMP_TypeDef *acmp, ACMP_Channel_TypeDef negSel,
                      ACMP_Channel_TypeDef posSel)
 {
-  /* Sanity checking of ACMP inputs */
-  EFM_ASSERT(posSel <= _ACMP_INPUTSEL_POSSEL_CH7);
+  /* Make sure the module exists on the selected chip */
+  EFM_ASSERT(ACMP_REF_VALID(acmp));
 
+  /* Make sure that posSel and negSel channel selectors are valid. */
 #if defined(_ACMP_INPUTSEL_NEGSEL_DAC0CH1)
   EFM_ASSERT(negSel <= _ACMP_INPUTSEL_NEGSEL_DAC0CH1);
 #elif defined(_ACMP_INPUTSEL_NEGSEL_CAPSENSE)
   EFM_ASSERT(negSel <= _ACMP_INPUTSEL_NEGSEL_CAPSENSE);
-#else
-#error Illegal negative input selection (ACMP).
 #endif
 
-  acmp->INPUTSEL = (acmp->INPUTSEL & ~(_ACMP_INPUTSEL_POSSEL_MASK |
-                                       _ACMP_INPUTSEL_NEGSEL_MASK))
+#if defined(_ACMP_INPUTSEL_POSSEL_CH7)
+  EFM_ASSERT(posSel <= _ACMP_INPUTSEL_POSSEL_CH7);
+#endif
+
+  acmp->INPUTSEL = (acmp->INPUTSEL & ~(_ACMP_INPUTSEL_POSSEL_MASK
+                                       | _ACMP_INPUTSEL_NEGSEL_MASK))
                    | (negSel << _ACMP_INPUTSEL_NEGSEL_SHIFT)
                    | (posSel << _ACMP_INPUTSEL_POSSEL_SHIFT);
 }
 
 /***************************************************************************//**
  * @brief
- *
+ *   Initialize ACMP.
  *
  * @param[in] acmp
  *   Pointer to the ACMP peripheral register block.
@@ -293,27 +354,102 @@
   /* Make sure biasprog is within bounds */
   EFM_ASSERT(init->biasProg < 16);
 
+  /* Make sure the ACMP is disable since we might be changing the
+   * ACMP power source */
+  BUS_RegBitWrite(&acmp->CTRL, _ACMP_CTRL_EN_SHIFT, 0);
+
   /* Set control register. No need to set interrupt modes */
   acmp->CTRL = (init->fullBias << _ACMP_CTRL_FULLBIAS_SHIFT)
+#if defined(_ACMP_CTRL_HALFBIAS_MASK)
                | (init->halfBias << _ACMP_CTRL_HALFBIAS_SHIFT)
+#endif
                | (init->biasProg << _ACMP_CTRL_BIASPROG_SHIFT)
                | (init->interruptOnFallingEdge << _ACMP_CTRL_IFALL_SHIFT)
                | (init->interruptOnRisingEdge << _ACMP_CTRL_IRISE_SHIFT)
+#if defined(_ACMP_CTRL_INPUTRANGE_MASK)
+               | (init->inputRange << _ACMP_CTRL_INPUTRANGE_SHIFT)
+#endif
+#if defined(_ACMP_CTRL_ACCURACY_MASK)
+               | (init->accuracy << _ACMP_CTRL_ACCURACY_SHIFT)
+#endif
+#if defined(_ACMP_CTRL_PWRSEL_MASK)
+               | (init->powerSource << _ACMP_CTRL_PWRSEL_SHIFT)
+#endif
+#if defined(_ACMP_CTRL_WARMTIME_MASK)
                | (init->warmTime << _ACMP_CTRL_WARMTIME_SHIFT)
+#endif
+#if defined(_ACMP_CTRL_HYSTSEL_MASK)
                | (init->hysteresisLevel << _ACMP_CTRL_HYSTSEL_SHIFT)
+#endif
                | (init->inactiveValue << _ACMP_CTRL_INACTVAL_SHIFT);
 
-  acmp->INPUTSEL = (init->lowPowerReferenceEnabled << _ACMP_INPUTSEL_LPREF_SHIFT)
-                   | (init->vddLevel << _ACMP_INPUTSEL_VDDLEVEL_SHIFT);
+  acmp->INPUTSEL = (0)
+#if defined(_ACMP_INPUTSEL_VLPSEL_MASK)
+               | (init->vlpInput << _ACMP_INPUTSEL_VLPSEL_SHIFT)
+#endif
+#if defined(_ACMP_INPUTSEL_LPREF_MASK)
+               | (init->lowPowerReferenceEnabled << _ACMP_INPUTSEL_LPREF_SHIFT)
+#endif
+#if defined(_ACMP_INPUTSEL_VDDLEVEL_MASK)
+               | (init->vddLevel << _ACMP_INPUTSEL_VDDLEVEL_SHIFT)
+#endif
+               ;
 
-  /* Enable ACMP if requested.
-   * Note: BITBAND_Peripheral() function is used for setting/clearing single
-   * bit peripheral register bitfields. */
-  BITBAND_Peripheral(&(acmp->CTRL),
-                     (uint32_t)_ACMP_CTRL_EN_SHIFT,
-                     (uint32_t)init->enable);
+  /* Enable ACMP if requested. */
+  BUS_RegBitWrite(&(acmp->CTRL), _ACMP_CTRL_EN_SHIFT, init->enable);
 }
 
+#if defined(_ACMP_INPUTSEL_VASEL_MASK)
+/***************************************************************************//**
+ * @brief
+ *   Setup the VA Source.
+ *
+ * @param[in] acmp
+ *   Pointer to the ACMP peripheral register block.
+ *
+ * @param[in] vaconfig
+ *   Pointer to the structure used to configure the VA source. This structure
+ *   contains the input source as well as the 2 divider values.
+ ******************************************************************************/
+void ACMP_VASetup(ACMP_TypeDef *acmp, const ACMP_VAConfig_TypeDef *vaconfig)
+{
+  EFM_ASSERT(vaconfig->div0 < 64);
+  EFM_ASSERT(vaconfig->div1 < 64);
+
+  BUS_RegMaskedWrite(&acmp->INPUTSEL, _ACMP_INPUTSEL_VASEL_MASK,
+      vaconfig->input << _ACMP_INPUTSEL_VASEL_SHIFT);
+  BUS_RegMaskedWrite(&acmp->HYSTERESIS0, _ACMP_HYSTERESIS0_DIVVA_MASK,
+      vaconfig->div0 << _ACMP_HYSTERESIS0_DIVVA_SHIFT);
+  BUS_RegMaskedWrite(&acmp->HYSTERESIS1, _ACMP_HYSTERESIS1_DIVVA_MASK,
+      vaconfig->div1 << _ACMP_HYSTERESIS1_DIVVA_SHIFT);
+}
+#endif
+
+#if defined(_ACMP_INPUTSEL_VBSEL_MASK)
+/***************************************************************************//**
+ * @brief
+ *   Setup the VB Source.
+ *
+ * @param[in] acmp
+ *   Pointer to the ACMP peripheral register block.
+ *
+ * @param[in] vbconfig
+ *   Pointer to the structure used to configure the VB source. This structure
+ *   contains the input source as well as the 2 divider values.
+ ******************************************************************************/
+void ACMP_VBSetup(ACMP_TypeDef *acmp, const ACMP_VBConfig_TypeDef *vbconfig)
+{
+  EFM_ASSERT(vbconfig->div0 < 64);
+  EFM_ASSERT(vbconfig->div1 < 64);
+
+  BUS_RegMaskedWrite(&acmp->INPUTSEL, _ACMP_INPUTSEL_VBSEL_MASK,
+      vbconfig->input << _ACMP_INPUTSEL_VBSEL_SHIFT);
+  BUS_RegMaskedWrite(&acmp->HYSTERESIS0, _ACMP_HYSTERESIS0_DIVVB_MASK,
+      vbconfig->div0 << _ACMP_HYSTERESIS0_DIVVB_SHIFT);
+  BUS_RegMaskedWrite(&acmp->HYSTERESIS1, _ACMP_HYSTERESIS1_DIVVB_MASK,
+      vbconfig->div1 << _ACMP_HYSTERESIS1_DIVVB_SHIFT);
+}
+#endif
 
 /** @} (end addtogroup ACMP) */
 /** @} (end addtogroup EM_Library) */

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_adc.c	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_adc.c	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /***************************************************************************//**
  * @file em_adc.c
  * @brief Analog to Digital Converter (ADC) Peripheral API
- * @version 3.20.12
+ * @version 4.2.1
  *******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
  *******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,12 +30,12 @@
  *
  ******************************************************************************/
 
-
 #include "em_adc.h"
-#if defined(ADC_COUNT) && (ADC_COUNT > 0)
+#if defined( ADC_COUNT ) && ( ADC_COUNT > 0 )
 
 #include "em_cmu.h"
 #include "em_assert.h"
+#include <stddef.h>
 
 /***************************************************************************//**
  * @addtogroup EM_Library
@@ -58,11 +58,124 @@
 #define ADC_REF_VALID(ref)    ((ref) == ADC0)
 
 /** Max ADC clock */
+#if defined( _SILICON_LABS_32B_PLATFORM_1 )
 #define ADC_MAX_CLOCK    13000000
+#else
+#define ADC_MAX_CLOCK    16000000
+#endif
 
 /** Min ADC clock */
 #define ADC_MIN_CLOCK    32000
 
+/** Helper defines for selecting ADC calibration and DEVINFO register fields. */
+#if defined( _DEVINFO_ADC0CAL0_1V25_GAIN_MASK )
+#define DEVINFO_ADC0_GAIN1V25_MASK _DEVINFO_ADC0CAL0_1V25_GAIN_MASK
+#elif defined( _DEVINFO_ADC0CAL0_GAIN1V25_MASK )
+#define DEVINFO_ADC0_GAIN1V25_MASK _DEVINFO_ADC0CAL0_GAIN1V25_MASK
+#endif
+
+#if defined( _DEVINFO_ADC0CAL0_1V25_GAIN_SHIFT )
+#define DEVINFO_ADC0_GAIN1V25_SHIFT _DEVINFO_ADC0CAL0_1V25_GAIN_SHIFT
+#elif defined( _DEVINFO_ADC0CAL0_GAIN1V25_SHIFT )
+#define DEVINFO_ADC0_GAIN1V25_SHIFT _DEVINFO_ADC0CAL0_GAIN1V25_SHIFT
+#endif
+
+#if defined( _DEVINFO_ADC0CAL0_1V25_OFFSET_MASK )
+#define DEVINFO_ADC0_OFFSET1V25_MASK _DEVINFO_ADC0CAL0_1V25_OFFSET_MASK
+#elif defined( _DEVINFO_ADC0CAL0_OFFSET1V25_MASK )
+#define DEVINFO_ADC0_OFFSET1V25_MASK _DEVINFO_ADC0CAL0_OFFSET1V25_MASK
+#endif
+
+#if defined( _DEVINFO_ADC0CAL0_1V25_OFFSET_SHIFT )
+#define DEVINFO_ADC0_OFFSET1V25_SHIFT _DEVINFO_ADC0CAL0_1V25_OFFSET_SHIFT
+#elif defined( _DEVINFO_ADC0CAL0_OFFSET1V25_SHIFT )
+#define DEVINFO_ADC0_OFFSET1V25_SHIFT _DEVINFO_ADC0CAL0_OFFSET1V25_SHIFT
+#endif
+
+#if defined( _DEVINFO_ADC0CAL0_2V5_GAIN_MASK )
+#define DEVINFO_ADC0_GAIN2V5_MASK _DEVINFO_ADC0CAL0_2V5_GAIN_MASK
+#elif defined( _DEVINFO_ADC0CAL0_GAIN2V5_MASK )
+#define DEVINFO_ADC0_GAIN2V5_MASK _DEVINFO_ADC0CAL0_GAIN2V5_MASK
+#endif
+
+#if defined( _DEVINFO_ADC0CAL0_2V5_GAIN_SHIFT )
+#define DEVINFO_ADC0_GAIN2V5_SHIFT _DEVINFO_ADC0CAL0_2V5_GAIN_SHIFT
+#elif defined( _DEVINFO_ADC0CAL0_GAIN2V5_SHIFT )
+#define DEVINFO_ADC0_GAIN2V5_SHIFT _DEVINFO_ADC0CAL0_GAIN2V5_SHIFT
+#endif
+
+#if defined( _DEVINFO_ADC0CAL0_2V5_OFFSET_MASK )
+#define DEVINFO_ADC0_OFFSET2V5_MASK _DEVINFO_ADC0CAL0_2V5_OFFSET_MASK
+#elif defined( _DEVINFO_ADC0CAL0_OFFSET2V5_MASK )
+#define DEVINFO_ADC0_OFFSET2V5_MASK _DEVINFO_ADC0CAL0_OFFSET2V5_MASK
+#endif
+
+#if defined( _DEVINFO_ADC0CAL0_2V5_OFFSET_SHIFT )
+#define DEVINFO_ADC0_OFFSET2V5_SHIFT _DEVINFO_ADC0CAL0_2V5_OFFSET_SHIFT
+#elif defined( _DEVINFO_ADC0CAL0_OFFSET2V5_SHIFT )
+#define DEVINFO_ADC0_OFFSET2V5_SHIFT _DEVINFO_ADC0CAL0_OFFSET2V5_SHIFT
+#endif
+
+#if defined( _DEVINFO_ADC0CAL1_VDD_GAIN_MASK )
+#define DEVINFO_ADC0_GAINVDD_MASK _DEVINFO_ADC0CAL1_VDD_GAIN_MASK
+#elif defined( _DEVINFO_ADC0CAL1_GAINVDD_MASK )
+#define DEVINFO_ADC0_GAINVDD_MASK _DEVINFO_ADC0CAL1_GAINVDD_MASK
+#endif
+
+#if defined( _DEVINFO_ADC0CAL1_VDD_GAIN_SHIFT )
+#define DEVINFO_ADC0_GAINVDD_SHIFT _DEVINFO_ADC0CAL1_VDD_GAIN_SHIFT
+#elif defined( _DEVINFO_ADC0CAL1_GAINVDD_SHIFT )
+#define DEVINFO_ADC0_GAINVDD_SHIFT _DEVINFO_ADC0CAL1_GAINVDD_SHIFT
+#endif
+
+#if defined( _DEVINFO_ADC0CAL1_VDD_OFFSET_MASK )
+#define DEVINFO_ADC0_OFFSETVDD_MASK _DEVINFO_ADC0CAL1_VDD_OFFSET_MASK
+#elif defined( _DEVINFO_ADC0CAL1_OFFSETVDD_MASK )
+#define DEVINFO_ADC0_OFFSETVDD_MASK _DEVINFO_ADC0CAL1_OFFSETVDD_MASK
+#endif
+
+#if defined( _DEVINFO_ADC0CAL1_VDD_OFFSET_SHIFT )
+#define DEVINFO_ADC0_OFFSETVDD_SHIFT _DEVINFO_ADC0CAL1_VDD_OFFSET_SHIFT
+#elif defined( _DEVINFO_ADC0CAL1_OFFSETVDD_SHIFT )
+#define DEVINFO_ADC0_OFFSETVDD_SHIFT _DEVINFO_ADC0CAL1_OFFSETVDD_SHIFT
+#endif
+
+#if defined( _DEVINFO_ADC0CAL1_5VDIFF_GAIN_MASK )
+#define DEVINFO_ADC0_GAIN5VDIFF_MASK _DEVINFO_ADC0CAL1_5VDIFF_GAIN_MASK
+#elif defined( _DEVINFO_ADC0CAL1_GAIN5VDIFF_MASK )
+#define DEVINFO_ADC0_GAIN5VDIFF_MASK _DEVINFO_ADC0CAL1_GAIN5VDIFF_MASK
+#endif
+
+#if defined( _DEVINFO_ADC0CAL1_5VDIFF_GAIN_SHIFT )
+#define DEVINFO_ADC0_GAIN5VDIFF_SHIFT _DEVINFO_ADC0CAL1_5VDIFF_GAIN_SHIFT
+#elif defined( _DEVINFO_ADC0CAL1_GAIN5VDIFF_SHIFT )
+#define DEVINFO_ADC0_GAIN5VDIFF_SHIFT _DEVINFO_ADC0CAL1_GAIN5VDIFF_SHIFT
+#endif
+
+#if defined( _DEVINFO_ADC0CAL1_5VDIFF_OFFSET_MASK )
+#define DEVINFO_ADC0_OFFSET5VDIFF_MASK _DEVINFO_ADC0CAL1_5VDIFF_OFFSET_MASK
+#elif defined( _DEVINFO_ADC0CAL1_OFFSET5VDIFF_MASK )
+#define DEVINFO_ADC0_OFFSET5VDIFF_MASK _DEVINFO_ADC0CAL1_OFFSET5VDIFF_MASK
+#endif
+
+#if defined( _DEVINFO_ADC0CAL1_5VDIFF_OFFSET_SHIFT )
+#define DEVINFO_ADC0_OFFSET5VDIFF_SHIFT _DEVINFO_ADC0CAL1_5VDIFF_OFFSET_SHIFT
+#elif defined( _DEVINFO_ADC0CAL1_OFFSET5VDIFF_SHIFT )
+#define DEVINFO_ADC0_OFFSET5VDIFF_SHIFT _DEVINFO_ADC0CAL1_OFFSET5VDIFF_SHIFT
+#endif
+
+#if defined( _DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_MASK )
+#define DEVINFO_ADC0_OFFSET2XVDD_MASK _DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_MASK
+#elif defined( _DEVINFO_ADC0CAL2_OFFSET2XVDD_MASK )
+#define DEVINFO_ADC0_OFFSET2XVDD_MASK _DEVINFO_ADC0CAL2_OFFSET2XVDD_MASK
+#endif
+
+#if defined( _DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_SHIFT )
+#define DEVINFO_ADC0_OFFSET2XVDD_SHIFT _DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_SHIFT
+#elif defined( _DEVINFO_ADC0CAL2_OFFSET2XVDD_SHIFT )
+#define DEVINFO_ADC0_OFFSET2XVDD_SHIFT _DEVINFO_ADC0CAL2_OFFSET2XVDD_SHIFT
+#endif
+
 /** @endcond */
 
 
@@ -74,14 +187,13 @@
 
 /***************************************************************************//**
  * @brief
- *   Load SCAN calibrate register with predefined values for a certain
- *   reference.
+ *   Load ADC calibration register for a selected reference and conversion mode.
  *
  * @details
- *   During production, calibration values are made and stored in the device
- *   information page for known references. Notice that for external references,
+ *   During production, calibration values are stored in the device
+ *   information page for internal references. Notice that for external references,
  *   calibration values must be determined explicitly, and this function
- *   will not modify the calibration register.
+ *   will not modify the calibration register for external references.
  *
  * @param[in] adc
  *   Pointer to ADC peripheral register block.
@@ -89,143 +201,135 @@
  * @param[in] ref
  *   Reference to load calibrated values for. No values are loaded for
  *   external references.
+ *
+ * @param[in] setScanCal
+ *   Select scan mode (true) or single mode (false) calibration load.
  ******************************************************************************/
-static void ADC_CalibrateLoadScan(ADC_TypeDef *adc, ADC_Ref_TypeDef ref)
+static void ADC_LoadDevinfoCal(ADC_TypeDef *adc,
+                               ADC_Ref_TypeDef ref,
+                               bool setScanCal)
 {
-  uint32_t cal;
+  uint32_t calReg;
+  uint32_t newCal;
+  uint32_t mask;
+  uint32_t shift;
 
-  /* Load proper calibration data depending on selected reference */
-  /* NOTE: We use ...SCAN... defines below, they are the same as */
-  /* similar ...SINGLE... defines. */
+  if (setScanCal)
+  {
+    shift = _ADC_CAL_SCANOFFSET_SHIFT;
+    mask  = ~(_ADC_CAL_SCANOFFSET_MASK
+#if defined( _ADC_CAL_SCANOFFSETINV_MASK )
+              | _ADC_CAL_SCANOFFSETINV_MASK
+#endif
+              | _ADC_CAL_SCANGAIN_MASK);
+  }
+  else
+  {
+    shift = _ADC_CAL_SINGLEOFFSET_SHIFT;
+    mask  = ~(_ADC_CAL_SINGLEOFFSET_MASK
+#if defined( _ADC_CAL_SINGLEOFFSETINV_MASK )
+              | _ADC_CAL_SINGLEOFFSETINV_MASK
+#endif
+              | _ADC_CAL_SINGLEGAIN_MASK);
+  }
+
+  calReg = adc->CAL & mask;
+  newCal = 0;
+
   switch (ref)
   {
-  case adcRef1V25:
-    cal  = adc->CAL & ~(_ADC_CAL_SCANOFFSET_MASK | _ADC_CAL_SCANGAIN_MASK);
-    cal |= ((DEVINFO->ADC0CAL0 & _DEVINFO_ADC0CAL0_1V25_GAIN_MASK) >>
-            _DEVINFO_ADC0CAL0_1V25_GAIN_SHIFT) << _ADC_CAL_SCANGAIN_SHIFT;
-    cal |= ((DEVINFO->ADC0CAL0 & _DEVINFO_ADC0CAL0_1V25_OFFSET_MASK) >>
-            _DEVINFO_ADC0CAL0_1V25_OFFSET_SHIFT) << _ADC_CAL_SCANOFFSET_SHIFT;
-    adc->CAL = cal;
-    break;
-
-  case adcRef2V5:
-    cal  = adc->CAL & ~(_ADC_CAL_SCANOFFSET_MASK | _ADC_CAL_SCANGAIN_MASK);
-    cal |= ((DEVINFO->ADC0CAL0 & _DEVINFO_ADC0CAL0_2V5_GAIN_MASK) >>
-            _DEVINFO_ADC0CAL0_2V5_GAIN_SHIFT) << _ADC_CAL_SCANGAIN_SHIFT;
-    cal |= ((DEVINFO->ADC0CAL0 & _DEVINFO_ADC0CAL0_2V5_OFFSET_MASK) >>
-            _DEVINFO_ADC0CAL0_2V5_OFFSET_SHIFT) << _ADC_CAL_SCANOFFSET_SHIFT;
-    adc->CAL = cal;
-    break;
+    case adcRef1V25:
+      newCal |= ((DEVINFO->ADC0CAL0 & DEVINFO_ADC0_GAIN1V25_MASK)
+                 >> DEVINFO_ADC0_GAIN1V25_SHIFT)
+                << _ADC_CAL_SINGLEGAIN_SHIFT;
+      newCal |= ((DEVINFO->ADC0CAL0 & DEVINFO_ADC0_OFFSET1V25_MASK)
+                 >> DEVINFO_ADC0_OFFSET1V25_SHIFT)
+                << _ADC_CAL_SINGLEOFFSET_SHIFT;
+#if defined( _ADC_CAL_SINGLEOFFSETINV_MASK )
+      newCal |= ((DEVINFO->ADC0CAL0 & _DEVINFO_ADC0CAL0_NEGSEOFFSET1V25_MASK)
+                 >> _DEVINFO_ADC0CAL0_NEGSEOFFSET1V25_SHIFT)
+                << _ADC_CAL_SINGLEOFFSETINV_SHIFT;
+#endif
+      break;
 
-  case adcRefVDD:
-    cal  = adc->CAL & ~(_ADC_CAL_SCANOFFSET_MASK | _ADC_CAL_SCANGAIN_MASK);
-    cal |= ((DEVINFO->ADC0CAL1 & _DEVINFO_ADC0CAL1_VDD_GAIN_MASK) >>
-            _DEVINFO_ADC0CAL1_VDD_GAIN_SHIFT) << _ADC_CAL_SCANGAIN_SHIFT;
-    cal |= ((DEVINFO->ADC0CAL1 & _DEVINFO_ADC0CAL1_VDD_OFFSET_MASK) >>
-            _DEVINFO_ADC0CAL1_VDD_OFFSET_SHIFT) << _ADC_CAL_SCANOFFSET_SHIFT;
-    adc->CAL = cal;
-    break;
+    case adcRef2V5:
+      newCal |= ((DEVINFO->ADC0CAL0 & DEVINFO_ADC0_GAIN2V5_MASK)
+                 >> DEVINFO_ADC0_GAIN2V5_SHIFT)
+                << _ADC_CAL_SINGLEGAIN_SHIFT;
+      newCal |= ((DEVINFO->ADC0CAL0 & DEVINFO_ADC0_OFFSET2V5_MASK)
+                 >> DEVINFO_ADC0_OFFSET2V5_SHIFT)
+                << _ADC_CAL_SINGLEOFFSET_SHIFT;
+#if defined( _ADC_CAL_SINGLEOFFSETINV_MASK )
+      newCal |= ((DEVINFO->ADC0CAL0 & _DEVINFO_ADC0CAL0_NEGSEOFFSET2V5_MASK)
+                 >> _DEVINFO_ADC0CAL0_NEGSEOFFSET2V5_SHIFT)
+                << _ADC_CAL_SINGLEOFFSETINV_SHIFT;
+#endif
+      break;
 
-  case adcRef5VDIFF:
-    cal  = adc->CAL & ~(_ADC_CAL_SCANOFFSET_MASK | _ADC_CAL_SCANGAIN_MASK);
-    cal |= ((DEVINFO->ADC0CAL1 & _DEVINFO_ADC0CAL1_5VDIFF_GAIN_MASK) >>
-            _DEVINFO_ADC0CAL1_5VDIFF_GAIN_SHIFT) << _ADC_CAL_SCANGAIN_SHIFT;
-    cal |= ((DEVINFO->ADC0CAL1 & _DEVINFO_ADC0CAL1_5VDIFF_OFFSET_MASK) >>
-            _DEVINFO_ADC0CAL1_5VDIFF_OFFSET_SHIFT) << _ADC_CAL_SCANOFFSET_SHIFT;
-    adc->CAL = cal;
-    break;
-
-  case adcRef2xVDD:
-    /* Gain value not of relevance for this reference, leave as is */
-    cal  = adc->CAL & ~_ADC_CAL_SCANOFFSET_MASK;
-    cal |= ((DEVINFO->ADC0CAL2 & _DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_MASK) >>
-            _DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_SHIFT) << _ADC_CAL_SCANOFFSET_SHIFT;
-    adc->CAL = cal;
-    break;
-
-  /* For external references, the calibration must be determined for the */
-  /* specific application and set explicitly. */
-  default:
-    break;
-  }
-}
+    case adcRefVDD:
+      newCal |= ((DEVINFO->ADC0CAL1 & DEVINFO_ADC0_GAINVDD_MASK)
+                 >> DEVINFO_ADC0_GAINVDD_SHIFT)
+                << _ADC_CAL_SINGLEGAIN_SHIFT;
+      newCal |= ((DEVINFO->ADC0CAL1 & DEVINFO_ADC0_OFFSETVDD_MASK)
+                 >> DEVINFO_ADC0_OFFSETVDD_SHIFT)
+                 << _ADC_CAL_SINGLEOFFSET_SHIFT;
+#if defined( _ADC_CAL_SINGLEOFFSETINV_MASK )
+      newCal |= ((DEVINFO->ADC0CAL1 & _DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_MASK)
+                 >> _DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_SHIFT)
+                << _ADC_CAL_SINGLEOFFSETINV_SHIFT;
+#endif
+      break;
 
-/***************************************************************************//**
- * @brief
- *   Load SINGLE calibrate register with predefined values for a certain
- *   reference.
- *
- * @details
- *   During production, calibration values are made and stored in the device
- *   information page for known references. Notice that for external references,
- *   calibration values must be determined explicitly, and this function
- *   will not modify the calibration register.
- *
- * @param[in] adc
- *   Pointer to ADC peripheral register block.
- *
- * @param[in] ref
- *   Reference to load calibrated values for. No values are loaded for
- *   external references.
- ******************************************************************************/
-static void ADC_CalibrateLoadSingle(ADC_TypeDef *adc, ADC_Ref_TypeDef ref)
-{
-  uint32_t cal;
-
-  /* Load proper calibration data depending on selected reference */
-  /* NOTE: We use ...SCAN... defines below, they are the same as */
-  /* similar ...SINGLE... defines. */
-  switch (ref)
-  {
-  case adcRef1V25:
-    cal  = adc->CAL & ~(_ADC_CAL_SINGLEOFFSET_MASK | _ADC_CAL_SINGLEGAIN_MASK);
-    cal |= ((DEVINFO->ADC0CAL0 & _DEVINFO_ADC0CAL0_1V25_GAIN_MASK) >>
-            _DEVINFO_ADC0CAL0_1V25_GAIN_SHIFT) << _ADC_CAL_SINGLEGAIN_SHIFT;
-    cal |= ((DEVINFO->ADC0CAL0 & _DEVINFO_ADC0CAL0_1V25_OFFSET_MASK) >>
-            _DEVINFO_ADC0CAL0_1V25_OFFSET_SHIFT) << _ADC_CAL_SINGLEOFFSET_SHIFT;
-    adc->CAL = cal;
-    break;
+    case adcRef5VDIFF:
+      newCal |= ((DEVINFO->ADC0CAL1 & DEVINFO_ADC0_GAIN5VDIFF_MASK)
+                 >> DEVINFO_ADC0_GAIN5VDIFF_SHIFT)
+                << _ADC_CAL_SINGLEGAIN_SHIFT;
+      newCal |= ((DEVINFO->ADC0CAL1 & DEVINFO_ADC0_OFFSET5VDIFF_MASK)
+                 >> DEVINFO_ADC0_OFFSET5VDIFF_SHIFT)
+                << _ADC_CAL_SINGLEOFFSET_SHIFT;
+#if defined( _ADC_CAL_SINGLEOFFSETINV_MASK )
+      newCal |= ((DEVINFO->ADC0CAL1 & _DEVINFO_ADC0CAL1_NEGSEOFFSET5VDIFF_MASK)
+                 >> _DEVINFO_ADC0CAL1_NEGSEOFFSET5VDIFF_SHIFT)
+                << _ADC_CAL_SINGLEOFFSETINV_SHIFT;
+#endif
+      break;
 
-  case adcRef2V5:
-    cal  = adc->CAL & ~(_ADC_CAL_SINGLEOFFSET_MASK | _ADC_CAL_SINGLEGAIN_MASK);
-    cal |= ((DEVINFO->ADC0CAL0 & _DEVINFO_ADC0CAL0_2V5_GAIN_MASK) >>
-            _DEVINFO_ADC0CAL0_2V5_GAIN_SHIFT) << _ADC_CAL_SINGLEGAIN_SHIFT;
-    cal |= ((DEVINFO->ADC0CAL0 & _DEVINFO_ADC0CAL0_2V5_OFFSET_MASK) >>
-            _DEVINFO_ADC0CAL0_2V5_OFFSET_SHIFT) << _ADC_CAL_SINGLEOFFSET_SHIFT;
-    adc->CAL = cal;
-    break;
-
-  case adcRefVDD:
-    cal  = adc->CAL & ~(_ADC_CAL_SINGLEOFFSET_MASK | _ADC_CAL_SINGLEGAIN_MASK);
-    cal |= ((DEVINFO->ADC0CAL1 & _DEVINFO_ADC0CAL1_VDD_GAIN_MASK) >>
-            _DEVINFO_ADC0CAL1_VDD_GAIN_SHIFT) << _ADC_CAL_SINGLEGAIN_SHIFT;
-    cal |= ((DEVINFO->ADC0CAL1 & _DEVINFO_ADC0CAL1_VDD_OFFSET_MASK) >>
-            _DEVINFO_ADC0CAL1_VDD_OFFSET_SHIFT) << _ADC_CAL_SINGLEOFFSET_SHIFT;
-    adc->CAL = cal;
-    break;
+    case adcRef2xVDD:
+      /* There is no gain calibration for this reference */
+      newCal |= ((DEVINFO->ADC0CAL2 & DEVINFO_ADC0_OFFSET2XVDD_MASK)
+                 >> DEVINFO_ADC0_OFFSET2XVDD_SHIFT)
+                << _ADC_CAL_SINGLEOFFSET_SHIFT;
+#if defined( _ADC_CAL_SINGLEOFFSETINV_MASK )
+      newCal |= ((DEVINFO->ADC0CAL2 & _DEVINFO_ADC0CAL2_NEGSEOFFSET2XVDD_MASK)
+                 >> _DEVINFO_ADC0CAL2_NEGSEOFFSET2XVDD_SHIFT)
+                << _ADC_CAL_SINGLEOFFSETINV_SHIFT;
+#endif
+      break;
 
-  case adcRef5VDIFF:
-    cal  = adc->CAL & ~(_ADC_CAL_SINGLEOFFSET_MASK | _ADC_CAL_SINGLEGAIN_MASK);
-    cal |= ((DEVINFO->ADC0CAL1 & _DEVINFO_ADC0CAL1_5VDIFF_GAIN_MASK) >>
-            _DEVINFO_ADC0CAL1_5VDIFF_GAIN_SHIFT) << _ADC_CAL_SINGLEGAIN_SHIFT;
-    cal |= ((DEVINFO->ADC0CAL1 & _DEVINFO_ADC0CAL1_5VDIFF_OFFSET_MASK) >>
-            _DEVINFO_ADC0CAL1_5VDIFF_OFFSET_SHIFT) << _ADC_CAL_SINGLEOFFSET_SHIFT;
-    adc->CAL = cal;
-    break;
+#if defined( _ADC_SINGLECTRLX_VREFSEL_VDDXWATT )
+    case adcRefVddxAtt:
+      newCal |= ((DEVINFO->ADC0CAL1 & DEVINFO_ADC0_GAINVDD_MASK)
+                 >> DEVINFO_ADC0_GAINVDD_SHIFT)
+                << _ADC_CAL_SINGLEGAIN_SHIFT;
+      newCal |= ((DEVINFO->ADC0CAL1 & DEVINFO_ADC0_OFFSETVDD_MASK)
+                 >> DEVINFO_ADC0_OFFSETVDD_SHIFT)
+                << _ADC_CAL_SINGLEOFFSET_SHIFT;
+      newCal |= ((DEVINFO->ADC0CAL1 & _DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_MASK)
+                 >> _DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_SHIFT)
+                << _ADC_CAL_SINGLEOFFSETINV_SHIFT;
+      break;
+#endif
 
-  case adcRef2xVDD:
-    /* Gain value not of relevance for this reference, leave as is */
-    cal  = adc->CAL & ~_ADC_CAL_SINGLEOFFSET_MASK;
-    cal |= ((DEVINFO->ADC0CAL2 & _DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_MASK) >>
-            _DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_SHIFT) << _ADC_CAL_SINGLEOFFSET_SHIFT;
-    adc->CAL = cal;
-    break;
+    /* For external references, the calibration must be determined for the
+       specific application and set by the user. Calibration data is also not
+       available for the internal references adcRefVBGR, adcRefVEntropy and
+       adcRefVBGRlow. */
+    default:
+      newCal = 0;
+      break;
+  }
 
-  /* For external references, the calibration must be determined for the */
-  /* specific application and set explicitly. */
-  default:
-    break;
-  }
+  adc->CAL = calReg | (newCal << shift);
 }
 
 /** @endcond */
@@ -243,6 +347,10 @@
  *   In addition, single and/or scan control configuration must be done, please
  *   refer to ADC_InitSingle() and ADC_InitScan() respectively.
  *
+ *   On ADC architectures with the ADCn->SCANCHCONF register,
+ *   ADC_ScanSingleEndedInit() and ADC_ScanDifferentialInit() can be used to
+ *   assist scan conversion input setup.
+ *
  * @note
  *   This function will stop any ongoing conversion.
  *
@@ -261,23 +369,295 @@
   /* Make sure conversion is not in progress */
   adc->CMD = ADC_CMD_SINGLESTOP | ADC_CMD_SCANSTOP;
 
-  tmp = ((uint32_t)(init->ovsRateSel) << _ADC_CTRL_OVSRSEL_SHIFT) |
-        (((uint32_t)(init->timebase) << _ADC_CTRL_TIMEBASE_SHIFT) & _ADC_CTRL_TIMEBASE_MASK) |
-        (((uint32_t)(init->prescale) << _ADC_CTRL_PRESC_SHIFT) & _ADC_CTRL_PRESC_MASK) |
-        ((uint32_t)(init->lpfMode) << _ADC_CTRL_LPFMODE_SHIFT) |
-        ((uint32_t)(init->warmUpMode) << _ADC_CTRL_WARMUPMODE_SHIFT);
+  tmp = ((uint32_t)(init->ovsRateSel) << _ADC_CTRL_OVSRSEL_SHIFT)
+        | (((uint32_t)(init->timebase) << _ADC_CTRL_TIMEBASE_SHIFT)
+          & _ADC_CTRL_TIMEBASE_MASK)
+        | (((uint32_t)(init->prescale) << _ADC_CTRL_PRESC_SHIFT)
+          & _ADC_CTRL_PRESC_MASK)
+#if defined ( _ADC_CTRL_LPFMODE_MASK )
+        | ((uint32_t)(init->lpfMode) << _ADC_CTRL_LPFMODE_SHIFT)
+#endif
+        | ((uint32_t)(init->warmUpMode) << _ADC_CTRL_WARMUPMODE_SHIFT);
 
   if (init->tailgate)
   {
     tmp |= ADC_CTRL_TAILGATE;
   }
+  adc->CTRL = tmp;
 
-  adc->CTRL = tmp;
+  /* Set ADC EM2 clock configuration */
+#if defined( _ADC_CTRL_ADCCLKMODE_MASK )
+  BUS_RegMaskedWrite(&ADC0->CTRL,
+                     _ADC_CTRL_ADCCLKMODE_MASK | _ADC_CTRL_ASYNCCLKEN_MASK,
+                     init->em2ClockConfig << _ADC_CTRL_ASYNCCLKEN_SHIFT);
+#endif
+
+#if defined( _SILICON_LABS_32B_PLATFORM_2 )
+  /* Fix for errata ADC_EXXX */
+  ADC_IntClear(adc, ADC_IFC_SCANUF);
+#endif
+}
+
+
+#if defined( _ADC_SCANINPUTSEL_MASK )
+/***************************************************************************//**
+ * @brief
+ *   Clear ADC scan input configuration.
+ *
+ * @param[in] scanInit
+ *   Struct to hold the scan configuration, input configuration.
+ ******************************************************************************/
+void ADC_ScanInputClear(ADC_InitScan_TypeDef *scanInit)
+{
+  /* Clear input configuration */
+
+  /* Select none */
+  scanInit->scanInputConfig.scanInputSel = 0xFFFFFFFF;
+  scanInit->scanInputConfig.scanInputEn = 0;
+
+  /* Default alternative negative inputs */
+  scanInit->scanInputConfig.scanNegSel = _ADC_SCANNEGSEL_RESETVALUE;
+}
+
+
+/***************************************************************************//**
+ * @brief
+ *   Initialize ADC scan single-ended input configuration.
+ *
+ * @details
+ *   Set configuration for ADC scan conversion with single-ended inputs. The
+ *   ADC_InitScan_TypeDef struct updated from this function should be passed to
+ *   ADC_InitScan().
+ *
+ * @param[in] inputGroup
+ *   ADC scan input group. See section 25.3.4 in the reference manual for
+ *   more information.
+ *
+ * @param[in] singleEndedSel
+ *   APORT select.
+ *
+ * @return
+ *   Scan ID of selected ADC input. ee section 25.3.4 in the reference manual for
+ *   more information. Note that the returned integer represents the bit position
+ *   in ADCn_SCANMASK set by this function. The accumulated mask is stored in
+ *   scanInit->scanInputConfig->scanInputEn.
+ ******************************************************************************/
+uint32_t ADC_ScanSingleEndedInputAdd(ADC_InitScan_TypeDef *scanInit,
+                                     ADC_ScanInputGroup_TypeDef inputGroup,
+                                     ADC_PosSel_TypeDef singleEndedSel)
+{
+  uint32_t currentSel;
+  uint32_t newSel;
+  uint32_t scanId;
+
+  scanInit->diff = false;
+
+  /* Check for unsupported APORTs */
+  EFM_ASSERT((singleEndedSel <= adcPosSelAPORT0YCH0) || (singleEndedSel >= adcPosSelAPORT0YCH15));
+
+  /* Decode the input group select by shifting right by 3 */
+  newSel = singleEndedSel >> 3;
+
+  currentSel = (scanInit->scanInputConfig.scanInputSel >> (inputGroup * 8)) & 0xFF;
+
+  /* If none selected */
+  if (currentSel == 0xFF)
+  {
+    scanInit->scanInputConfig.scanInputSel &= ~(0xFF << (inputGroup * 8));
+    scanInit->scanInputConfig.scanInputSel |= (newSel << (inputGroup * 8));
+  }
+  else if (currentSel == newSel)
+  {
+    /* Ok, but do nothing.  */
+  }
+  else
+  {
+    /* Invalid channel range. A range is already selected for this group. */
+    EFM_ASSERT(false);
+  }
+
+  /* Update and return scan input enable mask (SCANMASK) */
+  scanId = (inputGroup * 8) + (singleEndedSel & 0x7);
+  EFM_ASSERT(scanId < 32);
+  scanInit->scanInputConfig.scanInputEn |= 0x1 << scanId;
+  return scanId;
 }
 
 
 /***************************************************************************//**
  * @brief
+ *   Initialize ADC scan differential input configuration.
+ *
+ * @details
+ *   Set configuration for ADC scan conversion with differential inputs. The
+ *   ADC_InitScan_TypeDef struct updated by this function should be passed to
+ *   ADC_InitScan().
+ *
+ * @param[in] scanInit
+ *   Struct to hold the scan and input configuration.
+ *
+ * @param[in] inputGroup
+ *   ADC scan input group. See section 25.3.4 in the reference manual for
+ *   more information.
+ *
+ * @param[in] posSel
+ *   APORT bus pair select. The negative terminal is implicitly selected by
+ *   the positive terminal.
+ *
+ * @param[in] negInput
+ *   ADC scan alternative negative input. Set to adcScanNegInputDefault to select
+ *   default negative input (implicit from posSel).
+ *
+ * @return
+ *   Scan ID of selected ADC input. ee section 25.3.4 in the reference manual for
+ *   more information. Note that the returned integer represents the bit position
+ *   in ADCn_SCANMASK set by this function. The accumulated mask is stored in
+ *   scanInit->scanInputConfig->scanInputEn.
+ ******************************************************************************/
+uint32_t ADC_ScanDifferentialInputAdd(ADC_InitScan_TypeDef *scanInit,
+                                      ADC_ScanInputGroup_TypeDef inputGroup,
+                                      ADC_PosSel_TypeDef posSel,
+                                      ADC_ScanNegInput_TypeDef negInput)
+{
+  uint32_t negInputRegMask = 0;
+  uint32_t negInputRegShift = 0;
+  uint32_t negInputRegVal = 0;
+  uint32_t scanId = 0;
+
+  /* Do a single ended init, then update for differential scan. */
+  scanId = ADC_ScanSingleEndedInputAdd(scanInit, inputGroup, posSel);
+
+  /* Reset to differential mode */
+  scanInit->diff = true;
+
+  /* Set negative ADC input, unless the default is selected. */
+  if (negInput != adcScanNegInputDefault)
+  {
+    if (scanId == 0)
+    {
+      negInputRegMask  = _ADC_SCANNEGSEL_INPUT0NEGSEL_MASK;
+      negInputRegShift = _ADC_SCANNEGSEL_INPUT0NEGSEL_SHIFT;
+      EFM_ASSERT(inputGroup == 0);
+    }
+    else if (scanId == 2)
+    {
+      negInputRegMask  = _ADC_SCANNEGSEL_INPUT2NEGSEL_MASK;
+      negInputRegShift = _ADC_SCANNEGSEL_INPUT2NEGSEL_SHIFT;
+      EFM_ASSERT(inputGroup == 0);
+    }
+    else if (scanId == 4)
+    {
+      negInputRegMask  = _ADC_SCANNEGSEL_INPUT4NEGSEL_MASK;
+      negInputRegShift = _ADC_SCANNEGSEL_INPUT4NEGSEL_SHIFT;
+      EFM_ASSERT(inputGroup == 0);
+    }
+    else if (scanId == 6)
+    {
+      negInputRegMask  = _ADC_SCANNEGSEL_INPUT6NEGSEL_MASK;
+      negInputRegShift = _ADC_SCANNEGSEL_INPUT6NEGSEL_SHIFT;
+      EFM_ASSERT(inputGroup == 0);
+    }
+    else if (scanId == 9)
+    {
+      negInputRegMask  = _ADC_SCANNEGSEL_INPUT9NEGSEL_MASK;
+      negInputRegShift = _ADC_SCANNEGSEL_INPUT9NEGSEL_SHIFT;
+      EFM_ASSERT(inputGroup == 1);
+    }
+    else if (scanId == 11)
+    {
+      negInputRegMask  = _ADC_SCANNEGSEL_INPUT11NEGSEL_MASK;
+      negInputRegShift = _ADC_SCANNEGSEL_INPUT11NEGSEL_SHIFT;
+      EFM_ASSERT(inputGroup == 1);
+    }
+    else if (scanId == 13)
+    {
+      negInputRegMask  = _ADC_SCANNEGSEL_INPUT13NEGSEL_MASK;
+      negInputRegShift = _ADC_SCANNEGSEL_INPUT13NEGSEL_SHIFT;
+      EFM_ASSERT(inputGroup == 1);
+    }
+    else if (scanId == 15)
+    {
+      negInputRegMask  = _ADC_SCANNEGSEL_INPUT15NEGSEL_MASK;
+      negInputRegShift = _ADC_SCANNEGSEL_INPUT15NEGSEL_SHIFT;
+      EFM_ASSERT(inputGroup == 1);
+    }
+    else
+    {
+      /* There is not negative input option for this positive input (negInput is posInput + 1). */
+      EFM_ASSERT(false);
+    }
+
+    /* Find ADC_SCANNEGSEL_CHxNSEL value for positive input 0, 2, 4 and 6 */
+    if (inputGroup == 0)
+    {
+      switch (negInput)
+      {
+        case adcScanNegInput1:
+          negInputRegVal = _ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT1;
+          break;
+
+        case adcScanNegInput3:
+          negInputRegVal = _ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT3;
+          break;
+
+        case adcScanNegInput5:
+          negInputRegVal = _ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT5;
+          break;
+
+        case adcScanNegInput7:
+          negInputRegVal = _ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT7;
+          break;
+
+        default:
+          /* Invalid selection. Options are input 1, 3, 5 and 7. */
+          EFM_ASSERT(false);
+          break;
+      }
+    }
+    else if (inputGroup == 1)
+    {
+      /* Find ADC_SCANNEGSEL_CHxNSEL value for positive input 9, 11, 13 and 15 */
+      switch (negInput)
+      {
+        case adcScanNegInput8:
+          negInputRegVal = _ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT8;
+          break;
+
+        case adcScanNegInput10:
+          negInputRegVal = _ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT10;
+          break;
+
+        case adcScanNegInput12:
+          negInputRegVal = _ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT12;
+          break;
+
+        case adcScanNegInput14:
+          negInputRegVal = _ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT14;
+          break;
+
+        default:
+          /* Invalid selection. Options are input 8, 10, 12 and 14. */
+          EFM_ASSERT(false);
+          break;
+      }
+    }
+    else
+    {
+      /* No alternative negative input for input group > 1 */
+      EFM_ASSERT(false);
+    }
+
+    /* Update config */
+    scanInit->scanInputConfig.scanNegSel &= ~negInputRegMask;
+    scanInit->scanInputConfig.scanNegSel |= negInputRegVal << negInputRegShift;
+  }
+  return scanId;
+}
+#endif
+
+
+/***************************************************************************//**
+ * @brief
  *   Initialize ADC scan sequence.
  *
  * @details
@@ -305,14 +685,18 @@
   /* Make sure scan sequence is not in progress */
   adc->CMD = ADC_CMD_SCANSTOP;
 
-  /* Load proper calibration data depending on selected reference */
-  ADC_CalibrateLoadScan(adc, init->reference);
+  /* Load calibration data for selected reference */
+  ADC_LoadDevinfoCal(adc, init->reference, true);
 
-  tmp = ((uint32_t)(init->prsSel) << _ADC_SCANCTRL_PRSSEL_SHIFT) |
-        ((uint32_t)(init->acqTime) << _ADC_SCANCTRL_AT_SHIFT) |
-        ((uint32_t)(init->reference) << _ADC_SCANCTRL_REF_SHIFT) |
-        init->input |
-        ((uint32_t)(init->resolution) << _ADC_SCANCTRL_RES_SHIFT);
+  tmp = 0
+#if defined ( _ADC_SCANCTRL_PRSSEL_MASK )
+        | (init->prsSel << _ADC_SCANCTRL_PRSSEL_SHIFT)
+#endif
+        | (init->acqTime << _ADC_SCANCTRL_AT_SHIFT)
+#if defined ( _ADC_SCANCTRL_INPUTMASK_MASK )
+        | init->input
+#endif
+        | (init->resolution << _ADC_SCANCTRL_RES_SHIFT);
 
   if (init->prsEnable)
   {
@@ -324,17 +708,82 @@
     tmp |= ADC_SCANCTRL_ADJ_LEFT;
   }
 
+#if defined( _ADC_SCANCTRL_INPUTMASK_MASK )
   if (init->diff)
+#elif defined( _ADC_SCANINPUTSEL_MASK )
+  if (init->diff)
+#endif
   {
     tmp |= ADC_SCANCTRL_DIFF;
   }
 
   if (init->rep)
   {
+#if defined( _SILICON_LABS_32B_PLATFORM_2 )
+  /* Scan repeat mode does not work on platform 2 as described in errata  ADC_EXXX. */
+  EFM_ASSERT(false);
+#endif
     tmp |= ADC_SCANCTRL_REP;
   }
 
+  /* Set scan reference. Check if reference configuraion is extended to SCANCTRLX. */
+#if defined ( _ADC_SCANCTRLX_VREFSEL_MASK )
+  if (init->reference & ADC_CTRLX_VREFSEL_REG)
+  {
+    /* Select extension register */
+    tmp |= ADC_SCANCTRL_REF_CONF;
+  }
+  else
+  {
+    tmp |= init->reference << _ADC_SCANCTRL_REF_SHIFT;
+  }
+#else
+  tmp |= init->reference << _ADC_SCANCTRL_REF_SHIFT;
+#endif
+
+#if defined( _ADC_SCANCTRL_INPUTMASK_MASK )
+  tmp |= init->input;
+#endif
+
   adc->SCANCTRL = tmp;
+
+  /* Update SINGLECTRLX for reference select and PRS select */
+#if defined ( _ADC_SCANCTRLX_MASK )
+  tmp = adc->SCANCTRLX & ~(_ADC_SCANCTRLX_VREFSEL_MASK
+                         | _ADC_SCANCTRLX_PRSSEL_MASK
+                         | _ADC_SCANCTRLX_FIFOOFACT_MASK);
+  if (init->reference & ADC_CTRLX_VREFSEL_REG)
+  {
+    tmp |= (init->reference & ~ADC_CTRLX_VREFSEL_REG) << _ADC_SCANCTRLX_VREFSEL_SHIFT;
+  }
+
+  tmp |= init->prsSel << _ADC_SCANCTRLX_PRSSEL_SHIFT;
+
+  if (init->fifoOverwrite)
+  {
+    tmp |= ADC_SCANCTRLX_FIFOOFACT_OVERWRITE;
+  }
+
+  adc->SCANCTRLX = tmp;
+#endif
+
+#if defined( _ADC_CTRL_SCANDMAWU_MASK )
+  BUS_RegBitWrite(&adc->CTRL, _ADC_CTRL_SCANDMAWU_SHIFT, init->scanDmaEm2Wu);
+#endif
+
+  /* Write scan input configuration */
+#if defined( _ADC_SCANINPUTSEL_MASK )
+  adc->SCANINPUTSEL = init->scanInputConfig.scanInputSel;
+  adc->SCANMASK     = init->scanInputConfig.scanInputEn;
+  adc->SCANNEGSEL   = init->scanInputConfig.scanNegSel;
+#endif
+
+  /* Assert for any APORT bus conflicts programming errors */
+#if defined( _ADC_BUSCONFLICT_MASK )
+  tmp = adc->BUSREQ;
+  EFM_ASSERT(!(tmp & adc->BUSCONFLICT));
+  EFM_ASSERT(!(adc->STATUS & _ADC_STATUS_PROGERR_MASK));
+#endif
 }
 
 
@@ -367,14 +816,24 @@
   /* Make sure single conversion is not in progress */
   adc->CMD = ADC_CMD_SINGLESTOP;
 
-  /* Load proper calibration data depending on selected reference */
-  ADC_CalibrateLoadSingle(adc, init->reference);
+  /* Load calibration data for selected reference */
+  ADC_LoadDevinfoCal(adc, init->reference, false);
 
-  tmp = ((uint32_t)(init->prsSel) << _ADC_SINGLECTRL_PRSSEL_SHIFT) |
-        ((uint32_t)(init->acqTime) << _ADC_SINGLECTRL_AT_SHIFT) |
-        ((uint32_t)(init->reference) << _ADC_SINGLECTRL_REF_SHIFT) |
-        ((uint32_t)(init->input) << _ADC_SINGLECTRL_INPUTSEL_SHIFT) |
-        ((uint32_t)(init->resolution) << _ADC_SINGLECTRL_RES_SHIFT);
+  tmp = 0
+#if defined( _ADC_SINGLECTRL_PRSSEL_MASK )
+        | (init->prsSel << _ADC_SINGLECTRL_PRSSEL_SHIFT)
+#endif
+        | (init->acqTime << _ADC_SINGLECTRL_AT_SHIFT)
+#if defined( _ADC_SINGLECTRL_INPUTSEL_MASK )
+        | (init->input << _ADC_SINGLECTRL_INPUTSEL_SHIFT)
+#endif
+#if defined( _ADC_SINGLECTRL_POSSEL_MASK )
+        | (init->posSel << _ADC_SINGLECTRL_POSSEL_SHIFT)
+#endif
+#if defined( _ADC_SINGLECTRL_NEGSEL_MASK )
+        | (init->negSel << _ADC_SINGLECTRL_NEGSEL_SHIFT)
+#endif
+        | ((uint32_t)(init->resolution) << _ADC_SINGLECTRL_RES_SHIFT);
 
   if (init->prsEnable)
   {
@@ -396,10 +855,86 @@
     tmp |= ADC_SINGLECTRL_REP;
   }
 
+  /* Set single reference. Check if reference configuraion is extended to SINGLECTRLX. */
+#if defined ( _ADC_SINGLECTRLX_MASK )
+  if (init->reference & ADC_CTRLX_VREFSEL_REG)
+  {
+    /* Select extension register */
+    tmp |= ADC_SINGLECTRL_REF_CONF;
+  }
+  else
+  {
+    tmp |= (init->reference << _ADC_SINGLECTRL_REF_SHIFT);
+  }
+#else
+  tmp |= (init->reference << _ADC_SINGLECTRL_REF_SHIFT);
+#endif
   adc->SINGLECTRL = tmp;
+
+  /* Update SINGLECTRLX for reference select and PRS select */
+#if defined ( _ADC_SINGLECTRLX_VREFSEL_MASK )
+  tmp = adc->SINGLECTRLX & (_ADC_SINGLECTRLX_VREFSEL_MASK
+                          | _ADC_SINGLECTRLX_PRSSEL_MASK
+                          | _ADC_SINGLECTRLX_FIFOOFACT_MASK);
+  if (init->reference & ADC_CTRLX_VREFSEL_REG)
+  {
+    tmp |= ((init->reference & ~ADC_CTRLX_VREFSEL_REG) << _ADC_SINGLECTRLX_VREFSEL_SHIFT);
+  }
+
+  tmp |= ((init->prsSel << _ADC_SINGLECTRLX_PRSSEL_SHIFT));
+
+  if (init->fifoOverwrite)
+  {
+    tmp |= ADC_SINGLECTRLX_FIFOOFACT_OVERWRITE;
+  }
+
+  adc->SINGLECTRLX = tmp;
+#endif
+
+  /* Set DMA availability in EM2 */
+#if defined( _ADC_CTRL_SINGLEDMAWU_MASK )
+  BUS_RegBitWrite(&ADC0->CTRL, _ADC_CTRL_SINGLEDMAWU_SHIFT, init->singleDmaEm2Wu);
+#endif
+
+  /* Assert for any APORT bus conflicts programming errors */
+#if defined( _ADC_BUSCONFLICT_MASK )
+  tmp = adc->BUSREQ;
+  EFM_ASSERT(!(tmp & adc->BUSCONFLICT));
+  EFM_ASSERT(!(adc->STATUS & _ADC_STATUS_PROGERR_MASK));
+#endif
 }
 
 
+#if defined( _ADC_SCANDATAX_MASK )
+/***************************************************************************//**
+ * @brief
+ *   Get scan result and scan select ID.
+ *
+ * @note
+ *   Only use if scan data valid. This function does not check the DV flag.
+ *   The return value is intended to be used as a index for the scan select ID.
+ *
+ * @param[in] adc
+ *   Pointer to ADC peripheral register block.
+ *
+ * @param[out] scanId
+ *   Scan select ID of first data in scan FIFO.
+ *
+ * @return
+ *   First scan data in scan FIFO.
+ ******************************************************************************/
+uint32_t ADC_DataIdScanGet(ADC_TypeDef *adc, uint32_t *scanId)
+{
+  uint32_t scanData;
+
+  /* Pop data FIFO with scan ID */
+  scanData = adc->SCANDATAX;
+  *scanId = (scanData & _ADC_SCANDATAX_SCANINPUTID_MASK) >> _ADC_SCANDATAX_SCANINPUTID_SHIFT;
+  return (scanData & _ADC_SCANDATAX_DATA_MASK) >> _ADC_SCANDATAX_DATA_SHIFT;
+}
+#endif
+
+
 /***************************************************************************//**
  * @brief
  *   Calculate prescaler value used to determine ADC clock.
@@ -461,19 +996,42 @@
 void ADC_Reset(ADC_TypeDef *adc)
 {
   /* Stop conversions, before resetting other registers. */
-  adc->CMD        = ADC_CMD_SINGLESTOP | ADC_CMD_SCANSTOP;
-  adc->SINGLECTRL = _ADC_SINGLECTRL_RESETVALUE;
-  adc->SCANCTRL   = _ADC_SCANCTRL_RESETVALUE;
-  adc->CTRL       = _ADC_CTRL_RESETVALUE;
-  adc->IEN        = _ADC_IEN_RESETVALUE;
-  adc->IFC        = _ADC_IFC_MASK;
-  adc->BIASPROG   = _ADC_BIASPROG_RESETVALUE;
+  adc->CMD          = ADC_CMD_SINGLESTOP | ADC_CMD_SCANSTOP;
+  adc->SINGLECTRL   = _ADC_SINGLECTRL_RESETVALUE;
+#if defined( _ADC_SINGLECTRLX_MASK )
+  adc->SINGLECTRLX  = _ADC_SINGLECTRLX_RESETVALUE;
+#endif
+  adc->SCANCTRL     = _ADC_SCANCTRL_RESETVALUE;
+#if defined( _ADC_SCANCTRLX_MASK )
+  adc->SCANCTRLX    = _ADC_SCANCTRLX_RESETVALUE;
+#endif
+  adc->CTRL         = _ADC_CTRL_RESETVALUE;
+  adc->IEN          = _ADC_IEN_RESETVALUE;
+  adc->IFC          = _ADC_IFC_MASK;
+  adc->BIASPROG     = _ADC_BIASPROG_RESETVALUE;
+#if defined( _ADC_SCANMASK_MASK )
+  adc->SCANMASK     = _ADC_SCANMASK_RESETVALUE;
+#endif
+#if defined( _ADC_SCANINPUTSEL_MASK )
+  adc->SCANINPUTSEL = _ADC_SCANINPUTSEL_RESETVALUE;
+#endif
+#if defined( _ADC_SCANNEGSEL_MASK )
+  adc->SCANNEGSEL   = _ADC_SCANNEGSEL_RESETVALUE;
+#endif
+
+  /* Clear data FIFOs */
+#if defined( _ADC_SINGLEFIFOCLEAR_MASK )
+  adc->SINGLEFIFOCLEAR |= ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR;
+  adc->SCANFIFOCLEAR   |= ADC_SCANFIFOCLEAR_SCANFIFOCLEAR;
+#endif
 
   /* Load calibration values for the 1V25 internal reference. */
-  ADC_CalibrateLoadSingle(adc, adcRef1V25);
-  ADC_CalibrateLoadScan(adc, adcRef1V25);
+  ADC_LoadDevinfoCal(adc, adcRef1V25, false);
+  ADC_LoadDevinfoCal(adc, adcRef1V25, true);
 
+#if defined( _ADC_SCANINPUTSEL_MASK )
   /* Do not reset route register, setting should be done independently */
+#endif
 }
 
 
@@ -499,13 +1057,13 @@
       hfperFreq = 1;
     }
   }
-#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
+#if defined( _EFM32_GIANT_FAMILY ) || defined( _EFM32_WONDER_FAMILY )
   /* Handle errata on Giant Gecko, max TIMEBASE is 5 bits wide or max 0x1F */
   /* cycles. This will give a warmp up time of e.g. 0.645us, not the       */
   /* required 1us when operating at 48MHz. One must also increase acqTime  */
   /* to compensate for the missing clock cycles, adding up to 1us in total.*/
   /* See reference manual for details. */
-  if( hfperFreq > 32000000 )
+  if ( hfperFreq > 32000000 )
   {
     hfperFreq = 32000000;
   }

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_aes.c	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_aes.c	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /***************************************************************************//**
  * @file em_aes.c
- * @brief Advanced Encryption Standard (AES) accelerator peripheral API
- * @version 3.20.12
+ * @brief Advanced Encryption Standard (AES) accelerator peripheral API.
+ * @version 4.2.1
  *******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
  *******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,7 +30,6 @@
  *
  ******************************************************************************/
 
-
 #include "em_aes.h"
 #if defined(AES_COUNT) && (AES_COUNT > 0)
 
@@ -42,11 +41,10 @@
 
 /***************************************************************************//**
  * @addtogroup AES
- * @brief Advanced Encryption Standard Accelerator (AES) Peripheral API for
- *   EFM32
+ * @brief Advanced Encryption Standard Accelerator (AES) Peripheral API.
  * @details
- *   This API is intended for use on EFM32 target devices, and the following
- *   input/output notations should be noted:
+ *   This API is intended for use on Silicon Labs target devices, and the
+ *   following input/output notations should be noted:
  *
  *   @li Input/output data (plaintext, ciphertext, key etc) are treated as
  *     byte arrays, starting with most significant byte. Ie, 32 bytes of
@@ -58,7 +56,7 @@
  *
  *   @li Byte arrays should be word (32 bit) aligned for performance
  *     considerations, since the array is accessed with 32 bit access type.
- *     The EFM32 supports unaligned accesses, but with a performance penalty.
+ *     The Cortex-M supports unaligned accesses, but with a performance penalty.
  *
  *   @li It is possible to specify the same output buffer as input buffer
  *     as long as they point to the same address. In that case the provided input

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_assert.c	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_assert.c	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /***************************************************************************//**
  * @file em_assert.c
  * @brief Assert API
- * @version 3.20.12
+ * @version 4.2.1
  *******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
  *******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_burtc.c	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_burtc.c	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /***************************************************************************//**
  * @file em_burtc.c
  * @brief Backup Real Time Counter (BURTC) Peripheral API
- * @version 3.20.12
+ * @version 4.2.1
  *******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
  *******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -31,12 +31,8 @@
  ******************************************************************************/
 
 
-#include "em_device.h"
+#include "em_burtc.h"
 #if defined(BURTC_PRESENT)
-#include "em_burtc.h"
-
-#include "em_assert.h"
-#include "em_bitband.h"
 
 /***************************************************************************//**
  * @addtogroup EM_Library
@@ -57,13 +53,14 @@
  **************************   LOCAL FUNCTIONS   ********************************
  ******************************************************************************/
 
+/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
 /***************************************************************************//**
  * @brief Convert dividend to prescaler logarithmic value. Only works for even
  *        numbers equal to 2^n
  * @param[in] div Unscaled dividend,
  * @return Base 2 logarithm of input, as used by fixed prescalers
  ******************************************************************************/
-__STATIC_INLINE uint32_t BURTC_DivToLog2(uint32_t div)
+__STATIC_INLINE uint32_t divToLog2(uint32_t div)
 {
   uint32_t log2;
 
@@ -85,7 +82,7 @@
  *   Bitmask corresponding to SYNCBUSY register defined bits, indicating
  *   registers that must complete any ongoing synchronization.
  ******************************************************************************/
-__STATIC_INLINE void BURTC_Sync(uint32_t mask)
+__STATIC_INLINE void regSync(uint32_t mask)
 {
   /* Avoid deadlock if modifying the same register twice when freeze mode is
      activated, or when no clock is selected for the BURTC. If no clock is
@@ -100,6 +97,7 @@
   while (BURTC->SYNCBUSY & mask)
     ;
 }
+/** @endcond */
 
 
 /*******************************************************************************
@@ -116,7 +114,7 @@
  *   Before initialization, BURTC module must first be enabled by clearing the
  *   reset bit in the RMU, i.e.
  * @verbatim
- *   RMU_ResetControl(rmuResetBU, false);
+ *   RMU_ResetControl(rmuResetBU, rmuResetModeClear);
  * @endverbatim
  *   Compare channel 0 must be configured outside this function, before
  *   initialization if enable is set to true. The counter will always be reset.
@@ -138,16 +136,18 @@
   EFM_ASSERT(burtcInit->lowPowerComp <= 6);
   /* You cannot enable the BURTC if mode is set to disabled */
   EFM_ASSERT((burtcInit->enable == false) ||
-             ((burtcInit->enable == true) && (burtcInit->mode != burtcModeDisable)));
+             ((burtcInit->enable == true)
+              && (burtcInit->mode != burtcModeDisable)));
   /* Low power mode is only available with LFRCO or LFXO as clock source */
-  EFM_ASSERT((burtcInit->clkSel != burtcClkSelULFRCO) ||
-             ((burtcInit->clkSel == burtcClkSelULFRCO) && (burtcInit->lowPowerMode == burtcLPDisable)));
+  EFM_ASSERT((burtcInit->clkSel != burtcClkSelULFRCO)
+             || ((burtcInit->clkSel == burtcClkSelULFRCO)
+                  && (burtcInit->lowPowerMode == burtcLPDisable)));
 
   /* Calculate prescaler value from clock divider input */
   /* Note! If clock select (clkSel) is ULFRCO, a clock divisor (clkDiv) of
      value 1 will select a 2kHz ULFRCO clock, while any other value will
      select a 1kHz ULFRCO clock source. */
-  presc = BURTC_DivToLog2(burtcInit->clkDiv);
+  presc = divToLog2(burtcInit->clkDiv);
 
   /* Make sure all registers are updated simultaneously */
   if (burtcInit->enable)
@@ -157,20 +157,20 @@
 
   /* Modification of LPMODE register requires sync with potential ongoing
    * register updates in LF domain. */
-  BURTC_Sync(BURTC_SYNCBUSY_LPMODE);
+  regSync(BURTC_SYNCBUSY_LPMODE);
 
   /* Configure low power mode */
   BURTC->LPMODE = (uint32_t) (burtcInit->lowPowerMode);
 
   /* New configuration */
-  ctrl = ((BURTC_CTRL_RSTEN) |
-          (burtcInit->mode) |
-          (burtcInit->debugRun << _BURTC_CTRL_DEBUGRUN_SHIFT) |
-          (burtcInit->compare0Top << _BURTC_CTRL_COMP0TOP_SHIFT) |
-          (burtcInit->lowPowerComp << _BURTC_CTRL_LPCOMP_SHIFT) |
-          (presc << _BURTC_CTRL_PRESC_SHIFT) |
-          (burtcInit->clkSel) |
-          (burtcInit->timeStamp << _BURTC_CTRL_BUMODETSEN_SHIFT));
+  ctrl = (BURTC_CTRL_RSTEN
+          | (burtcInit->mode)
+          | (burtcInit->debugRun << _BURTC_CTRL_DEBUGRUN_SHIFT)
+          | (burtcInit->compare0Top << _BURTC_CTRL_COMP0TOP_SHIFT)
+          | (burtcInit->lowPowerComp << _BURTC_CTRL_LPCOMP_SHIFT)
+          | (presc << _BURTC_CTRL_PRESC_SHIFT)
+          | (burtcInit->clkSel)
+          | (burtcInit->timeStamp << _BURTC_CTRL_BUMODETSEN_SHIFT));
 
   /* Clear interrupts */
   BURTC_IntClear(0xFFFFFFFF);
@@ -205,7 +205,7 @@
 
   /* Modification of COMP0 register requires sync with potential ongoing
    * register updates in LF domain. */
-  BURTC_Sync(BURTC_SYNCBUSY_COMP0);
+  regSync(BURTC_SYNCBUSY_COMP0);
 
   /* Configure compare channel 0 */
   BURTC->COMP0 = value;
@@ -235,8 +235,8 @@
 void BURTC_CounterReset(void)
 {
   /* Set and clear reset bit */
-  BITBAND_Peripheral(&BURTC->CTRL, _BURTC_CTRL_RSTEN_SHIFT, 1);
-  BITBAND_Peripheral(&BURTC->CTRL, _BURTC_CTRL_RSTEN_SHIFT, 0);
+  BUS_RegBitWrite(&BURTC->CTRL, _BURTC_CTRL_RSTEN_SHIFT, 1);
+  BUS_RegBitWrite(&BURTC->CTRL, _BURTC_CTRL_RSTEN_SHIFT, 0);
 }
 
 
@@ -253,9 +253,9 @@
   bool buResetState;
 
   /* Read reset state, set reset and restore state */
-  buResetState = BITBAND_PeripheralRead(&RMU->CTRL, _RMU_CTRL_BURSTEN_SHIFT);
-  BITBAND_Peripheral(&RMU->CTRL, _RMU_CTRL_BURSTEN_SHIFT, 1);
-  BITBAND_Peripheral(&RMU->CTRL, _RMU_CTRL_BURSTEN_SHIFT, buResetState);
+  buResetState = BUS_RegBitRead(&RMU->CTRL, _RMU_CTRL_BURSTEN_SHIFT);
+  BUS_RegBitWrite(&RMU->CTRL, _RMU_CTRL_BURSTEN_SHIFT, 1);
+  BUS_RegBitWrite(&RMU->CTRL, _RMU_CTRL_BURSTEN_SHIFT, buResetState);
 }
 
 
@@ -277,32 +277,32 @@
 
   switch (clkSel)
   {
-  /** Ultra low frequency (1 kHz) clock */
-  case BURTC_CTRL_CLKSEL_ULFRCO:
-    if (_BURTC_CTRL_PRESC_DIV1 == clkDiv)
-    {
-      frequency = 2000;     /* 2KHz when clock divisor is 1. */
-    }
-    else
-    {
-      frequency = SystemULFRCOClockGet();  /* 1KHz when divisor is different
-                                              from 1. */
-    }
-    break;
+    /** Ultra low frequency (1 kHz) clock */
+    case BURTC_CTRL_CLKSEL_ULFRCO:
+      if (_BURTC_CTRL_PRESC_DIV1 == clkDiv)
+      {
+        frequency = 2000;     /* 2KHz when clock divisor is 1. */
+      }
+      else
+      {
+        frequency = SystemULFRCOClockGet();  /* 1KHz when divisor is different
+                                                from 1. */
+      }
+      break;
 
-  /** Low frequency RC oscillator */
-  case BURTC_CTRL_CLKSEL_LFRCO:
-    frequency = SystemLFRCOClockGet() / (1 << clkDiv); /* freq=32768/2^clkDiv */
-    break;
+    /** Low frequency RC oscillator */
+    case BURTC_CTRL_CLKSEL_LFRCO:
+      frequency = SystemLFRCOClockGet() / (1 << clkDiv); /* freq=32768/2^clkDiv */
+      break;
 
-  /** Low frequency crystal osciallator */
-  case BURTC_CTRL_CLKSEL_LFXO:
-    frequency = SystemLFXOClockGet() / (1 << clkDiv); /* freq=32768/2^clkDiv */
-    break;
+    /** Low frequency crystal osciallator */
+    case BURTC_CTRL_CLKSEL_LFXO:
+      frequency = SystemLFXOClockGet() / (1 << clkDiv); /* freq=32768/2^clkDiv */
+      break;
 
-  default:
-    /* No clock selected for BURTC. */
-    frequency = 0;
+    default:
+      /* No clock selected for BURTC. */
+      frequency = 0;
   }
   return frequency;
 }

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_cmu.c	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_cmu.c	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /***************************************************************************//**
  * @file em_cmu.c
  * @brief Clock management unit (CMU) Peripheral API
- * @version 3.20.12
+ * @version 4.2.1
  *******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
  *******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -29,14 +29,15 @@
  * arising from your use of this Software.
  *
  ******************************************************************************/
-
-
 #include "em_cmu.h"
 #if defined( CMU_PRESENT )
 
+#include <stddef.h>
+#include <limits.h>
 #include "em_assert.h"
-#include "em_bitband.h"
+#include "em_bus.h"
 #include "em_emu.h"
+#include "em_system.h"
 
 /***************************************************************************//**
  * @addtogroup EM_Library
@@ -55,30 +56,41 @@
 
 /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
 
-/** Maximum allowed core frequency when using 0 wait states on flash access. */
+#if defined( _SILICON_LABS_32B_PLATFORM_2 )
+/** Maximum allowed core frequency when using 0 wait-states on flash access. */
+#define CMU_MAX_FREQ_0WS    26000000
+/** Maximum allowed core frequency when using 1 wait-states on flash access */
+#define CMU_MAX_FREQ_1WS    40000000
+#elif defined( _SILICON_LABS_32B_PLATFORM_1 )
+/** Maximum allowed core frequency when using 0 wait-states on flash access. */
 #define CMU_MAX_FREQ_0WS    16000000
-/** Maximum allowed core frequency when using 1 wait states on flash access */
+/** Maximum allowed core frequency when using 1 wait-states on flash access */
 #define CMU_MAX_FREQ_1WS    32000000
+#else
+#error "Unkown MCU platform."
+#endif
 
 #if defined( CMU_CTRL_HFLE )
 /** Maximum frequency for HFLE needs to be enabled on Giant, Leopard and
     Wonder. */
-#if defined ( _EFM32_WONDER_FAMILY ) ||  \
-    defined ( _EZR32_LEOPARD_FAMILY ) || \
-    defined ( _EZR32_WONDER_FAMILY )
-#define CMU_MAX_FREQ_HFLE   24000000
+#if defined( _EFM32_WONDER_FAMILY )     \
+    || defined( _EZR32_LEOPARD_FAMILY ) \
+    || defined( _EZR32_WONDER_FAMILY )
+#define CMU_MAX_FREQ_HFLE() 24000000
 #elif defined ( _EFM32_GIANT_FAMILY )
-#define CMU_MAX_FREQ_HFLE   (CMU_MaxFreqHfle())
+#define CMU_MAX_FREQ_HFLE() (maxFreqHfle())
 #else
 #error Invalid part/device.
 #endif
 #endif
 
-/** Low frequency A group identifier */
-#define CMU_LFA             0
-
-/** Low frequency B group identifier */
-#define CMU_LFB             1
+/*******************************************************************************
+ **************************   LOCAL VARIABLES   ********************************
+ ******************************************************************************/
+
+#if defined( _CMU_AUXHFRCOCTRL_FREQRANGE_MASK )
+static CMU_AUXHFRCOFreq_TypeDef auxHfrcoFreq = cmuAUXHFRCOFreq_19M0Hz;
+#endif
 
 /** @endcond */
 
@@ -88,50 +100,104 @@
 
 /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
 
-#if defined( CMU_CTRL_HFLE ) &&         \
-  !defined ( _EFM32_WONDER_FAMILY ) &&  \
-  !defined ( _EZR32_LEOPARD_FAMILY ) && \
-  !defined ( _EZR32_WONDER_FAMILY )
+/***************************************************************************//**
+ * @brief
+ *   Get the AUX clock frequency. Used by MSC flash programming and LESENSE,
+ *   by default also as debug clock.
+ *
+ * @return
+ *   AUX Frequency in Hz
+ ******************************************************************************/
+static uint32_t auxClkGet(void)
+{
+  uint32_t ret;
+
+#if defined( _CMU_AUXHFRCOCTRL_FREQRANGE_MASK )
+  ret = auxHfrcoFreq;
+
+#elif defined( _CMU_AUXHFRCOCTRL_BAND_MASK )
+  /* All Geckos from TG and newer */
+  switch(CMU->AUXHFRCOCTRL & _CMU_AUXHFRCOCTRL_BAND_MASK)
+  {
+    case CMU_AUXHFRCOCTRL_BAND_1MHZ:
+      ret = 1000000;
+      break;
+
+    case CMU_AUXHFRCOCTRL_BAND_7MHZ:
+      ret = 7000000;
+      break;
+
+    case CMU_AUXHFRCOCTRL_BAND_11MHZ:
+      ret = 11000000;
+      break;
+
+    case CMU_AUXHFRCOCTRL_BAND_14MHZ:
+      ret = 14000000;
+      break;
+
+    case CMU_AUXHFRCOCTRL_BAND_21MHZ:
+      ret = 21000000;
+      break;
+
+#if defined( _CMU_AUXHFRCOCTRL_BAND_28MHZ )
+    case CMU_AUXHFRCOCTRL_BAND_28MHZ:
+      ret = 28000000;
+      break;
+#endif
+
+    default:
+      EFM_ASSERT(0);
+      ret = 0;
+      break;
+  }
+
+#else
+  /* Gecko has a fixed 14Mhz AUXHFRCO clock */
+  ret = 14000000;
+
+#endif
+
+  return ret;
+}
+
 
 /***************************************************************************//**
  * @brief
- *   Return max allowed frequency for low energy peripherals.
+ *   Get the Debug Trace clock frequency
+ *
+ * @return
+ *   Debug Trace frequency in Hz
  ******************************************************************************/
-static uint32_t CMU_MaxFreqHfle(void)
+static uint32_t dbgClkGet(void)
 {
-  /* SYSTEM_GetFamily and SYSTEM_ChipRevisionGet could have been used here
-     but we want to minimize dependencies in em_cmu.c. */
-  uint16_t majorMinorRev;
-  uint8_t  deviceFamily = ((DEVINFO->PART & _DEVINFO_PART_DEVICE_FAMILY_MASK)
-                           >> _DEVINFO_PART_DEVICE_FAMILY_SHIFT);
-  switch (deviceFamily)
+  uint32_t ret;
+  CMU_Select_TypeDef clk;
+
+  /* Get selected clock source */
+  clk = CMU_ClockSelectGet(cmuClock_DBG);
+
+  switch(clk)
   {
-  case _DEVINFO_PART_DEVICE_FAMILY_LG:
-    /* CHIP MAJOR bit [3:0] */
-    majorMinorRev = (((ROMTABLE->PID0 & _ROMTABLE_PID0_REVMAJOR_MASK)
-                      >> _ROMTABLE_PID0_REVMAJOR_SHIFT) << 8);
-    /* CHIP MINOR bit [7:4] */
-    majorMinorRev |= (((ROMTABLE->PID2 & _ROMTABLE_PID2_REVMINORMSB_MASK)
-                       >> _ROMTABLE_PID2_REVMINORMSB_SHIFT) << 4);
-    /* CHIP MINOR bit [3:0] */
-    majorMinorRev |=  ((ROMTABLE->PID3 & _ROMTABLE_PID3_REVMINORLSB_MASK)
-                       >> _ROMTABLE_PID3_REVMINORLSB_SHIFT);
-
-    if (majorMinorRev >= 0x0204)
-      return 24000000;
-    else
-      return 32000000;
-  case _DEVINFO_PART_DEVICE_FAMILY_GG:
-    return 32000000;
-  case _DEVINFO_PART_DEVICE_FAMILY_WG:
-    return 24000000;
-  default:
-    /* Invalid device family. */
-    EFM_ASSERT(false);
-    return 0;
+    case cmuSelect_HFCLK:
+      ret = SystemHFClockGet();
+#if defined( _CMU_CTRL_HFCLKDIV_MASK )
+      /* Family with an additional divider. */
+      ret = ret / (1 + ((CMU->CTRL & _CMU_CTRL_HFCLKDIV_MASK)
+                        >> _CMU_CTRL_HFCLKDIV_SHIFT));
+#endif
+      break;
+
+    case cmuSelect_AUXHFRCO:
+      ret = auxClkGet();
+      break;
+
+    default:
+      EFM_ASSERT(0);
+      ret = 0;
+      break;
   }
+  return ret;
 }
-#endif
 
 
 /***************************************************************************//**
@@ -139,15 +205,15 @@
  *   Configure flash access wait states in order to support given core clock
  *   frequency.
  *
- * @param[in] hfcoreclk
+ * @param[in] coreFreq
  *   Core clock frequency to configure flash wait-states for
  ******************************************************************************/
-static void CMU_FlashWaitStateControl(uint32_t hfcoreclk)
+static void flashWaitStateControl(uint32_t coreFreq)
 {
   uint32_t mode;
   bool mscLocked;
 #if defined( MSC_READCTRL_MODE_WS0SCBTP )
-  bool scbtpEn;
+  bool scbtpEn;   /* Suppressed Conditional Branch Target Prefetch setting. */
 #endif
 
   /* Make sure the MSC is unlocked */
@@ -180,12 +246,12 @@
   {
   }
 #if defined( MSC_READCTRL_MODE_WS2 )
-  else if (hfcoreclk > CMU_MAX_FREQ_1WS)
+  else if (coreFreq > CMU_MAX_FREQ_1WS)
   {
     mode = (scbtpEn ? MSC_READCTRL_MODE_WS2SCBTP : MSC_READCTRL_MODE_WS2);
   }
 #endif
-  else if ((hfcoreclk <= CMU_MAX_FREQ_1WS) && (hfcoreclk > CMU_MAX_FREQ_0WS))
+  else if ((coreFreq <= CMU_MAX_FREQ_1WS) && (coreFreq > CMU_MAX_FREQ_0WS))
   {
     mode = (scbtpEn ? MSC_READCTRL_MODE_WS1SCBTP : MSC_READCTRL_MODE_WS1);
   }
@@ -200,12 +266,12 @@
   {
   }
 #if defined( MSC_READCTRL_MODE_WS2 )
-  else if (hfcoreclk > CMU_MAX_FREQ_1WS)
+  else if (coreFreq > CMU_MAX_FREQ_1WS)
   {
     mode = MSC_READCTRL_MODE_WS2;
   }
 #endif
-  else if ((hfcoreclk <= CMU_MAX_FREQ_1WS) && (hfcoreclk > CMU_MAX_FREQ_0WS))
+  else if ((coreFreq <= CMU_MAX_FREQ_1WS) && (coreFreq > CMU_MAX_FREQ_0WS))
   {
     mode = MSC_READCTRL_MODE_WS1;
   }
@@ -229,62 +295,249 @@
 /***************************************************************************//**
  * @brief
  *   Configure flash access wait states to most conservative setting for
- *   this target. Retain SCBTP setting.
+ *   this target. Retain SCBTP (Suppressed Conditional Branch Target Prefetch)
+ *   setting.
  ******************************************************************************/
-static void CMU_FlashWaitStateMax(void)
+static void flashWaitStateMax(void)
 {
-  uint32_t maxCoreClock;
-#if defined   (_EFM32_GECKO_FAMILY)
-  maxCoreClock = 32000000;
-#elif defined (_EFM32_GIANT_FAMILY)
-  maxCoreClock = 48000000;
-#elif defined (_EFM32_TINY_FAMILY)
-  maxCoreClock = 32000000;
-#elif defined (_EFM32_LEOPARD_FAMILY)
-  maxCoreClock = 48000000;
-#elif defined (_EFM32_WONDER_FAMILY)
-  maxCoreClock = 48000000;
-#elif defined (_EFM32_ZERO_FAMILY)
-  maxCoreClock = 24000000;
-#elif defined (_EFM32_HAPPY_FAMILY)
-  maxCoreClock = 25000000;
-#else
-#error "Max core clock frequency is not defined for this family"
-#endif
-
-  /* Use SystemMaxCoreClockGet() when available in CMSIS */
-  CMU_FlashWaitStateControl(maxCoreClock);
+  flashWaitStateControl(SystemMaxCoreClockGet());
 }
 
 
 /***************************************************************************//**
- * @brief Convert dividend to prescaler logarithmic value. Only works for even
- *        numbers equal to 2^n
- * @param[in] div Unscaled dividend,
- * @return Base 2 logarithm of input, as used by fixed prescalers
+ * @brief
+ *   Get the LFnCLK frequency based on current configuration.
+ *
+ * @param[in] lfClkBranch
+ *   Selected LF branch
+ *
+ * @return
+ *   The LFnCLK frequency in Hz. If no LFnCLK is selected (disabled), 0 is
+ *   returned.
  ******************************************************************************/
-__STATIC_INLINE uint32_t CMU_DivToLog2(CMU_ClkDiv_TypeDef div)
+static uint32_t lfClkGet(CMU_Clock_TypeDef lfClkBranch)
 {
-  uint32_t log2;
-
-  /* Prescalers take argument of 32768 or less */
-  EFM_ASSERT((div>0) && (div <= 32768));
-
-  /* Count leading zeroes and "reverse" result, Cortex-M3 intrinsic */
-  log2 = (31 - __CLZ(div));
-
-  return log2;
+  uint32_t sel;
+  uint32_t ret = 0;
+
+  switch (lfClkBranch)
+  {
+    case cmuClock_LFA:
+    case cmuClock_LFB:
+#if defined( _CMU_LFCCLKEN0_MASK )
+    case cmuClock_LFC:
+#endif
+#if defined( _CMU_LFECLKSEL_MASK )
+    case cmuClock_LFE:
+#endif
+      break;
+
+    default:
+      EFM_ASSERT(0);
+      break;
+  }
+
+  sel = CMU_ClockSelectGet(lfClkBranch);
+
+  /* Get clock select field */
+  switch (lfClkBranch)
+  {
+    case cmuClock_LFA:
+#if defined( _CMU_LFCLKSEL_MASK )
+      sel = (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFA_MASK) >> _CMU_LFCLKSEL_LFA_SHIFT;
+#elif defined( _CMU_LFACLKSEL_MASK )
+      sel = (CMU->LFACLKSEL & _CMU_LFACLKSEL_LFA_MASK) >> _CMU_LFACLKSEL_LFA_SHIFT;
+#else
+      EFM_ASSERT(0);
+#endif
+      break;
+
+    case cmuClock_LFB:
+#if defined( _CMU_LFCLKSEL_MASK )
+      sel = (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFB_MASK) >> _CMU_LFCLKSEL_LFB_SHIFT;
+#elif defined( _CMU_LFBCLKSEL_MASK )
+      sel = (CMU->LFBCLKSEL & _CMU_LFBCLKSEL_LFB_MASK) >> _CMU_LFBCLKSEL_LFB_SHIFT;
+#else
+      EFM_ASSERT(0);
+#endif
+      break;
+
+#if defined( _CMU_LFCCLKEN0_MASK )
+    case cmuClock_LFC:
+      sel = (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFC_MASK) >> _CMU_LFCLKSEL_LFC_SHIFT;
+      break;
+#endif
+
+#if defined( _CMU_LFECLKSEL_MASK )
+    case cmuClock_LFE:
+      sel = (CMU->LFECLKSEL & _CMU_LFECLKSEL_LFE_MASK) >> _CMU_LFECLKSEL_LFE_SHIFT;
+      break;
+#endif
+
+    default:
+      EFM_ASSERT(0);
+      break;
+  }
+
+  /* Get clock frequency */
+#if defined( _CMU_LFCLKSEL_MASK )
+  switch (sel)
+  {
+    case _CMU_LFCLKSEL_LFA_LFRCO:
+      ret = SystemLFRCOClockGet();
+      break;
+
+    case _CMU_LFCLKSEL_LFA_LFXO:
+      ret = SystemLFXOClockGet();
+      break;
+
+#if defined( _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 )
+    case _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2:
+#if defined( CMU_CTRL_HFLE )
+      /* Family which can use an extra div 4 divider  */
+      /* (and must if >32MHz) or HFLE is set.         */
+      if(((CMU->HFCORECLKDIV & _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK)
+           == CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4)
+         || (CMU->CTRL & CMU_CTRL_HFLE))
+      {
+        ret = SystemCoreClockGet() / 4U;
+      }
+      else
+      {
+        ret = SystemCoreClockGet() / 2U;
+      }
+#else
+      ret = SystemCoreClockGet() / 2U;
+#endif
+      break;
+#endif
+
+    case _CMU_LFCLKSEL_LFA_DISABLED:
+      ret = 0;
+#if defined( CMU_LFCLKSEL_LFAE )
+      /* Check LF Extended bit setting for LFA or LFB ULFRCO clock */
+      if ((lfClkBranch == cmuClock_LFA) || (lfClkBranch == cmuClock_LFB))
+      {
+        if (CMU->LFCLKSEL >> (lfClkBranch == cmuClock_LFA
+                              ? _CMU_LFCLKSEL_LFAE_SHIFT
+                              : _CMU_LFCLKSEL_LFBE_SHIFT))
+        {
+          ret = SystemULFRCOClockGet();
+        }
+      }
+#endif
+      break;
+
+    default:
+      EFM_ASSERT(0);
+      ret = 0U;
+      break;
+  }
+#endif /* _CMU_LFCLKSEL_MASK */
+
+#if defined( _CMU_LFACLKSEL_MASK )
+  switch (sel)
+  {
+    case _CMU_LFACLKSEL_LFA_LFRCO:
+      ret = SystemLFRCOClockGet();
+      break;
+
+    case _CMU_LFACLKSEL_LFA_LFXO:
+      ret = SystemLFXOClockGet();
+      break;
+
+    case _CMU_LFACLKSEL_LFA_ULFRCO:
+      ret = SystemULFRCOClockGet();
+      break;
+
+#if defined( _CMU_LFACLKSEL_LFA_HFCLKLE )
+    case _CMU_LFACLKSEL_LFA_HFCLKLE:
+      ret = ((CMU->HFPRESC & _CMU_HFPRESC_HFCLKLEPRESC_MASK)
+             == CMU_HFPRESC_HFCLKLEPRESC_DIV4)
+            ? SystemCoreClockGet() / 4U
+            : SystemCoreClockGet() / 2U;
+      break;
+#elif defined( _CMU_LFBCLKSEL_LFB_HFCLKLE )
+    case _CMU_LFBCLKSEL_LFB_HFCLKLE:
+      ret = ((CMU->HFPRESC & _CMU_HFPRESC_HFCLKLEPRESC_MASK)
+             == CMU_HFPRESC_HFCLKLEPRESC_DIV4)
+            ? SystemCoreClockGet() / 4U
+            : SystemCoreClockGet() / 2U;
+      break;
+#endif
+
+    case _CMU_LFACLKSEL_LFA_DISABLED:
+      ret = 0;
+      break;
+  }
+#endif
+
+  return ret;
 }
 
 
+#if defined( CMU_CTRL_HFLE )              \
+    && !defined( _EFM32_WONDER_FAMILY )   \
+    && !defined( _EZR32_LEOPARD_FAMILY )  \
+    && !defined( _EZR32_WONDER_FAMILY )
+/***************************************************************************//**
+ * @brief
+ *   Return max allowed frequency for low energy peripherals.
+ ******************************************************************************/
+static uint32_t maxFreqHfle(void)
+{
+  uint16_t majorMinorRev;
+
+  switch (SYSTEM_GetFamily())
+  {
+    case systemPartFamilyEfm32Leopard:
+      /* CHIP MAJOR bit [5:0] */
+      majorMinorRev = (((ROMTABLE->PID0 & _ROMTABLE_PID0_REVMAJOR_MASK)
+                        >> _ROMTABLE_PID0_REVMAJOR_SHIFT) << 8);
+      /* CHIP MINOR bit [7:4] */
+      majorMinorRev |= (((ROMTABLE->PID2 & _ROMTABLE_PID2_REVMINORMSB_MASK)
+                         >> _ROMTABLE_PID2_REVMINORMSB_SHIFT) << 4);
+      /* CHIP MINOR bit [3:0] */
+      majorMinorRev |=  ((ROMTABLE->PID3 & _ROMTABLE_PID3_REVMINORLSB_MASK)
+                         >> _ROMTABLE_PID3_REVMINORLSB_SHIFT);
+
+      if (majorMinorRev >= 0x0204)
+        return 24000000;
+      else
+        return 32000000;
+
+    case systemPartFamilyEfm32Giant:
+      return 32000000;
+
+    default:
+      /* Invalid device family. */
+      EFM_ASSERT(false);
+      return 0;
+  }
+}
+#endif
+
+
 /***************************************************************************//**
- * @brief Convert logarithm of 2 prescaler to division factor
- * @param[in] log2
- * @return Dividend
+ * @brief
+ *   Wait for ongoing sync of register(s) to low frequency domain to complete.
+ *
+ * @param[in] mask
+ *   Bitmask corresponding to SYNCBUSY register defined bits, indicating
+ *   registers that must complete any ongoing synchronization.
  ******************************************************************************/
-__STATIC_INLINE uint32_t CMU_Log2ToDiv(uint32_t log2)
+__STATIC_INLINE void syncReg(uint32_t mask)
 {
-  return 1<<log2;
+  /* Avoid deadlock if modifying the same register twice when freeze mode is */
+  /* activated. */
+  if (CMU->FREEZE & CMU_FREEZE_REGFREEZE)
+    return;
+
+  /* Wait for any pending previous write operation to have been completed */
+  /* in low frequency domain */
+  while (CMU->SYNCBUSY & mask)
+  {
+  }
 }
 
 
@@ -296,7 +549,7 @@
  * @return
  *   USBC frequency in Hz
  ******************************************************************************/
-static uint32_t CMU_USBCClkGet(void)
+static uint32_t usbCClkGet(void)
 {
   uint32_t ret;
   CMU_Select_TypeDef clk;
@@ -306,215 +559,230 @@
 
   switch(clk)
   {
-  case cmuSelect_LFXO:
-    ret = SystemLFXOClockGet();
-    break;
-  case cmuSelect_LFRCO:
-    ret = SystemLFRCOClockGet();
-    break;
-  case cmuSelect_HFCLK:
-    ret = SystemHFClockGet();
-    break;
-  default:
-    /* Clock is not enabled */
-    ret = 0;
-    break;
+    case cmuSelect_LFXO:
+      ret = SystemLFXOClockGet();
+      break;
+    case cmuSelect_LFRCO:
+      ret = SystemLFRCOClockGet();
+      break;
+    case cmuSelect_HFCLK:
+      ret = SystemHFClockGet();
+      break;
+    default:
+      /* Clock is not enabled */
+      ret = 0;
+      break;
   }
   return ret;
 }
 #endif
 
 
-/***************************************************************************//**
- * @brief
- *   Get the AUX clock frequency. Used by MSC flash programming and LESENSE,
- *   by default also as debug clock.
- *
- * @return
- *   AUX Frequency in Hz
- ******************************************************************************/
-static uint32_t CMU_AUXClkGet(void)
-{
-  uint32_t ret;
-
-#if defined(_EFM32_GECKO_FAMILY)
-  /* Gecko has a fixed 14Mhz AUXHFRCO clock */
-  ret = 14000000;
-#else
-  switch(CMU->AUXHFRCOCTRL & _CMU_AUXHFRCOCTRL_BAND_MASK)
-  {
-  case CMU_AUXHFRCOCTRL_BAND_1MHZ:
-    ret = 1000000;
-    break;
-  case CMU_AUXHFRCOCTRL_BAND_7MHZ:
-    ret = 7000000;
-    break;
-  case CMU_AUXHFRCOCTRL_BAND_11MHZ:
-    ret = 11000000;
-    break;
-  case CMU_AUXHFRCOCTRL_BAND_14MHZ:
-    ret = 14000000;
-    break;
-  case CMU_AUXHFRCOCTRL_BAND_21MHZ:
-    ret = 21000000;
-    break;
-#if defined( _CMU_AUXHFRCOCTRL_BAND_28MHZ )
-  case CMU_AUXHFRCOCTRL_BAND_28MHZ:
-    ret = 28000000;
-    break;
-#endif
-  default:
-    ret = 0;
-    break;
-  }
-#endif
-  return ret;
-}
-
-
-/***************************************************************************//**
- * @brief
- *   Get the Debug Trace clock frequency
- *
- * @return
- *   Debug Trace frequency in Hz
- ******************************************************************************/
-static uint32_t CMU_DBGClkGet(void)
-{
-  uint32_t ret;
-  CMU_Select_TypeDef clk;
-
-  /* Get selected clock source */
-  clk = CMU_ClockSelectGet(cmuClock_DBG);
-
-  switch(clk)
-  {
-  case cmuSelect_HFCLK:
-    ret = SystemHFClockGet();
-#if defined( _CMU_CTRL_HFCLKDIV_MASK )
-    /* Giant Gecko has an additional divider, not used by USBC */
-    ret = ret / (1 + ((CMU->CTRL & _CMU_CTRL_HFCLKDIV_MASK) >>
-                      _CMU_CTRL_HFCLKDIV_SHIFT));
-#endif
-    break;
-
-  case cmuSelect_AUXHFRCO:
-    ret = CMU_AUXClkGet();
-    break;
-
-  default:
-    EFM_ASSERT(0);
-    ret = 0;
-    break;
-  }
-  return ret;
-}
-
-
-/***************************************************************************//**
- * @brief
- *   Get the LFnCLK frequency based on current configuration.
- *
- * @param[in] lfClkBranch
- *   LF branch, 0 = LFA, 1 = LFB, ...
- *
- * @return
- *   The LFnCLK frequency in Hz. If no LFnCLK is selected (disabled), 0 is
- *   returned.
- ******************************************************************************/
-static uint32_t CMU_LFClkGet(unsigned int lfClkBranch)
-{
-  uint32_t ret;
-
-  EFM_ASSERT(lfClkBranch == CMU_LFA || lfClkBranch == CMU_LFB);
-
-  switch ((CMU->LFCLKSEL >> (lfClkBranch * 2)) & 0x3)
-  {
-  case _CMU_LFCLKSEL_LFA_LFRCO:
-    ret = SystemLFRCOClockGet();
-    break;
-
-  case _CMU_LFCLKSEL_LFA_LFXO:
-    ret = SystemLFXOClockGet();
-    break;
-
-  case _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2:
-#if defined( CMU_CTRL_HFLE )
-    /* Giant Gecko can use a /4 divider (and must if >32MHz) or HFLE is set */
-    if(((CMU->HFCORECLKDIV & _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK) == CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4)||
-       (CMU->CTRL & CMU_CTRL_HFLE))
-    {
-      ret = SystemCoreClockGet() / 4;
-    }
-    else
-    {
-      ret = SystemCoreClockGet() / 2;
-    }
-#else
-    ret = SystemCoreClockGet() / 2;
-#endif
-    break;
-
-  case _CMU_LFCLKSEL_LFA_DISABLED:
-#if defined( CMU_LFCLKSEL_LFAE )
-    /* Check LF Extended bit setting for ULFRCO clock */
-    if(CMU->LFCLKSEL >> (_CMU_LFCLKSEL_LFAE_SHIFT + lfClkBranch * 4))
-    {
-      ret = SystemULFRCOClockGet();
-    }
-    else
-    {
-      ret = 0;
-    }
-#else
-    ret = 0;
-#endif
-    break;
-
-  default:
-    ret = 0;
-    break;
-  }
-
-  return ret;
-}
-
-
-/***************************************************************************//**
- * @brief
- *   Wait for ongoing sync of register(s) to low frequency domain to complete.
- *
- * @param[in] mask
- *   Bitmask corresponding to SYNCBUSY register defined bits, indicating
- *   registers that must complete any ongoing synchronization.
- ******************************************************************************/
-__STATIC_INLINE void CMU_Sync(uint32_t mask)
-{
-  /* Avoid deadlock if modifying the same register twice when freeze mode is */
-  /* activated. */
-  if (CMU->FREEZE & CMU_FREEZE_REGFREEZE)
-    return;
-
-  /* Wait for any pending previous write operation to have been completed */
-  /* in low frequency domain */
-  while (CMU->SYNCBUSY & mask)
-    ;
-}
-
-
 /** @endcond */
 
 /*******************************************************************************
  **************************   GLOBAL FUNCTIONS   *******************************
  ******************************************************************************/
 
+#if defined( _CMU_AUXHFRCOCTRL_BAND_MASK )
+/***************************************************************************//**
+ * @brief
+ *   Get AUXHFRCO band in use.
+ *
+ * @return
+ *   AUXHFRCO band in use.
+ ******************************************************************************/
+CMU_AUXHFRCOBand_TypeDef CMU_AUXHFRCOBandGet(void)
+{
+  return (CMU_AUXHFRCOBand_TypeDef)((CMU->AUXHFRCOCTRL
+                                     & _CMU_AUXHFRCOCTRL_BAND_MASK)
+                                    >> _CMU_AUXHFRCOCTRL_BAND_SHIFT);
+}
+#endif /* _CMU_AUXHFRCOCTRL_BAND_MASK */
+
+
+#if defined( _CMU_AUXHFRCOCTRL_BAND_MASK )
+/***************************************************************************//**
+ * @brief
+ *   Set AUXHFRCO band and the tuning value based on the value in the
+ *   calibration table made during production.
+ *
+ * @param[in] band
+ *   AUXHFRCO band to activate.
+ ******************************************************************************/
+void CMU_AUXHFRCOBandSet(CMU_AUXHFRCOBand_TypeDef band)
+{
+  uint32_t tuning;
+
+  /* Read tuning value from calibration table */
+  switch (band)
+  {
+    case cmuAUXHFRCOBand_1MHz:
+      tuning = (DEVINFO->AUXHFRCOCAL0 & _DEVINFO_AUXHFRCOCAL0_BAND1_MASK)
+               >> _DEVINFO_AUXHFRCOCAL0_BAND1_SHIFT;
+      break;
+
+    case cmuAUXHFRCOBand_7MHz:
+      tuning = (DEVINFO->AUXHFRCOCAL0 & _DEVINFO_AUXHFRCOCAL0_BAND7_MASK)
+               >> _DEVINFO_AUXHFRCOCAL0_BAND7_SHIFT;
+      break;
+
+    case cmuAUXHFRCOBand_11MHz:
+      tuning = (DEVINFO->AUXHFRCOCAL0 & _DEVINFO_AUXHFRCOCAL0_BAND11_MASK)
+               >> _DEVINFO_AUXHFRCOCAL0_BAND11_SHIFT;
+      break;
+
+    case cmuAUXHFRCOBand_14MHz:
+      tuning = (DEVINFO->AUXHFRCOCAL0 & _DEVINFO_AUXHFRCOCAL0_BAND14_MASK)
+               >> _DEVINFO_AUXHFRCOCAL0_BAND14_SHIFT;
+      break;
+
+    case cmuAUXHFRCOBand_21MHz:
+      tuning = (DEVINFO->AUXHFRCOCAL1 & _DEVINFO_AUXHFRCOCAL1_BAND21_MASK)
+               >> _DEVINFO_AUXHFRCOCAL1_BAND21_SHIFT;
+      break;
+
+#if defined( _CMU_AUXHFRCOCTRL_BAND_28MHZ )
+    case cmuAUXHFRCOBand_28MHz:
+      tuning = (DEVINFO->AUXHFRCOCAL1 & _DEVINFO_AUXHFRCOCAL1_BAND28_MASK)
+               >> _DEVINFO_AUXHFRCOCAL1_BAND28_SHIFT;
+      break;
+#endif
+
+    default:
+      EFM_ASSERT(0);
+      return;
+  }
+
+  /* Set band/tuning */
+  CMU->AUXHFRCOCTRL = (CMU->AUXHFRCOCTRL &
+                       ~(_CMU_AUXHFRCOCTRL_BAND_MASK
+                         | _CMU_AUXHFRCOCTRL_TUNING_MASK))
+                      | (band << _CMU_AUXHFRCOCTRL_BAND_SHIFT)
+                      | (tuning << _CMU_AUXHFRCOCTRL_TUNING_SHIFT);
+
+}
+#endif /* _CMU_AUXHFRCOCTRL_BAND_MASK */
+
+
+#if defined( _CMU_AUXHFRCOCTRL_FREQRANGE_MASK )
+/**************************************************************************//**
+ * @brief
+ *   Get a pointer to the AUXHFRCO frequency calibration word in DEVINFO
+ *
+ * @param[in] freq
+ *   Frequency in Hz
+ *
+ * @return
+ *   AUXHFRCO calibration word for a given frequency
+ *****************************************************************************/
+static uint32_t CMU_AUXHFRCODevinfoGet(CMU_AUXHFRCOFreq_TypeDef freq)
+{
+  switch (freq)
+  {
+  /* 1, 2 and 4MHz share the same calibration word */
+    case cmuAUXHFRCOFreq_1M0Hz:
+    case cmuAUXHFRCOFreq_2M0Hz:
+    case cmuAUXHFRCOFreq_4M0Hz:
+      return DEVINFO->AUXHFRCOCAL0;
+
+    case cmuAUXHFRCOFreq_7M0Hz:
+      return DEVINFO->AUXHFRCOCAL3;
+
+    case cmuAUXHFRCOFreq_13M0Hz:
+      return DEVINFO->AUXHFRCOCAL6;
+
+    case cmuAUXHFRCOFreq_16M0Hz:
+      return DEVINFO->AUXHFRCOCAL7;
+
+    case cmuAUXHFRCOFreq_19M0Hz:
+      return DEVINFO->AUXHFRCOCAL8;
+
+    case cmuAUXHFRCOFreq_26M0Hz:
+      return DEVINFO->AUXHFRCOCAL10;
+
+    case cmuAUXHFRCOFreq_32M0Hz:
+      return DEVINFO->AUXHFRCOCAL11;
+
+    case cmuAUXHFRCOFreq_38M0Hz:
+      return DEVINFO->AUXHFRCOCAL12;
+
+    default: /* cmuAUXHFRCOFreq_UserDefined */
+      return 0;
+  }
+}
+#endif /* _CMU_AUXHFRCOCTRL_FREQRANGE_MASK */
+
+
+#if defined( _CMU_AUXHFRCOCTRL_FREQRANGE_MASK )
+/***************************************************************************//**
+ * @brief
+ *   Get AUXHFRCO frequency enumeration in use
+ *
+ * @return
+ *   AUXHFRCO frequency enumeration in use
+ ******************************************************************************/
+CMU_AUXHFRCOFreq_TypeDef CMU_AUXHFRCOFreqGet(void)
+{
+  return auxHfrcoFreq;
+}
+#endif /* _CMU_AUXHFRCOCTRL_FREQRANGE_MASK */
+
+
+#if defined( _CMU_AUXHFRCOCTRL_FREQRANGE_MASK )
+/***************************************************************************//**
+ * @brief
+ *   Set AUXHFRCO calibration for the selected target frequency
+ *
+ * @param[in] frequency
+ *   AUXHFRCO frequency to set
+ ******************************************************************************/
+void CMU_AUXHFRCOFreqSet(CMU_AUXHFRCOFreq_TypeDef freq)
+{
+  uint32_t freqCal;
+
+  /* Get DEVINFO index, set global auxHfrcoFreq */
+  freqCal = CMU_AUXHFRCODevinfoGet(freq);
+  EFM_ASSERT((freqCal != 0) && (freqCal != UINT_MAX));
+  auxHfrcoFreq = freq;
+
+  /* Wait for any previous sync to complete, and then set calibration data
+     for the selected frequency.  */
+  while(BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT));
+
+  /* Set divider in AUXHFRCOCTRL for 1, 2 and 4MHz */
+  switch(freq)
+  {
+    case cmuAUXHFRCOFreq_1M0Hz:
+      freqCal = (freqCal & ~_CMU_AUXHFRCOCTRL_CLKDIV_MASK)
+                | CMU_AUXHFRCOCTRL_CLKDIV_DIV4;
+      break;
+
+    case cmuAUXHFRCOFreq_2M0Hz:
+      freqCal = (freqCal & ~_CMU_AUXHFRCOCTRL_CLKDIV_MASK)
+                | CMU_AUXHFRCOCTRL_CLKDIV_DIV2;
+      break;
+
+    case cmuAUXHFRCOFreq_4M0Hz:
+      freqCal = (freqCal & ~_CMU_AUXHFRCOCTRL_CLKDIV_MASK)
+                | CMU_AUXHFRCOCTRL_CLKDIV_DIV1;
+      break;
+
+    default:
+      break;
+  }
+  CMU->AUXHFRCOCTRL = freqCal;
+}
+#endif /* _CMU_AUXHFRCOCTRL_FREQRANGE_MASK */
+
+
 /***************************************************************************//**
  * @brief
  *   Calibrate clock.
  *
  * @details
  *   Run a calibration for HFCLK against a selectable reference clock. Please
- *   refer to the EFM32 reference manual, CMU chapter, for further details.
+ *   refer to the reference manual, CMU chapter, for further details.
  *
  * @note
  *   This function will not return until calibration measurement is completed.
@@ -537,29 +805,29 @@
   /* Set reference clock source */
   switch (ref)
   {
-  case cmuOsc_LFXO:
-    CMU->CALCTRL = CMU_CALCTRL_UPSEL_LFXO;
-    break;
-
-  case cmuOsc_LFRCO:
-    CMU->CALCTRL = CMU_CALCTRL_UPSEL_LFRCO;
-    break;
-
-  case cmuOsc_HFXO:
-    CMU->CALCTRL = CMU_CALCTRL_UPSEL_HFXO;
-    break;
-
-  case cmuOsc_HFRCO:
-    CMU->CALCTRL = CMU_CALCTRL_UPSEL_HFRCO;
-    break;
-
-  case cmuOsc_AUXHFRCO:
-    CMU->CALCTRL = CMU_CALCTRL_UPSEL_AUXHFRCO;
-    break;
-
-  default:
-    EFM_ASSERT(0);
-    return 0;
+    case cmuOsc_LFXO:
+      CMU->CALCTRL = CMU_CALCTRL_UPSEL_LFXO;
+      break;
+
+    case cmuOsc_LFRCO:
+      CMU->CALCTRL = CMU_CALCTRL_UPSEL_LFRCO;
+      break;
+
+    case cmuOsc_HFXO:
+      CMU->CALCTRL = CMU_CALCTRL_UPSEL_HFXO;
+      break;
+
+    case cmuOsc_HFRCO:
+      CMU->CALCTRL = CMU_CALCTRL_UPSEL_HFRCO;
+      break;
+
+    case cmuOsc_AUXHFRCO:
+      CMU->CALCTRL = CMU_CALCTRL_UPSEL_AUXHFRCO;
+      break;
+
+    default:
+      EFM_ASSERT(0);
+      return 0;
   }
 
   /* Set top value */
@@ -568,9 +836,17 @@
   /* Start calibration */
   CMU->CMD = CMU_CMD_CALSTART;
 
+#if defined( CMU_STATUS_CALRDY )
   /* Wait until calibration completes */
-  while (CMU->STATUS & CMU_STATUS_CALBSY)
-    ;
+  while (!BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_CALRDY_SHIFT))
+  {
+  }
+#else
+  /* Wait until calibration completes */
+  while (BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_CALBSY_SHIFT))
+  {
+  }
+#endif
 
   return CMU->CALCNT;
 }
@@ -584,7 +860,7 @@
  * @details
  *   Configure a calibration for a selectable clock source against another
  *   selectable reference clock.
- *   Refer to the EFM32 reference manual, CMU chapter, for further details.
+ *   Refer to the reference manual, CMU chapter, for further details.
  *
  * @note
  *   After configuration, a call to CMU_CalibrateStart() is required, and
@@ -607,7 +883,8 @@
                          CMU_Osc_TypeDef upSel)
 {
   /* Keep untouched configuration settings */
-  uint32_t calCtrl = CMU->CALCTRL & ~(_CMU_CALCTRL_UPSEL_MASK | _CMU_CALCTRL_DOWNSEL_MASK);
+  uint32_t calCtrl = CMU->CALCTRL
+                     & ~(_CMU_CALCTRL_UPSEL_MASK | _CMU_CALCTRL_DOWNSEL_MASK);
 
   /* 20 bits of precision to calibration count register */
   EFM_ASSERT(downCycles <= (_CMU_CALCNT_CALCNT_MASK >> _CMU_CALCNT_CALCNT_SHIFT));
@@ -615,29 +892,29 @@
   /* Set down counting clock source - down counter */
   switch (downSel)
   {
-  case cmuOsc_LFXO:
-    calCtrl |= CMU_CALCTRL_DOWNSEL_LFXO;
-    break;
-
-  case cmuOsc_LFRCO:
-    calCtrl |= CMU_CALCTRL_DOWNSEL_LFRCO;
-    break;
-
-  case cmuOsc_HFXO:
-    calCtrl |= CMU_CALCTRL_DOWNSEL_HFXO;
-    break;
-
-  case cmuOsc_HFRCO:
-    calCtrl |= CMU_CALCTRL_DOWNSEL_HFRCO;
-    break;
-
-  case cmuOsc_AUXHFRCO:
-    calCtrl |= CMU_CALCTRL_DOWNSEL_AUXHFRCO;
-    break;
-
-  default:
-    EFM_ASSERT(0);
-    break;
+    case cmuOsc_LFXO:
+      calCtrl |= CMU_CALCTRL_DOWNSEL_LFXO;
+      break;
+
+    case cmuOsc_LFRCO:
+      calCtrl |= CMU_CALCTRL_DOWNSEL_LFRCO;
+      break;
+
+    case cmuOsc_HFXO:
+      calCtrl |= CMU_CALCTRL_DOWNSEL_HFXO;
+      break;
+
+    case cmuOsc_HFRCO:
+      calCtrl |= CMU_CALCTRL_DOWNSEL_HFRCO;
+      break;
+
+    case cmuOsc_AUXHFRCO:
+      calCtrl |= CMU_CALCTRL_DOWNSEL_AUXHFRCO;
+      break;
+
+    default:
+      EFM_ASSERT(0);
+      break;
   }
 
   /* Set top value to be counted down by the downSel clock */
@@ -646,29 +923,29 @@
   /* Set reference clock source - up counter */
   switch (upSel)
   {
-  case cmuOsc_LFXO:
-    calCtrl |= CMU_CALCTRL_UPSEL_LFXO;
-    break;
-
-  case cmuOsc_LFRCO:
-    calCtrl |= CMU_CALCTRL_UPSEL_LFRCO;
-    break;
-
-  case cmuOsc_HFXO:
-    calCtrl |= CMU_CALCTRL_UPSEL_HFXO;
-    break;
-
-  case cmuOsc_HFRCO:
-    calCtrl |= CMU_CALCTRL_UPSEL_HFRCO;
-    break;
-
-  case cmuOsc_AUXHFRCO:
-    calCtrl |= CMU_CALCTRL_UPSEL_AUXHFRCO;
-    break;
-
-  default:
-    EFM_ASSERT(0);
-    break;
+    case cmuOsc_LFXO:
+      calCtrl |= CMU_CALCTRL_UPSEL_LFXO;
+      break;
+
+    case cmuOsc_LFRCO:
+      calCtrl |= CMU_CALCTRL_UPSEL_LFRCO;
+      break;
+
+    case cmuOsc_HFXO:
+      calCtrl |= CMU_CALCTRL_UPSEL_HFXO;
+      break;
+
+    case cmuOsc_HFRCO:
+      calCtrl |= CMU_CALCTRL_UPSEL_HFRCO;
+      break;
+
+    case cmuOsc_AUXHFRCO:
+      calCtrl |= CMU_CALCTRL_UPSEL_AUXHFRCO;
+      break;
+
+    default:
+      EFM_ASSERT(0);
+      break;
   }
 
   CMU->CALCTRL = calCtrl;
@@ -678,6 +955,47 @@
 
 /***************************************************************************//**
  * @brief
+ *    Get calibration count register
+ * @note
+ *    If continuous calibrartion mode is active, calibration busy will almost
+ *    always be off, and we just need to read the value, where the normal case
+ *    would be that this function call has been triggered by the CALRDY
+ *    interrupt flag.
+ * @return
+ *    Calibration count, the number of UPSEL clocks (see CMU_CalibrateConfig)
+ *    in the period of DOWNSEL oscillator clock cycles configured by a previous
+ *    write operation to CMU->CALCNT
+ ******************************************************************************/
+uint32_t CMU_CalibrateCountGet(void)
+{
+  /* Wait until calibration completes, UNLESS continuous calibration mode is  */
+  /* active */
+#if defined( CMU_CALCTRL_CONT )
+  if (!BUS_RegBitRead(&CMU->CALCTRL, _CMU_CALCTRL_CONT_SHIFT))
+  {
+#if defined( CMU_STATUS_CALRDY )
+    /* Wait until calibration completes */
+    while (!BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_CALRDY_SHIFT))
+    {
+    }
+#else
+    /* Wait until calibration completes */
+    while (BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_CALBSY_SHIFT))
+    {
+    }
+#endif
+  }
+#else
+  while (BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_CALBSY_SHIFT))
+  {
+  }
+#endif
+  return CMU->CALCNT;
+}
+
+
+/***************************************************************************//**
+ * @brief
  *   Get clock divisor/prescaler.
  *
  * @param[in] clock
@@ -690,6 +1008,10 @@
  ******************************************************************************/
 CMU_ClkDiv_TypeDef CMU_ClockDivGet(CMU_Clock_TypeDef clock)
 {
+#if defined( _SILICON_LABS_32B_PLATFORM_2 )
+  return 1 + (uint32_t)CMU_ClockPrescGet(clock);
+
+#elif defined( _SILICON_LABS_32B_PLATFORM_1 )
   uint32_t           divReg;
   CMU_ClkDiv_TypeDef ret;
 
@@ -699,99 +1021,101 @@
   switch (divReg)
   {
 #if defined( _CMU_CTRL_HFCLKDIV_MASK )
-  case CMU_HFCLKDIV_REG:
-    ret = 1 + ((CMU->CTRL & _CMU_CTRL_HFCLKDIV_MASK) >>
-               _CMU_CTRL_HFCLKDIV_SHIFT);
-    break;
+    case CMU_HFCLKDIV_REG:
+      ret = 1 + ((CMU->CTRL & _CMU_CTRL_HFCLKDIV_MASK)
+                 >> _CMU_CTRL_HFCLKDIV_SHIFT);
+      break;
 #endif
 
-  case CMU_HFPERCLKDIV_REG:
-    ret = (CMU_ClkDiv_TypeDef)((CMU->HFPERCLKDIV &
-                                _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK) >>
-                               _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT);
-    ret = CMU_Log2ToDiv(ret);
-    break;
-
-  case CMU_HFCORECLKDIV_REG:
-    ret = (CMU_ClkDiv_TypeDef)((CMU->HFCORECLKDIV &
-                                _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK) >>
-                               _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT);
-    ret = CMU_Log2ToDiv(ret);
-    break;
-
-  case CMU_LFAPRESC0_REG:
-    switch (clock)
-    {
-    case cmuClock_RTC:
-      ret = (CMU_ClkDiv_TypeDef)(((CMU->LFAPRESC0 & _CMU_LFAPRESC0_RTC_MASK) >>
-                                  _CMU_LFAPRESC0_RTC_SHIFT));
+    case CMU_HFPERCLKDIV_REG:
+      ret = (CMU_ClkDiv_TypeDef)((CMU->HFPERCLKDIV
+                                  & _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK)
+                                 >> _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT);
       ret = CMU_Log2ToDiv(ret);
       break;
 
-#if defined(_CMU_LFAPRESC0_LETIMER0_MASK)
-    case cmuClock_LETIMER0:
-      ret = (CMU_ClkDiv_TypeDef)(((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER0_MASK) >>
-                                  _CMU_LFAPRESC0_LETIMER0_SHIFT));
+    case CMU_HFCORECLKDIV_REG:
+      ret = (CMU_ClkDiv_TypeDef)((CMU->HFCORECLKDIV
+                                  & _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK)
+                                 >> _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT);
       ret = CMU_Log2ToDiv(ret);
       break;
+
+    case CMU_LFAPRESC0_REG:
+      switch (clock)
+      {
+        case cmuClock_RTC:
+          ret = (CMU_ClkDiv_TypeDef)((CMU->LFAPRESC0 & _CMU_LFAPRESC0_RTC_MASK)
+                                     >> _CMU_LFAPRESC0_RTC_SHIFT);
+          ret = CMU_Log2ToDiv(ret);
+          break;
+
+#if defined(_CMU_LFAPRESC0_LETIMER0_MASK)
+        case cmuClock_LETIMER0:
+          ret = (CMU_ClkDiv_TypeDef)((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER0_MASK)
+                                     >> _CMU_LFAPRESC0_LETIMER0_SHIFT);
+          ret = CMU_Log2ToDiv(ret);
+          break;
 #endif
 
 #if defined(_CMU_LFAPRESC0_LCD_MASK)
-    case cmuClock_LCDpre:
-      ret = (CMU_ClkDiv_TypeDef)(((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LCD_MASK) >>
-                                  _CMU_LFAPRESC0_LCD_SHIFT) + CMU_DivToLog2(cmuClkDiv_16));
-      ret = CMU_Log2ToDiv(ret);
-      break;
+        case cmuClock_LCDpre:
+          ret = (CMU_ClkDiv_TypeDef)(((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LCD_MASK)
+                                      >> _CMU_LFAPRESC0_LCD_SHIFT)
+                                     + CMU_DivToLog2(cmuClkDiv_16));
+          ret = CMU_Log2ToDiv(ret);
+          break;
 #endif
 
 #if defined(_CMU_LFAPRESC0_LESENSE_MASK)
-    case cmuClock_LESENSE:
-      ret = (CMU_ClkDiv_TypeDef)(((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LESENSE_MASK) >>
-                                  _CMU_LFAPRESC0_LESENSE_SHIFT));
-      ret = CMU_Log2ToDiv(ret);
+        case cmuClock_LESENSE:
+          ret = (CMU_ClkDiv_TypeDef)((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LESENSE_MASK)
+                                     >> _CMU_LFAPRESC0_LESENSE_SHIFT);
+          ret = CMU_Log2ToDiv(ret);
+          break;
+#endif
+
+        default:
+          EFM_ASSERT(0);
+          ret = cmuClkDiv_1;
+          break;
+      }
       break;
+
+    case CMU_LFBPRESC0_REG:
+      switch (clock)
+      {
+#if defined(_CMU_LFBPRESC0_LEUART0_MASK)
+        case cmuClock_LEUART0:
+          ret = (CMU_ClkDiv_TypeDef)((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART0_MASK)
+                                     >> _CMU_LFBPRESC0_LEUART0_SHIFT);
+          ret = CMU_Log2ToDiv(ret);
+          break;
 #endif
 
+#if defined(_CMU_LFBPRESC0_LEUART1_MASK)
+        case cmuClock_LEUART1:
+          ret = (CMU_ClkDiv_TypeDef)((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART1_MASK)
+                                     >> _CMU_LFBPRESC0_LEUART1_SHIFT);
+          ret = CMU_Log2ToDiv(ret);
+          break;
+#endif
+
+        default:
+          EFM_ASSERT(0);
+          ret = cmuClkDiv_1;
+          break;
+      }
+      break;
+
     default:
       EFM_ASSERT(0);
       ret = cmuClkDiv_1;
       break;
-    }
-    break;
-
-  case CMU_LFBPRESC0_REG:
-    switch (clock)
-    {
-#if defined(_CMU_LFBPRESC0_LEUART0_MASK)
-    case cmuClock_LEUART0:
-      ret = (CMU_ClkDiv_TypeDef)(((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART0_MASK) >>
-                                  _CMU_LFBPRESC0_LEUART0_SHIFT));
-      ret = CMU_Log2ToDiv(ret);
-      break;
+  }
+
+  return ret;
 #endif
-
-#if defined(_CMU_LFBPRESC0_LEUART1_MASK)
-    case cmuClock_LEUART1:
-      ret = (CMU_ClkDiv_TypeDef)(((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART1_MASK) >>
-                                  _CMU_LFBPRESC0_LEUART1_SHIFT));
-      ret = CMU_Log2ToDiv(ret);
-      break;
-#endif
-
-    default:
-      EFM_ASSERT(0);
-      ret = cmuClkDiv_1;
-      break;
-    }
-    break;
-
-  default:
-    EFM_ASSERT(0);
-    ret = cmuClkDiv_1;
-    break;
-  }
-
-  return(ret);
 }
 
 
@@ -816,6 +1140,10 @@
  ******************************************************************************/
 void CMU_ClockDivSet(CMU_Clock_TypeDef clock, CMU_ClkDiv_TypeDef div)
 {
+#if defined( _SILICON_LABS_32B_PLATFORM_2 )
+  CMU_ClockPrescSet(clock, (CMU_ClkPresc_TypeDef)(div - 1));
+
+#elif defined( _SILICON_LABS_32B_PLATFORM_1 )
   uint32_t freq;
   uint32_t divReg;
 
@@ -825,186 +1153,189 @@
   switch (divReg)
   {
 #if defined( _CMU_CTRL_HFCLKDIV_MASK )
-  case CMU_HFCLKDIV_REG:
-    EFM_ASSERT((div>=cmuClkDiv_1) && (div<=cmuClkDiv_8));
-
-    /* Configure worst case wait states for flash access before setting divisor */
-    CMU_FlashWaitStateMax();
-
-    /* Set divider */
-    CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFCLKDIV_MASK) |
-      ((div-1) << _CMU_CTRL_HFCLKDIV_SHIFT);
-
-    /* Update CMSIS core clock variable */
-    /* (The function will update the global variable) */
-    freq = SystemCoreClockGet();
-
-    /* Optimize flash access wait state setting for current core clk */
-    CMU_FlashWaitStateControl(freq);
-    break;
+    case CMU_HFCLKDIV_REG:
+      EFM_ASSERT((div>=cmuClkDiv_1) && (div<=cmuClkDiv_8));
+
+      /* Configure worst case wait states for flash access before setting divisor */
+      flashWaitStateMax();
+
+      /* Set divider */
+      CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFCLKDIV_MASK)
+                  | ((div-1) << _CMU_CTRL_HFCLKDIV_SHIFT);
+
+      /* Update CMSIS core clock variable */
+      /* (The function will update the global variable) */
+      freq = SystemCoreClockGet();
+
+      /* Optimize flash access wait state setting for current core clk */
+      flashWaitStateControl(freq);
+      break;
 #endif
 
-  case CMU_HFPERCLKDIV_REG:
-    EFM_ASSERT((div >= cmuClkDiv_1) && (div <= cmuClkDiv_512));
-    /* Convert to correct scale */
-    div = CMU_DivToLog2(div);
-    CMU->HFPERCLKDIV = (CMU->HFPERCLKDIV & ~_CMU_HFPERCLKDIV_HFPERCLKDIV_MASK) |
-                       (div << _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT);
-    break;
-
-  case CMU_HFCORECLKDIV_REG:
-    EFM_ASSERT(div <= cmuClkDiv_512);
-
-    /* Configure worst case wait states for flash access before setting divisor */
-    CMU_FlashWaitStateMax();
+    case CMU_HFPERCLKDIV_REG:
+      EFM_ASSERT((div >= cmuClkDiv_1) && (div <= cmuClkDiv_512));
+      /* Convert to correct scale */
+      div = CMU_DivToLog2(div);
+      CMU->HFPERCLKDIV = (CMU->HFPERCLKDIV & ~_CMU_HFPERCLKDIV_HFPERCLKDIV_MASK)
+                         | (div << _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT);
+      break;
+
+    case CMU_HFCORECLKDIV_REG:
+      EFM_ASSERT(div <= cmuClkDiv_512);
+
+      /* Configure worst case wait states for flash access before setting divisor */
+      flashWaitStateMax();
 
 #if defined( CMU_CTRL_HFLE )
-    /* Clear HFLE and set DIV2 factor for peripheral clock
-       when running at frequencies lower than or equal to CMU_MAX_FREQ_HFLE. */
-    if ((CMU_ClockFreqGet(cmuClock_HF) / div) <= CMU_MAX_FREQ_HFLE)
-    {
-      /* Clear CMU HFLE */
-      BITBAND_Peripheral(&(CMU->CTRL), _CMU_CTRL_HFLE_SHIFT, 0);
-
-      /* Set DIV2 factor for peripheral clock */
-      BITBAND_Peripheral(&(CMU->HFCORECLKDIV),
-                         _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT, 0);
-    }
-    else
-    {
-      /* Set CMU HFLE */
-      BITBAND_Peripheral(&(CMU->CTRL), _CMU_CTRL_HFLE_SHIFT, 1);
-
-      /* Set DIV4 factor for peripheral clock */
-      BITBAND_Peripheral(&(CMU->HFCORECLKDIV),
-                         _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT, 1);
-    }
+      /* Clear HFLE and set DIV2 factor for peripheral clock
+         when running at frequencies lower than or equal to CMU_MAX_FREQ_HFLE. */
+      if ((CMU_ClockFreqGet(cmuClock_HF) / div) <= CMU_MAX_FREQ_HFLE())
+      {
+        /* Clear CMU HFLE */
+        BUS_RegBitWrite(&CMU->CTRL, _CMU_CTRL_HFLE_SHIFT, 0);
+
+        /* Set DIV2 factor for peripheral clock */
+        BUS_RegBitWrite(&CMU->HFCORECLKDIV,
+                        _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT, 0);
+      }
+      else
+      {
+        /* Set CMU HFLE */
+        BUS_RegBitWrite(&CMU->CTRL, _CMU_CTRL_HFLE_SHIFT, 1);
+
+        /* Set DIV4 factor for peripheral clock */
+        BUS_RegBitWrite(&CMU->HFCORECLKDIV,
+                        _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT, 1);
+      }
 #endif
 
-    /* Convert to correct scale */
-    div = CMU_DivToLog2(div);
-
-    CMU->HFCORECLKDIV = (CMU->HFCORECLKDIV & ~_CMU_HFCORECLKDIV_HFCORECLKDIV_MASK) |
-                        (div << _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT);
-
-    /* Update CMSIS core clock variable */
-    /* (The function will update the global variable) */
-    freq = SystemCoreClockGet();
-
-    /* Optimize flash access wait state setting for current core clk */
-    CMU_FlashWaitStateControl(freq);
-    break;
-
-  case CMU_LFAPRESC0_REG:
-    switch (clock)
-    {
-    case cmuClock_RTC:
-      EFM_ASSERT(div <= cmuClkDiv_32768);
-
-      /* LF register about to be modified require sync. busy check */
-      CMU_Sync(CMU_SYNCBUSY_LFAPRESC0);
-
       /* Convert to correct scale */
       div = CMU_DivToLog2(div);
 
-      CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_RTC_MASK) |
-                       (div << _CMU_LFAPRESC0_RTC_SHIFT);
+      CMU->HFCORECLKDIV = (CMU->HFCORECLKDIV
+                           & ~_CMU_HFCORECLKDIV_HFCORECLKDIV_MASK)
+                          | (div << _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT);
+
+      /* Update CMSIS core clock variable */
+      /* (The function will update the global variable) */
+      freq = SystemCoreClockGet();
+
+      /* Optimize flash access wait state setting for current core clk */
+      flashWaitStateControl(freq);
       break;
 
+    case CMU_LFAPRESC0_REG:
+      switch (clock)
+      {
+        case cmuClock_RTC:
+          EFM_ASSERT(div <= cmuClkDiv_32768);
+
+          /* LF register about to be modified require sync. busy check */
+          syncReg(CMU_SYNCBUSY_LFAPRESC0);
+
+          /* Convert to correct scale */
+          div = CMU_DivToLog2(div);
+
+          CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_RTC_MASK)
+                           | (div << _CMU_LFAPRESC0_RTC_SHIFT);
+          break;
+
 #if defined(_CMU_LFAPRESC0_LETIMER0_MASK)
-    case cmuClock_LETIMER0:
-      EFM_ASSERT(div <= cmuClkDiv_32768);
-
-      /* LF register about to be modified require sync. busy check */
-      CMU_Sync(CMU_SYNCBUSY_LFAPRESC0);
-
-      /* Convert to correct scale */
-      div = CMU_DivToLog2(div);
-
-      CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LETIMER0_MASK) |
-                       (div << _CMU_LFAPRESC0_LETIMER0_SHIFT);
-      break;
+        case cmuClock_LETIMER0:
+          EFM_ASSERT(div <= cmuClkDiv_32768);
+
+          /* LF register about to be modified require sync. busy check */
+          syncReg(CMU_SYNCBUSY_LFAPRESC0);
+
+          /* Convert to correct scale */
+          div = CMU_DivToLog2(div);
+
+          CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LETIMER0_MASK)
+                           | (div << _CMU_LFAPRESC0_LETIMER0_SHIFT);
+          break;
 #endif
 
 #if defined(LCD_PRESENT)
-    case cmuClock_LCDpre:
-      EFM_ASSERT((div >= cmuClkDiv_16) && (div <= cmuClkDiv_128));
-
-      /* LF register about to be modified require sync. busy check */
-      CMU_Sync(CMU_SYNCBUSY_LFAPRESC0);
-
-      /* Convert to correct scale */
-      div = CMU_DivToLog2(div);
-
-      CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LCD_MASK) |
-                       ((div - CMU_DivToLog2(cmuClkDiv_16)) << _CMU_LFAPRESC0_LCD_SHIFT);
-      break;
+        case cmuClock_LCDpre:
+          EFM_ASSERT((div >= cmuClkDiv_16) && (div <= cmuClkDiv_128));
+
+          /* LF register about to be modified require sync. busy check */
+          syncReg(CMU_SYNCBUSY_LFAPRESC0);
+
+          /* Convert to correct scale */
+          div = CMU_DivToLog2(div);
+
+          CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LCD_MASK)
+                           | ((div - CMU_DivToLog2(cmuClkDiv_16))
+                              << _CMU_LFAPRESC0_LCD_SHIFT);
+          break;
 #endif /* defined(LCD_PRESENT) */
 
 #if defined(LESENSE_PRESENT)
-    case cmuClock_LESENSE:
-      EFM_ASSERT(div <= cmuClkDiv_8);
-
-      /* LF register about to be modified require sync. busy check */
-      CMU_Sync(CMU_SYNCBUSY_LFAPRESC0);
-
-      /* Convert to correct scale */
-      div = CMU_DivToLog2(div);
-
-      CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LESENSE_MASK) |
-                       (div << _CMU_LFAPRESC0_LESENSE_SHIFT);
+        case cmuClock_LESENSE:
+          EFM_ASSERT(div <= cmuClkDiv_8);
+
+          /* LF register about to be modified require sync. busy check */
+          syncReg(CMU_SYNCBUSY_LFAPRESC0);
+
+          /* Convert to correct scale */
+          div = CMU_DivToLog2(div);
+
+          CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LESENSE_MASK)
+                           | (div << _CMU_LFAPRESC0_LESENSE_SHIFT);
+          break;
+#endif /* defined(LESENSE_PRESENT) */
+
+        default:
+          EFM_ASSERT(0);
+          break;
+      }
       break;
-#endif /* defined(LESENSE_PRESENT) */
+
+    case CMU_LFBPRESC0_REG:
+      switch (clock)
+      {
+#if defined(_CMU_LFBPRESC0_LEUART0_MASK)
+        case cmuClock_LEUART0:
+          EFM_ASSERT(div <= cmuClkDiv_8);
+
+          /* LF register about to be modified require sync. busy check */
+          syncReg(CMU_SYNCBUSY_LFBPRESC0);
+
+          /* Convert to correct scale */
+          div = CMU_DivToLog2(div);
+
+          CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_LEUART0_MASK)
+                           | (((uint32_t)div) << _CMU_LFBPRESC0_LEUART0_SHIFT);
+          break;
+#endif
+
+#if defined(_CMU_LFBPRESC0_LEUART1_MASK)
+        case cmuClock_LEUART1:
+          EFM_ASSERT(div <= cmuClkDiv_8);
+
+          /* LF register about to be modified require sync. busy check */
+          syncReg(CMU_SYNCBUSY_LFBPRESC0);
+
+          /* Convert to correct scale */
+          div = CMU_DivToLog2(div);
+
+          CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_LEUART1_MASK)
+                           | (((uint32_t)div) << _CMU_LFBPRESC0_LEUART1_SHIFT);
+          break;
+#endif
+
+        default:
+          EFM_ASSERT(0);
+          break;
+      }
+      break;
 
     default:
       EFM_ASSERT(0);
       break;
-    }
-    break;
-
-  case CMU_LFBPRESC0_REG:
-    switch (clock)
-    {
-#if defined(_CMU_LFBPRESC0_LEUART0_MASK)
-    case cmuClock_LEUART0:
-      EFM_ASSERT(div <= cmuClkDiv_8);
-
-      /* LF register about to be modified require sync. busy check */
-      CMU_Sync(CMU_SYNCBUSY_LFBPRESC0);
-
-      /* Convert to correct scale */
-      div = CMU_DivToLog2(div);
-
-      CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_LEUART0_MASK) |
-                       (((uint32_t)div) << _CMU_LFBPRESC0_LEUART0_SHIFT);
-      break;
+  }
 #endif
-
-#if defined(_CMU_LFBPRESC0_LEUART1_MASK)
-    case cmuClock_LEUART1:
-      EFM_ASSERT(div <= cmuClkDiv_8);
-
-      /* LF register about to be modified require sync. busy check */
-      CMU_Sync(CMU_SYNCBUSY_LFBPRESC0);
-
-      /* Convert to correct scale */
-      div = CMU_DivToLog2(div);
-
-      CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_LEUART1_MASK) |
-                       (((uint32_t)div) << _CMU_LFBPRESC0_LEUART1_SHIFT);
-      break;
-#endif
-
-    default:
-      EFM_ASSERT(0);
-      break;
-    }
-    break;
-
-  default:
-    EFM_ASSERT(0);
-    break;
-  }
 }
 
 
@@ -1044,56 +1375,84 @@
   /* Identify enable register */
   switch ((clock >> CMU_EN_REG_POS) & CMU_EN_REG_MASK)
   {
-  case CMU_HFPERCLKDIV_EN_REG:
-    reg = &(CMU->HFPERCLKDIV);
-    break;
-
-  case CMU_HFPERCLKEN0_EN_REG:
-    reg = &(CMU->HFPERCLKEN0);
-    break;
-
-  case CMU_HFCORECLKEN0_EN_REG:
-    reg = &(CMU->HFCORECLKEN0);
-
+#if defined( _SILICON_LABS_32B_PLATFORM_2 )
+    case CMU_CTRL_EN_REG:
+      reg = &CMU->CTRL;
+      break;
+#endif
+
+#if defined( _SILICON_LABS_32B_PLATFORM_1 )
+    case CMU_HFCORECLKEN0_EN_REG:
+      reg = &CMU->HFCORECLKEN0;
 #if defined( CMU_CTRL_HFLE )
-    /* Set HFLE and DIV4 factor for peripheral clock when
-       running at frequencies higher than or equal to CMU_MAX_FREQ_HFLE. */
-    if ( CMU_ClockFreqGet(cmuClock_CORE) > CMU_MAX_FREQ_HFLE )
-    {
-      /* Enable CMU HFLE */
-      BITBAND_Peripheral(&(CMU->CTRL), _CMU_CTRL_HFLE_SHIFT, 1);
-
-      /* Set DIV4 factor for peripheral clock */
-      BITBAND_Peripheral(&(CMU->HFCORECLKDIV),
-                         _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT, 1);
-    }
+      /* Set HFLE and DIV4 factor for peripheral clock when
+         running at frequencies higher than or equal to CMU_MAX_FREQ_HFLE. */
+      if ( CMU_ClockFreqGet(cmuClock_CORE) > CMU_MAX_FREQ_HFLE())
+      {
+        /* Enable CMU HFLE */
+        BUS_RegBitWrite(&CMU->CTRL, _CMU_CTRL_HFLE_SHIFT, 1);
+
+        /* Set DIV4 factor for peripheral clock */
+        BUS_RegBitWrite(&CMU->HFCORECLKDIV,
+                        _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT, 1);
+      }
+#endif
+      break;
+#endif
+
+#if defined( _CMU_HFBUSCLKEN0_MASK )
+    case CMU_HFBUSCLKEN0_EN_REG:
+      reg = &CMU->HFBUSCLKEN0;
+      break;
 #endif
-    break;
-
-  case CMU_LFACLKEN0_EN_REG:
-    reg  = &(CMU->LFACLKEN0);
-    sync = CMU_SYNCBUSY_LFACLKEN0;
-    break;
-
-  case CMU_LFBCLKEN0_EN_REG:
-    reg  = &(CMU->LFBCLKEN0);
-    sync = CMU_SYNCBUSY_LFBCLKEN0;
-    break;
-
-  case CMU_PCNT_EN_REG:
-    reg = &(CMU->PCNTCTRL);
-    break;
+
+#if defined( _CMU_HFRADIOCLKEN0_MASK )
+    case CMU_HFRADIOCLKEN0_EN_REG:
+      reg = &CMU->HFRADIOCLKEN0;
+      break;
+#endif
+
+#if defined( _CMU_HFPERCLKDIV_MASK )
+    case CMU_HFPERCLKDIV_EN_REG:
+      reg = &CMU->HFPERCLKDIV;
+      break;
+#endif
+
+    case CMU_HFPERCLKEN0_EN_REG:
+      reg = &CMU->HFPERCLKEN0;
+      break;
+
+    case CMU_LFACLKEN0_EN_REG:
+      reg  = &CMU->LFACLKEN0;
+      sync = CMU_SYNCBUSY_LFACLKEN0;
+      break;
+
+    case CMU_LFBCLKEN0_EN_REG:
+      reg  = &CMU->LFBCLKEN0;
+      sync = CMU_SYNCBUSY_LFBCLKEN0;
+      break;
 
 #if defined( _CMU_LFCCLKEN0_MASK )
-  case CMU_LFCCLKEN0_EN_REG:
-    reg = &(CMU->LFCCLKEN0);
-    sync = CMU_SYNCBUSY_LFCCLKEN0;
-    break;
+    case CMU_LFCCLKEN0_EN_REG:
+      reg = &CMU->LFCCLKEN0;
+      sync = CMU_SYNCBUSY_LFCCLKEN0;
+      break;
 #endif
 
-  default: /* Cannot enable/disable clock point */
-    EFM_ASSERT(0);
-    return;
+#if defined( _CMU_LFECLKEN0_MASK )
+    case CMU_LFECLKEN0_EN_REG:
+      reg  = &CMU->LFECLKEN0;
+      sync = CMU_SYNCBUSY_LFECLKEN0;
+      break;
+#endif
+
+    case CMU_PCNT_EN_REG:
+      reg = &CMU->PCNTCTRL;
+      break;
+
+    default: /* Cannot enable/disable clock point */
+      EFM_ASSERT(0);
+      return;
   }
 
   /* Get bit position used to enable/disable */
@@ -1102,11 +1461,11 @@
   /* LF synchronization required? */
   if (sync)
   {
-    CMU_Sync(sync);
+    syncReg(sync);
   }
 
   /* Set/clear bit as requested */
-  BITBAND_Peripheral(reg, bit, (unsigned int)enable);
+  BUS_RegBitWrite(reg, bit, enable);
 }
 
 
@@ -1127,150 +1486,545 @@
   switch(clock & (CMU_CLK_BRANCH_MASK << CMU_CLK_BRANCH_POS))
   {
     case (CMU_HF_CLK_BRANCH << CMU_CLK_BRANCH_POS):
-    {
       ret = SystemHFClockGet();
 #if defined( _CMU_CTRL_HFCLKDIV_MASK )
-      /* Giant Gecko has an additional divider, not used by USBC */
-      ret = ret / (1 + ((CMU->CTRL & _CMU_CTRL_HFCLKDIV_MASK) >>
-                   _CMU_CTRL_HFCLKDIV_SHIFT));
+      /* Family with an additional divider. */
+      ret = ret / (1U + ((CMU->CTRL & _CMU_CTRL_HFCLKDIV_MASK)
+                         >> _CMU_CTRL_HFCLKDIV_SHIFT));
+#endif
+#if defined( _CMU_HFPRESC_MASK )
+      ret = ret / (1U + ((CMU->HFPRESC & _CMU_HFPRESC_PRESC_MASK)
+                         >> _CMU_HFPRESC_PRESC_SHIFT));
+#endif
+      break;
+
+    case (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS):
+      ret = SystemHFClockGet();
+#if defined( _SILICON_LABS_32B_PLATFORM_1 )
+#if defined( _CMU_CTRL_HFCLKDIV_MASK )
+      /* Family with an additional divider. */
+      ret = ret / (1U + ((CMU->CTRL & _CMU_CTRL_HFCLKDIV_MASK)
+                         >> _CMU_CTRL_HFCLKDIV_SHIFT));
+#endif
+      ret >>= (CMU->HFPERCLKDIV & _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK)
+              >> _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT;
+#elif defined( _SILICON_LABS_32B_PLATFORM_2 )
+      ret /= 1U + ((CMU->HFPERPRESC & _CMU_HFPERPRESC_PRESC_MASK)
+                   >> _CMU_HFPERPRESC_PRESC_SHIFT);
 #endif
-    } break;
-
-#if defined(_CMU_HFPERCLKEN0_USART0_MASK) || \
-    defined(_CMU_HFPERCLKEN0_USART1_MASK) || \
-    defined(_CMU_HFPERCLKEN0_USART2_MASK) || \
-    defined(_CMU_HFPERCLKEN0_UART0_MASK) || \
-    defined(_CMU_HFPERCLKEN0_UART1_MASK) || \
-    defined(_CMU_HFPERCLKEN0_TIMER0_MASK) || \
-    defined(_CMU_HFPERCLKEN0_TIMER1_MASK) || \
-    defined(_CMU_HFPERCLKEN0_TIMER2_MASK) || \
-    defined(_CMU_HFPERCLKEN0_TIMER3_MASK) || \
-    defined(_CMU_HFPERCLKEN0_ACMP0_MASK) || \
-    defined(_CMU_HFPERCLKEN0_ACMP1_MASK) || \
-    defined(_CMU_HFPERCLKEN0_DAC0_MASK) || \
-    defined(_CMU_HFPERCLKEN0_IDAC0_MASK) || \
-    defined(_CMU_HFPERCLKEN0_ADC0_MASK) || \
-    defined(_CMU_HFPERCLKEN0_I2C0_MASK) || \
-    defined(_CMU_HFPERCLKEN0_I2C1_MASK) || \
-    defined(PRS_PRESENT) || \
-    defined(VCMP_PRESENT)|| \
-    defined(GPIO_PRESENT)
-    case (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS):
-    {
-      ret   = SystemHFClockGet();
-#if defined( _CMU_CTRL_HFCLKDIV_MASK )
-      /* Leopard/Giant Gecko has an additional divider */
-      ret = ret / (1 + ((CMU->CTRL & _CMU_CTRL_HFCLKDIV_MASK) >>
-                        _CMU_CTRL_HFCLKDIV_SHIFT));
+      break;
+
+#if defined( _SILICON_LABS_32B_PLATFORM_2 )
+#if defined( _CMU_HFRADIOPRESC_PRESC_MASK )
+    case (CMU_HFRADIO_CLK_BRANCH << CMU_CLK_BRANCH_POS):
+      ret = SystemHFClockGet();
+      ret /= 1U + ((CMU->HFRADIOPRESC & _CMU_HFRADIOPRESC_PRESC_MASK)
+                   >> _CMU_HFRADIOPRESC_PRESC_SHIFT);
+      break;
+#endif
+
+#if defined( CRYPTO_PRESENT )   \
+    || defined( LDMA_PRESENT )  \
+    || defined( GPCRC_PRESENT ) \
+    || defined( PRS_PRESENT )   \
+    || defined( GPIO_PRESENT )
+    case (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS):
+      ret = SystemHFClockGet();
+      break;
 #endif
-      ret >>= (CMU->HFPERCLKDIV & _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK) >>
-              _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT;
-    } break;
+
+    case (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS):
+      ret = SystemHFClockGet();
+      ret /= 1U + ((CMU->HFCOREPRESC & _CMU_HFCOREPRESC_PRESC_MASK)
+                   >> _CMU_HFCOREPRESC_PRESC_SHIFT);
+      break;
+
+    case (CMU_HFEXP_CLK_BRANCH << CMU_CLK_BRANCH_POS):
+      ret = SystemHFClockGet();
+      ret /= 1U + ((CMU->HFEXPPRESC & _CMU_HFEXPPRESC_PRESC_MASK)
+                   >> _CMU_HFEXPPRESC_PRESC_SHIFT);
+      break;
 #endif
 
-#if defined(AES_PRESENT) || \
-    defined(DMA_PRESENT) || \
-    defined(EBI_PRESENT) || \
-    defined(USB_PRESENT)
+#if defined( _SILICON_LABS_32B_PLATFORM_1 )
+#if defined(AES_PRESENT)    \
+    || defined(DMA_PRESENT) \
+    || defined(EBI_PRESENT) \
+    || defined(USB_PRESENT)
     case (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS):
     {
       ret = SystemCoreClockGet();
     } break;
 #endif
+#endif
 
     case (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS):
-    {
-      ret = CMU_LFClkGet(CMU_LFA);
-    } break;
-#if defined(_CMU_LFACLKEN0_RTC_MASK)
+      ret = lfClkGet(cmuClock_LFA);
+      break;
+
+#if defined( _CMU_LFACLKEN0_RTC_MASK )
     case (CMU_RTC_CLK_BRANCH << CMU_CLK_BRANCH_POS):
-    {
-      ret   = CMU_LFClkGet(CMU_LFA);
-      ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_RTC_MASK) >>
-              _CMU_LFAPRESC0_RTC_SHIFT;
-    } break;
+      ret = lfClkGet(cmuClock_LFA);
+      ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_RTC_MASK)
+              >> _CMU_LFAPRESC0_RTC_SHIFT;
+      break;
+#endif
+
+#if defined( _CMU_LFECLKEN0_RTCC_MASK )
+    case (CMU_RTCC_CLK_BRANCH << CMU_CLK_BRANCH_POS):
+      ret = lfClkGet(cmuClock_LFE);
+      break;
 #endif
-#if defined(_CMU_LFACLKEN0_LETIMER0_MASK)
-    case (CMU_LETIMER_CLK_BRANCH << CMU_CLK_BRANCH_POS):
-    {
-      ret   = CMU_LFClkGet(CMU_LFA);
-      ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER0_MASK) >>
-              _CMU_LFAPRESC0_LETIMER0_SHIFT;
-    } break;
+
+#if defined( _CMU_LFACLKEN0_LETIMER0_MASK )
+    case (CMU_LETIMER0_CLK_BRANCH << CMU_CLK_BRANCH_POS):
+      ret = lfClkGet(cmuClock_LFA);
+#if defined( _SILICON_LABS_32B_PLATFORM_1 )
+      ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER0_MASK)
+              >> _CMU_LFAPRESC0_LETIMER0_SHIFT;
+#elif defined( _SILICON_LABS_32B_PLATFORM_2 )
+      ret /= CMU_Log2ToDiv((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER0_MASK)
+                           >> _CMU_LFAPRESC0_LETIMER0_SHIFT);
 #endif
+      break;
+#endif
+
 #if defined(_CMU_LFACLKEN0_LCD_MASK)
     case (CMU_LCDPRE_CLK_BRANCH << CMU_CLK_BRANCH_POS):
-    {
-      ret   = CMU_LFClkGet(CMU_LFA);
-      ret >>= ((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LCD_MASK) >>
-              _CMU_LFAPRESC0_LCD_SHIFT) + CMU_DivToLog2(cmuClkDiv_16);
-    } break;
+      ret = lfClkGet(cmuClock_LFA);
+      ret >>= ((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LCD_MASK)
+               >> _CMU_LFAPRESC0_LCD_SHIFT)
+              + CMU_DivToLog2(cmuClkDiv_16);
+      break;
 
     case (CMU_LCD_CLK_BRANCH << CMU_CLK_BRANCH_POS):
-    {
-      ret   = CMU_LFClkGet(CMU_LFA);
-      ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LCD_MASK) >>
-              _CMU_LFAPRESC0_LCD_SHIFT;
-      ret /= (1 + ((CMU->LCDCTRL & _CMU_LCDCTRL_FDIV_MASK) >>
-                   _CMU_LCDCTRL_FDIV_SHIFT));
-    } break;
+      ret = lfClkGet(cmuClock_LFA);
+      ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LCD_MASK)
+              >> _CMU_LFAPRESC0_LCD_SHIFT;
+      ret /= 1U + ((CMU->LCDCTRL & _CMU_LCDCTRL_FDIV_MASK)
+                   >> _CMU_LCDCTRL_FDIV_SHIFT);
+      break;
 #endif
+
 #if defined(_CMU_LFACLKEN0_LESENSE_MASK)
     case (CMU_LESENSE_CLK_BRANCH << CMU_CLK_BRANCH_POS):
-    {
-      ret   = CMU_LFClkGet(CMU_LFA);
-      ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LESENSE_MASK) >>
-              _CMU_LFAPRESC0_LESENSE_SHIFT;
-    } break;
+      ret = lfClkGet(cmuClock_LFA);
+      ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LESENSE_MASK)
+              >> _CMU_LFAPRESC0_LESENSE_SHIFT;
+      break;
 #endif
+
     case (CMU_LFB_CLK_BRANCH << CMU_CLK_BRANCH_POS):
-    {
-      ret = CMU_LFClkGet(CMU_LFB);
-    } break;
-#if defined(_CMU_LFBCLKEN0_LEUART0_MASK)
+      ret = lfClkGet(cmuClock_LFB);
+      break;
+
+#if defined( _CMU_LFBCLKEN0_LEUART0_MASK )
     case (CMU_LEUART0_CLK_BRANCH << CMU_CLK_BRANCH_POS):
-    {
-      ret   = CMU_LFClkGet(CMU_LFB);
-      ret >>= (CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART0_MASK) >>
-              _CMU_LFBPRESC0_LEUART0_SHIFT;
-    } break;
+      ret = lfClkGet(cmuClock_LFB);
+#if defined( _SILICON_LABS_32B_PLATFORM_1 )
+      ret >>= (CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART0_MASK)
+              >> _CMU_LFBPRESC0_LEUART0_SHIFT;
+#elif defined( _SILICON_LABS_32B_PLATFORM_2 )
+      ret /= CMU_Log2ToDiv((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART0_MASK)
+                           >> _CMU_LFBPRESC0_LEUART0_SHIFT);
+#endif
+      break;
 #endif
-#if defined(_CMU_LFBCLKEN0_LEUART1_MASK)
+
+#if defined( _CMU_LFBCLKEN0_LEUART1_MASK )
     case (CMU_LEUART1_CLK_BRANCH << CMU_CLK_BRANCH_POS):
-    {
-      ret   = CMU_LFClkGet(CMU_LFB);
-      ret >>= (CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART1_MASK) >>
-        _CMU_LFBPRESC0_LEUART1_SHIFT;
-    } break;
+      ret = lfClkGet(cmuClock_LFB);
+#if defined( _SILICON_LABS_32B_PLATFORM_1 )
+      ret >>= (CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART1_MASK)
+              >> _CMU_LFBPRESC0_LEUART1_SHIFT;
+#elif defined( _SILICON_LABS_32B_PLATFORM_2 )
+      ret /= CMU_Log2ToDiv((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART1_MASK)
+                           >> _CMU_LFBPRESC0_LEUART1_SHIFT);
+#endif
+      break;
+#endif
+
+#if defined( _SILICON_LABS_32B_PLATFORM_2 )
+    case (CMU_LFE_CLK_BRANCH << CMU_CLK_BRANCH_POS):
+      ret = lfClkGet(cmuClock_LFE);
+      break;
 #endif
 
     case (CMU_DBG_CLK_BRANCH << CMU_CLK_BRANCH_POS):
-    {
-      ret  = CMU_DBGClkGet();
-    } break;
+      ret = dbgClkGet();
+      break;
 
     case (CMU_AUX_CLK_BRANCH << CMU_CLK_BRANCH_POS):
-    {
-      ret  = CMU_AUXClkGet();
-    } break;
+      ret = auxClkGet();
+      break;
 
 #if defined(USB_PRESENT)
     case (CMU_USBC_CLK_BRANCH << CMU_CLK_BRANCH_POS):
-    {
-      ret = CMU_USBCClkGet();
-    } break;
+      ret = usbCClkGet();
+      break;
 #endif
+
     default:
-    {
       EFM_ASSERT(0);
       ret = 0;
-    } break;
+      break;
   }
+
+  return ret;
+}
+
+
+#if defined( _SILICON_LABS_32B_PLATFORM_2 )
+/***************************************************************************//**
+ * @brief
+ *   Get clock prescaler.
+ *
+ * @param[in] clock
+ *   Clock point to get the prescaler for. Notice that not all clock points
+ *   have a prescaler. Please refer to CMU overview in reference manual.
+ *
+ * @return
+ *   The prescaler value of the current clock point. 0 is returned
+ *   if @p clock specifies a clock point without a prescaler.
+ ******************************************************************************/
+uint32_t CMU_ClockPrescGet(CMU_Clock_TypeDef clock)
+{
+  uint32_t  prescReg;
+  uint32_t  ret;
+
+  /* Get prescaler register id. */
+  prescReg = (clock >> CMU_PRESC_REG_POS) & CMU_PRESC_REG_MASK;
+
+  switch (prescReg)
+  {
+    case CMU_HFPRESC_REG:
+      ret = ((CMU->HFPRESC & _CMU_HFPRESC_PRESC_MASK)
+             >> _CMU_HFPRESC_PRESC_SHIFT);
+      break;
+
+    case CMU_HFEXPPRESC_REG:
+      ret = ((CMU->HFEXPPRESC & _CMU_HFEXPPRESC_PRESC_MASK)
+             >> _CMU_HFEXPPRESC_PRESC_SHIFT);
+      break;
+
+    case CMU_HFCLKLEPRESC_REG:
+      ret = ((CMU->HFPRESC & _CMU_HFPRESC_HFCLKLEPRESC_MASK)
+             >> _CMU_HFPRESC_HFCLKLEPRESC_SHIFT);
+      break;
+
+    case CMU_HFPERPRESC_REG:
+      ret = ((CMU->HFPERPRESC & _CMU_HFPERPRESC_PRESC_MASK)
+             >> _CMU_HFPERPRESC_PRESC_SHIFT);
+      break;
+
+#if defined( _CMU_HFRADIOPRESC_PRESC_MASK )
+    case CMU_HFRADIOPRESC_REG:
+      ret = ((CMU->HFRADIOPRESC & _CMU_HFRADIOPRESC_PRESC_MASK)
+             >> _CMU_HFRADIOPRESC_PRESC_SHIFT);
+      break;
+#endif
+
+    case CMU_HFCOREPRESC_REG:
+      ret = ((CMU->HFCOREPRESC & _CMU_HFCOREPRESC_PRESC_MASK)
+             >> _CMU_HFCOREPRESC_PRESC_SHIFT);
+      break;
+
+    case CMU_LFAPRESC0_REG:
+      switch (clock)
+      {
+#if defined( _CMU_LFAPRESC0_LETIMER0_MASK )
+        case cmuClock_LETIMER0:
+          ret = (((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER0_MASK)
+                 >> _CMU_LFAPRESC0_LETIMER0_SHIFT));
+          /* Convert the exponent to prescaler value. */
+          ret = CMU_Log2ToDiv(ret) - 1U;
+          break;
+#endif
+
+        default:
+          EFM_ASSERT(0);
+          ret = 0U;
+          break;
+      }
+      break;
+
+    case CMU_LFBPRESC0_REG:
+      switch (clock)
+      {
+#if defined( _CMU_LFBPRESC0_LEUART0_MASK )
+        case cmuClock_LEUART0:
+          ret = (((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART0_MASK)
+                 >> _CMU_LFBPRESC0_LEUART0_SHIFT));
+          /* Convert the exponent to prescaler value. */
+          ret = CMU_Log2ToDiv(ret) - 1U;
+          break;
+#endif
+
+#if defined( _CMU_LFBPRESC0_LEUART1_MASK )
+        case cmuClock_LEUART1:
+          ret = (((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART1_MASK)
+                 >> _CMU_LFBPRESC0_LEUART1_SHIFT));
+          /* Convert the exponent to prescaler value. */
+          ret = CMU_Log2ToDiv(ret) - 1U;
+          break;
+#endif
+
+        default:
+          EFM_ASSERT(0);
+          ret = 0U;
+          break;
+      }
+      break;
+
+    case CMU_LFEPRESC0_REG:
+      switch (clock)
+      {
+#if defined( RTCC_PRESENT )
+        case cmuClock_RTCC:
+          /* No need to compute with LFEPRESC0_RTCC - DIV1 is the only  */
+          /* allowed value. Convert the exponent to prescaler value.    */
+          ret = _CMU_LFEPRESC0_RTCC_DIV1;
+          break;
+
+        default:
+          EFM_ASSERT(0);
+          ret = 0U;
+          break;
+#endif
+      }
+      break;
+
+    default:
+      EFM_ASSERT(0);
+      ret = 0U;
+      break;
+  }
+
   return ret;
 }
-
-
-/**************************************************************************//**
+#endif
+
+
+#if defined( _SILICON_LABS_32B_PLATFORM_2 )
+/***************************************************************************//**
+ * @brief
+ *   Set clock prescaler.
+ *
+ * @note
+ *   If setting a LF clock prescaler, synchronization into the low frequency
+ *   domain is required. If the same register is modified before a previous
+ *   update has completed, this function will stall until the previous
+ *   synchronization has completed. Please refer to CMU_FreezeEnable() for
+ *   a suggestion on how to reduce stalling time in some use cases.
+ *
+ * @param[in] clock
+ *   Clock point to set prescaler for. Notice that not all clock points
+ *   have a prescaler, please refer to CMU overview in the reference manual.
+ *
+ * @param[in] presc
+ *   The clock prescaler to use.
+ ******************************************************************************/
+void CMU_ClockPrescSet(CMU_Clock_TypeDef clock, CMU_ClkPresc_TypeDef presc)
+{
+  uint32_t freq;
+  uint32_t prescReg;
+
+  /* Get divisor reg id */
+  prescReg = (clock >> CMU_PRESC_REG_POS) & CMU_PRESC_REG_MASK;
+
+  switch (prescReg)
+  {
+    case CMU_HFPRESC_REG:
+      EFM_ASSERT(presc < 32U);
+
+      CMU->HFPRESC = (CMU->HFPRESC & ~_CMU_HFPRESC_PRESC_MASK)
+                     | (presc << _CMU_HFPRESC_PRESC_SHIFT);
+      break;
+
+    case CMU_HFEXPPRESC_REG:
+      EFM_ASSERT(presc < 32U);
+
+      CMU->HFEXPPRESC = (CMU->HFEXPPRESC & ~_CMU_HFEXPPRESC_PRESC_MASK)
+                        | (presc << _CMU_HFEXPPRESC_PRESC_SHIFT);
+      break;
+
+    case CMU_HFCLKLEPRESC_REG:
+      EFM_ASSERT(presc < 2U);
+
+      /* Specifies the clock divider for HFCLKLE. When running at frequencies
+       * higher than 32 MHz, this must be set to DIV4. */
+      CMU->HFPRESC = (CMU->HFPRESC & ~_CMU_HFPRESC_HFCLKLEPRESC_MASK)
+                     | (presc << _CMU_HFPRESC_HFCLKLEPRESC_SHIFT);
+      break;
+
+    case CMU_HFPERPRESC_REG:
+      EFM_ASSERT(presc < 512U);
+
+      CMU->HFPERPRESC = (CMU->HFPERPRESC & ~_CMU_HFPERPRESC_PRESC_MASK)
+                        | (presc << _CMU_HFPERPRESC_PRESC_SHIFT);
+      break;
+
+#if defined( _CMU_HFRADIOPRESC_PRESC_MASK )
+    case CMU_HFRADIOPRESC_REG:
+      EFM_ASSERT(presc < 512U);
+
+      CMU->HFRADIOPRESC = (CMU->HFRADIOPRESC & ~_CMU_HFRADIOPRESC_PRESC_MASK)
+                          | (presc << _CMU_HFRADIOPRESC_PRESC_SHIFT);
+      break;
+#endif
+
+    case CMU_HFCOREPRESC_REG:
+      EFM_ASSERT(presc < 512U);
+
+      /* Configure worst case wait states for flash access before setting
+       * the prescaler. */
+      flashWaitStateControl(CMU_MAX_FREQ_0WS + 1);
+
+      CMU->HFCOREPRESC = (CMU->HFCOREPRESC & ~_CMU_HFCOREPRESC_PRESC_MASK)
+                         | (presc << _CMU_HFCOREPRESC_PRESC_SHIFT);
+
+      /* Update CMSIS core clock variable */
+      /* (The function will update the global variable) */
+      freq = SystemCoreClockGet();
+
+      /* Optimize flash access wait state setting for current core clk */
+      flashWaitStateControl(freq);
+      break;
+
+    case CMU_LFAPRESC0_REG:
+      switch (clock)
+      {
+#if defined( RTC_PRESENT )
+        case cmuClock_RTC:
+          EFM_ASSERT(presc <= 32768U);
+
+          /* Convert prescaler value to DIV exponent scale. */
+          presc = CMU_PrescToLog2(presc);
+
+          /* LF register about to be modified require sync. Busy check. */
+          syncReg(CMU_SYNCBUSY_LFAPRESC0);
+
+          CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_RTC_MASK)
+                           | (presc << _CMU_LFAPRESC0_RTC_SHIFT);
+          break;
+#endif
+
+#if defined( RTCC_PRESENT )
+        case cmuClock_RTCC:
+#if defined( _CMU_LFEPRESC0_RTCC_MASK )
+          /* DIV1 is the only accepted value. */
+          EFM_ASSERT(presc <= 0U);
+
+          /* LF register about to be modified require sync. Busy check.. */
+          syncReg(CMU_SYNCBUSY_LFEPRESC0);
+
+          CMU->LFEPRESC0 = (CMU->LFEPRESC0 & ~_CMU_LFEPRESC0_RTCC_MASK)
+                           | (presc << _CMU_LFEPRESC0_RTCC_SHIFT);
+#else
+          EFM_ASSERT(presc <= 32768U);
+
+          /* Convert prescaler value to DIV exponent scale. */
+          presc = CMU_PrescToLog2(presc);
+
+          /* LF register about to be modified require sync. Busy check. */
+          syncReg(CMU_SYNCBUSY_LFAPRESC0);
+
+          CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_RTCC_MASK)
+                           | (presc << _CMU_LFAPRESC0_RTCC_SHIFT);
+#endif
+          break;
+#endif
+
+#if defined( _CMU_LFAPRESC0_LETIMER0_MASK )
+        case cmuClock_LETIMER0:
+          EFM_ASSERT(presc <= 32768U);
+
+          /* Convert prescaler value to DIV exponent scale. */
+          presc = CMU_PrescToLog2(presc);
+
+          /* LF register about to be modified require sync. Busy check. */
+          syncReg(CMU_SYNCBUSY_LFAPRESC0);
+
+          CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LETIMER0_MASK)
+                           | (presc << _CMU_LFAPRESC0_LETIMER0_SHIFT);
+          break;
+#endif
+
+        default:
+          EFM_ASSERT(0);
+          break;
+      }
+      break;
+
+    case CMU_LFBPRESC0_REG:
+      switch (clock)
+      {
+#if defined( _CMU_LFBPRESC0_LEUART0_MASK )
+        case cmuClock_LEUART0:
+          EFM_ASSERT(presc <= 8U);
+
+          /* Convert prescaler value to DIV exponent scale. */
+          presc = CMU_PrescToLog2(presc);
+
+          /* LF register about to be modified require sync. Busy check. */
+          syncReg(CMU_SYNCBUSY_LFBPRESC0);
+
+          CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_LEUART0_MASK)
+                           | (presc << _CMU_LFBPRESC0_LEUART0_SHIFT);
+          break;
+#endif
+
+#if defined( _CMU_LFBPRESC0_LEUART1_MASK )
+        case cmuClock_LEUART1:
+          EFM_ASSERT(presc <= 8U);
+
+          /* Convert prescaler value to DIV exponent scale. */
+          presc = CMU_PrescToLog2(presc);
+
+          /* LF register about to be modified require sync. Busy check. */
+          syncReg(CMU_SYNCBUSY_LFBPRESC0);
+
+          CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_LEUART1_MASK)
+                           | (presc << _CMU_LFBPRESC0_LEUART1_SHIFT);
+          break;
+#endif
+
+        default:
+          EFM_ASSERT(0);
+          break;
+      }
+      break;
+
+    case CMU_LFEPRESC0_REG:
+      switch (clock)
+      {
+#if defined( _CMU_LFEPRESC0_RTCC_MASK )
+        case cmuClock_RTCC:
+          EFM_ASSERT(presc <= 0U);
+
+          /* LF register about to be modified require sync. Busy check. */
+          syncReg(CMU_SYNCBUSY_LFEPRESC0);
+
+          CMU->LFEPRESC0 = (CMU->LFEPRESC0 & ~_CMU_LFEPRESC0_RTCC_MASK)
+                           | (presc << _CMU_LFEPRESC0_RTCC_SHIFT);
+          break;
+#endif
+
+        default:
+          EFM_ASSERT(0);
+          break;
+      }
+      break;
+
+    default:
+      EFM_ASSERT(0);
+      break;
+  }
+}
+#endif
+
+
+/***************************************************************************//**
  * @brief
  *   Get currently selected reference clock used for a clock branch.
  *
@@ -1278,7 +2032,11 @@
  *   Clock branch to fetch selected ref. clock for. One of:
  *   @li #cmuClock_HF
  *   @li #cmuClock_LFA
- *   @li #cmuClock_LFB
+ *   @li #cmuClock_LFB @if _CMU_LFCLKSEL_LFAE_ULFRCO
+ *   @li #cmuClock_LFC
+ *   @endif            @if _SILICON_LABS_32B_PLATFORM_2
+ *   @li #cmuClock_LFE
+ *   @endif
  *   @li #cmuClock_DBG @if DOXYDOC_USB_PRESENT
  *   @li #cmuClock_USBC
  *   @endif
@@ -1286,216 +2044,326 @@
  * @return
  *   Reference clock used for clocking selected branch, #cmuSelect_Error if
  *   invalid @p clock provided.
- *****************************************************************************/
+ ******************************************************************************/
 CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock)
 {
   CMU_Select_TypeDef ret = cmuSelect_Disabled;
-  uint32_t           selReg;
-  uint32_t           statusClkSelMask;
-
-  statusClkSelMask =
-    (CMU_STATUS_HFRCOSEL |
-     CMU_STATUS_HFXOSEL |
-     CMU_STATUS_LFRCOSEL |
-#if defined( CMU_STATUS_USHFRCODIV2SEL )
-     CMU_STATUS_USHFRCODIV2SEL |
-#endif
-     CMU_STATUS_LFXOSEL);
+  uint32_t selReg;
 
   selReg = (clock >> CMU_SEL_REG_POS) & CMU_SEL_REG_MASK;
 
   switch (selReg)
   {
-  case CMU_HFCLKSEL_REG:
-    switch (CMU->STATUS & statusClkSelMask)
-    {
-    case CMU_STATUS_LFXOSEL:
-      ret = cmuSelect_LFXO;
-      break;
-
-    case CMU_STATUS_LFRCOSEL:
-      ret = cmuSelect_LFRCO;
-      break;
-
-    case CMU_STATUS_HFXOSEL:
-      ret = cmuSelect_HFXO;
-      break;
+    case CMU_HFCLKSEL_REG:
+#if defined( _CMU_HFCLKSEL_HF_MASK )
+      switch (CMU->HFCLKSEL & _CMU_HFCLKSEL_HF_MASK)
+      {
+        case CMU_HFCLKSEL_HF_LFXO:
+          ret = cmuSelect_LFXO;
+          break;
+
+        case CMU_HFCLKSEL_HF_LFRCO:
+          ret = cmuSelect_LFRCO;
+          break;
+
+        case CMU_HFCLKSEL_HF_HFXO:
+          ret = cmuSelect_HFXO;
+          break;
+
+        default:
+          ret = cmuSelect_HFRCO;
+          break;
+      }
+#else
+      switch (CMU->STATUS
+              & (CMU_STATUS_HFRCOSEL
+                 | CMU_STATUS_HFXOSEL
+                 | CMU_STATUS_LFRCOSEL
+#if defined( CMU_STATUS_USHFRCODIV2SEL )
+                 | CMU_STATUS_USHFRCODIV2SEL
+#endif
+                 | CMU_STATUS_LFXOSEL))
+      {
+        case CMU_STATUS_LFXOSEL:
+          ret = cmuSelect_LFXO;
+          break;
+
+        case CMU_STATUS_LFRCOSEL:
+          ret = cmuSelect_LFRCO;
+          break;
+
+        case CMU_STATUS_HFXOSEL:
+          ret = cmuSelect_HFXO;
+          break;
 
 #if defined( CMU_STATUS_USHFRCODIV2SEL )
-    case CMU_STATUS_USHFRCODIV2SEL:
-      ret = cmuSelect_USHFRCODIV2;
+        case CMU_STATUS_USHFRCODIV2SEL:
+          ret = cmuSelect_USHFRCODIV2;
+          break;
+#endif
+
+        default:
+          ret = cmuSelect_HFRCO;
+          break;
+      }
+#endif
+      break;
+
+    case CMU_LFACLKSEL_REG:
+#if defined( _CMU_LFCLKSEL_MASK )
+      switch (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFA_MASK)
+      {
+        case CMU_LFCLKSEL_LFA_LFRCO:
+          ret = cmuSelect_LFRCO;
+          break;
+
+        case CMU_LFCLKSEL_LFA_LFXO:
+          ret = cmuSelect_LFXO;
+          break;
+
+#if defined( CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 )
+        case CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2:
+          ret = cmuSelect_CORELEDIV2;
+          break;
+#endif
+
+        default:
+#if defined( CMU_LFCLKSEL_LFAE )
+          if (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFAE_MASK)
+          {
+            ret = cmuSelect_ULFRCO;
+            break;
+          }
+#else
+          ret = cmuSelect_Disabled;
+#endif
+          break;
+      }
+#endif /* _CMU_LFCLKSEL_MASK */
+
+#if defined( _CMU_LFACLKSEL_MASK )
+      switch (CMU->LFACLKSEL & _CMU_LFACLKSEL_LFA_MASK)
+      {
+        case CMU_LFACLKSEL_LFA_LFRCO:
+          ret = cmuSelect_LFRCO;
+          break;
+
+        case CMU_LFACLKSEL_LFA_LFXO:
+          ret = cmuSelect_LFXO;
+          break;
+
+        case CMU_LFACLKSEL_LFA_ULFRCO:
+          ret = cmuSelect_ULFRCO;
+          break;
+
+#if defined( _CMU_LFACLKSEL_LFA_HFCLKLE )
+        case CMU_LFACLKSEL_LFA_HFCLKLE:
+          ret = cmuSelect_HFCLKLE;
+          break;
+#endif
+
+        default:
+          ret = cmuSelect_Disabled;
+          break;
+      }
+#endif
+      break;
+
+    case CMU_LFBCLKSEL_REG:
+#if defined( _CMU_LFCLKSEL_MASK )
+      switch (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFB_MASK)
+      {
+        case CMU_LFCLKSEL_LFB_LFRCO:
+          ret = cmuSelect_LFRCO;
+          break;
+
+        case CMU_LFCLKSEL_LFB_LFXO:
+          ret = cmuSelect_LFXO;
+          break;
+
+#if defined( CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 )
+        case CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2:
+          ret = cmuSelect_CORELEDIV2;
+          break;
+#endif
+
+#if defined( CMU_LFCLKSEL_LFB_HFCLKLE )
+        case CMU_LFCLKSEL_LFB_HFCLKLE:
+          ret = cmuSelect_HFCLKLE;
+          break;
+#endif
+
+        default:
+#if defined( CMU_LFCLKSEL_LFBE )
+          if (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFBE_MASK)
+          {
+            ret = cmuSelect_ULFRCO;
+            break;
+          }
+#else
+          ret = cmuSelect_Disabled;
+#endif
+          break;
+      }
+#endif /* _CMU_LFCLKSEL_MASK */
+
+#if defined( _CMU_LFBCLKSEL_MASK )
+      switch (CMU->LFBCLKSEL & _CMU_LFBCLKSEL_LFB_MASK)
+      {
+        case CMU_LFBCLKSEL_LFB_LFRCO:
+          ret = cmuSelect_LFRCO;
+          break;
+
+        case CMU_LFBCLKSEL_LFB_LFXO:
+          ret = cmuSelect_LFXO;
+          break;
+
+        case CMU_LFBCLKSEL_LFB_ULFRCO:
+          ret = cmuSelect_ULFRCO;
+          break;
+
+        case CMU_LFBCLKSEL_LFB_HFCLKLE:
+          ret = cmuSelect_HFCLKLE;
+          break;
+
+        default:
+          ret = cmuSelect_Disabled;
+          break;
+      }
+#endif
+      break;
+
+#if defined( _CMU_LFCLKSEL_LFC_MASK )
+    case CMU_LFCCLKSEL_REG:
+      switch (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFC_MASK)
+      {
+        case CMU_LFCLKSEL_LFC_LFRCO:
+          ret = cmuSelect_LFRCO;
+          break;
+
+        case CMU_LFCLKSEL_LFC_LFXO:
+          ret = cmuSelect_LFXO;
+          break;
+
+        default:
+          ret = cmuSelect_Disabled;
+          break;
+      }
+      break;
+#endif
+
+#if defined( _CMU_LFECLKSEL_LFE_MASK )
+    case CMU_LFECLKSEL_REG:
+      switch (CMU->LFECLKSEL & _CMU_LFECLKSEL_LFE_MASK)
+      {
+        case CMU_LFECLKSEL_LFE_LFRCO:
+          ret = cmuSelect_LFRCO;
+          break;
+
+        case CMU_LFECLKSEL_LFE_LFXO:
+          ret = cmuSelect_LFXO;
+          break;
+
+        case CMU_LFECLKSEL_LFE_ULFRCO:
+          ret = cmuSelect_ULFRCO;
+          break;
+
+#if defined ( _CMU_LFECLKSEL_LFE_HFCLKLE )
+        case CMU_LFECLKSEL_LFE_HFCLKLE:
+          ret = cmuSelect_HFCLKLE;
+          break;
+#endif
+
+        default:
+          ret = cmuSelect_Disabled;
+          break;
+      }
+      break;
+#endif /* CMU_LFECLKSEL_REG */
+
+    case CMU_DBGCLKSEL_REG:
+#if defined( _CMU_DBGCLKSEL_DBG_MASK )
+      switch (CMU->DBGCLKSEL & _CMU_DBGCLKSEL_DBG_MASK)
+      {
+        case CMU_DBGCLKSEL_DBG_HFCLK:
+          ret = cmuSelect_HFCLK;
+          break;
+
+        case CMU_DBGCLKSEL_DBG_AUXHFRCO:
+          ret = cmuSelect_AUXHFRCO;
+          break;
+      }
+#else
+      ret = cmuSelect_AUXHFRCO;
+#endif /* CMU_DBGCLKSEL_DBG */
+
+#if defined( _CMU_CTRL_DBGCLK_MASK )
+      switch(CMU->CTRL & _CMU_CTRL_DBGCLK_MASK)
+      {
+        case CMU_CTRL_DBGCLK_AUXHFRCO:
+          ret = cmuSelect_AUXHFRCO;
+          break;
+
+        case CMU_CTRL_DBGCLK_HFCLK:
+          ret = cmuSelect_HFCLK;
+          break;
+      }
+#else
+      ret = cmuSelect_AUXHFRCO;
+#endif
+      break;
+
+
+#if defined( USB_PRESENT )
+    case CMU_USBCCLKSEL_REG:
+      switch (CMU->STATUS
+              & (CMU_STATUS_USBCLFXOSEL
+#if defined(_CMU_STATUS_USBCHFCLKSEL_MASK)
+                 | CMU_STATUS_USBCHFCLKSEL
+#endif
+#if defined(_CMU_STATUS_USBCUSHFRCOSEL_MASK)
+                 | CMU_STATUS_USBCUSHFRCOSEL
+#endif
+                 | CMU_STATUS_USBCLFRCOSEL))
+      {
+#if defined(_CMU_STATUS_USBCHFCLKSEL_MASK)
+        case CMU_STATUS_USBCHFCLKSEL:
+          ret = cmuSelect_HFCLK;
+          break;
+#endif
+
+#if defined(_CMU_STATUS_USBCUSHFRCOSEL_MASK)
+        case CMU_STATUS_USBCUSHFRCOSEL:
+          ret = cmuSelect_USHFRCO;
+          break;
+#endif
+
+        case CMU_STATUS_USBCLFXOSEL:
+          ret = cmuSelect_LFXO;
+          break;
+
+        case CMU_STATUS_USBCLFRCOSEL:
+          ret = cmuSelect_LFRCO;
+          break;
+
+        default:
+          ret = cmuSelect_Disabled;
+          break;
+      }
       break;
 #endif
 
     default:
-      ret = cmuSelect_HFRCO;
-      break;
-    }
-    break;
-
-  case CMU_LFACLKSEL_REG:
-    switch (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFA_MASK)
-    {
-    case CMU_LFCLKSEL_LFA_LFRCO:
-      ret = cmuSelect_LFRCO;
-      break;
-
-    case CMU_LFCLKSEL_LFA_LFXO:
-      ret = cmuSelect_LFXO;
-      break;
-
-    case CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2:
-      ret = cmuSelect_CORELEDIV2;
-      break;
-
-    default:
-#if defined( CMU_LFCLKSEL_LFAE )
-      if (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFAE_MASK)
-      {
-        ret = cmuSelect_ULFRCO;
-        break;
-      }
-#else
-      ret = cmuSelect_Disabled;
-#endif
-      break;
-    }
-    break;
-
-  case CMU_LFBCLKSEL_REG:
-    switch (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFB_MASK)
-    {
-    case CMU_LFCLKSEL_LFB_LFRCO:
-      ret = cmuSelect_LFRCO;
-      break;
-
-    case CMU_LFCLKSEL_LFB_LFXO:
-      ret = cmuSelect_LFXO;
-      break;
-
-    case CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2:
-      ret = cmuSelect_CORELEDIV2;
-      break;
-
-    default:
-#if defined( CMU_LFCLKSEL_LFBE )
-      if (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFBE_MASK)
-      {
-        ret = cmuSelect_ULFRCO;
-        break;
-      }
-#else
-      ret = cmuSelect_Disabled;
-#endif
-      break;
-    }
-    break;
-
-#if defined( _CMU_LFCLKSEL_LFC_MASK )
-  case CMU_LFCCLKSEL_REG:
-    switch (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFC_MASK)
-    {
-    case CMU_LFCLKSEL_LFC_LFRCO:
-      ret = cmuSelect_LFRCO;
-      break;
-
-    case CMU_LFCLKSEL_LFC_LFXO:
-      ret = cmuSelect_LFXO;
-      break;
-
-    default:
-      ret = cmuSelect_Disabled;
+      EFM_ASSERT(0);
+      ret = cmuSelect_Error;
       break;
-    }
-    break;
-#endif
-
-  case CMU_DBGCLKSEL_REG:
-
-#if defined( _CMU_DBGCLKSEL_DBG_MASK )
-    switch (CMU->DBGCLKSEL & _CMU_DBGCLKSEL_DBG_MASK)
-    {
-    case CMU_DBGCLKSEL_DBG_HFCLK:
-      ret = cmuSelect_HFCLK;
-      break;
-
-    case CMU_DBGCLKSEL_DBG_AUXHFRCO:
-      ret = cmuSelect_AUXHFRCO;
-      break;
-    }
-#else
-    ret = cmuSelect_AUXHFRCO;
-#endif /* CMU_DBGCLKSEL_DBG */
-
-#if defined( _CMU_CTRL_DBGCLK_MASK )
-    switch(CMU->CTRL & _CMU_CTRL_DBGCLK_MASK)
-    {
-    case CMU_CTRL_DBGCLK_AUXHFRCO:
-      ret = cmuSelect_AUXHFRCO;
-      break;
-
-    case CMU_CTRL_DBGCLK_HFCLK:
-      ret = cmuSelect_HFCLK;
-      break;
-    }
-#else
-    ret = cmuSelect_AUXHFRCO;
-#endif
-    break;
-
-
-#if defined(USB_PRESENT)
-
-  case CMU_USBCCLKSEL_REG:
-    switch(CMU->STATUS &
-           (CMU_STATUS_USBCLFXOSEL |
-#if defined(_CMU_STATUS_USBCHFCLKSEL_MASK)
-            CMU_STATUS_USBCHFCLKSEL |
-#endif
-#if defined(_CMU_STATUS_USBCUSHFRCOSEL_MASK)
-            CMU_STATUS_USBCUSHFRCOSEL |
-#endif
-            CMU_STATUS_USBCLFRCOSEL))
-    {
-
-    case CMU_STATUS_USBCLFXOSEL:
-      ret = cmuSelect_LFXO;
-      break;
-
-    case CMU_STATUS_USBCLFRCOSEL:
-      ret = cmuSelect_LFRCO;
-      break;
-
-#if defined(_CMU_STATUS_USBCHFCLKSEL_MASK)
-    case CMU_STATUS_USBCHFCLKSEL:
-      ret = cmuSelect_HFCLK;
-      break;
-#endif
-
-#if defined(_CMU_STATUS_USBCUSHFRCOSEL_MASK)
-    case CMU_STATUS_USBCUSHFRCOSEL:
-      ret = cmuSelect_USHFRCO;
-      break;
-#endif
-
-    default:
-      ret = cmuSelect_Disabled;
-      break;
-    }
-    break;
-#endif
-
-  default:
-    EFM_ASSERT(0);
-    ret = cmuSelect_Error;
-    break;
   }
 
   return ret;
 }
 
 
-/**************************************************************************//**
+/***************************************************************************//**
  * @brief
  *   Select reference clock/oscillator used for a clock branch.
  *
@@ -1513,7 +2381,11 @@
  *   Clock branch to select reference clock for. One of:
  *   @li #cmuClock_HF
  *   @li #cmuClock_LFA
- *   @li #cmuClock_LFB
+ *   @li #cmuClock_LFB @if _CMU_LFCLKSEL_LFAE_ULFRCO
+ *   @li #cmuClock_LFC
+ *   @endif            @if _SILICON_LABS_32B_PLATFORM_2
+ *   @li #cmuClock_LFE
+ *   @endif
  *   @li #cmuClock_DBG @if DOXYDOC_USB_PRESENT
  *   @li #cmuClock_USBC
  *   @endif
@@ -1530,308 +2402,425 @@
  *   @li #cmuSelect_HFCLK @ifnot DOXYDOC_EFM32_GECKO_FAMILY
  *   @li #cmuSelect_ULFRCO
  *   @endif
- *****************************************************************************/
+ ******************************************************************************/
 void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref)
 {
   uint32_t        select = cmuOsc_HFRCO;
   CMU_Osc_TypeDef osc    = cmuOsc_HFRCO;
   uint32_t        freq;
-  uint32_t        selReg;
-#if !defined(_EFM32_GECKO_FAMILY)
+  uint32_t        tmp;
+  uint32_t        selRegId;
+#if defined( _SILICON_LABS_32B_PLATFORM_2 )
+  volatile uint32_t *selReg = NULL;
+#endif
+#if defined( CMU_LFCLKSEL_LFAE_ULFRCO )
   uint32_t        lfExtended = 0;
 #endif
-  uint32_t        tmp;
-
-  selReg = (clock >> CMU_SEL_REG_POS) & CMU_SEL_REG_MASK;
-
-  switch (selReg)
+
+  selRegId = (clock >> CMU_SEL_REG_POS) & CMU_SEL_REG_MASK;
+
+  switch (selRegId)
   {
-  case CMU_HFCLKSEL_REG:
-    switch (ref)
-    {
-    case cmuSelect_LFXO:
-      select = CMU_CMD_HFCLKSEL_LFXO;
-      osc    = cmuOsc_LFXO;
-      break;
-
-    case cmuSelect_LFRCO:
-      select = CMU_CMD_HFCLKSEL_LFRCO;
-      osc    = cmuOsc_LFRCO;
-      break;
-
-    case cmuSelect_HFXO:
-      select = CMU_CMD_HFCLKSEL_HFXO;
-      osc    = cmuOsc_HFXO;
+    case CMU_HFCLKSEL_REG:
+      switch (ref)
+      {
+        case cmuSelect_LFXO:
+#if defined( _SILICON_LABS_32B_PLATFORM_2 )
+          select = CMU_HFCLKSEL_HF_LFXO;
+#elif defined( _SILICON_LABS_32B_PLATFORM_1 )
+          select = CMU_CMD_HFCLKSEL_LFXO;
+#endif
+          osc = cmuOsc_LFXO;
+          break;
+
+        case cmuSelect_LFRCO:
+#if defined( _SILICON_LABS_32B_PLATFORM_2 )
+          select = CMU_HFCLKSEL_HF_LFRCO;
+#elif defined( _SILICON_LABS_32B_PLATFORM_1 )
+          select = CMU_CMD_HFCLKSEL_LFRCO;
+#endif
+          osc = cmuOsc_LFRCO;
+          break;
+
+        case cmuSelect_HFXO:
+          osc = cmuOsc_HFXO;
+#if defined( _SILICON_LABS_32B_PLATFORM_2 )
+          select = CMU_HFCLKSEL_HF_HFXO;
+          /* Adjust HFXO buffer current for high frequencies, */
+          /* enable WSHFLE for frequencies above 32MHz.       */
+          if (SystemHFXOClockGet() > 32000000)
+          {
+            CMU->CTRL |= CMU_CTRL_WSHFLE;
+          }
+#elif defined( _SILICON_LABS_32B_PLATFORM_1 )
+          select = CMU_CMD_HFCLKSEL_HFXO;
 #if defined( CMU_CTRL_HFLE )
-      /* Adjust HFXO buffer current for high frequencies, enable HFLE for */
-      /* frequencies above CMU_MAX_FREQ_HFLE. */
-      if(SystemHFXOClockGet() > CMU_MAX_FREQ_HFLE)
-      {
-        CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFXOBUFCUR_MASK) |
-          CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ |
-          /* Must have HFLE enabled to access some LE peripherals >=32MHz */
-          CMU_CTRL_HFLE;
-
-        /* Set HFLE and DIV4 factor for peripheral clock if HFCORE clock for
-           LE is enabled. */
-        if (CMU->HFCORECLKEN0 & CMU_HFCORECLKEN0_LE)
-        {
-          BITBAND_Peripheral(&(CMU->HFCORECLKDIV),
-                             _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT, 1);
-        }
-      } else {
-        /* This can happen if the user configures the EFM32_HFXO_FREQ to */
-        /* use another oscillator frequency */
-        CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFXOBUFCUR_MASK) |
-          CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ;
-      }
+          /* Adjust HFXO buffer current for high frequencies,     */
+          /* enable HFLE for frequencies above CMU_MAX_FREQ_HFLE. */
+          if(SystemHFXOClockGet() > CMU_MAX_FREQ_HFLE())
+          {
+            CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFXOBUFCUR_MASK)
+                        | CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ
+            /* Must have HFLE enabled to access some LE peripherals >=32MHz */
+                        | CMU_CTRL_HFLE;
+
+            /* Set HFLE and DIV4 factor for peripheral clock if HFCORE  */
+            /* clock for LE is enabled.                                 */
+            if (CMU->HFCORECLKEN0 & CMU_HFCORECLKEN0_LE)
+            {
+              BUS_RegBitWrite(&CMU->HFCORECLKDIV,
+                              _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT, 1);
+            }
+          }
+          else
+          {
+            /* This can happen if the user configures the EFM32_HFXO_FREQ to */
+            /* use another oscillator frequency */
+            CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFXOBUFCUR_MASK)
+                        | CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ;
+          }
 #endif
-      break;
-
-    case cmuSelect_HFRCO:
-      select = CMU_CMD_HFCLKSEL_HFRCO;
-      osc    = cmuOsc_HFRCO;
-      break;
+#endif
+          break;
+
+        case cmuSelect_HFRCO:
+#if defined( _SILICON_LABS_32B_PLATFORM_2 )
+          select = CMU_HFCLKSEL_HF_HFRCO;
+#elif defined( _SILICON_LABS_32B_PLATFORM_1 )
+          select = CMU_CMD_HFCLKSEL_HFRCO;
+#endif
+          osc = cmuOsc_HFRCO;
+          break;
 
 #if defined( CMU_CMD_HFCLKSEL_USHFRCODIV2 )
-    case cmuSelect_USHFRCODIV2:
-      select = CMU_CMD_HFCLKSEL_USHFRCODIV2;
-      osc    = cmuOsc_USHFRCO;
+        case cmuSelect_USHFRCODIV2:
+          select = CMU_CMD_HFCLKSEL_USHFRCODIV2;
+          osc = cmuOsc_USHFRCO;
+          break;
+#endif
+
+#if defined( CMU_LFCLKSEL_LFAE_ULFRCO ) || defined( CMU_LFACLKSEL_LFA_ULFRCO )
+        case cmuSelect_ULFRCO:
+          /* ULFRCO cannot be used as HFCLK  */
+          EFM_ASSERT(0);
+          return;
+#endif
+
+        default:
+          EFM_ASSERT(0);
+          return;
+      }
+
+      /* Ensure selected oscillator is enabled, waiting for it to stabilize */
+      CMU_OscillatorEnable(osc, true, true);
+
+      /* Configure worst case wait states for flash access before selecting */
+      flashWaitStateMax();
+
+      /* Switch to selected oscillator */
+#if defined( _SILICON_LABS_32B_PLATFORM_2 )
+      CMU->HFCLKSEL = select;
+#elif defined( _SILICON_LABS_32B_PLATFORM_1 )
+      CMU->CMD = select;
+#endif
+
+      /* Keep EMU module informed */
+      EMU_UpdateOscConfig();
+
+      /* Update CMSIS core clock variable */
+      /* (The function will update the global variable) */
+      freq = SystemCoreClockGet();
+
+      /* Optimize flash access wait state setting for currently selected core clk */
+      flashWaitStateControl(freq);
+      break;
+
+#if defined( _SILICON_LABS_32B_PLATFORM_2 )
+    case CMU_LFACLKSEL_REG:
+      selReg = (selReg == NULL) ? &CMU->LFACLKSEL : selReg;
+#if !defined( _CMU_LFACLKSEL_LFA_HFCLKLE )
+      /* HFCLKCLE can not be used as LFACLK */
+      EFM_ASSERT(ref != cmuSelect_HFCLKLE);
+#endif
+    case CMU_LFECLKSEL_REG:
+      selReg = (selReg == NULL) ? &CMU->LFECLKSEL : selReg;
+#if !defined( _CMU_LFECLKSEL_LFE_HFCLKLE )
+      /* HFCLKCLE can not be used as LFECLK */
+      EFM_ASSERT(ref != cmuSelect_HFCLKLE);
+#endif
+    case CMU_LFBCLKSEL_REG:
+      selReg = (selReg == NULL) ? &CMU->LFBCLKSEL : selReg;
+      switch (ref)
+      {
+        case cmuSelect_Disabled:
+          tmp = _CMU_LFACLKSEL_LFA_DISABLED;
+          break;
+
+        case cmuSelect_LFXO:
+          /* Ensure selected oscillator is enabled, waiting for it to stabilize */
+          CMU_OscillatorEnable(cmuOsc_LFXO, true, true);
+          tmp = _CMU_LFACLKSEL_LFA_LFXO;
+          break;
+
+        case cmuSelect_LFRCO:
+          /* Ensure selected oscillator is enabled, waiting for it to stabilize */
+          CMU_OscillatorEnable(cmuOsc_LFRCO, true, true);
+          tmp = _CMU_LFACLKSEL_LFA_LFRCO;
+          break;
+
+        case cmuSelect_HFCLKLE:
+          /* Ensure HFCORE to LE clocking is enabled */
+          BUS_RegBitWrite(&CMU->HFBUSCLKEN0, _CMU_HFBUSCLKEN0_LE_SHIFT, 1);
+          tmp = _CMU_LFBCLKSEL_LFB_HFCLKLE;
+
+          /* If core frequency is > 32MHz enable WSHFLE */
+          freq = SystemCoreClockGet();
+          if (freq > 32000000U)
+          {
+            /* Enable CMU HFLE */
+            BUS_RegBitWrite(&CMU->CTRL, _CMU_CTRL_WSHFLE_SHIFT, 1);
+
+            /* Enable DIV4 factor for peripheral clock */
+            BUS_RegBitWrite(&CMU->HFPRESC, _CMU_HFPRESC_HFCLKLEPRESC_SHIFT, 1);
+          }
+          break;
+
+        case cmuSelect_ULFRCO:
+          /* ULFRCO is always on, there is no need to enable it. */
+          tmp = _CMU_LFACLKSEL_LFA_ULFRCO;
+          break;
+
+        default:
+          EFM_ASSERT(0);
+          return;
+      }
+      *selReg = tmp;
+      break;
+
+#elif defined( _SILICON_LABS_32B_PLATFORM_1 )
+    case CMU_LFACLKSEL_REG:
+    case CMU_LFBCLKSEL_REG:
+      switch (ref)
+      {
+        case cmuSelect_Disabled:
+          tmp = _CMU_LFCLKSEL_LFA_DISABLED;
+          break;
+
+        case cmuSelect_LFXO:
+          /* Ensure selected oscillator is enabled, waiting for it to stabilize */
+          CMU_OscillatorEnable(cmuOsc_LFXO, true, true);
+          tmp = _CMU_LFCLKSEL_LFA_LFXO;
+          break;
+
+        case cmuSelect_LFRCO:
+          /* Ensure selected oscillator is enabled, waiting for it to stabilize */
+          CMU_OscillatorEnable(cmuOsc_LFRCO, true, true);
+          tmp = _CMU_LFCLKSEL_LFA_LFRCO;
+          break;
+
+        case cmuSelect_CORELEDIV2:
+          /* Ensure HFCORE to LE clocking is enabled */
+          BUS_RegBitWrite(&(CMU->HFCORECLKEN0), _CMU_HFCORECLKEN0_LE_SHIFT, 1);
+          tmp = _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2;
+#if defined( CMU_CTRL_HFLE )
+          /* If core frequency is higher than CMU_MAX_FREQ_HFLE on
+             Giant/Leopard/Wonder, enable HFLE and DIV4. */
+          freq = SystemCoreClockGet();
+          if(freq > CMU_MAX_FREQ_HFLE())
+          {
+            /* Enable CMU HFLE */
+            BUS_RegBitWrite(&CMU->CTRL, _CMU_CTRL_HFLE_SHIFT, 1);
+
+            /* Enable DIV4 factor for peripheral clock */
+            BUS_RegBitWrite(&CMU->HFCORECLKDIV,
+                            _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT, 1);
+          }
+#endif
+          break;
+
+#if defined( CMU_LFCLKSEL_LFAE_ULFRCO )
+        case cmuSelect_ULFRCO:
+          /* ULFRCO is always enabled */
+          tmp = _CMU_LFCLKSEL_LFA_DISABLED;
+          lfExtended = 1;
+          break;
+#endif
+
+        default:
+          /* Illegal clock source for LFA/LFB selected */
+          EFM_ASSERT(0);
+          return;
+      }
+
+      /* Apply select */
+      if (selRegId == CMU_LFACLKSEL_REG)
+      {
+#if defined( _CMU_LFCLKSEL_LFAE_MASK )
+        CMU->LFCLKSEL = (CMU->LFCLKSEL
+                         & ~(_CMU_LFCLKSEL_LFA_MASK | _CMU_LFCLKSEL_LFAE_MASK))
+                        | (tmp << _CMU_LFCLKSEL_LFA_SHIFT)
+                        | (lfExtended << _CMU_LFCLKSEL_LFAE_SHIFT);
+#else
+        CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFA_MASK)
+                        | (tmp << _CMU_LFCLKSEL_LFA_SHIFT);
+#endif
+      }
+      else
+      {
+#if defined( _CMU_LFCLKSEL_LFBE_MASK )
+        CMU->LFCLKSEL = (CMU->LFCLKSEL
+                         & ~(_CMU_LFCLKSEL_LFB_MASK | _CMU_LFCLKSEL_LFBE_MASK))
+                        | (tmp << _CMU_LFCLKSEL_LFB_SHIFT)
+                        | (lfExtended << _CMU_LFCLKSEL_LFBE_SHIFT);
+#else
+        CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFB_MASK)
+                        | (tmp << _CMU_LFCLKSEL_LFB_SHIFT);
+#endif
+      }
+      break;
+
+#if defined( _CMU_LFCLKSEL_LFC_MASK )
+    case CMU_LFCCLKSEL_REG:
+      switch(ref)
+      {
+        case cmuSelect_Disabled:
+          tmp = _CMU_LFCLKSEL_LFA_DISABLED;
+          break;
+
+        case cmuSelect_LFXO:
+          /* Ensure selected oscillator is enabled, waiting for it to stabilize */
+          CMU_OscillatorEnable(cmuOsc_LFXO, true, true);
+          tmp = _CMU_LFCLKSEL_LFC_LFXO;
+          break;
+
+        case cmuSelect_LFRCO:
+          /* Ensure selected oscillator is enabled, waiting for it to stabilize */
+          CMU_OscillatorEnable(cmuOsc_LFRCO, true, true);
+          tmp = _CMU_LFCLKSEL_LFC_LFRCO;
+          break;
+
+        default:
+          /* Illegal clock source for LFC selected */
+          EFM_ASSERT(0);
+          return;
+      }
+
+      /* Apply select */
+      CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFC_MASK)
+                      | (tmp << _CMU_LFCLKSEL_LFC_SHIFT);
       break;
 #endif
-
-#if !defined( _EFM32_GECKO_FAMILY )
-    case cmuSelect_ULFRCO:
-      /* ULFRCO cannot be used as HFCLK  */
-      EFM_ASSERT(0);
+#endif
+
+#if defined( CMU_DBGCLKSEL_DBG ) || defined( CMU_CTRL_DBGCLK )
+    case CMU_DBGCLKSEL_REG:
+      switch(ref)
+      {
+#if defined( CMU_DBGCLKSEL_DBG )
+        case cmuSelect_AUXHFRCO:
+          /* Select AUXHFRCO as debug clock */
+          CMU->DBGCLKSEL = CMU_DBGCLKSEL_DBG_AUXHFRCO;
+          break;
+
+        case cmuSelect_HFCLK:
+          /* Select divided HFCLK as debug clock */
+          CMU->DBGCLKSEL = CMU_DBGCLKSEL_DBG_HFCLK;
+          break;
+#endif
+
+#if defined( CMU_CTRL_DBGCLK )
+        case cmuSelect_AUXHFRCO:
+          /* Select AUXHFRCO as debug clock */
+          CMU->CTRL = (CMU->CTRL & ~(_CMU_CTRL_DBGCLK_MASK))
+                      | CMU_CTRL_DBGCLK_AUXHFRCO;
+          break;
+
+        case cmuSelect_HFCLK:
+          /* Select divided HFCLK as debug clock */
+          CMU->CTRL = (CMU->CTRL & ~(_CMU_CTRL_DBGCLK_MASK))
+                      | CMU_CTRL_DBGCLK_HFCLK;
+          break;
+#endif
+
+        default:
+          /* Illegal clock source for debug selected */
+          EFM_ASSERT(0);
+          return;
+      }
+      break;
+#endif
+
+#if defined(USB_PRESENT)
+    case CMU_USBCCLKSEL_REG:
+      switch(ref)
+      {
+        case cmuSelect_LFXO:
+          /* Select LFXO as clock source for USB, can only be used in sleep mode */
+          /* Ensure selected oscillator is enabled, waiting for it to stabilize */
+          CMU_OscillatorEnable(cmuOsc_LFXO, true, true);
+
+          /* Switch oscillator */
+          CMU->CMD = CMU_CMD_USBCCLKSEL_LFXO;
+
+          /* Wait until clock is activated */
+          while((CMU->STATUS & CMU_STATUS_USBCLFXOSEL)==0)
+          {
+          }
+          break;
+
+        case cmuSelect_LFRCO:
+          /* Select LFRCO as clock source for USB, can only be used in sleep mode */
+          /* Ensure selected oscillator is enabled, waiting for it to stabilize */
+          CMU_OscillatorEnable(cmuOsc_LFRCO, true, true);
+
+          /* Switch oscillator */
+          CMU->CMD = CMU_CMD_USBCCLKSEL_LFRCO;
+
+          /* Wait until clock is activated */
+          while((CMU->STATUS & CMU_STATUS_USBCLFRCOSEL)==0)
+          {
+          }
+          break;
+
+#if defined( CMU_STATUS_USBCHFCLKSEL )
+        case cmuSelect_HFCLK:
+          /* Select undivided HFCLK as clock source for USB */
+          /* Oscillator must already be enabled to avoid a core lockup */
+          CMU->CMD = CMU_CMD_USBCCLKSEL_HFCLKNODIV;
+          /* Wait until clock is activated */
+          while((CMU->STATUS & CMU_STATUS_USBCHFCLKSEL)==0)
+          {
+          }
+          break;
+#endif
+
+#if defined( CMU_CMD_USBCCLKSEL_USHFRCO )
+        case cmuSelect_USHFRCO:
+          /* Select USHFRCO as clock source for USB */
+          /* Ensure selected oscillator is enabled, waiting for it to stabilize */
+          CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true);
+
+          /* Switch oscillator */
+          CMU->CMD = CMU_CMD_USBCCLKSEL_USHFRCO;
+
+          /* Wait until clock is activated */
+          while((CMU->STATUS & CMU_STATUS_USBCUSHFRCOSEL)==0)
+          {
+          }
+          break;
+#endif
+
+        default:
+          /* Illegal clock source for USB */
+          EFM_ASSERT(0);
+          return;
+      }
       break;
 #endif
 
     default:
       EFM_ASSERT(0);
-      return;
-    }
-
-    /* Ensure selected oscillator is enabled, waiting for it to stabilize */
-    CMU_OscillatorEnable(osc, true, true);
-
-    /* Configure worst case wait states for flash access before selecting */
-    CMU_FlashWaitStateMax();
-
-    /* Switch to selected oscillator */
-    CMU->CMD = select;
-
-    /* Keep EMU module informed */
-    EMU_UpdateOscConfig();
-
-    /* Update CMSIS core clock variable */
-    /* (The function will update the global variable) */
-    freq = SystemCoreClockGet();
-
-    /* Optimize flash access wait state setting for currently selected core clk */
-    CMU_FlashWaitStateControl(freq);
-    break;
-
-  case CMU_LFACLKSEL_REG:
-  case CMU_LFBCLKSEL_REG:
-
-    switch (ref)
-    {
-    case cmuSelect_Disabled:
-      tmp = _CMU_LFCLKSEL_LFA_DISABLED;
       break;
-
-    case cmuSelect_LFXO:
-      /* Ensure selected oscillator is enabled, waiting for it to stabilize */
-      CMU_OscillatorEnable(cmuOsc_LFXO, true, true);
-      tmp = _CMU_LFCLKSEL_LFA_LFXO;
-      break;
-
-    case cmuSelect_LFRCO:
-      /* Ensure selected oscillator is enabled, waiting for it to stabilize */
-      CMU_OscillatorEnable(cmuOsc_LFRCO, true, true);
-      tmp = _CMU_LFCLKSEL_LFA_LFRCO;
-      break;
-
-    case cmuSelect_CORELEDIV2:
-      /* Ensure HFCORE to LE clocking is enabled */
-      BITBAND_Peripheral(&(CMU->HFCORECLKEN0), _CMU_HFCORECLKEN0_LE_SHIFT, 1);
-      tmp = _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2;
-#if defined( CMU_CTRL_HFLE )
-      /* If core frequency is higher than CMU_MAX_FREQ_HFLE on
-         Giant/Leopard/Wonder, enable HFLE and DIV4. */
-      freq = SystemCoreClockGet();
-      if(freq > CMU_MAX_FREQ_HFLE)
-      {
-        /* Enable CMU HFLE */
-        BITBAND_Peripheral(&(CMU->CTRL), _CMU_CTRL_HFLE_SHIFT, 1);
-
-        /* Enable DIV4 factor for peripheral clock */
-        BITBAND_Peripheral(&(CMU->HFCORECLKDIV),
-                           _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT, 1);
-      }
-#endif
-      break;
-
-#if !defined(_EFM32_GECKO_FAMILY)
-    case cmuSelect_ULFRCO:
-      /* ULFRCO is always enabled */
-      tmp        = _CMU_LFCLKSEL_LFA_DISABLED;
-      lfExtended = 1;
-      break;
-#endif
-
-    default:
-      /* Illegal clock source for LFA/LFB selected */
-      EFM_ASSERT(0);
-      return;
-    }
-
-    /* Apply select */
-    if (selReg == CMU_LFACLKSEL_REG)
-    {
-#if !defined( _EFM32_GECKO_FAMILY )
-      CMU->LFCLKSEL = (CMU->LFCLKSEL & ~(_CMU_LFCLKSEL_LFA_MASK | _CMU_LFCLKSEL_LFAE_MASK) ) |
-                    (tmp << _CMU_LFCLKSEL_LFA_SHIFT) | (lfExtended << _CMU_LFCLKSEL_LFAE_SHIFT);
-#else
-      CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFA_MASK) |
-                    (tmp << _CMU_LFCLKSEL_LFA_SHIFT);
-#endif
-    }
-    else
-    {
-#if !defined( _EFM32_GECKO_FAMILY )
-      CMU->LFCLKSEL = (CMU->LFCLKSEL & ~(_CMU_LFCLKSEL_LFB_MASK | _CMU_LFCLKSEL_LFBE_MASK) ) |
-                    (tmp << _CMU_LFCLKSEL_LFB_SHIFT) | (lfExtended << _CMU_LFCLKSEL_LFBE_SHIFT);
-#else
-      CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFB_MASK) |
-                    (tmp << _CMU_LFCLKSEL_LFB_SHIFT);
-#endif
-    }
-    break;
-
-#if defined( _CMU_LFCLKSEL_LFC_MASK )
-  case CMU_LFCCLKSEL_REG:
-    switch(ref)
-    {
-    case cmuSelect_Disabled:
-      tmp = _CMU_LFCLKSEL_LFA_DISABLED;
-      break;
-
-    case cmuSelect_LFXO:
-      /* Ensure selected oscillator is enabled, waiting for it to stabilize */
-      CMU_OscillatorEnable(cmuOsc_LFXO, true, true);
-      tmp = _CMU_LFCLKSEL_LFC_LFXO;
-      break;
-
-    case cmuSelect_LFRCO:
-      /* Ensure selected oscillator is enabled, waiting for it to stabilize */
-      CMU_OscillatorEnable(cmuOsc_LFRCO, true, true);
-      tmp = _CMU_LFCLKSEL_LFC_LFRCO;
-      break;
-
-    default:
-      /* Illegal clock source for LFC selected */
-      EFM_ASSERT(0);
-      return;
-    }
-
-    /* Apply select */
-    CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFC_MASK) |
-                    (tmp << _CMU_LFCLKSEL_LFC_SHIFT);
-    break;
-#endif
-
-#if defined( CMU_CTRL_DBGCLK )
-  case CMU_DBGCLKSEL_REG:
-    switch(ref)
-    {
-    case cmuSelect_AUXHFRCO:
-      /* Select AUXHFRCO as debug clock */
-      CMU->CTRL = (CMU->CTRL & ~(_CMU_CTRL_DBGCLK_MASK))| CMU_CTRL_DBGCLK_AUXHFRCO;
-      break;
-
-    case cmuSelect_HFCLK:
-      /* Select divided HFCLK as debug clock */
-      CMU->CTRL = (CMU->CTRL & ~(_CMU_CTRL_DBGCLK_MASK))| CMU_CTRL_DBGCLK_HFCLK;
-      break;
-
-    default:
-      /* Illegal clock source for debug selected */
-      EFM_ASSERT(0);
-      return;
-    }
-    break;
-#endif
-
-#if defined(USB_PRESENT)
-  case CMU_USBCCLKSEL_REG:
-    switch(ref)
-    {
-    case cmuSelect_LFXO:
-      /* Select LFXO as clock source for USB, can only be used in sleep mode */
-
-      /* Ensure selected oscillator is enabled, waiting for it to stabilize */
-      CMU_OscillatorEnable(cmuOsc_LFXO, true, true);
-
-      /* Switch oscillator */
-      CMU->CMD = CMU_CMD_USBCCLKSEL_LFXO;
-
-      /* Wait until clock is activated */
-      while((CMU->STATUS & CMU_STATUS_USBCLFXOSEL)==0);
-      break;
-
-    case cmuSelect_LFRCO:
-      /* Select LFRCO as clock source for USB, can only be used in sleep mode */
-
-      /* Ensure selected oscillator is enabled, waiting for it to stabilize */
-      CMU_OscillatorEnable(cmuOsc_LFRCO, true, true);
-
-      /* Switch oscillator */
-      CMU->CMD = CMU_CMD_USBCCLKSEL_LFRCO;
-
-      /* Wait until clock is activated */
-      while((CMU->STATUS & CMU_STATUS_USBCLFRCOSEL)==0);
-      break;
-
-#if defined( CMU_STATUS_USBCHFCLKSEL )
-    case cmuSelect_HFCLK:
-      /* Select undivided HFCLK as clock source for USB */
-
-      /* Oscillator must already be enabled to avoid a core lockup */
-      CMU->CMD = CMU_CMD_USBCCLKSEL_HFCLKNODIV;
-      /* Wait until clock is activated */
-      while((CMU->STATUS & CMU_STATUS_USBCHFCLKSEL)==0);
-      break;
-#endif
-
-#if defined( CMU_CMD_USBCCLKSEL_USHFRCO )
-    case cmuSelect_USHFRCO:
-      /* Select USHFRCO as clock source for USB */
-
-      /* Ensure selected oscillator is enabled, waiting for it to stabilize */
-      CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true);
-
-      /* Switch oscillator */
-      CMU->CMD = CMU_CMD_USBCCLKSEL_USHFRCO;
-
-      /* Wait until clock is activated */
-      while((CMU->STATUS & CMU_STATUS_USBCUSHFRCOSEL)==0);
-      break;
-#endif
-
-    default:
-      /* Illegal clock source for USB */
-      EFM_ASSERT(0);
-      return;
-    }
-    /* Wait until clock has been activated */
-    break;
-#endif
-
-  default:
-    EFM_ASSERT(0);
-    break;
   }
 }
 
@@ -1877,7 +2866,8 @@
     /* since modifying a register while it is in sync progress should be    */
     /* avoided.                                                             */
     while (CMU->SYNCBUSY)
-      ;
+    {
+    }
 
     CMU->FREEZE = CMU_FREEZE_REGFREEZE;
   }
@@ -1888,147 +2878,7 @@
 }
 
 
-#if defined( _CMU_AUXHFRCOCTRL_BAND_MASK )
-/***************************************************************************//**
- * @brief
- *   Get AUXHFRCO band in use.
- *
- * @return
- *   AUXHFRCO band in use.
- ******************************************************************************/
-CMU_AUXHFRCOBand_TypeDef CMU_AUXHFRCOBandGet(void)
-{
-  return (CMU_AUXHFRCOBand_TypeDef)((CMU->AUXHFRCOCTRL & _CMU_AUXHFRCOCTRL_BAND_MASK) >>
-                                 _CMU_AUXHFRCOCTRL_BAND_SHIFT);
-}
-
-/***************************************************************************//**
- * @brief
- *   Set AUIXHFRCO band and the tuning value based on the value in the
- *   calibration table made during production.
- *
- * @param[in] band
- *   AUXHFRCO band to activate.
- ******************************************************************************/
-void CMU_AUXHFRCOBandSet(CMU_AUXHFRCOBand_TypeDef band)
-{
-  uint32_t tuning;
-
-  /* Read tuning value from calibration table */
-  switch (band)
-  {
-  case cmuAUXHFRCOBand_1MHz:
-    tuning = (DEVINFO->AUXHFRCOCAL0 & _DEVINFO_AUXHFRCOCAL0_BAND1_MASK) >>
-             _DEVINFO_AUXHFRCOCAL0_BAND1_SHIFT;
-    break;
-
-  case cmuAUXHFRCOBand_7MHz:
-    tuning = (DEVINFO->AUXHFRCOCAL0 & _DEVINFO_AUXHFRCOCAL0_BAND7_MASK) >>
-             _DEVINFO_AUXHFRCOCAL0_BAND7_SHIFT;
-    break;
-
-  case cmuAUXHFRCOBand_11MHz:
-    tuning = (DEVINFO->AUXHFRCOCAL0 & _DEVINFO_AUXHFRCOCAL0_BAND11_MASK) >>
-             _DEVINFO_AUXHFRCOCAL0_BAND11_SHIFT;
-    break;
-
-  case cmuAUXHFRCOBand_14MHz:
-    tuning = (DEVINFO->AUXHFRCOCAL0 & _DEVINFO_AUXHFRCOCAL0_BAND14_MASK) >>
-             _DEVINFO_AUXHFRCOCAL0_BAND14_SHIFT;
-    break;
-
-  case cmuAUXHFRCOBand_21MHz:
-    tuning = (DEVINFO->AUXHFRCOCAL1 & _DEVINFO_AUXHFRCOCAL1_BAND21_MASK) >>
-             _DEVINFO_AUXHFRCOCAL1_BAND21_SHIFT;
-    break;
-
-#if defined( _CMU_AUXHFRCOCTRL_BAND_28MHZ )
-  case cmuAUXHFRCOBand_28MHz:
-    tuning = (DEVINFO->AUXHFRCOCAL1 & _DEVINFO_AUXHFRCOCAL1_BAND28_MASK) >>
-             _DEVINFO_AUXHFRCOCAL1_BAND28_SHIFT;
-    break;
-#endif
-
-  default:
-    EFM_ASSERT(0);
-    return;
-  }
-
-  /* Set band/tuning */
-  CMU->AUXHFRCOCTRL = (CMU->AUXHFRCOCTRL &
-                    ~(_CMU_AUXHFRCOCTRL_BAND_MASK | _CMU_AUXHFRCOCTRL_TUNING_MASK)) |
-                   (band << _CMU_AUXHFRCOCTRL_BAND_SHIFT) |
-                   (tuning << _CMU_AUXHFRCOCTRL_TUNING_SHIFT);
-
-}
-#endif
-
-
-#if defined( _CMU_USHFRCOCONF_BAND_MASK )
-/***************************************************************************//**
- * @brief
- *   Get USHFRCO band in use.
- *
- * @return
- *   USHFRCO band in use.
- ******************************************************************************/
-CMU_USHFRCOBand_TypeDef CMU_USHFRCOBandGet(void)
-{
-  return (CMU_USHFRCOBand_TypeDef)((CMU->USHFRCOCONF & _CMU_USHFRCOCONF_BAND_MASK) >>
-                                     _CMU_USHFRCOCONF_BAND_SHIFT);
-}
-
-void CMU_USHFRCOBandSet(CMU_USHFRCOBand_TypeDef band)
-{
-  uint32_t           tuning;
-  uint32_t           fineTuning;
-  CMU_Select_TypeDef osc;
-
-  /* Cannot switch band if USHFRCO is already selected as HF clock. */
-  osc = CMU_ClockSelectGet(cmuClock_HF);
-  EFM_ASSERT((CMU_USHFRCOBandGet() != band) && (osc != cmuSelect_USHFRCO));
-
-  /* Read tuning value from calibration table */
-  switch (band)
-  {
-  case cmuUSHFRCOBand_24MHz:
-    tuning = (DEVINFO->USHFRCOCAL0 & _DEVINFO_USHFRCOCAL0_BAND24_TUNING_MASK) >>
-         _DEVINFO_USHFRCOCAL0_BAND24_TUNING_SHIFT;
-    fineTuning = (DEVINFO->USHFRCOCAL0 & _DEVINFO_USHFRCOCAL0_BAND24_FINETUNING_MASK) >>
-         _DEVINFO_USHFRCOCAL0_BAND24_FINETUNING_SHIFT;
-    break;
-
-  case cmuUSHFRCOBand_48MHz:
-    tuning = (DEVINFO->USHFRCOCAL0 & _DEVINFO_USHFRCOCAL0_BAND48_TUNING_MASK) >>
-         _DEVINFO_USHFRCOCAL0_BAND48_TUNING_SHIFT;
-    fineTuning = (DEVINFO->USHFRCOCAL0 & _DEVINFO_USHFRCOCAL0_BAND48_FINETUNING_MASK) >>
-         _DEVINFO_USHFRCOCAL0_BAND48_FINETUNING_SHIFT;
-    /* Enable the clock divider before switching the band from 48 to 24MHz */
-    BITBAND_Peripheral(&CMU->USHFRCOCONF, _CMU_USHFRCOCONF_USHFRCODIV2DIS_SHIFT, 0);
-    break;
-
-  default:
-    EFM_ASSERT(0);
-    return;
-  }
-
-  /* Set band and tuning */
-  CMU->USHFRCOCONF = (CMU->USHFRCOCONF & ~_CMU_USHFRCOCONF_BAND_MASK) |
-                     (band << _CMU_USHFRCOCONF_BAND_SHIFT);
-  CMU->USHFRCOCTRL = (CMU->USHFRCOCTRL & ~_CMU_USHFRCOCTRL_TUNING_MASK) |
-                     (tuning << _CMU_USHFRCOCTRL_TUNING_SHIFT);
-  CMU->USHFRCOTUNE = (CMU->USHFRCOTUNE & ~_CMU_USHFRCOTUNE_FINETUNING_MASK) |
-                     (fineTuning << _CMU_USHFRCOTUNE_FINETUNING_SHIFT);
-
-  /* Disable the clock divider after switching the band from 48 to 24MHz */
-  if (band == cmuUSHFRCOBand_24MHz)
-  {
-    BITBAND_Peripheral(&CMU->USHFRCOCONF, _CMU_USHFRCOCONF_USHFRCODIV2DIS_SHIFT, 1);
-  }
-}
-#endif
-
-
+#if defined( _CMU_HFRCOCTRL_BAND_MASK )
 /***************************************************************************//**
  * @brief
  *   Get HFRCO band in use.
@@ -2038,11 +2888,13 @@
  ******************************************************************************/
 CMU_HFRCOBand_TypeDef CMU_HFRCOBandGet(void)
 {
-  return (CMU_HFRCOBand_TypeDef)((CMU->HFRCOCTRL & _CMU_HFRCOCTRL_BAND_MASK) >>
-                                 _CMU_HFRCOCTRL_BAND_SHIFT);
+  return (CMU_HFRCOBand_TypeDef)((CMU->HFRCOCTRL & _CMU_HFRCOCTRL_BAND_MASK)
+                                 >> _CMU_HFRCOCTRL_BAND_SHIFT);
 }
-
-
+#endif /* _CMU_HFRCOCTRL_BAND_MASK */
+
+
+#if defined( _CMU_HFRCOCTRL_BAND_MASK )
 /***************************************************************************//**
  * @brief
  *   Set HFRCO band and the tuning value based on the value in the calibration
@@ -2060,41 +2912,41 @@
   /* Read tuning value from calibration table */
   switch (band)
   {
-  case cmuHFRCOBand_1MHz:
-    tuning = (DEVINFO->HFRCOCAL0 & _DEVINFO_HFRCOCAL0_BAND1_MASK) >>
-             _DEVINFO_HFRCOCAL0_BAND1_SHIFT;
-    break;
-
-  case cmuHFRCOBand_7MHz:
-    tuning = (DEVINFO->HFRCOCAL0 & _DEVINFO_HFRCOCAL0_BAND7_MASK) >>
-             _DEVINFO_HFRCOCAL0_BAND7_SHIFT;
-    break;
-
-  case cmuHFRCOBand_11MHz:
-    tuning = (DEVINFO->HFRCOCAL0 & _DEVINFO_HFRCOCAL0_BAND11_MASK) >>
-             _DEVINFO_HFRCOCAL0_BAND11_SHIFT;
-    break;
-
-  case cmuHFRCOBand_14MHz:
-    tuning = (DEVINFO->HFRCOCAL0 & _DEVINFO_HFRCOCAL0_BAND14_MASK) >>
-             _DEVINFO_HFRCOCAL0_BAND14_SHIFT;
-    break;
-
-  case cmuHFRCOBand_21MHz:
-    tuning = (DEVINFO->HFRCOCAL1 & _DEVINFO_HFRCOCAL1_BAND21_MASK) >>
-             _DEVINFO_HFRCOCAL1_BAND21_SHIFT;
-    break;
+    case cmuHFRCOBand_1MHz:
+      tuning = (DEVINFO->HFRCOCAL0 & _DEVINFO_HFRCOCAL0_BAND1_MASK)
+               >> _DEVINFO_HFRCOCAL0_BAND1_SHIFT;
+      break;
+
+    case cmuHFRCOBand_7MHz:
+      tuning = (DEVINFO->HFRCOCAL0 & _DEVINFO_HFRCOCAL0_BAND7_MASK)
+               >> _DEVINFO_HFRCOCAL0_BAND7_SHIFT;
+      break;
+
+    case cmuHFRCOBand_11MHz:
+      tuning = (DEVINFO->HFRCOCAL0 & _DEVINFO_HFRCOCAL0_BAND11_MASK)
+               >> _DEVINFO_HFRCOCAL0_BAND11_SHIFT;
+      break;
+
+    case cmuHFRCOBand_14MHz:
+      tuning = (DEVINFO->HFRCOCAL0 & _DEVINFO_HFRCOCAL0_BAND14_MASK)
+               >> _DEVINFO_HFRCOCAL0_BAND14_SHIFT;
+      break;
+
+    case cmuHFRCOBand_21MHz:
+      tuning = (DEVINFO->HFRCOCAL1 & _DEVINFO_HFRCOCAL1_BAND21_MASK)
+               >> _DEVINFO_HFRCOCAL1_BAND21_SHIFT;
+      break;
 
 #if defined( _CMU_HFRCOCTRL_BAND_28MHZ )
-  case cmuHFRCOBand_28MHz:
-    tuning = (DEVINFO->HFRCOCAL1 & _DEVINFO_HFRCOCAL1_BAND28_MASK) >>
-             _DEVINFO_HFRCOCAL1_BAND28_SHIFT;
-    break;
+    case cmuHFRCOBand_28MHz:
+      tuning = (DEVINFO->HFRCOCAL1 & _DEVINFO_HFRCOCAL1_BAND28_MASK)
+               >> _DEVINFO_HFRCOCAL1_BAND28_SHIFT;
+      break;
 #endif
 
-  default:
-    EFM_ASSERT(0);
-    return;
+    default:
+      EFM_ASSERT(0);
+      return;
   }
 
   /* If HFRCO is used for core clock, we have to consider flash access WS. */
@@ -2102,14 +2954,14 @@
   if (osc == cmuSelect_HFRCO)
   {
     /* Configure worst case wait states for flash access before setting divider */
-    CMU_FlashWaitStateMax();
+    flashWaitStateMax();
   }
 
   /* Set band/tuning */
   CMU->HFRCOCTRL = (CMU->HFRCOCTRL &
-                    ~(_CMU_HFRCOCTRL_BAND_MASK | _CMU_HFRCOCTRL_TUNING_MASK)) |
-                   (band << _CMU_HFRCOCTRL_BAND_SHIFT) |
-                   (tuning << _CMU_HFRCOCTRL_TUNING_SHIFT);
+                    ~(_CMU_HFRCOCTRL_BAND_MASK | _CMU_HFRCOCTRL_TUNING_MASK))
+                   | (band << _CMU_HFRCOCTRL_BAND_SHIFT)
+                   | (tuning << _CMU_HFRCOCTRL_TUNING_SHIFT);
 
   /* If HFRCO is used for core clock, optimize flash WS */
   if (osc == cmuSelect_HFRCO)
@@ -2121,13 +2973,137 @@
     freq = SystemCoreClockGet();
 
     /* Optimize flash access wait state setting for current core clk */
-    CMU_FlashWaitStateControl(freq);
+    flashWaitStateControl(freq);
+  }
+}
+#endif /* _CMU_HFRCOCTRL_BAND_MASK */
+
+
+#if defined( _CMU_HFRCOCTRL_FREQRANGE_MASK )
+/**************************************************************************//**
+ * @brief
+ *   Get a pointer to the HFRCO frequency calibration word in DEVINFO
+ *
+ * @param[in] freq
+ *   Frequency in Hz
+ *
+ * @return
+ *   HFRCO calibration word for a given frequency
+ *****************************************************************************/
+static uint32_t CMU_HFRCODevinfoGet(CMU_HFRCOFreq_TypeDef freq)
+{
+  switch (freq)
+  {
+    /* 1, 2 and 4MHz share the same calibration word */
+    case cmuHFRCOFreq_1M0Hz:
+    case cmuHFRCOFreq_2M0Hz:
+    case cmuHFRCOFreq_4M0Hz:
+      return DEVINFO->HFRCOCAL0;
+
+    case cmuHFRCOFreq_7M0Hz:
+      return DEVINFO->HFRCOCAL3;
+
+    case cmuHFRCOFreq_13M0Hz:
+      return DEVINFO->HFRCOCAL6;
+
+    case cmuHFRCOFreq_16M0Hz:
+      return DEVINFO->HFRCOCAL7;
+
+    case cmuHFRCOFreq_19M0Hz:
+      return DEVINFO->HFRCOCAL8;
+
+    case cmuHFRCOFreq_26M0Hz:
+      return DEVINFO->HFRCOCAL10;
+
+    case cmuHFRCOFreq_32M0Hz:
+      return DEVINFO->HFRCOCAL11;
+
+    case cmuHFRCOFreq_38M0Hz:
+      return DEVINFO->HFRCOCAL12;
+
+    default: /* cmuHFRCOFreq_UserDefined */
+      return 0;
   }
 }
 
 
 /***************************************************************************//**
  * @brief
+ *   Get HFRCO frequency enumeration in use
+ *
+ * @return
+ *   HFRCO frequency enumeration in use
+ ******************************************************************************/
+CMU_HFRCOFreq_TypeDef CMU_HFRCOFreqGet(void)
+{
+  return (CMU_HFRCOFreq_TypeDef)SystemHfrcoFreq;
+}
+
+
+/***************************************************************************//**
+ * @brief
+ *   Set HFRCO calibration for the selected target frequency
+ *
+ * @param[in] freq
+ *   HFRCO frequency band to set
+ ******************************************************************************/
+void CMU_HFRCOFreqSet(CMU_HFRCOFreq_TypeDef freq)
+{
+  uint32_t freqCal;
+
+  /* Get DEVINFO index, set CMSIS frequency SystemHfrcoFreq */
+  freqCal = CMU_HFRCODevinfoGet(freq);
+  EFM_ASSERT((freqCal != 0) && (freqCal != UINT_MAX));
+  SystemHfrcoFreq = (uint32_t)freq;
+
+  /* Set max wait-states while changing core clock */
+  if (CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCO)
+  {
+    flashWaitStateMax();
+  }
+
+  /* Wait for any previous sync to complete, and then set calibration data
+     for the selected frequency.  */
+  while(BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_HFRCOBSY_SHIFT));
+
+  /* Check for valid calibration data */
+  EFM_ASSERT(freqCal != UINT_MAX);
+
+  /* Set divider in HFRCOCTRL for 1, 2 and 4MHz */
+  switch(freq)
+  {
+    case cmuHFRCOFreq_1M0Hz:
+      freqCal = (freqCal & ~_CMU_HFRCOCTRL_CLKDIV_MASK)
+                | CMU_HFRCOCTRL_CLKDIV_DIV4;
+      break;
+
+    case cmuHFRCOFreq_2M0Hz:
+      freqCal = (freqCal & ~_CMU_HFRCOCTRL_CLKDIV_MASK)
+                | CMU_HFRCOCTRL_CLKDIV_DIV2;
+      break;
+
+    case cmuHFRCOFreq_4M0Hz:
+      freqCal = (freqCal & ~_CMU_HFRCOCTRL_CLKDIV_MASK)
+                | CMU_HFRCOCTRL_CLKDIV_DIV1;
+      break;
+
+    default:
+      break;
+  }
+  CMU->HFRCOCTRL = freqCal;
+
+  /* Optimize flash access wait-state configuration for this frequency, */
+  /* if HFRCO is reference for core clock.                              */
+  if (CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCO)
+  {
+    flashWaitStateControl((uint32_t)freq);
+  }
+}
+#endif /* _CMU_HFRCOCTRL_FREQRANGE_MASK */
+
+#if defined( _CMU_HFRCOCTRL_SUDELAY_MASK )
+/***************************************************************************//**
+ * @brief
  *   Get the HFRCO startup delay.
  *
  * @details
@@ -2138,8 +3114,8 @@
  ******************************************************************************/
 uint32_t CMU_HFRCOStartupDelayGet(void)
 {
-  return((CMU->HFRCOCTRL & _CMU_HFRCOCTRL_SUDELAY_MASK) >>
-         _CMU_HFRCOCTRL_SUDELAY_SHIFT);
+  return (CMU->HFRCOCTRL & _CMU_HFRCOCTRL_SUDELAY_MASK)
+         >> _CMU_HFRCOCTRL_SUDELAY_SHIFT;
 }
 
 
@@ -2157,10 +3133,156 @@
 {
   EFM_ASSERT(delay <= 31);
 
-  delay         &= (_CMU_HFRCOCTRL_SUDELAY_MASK >> _CMU_HFRCOCTRL_SUDELAY_SHIFT);
-  CMU->HFRCOCTRL = (CMU->HFRCOCTRL & ~(_CMU_HFRCOCTRL_SUDELAY_MASK)) |
-                   (delay << _CMU_HFRCOCTRL_SUDELAY_SHIFT);
+  delay &= _CMU_HFRCOCTRL_SUDELAY_MASK >> _CMU_HFRCOCTRL_SUDELAY_SHIFT;
+  CMU->HFRCOCTRL = (CMU->HFRCOCTRL & ~(_CMU_HFRCOCTRL_SUDELAY_MASK))
+                   | (delay << _CMU_HFRCOCTRL_SUDELAY_SHIFT);
+}
+#endif
+
+
+#if defined( _CMU_HFXOCTRL_AUTOSTARTRDYSELRAC_MASK )
+/***************************************************************************//**
+ * @brief
+ *   Enable or disable HFXO autostart
+ *
+ * @param[in] enRACStartSel
+ *   If true, HFXO is automatically started and selected upon RAC wakeup.
+ *   If false, HFXO is not started or selected automatically upon RAC wakeup.
+ *
+ * @param[in] enEM0EM1Start
+ *   If true, HFXO is automatically started upon entering EM0/EM1 entry from
+ *   EM2/EM3. HFXO selection has to be handled by the user.
+ *   If false, HFXO is not started automatically when entering EM0/EM1.
+ *
+ * @param[in] enEM0EM1StartSel
+ *   If true, HFXO is automatically started and immediately selected upon
+ *   entering EM0/EM1 entry from EM2/EM3. Note that this option stalls the use of
+ *   HFSRCCLK until HFXO becomes ready.
+ *   If false, HFXO is not started or selected automatically when entering
+ *   EM0/EM1.
+ ******************************************************************************/
+void CMU_HFXOAutostartEnable(bool enRACStartSel,
+                             bool enEM0EM1Start,
+                             bool enEM0EM1StartSel)
+{
+  uint32_t hfxoCtrl;
+  hfxoCtrl = CMU->HFXOCTRL & ~(_CMU_HFXOCTRL_AUTOSTARTRDYSELRAC_MASK
+                              | _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK
+                              | _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK);
+
+  hfxoCtrl |= (enRACStartSel ? CMU_HFXOCTRL_AUTOSTARTRDYSELRAC : 0)
+              | (enEM0EM1Start ? CMU_HFXOCTRL_AUTOSTARTEM0EM1 : 0)
+              | (enEM0EM1StartSel ? CMU_HFXOCTRL_AUTOSTARTSELEM0EM1 : 0);
+
+  CMU->HFXOCTRL = hfxoCtrl;
 }
+#endif /* _CMU_HFXOCTRL_AUTOSTARTRDYSELRAC_MASK */
+
+
+#if defined( _CMU_HFXOCTRL_MASK )
+/**************************************************************************//**
+ * @brief
+ *   Set HFXO control registers
+ *
+ * @note
+ *   HFXO configuration should be obtained from a configuration tool,
+ *   app note or xtal datasheet. This function disables the HFXO to ensure
+ *   a valid state before update.
+ *
+ * @param[in] hfxoInit
+ *    HFXO setup parameters
+ *****************************************************************************/
+void CMU_HFXOInit(CMU_HFXOInit_TypeDef *hfxoInit)
+{
+  uint32_t ishReg;
+  uint32_t ishMax;
+
+  /* Do not disable HFXO if it is currently selected as HF/Core clock */
+  EFM_ASSERT(CMU_ClockSelectGet(cmuClock_HF) != cmuSelect_HFXO);
+
+  /* HFXO must be disabled before reconfiguration */
+  CMU_OscillatorEnable(cmuOsc_HFXO, false, false);
+
+  /* Apply control settings */
+  BUS_RegMaskedWrite(&CMU->HFXOCTRL,
+                     _CMU_HFXOCTRL_LOWPOWER_MASK
+#if defined( _CMU_HFXOCTRL_AUTOSTARTRDYSELRAC_MASK )
+                     | _CMU_HFXOCTRL_AUTOSTARTRDYSELRAC_MASK
+#endif
+                     | _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK
+                     | _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK,
+                     (hfxoInit->lowPowerMode
+                      ? CMU_HFXOCTRL_LOWPOWER : 0)
+#if defined( _CMU_HFXOCTRL_AUTOSTARTRDYSELRAC_MASK )
+                     | (hfxoInit->autoStartSelOnRacWakeup
+                        ? CMU_HFXOCTRL_AUTOSTARTRDYSELRAC : 0)
+#endif
+                     | (hfxoInit->autoStartEm01
+                        ? CMU_HFXOCTRL_AUTOSTARTEM0EM1 : 0)
+                     | (hfxoInit->autoSelEm01
+                        ? CMU_HFXOCTRL_AUTOSTARTSELEM0EM1 : 0));
+
+  /* Set XTAL tuning parameters */
+
+  /* Set peak detection threshold in CMU_HFXOCTRL1_PEAKDETTHR[2:0] (hidden). */
+  BUS_RegMaskedWrite((volatile uint32_t *)0x400E4028, 0x7, hfxoInit->thresholdPeakDetect);
+
+  /* Set tuning for startup and steady state */
+  BUS_RegMaskedWrite(&CMU->HFXOSTARTUPCTRL,
+                     _CMU_HFXOSTARTUPCTRL_CTUNE_MASK
+                     | _CMU_HFXOSTARTUPCTRL_REGISHWARM_MASK
+                     | _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK
+                     | _CMU_HFXOSTARTUPCTRL_IBTRIMXOCOREWARM_MASK,
+                     (hfxoInit->ctuneStartup
+                      << _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT)
+                     | (hfxoInit->regIshStartup
+                        << _CMU_HFXOSTARTUPCTRL_REGISHWARM_SHIFT)
+                     | (hfxoInit->xoCoreBiasTrimStartup
+                        << _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT)
+                     | 0x4 /* Recommended tuning */
+                        << _CMU_HFXOSTARTUPCTRL_IBTRIMXOCOREWARM_SHIFT);
+
+  /* Adjust CMU_HFXOSTEADYSTATECTRL_REGISHUPPER according to regIshSteadyState.
+     Saturate at max value. Please see the reference manual page 433 and Section
+     12.5.10 CMU_HFXOSTEADYSTATECTRL for more details. */
+  ishReg = hfxoInit->regIshSteadyState + 3;
+  ishMax = _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_MASK
+            >> _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_SHIFT;
+  ishReg = ishReg > ishMax ? ishMax : ishReg;
+  ishReg <<= _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_SHIFT;
+
+  BUS_RegMaskedWrite(&CMU->HFXOSTEADYSTATECTRL,
+                     _CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK
+                     | _CMU_HFXOSTEADYSTATECTRL_REGISH_MASK
+                     | _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK
+                     | _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_MASK,
+                     (hfxoInit->ctuneSteadyState
+                      << _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT)
+                     | (hfxoInit->regIshSteadyState
+                        << _CMU_HFXOSTEADYSTATECTRL_REGISH_SHIFT)
+                     | (hfxoInit->xoCoreBiasTrimSteadyState
+                        << _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT)
+                     | ishReg);
+
+  /* Set timeouts */
+  BUS_RegMaskedWrite(&CMU->HFXOTIMEOUTCTRL,
+                     _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_MASK
+                     | _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_MASK
+                     | _CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_MASK
+                     | _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_MASK
+                     | _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_MASK,
+                     (hfxoInit->timeoutShuntOptimization
+                      << _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_SHIFT)
+                     | (hfxoInit->timeoutPeakDetect
+                        << _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT)
+                     | (hfxoInit->timeoutWarmSteady
+                        << _CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_SHIFT)
+                     | (hfxoInit->timeoutSteady
+                        << _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT)
+                     | (hfxoInit->timeoutStartup
+                        << _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT));
+}
+#endif
 
 
 /***************************************************************************//**
@@ -2172,8 +3294,8 @@
  ******************************************************************************/
 uint32_t CMU_LCDClkFDIVGet(void)
 {
-#if defined(LCD_PRESENT)
-  return((CMU->LCDCTRL & _CMU_LCDCTRL_FDIV_MASK) >> _CMU_LCDCTRL_FDIV_SHIFT);
+#if defined( LCD_PRESENT )
+  return (CMU->LCDCTRL & _CMU_LCDCTRL_FDIV_MASK) >> _CMU_LCDCTRL_FDIV_SHIFT;
 #else
   return 0;
 #endif /* defined(LCD_PRESENT) */
@@ -2195,7 +3317,7 @@
  ******************************************************************************/
 void CMU_LCDClkFDIVSet(uint32_t div)
 {
-#if defined(LCD_PRESENT)
+#if defined( LCD_PRESENT )
   EFM_ASSERT(div <= cmuClkDiv_128);
 
   /* Do not allow modification if LCD clock enabled */
@@ -2213,6 +3335,38 @@
 }
 
 
+#if defined( _CMU_LFXOCTRL_MASK )
+/**************************************************************************//**
+ * @brief
+ *   Set LFXO control registers
+ *
+ * @note
+ *   LFXO configuration should be obtained from a configuration tool,
+ *   app note or xtal datasheet. This function disables the LFXO to ensure
+ *   a valid state before update.
+ *
+ * @param[in] lfxoInit
+ *    LFXO setup parameters
+ *****************************************************************************/
+void CMU_LFXOInit(CMU_LFXOInit_TypeDef *lfxoInit)
+{
+  /* Do not disable LFXO if it is currently selected as HF/Core clock */
+  EFM_ASSERT(CMU_ClockSelectGet(cmuClock_HF) != cmuSelect_LFXO);
+
+  /* LFXO must be disabled before reconfiguration */
+  CMU_OscillatorEnable(cmuOsc_LFXO, false, false);
+
+  BUS_RegMaskedWrite(&CMU->LFXOCTRL,
+                     _CMU_LFXOCTRL_TUNING_MASK
+                     | _CMU_LFXOCTRL_GAIN_MASK
+                     | _CMU_LFXOCTRL_TIMEOUT_MASK,
+                     (lfxoInit->ctune << _CMU_LFXOCTRL_TUNING_SHIFT)
+                     | (lfxoInit->gain << _CMU_LFXOCTRL_GAIN_SHIFT)
+                     | (lfxoInit->timeout << _CMU_LFXOCTRL_TIMEOUT_SHIFT));
+}
+#endif
+
+
 /***************************************************************************//**
  * @brief
  *   Enable/disable oscillator.
@@ -2239,76 +3393,125 @@
  ******************************************************************************/
 void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait)
 {
-  uint32_t status;
+  uint32_t rdyBitPos;
+#if defined( _SILICON_LABS_32B_PLATFORM_2 )
+  uint32_t ensBitPos;
+#endif
   uint32_t enBit;
   uint32_t disBit;
 
   switch (osc)
   {
-  case cmuOsc_HFRCO:
-    enBit  = CMU_OSCENCMD_HFRCOEN;
-    disBit = CMU_OSCENCMD_HFRCODIS;
-    status = CMU_STATUS_HFRCORDY;
-    break;
-
-  case cmuOsc_HFXO:
-    enBit  = CMU_OSCENCMD_HFXOEN;
-    disBit = CMU_OSCENCMD_HFXODIS;
-    status = CMU_STATUS_HFXORDY;
-    break;
-
-  case cmuOsc_AUXHFRCO:
-    enBit  = CMU_OSCENCMD_AUXHFRCOEN;
-    disBit = CMU_OSCENCMD_AUXHFRCODIS;
-    status = CMU_STATUS_AUXHFRCORDY;
-    break;
-
-  case cmuOsc_LFRCO:
-    enBit  = CMU_OSCENCMD_LFRCOEN;
-    disBit = CMU_OSCENCMD_LFRCODIS;
-    status = CMU_STATUS_LFRCORDY;
-    break;
-
-  case cmuOsc_LFXO:
-    enBit  = CMU_OSCENCMD_LFXOEN;
-    disBit = CMU_OSCENCMD_LFXODIS;
-    status = CMU_STATUS_LFXORDY;
-    break;
+    case cmuOsc_HFRCO:
+      enBit  = CMU_OSCENCMD_HFRCOEN;
+      disBit = CMU_OSCENCMD_HFRCODIS;
+      rdyBitPos = _CMU_STATUS_HFRCORDY_SHIFT;
+#if defined( _SILICON_LABS_32B_PLATFORM_2 )
+      ensBitPos = _CMU_STATUS_HFRCOENS_SHIFT;
+#endif
+      break;
+
+    case cmuOsc_HFXO:
+      enBit  = CMU_OSCENCMD_HFXOEN;
+      disBit = CMU_OSCENCMD_HFXODIS;
+      rdyBitPos = _CMU_STATUS_HFXORDY_SHIFT;
+#if defined( _SILICON_LABS_32B_PLATFORM_2 )
+      ensBitPos = _CMU_STATUS_HFXOENS_SHIFT;
+#endif
+      break;
+
+    case cmuOsc_AUXHFRCO:
+      enBit  = CMU_OSCENCMD_AUXHFRCOEN;
+      disBit = CMU_OSCENCMD_AUXHFRCODIS;
+      rdyBitPos = _CMU_STATUS_AUXHFRCORDY_SHIFT;
+#if defined( _SILICON_LABS_32B_PLATFORM_2 )
+      ensBitPos = _CMU_STATUS_AUXHFRCOENS_SHIFT;
+#endif
+      break;
+
+    case cmuOsc_LFRCO:
+      enBit  = CMU_OSCENCMD_LFRCOEN;
+      disBit = CMU_OSCENCMD_LFRCODIS;
+      rdyBitPos = _CMU_STATUS_LFRCORDY_SHIFT;
+#if defined( _SILICON_LABS_32B_PLATFORM_2 )
+      ensBitPos = _CMU_STATUS_LFRCOENS_SHIFT;
+#endif
+      break;
+
+    case cmuOsc_LFXO:
+      enBit  = CMU_OSCENCMD_LFXOEN;
+      disBit = CMU_OSCENCMD_LFXODIS;
+      rdyBitPos = _CMU_STATUS_LFXORDY_SHIFT;
+#if defined( _SILICON_LABS_32B_PLATFORM_2 )
+      ensBitPos = _CMU_STATUS_LFXOENS_SHIFT;
+#endif
+      break;
 
 #if defined( _CMU_STATUS_USHFRCOENS_MASK )
-  case cmuOsc_USHFRCO:
-    enBit  = CMU_OSCENCMD_USHFRCOEN;
-    disBit = CMU_OSCENCMD_USHFRCODIS;
-    status = CMU_STATUS_USHFRCORDY;
-    break;
+    case cmuOsc_USHFRCO:
+      enBit  = CMU_OSCENCMD_USHFRCOEN;
+      disBit = CMU_OSCENCMD_USHFRCODIS;
+      rdyBitPos = _CMU_STATUS_USHFRCORDY_SHIFT;
+#if defined( _SILICON_LABS_32B_PLATFORM_2 )
+      ensBitPos = _CMU_STATUS_USHFRCOENS_SHIFT;
+#endif
+      break;
 #endif
 
-#if defined( _CMU_LFCLKSEL_LFAE_ULFRCO )
-  case cmuOsc_ULFRCO:
-    /* ULFRCO is always enabled, and cannot be turned off */
-    return;
+#if defined( CMU_LFCLKSEL_LFAE_ULFRCO )
+    case cmuOsc_ULFRCO:
+      /* ULFRCO is always enabled, and cannot be turned off */
+      return;
 #endif
 
-  default:
-    /* Undefined clock source */
-    EFM_ASSERT(0);
-    return;
+    default:
+      /* Undefined clock source */
+      EFM_ASSERT(0);
+      return;
   }
 
   if (enable)
   {
     CMU->OSCENCMD = enBit;
 
-    /* Wait for clock to stabilize if requested */
+#if defined( _SILICON_LABS_32B_PLATFORM_2 )
+    /* Always wait for ENS to go high */
+    while (!BUS_RegBitRead(&CMU->STATUS, ensBitPos))
+    {
+    }
+#endif
+
+    /* Wait for clock to become ready after enable */
     if (wait)
     {
-      while (!(CMU->STATUS & status))
-        ;
+      while (!BUS_RegBitRead(&CMU->STATUS, rdyBitPos));
+#if defined( _CMU_STATUS_HFXOSHUNTOPTRDY_MASK )
+      /* Wait for shunt current optimization to complete */
+      if ((osc == cmuOsc_HFXO)
+          && (BUS_RegMaskedRead(&CMU->HFXOCTRL,
+                                _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK)
+              == CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD))
+      {
+        while (!BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_HFXOSHUNTOPTRDY_SHIFT))
+        {
+        }
+        /* Assert on failed peak detection. Incorrect HFXO initialization parameters
+           caused startup to fail. Please review parameters. */
+        EFM_ASSERT(BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_HFXOPEAKDETRDY_SHIFT));
+      }
+#endif
     }
   }
   else
   {
     CMU->OSCENCMD = disBit;
+
+#if defined( _SILICON_LABS_32B_PLATFORM_2 )
+    /* Always wait for ENS to go low */
+    while (BUS_RegBitRead(&CMU->STATUS, ensBitPos))
+    {
+    }
+#endif
   }
 
   /* Keep EMU module informed */
@@ -2335,28 +3538,28 @@
 
   switch (osc)
   {
-  case cmuOsc_LFRCO:
-    ret = (CMU->LFRCOCTRL & _CMU_LFRCOCTRL_TUNING_MASK) >>
-          _CMU_LFRCOCTRL_TUNING_SHIFT;
-    break;
-
-  case cmuOsc_HFRCO:
-    ret = (CMU->HFRCOCTRL & _CMU_HFRCOCTRL_TUNING_MASK) >>
-          _CMU_HFRCOCTRL_TUNING_SHIFT;
-    break;
-
-  case cmuOsc_AUXHFRCO:
-    ret = (CMU->AUXHFRCOCTRL & _CMU_AUXHFRCOCTRL_TUNING_MASK) >>
-          _CMU_AUXHFRCOCTRL_TUNING_SHIFT;
-    break;
-
-  default:
-    EFM_ASSERT(0);
-    ret = 0;
-    break;
+    case cmuOsc_LFRCO:
+      ret = (CMU->LFRCOCTRL & _CMU_LFRCOCTRL_TUNING_MASK)
+            >> _CMU_LFRCOCTRL_TUNING_SHIFT;
+      break;
+
+    case cmuOsc_HFRCO:
+      ret = (CMU->HFRCOCTRL & _CMU_HFRCOCTRL_TUNING_MASK)
+            >> _CMU_HFRCOCTRL_TUNING_SHIFT;
+      break;
+
+    case cmuOsc_AUXHFRCO:
+      ret = (CMU->AUXHFRCOCTRL & _CMU_AUXHFRCOCTRL_TUNING_MASK)
+            >> _CMU_AUXHFRCOCTRL_TUNING_SHIFT;
+      break;
+
+    default:
+      EFM_ASSERT(0);
+      ret = 0;
+      break;
   }
 
-  return(ret);
+  return ret;
 }
 
 
@@ -2382,33 +3585,46 @@
 {
   switch (osc)
   {
-  case cmuOsc_LFRCO:
-    EFM_ASSERT(val <= (_CMU_LFRCOCTRL_TUNING_MASK >> _CMU_LFRCOCTRL_TUNING_SHIFT));
-
-    val           &= (_CMU_LFRCOCTRL_TUNING_MASK >> _CMU_LFRCOCTRL_TUNING_SHIFT);
-    CMU->LFRCOCTRL = (CMU->LFRCOCTRL & ~(_CMU_LFRCOCTRL_TUNING_MASK)) |
-                     (val << _CMU_LFRCOCTRL_TUNING_SHIFT);
-    break;
-
-  case cmuOsc_HFRCO:
-    EFM_ASSERT(val <= (_CMU_HFRCOCTRL_TUNING_MASK >> _CMU_HFRCOCTRL_TUNING_SHIFT));
-
-    val           &= (_CMU_HFRCOCTRL_TUNING_MASK >> _CMU_HFRCOCTRL_TUNING_SHIFT);
-    CMU->HFRCOCTRL = (CMU->HFRCOCTRL & ~(_CMU_HFRCOCTRL_TUNING_MASK)) |
-                     (val << _CMU_HFRCOCTRL_TUNING_SHIFT);
-    break;
-
-  case cmuOsc_AUXHFRCO:
-    EFM_ASSERT(val <= (_CMU_AUXHFRCOCTRL_TUNING_MASK >> _CMU_AUXHFRCOCTRL_TUNING_SHIFT));
-
-    val             <<= _CMU_AUXHFRCOCTRL_TUNING_SHIFT;
-    val              &= _CMU_AUXHFRCOCTRL_TUNING_MASK;
-    CMU->AUXHFRCOCTRL = (CMU->AUXHFRCOCTRL & ~(_CMU_AUXHFRCOCTRL_TUNING_MASK)) | val;
-    break;
-
-  default:
-    EFM_ASSERT(0);
-    break;
+    case cmuOsc_LFRCO:
+      EFM_ASSERT(val <= (_CMU_LFRCOCTRL_TUNING_MASK
+                         >> _CMU_LFRCOCTRL_TUNING_SHIFT));
+      val &= (_CMU_LFRCOCTRL_TUNING_MASK >> _CMU_LFRCOCTRL_TUNING_SHIFT);
+#if defined( _SILICON_LABS_32B_PLATFORM_2 )
+      while(BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_LFRCOBSY_SHIFT));
+#endif
+      CMU->LFRCOCTRL = (CMU->LFRCOCTRL & ~(_CMU_LFRCOCTRL_TUNING_MASK))
+                       | (val << _CMU_LFRCOCTRL_TUNING_SHIFT);
+      break;
+
+    case cmuOsc_HFRCO:
+      EFM_ASSERT(val <= (_CMU_HFRCOCTRL_TUNING_MASK
+                         >> _CMU_HFRCOCTRL_TUNING_SHIFT));
+      val &= (_CMU_HFRCOCTRL_TUNING_MASK >> _CMU_HFRCOCTRL_TUNING_SHIFT);
+#if defined( _SILICON_LABS_32B_PLATFORM_2 )
+      while(BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_HFRCOBSY_SHIFT))
+      {
+      }
+#endif
+      CMU->HFRCOCTRL = (CMU->HFRCOCTRL & ~(_CMU_HFRCOCTRL_TUNING_MASK))
+                       | (val << _CMU_HFRCOCTRL_TUNING_SHIFT);
+      break;
+
+    case cmuOsc_AUXHFRCO:
+      EFM_ASSERT(val <= (_CMU_AUXHFRCOCTRL_TUNING_MASK
+                         >> _CMU_AUXHFRCOCTRL_TUNING_SHIFT));
+      val &= (_CMU_AUXHFRCOCTRL_TUNING_MASK >> _CMU_AUXHFRCOCTRL_TUNING_SHIFT);
+#if defined( _SILICON_LABS_32B_PLATFORM_2 )
+      while(BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT))
+      {
+      }
+#endif
+      CMU->AUXHFRCOCTRL = (CMU->AUXHFRCOCTRL & ~(_CMU_AUXHFRCOCTRL_TUNING_MASK))
+                          | (val << _CMU_AUXHFRCOCTRL_TUNING_SHIFT);
+      break;
+
+    default:
+      EFM_ASSERT(0);
+      break;
   }
 }
 
@@ -2417,52 +3633,42 @@
  * @brief
  *   Determine if currently selected PCNTn clock used is external or LFBCLK.
  *
- * @param[in] inst
+ * @param[in] instance
  *   PCNT instance number to get currently selected clock source for.
  *
  * @return
  *   @li true - selected clock is external clock.
  *   @li false - selected clock is LFBCLK.
  *****************************************************************************/
-bool CMU_PCNTClockExternalGet(unsigned int inst)
+bool CMU_PCNTClockExternalGet(unsigned int instance)
 {
-  bool     ret;
   uint32_t setting;
 
-  switch (inst)
+  switch (instance)
   {
-#if defined(_CMU_PCNTCTRL_PCNT0CLKEN_MASK)
-  case 0:
-    setting = CMU->PCNTCTRL & CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0;
-    break;
-
-#if defined(_CMU_PCNTCTRL_PCNT1CLKEN_MASK)
-  case 1:
-    setting = CMU->PCNTCTRL & CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0;
-    break;
-
-#if defined(_CMU_PCNTCTRL_PCNT2CLKEN_MASK)
-  case 2:
-    setting = CMU->PCNTCTRL & CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0;
-    break;
+#if defined( _CMU_PCNTCTRL_PCNT0CLKEN_MASK )
+    case 0:
+      setting = CMU->PCNTCTRL & CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0;
+      break;
+
+#if defined( _CMU_PCNTCTRL_PCNT1CLKEN_MASK )
+    case 1:
+      setting = CMU->PCNTCTRL & CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0;
+      break;
+
+#if defined( _CMU_PCNTCTRL_PCNT2CLKEN_MASK )
+    case 2:
+      setting = CMU->PCNTCTRL & CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0;
+      break;
 #endif
 #endif
 #endif
 
-  default:
-    setting = 0;
-    break;
+    default:
+      setting = 0;
+      break;
   }
-
-  if (setting)
-  {
-    ret = true;
-  }
-  else
-  {
-    ret = false;
-  }
-  return ret;
+  return (setting ? true : false);
 }
 
 
@@ -2470,33 +3676,111 @@
  * @brief
  *   Select PCNTn clock.
  *
- * @param[in] inst
+ * @param[in] instance
  *   PCNT instance number to set selected clock source for.
  *
  * @param[in] external
  *   Set to true to select external clock, false to select LFBCLK.
  *****************************************************************************/
-void CMU_PCNTClockExternalSet(unsigned int inst, bool external)
+void CMU_PCNTClockExternalSet(unsigned int instance, bool external)
 {
-#if defined(PCNT_PRESENT)
+#if defined( PCNT_PRESENT )
   uint32_t setting = 0;
 
-  EFM_ASSERT(inst < PCNT_COUNT);
+  EFM_ASSERT(instance < PCNT_COUNT);
 
   if (external)
   {
     setting = 1;
   }
 
-  BITBAND_Peripheral(&(CMU->PCNTCTRL), (inst * 2) + 1, setting);
+  BUS_RegBitWrite(&(CMU->PCNTCTRL), (instance * 2) + 1, setting);
 
 #else
-  (void)inst;      /* Unused parameter */
+  (void)instance;  /* Unused parameter */
   (void)external;  /* Unused parameter */
 #endif
 }
 
 
+#if defined( _CMU_USHFRCOCONF_BAND_MASK )
+/***************************************************************************//**
+ * @brief
+ *   Get USHFRCO band in use.
+ *
+ * @return
+ *   USHFRCO band in use.
+ ******************************************************************************/
+CMU_USHFRCOBand_TypeDef CMU_USHFRCOBandGet(void)
+{
+  return (CMU_USHFRCOBand_TypeDef)((CMU->USHFRCOCONF
+                                    & _CMU_USHFRCOCONF_BAND_MASK)
+                                   >> _CMU_USHFRCOCONF_BAND_SHIFT);
+}
+#endif
+
+#if defined( _CMU_USHFRCOCONF_BAND_MASK )
+/***************************************************************************//**
+ * @brief
+ *   Set USHFRCO band to use.
+ *
+ * @param[in] band
+ *   USHFRCO band to activate.
+ ******************************************************************************/
+void CMU_USHFRCOBandSet(CMU_USHFRCOBand_TypeDef band)
+{
+  uint32_t           tuning;
+  uint32_t           fineTuning;
+  CMU_Select_TypeDef osc;
+
+  /* Cannot switch band if USHFRCO is already selected as HF clock. */
+  osc = CMU_ClockSelectGet(cmuClock_HF);
+  EFM_ASSERT((CMU_USHFRCOBandGet() != band) && (osc != cmuSelect_USHFRCO));
+
+  /* Read tuning value from calibration table */
+  switch (band)
+  {
+    case cmuUSHFRCOBand_24MHz:
+      tuning = (DEVINFO->USHFRCOCAL0 & _DEVINFO_USHFRCOCAL0_BAND24_TUNING_MASK)
+               >> _DEVINFO_USHFRCOCAL0_BAND24_TUNING_SHIFT;
+      fineTuning = (DEVINFO->USHFRCOCAL0
+                    & _DEVINFO_USHFRCOCAL0_BAND24_FINETUNING_MASK)
+                   >> _DEVINFO_USHFRCOCAL0_BAND24_FINETUNING_SHIFT;
+      break;
+
+    case cmuUSHFRCOBand_48MHz:
+      tuning = (DEVINFO->USHFRCOCAL0 & _DEVINFO_USHFRCOCAL0_BAND48_TUNING_MASK)
+               >> _DEVINFO_USHFRCOCAL0_BAND48_TUNING_SHIFT;
+      fineTuning = (DEVINFO->USHFRCOCAL0
+                    & _DEVINFO_USHFRCOCAL0_BAND48_FINETUNING_MASK)
+                   >> _DEVINFO_USHFRCOCAL0_BAND48_FINETUNING_SHIFT;
+      /* Enable the clock divider before switching the band from 24 to 48MHz */
+      BUS_RegBitWrite(&CMU->USHFRCOCONF, _CMU_USHFRCOCONF_USHFRCODIV2DIS_SHIFT, 0);
+      break;
+
+    default:
+      EFM_ASSERT(0);
+      return;
+  }
+
+  /* Set band and tuning */
+  CMU->USHFRCOCONF = (CMU->USHFRCOCONF & ~_CMU_USHFRCOCONF_BAND_MASK)
+                     | (band << _CMU_USHFRCOCONF_BAND_SHIFT);
+  CMU->USHFRCOCTRL = (CMU->USHFRCOCTRL & ~_CMU_USHFRCOCTRL_TUNING_MASK)
+                     | (tuning << _CMU_USHFRCOCTRL_TUNING_SHIFT);
+  CMU->USHFRCOTUNE = (CMU->USHFRCOTUNE & ~_CMU_USHFRCOTUNE_FINETUNING_MASK)
+                     | (fineTuning << _CMU_USHFRCOTUNE_FINETUNING_SHIFT);
+
+  /* Disable the clock divider after switching the band from 48 to 24MHz */
+  if (band == cmuUSHFRCOBand_24MHz)
+  {
+    BUS_RegBitWrite(&CMU->USHFRCOCONF, _CMU_USHFRCOCONF_USHFRCODIV2DIS_SHIFT, 1);
+  }
+}
+#endif
+
+
+
 /** @} (end addtogroup CMU) */
 /** @} (end addtogroup EM_Library) */
 #endif /* __EM_CMU_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_crc.c	Fri Jan 15 07:45:16 2016 +0000
@@ -0,0 +1,122 @@
+/***************************************************************************//**
+ * @file
+ * @brief Cyclic Redundancy Check (CRC) API.
+ * @version 4.2.1
+ *******************************************************************************
+ * @section License
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
+ *******************************************************************************
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
+ * obligation to support this Software. Silicon Labs is providing the
+ * Software "AS IS", with no express or implied warranties of any kind,
+ * including, but not limited to, any implied warranties of merchantability
+ * or fitness for any particular purpose or warranties against infringement
+ * of any proprietary rights of a third party.
+ *
+ * Silicon Labs will not be liable for any consequential, incidental, or
+ * special damages, or any other relief, or for any claim by any third party,
+ * arising from your use of this Software.
+ *
+ ******************************************************************************/
+
+#include "em_crc.h"
+#include "em_assert.h"
+
+#if defined(CRC_COUNT) && (CRC_COUNT > 0)
+
+/***************************************************************************//**
+ * @addtogroup EM_Library
+ * @{
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * @addtogroup CRC
+ * @{
+ ******************************************************************************/
+
+/*******************************************************************************
+ ********************************   ENUMS   ************************************
+ ******************************************************************************/
+
+
+/*******************************************************************************
+ *******************************   STRUCTS   ***********************************
+ ******************************************************************************/
+
+
+/*******************************************************************************
+ ***************************   GLOBAL FUNCTIONS   ******************************
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * @brief
+ *   Initialize the Cyclic Redundancy Check (CRC) module of EFR.
+ *
+ * @details
+ *   Use this function to configure the main operational parameters of the CRC
+ *   such as CRC bytes, number of valid input bits, input/output bit- and bit
+ *   order reversing.
+ *   Refer to EFR Reference Manual Chapter 14 and the configuration structure
+ *   CRC_Init_TypeDef for more details.
+ *
+ * @note
+ *   Internal notes:
+ *   - Initialize the CRC in the Init() function or let users use the separate
+ *   command function?
+ *
+ * @param[in] init
+ *   Pointer to initialization structure used to configure the CRC.
+ ******************************************************************************/
+void CRC_Init(CRC_Init_TypeDef const *init)
+{
+  /* Sanity check of bitsPerWord. */
+  EFM_ASSERT(init->bitsPerWord < 16U);
+
+  /* Set CRC control configuration parameters such as CRC width, byte and bit
+   * bit order, the number of bits per word, inverting input/output, etc. */
+  CRC->CTRL = (uint32_t)init->crcWidth
+              | (uint32_t)init->byteReverse
+              | (uint32_t)init->inputBitOrder
+              | (uint32_t)init->bitReverse
+              | ((uint32_t)init->bitsPerWord >> _CRC_CTRL_BITSPERWORD_SHIFT)
+              | ((uint32_t)init->inputPadding >> _CRC_CTRL_PADCRCINPUT_SHIFT)
+              | ((uint32_t)init->invInput >> _CRC_CTRL_INPUTINV_SHIFT)
+              | ((uint32_t)init->invOutput >> _CRC_CTRL_OUTPUTINV_SHIFT);
+
+  /* Set CRC polynomial value. */
+  CRC->POLY = init->crcPoly;
+
+  /* Load CRC initialization value to CRC_INIT. Please note, that the
+   * initialization is not performed here! */
+  CRC->INIT = init->initValue;
+}
+
+
+/***************************************************************************//**
+ * @brief
+ *   Reset CRC registers to the hardware reset state.
+ ******************************************************************************/
+void CRC_Reset(void)
+{
+  /* Reset CRC registers to their default value. */
+  CRC->CTRL = _CRC_CTRL_RESETVALUE;
+  CRC->POLY = _CRC_POLY_RESETVALUE;
+  CRC->INIT = _CRC_INIT_RESETVALUE;
+}
+
+
+/** @} (end addtogroup CRC) */
+/** @} (end addtogroup EM_Library) */
+
+#endif /* defined(CRC_COUNT) && (CRC_COUNT > 0) */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_cryotimer.c	Fri Jan 15 07:45:16 2016 +0000
@@ -0,0 +1,61 @@
+/***************************************************************************//**
+ * @file em_cryotimer.c
+ * @brief Ultra Low Energy Timer/Counter (CRYOTIMER) peripheral API
+ * @version 4.2.1
+ *******************************************************************************
+ * @section License
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
+ *******************************************************************************
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software.@n
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.@n
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
+ * obligation to support this Software. Silicon Labs is providing the
+ * Software "AS IS", with no express or implied warranties of any kind,
+ * including, but not limited to, any implied warranties of merchantability
+ * or fitness for any particular purpose or warranties against infringement
+ * of any proprietary rights of a third party.
+ *
+ * Silicon Labs will not be liable for any consequential, incidental, or
+ * special damages, or any other relief, or for any claim by any third party,
+ * arising from your use of this Software.
+ *
+ ******************************************************************************/
+
+#include "em_cryotimer.h"
+#include "em_bus.h"
+
+#if defined(CRYOTIMER_PRESENT) && (CRYOTIMER_COUNT == 1)
+
+/***************************************************************************//**
+ * @brief
+ *   Initialize the CRYOTIMER.
+ *
+ * @details
+ *   Use this function to initialize the CRYOTIMER.
+ *   Select prescaler setting and select low frequency oscillator.
+ *   Refer to the configuration structure @ref CRYOTIMER_Init_TypeDef for more
+ *   details.
+ *
+ * @param[in] init
+ *   Pointer to initialization structure.
+ ******************************************************************************/
+void CRYOTIMER_Init(const CRYOTIMER_Init_TypeDef *init)
+{
+  CRYOTIMER->PERIODSEL = (uint32_t)init->period & _CRYOTIMER_PERIODSEL_MASK;
+  CRYOTIMER->CTRL = ((uint32_t)init->enable << _CRYOTIMER_CTRL_EN_SHIFT)
+                  | ((uint32_t)init->debugRun << _CRYOTIMER_CTRL_DEBUGRUN_SHIFT)
+                  | ((uint32_t)init->osc << _CRYOTIMER_CTRL_OSCSEL_SHIFT)
+                  | ((uint32_t)init->presc << _CRYOTIMER_CTRL_PRESC_SHIFT);
+  CRYOTIMER_EM4WakeupEnable(init->em4Wakeup);
+}
+
+#endif /* defined(CRYOTIMER_PRESENT) && (CRYOTIMER_COUNT > 0) */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_crypto.c	Fri Jan 15 07:45:16 2016 +0000
@@ -0,0 +1,1847 @@
+/***************************************************************************//**
+ * @file em_crypto.c
+ * @brief Cryptography accelerator peripheral API
+ * @version 4.2.1
+ *******************************************************************************
+ * @section License
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
+ *******************************************************************************
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software.@n
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.@n
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
+ * obligation to support this Software. Silicon Labs is providing the
+ * Software "AS IS", with no express or implied warranties of any kind,
+ * including, but not limited to, any implied warranties of merchantability
+ * or fitness for any particular purpose or warranties against infringement
+ * of any proprietary rights of a third party.
+ *
+ * Silicon Labs will not be liable for any consequential, incidental, or
+ * special damages, or any other relief, or for any claim by any third party,
+ * arising from your use of this Software.
+ *
+ ******************************************************************************/
+#include "em_device.h"
+
+#if defined(CRYPTO_COUNT) && (CRYPTO_COUNT > 0)
+
+#include "em_crypto.h"
+#include "em_assert.h"
+#include "em_bitband.h"
+
+/***************************************************************************//**
+ * @addtogroup EM_Library
+ * @{
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * @addtogroup CRYPTO
+ *
+ * @brief Cryptography accelerator peripheral API
+ *
+ * @details
+ *   This API is intended for use on Silicon Labs target devices, and provides
+ *   a thin software interface for the functions of the crypto module, including
+ *   @li AES (Advanced Encryption Standard) @ref crypto_aes
+ *   @li SHA (Secure Hash Algorithm) @ref crypto_sha
+ *   @li Big Integer multiplier @ref crypto_mul
+ *   @li Functions for loading data and executing instruction sequences @ref crypto_exec
+ *
+ *   @n @section crypto_aes AES
+ *   The AES APIs include support for AES-128 and AES-256 with block cipher
+ *   modes:
+ *   @li CBC - Cipher Block Chaining mode
+ *   @li CFB - Cipher Feedback mode
+ *   @li CTR - Counter mode
+ *   @li ECB - Electronic Code Book mode
+ *   @li OFB - Output Feedback mode
+ *
+ *   For the AES APIs Input/output data (plaintext, ciphertext, key etc) are
+ *   treated as byte arrays, starting with most significant byte. Ie, 32 bytes
+ *   of plaintext (B0...B31) is located in memory in the same order, with B0 at
+ *   the lower address and B31 at the higher address.
+ *
+ *   Byte arrays must always be a multiple of AES block size, ie. a multiple
+ *   of 16. Padding, if required, is done at the end of the byte array.
+ *
+ *   Byte arrays should be word (32 bit) aligned for performance
+ *   considerations, since the array is accessed with 32 bit access type.
+ *   The core MCUs supports unaligned accesses, but with a performance penalty.
+ *
+ *   It is possible to specify the same output buffer as input buffer as long
+ *   as they point to the same address. In that case the provided input buffer
+ *   is replaced with the encrypted/decrypted output. Notice that the buffers
+ *   must be exactly overlapping. If partly overlapping, the behavior is
+ *   undefined.
+ *
+ *   It is up to the user to use a cipher mode according to its requirements
+ *   in order to not break security. Please refer to specific cipher mode
+ *   theory for details.
+ *
+ *   References:
+ *   @li Wikipedia - Cipher modes, http://en.wikipedia.org/wiki/Cipher_modes
+ *
+ *   @li Recommendation for Block Cipher Modes of Operation,
+ *      NIST Special Publication 800-38A, 2001 Edition,
+ *      http://csrc.nist.gov/publications/nistpubs/800-38a/sp800-38a.pdf
+ *
+ *   @li Recommendation for Block Cipher Modes of Operation,
+ *      http://csrc.nist.gov/publications/fips/fips180-4/fips-180-4.pdf
+ *
+ *   @n @section crypto_sha SHA
+ *   The SHA APIs include support for 
+ *   @li SHA-1 @ref CRYPTO_SHA_1
+ *   @li SHA-256 @ref CRYPTO_SHA_256
+ *
+ *   The SHA-1 implementation is FIPS-180-1 compliant, ref:
+ *   @li Wikipedia -  SHA-1, https://en.wikipedia.org/wiki/SHA-1
+ *   @li SHA-1 spec - http://www.itl.nist.gov/fipspubs/fip180-1.htm
+ *
+ *   The SHA-256 implementation is FIPS-180-2 compliant, ref:
+ *   @li Wikipedia -  SHA-2, https://en.wikipedia.org/wiki/SHA-2
+ *   @li SHA-2 spec - http://csrc.nist.gov/publications/fips/fips180-2/fips180-2.pdf
+ *
+ *   @n @section crypto_mul CRYPTO_Mul
+ *   @ref CRYPTO_Mul is a function for multiplying big integers that are
+ *   bigger than the operand size of the MUL instruction which is 128 bits.
+ *   CRYPTO_Mul multiplies all partial operands of the input operands using
+ *   MUL to form a resulting number which may be twice the size of
+ *   the operands.
+ *
+ *   CRPYTO_Mul is typically used by RSA implementations which perform a
+ *   huge amount of multiplication and square operations in order to
+ *   implement modular exponentiation.
+ *   Some RSA implementations use a number representation including arrays
+ *   of 32bit words of variable size. The user should compile with
+ *   -D USE_VARIABLE_SIZED_DATA_LOADS in order to load these numbers
+ *   directly into CRYPTO without converting the number representation.
+ *
+ *   @n @section crypto_exec Load and Execute Instruction Sequences
+ *   The functions for loading data and executing instruction sequences can
+ *   be used to implement complex algorithms like elliptic curve cryptography
+ *   (ECC)) and authenticated encryption algorithms. There are two typical
+ *   modes of operation:
+ *   @li Multi sequence operation
+ *   @li Single static instruction sequence operation
+ *
+ *   In multi sequence mode the software starts by loading input data, then
+ *   an instruction sequence, execute, and finally read the result. This
+ *   process is repeated until the full crypto operation is complete.
+ *
+ *   When using a single static instruction sequence, there is just one
+ *   instruction sequence which is loaded initially. The sequence can be setup
+ *   to run multiple times. The data can be loaded during the execution of the
+ *   sequence by using DMA, BUFC and/or programmed I/O directly from the MCU
+ *   core. For details on how to program the instruction sequences please refer
+ *   to the reference manual of the particular Silicon Labs device.
+ *
+ *   In order to load input data to the CRYPTO module use any of the following
+ *   functions:
+ *   @li @ref CRYPTO_DataWrite  - Write 128 bits to a DATA register.
+ *   @li @ref CRYPTO_DDataWrite - Write 256 bits to a DDATA register.
+ *   @li @ref CRYPTO_QDataWrite - Write 512 bits to a QDATA register.
+ *
+ *   In order to read output data from the CRYPTO module use any of the
+ *   following functions:
+ *   @li @ref CRYPTO_DataRead  - Read 128 bits from a DATA register.
+ *   @li @ref CRYPTO_DDataRead - Read 256 bits from a DDATA register.
+ *   @li @ref CRYPTO_QDataRead - Read 512 bits from a QDATA register.
+ *
+ *   In order to load an instruction sequence to the CRYPTO module use
+ *   @ref CRYPTO_InstructionSequenceLoad.
+ *
+ *   In order to execute the current instruction sequence in the CRYPTO module
+ *   use @ref CRYPTO_InstructionSequenceExecute.
+ *
+ *   In order to check whether an instruction sequence has completed
+ *   use @ref CRYPTO_InstructionSequenceDone.
+ *
+ *   In order to wait for an instruction sequence to complete
+ *   use @ref CRYPTO_InstructionSequenceWait.
+ *
+ *   In order to optimally load (with regards to speed) and execute an
+ *   instruction sequence use any of the CRYPTO_EXECUTE_X macros (where X is
+ *   in the range 1-20) defined in @ref em_crypto.h. E.g. CRYPTO_EXECUTE_19.
+ * @{
+ ******************************************************************************/
+
+/*******************************************************************************
+ *******************************   DEFINES   ***********************************
+ ******************************************************************************/
+
+/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
+
+#define CRYPTO_INSTRUCTIONS_PER_REG              (4)
+#define CRYPTO_INSTRUCTIONS_MAX                  (12)
+#define CRYPTO_INSTRUCTION_REGS                  (CRYPTO_INSTRUCTIONS_MAX/CRYPTO_INSTRUCTIONS_PER_REG)
+
+#define CRYPTO_SHA1_BLOCK_SIZE_IN_BITS           (512)
+#define CRYPTO_SHA1_BLOCK_SIZE_IN_BYTES          (CRYPTO_SHA1_BLOCK_SIZE_IN_BITS/8)
+#define CRYPTO_SHA1_BLOCK_SIZE_IN_32BIT_WORDS    (CRYPTO_SHA1_BLOCK_SIZE_IN_BYTES/sizeof(uint32_t))
+#define CRYPTO_SHA1_DIGEST_SIZE_IN_32BIT_WORDS   (CRYPTO_SHA1_DIGEST_SIZE_IN_BYTES/sizeof(uint32_t))
+
+#define CRYPTO_SHA256_BLOCK_SIZE_IN_BITS         (512)
+#define CRYPTO_SHA256_BLOCK_SIZE_IN_BYTES        (CRYPTO_SHA256_BLOCK_SIZE_IN_BITS/8)
+#define CRYPTO_SHA256_BLOCK_SIZE_IN_32BIT_WORDS  (CRYPTO_SHA256_BLOCK_SIZE_IN_BYTES/sizeof(uint32_t))
+
+#define CRYPTO_SHA256_DIGEST_SIZE_IN_32BIT_WORDS (CRYPTO_SHA256_DIGEST_SIZE_IN_BYTES/sizeof(uint32_t))
+
+#define PARTIAL_OPERAND_WIDTH_LOG2               (7)  /* 2^7 = 128 */
+#define PARTIAL_OPERAND_WIDTH                    (1<<PARTIAL_OPERAND_WIDTH_LOG2)
+#define PARTIAL_OPERAND_WIDTH_MASK               (PARTIAL_OPERAND_WIDTH-1)
+#define PARTIAL_OPERAND_WIDTH_IN_BYTES           (PARTIAL_OPERAND_WIDTH/8)
+#define PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS     (PARTIAL_OPERAND_WIDTH_IN_BYTES/sizeof(uint32_t))
+
+#define SWAP32(x)                                (__REV(x))
+
+#define CRYPTO_AES_BLOCKSIZE                     (16)
+
+/*******************************************************************************
+ ***********************   STATIC FUNCTIONS   **********************************
+ ******************************************************************************/
+
+static inline void CRYPTO_AES_ProcessLoop(uint32_t len,
+                                          CRYPTO_DataReg_TypeDef inReg,
+                                          uint32_t * in,
+                                          CRYPTO_DataReg_TypeDef outReg,
+                                          uint32_t * out);
+
+static void CRYPTO_AES_CBCx(uint8_t * out,
+                            const uint8_t * in,
+                            unsigned int len,
+                            const uint8_t * key,
+                            const uint8_t * iv,
+                            bool encrypt,
+                            CRYPTO_KeyWidth_TypeDef keyWidth);
+
+static void CRYPTO_AES_CFBx(uint8_t * out,
+                            const uint8_t * in,
+                            unsigned int len,
+                            const uint8_t * key,
+                            const uint8_t * iv,
+                            bool encrypt,
+                            CRYPTO_KeyWidth_TypeDef keyWidth);
+
+static void CRYPTO_AES_CTRx(uint8_t * out,
+                            const uint8_t * in,
+                            unsigned int len,
+                            const uint8_t * key,
+                            uint8_t * ctr,
+                            CRYPTO_AES_CtrFuncPtr_TypeDef ctrFunc,
+                            CRYPTO_KeyWidth_TypeDef keyWidth);
+
+static void CRYPTO_AES_ECBx(uint8_t * out,
+                            const uint8_t * in,
+                            unsigned int len,
+                            const uint8_t * key,
+                            bool encrypt,
+                            CRYPTO_KeyWidth_TypeDef keyWidth);
+
+static void CRYPTO_AES_OFBx(uint8_t * out,
+                            const uint8_t * in,
+                            unsigned int len,
+                            const uint8_t * key,
+                            const uint8_t * iv,
+                            CRYPTO_KeyWidth_TypeDef keyWidth);
+
+#ifdef USE_VARIABLE_SIZED_DATA_LOADS
+/***************************************************************************//**
+ * @brief
+ *   Write variable sized 32 bit data array (max 128 bits) to a DATAX register
+ *
+ * @details
+ *   Write variable sized 32 bit array (max 128 bits / 4 words) to a DATAX
+ *   register in the CRYPTO module.
+ *
+ * @param[in]  dataReg    The 128 bits DATA register.
+ * @param[in]  val        Value of the data to write to the DATA register.
+ * @param[in]  valSize    Size of @ref val in number of 32bit words.
+ ******************************************************************************/
+__STATIC_INLINE
+void CRYPTO_DataWriteVariableSize(CRYPTO_DataReg_TypeDef    dataReg,
+                                  const CRYPTO_Data_TypeDef val,
+                                  int                       valSize)
+{
+  int i;
+  volatile uint32_t * reg = (volatile uint32_t *) dataReg;
+  
+  if (valSize < 4)
+  {
+    /* Non optimal write of data. */
+    for (i = 0; i < valSize; i++)
+      *reg = *val++;
+    for (; i < 4; i++)
+      *reg = 0;
+  }
+  else
+  {
+    CRYPTO_BurstToCrypto(reg, &val[0]);
+  }
+}
+#endif
+
+/** @endcond */
+
+/*******************************************************************************
+ **************************   GLOBAL FUNCTIONS   *******************************
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * @brief
+ *   Set the modulus type used for wide arithmetic operations.
+ *
+ * @details
+ *   This function sets the modulus type to be used by the Modulus instructions
+ *   of the CRYPTO module.
+ *
+ * @param[in]  modType  Modulus type.
+ ******************************************************************************/
+void CRYPTO_ModulusSet(CRYPTO_ModulusType_TypeDef modType)
+{
+  uint32_t temp = CRYPTO->WAC & (~(_CRYPTO_WAC_MODULUS_MASK | _CRYPTO_WAC_MODOP_MASK));
+
+  switch (modType)
+  {
+    case cryptoModulusBin256:
+    case cryptoModulusBin128:
+    case cryptoModulusGcmBin128:
+    case cryptoModulusEccB233:
+    case cryptoModulusEccB163:
+#ifdef _CRYPTO_WAC_MODULUS_ECCBIN233N
+    case cryptoModulusEccB233Order:
+    case cryptoModulusEccB233KOrder:
+    case cryptoModulusEccB163Order:
+    case cryptoModulusEccB163KOrder:
+#endif
+      CRYPTO->WAC = temp | modType | CRYPTO_WAC_MODOP_BINARY;
+      break;
+
+    case cryptoModulusEccP256:
+    case cryptoModulusEccP224:
+    case cryptoModulusEccP192:
+#ifdef _CRYPTO_WAC_MODULUS_ECCPRIME256P
+    case cryptoModulusEccP256Order:
+    case cryptoModulusEccP224Order:
+    case cryptoModulusEccP192Order:
+#endif
+      CRYPTO->WAC = temp | modType | CRYPTO_WAC_MODOP_REGULAR;
+      break;
+
+    default:
+      /* Unknown modulus type. */
+      EFM_ASSERT(0);
+  }
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Read the key value currently used by the CRYPTO module.
+ *
+ * @details
+ *   Read 128 bits or 256 bits from KEY register in the CRYPTO module.
+ *
+ * @param[in]  val     Value of the data to write to the KEYBUF register.
+ * @param[in]  keyWidth Key width - 128 or 256 bits
+ ******************************************************************************/
+void CRYPTO_KeyRead(CRYPTO_KeyBuf_TypeDef    val,
+                    CRYPTO_KeyWidth_TypeDef  keyWidth)
+{
+  EFM_ASSERT(val);
+
+  CRYPTO_BurstFromCrypto(&CRYPTO->KEY, &val[0]);
+  if (keyWidth == cryptoKey256Bits)
+  {
+    CRYPTO_BurstFromCrypto(&CRYPTO->KEY, &val[4]);
+  }
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Perform a SHA-1 hash operation on a message.
+ *
+ * @details
+ *   This function performs a SHA-1 hash operation on the message specified by
+ *   msg with length msgLen, and returns the message digest in msgDigest.
+ *
+ * @param[in]  msg        Message to hash.
+ * @param[in]  msgLen     Length of message in bytes.
+ * @param[out] msgDigest  Message digest.
+ ******************************************************************************/
+void CRYPTO_SHA_1(const uint8_t *              msg,
+                  uint64_t                     msgLen,
+                  CRYPTO_SHA1_Digest_TypeDef   msgDigest)
+{
+  uint32_t  temp;
+  int       len;
+  int       blockLen;
+  uint32_t  shaBlock[CRYPTO_SHA1_BLOCK_SIZE_IN_32BIT_WORDS]=
+  {
+    /* Initial value */
+    0x67452301, 0xefcdab89, 0x98badcfe, 0x10325476, 0xc3d2e1f0
+  };
+  uint8_t * p8ShaBlock = (uint8_t *) shaBlock;
+
+  /* Initialize crypto module to do SHA-1. */
+  CRYPTO->CTRL     = CRYPTO_CTRL_SHA_SHA1;
+  CRYPTO->SEQCTRL  = 0;
+  CRYPTO->SEQCTRLB = 0;
+
+  /* Set result width of MADD32 operation. */
+  CRYPTO_ResultWidthSet(cryptoResult256Bits);
+  
+  /* Write init value to DDATA1.  */
+  CRYPTO_DDataWrite(cryptoRegDDATA1, shaBlock);
+
+  /* Copy data to DDATA0 and select DDATA0 and DDATA1 for SHA operation. */
+  CRYPTO_EXECUTE_2(CRYPTO_CMD_INSTR_DDATA1TODDATA0,
+                   CRYPTO_CMD_INSTR_SELDDATA0DDATA1);
+
+  len = msgLen;
+
+  while (len >= CRYPTO_SHA1_BLOCK_SIZE_IN_BYTES)
+  {
+    /* Write block to QDATA1.  */
+    CRYPTO_QDataWrite(cryptoRegQDATA1BIG, (uint32_t *) msg);
+
+    /* Execute SHA */
+    CRYPTO_EXECUTE_3(CRYPTO_CMD_INSTR_SHA,
+                     CRYPTO_CMD_INSTR_MADD32,
+                     CRYPTO_CMD_INSTR_DDATA0TODDATA1);
+
+    len -= CRYPTO_SHA1_BLOCK_SIZE_IN_BYTES;
+    msg += CRYPTO_SHA1_BLOCK_SIZE_IN_BYTES;
+  }
+
+  blockLen = 0;
+
+  /* Build the last (or second to last) block */
+  for (; len; len--)
+    p8ShaBlock[blockLen++] = *msg++;
+
+  /* append the '1' bit */
+  p8ShaBlock[blockLen++] = 0x80;
+
+  /* if the length is currently above 56 bytes we append zeros
+   * then compress.  Then we can fall back to padding zeros and length
+   * encoding like normal.
+   */
+  if (blockLen > 56)
+  {
+    while (blockLen < 64)
+      p8ShaBlock[blockLen++] = 0;
+
+    /* Write block to QDATA1BIG. */
+    CRYPTO_QDataWrite(cryptoRegQDATA1BIG, shaBlock);
+
+    /* Execute SHA */
+    CRYPTO_EXECUTE_3(CRYPTO_CMD_INSTR_SHA,
+                     CRYPTO_CMD_INSTR_MADD32,
+                     CRYPTO_CMD_INSTR_DDATA0TODDATA1);
+    blockLen = 0;
+  }
+
+  /* pad upto 56 bytes of zeroes */
+  while (blockLen < 56)
+    p8ShaBlock[blockLen++] = 0;
+
+  /* And finally, encode the message length. */
+  {
+    uint64_t msgLenInBits = msgLen << 3;
+    temp = msgLenInBits >> 32;
+    *(uint32_t*)&p8ShaBlock[56] = SWAP32(temp);
+    temp = msgLenInBits & 0xFFFFFFFF;
+    *(uint32_t*)&p8ShaBlock[60] = SWAP32(temp);
+  }
+
+  /* Write block to QDATA1BIG. */
+  CRYPTO_QDataWrite(cryptoRegQDATA1BIG, shaBlock);
+
+  /* Execute SHA */
+  CRYPTO_EXECUTE_3(CRYPTO_CMD_INSTR_SHA,
+                   CRYPTO_CMD_INSTR_MADD32,
+                   CRYPTO_CMD_INSTR_DDATA0TODDATA1);
+
+  /* Read resulting message digest from DDATA0BIG.  */
+  ((uint32_t*)msgDigest)[0] = CRYPTO->DDATA0BIG;
+  ((uint32_t*)msgDigest)[1] = CRYPTO->DDATA0BIG;
+  ((uint32_t*)msgDigest)[2] = CRYPTO->DDATA0BIG;
+  ((uint32_t*)msgDigest)[3] = CRYPTO->DDATA0BIG;
+  ((uint32_t*)msgDigest)[4] = CRYPTO->DDATA0BIG;
+  temp = CRYPTO->DDATA0BIG;
+  temp = CRYPTO->DDATA0BIG;
+  temp = CRYPTO->DDATA0BIG;
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Perform a SHA-256 hash operation on a message.
+ *
+ * @details
+ *   This function performs a SHA-256 hash operation on the message specified
+ *   by msg with length msgLen, and returns the message digest in msgDigest.
+ *
+ * @param[in]  msg        Message to hash.
+ * @param[in]  msgLen     Length of message in bytes.
+ * @param[out] msgDigest  Message digest.
+ ******************************************************************************/
+void CRYPTO_SHA_256(const uint8_t *              msg,
+                    uint64_t                     msgLen,
+                    CRYPTO_SHA256_Digest_TypeDef msgDigest)
+{
+  uint32_t  temp;
+  int       len;
+  int       blockLen;
+  uint32_t  shaBlock[CRYPTO_SHA256_BLOCK_SIZE_IN_32BIT_WORDS]=
+  {
+    /* Initial value */
+    0x6a09e667, 0xbb67ae85, 0x3c6ef372, 0xa54ff53a,
+    0x510e527f, 0x9b05688c, 0x1f83d9ab, 0x5be0cd19
+  };
+  uint8_t * p8ShaBlock = (uint8_t *) shaBlock;
+
+  /* Initialize crypyo module to do SHA-256 (SHA-2). */
+  CRYPTO->CTRL     = CRYPTO_CTRL_SHA_SHA2;
+  CRYPTO->SEQCTRL  = 0;
+  CRYPTO->SEQCTRLB = 0;
+
+  /* Set result width of MADD32 operation. */
+  CRYPTO_ResultWidthSet(cryptoResult256Bits);
+
+  /* Write init value to DDATA1.  */
+  CRYPTO_DDataWrite(cryptoRegDDATA1, shaBlock);
+
+  /* Copy data ot DDATA0 and select DDATA0 and DDATA1 for SHA operation. */
+  CRYPTO_EXECUTE_2(CRYPTO_CMD_INSTR_DDATA1TODDATA0,
+                   CRYPTO_CMD_INSTR_SELDDATA0DDATA1);
+  len = msgLen;
+
+  while (len >= CRYPTO_SHA256_BLOCK_SIZE_IN_BYTES)
+  {
+    /* Write block to QDATA1BIG.  */
+    CRYPTO_QDataWrite(cryptoRegQDATA1BIG, (uint32_t *) msg);
+
+    /* Execute SHA */
+    CRYPTO_EXECUTE_3(CRYPTO_CMD_INSTR_SHA,
+                     CRYPTO_CMD_INSTR_MADD32,
+                     CRYPTO_CMD_INSTR_DDATA0TODDATA1);
+
+    len -= CRYPTO_SHA256_BLOCK_SIZE_IN_BYTES;
+    msg += CRYPTO_SHA256_BLOCK_SIZE_IN_BYTES;
+  }
+
+  blockLen = 0;
+
+  /* Build the last (or second to last) block */
+  for (; len; len--)
+    p8ShaBlock[blockLen++] = *msg++;
+
+  /* append the '1' bit */
+  p8ShaBlock[blockLen++] = 0x80;
+
+  /* if the length is currently above 56 bytes we append zeros
+   * then compress.  Then we can fall back to padding zeros and length
+   * encoding like normal.
+   */
+  if (blockLen > 56)
+  {
+    while (blockLen < 64)
+      p8ShaBlock[blockLen++] = 0;
+
+    /* Write block to QDATA1BIG. */
+    CRYPTO_QDataWrite(cryptoRegQDATA1BIG, shaBlock);
+
+    /* Execute SHA */
+    CRYPTO_EXECUTE_3(CRYPTO_CMD_INSTR_SHA,
+                     CRYPTO_CMD_INSTR_MADD32,
+                     CRYPTO_CMD_INSTR_DDATA0TODDATA1);
+    blockLen = 0;
+  }
+
+  /* Pad upto 56 bytes of zeroes */
+  while (blockLen < 56)
+    p8ShaBlock[blockLen++] = 0;
+
+  /* And finally, encode the message length. */
+  {
+    uint64_t msgLenInBits = msgLen << 3;
+    temp = msgLenInBits >> 32;
+    *(uint32_t *)&p8ShaBlock[56] = SWAP32(temp);
+    temp = msgLenInBits & 0xFFFFFFFF;
+    *(uint32_t *)&p8ShaBlock[60] = SWAP32(temp);
+  }
+
+  /* Write the final block to QDATA1BIG. */
+  CRYPTO_QDataWrite(cryptoRegQDATA1BIG, shaBlock);
+
+  /* Execute SHA */
+  CRYPTO_EXECUTE_3(CRYPTO_CMD_INSTR_SHA,
+                   CRYPTO_CMD_INSTR_MADD32,
+                   CRYPTO_CMD_INSTR_DDATA0TODDATA1);
+
+  /* Read resulting message digest from DDATA0BIG.  */
+  CRYPTO_DDataRead(cryptoRegDDATA0BIG, (uint32_t *)msgDigest);
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Set 32bit word array to zero.
+ *
+ * @param[in]  words32bits    Pointer to 32bit word array
+ * @param[in]  num32bitWords  Number of 32bit words in array
+ ******************************************************************************/
+__STATIC_INLINE void cryptoBigintZeroize(uint32_t * words32bits,
+                                         int        num32bitWords)
+{
+  while (num32bitWords--)
+    *words32bits++ = 0;
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Increment value of 32bit word array by one.
+ *
+ * @param[in] words32bits    Pointer to 32bit word array
+ * @param[in] num32bitWords  Number of 32bit words in array
+ ******************************************************************************/
+__STATIC_INLINE void cryptoBigintIncrement(uint32_t * words32bits,
+                                           int        num32bitWords)
+{
+  int i;
+  for (i=0; i<num32bitWords; i++)
+    if (++words32bits[i] != 0)
+      break;
+  return;
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Multiply two big integers.
+ *
+ * @details
+ *   This function uses the CRYPTO unit to multiply two big integer operands.
+ *   If USE_VARIABLE_SIZED_DATA_LOADS is defined, the sizes of the operands
+ *   may be any multiple of 32 bits. If USE_VARIABLE_SIZED_DATA_LOADS is _not_
+ *   defined, the sizes of the operands must be a multiple of 128 bits.
+ *
+ * @param[in]  A        operand A
+ * @param[in]  aSize    size of operand A in bits
+ * @param[in]  B        operand B
+ * @param[in]  bSize    size of operand B in bits
+ * @param[out] R        result of multiplication
+ * @param[in]  rSize    size of result buffer R in bits
+ ******************************************************************************/
+void CRYPTO_Mul(uint32_t * A, int aSize,
+                uint32_t * B, int bSize,
+                uint32_t * R, int rSize)
+{
+  int i, j;
+
+  /****************   Initializations   ******************/
+
+#ifdef USE_VARIABLE_SIZED_DATA_LOADS
+  int numWordsLastOperandA = (aSize&PARTIAL_OPERAND_WIDTH_MASK)>>5;
+  int numPartialOperandsA = numWordsLastOperandA ?
+    (aSize >> PARTIAL_OPERAND_WIDTH_LOG2) + 1 :
+    aSize >> PARTIAL_OPERAND_WIDTH_LOG2;
+  int numWordsLastOperandB = (bSize&PARTIAL_OPERAND_WIDTH_MASK)>>5;
+  int numPartialOperandsB = numWordsLastOperandB ?
+    (bSize >> PARTIAL_OPERAND_WIDTH_LOG2) + 1 :
+    bSize >> PARTIAL_OPERAND_WIDTH_LOG2;
+  int numWordsLastOperandR = (rSize&PARTIAL_OPERAND_WIDTH_MASK)>>5;
+  int numPartialOperandsR = numWordsLastOperandR ?
+    (rSize >> PARTIAL_OPERAND_WIDTH_LOG2) + 1 :
+    rSize >> PARTIAL_OPERAND_WIDTH_LOG2;
+  EFM_ASSERT(numPartialOperandsA + numPartialOperandsB <= numPartialOperandsR);
+#else
+  int      numPartialOperandsA = aSize >> PARTIAL_OPERAND_WIDTH_LOG2;
+  int      numPartialOperandsB = bSize >> PARTIAL_OPERAND_WIDTH_LOG2;
+  EFM_ASSERT((aSize & PARTIAL_OPERAND_WIDTH_MASK) == 0);
+  EFM_ASSERT((bSize & PARTIAL_OPERAND_WIDTH_MASK) == 0);
+#endif
+  EFM_ASSERT(aSize + bSize <= rSize);
+  
+  /* Set R to zero. */
+  cryptoBigintZeroize(R, rSize >> 5);
+
+  /* Set multiplication width. */
+  CRYPTO->WAC = CRYPTO_WAC_MULWIDTH_MUL128 | CRYPTO_WAC_RESULTWIDTH_256BIT;
+
+  /* Setup DMA request signalling in order for MCU to run in parallel with
+     CRYPTO instruction sequence execution, and prepare data loading which
+     can take place immediately when CRYPTO is ready inside the instruction
+     sequence. */
+  CRYPTO->CTRL =
+    CRYPTO_CTRL_DMA0RSEL_DATA0 | CRYPTO_CTRL_DMA0MODE_FULL |
+    CRYPTO_CTRL_DMA1RSEL_DATA1 | CRYPTO_CTRL_DMA1MODE_FULL;
+
+  CRYPTO_EXECUTE_4(
+                   CRYPTO_CMD_INSTR_CCLR,    /* Carry = 0 */
+                   CRYPTO_CMD_INSTR_CLR,     /* DDATA0 = 0 */
+                   /* clear result accumulation register */
+                   CRYPTO_CMD_INSTR_DDATA0TODDATA2,
+                   CRYPTO_CMD_INSTR_SELDDATA1DDATA3);
+  /*
+  register map:
+  DDATA0: working register
+  DDATA1: B(j)
+  DDATA2: R(i+j+1) and R(i+j), combined with DMA entry for B(j)
+  DDATA3: A(i)
+  */
+
+  CRYPTO_SEQ_LOAD_10(
+                     /* Temporarily load partial operand B(j) to DATA0. */
+                     /* R(i+j+1) is still in DATA1 */
+                     CRYPTO_CMD_INSTR_DMA0TODATA,
+                     /* Move B(j) to DDATA1 */
+                     CRYPTO_CMD_INSTR_DDATA2TODDATA1,
+
+                     /* Restore previous partial result (now R(i+j)) */
+                     CRYPTO_CMD_INSTR_DATA1TODATA0,
+
+                     /* Load next partial result R(i+j+1) */
+                     CRYPTO_CMD_INSTR_DMA1TODATA,
+
+                     /* Execute partial multiplication A(i)inDDATA1 * B(j)inDDATA3*/
+                     CRYPTO_CMD_INSTR_MULO,
+
+                     /* Add the result to the previous partial result */
+                     /* AND take the previous carry value into account */
+                     /* at the right place (bit 128, ADDIC instruction */
+                     CRYPTO_CMD_INSTR_SELDDATA0DDATA2,
+                     CRYPTO_CMD_INSTR_ADDIC,
+
+                     /* Save the new partial result (lower half) */
+                     CRYPTO_CMD_INSTR_DDATA0TODDATA2,
+                     CRYPTO_CMD_INSTR_DATATODMA0,
+                     /* Reset the operand selector for next*/
+                     CRYPTO_CMD_INSTR_SELDDATA2DDATA3
+                     );
+
+  /****************   End Initializations   ******************/
+
+  for(i=0; i<numPartialOperandsA; i++)
+  {
+    /* Load partial operand #1 A>>(i*PARTIAL_OPERAND_WIDTH) to DDATA1. */
+#ifdef USE_VARIABLE_SIZED_DATA_LOADS
+    if ( (numWordsLastOperandA != 0) && ( i == numPartialOperandsA-1 ) )
+      CRYPTO_DataWriteVariableSize(cryptoRegDATA2,
+                                   &A[i*PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS],
+                                   numWordsLastOperandA);
+    else
+      CRYPTO_DataWrite(cryptoRegDATA2, &A[i*PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS]);
+#else
+    CRYPTO_DataWrite(cryptoRegDATA2, &A[i*PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS]);
+#endif
+
+    /* Load partial result in R>>(i*PARTIAL_OPERAND_WIDTH) to DATA1. */
+#ifdef USE_VARIABLE_SIZED_DATA_LOADS
+    if ( (numWordsLastOperandR != 0) && ( i == numPartialOperandsR-1 ) )
+      CRYPTO_DataWriteVariableSize(cryptoRegDATA1,
+                                   &R[i*PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS],
+                                   numWordsLastOperandR);
+    else
+      CRYPTO_DataWrite(cryptoRegDATA1, &R[i*PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS]);
+#else
+    CRYPTO_DataWrite(cryptoRegDATA1, &R[i*PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS]);
+#endif
+    
+    /* Clear carry */
+    CRYPTO->CMD = CRYPTO_CMD_INSTR_CCLR;
+
+    /* Setup number of sequence iterations and block size. */
+    CRYPTO->SEQCTRL = CRYPTO_SEQCTRL_BLOCKSIZE_16BYTES
+      | (PARTIAL_OPERAND_WIDTH_IN_BYTES * numPartialOperandsB);
+
+    /* Execute the MULtiply instruction sequence. */
+    CRYPTO_InstructionSequenceExecute();
+
+    for (j=0; j<numPartialOperandsB; j++)
+    {
+      /* Load partial operand 2 B>>(j*`PARTIAL_OPERAND_WIDTH) to DDATA2
+         (via DATA0). */
+#ifdef USE_VARIABLE_SIZED_DATA_LOADS
+      if ( (numWordsLastOperandB != 0) && ( j == numPartialOperandsB-1 ) )
+        CRYPTO_DataWriteVariableSize(cryptoRegDATA0,
+                                     &B[j*PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS],
+                                     numWordsLastOperandB);
+      else
+        CRYPTO_DataWrite(cryptoRegDATA0,
+                         &B[j*PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS]);
+#else
+      CRYPTO_DataWrite(cryptoRegDATA0,
+                       &B[j*PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS]);
+#endif
+
+      /* Load most significant partial result
+         R>>((i+j+1)*`PARTIAL_OPERAND_WIDTH) into DATA1. */
+#ifdef USE_VARIABLE_SIZED_DATA_LOADS
+      if ( (numWordsLastOperandR != 0) && ( (i+j+1) == numPartialOperandsR-1 ) )
+        CRYPTO_DataWriteVariableSize(cryptoRegDATA1,
+                                     &R[(i+j+1)*PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS],
+                                     numWordsLastOperandR);
+      else
+        CRYPTO_DataWrite(cryptoRegDATA1,
+                         &R[(i+j+1)*PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS]);
+#else
+      CRYPTO_DataWrite(cryptoRegDATA1,
+                       &R[(i+j+1)*PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS]);
+#endif
+      /* Store least significant partial result */
+      CRYPTO_DataRead(cryptoRegDATA0,
+                      &R[(i+j)*PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS]);
+
+    } /* for (j=0; j<numPartialOperandsB; j++) */
+
+    /* Handle carry at the end of the inner loop. */
+    if (CRYPTO_CarryIsSet())
+      cryptoBigintIncrement(&R[(i+numPartialOperandsB+1)
+                               *PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS],
+                            (numPartialOperandsA-i-1)
+                            *PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS);
+
+    CRYPTO_DataRead(cryptoRegDATA1,
+                    &R[(i+numPartialOperandsB)
+                       * PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS]);
+
+  } /* for (i=0; i<numPartialOperandsA; i++) */
+}
+
+/***************************************************************************//**
+ * @brief
+ *   AES Cipher-block chaining (CBC) cipher mode encryption/decryption, 128 bit key.
+ *
+ * @details
+ *   Encryption:
+ * @verbatim
+ *           Plaintext                  Plaintext
+ *               |                          |
+ *               V                          V
+ * InitVector ->XOR        +-------------->XOR
+ *               |         |                |
+ *               V         |                V
+ *       +--------------+  |        +--------------+
+ * Key ->| Block cipher |  |  Key ->| Block cipher |
+ *       |  encryption  |  |        |  encryption  |
+ *       +--------------+  |        +--------------+
+ *               |---------+                |
+ *               V                          V
+ *           Ciphertext                 Ciphertext
+ * @endverbatim
+ *   Decryption:
+ * @verbatim
+ *         Ciphertext                 Ciphertext
+ *              |----------+                |
+ *              V          |                V
+ *       +--------------+  |        +--------------+
+ * Key ->| Block cipher |  |  Key ->| Block cipher |
+ *       |  decryption  |  |        |  decryption  |
+ *       +--------------+  |        +--------------+
+ *               |         |                |
+ *               V         |                V
+ * InitVector ->XOR        +-------------->XOR
+ *               |                          |
+ *               V                          V
+ *           Plaintext                  Plaintext
+ * @endverbatim
+ *   Please refer to general comments on layout and byte ordering of parameters.
+ *
+ * @param[out] out
+ *   Buffer to place encrypted/decrypted data. Must be at least @p len long. It
+ *   may be set equal to @p in, in which case the input buffer is overwritten.
+ *
+ * @param[in] in
+ *   Buffer holding data to encrypt/decrypt. Must be at least @p len long.
+ *
+ * @param[in] len
+ *   Number of bytes to encrypt/decrypt. Must be a multiple of 16.
+ *
+ * @param[in] key
+ *   When doing encryption, this is the 128 bit encryption key. When doing
+ *   decryption, this is the 128 bit decryption key. The decryption key may
+ *   be generated from the encryption key with CRYPTO_AES_DecryptKey128().
+ *   If this argument is null, the key will not be loaded, as it is assumed
+ *   the key has been loaded into KEYHA previously.
+ *
+ * @param[in] iv
+ *   128 bit initialization vector to use.
+ *
+ * @param[in] encrypt
+ *   Set to true to encrypt, false to decrypt.
+ ******************************************************************************/
+void CRYPTO_AES_CBC128(uint8_t * out,
+                       const uint8_t * in,
+                       unsigned int len,
+                       const uint8_t * key,
+                       const uint8_t * iv,
+                       bool encrypt)
+{
+  CRYPTO->CTRL = CRYPTO_CTRL_AES_AES128;
+  CRYPTO_AES_CBCx(out, in, len, key, iv, encrypt, cryptoKey128Bits);
+}
+
+/***************************************************************************//**
+ * @brief
+ *   AES Cipher-block chaining (CBC) cipher mode encryption/decryption, 256 bit
+ *   key.
+ *
+ * @details
+ *   Please see CRYPTO_AES_CBC128() for CBC figure.
+ *
+ *   Please refer to general comments on layout and byte ordering of parameters.
+ *
+ * @param[out] out
+ *   Buffer to place encrypted/decrypted data. Must be at least @p len long. It
+ *   may be set equal to @p in, in which case the input buffer is overwritten.
+ *
+ * @param[in] in
+ *   Buffer holding data to encrypt/decrypt. Must be at least @p len long.
+ *
+ * @param[in] len
+ *   Number of bytes to encrypt/decrypt. Must be a multiple of 16.
+ *
+ * @param[in] key
+ *   When doing encryption, this is the 256 bit encryption key. When doing
+ *   decryption, this is the 256 bit decryption key. The decryption key may
+ *   be generated from the encryption key with CRYPTO_AES_DecryptKey256().
+ *
+ * @param[in] iv
+ *   128 bit initialization vector to use.
+ *
+ * @param[in] encrypt
+ *   Set to true to encrypt, false to decrypt.
+ ******************************************************************************/
+void CRYPTO_AES_CBC256(uint8_t * out,
+                       const uint8_t * in,
+                       unsigned int len,
+                       const uint8_t * key,
+                       const uint8_t * iv,
+                       bool encrypt)
+{
+  CRYPTO->CTRL = CRYPTO_CTRL_AES_AES256;
+  CRYPTO_AES_CBCx(out, in, len, key, iv, encrypt, cryptoKey256Bits);
+}
+
+/***************************************************************************//**
+ * @brief
+ *   AES Cipher feedback (CFB) cipher mode encryption/decryption, 128 bit key.
+ *
+ * @details
+ *   Encryption:
+ * @verbatim
+ *           InitVector    +----------------+
+ *               |         |                |
+ *               V         |                V
+ *       +--------------+  |        +--------------+
+ * Key ->| Block cipher |  |  Key ->| Block cipher |
+ *       |  encryption  |  |        |  encryption  |
+ *       +--------------+  |        +--------------+
+ *               |         |                |
+ *               V         |                V
+ *  Plaintext ->XOR        |   Plaintext ->XOR
+ *               |---------+                |
+ *               V                          V
+ *           Ciphertext                 Ciphertext
+ * @endverbatim
+ *   Decryption:
+ * @verbatim
+ *          InitVector     +----------------+
+ *               |         |                |
+ *               V         |                V
+ *       +--------------+  |        +--------------+
+ * Key ->| Block cipher |  |  Key ->| Block cipher |
+ *       |  encryption  |  |        |  encryption  |
+ *       +--------------+  |        +--------------+
+ *               |         |                |
+ *               V         |                V
+ *              XOR<- Ciphertext           XOR<- Ciphertext
+ *               |                          |
+ *               V                          V
+ *           Plaintext                  Plaintext
+ * @endverbatim
+ *   Please refer to general comments on layout and byte ordering of parameters.
+ *
+ * @param[out] out
+ *   Buffer to place encrypted/decrypted data. Must be at least @p len long. It
+ *   may be set equal to @p in, in which case the input buffer is overwritten.
+ *
+ * @param[in] in
+ *   Buffer holding data to encrypt/decrypt. Must be at least @p len long.
+ *
+ * @param[in] len
+ *   Number of bytes to encrypt/decrypt. Must be a multiple of 16.
+ *
+ * @param[in] key
+ *   128 bit encryption key is used for both encryption and decryption modes.
+ *
+ * @param[in] iv
+ *   128 bit initialization vector to use.
+ *
+ * @param[in] encrypt
+ *   Set to true to encrypt, false to decrypt.
+ ******************************************************************************/
+void CRYPTO_AES_CFB128(uint8_t * out,
+                       const uint8_t * in,
+                       unsigned int len,
+                       const uint8_t * key,
+                       const uint8_t * iv,
+                       bool encrypt)
+{
+  CRYPTO->CTRL = CRYPTO_CTRL_AES_AES128;
+  CRYPTO_AES_CFBx(out, in, len, key, iv, encrypt, cryptoKey128Bits);
+}
+
+/***************************************************************************//**
+ * @brief
+ *   AES Cipher feedback (CFB) cipher mode encryption/decryption, 256 bit key.
+ *
+ * @details
+ *   Please see CRYPTO_AES_CFB128() for CFB figure.
+ *
+ *   Please refer to general comments on layout and byte ordering of parameters.
+ *
+ * @param[out] out
+ *   Buffer to place encrypted/decrypted data. Must be at least @p len long. It
+ *   may be set equal to @p in, in which case the input buffer is overwritten.
+ *
+ * @param[in] in
+ *   Buffer holding data to encrypt/decrypt. Must be at least @p len long.
+ *
+ * @param[in] len
+ *   Number of bytes to encrypt/decrypt. Must be a multiple of 16.
+ *
+ * @param[in] key
+ *   256 bit encryption key is used for both encryption and decryption modes.
+ *
+ * @param[in] iv
+ *   128 bit initialization vector to use.
+ *
+ * @param[in] encrypt
+ *   Set to true to encrypt, false to decrypt.
+ ******************************************************************************/
+void CRYPTO_AES_CFB256(uint8_t * out,
+                       const uint8_t * in,
+                       unsigned int len,
+                       const uint8_t * key,
+                       const uint8_t * iv,
+                       bool encrypt)
+{
+  CRYPTO->CTRL = CRYPTO_CTRL_AES_AES256;
+  CRYPTO_AES_CFBx(out, in, len, key, iv, encrypt, cryptoKey256Bits);
+}
+
+/***************************************************************************//**
+ * @brief
+ *   AES Counter (CTR) cipher mode encryption/decryption, 128 bit key.
+ *
+ * @details
+ *   Encryption:
+ * @verbatim
+ *           Counter                    Counter
+ *              |                          |
+ *              V                          V
+ *       +--------------+           +--------------+
+ * Key ->| Block cipher |     Key ->| Block cipher |
+ *       |  encryption  |           |  encryption  |
+ *       +--------------+           +--------------+
+ *              |                          |
+ * Plaintext ->XOR            Plaintext ->XOR
+ *              |                          |
+ *              V                          V
+ *         Ciphertext                 Ciphertext
+ * @endverbatim
+ *   Decryption:
+ * @verbatim
+ *           Counter                    Counter
+ *              |                          |
+ *              V                          V
+ *       +--------------+           +--------------+
+ * Key ->| Block cipher |     Key ->| Block cipher |
+ *       |  encryption  |           |  encryption  |
+ *       +--------------+           +--------------+
+ *               |                          |
+ * Ciphertext ->XOR           Ciphertext ->XOR
+ *               |                          |
+ *               V                          V
+ *           Plaintext                  Plaintext
+ * @endverbatim
+ *   Please refer to general comments on layout and byte ordering of parameters.
+ *
+ * @param[out] out
+ *   Buffer to place encrypted/decrypted data. Must be at least @p len long. It
+ *   may be set equal to @p in, in which case the input buffer is overwritten.
+ *
+ * @param[in] in
+ *   Buffer holding data to encrypt/decrypt. Must be at least @p len long.
+ *
+ * @param[in] len
+ *   Number of bytes to encrypt/decrypt. Must be a multiple of 16.
+ *
+ * @param[in] key
+ *   128 bit encryption key.
+ *   If this argument is null, the key will not be loaded, as it is assumed
+ *   the key has been loaded into KEYHA previously.
+ *
+ * @param[in,out] ctr
+ *   128 bit initial counter value. The counter is updated after each AES
+ *   block encoding through use of @p ctrFunc.
+ *
+ * @param[in] ctrFunc
+ *   Function used to update counter value. Not supported by CRYPTO.
+ *   This parameter is included in order for backwards compatibility with
+ *   the EFM32 em_aes.h API.
+ ******************************************************************************/
+void CRYPTO_AES_CTR128(uint8_t * out,
+                       const uint8_t * in,
+                       unsigned int len,
+                       const uint8_t * key,
+                       uint8_t * ctr,
+                       CRYPTO_AES_CtrFuncPtr_TypeDef ctrFunc)
+{
+  CRYPTO->CTRL = CRYPTO_CTRL_AES_AES128;
+  CRYPTO_AES_CTRx(out, in, len, key, ctr, ctrFunc, cryptoKey128Bits);
+}
+
+/***************************************************************************//**
+ * @brief
+ *   AES Counter (CTR) cipher mode encryption/decryption, 256 bit key.
+ *
+ * @details
+ *   Please see CRYPTO_AES_CTR128() for CTR figure.
+ *
+ *   Please refer to general comments on layout and byte ordering of parameters.
+ *
+ * @param[out] out
+ *   Buffer to place encrypted/decrypted data. Must be at least @p len long. It
+ *   may be set equal to @p in, in which case the input buffer is overwritten.
+ *
+ * @param[in] in
+ *   Buffer holding data to encrypt/decrypt. Must be at least @p len long.
+ *
+ * @param[in] len
+ *   Number of bytes to encrypt/decrypt. Must be a multiple of 16.
+ *
+ * @param[in] key
+ *   256 bit encryption key.
+ *
+ * @param[in,out] ctr
+ *   128 bit initial counter value. The counter is updated after each AES
+ *   block encoding through use of @p ctrFunc.
+ *
+ * @param[in] ctrFunc
+ *   Function used to update counter value. Not supported by CRYPTO.
+ *   This parameter is included in order for backwards compatibility with
+ *   the EFM32 em_aes.h API.
+ ******************************************************************************/
+void CRYPTO_AES_CTR256(uint8_t * out,
+                       const uint8_t * in,
+                       unsigned int len,
+                       const uint8_t * key,
+                       uint8_t * ctr,
+                       CRYPTO_AES_CtrFuncPtr_TypeDef ctrFunc)
+{
+  CRYPTO->CTRL = CRYPTO_CTRL_AES_AES256;
+  CRYPTO_AES_CTRx(out, in, len, key, ctr, ctrFunc, cryptoKey256Bits);
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Update last 32 bits of 128 bit counter, by incrementing with 1.
+ *
+ * @details
+ *   Notice that no special consideration is given to possible wrap around. If
+ *   32 least significant bits are 0xFFFFFFFF, they will be updated to 0x00000000,
+ *   ignoring overflow.
+ *
+ *   Please refer to general comments on layout and byte ordering of parameters.
+ *
+ * @param[in,out] ctr
+ *   Buffer holding 128 bit counter to be updated.
+ ******************************************************************************/
+void CRYPTO_AES_CTRUpdate32Bit(uint8_t * ctr)
+{
+  uint32_t * _ctr = (uint32_t *) ctr;
+
+  _ctr[3] = __REV(__REV(_ctr[3]) + 1);
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Generate 128 bit AES decryption key from 128 bit encryption key. The
+ *   decryption key is used for some cipher modes when decrypting.
+ *
+ * @details
+ *   Please refer to general comments on layout and byte ordering of parameters.
+ *
+ * @param[out] out
+ *   Buffer to place 128 bit decryption key. Must be at least 16 bytes long. It
+ *   may be set equal to @p in, in which case the input buffer is overwritten.
+ *
+ * @param[in] in
+ *   Buffer holding 128 bit encryption key. Must be at least 16 bytes long.
+ ******************************************************************************/
+void CRYPTO_AES_DecryptKey128(uint8_t * out, const uint8_t * in)
+{
+  uint32_t       * _out = (uint32_t *) out;
+  const uint32_t * _in  = (const uint32_t *) in;
+
+  /* Load key */
+  CRYPTO_BurstToCrypto(&CRYPTO->KEYBUF, &_in[0]);
+
+  /* Do dummy encryption to generate decrypt key */
+  CRYPTO->CTRL = CRYPTO_CTRL_AES_AES128;
+  CRYPTO_IntClear(CRYPTO_IF_INSTRDONE);
+  CRYPTO->CMD  = CRYPTO_CMD_INSTR_AESENC;
+
+  /* Save decryption key */
+  CRYPTO_BurstFromCrypto(&CRYPTO->KEY, &_out[0]);
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Generate 256 bit AES decryption key from 256 bit encryption key. The
+ *   decryption key is used for some cipher modes when decrypting.
+ *
+ * @details
+ *   Please refer to general comments on layout and byte ordering of parameters.
+ *
+ * @param[out] out
+ *   Buffer to place 256 bit decryption key. Must be at least 32 bytes long. It
+ *   may be set equal to @p in, in which case the input buffer is overwritten.
+ *
+ * @param[in] in
+ *   Buffer holding 256 bit encryption key. Must be at least 32 bytes long.
+ ******************************************************************************/
+void CRYPTO_AES_DecryptKey256(uint8_t * out, const uint8_t * in)
+{
+  uint32_t       * _out = (uint32_t *) out;
+  const uint32_t * _in  = (const uint32_t *) in;
+
+  /* Load key */
+  CRYPTO_BurstToCrypto(&CRYPTO->KEYBUF, &_in[0]);
+  CRYPTO_BurstToCrypto(&CRYPTO->KEYBUF, &_in[4]);
+
+  /* Do dummy encryption to generate decrypt key */
+  CRYPTO->CTRL = CRYPTO_CTRL_AES_AES256;
+  CRYPTO->CMD  = CRYPTO_CMD_INSTR_AESENC;
+
+  /* Save decryption key */
+  CRYPTO_BurstFromCrypto(&CRYPTO->KEY, &_out[0]);
+  CRYPTO_BurstFromCrypto(&CRYPTO->KEY, &_out[4]);
+}
+
+/***************************************************************************//**
+ * @brief
+ *   AES Electronic Codebook (ECB) cipher mode encryption/decryption,
+ *   128 bit key.
+ *
+ * @details
+ *   Encryption:
+ * @verbatim
+ *          Plaintext                  Plaintext
+ *              |                          |
+ *              V                          V
+ *       +--------------+           +--------------+
+ * Key ->| Block cipher |     Key ->| Block cipher |
+ *       |  encryption  |           |  encryption  |
+ *       +--------------+           +--------------+
+ *              |                          |
+ *              V                          V
+ *         Ciphertext                 Ciphertext
+ * @endverbatim
+ *   Decryption:
+ * @verbatim
+ *         Ciphertext                 Ciphertext
+ *              |                          |
+ *              V                          V
+ *       +--------------+           +--------------+
+ * Key ->| Block cipher |     Key ->| Block cipher |
+ *       |  decryption  |           |  decryption  |
+ *       +--------------+           +--------------+
+ *              |                          |
+ *              V                          V
+ *          Plaintext                  Plaintext
+ * @endverbatim
+ *   Please refer to general comments on layout and byte ordering of parameters.
+ *
+ * @param[out] out
+ *   Buffer to place encrypted/decrypted data. Must be at least @p len long. It
+ *   may be set equal to @p in, in which case the input buffer is overwritten.
+ *
+ * @param[in] in
+ *   Buffer holding data to encrypt/decrypt. Must be at least @p len long.
+ *
+ * @param[in] len
+ *   Number of bytes to encrypt/decrypt. Must be a multiple of 16.
+ *
+ * @param[in] key
+ *   When doing encryption, this is the 128 bit encryption key. When doing
+ *   decryption, this is the 128 bit decryption key. The decryption key may
+ *   be generated from the encryption key with CRYPTO_AES_DecryptKey128().
+ *
+ * @param[in] encrypt
+ *   Set to true to encrypt, false to decrypt.
+ ******************************************************************************/
+void CRYPTO_AES_ECB128(uint8_t * out,
+                       const uint8_t * in,
+                       unsigned int len,
+                       const uint8_t * key,
+                       bool encrypt)
+{
+  CRYPTO->CTRL = CRYPTO_CTRL_AES_AES128;
+  CRYPTO_AES_ECBx(out, in, len, key, encrypt, cryptoKey128Bits);
+}
+
+/***************************************************************************//**
+ * @brief
+ *   AES Electronic Codebook (ECB) cipher mode encryption/decryption,
+ *   256 bit key.
+ *
+ * @details
+ *   Please see CRYPTO_AES_ECB128() for ECB figure.
+ *
+ *   Please refer to general comments on layout and byte ordering of parameters.
+ *
+ * @param[out] out
+ *   Buffer to place encrypted/decrypted data. Must be at least @p len long. It
+ *   may be set equal to @p in, in which case the input buffer is overwritten.
+ *
+ * @param[in] in
+ *   Buffer holding data to encrypt/decrypt. Must be at least @p len long.
+ *
+ * @param[in] len
+ *   Number of bytes to encrypt/decrypt. Must be a multiple of 16.
+ *
+ * @param[in] key
+ *   When doing encryption, this is the 256 bit encryption key. When doing
+ *   decryption, this is the 256 bit decryption key. The decryption key may
+ *   be generated from the encryption key with CRYPTO_AES_DecryptKey256().
+ *
+ * @param[in] encrypt
+ *   Set to true to encrypt, false to decrypt.
+ ******************************************************************************/
+void CRYPTO_AES_ECB256(uint8_t * out,
+                       const uint8_t * in,
+                       unsigned int len,
+                       const uint8_t * key,
+                       bool encrypt)
+{
+  CRYPTO->CTRL = CRYPTO_CTRL_AES_AES256;
+  CRYPTO_AES_ECBx(out, in, len, key, encrypt, cryptoKey256Bits);
+}
+
+/***************************************************************************//**
+ * @brief
+ *   AES Output feedback (OFB) cipher mode encryption/decryption, 128 bit key.
+ *
+ * @details
+ *   Encryption:
+ * @verbatim
+ *          InitVector    +----------------+
+ *              |         |                |
+ *              V         |                V
+ *       +--------------+ |        +--------------+
+ * Key ->| Block cipher | |  Key ->| Block cipher |
+ *       |  encryption  | |        |  encryption  |
+ *       +--------------+ |        +--------------+
+ *              |         |                |
+ *              |---------+                |
+ *              V                          V
+ * Plaintext ->XOR            Plaintext ->XOR
+ *              |                          |
+ *              V                          V
+ *         Ciphertext                 Ciphertext
+ * @endverbatim
+ *   Decryption:
+ * @verbatim
+ *          InitVector    +----------------+
+ *              |         |                |
+ *              V         |                V
+ *       +--------------+ |        +--------------+
+ * Key ->| Block cipher | |  Key ->| Block cipher |
+ *       |  encryption  | |        |  encryption  |
+ *       +--------------+ |        +--------------+
+ *              |         |                |
+ *              |---------+                |
+ *              V                          V
+ * Ciphertext ->XOR           Ciphertext ->XOR
+ *              |                          |
+ *              V                          V
+ *          Plaintext                  Plaintext
+ * @endverbatim
+ *   Please refer to general comments on layout and byte ordering of parameters.
+ *
+ * @param[out] out
+ *   Buffer to place encrypted/decrypted data. Must be at least @p len long. It
+ *   may be set equal to @p in, in which case the input buffer is overwritten.
+ *
+ * @param[in] in
+ *   Buffer holding data to encrypt/decrypt. Must be at least @p len long.
+ *
+ * @param[in] len
+ *   Number of bytes to encrypt/decrypt. Must be a multiple of 16.
+ *
+ * @param[in] key
+ *   128 bit encryption key.
+ *
+ * @param[in] iv
+ *   128 bit initialization vector to use.
+ ******************************************************************************/
+void CRYPTO_AES_OFB128(uint8_t * out,
+                       const uint8_t * in,
+                       unsigned int len,
+                       const uint8_t * key,
+                       const uint8_t * iv)
+{
+  CRYPTO->CTRL = CRYPTO_CTRL_AES_AES128;
+  CRYPTO_AES_OFBx(out, in, len, key, iv, cryptoKey128Bits);
+}
+
+/***************************************************************************//**
+ * @brief
+ *   AES Output feedback (OFB) cipher mode encryption/decryption, 256 bit key.
+ *
+ * @details
+ *   Please see CRYPTO_AES_OFB128() for OFB figure.
+ *
+ *   Please refer to general comments on layout and byte ordering of parameters.
+ *
+ * @param[out] out
+ *   Buffer to place encrypted/decrypted data. Must be at least @p len long. It
+ *   may be set equal to @p in, in which case the input buffer is overwritten.
+ *
+ * @param[in] in
+ *   Buffer holding data to encrypt/decrypt. Must be at least @p len long.
+ *
+ * @param[in] len
+ *   Number of bytes to encrypt/decrypt. Must be a multiple of 16.
+ *
+ * @param[in] key
+ *   256 bit encryption key.
+ *
+ * @param[in] iv
+ *   128 bit initialization vector to use.
+ ******************************************************************************/
+void CRYPTO_AES_OFB256(uint8_t * out,
+                       const uint8_t * in,
+                       unsigned int len,
+                       const uint8_t * key,
+                       const uint8_t * iv)
+{
+  CRYPTO->CTRL = CRYPTO_CTRL_AES_AES256;
+  CRYPTO_AES_OFBx(out, in, len, key, iv, cryptoKey256Bits);
+}
+
+/*******************************************************************************
+ **************************   LOCAL FUNCTIONS   *******************************
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * @brief
+ *   Cipher-block chaining (CBC) cipher mode encryption/decryption, 128/256 bit key.
+ *
+ * @details
+ *   Please see CRYPTO_AES_CBC128() for CBC figure.
+ *
+ *   Please refer to general comments on layout and byte ordering of parameters.
+ *
+ * @param[out] out
+ *   Buffer to place encrypted/decrypted data. Must be at least @p len long. It
+ *   may be set equal to @p in, in which case the input buffer is overwritten.
+ *
+ * @param[in] in
+ *   Buffer holding data to encrypt/decrypt. Must be at least @p len long.
+ *
+ * @param[in] len
+ *   Number of bytes to encrypt/decrypt. Must be a multiple of 16.
+ *
+ * @param[in] key
+ *   When doing encryption, this is the 256 bit encryption key. When doing
+ *   decryption, this is the 256 bit decryption key. The decryption key may
+ *   be generated from the encryption key with CRYPTO_AES_DecryptKey256().
+ *
+ * @param[in] iv
+ *   128 bit initialization vector to use.
+ *
+ * @param[in] encrypt
+ *   Set to true to encrypt, false to decrypt.
+ *
+ * @param[in] keyWidth
+ *   Set to cryptoKey128Bits or cryptoKey256Bits.
+ ******************************************************************************/
+static void CRYPTO_AES_CBCx(uint8_t * out,
+                            const uint8_t * in,
+                            unsigned int len,
+                            const uint8_t * key,
+                            const uint8_t * iv,
+                            bool encrypt,
+                            CRYPTO_KeyWidth_TypeDef keyWidth)
+{
+  EFM_ASSERT(!(len % CRYPTO_AES_BLOCKSIZE));
+
+  /* Initialize control registers. */
+  CRYPTO->WAC = 0;
+  
+  CRYPTO_KeyBufWrite((uint32_t *)key, keyWidth);
+
+  if (encrypt)
+  {
+    CRYPTO_DataWrite(cryptoRegDATA0, (uint32_t *)iv);
+
+    CRYPTO->SEQ0 =
+      CRYPTO_CMD_INSTR_DATA1TODATA0XOR << _CRYPTO_SEQ0_INSTR0_SHIFT |
+      CRYPTO_CMD_INSTR_AESENC          << _CRYPTO_SEQ0_INSTR1_SHIFT;
+        
+    CRYPTO_AES_ProcessLoop(len,
+                           cryptoRegDATA1, (uint32_t *) in,
+                           cryptoRegDATA0, (uint32_t *) out);
+  }
+  else
+  {
+    CRYPTO_DataWrite(cryptoRegDATA2, (uint32_t *) iv);
+
+    CRYPTO->SEQ0 =
+      CRYPTO_CMD_INSTR_DATA1TODATA0    << _CRYPTO_SEQ0_INSTR0_SHIFT |
+      CRYPTO_CMD_INSTR_AESDEC          << _CRYPTO_SEQ0_INSTR1_SHIFT |
+      CRYPTO_CMD_INSTR_DATA2TODATA0XOR << _CRYPTO_SEQ0_INSTR2_SHIFT |
+      CRYPTO_CMD_INSTR_DATA1TODATA2    << _CRYPTO_SEQ0_INSTR3_SHIFT;
+
+    CRYPTO->SEQ1 = 0;
+
+    /* The following call is equivalent to the last call in the
+       'if( encrypt )' branch. However moving this
+       call outside the conditional scope results in slightly poorer
+       performance for some compiler optimizations. */
+    CRYPTO_AES_ProcessLoop(len,
+                           cryptoRegDATA1, (uint32_t *) in,
+                           cryptoRegDATA0, (uint32_t *) out);
+  }
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Cipher feedback (CFB) cipher mode encryption/decryption, 128/256 bit key.
+ *
+ * @details
+ *   Please see CRYPTO_AES_CFB128() for CFB figure.
+ *
+ *   Please refer to general comments on layout and byte ordering of parameters.
+ *
+ * @param[out] out
+ *   Buffer to place encrypted/decrypted data. Must be at least @p len long. It
+ *   may be set equal to @p in, in which case the input buffer is overwritten.
+ *
+ * @param[in] in
+ *   Buffer holding data to encrypt/decrypt. Must be at least @p len long.
+ *
+ * @param[in] len
+ *   Number of bytes to encrypt/decrypt. Must be a multiple of 16.
+ *
+ * @param[in] key
+ *   256 bit encryption key is used for both encryption and decryption modes.
+ *
+ * @param[in] iv
+ *   128 bit initialization vector to use.
+ *
+ * @param[in] encrypt
+ *   Set to true to encrypt, false to decrypt.
+ *
+ * @param[in] keyWidth
+ *   Set to cryptoKey128Bits or cryptoKey256Bits.
+ ******************************************************************************/
+static void CRYPTO_AES_CFBx(uint8_t * out,
+                            const uint8_t * in,
+                            unsigned int len,
+                            const uint8_t * key,
+                            const uint8_t * iv,
+                            bool encrypt,
+                            CRYPTO_KeyWidth_TypeDef keyWidth)
+{
+  EFM_ASSERT(!(len % CRYPTO_AES_BLOCKSIZE));
+
+  /* Initialize control registers. */
+  CRYPTO->WAC = 0;
+
+  /* Load Key */
+  CRYPTO_KeyBufWrite((uint32_t *)key, keyWidth);
+
+  /* Load instructions to CRYPTO sequencer. */
+  if (encrypt)
+  {
+    /* Load IV */
+    CRYPTO_DataWrite(cryptoRegDATA0, (uint32_t *)iv);
+
+    CRYPTO->SEQ0 =
+      CRYPTO_CMD_INSTR_AESENC          << _CRYPTO_SEQ0_INSTR0_SHIFT |
+      CRYPTO_CMD_INSTR_DATA1TODATA0XOR << _CRYPTO_SEQ0_INSTR1_SHIFT;
+    
+    CRYPTO_AES_ProcessLoop(len,
+                           cryptoRegDATA1, (uint32_t *)in,
+                           cryptoRegDATA0, (uint32_t *)out
+                           );
+  }
+  else
+  {
+    /* Load IV */
+    CRYPTO_DataWrite(cryptoRegDATA2, (uint32_t *)iv);
+
+    CRYPTO->SEQ0 =
+      CRYPTO_CMD_INSTR_DATA2TODATA0    << _CRYPTO_SEQ0_INSTR0_SHIFT |
+      CRYPTO_CMD_INSTR_AESENC          << _CRYPTO_SEQ0_INSTR1_SHIFT |
+      CRYPTO_CMD_INSTR_DATA1TODATA0XOR << _CRYPTO_SEQ0_INSTR2_SHIFT |
+      CRYPTO_CMD_INSTR_DATA1TODATA2    << _CRYPTO_SEQ0_INSTR3_SHIFT;
+    CRYPTO->SEQ1 = 0;
+    
+    CRYPTO_AES_ProcessLoop(len,
+                           cryptoRegDATA1, (uint32_t *)in,
+                           cryptoRegDATA0, (uint32_t *)out
+                           );
+  }
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Counter (CTR) cipher mode encryption/decryption, 128/256 bit key.
+ *
+ * @details
+ *   Please see CRYPTO_AES_CTR128() for CTR figure.
+ *
+ *   Please refer to general comments on layout and byte ordering of parameters.
+ *
+ * @param[out] out
+ *   Buffer to place encrypted/decrypted data. Must be at least @p len long. It
+ *   may be set equal to @p in, in which case the input buffer is overwritten.
+ *
+ * @param[in] in
+ *   Buffer holding data to encrypt/decrypt. Must be at least @p len long.
+ *
+ * @param[in] len
+ *   Number of bytes to encrypt/decrypt. Must be a multiple of 16.
+ *
+ * @param[in] key
+ *   256 bit encryption key.
+ *
+ * @param[in,out] ctr
+ *   128 bit initial counter value. The counter is updated after each AES
+ *   block encoding through use of @p ctrFunc.
+ *
+ * @param[in] ctrFunc
+ *   Function used to update counter value. Not supported by CRYPTO.
+ *   This parameter is included in order for backwards compatibility with
+ *   the EFM32 em_aes.h API.
+ *
+ * @param[in] keyWidth
+ *   Set to cryptoKey128Bits or cryptoKey256Bits.
+ ******************************************************************************/
+static void CRYPTO_AES_CTRx(uint8_t * out,
+                            const uint8_t * in,
+                            unsigned int len,
+                            const uint8_t * key,
+                            uint8_t * ctr,
+                            CRYPTO_AES_CtrFuncPtr_TypeDef ctrFunc,
+                            CRYPTO_KeyWidth_TypeDef keyWidth)
+{
+  (void) ctrFunc;
+  
+  EFM_ASSERT(!(len % CRYPTO_AES_BLOCKSIZE));
+
+  /* Initialize control registers. */
+  CRYPTO->CTRL |= CRYPTO_CTRL_INCWIDTH_INCWIDTH4;
+  CRYPTO->WAC   = 0;
+
+  CRYPTO_KeyBufWrite((uint32_t *)key, keyWidth);
+
+  CRYPTO_DataWrite(cryptoRegDATA1, (uint32_t *) ctr);
+
+  CRYPTO->SEQ0 = CRYPTO_CMD_INSTR_DATA1TODATA0  << _CRYPTO_SEQ0_INSTR0_SHIFT |
+                 CRYPTO_CMD_INSTR_AESENC        << _CRYPTO_SEQ0_INSTR1_SHIFT |
+                 CRYPTO_CMD_INSTR_DATA0TODATA3  << _CRYPTO_SEQ0_INSTR2_SHIFT |
+                 CRYPTO_CMD_INSTR_DATA1INC      << _CRYPTO_SEQ0_INSTR3_SHIFT;
+
+  CRYPTO->SEQ1 = CRYPTO_CMD_INSTR_DATA2TODATA0XOR << _CRYPTO_SEQ1_INSTR4_SHIFT;
+
+  CRYPTO_AES_ProcessLoop(len,
+                         cryptoRegDATA2, (uint32_t *) in,
+                         cryptoRegDATA0, (uint32_t *) out);
+
+  CRYPTO_DataRead(cryptoRegDATA1, (uint32_t *) ctr);
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Electronic Codebook (ECB) cipher mode encryption/decryption, 128/256 bit key.
+ *
+ * @details
+ *   Please see CRYPTO_AES_ECB128() for ECB figure.
+ *
+ *   Please refer to general comments on layout and byte ordering of parameters.
+ *
+ * @param[out] out
+ *   Buffer to place encrypted/decrypted data. Must be at least @p len long. It
+ *   may be set equal to @p in, in which case the input buffer is overwritten.
+ *
+ * @param[in] in
+ *   Buffer holding data to encrypt/decrypt. Must be at least @p len long.
+ *
+ * @param[in] len
+ *   Number of bytes to encrypt/decrypt. Must be a multiple of 16.
+ *
+ * @param[in] key
+ *   When doing encryption, this is the 256 bit encryption key. When doing
+ *   decryption, this is the 256 bit decryption key. The decryption key may
+ *   be generated from the encryption key with CRYPTO_AES_DecryptKey256().
+ *
+ * @param[in] encrypt
+ *   Set to true to encrypt, false to decrypt.
+ *
+ * @param[in] keyWidth
+ *   Set to cryptoKey128Bits or cryptoKey256Bits.
+ ******************************************************************************/
+static void CRYPTO_AES_ECBx(uint8_t * out,
+                            const uint8_t * in,
+                            unsigned int len,
+                            const uint8_t * key,
+                            bool encrypt,
+                            CRYPTO_KeyWidth_TypeDef keyWidth)
+{
+  EFM_ASSERT(!(len % CRYPTO_AES_BLOCKSIZE));
+
+  CRYPTO->WAC = 0;
+
+  CRYPTO_KeyBufWrite((uint32_t *)key, keyWidth);
+
+  if (encrypt)
+  {
+    CRYPTO->SEQ0 =
+      (CRYPTO_CMD_INSTR_AESENC       << _CRYPTO_SEQ0_INSTR0_SHIFT |
+       CRYPTO_CMD_INSTR_DATA0TODATA1 << _CRYPTO_SEQ0_INSTR1_SHIFT);
+  }
+  else
+  {
+    CRYPTO->SEQ0 =
+      (CRYPTO_CMD_INSTR_AESDEC       << _CRYPTO_SEQ0_INSTR0_SHIFT |
+       CRYPTO_CMD_INSTR_DATA0TODATA1 << _CRYPTO_SEQ0_INSTR1_SHIFT);
+  }
+
+  CRYPTO_AES_ProcessLoop(len,
+                         cryptoRegDATA0, (uint32_t *) in,
+                         cryptoRegDATA1, (uint32_t *) out);
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Output feedback (OFB) cipher mode encryption/decryption, 128/256 bit key.
+ *
+ * @details
+ *   Please see CRYPTO_AES_OFB128() for OFB figure.
+ *
+ *   Please refer to general comments on layout and byte ordering of parameters.
+ *
+ * @param[out] out
+ *   Buffer to place encrypted/decrypted data. Must be at least @p len long. It
+ *   may be set equal to @p in, in which case the input buffer is overwritten.
+ *
+ * @param[in] in
+ *   Buffer holding data to encrypt/decrypt. Must be at least @p len long.
+ *
+ * @param[in] len
+ *   Number of bytes to encrypt/decrypt. Must be a multiple of 16.
+ *
+ * @param[in] key
+ *   256 bit encryption key.
+ *
+ * @param[in] iv
+ *   128 bit initialization vector to use.
+ *
+ * @param[in] keyWidth
+ *   Set to cryptoKey128Bits or cryptoKey256Bits.
+ ******************************************************************************/
+static void CRYPTO_AES_OFBx(uint8_t * out,
+                            const uint8_t * in,
+                            unsigned int len,
+                            const uint8_t * key,
+                            const uint8_t * iv,
+                            CRYPTO_KeyWidth_TypeDef keyWidth)
+{
+  EFM_ASSERT(!(len % CRYPTO_AES_BLOCKSIZE));
+
+  CRYPTO->WAC = 0;
+
+  CRYPTO_KeyBufWrite((uint32_t *)key, keyWidth);
+
+  CRYPTO_DataWrite(cryptoRegDATA2, (uint32_t *)iv);
+
+  CRYPTO->SEQ0 =
+    CRYPTO_CMD_INSTR_DATA0TODATA1    << _CRYPTO_SEQ0_INSTR0_SHIFT |
+    CRYPTO_CMD_INSTR_DATA2TODATA0    << _CRYPTO_SEQ0_INSTR1_SHIFT |
+    CRYPTO_CMD_INSTR_AESENC          << _CRYPTO_SEQ0_INSTR2_SHIFT |
+    CRYPTO_CMD_INSTR_DATA0TODATA2    << _CRYPTO_SEQ0_INSTR3_SHIFT;
+  CRYPTO->SEQ1 =
+    CRYPTO_CMD_INSTR_DATA1TODATA0XOR << _CRYPTO_SEQ1_INSTR4_SHIFT |
+    CRYPTO_CMD_INSTR_DATA0TODATA1    << _CRYPTO_SEQ1_INSTR5_SHIFT;
+
+  CRYPTO_AES_ProcessLoop(len,
+                         cryptoRegDATA0, (uint32_t *) in,
+                         cryptoRegDATA1, (uint32_t *) out);
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Function performs generic AES loop.
+ *
+ * @details
+ *   Function loads given register with provided input data. Triggers CRYPTO to
+ *   perform sequence of instructions and read specified output register to
+ *   output buffer.
+ *
+ * @param[in] len
+ *   Number of bytes to encrypt/decrypt. Must be a multiple of 16.
+ *
+ * @param[in] inReg
+ *   Input register - one of DATA0,DATA1,DATA2,DATA3
+ *
+ * @param[in] in
+ *   Buffer holding data to encrypt/decrypt. Must be at least @p len long.
+ *
+ * @param[in] outReg
+ *   Output register - one of DATA0,DATA1,DATA2,DATA3
+ *
+ * @param[out] out
+ *   Buffer to place encrypted/decrypted data. Must be at least @p len long. It
+ *   may be set equal to @p in, in which case the input buffer is overwritten.
+ ******************************************************************************/
+static inline void CRYPTO_AES_ProcessLoop(uint32_t                len,
+                                          CRYPTO_DataReg_TypeDef  inReg,
+                                          uint32_t *              in,
+                                          CRYPTO_DataReg_TypeDef  outReg,
+                                          uint32_t *              out)
+{
+  len /= CRYPTO_AES_BLOCKSIZE;
+  CRYPTO->SEQCTRL = 16 << _CRYPTO_SEQCTRL_LENGTHA_SHIFT;
+
+  while (len--)
+  {
+    /* Load data and trigger encryption */
+    CRYPTO_DataWrite(inReg, (uint32_t *)in);
+
+    CRYPTO->CMD = CRYPTO_CMD_SEQSTART;
+
+    /* Save encrypted/decrypted data */
+    CRYPTO_DataRead(outReg, (uint32_t *)out);
+
+    out += 4;
+    in  += 4;
+  }
+}
+
+/** @} (end addtogroup CRYPTO) */
+/** @} (end addtogroup EM_Library) */
+
+#endif /* defined(CRYPTO_COUNT) && (CRYPTO_COUNT > 0) */

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_dac.c	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_dac.c	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /***************************************************************************//**
  * @file em_dac.c
  * @brief Digital to Analog Coversion (DAC) Peripheral API
- * @version 3.20.12
+ * @version 4.2.1
  *******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
  *******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,12 +30,11 @@
  *
  ******************************************************************************/
 
-
 #include "em_dac.h"
 #if defined(DAC_COUNT) && (DAC_COUNT > 0)
 #include "em_cmu.h"
 #include "em_assert.h"
-#include "em_bitband.h"
+#include "em_bus.h"
 
 /***************************************************************************//**
  * @addtogroup EM_Library
@@ -95,7 +94,7 @@
     reg = &(dac->CH1CTRL);
   }
 
-  BITBAND_Peripheral(reg, _DAC_CH0CTRL_EN_SHIFT, (unsigned int)enable);
+  BUS_RegBitWrite(reg, _DAC_CH0CTRL_EN_SHIFT, enable);
 }
 
 
@@ -123,30 +122,31 @@
   EFM_ASSERT(DAC_REF_VALID(dac));
 
   /* Make sure both channels are disabled. */
-  BITBAND_Peripheral(&(dac->CH0CTRL), _DAC_CH0CTRL_EN_SHIFT, 0);
-  BITBAND_Peripheral(&(dac->CH1CTRL), _DAC_CH0CTRL_EN_SHIFT, 0);
+  BUS_RegBitWrite(&(dac->CH0CTRL), _DAC_CH0CTRL_EN_SHIFT, 0);
+  BUS_RegBitWrite(&(dac->CH1CTRL), _DAC_CH0CTRL_EN_SHIFT, 0);
 
   /* Load proper calibration data depending on selected reference */
   switch (init->reference)
   {
-  case dacRef2V5:
-    dac->CAL = DEVINFO->DAC0CAL1;
-    break;
+    case dacRef2V5:
+      dac->CAL = DEVINFO->DAC0CAL1;
+      break;
 
-  case dacRefVDD:
-    dac->CAL = DEVINFO->DAC0CAL2;
-    break;
+    case dacRefVDD:
+      dac->CAL = DEVINFO->DAC0CAL2;
+      break;
 
-  default: /* 1.25V */
-    dac->CAL = DEVINFO->DAC0CAL0;
-    break;
+    default: /* 1.25V */
+      dac->CAL = DEVINFO->DAC0CAL0;
+      break;
   }
 
-  tmp = ((uint32_t)(init->refresh) << _DAC_CTRL_REFRSEL_SHIFT) |
-        (((uint32_t)(init->prescale) << _DAC_CTRL_PRESC_SHIFT) & _DAC_CTRL_PRESC_MASK) |
-        ((uint32_t)(init->reference) << _DAC_CTRL_REFSEL_SHIFT) |
-        ((uint32_t)(init->outMode) << _DAC_CTRL_OUTMODE_SHIFT) |
-        ((uint32_t)(init->convMode) << _DAC_CTRL_CONVMODE_SHIFT);
+  tmp = ((uint32_t)(init->refresh)     << _DAC_CTRL_REFRSEL_SHIFT)
+        | (((uint32_t)(init->prescale) << _DAC_CTRL_PRESC_SHIFT)
+           & _DAC_CTRL_PRESC_MASK)
+        | ((uint32_t)(init->reference) << _DAC_CTRL_REFSEL_SHIFT)
+        | ((uint32_t)(init->outMode)   << _DAC_CTRL_OUTMODE_SHIFT)
+        | ((uint32_t)(init->convMode)  << _DAC_CTRL_CONVMODE_SHIFT);
 
   if (init->ch0ResetPre)
   {
@@ -245,15 +245,15 @@
 {
   switch(channel)
   {
-  case 0:
-    DAC_Channel0OutputSet(dac, value);
-    break;
-  case 1:
-    DAC_Channel1OutputSet(dac, value);
-    break;
-  default:
-    EFM_ASSERT(0);
-    break;
+    case 0:
+      DAC_Channel0OutputSet(dac, value);
+      break;
+    case 1:
+      DAC_Channel1OutputSet(dac, value);
+      break;
+    default:
+      EFM_ASSERT(0);
+      break;
   }
 }
 
@@ -311,7 +311,7 @@
     ret = _DAC_CTRL_PRESC_MASK >> _DAC_CTRL_PRESC_SHIFT;
   }
 
-  return((uint8_t)ret);
+  return (uint8_t)ret;
 }
 
 

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_dbg.c	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_dbg.c	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /***************************************************************************//**
  * @file em_dbg.c
  * @brief Debug (DBG) Peripheral API
- * @version 3.20.12
+ * @version 4.2.1
  *******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
  *******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -32,7 +32,7 @@
 
 #include "em_dbg.h"
 
-#if defined ( CoreDebug_DHCSR_C_DEBUGEN_Msk )
+#if defined( CoreDebug_DHCSR_C_DEBUGEN_Msk )
 
 #include "em_assert.h"
 #include "em_cmu.h"
@@ -53,7 +53,7 @@
  **************************   GLOBAL FUNCTIONS   *******************************
  ******************************************************************************/
 
-#if defined( GPIO_ROUTE_SWOPEN )
+#if defined( GPIO_ROUTE_SWOPEN ) || defined( GPIO_ROUTEPEN_SWVPEN )
 /***************************************************************************//**
  * @brief
  *   Enable Serial Wire Output (SWO) pin.
@@ -92,8 +92,15 @@
 
   EFM_ASSERT(location < AFCHANLOC_MAX);
 
+#if defined ( AF_DBG_SWO_PORT )
   port = AF_DBG_SWO_PORT(location);
   pin  = AF_DBG_SWO_PIN(location);
+#elif defined (AF_DBG_SWV_PORT )
+  port = AF_DBG_SWV_PORT(location);
+  pin  = AF_DBG_SWV_PIN(location);
+#else
+#warning "AF debug port is not defined."
+#endif
 
   /* Port/pin location not defined for device? */
   if ((pin < 0) || (port < 0))
@@ -116,4 +123,4 @@
 
 /** @} (end addtogroup DBG) */
 /** @} (end addtogroup EM_Library) */
-#endif /* defined ( CoreDebug_DHCSR_C_DEBUGEN_Msk ) */
+#endif /* defined( CoreDebug_DHCSR_C_DEBUGEN_Msk ) */

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_dma.c	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_dma.c	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /***************************************************************************//**
  * @file em_dma.c
  * @brief Direct memory access (DMA) module peripheral API
- * @version 3.20.12
+ * @version 4.2.1
  *******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
  *******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,13 +30,12 @@
  *
  ******************************************************************************/
 
-
 #include "em_dma.h"
 #if defined( DMA_PRESENT )
 
 #include "em_cmu.h"
 #include "em_assert.h"
-#include "em_bitband.h"
+#include "em_bus.h"
 
 /***************************************************************************//**
  * @addtogroup EM_Library
@@ -61,7 +60,7 @@
  *    buffers between memory and peripherals.
  *
  *  A basic understanding of the DMA controller is assumed. Please refer to
- *  the EFM32 reference manual for further details.
+ *  the reference manual for further details.
  *
  *  The term 'descriptor' is used as a synonym to the 'channel control data
  *  structure' term.
@@ -251,9 +250,9 @@
   }
 
   /* Set cycle control */
-  tmp         = descr->CTRL & ~(_DMA_CTRL_CYCLE_CTRL_MASK | _DMA_CTRL_N_MINUS_1_MASK);
-  tmp        |= nMinus1 << _DMA_CTRL_N_MINUS_1_SHIFT;
-  tmp        |= (uint32_t)cycleCtrl << _DMA_CTRL_CYCLE_CTRL_SHIFT;
+  tmp  = descr->CTRL & ~(_DMA_CTRL_CYCLE_CTRL_MASK | _DMA_CTRL_N_MINUS_1_MASK);
+  tmp |= nMinus1 << _DMA_CTRL_N_MINUS_1_SHIFT;
+  tmp |= (uint32_t)cycleCtrl << _DMA_CTRL_CYCLE_CTRL_SHIFT;
   descr->CTRL = tmp;
 }
 
@@ -629,8 +628,8 @@
   cycleCtrl  = altDescr->CTRL & _DMA_CTRL_CYCLE_CTRL_MASK;
   cycleCtrl &= ~(1 << _DMA_CTRL_CYCLE_CTRL_SHIFT);
 
-  EFM_ASSERT((cycleCtrl == dmaCycleCtrlMemScatterGather) ||
-             (cycleCtrl == dmaCycleCtrlPerScatterGather));
+  EFM_ASSERT((cycleCtrl == dmaCycleCtrlMemScatterGather)
+             || (cycleCtrl == dmaCycleCtrlPerScatterGather));
 
   /* Set last alternate descriptor to basic or auto-request cycle type in */
   /* order to have dma_done signal asserted when complete. Otherwise interrupt */
@@ -638,11 +637,13 @@
   altDescr[count - 1].CTRL &= ~_DMA_CTRL_CYCLE_CTRL_MASK;
   if (cycleCtrl == dmaCycleCtrlMemScatterGather)
   {
-    altDescr[count - 1].CTRL |= (uint32_t)dmaCycleCtrlAuto << _DMA_CTRL_CYCLE_CTRL_SHIFT;
+    altDescr[count - 1].CTRL |= (uint32_t)dmaCycleCtrlAuto
+                                << _DMA_CTRL_CYCLE_CTRL_SHIFT;
   }
   else
   {
-    altDescr[count - 1].CTRL |= (uint32_t)dmaCycleCtrlBasic << _DMA_CTRL_CYCLE_CTRL_SHIFT;
+    altDescr[count - 1].CTRL |= (uint32_t)dmaCycleCtrlBasic
+                                << _DMA_CTRL_CYCLE_CTRL_SHIFT;
   }
 
   /* If callback defined, update info on whether callback is issued for */
@@ -656,17 +657,16 @@
   }
 
   /* Configure primary descriptor control word */
-  descr->CTRL =
-    ((uint32_t)dmaDataInc4 << _DMA_CTRL_DST_INC_SHIFT) |
-    ((uint32_t)dmaDataSize4 << _DMA_CTRL_DST_SIZE_SHIFT) |
-    ((uint32_t)dmaDataInc4 << _DMA_CTRL_SRC_INC_SHIFT) |
-    ((uint32_t)dmaDataSize4 << _DMA_CTRL_SRC_SIZE_SHIFT) |
-    /* Use same protection scheme as for alternate descriptors */
-    (altDescr->CTRL & _DMA_CTRL_SRC_PROT_CTRL_MASK) |
-    ((uint32_t)dmaArbitrate4 << _DMA_CTRL_R_POWER_SHIFT) |
-    (((count * 4) - 1) << _DMA_CTRL_N_MINUS_1_SHIFT) |
-    (((uint32_t)useBurst & 1) << _DMA_CTRL_NEXT_USEBURST_SHIFT) |
-    cycleCtrl;
+  descr->CTRL =((uint32_t)dmaDataInc4 << _DMA_CTRL_DST_INC_SHIFT)
+               | ((uint32_t)dmaDataSize4 << _DMA_CTRL_DST_SIZE_SHIFT)
+               | ((uint32_t)dmaDataInc4 << _DMA_CTRL_SRC_INC_SHIFT)
+               | ((uint32_t)dmaDataSize4 << _DMA_CTRL_SRC_SIZE_SHIFT)
+               /* Use same protection scheme as for alternate descriptors */
+               | (altDescr->CTRL & _DMA_CTRL_SRC_PROT_CTRL_MASK)
+               | ((uint32_t)dmaArbitrate4 << _DMA_CTRL_R_POWER_SHIFT)
+               | (((count * 4) - 1) << _DMA_CTRL_N_MINUS_1_SHIFT)
+               | (((uint32_t)useBurst & 1) << _DMA_CTRL_NEXT_USEBURST_SHIFT)
+               | cycleCtrl;
 
   chBit = 1 << channel;
 
@@ -731,11 +731,11 @@
   if (cfg->enableInt)
   {
     DMA->IFC = (1 << channel);
-    BITBAND_Peripheral(&(DMA->IEN), channel, 1);
+    BUS_RegBitWrite(&(DMA->IEN), channel, 1);
   }
   else
   {
-    BITBAND_Peripheral(&(DMA->IEN), channel, 0);
+    BUS_RegBitWrite(&(DMA->IEN), channel, 0);
   }
 }
 
@@ -800,16 +800,15 @@
 
   /* Prepare the descriptor */
   /* Source/destination end addresses set when started */
-  descr->CTRL =
-    (cfg->dstInc << _DMA_CTRL_DST_INC_SHIFT) |
-    (cfg->size << _DMA_CTRL_DST_SIZE_SHIFT) |
-    (cfg->srcInc << _DMA_CTRL_SRC_INC_SHIFT) |
-    (cfg->size << _DMA_CTRL_SRC_SIZE_SHIFT) |
-    ((uint32_t)(cfg->hprot) << _DMA_CTRL_SRC_PROT_CTRL_SHIFT) |
-    (cfg->arbRate << _DMA_CTRL_R_POWER_SHIFT) |
-    (0 << _DMA_CTRL_N_MINUS_1_SHIFT) |         /* Set when activated */
-    (0 << _DMA_CTRL_NEXT_USEBURST_SHIFT) |     /* Set when activated */
-    DMA_CTRL_CYCLE_CTRL_INVALID;               /* Set when activated */
+  descr->CTRL = (cfg->dstInc << _DMA_CTRL_DST_INC_SHIFT)
+                | (cfg->size << _DMA_CTRL_DST_SIZE_SHIFT)
+                | (cfg->srcInc << _DMA_CTRL_SRC_INC_SHIFT)
+                | (cfg->size << _DMA_CTRL_SRC_SIZE_SHIFT)
+                | ((uint32_t)(cfg->hprot) << _DMA_CTRL_SRC_PROT_CTRL_SHIFT)
+                | (cfg->arbRate << _DMA_CTRL_R_POWER_SHIFT)
+                | (0 << _DMA_CTRL_N_MINUS_1_SHIFT)     /* Set when activated */
+                | (0 << _DMA_CTRL_NEXT_USEBURST_SHIFT) /* Set when activated */
+                | DMA_CTRL_CYCLE_CTRL_INVALID;         /* Set when activated */
 }
 
 
@@ -836,12 +835,12 @@
   switch( channel )
   {
   case 0:
-    DMA->LOOP0 = (cfg->enable << _DMA_LOOP0_EN_SHIFT|
-                  cfg->nMinus1 << _DMA_LOOP0_WIDTH_SHIFT);
+    DMA->LOOP0 = (cfg->enable << _DMA_LOOP0_EN_SHIFT)
+                 | (cfg->nMinus1 << _DMA_LOOP0_WIDTH_SHIFT);
     break;
   case 1:
-    DMA->LOOP1 = (cfg->enable << _DMA_LOOP1_EN_SHIFT|
-                  cfg->nMinus1 << _DMA_LOOP1_WIDTH_SHIFT);
+    DMA->LOOP1 = (cfg->enable << _DMA_LOOP1_EN_SHIFT)
+                 | (cfg->nMinus1 << _DMA_LOOP1_WIDTH_SHIFT);
     break;
   }
 }
@@ -868,9 +867,9 @@
   EFM_ASSERT(cfg->height <= 1023);
 
   /* Configure rectangular/2D copy */
-  DMA->RECT0 = (cfg->dstStride << _DMA_RECT0_DSTSTRIDE_SHIFT|
-                cfg->srcStride << _DMA_RECT0_SRCSTRIDE_SHIFT|
-                cfg->height << _DMA_RECT0_HEIGHT_SHIFT);
+  DMA->RECT0 =  (cfg->dstStride << _DMA_RECT0_DSTSTRIDE_SHIFT)
+                | (cfg->srcStride << _DMA_RECT0_SRCSTRIDE_SHIFT)
+                | (cfg->height << _DMA_RECT0_HEIGHT_SHIFT);
 }
 #endif
 
@@ -919,7 +918,8 @@
   }
   else
   {
-    descr->SRCEND = (void *)((uint32_t)(cfg->src) + ((uint32_t)(cfg->nMinus1) << cfg->srcInc));
+    descr->SRCEND = (void *)((uint32_t)(cfg->src)
+                             + ((uint32_t)(cfg->nMinus1) << cfg->srcInc));
   }
 
   if (cfg->dstInc == dmaDataIncNone)
@@ -928,7 +928,8 @@
   }
   else
   {
-    descr->DSTEND = (void *)((uint32_t)(cfg->dst) + ((uint32_t)(cfg->nMinus1) << cfg->dstInc));
+    descr->DSTEND = (void *)((uint32_t)(cfg->dst)
+                             + ((uint32_t)(cfg->nMinus1) << cfg->dstInc));
   }
 
   /* User definable part not used */
@@ -943,20 +944,19 @@
     cycleCtrl = (uint32_t)dmaCycleCtrlMemScatterGather + 1;
   }
 
-  descr->CTRL =
-    (cfg->dstInc << _DMA_CTRL_DST_INC_SHIFT) |
-    (cfg->size << _DMA_CTRL_DST_SIZE_SHIFT) |
-    (cfg->srcInc << _DMA_CTRL_SRC_INC_SHIFT) |
-    (cfg->size << _DMA_CTRL_SRC_SIZE_SHIFT) |
-    ((uint32_t)(cfg->hprot) << _DMA_CTRL_SRC_PROT_CTRL_SHIFT) |
-    (cfg->arbRate << _DMA_CTRL_R_POWER_SHIFT) |
-    ((uint32_t)(cfg->nMinus1) << _DMA_CTRL_N_MINUS_1_SHIFT) |
+  descr->CTRL =(cfg->dstInc << _DMA_CTRL_DST_INC_SHIFT)
+               | (cfg->size << _DMA_CTRL_DST_SIZE_SHIFT)
+               | (cfg->srcInc << _DMA_CTRL_SRC_INC_SHIFT)
+               | (cfg->size << _DMA_CTRL_SRC_SIZE_SHIFT)
+               | ((uint32_t)(cfg->hprot) << _DMA_CTRL_SRC_PROT_CTRL_SHIFT)
+               | (cfg->arbRate << _DMA_CTRL_R_POWER_SHIFT)
+               | ((uint32_t)(cfg->nMinus1) << _DMA_CTRL_N_MINUS_1_SHIFT)
     /* Never set next useburst bit, since the descriptor used after the */
     /* alternate descriptor is the primary descriptor which operates on */
     /* memory. If the alternate descriptors need to have useBurst set, this */
     /* done when setting up the primary descriptor, ie when activating. */
-    (0 << _DMA_CTRL_NEXT_USEBURST_SHIFT) |
-    (cycleCtrl << _DMA_CTRL_CYCLE_CTRL_SHIFT);
+               | (0 << _DMA_CTRL_NEXT_USEBURST_SHIFT)
+               | (cycleCtrl << _DMA_CTRL_CYCLE_CTRL_SHIFT);
 }
 
 
@@ -1062,7 +1062,8 @@
   DMA->CTRLBASE = (uint32_t)(init->controlBlock);
 
   /* Configure and enable the DMA controller */
-  DMA->CONFIG = ((uint32_t)(init->hprot) << _DMA_CONFIG_CHPROT_SHIFT) | DMA_CONFIG_EN;
+  DMA->CONFIG = ((uint32_t)(init->hprot) << _DMA_CONFIG_CHPROT_SHIFT)
+                | DMA_CONFIG_EN;
 }
 
 
@@ -1181,9 +1182,9 @@
   }
 
   /* Set cycle control */
-  tmp         = descr->CTRL & ~(_DMA_CTRL_CYCLE_CTRL_MASK | _DMA_CTRL_N_MINUS_1_MASK);
-  tmp        |= nMinus1 << _DMA_CTRL_N_MINUS_1_SHIFT;
-  tmp        |= cycleCtrl << _DMA_CTRL_CYCLE_CTRL_SHIFT;
+  tmp  = descr->CTRL & ~(_DMA_CTRL_CYCLE_CTRL_MASK | _DMA_CTRL_N_MINUS_1_MASK);
+  tmp |= nMinus1 << _DMA_CTRL_N_MINUS_1_SHIFT;
+  tmp |= cycleCtrl << _DMA_CTRL_CYCLE_CTRL_SHIFT;
   descr->CTRL = tmp;
 }
 

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_ebi.c	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_ebi.c	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /***************************************************************************//**
  * @file em_ebi.c
  * @brief External Bus Interface (EBI) Peripheral API
- * @version 3.20.12
+ * @version 4.2.1
  *******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
  *******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,11 +30,10 @@
  *
  ******************************************************************************/
 
-
 #include "em_ebi.h"
 #if defined(EBI_COUNT) && (EBI_COUNT > 0)
 #include "em_assert.h"
-#include "em_bitband.h"
+#include "em_bus.h"
 
 /***************************************************************************//**
  * @addtogroup EM_Library
@@ -95,85 +94,85 @@
 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
   if (ebiInit->banks & EBI_BANK0)
   {
-    ctrl &= ~(_EBI_CTRL_MODE_MASK|
-              _EBI_CTRL_ARDYEN_MASK|
-              _EBI_CTRL_ARDYTODIS_MASK|
-              _EBI_CTRL_BL_MASK|
-              _EBI_CTRL_NOIDLE_MASK|
-              _EBI_CTRL_BANK0EN_MASK);
+    ctrl &= ~(_EBI_CTRL_MODE_MASK
+              | _EBI_CTRL_ARDYEN_MASK
+              | _EBI_CTRL_ARDYTODIS_MASK
+              | _EBI_CTRL_BL_MASK
+              | _EBI_CTRL_NOIDLE_MASK
+              | _EBI_CTRL_BANK0EN_MASK);
     ctrl |= (ebiInit->mode << _EBI_CTRL_MODE_SHIFT);
     ctrl |= (ebiInit->ardyEnable << _EBI_CTRL_ARDYEN_SHIFT);
     ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTODIS_SHIFT);
     ctrl |= (ebiInit->blEnable << _EBI_CTRL_BL_SHIFT);
     ctrl |= (ebiInit->noIdle << _EBI_CTRL_NOIDLE_SHIFT);
-    if ( ebiInit->enable) 
+    if ( ebiInit->enable)
     {
       ctrl |= EBI_CTRL_BANK0EN;
     }
   }
   if (ebiInit->banks & EBI_BANK1)
   {
-    ctrl &= ~(_EBI_CTRL_BL1_MASK|
-              _EBI_CTRL_MODE1_MASK|
-              _EBI_CTRL_ARDY1EN_MASK|
-              _EBI_CTRL_ARDYTO1DIS_MASK|
-              _EBI_CTRL_NOIDLE1_MASK|
-              _EBI_CTRL_BANK1EN_MASK); 
+    ctrl &= ~(_EBI_CTRL_BL1_MASK
+              | _EBI_CTRL_MODE1_MASK
+              | _EBI_CTRL_ARDY1EN_MASK
+              | _EBI_CTRL_ARDYTO1DIS_MASK
+              | _EBI_CTRL_NOIDLE1_MASK
+              | _EBI_CTRL_BANK1EN_MASK);
     ctrl |= (ebiInit->mode << _EBI_CTRL_MODE1_SHIFT);
     ctrl |= (ebiInit->ardyEnable << _EBI_CTRL_ARDY1EN_SHIFT);
     ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTO1DIS_SHIFT);
     ctrl |= (ebiInit->blEnable << _EBI_CTRL_BL1_SHIFT);
     ctrl |= (ebiInit->noIdle << _EBI_CTRL_NOIDLE1_SHIFT);
-    if ( ebiInit->enable) 
+    if ( ebiInit->enable)
     {
       ctrl |= EBI_CTRL_BANK1EN;
     }
   }
   if (ebiInit->banks & EBI_BANK2)
   {
-    ctrl &= ~(_EBI_CTRL_BL2_MASK|
-              _EBI_CTRL_MODE2_MASK|
-              _EBI_CTRL_ARDY2EN_MASK|
-              _EBI_CTRL_ARDYTO2DIS_MASK|
-              _EBI_CTRL_NOIDLE2_MASK|
-              _EBI_CTRL_BANK2EN_MASK);
+    ctrl &= ~(_EBI_CTRL_BL2_MASK
+              | _EBI_CTRL_MODE2_MASK
+              | _EBI_CTRL_ARDY2EN_MASK
+              | _EBI_CTRL_ARDYTO2DIS_MASK
+              | _EBI_CTRL_NOIDLE2_MASK
+              | _EBI_CTRL_BANK2EN_MASK);
     ctrl |= (ebiInit->mode << _EBI_CTRL_MODE2_SHIFT);
     ctrl |= (ebiInit->ardyEnable << _EBI_CTRL_ARDY2EN_SHIFT);
     ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTO2DIS_SHIFT);
     ctrl |= (ebiInit->blEnable << _EBI_CTRL_BL2_SHIFT);
     ctrl |= (ebiInit->noIdle << _EBI_CTRL_NOIDLE2_SHIFT);
-    if ( ebiInit->enable) 
+    if ( ebiInit->enable)
     {
       ctrl |= EBI_CTRL_BANK2EN;
     }
   }
   if (ebiInit->banks & EBI_BANK3)
   {
-    ctrl &= ~(_EBI_CTRL_BL3_MASK|
-              _EBI_CTRL_MODE3_MASK|
-              _EBI_CTRL_ARDY3EN_MASK|
-              _EBI_CTRL_ARDYTO3DIS_MASK|
-              _EBI_CTRL_NOIDLE3_MASK|
-              _EBI_CTRL_BANK3EN_MASK); 
+    ctrl &= ~(_EBI_CTRL_BL3_MASK
+              | _EBI_CTRL_MODE3_MASK
+              | _EBI_CTRL_ARDY3EN_MASK
+              | _EBI_CTRL_ARDYTO3DIS_MASK
+              | _EBI_CTRL_NOIDLE3_MASK
+              | _EBI_CTRL_BANK3EN_MASK);
     ctrl |= (ebiInit->mode << _EBI_CTRL_MODE3_SHIFT);
     ctrl |= (ebiInit->ardyEnable << _EBI_CTRL_ARDY3EN_SHIFT);
     ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTO3DIS_SHIFT);
     ctrl |= (ebiInit->blEnable << _EBI_CTRL_BL3_SHIFT);
     ctrl |= (ebiInit->noIdle << _EBI_CTRL_NOIDLE3_SHIFT);
-    if ( ebiInit->enable) 
+    if ( ebiInit->enable)
     {
       ctrl |= EBI_CTRL_BANK3EN;
     }
   }
 #else
-  ctrl &= ~(_EBI_CTRL_MODE_MASK|
-            _EBI_CTRL_ARDYEN_MASK|
-            _EBI_CTRL_ARDYTODIS_MASK|
-            _EBI_CTRL_BANK0EN_MASK|
-            _EBI_CTRL_BANK1EN_MASK|
-            _EBI_CTRL_BANK2EN_MASK|
-            _EBI_CTRL_BANK3EN_MASK);
-  if ( ebiInit->enable) 
+  ctrl &= ~(_EBI_CTRL_MODE_MASK
+            | _EBI_CTRL_ARDYEN_MASK
+            | _EBI_CTRL_ARDYTODIS_MASK
+            | _EBI_CTRL_BANK0EN_MASK
+            | _EBI_CTRL_BANK1EN_MASK
+            | _EBI_CTRL_BANK2EN_MASK
+            | _EBI_CTRL_BANK3EN_MASK);
+  if ( ebiInit->enable)
   {
     if ( ebiInit->banks & EBI_BANK0 )
     {
@@ -231,23 +230,23 @@
 #endif
 
   /* Activate new configuration */
-  EBI->CTRL = ctrl;  
+  EBI->CTRL = ctrl;
 
   /* Configure Adress Latch Enable */
   switch (ebiInit->mode)
   {
-  case ebiModeD16A16ALE:
-  case ebiModeD8A24ALE:
-    /* Address Latch Enable */
-    BITBAND_Peripheral(&(EBI->ROUTE), _EBI_ROUTE_ALEPEN_SHIFT, 1);
-    break;
+    case ebiModeD16A16ALE:
+    case ebiModeD8A24ALE:
+      /* Address Latch Enable */
+      BUS_RegBitWrite(&(EBI->ROUTE), _EBI_ROUTE_ALEPEN_SHIFT, 1);
+      break;
 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
-  case ebiModeD16:
+    case ebiModeD16:
 #endif
-  case ebiModeD8A8:
-    /* Make sure Address Latch is disabled */
-    BITBAND_Peripheral(&(EBI->ROUTE), _EBI_ROUTE_ALEPEN_SHIFT, 0);
-    break;
+    case ebiModeD8A8:
+      /* Make sure Address Latch is disabled */
+      BUS_RegBitWrite(&(EBI->ROUTE), _EBI_ROUTE_ALEPEN_SHIFT, 0);
+      break;
   }
 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
   /* Limit pin enable */
@@ -259,11 +258,11 @@
   /* Enable EBI BL pin if necessary */
   if(ctrl & (_EBI_CTRL_BL_MASK|_EBI_CTRL_BL1_MASK|_EBI_CTRL_BL2_MASK|_EBI_CTRL_BL3_MASK))
   {
-    BITBAND_Peripheral(&(EBI->ROUTE), _EBI_ROUTE_BLPEN_SHIFT, ebiInit->blEnable);
+    BUS_RegBitWrite(&(EBI->ROUTE), _EBI_ROUTE_BLPEN_SHIFT, ebiInit->blEnable);
   }
 #endif
   /* Enable EBI pins EBI_WEn and EBI_REn */
-  BITBAND_Peripheral(&(EBI->ROUTE), _EBI_ROUTE_EBIPEN_SHIFT, 1);
+  BUS_RegBitWrite(&(EBI->ROUTE), _EBI_ROUTE_EBIPEN_SHIFT, 1);
 
   /* Enable chip select lines */
   EBI_ChipSelectEnable(ebiInit->csLines, true);
@@ -297,19 +296,19 @@
 {
   if (banks & EBI_BANK0)
   {
-    BITBAND_Peripheral(&(EBI->CTRL), _EBI_CTRL_BANK0EN_SHIFT, enable);
+    BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_BANK0EN_SHIFT, enable);
   }
   if (banks & EBI_BANK1)
   {
-    BITBAND_Peripheral(&(EBI->CTRL), _EBI_CTRL_BANK1EN_SHIFT, enable);
+    BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_BANK1EN_SHIFT, enable);
   }
   if (banks & EBI_BANK2)
   {
-    BITBAND_Peripheral(&(EBI->CTRL), _EBI_CTRL_BANK2EN_SHIFT, enable);
+    BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_BANK2EN_SHIFT, enable);
   }
   if (banks & EBI_BANK3)
   {
-    BITBAND_Peripheral(&(EBI->CTRL), _EBI_CTRL_BANK3EN_SHIFT, enable);
+    BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_BANK3EN_SHIFT, enable);
   }
 }
 
@@ -331,41 +330,41 @@
   {
     switch (bank)
     {
-    case EBI_BANK0:
-      return(EBI_MEM_BASE);
+      case EBI_BANK0:
+        return(EBI_MEM_BASE);
 
-    case EBI_BANK1:
-      return(EBI_MEM_BASE + 0x10000000UL);
+      case EBI_BANK1:
+        return(EBI_MEM_BASE + 0x10000000UL);
 
-    case EBI_BANK2:
-      return(EBI_MEM_BASE + 0x20000000UL);
+      case EBI_BANK2:
+        return(EBI_MEM_BASE + 0x20000000UL);
 
-    case EBI_BANK3:
-      return(EBI_MEM_BASE + 0x30000000UL);
+      case EBI_BANK3:
+        return(EBI_MEM_BASE + 0x30000000UL);
 
-    default:
-      EFM_ASSERT(0);
-      break;
+      default:
+        EFM_ASSERT(0);
+        break;
     }
   }
 #endif
   switch (bank)
   {
-  case EBI_BANK0:
-    return(EBI_MEM_BASE);
+    case EBI_BANK0:
+      return(EBI_MEM_BASE);
 
-  case EBI_BANK1:
-    return(EBI_MEM_BASE + 0x04000000UL);
+    case EBI_BANK1:
+      return(EBI_MEM_BASE + 0x04000000UL);
 
-  case EBI_BANK2:
-    return(EBI_MEM_BASE + 0x08000000UL);
+    case EBI_BANK2:
+      return(EBI_MEM_BASE + 0x08000000UL);
 
-  case EBI_BANK3:
-    return(EBI_MEM_BASE + 0x0C000000UL);
+    case EBI_BANK3:
+      return(EBI_MEM_BASE + 0x0C000000UL);
 
-  default:
-    EFM_ASSERT(0);
-    break;
+    default:
+      EFM_ASSERT(0);
+      break;
   }
   return 0;
 }
@@ -385,19 +384,19 @@
 {
   if (cs & EBI_CS0)
   {
-    BITBAND_Peripheral(&(EBI->ROUTE), _EBI_ROUTE_CS0PEN_SHIFT, enable);
+    BUS_RegBitWrite(&(EBI->ROUTE), _EBI_ROUTE_CS0PEN_SHIFT, enable);
   }
   if (cs & EBI_CS1)
   {
-    BITBAND_Peripheral(&(EBI->ROUTE), _EBI_ROUTE_CS1PEN_SHIFT, enable);
+    BUS_RegBitWrite(&(EBI->ROUTE), _EBI_ROUTE_CS1PEN_SHIFT, enable);
   }
   if (cs & EBI_CS2)
   {
-    BITBAND_Peripheral(&(EBI->ROUTE), _EBI_ROUTE_CS2PEN_SHIFT, enable);
+    BUS_RegBitWrite(&(EBI->ROUTE), _EBI_ROUTE_CS2PEN_SHIFT, enable);
   }
   if (cs & EBI_CS3)
   {
-    BITBAND_Peripheral(&(EBI->ROUTE), _EBI_ROUTE_CS3PEN_SHIFT, enable);
+    BUS_RegBitWrite(&(EBI->ROUTE), _EBI_ROUTE_CS3PEN_SHIFT, enable);
   }
 }
 
@@ -416,44 +415,44 @@
 {
   switch (line)
   {
-  case ebiLineARDY:
-    BITBAND_Peripheral(&(EBI->POLARITY), _EBI_POLARITY_ARDYPOL_SHIFT, polarity);
-    break;
-  case ebiLineALE:
-    BITBAND_Peripheral(&(EBI->POLARITY), _EBI_POLARITY_ALEPOL_SHIFT, polarity);
-    break;
-  case ebiLineWE:
-    BITBAND_Peripheral(&(EBI->POLARITY), _EBI_POLARITY_WEPOL_SHIFT, polarity);
-    break;
-  case ebiLineRE:
-    BITBAND_Peripheral(&(EBI->POLARITY), _EBI_POLARITY_REPOL_SHIFT, polarity);
-    break;
-  case ebiLineCS:
-    BITBAND_Peripheral(&(EBI->POLARITY), _EBI_POLARITY_CSPOL_SHIFT, polarity);
-    break;
+    case ebiLineARDY:
+      BUS_RegBitWrite(&(EBI->POLARITY), _EBI_POLARITY_ARDYPOL_SHIFT, polarity);
+      break;
+    case ebiLineALE:
+      BUS_RegBitWrite(&(EBI->POLARITY), _EBI_POLARITY_ALEPOL_SHIFT, polarity);
+      break;
+    case ebiLineWE:
+      BUS_RegBitWrite(&(EBI->POLARITY), _EBI_POLARITY_WEPOL_SHIFT, polarity);
+      break;
+    case ebiLineRE:
+      BUS_RegBitWrite(&(EBI->POLARITY), _EBI_POLARITY_REPOL_SHIFT, polarity);
+      break;
+    case ebiLineCS:
+      BUS_RegBitWrite(&(EBI->POLARITY), _EBI_POLARITY_CSPOL_SHIFT, polarity);
+      break;
 #if defined (_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
-  case ebiLineBL:
-    BITBAND_Peripheral(&(EBI->POLARITY), _EBI_POLARITY_BLPOL_SHIFT, polarity);
-    break;
-  case ebiLineTFTVSync:
-    BITBAND_Peripheral(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_VSYNCPOL_SHIFT, polarity);
-    break;
-  case ebiLineTFTHSync:
-    BITBAND_Peripheral(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_HSYNCPOL_SHIFT, polarity);
-    break;
-  case ebiLineTFTDataEn:
-    BITBAND_Peripheral(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_DATAENPOL_SHIFT, polarity);
-    break;
-  case ebiLineTFTDClk:
-    BITBAND_Peripheral(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_DCLKPOL_SHIFT, polarity);
-    break;
-  case ebiLineTFTCS:
-    BITBAND_Peripheral(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_CSPOL_SHIFT, polarity);
-    break;
+    case ebiLineBL:
+      BUS_RegBitWrite(&(EBI->POLARITY), _EBI_POLARITY_BLPOL_SHIFT, polarity);
+      break;
+    case ebiLineTFTVSync:
+      BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_VSYNCPOL_SHIFT, polarity);
+      break;
+    case ebiLineTFTHSync:
+      BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_HSYNCPOL_SHIFT, polarity);
+      break;
+    case ebiLineTFTDataEn:
+      BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_DATAENPOL_SHIFT, polarity);
+      break;
+    case ebiLineTFTDClk:
+      BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_DCLKPOL_SHIFT, polarity);
+      break;
+    case ebiLineTFTCS:
+      BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_CSPOL_SHIFT, polarity);
+      break;
 #endif
-  default:
-    EFM_ASSERT(0);
-    break;
+    default:
+      EFM_ASSERT(0);
+      break;
   }
 }
 
@@ -482,15 +481,16 @@
   EFM_ASSERT(holdCycles < 4);
 
   /* Configure timing values */
-  readTiming = (setupCycles << _EBI_RDTIMING_RDSETUP_SHIFT) |
-               (strobeCycles << _EBI_RDTIMING_RDSTRB_SHIFT) |
-               (holdCycles << _EBI_RDTIMING_RDHOLD_SHIFT);
+  readTiming = (setupCycles << _EBI_RDTIMING_RDSETUP_SHIFT)
+               | (strobeCycles << _EBI_RDTIMING_RDSTRB_SHIFT)
+               | (holdCycles << _EBI_RDTIMING_RDHOLD_SHIFT);
 
 
-  EBI->RDTIMING = (EBI->RDTIMING &
-                   ~(_EBI_RDTIMING_RDSETUP_MASK |
-                     _EBI_RDTIMING_RDSTRB_MASK |
-                     _EBI_RDTIMING_RDHOLD_MASK)) | readTiming;
+  EBI->RDTIMING = (EBI->RDTIMING
+                   & ~(_EBI_RDTIMING_RDSETUP_MASK
+                       | _EBI_RDTIMING_RDSTRB_MASK
+                       | _EBI_RDTIMING_RDHOLD_MASK))
+                  | readTiming;
 }
 
 
@@ -517,14 +517,15 @@
   EFM_ASSERT(holdCycles < 4);
 
   /* Configure timing values */
-  writeTiming = (setupCycles << _EBI_WRTIMING_WRSETUP_SHIFT) |
-                (strobeCycles << _EBI_WRTIMING_WRSTRB_SHIFT) |
-                (holdCycles << _EBI_WRTIMING_WRHOLD_SHIFT);
+  writeTiming = (setupCycles << _EBI_WRTIMING_WRSETUP_SHIFT)
+                | (strobeCycles << _EBI_WRTIMING_WRSTRB_SHIFT)
+                | (holdCycles << _EBI_WRTIMING_WRHOLD_SHIFT);
 
-  EBI->WRTIMING = (EBI->WRTIMING &
-                   ~(_EBI_WRTIMING_WRSETUP_MASK |
-                     _EBI_WRTIMING_WRSTRB_MASK |
-                     _EBI_WRTIMING_WRHOLD_MASK)) | writeTiming;
+  EBI->WRTIMING = (EBI->WRTIMING
+                   & ~(_EBI_WRTIMING_WRSETUP_MASK
+                       | _EBI_WRTIMING_WRSTRB_MASK
+                       | _EBI_WRTIMING_WRHOLD_MASK))
+                  | writeTiming;
 }
 
 
@@ -548,12 +549,13 @@
   EFM_ASSERT(holdCycles < 4);
 
   /* Configure address latch timing values */
-  addressLatchTiming = (setupCycles << _EBI_ADDRTIMING_ADDRSETUP_SHIFT) |
-                       (holdCycles << _EBI_ADDRTIMING_ADDRHOLD_SHIFT);
+  addressLatchTiming = (setupCycles << _EBI_ADDRTIMING_ADDRSETUP_SHIFT)
+                       | (holdCycles << _EBI_ADDRTIMING_ADDRHOLD_SHIFT);
 
-  EBI->ADDRTIMING = (EBI->ADDRTIMING &
-                     ~(_EBI_ADDRTIMING_ADDRSETUP_MASK |
-                       _EBI_ADDRTIMING_ADDRHOLD_MASK)) | addressLatchTiming;
+  EBI->ADDRTIMING = (EBI->ADDRTIMING
+                     & ~(_EBI_ADDRTIMING_ADDRSETUP_MASK
+                         | _EBI_ADDRTIMING_ADDRHOLD_MASK))
+                    | addressLatchTiming;
 }
 
 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
@@ -595,22 +597,22 @@
   EBI_PolaritySet(ebiLineTFTHSync, ebiTFTInit->hsyncPolarity);
 
   /* Main control, EBI bank select, mask and blending configuration */
-  ctrl =
-    (uint32_t)(ebiTFTInit->bank) |
-    (uint32_t)(ebiTFTInit->width) |
-    (uint32_t)(ebiTFTInit->colSrc) |
-    (uint32_t)(ebiTFTInit->interleave) |
-    (uint32_t)(ebiTFTInit->fbTrigger) |
-    (uint32_t)(ebiTFTInit->shiftDClk == true ? (1 << _EBI_TFTCTRL_SHIFTDCLKEN_SHIFT) : 0) |
-    (uint32_t)(ebiTFTInit->maskBlend) |
-    (uint32_t)(ebiTFTInit->driveMode);
+  ctrl = (uint32_t)ebiTFTInit->bank
+         | (uint32_t)ebiTFTInit->width
+         | (uint32_t)ebiTFTInit->colSrc
+         | (uint32_t)ebiTFTInit->interleave
+         | (uint32_t)ebiTFTInit->fbTrigger
+         | (uint32_t)(ebiTFTInit->shiftDClk == true
+                      ? (1 << _EBI_TFTCTRL_SHIFTDCLKEN_SHIFT) : 0)
+         | (uint32_t)ebiTFTInit->maskBlend
+         | (uint32_t)ebiTFTInit->driveMode;
 
   EBI->TFTCTRL = ctrl;
 
   /* Enable TFT pins */
   if (ebiTFTInit->driveMode != ebiTFTDDModeDisabled)
   {
-    EBI->ROUTE |= (EBI_ROUTE_TFTPEN);
+    EBI->ROUTE |= EBI_ROUTE_TFTPEN;
   }
 }
 
@@ -629,8 +631,8 @@
   EFM_ASSERT((horizontal-1) < 1024);
   EFM_ASSERT((vertical-1) < 1024);
 
-  EBI->TFTSIZE = ((horizontal-1) << _EBI_TFTSIZE_HSZ_SHIFT) |
-    ((vertical-1) << _EBI_TFTSIZE_VSZ_SHIFT);
+  EBI->TFTSIZE = ((horizontal-1) << _EBI_TFTSIZE_HSZ_SHIFT)
+                 | ((vertical-1) << _EBI_TFTSIZE_VSZ_SHIFT);
 }
 
 /***************************************************************************//**
@@ -650,9 +652,9 @@
   EFM_ASSERT(back < 256);
   EFM_ASSERT((pulseWidth-1) < 128);
 
-  EBI->TFTHPORCH = (front << _EBI_TFTHPORCH_HFPORCH_SHIFT) |
-                   (back << _EBI_TFTHPORCH_HBPORCH_SHIFT) |
-                   ((pulseWidth-1) << _EBI_TFTHPORCH_HSYNC_SHIFT);
+  EBI->TFTHPORCH = (front << _EBI_TFTHPORCH_HFPORCH_SHIFT)
+                   | (back << _EBI_TFTHPORCH_HBPORCH_SHIFT)
+                   | ((pulseWidth-1) << _EBI_TFTHPORCH_HSYNC_SHIFT);
 }
 
 
@@ -673,9 +675,9 @@
   EFM_ASSERT(back < 256);
   EFM_ASSERT((pulseWidth-1) < 128);
 
-  EBI->TFTVPORCH = (front << _EBI_TFTVPORCH_VFPORCH_SHIFT) |
-                   (back << _EBI_TFTVPORCH_VBPORCH_SHIFT) |
-                   ((pulseWidth-1) << _EBI_TFTVPORCH_VSYNC_SHIFT);
+  EBI->TFTVPORCH = (front << _EBI_TFTVPORCH_VFPORCH_SHIFT)
+                   | (back << _EBI_TFTVPORCH_VBPORCH_SHIFT)
+                   | ((pulseWidth-1) << _EBI_TFTVPORCH_VSYNC_SHIFT);
 }
 
 
@@ -702,10 +704,10 @@
   EFM_ASSERT(setup < 4);
   EFM_ASSERT(hold < 4);
 
-  EBI->TFTTIMING = (dclkPeriod << _EBI_TFTTIMING_DCLKPERIOD_SHIFT) |
-                   (start << _EBI_TFTTIMING_TFTSTART_SHIFT) |
-                   (setup << _EBI_TFTTIMING_TFTSETUP_SHIFT) |
-                   (hold << _EBI_TFTTIMING_TFTHOLD_SHIFT);
+  EBI->TFTTIMING = (dclkPeriod << _EBI_TFTTIMING_DCLKPERIOD_SHIFT)
+                   | (start << _EBI_TFTTIMING_TFTSTART_SHIFT)
+                   | (setup << _EBI_TFTTIMING_TFTSETUP_SHIFT)
+                   | (hold << _EBI_TFTTIMING_TFTHOLD_SHIFT);
 }
 #endif
 
@@ -734,27 +736,27 @@
   /* Configure read operation parameters */
   if( banks & EBI_BANK0 )
   {
-    BITBAND_Peripheral(&EBI->RDTIMING, _EBI_RDTIMING_PAGEMODE_SHIFT, pageMode);
-    BITBAND_Peripheral(&EBI->RDTIMING, _EBI_RDTIMING_PREFETCH_SHIFT, prefetch);
-    BITBAND_Peripheral(&EBI->RDTIMING, _EBI_RDTIMING_HALFRE_SHIFT, halfRE);
+    BUS_RegBitWrite(&EBI->RDTIMING, _EBI_RDTIMING_PAGEMODE_SHIFT, pageMode);
+    BUS_RegBitWrite(&EBI->RDTIMING, _EBI_RDTIMING_PREFETCH_SHIFT, prefetch);
+    BUS_RegBitWrite(&EBI->RDTIMING, _EBI_RDTIMING_HALFRE_SHIFT, halfRE);
   }
   if( banks & EBI_BANK1 )
   {
-    BITBAND_Peripheral(&EBI->RDTIMING1, _EBI_RDTIMING_PAGEMODE_SHIFT, pageMode);
-    BITBAND_Peripheral(&EBI->RDTIMING1, _EBI_RDTIMING_PREFETCH_SHIFT, prefetch);
-    BITBAND_Peripheral(&EBI->RDTIMING1, _EBI_RDTIMING_HALFRE_SHIFT, halfRE);
+    BUS_RegBitWrite(&EBI->RDTIMING1, _EBI_RDTIMING_PAGEMODE_SHIFT, pageMode);
+    BUS_RegBitWrite(&EBI->RDTIMING1, _EBI_RDTIMING_PREFETCH_SHIFT, prefetch);
+    BUS_RegBitWrite(&EBI->RDTIMING1, _EBI_RDTIMING_HALFRE_SHIFT, halfRE);
   }
   if( banks & EBI_BANK2 )
   {
-    BITBAND_Peripheral(&EBI->RDTIMING2, _EBI_RDTIMING_PAGEMODE_SHIFT, pageMode);
-    BITBAND_Peripheral(&EBI->RDTIMING2, _EBI_RDTIMING_PREFETCH_SHIFT, prefetch);
-    BITBAND_Peripheral(&EBI->RDTIMING2, _EBI_RDTIMING_HALFRE_SHIFT, halfRE);
+    BUS_RegBitWrite(&EBI->RDTIMING2, _EBI_RDTIMING_PAGEMODE_SHIFT, pageMode);
+    BUS_RegBitWrite(&EBI->RDTIMING2, _EBI_RDTIMING_PREFETCH_SHIFT, prefetch);
+    BUS_RegBitWrite(&EBI->RDTIMING2, _EBI_RDTIMING_HALFRE_SHIFT, halfRE);
   }
   if( banks & EBI_BANK3 )
   {
-    BITBAND_Peripheral(&EBI->RDTIMING3, _EBI_RDTIMING_PAGEMODE_SHIFT, pageMode);
-    BITBAND_Peripheral(&EBI->RDTIMING3, _EBI_RDTIMING_PREFETCH_SHIFT, prefetch);
-    BITBAND_Peripheral(&EBI->RDTIMING3, _EBI_RDTIMING_HALFRE_SHIFT, halfRE);
+    BUS_RegBitWrite(&EBI->RDTIMING3, _EBI_RDTIMING_PAGEMODE_SHIFT, pageMode);
+    BUS_RegBitWrite(&EBI->RDTIMING3, _EBI_RDTIMING_PREFETCH_SHIFT, prefetch);
+    BUS_RegBitWrite(&EBI->RDTIMING3, _EBI_RDTIMING_HALFRE_SHIFT, halfRE);
   }
 }
 
@@ -788,37 +790,41 @@
   EFM_ASSERT(holdCycles < 4);
 
   /* Configure timing values */
-  readTiming = (setupCycles << _EBI_RDTIMING_RDSETUP_SHIFT) |
-               (strobeCycles << _EBI_RDTIMING_RDSTRB_SHIFT) |
-               (holdCycles << _EBI_RDTIMING_RDHOLD_SHIFT);
+  readTiming = (setupCycles << _EBI_RDTIMING_RDSETUP_SHIFT)
+               | (strobeCycles << _EBI_RDTIMING_RDSTRB_SHIFT)
+               | (holdCycles << _EBI_RDTIMING_RDHOLD_SHIFT);
 
   if (banks & EBI_BANK0)
   {
-    EBI->RDTIMING = (EBI->RDTIMING &
-                     ~(_EBI_RDTIMING_RDSETUP_MASK |
-                       _EBI_RDTIMING_RDSTRB_MASK |
-                       _EBI_RDTIMING_RDHOLD_MASK)) | readTiming;
+    EBI->RDTIMING = (EBI->RDTIMING
+                     & ~(_EBI_RDTIMING_RDSETUP_MASK
+                         | _EBI_RDTIMING_RDSTRB_MASK
+                         | _EBI_RDTIMING_RDHOLD_MASK))
+                    | readTiming;
   }
   if (banks & EBI_BANK1)
   {
-    EBI->RDTIMING1 = (EBI->RDTIMING1 &
-                      ~(_EBI_RDTIMING1_RDSETUP_MASK |
-                        _EBI_RDTIMING1_RDSTRB_MASK |
-                        _EBI_RDTIMING1_RDHOLD_MASK)) | readTiming;
+    EBI->RDTIMING1 = (EBI->RDTIMING1
+                      & ~(_EBI_RDTIMING1_RDSETUP_MASK
+                           | _EBI_RDTIMING1_RDSTRB_MASK
+                           | _EBI_RDTIMING1_RDHOLD_MASK))
+                     | readTiming;
   }
   if (banks & EBI_BANK2)
   {
-    EBI->RDTIMING2 = (EBI->RDTIMING2 &
-                      ~(_EBI_RDTIMING2_RDSETUP_MASK |
-                        _EBI_RDTIMING2_RDSTRB_MASK |
-                        _EBI_RDTIMING2_RDHOLD_MASK)) | readTiming;
+    EBI->RDTIMING2 = (EBI->RDTIMING2
+                      & ~(_EBI_RDTIMING2_RDSETUP_MASK
+                          | _EBI_RDTIMING2_RDSTRB_MASK
+                          | _EBI_RDTIMING2_RDHOLD_MASK))
+                     | readTiming;
   }
   if (banks & EBI_BANK3)
   {
-    EBI->RDTIMING3 = (EBI->RDTIMING3 &
-                      ~(_EBI_RDTIMING3_RDSETUP_MASK |
-                        _EBI_RDTIMING3_RDSTRB_MASK |
-                        _EBI_RDTIMING3_RDHOLD_MASK)) | readTiming;
+    EBI->RDTIMING3 = (EBI->RDTIMING3
+                      & ~(_EBI_RDTIMING3_RDSETUP_MASK
+                          | _EBI_RDTIMING3_RDSTRB_MASK
+                          | _EBI_RDTIMING3_RDHOLD_MASK))
+                     | readTiming;
   }
 }
 
@@ -844,23 +850,23 @@
   /* Configure write operation parameters */
   if( banks & EBI_BANK0 )
   {
-    BITBAND_Peripheral(&EBI->WRTIMING, _EBI_WRTIMING_WBUFDIS_SHIFT, writeBufDisable);
-    BITBAND_Peripheral(&EBI->WRTIMING, _EBI_WRTIMING_HALFWE_SHIFT, halfWE);
+    BUS_RegBitWrite(&EBI->WRTIMING, _EBI_WRTIMING_WBUFDIS_SHIFT, writeBufDisable);
+    BUS_RegBitWrite(&EBI->WRTIMING, _EBI_WRTIMING_HALFWE_SHIFT, halfWE);
   }
   if( banks & EBI_BANK1 )
   {
-    BITBAND_Peripheral(&EBI->WRTIMING1, _EBI_WRTIMING_WBUFDIS_SHIFT, writeBufDisable);
-    BITBAND_Peripheral(&EBI->WRTIMING1, _EBI_WRTIMING_HALFWE_SHIFT, halfWE);
+    BUS_RegBitWrite(&EBI->WRTIMING1, _EBI_WRTIMING_WBUFDIS_SHIFT, writeBufDisable);
+    BUS_RegBitWrite(&EBI->WRTIMING1, _EBI_WRTIMING_HALFWE_SHIFT, halfWE);
   }
   if( banks & EBI_BANK2 )
   {
-    BITBAND_Peripheral(&EBI->WRTIMING2, _EBI_WRTIMING_WBUFDIS_SHIFT, writeBufDisable);
-    BITBAND_Peripheral(&EBI->WRTIMING2, _EBI_WRTIMING_HALFWE_SHIFT, halfWE);
+    BUS_RegBitWrite(&EBI->WRTIMING2, _EBI_WRTIMING_WBUFDIS_SHIFT, writeBufDisable);
+    BUS_RegBitWrite(&EBI->WRTIMING2, _EBI_WRTIMING_HALFWE_SHIFT, halfWE);
   }
   if( banks & EBI_BANK3 )
   {
-    BITBAND_Peripheral(&EBI->WRTIMING3, _EBI_WRTIMING_WBUFDIS_SHIFT, writeBufDisable);
-    BITBAND_Peripheral(&EBI->WRTIMING3, _EBI_WRTIMING_HALFWE_SHIFT, halfWE);
+    BUS_RegBitWrite(&EBI->WRTIMING3, _EBI_WRTIMING_WBUFDIS_SHIFT, writeBufDisable);
+    BUS_RegBitWrite(&EBI->WRTIMING3, _EBI_WRTIMING_HALFWE_SHIFT, halfWE);
   }
 }
 
@@ -894,37 +900,41 @@
   EFM_ASSERT(holdCycles < 4);
 
   /* Configure timing values */
-  writeTiming = (setupCycles << _EBI_WRTIMING_WRSETUP_SHIFT) |
-                (strobeCycles << _EBI_WRTIMING_WRSTRB_SHIFT) |
-                (holdCycles << _EBI_WRTIMING_WRHOLD_SHIFT);
+  writeTiming = (setupCycles << _EBI_WRTIMING_WRSETUP_SHIFT)
+                | (strobeCycles << _EBI_WRTIMING_WRSTRB_SHIFT)
+                | (holdCycles << _EBI_WRTIMING_WRHOLD_SHIFT);
 
   if (banks & EBI_BANK0)
   {
-    EBI->WRTIMING = (EBI->WRTIMING &
-                     ~(_EBI_WRTIMING_WRSETUP_MASK |
-                       _EBI_WRTIMING_WRSTRB_MASK |
-                       _EBI_WRTIMING_WRHOLD_MASK)) | writeTiming;
+    EBI->WRTIMING = (EBI->WRTIMING
+                     & ~(_EBI_WRTIMING_WRSETUP_MASK
+                         | _EBI_WRTIMING_WRSTRB_MASK
+                         | _EBI_WRTIMING_WRHOLD_MASK))
+                    | writeTiming;
   }
   if (banks & EBI_BANK1)
   {
-    EBI->WRTIMING1 = (EBI->WRTIMING1 &
-                      ~(_EBI_WRTIMING1_WRSETUP_MASK |
-                        _EBI_WRTIMING1_WRSTRB_MASK |
-                        _EBI_WRTIMING1_WRHOLD_MASK)) | writeTiming;
+    EBI->WRTIMING1 = (EBI->WRTIMING1
+                      & ~(_EBI_WRTIMING1_WRSETUP_MASK
+                          | _EBI_WRTIMING1_WRSTRB_MASK
+                          | _EBI_WRTIMING1_WRHOLD_MASK))
+                     | writeTiming;
   }
   if (banks & EBI_BANK2)
   {
-    EBI->WRTIMING2 = (EBI->WRTIMING2 &
-                      ~(_EBI_WRTIMING2_WRSETUP_MASK |
-                        _EBI_WRTIMING2_WRSTRB_MASK |
-                        _EBI_WRTIMING2_WRHOLD_MASK)) | writeTiming;
+    EBI->WRTIMING2 = (EBI->WRTIMING2
+                      & ~(_EBI_WRTIMING2_WRSETUP_MASK
+                          | _EBI_WRTIMING2_WRSTRB_MASK
+                          | _EBI_WRTIMING2_WRHOLD_MASK))
+                     | writeTiming;
   }
   if (banks & EBI_BANK3)
   {
-    EBI->WRTIMING3 = (EBI->WRTIMING3 &
-                      ~(_EBI_WRTIMING3_WRSETUP_MASK |
-                        _EBI_WRTIMING3_WRSTRB_MASK |
-                        _EBI_WRTIMING3_WRHOLD_MASK)) | writeTiming;
+    EBI->WRTIMING3 = (EBI->WRTIMING3
+                      & ~(_EBI_WRTIMING3_WRSETUP_MASK
+                          | _EBI_WRTIMING3_WRSTRB_MASK
+                          | _EBI_WRTIMING3_WRHOLD_MASK))
+                     | writeTiming;
   }
 }
 
@@ -946,19 +956,19 @@
 
   if( banks & EBI_BANK0 )
   {
-    BITBAND_Peripheral(&EBI->ADDRTIMING, _EBI_ADDRTIMING_HALFALE_SHIFT, halfALE);
+    BUS_RegBitWrite(&EBI->ADDRTIMING, _EBI_ADDRTIMING_HALFALE_SHIFT, halfALE);
   }
   if( banks & EBI_BANK1 )
   {
-    BITBAND_Peripheral(&EBI->ADDRTIMING1, _EBI_ADDRTIMING_HALFALE_SHIFT, halfALE);
+    BUS_RegBitWrite(&EBI->ADDRTIMING1, _EBI_ADDRTIMING_HALFALE_SHIFT, halfALE);
   }
   if( banks & EBI_BANK2 )
   {
-    BITBAND_Peripheral(&EBI->ADDRTIMING2, _EBI_ADDRTIMING_HALFALE_SHIFT, halfALE);
+    BUS_RegBitWrite(&EBI->ADDRTIMING2, _EBI_ADDRTIMING_HALFALE_SHIFT, halfALE);
   }
   if( banks & EBI_BANK3 )
   {
-    BITBAND_Peripheral(&EBI->ADDRTIMING3, _EBI_ADDRTIMING_HALFALE_SHIFT, halfALE);
+    BUS_RegBitWrite(&EBI->ADDRTIMING3, _EBI_ADDRTIMING_HALFALE_SHIFT, halfALE);
   }
 }
 
@@ -989,32 +999,36 @@
   EFM_ASSERT(holdCycles < 4);
 
   /* Configure address latch timing values */
-  addressLatchTiming = (setupCycles << _EBI_ADDRTIMING_ADDRSETUP_SHIFT) |
-                       (holdCycles << _EBI_ADDRTIMING_ADDRHOLD_SHIFT);
+  addressLatchTiming = (setupCycles << _EBI_ADDRTIMING_ADDRSETUP_SHIFT)
+                       | (holdCycles << _EBI_ADDRTIMING_ADDRHOLD_SHIFT);
 
   if (banks & EBI_BANK0)
   {
-    EBI->ADDRTIMING = (EBI->ADDRTIMING &
-                       ~(_EBI_ADDRTIMING_ADDRSETUP_MASK |
-                         _EBI_ADDRTIMING_ADDRHOLD_MASK)) | addressLatchTiming;
+    EBI->ADDRTIMING = (EBI->ADDRTIMING
+                       & ~(_EBI_ADDRTIMING_ADDRSETUP_MASK
+                           | _EBI_ADDRTIMING_ADDRHOLD_MASK))
+                      | addressLatchTiming;
   }
   if (banks & EBI_BANK1)
   {
-    EBI->ADDRTIMING1 = (EBI->ADDRTIMING1 &
-                        ~(_EBI_ADDRTIMING1_ADDRSETUP_MASK |
-                          _EBI_ADDRTIMING1_ADDRHOLD_MASK)) | addressLatchTiming;
+    EBI->ADDRTIMING1 = (EBI->ADDRTIMING1
+                        & ~(_EBI_ADDRTIMING1_ADDRSETUP_MASK
+                            | _EBI_ADDRTIMING1_ADDRHOLD_MASK))
+                       | addressLatchTiming;
   }
   if (banks & EBI_BANK2)
   {
-    EBI->ADDRTIMING2 = (EBI->ADDRTIMING2 &
-                        ~(_EBI_ADDRTIMING2_ADDRSETUP_MASK |
-                          _EBI_ADDRTIMING2_ADDRHOLD_MASK)) | addressLatchTiming;
+    EBI->ADDRTIMING2 = (EBI->ADDRTIMING2
+                        & ~(_EBI_ADDRTIMING2_ADDRSETUP_MASK
+                            | _EBI_ADDRTIMING2_ADDRHOLD_MASK))
+                       | addressLatchTiming;
   }
   if (banks & EBI_BANK3)
   {
-    EBI->ADDRTIMING3 = (EBI->ADDRTIMING3 &
-                        ~(_EBI_ADDRTIMING3_ADDRSETUP_MASK |
-                          _EBI_ADDRTIMING3_ADDRHOLD_MASK)) | addressLatchTiming;
+    EBI->ADDRTIMING3 = (EBI->ADDRTIMING3
+                        & ~(_EBI_ADDRTIMING3_ADDRSETUP_MASK
+                            | _EBI_ADDRTIMING3_ADDRHOLD_MASK))
+                       | addressLatchTiming;
   }
 }
 
@@ -1072,46 +1086,46 @@
     /* What line to configure */
     switch (line)
     {
-    case ebiLineARDY:
-      BITBAND_Peripheral(polRegister, _EBI_POLARITY_ARDYPOL_SHIFT, polarity);
-      break;
-    case ebiLineALE:
-      BITBAND_Peripheral(polRegister, _EBI_POLARITY_ALEPOL_SHIFT, polarity);
-      break;
-    case ebiLineWE:
-      BITBAND_Peripheral(polRegister, _EBI_POLARITY_WEPOL_SHIFT, polarity);
-      break;
-    case ebiLineRE:
-      BITBAND_Peripheral(polRegister, _EBI_POLARITY_REPOL_SHIFT, polarity);
-      break;
-    case ebiLineCS:
-      BITBAND_Peripheral(polRegister, _EBI_POLARITY_CSPOL_SHIFT, polarity);
-      break;
+      case ebiLineARDY:
+        BUS_RegBitWrite(polRegister, _EBI_POLARITY_ARDYPOL_SHIFT, polarity);
+        break;
+      case ebiLineALE:
+        BUS_RegBitWrite(polRegister, _EBI_POLARITY_ALEPOL_SHIFT, polarity);
+        break;
+      case ebiLineWE:
+        BUS_RegBitWrite(polRegister, _EBI_POLARITY_WEPOL_SHIFT, polarity);
+        break;
+      case ebiLineRE:
+        BUS_RegBitWrite(polRegister, _EBI_POLARITY_REPOL_SHIFT, polarity);
+        break;
+      case ebiLineCS:
+        BUS_RegBitWrite(polRegister, _EBI_POLARITY_CSPOL_SHIFT, polarity);
+        break;
 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
-    case ebiLineBL:
-      BITBAND_Peripheral(polRegister, _EBI_POLARITY_BLPOL_SHIFT, polarity);
-      break;
-    case ebiLineTFTVSync:
-      BITBAND_Peripheral(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_VSYNCPOL_SHIFT, polarity);
-      break;
-    case ebiLineTFTHSync:
-      BITBAND_Peripheral(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_HSYNCPOL_SHIFT, polarity);
-      break;
-    case ebiLineTFTDataEn:
-      BITBAND_Peripheral(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_DATAENPOL_SHIFT, polarity);
-      break;
-    case ebiLineTFTDClk:
-      BITBAND_Peripheral(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_DCLKPOL_SHIFT, polarity);
-      break;
-    case ebiLineTFTCS:
-      BITBAND_Peripheral(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_CSPOL_SHIFT, polarity);
-      break;
+      case ebiLineBL:
+        BUS_RegBitWrite(polRegister, _EBI_POLARITY_BLPOL_SHIFT, polarity);
+        break;
+      case ebiLineTFTVSync:
+        BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_VSYNCPOL_SHIFT, polarity);
+        break;
+      case ebiLineTFTHSync:
+        BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_HSYNCPOL_SHIFT, polarity);
+        break;
+      case ebiLineTFTDataEn:
+        BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_DATAENPOL_SHIFT, polarity);
+        break;
+      case ebiLineTFTDClk:
+        BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_DCLKPOL_SHIFT, polarity);
+        break;
+      case ebiLineTFTCS:
+        BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_CSPOL_SHIFT, polarity);
+        break;
 #endif
-    default:
-      EFM_ASSERT(0);
-      break;
+      default:
+        EFM_ASSERT(0);
+        break;
     }
-    banks = banks & (~bankSet);
+    banks = banks & ~bankSet;
   }
 }
 
@@ -1135,19 +1149,19 @@
   /* Configure byte lane support for each selected bank */
   if (banks & EBI_BANK0)
   {
-    BITBAND_Peripheral(&(EBI->CTRL), _EBI_CTRL_BL_SHIFT, enable);
+    BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_BL_SHIFT, enable);
   }
   if (banks & EBI_BANK1)
   {
-    BITBAND_Peripheral(&(EBI->CTRL), _EBI_CTRL_BL1_SHIFT, enable);
+    BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_BL1_SHIFT, enable);
   }
   if (banks & EBI_BANK2)
   {
-    BITBAND_Peripheral(&(EBI->CTRL), _EBI_CTRL_BL2_SHIFT, enable);
+    BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_BL2_SHIFT, enable);
   }
   if (banks & EBI_BANK3)
   {
-    BITBAND_Peripheral(&(EBI->CTRL), _EBI_CTRL_BL3_SHIFT, enable);
+    BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_BL3_SHIFT, enable);
   }
 }
 
@@ -1162,7 +1176,7 @@
  ******************************************************************************/
 void EBI_AltMapEnable(bool enable)
 {
-  BITBAND_Peripheral(&(EBI->CTRL), _EBI_CTRL_ALTMAP_SHIFT, enable);
+  BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_ALTMAP_SHIFT, enable);
 }
 
 #endif

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_emu.c	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_emu.c	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /***************************************************************************//**
  * @file em_emu.c
  * @brief Energy Management Unit (EMU) Peripheral API
- * @version 3.20.12
+ * @version 4.2.1
  *******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
  *******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,7 @@
  *
  ******************************************************************************/
 
+#include <limits.h>
 
 #include "em_emu.h"
 #if defined( EMU_PRESENT ) && ( EMU_COUNT > 0 )
@@ -67,32 +68,50 @@
 
 /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
 /* Fix for errata EMU_E107 - non-WIC interrupt masks. */
-#if defined(_EFM32_GECKO_FAMILY)
-  #define ERRATA_FIX_EMU_E107_EN
-  #define NON_WIC_INT_MASK_0    (~(0x0dfc0323U))
-  #define NON_WIC_INT_MASK_1    (~(0x0U))
-#elif defined(_EFM32_TINY_FAMILY)
-  #define ERRATA_FIX_EMU_E107_EN
-  #define NON_WIC_INT_MASK_0    (~(0x001be323U))
-  #define NON_WIC_INT_MASK_1    (~(0x0U))
-#elif defined(_EFM32_GIANT_FAMILY)
-  #define ERRATA_FIX_EMU_E107_EN
-  #define NON_WIC_INT_MASK_0    (~(0xff020e63U))
-  #define NON_WIC_INT_MASK_1    (~(0x00000046U))
-#elif defined(_EFM32_WONDER_FAMILY)
-  #define ERRATA_FIX_EMU_E107_EN
-  #define NON_WIC_INT_MASK_0    (~(0xff020e63U))
-  #define NON_WIC_INT_MASK_1    (~(0x00000046U))
+#if defined( _EFM32_GECKO_FAMILY )
+#define ERRATA_FIX_EMU_E107_EN
+#define NON_WIC_INT_MASK_0    (~(0x0dfc0323U))
+#define NON_WIC_INT_MASK_1    (~(0x0U))
+
+#elif defined( _EFM32_TINY_FAMILY )
+#define ERRATA_FIX_EMU_E107_EN
+#define NON_WIC_INT_MASK_0    (~(0x001be323U))
+#define NON_WIC_INT_MASK_1    (~(0x0U))
+
+#elif defined( _EFM32_GIANT_FAMILY )
+#define ERRATA_FIX_EMU_E107_EN
+#define NON_WIC_INT_MASK_0    (~(0xff020e63U))
+#define NON_WIC_INT_MASK_1    (~(0x00000046U))
+
+#elif defined( _EFM32_WONDER_FAMILY )
+#define ERRATA_FIX_EMU_E107_EN
+#define NON_WIC_INT_MASK_0    (~(0xff020e63U))
+#define NON_WIC_INT_MASK_1    (~(0x00000046U))
+
 #else
 /* Zero Gecko and future families are not affected by errata EMU_E107 */
 #endif
 
 /* Fix for errata EMU_E108 - High Current Consumption on EM4 Entry. */
-#if defined(_EFM32_HAPPY_FAMILY)
+#if defined( _EFM32_HAPPY_FAMILY )
 #define ERRATA_FIX_EMU_E108_EN
 #endif
 /** @endcond */
 
+
+#if defined( _EMU_DCDCCTRL_MASK )
+/* DCDCTODVDD output range min/max */
+#define PWRCFG_DCDCTODVDD_VMIN          1200
+#define PWRCFG_DCDCTODVDD_VMAX          3000
+typedef enum
+{
+  errataFixDcdcHsInit,
+  errataFixDcdcHsTrimSet,
+  errataFixDcdcHsLnWaitDone
+} errataFixDcdcHs_TypeDef;
+errataFixDcdcHs_TypeDef errataFixDcdcHsState = errataFixDcdcHsInit;
+#endif
+
 /*******************************************************************************
  **************************   LOCAL VARIABLES   ********************************
  ******************************************************************************/
@@ -108,6 +127,14 @@
  * for oscillator control).
  */
 static uint32_t cmuStatus;
+#if defined( _CMU_HFCLKSTATUS_RESETVALUE )
+static uint16_t cmuHfclkStatus;
+#endif
+#if defined( _EMU_DCDCCTRL_MASK )
+static uint16_t dcdcMaxCurrent_mA;
+static uint16_t dcdcOutput_mVout;
+#endif
+
 /** @endcond */
 
 
@@ -121,11 +148,10 @@
  * @brief
  *   Restore oscillators and core clock after having been in EM2 or EM3.
  ******************************************************************************/
-static void EMU_Restore(void)
+static void emuRestore(void)
 {
   uint32_t oscEnCmd;
   uint32_t cmuLocked;
-  uint32_t statusClkSelMask;
 
   /* Although we could use the CMU API for most of the below handling, we */
   /* would like this function to be as efficient as possible. */
@@ -149,52 +175,91 @@
 #endif
   CMU->OSCENCMD = oscEnCmd;
 
-  statusClkSelMask =
-    (CMU_STATUS_HFRCOSEL |
-     CMU_STATUS_HFXOSEL |
-     CMU_STATUS_LFRCOSEL |
-#if defined( CMU_STATUS_USHFRCODIV2SEL )
-     CMU_STATUS_USHFRCODIV2SEL |
-#endif
-     CMU_STATUS_LFXOSEL);
 
+#if defined( _CMU_HFCLKSTATUS_RESETVALUE )
   /* Restore oscillator used for clocking core */
-  switch (cmuStatus & statusClkSelMask)
+  switch (cmuHfclkStatus & _CMU_HFCLKSTATUS_SELECTED_MASK)
   {
-  case CMU_STATUS_LFRCOSEL:
-    /* Wait for LFRCO to stabilize */
-    while (!(CMU->STATUS & CMU_STATUS_LFRCORDY))
-      ;
-    CMU->CMD = CMU_CMD_HFCLKSEL_LFRCO;
-    break;
+    case CMU_HFCLKSTATUS_SELECTED_LFRCO:
+      /* HFRCO could only be selected if the autostart HFXO feature is not
+       * enabled, otherwise the HFXO would be started and selected automatically.
+       * Note: this error hook helps catching erroneous oscillator configurations,
+       * when the AUTOSTARTSELEM0EM1 is set in CMU_HFXOCTRL. */
+      if (!(CMU->HFXOCTRL & CMU_HFXOCTRL_AUTOSTARTSELEM0EM1))
+      {
+        /* Wait for LFRCO to stabilize */
+        while (!(CMU->STATUS & CMU_STATUS_LFRCORDY))
+          ;
+        CMU->HFCLKSEL = CMU_HFCLKSEL_HF_LFRCO;
+      }
+      else
+      {
+        EFM_ASSERT(0);
+      }
+      break;
+
+    case CMU_HFCLKSTATUS_SELECTED_LFXO:
+      /* Wait for LFXO to stabilize */
+      while (!(CMU->STATUS & CMU_STATUS_LFXORDY))
+        ;
+      CMU->HFCLKSEL = CMU_HFCLKSEL_HF_LFXO;
+      break;
+
+    case CMU_HFCLKSTATUS_SELECTED_HFXO:
+      /* Wait for HFXO to stabilize */
+      while (!(CMU->STATUS & CMU_STATUS_HFXORDY))
+        ;
+      CMU->HFCLKSEL = CMU_HFCLKSEL_HF_HFXO;
+      break;
 
-  case CMU_STATUS_LFXOSEL:
-    /* Wait for LFXO to stabilize */
-    while (!(CMU->STATUS & CMU_STATUS_LFXORDY))
-      ;
-    CMU->CMD = CMU_CMD_HFCLKSEL_LFXO;
-    break;
+    default: /* CMU_HFCLKSTATUS_SELECTED_HFRCO */
+      /* If core clock was HFRCO core clock, it is automatically restored to */
+      /* state prior to entering energy mode. No need for further action. */
+      break;
+  }
+#else
+  switch (cmuStatus & (CMU_STATUS_HFRCOSEL
+                      | CMU_STATUS_HFXOSEL
+                      | CMU_STATUS_LFRCOSEL
+#if defined( CMU_STATUS_USHFRCODIV2SEL )
+                      | CMU_STATUS_USHFRCODIV2SEL
+#endif
+                      | CMU_STATUS_LFXOSEL))
+  {
+    case CMU_STATUS_LFRCOSEL:
+      /* Wait for LFRCO to stabilize */
+      while (!(CMU->STATUS & CMU_STATUS_LFRCORDY))
+        ;
+      CMU->CMD = CMU_CMD_HFCLKSEL_LFRCO;
+      break;
 
-  case CMU_STATUS_HFXOSEL:
-    /* Wait for HFXO to stabilize */
-    while (!(CMU->STATUS & CMU_STATUS_HFXORDY))
-      ;
-    CMU->CMD = CMU_CMD_HFCLKSEL_HFXO;
-    break;
+    case CMU_STATUS_LFXOSEL:
+      /* Wait for LFXO to stabilize */
+      while (!(CMU->STATUS & CMU_STATUS_LFXORDY))
+        ;
+      CMU->CMD = CMU_CMD_HFCLKSEL_LFXO;
+      break;
+
+    case CMU_STATUS_HFXOSEL:
+      /* Wait for HFXO to stabilize */
+      while (!(CMU->STATUS & CMU_STATUS_HFXORDY))
+        ;
+      CMU->CMD = CMU_CMD_HFCLKSEL_HFXO;
+      break;
 
 #if defined( CMU_STATUS_USHFRCODIV2SEL )
-  case CMU_STATUS_USHFRCODIV2SEL:
-    /* Wait for USHFRCO to stabilize */
-    while (!(CMU->STATUS & CMU_STATUS_USHFRCORDY))
-      ;
-    CMU->CMD = _CMU_CMD_HFCLKSEL_USHFRCODIV2;
-    break;
+    case CMU_STATUS_USHFRCODIV2SEL:
+      /* Wait for USHFRCO to stabilize */
+      while (!(CMU->STATUS & CMU_STATUS_USHFRCORDY))
+        ;
+      CMU->CMD = _CMU_CMD_HFCLKSEL_USHFRCODIV2;
+      break;
 #endif
 
-  default: /* CMU_STATUS_HFRCOSEL */
-    /* If core clock was HFRCO core clock, it is automatically restored to */
-    /* state prior to entering energy mode. No need for further action. */
-    break;
+    default: /* CMU_STATUS_HFRCOSEL */
+      /* If core clock was HFRCO core clock, it is automatically restored to */
+      /* state prior to entering energy mode. No need for further action. */
+      break;
   }
 
   /* If HFRCO was disabled before entering Energy Mode, turn it off again */
@@ -203,7 +268,7 @@
   {
     CMU->OSCENCMD = CMU_OSCENCMD_HFRCODIS;
   }
-
+#endif
   /* Restore CMU register locking */
   if (cmuLocked)
   {
@@ -212,27 +277,34 @@
 }
 
 
+#if defined( ERRATA_FIX_EMU_E107_EN )
 /* Get enable conditions for errata EMU_E107 fix. */
-#if defined(ERRATA_FIX_EMU_E107_EN)
 static __INLINE bool getErrataFixEmuE107En(void)
 {
-  /* SYSTEM_ChipRevisionGet could have been used here, but we would like a faster implementation in this case. */
+  /* SYSTEM_ChipRevisionGet could have been used here, but we would like a
+   * faster implementation in this case.
+   */
   uint16_t majorMinorRev;
 
   /* CHIP MAJOR bit [3:0] */
-  majorMinorRev = (((ROMTABLE->PID0 & _ROMTABLE_PID0_REVMAJOR_MASK) >> _ROMTABLE_PID0_REVMAJOR_SHIFT) << 8);
+  majorMinorRev = ((ROMTABLE->PID0 & _ROMTABLE_PID0_REVMAJOR_MASK)
+                   >> _ROMTABLE_PID0_REVMAJOR_SHIFT)
+                  << 8;
   /* CHIP MINOR bit [7:4] */
-  majorMinorRev |= (((ROMTABLE->PID2 & _ROMTABLE_PID2_REVMINORMSB_MASK) >> _ROMTABLE_PID2_REVMINORMSB_SHIFT) << 4);
+  majorMinorRev |= ((ROMTABLE->PID2 & _ROMTABLE_PID2_REVMINORMSB_MASK)
+                    >> _ROMTABLE_PID2_REVMINORMSB_SHIFT)
+                   << 4;
   /* CHIP MINOR bit [3:0] */
-  majorMinorRev |=  ((ROMTABLE->PID3 & _ROMTABLE_PID3_REVMINORLSB_MASK) >> _ROMTABLE_PID3_REVMINORLSB_SHIFT);
+  majorMinorRev |= (ROMTABLE->PID3 & _ROMTABLE_PID3_REVMINORLSB_MASK)
+                   >> _ROMTABLE_PID3_REVMINORLSB_SHIFT;
 
-#if defined(_EFM32_GECKO_FAMILY)
+#if defined( _EFM32_GECKO_FAMILY )
   return (majorMinorRev <= 0x0103);
-#elif defined(_EFM32_TINY_FAMILY)
+#elif defined( _EFM32_TINY_FAMILY )
   return (majorMinorRev <= 0x0102);
-#elif defined(_EFM32_GIANT_FAMILY)
+#elif defined( _EFM32_GIANT_FAMILY )
   return (majorMinorRev <= 0x0103) || (majorMinorRev == 0x0204);
-#elif defined(_EFM32_WONDER_FAMILY)
+#elif defined( _EFM32_WONDER_FAMILY )
   return (majorMinorRev == 0x0100);
 #else
   /* Zero Gecko and future families are not affected by errata EMU_E107 */
@@ -241,6 +313,50 @@
 }
 #endif
 
+
+#if defined( _EMU_DCDCCTRL_MASK )
+/* LP prepare / LN restore P/NFET count */
+static void maxCurrentUpdate(void);
+#define DCDC_LP_PFET_CNT        7
+#define DCDC_LP_NFET_CNT        15
+void dcdcFetCntSet(bool lpModeSet)
+{
+  uint32_t tmp;
+  static uint32_t emuDcdcMiscCtrlReg;
+
+  if (lpModeSet)
+  {
+    emuDcdcMiscCtrlReg = EMU->DCDCMISCCTRL;
+    tmp  = EMU->DCDCMISCCTRL
+           & ~(_EMU_DCDCMISCCTRL_PFETCNT_MASK | _EMU_DCDCMISCCTRL_NFETCNT_MASK);
+    tmp |= (DCDC_LP_PFET_CNT << _EMU_DCDCMISCCTRL_PFETCNT_SHIFT)
+            | (DCDC_LP_NFET_CNT << _EMU_DCDCMISCCTRL_NFETCNT_SHIFT);
+    EMU->DCDCMISCCTRL = tmp;
+    maxCurrentUpdate();
+  }
+  else
+  {
+    EMU->DCDCMISCCTRL = emuDcdcMiscCtrlReg;
+    maxCurrentUpdate();
+  }
+}
+
+void dcdcHsFixLnBlock(void)
+{
+#define EMU_DCDCSTATUS  (* (volatile uint32_t *)(EMU_BASE + 0x7C))
+  if (errataFixDcdcHsState == errataFixDcdcHsTrimSet)
+  {
+    /* Wait for LNRUNNING */
+    if ((EMU->DCDCCTRL & ~_EMU_DCDCCTRL_DCDCMODE_MASK) == EMU_DCDCCTRL_DCDCMODE_LOWNOISE)
+    {
+      while (!(EMU_DCDCSTATUS & (0x1 << 16)));
+    }
+    errataFixDcdcHsState = errataFixDcdcHsLnWaitDone;
+  }
+}
+#endif
+
+
 /** @endcond */
 
 
@@ -281,6 +397,11 @@
  *   If a debugger is attached, the AUXHFRCO will not be disabled if enabled
  *   upon entering EM2. It will thus remain enabled when returning to EM0
  *   regardless of the @p restore parameter.
+ * @par
+ *   If HFXO autostart and select is enabled by using CMU_HFXOAutostartEnable(),
+ *   the starting and selecting of the core clocks will be identical to the user
+ *   independently of the value of the @p restore parameter when waking up on
+ *   the wakeup sources corresponding to the autostart and select setting.
  *
  * @param[in] restore
  *   @li true - restore oscillators and clocks, see function details.
@@ -291,7 +412,7 @@
  ******************************************************************************/
 void EMU_EnterEM2(bool restore)
 {
-#if defined(ERRATA_FIX_EMU_E107_EN)
+#if defined( ERRATA_FIX_EMU_E107_EN )
   bool errataFixEmuE107En;
   uint32_t nonWicIntEn[2];
 #endif
@@ -299,13 +420,16 @@
   /* Auto-update CMU status just in case before entering energy mode. */
   /* This variable is normally kept up-to-date by the CMU API. */
   cmuStatus = CMU->STATUS;
+#if defined( _CMU_HFCLKSTATUS_RESETVALUE )
+  cmuHfclkStatus = (uint16_t)(CMU->HFCLKSTATUS);
+#endif
 
-  /* Enter Cortex-M3 deep sleep mode */
+  /* Enter Cortex deep sleep mode */
   SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
 
   /* Fix for errata EMU_E107 - store non-WIC interrupt enable flags.
      Disable the enabled non-WIC interrupts. */
-#if defined(ERRATA_FIX_EMU_E107_EN)
+#if defined( ERRATA_FIX_EMU_E107_EN )
   errataFixEmuE107En = getErrataFixEmuE107En();
   if (errataFixEmuE107En)
   {
@@ -318,10 +442,19 @@
   }
 #endif
 
+#if defined( _EMU_DCDCCTRL_MASK )
+  dcdcFetCntSet(true);
+  dcdcHsFixLnBlock();
+#endif
+
   __WFI();
 
+#if defined( _EMU_DCDCCTRL_MASK )
+  dcdcFetCntSet(false);
+#endif
+
   /* Fix for errata EMU_E107 - restore state of non-WIC interrupt enable flags. */
-#if defined(ERRATA_FIX_EMU_E107_EN)
+#if defined( ERRATA_FIX_EMU_E107_EN )
   if (errataFixEmuE107En)
   {
     NVIC->ISER[0] = nonWicIntEn[0];
@@ -334,12 +467,17 @@
   /* Restore oscillators/clocks if specified */
   if (restore)
   {
-    EMU_Restore();
+    emuRestore();
   }
   /* If not restoring, and original clock was not HFRCO, we have to */
   /* update CMSIS core clock variable since core clock has changed */
   /* to using HFRCO. */
+#if defined( _CMU_HFCLKSTATUS_RESETVALUE )
+  else if ((cmuHfclkStatus & _CMU_HFCLKSTATUS_SELECTED_MASK)
+           != CMU_HFCLKSTATUS_SELECTED_HFRCO)
+#else
   else if (!(cmuStatus & CMU_STATUS_HFRCOSEL))
+#endif
   {
     SystemCoreClockUpdate();
   }
@@ -392,7 +530,7 @@
 {
   uint32_t cmuLocked;
 
-#if defined(ERRATA_FIX_EMU_E107_EN)
+#if defined( ERRATA_FIX_EMU_E107_EN )
   bool errataFixEmuE107En;
   uint32_t nonWicIntEn[2];
 #endif
@@ -400,6 +538,9 @@
   /* Auto-update CMU status just in case before entering energy mode. */
   /* This variable is normally kept up-to-date by the CMU API. */
   cmuStatus = CMU->STATUS;
+#if defined( _CMU_HFCLKSTATUS_RESETVALUE )
+  cmuHfclkStatus = (uint16_t)(CMU->HFCLKSTATUS);
+#endif
 
   /* CMU registers may be locked */
   cmuLocked = CMU->LOCK & CMU_LOCK_LOCKKEY_LOCKED;
@@ -414,12 +555,12 @@
     CMU_Lock();
   }
 
-  /* Enter Cortex-M3 deep sleep mode */
+  /* Enter Cortex deep sleep mode */
   SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
 
   /* Fix for errata EMU_E107 - store non-WIC interrupt enable flags.
      Disable the enabled non-WIC interrupts. */
-#if defined(ERRATA_FIX_EMU_E107_EN)
+#if defined( ERRATA_FIX_EMU_E107_EN )
   errataFixEmuE107En = getErrataFixEmuE107En();
   if (errataFixEmuE107En)
   {
@@ -433,10 +574,19 @@
   }
 #endif
 
+#if defined( _EMU_DCDCCTRL_MASK )
+  dcdcFetCntSet(true);
+  dcdcHsFixLnBlock();
+#endif
+
   __WFI();
 
+#if defined( _EMU_DCDCCTRL_MASK )
+  dcdcFetCntSet(false);
+#endif
+
   /* Fix for errata EMU_E107 - restore state of non-WIC interrupt enable flags. */
-#if defined(ERRATA_FIX_EMU_E107_EN)
+#if defined( ERRATA_FIX_EMU_E107_EN )
   if (errataFixEmuE107En)
   {
     NVIC->ISER[0] = nonWicIntEn[0];
@@ -449,12 +599,17 @@
   /* Restore oscillators/clocks if specified */
   if (restore)
   {
-    EMU_Restore();
+    emuRestore();
   }
   /* If not restoring, and original clock was not HFRCO, we have to */
   /* update CMSIS core clock variable since core clock has changed */
   /* to using HFRCO. */
+#if defined( _CMU_HFCLKSTATUS_RESETVALUE )
+  else if ((cmuHfclkStatus & _CMU_HFCLKSTATUS_SELECTED_MASK)
+           != CMU_HFCLKSTATUS_SELECTED_HFRCO)
+#else
   else if (!(cmuStatus & CMU_STATUS_HFRCOSEL))
+#endif
   {
     SystemCoreClockUpdate();
   }
@@ -471,27 +626,46 @@
 void EMU_EnterEM4(void)
 {
   int i;
-  uint32_t em4seq2;
-  uint32_t em4seq3;
 
-  em4seq2 = (EMU->CTRL & ~_EMU_CTRL_EM4CTRL_MASK) | (2 << _EMU_CTRL_EM4CTRL_SHIFT);
-  em4seq3 = (EMU->CTRL & ~_EMU_CTRL_EM4CTRL_MASK) | (3 << _EMU_CTRL_EM4CTRL_SHIFT);
+#if defined( _EMU_EM4CTRL_EM4ENTRY_SHIFT )
+  uint32_t em4seq2 = (EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4ENTRY_MASK)
+                     | (2 << _EMU_EM4CTRL_EM4ENTRY_SHIFT);
+  uint32_t em4seq3 = (EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4ENTRY_MASK)
+                     | (3 << _EMU_EM4CTRL_EM4ENTRY_SHIFT);
+#else
+  uint32_t em4seq2 = (EMU->CTRL & ~_EMU_CTRL_EM4CTRL_MASK)
+                     | (2 << _EMU_CTRL_EM4CTRL_SHIFT);
+  uint32_t em4seq3 = (EMU->CTRL & ~_EMU_CTRL_EM4CTRL_MASK)
+                     | (3 << _EMU_CTRL_EM4CTRL_SHIFT);
+#endif
 
   /* Make sure register write lock is disabled */
   EMU_Unlock();
 
-#if defined(ERRATA_FIX_EMU_E108_EN)
+#if defined( ERRATA_FIX_EMU_E108_EN )
   /* Fix for errata EMU_E108 - High Current Consumption on EM4 Entry. */
   __disable_irq();
   *(volatile uint32_t *)0x400C80E4 = 0;
 #endif
 
+#if defined( _EMU_DCDCCTRL_MASK )
+  dcdcFetCntSet(true);
+  dcdcHsFixLnBlock();
+#endif
+
   for (i = 0; i < 4; i++)
   {
+#if defined( _EMU_EM4CTRL_EM4ENTRY_SHIFT )
+    EMU->EM4CTRL = em4seq2;
+    EMU->EM4CTRL = em4seq3;
+  }
+  EMU->EM4CTRL = em4seq2;
+#else
     EMU->CTRL = em4seq2;
     EMU->CTRL = em4seq3;
   }
   EMU->CTRL = em4seq2;
+#endif
 }
 
 
@@ -502,7 +676,7 @@
  * @param[in] blocks
  *   Specifies a logical OR of bits indicating memory blocks to power down.
  *   Bit 0 selects block 1, bit 1 selects block 2, etc. Memory block 0 cannot
- *   be disabled. Please refer to the EFM32 reference manual for available
+ *   be disabled. Please refer to the reference manual for available
  *   memory blocks for a device.
  *
  * @note
@@ -512,10 +686,28 @@
  ******************************************************************************/
 void EMU_MemPwrDown(uint32_t blocks)
 {
-#if defined(_EMU_MEMCTRL_RESETVALUE)
-  EFM_ASSERT(blocks <= _EMU_MEMCTRL_MASK);
+#if defined( _EMU_MEMCTRL_POWERDOWN_MASK )
+  EFM_ASSERT(blocks <= (_EMU_MEMCTRL_POWERDOWN_MASK
+                        >> _EMU_MEMCTRL_POWERDOWN_SHIFT));
+  EMU->MEMCTRL = blocks;
 
+#elif defined( _EMU_MEMCTRL_RAMPOWERDOWN_MASK )       \
+      && defined( _EMU_MEMCTRL_RAMHPOWERDOWN_MASK )   \
+      && defined( _EMU_MEMCTRL_SEQRAMPOWERDOWN_MASK )
+  EFM_ASSERT((blocks & (_EMU_MEMCTRL_RAMPOWERDOWN_MASK
+                        | _EMU_MEMCTRL_RAMHPOWERDOWN_MASK
+                        | _EMU_MEMCTRL_SEQRAMPOWERDOWN_MASK))
+             == blocks);
   EMU->MEMCTRL = blocks;
+
+#elif defined( _EMU_MEMCTRL_RAMPOWERDOWN_MASK )
+  EFM_ASSERT((blocks & _EMU_MEMCTRL_RAMPOWERDOWN_MASK) == blocks);
+  EMU->MEMCTRL = blocks;
+
+#elif defined( _EMU_RAM0CTRL_RAMPOWERDOWN_MASK )
+  EFM_ASSERT((blocks & _EMU_RAM0CTRL_RAMPOWERDOWN_MASK) == blocks);
+  EMU->RAM0CTRL = blocks;
+
 #else
   (void)blocks;
 #endif
@@ -545,10 +737,12 @@
 {
   /* Fetch current configuration */
   cmuStatus = CMU->STATUS;
+#if defined( _CMU_HFCLKSTATUS_RESETVALUE )
+  cmuHfclkStatus = (uint16_t)(CMU->HFCLKSTATUS);
+#endif
 }
 
 
-#if defined( _EMU_CTRL_EMVREG_MASK ) || defined( _EMU_CTRL_EM23VREG_MASK )
 /***************************************************************************//**
  * @brief
  *   Update EMU module with Energy Mode 2 and 3 configuration
@@ -559,15 +753,18 @@
 void EMU_EM23Init(EMU_EM23Init_TypeDef *em23Init)
 {
 #if defined( _EMU_CTRL_EMVREG_MASK )
-  EMU->CTRL = em23Init->em23Vreg ? (EMU->CTRL | EMU_CTRL_EMVREG) : (EMU->CTRL & ~EMU_CTRL_EMVREG);
+  EMU->CTRL = em23Init->em23VregFullEn ? (EMU->CTRL | EMU_CTRL_EMVREG)
+                                         : (EMU->CTRL & ~EMU_CTRL_EMVREG);
 #elif defined( _EMU_CTRL_EM23VREG_MASK )
-  EMU->CTRL = em23Init->em23Vreg ? (EMU->CTRL | EMU_CTRL_EM23VREG) : (EMU->CTRL & ~EMU_CTRL_EM23VREG);
+  EMU->CTRL = em23Init->em23VregFullEn ? (EMU->CTRL | EMU_CTRL_EM23VREG)
+                                         : (EMU->CTRL & ~EMU_CTRL_EM23VREG);
+#else
+  (void)em23Init;
 #endif
 }
-#endif
 
 
-#if defined( _EMU_EM4CONF_MASK )
+#if defined( _EMU_EM4CONF_MASK ) || defined( _EMU_EM4CTRL_MASK )
 /***************************************************************************//**
  * @brief
  *   Update EMU module with Energy Mode 4 configuration
@@ -577,30 +774,49 @@
  ******************************************************************************/
 void EMU_EM4Init(EMU_EM4Init_TypeDef *em4Init)
 {
+#if defined( _EMU_EM4CONF_MASK )
+  /* Init for platforms with EMU->EM4CONF register */
   uint32_t em4conf = EMU->EM4CONF;
 
   /* Clear fields that will be reconfigured */
-  em4conf &= ~(
-    _EMU_EM4CONF_LOCKCONF_MASK |
-    _EMU_EM4CONF_OSC_MASK |
-    _EMU_EM4CONF_BURTCWU_MASK |
-    _EMU_EM4CONF_VREGEN_MASK);
+  em4conf &= ~(_EMU_EM4CONF_LOCKCONF_MASK
+               | _EMU_EM4CONF_OSC_MASK
+               | _EMU_EM4CONF_BURTCWU_MASK
+               | _EMU_EM4CONF_VREGEN_MASK);
 
   /* Configure new settings */
-  em4conf |= (
-    (em4Init->lockConfig << _EMU_EM4CONF_LOCKCONF_SHIFT) |
-    (em4Init->osc) |
-    (em4Init->buRtcWakeup << _EMU_EM4CONF_BURTCWU_SHIFT) |
-    (em4Init->vreg << _EMU_EM4CONF_VREGEN_SHIFT));
+  em4conf |= (em4Init->lockConfig << _EMU_EM4CONF_LOCKCONF_SHIFT)
+             | (em4Init->osc)
+             | (em4Init->buRtcWakeup << _EMU_EM4CONF_BURTCWU_SHIFT)
+             | (em4Init->vreg << _EMU_EM4CONF_VREGEN_SHIFT);
 
   /* Apply configuration. Note that lock can be set after this stage. */
   EMU->EM4CONF = em4conf;
+
+#elif defined( _EMU_EM4CTRL_MASK )
+  /* Init for platforms with EMU->EM4CTRL register */
+
+  uint32_t em4ctrl = EMU->EM4CTRL;
+
+  em4ctrl &= ~(_EMU_EM4CTRL_RETAINLFXO_MASK
+               | _EMU_EM4CTRL_RETAINLFRCO_MASK
+               | _EMU_EM4CTRL_RETAINULFRCO_MASK
+               | _EMU_EM4CTRL_EM4STATE_MASK
+               | _EMU_EM4CTRL_EM4IORETMODE_MASK);
+
+     em4ctrl |= (em4Init->retainLfxo     ? EMU_EM4CTRL_RETAINLFXO : 0)
+                | (em4Init->retainLfrco  ? EMU_EM4CTRL_RETAINLFRCO : 0)
+                | (em4Init->retainUlfrco ? EMU_EM4CTRL_RETAINULFRCO : 0)
+                | (em4Init->em4State     ? EMU_EM4CTRL_EM4STATE_EM4H : 0)
+                | (em4Init->pinRetentionMode);
+
+  EMU->EM4CTRL = em4ctrl;
+#endif
 }
 #endif
 
 
 #if defined( BU_PRESENT )
-
 /***************************************************************************//**
  * @brief
  *   Configure Backup Power Domain settings
@@ -613,16 +829,15 @@
   uint32_t reg;
 
   /* Set power connection configuration */
-  reg = EMU->PWRCONF & ~(
-    _EMU_PWRCONF_PWRRES_MASK|
-    _EMU_PWRCONF_VOUTSTRONG_MASK|
-    _EMU_PWRCONF_VOUTMED_MASK|
-    _EMU_PWRCONF_VOUTWEAK_MASK);
+  reg = EMU->PWRCONF & ~(_EMU_PWRCONF_PWRRES_MASK
+                         | _EMU_PWRCONF_VOUTSTRONG_MASK
+                         | _EMU_PWRCONF_VOUTMED_MASK
+                         | _EMU_PWRCONF_VOUTWEAK_MASK);
 
-  reg |= (bupdInit->resistor|
-         (bupdInit->voutStrong << _EMU_PWRCONF_VOUTSTRONG_SHIFT)|
-         (bupdInit->voutMed    << _EMU_PWRCONF_VOUTMED_SHIFT)|
-         (bupdInit->voutWeak   << _EMU_PWRCONF_VOUTWEAK_SHIFT));
+  reg |= bupdInit->resistor
+         | (bupdInit->voutStrong << _EMU_PWRCONF_VOUTSTRONG_SHIFT)
+         | (bupdInit->voutMed    << _EMU_PWRCONF_VOUTMED_SHIFT)
+         | (bupdInit->voutWeak   << _EMU_PWRCONF_VOUTWEAK_SHIFT);
 
   EMU->PWRCONF = reg;
 
@@ -637,18 +852,17 @@
   EMU->BUACT = reg;
 
   /* Set power control configuration */
-  reg = EMU->BUCTRL & ~(
-    _EMU_BUCTRL_PROBE_MASK|
-    _EMU_BUCTRL_BODCAL_MASK|
-    _EMU_BUCTRL_STATEN_MASK|
-    _EMU_BUCTRL_EN_MASK);
+  reg = EMU->BUCTRL & ~(_EMU_BUCTRL_PROBE_MASK
+                        | _EMU_BUCTRL_BODCAL_MASK
+                        | _EMU_BUCTRL_STATEN_MASK
+                        | _EMU_BUCTRL_EN_MASK);
 
   /* Note use of ->enable to both enable BUPD, use BU_VIN pin input and
      release reset */
-  reg |= (bupdInit->probe|
-         (bupdInit->bodCal          << _EMU_BUCTRL_BODCAL_SHIFT)|
-         (bupdInit->statusPinEnable << _EMU_BUCTRL_STATEN_SHIFT)|
-         (bupdInit->enable          << _EMU_BUCTRL_EN_SHIFT));
+  reg |= bupdInit->probe
+         | (bupdInit->bodCal          << _EMU_BUCTRL_BODCAL_SHIFT)
+         | (bupdInit->statusPinEnable << _EMU_BUCTRL_STATEN_SHIFT)
+         | (bupdInit->enable          << _EMU_BUCTRL_EN_SHIFT);
 
   /* Enable configuration */
   EMU->BUCTRL = reg;
@@ -657,7 +871,7 @@
   EMU_BUPinEnable(bupdInit->enable);
 
   /* If enable is true, release BU reset, if not keep reset asserted */
-  BITBAND_Peripheral(&(RMU->CTRL), _RMU_CTRL_BURSTEN_SHIFT, !bupdInit->enable);
+  BUS_RegBitWrite(&(RMU->CTRL), _RMU_CTRL_BURSTEN_SHIFT, !bupdInit->enable);
 }
 
 
@@ -671,16 +885,19 @@
  ******************************************************************************/
 void EMU_BUThresholdSet(EMU_BODMode_TypeDef mode, uint32_t value)
 {
+  EFM_ASSERT(value<8);
   EFM_ASSERT(value<=(_EMU_BUACT_BUEXTHRES_MASK>>_EMU_BUACT_BUEXTHRES_SHIFT));
 
   switch(mode)
   {
-  case emuBODMode_Active:
-    EMU->BUACT = (EMU->BUACT & ~(_EMU_BUACT_BUEXTHRES_MASK))|(value<<_EMU_BUACT_BUEXTHRES_SHIFT);
-    break;
-  case emuBODMode_Inactive:
-    EMU->BUINACT = (EMU->BUINACT & ~(_EMU_BUINACT_BUENTHRES_MASK))|(value<<_EMU_BUINACT_BUENTHRES_SHIFT);
-    break;
+    case emuBODMode_Active:
+      EMU->BUACT = (EMU->BUACT & ~_EMU_BUACT_BUEXTHRES_MASK)
+                   | (value<<_EMU_BUACT_BUEXTHRES_SHIFT);
+      break;
+    case emuBODMode_Inactive:
+      EMU->BUINACT = (EMU->BUINACT & ~_EMU_BUINACT_BUENTHRES_MASK)
+                     | (value<<_EMU_BUINACT_BUENTHRES_SHIFT);
+      break;
   }
 }
 
@@ -695,22 +912,894 @@
  ******************************************************************************/
 void EMU_BUThresRangeSet(EMU_BODMode_TypeDef mode, uint32_t value)
 {
+  EFM_ASSERT(value < 4);
   EFM_ASSERT(value<=(_EMU_BUACT_BUEXRANGE_MASK>>_EMU_BUACT_BUEXRANGE_SHIFT));
 
   switch(mode)
   {
-  case emuBODMode_Active:
-    EMU->BUACT = (EMU->BUACT & ~(_EMU_BUACT_BUEXRANGE_MASK))|(value<<_EMU_BUACT_BUEXRANGE_SHIFT);
-    break;
-  case emuBODMode_Inactive:
-    EMU->BUINACT = (EMU->BUINACT & ~(_EMU_BUINACT_BUENRANGE_MASK))|(value<<_EMU_BUINACT_BUENRANGE_SHIFT);
-    break;
+    case emuBODMode_Active:
+      EMU->BUACT = (EMU->BUACT & ~_EMU_BUACT_BUEXRANGE_MASK)
+                   | (value<<_EMU_BUACT_BUEXRANGE_SHIFT);
+      break;
+    case emuBODMode_Inactive:
+      EMU->BUINACT = (EMU->BUINACT & ~_EMU_BUINACT_BUENRANGE_MASK)
+                     | (value<<_EMU_BUINACT_BUENRANGE_SHIFT);
+      break;
+  }
+}
+#endif
+
+
+#if defined( _EMU_DCDCCTRL_MASK )
+
+/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
+
+/***************************************************************************//**
+ * @brief
+ *   Load DCDC calibration constants from DI page. Const means calibration
+ *   data that does not change depending on other configuration parameters.
+ *
+ * @return
+ *   False if calibration registers are locked
+ ******************************************************************************/
+static bool ConstCalibrationLoad(void)
+{
+  uint32_t val;
+  volatile uint32_t *reg;
+
+  /* DI calib data in flash */
+  volatile uint32_t* const diCal_EMU_DCDCLNFREQCTRL =  (volatile uint32_t *)(0x0FE08038);
+  volatile uint32_t* const diCal_EMU_DCDCLNVCTRL =     (volatile uint32_t *)(0x0FE08040);
+  volatile uint32_t* const diCal_EMU_DCDCLPCTRL =      (volatile uint32_t *)(0x0FE08048);
+  volatile uint32_t* const diCal_EMU_DCDCLPVCTRL =     (volatile uint32_t *)(0x0FE08050);
+  volatile uint32_t* const diCal_EMU_DCDCTRIM0 =       (volatile uint32_t *)(0x0FE08058);
+  volatile uint32_t* const diCal_EMU_DCDCTRIM1 =       (volatile uint32_t *)(0x0FE08060);
+
+  if (DEVINFO->DCDCLPVCTRL0 != UINT_MAX)
+  {
+    val = *(diCal_EMU_DCDCLNFREQCTRL + 1);
+    reg = (volatile uint32_t *)*diCal_EMU_DCDCLNFREQCTRL;
+    *reg = val;
+
+    val = *(diCal_EMU_DCDCLNVCTRL + 1);
+    reg = (volatile uint32_t *)*diCal_EMU_DCDCLNVCTRL;
+    *reg = val;
+
+    val = *(diCal_EMU_DCDCLPCTRL + 1);
+    reg = (volatile uint32_t *)*diCal_EMU_DCDCLPCTRL;
+    *reg = val;
+
+    val = *(diCal_EMU_DCDCLPVCTRL + 1);
+    reg = (volatile uint32_t *)*diCal_EMU_DCDCLPVCTRL;
+    *reg = val;
+
+    val = *(diCal_EMU_DCDCTRIM0 + 1);
+    reg = (volatile uint32_t *)*diCal_EMU_DCDCTRIM0;
+    *reg = val;
+
+    val = *(diCal_EMU_DCDCTRIM1 + 1);
+    reg = (volatile uint32_t *)*diCal_EMU_DCDCTRIM1;
+    *reg = val;
+
+    return true;
+  }
+  EFM_ASSERT(false);
+  /* Return when assertions are disabled */
+  return false;
+}
+
+
+/***************************************************************************//**
+ * @brief
+ *   Set recommended and validated current optimization settings
+ *
+ ******************************************************************************/
+void ValidatedConfigSet(void)
+{
+#define EMU_DCDCSMCTRL  (* (volatile uint32_t *)(EMU_BASE + 0x44))
+
+  uint32_t dcdcTiming;
+  SYSTEM_PartFamily_TypeDef family;
+  SYSTEM_ChipRevision_TypeDef rev;
+
+  /* Enable duty cycling of the bias */
+  EMU->DCDCLPCTRL |= EMU_DCDCLPCTRL_LPVREFDUTYEN;
+
+  /* Set low-noise RCO for EFM32 and EFR32 */
+#if defined( _EFR_DEVICE )
+  /* 7MHz is recommended for all EFR32 parts with DCDC */
+  EMU->DCDCLNFREQCTRL = (EMU->DCDCLNFREQCTRL & ~_EMU_DCDCLNFREQCTRL_RCOBAND_MASK)
+                          | (EMU_DcdcLnRcoBand_7MHz << _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT);
+#else
+  /* 3MHz is recommended for all EFM32 parts with DCDC */
+  EMU->DCDCLNFREQCTRL = (EMU->DCDCLNFREQCTRL & ~_EMU_DCDCLNFREQCTRL_RCOBAND_MASK)
+                          | (EMU_DcdcLnRcoBand_3MHz << _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT);
+#endif
+
+  EMU->DCDCTIMING &= ~_EMU_DCDCTIMING_DUTYSCALE_MASK;
+
+  family = SYSTEM_GetFamily();
+  SYSTEM_ChipRevisionGet(&rev);
+  if ((((family >= systemPartFamilyMighty1P)
+         && (family <= systemPartFamilyFlex1V))
+       || (family == systemPartFamilyEfm32Pearl1B)
+       || (family == systemPartFamilyEfm32Jade1B))
+      && ((rev.major == 1) && (rev.minor < 3))
+      && (errataFixDcdcHsState == errataFixDcdcHsInit))
+  {
+    /* LPCMPWAITDIS = 1 */
+    EMU_DCDCSMCTRL |= 1;
+
+    dcdcTiming = EMU->DCDCTIMING;
+    dcdcTiming &= ~(_EMU_DCDCTIMING_LPINITWAIT_MASK
+                    |_EMU_DCDCTIMING_LNWAIT_MASK
+                    |_EMU_DCDCTIMING_BYPWAIT_MASK);
+
+    dcdcTiming |= ((180 << _EMU_DCDCTIMING_LPINITWAIT_SHIFT)
+                   | (12 << _EMU_DCDCTIMING_LNWAIT_SHIFT)
+                   | (180 << _EMU_DCDCTIMING_BYPWAIT_SHIFT));
+    EMU->DCDCTIMING = dcdcTiming;
+
+    errataFixDcdcHsState = errataFixDcdcHsTrimSet;
   }
 }
 
+
+/***************************************************************************//**
+ * @brief
+ *   Calculate and update EMU->DCDCMISCCTRL for maximum DCDC current based
+ *   on the slice configuration and user set maximum.
+ ******************************************************************************/
+static void maxCurrentUpdate(void)
+{
+  uint32_t lncLimImSel;
+  uint32_t lpcLimImSel;
+  uint32_t pFetCnt;
+
+  pFetCnt = (EMU->DCDCMISCCTRL & _EMU_DCDCMISCCTRL_PFETCNT_MASK)
+             >> _EMU_DCDCMISCCTRL_PFETCNT_SHIFT;
+
+  /* Equation from Reference Manual section 11.5.20, in the register
+     field description for LNCLIMILIMSEL and LPCLIMILIMSEL. */
+  lncLimImSel = (dcdcMaxCurrent_mA / (5 * (pFetCnt + 1))) - 1;
+  /* 80mA as recommended in Application Note AN0948 */
+  lpcLimImSel = (80 / (5 * (pFetCnt + 1))) - 1;
+
+  lncLimImSel <<= _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT;
+  lpcLimImSel <<= _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_SHIFT;
+  EMU->DCDCMISCCTRL = (EMU->DCDCMISCCTRL & ~(_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK
+                                             | _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK))
+                       | (lncLimImSel | lpcLimImSel);
+}
+
+
+/***************************************************************************//**
+ * @brief
+ *   Set static variable that holds the user set maximum current. Update
+ *   DCDC configuration.
+ *
+ * @param[in] mAmaxCurrent
+ *   Maximum allowed current drawn by the DCDC from VREGVDD in mA.
+ ******************************************************************************/
+static void maxCurrentSet(uint32_t mAmaxCurrent)
+{
+  dcdcMaxCurrent_mA = mAmaxCurrent;
+  maxCurrentUpdate();
+}
+
+
+/***************************************************************************//**
+ * @brief
+ *   Load EMU_DCDCLPCTRL_LPCMPHYSSEL depending on LP bias, LP feedback
+ *   attenuation and DEVINFOREV.
+ *
+ * @param[in] attSet
+ *   LP feedback attenuation.
+ * @param[in] lpCmpBias
+ *   lpCmpBias selection
+ ******************************************************************************/
+static bool LpCmpHystCalibrationLoad(bool lpAttenuation, uint32_t lpCmpBias)
+{
+  uint8_t devinfoRev;
+  uint32_t lpcmpHystSel;
+
+  /* Get calib data revision */
+  devinfoRev = SYSTEM_GetDevinfoRev();
+
+  /* Load LPATT indexed calibration data */
+  if (devinfoRev < 4)
+  {
+    lpcmpHystSel = DEVINFO->DCDCLPCMPHYSSEL0;
+
+    if (lpAttenuation)
+    {
+      lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_MASK)
+                      >> _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_SHIFT;
+    }
+    else
+    {
+      lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_MASK)
+                      >> _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_SHIFT;
+    }
+  }
+  /* devinfoRev >= 4
+     Load LPCMPBIAS indexed calibration data */
+  else
+  {
+    lpcmpHystSel = DEVINFO->DCDCLPCMPHYSSEL1;
+    switch (lpCmpBias)
+    {
+      case _EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS0:
+        lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_MASK)
+                        >> _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_SHIFT;
+        break;
+
+      case _EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS1:
+        lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_MASK)
+                        >> _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_SHIFT;
+        break;
+
+      case _EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS2:
+        lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_MASK)
+                        >> _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_SHIFT;
+        break;
+
+      case _EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS3:
+        lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_MASK)
+                        >> _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_SHIFT;
+        break;
+
+      default:
+        EFM_ASSERT(false);
+        /* Return when assertions are disabled */
+        return false;
+    }
+  }
+
+  /* Make sure the sel value is within the field range. */
+  lpcmpHystSel <<= _EMU_DCDCLPCTRL_LPCMPHYSSEL_SHIFT;
+  if (lpcmpHystSel & ~_EMU_DCDCLPCTRL_LPCMPHYSSEL_MASK)
+  {
+    EFM_ASSERT(false);
+    /* Return when assertions are disabled */
+    return false;
+  }
+  EMU->DCDCLPCTRL = (EMU->DCDCLPCTRL & ~_EMU_DCDCLPCTRL_LPCMPHYSSEL_MASK) | lpcmpHystSel;
+
+  return true;
+}
+
+
+/** @endcond */
+
+/***************************************************************************//**
+ * @brief
+ *   Set DCDC regulator operating mode
+ *
+ * @param[in] dcdcMode
+ *   DCDC mode
+ ******************************************************************************/
+void EMU_DCDCModeSet(EMU_DcdcMode_TypeDef dcdcMode)
+{
+  while(EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY);
+  BUS_RegBitWrite(&EMU->DCDCCLIMCTRL, _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT, dcdcMode == emuDcdcMode_Bypass ? 0 : 1);
+  EMU->DCDCCTRL = (EMU->DCDCCTRL & ~_EMU_DCDCCTRL_DCDCMODE_MASK) | dcdcMode;
+}
+
+
+/***************************************************************************//**
+ * @brief
+ *   Configure DCDC regulator
+ *
+ * @note
+ *   Use the function EMU_DCDCPowerDown() to if the power circuit is configured
+ *   for NODCDC as decribed in Section 11.3.4.3 in the Reference Manual.
+ *
+ * @param[in] dcdcInit
+ *   DCDC initialization structure
+ *
+ * @return
+ *   True if initialization parameters are valid
+ ******************************************************************************/
+bool EMU_DCDCInit(EMU_DCDCInit_TypeDef *dcdcInit)
+{
+  uint32_t lpCmpBiasSel;
+
+  /* Set external power configuration. This enables writing to the other
+     DCDC registers. */
+  EMU->PWRCFG = dcdcInit->powerConfig;
+
+  /* EMU->PWRCFG is write-once and POR reset only. Check that
+     we could set the desired power configuration. */
+  if ((EMU->PWRCFG & _EMU_PWRCFG_PWRCFG_MASK) != dcdcInit->powerConfig)
+  {
+    /* If this assert triggers unexpectedly, please power cycle the
+       kit to reset the power configuration. */
+    EFM_ASSERT(false);
+    /* Return when assertions are disabled */
+    return false;
+  }
+
+  /* Load DCDC calibration data from the DI page */
+  ConstCalibrationLoad();
+
+  /* Check current parameters */
+  EFM_ASSERT(dcdcInit->maxCurrent_mA <= 200);
+  EFM_ASSERT(dcdcInit->em01LoadCurrent_mA <= dcdcInit->maxCurrent_mA);
+
+  /* DCDC low-noise supports max 200mA */
+  if (dcdcInit->dcdcMode == emuDcdcMode_LowNoise)
+  {
+    EFM_ASSERT(dcdcInit->em01LoadCurrent_mA <= 200);
+  }
+
+  /* EM2, 3 and 4 current above 100uA is not supported */
+  EFM_ASSERT(dcdcInit->em234LoadCurrent_uA <= 100);
+
+  /* Decode LP comparator bias for EM0/1 and EM2/3 */
+  lpCmpBiasSel  = EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS1;
+  if (dcdcInit->em234LoadCurrent_uA <= 10)
+  {
+    lpCmpBiasSel  = EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS0;
+  }
+
+  /* Set DCDC low-power mode comparator bias selection */
+  EMU->DCDCMISCCTRL = (EMU->DCDCMISCCTRL & ~(_EMU_DCDCMISCCTRL_LPCMPBIAS_MASK
+                                             | _EMU_DCDCMISCCTRL_LNFORCECCM_MASK))
+                       | ((uint32_t)lpCmpBiasSel
+                          | (uint32_t)dcdcInit->lnTransientMode);
+
+  /* Set recommended and validated current optimization settings */
+  ValidatedConfigSet();
+
+  /* Set the maximum current that the DCDC can draw from the power source */
+  maxCurrentSet(dcdcInit->maxCurrent_mA);
+
+  /* Optimize LN slice based on given load current estimate */
+  EMU_DCDCOptimizeSlice(dcdcInit->em01LoadCurrent_mA);
+
+  /* Set DCDC output voltage */
+  dcdcOutput_mVout = dcdcInit->mVout;
+  if (!EMU_DCDCOutputVoltageSet(dcdcOutput_mVout, true, true))
+  {
+    EFM_ASSERT(false);
+    /* Return when assertions are disabled */
+    return false;
+  }
+
+  /* Set EM0 DCDC operating mode. Output voltage set in EMU_DCDCOutputVoltageSet()
+     above takes effect if mode is changed from bypass here. */
+  EMU_DCDCModeSet(dcdcInit->dcdcMode);
+
+  /* Select analog peripheral power supply */
+  BUS_RegBitWrite(&EMU->PWRCTRL, _EMU_PWRCTRL_ANASW_SHIFT, dcdcInit->anaPeripheralPower ? 1 : 0);
+
+  return true;
+}
+
+
+/***************************************************************************//**
+ * @brief
+ *   Set DCDC output voltage
+ *
+ * @param[in] mV
+ *   Target DCDC output voltage in mV
+ *
+ * @return
+ *   True if the mV parameter is valid
+ ******************************************************************************/
+bool EMU_DCDCOutputVoltageSet(uint32_t mV,
+                              bool setLpVoltage,
+                              bool setLnVoltage)
+{
+#if defined( _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_MASK )
+
+  bool validOutVoltage;
+  uint8_t lnMode;
+  bool attSet;
+  uint32_t attMask;
+  uint32_t vrefLow = 0;
+  uint32_t vrefHigh = 0;
+  uint32_t vrefVal = 0;
+  uint32_t mVlow = 0;
+  uint32_t mVhigh = 0;
+  uint32_t vrefShift;
+  uint32_t lpcmpBias;
+  volatile uint32_t* ctrlReg;
+
+  /* Check that the set voltage is within valid range.
+     Voltages are obtained from the datasheet. */
+  validOutVoltage = false;
+  if ((EMU->PWRCFG & _EMU_PWRCFG_PWRCFG_MASK) == EMU_PWRCFG_PWRCFG_DCDCTODVDD)
+  {
+    validOutVoltage = ((mV >= PWRCFG_DCDCTODVDD_VMIN)
+                       && (mV <= PWRCFG_DCDCTODVDD_VMAX));
+  }
+
+  if (!validOutVoltage)
+  {
+    EFM_ASSERT(false);
+    /* Return when assertions are disabled */
+    return false;
+  }
+
+  /* Populate both LP and LN registers, set control reg pointer and VREF shift. */
+  for (lnMode = 0; lnMode <= 1; lnMode++)
+  {
+    if (((lnMode == 0) && !setLpVoltage)
+        || ((lnMode == 1) && !setLnVoltage))
+    {
+      continue;
+    }
+
+    ctrlReg   = (lnMode ? &EMU->DCDCLNVCTRL : &EMU->DCDCLPVCTRL);
+    vrefShift = (lnMode ? _EMU_DCDCLNVCTRL_LNVREF_SHIFT
+                        : _EMU_DCDCLPVCTRL_LPVREF_SHIFT);
+
+    /* Set attenuation to use */
+    attSet = (mV > 1800);
+    if (attSet)
+    {
+      mVlow = 1800;
+      mVhigh = 3000;
+      attMask = (lnMode ? EMU_DCDCLNVCTRL_LNATT : EMU_DCDCLPVCTRL_LPATT);
+    }
+    else
+    {
+      mVlow = 1200;
+      mVhigh = 1800;
+      attMask = 0;
+    }
+
+    /* Get 2-point calib data from DEVINFO, calculate trimming and set voltege */
+    if (lnMode)
+    {
+      /* Set low-noise DCDC output voltage tuning */
+      if (attSet)
+      {
+        vrefLow  = DEVINFO->DCDCLNVCTRL0;
+        vrefHigh = (vrefLow & _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_MASK)
+                   >> _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_SHIFT;
+        vrefLow  = (vrefLow & _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_MASK)
+                   >> _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_SHIFT;
+      }
+      else
+      {
+        vrefLow  = DEVINFO->DCDCLNVCTRL0;
+        vrefHigh = (vrefLow & _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_MASK)
+                   >> _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_SHIFT;
+        vrefLow  = (vrefLow & _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_MASK)
+                   >> _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_SHIFT;
+      }
+    }
+    else
+    {
+      /* Set low-power DCDC output voltage tuning */
+
+      /* Get LPCMPBIAS and make sure masks are not overlayed */
+      lpcmpBias = EMU->DCDCMISCCTRL & _EMU_DCDCMISCCTRL_LPCMPBIAS_MASK;
+      EFM_ASSERT(!(_EMU_DCDCMISCCTRL_LPCMPBIAS_MASK & attMask));
+      switch (attMask | lpcmpBias)
+      {
+        case EMU_DCDCLPVCTRL_LPATT | EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS0:
+          vrefLow  = DEVINFO->DCDCLPVCTRL2;
+          vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_MASK)
+                     >> _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_SHIFT;
+          vrefLow  = (vrefLow & _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_MASK)
+                     >> _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_SHIFT;
+          break;
+
+        case EMU_DCDCLPVCTRL_LPATT | EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS1:
+          vrefLow  = DEVINFO->DCDCLPVCTRL2;
+          vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_MASK)
+                     >> _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_SHIFT;
+          vrefLow  = (vrefLow & _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_MASK)
+                     >> _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_SHIFT;
+          break;
+
+        case EMU_DCDCLPVCTRL_LPATT | EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS2:
+          vrefLow  = DEVINFO->DCDCLPVCTRL3;
+          vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_MASK)
+                     >> _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_SHIFT;
+          vrefLow  = (vrefLow & _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_MASK)
+                     >> _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_SHIFT;
+          break;
+
+        case EMU_DCDCLPVCTRL_LPATT | EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS3:
+          vrefLow  = DEVINFO->DCDCLPVCTRL3;
+          vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_MASK)
+                     >> _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_SHIFT;
+          vrefLow  = (vrefLow & _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_MASK)
+                     >> _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_SHIFT;
+          break;
+
+        case EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS0:
+          vrefLow  = DEVINFO->DCDCLPVCTRL0;
+          vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_MASK)
+                     >> _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_SHIFT;
+          vrefLow  = (vrefLow & _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_MASK)
+                     >> _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_SHIFT;
+          break;
+
+        case EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS1:
+          vrefLow  = DEVINFO->DCDCLPVCTRL0;
+          vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_MASK)
+                     >> _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_SHIFT;
+          vrefLow  = (vrefLow & _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_MASK)
+                     >> _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_SHIFT;
+          break;
+
+        case EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS2:
+          vrefLow  = DEVINFO->DCDCLPVCTRL1;
+          vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_MASK)
+                     >> _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_SHIFT;
+          vrefLow  = (vrefLow & _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_MASK)
+                     >> _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_SHIFT;
+          break;
+
+        case EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS3:
+          vrefLow  = DEVINFO->DCDCLPVCTRL1;
+          vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_MASK)
+                     >> _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_SHIFT;
+          vrefLow  = (vrefLow & _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_MASK)
+                     >> _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_SHIFT;
+          break;
+
+        default:
+          EFM_ASSERT(false);
+          break;
+      }
+
+      /* Load LP comparator hysteresis calibration */
+      if(!(LpCmpHystCalibrationLoad(attSet, lpcmpBias >> _EMU_DCDCMISCCTRL_LPCMPBIAS_SHIFT)))
+      {
+        EFM_ASSERT(false);
+        /* Return when assertions are disabled */
+        return false;
+      }
+    } /* Low-nise / low-power mode */
+
+
+    /* Check for valid 2-point trim values */
+    if ((vrefLow == 0xFF) && (vrefHigh == 0xFF))
+    {
+      EFM_ASSERT(false);
+      /* Return when assertions are disabled */
+      return false;
+    }
+
+    /* Calculate and set voltage trim */
+    vrefVal = ((mV - mVlow) * (vrefHigh - vrefLow))  / (mVhigh - mVlow);
+    vrefVal += vrefLow;
+
+    /* Range check */
+    if ((vrefVal > vrefHigh) || (vrefVal < vrefLow))
+    {
+      EFM_ASSERT(false);
+      /* Return when assertions are disabled */
+      return false;
+    }
+
+    /* Update DCDCLNVCTRL/DCDCLPVCTRL */
+    *ctrlReg = (vrefVal << vrefShift) | attMask;
+  }
+#endif
+  return true;
+}
+
+
+/***************************************************************************//**
+ * @brief
+ *   Optimize DCDC slice count based on the estimated average load current
+ *   in EM0
+ *
+ * @param[in] mAEm0LoadCurrent
+ *   Estimated average EM0 load current in mA.
+ ******************************************************************************/
+void EMU_DCDCOptimizeSlice(uint32_t mAEm0LoadCurrent)
+{
+  uint32_t sliceCount = 0;
+  uint32_t rcoBand = (EMU->DCDCLNFREQCTRL & _EMU_DCDCLNFREQCTRL_RCOBAND_MASK)
+                      >> _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT;
+
+  /* Set recommended slice count */
+  if ((EMU->DCDCMISCCTRL & _EMU_DCDCMISCCTRL_LNFORCECCM_MASK) && (rcoBand >= EMU_DcdcLnRcoBand_5MHz))
+  {
+    if (mAEm0LoadCurrent < 20)
+    {
+      sliceCount = 4;
+    }
+    else if ((mAEm0LoadCurrent >= 20) && (mAEm0LoadCurrent < 40))
+    {
+      sliceCount = 8;
+    }
+    else
+    {
+      sliceCount = 16;
+    }
+  }
+  else if ((!(EMU->DCDCMISCCTRL & _EMU_DCDCMISCCTRL_LNFORCECCM_MASK)) && (rcoBand <= EMU_DcdcLnRcoBand_4MHz))
+  {
+    if (mAEm0LoadCurrent < 10)
+    {
+      sliceCount = 4;
+    }
+    else if ((mAEm0LoadCurrent >= 10) && (mAEm0LoadCurrent < 20))
+    {
+      sliceCount = 8;
+    }
+    else
+    {
+      sliceCount = 16;
+    }
+  }
+  else if ((EMU->DCDCMISCCTRL & _EMU_DCDCMISCCTRL_LNFORCECCM_MASK) && (rcoBand <= EMU_DcdcLnRcoBand_4MHz))
+  {
+    if (mAEm0LoadCurrent < 40)
+    {
+      sliceCount = 8;
+    }
+    else
+    {
+      sliceCount = 16;
+    }
+  }
+  else
+  {
+    /* This configuration is not recommended. EMU_DCDCInit() applies a recommended
+       configuration. */
+    EFM_ASSERT(false);
+  }
+
+  /* The selected silices are PSLICESEL + 1 */
+  sliceCount--;
+
+  /* Apply slice count to both N and P slice */
+  sliceCount = (sliceCount << _EMU_DCDCMISCCTRL_PFETCNT_SHIFT
+                | sliceCount << _EMU_DCDCMISCCTRL_NFETCNT_SHIFT);
+  EMU->DCDCMISCCTRL = (EMU->DCDCMISCCTRL & ~(_EMU_DCDCMISCCTRL_PFETCNT_MASK
+                                             | _EMU_DCDCMISCCTRL_NFETCNT_MASK))
+                      | sliceCount;
+
+  /* Update current limit configuration as it depends on the slice configuration. */
+  maxCurrentUpdate();
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Set DCDC Low-noise RCO band.
+ *
+ * @param[in] band
+ *   RCO band to set.
+ ******************************************************************************/
+void EMU_DCDCLnRcoBandSet(EMU_DcdcLnRcoBand_TypeDef band)
+{
+  EMU->DCDCLNFREQCTRL = (EMU->DCDCLNFREQCTRL & ~_EMU_DCDCLNFREQCTRL_RCOBAND_MASK)
+                         | (band << _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT);
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Power off the DCDC regulator.
+ *
+ * @details
+ *   This function powers off the DCDC controller. This function should only be
+ *   used if the external power circuit is wired for no DCDC. If the external power
+ *   circuit is wired for DCDC usage, then use EMU_DCDCInit() and set the
+ *   DCDC in bypass mode to disable DCDC.
+ *
+ * @return
+ *   Return false if the DCDC could not be disabled.
+ ******************************************************************************/
+bool EMU_DCDCPowerOff(void)
+{
+  /* Set power configuration to hard bypass */
+  EMU->PWRCFG = 0xF;
+  if ((EMU->PWRCFG & _EMU_PWRCFG_PWRCFG_MASK) != 0xF)
+  {
+    EFM_ASSERT(false);
+    /* Return when assertions are disabled */
+    return false;
+  }
+
+  /* Set DCDC to OFF and disable LP in EM2/3/4 */
+  EMU->DCDCCTRL = EMU_DCDCCTRL_DCDCMODE_OFF;
+  return true;
+}
 #endif
 
 
+#if defined( EMU_STATUS_VMONRDY )
+/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
+__STATIC_INLINE uint32_t vmonMilliVoltToCoarseThreshold(int mV)
+{
+  return (mV - 1200) / 200;
+}
+
+__STATIC_INLINE uint32_t vmonMilliVoltToFineThreshold(int mV, uint32_t coarseThreshold)
+{
+  return (mV - 1200 - (coarseThreshold * 200)) / 20;
+}
+/** @endcond */
+
+/***************************************************************************//**
+ * @brief
+ *   Initialize VMON channel.
+ *
+ * @details
+ *   Initialize a VMON channel without hysteresis. If the channel supports
+ *   separate rise and fall triggers, both thresholds will be set to the same
+ *   value.
+ *
+ * @param[in] vmonInit
+ *   VMON initialization struct
+ ******************************************************************************/
+void EMU_VmonInit(EMU_VmonInit_TypeDef *vmonInit)
+{
+  uint32_t thresholdCoarse, thresholdFine;
+  EFM_ASSERT((vmonInit->threshold >= 1200) && (vmonInit->threshold <= 3980));
+
+  thresholdCoarse = vmonMilliVoltToCoarseThreshold(vmonInit->threshold);
+  thresholdFine = vmonMilliVoltToFineThreshold(vmonInit->threshold, thresholdCoarse);
+
+  switch(vmonInit->channel)
+  {
+  case emuVmonChannel_AVDD:
+    EMU->VMONAVDDCTRL = (thresholdCoarse << _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT)
+                      | (thresholdFine << _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT)
+                      | (thresholdCoarse << _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT)
+                      | (thresholdFine << _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT)
+                      | (vmonInit->riseWakeup ? EMU_VMONAVDDCTRL_RISEWU : 0)
+                      | (vmonInit->fallWakeup ? EMU_VMONAVDDCTRL_FALLWU : 0)
+                      | (vmonInit->enable     ? EMU_VMONAVDDCTRL_EN     : 0);
+    break;
+  case emuVmonChannel_ALTAVDD:
+    EMU->VMONALTAVDDCTRL = (thresholdCoarse << _EMU_VMONALTAVDDCTRL_THRESCOARSE_SHIFT)
+                         | (thresholdFine << _EMU_VMONALTAVDDCTRL_THRESFINE_SHIFT)
+                         | (vmonInit->riseWakeup ? EMU_VMONALTAVDDCTRL_RISEWU : 0)
+                         | (vmonInit->fallWakeup ? EMU_VMONALTAVDDCTRL_FALLWU : 0)
+                         | (vmonInit->enable     ? EMU_VMONALTAVDDCTRL_EN     : 0);
+    break;
+  case emuVmonChannel_DVDD:
+    EMU->VMONDVDDCTRL = (thresholdCoarse << _EMU_VMONDVDDCTRL_THRESCOARSE_SHIFT)
+                      | (thresholdFine << _EMU_VMONDVDDCTRL_THRESFINE_SHIFT)
+                      | (vmonInit->riseWakeup ? EMU_VMONDVDDCTRL_RISEWU : 0)
+                      | (vmonInit->fallWakeup ? EMU_VMONDVDDCTRL_FALLWU : 0)
+                      | (vmonInit->enable     ? EMU_VMONDVDDCTRL_EN     : 0);
+    break;
+  case emuVmonChannel_IOVDD0:
+    EMU->VMONIO0CTRL = (thresholdCoarse << _EMU_VMONIO0CTRL_THRESCOARSE_SHIFT)
+                     | (thresholdFine << _EMU_VMONIO0CTRL_THRESFINE_SHIFT)
+                     | (vmonInit->retDisable ? EMU_VMONIO0CTRL_RETDIS : 0)
+                     | (vmonInit->riseWakeup ? EMU_VMONIO0CTRL_RISEWU : 0)
+                     | (vmonInit->fallWakeup ? EMU_VMONIO0CTRL_FALLWU : 0)
+                     | (vmonInit->enable     ? EMU_VMONIO0CTRL_EN     : 0);
+    break;
+  default:
+    EFM_ASSERT(false);
+    return;
+  }
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Initialize VMON channel with hysteresis (separate rise and fall triggers).
+ *
+ * @details
+ *   Initialize a VMON channel which supports hysteresis. The AVDD channel is
+ *   the only channel to support separate rise and fall triggers.
+ *
+ * @param[in] vmonInit
+ *   VMON Hysteresis initialization struct
+ ******************************************************************************/
+void EMU_VmonHystInit(EMU_VmonHystInit_TypeDef *vmonInit)
+{
+  uint32_t riseThresholdCoarse, riseThresholdFine, fallThresholdCoarse, fallThresholdFine;
+  /* VMON supports voltages between 1200 mV and 3980 mV (inclusive) in 20 mV increments */
+  EFM_ASSERT((vmonInit->riseThreshold >= 1200) && (vmonInit->riseThreshold < 4000));
+  EFM_ASSERT((vmonInit->fallThreshold >= 1200) && (vmonInit->fallThreshold < 4000));
+  /* Fall threshold has to be lower than rise threshold */
+  EFM_ASSERT(vmonInit->fallThreshold <= vmonInit->riseThreshold);
+
+  riseThresholdCoarse = vmonMilliVoltToCoarseThreshold(vmonInit->riseThreshold);
+  riseThresholdFine = vmonMilliVoltToFineThreshold(vmonInit->riseThreshold, riseThresholdCoarse);
+  fallThresholdCoarse = vmonMilliVoltToCoarseThreshold(vmonInit->fallThreshold);
+  fallThresholdFine = vmonMilliVoltToFineThreshold(vmonInit->fallThreshold, fallThresholdCoarse);
+
+  switch(vmonInit->channel)
+  {
+  case emuVmonChannel_AVDD:
+    EMU->VMONAVDDCTRL = (riseThresholdCoarse << _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT)
+                      | (riseThresholdFine << _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT)
+                      | (fallThresholdCoarse << _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT)
+                      | (fallThresholdFine << _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT)
+                      | (vmonInit->riseWakeup ? EMU_VMONAVDDCTRL_RISEWU : 0)
+                      | (vmonInit->fallWakeup ? EMU_VMONAVDDCTRL_FALLWU : 0)
+                      | (vmonInit->enable     ? EMU_VMONAVDDCTRL_EN     : 0);
+    break;
+  default:
+    EFM_ASSERT(false);
+    return;
+  }
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Enable or disable a VMON channel
+ *
+ * @param[in] channel
+ *   VMON channel to enable/disable
+ *
+ * @param[in] enable
+ *   Whether to enable or disable
+ ******************************************************************************/
+void EMU_VmonEnable(EMU_VmonChannel_TypeDef channel, bool enable)
+{
+  uint32_t volatile * reg;
+  uint32_t bit;
+
+  switch(channel)
+  {
+  case emuVmonChannel_AVDD:
+    reg = &(EMU->VMONAVDDCTRL);
+    bit = _EMU_VMONAVDDCTRL_EN_SHIFT;
+    break;
+  case emuVmonChannel_ALTAVDD:
+    reg = &(EMU->VMONALTAVDDCTRL);
+    bit = _EMU_VMONALTAVDDCTRL_EN_SHIFT;
+    break;
+  case emuVmonChannel_DVDD:
+    reg = &(EMU->VMONDVDDCTRL);
+    bit = _EMU_VMONDVDDCTRL_EN_SHIFT;
+    break;
+  case emuVmonChannel_IOVDD0:
+    reg = &(EMU->VMONIO0CTRL);
+    bit = _EMU_VMONIO0CTRL_EN_SHIFT;
+    break;
+  default:
+    EFM_ASSERT(false);
+    return;
+  }
+
+  BUS_RegBitWrite(reg, bit, enable);
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Get the status of a voltage monitor channel.
+ *
+ * @param[in] channel
+ *   VMON channel to get status for
+ *
+ * @return
+ *   Status of the selected VMON channel. True if channel is triggered.
+ ******************************************************************************/
+bool EMU_VmonChannelStatusGet(EMU_VmonChannel_TypeDef channel)
+{
+  uint32_t bit;
+  switch(channel)
+  {
+  case emuVmonChannel_AVDD:
+    bit = _EMU_STATUS_VMONAVDD_SHIFT;
+    break;
+  case emuVmonChannel_ALTAVDD:
+    bit = _EMU_STATUS_VMONALTAVDD_SHIFT;
+    break;
+  case emuVmonChannel_DVDD:
+    bit = _EMU_STATUS_VMONDVDD_SHIFT;
+    break;
+  case emuVmonChannel_IOVDD0:
+    bit = _EMU_STATUS_VMONIO0_SHIFT;
+    break;
+  default:
+    EFM_ASSERT(false);
+    bit = 0;
+  }
+
+  return BUS_RegBitRead(&EMU->STATUS, bit);
+}
+#endif /* EMU_STATUS_VMONRDY */
+
 /** @} (end addtogroup EMU) */
 /** @} (end addtogroup EM_Library) */
 #endif /* __EM_EMU_H */

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_gpio.c	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_gpio.c	Fri Jan 15 07:45:16 2016 +0000
@@ -2,10 +2,10 @@
  * @file em_gpio.c
  * @brief General Purpose IO (GPIO) peripheral API
  *   devices.
- * @version 3.20.12
+ * @version 4.2.1
  *******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
  *******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -35,6 +35,7 @@
 #include "em_gpio.h"
 
 #if defined(GPIO_COUNT) && (GPIO_COUNT > 0)
+
 /***************************************************************************//**
  * @addtogroup EM_Library
  * @{
@@ -54,7 +55,9 @@
 
 /** Validation of pin typically usable in assert statements. */
 #define GPIO_DRIVEMODE_VALID(mode)    ((mode) <= 3)
-
+#define GPIO_STRENGHT_VALID(strenght) (!((strenght) & \
+                                         ~(_GPIO_P_CTRL_DRIVESTRENGTH_MASK \
+                                           | _GPIO_P_CTRL_DRIVESTRENGTHALT_MASK)))
 /** @endcond */
 
 
@@ -84,7 +87,7 @@
 #endif
 }
 
-
+#if defined (_GPIO_P_CTRL_DRIVEMODE_MASK)
 /***************************************************************************//**
  * @brief
  *   Sets the drive mode for a GPIO port.
@@ -102,8 +105,30 @@
   GPIO->P[port].CTRL = (GPIO->P[port].CTRL & ~(_GPIO_P_CTRL_DRIVEMODE_MASK))
                        | (mode << _GPIO_P_CTRL_DRIVEMODE_SHIFT);
 }
+#endif
 
 
+#if defined (_GPIO_P_CTRL_DRIVESTRENGTH_MASK)
+/***************************************************************************//**
+ * @brief
+ *   Sets the drive strength for a GPIO port.
+ *
+ * @param[in] port
+ *   The GPIO port to access.
+ *
+ * @param[in] strength
+ *   Drive strength to use for port.
+ ******************************************************************************/
+void GPIO_DriveStrengthSet(GPIO_Port_TypeDef port,
+                           GPIO_DriveStrength_TypeDef strength)
+{
+  EFM_ASSERT(GPIO_PORT_VALID(port) && GPIO_STRENGHT_VALID(strength));
+  BUS_RegMaskedWrite(&GPIO->P[port].CTRL,
+                     _GPIO_P_CTRL_DRIVESTRENGTH_MASK | _GPIO_P_CTRL_DRIVESTRENGTHALT_MASK,
+                     strength);
+}
+#endif
+
 /***************************************************************************//**
  * @brief
  *   Configure GPIO interrupt.
@@ -148,34 +173,36 @@
 {
   uint32_t tmp;
 
-  EFM_ASSERT(GPIO_PORT_VALID(port) && GPIO_PIN_VALID(pin));
+  EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin));
 
   /* There are two registers controlling the interrupt configuration:
    * The EXTIPSELL register controls pins 0-7 and EXTIPSELH controls
    * pins 8-15. */
   if (pin < 8)
   {
-    GPIO->EXTIPSELL = (GPIO->EXTIPSELL & ~(0xF << (4 * pin))) |
-                      (port << (4 * pin));
+    BUS_RegMaskedWrite(&GPIO->EXTIPSELL,
+                       0xF << (4 * pin),
+                       port << (4 * pin));
   }
   else
   {
     tmp             = pin - 8;
-    GPIO->EXTIPSELH = (GPIO->EXTIPSELH & ~(0xF << (4 * tmp))) |
-                      (port << (4 * tmp));
+    BUS_RegMaskedWrite(&GPIO->EXTIPSELH,
+                       0xF << (4 * tmp),
+                       port << (4 * tmp));
   }
 
   /* Enable/disable rising edge */
-  BITBAND_Peripheral(&(GPIO->EXTIRISE), pin, (unsigned int)risingEdge);
+  BUS_RegBitWrite(&(GPIO->EXTIRISE), pin, risingEdge);
 
   /* Enable/disable falling edge */
-  BITBAND_Peripheral(&(GPIO->EXTIFALL), pin, (unsigned int)fallingEdge);
+  BUS_RegBitWrite(&(GPIO->EXTIFALL), pin, fallingEdge);
 
   /* Clear any pending interrupt */
   GPIO->IFC = 1 << pin;
 
   /* Finally enable/disable interrupt */
-  BITBAND_Peripheral(&(GPIO->IEN), pin, (unsigned int)enable);
+  BUS_RegBitWrite(&(GPIO->IEN), pin, enable);
 }
 
 
@@ -201,7 +228,7 @@
                      GPIO_Mode_TypeDef mode,
                      unsigned int out)
 {
-  EFM_ASSERT(GPIO_PORT_VALID(port) && GPIO_PIN_VALID(pin));
+  EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin));
 
   /* If disabling pin, do not modify DOUT in order to reduce chance for */
   /* glitch/spike (may not be sufficient precaution in all use cases) */
@@ -209,11 +236,11 @@
   {
     if (out)
     {
-      GPIO->P[port].DOUTSET = 1 << pin;
+      GPIO_PinOutSet(port, pin);
     }
     else
     {
-      GPIO->P[port].DOUTCLR = 1 << pin;
+      GPIO_PinOutClear(port, pin);
     }
   }
 
@@ -221,28 +248,72 @@
    * register controls pins 0-7 and MODEH controls pins 8-15. */
   if (pin < 8)
   {
-    GPIO->P[port].MODEL = (GPIO->P[port].MODEL & ~(0xF << (pin * 4))) |
-                          (mode << (pin * 4));
+    BUS_RegMaskedWrite(&GPIO->P[port].MODEL,
+                       0xF << (pin * 4),
+                       mode << (pin * 4));
   }
   else
   {
-    GPIO->P[port].MODEH = (GPIO->P[port].MODEH & ~(0xF << ((pin - 8) * 4))) |
-                          (mode << ((pin - 8) * 4));
+    BUS_RegMaskedWrite(&GPIO->P[port].MODEH,
+                       0xF << ((pin - 8) * 4),
+                       mode << ((pin - 8) * 4));
   }
 
   if (mode == gpioModeDisabled)
   {
     if (out)
     {
-      GPIO->P[port].DOUTSET = 1 << pin;
+      GPIO_PinOutSet(port, pin);
     }
     else
     {
-      GPIO->P[port].DOUTCLR = 1 << pin;
+      GPIO_PinOutClear(port, pin);
     }
   }
 }
 
+#if defined( _GPIO_EM4WUEN_MASK )
+/**************************************************************************//**
+ * @brief
+ *   Enable GPIO pin wake-up from EM4. When the function exits,
+ *   EM4 mode can be safely entered.
+ *
+ * @note
+ *   It is assumed that the GPIO pin modes are set correctly.
+ *   Valid modes are @ref gpioModeInput and @ref gpioModeInputPull.
+ *
+ * @param[in] pinmask
+ *   Bitmask containing the bitwise logic OR of which GPIO pin(s) to enable.
+ *   Refer to Reference Manuals for pinmask to GPIO port/pin mapping.
+ * @param[in] polaritymask
+ *   Bitmask containing the bitwise logic OR of GPIO pin(s) wake-up polarity.
+ *   Refer to Reference Manuals for pinmask to GPIO port/pin mapping.
+ *****************************************************************************/
+void GPIO_EM4EnablePinWakeup(uint32_t pinmask, uint32_t polaritymask)
+{
+  EFM_ASSERT((pinmask & ~_GPIO_EM4WUEN_MASK) == 0);
+
+#if defined( _GPIO_EM4WUPOL_MASK )
+  EFM_ASSERT((polaritymask & ~_GPIO_EM4WUPOL_MASK) == 0);
+  GPIO->EM4WUPOL &= ~pinmask;               /* Set wakeup polarity */
+  GPIO->EM4WUPOL |= pinmask & polaritymask;
+#elif defined( _GPIO_EXTILEVEL_MASK )
+  EFM_ASSERT((polaritymask & ~_GPIO_EXTILEVEL_MASK) == 0);
+  GPIO->EXTILEVEL &= ~pinmask;
+  GPIO->EXTILEVEL |= pinmask & polaritymask;
+#endif
+  GPIO->EM4WUEN  |= pinmask;                /* Enable wakeup */
+
+  GPIO_EM4SetPinRetention(true);            /* Enable pin retention */
+
+#if defined( _GPIO_CMD_EM4WUCLR_MASK )
+  GPIO->CMD = GPIO_CMD_EM4WUCLR;            /* Clear wake-up logic */
+#elif defined( _GPIO_IFC_EM4WU_MASK )
+  GPIO_IntClear(pinmask);
+#endif
+}
+#endif
+
 /** @} (end addtogroup GPIO) */
 /** @} (end addtogroup EM_Library) */
 

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_i2c.c	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_i2c.c	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /***************************************************************************//**
  * @file em_i2c.c
  * @brief Inter-integrated Circuit (I2C) Peripheral API
- * @version 3.20.12
+ * @version 4.2.1
  *******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
  *******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,14 +30,15 @@
  *
  ******************************************************************************/
 
-
 #include "em_i2c.h"
 #if defined(I2C_COUNT) && (I2C_COUNT > 0)
 
 #include "em_cmu.h"
-#include "em_bitband.h"
+#include "em_bus.h"
 #include "em_assert.h"
 
+ #include <limits.h>
+
 /***************************************************************************//**
  * @addtogroup EM_Library
  * @{
@@ -55,13 +56,13 @@
 
 /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
 
+/** Validation of I2C register block pointer reference for assert statements. */
 #if (I2C_COUNT == 1)
-/** Validation of I2C register block pointer reference for assert statements. */
 #define I2C_REF_VALID(ref)    ((ref) == I2C0)
-
 #elif (I2C_COUNT == 2)
-/** Validation of I2C register block pointer reference for assert statements. */
 #define I2C_REF_VALID(ref)    ((ref == I2C0) || (ref == I2C1))
+#elif (I2C_COUNT == 3)
+#define I2C_REF_VALID(ref)    ((ref == I2C0) || (ref == I2C1)|| (ref == I2C2))
 #endif
 
 /** Error flags indicating I2C transfer has failed somehow. */
@@ -71,6 +72,15 @@
 /* RXDATA register. Thus, we ignore those types of fault. */
 #define I2C_IF_ERRORS    (I2C_IF_BUSERR | I2C_IF_ARBLOST)
 
+/* Max I2C transmission rate constant  */
+#if defined( _SILICON_LABS_32B_PLATFORM_1 )
+#define I2C_CR_MAX       4
+#elif defined( _SILICON_LABS_32B_PLATFORM_2 )
+#define I2C_CR_MAX       8
+#else
+#warning "Max I2C transmission rate constant is not defined"
+#endif
+
 /** @endcond */
 
 /*******************************************************************************
@@ -159,14 +169,17 @@
  ******************************************************************************/
 uint32_t I2C_BusFreqGet(I2C_TypeDef *i2c)
 {
-  uint32_t hfperclk;
+  uint32_t freqHfper;
   uint32_t n;
 
-  /* Max frequency is given by fSCL = fHFPERCLK/((Nlow + Nhigh)(DIV + 1) + 4) */
-  hfperclk = CMU_ClockFreqGet(cmuClock_HFPER);
+  /* Max frequency is given by freqScl = freqHfper/((Nlow + Nhigh)(DIV + 1) + I2C_CR_MAX)
+   * More details can be found in the reference manual,
+   * I2C Clock Generation chapter. */
+  freqHfper = CMU_ClockFreqGet(cmuClock_HFPER);
+  /* n = Nlow + Nhigh */
   n        = (uint32_t)(i2cNSum[(i2c->CTRL & _I2C_CTRL_CLHR_MASK) >> _I2C_CTRL_CLHR_SHIFT]);
 
-  return(hfperclk / ((n * (i2c->CLKDIV + 1)) + 4));
+  return (freqHfper / ((n * (i2c->CLKDIV + 1)) + I2C_CR_MAX));
 }
 
 
@@ -189,54 +202,108 @@
  * @param[in] i2c
  *   Pointer to I2C peripheral register block.
  *
- * @param[in] refFreq
+ * @param[in] freqRef
  *   I2C reference clock frequency in Hz that will be used. If set to 0,
- *   the currently configured reference clock is assumed. Setting it to a higher
- *   than actual configured value only has the consequence of reducing the real
- *   I2C frequency.
+ *   then HFPER clock is used. Setting it to a higher than actual configured
+ *   value only has the consequence of reducing the real I2C frequency.
  *
- * @param[in] freq
+ * @param[in] freqScl
  *   Bus frequency to set (actual bus speed may be lower due to integer
  *   prescaling). Safe (according to I2C specification) max frequencies for
  *   standard, fast and fast+ modes are available using I2C_FREQ_ defines.
  *   (Using I2C_FREQ_ defines requires corresponding setting of @p type.)
  *   Slowest slave device on bus must always be considered.
  *
- * @param[in] type
+ * @param[in] i2cMode
  *   Clock low to high ratio type to use. If not using i2cClockHLRStandard,
  *   make sure all devices on the bus support the specified mode. Using a
  *   non-standard ratio is useful to achieve higher bus clock in fast and
  *   fast+ modes.
  ******************************************************************************/
 void I2C_BusFreqSet(I2C_TypeDef *i2c,
-                    uint32_t refFreq,
-                    uint32_t freq,
-                    I2C_ClockHLR_TypeDef type)
+                    uint32_t freqRef,
+                    uint32_t freqScl,
+                    I2C_ClockHLR_TypeDef i2cMode)
 {
-  uint32_t n;
-  uint32_t div;
+  uint32_t n, minFreq;
+  int32_t div;
 
   /* Avoid divide by 0 */
-  EFM_ASSERT(freq);
-  if (!freq)
+  EFM_ASSERT(freqScl);
+  if (!freqScl)
   {
     return;
   }
 
   /* Set the CLHR (clock low to high ratio). */
   i2c->CTRL &= ~_I2C_CTRL_CLHR_MASK;
-  i2c->CTRL |= type <<_I2C_CTRL_CLHR_SHIFT;
+  BUS_RegMaskedWrite(&i2c->CTRL,
+                     _I2C_CTRL_CLHR_MASK,
+                     i2cMode <<_I2C_CTRL_CLHR_SHIFT);
 
-  /* Frequency is given by fSCL = fHFPERCLK/((Nlow + Nhigh)(DIV + 1) + 4), thus */
-  /* DIV = ((fHFPERCLK - 4fSCL)/((Nlow + Nhigh)fSCL)) - 1 */
+  if (!freqRef)
+  {
+    freqRef = CMU_ClockFreqGet(cmuClock_HFPER);
+  }
 
-  if (!refFreq)
+    /* Check minumum HF peripheral clock */
+  minFreq = UINT_MAX;
+  if (i2c->CTRL & I2C_CTRL_SLAVE)
   {
-    refFreq = CMU_ClockFreqGet(cmuClock_HFPER);
+    switch(i2cMode)
+    {
+      case i2cClockHLRStandard:
+#if defined( _SILICON_LABS_32B_PLATFORM_1 )
+        minFreq = 4200000; break;
+#elif defined( _SILICON_LABS_32B_PLATFORM_2 )
+        minFreq = 2000000; break;
+#endif
+      case i2cClockHLRAsymetric:
+#if defined( _SILICON_LABS_32B_PLATFORM_1 )
+        minFreq = 11000000; break;
+#elif defined( _SILICON_LABS_32B_PLATFORM_2 )
+        minFreq = 5000000; break;
+#endif
+      case i2cClockHLRFast:
+#if defined( _SILICON_LABS_32B_PLATFORM_1 )
+        minFreq = 24400000; break;
+#elif defined( _SILICON_LABS_32B_PLATFORM_2 )
+        minFreq = 14000000; break;
+#endif
+    }
   }
-  n = (uint32_t)(i2cNSum[type]);
+  else
+  {
+    /* For master mode, platform 1 and 2 share the same
+       min frequencies */
+    switch(i2cMode)
+    {
+      case i2cClockHLRStandard:
+        minFreq = 2000000; break;
+      case i2cClockHLRAsymetric:
+        minFreq = 9000000; break;
+      case i2cClockHLRFast:
+        minFreq = 20000000; break;
+    }
+  }
 
-  div = (refFreq - (4 * freq)) / (n * freq);
+  /* Frequency most be larger-than */
+  EFM_ASSERT(freqRef > minFreq);
+
+  /* SCL frequency is given by
+   * freqScl = freqRef/((Nlow + Nhigh) * (DIV + 1) + I2C_C_MAX)
+   *
+   * Thus
+   * DIV = ((freqRef - (I2C_C_MAX * freqScl))/((Nlow + Nhigh) * freqScl)) - 1
+   *
+   * More details can be found in the reference manual,
+   * I2C Clock Generation chapter.  */
+
+  /* n = Nlow + Nhigh */
+  n = (uint32_t)(i2cNSum[i2cMode]);
+  div = ((freqRef - (I2C_CR_MAX * freqScl)) / (n * freqScl)) - 1;
+  EFM_ASSERT(div >= 0);
+  EFM_ASSERT((uint32_t)div <= _I2C_CLKDIV_DIV_MASK);
 
   /* Clock divisor must be at least 1 in slave mode according to reference */
   /* manual (in which case there is normally no need to set bus frequency). */
@@ -244,9 +311,7 @@
   {
     div = 1;
   }
-
-  EFM_ASSERT(div <= _I2C_CLKDIV_DIV_MASK);
-  i2c->CLKDIV = div;
+  i2c->CLKDIV = (uint32_t)div;
 }
 
 
@@ -267,7 +332,7 @@
 {
   EFM_ASSERT(I2C_REF_VALID(i2c));
 
-  BITBAND_Peripheral(&(i2c->CTRL), _I2C_CTRL_EN_SHIFT, (unsigned int)enable);
+  BUS_RegBitWrite(&(i2c->CTRL), _I2C_CTRL_EN_SHIFT, enable);
 }
 
 
@@ -289,15 +354,11 @@
   i2c->IFC = _I2C_IFC_MASK;
 
   /* Set SLAVE select mode */
-  BITBAND_Peripheral(&(i2c->CTRL),
-                     _I2C_CTRL_SLAVE_SHIFT,
-                     init->master ? 0 : 1);
+  BUS_RegBitWrite(&(i2c->CTRL), _I2C_CTRL_SLAVE_SHIFT, init->master ? 0 : 1);
 
   I2C_BusFreqSet(i2c, init->refFreq, init->freq, init->clhr);
 
-  BITBAND_Peripheral(&(i2c->CTRL),
-                     _I2C_CTRL_EN_SHIFT,
-                     (unsigned int)(init->enable));
+  BUS_RegBitWrite(&(i2c->CTRL), _I2C_CTRL_EN_SHIFT, init->enable);
 }
 
 
@@ -382,7 +443,7 @@
 #endif
   else
   {
-    return(i2cTransferUsageFault);
+    return i2cTransferUsageFault;
   }
 
   seq = transfer->seq;
@@ -707,7 +768,7 @@
   /* Until transfer is done keep returning i2cTransferInProgress */
   else
   {
-    return(i2cTransferInProgress);
+    return i2cTransferInProgress;
   }
 
   return transfer->result;
@@ -760,7 +821,7 @@
 #endif
   else
   {
-    return(i2cTransferUsageFault);
+    return i2cTransferUsageFault;
   }
 
   /* Check if in busy state. Since this SW assumes single master, we can */
@@ -778,7 +839,7 @@
       ((seq->flags & I2C_FLAG_WRITE_READ) && !(seq->buf[1].len))
       )
   {
-    return(i2cTransferUsageFault);
+    return i2cTransferUsageFault;
   }
 
   /* Prepare for a transfer */
@@ -805,7 +866,7 @@
              I2C_IF_RXDATAV | I2C_IF_ERRORS;
 
   /* Start transfer */
-  return(I2C_Transfer(i2c));
+  return I2C_Transfer(i2c);
 }
 
 /** @} (end addtogroup I2C) */

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_idac.c	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_idac.c	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /***************************************************************************//**
  * @file em_idac.c
  * @brief Current Digital to Analog Converter (IDAC) peripheral API
- * @version 3.20.12
+ * @version 4.2.1
  *******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
  *******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,12 +30,11 @@
  *
  ******************************************************************************/
 
-
 #include "em_idac.h"
 #if defined(IDAC_COUNT) && (IDAC_COUNT > 0)
 #include "em_cmu.h"
 #include "em_assert.h"
-#include "em_bitband.h"
+#include "em_bus.h"
 
 /***************************************************************************//**
  * @addtogroup EM_Library
@@ -50,9 +49,7 @@
 
 /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
 /* Fix for errata IDAC_E101 - IDAC output current degradation */
-#if defined(_EFM32_ZERO_FAMILY)
-#define ERRATA_FIX_IDAC_E101_EN
-#elif defined(_EFM32_HAPPY_FAMILY)
+#if defined(_EFM32_ZERO_FAMILY) || defined(_EFM32_HAPPY_FAMILY)
 #define ERRATA_FIX_IDAC_E101_EN
 #endif
 /** @endcond */
@@ -122,7 +119,7 @@
 
   reg = &(idac->CTRL);
 
-  BITBAND_Peripheral(reg, _IDAC_CTRL_EN_SHIFT, (unsigned int) enable);
+  BUS_RegBitWrite(reg, _IDAC_CTRL_EN_SHIFT, enable);
 }
 
 
@@ -139,7 +136,7 @@
 
 #if defined(ERRATA_FIX_IDAC_E101_EN)
   /* Fix for errata IDAC_E101 - IDAC output current degradation:
-     Instead of disabling it we will put it in it’s lowest power state (50 nA)
+     Instead of disabling it we will put it in it's lowest power state (50 nA)
      to avoid degradation over time */
 
   /* Make sure IDAC is enabled with disabled output */
@@ -156,7 +153,9 @@
   idac->CURPROG    = _IDAC_CURPROG_RESETVALUE;
   idac->DUTYCONFIG = _IDAC_DUTYCONFIG_RESETVALUE;
 #endif
+#if defined ( _IDAC_CAL_MASK )
   idac->CAL        = _IDAC_CAL_RESETVALUE;
+#endif
 }
 
 
@@ -178,7 +177,7 @@
 
   reg = &(idac->CTRL);
 
-  BITBAND_Peripheral(reg, _IDAC_CTRL_MINOUTTRANS_SHIFT, (unsigned int) enable);
+  BUS_RegBitWrite(reg, _IDAC_CTRL_MINOUTTRANS_SHIFT, enable);
 }
 
 
@@ -201,29 +200,121 @@
 void IDAC_RangeSet(IDAC_TypeDef *idac, const IDAC_Range_TypeDef range)
 {
   uint32_t tmp;
+#if defined( _IDAC_CURPROG_TUNING_MASK )
+  uint32_t diCal0;
+  uint32_t diCal1;
+#endif
 
   EFM_ASSERT(IDAC_REF_VALID(idac));
-  EFM_ASSERT((range >> _IDAC_CURPROG_RANGESEL_SHIFT) <= (_IDAC_CURPROG_RANGESEL_MASK >> _IDAC_CURPROG_RANGESEL_SHIFT));
+  EFM_ASSERT(((uint32_t)range >> _IDAC_CURPROG_RANGESEL_SHIFT)
+             <= (_IDAC_CURPROG_RANGESEL_MASK >> _IDAC_CURPROG_RANGESEL_SHIFT));
+
+#if defined ( _IDAC_CAL_MASK )
 
   /* Load proper calibration data depending on selected range */
-  switch ((IDAC_Range_TypeDef) range)
+  switch ((IDAC_Range_TypeDef)range)
   {
-  case idacCurrentRange0:
-    idac->CAL = (DEVINFO->IDAC0CAL0 & _DEVINFO_IDAC0CAL0_RANGE0_MASK) >> _DEVINFO_IDAC0CAL0_RANGE0_SHIFT;
-    break;
-  case idacCurrentRange1:
-    idac->CAL = (DEVINFO->IDAC0CAL0 & _DEVINFO_IDAC0CAL0_RANGE1_MASK) >> _DEVINFO_IDAC0CAL0_RANGE1_SHIFT;
-    break;
-  case idacCurrentRange2:
-    idac->CAL = (DEVINFO->IDAC0CAL0 & _DEVINFO_IDAC0CAL0_RANGE2_MASK) >> _DEVINFO_IDAC0CAL0_RANGE2_SHIFT;
-    break;
-  case idacCurrentRange3:
-    idac->CAL = (DEVINFO->IDAC0CAL0 & _DEVINFO_IDAC0CAL0_RANGE3_MASK) >> _DEVINFO_IDAC0CAL0_RANGE3_SHIFT;
-    break;
+    case idacCurrentRange0:
+      idac->CAL = (DEVINFO->IDAC0CAL0 & _DEVINFO_IDAC0CAL0_RANGE0_MASK)
+                  >> _DEVINFO_IDAC0CAL0_RANGE0_SHIFT;
+      break;
+    case idacCurrentRange1:
+      idac->CAL = (DEVINFO->IDAC0CAL0 & _DEVINFO_IDAC0CAL0_RANGE1_MASK)
+                  >> _DEVINFO_IDAC0CAL0_RANGE1_SHIFT;
+      break;
+    case idacCurrentRange2:
+      idac->CAL = (DEVINFO->IDAC0CAL0 & _DEVINFO_IDAC0CAL0_RANGE2_MASK)
+                  >> _DEVINFO_IDAC0CAL0_RANGE2_SHIFT;
+      break;
+    case idacCurrentRange3:
+      idac->CAL = (DEVINFO->IDAC0CAL0 & _DEVINFO_IDAC0CAL0_RANGE3_MASK)
+                  >> _DEVINFO_IDAC0CAL0_RANGE3_SHIFT;
+      break;
   }
 
   tmp  = idac->CURPROG & ~_IDAC_CURPROG_RANGESEL_MASK;
-  tmp |= (uint32_t) range;
+  tmp |= (uint32_t)range;
+
+#elif defined( _IDAC_CURPROG_TUNING_MASK )
+
+  /* Load calibration data depending on selected range and sink/source mode */
+  /* TUNING (calibration) field in CURPROG register. */
+  if (idac == IDAC0)
+  {
+    diCal0 = DEVINFO->IDAC0CAL0;
+    diCal1 = DEVINFO->IDAC0CAL1;
+  }
+  else
+  {
+    EFM_ASSERT(false);
+  }
+
+  tmp = idac->CURPROG & ~(_IDAC_CURPROG_TUNING_MASK
+                          | _IDAC_CURPROG_RANGESEL_MASK);
+  if (idac->CTRL & IDAC_CTRL_CURSINK)
+  {
+    switch (range)
+    {
+      case idacCurrentRange0:
+        tmp |= ((diCal1 & _DEVINFO_IDAC0CAL1_SINKRANGE0TUNING_MASK)
+                >> _DEVINFO_IDAC0CAL1_SINKRANGE0TUNING_SHIFT)
+               << _IDAC_CURPROG_TUNING_SHIFT;
+        break;
+
+      case idacCurrentRange1:
+        tmp |= ((diCal1 & _DEVINFO_IDAC0CAL1_SINKRANGE1TUNING_MASK)
+                >> _DEVINFO_IDAC0CAL1_SINKRANGE1TUNING_SHIFT)
+               << _IDAC_CURPROG_TUNING_SHIFT;
+        break;
+
+      case idacCurrentRange2:
+        tmp |= ((diCal1 & _DEVINFO_IDAC0CAL1_SINKRANGE2TUNING_MASK)
+                >> _DEVINFO_IDAC0CAL1_SINKRANGE2TUNING_SHIFT)
+               << _IDAC_CURPROG_TUNING_SHIFT;
+        break;
+
+      case idacCurrentRange3:
+        tmp |= ((diCal1 & _DEVINFO_IDAC0CAL1_SINKRANGE3TUNING_MASK)
+                >> _DEVINFO_IDAC0CAL1_SINKRANGE3TUNING_SHIFT)
+               << _IDAC_CURPROG_TUNING_SHIFT;
+        break;
+    }
+  }
+  else
+  {
+    switch (range)
+    {
+      case idacCurrentRange0:
+        tmp |= ((diCal0 & _DEVINFO_IDAC0CAL0_SOURCERANGE0TUNING_MASK)
+                >> _DEVINFO_IDAC0CAL0_SOURCERANGE0TUNING_SHIFT)
+               << _IDAC_CURPROG_TUNING_SHIFT;
+        break;
+
+      case idacCurrentRange1:
+        tmp |= ((diCal0 & _DEVINFO_IDAC0CAL0_SOURCERANGE1TUNING_MASK)
+                >> _DEVINFO_IDAC0CAL0_SOURCERANGE1TUNING_SHIFT)
+               << _IDAC_CURPROG_TUNING_SHIFT;
+        break;
+
+      case idacCurrentRange2:
+        tmp |= ((diCal0 & _DEVINFO_IDAC0CAL0_SOURCERANGE2TUNING_MASK)
+                >> _DEVINFO_IDAC0CAL0_SOURCERANGE2TUNING_SHIFT)
+               << _IDAC_CURPROG_TUNING_SHIFT;
+        break;
+
+      case idacCurrentRange3:
+        tmp |= ((diCal0 & _DEVINFO_IDAC0CAL0_SOURCERANGE3TUNING_MASK)
+                >> _DEVINFO_IDAC0CAL0_SOURCERANGE3TUNING_SHIFT)
+               << _IDAC_CURPROG_TUNING_SHIFT;
+        break;
+    }
+  }
+
+  tmp |= (uint32_t)range;
+
+#else
+#warning "IDAC calibration register definition unknown."
+#endif
 
   idac->CURPROG = tmp;
 }
@@ -271,7 +362,7 @@
 
   reg = &(idac->CTRL);
 
-  BITBAND_Peripheral(reg, _IDAC_CTRL_OUTEN_SHIFT, (unsigned int) enable);
+  BUS_RegBitWrite(reg, _IDAC_CTRL_OUTEN_SHIFT, enable);
 }
 
 

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_int.c	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_int.c	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file em_int.c
  * @brief Interrupt enable/disable unit API
- * @version 3.20.12
+ * @version 4.2.1
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
  *******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,7 +30,6 @@
  *
  ******************************************************************************/
 
-
 #include <stdint.h>
 #include "em_int.h"
 
@@ -41,15 +40,17 @@
 
 /***************************************************************************//**
  * @addtogroup INT
- * @brief Safe nesting interrupt disable/enable API
+ * @brief Safe nesting of interrupt disable/enable API
  * @{
  * @details
  *  This module contains functions to safely disable and enable interrupts
- *  at cpu level. INT_Disable() disables interrupts and increments a lock
- *  level counter. INT_Enable() decrements the lock level counter and enable
- *  interrupts if the counter was decremented to zero.
+ *  at CPU level. INT_Disable() disables interrupts globally and increments a lock
+ *  level counter (counting semaphore). INT_Enable() decrements the lock level 
+ *  counter and enable interrupts if the counter reaches zero.
  *
- *  These functions would normally be used to secure critical regions.
+ *  These functions would normally be used to secure critical regions, and 
+ *  to make sure that a critical section that calls into another critical 
+ *  section does not unintentionally terminate the callee critical section.
  *
  *  These functions should also be used inside interrupt handlers:
  *  @verbatim
@@ -68,6 +69,5 @@
  * main with interrupts enabled  */
 uint32_t INT_LockCnt = 0;
 
-
 /** @} (end addtogroup INT) */
 /** @} (end addtogroup EM_Library) */

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_lcd.c	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_lcd.c	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /***************************************************************************//**
  * @file em_lcd.c
  * @brief Liquid Crystal Display (LCD) Peripheral API
- * @version 3.20.12
+ * @version 4.2.1
  *******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
  *******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,11 +30,10 @@
  *
  ******************************************************************************/
 
-
 #include "em_lcd.h"
 #if defined(LCD_COUNT) && (LCD_COUNT > 0)
 #include "em_assert.h"
-#include "em_bitband.h"
+#include "em_bus.h"
 
 /***************************************************************************//**
  * @addtogroup EM_Library
@@ -70,15 +69,15 @@
   LCD_Enable(false);
 
   /* Make sure we don't touch other bit fields (i.e. voltage boost) */
-  dispCtrl &= ~(
-#if defined(_EFM32_TINY_FAMILY) || defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
-    _LCD_DISPCTRL_MUXE_MASK |
+  dispCtrl &= ~(0
+#if defined(LCD_DISPCTRL_MUXE)
+                | _LCD_DISPCTRL_MUXE_MASK
 #endif
-    _LCD_DISPCTRL_MUX_MASK |
-    _LCD_DISPCTRL_BIAS_MASK |
-    _LCD_DISPCTRL_WAVE_MASK |
-    _LCD_DISPCTRL_VLCDSEL_MASK |
-    _LCD_DISPCTRL_CONCONF_MASK);
+                | _LCD_DISPCTRL_MUX_MASK
+                | _LCD_DISPCTRL_BIAS_MASK
+                | _LCD_DISPCTRL_WAVE_MASK
+                | _LCD_DISPCTRL_VLCDSEL_MASK
+                | _LCD_DISPCTRL_CONCONF_MASK);
 
   /* Configure controller according to initialization structure */
   dispCtrl |= lcdInit->mux; /* also configures MUXE */
@@ -110,17 +109,17 @@
   uint32_t dispctrl = LCD->DISPCTRL;
 
   /* Select VEXT or VDD */
-  dispctrl &= ~(_LCD_DISPCTRL_VLCDSEL_MASK);
+  dispctrl &= ~_LCD_DISPCTRL_VLCDSEL_MASK;
   switch (vlcd)
   {
-  case lcdVLCDSelVExtBoost:
-    dispctrl |= LCD_DISPCTRL_VLCDSEL_VEXTBOOST;
-    break;
-  case lcdVLCDSelVDD:
-    dispctrl |= LCD_DISPCTRL_VLCDSEL_VDD;
-    break;
-  default:
-    break;
+    case lcdVLCDSelVExtBoost:
+      dispctrl |= LCD_DISPCTRL_VLCDSEL_VEXTBOOST;
+      break;
+    case lcdVLCDSelVDD:
+      dispctrl |= LCD_DISPCTRL_VLCDSEL_VDD;
+      break;
+    default:
+      break;
   }
 
   LCD->DISPCTRL = dispctrl;
@@ -157,8 +156,8 @@
   EFM_ASSERT(fcInit->top < 64);
 
   /* Reconfigure frame count configuration */
-  bactrl &= ~(_LCD_BACTRL_FCTOP_MASK |
-              _LCD_BACTRL_FCPRESC_MASK);
+  bactrl &= ~(_LCD_BACTRL_FCTOP_MASK
+              | _LCD_BACTRL_FCPRESC_MASK);
   bactrl |= (fcInit->top << _LCD_BACTRL_FCTOP_SHIFT);
   bactrl |= fcInit->prescale;
 
@@ -187,15 +186,15 @@
   LCD->AREGB = animInit->BReg;
 
   /* Configure Animation Shift and Logic */
-  bactrl &= ~(_LCD_BACTRL_AREGASC_MASK |
-              _LCD_BACTRL_AREGBSC_MASK |
-              _LCD_BACTRL_ALOGSEL_MASK);
+  bactrl &= ~(_LCD_BACTRL_AREGASC_MASK
+              | _LCD_BACTRL_AREGBSC_MASK
+              | _LCD_BACTRL_ALOGSEL_MASK);
 
   bactrl |= (animInit->AShift << _LCD_BACTRL_AREGASC_SHIFT);
   bactrl |= (animInit->BShift << _LCD_BACTRL_AREGBSC_SHIFT);
   bactrl |= animInit->animLogic;
 
-#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
+#if defined(LCD_BACTRL_ALOC)
   bactrl &= ~(_LCD_BACTRL_ALOC_MASK);
 
   if(animInit->startSeg == 0)
@@ -260,7 +259,7 @@
  ******************************************************************************/
 void LCD_SegmentSet(int com, int bit, bool enable)
 {
-#if defined(_EFM32_TINY_FAMILY) || defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
+#if defined(_LCD_SEGD7L_MASK)
   /* Tiny and Giant Family supports up to 8 COM lines */
   EFM_ASSERT(com < 8);
 #else
@@ -268,7 +267,7 @@
   EFM_ASSERT(com < 4);
 #endif
 
-#if defined(_EFM32_GECKO_FAMILY) || defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
+#if defined(_LCD_SEGD0H_MASK)
   EFM_ASSERT(bit < 40);
 #else
   /* Tiny Gecko Family supports only "low" segment registers */
@@ -278,122 +277,122 @@
   /* Use bitband access for atomic bit set/clear of segment */
   switch (com)
   {
-  case 0:
-    if (bit < 32)
-    {
-      BITBAND_Peripheral(&(LCD->SEGD0L), bit, (unsigned int)enable);
-    }
-#if defined(_EFM32_GECKO_FAMILY) || defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
-    else
-    {
-      bit -= 32;
-      BITBAND_Peripheral(&(LCD->SEGD0H), bit, (unsigned int)enable);
-    }
+    case 0:
+      if (bit < 32)
+      {
+        BUS_RegBitWrite(&(LCD->SEGD0L), bit, enable);
+      }
+#if defined(_LCD_SEGD0H_MASK)
+      else
+      {
+        bit -= 32;
+        BUS_RegBitWrite(&(LCD->SEGD0H), bit, enable);
+      }
 #endif
-    break;
-  case 1:
-    if (bit < 32)
-    {
-      BITBAND_Peripheral(&(LCD->SEGD1L), bit, (unsigned int)enable);
-    }
-#if defined(_EFM32_GECKO_FAMILY) || defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
-    else
-    {
-      bit -= 32;
-      BITBAND_Peripheral(&(LCD->SEGD1H), bit, (unsigned int)enable);
-    }
+      break;
+    case 1:
+      if (bit < 32)
+      {
+        BUS_RegBitWrite(&(LCD->SEGD1L), bit, enable);
+      }
+#if defined(_LCD_SEGD1H_MASK)
+      else
+      {
+        bit -= 32;
+        BUS_RegBitWrite(&(LCD->SEGD1H), bit, enable);
+      }
 #endif
-    break;
-  case 2:
-    if (bit < 32)
-    {
-      BITBAND_Peripheral(&(LCD->SEGD2L), bit, (unsigned int)enable);
-    }
-#if defined(_EFM32_GECKO_FAMILY) || defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
-    else
-    {
-      bit -= 32;
-      BITBAND_Peripheral(&(LCD->SEGD2H), bit, (unsigned int)enable);
-    }
+      break;
+    case 2:
+      if (bit < 32)
+      {
+        BUS_RegBitWrite(&(LCD->SEGD2L), bit, enable);
+      }
+#if defined(_LCD_SEGD2H_MASK)
+      else
+      {
+        bit -= 32;
+        BUS_RegBitWrite(&(LCD->SEGD2H), bit, enable);
+      }
 #endif
-    break;
-  case 3:
-    if (bit < 32)
-    {
-      BITBAND_Peripheral(&(LCD->SEGD3L), bit, (unsigned int)enable);
-    }
-#if defined(_EFM32_GECKO_FAMILY) || defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
-    else
-    {
-      bit -= 32;
-      BITBAND_Peripheral(&(LCD->SEGD3H), bit, (unsigned int)enable);
-    }
+      break;
+    case 3:
+      if (bit < 32)
+      {
+        BUS_RegBitWrite(&(LCD->SEGD3L), bit, enable);
+      }
+#if defined(_LCD_SEGD3H_MASK)
+      else
+      {
+        bit -= 32;
+        BUS_RegBitWrite(&(LCD->SEGD3H), bit, enable);
+      }
 #endif
-    break;
-  case 4:
-#if defined(_EFM32_TINY_FAMILY) || defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
-    if (bit < 32)
-    {
-      BITBAND_Peripheral(&(LCD->SEGD4L), bit, (unsigned int)enable);
-    }
-#endif
-#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
-    else
-    {
-      bit -= 32;
-      BITBAND_Peripheral(&(LCD->SEGD4H), bit, (unsigned int)enable);
-    }
+      break;
+#if defined(_LCD_SEGD4L_MASK)
+    case 4:
+      if (bit < 32)
+      {
+        BUS_RegBitWrite(&(LCD->SEGD4L), bit, enable);
+      }
+#if defined(_LCD_SEGD4H_MASK)
+      else
+      {
+        bit -= 32;
+        BUS_RegBitWrite(&(LCD->SEGD4H), bit, enable);
+      }
 #endif
-    break;
-  case 5:
-#if defined(_EFM32_TINY_FAMILY) || defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
-    if (bit < 32)
-    {
-      BITBAND_Peripheral(&(LCD->SEGD5L), bit, (unsigned int)enable);
-    }
+      break;
 #endif
-#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
-    else
-    {
-      bit -= 32;
-      BITBAND_Peripheral(&(LCD->SEGD5H), bit, (unsigned int)enable);
-    }
+#if defined(_LCD_SEGD5L_MASK)
+    case 5:
+      if (bit < 32)
+      {
+        BUS_RegBitWrite(&(LCD->SEGD5L), bit, enable);
+      }
+#if defined(_LCD_SEGD5H_MASK)
+      else
+      {
+        bit -= 32;
+        BUS_RegBitWrite(&(LCD->SEGD5H), bit, enable);
+      }
+#endif
+      break;
 #endif
-    break;
-  case 6:
-#if defined(_EFM32_TINY_FAMILY) || defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
-    if (bit < 32)
-    {
-      BITBAND_Peripheral(&(LCD->SEGD6L), bit, (unsigned int)enable);
-    }
+    case 6:
+#if defined(_LCD_SEGD6L_MASK)
+      if (bit < 32)
+      {
+        BUS_RegBitWrite(&(LCD->SEGD6L), bit, enable);
+      }
+#if defined(_LCD_SEGD6H_MASK)
+      else
+      {
+        bit -= 32;
+        BUS_RegBitWrite(&(LCD->SEGD6H), bit, enable);
+      }
 #endif
-#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
-    else
-    {
-      bit -= 32;
-      BITBAND_Peripheral(&(LCD->SEGD6H), bit, (unsigned int)enable);
-    }
+      break;
 #endif
-    break;
-  case 7:
-#if defined(_EFM32_TINY_FAMILY) || defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
-    if (bit < 32)
-    {
-      BITBAND_Peripheral(&(LCD->SEGD7L), bit, (unsigned int)enable);
-    }
+#if defined(_LCD_SEGD7L_MASK)
+    case 7:
+      if (bit < 32)
+      {
+        BUS_RegBitWrite(&(LCD->SEGD7L), bit, enable);
+      }
+#if defined(_LCD_SEGD7H_MASK)
+      else
+      {
+        bit -= 32;
+        BUS_RegBitWrite(&(LCD->SEGD7H), bit, enable);
+      }
 #endif
-#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
-    else
-    {
-      bit -= 32;
-      BITBAND_Peripheral(&(LCD->SEGD7H), bit, (unsigned int)enable);
-    }
+      break;
 #endif
-    break;
 
-  default:
-    EFM_ASSERT(0);
-    break;
+    default:
+      EFM_ASSERT(0);
+      break;
   }
 }
 
@@ -417,7 +416,7 @@
   uint32_t segData;
 
   /* Maximum number of com lines */
-#if defined(_EFM32_TINY_FAMILY) || defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
+#if defined(_LCD_SEGD7L_MASK)
   EFM_ASSERT(com < 8);
 #else
   /* Gecko Family supports up to 4 COM lines */
@@ -426,70 +425,70 @@
 
   switch (com)
   {
-  case 0:
-    segData     = LCD->SEGD0L;
-    segData    &= ~(mask);
-    segData    |= (mask & bits);
-    LCD->SEGD0L = segData;
-    break;
-  case 1:
-    segData     = LCD->SEGD1L;
-    segData    &= ~(mask);
-    segData    |= (mask & bits);
-    LCD->SEGD1L = segData;
-    break;
-  case 2:
-    segData     = LCD->SEGD2L;
-    segData    &= ~(mask);
-    segData    |= (mask & bits);
-    LCD->SEGD2L = segData;
-    break;
-  case 3:
-    segData     = LCD->SEGD3L;
-    segData    &= ~(mask);
-    segData    |= (mask & bits);
-    LCD->SEGD3L = segData;
-    break;
-#if defined(_EFM32_TINY_FAMILY) || defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
-  case 4:
-    segData     = LCD->SEGD4L;
-    segData    &= ~(mask);
-    segData    |= (mask & bits);
-    LCD->SEGD4L = segData;
-    break;
+    case 0:
+      segData     = LCD->SEGD0L;
+      segData    &= ~(mask);
+      segData    |= (mask & bits);
+      LCD->SEGD0L = segData;
+      break;
+    case 1:
+      segData     = LCD->SEGD1L;
+      segData    &= ~(mask);
+      segData    |= (mask & bits);
+      LCD->SEGD1L = segData;
+      break;
+    case 2:
+      segData     = LCD->SEGD2L;
+      segData    &= ~(mask);
+      segData    |= (mask & bits);
+      LCD->SEGD2L = segData;
+      break;
+    case 3:
+      segData     = LCD->SEGD3L;
+      segData    &= ~(mask);
+      segData    |= (mask & bits);
+      LCD->SEGD3L = segData;
+      break;
+#if defined(_LCD_SEGD4L_MASK)
+    case 4:
+      segData     = LCD->SEGD4L;
+      segData    &= ~(mask);
+      segData    |= (mask & bits);
+      LCD->SEGD4L = segData;
+      break;
 #endif
-#if defined(_EFM32_TINY_FAMILY) || defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY) 
-  case 5:
-    segData     = LCD->SEGD5L;
-    segData    &= ~(mask);
-    segData    |= (mask & bits);
-    LCD->SEGD5L = segData;
-    break;
+#if defined(_LCD_SEGD5L_MASK)
+    case 5:
+      segData     = LCD->SEGD5L;
+      segData    &= ~(mask);
+      segData    |= (mask & bits);
+      LCD->SEGD5L = segData;
+      break;
 #endif
-#if defined(_EFM32_TINY_FAMILY) || defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
-  case 6:
-    segData     = LCD->SEGD6L;
-    segData    &= ~(mask);
-    segData    |= (mask & bits);
-    LCD->SEGD6L = segData;
-    break;
+#if defined(_LCD_SEGD6L_MASK)
+    case 6:
+      segData     = LCD->SEGD6L;
+      segData    &= ~(mask);
+      segData    |= (mask & bits);
+      LCD->SEGD6L = segData;
+      break;
 #endif
-#if defined(_EFM32_TINY_FAMILY) || defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
-  case 7:
-    segData     = LCD->SEGD7L;
-    segData    &= ~(mask);
-    segData    |= (mask & bits);
-    LCD->SEGD7L = segData;
-    break;
+#if defined(_LCD_SEGD7L_MASK)
+    case 7:
+      segData     = LCD->SEGD7L;
+      segData    &= ~(mask);
+      segData    |= (mask & bits);
+      LCD->SEGD7L = segData;
+      break;
 #endif
-  default:
-    EFM_ASSERT(0);
-    break;
+    default:
+      EFM_ASSERT(0);
+      break;
   }
 }
 
 
-#if defined(_EFM32_GECKO_FAMILY) || defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
+#if defined(_LCD_SEGD0H_MASK)
 /***************************************************************************//**
  * @brief
  *   Updated the high (32-39) segments on a given COM-line in one operation
@@ -507,74 +506,73 @@
 {
   uint32_t segData;
 
-#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
+#if defined(_LCD_SEGD7H_MASK)
   EFM_ASSERT(com < 8);
-#endif
-#if defined(_EFM32_GECKO_FAMILY)
+#else
   EFM_ASSERT(com < 4);
 #endif
 
   /* Maximum number of com lines */
   switch (com)
   {
-  case 0:
-    segData     = LCD->SEGD0H;
-    segData    &= ~(mask);
-    segData    |= (mask & bits);
-    LCD->SEGD0H = segData;
-    break;
-  case 1:
-    segData     = LCD->SEGD1H;
-    segData    &= ~(mask);
-    segData    |= (mask & bits);
-    LCD->SEGD1H = segData;
-    break;
-  case 2:
-    segData     = LCD->SEGD2H;
-    segData    &= ~(mask);
-    segData    |= (mask & bits);
-    LCD->SEGD2H = segData;
-    break;
-  case 3:
-    segData     = LCD->SEGD3H;
-    segData    &= ~(mask);
-    segData    |= (mask & bits);
-    LCD->SEGD3H = segData;
-    break;
-#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
-  case 4:
-    segData     = LCD->SEGD4H;
-    segData    &= ~(mask);
-    segData    |= (mask & bits);
-    LCD->SEGD4H = segData;
-    break;
+    case 0:
+      segData     = LCD->SEGD0H;
+      segData    &= ~(mask);
+      segData    |= (mask & bits);
+      LCD->SEGD0H = segData;
+      break;
+    case 1:
+      segData     = LCD->SEGD1H;
+      segData    &= ~(mask);
+      segData    |= (mask & bits);
+      LCD->SEGD1H = segData;
+      break;
+    case 2:
+      segData     = LCD->SEGD2H;
+      segData    &= ~(mask);
+      segData    |= (mask & bits);
+      LCD->SEGD2H = segData;
+      break;
+    case 3:
+      segData     = LCD->SEGD3H;
+      segData    &= ~(mask);
+      segData    |= (mask & bits);
+      LCD->SEGD3H = segData;
+      break;
+#if defined(_LCD_SEGD4H_MASK)
+    case 4:
+      segData     = LCD->SEGD4H;
+      segData    &= ~(mask);
+      segData    |= (mask & bits);
+      LCD->SEGD4H = segData;
+      break;
 #endif
-#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
-  case 5:
-    segData     = LCD->SEGD5H;
-    segData    &= ~(mask);
-    segData    |= (mask & bits);
-    LCD->SEGD5H = segData;
-    break;
+#if defined(_LCD_SEGD5H_MASK)
+    case 5:
+      segData     = LCD->SEGD5H;
+      segData    &= ~(mask);
+      segData    |= (mask & bits);
+      LCD->SEGD5H = segData;
+      break;
 #endif
-#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
-  case 6:
-    segData     = LCD->SEGD6H;
-    segData    &= ~(mask);
-    segData    |= (mask & bits);
-    LCD->SEGD6H = segData;
-    break;
+#if defined(_LCD_SEGD6H_MASK)
+    case 6:
+      segData     = LCD->SEGD6H;
+      segData    &= ~(mask);
+      segData    |= (mask & bits);
+      LCD->SEGD6H = segData;
+      break;
 #endif
-#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
-  case 7:
-    segData     = LCD->SEGD7H;
-    segData    &= ~(mask);
-    segData    |= (mask & bits);
-    LCD->SEGD7H = segData;
-    break;
+#if defined(_LCD_SEGD7H_MASK)
+    case 7:
+      segData     = LCD->SEGD7H;
+      segData    &= ~(mask);
+      segData    |= (mask & bits);
+      LCD->SEGD7H = segData;
+      break;
 #endif
-  default:
-    break;
+    default:
+      break;
   }
 }
 #endif
@@ -611,7 +609,7 @@
 }
 
 
-#if defined(_EFM32_TINY_FAMILY) || defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
+#if defined(LCD_CTRL_DSC)
 /***************************************************************************//**
  * @brief
  *   Configure bias level for a specific segment line for Direct Segment Control
@@ -637,100 +635,99 @@
   int               bitShift;
   volatile uint32_t *segmentRegister;
 
-#if defined(_EFM32_TINY_FAMILY)
+#if !defined(_LCD_SEGD0H_MASK)
   EFM_ASSERT(segmentLine < 20);
-#endif
-#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
-  EFM_ASSERT(segmentLine < 40);
-#endif
-#if defined(_EFM32_TINY_FAMILY)
+
   /* Bias config for 8 segment lines per SEGDnL register */
   biasRegister = segmentLine / 8;
   bitShift     = (segmentLine % 8) * 4;
 
   switch (biasRegister)
   {
-  case 0:
-    segmentRegister = &LCD->SEGD0L;
-    break;
-  case 1:
-    segmentRegister = &LCD->SEGD1L;
-    break;
-  case 2:
-    segmentRegister = &LCD->SEGD2L;
-    break;
-  case 3:
-    segmentRegister = &LCD->SEGD3L;
-    break;
-  default:
-    segmentRegister = (uint32_t *)0x00000000;
-    EFM_ASSERT(0);
-    break;
+    case 0:
+      segmentRegister = &LCD->SEGD0L;
+      break;
+    case 1:
+      segmentRegister = &LCD->SEGD1L;
+      break;
+    case 2:
+      segmentRegister = &LCD->SEGD2L;
+      break;
+    case 3:
+      segmentRegister = &LCD->SEGD3L;
+      break;
+    default:
+      segmentRegister = (uint32_t *)0x00000000;
+      EFM_ASSERT(0);
+      break;
   }
-#endif
-#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY) 
+#else
+  EFM_ASSERT(segmentLine < 40);
+
   /* Bias config for 10 segment lines per SEGDn L+H registers */
   biasRegister = segmentLine / 10;
   bitShift     = (segmentLine % 10) * 4;
 
   switch (biasRegister)
   {
-  case 0:
-    if (bitShift < 32)
-    {
-      segmentRegister = &LCD->SEGD0L;
-    }
-    else
-    {
-      segmentRegister = &LCD->SEGD0H;
-      bitShift       -= 32;
-    }
-    break;
-  case 1:
-    if (bitShift < 32)
-    {
-      segmentRegister = &LCD->SEGD1L;
-    }
-    else
-    {
-      segmentRegister = &LCD->SEGD1H;
-      bitShift       -= 32;
-    }
-    break;
-  case 2:
-    if (bitShift < 32)
-    {
-      segmentRegister = &LCD->SEGD2L;
-    }
-    else
-    {
-      segmentRegister = &LCD->SEGD1H;
-      bitShift       -= 32;
-    }
-    break;
-  case 3:
-    if (bitShift < 32)
-    {
-      segmentRegister = &LCD->SEGD3L;
-    }
-    else
-    {
-      segmentRegister = &LCD->SEGD3H;
-      bitShift       -= 32;
-    }
-    break;
-  default:
-    segmentRegister = (uint32_t *)0x00000000;
-    EFM_ASSERT(0);
-    break;
+    case 0:
+      if (bitShift < 32)
+      {
+        segmentRegister = &LCD->SEGD0L;
+      }
+      else
+      {
+        segmentRegister = &LCD->SEGD0H;
+        bitShift       -= 32;
+      }
+      break;
+    case 1:
+      if (bitShift < 32)
+      {
+        segmentRegister = &LCD->SEGD1L;
+      }
+      else
+      {
+        segmentRegister = &LCD->SEGD1H;
+        bitShift       -= 32;
+      }
+      break;
+    case 2:
+      if (bitShift < 32)
+      {
+        segmentRegister = &LCD->SEGD2L;
+      }
+      else
+      {
+        segmentRegister = &LCD->SEGD1H;
+        bitShift       -= 32;
+      }
+      break;
+    case 3:
+      if (bitShift < 32)
+      {
+        segmentRegister = &LCD->SEGD3L;
+      }
+      else
+      {
+        segmentRegister = &LCD->SEGD3H;
+        bitShift       -= 32;
+      }
+      break;
+    default:
+      segmentRegister = (uint32_t *)0x00000000;
+      EFM_ASSERT(0);
+      break;
   }
 #endif
 
   /* Configure new bias setting */
   *segmentRegister = (*segmentRegister & ~(0xF << bitShift)) | (biasLevel << bitShift);
 }
+#endif
 
 
+#if defined(LCD_CTRL_DSC)
 /***************************************************************************//**
  * @brief
  *   Configure bias level for a specific segment line

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_ldma.c	Fri Jan 15 07:45:16 2016 +0000
@@ -0,0 +1,499 @@
+/***************************************************************************//**
+ * @file em_ldma.c
+ * @brief Direct memory access (LDMA) module peripheral API
+ * @version 4.2.1
+ *******************************************************************************
+ * @section License
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
+ *******************************************************************************
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software.@n
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.@n
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
+ * obligation to support this Software. Silicon Labs is providing the
+ * Software "AS IS", with no express or implied warranties of any kind,
+ * including, but not limited to, any implied warranties of merchantability
+ * or fitness for any particular purpose or warranties against infringement
+ * of any proprietary rights of a third party.
+ *
+ * Silicon Labs will not be liable for any consequential, incidental, or
+ * special damages, or any other relief, or for any claim by any third party,
+ * arising from your use of this Software.
+ *
+ ******************************************************************************/
+
+#include "em_ldma.h"
+
+#if defined( LDMA_PRESENT ) && ( LDMA_COUNT == 1 )
+
+#include <stddef.h>
+#include "em_assert.h"
+#include "em_bus.h"
+#include "em_cmu.h"
+#include "em_int.h"
+
+/***************************************************************************//**
+ * @addtogroup EM_Library
+ * @{
+ ******************************************************************************/
+
+/***************************************************************************//**
+  @addtogroup LDMA
+  @brief Direct Memory Access (LDMA) Peripheral API
+  @details
+  The LDMA API functions provide full support for the LDMA peripheral.
+
+  The LDMA supports these DMA transfer types:
+
+  @li Memory to memory.
+  @li Memory to peripheral.
+  @li Peripheral to memory.
+  @li Peripheral to peripheral.
+  @li Constant value to memory.
+
+  The LDMA supports linked lists of DMA descriptors allowing:
+
+  @li Circular and ping-pong buffer transfers.
+  @li Scatter-gather transfers.
+  @li Looped transfers.
+
+  The LDMA has some advanced features:
+
+  @li Intra-channel synchronization (SYNC), allowing hardware events to
+      pause and restart a DMA sequence.
+  @li Immediate-write (WRI), allowing the DMA to write a constant anywhere
+      in the memory map.
+  @li Complex flow control allowing if-else constructs.
+
+  A basic understanding of the LDMA controller is assumed. Please refer to
+  the reference manual for further details. The LDMA examples described
+  in the reference manual are particularly helpful in understanding LDMA
+  operations.
+
+  In order to use the DMA controller, the initialization function @ref
+  LDMA_Init() must have been executed once (normally during system init).
+
+  DMA transfers are initiated by a call to @ref LDMA_StartTransfer(), the
+  transfer properties are controlled by the contents of @ref LDMA_TransferCfg_t
+  and @ref LDMA_Descriptor_t structure parameters.
+  The @htmlonly LDMA_Descriptor_t @endhtmlonly structure parameter may be a
+  pointer to an array of descriptors, the descriptors in the array should
+  be linked together as needed.
+
+  Transfer and descriptor initialization macros are provided for the most common
+  transfer types. Due to the flexibility of the LDMA peripheral only a small
+  subset of all possible initializer macros are provided, the user should create
+  new one's when needed.
+
+  @note The LDMA module does not implement the LDMA interrupt handler. A
+  template for a handler is include in the code.
+
+  <b> Examples of LDMA usage: </b>
+
+  A simple memory to memory transfer:
+  @verbatim
+  // A single transfer of 4 half words.
+
+  const LDMA_TransferCfg_t memTransfer = LDMA_TRANSFER_CFG_MEMORY();
+  const LDMA_Descriptor_t xfer         = LDMA_DESCRIPTOR_SINGLE_M2M_HALF( src, dest, 4 );
+  LDMA_Init_t init                     = LDMA_INIT_DEFAULT;
+
+  LDMA_Init( &init );
+
+  LDMA_StartTransfer( 0, (void*)&memTransfer, (void*)&xfer );
+  @endverbatim
+
+  @n A list of two memory to memory transfers:
+  @verbatim
+  // A transfer of 4 half words which links to another transfer of 4 half words.
+
+  const LDMA_TransferCfg_t memTransfer = LDMA_TRANSFER_CFG_MEMORY();
+
+  const LDMA_Descriptor_t xfer[] =
+  {
+    LDMA_DESCRIPTOR_LINKREL_M2M_HALF( src, dest     , 4, 1 ),
+    LDMA_DESCRIPTOR_SINGLE_M2M_HALF ( src, dest + 10, 4 )
+  };
+
+  LDMA_Init_t init = LDMA_INIT_DEFAULT;
+
+  LDMA_Init( &init );
+
+  LDMA_StartTransfer( 0, (void*)&memTransfer, (void*)&xfer );
+  @endverbatim
+
+  @n A list of three memory to memory transfers:
+  @verbatim
+  // A transfer of 4 half words which links to another transfer of 4 half words,
+  // which again links to a third transfer of 4 half words.
+
+  const LDMA_TransferCfg_t memTransfer = LDMA_TRANSFER_CFG_MEMORY();
+
+  const LDMA_Descriptor_t xfer[] =
+  {
+    LDMA_DESCRIPTOR_LINKREL_M2M_HALF( src    , dest     , 4, 1 ),
+    LDMA_DESCRIPTOR_LINKREL_M2M_HALF( src + 2, dest + 5 , 4, 1 ),
+    LDMA_DESCRIPTOR_SINGLE_M2M_HALF ( src + 4, dest + 10, 4 )
+  };
+
+  LDMA_Init_t init = LDMA_INIT_DEFAULT;
+
+  LDMA_Init( &init );
+
+  LDMA_StartTransfer( 0, (void*)&memTransfer, (void*)&xfer );
+  @endverbatim
+
+  @n DMA from serial port peripheral to memory:
+  @verbatim
+  // Transfer 4 chars from USART1.
+
+  const LDMA_TransferCfg_t periTransferRx =
+        LDMA_TRANSFER_CFG_PERIPHERAL( ldmaPeripheralSignal_USART1_RXDATAV );
+
+  const LDMA_Descriptor_t xfer =
+    LDMA_DESCRIPTOR_SINGLE_P2M_BYTE( &USART1->RXDATA, // Peripheral address
+                                     dest,            // Destination (SRAM)
+                                     4 );             // Number of bytes
+
+  LDMA_Init_t init = LDMA_INIT_DEFAULT;
+
+  LDMA_Init( &init );
+
+  LDMA_StartTransfer( 0, (void*)&periTransferRx, (void*)&xfer );
+  @endverbatim
+
+  @n Ping pong DMA from serial port peripheral to memory:
+  @verbatim
+  // Ping Pong transfer from USART1.
+
+  static char buff1[5];
+  static char buff2[5];
+
+  const LDMA_TransferCfg_t periTransferRx =
+        LDMA_TRANSFER_CFG_PERIPHERAL( ldmaPeripheralSignal_USART1_RXDATAV );
+
+  const LDMA_Descriptor_t xfer[] =
+  {
+    // Note the 1 and -1 link jump increments. This will cause each DMA transfer
+    // to link to the other one in an endless loop.
+    LDMA_DESCRIPTOR_LINKREL_P2M_BYTE( &USART1->RXDATA,  // Peripheral address
+                                      buff1,            // Destination (SRAM)
+                                      5,                // Number of bytes
+                                      1 ),              // Next descriptor
+    LDMA_DESCRIPTOR_LINKREL_P2M_BYTE( &USART1->RXDATA,  // Peripheral address
+                                      buff2,            // Destination (SRAM)
+                                      5,                // Number of bytes
+                                      -1 )              // Next descriptor
+  };
+
+  LDMA_Init_t init = LDMA_INIT_DEFAULT;
+
+  LDMA_Init( &init );
+
+  LDMA_StartTransfer( 0, (void*)&periTransferRx, (void*)&xfer );
+  @endverbatim
+ * @{ *************************************************************************/
+
+#if defined( LDMA_IRQ_HANDLER_TEMPLATE )
+/***************************************************************************//**
+ * @brief
+ *   Template for an LDMA IRQ handler.
+ ******************************************************************************/
+void LDMA_IRQHandler( void )
+{
+  uint32_t pending, chnum, chmask;
+
+  /* Get all pending and enabled interrupts */
+  pending  = LDMA->IF;
+  pending &= LDMA->IEN;
+
+  /* Check for LDMA error */
+  if ( pending & LDMA_IF_ERROR )
+  {
+    /* Loop here to enable the debugger to see what has happened */
+    while (1)
+      ;
+  }
+
+  /* Iterate over all LDMA channels. */
+  for ( chnum = 0,                chmask = 1;
+        chnum < DMA_CHAN_COUNT;
+        chnum++,                  chmask <<= 1 )
+  {
+    if ( pending & chmask )
+    {
+      /* Clear interrupt flag. */
+      LDMA->IFC = chmask;
+
+      /* Do more stuff here, execute callbacks etc. */
+    }
+  }
+}
+#endif
+
+/***************************************************************************//**
+ * @brief
+ *   De-initialize the LDMA controller.
+ *
+ *   LDMA interrupts are disabled and the LDMA clock is stopped.
+ ******************************************************************************/
+void LDMA_DeInit( void )
+{
+  NVIC_DisableIRQ( LDMA_IRQn );
+  LDMA->IEN  = 0;
+  LDMA->CHEN = 0;
+  CMU_ClockEnable( cmuClock_LDMA, false );
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Initialize the LDMA controller.
+ *
+ * @param[in] init
+ *   Pointer to initialization structure used to configure the setup.
+ ******************************************************************************/
+void LDMA_Init( LDMA_Init_t *init )
+{
+  EFM_ASSERT( init != NULL );
+  EFM_ASSERT( !( ( init->ldmaInitCtrlNumFixed << _LDMA_CTRL_NUMFIXED_SHIFT )
+                 & ~_LDMA_CTRL_NUMFIXED_MASK ) );
+  EFM_ASSERT( !( ( init->ldmaInitCtrlSyncPrsClrEn << _LDMA_CTRL_SYNCPRSCLREN_SHIFT )
+                 & ~_LDMA_CTRL_SYNCPRSCLREN_MASK ) );
+  EFM_ASSERT( !( ( init->ldmaInitCtrlSyncPrsSetEn << _LDMA_CTRL_SYNCPRSSETEN_SHIFT )
+                 & ~_LDMA_CTRL_SYNCPRSSETEN_MASK ) );
+  EFM_ASSERT( init->ldmaInitIrqPriority < ( 1 << __NVIC_PRIO_BITS ) );
+
+  CMU_ClockEnable( cmuClock_LDMA, true );
+
+  LDMA->CTRL = (   init->ldmaInitCtrlNumFixed     << _LDMA_CTRL_NUMFIXED_SHIFT     )
+               | ( init->ldmaInitCtrlSyncPrsClrEn << _LDMA_CTRL_SYNCPRSCLREN_SHIFT )
+               | ( init->ldmaInitCtrlSyncPrsSetEn << _LDMA_CTRL_SYNCPRSSETEN_SHIFT );
+
+  LDMA->CHEN    = 0;
+  LDMA->DBGHALT = 0;
+  LDMA->REQDIS  = 0;
+
+  /* Enable LDMA error interrupt. */
+  LDMA->IEN = LDMA_IEN_ERROR;
+  LDMA->IFC = 0xFFFFFFFF;
+
+  NVIC_ClearPendingIRQ( LDMA_IRQn );
+
+  /* Range is 0..7, 0 is highest priority. */
+  NVIC_SetPriority( LDMA_IRQn, init->ldmaInitIrqPriority );
+
+  NVIC_EnableIRQ( LDMA_IRQn );
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Start a DMA transfer.
+ *
+ * @param[in] ch
+ *   DMA channel.
+ *
+ * @param[in] transfer
+ *   Initialization structure used to configure the transfer.
+ *
+ * @param[in] descriptor
+ *   Transfer descriptor, can be an array of descriptors linked together.
+ ******************************************************************************/
+void LDMA_StartTransfer(  int ch,
+                          LDMA_TransferCfg_t *transfer,
+                          LDMA_Descriptor_t  *descriptor )
+{
+  uint32_t tmp;
+  uint32_t chMask = 1 << ch;
+
+  EFM_ASSERT( ch < DMA_CHAN_COUNT );
+  EFM_ASSERT( transfer != NULL );
+  EFM_ASSERT( !( transfer->ldmaReqSel & ~_LDMA_CH_REQSEL_MASK ) );
+
+  EFM_ASSERT( !( ( transfer->ldmaCtrlSyncPrsClrOff << _LDMA_CTRL_SYNCPRSCLREN_SHIFT )
+                 & ~_LDMA_CTRL_SYNCPRSCLREN_MASK ) );
+  EFM_ASSERT( !( ( transfer->ldmaCtrlSyncPrsClrOn << _LDMA_CTRL_SYNCPRSCLREN_SHIFT )
+                 & ~_LDMA_CTRL_SYNCPRSCLREN_MASK ) );
+  EFM_ASSERT( !( ( transfer->ldmaCtrlSyncPrsSetOff << _LDMA_CTRL_SYNCPRSSETEN_SHIFT )
+                 & ~_LDMA_CTRL_SYNCPRSSETEN_MASK ) );
+  EFM_ASSERT( !( ( transfer->ldmaCtrlSyncPrsSetOn << _LDMA_CTRL_SYNCPRSSETEN_SHIFT  )
+                 & ~_LDMA_CTRL_SYNCPRSSETEN_MASK ) );
+
+  EFM_ASSERT( !( ( transfer->ldmaCfgArbSlots << _LDMA_CH_CFG_ARBSLOTS_SHIFT )
+                 & ~_LDMA_CH_CFG_ARBSLOTS_MASK ) );
+  EFM_ASSERT( !( ( transfer->ldmaCfgSrcIncSign << _LDMA_CH_CFG_SRCINCSIGN_SHIFT )
+                 & ~_LDMA_CH_CFG_SRCINCSIGN_MASK ) );
+  EFM_ASSERT( !( ( transfer->ldmaCfgDstIncSign << _LDMA_CH_CFG_DSTINCSIGN_SHIFT )
+                 & ~_LDMA_CH_CFG_DSTINCSIGN_MASK ) );
+  EFM_ASSERT( !( ( transfer->ldmaLoopCnt << _LDMA_CH_LOOP_LOOPCNT_SHIFT )
+                 & ~_LDMA_CH_LOOP_LOOPCNT_MASK ) );
+
+  LDMA->CH[ ch ].REQSEL = transfer->ldmaReqSel;
+
+  LDMA->CH[ ch ].LOOP =
+    (   transfer->ldmaLoopCnt       << _LDMA_CH_LOOP_LOOPCNT_SHIFT     );
+
+  LDMA->CH[ ch ].CFG =
+    ( transfer->ldmaCfgArbSlots     << _LDMA_CH_CFG_ARBSLOTS_SHIFT     )
+    | ( transfer->ldmaCfgSrcIncSign << _LDMA_CH_CFG_SRCINCSIGN_SHIFT   )
+    | ( transfer->ldmaCfgDstIncSign << _LDMA_CH_CFG_DSTINCSIGN_SHIFT   );
+
+  /* Set descriptor address. */
+  LDMA->CH[ ch ].LINK = (uint32_t)descriptor & _LDMA_CH_LINK_LINKADDR_MASK;
+
+  /* Clear pending channel interrupt. */
+  LDMA->IFC = chMask;
+
+  /* Critical region. */
+  INT_Disable();
+
+  /* Enable channel interrupt. */
+  LDMA->IEN |= chMask;
+
+  if ( transfer->ldmaReqDis )
+  {
+    LDMA->REQDIS |= chMask;
+  }
+
+  if ( transfer->ldmaDbgHalt )
+  {
+    LDMA->DBGHALT |= chMask;
+  }
+
+  tmp = LDMA->CTRL;
+
+  if ( transfer->ldmaCtrlSyncPrsClrOff )
+  {
+    tmp &= ~_LDMA_CTRL_SYNCPRSCLREN_MASK
+           | (~transfer->ldmaCtrlSyncPrsClrOff << _LDMA_CTRL_SYNCPRSCLREN_SHIFT);
+  }
+
+  if ( transfer->ldmaCtrlSyncPrsClrOn )
+  {
+    tmp |= transfer->ldmaCtrlSyncPrsClrOn << _LDMA_CTRL_SYNCPRSCLREN_SHIFT;
+  }
+
+  if ( transfer->ldmaCtrlSyncPrsSetOff )
+  {
+    tmp &= ~_LDMA_CTRL_SYNCPRSSETEN_MASK
+           | (~transfer->ldmaCtrlSyncPrsSetOff << _LDMA_CTRL_SYNCPRSSETEN_SHIFT);
+  }
+
+  if ( transfer->ldmaCtrlSyncPrsSetOn )
+  {
+    tmp |= transfer->ldmaCtrlSyncPrsSetOn << _LDMA_CTRL_SYNCPRSSETEN_SHIFT;
+  }
+
+  LDMA->CTRL = tmp;
+
+  BUS_RegMaskedClear(&LDMA->CHDONE, chMask);  /* Clear the done flag.     */
+  LDMA->LINKLOAD = chMask;                    /* Enable descriptor load.  */
+  BUS_RegMaskedSet(&LDMA->CHEN, chMask);      /* Enable channel.          */
+
+  /* Critical region end. */
+  INT_Enable();
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Stop a DMA transfer.
+ *
+ * @note
+ *   The DMA will complete the current AHB burst transfer before stopping.
+ *
+ * @param[in] ch
+ *   DMA channel to stop.
+ ******************************************************************************/
+void LDMA_StopTransfer( int ch )
+{
+  uint32_t chMask = 1 << ch;
+
+  EFM_ASSERT( ch < DMA_CHAN_COUNT );
+
+  INT_Disable();
+
+  LDMA->IEN &= ~chMask;
+  BUS_RegMaskedClear(&LDMA->CHEN, chMask);
+
+  INT_Enable();
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Check if a DMA transfer has completed.
+ *
+ * @param[in] ch
+ *   DMA channel to check.
+ *
+ * @return
+ *   True if transfer has completed, false if not.
+ ******************************************************************************/
+bool LDMA_TransferDone( int ch )
+{
+  bool     retVal = false;
+  uint32_t chMask = 1 << ch;
+
+  EFM_ASSERT( ch < DMA_CHAN_COUNT );
+
+  INT_Disable();
+  if (    ( ( LDMA->CHEN   & chMask ) == 0      )
+       && ( ( LDMA->CHDONE & chMask ) == chMask ) )
+  {
+    retVal = true;
+  }
+  INT_Enable();
+  return retVal;
+}
+
+/***************************************************************************//**
+ * @brief
+ *  Get number of items remaining in a transfer.
+ *
+ * @note
+ *  This function is does not take into account that a DMA transfers with
+ *  a chain of linked transfers might be ongoing. It will only check the
+ *  count for the current transfer.
+ *
+ * @param[in] ch
+ *  The channel number of the transfer to check.
+ *
+ * @return
+ *  Number of items remaining in the transfer.
+ ******************************************************************************/
+uint32_t LDMA_TransferRemainingCount( int ch )
+{
+  uint32_t remaining, done, iflag;
+  uint32_t chMask = 1 << ch;
+
+  EFM_ASSERT( ch < DMA_CHAN_COUNT );
+
+  INT_Disable();
+  iflag  = LDMA->IF;
+  done   = LDMA->CHDONE;
+  remaining = LDMA->CH[ ch ].CTRL;
+  INT_Enable();
+
+  iflag    &= chMask;
+  done     &= chMask;
+  remaining = ( remaining
+                & _LDMA_CH_CTRL_XFERCNT_MASK )
+              >> _LDMA_CH_CTRL_XFERCNT_SHIFT;
+
+  if ( done || ( ( remaining == 0 ) && iflag ) )
+  {
+    return 0;
+  }
+
+  return remaining + 1;
+}
+
+/** @} (end addtogroup LDMA) */
+/** @} (end addtogroup EM_Library) */
+#endif /* defined( LDMA_PRESENT ) && ( LDMA_COUNT == 1 ) */

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_lesense.c	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_lesense.c	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /***************************************************************************//**
  * @file em_lesense.c
  * @brief Low Energy Sensor (LESENSE) Peripheral API
- * @version 3.20.12
+ * @version 4.2.1
  *******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
  *******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,15 +30,14 @@
  *
  ******************************************************************************/
 
-
 #include "em_lesense.h"
 #if defined(LESENSE_COUNT) && (LESENSE_COUNT > 0)
 #include "em_assert.h"
-#include "em_bitband.h"
+#include "em_bus.h"
 #include "em_cmu.h"
 
 /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
-#ifndef UINT32_MAX
+#if !defined(UINT32_MAX)
 #define UINT32_MAX ((uint32_t)(0xFFFFFFFF))
 #endif
 /** @endcond */
@@ -116,23 +115,17 @@
    * SCANRES in CNT_RES after each scan, enable/disable to always write to the
    * result buffer, even if it is full, enable/disable LESENSE running in debug
    * mode. */
-  LESENSE->CTRL = ((uint32_t)init->coreCtrl.prsSel <<
-                   _LESENSE_CTRL_PRSSEL_SHIFT) |
-                  (uint32_t)init->coreCtrl.scanConfSel |
-                  (uint32_t)init->coreCtrl.bufTrigLevel |
-                  (uint32_t)init->coreCtrl.wakeupOnDMA |
-                  ((uint32_t)init->coreCtrl.invACMP0 <<
-                   _LESENSE_CTRL_ACMP0INV_SHIFT) |
-                  ((uint32_t)init->coreCtrl.invACMP1 <<
-                   _LESENSE_CTRL_ACMP1INV_SHIFT) |
-                  ((uint32_t)init->coreCtrl.dualSample <<
-                   _LESENSE_CTRL_DUALSAMPLE_SHIFT) |
-                  ((uint32_t)init->coreCtrl.storeScanRes <<
-                   _LESENSE_CTRL_STRSCANRES_SHIFT) |
-                  ((uint32_t)init->coreCtrl.bufOverWr <<
-                   _LESENSE_CTRL_BUFOW_SHIFT) |
-                  ((uint32_t)init->coreCtrl.debugRun <<
-                   _LESENSE_CTRL_DEBUGRUN_SHIFT);
+  LESENSE->CTRL =
+    ((uint32_t)init->coreCtrl.prsSel         << _LESENSE_CTRL_PRSSEL_SHIFT)
+    | (uint32_t)init->coreCtrl.scanConfSel
+    | (uint32_t)init->coreCtrl.bufTrigLevel
+    | (uint32_t)init->coreCtrl.wakeupOnDMA
+    | ((uint32_t)init->coreCtrl.invACMP0     << _LESENSE_CTRL_ACMP0INV_SHIFT)
+    | ((uint32_t)init->coreCtrl.invACMP1     << _LESENSE_CTRL_ACMP1INV_SHIFT)
+    | ((uint32_t)init->coreCtrl.dualSample   << _LESENSE_CTRL_DUALSAMPLE_SHIFT)
+    | ((uint32_t)init->coreCtrl.storeScanRes << _LESENSE_CTRL_STRSCANRES_SHIFT)
+    | ((uint32_t)init->coreCtrl.bufOverWr    << _LESENSE_CTRL_BUFOW_SHIFT)
+    | ((uint32_t)init->coreCtrl.debugRun     << _LESENSE_CTRL_DEBUGRUN_SHIFT);
 
   /* Set scan mode in the CTRL register using the provided function, don't
    * start scanning immediately. */
@@ -142,26 +135,18 @@
    * Set DAC0 and DAC1 data source, conversion mode, output mode. Set DAC
    * prescaler and reference. Set ACMP0 and ACMP1 control mode. Set ACMP and DAC
    * duty cycle (warm up) mode. */
-  LESENSE->PERCTRL = ((uint32_t)init->perCtrl.dacCh0Data <<
-                      _LESENSE_PERCTRL_DACCH0DATA_SHIFT) |
-                     ((uint32_t)init->perCtrl.dacCh0ConvMode <<
-                      _LESENSE_PERCTRL_DACCH0CONV_SHIFT) |
-                     ((uint32_t)init->perCtrl.dacCh0OutMode <<
-                      _LESENSE_PERCTRL_DACCH0OUT_SHIFT) |
-                     ((uint32_t)init->perCtrl.dacCh1Data <<
-                      _LESENSE_PERCTRL_DACCH1DATA_SHIFT) |
-                     ((uint32_t)init->perCtrl.dacCh1ConvMode <<
-                      _LESENSE_PERCTRL_DACCH1CONV_SHIFT) |
-                     ((uint32_t)init->perCtrl.dacCh1OutMode <<
-                      _LESENSE_PERCTRL_DACCH1OUT_SHIFT) |
-                     ((uint32_t)init->perCtrl.dacPresc <<
-                      _LESENSE_PERCTRL_DACPRESC_SHIFT) |
-                     (uint32_t)init->perCtrl.dacRef |
-                     ((uint32_t)init->perCtrl.acmp0Mode <<
-                      _LESENSE_PERCTRL_ACMP0MODE_SHIFT) |
-                     ((uint32_t)init->perCtrl.acmp1Mode <<
-                      _LESENSE_PERCTRL_ACMP1MODE_SHIFT) |
-                     (uint32_t)init->perCtrl.warmupMode;
+  LESENSE->PERCTRL =
+    ((uint32_t)init->perCtrl.dacCh0Data       << _LESENSE_PERCTRL_DACCH0DATA_SHIFT)
+    | ((uint32_t)init->perCtrl.dacCh0ConvMode << _LESENSE_PERCTRL_DACCH0CONV_SHIFT)
+    | ((uint32_t)init->perCtrl.dacCh0OutMode  << _LESENSE_PERCTRL_DACCH0OUT_SHIFT)
+    | ((uint32_t)init->perCtrl.dacCh1Data     << _LESENSE_PERCTRL_DACCH1DATA_SHIFT)
+    | ((uint32_t)init->perCtrl.dacCh1ConvMode << _LESENSE_PERCTRL_DACCH1CONV_SHIFT)
+    | ((uint32_t)init->perCtrl.dacCh1OutMode  << _LESENSE_PERCTRL_DACCH1OUT_SHIFT)
+    | ((uint32_t)init->perCtrl.dacPresc       << _LESENSE_PERCTRL_DACPRESC_SHIFT)
+    | (uint32_t)init->perCtrl.dacRef
+    | ((uint32_t)init->perCtrl.acmp0Mode      << _LESENSE_PERCTRL_ACMP0MODE_SHIFT)
+    | ((uint32_t)init->perCtrl.acmp1Mode      << _LESENSE_PERCTRL_ACMP1MODE_SHIFT)
+    | (uint32_t)init->perCtrl.warmupMode;
 
   /* LESENSE decoder general control configuration.
    * Set decoder input source, select PRS input for decoder bits.
@@ -171,29 +156,19 @@
    * Enable/disable decoder hysteresis on count events.
    * Enable/disable decoder hysteresis on interrupt requests.
    * Enable/disable count mode on LESPRS0 and LESPRS1. */
-  LESENSE->DECCTRL = (uint32_t)init->decCtrl.decInput |
-                     ((uint32_t)init->decCtrl.prsChSel0 <<
-                      _LESENSE_DECCTRL_PRSSEL0_SHIFT) |
-                     ((uint32_t)init->decCtrl.prsChSel1 <<
-                      _LESENSE_DECCTRL_PRSSEL1_SHIFT) |
-                     ((uint32_t)init->decCtrl.prsChSel2 <<
-                      _LESENSE_DECCTRL_PRSSEL2_SHIFT) |
-                     ((uint32_t)init->decCtrl.prsChSel3 <<
-                      _LESENSE_DECCTRL_PRSSEL3_SHIFT) |
-                     ((uint32_t)init->decCtrl.chkState <<
-                      _LESENSE_DECCTRL_ERRCHK_SHIFT) |
-                     ((uint32_t)init->decCtrl.intMap <<
-                      _LESENSE_DECCTRL_INTMAP_SHIFT) |
-                     ((uint32_t)init->decCtrl.hystPRS0 <<
-                      _LESENSE_DECCTRL_HYSTPRS0_SHIFT) |
-                     ((uint32_t)init->decCtrl.hystPRS1 <<
-                      _LESENSE_DECCTRL_HYSTPRS1_SHIFT) |
-                     ((uint32_t)init->decCtrl.hystPRS2 <<
-                      _LESENSE_DECCTRL_HYSTPRS2_SHIFT) |
-                     ((uint32_t)init->decCtrl.hystIRQ <<
-                      _LESENSE_DECCTRL_HYSTIRQ_SHIFT) |
-                     ((uint32_t)init->decCtrl.prsCount <<
-                      _LESENSE_DECCTRL_PRSCNT_SHIFT);
+  LESENSE->DECCTRL =
+    (uint32_t)init->decCtrl.decInput
+    | ((uint32_t)init->decCtrl.prsChSel0 << _LESENSE_DECCTRL_PRSSEL0_SHIFT)
+    | ((uint32_t)init->decCtrl.prsChSel1 << _LESENSE_DECCTRL_PRSSEL1_SHIFT)
+    | ((uint32_t)init->decCtrl.prsChSel2 << _LESENSE_DECCTRL_PRSSEL2_SHIFT)
+    | ((uint32_t)init->decCtrl.prsChSel3 << _LESENSE_DECCTRL_PRSSEL3_SHIFT)
+    | ((uint32_t)init->decCtrl.chkState  << _LESENSE_DECCTRL_ERRCHK_SHIFT)
+    | ((uint32_t)init->decCtrl.intMap    << _LESENSE_DECCTRL_INTMAP_SHIFT)
+    | ((uint32_t)init->decCtrl.hystPRS0  << _LESENSE_DECCTRL_HYSTPRS0_SHIFT)
+    | ((uint32_t)init->decCtrl.hystPRS1  << _LESENSE_DECCTRL_HYSTPRS1_SHIFT)
+    | ((uint32_t)init->decCtrl.hystPRS2  << _LESENSE_DECCTRL_HYSTPRS2_SHIFT)
+    | ((uint32_t)init->decCtrl.hystIRQ   << _LESENSE_DECCTRL_HYSTIRQ_SHIFT)
+    | ((uint32_t)init->decCtrl.prsCount  << _LESENSE_DECCTRL_PRSCNT_SHIFT);
 
   /* Set initial LESENSE decoder state. */
   LESENSE_DecoderStateSet((uint32_t)init->decCtrl.initState);
@@ -256,8 +231,8 @@
   /* Calculate the minimum necessary prescaler value in order to provide the
    * biggest possible resolution for setting scan frequency.
    * Maximum number of calculation cycles is 7 (value of lesenseClkDiv_128). */
-  while ((refFreq / ((uint32_t)scanFreq * clkDiv) > (pcTop + 1UL)) &&
-         (pcPresc < lesenseClkDiv_128))
+  while ((refFreq / ((uint32_t)scanFreq * clkDiv) > (pcTop + 1UL))
+         && (pcPresc < lesenseClkDiv_128))
   {
     ++pcPresc;
     clkDiv = (uint32_t)1UL << pcPresc;
@@ -268,12 +243,12 @@
 
   /* Clear current PCPRESC and PCTOP settings. Be aware of the effect of
    * non-atomic Read-Modify-Write on LESENSE->TIMCRTL. */
-  tmp = LESENSE->TIMCTRL & (~(_LESENSE_TIMCTRL_PCPRESC_MASK)&
-                            ~(_LESENSE_TIMCTRL_PCTOP_MASK));
+  tmp = LESENSE->TIMCTRL & (~_LESENSE_TIMCTRL_PCPRESC_MASK
+                            & ~_LESENSE_TIMCTRL_PCTOP_MASK);
 
   /* Set new values in tmp while reserving other settings. */
-  tmp |= ((uint32_t)pcPresc << _LESENSE_TIMCTRL_PCPRESC_SHIFT) |
-         ((uint32_t)pcTop << _LESENSE_TIMCTRL_PCTOP_SHIFT);
+  tmp |= ((uint32_t)pcPresc << _LESENSE_TIMCTRL_PCPRESC_SHIFT)
+         | ((uint32_t)pcTop << _LESENSE_TIMCTRL_PCTOP_SHIFT);
 
   /* Set values in LESENSE_TIMCTRL register. */
   LESENSE->TIMCTRL = tmp;
@@ -405,40 +380,34 @@
   /* Select clock to prescale */
   switch (clk)
   {
-  case lesenseClkHF:
-  {
-    /* Sanity check of clock divisor for HF clock. */
-    EFM_ASSERT((uint32_t)clkDiv <= lesenseClkDiv_8);
+    case lesenseClkHF:
+      /* Sanity check of clock divisor for HF clock. */
+      EFM_ASSERT((uint32_t)clkDiv <= lesenseClkDiv_8);
 
-    /* Clear current AUXPRESC settings. */
-    tmp = LESENSE->TIMCTRL & ~(_LESENSE_TIMCTRL_AUXPRESC_MASK);
+      /* Clear current AUXPRESC settings. */
+      tmp = LESENSE->TIMCTRL & ~(_LESENSE_TIMCTRL_AUXPRESC_MASK);
 
-    /* Set new values in tmp while reserving other settings. */
-    tmp |= ((uint32_t)clkDiv << _LESENSE_TIMCTRL_AUXPRESC_SHIFT);
+      /* Set new values in tmp while reserving other settings. */
+      tmp |= ((uint32_t)clkDiv << _LESENSE_TIMCTRL_AUXPRESC_SHIFT);
 
-    /* Set values in LESENSE_TIMCTRL register. */
-    LESENSE->TIMCTRL = tmp;
-  }
-  break;
+      /* Set values in LESENSE_TIMCTRL register. */
+      LESENSE->TIMCTRL = tmp;
+      break;
 
-  case lesenseClkLF:
-  {
-    /* Clear current LFPRESC settings. */
-    tmp = LESENSE->TIMCTRL & ~(_LESENSE_TIMCTRL_LFPRESC_MASK);
+    case lesenseClkLF:
+      /* Clear current LFPRESC settings. */
+      tmp = LESENSE->TIMCTRL & ~(_LESENSE_TIMCTRL_LFPRESC_MASK);
 
-    /* Set new values in tmp while reserving other settings. */
-    tmp |= ((uint32_t)clkDiv << _LESENSE_TIMCTRL_LFPRESC_SHIFT);
+      /* Set new values in tmp while reserving other settings. */
+      tmp |= ((uint32_t)clkDiv << _LESENSE_TIMCTRL_LFPRESC_SHIFT);
 
-    /* Set values in LESENSE_TIMCTRL register. */
-    LESENSE->TIMCTRL = tmp;
-  }
-  break;
+      /* Set values in LESENSE_TIMCTRL register. */
+      LESENSE->TIMCTRL = tmp;
+      break;
 
-  default:
-  {
-    EFM_ASSERT(0);
-  }
-  break;
+    default:
+      EFM_ASSERT(0);
+      break;
   }
 }
 
@@ -468,7 +437,6 @@
 {
   uint32_t i;
 
-
   /* Iterate through all the 16 channels */
   for (i = 0U; i < 16U; ++i)
   {
@@ -515,13 +483,21 @@
    * configuration parameters, check the parameter description of acmpThres for
    * for more details! */
   EFM_ASSERT(confCh->acmpThres < 4096U);
-  EFM_ASSERT(!(confCh->chPinExMode == lesenseChPinExDACOut &&
-               (chIdx != 2U) && (chIdx != 3U) && (chIdx != 4U) && (chIdx != 5U)));
-  EFM_ASSERT(!(confCh->chPinIdleMode == lesenseChPinIdleDACCh1 &&
-               ((chIdx != 12U) && (chIdx != 13U) && (chIdx != 14U) && (chIdx != 15U))));
-  EFM_ASSERT(!(confCh->chPinIdleMode == lesenseChPinIdleDACCh0 &&
-               ((chIdx != 0U) && (chIdx != 1U) && (chIdx != 2U) && (chIdx != 3U))));
-
+  EFM_ASSERT(!(confCh->chPinExMode == lesenseChPinExDACOut
+               && (chIdx != 2U)
+               && (chIdx != 3U)
+               && (chIdx != 4U)
+               && (chIdx != 5U)));
+  EFM_ASSERT(!(confCh->chPinIdleMode == lesenseChPinIdleDACCh1
+               && ((chIdx != 12U)
+                   && (chIdx != 13U)
+                   && (chIdx != 14U)
+                   && (chIdx != 15U))));
+  EFM_ASSERT(!(confCh->chPinIdleMode == lesenseChPinIdleDACCh0
+               && ((chIdx != 0U)
+                   && (chIdx != 1U)
+                   && (chIdx != 2U)
+                   && (chIdx != 3U))));
 
   /* Configure chIdx setup in LESENSE idle phase.
    * Read-modify-write in order to support reconfiguration during LESENSE
@@ -540,26 +516,22 @@
   /* Channel specific configuration of clocks, sample mode, excitation pin mode
    * alternate excitation usage and interrupt mode on scan channel chIdx in
    * LESENSE_CHchIdx_INTERACT. */
-  LESENSE->CH[chIdx].INTERACT = ((uint32_t)confCh->exClk << 
-                                 _LESENSE_CH_INTERACT_EXCLK_SHIFT) |
-                                ((uint32_t)confCh->sampleClk <<
-                                 _LESENSE_CH_INTERACT_SAMPLECLK_SHIFT) |
-                                (uint32_t)confCh->sampleMode |
-                                (uint32_t)confCh->intMode |
-                                (uint32_t)confCh->chPinExMode |
-                                ((uint32_t)confCh->useAltEx <<
-                                 _LESENSE_CH_INTERACT_ALTEX_SHIFT);
+  LESENSE->CH[chIdx].INTERACT =
+        ((uint32_t)confCh->exClk       << _LESENSE_CH_INTERACT_EXCLK_SHIFT)
+        | ((uint32_t)confCh->sampleClk << _LESENSE_CH_INTERACT_SAMPLECLK_SHIFT)
+        | (uint32_t)confCh->sampleMode
+        | (uint32_t)confCh->intMode
+        | (uint32_t)confCh->chPinExMode
+        | ((uint32_t)confCh->useAltEx  << _LESENSE_CH_INTERACT_ALTEX_SHIFT);
 
   /* Configure channel specific counter comparison mode, optional result
    * forwarding to decoder, optional counter value storing and optional result
    * inverting on scan channel chIdx in LESENSE_CHchIdx_EVAL. */
-  LESENSE->CH[chIdx].EVAL = (uint32_t)confCh->compMode |
-                            ((uint32_t)confCh->shiftRes <<
-                             _LESENSE_CH_EVAL_DECODE_SHIFT) |
-                            ((uint32_t)confCh->storeCntRes <<
-                             _LESENSE_CH_EVAL_STRSAMPLE_SHIFT) |
-                            ((uint32_t)confCh->invRes <<
-                             _LESENSE_CH_EVAL_SCANRESINV_SHIFT);
+  LESENSE->CH[chIdx].EVAL =
+        (uint32_t)confCh->compMode
+        | ((uint32_t)confCh->shiftRes    << _LESENSE_CH_EVAL_DECODE_SHIFT)
+        | ((uint32_t)confCh->storeCntRes << _LESENSE_CH_EVAL_STRSAMPLE_SHIFT)
+        | ((uint32_t)confCh->invRes      << _LESENSE_CH_EVAL_SCANRESINV_SHIFT);
 
   /* Configure analog comparator (ACMP) threshold and decision threshold for
    * counter separately with the function provided for that. */
@@ -567,23 +539,14 @@
                          (uint32_t)confCh->acmpThres,
                          (uint32_t)confCh->cntThres);
 
-  /* Enable/disable interrupts on channel.
-   * Note: BITBAND_Peripheral() function is used for setting/clearing single
-   * bit peripheral register bitfields. Read the function description in
-   * efm32_bitband.h for more details. */
-  BITBAND_Peripheral(&(LESENSE->IEN),
-                     (uint32_t)chIdx,
-                     (uint32_t)confCh->enaInt);
+  /* Enable/disable interrupts on channel */
+  BUS_RegBitWrite(&(LESENSE->IEN), chIdx, confCh->enaInt);
 
   /* Enable/disable CHchIdx pin. */
-  BITBAND_Peripheral(&(LESENSE->ROUTE),
-                     (uint32_t)chIdx,
-                     (uint32_t)confCh->enaPin);
+  BUS_RegBitWrite(&(LESENSE->ROUTE), chIdx, confCh->enaPin);
 
   /* Enable/disable scan channel chIdx. */
-  BITBAND_Peripheral(&(LESENSE->CHEN),
-                     (uint32_t)chIdx,
-                     (uint32_t)confCh->enaScanCh);
+  BUS_RegBitWrite(&(LESENSE->CHEN), chIdx, confCh->enaScanCh);
 }
 
 
@@ -611,54 +574,55 @@
 
 
   /* Configure alternate excitation mapping.
-   * Atomic read-modify-write using BITBAND_Peripheral function in order to
+   * Atomic read-modify-write using BUS_RegBitWrite function in order to
    * support reconfiguration during LESENSE operation. */
-  BITBAND_Peripheral(&(LESENSE->CTRL),
-                     _LESENSE_CTRL_ALTEXMAP_SHIFT,
-                     (uint32_t)confAltEx->altExMap);
+  BUS_RegBitWrite(&(LESENSE->CTRL),
+                  _LESENSE_CTRL_ALTEXMAP_SHIFT,
+                  confAltEx->altExMap);
 
   switch (confAltEx->altExMap)
   {
-  case lesenseAltExMapALTEX:
-    /* Iterate through the 8 possible alternate excitation pin descriptors. */
-    for (i = 0U; i < 8U; ++i)
-    {
-      /* Enable/disable alternate excitation pin i.
-       * Atomic read-modify-write using BITBAND_Peripheral function in order to
-       * support reconfiguration during LESENSE operation. */
-      BITBAND_Peripheral(&(LESENSE->ROUTE),
-                         (16UL + i),
-                         (uint32_t)confAltEx->AltEx[i].enablePin);
- 
-      /* Setup the idle phase state of alternate excitation pin i.
-       * Read-modify-write in order to support reconfiguration during LESENSE
-       * operation. */
-      tmp                = (LESENSE->ALTEXCONF & ~((uint32_t)0x3UL << (i * 2UL)));
-      tmp               |= ((uint32_t)confAltEx->AltEx[i].idleConf << (i * 2UL));
-      LESENSE->ALTEXCONF = tmp;
-      
-      /* Enable/disable always excite on channel i */
-      BITBAND_Peripheral(&(LESENSE->ALTEXCONF),
-                         (16UL + i),
-                         (uint32_t)confAltEx->AltEx[i].alwaysEx);
-    }
-    break;
+    case lesenseAltExMapALTEX:
+      /* Iterate through the 8 possible alternate excitation pin descriptors. */
+      for (i = 0U; i < 8U; ++i)
+      {
+        /* Enable/disable alternate excitation pin i.
+         * Atomic read-modify-write using BUS_RegBitWrite function in order to
+         * support reconfiguration during LESENSE operation. */
+        BUS_RegBitWrite(&(LESENSE->ROUTE),
+                        (16UL + i),
+                        confAltEx->AltEx[i].enablePin);
+
+        /* Setup the idle phase state of alternate excitation pin i.
+         * Read-modify-write in order to support reconfiguration during LESENSE
+         * operation. */
+        tmp                = (LESENSE->ALTEXCONF & ~((uint32_t)0x3UL << (i * 2UL)));
+        tmp               |= ((uint32_t)confAltEx->AltEx[i].idleConf << (i * 2UL));
+        LESENSE->ALTEXCONF = tmp;
 
-  case lesenseAltExMapACMP:
-    /* Iterate through all the 16 alternate excitation channels */
-    for (i = 0U; i < 16U; ++i)
-    {
-      /* Enable/disable alternate ACMP excitation channel pin i. */
-      /* Atomic read-modify-write using BITBAND_Peripheral function in order to
-       * support reconfiguration during LESENSE operation. */
-      BITBAND_Peripheral(&(LESENSE->ROUTE),
-                         i,
-                         (uint32_t)confAltEx->AltEx[i].enablePin);
-    }
-    break;
-  default:
-    /* Illegal value. */
-    EFM_ASSERT(0);
+        /* Enable/disable always excite on channel i */
+        BUS_RegBitWrite(&(LESENSE->ALTEXCONF),
+                        (16UL + i),
+                        confAltEx->AltEx[i].alwaysEx);
+      }
+      break;
+
+    case lesenseAltExMapACMP:
+      /* Iterate through all the 16 alternate excitation channels */
+      for (i = 0U; i < 16U; ++i)
+      {
+        /* Enable/disable alternate ACMP excitation channel pin i. */
+        /* Atomic read-modify-write using BUS_RegBitWrite function in order to
+         * support reconfiguration during LESENSE operation. */
+        BUS_RegBitWrite(&(LESENSE->ROUTE),
+                        i,
+                        confAltEx->AltEx[i].enablePin);
+      }
+      break;
+    default:
+      /* Illegal value. */
+      EFM_ASSERT(0);
+      break;
   }
 }
 
@@ -692,17 +656,13 @@
                            bool const enaPin)
 {
   /* Enable/disable the assigned pin of scan channel chIdx.
-   * Note: BITBAND_Peripheral() function is used for setting/clearing single
+   * Note: BUS_RegBitWrite() function is used for setting/clearing single
    * bit peripheral register bitfields. Read the function description in
-   * efm32_bitband.h for more details. */
-  BITBAND_Peripheral(&(LESENSE->ROUTE),
-                     (uint32_t)chIdx,
-                     (uint32_t)enaPin);
+   * em_bus.h for more details. */
+  BUS_RegBitWrite(&(LESENSE->ROUTE), chIdx, enaPin);
 
   /* Enable/disable scan channel chIdx. */
-  BITBAND_Peripheral(&(LESENSE->CHEN),
-                     (uint32_t)chIdx,
-                     (uint32_t)enaScanCh);
+  BUS_RegBitWrite(&(LESENSE->CHEN), chIdx, enaScanCh);
 }
 
 
@@ -777,12 +737,10 @@
 
   /* Channel specific timing configuration on scan channel chIdx.
    * Setting excitation time, sampling delay, measurement delay. */
-  LESENSE->CH[chIdx].TIMING = ((uint32_t)exTime <<
-                               _LESENSE_CH_TIMING_EXTIME_SHIFT) |
-                              ((uint32_t)sampleDelay <<
-                               _LESENSE_CH_TIMING_SAMPLEDLY_SHIFT) |
-                              ((uint32_t)measDelay <<
-                               _LESENSE_CH_TIMING_MEASUREDLY_SHIFT);
+  LESENSE->CH[chIdx].TIMING =
+              ((uint32_t)exTime        << _LESENSE_CH_TIMING_EXTIME_SHIFT)
+              | ((uint32_t)sampleDelay << _LESENSE_CH_TIMING_SAMPLEDLY_SHIFT)
+              | ((uint32_t)measDelay   << _LESENSE_CH_TIMING_MEASUREDLY_SHIFT);
 }
 
 
@@ -869,7 +827,6 @@
 {
   uint32_t i;
 
-
   /* Iterate through all the 16 decoder states. */
   for (i = 0U; i < 16U; ++i)
   {
@@ -910,30 +867,23 @@
    * Setting sensor compare value, sensor mask, next state index,
    * transition action, interrupt flag option and state descriptor chaining
    * configurations. */
-  LESENSE->ST[decSt].TCONFA = (uint32_t)confDecSt->confA.prsAct |
-                              ((uint32_t)confDecSt->confA.compMask <<
-                               _LESENSE_ST_TCONFA_MASK_SHIFT) |
-                              ((uint32_t)confDecSt->confA.compVal <<
-                               _LESENSE_ST_TCONFA_COMP_SHIFT) |
-                              ((uint32_t)confDecSt->confA.nextState <<
-                               _LESENSE_ST_TCONFA_NEXTSTATE_SHIFT) |
-                              ((uint32_t)confDecSt->confA.setInt <<
-                               _LESENSE_ST_TCONFA_SETIF_SHIFT) |
-                              ((uint32_t)confDecSt->chainDesc <<
-                               _LESENSE_ST_TCONFA_CHAIN_SHIFT);
+  LESENSE->ST[decSt].TCONFA =
+    (uint32_t)confDecSt->confA.prsAct
+    | ((uint32_t)confDecSt->confA.compMask  << _LESENSE_ST_TCONFA_MASK_SHIFT)
+    | ((uint32_t)confDecSt->confA.compVal   << _LESENSE_ST_TCONFA_COMP_SHIFT)
+    | ((uint32_t)confDecSt->confA.nextState << _LESENSE_ST_TCONFA_NEXTSTATE_SHIFT)
+    | ((uint32_t)confDecSt->confA.setInt    << _LESENSE_ST_TCONFA_SETIF_SHIFT)
+    | ((uint32_t)confDecSt->chainDesc       << _LESENSE_ST_TCONFA_CHAIN_SHIFT);
 
   /* Configure state descriptor Bi (LESENSE_STi_TCONFB).
    * Setting sensor compare value, sensor mask, next state index, transition
    * action and interrupt flag option configurations. */
-  LESENSE->ST[decSt].TCONFB = (uint32_t)confDecSt->confB.prsAct |
-                              ((uint32_t)confDecSt->confB.compMask <<
-                               _LESENSE_ST_TCONFB_MASK_SHIFT) |
-                              ((uint32_t)confDecSt->confB.compVal <<
-                               _LESENSE_ST_TCONFB_COMP_SHIFT) |
-                              ((uint32_t)confDecSt->confB.nextState <<
-                               _LESENSE_ST_TCONFB_NEXTSTATE_SHIFT) |
-                              ((uint32_t)confDecSt->confB.setInt <<
-                               _LESENSE_ST_TCONFB_SETIF_SHIFT);
+  LESENSE->ST[decSt].TCONFB =
+  (uint32_t)confDecSt->confB.prsAct
+    | ((uint32_t)confDecSt->confB.compMask  << _LESENSE_ST_TCONFB_MASK_SHIFT)
+    | ((uint32_t)confDecSt->confB.compVal   << _LESENSE_ST_TCONFB_COMP_SHIFT)
+    | ((uint32_t)confDecSt->confB.nextState << _LESENSE_ST_TCONFB_NEXTSTATE_SHIFT)
+    | ((uint32_t)confDecSt->confB.setInt    << _LESENSE_ST_TCONFB_SETIF_SHIFT);
 }
 
 
@@ -985,20 +935,22 @@
  *   returning. Each write operation to the CMD register may take up to 3 LF
  *   clock cycles, so the user should expect some delay. The user may implement
  *   a separate function to write multiple command bits in the CMD register
- *   in one single operation in order to optimize an application. 
+ *   in one single operation in order to optimize an application.
  ******************************************************************************/
 void LESENSE_ScanStart(void)
 {
   /* Wait for any pending previous write operation to the CMD register to
      complete before accessing the CMD register. */
-  while (LESENSE_SYNCBUSY_CMD & LESENSE->SYNCBUSY);
+  while (LESENSE_SYNCBUSY_CMD & LESENSE->SYNCBUSY)
+    ;
 
   /* Start scanning of sensors */
   LESENSE->CMD = LESENSE_CMD_START;
 
   /* Wait for the write operation to the CMD register to complete before
      returning. */
-  while (LESENSE_SYNCBUSY_CMD & LESENSE->SYNCBUSY);
+  while (LESENSE_SYNCBUSY_CMD & LESENSE->SYNCBUSY)
+    ;
 }
 
 
@@ -1013,7 +965,7 @@
  *   returning. Each write operation to the CMD register may take up to 3 LF
  *   clock cycles, so the user should expect some delay. The user may implement
  *   a separate function to write multiple command bits in the CMD register
- *   in one single operation in order to optimize an application. 
+ *   in one single operation in order to optimize an application.
  *
  * @note
  *   If issued during a scan, the command takes effect after scan completion.
@@ -1022,14 +974,16 @@
 {
   /* Wait for any pending previous write operation to the CMD register to
      complete before accessing the CMD register. */
-  while (LESENSE_SYNCBUSY_CMD & LESENSE->SYNCBUSY);
+  while (LESENSE_SYNCBUSY_CMD & LESENSE->SYNCBUSY)
+    ;
 
   /* Stop scanning of sensors */
   LESENSE->CMD = LESENSE_CMD_STOP;
 
   /* Wait for the write operation to the CMD register to complete before
      returning. */
-  while (LESENSE_SYNCBUSY_CMD & LESENSE->SYNCBUSY);
+  while (LESENSE_SYNCBUSY_CMD & LESENSE->SYNCBUSY)
+    ;
 }
 
 
@@ -1044,20 +998,22 @@
  *   returning. Each write operation to the CMD register may take up to 3 LF
  *   clock cycles, so the user should expect some delay. The user may implement
  *   a separate function to write multiple command bits in the CMD register
- *   in one single operation in order to optimize an application. 
+ *   in one single operation in order to optimize an application.
  ******************************************************************************/
 void LESENSE_DecoderStart(void)
 {
   /* Wait for any pending previous write operation to the CMD register to
      complete before accessing the CMD register. */
-  while (LESENSE_SYNCBUSY_CMD & LESENSE->SYNCBUSY);
+  while (LESENSE_SYNCBUSY_CMD & LESENSE->SYNCBUSY)
+    ;
 
   /* Start decoder */
   LESENSE->CMD = LESENSE_CMD_DECODE;
 
   /* Wait for the write operation to the CMD register to complete before
      returning. */
-  while (LESENSE_SYNCBUSY_CMD & LESENSE->SYNCBUSY);
+  while (LESENSE_SYNCBUSY_CMD & LESENSE->SYNCBUSY)
+    ;
 }
 
 
@@ -1072,19 +1028,21 @@
  *   returning. Each write operation to the CMD register may take up to 3 LF
  *   clock cycles, so the user should expect some delay. The user may implement
  *   a separate function to write multiple command bits in the CMD register
- *   in one single operation in order to optimize an application. 
+ *   in one single operation in order to optimize an application.
  ******************************************************************************/
 void LESENSE_ResultBufferClear(void)
 {
   /* Wait for any pending previous write operation to the CMD register to
      complete before accessing the CMD register. */
-  while (LESENSE_SYNCBUSY_CMD & LESENSE->SYNCBUSY);
+  while (LESENSE_SYNCBUSY_CMD & LESENSE->SYNCBUSY)
+    ;
 
   LESENSE->CMD = LESENSE_CMD_CLEARBUF;
 
   /* Wait for the write operation to the CMD register to complete before
      returning. */
-  while (LESENSE_SYNCBUSY_CMD & LESENSE->SYNCBUSY);
+  while (LESENSE_SYNCBUSY_CMD & LESENSE->SYNCBUSY)
+    ;
 }
 
 
@@ -1105,7 +1063,6 @@
 {
   uint32_t i;
 
-
   /* Disable all LESENSE interrupts first */
   LESENSE->IEN = _LESENSE_IEN_RESETVALUE;
 
@@ -1117,7 +1074,9 @@
 
   /* Wait for any pending previous write operation to the CMD register to
      complete before accessing the CMD register. */
-  while (LESENSE_SYNCBUSY_CMD & LESENSE->SYNCBUSY);
+  while (LESENSE_SYNCBUSY_CMD & LESENSE->SYNCBUSY)
+    ;
+
   /* Stop sensor scan and clear result buffer */
   LESENSE->CMD = (LESENSE_CMD_STOP | LESENSE_CMD_CLEARBUF);
 
@@ -1147,9 +1106,11 @@
     LESENSE->ST[i].TCONFA = _LESENSE_ST_TCONFA_RESETVALUE;
     LESENSE->ST[i].TCONFB = _LESENSE_ST_TCONFB_RESETVALUE;
   }
+
   /* Wait for the write operation to the CMD register to complete before
      returning. */
-  while (LESENSE_SYNCBUSY_CMD & LESENSE->SYNCBUSY);
+  while (LESENSE_SYNCBUSY_CMD & LESENSE->SYNCBUSY)
+    ;
 }
 
 

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_letimer.c	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_letimer.c	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /***************************************************************************//**
  * @file em_letimer.c
  * @brief Low Energy Timer (LETIMER) Peripheral API
- * @version 3.20.12
+ * @version 4.2.1
  *******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
  *******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,7 +30,6 @@
  *
  ******************************************************************************/
 
-
 #include "em_letimer.h"
 #if defined(LETIMER_COUNT) && (LETIMER_COUNT > 0)
 #include "em_cmu.h"
@@ -88,12 +87,14 @@
  *   Bitmask corresponding to SYNCBUSY register defined bits, indicating
  *   registers that must complete any ongoing synchronization.
  ******************************************************************************/
-__STATIC_INLINE void LETIMER_Sync(LETIMER_TypeDef *letimer, uint32_t mask)
+__STATIC_INLINE void regSync(LETIMER_TypeDef *letimer, uint32_t mask)
 {
+#if defined(_LETIMER_FREEZE_MASK)
   /* Avoid deadlock if modifying the same register twice when freeze mode is */
   /* activated. */
   if (letimer->FREEZE & LETIMER_FREEZE_REGFREEZE)
     return;
+#endif
 
   /* Wait for any pending previous write operation to have been completed */
   /* in low frequency domain, only required for Gecko Family of devices  */
@@ -130,18 +131,18 @@
   /* Initialize selected compare value */
   switch (comp)
   {
-  case 0:
-    ret = letimer->COMP0;
-    break;
+    case 0:
+      ret = letimer->COMP0;
+      break;
 
-  case 1:
-    ret = letimer->COMP1;
-    break;
+    case 1:
+      ret = letimer->COMP1;
+      break;
 
-  default:
-    /* Unknown compare register selected */
-    ret = 0;
-    break;
+    default:
+      /* Unknown compare register selected */
+      ret = 0;
+      break;
   }
 
   return(ret);
@@ -174,29 +175,31 @@
 {
   volatile uint32_t *compReg;
 
-  EFM_ASSERT(LETIMER_REF_VALID(letimer) &&
-             LETIMER_COMP_REG_VALID(comp) &&
-             ((value & ~(_LETIMER_COMP0_COMP0_MASK >> _LETIMER_COMP0_COMP0_SHIFT)) == 0));
+  EFM_ASSERT(LETIMER_REF_VALID(letimer)
+             && LETIMER_COMP_REG_VALID(comp)
+             && ((value & ~(_LETIMER_COMP0_COMP0_MASK
+                            >> _LETIMER_COMP0_COMP0_SHIFT))
+                 == 0));
 
   /* Initialize selected compare value */
   switch (comp)
   {
-  case 0:
-    compReg  = &(letimer->COMP0);
-    break;
+    case 0:
+      compReg  = &(letimer->COMP0);
+      break;
 
-  case 1:
-    compReg  = &(letimer->COMP1);
-    break;
+    case 1:
+      compReg  = &(letimer->COMP1);
+      break;
 
-  default:
-    /* Unknown compare register selected, abort */
-    return;
+    default:
+      /* Unknown compare register selected, abort */
+      return;
   }
 
 #if defined(_EFM32_GECKO_FAMILY)
   /* LF register about to be modified require sync. busy check */
-  LETIMER_Sync(letimer, comp ? LETIMER_SYNCBUSY_COMP1 : LETIMER_SYNCBUSY_COMP0);
+  regSync(letimer, comp ? LETIMER_SYNCBUSY_COMP1 : LETIMER_SYNCBUSY_COMP0);
 #endif
 
   *compReg = value;
@@ -227,7 +230,7 @@
 
 #if defined(_EFM32_GECKO_FAMILY)
   /* LF register about to be modified require sync. busy check */
-  LETIMER_Sync(letimer, LETIMER_SYNCBUSY_CMD);
+  regSync(letimer, LETIMER_SYNCBUSY_CMD);
 #endif
 
   if (enable)
@@ -240,7 +243,7 @@
   }
 }
 
-
+#if defined(_LETIMER_FREEZE_MASK)
 /***************************************************************************//**
  * @brief
  *   LETIMER register synchronization freeze control.
@@ -291,7 +294,7 @@
     letimer->FREEZE = 0;
   }
 }
-
+#endif /* defined(_LETIMER_FREEZE_MASK) */
 
 /***************************************************************************//**
  * @brief
@@ -328,7 +331,7 @@
   {
 #if defined(_EFM32_GECKO_FAMILY)
     /* LF register about to be modified require sync. busy check */
-    LETIMER_Sync(letimer, LETIMER_SYNCBUSY_CMD);
+    regSync(letimer, LETIMER_SYNCBUSY_CMD);
 #endif
     letimer->CMD = LETIMER_CMD_STOP;
   }
@@ -340,6 +343,7 @@
     tmp |= LETIMER_CTRL_DEBUGRUN;
   }
 
+#if defined(LETIMER_CTRL_RTCC0TEN)
   if (init->rtcComp0Enable)
   {
     tmp |= LETIMER_CTRL_RTCC0TEN;
@@ -349,6 +353,7 @@
   {
     tmp |= LETIMER_CTRL_RTCC1TEN;
   }
+#endif
 
   if (init->comp0Top)
   {
@@ -376,7 +381,7 @@
 
 #if defined(_EFM32_GECKO_FAMILY)
   /* LF register about to be modified require sync. busy check */
-  LETIMER_Sync(letimer, LETIMER_SYNCBUSY_CTRL);
+  regSync(letimer, LETIMER_SYNCBUSY_CTRL);
 #endif
   letimer->CTRL = tmp;
 
@@ -385,7 +390,7 @@
   {
 #if defined(_EFM32_GECKO_FAMILY)
     /* LF register about to be modified require sync. busy check */
-    LETIMER_Sync(letimer, LETIMER_SYNCBUSY_CMD);
+    regSync(letimer, LETIMER_SYNCBUSY_CMD);
 #endif
     letimer->CMD = LETIMER_CMD_START;
   }
@@ -414,18 +419,18 @@
   /* Initialize selected compare value */
   switch (rep)
   {
-  case 0:
-    ret = letimer->REP0;
-    break;
+    case 0:
+      ret = letimer->REP0;
+      break;
 
-  case 1:
-    ret = letimer->REP1;
-    break;
+    case 1:
+      ret = letimer->REP1;
+      break;
 
-  default:
-    /* Unknown compare register selected */
-    ret = 0;
-    break;
+    default:
+      /* Unknown compare register selected */
+      ret = 0;
+      break;
   }
 
   return(ret);
@@ -460,35 +465,37 @@
 #if defined(_EFM32_GECKO_FAMILY)
   uint32_t          syncbusy;
 #endif
-  EFM_ASSERT(LETIMER_REF_VALID(letimer) &&
-             LETIMER_REP_REG_VALID(rep) &&
-             ((value & ~(_LETIMER_REP0_REP0_MASK >> _LETIMER_REP0_REP0_SHIFT)) == 0));
+  EFM_ASSERT(LETIMER_REF_VALID(letimer)
+             && LETIMER_REP_REG_VALID(rep)
+             && ((value & ~(_LETIMER_REP0_REP0_MASK
+                            >> _LETIMER_REP0_REP0_SHIFT))
+                 == 0));
 
   /* Initialize selected compare value */
   switch (rep)
   {
-  case 0:
-    repReg = &(letimer->REP0);
+    case 0:
+      repReg = &(letimer->REP0);
 #if defined(_EFM32_GECKO_FAMILY)
-    syncbusy = LETIMER_SYNCBUSY_REP0;
+      syncbusy = LETIMER_SYNCBUSY_REP0;
 #endif
-    break;
+      break;
 
-  case 1:
-    repReg = &(letimer->REP1);
+    case 1:
+      repReg = &(letimer->REP1);
 #if defined(_EFM32_GECKO_FAMILY)
-    syncbusy = LETIMER_SYNCBUSY_REP1;
+      syncbusy = LETIMER_SYNCBUSY_REP1;
 #endif
-    break;
+      break;
 
-  default:
-    /* Unknown compare register selected, abort */
-    return;
+    default:
+      /* Unknown compare register selected, abort */
+      return;
   }
 
 #if defined(_EFM32_GECKO_FAMILY)
   /* LF register about to be modified require sync. busy check */
-  LETIMER_Sync(letimer, syncbusy);
+  regSync(letimer, syncbusy);
 #endif
 
   *repReg = value;
@@ -508,12 +515,14 @@
  ******************************************************************************/
 void LETIMER_Reset(LETIMER_TypeDef *letimer)
 {
+#if defined(_LETIMER_FREEZE_MASK)
   /* Freeze registers to avoid stalling for LF synchronization */
   LETIMER_FreezeEnable(letimer, true);
+#endif
 
   /* Make sure disabled first, before resetting other registers */
-  letimer->CMD = LETIMER_CMD_STOP | LETIMER_CMD_CLEAR |
-                 LETIMER_CMD_CTO0 | LETIMER_CMD_CTO1;
+  letimer->CMD = LETIMER_CMD_STOP | LETIMER_CMD_CLEAR
+                 | LETIMER_CMD_CTO0 | LETIMER_CMD_CTO1;
   letimer->CTRL  = _LETIMER_CTRL_RESETVALUE;
   letimer->COMP0 = _LETIMER_COMP0_RESETVALUE;
   letimer->COMP1 = _LETIMER_COMP1_RESETVALUE;
@@ -523,8 +532,10 @@
   letimer->IFC   = _LETIMER_IFC_MASK;
   /* Do not reset route register, setting should be done independently */
 
+#if defined(_LETIMER_FREEZE_MASK)
   /* Unfreeze registers, pass new settings on to LETIMER */
   LETIMER_FreezeEnable(letimer, false);
+#endif
 }
 
 

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_leuart.c	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_leuart.c	Fri Jan 15 07:45:16 2016 +0000
@@ -2,10 +2,10 @@
  * @file em_leuart.c
  * @brief Low Energy Universal Asynchronous Receiver/Transmitter (LEUART)
  *   Peripheral API
- * @version 3.20.12
+ * @version 4.2.1
  *******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
  *******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -31,7 +31,6 @@
  *
  ******************************************************************************/
 
-
 #include "em_leuart.h"
 #if defined(LEUART_COUNT) && (LEUART_COUNT > 0)
 
@@ -64,7 +63,7 @@
 #elif (LEUART_COUNT == 2)
 #define LEUART_REF_VALID(ref)    (((ref) == LEUART0) || ((ref) == LEUART1))
 #else
-#error Undefined number of low energy UARTs (LEUART).
+#error "Undefined number of low energy UARTs (LEUART)."
 #endif
 
 /** @endcond */
@@ -174,8 +173,7 @@
    * where a is 'refFreq' and b is 'divisor', referring to variable names.
    */
 
-  divisor = 256 + clkdiv;
-
+  divisor   = 256 + clkdiv;
   quotient  = refFreq / divisor;
   remainder = refFreq % divisor;
 
@@ -470,17 +468,17 @@
   LEUART_FreezeEnable(leuart, true);
 
   /* Configure databits and stopbits */
-  leuart->CTRL = (leuart->CTRL & ~(_LEUART_CTRL_PARITY_MASK |
-                                   _LEUART_CTRL_STOPBITS_MASK)) |
-                 (uint32_t)(init->databits) |
-                 (uint32_t)(init->parity) |
-                 (uint32_t)(init->stopbits);
+  leuart->CTRL = (leuart->CTRL & ~(_LEUART_CTRL_PARITY_MASK
+                                   | _LEUART_CTRL_STOPBITS_MASK))
+                 | (uint32_t)(init->databits)
+                 | (uint32_t)(init->parity)
+                 | (uint32_t)(init->stopbits);
 
   /* Configure baudrate */
   LEUART_BaudrateSet(leuart, init->refFreq, init->baudrate);
 
   /* Finally enable (as specified) */
-  leuart->CMD = (uint32_t)(init->enable);
+  leuart->CMD = (uint32_t)init->enable;
 
   /* Unfreeze registers, pass new settings on to LEUART */
   LEUART_FreezeEnable(leuart, false);
@@ -503,8 +501,8 @@
   LEUART_FreezeEnable(leuart, true);
 
   /* Make sure disabled first, before resetting other registers */
-  leuart->CMD = LEUART_CMD_RXDIS | LEUART_CMD_TXDIS | LEUART_CMD_RXBLOCKDIS |
-                LEUART_CMD_CLEARTX | LEUART_CMD_CLEARRX;
+  leuart->CMD = LEUART_CMD_RXDIS | LEUART_CMD_TXDIS | LEUART_CMD_RXBLOCKDIS
+                | LEUART_CMD_CLEARTX | LEUART_CMD_CLEARRX;
   leuart->CTRL       = _LEUART_CTRL_RESETVALUE;
   leuart->CLKDIV     = _LEUART_CLKDIV_RESETVALUE;
   leuart->STARTFRAME = _LEUART_STARTFRAME_RESETVALUE;
@@ -512,7 +510,12 @@
   leuart->IEN        = _LEUART_IEN_RESETVALUE;
   leuart->IFC        = _LEUART_IFC_MASK;
   leuart->PULSECTRL  = _LEUART_PULSECTRL_RESETVALUE;
+#if defined(_LEUART_ROUTEPEN_MASK)
+  leuart->ROUTEPEN   = _LEUART_ROUTEPEN_RESETVALUE;
+  leuart->ROUTELOC0  = _LEUART_ROUTELOC0_RESETVALUE;
+#else
   leuart->ROUTE      = _LEUART_ROUTE_RESETVALUE;
+#endif
 
   /* Unfreeze registers, pass new settings on to LEUART */
   LEUART_FreezeEnable(leuart, false);
@@ -545,7 +548,7 @@
   while (!(leuart->STATUS & LEUART_STATUS_RXDATAV))
     ;
 
-  return (uint8_t)(leuart->RXDATA);
+  return (uint8_t)leuart->RXDATA;
 }
 
 
@@ -571,7 +574,7 @@
   while (!(leuart->STATUS & LEUART_STATUS_RXDATAV))
     ;
 
-  return (uint16_t)(leuart->RXDATAX);
+  return (uint16_t)leuart->RXDATAX;
 }
 
 
@@ -628,7 +631,7 @@
  * @param[in] data
  *   Data to transmit with extended control. Least significant bits contains
  *   frame bits, and additional control bits are available as documented in
- *   the EFM32 reference manual (set to 0 if not used).
+ *   the reference manual (set to 0 if not used).
  ******************************************************************************/
 void LEUART_TxExt(LEUART_TypeDef *leuart, uint16_t data)
 {

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_mpu.c	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_mpu.c	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /***************************************************************************//**
  * @file em_mpu.c
  * @brief Memory Protection Unit (MPU) Peripheral API
- * @version 3.20.12
+ * @version 4.2.1
  *******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
  *******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,7 +30,6 @@
  *
  ******************************************************************************/
 
-
 #include "em_mpu.h"
 #if defined(__MPU_PRESENT) && (__MPU_PRESENT == 1)
 #include "em_assert.h"
@@ -102,15 +101,15 @@
     EFM_ASSERT(init->tex <= 0x7);
 
     MPU->RBAR = init->baseAddress;
-    MPU->RASR = ((init->disableExec ? 1 : 0) << MPU_RASR_XN_Pos)   |
-                (init->accessPermission      << MPU_RASR_AP_Pos)   |
-                (init->tex                   << MPU_RASR_TEX_Pos)  |
-                ((init->shareable   ? 1 : 0) << MPU_RASR_S_Pos)    |
-                ((init->cacheable   ? 1 : 0) << MPU_RASR_C_Pos)    |
-                ((init->bufferable  ? 1 : 0) << MPU_RASR_B_Pos)    |
-                (init->srd                   << MPU_RASR_SRD_Pos)  |
-                (init->size                  << MPU_RASR_SIZE_Pos) |
-                (1                           << MPU_RASR_ENABLE_Pos);
+    MPU->RASR = ((init->disableExec ? 1 : 0)   << MPU_RASR_XN_Pos)
+                | (init->accessPermission      << MPU_RASR_AP_Pos)
+                | (init->tex                   << MPU_RASR_TEX_Pos)
+                | ((init->shareable   ? 1 : 0) << MPU_RASR_S_Pos)
+                | ((init->cacheable   ? 1 : 0) << MPU_RASR_C_Pos)
+                | ((init->bufferable  ? 1 : 0) << MPU_RASR_B_Pos)
+                | (init->srd                   << MPU_RASR_SRD_Pos)
+                | (init->size                  << MPU_RASR_SIZE_Pos)
+                | (1                           << MPU_RASR_ENABLE_Pos);
   }
   else
   {

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_msc.c	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_msc.c	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /***************************************************************************//**
  * @file em_msc.c
  * @brief Flash controller (MSC) Peripheral API
- * @version 3.20.12
+ * @version 4.2.1
  *******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
  *******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -34,9 +34,9 @@
 #if defined( MSC_COUNT ) && ( MSC_COUNT > 0 )
 
 #include "em_system.h"
+#include "em_int.h"
 #if defined( _MSC_TIMEBASE_MASK )
 #include "em_cmu.h"
-#include "em_int.h"
 #endif
 #include "em_assert.h"
 
@@ -53,6 +53,20 @@
   mscWriteFast,
 } MSC_WriteStrategy_Typedef;
 
+MSC_FUNC_PREFIX static MSC_Status_TypeDef
+  MSC_WriteWordI(uint32_t *address,
+                 void const *data,
+                 uint32_t numBytes,
+                 MSC_WriteStrategy_Typedef writeStrategy) MSC_FUNC_POSTFIX;
+
+MSC_FUNC_PREFIX __STATIC_INLINE MSC_Status_TypeDef
+  MSC_LoadWriteData(uint32_t* data,
+                    uint32_t numWords,
+                    MSC_WriteStrategy_Typedef writeStrategy) MSC_FUNC_POSTFIX;
+
+MSC_FUNC_PREFIX __STATIC_INLINE MSC_Status_TypeDef
+  MSC_LoadVerifyAddress(uint32_t* address) MSC_FUNC_POSTFIX;
+
 /** @endcond */
 
 /***************************************************************************//**
@@ -76,6 +90,13 @@
  * @note
  *   IMPORTANT: This function must be called before flash operations when
  *   AUXHFRCO clock has been changed from default 14MHz band.
+ * @note
+ *   This function calls SystemCoreClockGet in order to set the global variable
+ *   SystemCoreClock which is used in subseqent calls of MSC_WriteWord to make
+ *   sure the frequency is sufficiently high for flash operations. If the clock
+ *   frequency is changed then software is responsible for calling MSC_Init or
+ *   SystemCoreClockGet in order to set the SystemCoreClock variable to the
+ *   correct value.
  ******************************************************************************/
 void MSC_Init(void)
 {
@@ -87,6 +108,13 @@
   /* Disable writing to the flash */
   MSC->WRITECTRL &= ~MSC_WRITECTRL_WREN;
 
+  /* Call SystemCoreClockGet in order to set the global variable SystemCoreClock
+     which is used in MSC_LoadWriteData to make sure the frequency is
+     sufficiently high. If the clock frequency is changed then software is
+     responsible for calling MSC_Init or SystemCoreClockGet in order to set the
+     SystemCoreClock variable to the correct value. */
+  SystemCoreClockGet();
+
 #if defined( _MSC_TIMEBASE_MASK )
   /* Configure MSC->TIMEBASE according to selected frequency */
   freq = CMU_ClockFreqGet(cmuClock_AUX);
@@ -98,10 +126,10 @@
     cycles = (freq / 1000000) + 1;
 
     /* Configure clock cycles for flash timing */
-    MSC->TIMEBASE = (MSC->TIMEBASE & ~(_MSC_TIMEBASE_BASE_MASK |
-                                       _MSC_TIMEBASE_PERIOD_MASK)) |
-                    MSC_TIMEBASE_PERIOD_1US |
-                    (cycles << _MSC_TIMEBASE_BASE_SHIFT);
+    MSC->TIMEBASE = (MSC->TIMEBASE & ~(_MSC_TIMEBASE_BASE_MASK
+                                       | _MSC_TIMEBASE_PERIOD_MASK))
+                    | MSC_TIMEBASE_PERIOD_1US
+                    | (cycles << _MSC_TIMEBASE_BASE_SHIFT);
   }
   else
   {
@@ -110,10 +138,10 @@
     cycles = (freq / 1000000) + 1;
 
     /* Configure clock cycles for flash timing */
-    MSC->TIMEBASE = (MSC->TIMEBASE & ~(_MSC_TIMEBASE_BASE_MASK |
-                                       _MSC_TIMEBASE_PERIOD_MASK)) |
-                    MSC_TIMEBASE_PERIOD_5US |
-                    (cycles << _MSC_TIMEBASE_BASE_SHIFT);
+    MSC->TIMEBASE = (MSC->TIMEBASE & ~(_MSC_TIMEBASE_BASE_MASK
+                                       | _MSC_TIMEBASE_PERIOD_MASK))
+                    | MSC_TIMEBASE_PERIOD_5US
+                    | (cycles << _MSC_TIMEBASE_BASE_SHIFT);
   }
 #endif
 }
@@ -130,6 +158,63 @@
   MSC->LOCK = 0;
 }
 
+
+#if !defined( _EFM32_GECKO_FAMILY )
+/***************************************************************************//**
+ * @brief
+ *   Set MSC code execution configuration
+ *
+ * @param[in] execConfig
+ *   Code execution configuration
+ ******************************************************************************/
+void MSC_ExecConfigSet(MSC_ExecConfig_TypeDef *execConfig)
+{
+  uint32_t mscReadCtrl;
+
+  mscReadCtrl = MSC->READCTRL & ~(0
+#if defined( MSC_READCTRL_SCBTP )
+                                  | MSC_READCTRL_SCBTP
+#endif
+#if defined( MSC_READCTRL_USEHPROT )
+                                  | MSC_READCTRL_USEHPROT
+#endif
+#if defined( MSC_READCTRL_PREFETCH )
+                                  | MSC_READCTRL_PREFETCH
+#endif
+#if defined( MSC_READCTRL_ICCDIS )
+                                  | MSC_READCTRL_ICCDIS
+#endif
+#if defined( MSC_READCTRL_AIDIS )
+                                  | MSC_READCTRL_AIDIS
+#endif
+#if defined( MSC_READCTRL_IFCDIS )
+                                  | MSC_READCTRL_IFCDIS
+#endif
+                                  );
+  mscReadCtrl |= (0
+#if defined( MSC_READCTRL_SCBTP )
+                 | (execConfig->scbtEn ? MSC_READCTRL_SCBTP : 0)
+#endif
+#if defined( MSC_READCTRL_USEHPROT )
+                 | (execConfig->useHprot ? MSC_READCTRL_USEHPROT : 0)
+#endif
+#if defined( MSC_READCTRL_PREFETCH )
+                 | (execConfig->prefetchEn ? MSC_READCTRL_PREFETCH : 0)
+#endif
+#if defined( MSC_READCTRL_ICCDIS )
+                 | (execConfig->iccDis ? MSC_READCTRL_ICCDIS : 0)
+#endif
+#if defined( MSC_READCTRL_AIDIS )
+                 | (execConfig->aiDis ? MSC_READCTRL_AIDIS : 0)
+#endif
+#if defined( MSC_READCTRL_IFCDIS )
+                 | (execConfig->ifcDis ? MSC_READCTRL_IFCDIS : 0)
+#endif
+                 );
+  MSC->READCTRL = mscReadCtrl;
+}
+#endif
+
 /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
 
 /***************************************************************************//**
@@ -149,10 +234,10 @@
  *   mscReturnLocked - Operation tried to erase a locked area of the flash.
  * @endverbatim
  ******************************************************************************/
-#ifdef __CC_ARM  /* MDK-ARM compiler */
+#if !defined(EM_MSC_RUN_FROM_FLASH)
+#if defined(__CC_ARM)  /* MDK-ARM compiler */
 #pragma arm section code="ram_code"
-#endif /* __CC_ARM */
-#ifdef __ICCARM__
+#elif defined(__ICCARM__)
 /* Suppress warnings originating from use of EFM_ASSERT():              */
 /* "Call to a non __ramfunc function from within a __ramfunc function"  */
 /* "Possible rom access from within a __ramfunc function"               */
@@ -160,6 +245,7 @@
 #pragma diag_suppress=Ta023
 __ramfunc
 #endif
+#endif /* !EM_MSC_RUN_FROM_FLASH */
 __STATIC_INLINE MSC_Status_TypeDef MSC_LoadVerifyAddress(uint32_t* address)
 {
   uint32_t status;
@@ -193,11 +279,10 @@
   }
   return mscReturnOk;
 }
-#ifdef __ICCARM__
+#if defined(__ICCARM__)
 #pragma diag_default=Ta022
 #pragma diag_default=Ta023
-#endif
-#ifdef __CC_ARM  /* MDK-ARM compiler */
+#elif defined(__CC_ARM)  /* MDK-ARM compiler */
 #pragma arm section code
 #endif /* __CC_ARM */
 
@@ -222,10 +307,10 @@
  *                      to complete.
  * @endverbatim
  ******************************************************************************/
-#ifdef __CC_ARM  /* MDK-ARM compiler */
+#if !defined(EM_MSC_RUN_FROM_FLASH)
+#if defined(__CC_ARM)  /* MDK-ARM compiler */
 #pragma arm section code="ram_code"
-#endif /* __CC_ARM */
-#ifdef __ICCARM__
+#elif defined(__ICCARM__)
 /* Suppress warnings originating from use of EFM_ASSERT():              */
 /* "Call to a non __ramfunc function from within a __ramfunc function"  */
 /* "Possible rom access from within a __ramfunc function"               */
@@ -233,16 +318,18 @@
 #pragma diag_suppress=Ta023
 __ramfunc
 #endif
-__STATIC_INLINE MSC_Status_TypeDef MSC_LoadWriteData(uint32_t* data,
-                                                     uint32_t numWords,
-                                                     MSC_WriteStrategy_Typedef writeStrategy)
+#endif /* !EM_MSC_RUN_FROM_FLASH */
+__STATIC_INLINE MSC_Status_TypeDef
+  MSC_LoadWriteData(uint32_t* data,
+                    uint32_t numWords,
+                    MSC_WriteStrategy_Typedef writeStrategy)
 {
   uint32_t timeOut;
   uint32_t wordIndex;
   uint32_t wordsPerDataPhase;
   MSC_Status_TypeDef retval = mscReturnOk;
 
-#if defined( _MSC_WRITECTRL_LPWRITE_MASK ) && defined( _MSC_WRITECTRL_WDOUBLE_MASK )
+#if defined(_MSC_WRITECTRL_LPWRITE_MASK) && defined(_MSC_WRITECTRL_WDOUBLE_MASK)
   /* If LPWRITE (Low Power Write) is NOT enabled, set WDOUBLE (Write Double word) */
   if (!(MSC->WRITECTRL & MSC_WRITECTRL_LPWRITE))
   {
@@ -360,13 +447,17 @@
              If WDATAREADY became high since entry into this loop, exit and continue
              to the next WDATA write.
           */
-          if ((MSC->STATUS & (MSC_STATUS_WORDTIMEOUT | MSC_STATUS_BUSY | MSC_STATUS_WDATAREADY)) == MSC_STATUS_WORDTIMEOUT)
+          if ((MSC->STATUS & (MSC_STATUS_WORDTIMEOUT
+                              | MSC_STATUS_BUSY
+                              | MSC_STATUS_WDATAREADY))
+              == MSC_STATUS_WORDTIMEOUT)
           {
             MSC->WRITECMD = MSC_WRITECMD_WRITETRIG;
           }
         }
         MSC->WDATA = *data;
-        if ((wordsPerDataPhase == 1) || ((wordsPerDataPhase == 2) && (wordIndex & 0x1)))
+        if ((wordsPerDataPhase == 1)
+            || ((wordsPerDataPhase == 2) && (wordIndex & 0x1)))
         {
           MSC->WRITECMD = MSC_WRITECMD_WRITETRIG;
         }
@@ -397,11 +488,10 @@
 
   return retval;
 }
-#ifdef __ICCARM__
+#if defined(__ICCARM__)
 #pragma diag_default=Ta022
 #pragma diag_default=Ta023
-#endif
-#ifdef __CC_ARM  /* MDK-ARM compiler */
+#elif defined(__CC_ARM)  /* MDK-ARM compiler */
 #pragma arm section code
 #endif /* __CC_ARM */
 
@@ -420,16 +510,17 @@
  * @return
  *   Returns the status of the data load operation
  ******************************************************************************/
-#ifdef __CC_ARM  /* MDK-ARM compiler */
+#if !defined(EM_MSC_RUN_FROM_FLASH)
+#if defined(__CC_ARM)  /* MDK-ARM compiler */
 #pragma arm section code="ram_code"
-#endif /* __CC_ARM */
-#ifdef __ICCARM__
+#elif defined(__ICCARM__)
 /* Suppress warnings originating from use of EFM_ASSERT():              */
 /* "Call to a non __ramfunc function from within a __ramfunc function"  */
 /* "Possible rom access from within a __ramfunc function"               */
 #pragma diag_suppress=Ta022
 #pragma diag_suppress=Ta023
 #endif
+#endif /* !EM_MSC_RUN_FROM_FLASH */
 static MSC_Status_TypeDef MSC_WriteWordI(uint32_t *address,
                                          void const *data,
                                          uint32_t numBytes,
@@ -497,11 +588,10 @@
 
   return retval;
 }
-#ifdef __ICCARM__
+#if defined(__ICCARM__)
 #pragma diag_default=Ta022
 #pragma diag_default=Ta023
-#endif
-#ifdef __CC_ARM  /* MDK-ARM compiler */
+#elif defined(__CC_ARM)  /* MDK-ARM compiler */
 #pragma arm section code
 #endif /* __CC_ARM */
 
@@ -533,16 +623,17 @@
  *       to complete.
  * @endverbatim
  ******************************************************************************/
-#ifdef __CC_ARM  /* MDK-ARM compiler */
+#if !defined(EM_MSC_RUN_FROM_FLASH)
+#if defined(__CC_ARM)  /* MDK-ARM compiler */
 #pragma arm section code="ram_code"
-#endif /* __CC_ARM */
-#ifdef __ICCARM__
+#elif defined(__ICCARM__)
 /* Suppress warnings originating from use of EFM_ASSERT():              */
 /* "Call to a non __ramfunc function from within a __ramfunc function"  */
 /* "Possible rom access from within a __ramfunc function"               */
 #pragma diag_suppress=Ta022
 #pragma diag_suppress=Ta023
 #endif
+#endif /* !EM_MSC_RUN_FROM_FLASH */
 MSC_Status_TypeDef MSC_ErasePage(uint32_t *startAddress)
 {
   uint32_t timeOut = MSC_PROGRAM_TIMEOUT;
@@ -589,11 +680,10 @@
   MSC->WRITECTRL &= ~MSC_WRITECTRL_WREN;
   return mscReturnOk;
 }
-#ifdef __ICCARM__
+#if defined(__ICCARM__)
 #pragma diag_default=Ta022
 #pragma diag_default=Ta023
-#endif
-#ifdef __CC_ARM  /* MDK-ARM compiler */
+#elif defined(__CC_ARM)  /* MDK-ARM compiler */
 #pragma arm section code
 #endif /* __CC_ARM */
 
@@ -634,27 +724,27 @@
  *       the next word into the DWORD register.
  * @endverbatim
  ******************************************************************************/
-#ifdef __CC_ARM  /* MDK-ARM compiler */
+#if !defined(EM_MSC_RUN_FROM_FLASH)
+#if defined(__CC_ARM)  /* MDK-ARM compiler */
 #pragma arm section code="ram_code"
-#endif /* __CC_ARM */
-#ifdef __ICCARM__
+#elif defined(__ICCARM__)
 /* Suppress warnings originating from use of EFM_ASSERT():              */
 /* "Call to a non __ramfunc function from within a __ramfunc function"  */
 /* "Possible rom access from within a __ramfunc function"               */
 #pragma diag_suppress=Ta022
 #pragma diag_suppress=Ta023
 #endif
+#endif /* !EM_MSC_RUN_FROM_FLASH */
 MSC_Status_TypeDef MSC_WriteWord(uint32_t *address,
                                   void const *data,
                                   uint32_t numBytes)
 {
   return MSC_WriteWordI(address, data, numBytes, mscWriteIntSafe);
 }
-#ifdef __ICCARM__
+#if defined(__ICCARM__)
 #pragma diag_default=Ta022
 #pragma diag_default=Ta023
-#endif
-#ifdef __CC_ARM  /* MDK-ARM compiler */
+#elif defined(__CC_ARM)  /* MDK-ARM compiler */
 #pragma arm section code
 #endif /* __CC_ARM */
 
@@ -693,27 +783,27 @@
  *       the next word into the DWORD register.
  * @endverbatim
  ******************************************************************************/
-#ifdef __CC_ARM  /* MDK-ARM compiler */
+#if !defined(EM_MSC_RUN_FROM_FLASH)
+#if defined(__CC_ARM)  /* MDK-ARM compiler */
 #pragma arm section code="ram_code"
-#endif /* __CC_ARM */
-#ifdef __ICCARM__
+#elif defined(__ICCARM__)
 /* Suppress warnings originating from use of EFM_ASSERT():              */
 /* "Call to a non __ramfunc function from within a __ramfunc function"  */
 /* "Possible rom access from within a __ramfunc function"               */
 #pragma diag_suppress=Ta022
 #pragma diag_suppress=Ta023
 #endif
+#endif /* !EM_MSC_RUN_FROM_FLASH */
 MSC_Status_TypeDef MSC_WriteWordFast(uint32_t *address,
                                   void const *data,
                                   uint32_t numBytes)
 {
   return MSC_WriteWordI(address, data, numBytes, mscWriteFast);
 }
-#ifdef __ICCARM__
+#if defined(__ICCARM__)
 #pragma diag_default=Ta022
 #pragma diag_default=Ta023
-#endif
-#ifdef __CC_ARM  /* MDK-ARM compiler */
+#elif defined(__CC_ARM)  /* MDK-ARM compiler */
 #pragma arm section code
 #endif /* __CC_ARM */
 #endif
@@ -729,9 +819,11 @@
  *   lost. The lock bit, MLW will prevent this operation from executing and
  *   might prevent successful mass erase.
  ******************************************************************************/
-#ifdef __CC_ARM  /* MDK-ARM compiler */
+#if !defined(EM_MSC_RUN_FROM_FLASH)
+#if defined(__CC_ARM)  /* MDK-ARM compiler */
 #pragma arm section code="ram_code"
 #endif /* __CC_ARM */
+#endif /* !EM_MSC_RUN_FROM_FLASH */
 MSC_Status_TypeDef MSC_MassErase(void)
 {
   /* Enable writing to the MSC */
@@ -746,7 +838,7 @@
   /* Waiting for erase to complete */
   while ((MSC->STATUS & MSC_STATUS_BUSY));
 
-#if (FLASH_SIZE >= (512 * 1024))
+#if ((FLASH_SIZE >= (512 * 1024)) && defined( _MSC_WRITECMD_ERASEMAIN1_MASK ))
   /* Erase second 512K block */
   MSC->WRITECMD = MSC_WRITECMD_ERASEMAIN1;
 
@@ -760,7 +852,7 @@
   /* This will only successfully return if calling function is also in SRAM */
   return mscReturnOk;
 }
-#ifdef __CC_ARM  /* MDK-ARM compiler */
+#if defined(__CC_ARM)  /* MDK-ARM compiler */
 #pragma arm section code
 #endif /* __CC_ARM */
 #endif

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_opamp.c	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_opamp.c	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /**************************************************************************//**
  * @file em_opamp.c
  * @brief Operational Amplifier (OPAMP) peripheral API
- * @version 3.20.12
+ * @version 4.2.1
  ******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
  *******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,13 +30,11 @@
  *
  ******************************************************************************/
 
-
-#include "em_device.h"
-#if defined( OPAMP_PRESENT ) && ( OPAMP_COUNT == 1 )
+#include "em_opamp.h"
+#if defined(OPAMP_PRESENT) && (OPAMP_COUNT == 1)
 
 #include "em_system.h"
 #include "em_assert.h"
-#include "em_opamp.h"
 
 /***************************************************************************//**
  * @addtogroup EM_Library
@@ -204,17 +202,17 @@
  * @param[in] opa
  *   Selects an OPA, valid vaules are @ref OPA0, @ref OPA1 and @ref OPA2.
  ******************************************************************************/
-void OPAMP_Disable( DAC_TypeDef *dac, OPAMP_TypeDef opa )
+void OPAMP_Disable(DAC_TypeDef *dac, OPAMP_TypeDef opa)
 {
-  EFM_ASSERT( DAC_REF_VALID( dac ) );
-  EFM_ASSERT( DAC_OPA_VALID( opa ) );
+  EFM_ASSERT(DAC_REF_VALID(dac));
+  EFM_ASSERT(DAC_OPA_VALID(opa));
 
-  if ( opa == OPA0 )
+  if (opa == OPA0)
   {
     dac->CH0CTRL &= ~DAC_CH0CTRL_EN;
     dac->OPACTRL &= ~DAC_OPACTRL_OPA0EN;
   }
-  else if ( opa == OPA1 )
+  else if (opa == OPA1)
   {
     dac->CH1CTRL &= ~DAC_CH1CTRL_EN;
     dac->OPACTRL &= ~DAC_OPACTRL_OPA1EN;
@@ -265,163 +263,163 @@
  * @param[in] init
  *   Pointer to a structure containing OPAMP init information.
  ******************************************************************************/
-void OPAMP_Enable( DAC_TypeDef *dac, OPAMP_TypeDef opa, const OPAMP_Init_TypeDef *init )
+void OPAMP_Enable(DAC_TypeDef *dac, OPAMP_TypeDef opa, const OPAMP_Init_TypeDef *init)
 {
   uint32_t offset;
 
-  EFM_ASSERT( DAC_REF_VALID( dac ) );
-  EFM_ASSERT( DAC_OPA_VALID( opa ) );
-  EFM_ASSERT( init->bias <= ( _DAC_BIASPROG_BIASPROG_MASK  >>
-                              _DAC_BIASPROG_BIASPROG_SHIFT    ) );
+  EFM_ASSERT(DAC_REF_VALID(dac));
+  EFM_ASSERT(DAC_OPA_VALID(opa));
+  EFM_ASSERT(init->bias <= (_DAC_BIASPROG_BIASPROG_MASK
+                             >> _DAC_BIASPROG_BIASPROG_SHIFT));
 
-  if ( opa == OPA0 )
+  if (opa == OPA0)
   {
-    EFM_ASSERT( ( init->outPen & ~_DAC_OPA0MUX_OUTPEN_MASK ) == 0 );
+    EFM_ASSERT((init->outPen & ~_DAC_OPA0MUX_OUTPEN_MASK) == 0);
 
-    dac->BIASPROG = ( dac->BIASPROG
-                      & ~( _DAC_BIASPROG_BIASPROG_MASK             |
-                            DAC_BIASPROG_HALFBIAS                    )  ) |
-                    ( init->bias      << _DAC_BIASPROG_BIASPROG_SHIFT   ) |
-                    ( init->halfBias   ? DAC_BIASPROG_HALFBIAS      : 0 );
+    dac->BIASPROG = (dac->BIASPROG
+                     & ~(_DAC_BIASPROG_BIASPROG_MASK
+                         | DAC_BIASPROG_HALFBIAS))
+                    | (init->bias     << _DAC_BIASPROG_BIASPROG_SHIFT)
+                    | (init->halfBias ?   DAC_BIASPROG_HALFBIAS : 0);
 
-    if ( init->defaultOffset )
+    if (init->defaultOffset)
     {
-      offset = SYSTEM_GetCalibrationValue( &dac->CAL );
-      dac->CAL = ( dac->CAL & ~_DAC_CAL_CH0OFFSET_MASK ) |
-                 ( offset   &  _DAC_CAL_CH0OFFSET_MASK );
+      offset = SYSTEM_GetCalibrationValue(&dac->CAL);
+      dac->CAL = (dac->CAL & ~_DAC_CAL_CH0OFFSET_MASK)
+                 | (offset &  _DAC_CAL_CH0OFFSET_MASK);
     }
     else
     {
-      EFM_ASSERT( init->offset <= ( _DAC_CAL_CH0OFFSET_MASK >>
-                                    _DAC_CAL_CH0OFFSET_SHIFT   ) );
+      EFM_ASSERT(init->offset <= (_DAC_CAL_CH0OFFSET_MASK
+                                  >> _DAC_CAL_CH0OFFSET_SHIFT));
 
-      dac->CAL = ( dac->CAL      & ~_DAC_CAL_CH0OFFSET_MASK  ) |
-                 ( init->offset <<  _DAC_CAL_CH0OFFSET_SHIFT );
+      dac->CAL = (dac->CAL & ~_DAC_CAL_CH0OFFSET_MASK)
+                 | (init->offset << _DAC_CAL_CH0OFFSET_SHIFT);
     }
 
-    dac->OPA0MUX  = (uint32_t)init->resSel                                |
-                    (uint32_t)init->outMode                               |
-                    init->outPen                                          |
-                    (uint32_t)init->resInMux                              |
-                    (uint32_t)init->negSel                                |
-                    (uint32_t)init->posSel                                |
-                    ( init->nextOut     ? DAC_OPA0MUX_NEXTOUT       : 0 ) |
-                    ( init->npEn        ? DAC_OPA0MUX_NPEN          : 0 ) |
-                    ( init->ppEn        ? DAC_OPA0MUX_PPEN          : 0 );
+    dac->OPA0MUX  = (uint32_t)init->resSel
+                    | (uint32_t)init->outMode
+                    | init->outPen
+                    | (uint32_t)init->resInMux
+                    | (uint32_t)init->negSel
+                    | (uint32_t)init->posSel
+                    | ( init->nextOut ? DAC_OPA0MUX_NEXTOUT : 0)
+                    | ( init->npEn    ? DAC_OPA0MUX_NPEN    : 0)
+                    | ( init->ppEn    ? DAC_OPA0MUX_PPEN    : 0);
 
     dac->CH0CTRL |= DAC_CH0CTRL_EN;
-    dac->OPACTRL  = ( dac->OPACTRL
-                      & ~(  DAC_OPACTRL_OPA0SHORT                  |
-                           _DAC_OPACTRL_OPA0LPFDIS_MASK            |
-                            DAC_OPACTRL_OPA0HCMDIS                   )  ) |
-                    ( init->shortInputs ?  DAC_OPACTRL_OPA0SHORT    : 0 ) |
-                    ( init->lpfPosPadDisable ?
-                                     DAC_OPACTRL_OPA0LPFDIS_PLPFDIS : 0 ) |
-                    ( init->lpfNegPadDisable ?
-                                     DAC_OPACTRL_OPA0LPFDIS_NLPFDIS : 0 ) |
-                    ( init->hcmDisable  ?  DAC_OPACTRL_OPA0HCMDIS   : 0 ) |
-                    ( DAC_OPACTRL_OPA0EN                                );
+    dac->OPACTRL  = (dac->OPACTRL
+                     & ~(DAC_OPACTRL_OPA0SHORT
+                         | _DAC_OPACTRL_OPA0LPFDIS_MASK
+                         |  DAC_OPACTRL_OPA0HCMDIS))
+                    | (init->shortInputs ?  DAC_OPACTRL_OPA0SHORT : 0)
+                    | (init->lpfPosPadDisable
+                       ? DAC_OPACTRL_OPA0LPFDIS_PLPFDIS : 0)
+                    | (init->lpfNegPadDisable
+                       ? DAC_OPACTRL_OPA0LPFDIS_NLPFDIS : 0)
+                    | (init->hcmDisable ? DAC_OPACTRL_OPA0HCMDIS : 0)
+                    | DAC_OPACTRL_OPA0EN;
   }
   else if ( opa == OPA1 )
   {
-    EFM_ASSERT( ( init->outPen & ~_DAC_OPA1MUX_OUTPEN_MASK ) == 0 );
+    EFM_ASSERT((init->outPen & ~_DAC_OPA1MUX_OUTPEN_MASK) == 0);
 
-    dac->BIASPROG = ( dac->BIASPROG
-                      & ~( _DAC_BIASPROG_BIASPROG_MASK             |
-                            DAC_BIASPROG_HALFBIAS                    )  ) |
-                    ( init->bias      << _DAC_BIASPROG_BIASPROG_SHIFT   ) |
-                    ( init->halfBias   ? DAC_BIASPROG_HALFBIAS      : 0 );
+    dac->BIASPROG = (dac->BIASPROG
+                     & ~(_DAC_BIASPROG_BIASPROG_MASK
+                         | DAC_BIASPROG_HALFBIAS))
+                    | (init->bias   << _DAC_BIASPROG_BIASPROG_SHIFT)
+                    | (init->halfBias ? DAC_BIASPROG_HALFBIAS : 0 );
 
-    if ( init->defaultOffset )
+    if (init->defaultOffset)
     {
-      offset = SYSTEM_GetCalibrationValue( &dac->CAL );
-      dac->CAL = ( dac->CAL & ~_DAC_CAL_CH1OFFSET_MASK ) |
-                 ( offset   &  _DAC_CAL_CH1OFFSET_MASK );
+      offset = SYSTEM_GetCalibrationValue(&dac->CAL);
+      dac->CAL = (dac->CAL & ~_DAC_CAL_CH1OFFSET_MASK)
+                 | (offset &  _DAC_CAL_CH1OFFSET_MASK);
     }
     else
     {
-      EFM_ASSERT( init->offset <= ( _DAC_CAL_CH1OFFSET_MASK >>
-                                    _DAC_CAL_CH1OFFSET_SHIFT   ) );
+      EFM_ASSERT(init->offset <= (_DAC_CAL_CH1OFFSET_MASK
+                                  >> _DAC_CAL_CH1OFFSET_SHIFT));
 
-      dac->CAL = ( dac->CAL      & ~_DAC_CAL_CH1OFFSET_MASK  ) |
-                 ( init->offset <<  _DAC_CAL_CH1OFFSET_SHIFT );
+      dac->CAL = (dac->CAL & ~_DAC_CAL_CH1OFFSET_MASK)
+                 | (init->offset << _DAC_CAL_CH1OFFSET_SHIFT);
     }
 
-    dac->OPA1MUX  = (uint32_t)init->resSel                                |
-                    (uint32_t)init->outMode                               |
-                    init->outPen                                          |
-                    (uint32_t)init->resInMux                              |
-                    (uint32_t)init->negSel                                |
-                    (uint32_t)init->posSel                                |
-                    ( init->nextOut     ? DAC_OPA1MUX_NEXTOUT       : 0 ) |
-                    ( init->npEn        ? DAC_OPA1MUX_NPEN          : 0 ) |
-                    ( init->ppEn        ? DAC_OPA1MUX_PPEN          : 0 );
+    dac->OPA1MUX  = (uint32_t)init->resSel
+                    | (uint32_t)init->outMode
+                    | init->outPen
+                    | (uint32_t)init->resInMux
+                    | (uint32_t)init->negSel
+                    | (uint32_t)init->posSel
+                    | (init->nextOut ? DAC_OPA1MUX_NEXTOUT : 0)
+                    | (init->npEn    ? DAC_OPA1MUX_NPEN    : 0)
+                    | (init->ppEn    ? DAC_OPA1MUX_PPEN    : 0);
 
     dac->CH1CTRL |= DAC_CH1CTRL_EN;
-    dac->OPACTRL  = ( dac->OPACTRL
-                      & ~(  DAC_OPACTRL_OPA1SHORT                  |
-                           _DAC_OPACTRL_OPA1LPFDIS_MASK            |
-                             DAC_OPACTRL_OPA1HCMDIS                  )  ) |
-                    ( init->shortInputs ?  DAC_OPACTRL_OPA1SHORT    : 0 ) |
-                    ( init->lpfPosPadDisable ?
-                                     DAC_OPACTRL_OPA1LPFDIS_PLPFDIS : 0 ) |
-                    ( init->lpfNegPadDisable ?
-                                     DAC_OPACTRL_OPA1LPFDIS_NLPFDIS : 0 ) |
-                    ( init->hcmDisable  ?  DAC_OPACTRL_OPA1HCMDIS   : 0 ) |
-                    ( DAC_OPACTRL_OPA1EN                                );
+    dac->OPACTRL  = (dac->OPACTRL
+                     & ~(DAC_OPACTRL_OPA1SHORT
+                         | _DAC_OPACTRL_OPA1LPFDIS_MASK
+                         | DAC_OPACTRL_OPA1HCMDIS))
+                    | (init->shortInputs ? DAC_OPACTRL_OPA1SHORT : 0)
+                    | (init->lpfPosPadDisable
+                       ? DAC_OPACTRL_OPA1LPFDIS_PLPFDIS : 0)
+                    | (init->lpfNegPadDisable
+                       ? DAC_OPACTRL_OPA1LPFDIS_NLPFDIS : 0)
+                    | (init->hcmDisable ? DAC_OPACTRL_OPA1HCMDIS : 0)
+                    | DAC_OPACTRL_OPA1EN;
   }
   else /* OPA2 */
   {
-    EFM_ASSERT( ( init->posSel == DAC_OPA2MUX_POSSEL_DISABLE ) ||
-                ( init->posSel == DAC_OPA2MUX_POSSEL_POSPAD  ) ||
-                ( init->posSel == DAC_OPA2MUX_POSSEL_OPA1INP ) ||
-                ( init->posSel == DAC_OPA2MUX_POSSEL_OPATAP  )    );
+    EFM_ASSERT((init->posSel == DAC_OPA2MUX_POSSEL_DISABLE)
+               || (init->posSel == DAC_OPA2MUX_POSSEL_POSPAD)
+               || (init->posSel == DAC_OPA2MUX_POSSEL_OPA1INP)
+               || (init->posSel == DAC_OPA2MUX_POSSEL_OPATAP));
 
-    EFM_ASSERT( ( init->outMode & ~DAC_OPA2MUX_OUTMODE ) == 0 );
+    EFM_ASSERT((init->outMode & ~DAC_OPA2MUX_OUTMODE) == 0);
 
-    EFM_ASSERT( ( init->outPen & ~_DAC_OPA2MUX_OUTPEN_MASK ) == 0 );
+    EFM_ASSERT((init->outPen & ~_DAC_OPA2MUX_OUTPEN_MASK) == 0);
 
-    dac->BIASPROG = ( dac->BIASPROG
-                      & ~( _DAC_BIASPROG_OPA2BIASPROG_MASK         |
-                            DAC_BIASPROG_OPA2HALFBIAS                )  ) |
-                    ( init->bias   << _DAC_BIASPROG_OPA2BIASPROG_SHIFT  ) |
-                    ( init->halfBias   ? DAC_BIASPROG_OPA2HALFBIAS  : 0 );
+    dac->BIASPROG = (dac->BIASPROG
+                     & ~(_DAC_BIASPROG_OPA2BIASPROG_MASK
+                         | DAC_BIASPROG_OPA2HALFBIAS))
+                    | (init->bias << _DAC_BIASPROG_OPA2BIASPROG_SHIFT)
+                    | (init->halfBias ? DAC_BIASPROG_OPA2HALFBIAS : 0);
 
-    if ( init->defaultOffset )
+    if (init->defaultOffset)
     {
-      offset = SYSTEM_GetCalibrationValue( &dac->OPAOFFSET );
-      dac->OPAOFFSET = ( dac->OPAOFFSET & ~_DAC_OPAOFFSET_OPA2OFFSET_MASK ) |
-                       ( offset         &  _DAC_OPAOFFSET_OPA2OFFSET_MASK );
+      offset = SYSTEM_GetCalibrationValue(&dac->OPAOFFSET);
+      dac->OPAOFFSET = (dac->OPAOFFSET & ~_DAC_OPAOFFSET_OPA2OFFSET_MASK)
+                       | (offset       &  _DAC_OPAOFFSET_OPA2OFFSET_MASK);
     }
     else
     {
-      EFM_ASSERT( init->offset <= ( _DAC_OPAOFFSET_OPA2OFFSET_MASK >>
-                                    _DAC_OPAOFFSET_OPA2OFFSET_SHIFT   ) );
-      dac->OPAOFFSET = ( dac->OPAOFFSET & ~_DAC_OPAOFFSET_OPA2OFFSET_MASK ) |
-                       ( init->offset <<  _DAC_OPAOFFSET_OPA2OFFSET_SHIFT );
+      EFM_ASSERT(init->offset <= (_DAC_OPAOFFSET_OPA2OFFSET_MASK
+                                  >> _DAC_OPAOFFSET_OPA2OFFSET_SHIFT));
+      dac->OPAOFFSET = (dac->OPAOFFSET & ~_DAC_OPAOFFSET_OPA2OFFSET_MASK)
+                       | (init->offset << _DAC_OPAOFFSET_OPA2OFFSET_SHIFT);
     }
 
-    dac->OPA2MUX  = (uint32_t)init->resSel                                |
-                    (uint32_t)init->outMode                               |
-                    init->outPen                                          |
-                    (uint32_t)init->resInMux                              |
-                    (uint32_t)init->negSel                                |
-                    (uint32_t)init->posSel                                |
-                    ( init->nextOut     ? DAC_OPA2MUX_NEXTOUT       : 0 ) |
-                    ( init->npEn        ? DAC_OPA2MUX_NPEN          : 0 ) |
-                    ( init->ppEn        ? DAC_OPA2MUX_PPEN          : 0 );
+    dac->OPA2MUX  = (uint32_t)init->resSel
+                    | (uint32_t)init->outMode
+                    | init->outPen
+                    | (uint32_t)init->resInMux
+                    | (uint32_t)init->negSel
+                    | (uint32_t)init->posSel
+                    | ( init->nextOut ? DAC_OPA2MUX_NEXTOUT : 0 )
+                    | ( init->npEn    ? DAC_OPA2MUX_NPEN    : 0 )
+                    | ( init->ppEn    ? DAC_OPA2MUX_PPEN    : 0 );
 
-    dac->OPACTRL  = ( dac->OPACTRL
-                      & ~(  DAC_OPACTRL_OPA2SHORT                  |
-                           _DAC_OPACTRL_OPA2LPFDIS_MASK            |
-                            DAC_OPACTRL_OPA2HCMDIS                   )  ) |
-                    ( init->shortInputs ?  DAC_OPACTRL_OPA2SHORT    : 0 ) |
-                    ( init->lpfPosPadDisable ?
-                                     DAC_OPACTRL_OPA2LPFDIS_PLPFDIS : 0 ) |
-                    ( init->lpfNegPadDisable ?
-                                     DAC_OPACTRL_OPA2LPFDIS_NLPFDIS : 0 ) |
-                    ( init->hcmDisable  ?  DAC_OPACTRL_OPA2HCMDIS   : 0 ) |
-                    ( DAC_OPACTRL_OPA2EN                                );
+    dac->OPACTRL  = (dac->OPACTRL
+                     & ~(DAC_OPACTRL_OPA2SHORT
+                         | _DAC_OPACTRL_OPA2LPFDIS_MASK
+                         | DAC_OPACTRL_OPA2HCMDIS))
+                    | (init->shortInputs ?  DAC_OPACTRL_OPA2SHORT : 0)
+                    | (init->lpfPosPadDisable
+                       ? DAC_OPACTRL_OPA2LPFDIS_PLPFDIS : 0)
+                    | (init->lpfNegPadDisable
+                       ? DAC_OPACTRL_OPA2LPFDIS_NLPFDIS : 0)
+                    | (init->hcmDisable ? DAC_OPACTRL_OPA2HCMDIS : 0)
+                    | DAC_OPACTRL_OPA2EN;
   }
 }
 

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_pcnt.c	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_pcnt.c	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /***************************************************************************//**
  * @file em_pcnt.c
  * @brief Pulse Counter (PCNT) peripheral API
- * @version 3.20.12
+ * @version 4.2.1
  *******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
  *******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,13 +30,12 @@
  *
  ******************************************************************************/
 
-
 #include "em_pcnt.h"
 #if defined(PCNT_COUNT) && (PCNT_COUNT > 0)
 
 #include "em_cmu.h"
 #include "em_assert.h"
-#include "em_bitband.h"
+#include "em_bus.h"
 
 /***************************************************************************//**
  * @addtogroup EM_Library
@@ -65,7 +64,7 @@
 #define PCNT_REF_VALID(ref)    (((ref) == PCNT0) || ((ref) == PCNT1) || \
                                 ((ref) == PCNT2))
 #else
-#error Undefined number of pulse counters (PCNT).
+#error "Undefined number of pulse counters (PCNT)."
 #endif
 
 /** @endcond */
@@ -89,7 +88,7 @@
  ******************************************************************************/
 __STATIC_INLINE unsigned int PCNT_Map(PCNT_TypeDef *pcnt)
 {
-  return(((uint32_t)pcnt - PCNT0_BASE) / 0x400);
+  return ((uint32_t)pcnt - PCNT0_BASE) / 0x400;
 }
 
 
@@ -144,10 +143,10 @@
   EFM_ASSERT(PCNT_REF_VALID(pcnt));
 
   /* Enable reset of CNT and TOP register */
-  BITBAND_Peripheral(&(pcnt->CTRL), _PCNT_CTRL_RSTEN_SHIFT, 1);
+  BUS_RegBitWrite(&(pcnt->CTRL), _PCNT_CTRL_RSTEN_SHIFT, 1);
 
   /* Disable reset of CNT and TOP register */
-  BITBAND_Peripheral(&(pcnt->CTRL), _PCNT_CTRL_RSTEN_SHIFT, 0);
+  BUS_RegBitWrite(&(pcnt->CTRL), _PCNT_CTRL_RSTEN_SHIFT, 0);
 }
 
 
@@ -292,7 +291,7 @@
   pcnt->CTRL = tmp;
 }
 
-#if defined( _PCNT_INPUT_MASK )
+#if defined(_PCNT_INPUT_MASK)
 /***************************************************************************//**
  * @brief
  *   Enable/disable the selected PRS input of PCNT.
@@ -318,26 +317,20 @@
   /* Enable/disable the selected PRS input on the selected PCNT module. */
   switch (prsInput)
   {
-  /* Enable/disable PRS input S0. */
-  case pcntPRSInputS0:
-  {
-    BITBAND_Peripheral(&(pcnt->INPUT), _PCNT_INPUT_S0PRSEN_SHIFT, (uint32_t)enable);
-  }
-  break;
+    /* Enable/disable PRS input S0. */
+    case pcntPRSInputS0:
+      BUS_RegBitWrite(&(pcnt->INPUT), _PCNT_INPUT_S0PRSEN_SHIFT, enable);
+      break;
 
-  /* Enable/disable PRS input S1. */
-  case pcntPRSInputS1:
-  {
-    BITBAND_Peripheral(&(pcnt->INPUT), _PCNT_INPUT_S1PRSEN_SHIFT, (uint32_t)enable);
-  }
-  break;
+    /* Enable/disable PRS input S1. */
+    case pcntPRSInputS1:
+      BUS_RegBitWrite(&(pcnt->INPUT), _PCNT_INPUT_S1PRSEN_SHIFT, enable);
+      break;
 
-  /* Invalid parameter, asserted. */
-  default:
-  {
-    EFM_ASSERT(0);
-  }
-  break;
+    /* Invalid parameter, asserted. */
+    default:
+      EFM_ASSERT(0);
+    break;
   }
 }
 #endif
@@ -448,7 +441,7 @@
     EFM_ASSERT((1<<PCNT0_CNT_SIZE) > init->top);
   }
 #endif
-  
+
 #ifdef PCNT1
   if (PCNT1 == pcnt)
   {
@@ -456,7 +449,7 @@
     EFM_ASSERT((1<<PCNT1_CNT_SIZE) > init->top);
   }
 #endif
-  
+
 #ifdef PCNT2
   if (PCNT2 == pcnt)
   {
@@ -464,11 +457,11 @@
     EFM_ASSERT((1<<PCNT2_CNT_SIZE) > init->top);
   }
 #endif
-  
+
   /* Map pointer to instance */
   inst = PCNT_Map(pcnt);
 
-#if defined( _PCNT_INPUT_MASK )
+#if defined(_PCNT_INPUT_MASK)
   /* Selecting the PRS channels for the PRS input sources of the PCNT. These are
    * written with a Read-Modify-Write sequence in order to keep the value of the
    * input enable bits which can be modified using PCNT_PRSInputEnable(). */
@@ -495,14 +488,14 @@
     tmp |= PCNT_CTRL_FILT;
   }
 
-#if defined( PCNT_CTRL_HYST )
+#if defined(PCNT_CTRL_HYST)
   if (init->hyst)
   {
     tmp |= PCNT_CTRL_HYST;
   }
 #endif
 
-#if defined( PCNT_CTRL_S1CDIR )
+#if defined(PCNT_CTRL_S1CDIR)
   if (init->s1CntDir)
   {
     tmp |= PCNT_CTRL_S1CDIR;
@@ -510,11 +503,11 @@
 #endif
 
   /* Configure counter events for regular and auxiliary counter. */
-#if defined( _PCNT_CTRL_CNTEV_SHIFT )
+#if defined(_PCNT_CTRL_CNTEV_SHIFT)
   tmp |= init->cntEvent << _PCNT_CTRL_CNTEV_SHIFT;
 #endif
 
-#if defined( _PCNT_CTRL_AUXCNTEV_SHIFT )
+#if defined(_PCNT_CTRL_AUXCNTEV_SHIFT)
   {
     /* Modify the auxCntEvent value before writing to the AUXCNTEV field in
        the CTRL register because the AUXCNTEV field values are different from
@@ -524,19 +517,20 @@
     uint32_t auxCntEventField = 0; /* Get rid of compiler warning. */
     switch (init->auxCntEvent)
     {
-    case pcntCntEventBoth:
-      auxCntEventField = pcntCntEventNone;
-      break;
-    case pcntCntEventNone:
-      auxCntEventField = pcntCntEventBoth;
-      break;
-    case pcntCntEventUp:
-    case pcntCntEventDown:
-      auxCntEventField = init->auxCntEvent;
-      break;
-    default:
-      /* Invalid parameter, asserted. */
-      EFM_ASSERT(0);
+      case pcntCntEventBoth:
+        auxCntEventField = pcntCntEventNone;
+        break;
+      case pcntCntEventNone:
+        auxCntEventField = pcntCntEventBoth;
+        break;
+      case pcntCntEventUp:
+      case pcntCntEventDown:
+        auxCntEventField = init->auxCntEvent;
+        break;
+      default:
+        /* Invalid parameter, asserted. */
+        EFM_ASSERT(0);
+        break;
     }
     tmp |= auxCntEventField << _PCNT_CTRL_AUXCNTEV_SHIFT;
   }
@@ -544,7 +538,7 @@
 
   /* Reset pulse counter while changing clock source. The reset bit */
   /* is asynchronous, we don't have to check for SYNCBUSY. */
-  BITBAND_Peripheral(&(pcnt->CTRL), _PCNT_CTRL_RSTEN_SHIFT, 1);
+  BUS_RegBitWrite(&(pcnt->CTRL), _PCNT_CTRL_RSTEN_SHIFT, 1);
 
   /* Select LFACLK to clock in control setting */
   CMU_PCNTClockExternalSet(inst, false);
@@ -552,76 +546,76 @@
   /* Handling depends on whether using external clock or not. */
   switch (init->mode)
   {
-  case pcntModeExtSingle:
-  case pcntModeExtQuad:
-    tmp |= init->mode << _PCNT_CTRL_MODE_SHIFT;
+    case pcntModeExtSingle:
+    case pcntModeExtQuad:
+      tmp |= init->mode << _PCNT_CTRL_MODE_SHIFT;
 
-    /* In most cases, the SYNCBUSY bit is set due to reset bit set, and waiting
-     * for asynchronous reset bit is strictly not necessary.
-     * But in theory, other operations on CTRL register may have been done
-     * outside this function, so wait. */
-    PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL);
+      /* In most cases, the SYNCBUSY bit is set due to reset bit set, and waiting
+       * for asynchronous reset bit is strictly not necessary.
+       * But in theory, other operations on CTRL register may have been done
+       * outside this function, so wait. */
+      PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL);
 
-    /* Enable PCNT Clock Domain Reset. The PCNT must be in reset before changing
-     * the clock source to an external clock */
-    pcnt->CTRL = PCNT_CTRL_RSTEN;
+      /* Enable PCNT Clock Domain Reset. The PCNT must be in reset before changing
+       * the clock source to an external clock */
+      pcnt->CTRL = PCNT_CTRL_RSTEN;
 
-    /* Wait until CTRL write synchronized into LF domain. */
-    PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL);
+      /* Wait until CTRL write synchronized into LF domain. */
+      PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL);
 
-    /* Change to external clock BEFORE disabling reset */
-    CMU_PCNTClockExternalSet(inst, true);
+      /* Change to external clock BEFORE disabling reset */
+      CMU_PCNTClockExternalSet(inst, true);
 
-    /* Write to TOPB. If using external clock TOPB will sync to TOP at the same
-     * time as the mode. This will insure that if the user chooses to count
-     * down, the first "countable" pulse will make CNT go to TOP and not 0xFF
-     * (default TOP value). */
-    pcnt->TOPB = init->top;
+      /* Write to TOPB. If using external clock TOPB will sync to TOP at the same
+       * time as the mode. This will insure that if the user chooses to count
+       * down, the first "countable" pulse will make CNT go to TOP and not 0xFF
+       * (default TOP value). */
+      pcnt->TOPB = init->top;
 
-    /* This bit has no effect on rev. C and onwards parts - for compatibility */
-    pcnt->CMD = PCNT_CMD_LTOPBIM;
+      /* This bit has no effect on rev. C and onwards parts - for compatibility */
+      pcnt->CMD = PCNT_CMD_LTOPBIM;
 
-    /* Write the CTRL register with the configurations.
-     * This should be written after TOPB in the eventuality of a pulse between
-     * these two writes that would cause the CTRL register to be synced one
-     * clock cycle earlier than the TOPB. */
-    pcnt->CTRL = tmp;
+      /* Write the CTRL register with the configurations.
+       * This should be written after TOPB in the eventuality of a pulse between
+       * these two writes that would cause the CTRL register to be synced one
+       * clock cycle earlier than the TOPB. */
+      pcnt->CTRL = tmp;
 
-    /* There are no syncs for TOP, CMD or CTRL because the clock rate is unknown
-     * and the program could stall
-     * These will be synced within 3 clock cycles of the external clock  /
-     * For the same reason CNT cannot be written here. */
-    break;
+      /* There are no syncs for TOP, CMD or CTRL because the clock rate is unknown
+       * and the program could stall
+       * These will be synced within 3 clock cycles of the external clock  /
+       * For the same reason CNT cannot be written here. */
+      break;
 
-  /* pcntModeDisable */
-  /* pcntModeOvsSingle */
-  default:
-    /* No need to set disabled mode if already disabled. */
-    if ((pcnt->CTRL & _PCNT_CTRL_MODE_MASK) != PCNT_CTRL_MODE_DISABLE)
-    {
-      /* Set control to disabled mode, leave reset on until ensured disabled.
-       * We don't need to wait for CTRL SYNCBUSY completion here, it was
-       * triggered by reset bit above, which is asynchronous. */
-      pcnt->CTRL = tmp | PCNT_CTRL_MODE_DISABLE | PCNT_CTRL_RSTEN;
+    /* pcntModeDisable */
+    /* pcntModeOvsSingle */
+    default:
+      /* No need to set disabled mode if already disabled. */
+      if ((pcnt->CTRL & _PCNT_CTRL_MODE_MASK) != PCNT_CTRL_MODE_DISABLE)
+      {
+        /* Set control to disabled mode, leave reset on until ensured disabled.
+         * We don't need to wait for CTRL SYNCBUSY completion here, it was
+         * triggered by reset bit above, which is asynchronous. */
+        pcnt->CTRL = tmp | PCNT_CTRL_MODE_DISABLE | PCNT_CTRL_RSTEN;
 
-      /* Wait until CTRL write synchronized into LF domain before proceeding
-       * to disable reset. */
-      PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL);
-    }
+        /* Wait until CTRL write synchronized into LF domain before proceeding
+         * to disable reset. */
+        PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL);
+      }
 
-    /* Disable reset bit, counter should now be in disabled mode. */
-    BITBAND_Peripheral(&(pcnt->CTRL), _PCNT_CTRL_RSTEN_SHIFT, 0);
+      /* Disable reset bit, counter should now be in disabled mode. */
+      BUS_RegBitWrite(&(pcnt->CTRL), _PCNT_CTRL_RSTEN_SHIFT, 0);
 
-    /* Set counter and top values as specified. */
-    PCNT_CounterTopSet(pcnt, init->counter, init->top);
+      /* Set counter and top values as specified. */
+      PCNT_CounterTopSet(pcnt, init->counter, init->top);
 
-    /* Enter oversampling mode if selected. */
-    if (init->mode == pcntModeOvsSingle)
-    {
-      PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL);
-      pcnt->CTRL = tmp | (init->mode << _PCNT_CTRL_MODE_SHIFT);
-    }
-    break;
+      /* Enter oversampling mode if selected. */
+      if (init->mode == pcntModeOvsSingle)
+      {
+        PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL);
+        pcnt->CTRL = tmp | (init->mode << _PCNT_CTRL_MODE_SHIFT);
+      }
+      break;
   }
 }
 
@@ -658,7 +652,7 @@
    * modifying RSTEN. The SYNCBUSY bit will be set, leading to a
    * synchronization in the LF domain, with in reality no changes to LF domain.
    * Enable reset of CNT and TOP register. */
-  BITBAND_Peripheral(&(pcnt->CTRL), _PCNT_CTRL_RSTEN_SHIFT, 1);
+  BUS_RegBitWrite(&(pcnt->CTRL), _PCNT_CTRL_RSTEN_SHIFT, 1);
 
   /* Select LFACLK as default */
   CMU_PCNTClockExternalSet(inst, false);
@@ -670,7 +664,7 @@
 
   /* Disable reset after CTRL reg has been synchronized */
   PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL);
-  BITBAND_Peripheral(&(pcnt->CTRL), _PCNT_CTRL_RSTEN_SHIFT, 0);
+  BUS_RegBitWrite(&(pcnt->CTRL), _PCNT_CTRL_RSTEN_SHIFT, 0);
 
   /* Clear pending interrupts */
   pcnt->IFC = _PCNT_IFC_MASK;
@@ -678,6 +672,97 @@
   /* Do not reset route register, setting should be done independently */
 }
 
+#if defined(PCNT_OVSCFG_FILTLEN_DEFAULT)
+/***************************************************************************//**
+ * @brief
+ *   Set filter configuration.
+ *
+ * @details
+ *   This function will configure the PCNT input filter, when the PCNT mode is
+ *   configured to take an LFA-derived clock as input clock.
+ *
+ * @param[in] pcnt
+ *   Pointer to PCNT peripheral register block.
+ *
+ * @param[in] config
+ *   Pointer to configuration structure to be applied.
+ *
+ * @param[in] enable
+ *   Whether to enable or disable filtering
+ ******************************************************************************/
+void PCNT_FilterConfiguration(PCNT_TypeDef *pcnt, const PCNT_Filter_TypeDef *config, bool enable) {
+  uint32_t ovscfg = 0;
+  
+  EFM_ASSERT(PCNT_REF_VALID(pcnt));
+  
+  /* Construct new filter setting value */
+  ovscfg  = ((config->filtLen & _PCNT_OVSCFG_FILTLEN_MASK) << _PCNT_OVSCFG_FILTLEN_SHIFT)
+            | ((config->flutterrm & 0x1) << _PCNT_OVSCFG_FLUTTERRM_SHIFT);
+  
+  /* Set new configuration. LF register requires sync check before writing. */
+  PCNT_Sync(pcnt, PCNT_SYNCBUSY_OVSCFG);
+  pcnt->OVSCFG = ovscfg;
+
+  
+  /* Set new state of filter. LF register requires sync check before writing. */
+  PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL);
+  if(enable) 
+  {
+    pcnt->CTRL |= PCNT_CTRL_FILT;
+  } 
+  else 
+  {
+    pcnt->CTRL &= ~PCNT_CTRL_FILT;
+  }
+}
+#endif
+
+#if defined(PCNT_CTRL_TCCMODE_DEFAULT)
+/***************************************************************************//**
+ * @brief
+ *   Set Triggered Compare and Clear configuration.
+ *
+ * @details
+ *   This function will configure the PCNT TCC (Triggered Compare and Clear)
+ *   module. This module can, upon a configurable trigger source, compare the
+ *   current counter value with the configured TOP value. Upon match, the counter
+ *   will be reset, and the TCC PRS output and TCC interrupt flag will be set.
+ *
+ *   Since there is a comparison with the TOP value, the counter will not stop
+ *   counting nor wrap when hitting the TOP value, but it will keep on counting
+ *   until its maximum value. Then, it will not wrap, but instead stop counting
+ *   and set the overflow flag.
+ *
+ * @param[in] pcnt
+ *   Pointer to PCNT peripheral register block.
+ *
+ * @param[in] config
+ *   Pointer to configuration structure to be applied.
+ ******************************************************************************/
+void PCNT_TCCConfiguration(PCNT_TypeDef *pcnt, const PCNT_TCC_TypeDef *config){
+  uint32_t ctrl = 0;
+  uint32_t mask = _PCNT_CTRL_TCCMODE_MASK
+                  | _PCNT_CTRL_TCCPRESC_MASK
+                  | _PCNT_CTRL_TCCCOMP_MASK
+                  | _PCNT_CTRL_PRSGATEEN_MASK
+                  | _PCNT_CTRL_TCCPRSPOL_MASK
+                  | _PCNT_CTRL_TCCPRSSEL_MASK;
+  
+  EFM_ASSERT(PCNT_REF_VALID(pcnt));
+  
+  /* construct TCC part of configuration register */
+  ctrl |= (config->mode          << _PCNT_CTRL_TCCMODE_SHIFT   ) & _PCNT_CTRL_TCCMODE_MASK;
+  ctrl |= (config->prescaler     << _PCNT_CTRL_TCCPRESC_SHIFT  ) & _PCNT_CTRL_TCCPRESC_MASK;
+  ctrl |= (config->compare       << _PCNT_CTRL_TCCCOMP_SHIFT   ) & _PCNT_CTRL_TCCCOMP_MASK;
+  ctrl |= (config->tccPRS        << _PCNT_CTRL_TCCPRSSEL_SHIFT ) & _PCNT_CTRL_TCCPRSSEL_MASK;
+  ctrl |= (config->prsPolarity   << _PCNT_CTRL_TCCPRSPOL_SHIFT ) & _PCNT_CTRL_TCCPRSPOL_MASK;
+  ctrl |= (config->prsGateEnable << _PCNT_CTRL_PRSGATEEN_SHIFT ) & _PCNT_CTRL_PRSGATEEN_MASK;
+  
+  /* Load new TCC config to PCNT. LF register requires sync check before write. */
+  PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL);
+  pcnt->CTRL = (pcnt->CTRL & (~mask)) | ctrl;
+}
+#endif
 
 /***************************************************************************//**
  * @brief
@@ -757,7 +842,6 @@
   pcnt->CMD = PCNT_CMD_LTOPBIM;
 }
 
-
 /** @} (end addtogroup PCNT) */
 /** @} (end addtogroup EM_Library) */
 #endif /* defined(PCNT_COUNT) && (PCNT_COUNT > 0) */

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_prs.c	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_prs.c	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /***************************************************************************//**
  * @file em_prs.c
  * @brief Peripheral Reflex System (PRS) Peripheral API
- * @version 3.20.12
+ * @version 4.2.1
  *******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
  *******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,12 +30,10 @@
  *
  ******************************************************************************/
 
-
 #include "em_prs.h"
 #if defined(PRS_COUNT) && (PRS_COUNT > 0)
 
 #include "em_assert.h"
-#include "em_bitband.h"
 
 /***************************************************************************//**
  * @addtogroup EM_Library
@@ -76,9 +74,9 @@
 {
   EFM_ASSERT(ch < PRS_CHAN_COUNT);
 
-  PRS->CH[ch].CTRL = (source & _PRS_CH_CTRL_SOURCESEL_MASK) |
-                     (signal & _PRS_CH_CTRL_SIGSEL_MASK) |
-                     (uint32_t)edge;
+  PRS->CH[ch].CTRL = (source & _PRS_CH_CTRL_SOURCESEL_MASK)
+                     | (signal & _PRS_CH_CTRL_SIGSEL_MASK)
+                     | (uint32_t)edge;
 }
 
 #if defined( PRS_CH_CTRL_ASYNC )
@@ -95,12 +93,7 @@
  *   asynchronous signals and consumers.
  *
  * @note
- *   This function is supported on the following device families:
- *   @li Giant Gecko (EFM32GGxxxFxxx)
- *   @li Leopard Gecko (EFM32LGxxxFxxx)
- *   @li Tiny Gecko (EFM32TGxxxFxxx)
- *   @li Wonder Gecko (EFM32WGxxxFxxx)
- *   @li Zero Gecko (EFM32ZGxxxFxxx)
+ *   This function is not supported on EFM32GxxxFyyy parts.
  *   In asynchronous mode, the edge detector only works in EM0, hence it shall
  *   not be used. The EDSEL parameter in PRS_CHx_CTRL register is set to 0 (OFF)
  *   by default.
@@ -121,10 +114,10 @@
 {
   EFM_ASSERT(ch < PRS_CHAN_COUNT);
 
-  PRS->CH[ch].CTRL = PRS_CH_CTRL_ASYNC |
-                     (source & _PRS_CH_CTRL_SOURCESEL_MASK) |
-                     (signal & _PRS_CH_CTRL_SIGSEL_MASK) |
-                     PRS_CH_CTRL_EDSEL_OFF;
+  PRS->CH[ch].CTRL = PRS_CH_CTRL_ASYNC
+                     | (source & _PRS_CH_CTRL_SOURCESEL_MASK)
+                     | (signal & _PRS_CH_CTRL_SIGSEL_MASK)
+                     | PRS_CH_CTRL_EDSEL_OFF;
 }
 #endif
 

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_rmu.c	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_rmu.c	Fri Jan 15 07:45:16 2016 +0000
@@ -2,10 +2,10 @@
  * @file em_rmu.c
  * @brief Reset Management Unit (RMU) peripheral module peripheral API
  *
- * @version 3.20.12
+ * @version 4.2.1
  *******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
  *******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -31,12 +31,12 @@
  *
  ******************************************************************************/
 
-
 #include "em_rmu.h"
 #if defined(RMU_COUNT) && (RMU_COUNT > 0)
 
+#include "em_common.h"
 #include "em_emu.h"
-#include "em_bitband.h"
+#include "em_bus.h"
 
 /***************************************************************************//**
  * @addtogroup EM_Library
@@ -57,6 +57,7 @@
 
 /* Reset cause "don't care" definitions.
    1's mark the bits that must be zero, zeros are "don't cares". */
+#if (_RMU_RSTCAUSE_MASK == 0x0000007FUL)
 #define RMU_RSTCAUSE_PORST_XMASK         (0x00000000) /**0b0000000000000000  < Power On Reset */
 #define RMU_RSTCAUSE_BODUNREGRST_XMASK   (0x00000081) /**0b0000000010000001  < Brown Out Detector Unregulated Domain Reset */
 #define RMU_RSTCAUSE_BODREGRST_XMASK     (0x00000091) /**0b0000000010010001  < Brown Out Detector Regulated Domain Reset */
@@ -65,22 +66,54 @@
 #define RMU_RSTCAUSE_LOCKUPRST_XMASK     (0x0000EFDF) /**0b1110111111011111  < LOCKUP Reset */
 #define RMU_RSTCAUSE_SYSREQRST_XMASK     (0x0000EF9F) /**0b1110111110011111  < System Request Reset */
 #define NUM_RSTCAUSES                             (7)
-#ifndef _EFM32_GECKO_FAMILY
+
+#elif (_RMU_RSTCAUSE_MASK == 0x000007FFUL)
+#define RMU_RSTCAUSE_PORST_XMASK         (0x00000000) /**0b0000000000000000  < Power On Reset */
+#define RMU_RSTCAUSE_BODUNREGRST_XMASK   (0x00000081) /**0b0000000010000001  < Brown Out Detector Unregulated Domain Reset */
+#define RMU_RSTCAUSE_BODREGRST_XMASK     (0x00000091) /**0b0000000010010001  < Brown Out Detector Regulated Domain Reset */
+#define RMU_RSTCAUSE_EXTRST_XMASK        (0x00000001) /**0b0000000000000001  < External Pin Reset */
+#define RMU_RSTCAUSE_WDOGRST_XMASK       (0x00000003) /**0b0000000000000011  < Watchdog Reset */
+#define RMU_RSTCAUSE_LOCKUPRST_XMASK     (0x0000EFDF) /**0b1110111111011111  < LOCKUP Reset */
+#define RMU_RSTCAUSE_SYSREQRST_XMASK     (0x0000EF9F) /**0b1110111110011111  < System Request Reset */
 #define RMU_RSTCAUSE_EM4RST_XMASK        (0x00000719) /**0b0000011100011001  < EM4 Reset */
 #define RMU_RSTCAUSE_EM4WURST_XMASK      (0x00000619) /**0b0000011000011001  < EM4 Wake-up Reset */
 #define RMU_RSTCAUSE_BODAVDD0_XMASK      (0x0000041F) /**0b0000010000011111  < AVDD0 Bod Reset. */
 #define RMU_RSTCAUSE_BODAVDD1_XMASK      (0x0000021F) /**0b0000001000011111  < AVDD1 Bod Reset. */
-#undef NUM_RSTCAUSES
 #define NUM_RSTCAUSES                            (11)
-#endif
-#ifdef BU_PRESENT
+
+#elif (_RMU_RSTCAUSE_MASK == 0x0000FFFFUL)
+#define RMU_RSTCAUSE_PORST_XMASK         (0x00000000) /**0b0000000000000000  < Power On Reset */
+#define RMU_RSTCAUSE_BODUNREGRST_XMASK   (0x00000081) /**0b0000000010000001  < Brown Out Detector Unregulated Domain Reset */
+#define RMU_RSTCAUSE_BODREGRST_XMASK     (0x00000091) /**0b0000000010010001  < Brown Out Detector Regulated Domain Reset */
+#define RMU_RSTCAUSE_EXTRST_XMASK        (0x00000001) /**0b0000000000000001  < External Pin Reset */
+#define RMU_RSTCAUSE_WDOGRST_XMASK       (0x00000003) /**0b0000000000000011  < Watchdog Reset */
+#define RMU_RSTCAUSE_LOCKUPRST_XMASK     (0x0000EFDF) /**0b1110111111011111  < LOCKUP Reset */
+#define RMU_RSTCAUSE_SYSREQRST_XMASK     (0x0000EF9F) /**0b1110111110011111  < System Request Reset */
+#define RMU_RSTCAUSE_EM4RST_XMASK        (0x00000719) /**0b0000011100011001  < EM4 Reset */
+#define RMU_RSTCAUSE_EM4WURST_XMASK      (0x00000619) /**0b0000011000011001  < EM4 Wake-up Reset */
+#define RMU_RSTCAUSE_BODAVDD0_XMASK      (0x0000041F) /**0b0000010000011111  < AVDD0 Bod Reset */
+#define RMU_RSTCAUSE_BODAVDD1_XMASK      (0x0000021F) /**0b0000001000011111  < AVDD1 Bod Reset */
 #define RMU_RSTCAUSE_BUBODVDDDREG_XMASK  (0x00000001) /**0b0000000000000001  < Backup Brown Out Detector, VDD_DREG */
 #define RMU_RSTCAUSE_BUBODBUVIN_XMASK    (0x00000001) /**0b0000000000000001  < Backup Brown Out Detector, BU_VIN */
 #define RMU_RSTCAUSE_BUBODUNREG_XMASK    (0x00000001) /**0b0000000000000001  < Backup Brown Out Detector Unregulated Domain */
 #define RMU_RSTCAUSE_BUBODREG_XMASK      (0x00000001) /**0b0000000000000001  < Backup Brown Out Detector Regulated Domain */
 #define RMU_RSTCAUSE_BUMODERST_XMASK     (0x00000001) /**0b0000000000000001  < Backup mode reset */
-#undef NUM_RSTCAUSES
 #define NUM_RSTCAUSES                            (16)
+
+#elif ((_RMU_RSTCAUSE_MASK & 0x0FFFFFFF) == 0x00010F1DUL)
+#define RMU_RSTCAUSE_PORST_XMASK         (0x00000000) /**0b0000000000000000  < Power On Reset */
+#define RMU_RSTCAUSE_BODAVDD_XMASK       (0x00000001) /**0b0000000000000001  < AVDD Bod Reset */
+#define RMU_RSTCAUSE_BODDVDD_XMASK       (0x00000003) /**0b0000000000000011  < DVDD Bod Reset */
+#define RMU_RSTCAUSE_BODREGRST_XMASK     (0x0000000F) /**0b0000000000001111  < Brown Out Detector Regulated Domain Reset */
+#define RMU_RSTCAUSE_EXTRST_XMASK        (0x0000000F) /**0b0000000000001111  < External Pin Reset */
+#define RMU_RSTCAUSE_LOCKUPRST_XMASK     (0x0000001F) /**0b0000000000011111  < LOCKUP Reset */
+#define RMU_RSTCAUSE_SYSREQRST_XMASK     (0x0000001F) /**0b0000000000011111  < System Request Reset */
+#define RMU_RSTCAUSE_WDOGRST_XMASK       (0x0000001F) /**0b0000000000011111  < Watchdog Reset */
+#define RMU_RSTCAUSE_EM4RST_XMASK        (0x00000003) /**0b0000000000000011  < EM4H/S Reset */
+#define NUM_RSTCAUSES                             (9)
+
+#else
+#warning "RMU_RSTCAUSE XMASKs are not defined for this family."
 #endif
 
 /*******************************************************************************
@@ -90,8 +123,8 @@
 /** Reset cause mask type. */
 typedef struct
 {
-  uint32_t    resetCauseMask;
-  uint32_t    dontCareMask;
+  uint32_t resetCauseMask;
+  uint32_t dontCareMask;
 } RMU_ResetCauseMasks_Typedef;
 
 
@@ -103,19 +136,38 @@
 static const RMU_ResetCauseMasks_Typedef  resetCauseMasks[NUM_RSTCAUSES] =
   {
     { RMU_RSTCAUSE_PORST,        RMU_RSTCAUSE_PORST_XMASK },
+#if defined(RMU_RSTCAUSE_BODUNREGRST)
     { RMU_RSTCAUSE_BODUNREGRST,  RMU_RSTCAUSE_BODUNREGRST_XMASK },
+#endif
+#if defined(RMU_RSTCAUSE_BODREGRST)
     { RMU_RSTCAUSE_BODREGRST,    RMU_RSTCAUSE_BODREGRST_XMASK },
+#endif
+#if defined(RMU_RSTCAUSE_AVDDBOD)
+    { RMU_RSTCAUSE_AVDDBOD,      RMU_RSTCAUSE_BODAVDD_XMASK },
+#endif
+#if defined(RMU_RSTCAUSE_DVDDBOD)
+    { RMU_RSTCAUSE_DVDDBOD,      RMU_RSTCAUSE_BODDVDD_XMASK },
+#endif
+#if defined(RMU_RSTCAUSE_DECBOD)
+    { RMU_RSTCAUSE_DECBOD,       RMU_RSTCAUSE_BODREGRST_XMASK },
+#endif
     { RMU_RSTCAUSE_EXTRST,       RMU_RSTCAUSE_EXTRST_XMASK },
     { RMU_RSTCAUSE_WDOGRST,      RMU_RSTCAUSE_WDOGRST_XMASK },
     { RMU_RSTCAUSE_LOCKUPRST,    RMU_RSTCAUSE_LOCKUPRST_XMASK },
     { RMU_RSTCAUSE_SYSREQRST,    RMU_RSTCAUSE_SYSREQRST_XMASK },
-#ifndef _EFM32_GECKO_FAMILY
+#if defined(RMU_RSTCAUSE_EM4RST)
     { RMU_RSTCAUSE_EM4RST,       RMU_RSTCAUSE_EM4RST_XMASK },
+#endif
+#if defined(RMU_RSTCAUSE_EM4WURST)
     { RMU_RSTCAUSE_EM4WURST,     RMU_RSTCAUSE_EM4WURST_XMASK },
+#endif
+#if defined(RMU_RSTCAUSE_BODAVDD0)
     { RMU_RSTCAUSE_BODAVDD0,     RMU_RSTCAUSE_BODAVDD0_XMASK },
+#endif
+#if defined(RMU_RSTCAUSE_BODAVDD1)
     { RMU_RSTCAUSE_BODAVDD1,     RMU_RSTCAUSE_BODAVDD1_XMASK },
 #endif
-#ifdef BU_PRESENT
+#if defined(BU_PRESENT)
     { RMU_RSTCAUSE_BUBODVDDDREG, RMU_RSTCAUSE_BUBODVDDDREG_XMASK },
     { RMU_RSTCAUSE_BUBODBUVIN,   RMU_RSTCAUSE_BUBODBUVIN_XMASK },
     { RMU_RSTCAUSE_BUBODUNREG,   RMU_RSTCAUSE_BUBODUNREG_XMASK },
@@ -128,7 +180,7 @@
 /*******************************************************************************
  ********************************     TEST     ********************************
  ******************************************************************************/
-#ifdef EMLIB_REGRESSION_TEST
+#if defined(EMLIB_REGRESSION_TEST)
 /* Test variable that replaces the RSTCAUSE cause register when testing
    the RMU_ResetCauseGet function. */
 extern uint32_t rstCause;
@@ -147,13 +199,23 @@
  *
  * @param[in] reset Reset types to enable/disable
  *
- * @param[in] enable
- *   @li false - Disable reset signal or flag
- *   @li true - Enable reset signal or flag
+ * @param[in] mode  Reset mode
  ******************************************************************************/
-void RMU_ResetControl(RMU_Reset_TypeDef reset, bool enable)
+void RMU_ResetControl(RMU_Reset_TypeDef reset, RMU_ResetMode_TypeDef mode)
 {
-  BITBAND_Peripheral(&(RMU->CTRL), (uint32_t)reset, (uint32_t)enable);
+  /* Note that the RMU supports bit-band access, but not peripheral bit-field set/clear */
+#if defined(_RMU_CTRL_PINRMODE_MASK)
+  uint32_t val;
+#endif
+  uint32_t shift;
+
+  shift = EFM32_CTZ((uint32_t)reset);
+#if defined(_RMU_CTRL_PINRMODE_MASK)
+  val = (uint32_t)mode << shift;
+  RMU->CTRL = (RMU->CTRL & ~reset) | val;
+#else
+  BUS_RegBitWrite(&RMU->CTRL, (uint32_t)shift, mode ? 1 : 0);
+#endif
 }
 
 
@@ -168,25 +230,29 @@
  ******************************************************************************/
 void RMU_ResetCauseClear(void)
 {
-  uint32_t locked;
-
   RMU->CMD = RMU_CMD_RCCLR;
 
-  /* Clear some reset causes not cleared with RMU CMD register */
-  /* (If EMU registers locked, they must be unlocked first) */
-  locked = EMU->LOCK & EMU_LOCK_LOCKKEY_LOCKED;
-  if (locked)
+#if defined(EMU_AUXCTRL_HRCCLR)
   {
-    EMU_Unlock();
-  }
+    uint32_t locked;
 
-  BITBAND_Peripheral(&(EMU->AUXCTRL), 0, 1);
-  BITBAND_Peripheral(&(EMU->AUXCTRL), 0, 0);
+    /* Clear some reset causes not cleared with RMU CMD register */
+    /* (If EMU registers locked, they must be unlocked first) */
+    locked = EMU->LOCK & EMU_LOCK_LOCKKEY_LOCKED;
+    if (locked)
+    {
+      EMU_Unlock();
+    }
 
-  if (locked)
-  {
-    EMU_Lock();
+    BUS_RegBitWrite(&(EMU->AUXCTRL), _EMU_AUXCTRL_HRCCLR_SHIFT, 1);
+    BUS_RegBitWrite(&(EMU->AUXCTRL), _EMU_AUXCTRL_HRCCLR_SHIFT, 0);
+
+    if (locked)
+    {
+      EMU_Lock();
+    }
   }
+#endif
 }
 
 
@@ -195,49 +261,33 @@
  *   Get the cause of the last reset.
  *
  * @details
- *   In order to be useful, the reset cause must be cleared by SW before a new
+ *   In order to be useful, the reset cause must be cleared by software before a new
  *   reset occurs, otherwise reset causes may accumulate. See @ref
  *   RMU_ResetCauseClear(). This function call will return the main cause for
  *   reset, which can be a bit mask (several causes), and clear away "noise".
  *
  * @return
- *   The reset cause, a bit mask of (typically, but not always, only one) of:
- *   @li RMU_RSTCAUSE_PORST - Power on reset
- *   @li RMU_RSTCAUSE_BODUNREGRST - Brown out detector, unregulated power
- *   @li RMU_RSTCAUSE_BODREGRST - Brown out detector, regulated power
- *   @li RMU_RSTCAUSE_EXTRST - External reset
- *   @li RMU_RSTCAUSE_WDOGRST - Watchdog reset
- *   @li RMU_RSTCAUSE_LOCKUPRST - Cortex-M3 lockup reset
- *   @li RMU_RSTCAUSE_SYSREQRST - Cortex-M3 system request reset
- *   @li RMU_RSTCAUSE_EM4RST - Set if the system has been in EM4
- *   @li RMU_RSTCAUSE_EM4WURST - Set if the system woke up on a pin from EM4
- *   @li RMU_RSTCAUSE_BODAVDD0 - Analog power domain 0 brown out detector reset
- *   @li RMU_RSTCAUSE_BODAVDD1 - Analog power domain 1 brown out detector reset
- *   @li RMU_RSTCAUSE_BUBODVDDDREG - Backup BOD on VDDD_REG triggered
- *   @li RMU_RSTCAUSE_BUBODBUVIN - Backup BOD on BU_VIN triggered
- *   @li RMU_RSTCAUSE_BUBODUNREG - Backup BOD on unregulated power triggered
- *   @li RMU_RSTCAUSE_BUBODREG - Backup BOD on regulated powered has triggered
- *   @li RMU_RSTCAUSE_BUMODERST - System has been in Backup mode
+ *   Reset cause mask. Please consult the reference manual for description
+ *   of the reset cause mask.
  ******************************************************************************/
 uint32_t RMU_ResetCauseGet(void)
 {
-#ifndef EMLIB_REGRESSION_TEST
-  uint32_t rstCause      = RMU->RSTCAUSE;
+#if !defined(EMLIB_REGRESSION_TEST)
+  uint32_t rstCause = RMU->RSTCAUSE;
 #endif
   uint32_t validRstCause = 0;
-  int      i;
-  
-  for (i=0; i<NUM_RSTCAUSES; i++)
+  uint32_t i;
+
+  for (i = 0; i < NUM_RSTCAUSES; i++)
   {
-    //Checks to see if rstCause matches a RSTCAUSE and is not excluded by the X-mask
-    if ((rstCause & resetCauseMasks[i].resetCauseMask) &&
-        !(rstCause & resetCauseMasks[i].dontCareMask))
+    /* Checks to see if rstCause matches a RSTCAUSE and is not excluded by the X-mask */
+    if ((rstCause & resetCauseMasks[i].resetCauseMask)
+        && !(rstCause & resetCauseMasks[i].dontCareMask))
     {
-      //Adds the reset-cause to list of real reset-causes
+      /* Adds the reset-cause to list of real reset-causes */
       validRstCause |= resetCauseMasks[i].resetCauseMask;
     }
   }
-  
   return validRstCause;
 }
 

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_rtc.c	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_rtc.c	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /***************************************************************************//**
  * @file em_rtc.c
  * @brief Real Time Counter (RTC) Peripheral API
- * @version 3.20.12
+ * @version 4.2.1
  *******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
  *******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,12 +30,11 @@
  *
  ******************************************************************************/
 
-
 #include "em_rtc.h"
 #if defined(RTC_COUNT) && (RTC_COUNT > 0)
 
 #include "em_assert.h"
-#include "em_bitband.h"
+#include "em_bus.h"
 
 /***************************************************************************//**
  * @addtogroup EM_Library
@@ -82,7 +81,7 @@
  *   Bitmask corresponding to SYNCBUSY register defined bits, indicating
  *   registers that must complete any ongoing synchronization.
  ******************************************************************************/
-__STATIC_INLINE void RTC_Sync(uint32_t mask)
+__STATIC_INLINE void regSync(uint32_t mask)
 {
   /* Avoid deadlock if modifying the same register twice when freeze mode is */
   /* activated. */
@@ -121,18 +120,18 @@
   /* Initialize selected compare value */
   switch (comp)
   {
-  case 0:
-    ret = RTC->COMP0;
-    break;
+    case 0:
+      ret = RTC->COMP0;
+      break;
 
-  case 1:
-    ret = RTC->COMP1;
-    break;
+    case 1:
+      ret = RTC->COMP1;
+      break;
 
-  default:
-    /* Unknown compare register selected */
-    ret = 0;
-    break;
+    default:
+      /* Unknown compare register selected */
+      ret = 0;
+      break;
   }
 
   return ret;
@@ -148,7 +147,7 @@
  *   low frequency domain. If the same register is modified before a previous
  *   update has completed, this function will stall until the previous
  *   synchronization has completed. This only applies to the Gecko Family, see
- *   comment in the RTC_Sync() internal function call.
+ *   comment in the regSync() internal function call.
  *
  * @param[in] comp
  *   Compare register to set, either 0 or 1
@@ -163,33 +162,34 @@
   uint32_t          syncbusy;
 #endif
 
-  EFM_ASSERT(RTC_COMP_REG_VALID(comp) &&
-             ((value & ~(_RTC_COMP0_COMP0_MASK >> _RTC_COMP0_COMP0_SHIFT)) == 0));
+  EFM_ASSERT(RTC_COMP_REG_VALID(comp)
+             && ((value & ~(_RTC_COMP0_COMP0_MASK
+                            >> _RTC_COMP0_COMP0_SHIFT)) == 0));
 
   /* Initialize selected compare value */
   switch (comp)
   {
-  case 0:
-    compReg = &(RTC->COMP0);
+    case 0:
+      compReg = &(RTC->COMP0);
 #if defined(_EFM32_GECKO_FAMILY)
-    syncbusy = RTC_SYNCBUSY_COMP0;
+      syncbusy = RTC_SYNCBUSY_COMP0;
 #endif
-    break;
+      break;
 
-  case 1:
-    compReg = &(RTC->COMP1);
+    case 1:
+      compReg = &(RTC->COMP1);
 #if defined(_EFM32_GECKO_FAMILY)
-    syncbusy = RTC_SYNCBUSY_COMP1;
+      syncbusy = RTC_SYNCBUSY_COMP1;
 #endif
-    break;
+      break;
 
-  default:
-    /* Unknown compare register selected, abort */
-    return;
+    default:
+      /* Unknown compare register selected, abort */
+      return;
   }
 #if defined(_EFM32_GECKO_FAMILY)
   /* LF register about to be modified require sync. busy check */
-  RTC_Sync(syncbusy);
+  regSync(syncbusy);
 #endif
 
   *compReg = value;
@@ -205,7 +205,7 @@
  *   requires synchronization into the low frequency domain. If this register is
  *   modified before a previous update to the same register has completed, this
  *   function will stall until the previous synchronization has completed. This
- *   only applies to the Gecko Family, see comment in the RTC_Sync() internal
+ *   only applies to the Gecko Family, see comment in the regSync() internal
  *   function call.
  *
  * @param[in] enable
@@ -215,16 +215,16 @@
 {
 #if defined(_EFM32_GECKO_FAMILY)
   /* LF register about to be modified require sync. busy check */
-  RTC_Sync(RTC_SYNCBUSY_CTRL);
+  regSync(RTC_SYNCBUSY_CTRL);
 #endif
 
-  BITBAND_Peripheral(&(RTC->CTRL), _RTC_CTRL_EN_SHIFT, (unsigned int) enable);
+  BUS_RegBitWrite(&(RTC->CTRL), _RTC_CTRL_EN_SHIFT, enable);
 
 #if defined(_EFM32_GECKO_FAMILY)
   /* Wait for CTRL to be updated before returning, because calling code may
      depend upon that the CTRL register is updated after this function has
      returned. */
-  RTC_Sync(RTC_SYNCBUSY_CTRL);
+  regSync(RTC_SYNCBUSY_CTRL);
 #endif
 }
 
@@ -293,7 +293,7 @@
  *   synchronization into the low frequency domain. If this register is
  *   modified before a previous update to the same register has completed, this
  *   function will stall until the previous synchronization has completed. This
- *   only applies to the Gecko Family, see comment in the RTC_Sync() internal
+ *   only applies to the Gecko Family, see comment in the regSync() internal
  *   function call.
  *
  * @param[in] init
@@ -328,7 +328,7 @@
 
 #if defined(_EFM32_GECKO_FAMILY)
   /* LF register about to be modified require sync. busy check */
-  RTC_Sync(RTC_SYNCBUSY_CTRL);
+  regSync(RTC_SYNCBUSY_CTRL);
 #endif
 
   RTC->CTRL = tmp;
@@ -354,7 +354,7 @@
   /* Wait for CTRL, COMP0 and COMP1 to be updated before returning, because the
      calling code may depend upon that the register values are updated after
      this function has returned. */
-  RTC_Sync(RTC_SYNCBUSY_CTRL | RTC_SYNCBUSY_COMP0 | RTC_SYNCBUSY_COMP1);
+  regSync(RTC_SYNCBUSY_CTRL | RTC_SYNCBUSY_COMP0 | RTC_SYNCBUSY_COMP1);
 #endif
 }
 

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_rtcc.c	Fri Jan 15 07:45:16 2016 +0000
@@ -0,0 +1,180 @@
+/***************************************************************************//**
+ * @file
+ * @brief Real Time Counter with Calendar (RTCC) Peripheral API
+ * @version 4.2.1
+ *******************************************************************************
+ * @section License
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
+ *******************************************************************************
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
+ * obligation to support this Software. Silicon Labs is providing the
+ * Software "AS IS", with no express or implied warranties of any kind,
+ * including, but not limited to, any implied warranties of merchantability
+ * or fitness for any particular purpose or warranties against infringement
+ * of any proprietary rights of a third party.
+ *
+ * Silicon Labs will not be liable for any consequential, incidental, or
+ * special damages, or any other relief, or for any claim by any third party,
+ * arising from your use of this Software.
+ *
+ ******************************************************************************/
+
+#include "em_rtcc.h"
+#if defined( RTCC_COUNT ) && ( RTCC_COUNT == 1 )
+#include "em_bus.h"
+
+/***************************************************************************//**
+ * @addtogroup EM_Library
+ * @{
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * @addtogroup RTCC
+ * @brief Real Time Counter (RTCC) Peripheral API
+ * @{
+ ******************************************************************************/
+
+/*******************************************************************************
+ *******************************   DEFINES   ***********************************
+ ******************************************************************************/
+
+/*******************************************************************************
+ **************************   LOCAL FUNCTIONS   ********************************
+ ******************************************************************************/
+
+/*******************************************************************************
+ **************************   GLOBAL FUNCTIONS   *******************************
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * @brief
+ *   Configure the selected capture/compare channel of the RTCC.
+ *
+ * @details
+ *   Use this function to configure a RTCC channel.
+ *   Select capture/compare mode, match output action, overflow output action
+ *   and PRS input configuration.
+ *   Refer to the configuration structure @ref RTCC_CCChConf_TypeDef for more
+ *   details.
+ *
+ * @param[in] ch
+ *   Channel selector.
+ *
+ * @param[in] confPtr
+ *   Pointer to configuration structure.
+ ******************************************************************************/
+void RTCC_ChannelInit( int ch, RTCC_CCChConf_TypeDef const *confPtr )
+{
+  EFM_ASSERT( RTCC_CH_VALID( ch ) );
+  EFM_ASSERT( (uint32_t)confPtr->compMask
+              < ( _RTCC_CC_CTRL_COMPMASK_MASK >> _RTCC_CC_CTRL_COMPMASK_SHIFT )
+              + 1 );
+
+  /** Configure the selected capture/compare channel. */
+  RTCC->CC[ch].CTRL = ( (uint32_t)confPtr->chMode << _RTCC_CC_CTRL_MODE_SHIFT )
+                      | ( (uint32_t)confPtr->compMatchOutAction << _RTCC_CC_CTRL_CMOA_SHIFT )
+                      | ( (uint32_t)confPtr->prsSel << _RTCC_CC_CTRL_PRSSEL_SHIFT )
+                      | ( (uint32_t)confPtr->inputEdgeSel << _RTCC_CC_CTRL_ICEDGE_SHIFT )
+                      | ( (uint32_t)confPtr->compBase << _RTCC_CC_CTRL_COMPBASE_SHIFT )
+                      | ( (uint32_t)confPtr->compMask << _RTCC_CC_CTRL_COMPMASK_SHIFT )
+                      | ( (uint32_t)confPtr->dayCompMode << _RTCC_CC_CTRL_DAYCC_SHIFT );
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Enable/disable RTCC.
+ *
+ * @param[in] enable
+ *   True to enable RTCC, false to disable.
+ ******************************************************************************/
+void RTCC_Enable( bool enable )
+{
+  /* Bitbanding the enable bit in the CTRL register (atomic). */
+  BUS_RegBitWrite((&RTCC->CTRL), _RTCC_CTRL_ENABLE_SHIFT, enable);
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Initialize RTCC.
+ *
+ * @details
+ *   Note that the compare values must be set separately with RTCC_CompareSet().
+ *   That should probably be done prior to the use of this function if
+ *   configuring the RTCC to start when initialization is completed.
+ *
+ * @param[in] init
+ *   Pointer to RTCC initialization structure.
+ ******************************************************************************/
+void RTCC_Init( const RTCC_Init_TypeDef *init )
+{
+  RTCC->CTRL = ( (uint32_t)init->enable << _RTCC_CTRL_ENABLE_SHIFT )
+               | ( (uint32_t)init->debugRun << _RTCC_CTRL_DEBUGRUN_SHIFT )
+               | ( (uint32_t)init->precntWrapOnCCV0 << _RTCC_CTRL_PRECCV0TOP_SHIFT )
+               | ( (uint32_t)init->cntWrapOnCCV1 << _RTCC_CTRL_CCV1TOP_SHIFT )
+               | ( (uint32_t)init->presc << _RTCC_CTRL_CNTPRESC_SHIFT )
+               | ( (uint32_t)init->prescMode << _RTCC_CTRL_CNTTICK_SHIFT )
+#if defined(_RTCC_CTRL_BUMODETSEN_MASK)
+               | ( (uint32_t)init->enaBackupModeSet << _RTCC_CTRL_BUMODETSEN_SHIFT )
+#endif
+               | ( (uint32_t)init->enaOSCFailDetect << _RTCC_CTRL_OSCFDETEN_SHIFT )
+               | ( (uint32_t)init->cntMode << _RTCC_CTRL_CNTMODE_SHIFT )
+               | ( (uint32_t)init->disLeapYearCorr << _RTCC_CTRL_LYEARCORRDIS_SHIFT );
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Restore RTCC to its reset state.
+ ******************************************************************************/
+void RTCC_Reset( void )
+{
+  int i;
+
+  /* Restore all RTCC registers to their default values. */
+  RTCC_Unlock();
+  RTCC->CTRL    = _RTCC_CTRL_RESETVALUE;
+  RTCC->PRECNT  = _RTCC_PRECNT_RESETVALUE;
+  RTCC->CNT     = _RTCC_CNT_RESETVALUE;
+  RTCC->TIME    = _RTCC_TIME_RESETVALUE;
+  RTCC->DATE    = _RTCC_DATE_RESETVALUE;
+  RTCC->IEN     = _RTCC_IEN_RESETVALUE;
+  RTCC->IFC     = _RTCC_IFC_MASK;
+  RTCC_StatusClear();
+  RTCC->EM4WUEN = _RTCC_EM4WUEN_RESETVALUE;
+
+  for (i = 0; i < 3; i++)
+  {
+    RTCC->CC[i].CTRL = _RTCC_CC_CTRL_RESETVALUE;
+    RTCC->CC[i].CCV  = _RTCC_CC_CCV_RESETVALUE;
+    RTCC->CC[i].TIME = _RTCC_CC_TIME_RESETVALUE;
+    RTCC->CC[i].DATE = _RTCC_CC_DATE_RESETVALUE;
+  }
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Clear STATUS register.
+ ******************************************************************************/
+void RTCC_StatusClear( void )
+{
+  while ( RTCC->SYNCBUSY & RTCC_SYNCBUSY_CMD )
+  {
+    // Wait for syncronization.
+  }
+  RTCC->CMD = RTCC_CMD_CLRSTATUS;
+}
+
+/** @} (end addtogroup RTCC) */
+/** @} (end addtogroup EM_Library) */
+
+#endif /* defined( RTCC_COUNT ) && ( RTCC_COUNT == 1 ) */

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_system.c	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_system.c	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /***************************************************************************//**
  * @file em_system.c
  * @brief System Peripheral API
- * @version 3.20.12
+ * @version 4.2.1
  *******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
  *******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,7 +30,6 @@
  *
  ******************************************************************************/
 
-
 #include "em_system.h"
 #include "em_assert.h"
 
@@ -60,24 +59,26 @@
 {
   uint8_t tmp;
 
-  EFM_ASSERT(rev);  
-  
+  EFM_ASSERT(rev);
+
   /* CHIP FAMILY bit [5:2] */
-  tmp  = (((ROMTABLE->PID1 & _ROMTABLE_PID1_FAMILYMSB_MASK) >> _ROMTABLE_PID1_FAMILYMSB_SHIFT) << 2);           
+  tmp  = (((ROMTABLE->PID1 & _ROMTABLE_PID1_FAMILYMSB_MASK) >> _ROMTABLE_PID1_FAMILYMSB_SHIFT) << 2);
   /* CHIP FAMILY bit [1:0] */
-  tmp |=  ((ROMTABLE->PID0 & _ROMTABLE_PID0_FAMILYLSB_MASK) >> _ROMTABLE_PID0_FAMILYLSB_SHIFT);                 
+  tmp |=  ((ROMTABLE->PID0 & _ROMTABLE_PID0_FAMILYLSB_MASK) >> _ROMTABLE_PID0_FAMILYLSB_SHIFT);
   rev->family = tmp;
 
   /* CHIP MAJOR bit [3:0] */
-  rev->major = (ROMTABLE->PID0 & _ROMTABLE_PID0_REVMAJOR_MASK) >> _ROMTABLE_PID0_REVMAJOR_SHIFT;                
+  rev->major = (ROMTABLE->PID0 & _ROMTABLE_PID0_REVMAJOR_MASK) >> _ROMTABLE_PID0_REVMAJOR_SHIFT;
 
   /* CHIP MINOR bit [7:4] */
-  tmp  = (((ROMTABLE->PID2 & _ROMTABLE_PID2_REVMINORMSB_MASK) >> _ROMTABLE_PID2_REVMINORMSB_SHIFT) << 4);  
+  tmp  = (((ROMTABLE->PID2 & _ROMTABLE_PID2_REVMINORMSB_MASK) >> _ROMTABLE_PID2_REVMINORMSB_SHIFT) << 4);
   /* CHIP MINOR bit [3:0] */
-  tmp |=  ((ROMTABLE->PID3 & _ROMTABLE_PID3_REVMINORLSB_MASK) >> _ROMTABLE_PID3_REVMINORLSB_SHIFT);             
+  tmp |=  ((ROMTABLE->PID3 & _ROMTABLE_PID3_REVMINORLSB_MASK) >> _ROMTABLE_PID3_REVMINORLSB_SHIFT);
   rev->minor = tmp;
 }
 
+
+#if defined(CALIBRATE)
 /***************************************************************************//**
  * @brief
  *    Get factory calibration value for a given peripheral register.
@@ -114,6 +115,7 @@
     regCount++;
   }
 }
+#endif /* defined (CALIBRATE) */
 
 /** @} (end addtogroup SYSTEM) */
 /** @} (end addtogroup EM_Library) */

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_timer.c	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_timer.c	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /***************************************************************************//**
  * @file em_timer.c
  * @brief Timer/counter (TIMER) Peripheral API
- * @version 3.20.12
+ * @version 4.2.1
  *******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
  *******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,7 +30,6 @@
  *
  ******************************************************************************/
 
-
 #include "em_timer.h"
 #if defined(TIMER_COUNT) && (TIMER_COUNT > 0)
 
@@ -87,22 +86,21 @@
   /* Reset counter */
   timer->CNT = _TIMER_CNT_RESETVALUE;
 
-  timer->CTRL =
-    ((uint32_t)(init->prescale) << _TIMER_CTRL_PRESC_SHIFT) |
-    ((uint32_t)(init->clkSel) << _TIMER_CTRL_CLKSEL_SHIFT) |
-    ((uint32_t)(init->fallAction) << _TIMER_CTRL_FALLA_SHIFT) |
-    ((uint32_t)(init->riseAction) << _TIMER_CTRL_RISEA_SHIFT) |
-    ((uint32_t)(init->mode) << _TIMER_CTRL_MODE_SHIFT) |
-    (init->debugRun               ?   TIMER_CTRL_DEBUGRUN  : 0) |
-    (init->dmaClrAct              ?   TIMER_CTRL_DMACLRACT : 0) |
-    (init->quadModeX4             ?   TIMER_CTRL_QDM_X4    : 0) |
-    (init->oneShot                ?   TIMER_CTRL_OSMEN     : 0) |
+  timer->CTRL = ((uint32_t)(init->prescale)     << _TIMER_CTRL_PRESC_SHIFT)
+                | ((uint32_t)(init->clkSel)     << _TIMER_CTRL_CLKSEL_SHIFT)
+                | ((uint32_t)(init->fallAction) << _TIMER_CTRL_FALLA_SHIFT)
+                | ((uint32_t)(init->riseAction) << _TIMER_CTRL_RISEA_SHIFT)
+                | ((uint32_t)(init->mode)       << _TIMER_CTRL_MODE_SHIFT)
+                | (init->debugRun               ?   TIMER_CTRL_DEBUGRUN  : 0)
+                | (init->dmaClrAct              ?   TIMER_CTRL_DMACLRACT : 0)
+                | (init->quadModeX4             ?   TIMER_CTRL_QDM_X4    : 0)
+                | (init->oneShot                ?   TIMER_CTRL_OSMEN     : 0)
 
-#if defined( TIMER_CTRL_X2CNT ) && defined( TIMER_CTRL_ATI )
-    (init->count2x                ?   TIMER_CTRL_X2CNT     : 0) |
-    (init->ati                    ?   TIMER_CTRL_ATI       : 0) |
+#if defined(TIMER_CTRL_X2CNT) && defined(TIMER_CTRL_ATI)
+                | (init->count2x                ?   TIMER_CTRL_X2CNT     : 0)
+                | (init->ati                    ?   TIMER_CTRL_ATI       : 0)
 #endif
-    (init->sync                   ?   TIMER_CTRL_SYNC      : 0);
+                | (init->sync                   ?   TIMER_CTRL_SYNC      : 0);
 
   /* Start timer if specified to be enabled (dosn't hurt if already started) */
   if (init->enable)
@@ -137,21 +135,21 @@
   EFM_ASSERT(TIMER_CH_VALID(ch));
 
   timer->CC[ch].CTRL =
-    ((uint32_t)(init->eventCtrl) << _TIMER_CC_CTRL_ICEVCTRL_SHIFT) |
-    ((uint32_t)(init->edge) << _TIMER_CC_CTRL_ICEDGE_SHIFT) |
-    ((uint32_t)(init->prsSel) << _TIMER_CC_CTRL_PRSSEL_SHIFT) |
-    ((uint32_t)(init->cufoa) << _TIMER_CC_CTRL_CUFOA_SHIFT) |
-    ((uint32_t)(init->cofoa) << _TIMER_CC_CTRL_COFOA_SHIFT) |
-    ((uint32_t)(init->cmoa) << _TIMER_CC_CTRL_CMOA_SHIFT) |
-    ((uint32_t)(init->mode) << _TIMER_CC_CTRL_MODE_SHIFT) |
-    (init->filter                ?   TIMER_CC_CTRL_FILT_ENABLE : 0) |
-    (init->prsInput              ?   TIMER_CC_CTRL_INSEL_PRS   : 0) |
-    (init->coist                 ?   TIMER_CC_CTRL_COIST       : 0) |
-    (init->outInvert             ?   TIMER_CC_CTRL_OUTINV      : 0);
+    ((uint32_t)(init->eventCtrl) << _TIMER_CC_CTRL_ICEVCTRL_SHIFT)
+    | ((uint32_t)(init->edge)    << _TIMER_CC_CTRL_ICEDGE_SHIFT)
+    | ((uint32_t)(init->prsSel)  << _TIMER_CC_CTRL_PRSSEL_SHIFT)
+    | ((uint32_t)(init->cufoa)   << _TIMER_CC_CTRL_CUFOA_SHIFT)
+    | ((uint32_t)(init->cofoa)   << _TIMER_CC_CTRL_COFOA_SHIFT)
+    | ((uint32_t)(init->cmoa)    << _TIMER_CC_CTRL_CMOA_SHIFT)
+    | ((uint32_t)(init->mode)    << _TIMER_CC_CTRL_MODE_SHIFT)
+    | (init->filter              ?   TIMER_CC_CTRL_FILT_ENABLE : 0)
+    | (init->prsInput            ?   TIMER_CC_CTRL_INSEL_PRS   : 0)
+    | (init->coist               ?   TIMER_CC_CTRL_COIST       : 0)
+    | (init->outInvert           ?   TIMER_CC_CTRL_OUTINV      : 0);
 }
 
 
-#ifdef _TIMER_DTCTRL_MASK
+#if defined(_TIMER_DTCTRL_MASK)
 /***************************************************************************//**
  * @brief
  *   Initialize the TIMER DTI unit.
@@ -172,27 +170,27 @@
   /* Setup the DTCTRL register.
      The enable bit will be set at the end of the function if specified. */
   timer->DTCTRL =
-    (init->autoRestart             ?  TIMER_DTCTRL_DTDAS      : 0) |
-    (init->activeLowOut            ?  TIMER_DTCTRL_DTIPOL     : 0) |
-    (init->invertComplementaryOut  ?  TIMER_DTCTRL_DTCINV     : 0) |
-    (init->enablePrsSource         ?  TIMER_DTCTRL_DTPRSEN    : 0) |
-    ((uint32_t)(init->prsSel)     << _TIMER_DTCTRL_DTPRSSEL_SHIFT);
+    (init->autoRestart              ?   TIMER_DTCTRL_DTDAS   : 0)
+    | (init->activeLowOut           ?   TIMER_DTCTRL_DTIPOL  : 0)
+    | (init->invertComplementaryOut ?   TIMER_DTCTRL_DTCINV  : 0)
+    | (init->enablePrsSource        ?   TIMER_DTCTRL_DTPRSEN : 0)
+    | ((uint32_t)(init->prsSel)     << _TIMER_DTCTRL_DTPRSSEL_SHIFT);
 
   /* Setup the DTTIME register. */
   timer->DTTIME =
-    ((uint32_t)(init->prescale)   << _TIMER_DTTIME_DTPRESC_SHIFT) |
-    ((uint32_t)(init->riseTime)   << _TIMER_DTTIME_DTRISET_SHIFT) |
-    ((uint32_t)(init->fallTime)   << _TIMER_DTTIME_DTFALLT_SHIFT);
+    ((uint32_t)(init->prescale)   << _TIMER_DTTIME_DTPRESC_SHIFT)
+    | ((uint32_t)(init->riseTime) << _TIMER_DTTIME_DTRISET_SHIFT)
+    | ((uint32_t)(init->fallTime) << _TIMER_DTTIME_DTFALLT_SHIFT);
 
   /* Setup the DTFC register. */
   timer->DTFC =
-    (init->enableFaultSourceCoreLockup     ?  TIMER_DTFC_DTLOCKUPFEN     : 0) |
-    (init->enableFaultSourceDebugger       ?  TIMER_DTFC_DTDBGFEN        : 0) |
-    (init->enableFaultSourcePrsSel0        ?  TIMER_DTFC_DTPRS0FEN       : 0) |
-    (init->enableFaultSourcePrsSel1        ?  TIMER_DTFC_DTPRS1FEN       : 0) |
-    ((uint32_t)(init->faultAction)        << _TIMER_DTFC_DTFA_SHIFT)          |
-    ((uint32_t)(init->faultSourcePrsSel0) << _TIMER_DTFC_DTPRS0FSEL_SHIFT)    |
-    ((uint32_t)(init->faultSourcePrsSel1) << _TIMER_DTFC_DTPRS1FSEL_SHIFT);
+    (init->enableFaultSourceCoreLockup      ?   TIMER_DTFC_DTLOCKUPFEN : 0)
+    | (init->enableFaultSourceDebugger      ?   TIMER_DTFC_DTDBGFEN    : 0)
+    | (init->enableFaultSourcePrsSel0       ?   TIMER_DTFC_DTPRS0FEN   : 0)
+    | (init->enableFaultSourcePrsSel1       ?   TIMER_DTFC_DTPRS1FEN   : 0)
+    | ((uint32_t)(init->faultAction)        << _TIMER_DTFC_DTFA_SHIFT)
+    | ((uint32_t)(init->faultSourcePrsSel0) << _TIMER_DTFC_DTPRS0FSEL_SHIFT)
+    | ((uint32_t)(init->faultSourcePrsSel1) << _TIMER_DTFC_DTPRS1FSEL_SHIFT);
 
   /* Setup the DTOGEN register. */
   timer->DTOGEN = init->outputsEnableMask;
@@ -244,7 +242,7 @@
 
   /* Reset dead time insertion module, no effect on timers without DTI */
 
-#ifdef TIMER_DTLOCK_LOCKKEY_UNLOCK
+#if defined(TIMER_DTLOCK_LOCKKEY_UNLOCK)
   /* Unlock DTI registers first in case locked */
   timer->DTLOCK = TIMER_DTLOCK_LOCKKEY_UNLOCK;
 

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_usart.c	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_usart.c	Fri Jan 15 07:45:16 2016 +0000
@@ -2,10 +2,10 @@
  * @file em_usart.c
  * @brief Universal synchronous/asynchronous receiver/transmitter (USART/UART)
  *   Peripheral API
- * @version 3.20.12
+ * @version 4.2.1
  *******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
  *******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -31,11 +31,11 @@
  *
  ******************************************************************************/
 
-
 #include "em_usart.h"
 #if defined(USART_COUNT) && (USART_COUNT > 0)
 
 #include "em_cmu.h"
+#include "em_bus.h"
 #include "em_assert.h"
 
 /***************************************************************************//**
@@ -76,17 +76,33 @@
 #elif (USART_COUNT == 4)
 #define USART_REF_VALID(ref)    (((ref) == USART0) || ((ref) == USART1) || \
                                  ((ref) == USART2) || ((ref) == USART3))
+#elif (USART_COUNT == 5)
+#define USART_REF_VALID(ref)    (((ref) == USART0) || ((ref) == USART1) || \
+                                 ((ref) == USART2) || ((ref) == USART3) || \
+                                 ((ref) == USART4))
+#elif (USART_COUNT == 6)
+#define USART_REF_VALID(ref)    (((ref) == USART0) || ((ref) == USART1) || \
+                                 ((ref) == USART2) || ((ref) == USART3) || \
+                                 ((ref) == USART4) || ((ref) == USART5))
 #else
-#error Undefined number of USARTs.
+#error "Undefined number of USARTs."
 #endif
 
+#if defined(USARTRF_COUNT) && (USARTRF_COUNT > 0)
 #if (USARTRF_COUNT == 1) && defined(USARTRF0)
 #define USARTRF_REF_VALID(ref)  ((ref) == USARTRF0)
+#elif (USARTRF_COUNT == 1) && defined(USARTRF1)
+#define USARTRF_REF_VALID(ref)  ((ref) == USARTRF1)
+#else
+#define USARTRF_REF_VALID(ref)  (0)
+#endif
 #else
 #define USARTRF_REF_VALID(ref)  (0)
 #endif
 
-#if defined( _EFM32_HAPPY_FAMILY )
+#if defined(_EZR32_HAPPY_FAMILY)
+#define USART_IRDA_VALID(ref)    ((ref) == USART0)
+#elif defined(_EFM32_HAPPY_FAMILY)
 #define USART_IRDA_VALID(ref)    (((ref) == USART0) || ((ref) == USART1))
 #elif defined(USART0)
 #define USART_IRDA_VALID(ref)    ((ref) == USART0)
@@ -96,9 +112,11 @@
 #define USART_IRDA_VALID(ref)    (0)
 #endif
 
-#if defined( _EFM32_HAPPY_FAMILY )
+#if defined(_EZR32_HAPPY_FAMILY)
+#define USART_I2S_VALID(ref)    ((ref) == USART0)
+#elif defined(_EFM32_HAPPY_FAMILY)
 #define USART_I2S_VALID(ref)    (((ref) == USART0) || ((ref) == USART1))
-#elif defined(_EFM32_TINY_FAMILY) || defined(_EFM32_ZERO_FAMILY)
+#elif defined(_EFM32_TINY_FAMILY) || defined(_EFM32_ZERO_FAMILY) || defined(_SILICON_LABS_32B_PLATFORM_2)
 #define USART_I2S_VALID(ref)    ((ref) == USART1)
 #elif defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
 #define USART_I2S_VALID(ref)    (((ref) == USART1) || ((ref) == USART2))
@@ -169,10 +187,12 @@
    * to make too harsh restrictions on max fHFPERCLK value either.
    *
    * One can possibly factorize 256 and oversample/br. However,
-   * since the last 6 bits of CLKDIV are don't care, we can base our
+   * since the last 6 or 3 bits of CLKDIV are don't care, we can base our
    * integer arithmetic on the below formula
    *
-   * CLKDIV / 64 = (4 * fHFPERCLK)/(oversample * br) - 4
+   * CLKDIV / 64 = (4 * fHFPERCLK)/(oversample * br) - 4 (3 bits dont care)
+   * or
+   * CLKDIV / 8  = (32 * fHFPERCLK)/(oversample * br) - 32 (6 bits dont care)
    *
    * and calculate 1/64 of CLKDIV first. This allows for fHFPERCLK
    * up to 1GHz without overflowing a 32 bit value!
@@ -187,30 +207,30 @@
   /* Map oversampling */
   switch (ovs)
   {
-  case USART_CTRL_OVS_X16:
-    EFM_ASSERT(baudrate <= (refFreq / 16));
-    oversample = 16;
-    break;
+    case USART_CTRL_OVS_X16:
+      EFM_ASSERT(baudrate <= (refFreq / 16));
+      oversample = 16;
+      break;
 
-  case USART_CTRL_OVS_X8:
-    EFM_ASSERT(baudrate <= (refFreq / 8));
-    oversample = 8;
-    break;
+    case USART_CTRL_OVS_X8:
+      EFM_ASSERT(baudrate <= (refFreq / 8));
+      oversample = 8;
+      break;
 
-  case USART_CTRL_OVS_X6:
-    EFM_ASSERT(baudrate <= (refFreq / 6));
-    oversample = 6;
-    break;
+    case USART_CTRL_OVS_X6:
+      EFM_ASSERT(baudrate <= (refFreq / 6));
+      oversample = 6;
+      break;
 
-  case USART_CTRL_OVS_X4:
-    EFM_ASSERT(baudrate <= (refFreq / 4));
-    oversample = 4;
-    break;
+    case USART_CTRL_OVS_X4:
+      EFM_ASSERT(baudrate <= (refFreq / 4));
+      oversample = 4;
+      break;
 
-  default:
-    /* Invalid input */
-    EFM_ASSERT(0);
-    return;
+    default:
+      /* Invalid input */
+      EFM_ASSERT(0);
+      return;
   }
 
   /* Calculate and set CLKDIV with fractional bits.
@@ -218,16 +238,23 @@
    * divisor up by half the divisor before the division in order to reduce the
    * integer division error, which consequently results in a higher baudrate
    * than desired. */
+#if defined(_USART_CLKDIV_DIV_MASK) && (_USART_CLKDIV_DIV_MASK >= 0x7FFFF8UL)
+  clkdiv  = 32 * refFreq + (oversample * baudrate) / 2;
+  clkdiv /= (oversample * baudrate);
+  clkdiv -= 32;
+  clkdiv *= 8;
+#else
   clkdiv  = 4 * refFreq + (oversample * baudrate) / 2;
   clkdiv /= (oversample * baudrate);
   clkdiv -= 4;
   clkdiv *= 64;
+#endif
 
   /* Verify that resulting clock divider is within limits */
-  EFM_ASSERT(clkdiv <= _USART_CLKDIV_MASK);
+  EFM_ASSERT(clkdiv <= _USART_CLKDIV_DIV_MASK);
 
   /* If EFM_ASSERT is not enabled, make sure we don't write to reserved bits */
-  clkdiv &= _USART_CLKDIV_MASK;
+  clkdiv &= _USART_CLKDIV_DIV_MASK;
 
   usart->CTRL  &= ~_USART_CTRL_OVS_MASK;
   usart->CTRL  |= ovs;
@@ -269,10 +296,10 @@
                             USART_OVS_TypeDef ovs)
 {
   uint32_t oversample;
-  uint32_t divisor;
-  uint32_t factor;
-  uint32_t remainder;
-  uint32_t quotient;
+  uint64_t divisor;
+  uint64_t factor;
+  uint64_t remainder;
+  uint64_t quotient;
   uint32_t br;
 
   /* Mask out unused bits */
@@ -313,31 +340,31 @@
 
     switch (ovs)
     {
-    case USART_CTRL_OVS_X16:
-      oversample = 1;
-      factor     = 256 / 16;
-      break;
+      case USART_CTRL_OVS_X16:
+        oversample = 1;
+        factor     = 256 / 16;
+        break;
 
-    case USART_CTRL_OVS_X8:
-      oversample = 1;
-      factor     = 256 / 8;
-      break;
+      case USART_CTRL_OVS_X8:
+        oversample = 1;
+        factor     = 256 / 8;
+        break;
 
-    case USART_CTRL_OVS_X6:
-      oversample = 3;
-      factor     = 256 / 2;
-      break;
+      case USART_CTRL_OVS_X6:
+        oversample = 3;
+        factor     = 256 / 2;
+        break;
 
-    default:
-      oversample = 1;
-      factor     = 256 / 4;
-      break;
+      default:
+        oversample = 1;
+        factor     = 256 / 4;
+        break;
     }
   }
 
   /*
    * The basic problem with integer division in the above formula is that
-   * the dividend (factor * fHFPERCLK) may become higher than max 32 bit
+   * the dividend (factor * fHFPERCLK) may become larger than a 32 bit
    * integer. Yet we want to evaluate dividend first before dividing in
    * order to get as small rounding effects as possible. We do not want
    * to make too harsh restrictions on max fHFPERCLK value either.
@@ -356,7 +383,7 @@
    * variable names.
    */
 
-  /* Divisor will never exceed max 32 bit value since clkdiv <= 0x1fffc0 */
+  /* Divisor will never exceed max 32 bit value since clkdiv <= 0xFFFFF8 */
   /* and 'oversample' has been reduced to <= 3. */
   divisor = oversample * (256 + clkdiv);
 
@@ -364,15 +391,16 @@
   remainder = refFreq % divisor;
 
   /* factor <= 128 and since divisor >= 256, the below cannot exceed max */
-  /* 32 bit value. */
-  br = factor * quotient;
+  /* 32 bit value. However, factor * remainder can become larger than 32-bit */
+  /* because of the size of _USART_CLKDIV_DIV_MASK on some families. */
+  br = (uint32_t)(factor * quotient);
 
   /*
    * factor <= 128 and remainder < (oversample*(256 + clkdiv)), which
    * means dividend (factor * remainder) worst case is
-   * 128*(3 * (256 + 0x1fffc0)) = 0x30012000.
+   * 128 * (3 * (256 + _USART_CLKDIV_DIV_MASK)) = 0x1_8001_7400.
    */
-  br += (factor * remainder) / divisor;
+  br += (uint32_t)((factor * remainder) / divisor);
 
   return br;
 }
@@ -409,7 +437,7 @@
 
   /* HFPERCLK used to clock all USART/UART peripheral modules */
   freq = CMU_ClockFreqGet(cmuClock_HFPER);
-  ovs  = (USART_OVS_TypeDef) (usart->CTRL & _USART_CTRL_OVS_MASK);
+  ovs  = (USART_OVS_TypeDef)(usart->CTRL & _USART_CTRL_OVS_MASK);
   return USART_BaudrateCalc(freq, usart->CLKDIV, syncmode, ovs);
 }
 
@@ -443,35 +471,19 @@
  ******************************************************************************/
 void USART_BaudrateSyncSet(USART_TypeDef *usart, uint32_t refFreq, uint32_t baudrate)
 {
+#if defined(_USART_CLKDIV_DIV_MASK) && (_USART_CLKDIV_DIV_MASK >= 0x7FFFF8UL)
+  uint64_t clkdiv;
+#else
   uint32_t clkdiv;
+#endif
 
   /* Inhibit divide by 0 */
   EFM_ASSERT(baudrate);
 
   /*
-   * We want to use integer division to avoid forcing in float division
-   * utils, and yet keep rounding effect errors to a minimum.
-   *
    * CLKDIV in synchronous mode is given by:
    *
    * CLKDIV = 256 * (fHFPERCLK/(2 * br) - 1)
-   * or
-   * CLKDIV = (256 * fHFPERCLK)/(2 * br) - 256 = (128 * fHFPERCLK)/br - 256
-   *
-   * The basic problem with integer division in the above formula is that
-   * the dividend (128 * fHFPERCLK) may become higher than max 32 bit
-   * integer. Yet, we want to evaluate dividend first before dividing in
-   * order to get as small rounding effects as possible. We do not want
-   * to make too harsh restrictions on max fHFPERCLK value either.
-   *
-   * One can possibly factorize 128 and br. However, since the last
-   * 6 bits of CLKDIV are don't care, we can base our integer arithmetic
-   * on the below formula without loosing any extra precision:
-   *
-   * CLKDIV / 64 = (2 * fHFPERCLK)/br - 4
-   *
-   * and calculate 1/64 of CLKDIV first. This allows for fHFPERCLK
-   * up to 2GHz without overflowing a 32 bit value!
    */
 
   /* HFPERCLK used to clock all USART/UART peripheral modules */
@@ -480,6 +492,14 @@
     refFreq = CMU_ClockFreqGet(cmuClock_HFPER);
   }
 
+#if defined(_USART_CLKDIV_DIV_MASK) && (_USART_CLKDIV_DIV_MASK >= 0x7FFFF8UL)
+  /* Calculate and set CLKDIV without fractional bits */
+  clkdiv = 2 * baudrate;
+  clkdiv = (0x100ULL * (uint64_t)refFreq) / clkdiv;
+
+  /* Round up by not subtracting 256 and mask off fractional part */
+  clkdiv &= ~0xFF;
+#else
   /* Calculate and set CLKDIV with fractional bits */
   clkdiv  = 2 * refFreq;
   clkdiv += baudrate - 1;
@@ -491,14 +511,15 @@
   /* specified value). */
   clkdiv += 0xc0;
   clkdiv &= 0xffffff00;
+#endif
 
   /* Verify that resulting clock divider is within limits */
-  EFM_ASSERT(clkdiv <= _USART_CLKDIV_MASK);
+  EFM_ASSERT(!(clkdiv & ~_USART_CLKDIV_DIV_MASK));
 
   /* If EFM_ASSERT is not enabled, make sure we don't write to reserved bits */
   clkdiv &= _USART_CLKDIV_DIV_MASK;
 
-  usart->CLKDIV = clkdiv;
+  BUS_RegMaskedWrite(&usart->CLKDIV, _USART_CLKDIV_DIV_MASK, clkdiv);
 }
 
 
@@ -584,15 +605,25 @@
 #endif
 
   /* Configure databits, stopbits and parity */
-  usart->FRAME = (uint32_t) (init->databits) |
-                 (uint32_t) (init->stopbits) |
-                 (uint32_t) (init->parity);
+  usart->FRAME = (uint32_t)init->databits
+                 | (uint32_t)init->stopbits
+                 | (uint32_t)init->parity;
 
   /* Configure baudrate */
   USART_BaudrateAsyncSet(usart, init->refFreq, init->baudrate, init->oversampling);
 
+#if defined(_USART_TIMING_CSHOLD_MASK)
+  usart->TIMING = ((init->autoCsHold << _USART_TIMING_CSHOLD_SHIFT)
+                   & _USART_TIMING_CSHOLD_MASK)
+                  | ((init->autoCsSetup << _USART_TIMING_CSSETUP_SHIFT)
+                     & _USART_TIMING_CSSETUP_MASK);
+  if (init->autoCsEnable)
+  {
+    usart->CTRL |= USART_CTRL_AUTOCS;
+  }
+#endif
   /* Finally enable (as specified) */
-  usart->CMD = (uint32_t) (init->enable);
+  usart->CMD = (uint32_t)init->enable;
 }
 
 
@@ -629,19 +660,26 @@
   USART_Reset(usart);
 
   /* Set bits for synchronous mode */
-  usart->CTRL |= (USART_CTRL_SYNC) |
-                 ((uint32_t) init->clockMode) |
-                 (init->msbf ? USART_CTRL_MSBF : 0);
+  usart->CTRL |= (USART_CTRL_SYNC)
+                 | (uint32_t)init->clockMode
+                 | (init->msbf ? USART_CTRL_MSBF : 0);
 
-#if defined(USART_INPUT_RXPRS) && defined(USART_TRIGCTRL_AUTOTXTEN)
-  usart->CTRL |= (init->prsRxEnable ? USART_INPUT_RXPRS : 0) |
-                 (init->autoTx      ? USART_CTRL_AUTOTX : 0);
+#if defined(_USART_CTRL_AUTOTX_MASK)
+  usart->CTRL |= init->autoTx ? USART_CTRL_AUTOTX : 0;
+#endif
+
+#if defined(_USART_INPUT_RXPRS_MASK)
+  /* Configure PRS input mode. */
+  if (init->prsRxEnable)
+  {
+    usart->INPUT = (uint32_t)init->prsRxCh | USART_INPUT_RXPRS;
+  }
 #endif
 
   /* Configure databits, leave stopbits and parity at reset default (not used) */
-  usart->FRAME = ((uint32_t) (init->databits)) |
-                 (USART_FRAME_STOPBITS_DEFAULT) |
-                 (USART_FRAME_PARITY_DEFAULT);
+  usart->FRAME = (uint32_t)init->databits
+                 | USART_FRAME_STOPBITS_DEFAULT
+                 | USART_FRAME_PARITY_DEFAULT;
 
   /* Configure baudrate */
   USART_BaudrateSyncSet(usart, init->refFreq, init->baudrate);
@@ -652,7 +690,18 @@
     usart->CMD = USART_CMD_MASTEREN;
   }
 
-  usart->CMD = (uint32_t) (init->enable);
+#if defined(_USART_TIMING_CSHOLD_MASK)
+  usart->TIMING = ((init->autoCsHold << _USART_TIMING_CSHOLD_SHIFT)
+                   & _USART_TIMING_CSHOLD_MASK)
+                  | ((init->autoCsSetup << _USART_TIMING_CSSETUP_SHIFT)
+                     & _USART_TIMING_CSSETUP_MASK);
+  if (init->autoCsEnable)
+  {
+    usart->CTRL |= USART_CTRL_AUTOCS;
+  }
+#endif
+
+  usart->CMD = (uint32_t)init->enable;
 }
 
 
@@ -704,10 +753,10 @@
   }
 
   /* Configure IrDA */
-  usart->IRCTRL |= (uint32_t) init->irPw |
-                   (uint32_t) init->irPrsSel |
-                   ((uint32_t) init->irFilt << _USART_IRCTRL_IRFILT_SHIFT) |
-                   ((uint32_t) init->irPrsEn << _USART_IRCTRL_IRPRSEN_SHIFT);
+  usart->IRCTRL |= (uint32_t)init->irPw
+                   | (uint32_t)init->irPrsSel
+                   | ((uint32_t)init->irFilt << _USART_IRCTRL_IRFILT_SHIFT)
+                   | ((uint32_t)init->irPrsEn << _USART_IRCTRL_IRPRSEN_SHIFT);
 
   /* Enable IrDA */
   usart->IRCTRL |= USART_IRCTRL_IREN;
@@ -760,12 +809,12 @@
   USART_InitSync(usart, &init->sync);
 
   /* Configure and enable I2CCTRL register acording to selected mode. */
-  usart->I2SCTRL = ((uint32_t) init->format) |
-                   ((uint32_t) init->justify) |
-                   (init->delay    ? USART_I2SCTRL_DELAY    : 0) |
-                   (init->dmaSplit ? USART_I2SCTRL_DMASPLIT : 0) |
-                   (init->mono     ? USART_I2SCTRL_MONO     : 0) |
-                   (USART_I2SCTRL_EN);
+  usart->I2SCTRL = (uint32_t)init->format
+                   | (uint32_t)init->justify
+                   | (init->delay    ? USART_I2SCTRL_DELAY    : 0)
+                   | (init->dmaSplit ? USART_I2SCTRL_DMASPLIT : 0)
+                   | (init->mono     ? USART_I2SCTRL_MONO     : 0)
+                   | USART_I2SCTRL_EN;
 
   if (enable != usartDisable)
   {
@@ -789,12 +838,12 @@
   uint32_t trigctrl;
 
   /* Clear values that will be reconfigured  */
-  trigctrl = usart->TRIGCTRL & ~(_USART_TRIGCTRL_RXTEN_MASK |
-                                 _USART_TRIGCTRL_TXTEN_MASK |
+  trigctrl = usart->TRIGCTRL & ~(_USART_TRIGCTRL_RXTEN_MASK
+                                 | _USART_TRIGCTRL_TXTEN_MASK
 #if defined(USART_TRIGCTRL_AUTOTXTEN)
-                                 _USART_TRIGCTRL_AUTOTXTEN_MASK |
+                                 | _USART_TRIGCTRL_AUTOTXTEN_MASK
 #endif
-                                 _USART_TRIGCTRL_TSEL_MASK);
+                                 | _USART_TRIGCTRL_TSEL_MASK);
 
 #if defined(USART_TRIGCTRL_AUTOTXTEN)
   if (init->autoTxTriggerEnable)
@@ -832,15 +881,22 @@
               || UART_REF_VALID(usart) );
 
   /* Make sure disabled first, before resetting other registers */
-  usart->CMD = USART_CMD_RXDIS | USART_CMD_TXDIS | USART_CMD_MASTERDIS |
-               USART_CMD_RXBLOCKDIS | USART_CMD_TXTRIDIS | USART_CMD_CLEARTX | USART_CMD_CLEARRX;
-  usart->CTRL     = _USART_CTRL_RESETVALUE;
-  usart->FRAME    = _USART_FRAME_RESETVALUE;
-  usart->TRIGCTRL = _USART_TRIGCTRL_RESETVALUE;
-  usart->CLKDIV   = _USART_CLKDIV_RESETVALUE;
-  usart->IEN      = _USART_IEN_RESETVALUE;
-  usart->IFC      = _USART_IFC_MASK;
-  usart->ROUTE    = _USART_ROUTE_RESETVALUE;
+  usart->CMD = USART_CMD_RXDIS | USART_CMD_TXDIS | USART_CMD_MASTERDIS
+               | USART_CMD_RXBLOCKDIS | USART_CMD_TXTRIDIS | USART_CMD_CLEARTX
+               | USART_CMD_CLEARRX;
+  usart->CTRL      = _USART_CTRL_RESETVALUE;
+  usart->FRAME     = _USART_FRAME_RESETVALUE;
+  usart->TRIGCTRL  = _USART_TRIGCTRL_RESETVALUE;
+  usart->CLKDIV    = _USART_CLKDIV_RESETVALUE;
+  usart->IEN       = _USART_IEN_RESETVALUE;
+  usart->IFC       = _USART_IFC_MASK;
+#if defined(_USART_ROUTEPEN_MASK) || defined(_UART_ROUTEPEN_MASK)
+  usart->ROUTEPEN  = _USART_ROUTEPEN_RESETVALUE;
+  usart->ROUTELOC0 = _USART_ROUTELOC0_RESETVALUE;
+  usart->ROUTELOC1 = _USART_ROUTELOC1_RESETVALUE;
+#else
+  usart->ROUTE     = _USART_ROUTE_RESETVALUE;
+#endif
 
   if (USART_IRDA_VALID(usart))
   {
@@ -889,7 +945,7 @@
   while (!(usart->STATUS & USART_STATUS_RXDATAV))
     ;
 
-  return (uint8_t) (usart->RXDATA);
+  return (uint8_t)usart->RXDATA;
 }
 
 
@@ -922,7 +978,7 @@
   while (!(usart->STATUS & USART_STATUS_RXFULL))
     ;
 
-  return (uint16_t) (usart->RXDOUBLE);
+  return (uint16_t)usart->RXDOUBLE;
 }
 
 
@@ -988,7 +1044,7 @@
   while (!(usart->STATUS & USART_STATUS_RXDATAV))
     ;
 
-  return (uint16_t) (usart->RXDATAX);
+  return (uint16_t)usart->RXDATAX;
 }
 
 
@@ -1015,10 +1071,10 @@
 {
   while (!(usart->STATUS & USART_STATUS_TXBL))
     ;
-  usart->TXDATA = (uint32_t) data;
+  usart->TXDATA = (uint32_t)data;
   while (!(usart->STATUS & USART_STATUS_TXC))
     ;
-  return (uint8_t) (usart->RXDATA);
+  return (uint8_t)usart->RXDATA;
 }
 
 
@@ -1050,7 +1106,7 @@
   /* Check that transmit buffer is empty */
   while (!(usart->STATUS & USART_STATUS_TXBL))
     ;
-  usart->TXDATA = (uint32_t) data;
+  usart->TXDATA = (uint32_t)data;
 }
 
 
@@ -1086,7 +1142,7 @@
   /* Check that transmit buffer is empty */
   while (!(usart->STATUS & USART_STATUS_TXBL))
     ;
-  usart->TXDOUBLE = (uint32_t) data;
+  usart->TXDOUBLE = (uint32_t)data;
 }
 
 
@@ -1113,7 +1169,7 @@
  *   If frame length is 10-16 bits, 8 data bits are taken from the least
  *   significant 16 bit word, and the remaining bits from the other 16 bit word.
  * @par
- *   Additional control bits are available as documented in the EFM32 reference
+ *   Additional control bits are available as documented in the reference
  *   manual (set to 0 if not used). For 10-16 bit frame length, these control
  *   bits are taken from the most significant 16 bit word.
  ******************************************************************************/
@@ -1143,14 +1199,14 @@
  * @param[in] data
  *   Data to transmit with extended control. Least significant bits contains
  *   frame bits, and additional control bits are available as documented in
- *   the EFM32 reference manual (set to 0 if not used).
+ *   the reference manual (set to 0 if not used).
  ******************************************************************************/
 void USART_TxExt(USART_TypeDef *usart, uint16_t data)
 {
   /* Check that transmit buffer is empty */
   while (!(usart->STATUS & USART_STATUS_TXBL))
     ;
-  usart->TXDATAX = (uint32_t) data;
+  usart->TXDATAX = (uint32_t)data;
 }
 
 

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_vcmp.c	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_vcmp.c	Fri Jan 15 07:45:16 2016 +0000
@@ -1,10 +1,10 @@
 /***************************************************************************//**
  * @file em_vcmp.c
  * @brief Voltage Comparator (VCMP) peripheral API
- * @version 3.20.12
+ * @version 4.2.1
  *******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
  *******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -30,7 +30,6 @@
  *
  ******************************************************************************/
 
-
 #include "em_vcmp.h"
 #if defined(VCMP_COUNT) && (VCMP_COUNT > 0)
 
@@ -101,14 +100,14 @@
   /* Configure hysteresis */
   switch (vcmpInit->hyst)
   {
-  case vcmpHyst20mV:
-    VCMP->CTRL |= VCMP_CTRL_HYSTEN;
-    break;
-  case vcmpHystNone:
-    VCMP->CTRL &= ~(VCMP_CTRL_HYSTEN);
-    break;
-  default:
-    break;
+    case vcmpHyst20mV:
+      VCMP->CTRL |= VCMP_CTRL_HYSTEN;
+      break;
+    case vcmpHystNone:
+      VCMP->CTRL &= ~(VCMP_CTRL_HYSTEN);
+      break;
+    default:
+      break;
   }
 
   /* Configure inactive output value */
@@ -157,7 +156,7 @@
   }
   else
   {
-    VCMP->INPUTSEL &= ~(VCMP_INPUTSEL_LPREF);
+    VCMP->INPUTSEL &= ~VCMP_INPUTSEL_LPREF;
   }
 }
 
@@ -175,8 +174,8 @@
   EFM_ASSERT((level > 0) && (level < 64));
 
   /* Set trigger level */
-  VCMP->INPUTSEL = (VCMP->INPUTSEL & ~(_VCMP_INPUTSEL_TRIGLEVEL_MASK)) |
-                   (level << _VCMP_INPUTSEL_TRIGLEVEL_SHIFT);
+  VCMP->INPUTSEL = (VCMP->INPUTSEL & ~(_VCMP_INPUTSEL_TRIGLEVEL_MASK))
+                   | (level << _VCMP_INPUTSEL_TRIGLEVEL_SHIFT);
 }
 
 

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_wdog.c	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_wdog.c	Fri Jan 15 07:45:16 2016 +0000
@@ -2,10 +2,10 @@
  * @file em_wdog.c
  * @brief Watchdog (WDOG) peripheral API
  *   devices.
- * @version 3.20.12
+ * @version 4.2.1
  *******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
  *******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -31,11 +31,17 @@
  *
  ******************************************************************************/
 
-
 #include "em_wdog.h"
 #if defined(WDOG_COUNT) && (WDOG_COUNT > 0)
 
-#include "em_bitband.h"
+#if defined(WDOG0)
+#define WDOG WDOG0
+#if (WDOG_COUNT > 1)
+#warning "Multiple watchdogs not supported"
+#endif
+#endif
+
+#include "em_bus.h"
 
 /***************************************************************************//**
  * @addtogroup EM_Library
@@ -75,7 +81,7 @@
     while (WDOG->SYNCBUSY & WDOG_SYNCBUSY_CTRL)
       ;
   }
-  BITBAND_Peripheral(&(WDOG->CTRL), _WDOG_CTRL_EN_SHIFT, (unsigned int)enable);
+  BUS_RegBitWrite(&(WDOG->CTRL), _WDOG_CTRL_EN_SHIFT, enable);
 }
 
 
@@ -104,9 +110,10 @@
   {
     return;
   }
-  /* Before writing to the WDOG_CMD register we also need to make sure that 
+  /* Before writing to the WDOG_CMD register we also need to make sure that
    * any previous write to WDOG_CTRL is complete. */
-  while ( WDOG->SYNCBUSY & WDOG_SYNCBUSY_CTRL );
+  while ( WDOG->SYNCBUSY & WDOG_SYNCBUSY_CTRL )
+    ;
 
   WDOG->CMD = WDOG_CMD_CLEAR;
 }
@@ -165,8 +172,8 @@
     setting |= WDOG_CTRL_SWOSCBLOCK;
   }
 
-  setting |= ((uint32_t)(init->clkSel) << _WDOG_CTRL_CLKSEL_SHIFT) |
-             ((uint32_t)(init->perSel) << _WDOG_CTRL_PERSEL_SHIFT);
+  setting |= ((uint32_t)(init->clkSel)   << _WDOG_CTRL_CLKSEL_SHIFT)
+             | ((uint32_t)(init->perSel) << _WDOG_CTRL_PERSEL_SHIFT);
 
   /* Wait for any pending previous write operation to have been completed in */
   /* low frequency domain */
@@ -184,7 +191,7 @@
     }
     else
     {
-      BITBAND_Peripheral(&(WDOG->CTRL), _WDOG_CTRL_LOCK_SHIFT, 1);
+      BUS_RegBitWrite(&(WDOG->CTRL), _WDOG_CTRL_LOCK_SHIFT, 1);
     }
   }
 }
@@ -216,7 +223,7 @@
     ;
 
   /* Disable writing to the control register */
-  BITBAND_Peripheral(&(WDOG->CTRL), _WDOG_CTRL_LOCK_SHIFT, 1);
+  BUS_RegBitWrite(&(WDOG->CTRL), _WDOG_CTRL_LOCK_SHIFT, 1);
 }
 
 

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/gpio_api.c	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/gpio_api.c	Fri Jan 15 07:45:16 2016 +0000
@@ -55,7 +55,7 @@
 
 int gpio_is_connected(const gpio_t *obj)
 {
-    return (obj->pin | 0xFFFFFF00 )!= (PinName)NC;
+    return ((uint32_t)obj->pin | 0xFFFFFF00 ) != (uint32_t)((PinName)NC);
 }
 
 /*
@@ -80,7 +80,10 @@
 
 void gpio_mode(gpio_t *obj, PinMode mode)
 {
-        if(obj->dir == PIN_INPUT) {
+    uint32_t pin = 1 << (obj->pin & 0xF);
+    uint32_t port = (obj->pin >> 4) & 0xF;
+
+    if(obj->dir == PIN_INPUT) {
         switch(mode) {
             case PullDefault:
                 mode = Input;
@@ -94,14 +97,22 @@
             default:
                 break;
         }
-        
+
         //Handle DOUT setting
         if((mode & 0x10) != 0) {
             //Set DOUT
-            GPIO->P[(obj->pin >> 4) & 0xF].DOUTSET = 1 << (obj->pin & 0xF);
+#ifdef _GPIO_P_DOUTSET_MASK
+            GPIO->P[port].DOUTSET = pin;
+#else
+            GPIO->P[port].DOUT |= pin;
+#endif
         } else {
             //Clear DOUT
-            GPIO->P[(obj->pin >> 4) & 0xF].DOUTCLR = 1 << (obj->pin & 0xF);
+#ifdef _GPIO_P_DOUTCLR_MASK
+            GPIO->P[port].DOUTCLR = pin;
+#else
+            GPIO->P[port].DOUT &= ~pin;
+#endif
         }
     } else {
         switch(mode) {
@@ -118,7 +129,7 @@
                 break;
         }
     }
-    
+
     obj->mode = mode; // Update object
     pin_mode(obj->pin, mode); // Update register
 }

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/gpio_irq_api.c	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/gpio_irq_api.c	Fri Jan 15 07:45:16 2016 +0000
@@ -147,7 +147,7 @@
     bool was_disabled = false;
     if(GPIO->IEN == 0) was_disabled = true;
 
-    GPIO_IntConfig((GPIO_Port_TypeDef)(obj->pin >> 4 & 0xF), obj->pin &0xF, obj->risingEdge, obj->fallingEdge, obj->risingEdge || obj->fallingEdge);
+    GPIO_IntConfig((GPIO_Port_TypeDef)((obj->pin >> 4) & 0xF), obj->pin &0xF, obj->risingEdge, obj->fallingEdge, obj->risingEdge || obj->fallingEdge);
     if ((GPIO->IEN != 0) && (obj->risingEdge || obj->fallingEdge) && was_disabled) {
         blockSleepMode(GPIO_LEAST_ACTIVE_SLEEPMODE);
     }
@@ -156,12 +156,12 @@
 inline void gpio_irq_enable(gpio_irq_t *obj)
 {
     if(GPIO->IEN == 0) blockSleepMode(GPIO_LEAST_ACTIVE_SLEEPMODE);
-    GPIO_IntEnable(1 << obj->pin & 0xF); // pin mask for pins to enable
+    GPIO_IntEnable(1 << (obj->pin & 0xF)); // pin mask for pins to enable
 }
 
 inline void gpio_irq_disable(gpio_irq_t *obj)
 {
-    GPIO_IntDisable(1 << obj->pin & 0xF); // pin mask for pins to disable
+    GPIO_IntDisable(1 << (obj->pin & 0xF)); // pin mask for pins to disable
     if(GPIO->IEN == 0) unblockSleepMode(GPIO_LEAST_ACTIVE_SLEEPMODE);
 }
 

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/i2c_api.c	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/i2c_api.c	Fri Jan 15 07:45:16 2016 +0000
@@ -100,26 +100,14 @@
     return clock;
 }
 
-void i2c_preinit(i2c_t *obj, PinName sda, PinName scl)
+void i2c_init(i2c_t *obj, PinName sda, PinName scl)
 {
+    /* Find out which I2C peripheral we're asked to use */
     I2CName i2c_sda = (I2CName) pinmap_peripheral(sda, PinMap_I2C_SDA);
     I2CName i2c_scl = (I2CName) pinmap_peripheral(scl, PinMap_I2C_SCL);
     obj->i2c.i2c = (I2C_TypeDef*) pinmap_merge(i2c_sda, i2c_scl);
     MBED_ASSERT(((int) obj->i2c.i2c) != NC);
 
-    int loc_sda = pin_location(sda, PinMap_I2C_SDA);
-    int loc_scl = pin_location(scl, PinMap_I2C_SCL);
-    obj->i2c.loc = pinmap_merge(loc_sda, loc_scl);
-    MBED_ASSERT(obj->i2c.loc != NC);
-    obj->i2c.sda = sda;
-    obj->i2c.scl = scl;
-}
-
-void i2c_init(i2c_t *obj, PinName sda, PinName scl)
-{
-    /* Assign mbed pins */
-    i2c_preinit(obj, sda, scl);
-
     /* Enable clock for the peripheral */
     CMU_ClockEnable(i2c_get_clock(obj), true);
 
@@ -129,8 +117,23 @@
     I2C_Init(obj->i2c.i2c, &i2cInit);
 
     /* Enable pins at correct location */
-    obj->i2c.i2c->ROUTE = I2C_ROUTE_SDAPEN | I2C_ROUTE_SCLPEN | (obj->i2c.loc << _I2C_ROUTE_LOCATION_SHIFT);
-    i2c_enable_pins(obj, true);
+#ifdef I2C_ROUTE_SDAPEN
+    /* Find common location in pinmap */
+    int loc_sda = pin_location(sda, PinMap_I2C_SDA);
+    int loc_scl = pin_location(scl, PinMap_I2C_SCL);
+    int loc = pinmap_merge(loc_sda, loc_scl);
+    MBED_ASSERT(loc != NC);
+    /* Set location */
+    obj->i2c.i2c->ROUTE = I2C_ROUTE_SDAPEN | I2C_ROUTE_SCLPEN | (loc << _I2C_ROUTE_LOCATION_SHIFT);
+#else
+    obj->i2c.i2c->ROUTEPEN  = I2C_ROUTEPEN_SDAPEN | I2C_ROUTEPEN_SCLPEN;
+    obj->i2c.i2c->ROUTELOC0 = (pin_location(sda, PinMap_I2C_SDA) << _I2C_ROUTELOC0_SDALOC_SHIFT) |
+                              (pin_location(scl, PinMap_I2C_SCL) << _I2C_ROUTELOC0_SCLLOC_SHIFT);
+#endif
+
+    /* Set up the pins for I2C use */
+    pin_mode(scl, WiredAndPullUp);
+    pin_mode(sda, WiredAndPullUp);
 
     /* Enable General Call Address Mode. That is; we respond to the general address (0x0) */
     obj->i2c.i2c->CTRL |= _I2C_CTRL_GCAMEN_MASK;
@@ -138,6 +141,9 @@
     /* We are assuming that there is only one master. So disable automatic arbitration */
     obj->i2c.i2c->CTRL |= _I2C_CTRL_ARBDIS_MASK;
 
+    /* Set to master (needed if this I2C block was used previously as slave) */
+    i2c_slave_mode(obj, false);
+
     /* Enable i2c */
     i2c_enable(obj, true);
 }
@@ -151,19 +157,6 @@
         if (obj->i2c.i2c->STATE & I2C_STATE_BUSY) {
             obj->i2c.i2c->CMD = I2C_CMD_ABORT;
         }
-
-    }
-}
-
-void i2c_enable_pins(i2c_t *obj, uint8_t enable)
-{
-    if (enable) {
-        pin_mode(obj->i2c.scl, WiredAndPullUp);
-        pin_mode(obj->i2c.sda, WiredAndPullUp);
-    } else {
-        // TODO_LP return PinMode to the previous state
-        pin_mode(obj->i2c.sda, Disabled);
-        pin_mode(obj->i2c.scl, Disabled);
     }
 }
 

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/lp_ticker.c	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/lp_ticker.c	Fri Jan 15 07:45:16 2016 +0000
@@ -35,18 +35,46 @@
 #include "rtc_api_HAL.h"
 #include "lp_ticker_api.h"
 
+#include "em_int.h"
+#if (defined RTCC_COUNT) && (RTCC_COUNT > 0)
+#include "em_rtcc.h"
+#endif
+
+static int rtc_reserved = 0;
+
 void lp_ticker_init()
 {
-    rtc_init_real(RTC_INIT_LPTIMER);
-    rtc_set_comp0_handler((uint32_t)lp_ticker_irq_handler);
+    if(!rtc_reserved) {
+        INT_Disable();
+        rtc_init_real(RTC_INIT_LPTIMER);
+        rtc_set_comp0_handler((uint32_t)lp_ticker_irq_handler);
+        rtc_reserved = 1;
+        INT_Enable();
+    }
 }
 
+void lp_ticker_free()
+{
+    if(rtc_reserved) {
+        INT_Disable();
+        rtc_free_real(RTC_INIT_LPTIMER);
+        rtc_reserved = 0;
+        INT_Enable();
+    }
+}
+
+#ifndef RTCC_COUNT
+
+/* RTC API */
+
 void lp_ticker_set_interrupt(timestamp_t timestamp)
 {
     uint64_t timestamp_ticks;
     uint64_t current_ticks = RTC_CounterGet();
     timestamp_t current_time = ((uint64_t)(current_ticks * 1000000) / (LOW_ENERGY_CLOCK_FREQUENCY / RTC_CLOCKDIV_INT));
 
+    /* Initialize RTC */
+    lp_ticker_init();
 
     /* calculate offset value */
     timestamp_t offset = timestamp - current_time;
@@ -73,6 +101,7 @@
 inline void lp_ticker_disable_interrupt()
 {
     RTC_IntDisable(RTC_IF_COMP0);
+    lp_ticker_free();
 }
 
 inline void lp_ticker_clear_interrupt()
@@ -82,6 +111,8 @@
 
 timestamp_t lp_ticker_read()
 {
+    lp_ticker_init();
+    
     uint64_t ticks_temp;
     uint64_t ticks = RTC_CounterGet();
 
@@ -94,4 +125,75 @@
     return (timestamp_t) (ticks_temp & 0xFFFFFFFF);
 }
 
+#else
+
+/* RTCC API */
+
+void lp_ticker_set_interrupt(timestamp_t timestamp)
+{
+    uint64_t timestamp_ticks;
+    uint64_t current_ticks = RTCC_CounterGet();
+    timestamp_t current_time = ((uint64_t)(current_ticks * 1000000) / (LOW_ENERGY_CLOCK_FREQUENCY / RTC_CLOCKDIV_INT));
+
+    /* Initialize RTC */
+    lp_ticker_init();
+
+    /* calculate offset value */
+    timestamp_t offset = timestamp - current_time;
+    if(offset > 0xEFFFFFFF) offset = 100;
+
+    /* map offset to RTC value */
+    // ticks = offset * RTC frequency div 1000000
+    timestamp_ticks = ((uint64_t)offset * (LOW_ENERGY_CLOCK_FREQUENCY / RTC_CLOCKDIV_INT)) / 1000000;
+    // checking the rounding. If timeout is wanted between RTCC ticks, irq should be configured to
+    // trigger in the latter RTCC-tick. Otherwise ticker-api fails to send timer event to its client
+    if(((timestamp_ticks * 1000000) / (LOW_ENERGY_CLOCK_FREQUENCY / RTC_CLOCKDIV_INT)) < offset){
+        timestamp_ticks++;
+    }
+
+    timestamp_ticks += current_ticks;
+
+    /* RTCC has 32 bit resolution */
+    timestamp_ticks &= 0xFFFFFFFF;
+
+    /* check for RTCC limitation */
+    if((timestamp_ticks - RTCC_CounterGet()) >= 0x80000000) timestamp_ticks = RTCC_CounterGet() + 2;
+
+    /* init channel */
+    RTCC_CCChConf_TypeDef ccchConf = RTCC_CH_INIT_COMPARE_DEFAULT;
+    RTCC_ChannelInit(0,&ccchConf);
+    /* Set callback */
+    RTCC_ChannelCCVSet(0, (uint32_t)timestamp_ticks);
+    RTCC_IntEnable(RTCC_IF_CC0);
+}
+
+inline void lp_ticker_disable_interrupt()
+{
+    RTCC_IntDisable(RTCC_IF_CC0);
+    lp_ticker_free();
+}
+
+inline void lp_ticker_clear_interrupt()
+{
+    RTCC_IntClear(RTCC_IF_CC0);
+}
+
+timestamp_t lp_ticker_read()
+{
+    lp_ticker_init();
+    
+    uint64_t ticks_temp;
+    uint64_t ticks = RTCC_CounterGet();
+
+    /* ticks = counter tick value
+     * timestamp = value in microseconds
+     * timestamp = ticks * 1.000.000 / RTC frequency
+     */
+
+    ticks_temp = (ticks * 1000000) / (LOW_ENERGY_CLOCK_FREQUENCY / RTC_CLOCKDIV_INT);
+    return (timestamp_t) (ticks_temp & 0xFFFFFFFF);
+}
+
+#endif /* RTCC */
+
 #endif

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/mbed_overrides.c	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/mbed_overrides.c	Fri Jan 15 07:45:16 2016 +0000
@@ -39,86 +39,75 @@
 
 gpio_t bc_enable;
 
-void check_usart_clock(USART_TypeDef* usart, uint32_t clockmask);
-
 /* Called before main - implement here if board needs it.
  * Otherwise, let the application override this if necessary */
 void mbed_sdk_init()
 {
     CHIP_Init();
 
+#if defined(_SILICON_LABS_32B_PLATFORM_2)
+    EMU_DCDCInit_TypeDef dcdcInit = EMU_DCDCINIT_DEFAULT;
+    EMU_DCDCInit(&dcdcInit);
+#endif
+
     /* Set up the clock sources for this chip */
 #if( CORE_CLOCK_SOURCE == HFXO)
     CMU_ClockSelectSet(cmuClock_HF, cmuSelect_HFXO);
     SystemHFXOClockSet(HFXO_FREQUENCY);
 #elif( CORE_CLOCK_SOURCE == HFRCO)
     CMU_ClockSelectSet(cmuClock_HF, cmuSelect_HFRCO);
+# if defined _CMU_HFRCOCTRL_BAND_MASK
     CMU_HFRCOBandSet(HFRCO_FREQUENCY);
+# elif defined _CMU_HFRCOCTRL_FREQRANGE_MASK
+    CMU_HFRCOFreqSet(HFRCO_FREQUENCY_ENUM);
+# else
+#  error "Can't set HFRCO frequency"
+# endif
 #else
-#error "Core clock selection not valid (mbed_overrides.c)"
+# error "Core clock selection not valid (mbed_overrides.c)"
 #endif
 
     CMU_ClockEnable(cmuClock_CORELE, true);
 
 #if( LOW_ENERGY_CLOCK_SOURCE == LFXO )
-#ifdef CMU_LFACLKSEL_REG
+# ifdef _CMU_LFACLKEN0_MASK
     CMU_ClockSelectSet(cmuClock_LFA, cmuSelect_LFXO);
-#endif
-#ifdef CMU_LFBCLKSEL_REG
+# endif
+# ifdef _CMU_LFBCLKEN0_MASK
     /* cmuClock_LFB (to date) only has LEUART peripherals.
     *  This gets set automatically whenever you create serial objects using LEUART
     */
-#endif
-#ifdef CMU_LFECLKSEL_REG
+# endif
+# ifdef _CMU_LFECLKEN0_MASK
     CMU_ClockSelectSet(cmuClock_LFE, cmuSelect_LFXO);
-#endif
+# endif
     SystemLFXOClockSet(LFXO_FREQUENCY);
 
 #elif( LOW_ENERGY_CLOCK_SOURCE == LFRCO )
-#ifdef CMU_LFACLKSEL_REG
+# ifdef _CMU_LFACLKEN0_MASK
     CMU_ClockSelectSet(cmuClock_LFA, cmuSelect_LFRCO);
-#endif
-#ifdef CMU_LFBCLKSEL_REG
+# endif
+# ifdef _CMU_LFBCLKEN0_MASK
     //CMU_ClockSelectSet(cmuClock_LFB, cmuSelect_LFRCO);
-#endif
-#ifdef CMU_LFECLKSEL_REG
+# endif
+# ifdef _CMU_LFECLKEN0_MASK
     CMU_ClockSelectSet(cmuClock_LFE, cmuSelect_LFRCO);
-#endif
-    CMU_HFRCOBandSet(HFRCO_FREQUENCY);
+# endif
 
 #elif( LOW_ENERGY_CLOCK_SOURCE == ULFRCO)
-#ifdef CMU_LFACLKSEL_REG
+# ifdef _CMU_LFACLKEN0_MASK
     CMU_ClockSelectSet(cmuClock_LFA, cmuSelect_ULFRCO);
-#endif
-#ifdef CMU_LFBCLKSEL_REG
+# endif
+# ifdef _CMU_LFBCLKEN0_MASK
     CMU_ClockSelectSet(cmuClock_LFB, cmuSelect_ULFRCO);
-#endif
-#ifdef CMU_LFECLKSEL_REG
+# endif
+# ifdef _CMU_LFECLKEN0_MASK
     CMU_ClockSelectSet(cmuClock_LFE, cmuSelect_ULFRCO);
-#endif
+# endif
 #else
-#error "Low energy clock selection not valid"
+# error "Low energy clock selection not valid"
 #endif
 
     /* Enable BC line driver to avoid garbage on CDC port */
     gpio_init_out_ex(&bc_enable, EFM_BC_EN, 1);
 }
-
-void check_usart_clock(USART_TypeDef* usart, uint32_t clockmask)
-{
-    uint32_t freq = 14000000, baudrate;
-    USART_OVS_TypeDef ovs;
-
-    if(CMU->HFPERCLKEN0 & clockmask) {
-        /* Different methods for sync vs async */
-        if(usart->CTRL & USART_CTRL_SYNC) {
-            ovs  = (USART_OVS_TypeDef) (usart->CTRL & _USART_CTRL_OVS_MASK);
-            baudrate = USART_BaudrateCalc(freq, usart->CLKDIV, true, ovs);
-            USART_BaudrateSyncSet(usart, 0, baudrate);
-        } else {
-            ovs  = (USART_OVS_TypeDef) (usart->CTRL & _USART_CTRL_OVS_MASK);
-            baudrate = USART_BaudrateCalc(freq, usart->CLKDIV, false, ovs);
-            USART_BaudrateAsyncSet(usart, 0, baudrate, ovs);
-        }
-    }
-}

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/objects.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/objects.h	Fri Jan 15 07:45:16 2016 +0000
@@ -66,11 +66,6 @@
 #if DEVICE_I2C
 struct i2c_s {
     I2C_TypeDef *i2c;
-    int loc;
-    uint8_t index;
-    PinName sda;
-    PinName scl;
-    uint32_t clock;
 #if DEVICE_I2C_ASYNCH
     uint32_t events;
     I2C_TransferSeq_TypeDef xfer;
@@ -88,10 +83,6 @@
 
 #if DEVICE_PWMOUT
 struct pwmout_s {
-    //The period of the pulse in clock cycles
-    uint16_t period_cycles;
-    //The width of the pulse in clock cycles
-    uint16_t width_cycles;
     //Channel on TIMER
     uint32_t channel;
     PinName pin;
@@ -107,14 +98,17 @@
 #endif
 
 #if DEVICE_SERIAL
-#define SERIAL_NUM_UARTS (7)
-
 struct serial_s {
     union {
         USART_TypeDef *uart;
         LEUART_TypeDef *leuart;
     } periph;
+#ifndef _SILICON_LABS_32B_PLATFORM_2
     uint32_t location;
+#else
+    uint32_t location_tx;
+    uint32_t location_rx;
+#endif
     PinName rx_pin;
     PinName tx_pin;
 #if DEVICE_SERIAL_ASYNCH
@@ -122,6 +116,7 @@
     DMA_OPTIONS_t dmaOptionsTX;
     DMA_OPTIONS_t dmaOptionsRX;
 #endif
+    uint32_t sleep_blocked;
 };
 #endif
 

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/port_api.c	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/port_api.c	Fri Jan 15 07:45:16 2016 +0000
@@ -39,26 +39,17 @@
 
 #define PORT_NUM_PINS 16
 
-uint8_t port_get_index(port_t *obj)
-{
-    return 0;
-}
-
 PinName port_pin(PortName port, int pin_n)
 {
     return (PinName) (pin_n | port << 4); // Encode pin and port number in one uint32
 }
 
-void port_preinit(port_t *obj, PortName port, int mask, PinDirection dir)
+void port_init(port_t *obj, PortName port, int mask, PinDirection dir)
 {
     obj->mask = mask;
     obj->port = port;
     obj->dir = dir;
-}
-
-void port_init(port_t *obj, PortName port, int mask, PinDirection dir)
-{
-    port_preinit(obj, port, mask, dir);
+    
     port_dir(obj, obj->dir);
 }
 
@@ -80,21 +71,17 @@
     /* Set default pin mode for pins given by mask */
     switch (dir) {
         case PIN_INPUT:
-            port_mode(obj, PullDefault);
+            port_mode(obj, Input);
             break;
         case PIN_OUTPUT:
-            port_mode(obj, PullNone);
+            port_mode(obj, PushPull);
             break;
     }
 }
 
 void port_write(port_t *obj, int value)
 {
-    if (value) {
-        GPIO_PortOutSet(obj->port, obj->mask);
-    } else {
-        GPIO_PortOutClear(obj->port, obj->mask);
-    }
+    GPIO_PortOutSetVal(obj->port, value, obj->mask);
 }
 
 int port_read(port_t *obj)

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/pwmout_api.c	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/pwmout_api.c	Fri Jan 15 07:45:16 2016 +0000
@@ -46,11 +46,28 @@
 
 static int pwm_prescaler_div;
 
-uint32_t pwmout_get_channel_route(pwmout_t *obj)
+float   pwmout_calculate_duty(uint32_t width_cycles, uint32_t period_cycles);
+void    pwmout_write_channel(uint32_t channel, float value);
+
+uint32_t pwmout_get_channel_route(uint32_t channel)
 {
-    MBED_ASSERT(obj->channel != (PWMName) NC);
+    MBED_ASSERT(channel != (PWMName) NC);
 
-    switch (obj->channel) {
+    switch (channel) {
+#ifdef TIMER_ROUTEPEN_CC0PEN
+        case PWM_CH0:
+            return TIMER_ROUTEPEN_CC0PEN;
+            break;
+        case PWM_CH1:
+            return TIMER_ROUTEPEN_CC1PEN;
+            break;
+        case PWM_CH2:
+            return TIMER_ROUTEPEN_CC2PEN;
+            break;
+        case PWM_CH3:
+            return TIMER_ROUTEPEN_CC3PEN;
+            break;
+#else
         case PWM_CH0:
             return TIMER_ROUTE_CC0PEN;
             break;
@@ -60,11 +77,75 @@
         case PWM_CH2:
             return TIMER_ROUTE_CC2PEN;
             break;
+#endif
         default:
             return 0;
     }
 }
 
+/*
+* Disables the route location given. Returns true if it was enabled, false if it wasn't.
+*/
+bool pwmout_disable_channel_route(uint32_t routeloc) {
+#ifdef TIMER_ROUTEPEN_CC0PEN
+    if(PWM_TIMER->ROUTEPEN & routeloc) {
+        //This channel was in use, so disable
+        PWM_TIMER->ROUTEPEN &= ~routeloc;
+        return true;
+    }
+#else
+    if(PWM_TIMER->ROUTE & routeloc) {
+        //This channel was in use, so disable
+        PWM_TIMER->ROUTE &= ~routeloc;
+        return true;
+    }
+#endif
+    return false;
+}
+
+/*
+* Check if a channel is active
+*/
+bool pwmout_channel_route_active(uint32_t routeloc) {
+#ifdef TIMER_ROUTEPEN_CC0PEN
+    if(PWM_TIMER->ROUTEPEN & routeloc) {
+        return true;
+    }
+#else
+    if(PWM_TIMER->ROUTE & routeloc) {
+        return true;
+    }
+#endif
+    return false;
+}
+
+/*
+* Set the given route PEN flag
+*/
+void pwmout_set_channel_route(uint32_t routeloc) {
+#ifdef TIMER_ROUTEPEN_CC0PEN
+    PWM_TIMER->ROUTEPEN |= routeloc;
+#else
+    PWM_TIMER->ROUTE    |= routeloc;
+#endif
+}
+
+/*
+* Check if all routes are disabled
+*/
+bool pwmout_all_inactive(void) {
+#ifdef TIMER_ROUTEPEN_CC0PEN
+    if(PWM_TIMER->ROUTEPEN == _TIMER_ROUTEPEN_RESETVALUE) {
+        return true;
+    }
+#else
+    if(PWM_TIMER->ROUTE == PWM_ROUTE) {
+        return true;
+    }
+#endif
+    return false;
+}
+
 void pwmout_enable_pins(pwmout_t *obj, uint8_t enable)
 {
     if (enable) {
@@ -75,17 +156,14 @@
     }
 }
 
-void pwmout_enable(pwmout_t *obj, uint8_t enable)
-{
-    /* Start with default CC (Compare/Capture) channel parameters */
-    TIMER_InitCC_TypeDef timerCCInit = TIMER_INITCC_DEFAULT;
+void pwmout_enable(pwmout_t *obj, uint8_t enable){
     if (enable) {
-        /* Set mode to PWM */
-        timerCCInit.mode = timerCCModePWM;
+        // Set mode to PWM
+        PWM_TIMER->CC[obj->channel].CTRL = TIMER_CC_CTRL_MODE_PWM;
+    } else {
+        // Set mode to default (== disabled)
+        PWM_TIMER->CC[obj->channel].CTRL = _TIMER_CC_CTRL_MODE_DEFAULT;
     }
-
-    /* Configure CC channel */
-    TIMER_InitCC(PWM_TIMER, obj->channel, &timerCCInit);
 }
 
 void pwmout_init(pwmout_t *obj, PinName pin)
@@ -103,62 +181,107 @@
         TIMER_Init(PWM_TIMER, &timerInit);
     }
 
-    /* Enable correct channel */
-    uint32_t routeloc = pwmout_get_channel_route(obj);
-    if(PWM_TIMER->ROUTE & routeloc) {
+    // Set route enable
+    if(pwmout_channel_route_active(pwmout_get_channel_route(obj->channel))) {
         //This channel was already in use
-        //TODO: gracefully handle this case
+        //TODO: gracefully handle this case. mbed_error?
+        return;
     } else {
-        //This channel was unused up to now
-        PWM_TIMER->ROUTE |= routeloc;
+        pwmout_set_channel_route(pwmout_get_channel_route(obj->channel));
         blockSleepMode(EM1);
-
-        //TODO: check if any channel was up already, then don't re-init timer
         pwmout_enable(obj, true);
         pwmout_enable_pins(obj, true);
     }
 
-    /* Route correct channel to location 1 */
+    // Set route location
+#ifdef _TIMER_ROUTELOC0_CC0LOC_LOC0
+    switch (obj->channel) {
+        case PWM_CH0:
+            PWM_TIMER->ROUTELOC0 &= ~_TIMER_ROUTELOC0_CC0LOC_MASK;
+            PWM_TIMER->ROUTELOC0 |= pinmap_find_function(pin,PinMap_PWM) << _TIMER_ROUTELOC0_CC0LOC_SHIFT;
+            break;
+        case PWM_CH1:
+            PWM_TIMER->ROUTELOC0 &= ~_TIMER_ROUTELOC0_CC1LOC_MASK;
+            PWM_TIMER->ROUTELOC0 |= pinmap_find_function(pin,PinMap_PWM)<< _TIMER_ROUTELOC0_CC1LOC_SHIFT;
+            break;
+        case PWM_CH2:
+            PWM_TIMER->ROUTELOC0 &= ~_TIMER_ROUTELOC0_CC2LOC_MASK;
+            PWM_TIMER->ROUTELOC0 |= pinmap_find_function(pin,PinMap_PWM) << _TIMER_ROUTELOC0_CC2LOC_SHIFT;
+            break;
+        case PWM_CH3:
+            PWM_TIMER->ROUTELOC0 &= ~_TIMER_ROUTELOC0_CC3LOC_MASK;
+            PWM_TIMER->ROUTELOC0 |= pinmap_find_function(pin,PinMap_PWM) << _TIMER_ROUTELOC0_CC3LOC_SHIFT;
+            break;
+        default:
+            MBED_ASSERT(false);
+    }
+#else
+    // On P1, the route location is statically defined for the entire timer.
     PWM_TIMER->ROUTE &= ~_TIMER_ROUTE_LOCATION_MASK;
     PWM_TIMER->ROUTE |= PWM_ROUTE;
+#endif
 
-    /* Set default 20ms frequency and 0ms pulse width */
+    // Set default 20ms frequency and 0ms pulse width
     pwmout_period(obj, 0.02);
 }
 
 void pwmout_free(pwmout_t *obj)
 {
-    uint32_t routeloc = pwmout_get_channel_route(obj);
-    if(PWM_TIMER->ROUTE & routeloc) {
-        //This channel was in use, so disable
-        PWM_TIMER->ROUTE &= ~routeloc;
-        pwmout_enable_pins(obj, false);
+    if(pwmout_disable_channel_route(pwmout_get_channel_route(obj->channel))) {
+        //Channel was previously enabled, so do housekeeping
         unblockSleepMode(EM1);
-
-        //TODO: check if all channels are down, then switch off timer
     } else {
         //This channel was disabled already
     }
+    
+    pwmout_enable_pins(obj, false);
+    
+    if(pwmout_all_inactive()) {
+        //Stop timer
+        PWM_TIMER->CMD = TIMER_CMD_STOP;
+        while(PWM_TIMER->STATUS & TIMER_STATUS_RUNNING);
+        
+        //Disable clock
+        CMU_ClockEnable(PWM_TIMER_CLOCK, false);
+    }
 }
 
 void pwmout_write(pwmout_t *obj, float value)
 {
+    pwmout_write_channel(obj->channel, value);
+}
+
+void pwmout_write_channel(uint32_t channel, float value) {
+    uint32_t width_cycles = 0;
     if (value < 0.0f) {
-        value = 0;
-    } else if (value > 1.0f) {
-        value = 1;
+        width_cycles = 0;
+    } else if (value >= 1.0f) {
+        width_cycles = PWM_TIMER->TOPB + 1;
+    } else {
+       width_cycles = (uint16_t)((float)PWM_TIMER->TOPB * value);
     }
 
-    float pulse_period_in_s = obj->period_cycles / ((float) (REFERENCE_FREQUENCY >> pwm_prescaler_div));
-    pwmout_pulsewidth(obj, value * pulse_period_in_s);
+    TIMER_CompareBufSet(PWM_TIMER, channel, width_cycles);
 }
 
 float pwmout_read(pwmout_t *obj)
 {
-    return obj->width_cycles / (float) obj->period_cycles;
+    return pwmout_calculate_duty(TIMER_CaptureGet(PWM_TIMER, obj->channel), TIMER_TopGet(PWM_TIMER));
 }
 
-// Set the PWM period, keeping the absolute pulse width the same.
+float pwmout_calculate_duty(uint32_t width_cycles, uint32_t period_cycles) {
+    if(width_cycles > period_cycles) {
+        return 1.0f;
+    }
+    else if (width_cycles == 0) {
+        return 0.0f;
+    }
+    else {
+        return (float) width_cycles / (float) period_cycles;
+    }
+}
+
+// Set the PWM period, keeping the duty cycle the same.
 void pwmout_period(pwmout_t *obj, float seconds)
 {
     // Find the lowest prescaler divider possible.
@@ -181,13 +304,27 @@
         }
     }
 
-    obj->period_cycles = cycles;
+    //Check if anything changed
+    if(((PWM_TIMER->CTRL & ~_TIMER_CTRL_PRESC_MASK) == (pwm_prescaler_div << _TIMER_CTRL_PRESC_SHIFT)) && (TIMER_TopGet(PWM_TIMER) == cycles)) return;
+
+    //Save previous period for recalculation of duty cycles
+    uint32_t previous_period_cycles = PWM_TIMER->TOPB;
 
     //Set prescaler
     PWM_TIMER->CTRL = (PWM_TIMER->CTRL & ~_TIMER_CTRL_PRESC_MASK) | (pwm_prescaler_div << _TIMER_CTRL_PRESC_SHIFT);
 
-    /* Set Top Value, which controls the PWM period */
-    TIMER_TopSet(PWM_TIMER, obj->period_cycles);
+    //Set Top Value, which controls the PWM period
+    TIMER_TopBufSet(PWM_TIMER, cycles);
+
+    //For each active channel, re-calculate the compare value
+    uint32_t channel = 0;
+    while(pwmout_get_channel_route(channel) != 0) {
+        if(pwmout_channel_route_active(channel)) {
+            //recalc and reset compare value
+            pwmout_write_channel(channel, pwmout_calculate_duty(PWM_TIMER->CC[channel].CCVB, previous_period_cycles));
+        }
+        channel++;
+    }
 }
 
 void pwmout_period_ms(pwmout_t *obj, int ms)
@@ -202,20 +339,20 @@
 
 void pwmout_pulsewidth(pwmout_t *obj, float seconds)
 {
-    obj->width_cycles = (uint32_t) (((float) (REFERENCE_FREQUENCY >> pwm_prescaler_div)) * seconds);
-    TIMER_CompareBufSet(PWM_TIMER, obj->channel, obj->width_cycles);
+    uint16_t width_cycles = (uint16_t) (((float) (REFERENCE_FREQUENCY >> pwm_prescaler_div)) * seconds);
+    TIMER_CompareBufSet(PWM_TIMER, obj->channel, width_cycles);
 }
 
 void pwmout_pulsewidth_ms(pwmout_t *obj, int ms)
 {
-    obj->width_cycles = (uint32_t) ((REFERENCE_FREQUENCY >> pwm_prescaler_div) * ms) / 1000;
-    TIMER_CompareBufSet(PWM_TIMER, obj->channel, obj->width_cycles);
+    uint16_t width_cycles = (uint16_t) ((REFERENCE_FREQUENCY >> pwm_prescaler_div) * ms) / 1000;
+    TIMER_CompareBufSet(PWM_TIMER, obj->channel, width_cycles);
 }
 
 void pwmout_pulsewidth_us(pwmout_t *obj, int us)
 {
-    obj->width_cycles = (uint32_t) ((REFERENCE_FREQUENCY >> pwm_prescaler_div) * us) / 1000000;
-    TIMER_CompareBufSet(PWM_TIMER, obj->channel, obj->width_cycles);
+    uint16_t width_cycles = (uint16_t) ((REFERENCE_FREQUENCY >> pwm_prescaler_div) * us) / 1000000;
+    TIMER_CompareBufSet(PWM_TIMER, obj->channel, width_cycles);
 }
 
 #endif

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/rtc_api.c	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/rtc_api.c	Fri Jan 15 07:45:16 2016 +0000
@@ -34,10 +34,17 @@
 #include "rtc_api.h"
 #include "rtc_api_HAL.h"
 #include "em_cmu.h"
-#include "em_rtc.h"
 #include "sleep_api.h"
 #include "sleepmodes.h"
 
+#if (defined RTC_COUNT) && (RTC_COUNT > 0)
+#include "em_rtc.h"
+#endif
+
+#if (defined RTCC_COUNT) && (RTCC_COUNT > 0)
+#include "em_rtcc.h"
+#endif
+
 static bool         rtc_inited  = false;
 static time_t       time_base   = 0;
 static uint32_t     useflags    = 0;
@@ -45,6 +52,10 @@
 
 static void (*comp0_handler)(void) = NULL;
 
+#ifndef RTCC_COUNT
+
+/* Using RTC API */
+
 #define RTC_LEAST_ACTIVE_SLEEPMODE  EM2
 #define RTC_NUM_BITS                (24)
 
@@ -65,12 +76,12 @@
     }
 }
 
-uint32_t rtc_get_32bit(void) 
+uint32_t rtc_get_32bit(void)
 {
     return (RTC_CounterGet() + (time_extend << RTC_NUM_BITS));
 }
 
-uint64_t rtc_get_full(void) 
+uint64_t rtc_get_full(void)
 {
     uint64_t ticks = 0;
     ticks += time_extend;
@@ -79,18 +90,6 @@
     return ticks;
 }
 
-void rtc_set_comp0_handler(uint32_t handler)
-{
-    comp0_handler = (void (*)(void)) handler;
-}
-
-void rtc_init(void)
-{
-    /* Register that the RTC is used for timekeeping. */
-    rtc_init_real(RTC_INIT_RTC);
-}
-
-
 void rtc_init_real(uint32_t flags)
 {
     useflags |= flags;
@@ -143,6 +142,113 @@
     }
 }
 
+#else
+
+/* Using RTCC API */
+
+#define RTCC_LEAST_ACTIVE_SLEEPMODE  EM2
+#define RTCC_NUM_BITS                (32)
+
+void RTCC_IRQHandler(void)
+{
+    uint32_t flags;
+    flags = RTCC_IntGet();
+
+    if (flags & RTCC_IF_OF) {
+        RTCC_IntClear(RTCC_IF_OF);
+        /* RTC has overflowed (32 bits). Use time_extend as software counter for 32 more bits. */
+        time_extend += 1;
+    }
+
+    if (flags & RTCC_IF_CC0) {
+        RTCC_IntClear(RTCC_IF_CC0);
+        if (comp0_handler != NULL) {
+            comp0_handler();
+        }
+    }
+}
+
+uint32_t rtc_get_32bit(void)
+{
+    return RTCC_CounterGet();
+}
+
+uint64_t rtc_get_full(void)
+{
+    uint64_t ticks = 0;
+    ticks += time_extend;
+    ticks = ticks << RTCC_NUM_BITS;
+    ticks += RTCC_CounterGet();
+    return ticks;
+}
+
+void rtc_init_real(uint32_t flags)
+{
+    useflags |= flags;
+
+    if (!rtc_inited) {
+        CMU_ClockEnable(cmuClock_RTCC, true);
+
+        /* Enable clock to the interface of the low energy modules */
+        CMU_ClockEnable(cmuClock_CORELE, true);
+
+        /* Initialize RTC */
+        RTCC_Init_TypeDef init = RTCC_INIT_DEFAULT;
+        init.enable = 1;
+        init.precntWrapOnCCV0 = false;
+        init.cntWrapOnCCV1 = false;
+#if RTC_CLOCKDIV_INT == 8
+        init.presc = rtccCntPresc_8;
+#else
+#error invalid prescaler value RTC_CLOCKDIV_INT
+#endif
+
+        /* Enable Interrupt from RTC */
+        RTCC_IntEnable(RTCC_IEN_OF);
+        NVIC_EnableIRQ(RTCC_IRQn);
+        NVIC_SetVector(RTCC_IRQn, (uint32_t)RTCC_IRQHandler);
+
+        /* Initialize */
+        RTCC_Init(&init);
+
+        blockSleepMode(RTCC_LEAST_ACTIVE_SLEEPMODE);
+        rtc_inited = true;
+    }
+}
+
+void rtc_free(void)
+{
+    rtc_free_real(RTC_INIT_RTC);
+}
+
+void rtc_free_real(uint32_t flags)
+{
+    /* Clear use flag */
+    useflags &= ~flags;
+
+    /* Disable the RTC if it was inited and is no longer in use by anyone. */
+    if (rtc_inited && (useflags == 0)) {
+        NVIC_DisableIRQ(RTCC_IRQn);
+        RTCC_Reset();
+        CMU_ClockEnable(cmuClock_RTCC, false);
+        unblockSleepMode(RTCC_LEAST_ACTIVE_SLEEPMODE);
+        rtc_inited = false;
+    }
+}
+
+#endif /* RTCC_COUNT */
+
+void rtc_set_comp0_handler(uint32_t handler)
+{
+    comp0_handler = (void (*)(void)) handler;
+}
+
+void rtc_init(void)
+{
+    /* Register that the RTC is used for timekeeping. */
+    rtc_init_real(RTC_INIT_RTC);
+}
+
 int rtc_isenabled(void)
 {
     return rtc_inited;
@@ -153,7 +259,7 @@
     return (time_t) (rtc_get_full() >> RTC_FREQ_SHIFT) + time_base;
 }
 
-time_t rtc_read_uncompensated(void) 
+time_t rtc_read_uncompensated(void)
 {
     return (time_t) (rtc_get_full() >> RTC_FREQ_SHIFT);
 }
@@ -166,7 +272,7 @@
     do {
         time = rtc_read_uncompensated();
         time_base = t - time;
-    } while (time != rtc_read_uncompensated());
+    } while (time != (uint32_t)rtc_read_uncompensated());
 }
 
 #endif

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/serial_api.c	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/serial_api.c	Fri Jan 15 07:45:16 2016 +0000
@@ -34,6 +34,7 @@
 
 #include "mbed_assert.h"
 #include "serial_api.h"
+#include "serial_api_HAL.h"
 #include <string.h>
 #include <stdbool.h>
 
@@ -68,7 +69,7 @@
 #endif
 
 /* Store IRQ id for each UART */
-static uint32_t serial_irq_ids[SERIAL_NUM_UARTS] = { 0 };
+static uint32_t serial_irq_ids[MODULES_SIZE_SERIAL] = { 0 };
 /* Interrupt handler from mbed common */
 static uart_irq_handler irq_handler;
 /* Keep track of incoming DMA IRQ's */
@@ -78,52 +79,64 @@
 int stdio_uart_inited = 0;
 serial_t stdio_uart;
 
-static void uart_irq(UARTName, int, SerialIrq);
-uint8_t serial_get_index(serial_t *obj);
-void serial_enable(serial_t *obj, uint8_t enable);
-void serial_enable_pins(serial_t *obj, uint8_t enable);
-IRQn_Type serial_get_rx_irq_index(serial_t *obj);
-IRQn_Type serial_get_tx_irq_index(serial_t *obj);
-CMU_Clock_TypeDef serial_get_clock(serial_t *obj);
+static void uart_irq(UARTName, SerialIrq);
+static uint8_t serial_get_index(serial_t *obj);
+static void serial_enable(serial_t *obj, uint8_t enable);
+static void serial_enable_pins(serial_t *obj, uint8_t enable);
+static IRQn_Type serial_get_rx_irq_index(serial_t *obj);
+static IRQn_Type serial_get_tx_irq_index(serial_t *obj);
+static CMU_Clock_TypeDef serial_get_clock(serial_t *obj);
+static void serial_dmaSetupChannel(serial_t *obj, bool tx_nrx);
+static void serial_rx_abort_asynch_intern(serial_t *obj, int unblock_sleep);
+static void serial_tx_abort_asynch_intern(serial_t *obj, int unblock_sleep);
+static void serial_block_sleep(serial_t *obj);
+static void serial_unblock_sleep(serial_t *obj);
+static void serial_leuart_baud(serial_t *obj, int baudrate);
 
 /* ISRs for RX and TX events */
 #ifdef UART0
-static void uart0_rx_irq() { uart_irq(UART_0, 0, RxIrq); }
-static void uart0_tx_irq() { uart_irq(UART_0, 0, TxIrq); USART_IntClear((USART_TypeDef*)UART_0, USART_IFC_TXC);}
+static void uart0_rx_irq() { uart_irq(UART_0, RxIrq); }
+static void uart0_tx_irq() { uart_irq(UART_0, TxIrq); USART_IntClear((USART_TypeDef*)UART_0, USART_IFC_TXC);}
 #endif
 #ifdef UART1
-static void uart1_rx_irq() { uart_irq(UART_1, 1, RxIrq); }
-static void uart1_tx_irq() { uart_irq(UART_1, 1, TxIrq); USART_IntClear((USART_TypeDef*)UART_1, USART_IFC_TXC);}
+static void uart1_rx_irq() { uart_irq(UART_1, RxIrq); }
+static void uart1_tx_irq() { uart_irq(UART_1, TxIrq); USART_IntClear((USART_TypeDef*)UART_1, USART_IFC_TXC);}
 #endif
 #ifdef USART0
-static void usart0_rx_irq() { uart_irq(USART_0, 2, RxIrq); }
-static void usart0_tx_irq() { uart_irq(USART_0, 2, TxIrq); USART_IntClear((USART_TypeDef*)USART_0, USART_IFC_TXC);}
+static void usart0_rx_irq() { uart_irq(USART_0, RxIrq); }
+static void usart0_tx_irq() { uart_irq(USART_0, TxIrq); USART_IntClear((USART_TypeDef*)USART_0, USART_IFC_TXC);}
 #endif
 #ifdef USART1
-static void usart1_rx_irq() { uart_irq(USART_1, 3, RxIrq); }
-static void usart1_tx_irq() { uart_irq(USART_1, 3, TxIrq); USART_IntClear((USART_TypeDef*)USART_1, USART_IFC_TXC);}
+static void usart1_rx_irq() { uart_irq(USART_1, RxIrq); }
+static void usart1_tx_irq() { uart_irq(USART_1, TxIrq); USART_IntClear((USART_TypeDef*)USART_1, USART_IFC_TXC);}
 #endif
 #ifdef USART2
-static void usart2_rx_irq() { uart_irq(USART_2, 4, RxIrq); }
-static void usart2_tx_irq() { uart_irq(USART_2, 4, TxIrq); USART_IntClear((USART_TypeDef*)USART_2, USART_IFC_TXC);}
+static void usart2_rx_irq() { uart_irq(USART_2, RxIrq); }
+static void usart2_tx_irq() { uart_irq(USART_2, TxIrq); USART_IntClear((USART_TypeDef*)USART_2, USART_IFC_TXC);}
 #endif
 #ifdef LEUART0
 static void leuart0_irq()
 {
-    if(LEUART_IntGetEnabled(LEUART0) && (LEUART_IF_RXDATAV | LEUART_IF_FERR | LEUART_IFC_PERR | LEUART_IF_RXOF)) {
-        uart_irq(LEUART_0, 5, RxIrq);
-    } else {
-        uart_irq(LEUART_0, 5, TxIrq);
+    if(LEUART_IntGetEnabled(LEUART0) & (LEUART_IF_RXDATAV | LEUART_IF_FERR | LEUART_IF_PERR | LEUART_IF_RXOF)) {
+        uart_irq(LEUART_0, RxIrq);
+    }
+
+    if(LEUART_IntGetEnabled(LEUART0) & (LEUART_IF_TXC | LEUART_IF_TXBL | LEUART_IF_TXOF)) {
+        uart_irq(LEUART_0, TxIrq);
+        LEUART_IntClear(LEUART0, LEUART_IFC_TXC);
     }
 }
 #endif
 #ifdef LEUART1
 static void leuart1_irq()
 {
-    if(LEUART_IntGetEnabled(LEUART1) && (LEUART_IF_RXDATAV | LEUART_IF_FERR | LEUART_IFC_PERR | LEUART_IF_RXOF)) {
-        uart_irq(LEUART_1, 6, RxIrq);
-    } else {
-        uart_irq(LEUART_1, 6, TxIrq);
+    if(LEUART_IntGetEnabled(LEUART1) & (LEUART_IF_RXDATAV | LEUART_IF_FERR | LEUART_IF_PERR | LEUART_IF_RXOF)) {
+        uart_irq(LEUART_1, RxIrq);
+    }
+
+    if(LEUART_IntGetEnabled(LEUART1) & (LEUART_IF_TXC | LEUART_IF_TXBL | LEUART_IF_TXOF)) {
+        uart_irq(LEUART_1, TxIrq);
+        LEUART_IntClear(LEUART1, LEUART_IFC_TXC);
     }
 }
 #endif
@@ -133,78 +146,124 @@
  *
  * @param obj pointer to serial object
  */
-static void uart_init(serial_t *obj)
+static void uart_init(serial_t *obj, uint32_t baudrate, SerialParity parity, int stop_bits)
 {
     if(LEUART_REF_VALID(obj->serial.periph.leuart)) {
         LEUART_Init_TypeDef init = LEUART_INIT_DEFAULT;
 
+        if (stop_bits == 2) {
+            init.stopbits = leuartStopbits2;
+        } else {
+            init.stopbits = leuartStopbits1;
+        }
+
+        switch (parity) {
+            case ParityOdd:
+            case ParityForced0:
+                init.parity = leuartOddParity;
+                break;
+            case ParityEven:
+            case ParityForced1:
+                init.parity = leuartEvenParity;
+                break;
+            default: /* ParityNone */
+                init.parity = leuartNoParity;
+                break;
+        }
+
         init.enable = leuartDisable;
         init.baudrate = 9600;
         init.databits = leuartDatabits8;
-        init.parity = leuartNoParity;
-        init.stopbits = leuartStopbits1;
 #ifdef LEUART_USING_LFXO
         init.refFreq = LEUART_LF_REF_FREQ;
 #else
         init.refFreq = LEUART_REF_FREQ;
 #endif
         LEUART_Init(obj->serial.periph.leuart, &init);
+
+        if (baudrate != 9600) {
+            serial_baud(obj, baudrate);
+        }
     } else {
         USART_InitAsync_TypeDef init = USART_INITASYNC_DEFAULT;
 
+        if (stop_bits == 2) {
+            init.stopbits = usartStopbits2;
+        } else {
+            init.stopbits = usartStopbits1;
+        }
+        switch (parity) {
+            case ParityOdd:
+            case ParityForced0:
+                init.parity = usartOddParity;
+                break;
+            case ParityEven:
+            case ParityForced1:
+                init.parity = usartEvenParity;
+                break;
+            default: /* ParityNone */
+                init.parity = usartNoParity;
+                break;
+        }
+
         init.enable = usartDisable;
-        init.baudrate = 9600;
+        init.baudrate = baudrate;
         init.oversampling = usartOVS16;
         init.databits = usartDatabits8;
-        init.parity = usartNoParity;
-        init.stopbits = usartStopbits1;
-
-        /* Determine the reference clock, because the correct clock is not set up at init time */
         init.refFreq = REFERENCE_FREQUENCY;
 
         USART_InitAsync(obj->serial.periph.uart, &init);
     }
 }
+/**
+* Get index of serial object, relating it to the physical peripheral.
+*
+* @param obj pointer to serial peripheral (= base address of periph)
+* @return internal index of U(S)ART peripheral
+*/
+static inline uint8_t serial_pointer_get_index(uint32_t serial_ptr)
+{
+    uint8_t index = 0;
+#ifdef UART0
+    if (serial_ptr == UART_0) return index;
+    index++;
+#endif
+#ifdef UART1
+    if (serial_ptr == UART_1) return index;
+    index++;
+#endif
+#ifdef USART0
+    if (serial_ptr == USART_0) return index;
+    index++;
+#endif
+#ifdef USART1
+    if (serial_ptr == USART_1) return index;
+    index++;
+#endif
+#ifdef USART2
+    if (serial_ptr == USART_2) return index;
+    index++;
+#endif
+#ifdef LEUART0
+    if (serial_ptr == LEUART_0) return index;
+    index++;
+#endif
+#ifdef LEUART1
+    if (serial_ptr == LEUART_1) return index;
+    index++;
+#endif
+    return 0;
+}
 
 /**
 * Get index of serial object, relating it to the physical peripheral.
 *
-* @param obj pointer to serial object
+* @param obj pointer to serial object (mbed object)
 * @return internal index of U(S)ART peripheral
 */
-inline uint8_t serial_get_index(serial_t *obj)
+static inline uint8_t serial_get_index(serial_t *obj)
 {
-    switch ((uint32_t)obj->serial.periph.uart) {
-#ifdef UART0
-        case UART_0:
-            return 0;
-#endif
-#ifdef UART1
-        case UART_1:
-            return 1;
-#endif
-#ifdef USART0
-        case USART_0:
-            return 2;
-#endif
-#ifdef USART1
-        case USART_1:
-            return 3;
-#endif
-#ifdef USART2
-        case USART_2:
-            return 4;
-#endif
-#ifdef LEUART0
-        case LEUART_0:
-            return 5;
-#endif
-#ifdef LEUART1
-        case LEUART_1:
-            return 6;
-#endif
-    }
-    return 0;
+    return serial_pointer_get_index((uint32_t)obj->serial.periph.uart);
 }
 
 /**
@@ -213,7 +272,7 @@
 * @param obj pointer to serial object
 * @return internal NVIC RX IRQ index of U(S)ART peripheral
 */
-inline IRQn_Type serial_get_rx_irq_index(serial_t *obj)
+static inline IRQn_Type serial_get_rx_irq_index(serial_t *obj)
 {
     switch ((uint32_t)obj->serial.periph.uart) {
 #ifdef UART0
@@ -256,7 +315,7 @@
 * @param obj pointer to serial object
 * @return internal NVIC TX IRQ index of U(S)ART peripheral
 */
-inline IRQn_Type serial_get_tx_irq_index(serial_t *obj)
+static inline IRQn_Type serial_get_tx_irq_index(serial_t *obj)
 {
     switch ((uint32_t)obj->serial.periph.uart) {
 #ifdef UART0
@@ -349,11 +408,18 @@
     /* Get location */
     uint32_t uart_tx_loc = pin_location(tx, PinMap_UART_TX);
     uint32_t uart_rx_loc = pin_location(rx, PinMap_UART_RX);
+
+#if defined(_SILICON_LABS_32B_PLATFORM_1)
     /* Check that pins are used by same location for the given UART */
     obj->serial.location = pinmap_merge(uart_tx_loc, uart_rx_loc);
     MBED_ASSERT(obj->serial.location != (uint32_t)NC);
+#else
+    obj->serial.location_tx = uart_tx_loc;
+    obj->serial.location_rx = uart_rx_loc;
+#endif
 
     /* Store pins in object for easy disabling in serial_free() */
+    //TODO: replace all usages with AF_USARTx_TX_PORT(location) macro to save 8 bytes from struct
     obj->serial.rx_pin = rx;
     obj->serial.tx_pin = tx;
 
@@ -407,57 +473,123 @@
     }
 }
 
-void serial_enable_pins(serial_t *obj, uint8_t enable)
+static void serial_enable_pins(serial_t *obj, uint8_t enable)
 {
     if (enable) {
         /* Configure GPIO pins*/
-        pin_mode(obj->serial.rx_pin, Input);
-        /* 0x10 sets DOUT. Prevents false start. */
-        pin_mode(obj->serial.tx_pin, PushPull | 0x10);
+        if(obj->serial.rx_pin != NC) {
+            pin_mode(obj->serial.rx_pin, Input);
+        }
+        /* Set DOUT first to prevent glitches */
+        if(obj->serial.tx_pin != NC) {
+			GPIO_PinOutSet((GPIO_Port_TypeDef)(obj->serial.tx_pin >> 4 & 0xF), obj->serial.tx_pin & 0xF);
+            pin_mode(obj->serial.tx_pin, PushPull);
+        }
     } else {
-        pin_mode(obj->serial.rx_pin, Disabled);
-        pin_mode(obj->serial.tx_pin, Disabled);
+        if(obj->serial.rx_pin != NC) {
+            pin_mode(obj->serial.rx_pin, Disabled);
+        }
+        if(obj->serial.tx_pin != NC) {
+            pin_mode(obj->serial.tx_pin, Disabled);
+        }
     }
 }
 
+
 void serial_init(serial_t *obj, PinName tx, PinName rx)
 {
+    uint32_t baudrate;
+    uint32_t uart_for_stdio = false;
+
     serial_preinit(obj, tx, rx);
 
     if(LEUART_REF_VALID(obj->serial.periph.leuart)) {
         // Set up LEUART clock tree
 #ifdef LEUART_USING_LFXO
         //set to use LFXO
+        CMU_ClockEnable(cmuClock_CORELE, true);
         CMU_ClockSelectSet(cmuClock_LFB, cmuSelect_LFXO);
-        CMU_ClockEnable(cmuClock_CORELE, true);
 #else
         //set to use high-speed clock
+#ifdef _SILICON_LABS_32B_PLATFORM_2
+        CMU_ClockSelectSet(cmuClock_LFB, cmuSelect_HFCLKLE);
+#else
         CMU_ClockSelectSet(cmuClock_LFB, cmuSelect_CORELEDIV2);
 #endif
+#endif
     }
 
     CMU_ClockEnable(serial_get_clock(obj), true);
 
-    /* Configure UART for async operation */
-    uart_init(obj);
+    /* Limitations of board controller: CDC port only supports 115kbaud */
+    if(((tx == STDIO_UART_TX) || (rx == STDIO_UART_RX))
+       && (obj->serial.periph.uart == (USART_TypeDef*)STDIO_UART )
+      ) {
+        baudrate = 115200;
+        uart_for_stdio = true;
+    } else {
+        baudrate = 9600;
+    }
 
-    /* Limitations of board controller: CDC port only supports 115kbaud */
-    if((tx == STDIO_UART_TX) && (rx == STDIO_UART_RX) && (obj->serial.periph.uart == (USART_TypeDef*)STDIO_UART )) {
-        serial_baud(obj, 115200);
-    }
+    /* Configure UART for async operation */
+    uart_init(obj, baudrate, ParityNone, 1);
 
     /* Enable pins for UART at correct location */
     if(LEUART_REF_VALID(obj->serial.periph.leuart)) {
-        obj->serial.periph.leuart->ROUTE = LEUART_ROUTE_RXPEN | LEUART_ROUTE_TXPEN | (obj->serial.location << _LEUART_ROUTE_LOCATION_SHIFT);
+#ifdef _LEUART_ROUTE_LOCATION_SHIFT
+        obj->serial.periph.leuart->ROUTE = (obj->serial.location << _LEUART_ROUTE_LOCATION_SHIFT);
+        if(tx != (uint32_t)NC) {
+            obj->serial.periph.leuart->ROUTE |= LEUART_ROUTE_TXPEN;
+        }
+        if(rx != (uint32_t)NC) {
+            obj->serial.periph.leuart->ROUTE |= LEUART_ROUTE_RXPEN;
+        }
+#else
+        if(obj->serial.location_tx != NC) {
+            obj->serial.periph.leuart->ROUTELOC0 = (obj->serial.periph.leuart->ROUTELOC0 & (~_LEUART_ROUTELOC0_TXLOC_MASK)) | (obj->serial.location_tx << _LEUART_ROUTELOC0_TXLOC_SHIFT);
+            obj->serial.periph.leuart->ROUTEPEN  = (obj->serial.periph.leuart->ROUTEPEN & (~_LEUART_ROUTEPEN_TXPEN_MASK)) | LEUART_ROUTEPEN_TXPEN;
+        } else {
+            obj->serial.periph.leuart->ROUTEPEN  = (obj->serial.periph.leuart->ROUTEPEN & (~_LEUART_ROUTEPEN_TXPEN_MASK));
+        }
+        if(obj->serial.location_rx != NC) {
+            obj->serial.periph.leuart->ROUTELOC0 = (obj->serial.periph.leuart->ROUTELOC0 & (~_LEUART_ROUTELOC0_RXLOC_MASK)) | (obj->serial.location_rx << _LEUART_ROUTELOC0_RXLOC_SHIFT);
+            obj->serial.periph.leuart->ROUTEPEN  = (obj->serial.periph.leuart->ROUTEPEN & (~_LEUART_ROUTEPEN_RXPEN_MASK)) | LEUART_ROUTEPEN_RXPEN;
+        } else {
+            obj->serial.periph.leuart->CMD       = LEUART_CMD_RXBLOCKEN;
+            obj->serial.periph.leuart->ROUTEPEN  = (obj->serial.periph.leuart->ROUTEPEN & (~_LEUART_ROUTEPEN_RXPEN_MASK));
+        }
+#endif
         obj->serial.periph.leuart->IFC = LEUART_IFC_TXC;
         obj->serial.periph.leuart->CTRL |= LEUART_CTRL_RXDMAWU | LEUART_CTRL_TXDMAWU;
     } else {
-        obj->serial.periph.uart->ROUTE = USART_ROUTE_RXPEN | USART_ROUTE_TXPEN | (obj->serial.location << _USART_ROUTE_LOCATION_SHIFT);
+#ifdef _USART_ROUTE_LOCATION_SHIFT
+        obj->serial.periph.uart->ROUTE = (obj->serial.location << _USART_ROUTE_LOCATION_SHIFT);
+        if(tx != (uint32_t)NC) {
+            obj->serial.periph.uart->ROUTE |= USART_ROUTE_TXPEN;
+        }
+        if(rx != (uint32_t)NC) {
+            obj->serial.periph.uart->ROUTE |= USART_ROUTE_RXPEN;
+        }
+#else
+        if(obj->serial.location_tx != NC) {
+            obj->serial.periph.uart->ROUTELOC0 = (obj->serial.periph.uart->ROUTELOC0 & (~_USART_ROUTELOC0_TXLOC_MASK)) | (obj->serial.location_tx << _USART_ROUTELOC0_TXLOC_SHIFT);
+            obj->serial.periph.uart->ROUTEPEN  = (obj->serial.periph.uart->ROUTEPEN & (~_USART_ROUTEPEN_TXPEN_MASK)) | USART_ROUTEPEN_TXPEN;
+        } else {
+            obj->serial.periph.uart->ROUTEPEN  = (obj->serial.periph.uart->ROUTEPEN & (~_USART_ROUTEPEN_TXPEN_MASK));
+        }
+        if(obj->serial.location_rx != NC) {
+            obj->serial.periph.uart->ROUTELOC0 = (obj->serial.periph.uart->ROUTELOC0 & (~_USART_ROUTELOC0_RXLOC_MASK)) | (obj->serial.location_rx << _USART_ROUTELOC0_RXLOC_SHIFT);
+            obj->serial.periph.uart->ROUTEPEN  = (obj->serial.periph.uart->ROUTEPEN & (~_USART_ROUTEPEN_RXPEN_MASK)) | USART_ROUTEPEN_RXPEN;
+        } else {
+            obj->serial.periph.uart->CMD       = USART_CMD_RXBLOCKEN;
+            obj->serial.periph.uart->ROUTEPEN  = (obj->serial.periph.uart->ROUTEPEN & (~_USART_ROUTEPEN_RXPEN_MASK));
+        }
+#endif
         obj->serial.periph.uart->IFC = USART_IFC_TXC;
     }
 
     /* If this is the UART to be used for stdio, copy it to the stdio_uart struct */
-    if (obj->serial.periph.uart == (USART_TypeDef*)STDIO_UART ) {
+    if(uart_for_stdio) {
         stdio_uart_inited = 1;
         memcpy(&stdio_uart, obj, sizeof(serial_t));
     }
@@ -465,7 +597,6 @@
     serial_enable_pins(obj, true);
     serial_enable(obj, true);
 
-
     obj->serial.dmaOptionsTX.dmaChannel = -1;
     obj->serial.dmaOptionsTX.dmaUsageState = DMA_USAGE_OPPORTUNISTIC;
 
@@ -474,7 +605,17 @@
 
 }
 
-void serial_enable(serial_t *obj, uint8_t enable)
+void serial_free(serial_t *obj)
+{
+    if( LEUART_REF_VALID(obj->serial.periph.leuart) ) {
+        LEUART_Enable(obj->serial.periph.leuart, leuartDisable);
+    } else {
+        USART_Enable(obj->serial.periph.uart, usartDisable);
+    }
+    serial_enable_pins(obj, false);
+}
+
+static void serial_enable(serial_t *obj, uint8_t enable)
 {
     if(LEUART_REF_VALID(obj->serial.periph.leuart)) {
         if (enable) {
@@ -498,53 +639,86 @@
 void serial_baud(serial_t *obj, int baudrate)
 {
     if(LEUART_REF_VALID(obj->serial.periph.leuart)) {
-#ifdef LEUART_USING_LFXO
-
-        /* check if baudrate is within allowed range */
-        MBED_ASSERT(baudrate >= (LEUART_LF_REF_FREQ >> 7));
-
-        if(baudrate > (LEUART_LF_REF_FREQ >> 1)){
-            /* check if baudrate is within allowed range */
-            MBED_ASSERT((baudrate <= (LEUART_HF_REF_FREQ >> 1)) && (baudrate > (LEUART_HF_REF_FREQ >> 10)));
-
-            CMU_ClockSelectSet(cmuClock_LFB, cmuSelect_CORELEDIV2);
-            uint8_t divisor = 1;
+        serial_leuart_baud(obj, baudrate);
+    } else {
+        USART_BaudrateAsyncSet(obj->serial.periph.uart, REFERENCE_FREQUENCY, (uint32_t)baudrate, usartOVS16);
+    }
+}
 
-            if(baudrate > (LEUART_HF_REF_FREQ >> 7)){
-                divisor = 1;
-            }else if(baudrate > (LEUART_HF_REF_FREQ >> 8)){
-                divisor = 2;
-            }else if(baudrate > (LEUART_HF_REF_FREQ >> 9)){
-                divisor = 4;
-            }else{
-                divisor = 8;
-            }
-            CMU_ClockDivSet(serial_get_clock(obj), divisor);
-            LEUART_BaudrateSet(obj->serial.periph.leuart, LEUART_HF_REF_FREQ/divisor, (uint32_t)baudrate);
-        }else{
-            CMU_ClockSelectSet(cmuClock_LFB, cmuSelect_LFXO);
-            CMU_ClockDivSet(serial_get_clock(obj), 1);
-            LEUART_BaudrateSet(obj->serial.periph.leuart, LEUART_LF_REF_FREQ, (uint32_t)baudrate);
-        }
+/**
+ * Set LEUART baud rate
+ * Calculate whether LF or HF clock should be used.
+ */
+static void serial_leuart_baud(serial_t *obj, int baudrate)
+{
+#ifdef LEUART_USING_LFXO
+    /* check if baudrate is within allowed range */
+#if defined(_SILICON_LABS_32B_PLATFORM_2)
+    // P2 has 9 bits + 5 fractional bits in LEUART CLKDIV register
+    MBED_ASSERT(baudrate >= (LEUART_LF_REF_FREQ >> 9));
 #else
-        /* check if baudrate is within allowed range */
-        MBED_ASSERT((baudrate > (LEUART_REF_FREQ >> 10)) && (baudrate <= (LEUART_REF_FREQ >> 1)));
+    // P1 has 7 bits + 5 fractional bits in LEUART CLKDIV register
+    MBED_ASSERT(baudrate >= (LEUART_LF_REF_FREQ >> 7));
+#endif
+
+    if(baudrate > (LEUART_LF_REF_FREQ >> 1)){
+        // Baudrate is bigger than LFCLK/2 - we need to use the HF clock
         uint8_t divisor = 1;
-        if(baudrate > (LEUART_REF_FREQ >> 7)){
+
+#if defined(_SILICON_LABS_32B_PLATFORM_2)
+        /* Check if baudrate is within allowed range: (HFCLK/4096, HFCLK/2] */
+        MBED_ASSERT((baudrate <= (LEUART_HF_REF_FREQ >> 1)) && (baudrate > (LEUART_HF_REF_FREQ >> 12)));
+
+        CMU_ClockSelectSet(cmuClock_LFB, cmuSelect_HFCLKLE);
+
+        if(baudrate > (LEUART_HF_REF_FREQ >> 9)){
             divisor = 1;
-        }else if(baudrate > (LEUART_REF_FREQ >> 8)){
+        }else if(baudrate > (LEUART_HF_REF_FREQ >> 10)){
             divisor = 2;
-        }else if(baudrate > (LEUART_REF_FREQ >> 9)){
+        }else if(baudrate > (LEUART_HF_REF_FREQ >> 11)){
             divisor = 4;
         }else{
             divisor = 8;
         }
-        CMU_ClockDivSet(serial_get_clock(obj), divisor);
-        LEUART_BaudrateSet(obj->serial.periph.leuart, LEUART_REF_FREQ/divisor, (uint32_t)baudrate);
+#else // P1
+        /* Check if baudrate is within allowed range */
+        MBED_ASSERT((baudrate <= (LEUART_HF_REF_FREQ >> 1)) && (baudrate > (LEUART_HF_REF_FREQ >> 10)));
+
+        CMU_ClockSelectSet(cmuClock_LFB, cmuSelect_CORELEDIV2);
+
+        if(baudrate > (LEUART_HF_REF_FREQ >> 7)){
+            divisor = 1;
+        }else if(baudrate > (LEUART_HF_REF_FREQ >> 8)){
+            divisor = 2;
+        }else if(baudrate > (LEUART_HF_REF_FREQ >> 9)){
+            divisor = 4;
+        }else{
+            divisor = 8;
+        }
 #endif
-    } else {
-        USART_BaudrateAsyncSet(obj->serial.periph.uart, REFERENCE_FREQUENCY, (uint32_t)baudrate, usartOVS16);
+        CMU_ClockDivSet(serial_get_clock(obj), divisor);
+        LEUART_BaudrateSet(obj->serial.periph.leuart, LEUART_HF_REF_FREQ/divisor, (uint32_t)baudrate);
+    }else{
+        CMU_ClockSelectSet(cmuClock_LFB, cmuSelect_LFXO);
+        CMU_ClockDivSet(serial_get_clock(obj), 1);
+        LEUART_BaudrateSet(obj->serial.periph.leuart, LEUART_LF_REF_FREQ, (uint32_t)baudrate);
     }
+#else
+    /* check if baudrate is within allowed range */
+    MBED_ASSERT((baudrate > (LEUART_REF_FREQ >> 10)) && (baudrate <= (LEUART_REF_FREQ >> 1)));
+    uint8_t divisor = 1;
+    if(baudrate > (LEUART_REF_FREQ >> 7)){
+        divisor = 1;
+    }else if(baudrate > (LEUART_REF_FREQ >> 8)){
+        divisor = 2;
+    }else if(baudrate > (LEUART_REF_FREQ >> 9)){
+        divisor = 4;
+    }else{
+        divisor = 8;
+    }
+    CMU_ClockDivSet(serial_get_clock(obj), divisor);
+    LEUART_BaudrateSet(obj->serial.periph.leuart, LEUART_REF_FREQ/divisor, (uint32_t)baudrate);
+#endif
 }
 
 /**
@@ -587,7 +761,28 @@
         LEUART_Init(obj->serial.periph.leuart, &init);
 
         /* Re-enable pins for UART at correct location */
-        obj->serial.periph.leuart->ROUTE = LEUART_ROUTE_RXPEN | LEUART_ROUTE_TXPEN | (obj->serial.location << _LEUART_ROUTE_LOCATION_SHIFT);
+#ifdef _LEUART_ROUTE_LOCATION_SHIFT
+        obj->serial.periph.leuart->ROUTE = (obj->serial.location << _LEUART_ROUTE_LOCATION_SHIFT);
+        if(obj->serial.tx_pin != (uint32_t)NC) {
+            obj->serial.periph.leuart->ROUTE |= LEUART_ROUTE_TXPEN;
+        }
+        if(obj->serial.rx_pin != (uint32_t)NC) {
+            obj->serial.periph.leuart->ROUTE |= LEUART_ROUTE_RXPEN;
+        }
+#else
+        if(obj->serial.location_tx != NC) {
+            obj->serial.periph.leuart->ROUTELOC0 = (obj->serial.periph.leuart->ROUTELOC0 & (~_LEUART_ROUTELOC0_TXLOC_MASK)) | (obj->serial.location_tx << _LEUART_ROUTELOC0_TXLOC_SHIFT);
+            obj->serial.periph.leuart->ROUTEPEN  = (obj->serial.periph.leuart->ROUTEPEN & (~_LEUART_ROUTEPEN_TXPEN_MASK)) | LEUART_ROUTEPEN_TXPEN;
+        } else {
+            obj->serial.periph.leuart->ROUTEPEN  = (obj->serial.periph.leuart->ROUTEPEN & (~_LEUART_ROUTEPEN_TXPEN_MASK));
+        }
+        if(obj->serial.location_rx != NC) {
+            obj->serial.periph.leuart->ROUTELOC0 = (obj->serial.periph.leuart->ROUTELOC0 & (~_LEUART_ROUTELOC0_RXLOC_MASK)) | (obj->serial.location_rx << _LEUART_ROUTELOC0_RXLOC_SHIFT);
+            obj->serial.periph.leuart->ROUTEPEN  = (obj->serial.periph.leuart->ROUTEPEN & (~_LEUART_ROUTEPEN_RXPEN_MASK)) | LEUART_ROUTEPEN_RXPEN;
+        } else {
+            obj->serial.periph.leuart->ROUTEPEN  = (obj->serial.periph.leuart->ROUTEPEN & (~_LEUART_ROUTEPEN_RXPEN_MASK));
+        }
+#endif
 
         /* Re-enable interrupts */
         if(was_enabled != 0) {
@@ -632,7 +827,28 @@
         USART_InitAsync(obj->serial.periph.uart, &init);
 
         /* Re-enable pins for UART at correct location */
-        obj->serial.periph.uart->ROUTE = USART_ROUTE_RXPEN | USART_ROUTE_TXPEN | (obj->serial.location << _USART_ROUTE_LOCATION_SHIFT);
+#ifdef _USART_ROUTE_LOCATION_SHIFT
+        obj->serial.periph.uart->ROUTE = (obj->serial.location << _USART_ROUTE_LOCATION_SHIFT);
+        if(obj->serial.tx_pin != (uint32_t)NC) {
+            obj->serial.periph.uart->ROUTE |= USART_ROUTE_TXPEN;
+        }
+        if(obj->serial.rx_pin != (uint32_t)NC) {
+            obj->serial.periph.uart->ROUTE |= USART_ROUTE_RXPEN;
+        }
+#else
+        if(obj->serial.location_tx != NC) {
+            obj->serial.periph.uart->ROUTELOC0 = (obj->serial.periph.uart->ROUTELOC0 & (~_USART_ROUTELOC0_TXLOC_MASK)) | (obj->serial.location_tx << _USART_ROUTELOC0_TXLOC_SHIFT);
+            obj->serial.periph.uart->ROUTEPEN  = (obj->serial.periph.uart->ROUTEPEN & (~_USART_ROUTEPEN_TXPEN_MASK)) | USART_ROUTEPEN_TXPEN;
+        } else {
+            obj->serial.periph.uart->ROUTEPEN  = (obj->serial.periph.uart->ROUTEPEN & (~_USART_ROUTEPEN_TXPEN_MASK));
+        }
+        if(obj->serial.location_rx != NC) {
+            obj->serial.periph.uart->ROUTELOC0 = (obj->serial.periph.uart->ROUTELOC0 & (~_USART_ROUTELOC0_RXLOC_MASK)) | (obj->serial.location_rx << _USART_ROUTELOC0_RXLOC_SHIFT);
+            obj->serial.periph.uart->ROUTEPEN  = (obj->serial.periph.uart->ROUTEPEN & (~_USART_ROUTEPEN_RXPEN_MASK)) | USART_ROUTEPEN_RXPEN;
+        } else {
+            obj->serial.periph.uart->ROUTEPEN  = (obj->serial.periph.uart->ROUTEPEN & (~_USART_ROUTEPEN_RXPEN_MASK));
+        }
+#endif
 
         /* Re-enable interrupts */
         if(was_enabled != 0) {
@@ -764,8 +980,9 @@
 /**
  * Generic ISR for all UARTs, both TX and RX
  */
-static void uart_irq(UARTName name, int index, SerialIrq irq)
+static void uart_irq(UARTName name, SerialIrq irq)
 {
+    uint8_t index = serial_pointer_get_index((uint32_t)name);
     if (serial_irq_ids[index] != 0) {
         /* Pass interrupt on to mbed common handler */
         irq_handler(serial_irq_ids[index], irq);
@@ -852,8 +1069,10 @@
      * need to use serial_writable(). */
     if(LEUART_REF_VALID(obj->serial.periph.leuart)) {
         LEUART_Tx(obj->serial.periph.leuart, (uint8_t)(c));
+        while (!(obj->serial.periph.leuart->STATUS & LEUART_STATUS_TXC));
     } else {
         USART_Tx(obj->serial.periph.uart, (uint8_t)(c));
+        while (!(obj->serial.periph.uart->STATUS & USART_STATUS_TXC));
     }
 }
 
@@ -940,6 +1159,8 @@
     }
 }
 
+#ifndef LDMA_PRESENT
+
 /******************************************
 * static void serial_setupDmaChannel(serial_t *obj, bool tx_nrx)
 *
@@ -1041,9 +1262,9 @@
 
         DMA_CfgChannel(obj->serial.dmaOptionsRX.dmaChannel, &channelConfig);
     }
-
+}
 
-}
+#endif /* LDMA_PRESENT */
 
 /******************************************
 * static void serial_dmaTrySetState(DMA_OPTIONS_t *obj, DMAUsage requestedState)
@@ -1097,6 +1318,8 @@
     }
 }
 
+#ifndef LDMA_PRESENT
+
 static void serial_dmaActivate(serial_t *obj, void* cb, void* buffer, int length, bool tx_nrx)
 {
     DMA_CfgDescr_TypeDef channelConfig;
@@ -1104,7 +1327,7 @@
     if(tx_nrx) {
         // Set DMA callback
         obj->serial.dmaOptionsTX.dmaCallback.cbFunc = serial_dmaTransferComplete;
-        obj->serial.dmaOptionsTX.dmaCallback.userPtr = cb;
+        obj->serial.dmaOptionsTX.dmaCallback.userPtr = NULL;
 
         // Set up configuration structure
         channelConfig.dstInc = dmaDataIncNone;
@@ -1113,9 +1336,23 @@
         channelConfig.arbRate = dmaArbitrate1;
         channelConfig.hprot = 0;
 
+        // Clear TXC
+        if(LEUART_REF_VALID(obj->serial.periph.leuart)) {
+            LEUART_IntClear(obj->serial.periph.leuart, LEUART_IFC_TXC);
+        } else {
+            USART_IntClear(obj->serial.periph.uart, USART_IFC_TXC);
+        }
+
+        // Set callback and enable TXC. This will fire once the
+        // serial transfer finishes
+        NVIC_SetVector(serial_get_tx_irq_index(obj), (uint32_t)cb);
+        serial_irq_set(obj, TxIrq, true);
+
         DMA_CfgDescr(obj->serial.dmaOptionsTX.dmaChannel, true, &channelConfig);
         if(LEUART_REF_VALID(obj->serial.periph.leuart)) {
-            // Activate TX
+            // Activate TX and clear TX buffer (note that clear must be done
+            // separately and before TXEN or DMA will die on some platforms)
+            obj->serial.periph.leuart->CMD = LEUART_CMD_CLEARTX;
             obj->serial.periph.leuart->CMD = LEUART_CMD_TXEN;
             while(obj->serial.periph.leuart->SYNCBUSY & LEUART_SYNCBUSY_CMD);
 
@@ -1128,6 +1365,8 @@
             // Kick off TX DMA
             DMA_ActivateBasic(obj->serial.dmaOptionsTX.dmaChannel, true, false, (void*) &(obj->serial.periph.uart->TXDATA), buffer, length - 1);
         }
+
+
     } else {
         // Set DMA callback
         obj->serial.dmaOptionsRX.dmaCallback.cbFunc = serial_dmaTransferComplete;
@@ -1144,7 +1383,8 @@
 
         if(LEUART_REF_VALID(obj->serial.periph.leuart)) {
             // Activate RX and clear RX buffer
-            obj->serial.periph.leuart->CMD = LEUART_CMD_RXEN | LEUART_CMD_CLEARRX;
+            obj->serial.periph.leuart->CMD = LEUART_CMD_CLEARRX;
+            obj->serial.periph.leuart->CMD = LEUART_CMD_RXEN;
             while(obj->serial.periph.leuart->SYNCBUSY & LEUART_SYNCBUSY_CMD);
 
             // Kick off RX DMA
@@ -1159,6 +1399,112 @@
     }
 }
 
+#endif
+
+
+#ifdef LDMA_PRESENT
+
+static void serial_dmaSetupChannel(serial_t *obj, bool tx_nrx)
+{
+}
+
+static void serial_dmaActivate(serial_t *obj, void* cb, void* buffer, int length, bool tx_nrx)
+{
+    LDMA_PeripheralSignal_t dma_periph;
+
+    obj->serial.dmaOptionsRX.dmaCallback.userPtr = cb;
+
+    if( tx_nrx ) {
+        volatile void *target_addr;
+
+        // Clear TXC
+        if(LEUART_REF_VALID(obj->serial.periph.leuart)) {
+            LEUART_IntClear(obj->serial.periph.leuart, LEUART_IFC_TXC);
+        } else {
+            USART_IntClear(obj->serial.periph.uart, USART_IFC_TXC);
+        }
+
+        switch((uint32_t)(obj->serial.periph.uart)) {
+#ifdef USART0
+            case USART_0:
+                dma_periph = ldmaPeripheralSignal_USART0_TXBL;
+                target_addr = &USART0->TXDATA;
+                obj->serial.periph.uart->CMD = USART_CMD_TXEN | USART_CMD_CLEARTX;
+                break;
+#endif
+#ifdef USART1
+            case USART_1:
+                dma_periph = ldmaPeripheralSignal_USART1_TXBL;
+                target_addr = &USART1->TXDATA;
+                obj->serial.periph.uart->CMD = USART_CMD_TXEN | USART_CMD_CLEARTX;
+                break;
+#endif
+#ifdef LEUART0
+            case LEUART_0:
+                dma_periph = ldmaPeripheralSignal_LEUART0_TXBL;
+                target_addr = &LEUART0->TXDATA;
+                obj->serial.periph.leuart->CMD = LEUART_CMD_CLEARTX;
+                obj->serial.periph.leuart->CMD = LEUART_CMD_TXEN;
+                while(obj->serial.periph.leuart->SYNCBUSY & LEUART_SYNCBUSY_CMD);
+                break;
+#endif
+            default:
+                MBED_ASSERT(0);
+                while(1);
+                break;
+        }
+
+        // Set callback and enable TXC. This will fire once the
+        // serial transfer finishes
+        NVIC_SetVector(serial_get_tx_irq_index(obj), (uint32_t)cb);
+        serial_irq_set(obj, TxIrq, true);
+
+        // Start DMA transfer
+        LDMA_TransferCfg_t xferConf = LDMA_TRANSFER_CFG_PERIPHERAL(dma_periph);
+        LDMA_Descriptor_t desc = LDMA_DESCRIPTOR_SINGLE_M2P_BYTE(buffer, target_addr, length);
+        LDMAx_StartTransfer(obj->serial.dmaOptionsTX.dmaChannel, &xferConf, &desc, serial_dmaTransferComplete, NULL);
+
+    } else {
+        volatile const void *source_addr;
+
+        switch((uint32_t)(obj->serial.periph.uart)) {
+#ifdef USART0
+            case USART_0:
+                dma_periph = ldmaPeripheralSignal_USART0_RXDATAV;
+                source_addr = &USART0->RXDATA;
+                obj->serial.periph.uart->CMD = USART_CMD_RXEN | USART_CMD_CLEARRX;
+                break;
+#endif
+#ifdef USART1
+            case USART_1:
+                dma_periph = ldmaPeripheralSignal_USART1_RXDATAV;
+                source_addr = &USART1->RXDATA;
+                obj->serial.periph.uart->CMD = USART_CMD_RXEN | USART_CMD_CLEARRX;
+                break;
+#endif
+#ifdef LEUART0
+            case LEUART_0:
+                dma_periph = ldmaPeripheralSignal_LEUART0_RXDATAV;
+                source_addr = &LEUART0->RXDATA;
+                obj->serial.periph.leuart->CMD = LEUART_CMD_CLEARRX;
+                obj->serial.periph.leuart->CMD = LEUART_CMD_RXEN;
+                while(obj->serial.periph.leuart->SYNCBUSY & LEUART_SYNCBUSY_CMD);
+                break;
+#endif
+            default:
+                MBED_ASSERT(0);
+                while(1);
+                break;
+        }
+
+        LDMA_TransferCfg_t xferConf = LDMA_TRANSFER_CFG_PERIPHERAL(dma_periph);
+        LDMA_Descriptor_t desc = LDMA_DESCRIPTOR_SINGLE_P2M_BYTE(source_addr, buffer, length);
+        LDMAx_StartTransfer(obj->serial.dmaOptionsRX.dmaChannel, &xferConf, &desc, serial_dmaTransferComplete, cb);
+    }
+}
+
+#endif /* LDMA_PRESENT */
+
 /************************************************************************************
  *          ASYNCHRONOUS HAL                                                        *
  ************************************************************************************/
@@ -1283,7 +1629,7 @@
  */
 int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint)
 {
-    // Check that a buffer has indeed been set up
+   // Check that a buffer has indeed been set up
     MBED_ASSERT(tx != (void*)0);
     if(tx_length == 0) return 0;
 
@@ -1295,15 +1641,7 @@
     serial_tx_enable_event(obj, event, true);
 
     // Set up sleepmode
-#ifdef LEUART_USING_LFXO
-    if(LEUART_REF_VALID(obj->serial.periph.leuart) && (LEUART_BaudrateGet(obj->serial.periph.leuart) <= (LEUART_LF_REF_FREQ/2))){
-        blockSleepMode(SERIAL_LEAST_ACTIVE_SLEEPMODE_LEUART);
-    }else{
-        blockSleepMode(SERIAL_LEAST_ACTIVE_SLEEPMODE);
-    }
-#else
-    blockSleepMode(SERIAL_LEAST_ACTIVE_SLEEPMODE);
-#endif
+    serial_block_sleep(obj);
 
     // Determine DMA strategy
     serial_dmaTrySetState(&(obj->serial.dmaOptionsTX), hint, obj, true);
@@ -1323,7 +1661,8 @@
 
         if(LEUART_REF_VALID(obj->serial.periph.leuart)) {
             // Activate TX and clear TX buffer
-            obj->serial.periph.leuart->CMD = LEUART_CMD_TXEN | LEUART_CMD_CLEARTX;
+            obj->serial.periph.leuart->CMD = LEUART_CMD_CLEARTX;
+            obj->serial.periph.leuart->CMD = LEUART_CMD_TXEN;
             while(obj->serial.periph.leuart->SYNCBUSY & LEUART_SYNCBUSY_CMD);
 
             // Enable interrupt
@@ -1374,15 +1713,7 @@
     obj->char_match = char_match;
 
     // Set up sleepmode
-#ifdef LEUART_USING_LFXO
-    if(LEUART_REF_VALID(obj->serial.periph.leuart) && (LEUART_BaudrateGet(obj->serial.periph.leuart) <= (LEUART_LF_REF_FREQ/2))){
-        blockSleepMode(SERIAL_LEAST_ACTIVE_SLEEPMODE_LEUART);
-    }else{
-        blockSleepMode(SERIAL_LEAST_ACTIVE_SLEEPMODE);
-    }
-#else
-    blockSleepMode(SERIAL_LEAST_ACTIVE_SLEEPMODE);
-#endif
+    serial_block_sleep(obj);
 
     // Determine DMA strategy
     // If character match is enabled, we can't use DMA, sadly. We could when using LEUART though, but that support is not in here yet.
@@ -1406,7 +1737,8 @@
 
         if(LEUART_REF_VALID(obj->serial.periph.leuart)) {
             // Activate RX and clear RX buffer
-            obj->serial.periph.leuart->CMD = LEUART_CMD_RXEN | LEUART_CMD_CLEARRX;
+            obj->serial.periph.leuart->CMD = LEUART_CMD_CLEARRX;
+            obj->serial.periph.leuart->CMD = LEUART_CMD_RXEN;
             while(obj->serial.periph.leuart->SYNCBUSY & LEUART_SYNCBUSY_CMD);
 
             // Enable interrupt
@@ -1433,20 +1765,10 @@
  */
 uint8_t serial_tx_active(serial_t *obj)
 {
-    switch(obj->serial.dmaOptionsTX.dmaUsageState) {
-        case DMA_USAGE_TEMPORARY_ALLOCATED:
-            /* Temporary allocation always means its active, as this state gets cleared afterwards */
-            return 1;
-        case DMA_USAGE_ALLOCATED:
-            /* Check whether the allocated DMA channel is active by checking the DMA transfer */
-            return(DMA_ChannelEnabled(obj->serial.dmaOptionsTX.dmaChannel));
-        default:
-            /* Check whether interrupt for serial TX is enabled */
-            if(LEUART_REF_VALID(obj->serial.periph.leuart)) {
-                return (obj->serial.periph.leuart->IEN & (LEUART_IEN_TXBL)) ? true : false;
-            } else {
-                return (obj->serial.periph.uart->IEN & (USART_IEN_TXBL)) ? true : false;
-            }
+    if(LEUART_REF_VALID(obj->serial.periph.leuart)) {
+        return (obj->serial.periph.leuart->IEN & (LEUART_IEN_TXBL|LEUART_IEN_TXC)) ? true : false;
+    } else {
+        return (obj->serial.periph.uart->IEN & (USART_IEN_TXBL|USART_IEN_TXC)) ? true : false;
     }
 }
 
@@ -1463,7 +1785,13 @@
             return 1;
         case DMA_USAGE_ALLOCATED:
             /* Check whether the allocated DMA channel is active by checking the DMA transfer */
-            return(DMA_ChannelEnabled(obj->serial.dmaOptionsRX.dmaChannel));
+#ifndef LDMA_PRESENT
+            return DMA_ChannelEnabled(obj->serial.dmaOptionsRX.dmaChannel);
+#else
+            // LDMA_TransferDone does not work since the CHDONE bits get cleared,
+            // so just check if the channel is enabled
+            return LDMA->CHEN & (1 << obj->serial.dmaOptionsRX.dmaChannel);
+#endif
         default:
             /* Check whether interrupt for serial TX is enabled */
             if(LEUART_REF_VALID(obj->serial.periph.leuart)) {
@@ -1497,10 +1825,11 @@
                 /* Last byte has been put in TX, set up TXC interrupt */
                 LEUART_IntDisable(obj->serial.periph.leuart, LEUART_IEN_TXBL);
                 LEUART_IntEnable(obj->serial.periph.leuart, LEUART_IEN_TXC);
+                while (obj->serial.periph.leuart->SYNCBUSY);
             }
         }else if (obj->serial.periph.leuart->IF & LEUART_IF_TXC){
             /* Last byte has been successfully transmitted. Stop the procedure */
-            serial_tx_abort_asynch(obj);
+            serial_tx_abort_asynch_intern(obj, 1);
             return SERIAL_EVENT_TX_COMPLETE & obj->serial.events;
         }
     } else {
@@ -1517,7 +1846,7 @@
             }
         } else if (obj->serial.periph.uart->IF & USART_IF_TXC) {
             /* Last byte has been successfully transmitted. Stop the procedure */
-            serial_tx_abort_asynch(obj);
+            serial_tx_abort_asynch_intern(obj, 1);
             return SERIAL_EVENT_TX_COMPLETE & obj->serial.events;
         }
     }
@@ -1542,21 +1871,21 @@
         if(LEUART_IntGetEnabled(obj->serial.periph.leuart) & LEUART_IF_PERR) {
             /* Parity error has occurred, and we are notifying. */
             LEUART_IntClear(obj->serial.periph.leuart, LEUART_IFC_PERR);
-            serial_rx_abort_asynch(obj);
+            serial_rx_abort_asynch_intern(obj, 1);
             return SERIAL_EVENT_RX_PARITY_ERROR;
         }
 
         if(LEUART_IntGetEnabled(obj->serial.periph.leuart) & LEUART_IF_FERR) {
             /* Framing error has occurred, and we are notifying */
             LEUART_IntClear(obj->serial.periph.leuart, LEUART_IFC_FERR);
-            serial_rx_abort_asynch(obj);
+            serial_rx_abort_asynch_intern(obj, 1);
             return SERIAL_EVENT_RX_FRAMING_ERROR;
         }
 
         if(LEUART_IntGetEnabled(obj->serial.periph.leuart) & LEUART_IF_RXOF) {
             /* RX buffer overflow has occurred, and we are notifying */
             LEUART_IntClear(obj->serial.periph.leuart, LEUART_IFC_RXOF);
-            serial_rx_abort_asynch(obj);
+            serial_rx_abort_asynch_intern(obj, 1);
             return SERIAL_EVENT_RX_OVERFLOW;
         }
 
@@ -1570,7 +1899,7 @@
 
                 if((buf[obj->rx_buff.pos] == obj->char_match) && (obj->serial.events & SERIAL_EVENT_RX_CHARACTER_MATCH)) event |= SERIAL_EVENT_RX_CHARACTER_MATCH;
 
-                serial_rx_abort_asynch(obj);
+                serial_rx_abort_asynch_intern(obj, 1);
                 return event & obj->serial.events;
             } else {
                 /* There's still space in the receive buffer */
@@ -1592,7 +1921,7 @@
                     }
 
                     if(aborting) {
-                        serial_rx_abort_asynch(obj);
+                        serial_rx_abort_asynch_intern(obj, 1);
                         return event & obj->serial.events;
                     }
                 }
@@ -1603,21 +1932,21 @@
         if(USART_IntGetEnabled(obj->serial.periph.uart) & USART_IF_PERR) {
             /* Parity error has occurred, and we are notifying. */
             USART_IntClear(obj->serial.periph.uart, USART_IFC_PERR);
-            serial_rx_abort_asynch(obj);
+            serial_rx_abort_asynch_intern(obj, 1);
             return SERIAL_EVENT_RX_PARITY_ERROR;
         }
 
         if(USART_IntGetEnabled(obj->serial.periph.uart) & USART_IF_FERR) {
             /* Framing error has occurred, and we are notifying */
             USART_IntClear(obj->serial.periph.uart, USART_IFC_FERR);
-            serial_rx_abort_asynch(obj);
+            serial_rx_abort_asynch_intern(obj, 1);
             return SERIAL_EVENT_RX_FRAMING_ERROR;
         }
 
         if(USART_IntGetEnabled(obj->serial.periph.uart) & USART_IF_RXOF) {
             /* RX buffer overflow has occurred, and we are notifying */
             USART_IntClear(obj->serial.periph.uart, USART_IFC_RXOF);
-            serial_rx_abort_asynch(obj);
+            serial_rx_abort_asynch_intern(obj, 1);
             return SERIAL_EVENT_RX_OVERFLOW;
         }
 
@@ -1631,7 +1960,7 @@
 
                 if((buf[obj->rx_buff.pos] == obj->char_match) && (obj->serial.events & SERIAL_EVENT_RX_CHARACTER_MATCH)) event |= SERIAL_EVENT_RX_CHARACTER_MATCH;
 
-                serial_rx_abort_asynch(obj);
+                serial_rx_abort_asynch_intern(obj, 1);
                 return event & obj->serial.events;
             } else {
                 /* There's still space in the receive buffer */
@@ -1653,7 +1982,7 @@
                     }
 
                     if(aborting) {
-                        serial_rx_abort_asynch(obj);
+                        serial_rx_abort_asynch_intern(obj, 1);
                         return event & obj->serial.events;
                     }
                 }
@@ -1671,37 +2000,37 @@
  */
 int serial_irq_handler_asynch(serial_t *obj)
 {
+    uint32_t txc_int;
+
+    if(LEUART_REF_VALID(obj->serial.periph.leuart)) {
+        txc_int = LEUART_IntGetEnabled(obj->serial.periph.leuart) & LEUART_IF_TXC;
+    } else {
+        txc_int = USART_IntGetEnabled(obj->serial.periph.uart) & USART_IF_TXC;
+    }
+
     /* First, check if we're running in DMA mode */
-    if(serial_dma_irq_fired[obj->serial.dmaOptionsRX.dmaChannel]) {
+    if( (obj->serial.dmaOptionsRX.dmaChannel != -1) &&
+        serial_dma_irq_fired[obj->serial.dmaOptionsRX.dmaChannel]) {
         /* Clean up */
         serial_dma_irq_fired[obj->serial.dmaOptionsRX.dmaChannel] = false;
-        serial_rx_abort_asynch(obj);
+        serial_rx_abort_asynch_intern(obj, 1);
 
         /* Notify CPP land of RX completion */
         return SERIAL_EVENT_RX_COMPLETE & obj->serial.events;
-    } else if (serial_dma_irq_fired[obj->serial.dmaOptionsTX.dmaChannel]) {
+    } else if (txc_int && (obj->serial.dmaOptionsTX.dmaChannel != -1) &&
+               serial_dma_irq_fired[obj->serial.dmaOptionsTX.dmaChannel]) {
         if(LEUART_REF_VALID(obj->serial.periph.leuart)) {
-            if(obj->serial.periph.leuart->IEN & LEUART_IEN_TXC){
-                LEUART_IntDisable(obj->serial.periph.leuart,LEUART_IEN_TXC);
-                /* Clean up */
-                serial_dma_irq_fired[obj->serial.dmaOptionsTX.dmaChannel] = false;
-                serial_tx_abort_asynch(obj);
-                /* Notify CPP land of completion */
-                return SERIAL_EVENT_TX_COMPLETE & obj->serial.events;
-            }else{
-                LEUART_IntEnable(obj->serial.periph.leuart,LEUART_IEN_TXC);
-            }
+            /* Clean up */
+            serial_dma_irq_fired[obj->serial.dmaOptionsTX.dmaChannel] = false;
+            serial_tx_abort_asynch_intern(obj, 1);
+            /* Notify CPP land of completion */
+            return SERIAL_EVENT_TX_COMPLETE & obj->serial.events;
         }else{
-            if(obj->serial.periph.uart->IEN & USART_IEN_TXC){
-                USART_IntDisable(obj->serial.periph.uart,USART_IEN_TXC);
-                /* Clean up */
-                serial_dma_irq_fired[obj->serial.dmaOptionsTX.dmaChannel] = false;
-                serial_tx_abort_asynch(obj);
-                /* Notify CPP land of completion */
-                return SERIAL_EVENT_TX_COMPLETE & obj->serial.events;
-            }else{
-                USART_IntEnable(obj->serial.periph.uart,USART_IEN_TXC);
-            }
+            /* Clean up */
+            serial_dma_irq_fired[obj->serial.dmaOptionsTX.dmaChannel] = false;
+            serial_tx_abort_asynch_intern(obj, 1);
+            /* Notify CPP land of completion */
+            return SERIAL_EVENT_TX_COMPLETE & obj->serial.events;
         }
     } else {
         /* Check the NVIC to see which interrupt we're running from
@@ -1733,43 +2062,96 @@
  */
 void serial_tx_abort_asynch(serial_t *obj)
 {
-    /* Stop transmitter */
-    //obj->serial.periph.uart->CMD |= USART_CMD_TXDIS;
+    serial_tx_abort_asynch_intern(obj, 0);
+}
+
+static void serial_tx_abort_asynch_intern(serial_t *obj, int unblock_sleep)
+{
+    // Transmitter should be disabled here but there are multiple issues
+    // making that quite difficult.
+    //
+    // - Disabling the transmitter when using DMA on platforms prior to
+    //   Pearl can cause the UART to leave the line low, generating a break
+    //   condition until the next transmission begins.
+    //
+    // - On (at least) Pearl, once TXC interrupt has fired it will take some time
+    //   (some tens of microsec) for TXC to be set in STATUS. If we turn off
+    //   the transmitter before this, bad things will happen.
+    //
+    // - On (at least) Pearl, when using TX DMA it is possible for the USART
+    //   status to be: TXENS TXBL TXIDLE = 1, TXBUFCNT = 0, but TXC = 0.
+    //
+    // All in all, the logic was so fragile it's best to leave it out.
 
     /* Clean up */
     switch(obj->serial.dmaOptionsTX.dmaUsageState) {
         case DMA_USAGE_ALLOCATED:
             /* stop DMA transfer */
+#ifndef LDMA_PRESENT
             DMA_ChannelEnable(obj->serial.dmaOptionsTX.dmaChannel, false);
+#else
+            LDMA_StopTransfer(obj->serial.dmaOptionsTX.dmaChannel);
+#endif
             break;
         case DMA_USAGE_TEMPORARY_ALLOCATED:
             /* stop DMA transfer and release channel */
+#ifndef LDMA_PRESENT
             DMA_ChannelEnable(obj->serial.dmaOptionsTX.dmaChannel, false);
+#else
+            LDMA_StopTransfer(obj->serial.dmaOptionsTX.dmaChannel);
+#endif
             dma_channel_free(obj->serial.dmaOptionsTX.dmaChannel);
             obj->serial.dmaOptionsTX.dmaChannel = -1;
             obj->serial.dmaOptionsTX.dmaUsageState = DMA_USAGE_OPPORTUNISTIC;
             break;
         default:
-            /* stop interrupting */
-            if(LEUART_REF_VALID(obj->serial.periph.leuart)) {
-                LEUART_IntDisable(obj->serial.periph.leuart, LEUART_IEN_TXC);
-                LEUART_IntClear(obj->serial.periph.leuart, LEUART_IFC_TXC);
-            } else {
-                USART_IntDisable(obj->serial.periph.uart, USART_IEN_TXC);
-                USART_IntClear(obj->serial.periph.uart, USART_IFC_TXC);
-            }
             break;
     }
 
+    /* stop interrupting */
+    if(LEUART_REF_VALID(obj->serial.periph.leuart)) {
+        LEUART_IntDisable(obj->serial.periph.leuart, LEUART_IEN_TXBL);
+        LEUART_IntDisable(obj->serial.periph.leuart, LEUART_IEN_TXC);
+        LEUART_IntClear(obj->serial.periph.leuart, LEUART_IFC_TXC);
+    } else {
+        USART_IntDisable(obj->serial.periph.uart, USART_IEN_TXBL);
+        USART_IntDisable(obj->serial.periph.uart, USART_IEN_TXC);
+        USART_IntClear(obj->serial.periph.uart, USART_IFC_TXC);
+    }
+
     /* Say that we can stop using this emode */
+    if(unblock_sleep)
+        serial_unblock_sleep(obj);
+}
+
+
+static void serial_unblock_sleep(serial_t *obj)
+{
+    if( obj->serial.sleep_blocked > 0 ) {
+#ifdef LEUART_USING_LFXO
+        if(LEUART_REF_VALID(obj->serial.periph.leuart) && (LEUART_BaudrateGet(obj->serial.periph.leuart) <= (LEUART_LF_REF_FREQ/2))){
+            unblockSleepMode(SERIAL_LEAST_ACTIVE_SLEEPMODE_LEUART);
+        }else{
+            unblockSleepMode(SERIAL_LEAST_ACTIVE_SLEEPMODE);
+        }
+#else
+        unblockSleepMode(SERIAL_LEAST_ACTIVE_SLEEPMODE);
+#endif
+        obj->serial.sleep_blocked--;
+    }
+}
+
+static void serial_block_sleep(serial_t *obj)
+{
+    obj->serial.sleep_blocked++;
 #ifdef LEUART_USING_LFXO
     if(LEUART_REF_VALID(obj->serial.periph.leuart) && (LEUART_BaudrateGet(obj->serial.periph.leuart) <= (LEUART_LF_REF_FREQ/2))){
-        unblockSleepMode(SERIAL_LEAST_ACTIVE_SLEEPMODE_LEUART);
+        blockSleepMode(SERIAL_LEAST_ACTIVE_SLEEPMODE_LEUART);
     }else{
-        unblockSleepMode(SERIAL_LEAST_ACTIVE_SLEEPMODE);
+        blockSleepMode(SERIAL_LEAST_ACTIVE_SLEEPMODE);
     }
 #else
-    unblockSleepMode(SERIAL_LEAST_ACTIVE_SLEEPMODE);
+    blockSleepMode(SERIAL_LEAST_ACTIVE_SLEEPMODE);
 #endif
 }
 
@@ -1780,18 +2162,36 @@
  */
 void serial_rx_abort_asynch(serial_t *obj)
 {
+    serial_rx_abort_asynch_intern(obj, 0);
+}
+
+static void serial_rx_abort_asynch_intern(serial_t *obj, int unblock_sleep)
+{
     /* Stop receiver */
-    obj->serial.periph.uart->CMD |= USART_CMD_RXDIS;
+    if(LEUART_REF_VALID(obj->serial.periph.leuart)) {
+        obj->serial.periph.leuart->CMD = LEUART_CMD_RXDIS;
+        while(obj->serial.periph.leuart->SYNCBUSY & LEUART_SYNCBUSY_CMD);
+    } else {
+        obj->serial.periph.uart->CMD = USART_CMD_RXDIS;
+    }
 
     /* Clean up */
     switch(obj->serial.dmaOptionsRX.dmaUsageState) {
         case DMA_USAGE_ALLOCATED:
             /* stop DMA transfer */
+#ifndef LDMA_PRESENT
             DMA_ChannelEnable(obj->serial.dmaOptionsRX.dmaChannel, false);
+#else
+            LDMA_StopTransfer(obj->serial.dmaOptionsRX.dmaChannel);
+#endif
             break;
         case DMA_USAGE_TEMPORARY_ALLOCATED:
             /* stop DMA transfer and release channel */
+#ifndef LDMA_PRESENT
             DMA_ChannelEnable(obj->serial.dmaOptionsRX.dmaChannel, false);
+#else
+            LDMA_StopTransfer(obj->serial.dmaOptionsRX.dmaChannel);
+#endif
             dma_channel_free(obj->serial.dmaOptionsRX.dmaChannel);
             obj->serial.dmaOptionsRX.dmaChannel = -1;
             obj->serial.dmaOptionsRX.dmaUsageState = DMA_USAGE_OPPORTUNISTIC;
@@ -1814,15 +2214,8 @@
     }
 
     /* Say that we can stop using this emode */
-#ifdef LEUART_USING_LFXO
-    if(LEUART_REF_VALID(obj->serial.periph.leuart) && (LEUART_BaudrateGet(obj->serial.periph.leuart) <= (LEUART_LF_REF_FREQ/2))){
-        unblockSleepMode(SERIAL_LEAST_ACTIVE_SLEEPMODE_LEUART);
-    }else{
-        unblockSleepMode(SERIAL_LEAST_ACTIVE_SLEEPMODE);
-    }
-#else
-    unblockSleepMode(SERIAL_LEAST_ACTIVE_SLEEPMODE);
-#endif
+    if( unblock_sleep )
+        serial_unblock_sleep(obj);
 }
 
 #endif //DEVICE_SERIAL_ASYNCH

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/serial_api_HAL.h	Fri Jan 15 07:45:16 2016 +0000
@@ -0,0 +1,52 @@
+/***************************************************************************//**
+ * @file serial_api_HAL.h
+ *******************************************************************************
+ * @section License
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
+ *******************************************************************************
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
+ * obligation to support this Software. Silicon Labs is providing the
+ * Software "AS IS", with no express or implied warranties of any kind,
+ * including, but not limited to, any implied warranties of merchantability
+ * or fitness for any particular purpose or warranties against infringement
+ * of any proprietary rights of a third party.
+ *
+ * Silicon Labs will not be liable for any consequential, incidental, or
+ * special damages, or any other relief, or for any claim by any third party,
+ * arising from your use of this Software.
+ *
+ ******************************************************************************/
+
+#ifndef MBED_SERIAL_API_HAL_H
+#define MBED_SERIAL_API_HAL_H
+
+#include "em_device.h"
+
+#ifdef _SILICON_LABS_32B_PLATFORM_2
+
+#define UART_TYPE_USART  0x01
+#define UART_TYPE_LEUART 0x02
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif
+
+#endif

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/sleepmodes.h	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/sleepmodes.h	Fri Jan 15 07:45:16 2016 +0000
@@ -37,7 +37,18 @@
 extern "C" {
 #endif
 
+/*
+* Blocks all sleepmodes below the one passed as argument
+*
+* @param minimumMode The lowest-power sleep mode which must remain active
+*/
 void blockSleepMode(sleepstate_enum minimumMode);
+
+/*
+* Unblocks a previously-blocked sleep mode
+* 
+*@param minimumMode The same sleepmode that was previously passed to blockSleepMode
+*/
 void unblockSleepMode(sleepstate_enum minimumMode);
 
 #ifdef __cplusplus

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/spi_api.c	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/spi_api.c	Fri Jan 15 07:45:16 2016 +0000
@@ -40,6 +40,7 @@
 
 #include "dma_api.h"
 #include "dma_api_HAL.h"
+#include "serial_api_HAL.h"
 #include "spi_api.h"
 #include "em_usart.h"
 #include "em_cmu.h"
@@ -48,6 +49,7 @@
 #include "sleepmodes.h"
 
 static uint16_t fill_word = SPI_FILL_WORD;
+
 #define SPI_LEAST_ACTIVE_SLEEPMODE EM1
 
 static inline CMU_Clock_TypeDef spi_get_clock_tree(spi_t *obj)
@@ -109,10 +111,10 @@
     init.baudrate = baudrate;
     init.databits = databits;
     init.master = master;
-    init.msbf	= 1;
+    init.msbf   = 1;
     init.clockMode = clockMode;
 
-    /* Determine the reference clock, because the correct clock is not set up at init time */
+    /* Determine the reference clock, because the correct clock may not be set up at init time (e.g. before main()) */
     init.refFreq = REFERENCE_FREQUENCY;
 
     USART_InitSync(obj->spi.spi, &init);
@@ -136,6 +138,8 @@
         obj->spi.master = true;
     }
 
+#if defined(_SILICON_LABS_32B_PLATFORM_1)
+    // On P1, we need to ensure all pins are on same location
     uint32_t loc_mosi = pin_location(mosi, PinMap_SPI_MOSI);
     uint32_t loc_miso = pin_location(miso, PinMap_SPI_MISO);
     uint32_t loc_clk = pin_location(clk, PinMap_SPI_CLK);
@@ -144,6 +148,7 @@
     uint32_t loc_ctrl = pinmap_merge(loc_clk, loc_cs);
     obj->spi.location = pinmap_merge(loc_data, loc_ctrl);
     MBED_ASSERT(obj->spi.location != NC);
+#endif
 
     obj->spi.dmaOptionsTX.dmaUsageState = DMA_USAGE_OPPORTUNISTIC;
 }
@@ -196,6 +201,28 @@
     }
 
     /* Enabling pins and setting location */
+#ifdef _USART_ROUTEPEN_RESETVALUE
+    uint32_t route = USART_ROUTEPEN_CLKPEN;
+    obj->spi.spi->ROUTELOC0 &= ~_USART_ROUTELOC0_CLKLOC_MASK;
+    obj->spi.spi->ROUTELOC0 |= pin_location(clk, PinMap_SPI_CLK)<<_USART_ROUTELOC0_CLKLOC_SHIFT;
+    if (mosi != NC) {
+        route |= USART_ROUTEPEN_TXPEN;
+        obj->spi.spi->ROUTELOC0 &= ~_USART_ROUTELOC0_TXLOC_MASK;
+        obj->spi.spi->ROUTELOC0 |= pin_location(mosi, PinMap_SPI_MOSI)<<_USART_ROUTELOC0_TXLOC_SHIFT;
+    }
+    if (miso != NC) {
+        route |= USART_ROUTEPEN_RXPEN;
+        obj->spi.spi->ROUTELOC0 &= ~_USART_ROUTELOC0_RXLOC_MASK;
+        obj->spi.spi->ROUTELOC0 |= pin_location(mosi, PinMap_SPI_MOSI)<<_USART_ROUTELOC0_RXLOC_SHIFT;
+    }
+    if (!obj->spi.master) {
+        route |= USART_ROUTEPEN_CSPEN;
+        obj->spi.spi->ROUTELOC0 &= ~_USART_ROUTELOC0_CSLOC_MASK;
+        obj->spi.spi->ROUTELOC0 |= pin_location(mosi, PinMap_SPI_MOSI)<<_USART_ROUTELOC0_CSLOC_SHIFT;
+    }
+    obj->spi.spi->ROUTEPEN = route;
+}
+#else
     uint32_t route = USART_ROUTE_CLKPEN | (obj->spi.location << _USART_ROUTE_LOCATION_SHIFT);
 
     if (mosi != NC) {
@@ -209,7 +236,7 @@
     }
     obj->spi.spi->ROUTE = route;
 }
-
+#endif
 void spi_enable(spi_t *obj, uint8_t enable)
 {
     USART_Enable(obj->spi.spi, (enable ? usartEnable : usartDisable));
@@ -306,14 +333,24 @@
     }
 
     //save state
+#ifdef _USART_ROUTEPEN_RESETVALUE
+    uint32_t route = obj->spi.spi->ROUTEPEN;
+    uint32_t loc = obj->spi.spi->ROUTELOC0;
+#else
     uint32_t route = obj->spi.spi->ROUTE;
+#endif
     uint32_t iflags = obj->spi.spi->IEN;
     bool enabled = (obj->spi.spi->STATUS & (USART_STATUS_RXENS | USART_STATUS_TXENS)) != 0;
 
     usart_init(obj, 100000, databits, (slave ? false : true), clockMode);
 
     //restore state
+#ifdef _USART_ROUTEPEN_RESETVALUE
+    obj->spi.spi->ROUTEPEN = route;
+    obj->spi.spi->ROUTELOC0 = loc;
+#else
     obj->spi.spi->ROUTE = route;
+#endif
     obj->spi.spi->IEN = iflags;
 
     if(enabled) spi_enable(obj, enabled);
@@ -406,7 +443,11 @@
             return true;
         case DMA_USAGE_ALLOCATED:
             /* Check whether the allocated DMA channel is active */
+#ifdef LDMA_PRESENT
+            return(LDMAx_ChannelEnabled(obj->spi.dmaOptionsTX.dmaChannel) || LDMAx_ChannelEnabled(obj->spi.dmaOptionsRX.dmaChannel));
+#else
             return(DMA_ChannelEnabled(obj->spi.dmaOptionsTX.dmaChannel) || DMA_ChannelEnabled(obj->spi.dmaOptionsRX.dmaChannel));
+#endif
         default:
             /* Check whether interrupt for spi is enabled */
             return (obj->spi.spi->IEN & (USART_IEN_RXDATAV | USART_IEN_TXBL)) ? true : false;
@@ -438,53 +479,32 @@
 static void spi_buffer_tx_write(spi_t *obj)
 {
     uint32_t data;
-    // This routine gets triggered on TXBL (= buffer empty), so check to see if we can write a double value
-    if (obj->spi.bits % 9 != 0) {
-        // No special 9-bit scenario
-        if((obj->tx_buff.pos < obj->tx_buff.length - 1) && ((obj->tx_buff.pos & 0x1) == 0)) {
-            // write double frame
-            if (obj->tx_buff.buffer == (void *)0) {
-                data = SPI_FILL_WORD;
-            } else {
-                uint16_t *tx = (uint16_t *)(obj->tx_buff.buffer);
-                data = tx[obj->tx_buff.pos / 2] & 0xFFFF;
-            }
-            obj->tx_buff.pos += 2;
-            obj->spi.spi->TXDOUBLE = data;
-        } else if (obj->tx_buff.pos < obj->tx_buff.length) {
-            // write single frame
-            if (obj->tx_buff.buffer == (void *)0) {
-                data = SPI_FILL_WORD & 0xFF;
-            } else {
-                uint8_t *tx = (uint8_t *)(obj->tx_buff.buffer);
-                data = tx[obj->tx_buff.pos] & 0xFF;
-            }
-            obj->tx_buff.pos++;
-            obj->spi.spi->TXDATA = data;
+    if(obj->spi.bits >= 9) {
+        // write double frame
+        if (obj->tx_buff.buffer == (void *)0) {
+            data = SPI_FILL_WORD;
+        } else {
+            uint16_t *tx = (uint16_t *)(obj->tx_buff.buffer);
+            data = tx[obj->tx_buff.pos] & 0xFFFF;
         }
-    } else {
-        // 9-bit frame
-        if(obj->tx_buff.pos < obj->tx_buff.length - 3) {
-            // write double frame
-            if (obj->tx_buff.buffer == (void *)0) {
-                data = ((SPI_FILL_WORD & 0x01FF) << 16) | (SPI_FILL_WORD & 0x1FF);
-            } else {
-                uint32_t *tx = (uint32_t *)(obj->tx_buff.buffer);
-                data = tx[obj->tx_buff.pos / 4] & 0x01FF01FF;
-            }
-            obj->tx_buff.pos += 4;
-            obj->spi.spi->TXDOUBLEX = data;
-        } else if (obj->tx_buff.pos < obj->tx_buff.length - 1) {
-            // write single frame
-            if (obj->tx_buff.buffer == (void *)0) {
-                data = SPI_FILL_WORD & 0x01FF;
-            } else {
-                uint16_t *tx = (uint16_t *)(obj->tx_buff.buffer);
-                data = tx[obj->tx_buff.pos / 2] & 0x01FF;
-            }
-            obj->tx_buff.pos += 2;
+        obj->tx_buff.pos += 1;
+        if(obj->spi.bits == 9){
             obj->spi.spi->TXDATAX = data;
+        }else {
+            obj->spi.spi->TXDOUBLE = data;
         }
+
+    } else if (obj->tx_buff.pos < obj->tx_buff.length) {
+        // write single frame
+        if (obj->tx_buff.buffer == (void *)0) {
+            data = SPI_FILL_WORD & 0xFF;
+        } else {
+            uint8_t *tx = (uint8_t *)(obj->tx_buff.buffer);
+            data = tx[obj->tx_buff.pos] & 0xFF;
+        }
+        obj->tx_buff.pos++;
+
+        obj->spi.spi->TXDATA = data;
     }
 }
 
@@ -669,11 +689,11 @@
 * This function tries to allocate DMA as indicated by the hint (state).
 * There are three possibilities:
 *   * state = NEVER:
-*		if there were channels allocated by state = ALWAYS, they will be released
+*       if there were channels allocated by state = ALWAYS, they will be released
 *   * state = OPPORTUNITIC:
-*		if there are channels available, they will get used, but freed upon transfer completion
-*	* state = ALWAYS
-*		if there are channels available, they will get allocated and not be freed until state changes
+*       if there are channels available, they will get used, but freed upon transfer completion
+*   * state = ALWAYS
+*       if there are channels available, they will get allocated and not be freed until state changes
 ******************************************/
 void spi_enable_dma(spi_t *obj, DMAUsage state)
 {
@@ -706,6 +726,29 @@
     }
 }
 
+#ifdef LDMA_PRESENT
+/************************************************************************************
+ *          DMA helper functions                                                    *
+ ************************************************************************************/
+/******************************************
+* static void serial_dmaTransferComplete(uint channel, bool primary, void* user)
+*
+* Callback function which gets called upon DMA transfer completion
+* the user-defined pointer is pointing to the CPP-land thunk
+******************************************/
+static void serial_dmaTransferComplete(unsigned int channel, bool primary, void *user)
+{
+
+    /* User pointer should be a thunk to CPP land */
+    if (user != NULL) {
+        ((DMACallback)user)();
+    }
+}
+static void spi_master_dma_channel_setup(spi_t *obj, void* callback)
+{
+    obj->spi.dmaOptionsRX.dmaCallback.userPtr = callback;
+}
+#else
 /******************************************
 * void spi_master_dma_channel_setup(spi_t *obj)
 *
@@ -761,7 +804,115 @@
     DMA_CfgChannel(obj->spi.dmaOptionsRX.dmaChannel, &rxChnlCfg);
     DMA_CfgChannel(obj->spi.dmaOptionsTX.dmaChannel, &txChnlCfg);
 }
+#endif // LDMA_PRESENT
+/******************************************
+* void spi_activate_dma(spi_t *obj, void* rxdata, void* txdata, int length)
+*
+* This function will start the DMA engine for SPI transfers
+*
+*   * rxdata: pointer to RX buffer, if needed.
+*   * txdata: pointer to TX buffer, if needed. Else FF's.
+*   * tx_length: how many bytes will get sent.
+*   * rx_length: how many bytes will get received. If > tx_length, TX will get padded with n lower bits of SPI_FILL_WORD.
+******************************************/
+#ifdef LDMA_PRESENT
+static void spi_activate_dma(spi_t *obj, void* rxdata, const void* txdata, int tx_length, int rx_length)
+{
+    LDMA_PeripheralSignal_t dma_periph;
 
+    if( txdata ) {
+        volatile void *target_addr;
+
+        /* Select TX target address. 9 bit frame length requires to use extended register.
+           10 bit and larger frame requires to use TXDOUBLE register. */
+        switch((int)obj->spi.spi) {
+            case USART_0:
+                dma_periph = ldmaPeripheralSignal_USART0_TXBL;
+                if(obj->spi.bits <= 8){
+                    target_addr = &USART0->TXDATA;
+                }else if(obj->spi.bits == 9){
+                    target_addr = &USART0->TXDATAX;
+                }else{
+                    target_addr = &USART0->TXDOUBLE;
+                }
+                break;
+            case USART_1:
+                dma_periph = ldmaPeripheralSignal_USART1_TXBL;
+                if(obj->spi.bits <= 8){
+                    target_addr = &USART1->TXDATA;
+                }else if(obj->spi.bits == 9){
+                    target_addr = &USART1->TXDATAX;
+                }else{
+                    target_addr = &USART1->TXDOUBLE;
+                }
+                break;
+            default:
+                EFM_ASSERT(0);
+                while(1);
+                break;
+        }
+
+        /*  Check the transmit lenght, and split long transfers to smaller ones*/
+        int max_length = 1024;
+#ifdef _LDMA_CH_CTRL_XFERCNT_MASK
+        max_length = (_LDMA_CH_CTRL_XFERCNT_MASK>>_LDMA_CH_CTRL_XFERCNT_SHIFT)+1;
+#endif
+        if(tx_length>max_length){
+            tx_length = max_length;
+        }
+
+        /* Save amount of TX done by DMA */
+        obj->tx_buff.pos += tx_length;
+
+        LDMA_TransferCfg_t xferConf = LDMA_TRANSFER_CFG_PERIPHERAL(dma_periph);
+        LDMA_Descriptor_t desc = LDMA_DESCRIPTOR_SINGLE_M2P_BYTE(txdata, target_addr, tx_length);
+        if(obj->spi.bits >= 9){
+            desc.xfer.size = ldmaCtrlSizeHalf;
+        }
+        LDMAx_StartTransfer(obj->spi.dmaOptionsTX.dmaChannel, &xferConf, &desc, serial_dmaTransferComplete,obj->spi.dmaOptionsRX.dmaCallback.userPtr);
+
+    }
+    if(rxdata) {
+        volatile const void *source_addr;
+        /* Select RX source address. 9 bit frame length requires to use extended register.
+           10 bit and larger frame requires to use RXDOUBLE register. */
+        switch((int)obj->spi.spi) {
+            case USART_0:
+                dma_periph = ldmaPeripheralSignal_USART0_RXDATAV;
+                if(obj->spi.bits <= 8){
+                    source_addr = &USART0->RXDATA;
+                }else if(obj->spi.bits == 9){
+                    source_addr = &USART0->RXDATAX;
+                }else{
+                    source_addr = &USART0->RXDOUBLE;
+                }
+                break;
+            case USART_1:
+                dma_periph = ldmaPeripheralSignal_USART1_RXDATAV;
+                if(obj->spi.bits <= 8){
+                    source_addr = &USART1->RXDATA;
+                }else if(obj->spi.bits == 9){
+                    source_addr = &USART1->RXDATAX;
+                }else{
+                    source_addr = &USART1->RXDOUBLE;
+                }
+                break;
+            default:
+                EFM_ASSERT(0);
+                while(1);
+                break;
+        }
+
+        LDMA_TransferCfg_t xferConf = LDMA_TRANSFER_CFG_PERIPHERAL(dma_periph);
+        LDMA_Descriptor_t desc = LDMA_DESCRIPTOR_SINGLE_P2M_BYTE(source_addr, rxdata, rx_length);
+        if(obj->spi.bits >= 9){
+            desc.xfer.size = ldmaCtrlSizeHalf;
+        }
+        LDMAx_StartTransfer(obj->spi.dmaOptionsRX.dmaChannel, &xferConf, &desc, serial_dmaTransferComplete,obj->spi.dmaOptionsRX.dmaCallback.userPtr);
+    }
+}
+
+#else
 /******************************************
 * void spi_activate_dma(spi_t *obj, void* rxdata, void* txdata, int length)
 *
@@ -808,9 +959,6 @@
             rxDescrCfg.hprot = 0;
             DMA_CfgDescr(obj->spi.dmaOptionsRX.dmaChannel, true, &rxDescrCfg);
 
-            // Clear RX registers - Useful if previous command transfered don't
-            obj->spi.spi->CMD = USART_CMD_CLEARRX;
-
             /* Activate RX channel */
             DMA_ActivateBasic(obj->spi.dmaOptionsRX.dmaChannel, true, false, rxdata, (void *)&(obj->spi.spi->RXDATA),
                               rx_length - 1);
@@ -825,16 +973,13 @@
         txDescrCfg.hprot = 0;
         DMA_CfgDescr(obj->spi.dmaOptionsTX.dmaChannel, true, &txDescrCfg);
 
-        /* Clear TX registers */
-        obj->spi.spi->CMD = USART_CMD_CLEARTX;
-
         /* Activate TX channel */
-        DMA_ActivateBasic(	obj->spi.dmaOptionsTX.dmaChannel,
+        DMA_ActivateBasic(  obj->spi.dmaOptionsTX.dmaChannel,
                             true,
                             false,
                             (obj->spi.bits <= 8 ? (void *)&(obj->spi.spi->TXDATA) : (void *)&(obj->spi.spi->TXDOUBLE)), //When frame size > 9, point to TXDOUBLE
                             (txdata == 0 ? &fill_word : (void *)txdata), // When there is nothing to transmit, point to static fill word
-                            (obj->spi.bits <= 8 ? tx_length - 1 : (tx_length / 2) - 1)); // When using TXDOUBLE, recalculate transfer length
+                            (tx_length - 1));
     } else {
         /* Frame size == 9 */
         /* Only activate RX DMA if a receive buffer is specified */
@@ -847,9 +992,6 @@
             rxDescrCfg.hprot = 0;
             DMA_CfgDescr(obj->spi.dmaOptionsRX.dmaChannel, true, &rxDescrCfg);
 
-            // Clear RX registers - Useful if previous command transfered don't
-            obj->spi.spi->CMD = USART_CMD_CLEARRX;
-
             /* Activate RX channel */
             DMA_ActivateBasic(obj->spi.dmaOptionsRX.dmaChannel, true, false, rxdata, (void *)&(obj->spi.spi->RXDATAX),
                               (rx_length / 2) - 1);
@@ -863,19 +1005,16 @@
         txDescrCfg.hprot = 0;
         DMA_CfgDescr(obj->spi.dmaOptionsTX.dmaChannel, true, &txDescrCfg);
 
-        /* Clear TX registers */
-        obj->spi.spi->CMD = USART_CMD_CLEARTX;
-
         /* Activate TX channel */
-        DMA_ActivateBasic(	obj->spi.dmaOptionsTX.dmaChannel,
+        DMA_ActivateBasic(  obj->spi.dmaOptionsTX.dmaChannel,
                             true,
                             false,
                             (void *)&(obj->spi.spi->TXDATAX), //When frame size > 9, point to TXDOUBLE
                             (txdata == 0 ? &fill_word : (void *)txdata), // When there is nothing to transmit, point to static fill word
-                            (tx_length / 2) - 1); // When using TXDOUBLE, recalculate transfer length
+                            (tx_length - 1));
     }
 }
-
+#endif //LDMA_PRESENT
 /********************************************************************
 * spi_master_transfer_dma(spi_t *obj, void *rxdata, void *txdata, int length, DMACallback cb, DMAUsage hint)
 *
@@ -897,6 +1036,9 @@
 {
     /* Init DMA here to include it in the power figure */
     dma_init();
+    /* Clear TX and RX registers */
+    obj->spi.spi->CMD = USART_CMD_CLEARTX;
+    obj->spi.spi->CMD = USART_CMD_CLEARRX;
     /* If the DMA channels are already allocated, we can assume they have been setup already */
     if (hint != DMA_USAGE_NEVER && obj->spi.dmaOptionsTX.dmaUsageState == DMA_USAGE_ALLOCATED) {
         /* setup has already been done, so just activate the transfer */
@@ -980,6 +1122,72 @@
 * return: event mask. Currently only 0 or SPI_EVENT_COMPLETE upon transfer completion.
 *
 ********************************************************************/
+#ifdef LDMA_PRESENT
+uint32_t spi_irq_handler_asynch(spi_t* obj)
+{
+    if (obj->spi.dmaOptionsTX.dmaUsageState == DMA_USAGE_ALLOCATED || obj->spi.dmaOptionsTX.dmaUsageState == DMA_USAGE_TEMPORARY_ALLOCATED) {
+        /* DMA implementation */
+        /* If there is still data in the TX buffer, setup a new transfer. */
+        if (obj->tx_buff.pos < obj->tx_buff.length) {
+            /* Find position and remaining length without modifying tx_buff. */
+            void* tx_pointer = (char*)obj->tx_buff.buffer + obj->tx_buff.pos;
+            uint32_t tx_length = obj->tx_buff.length - obj->tx_buff.pos;
+
+            /* Begin transfer. Rely on spi_activate_dma to split up the transfer further. */
+            spi_activate_dma(obj, obj->rx_buff.buffer, tx_pointer, tx_length, obj->rx_buff.length);
+
+            return 0;
+        }
+        /* If there is an RX transfer ongoing, wait for it to finish */
+        if (LDMAx_ChannelEnabled(obj->spi.dmaOptionsRX.dmaChannel)) {
+            /* Check if we need to kick off TX transfer again to force more incoming data. */
+            if (LDMA_TransferDone(obj->spi.dmaOptionsTX.dmaChannel) && (obj->tx_buff.pos < obj->rx_buff.length)) {
+                void* tx_pointer = (char*)obj->tx_buff.buffer + obj->tx_buff.pos;
+                uint32_t tx_length = obj->tx_buff.length - obj->tx_buff.pos;
+                /* Begin transfer. Rely on spi_activate_dma to split up the transfer further. */
+                spi_activate_dma(obj, obj->rx_buff.buffer, tx_pointer, tx_length, obj->rx_buff.length);
+            } else return 0;
+        }
+        /* If there is still a TX transfer ongoing (tx_length > rx_length), wait for it to finish */
+        if (!LDMA_TransferDone(obj->spi.dmaOptionsTX.dmaChannel)) {
+            return 0;
+        }
+        /* Release the dma channels if they were opportunistically allocated */
+        if (obj->spi.dmaOptionsTX.dmaUsageState == DMA_USAGE_TEMPORARY_ALLOCATED) {
+            dma_channel_free(obj->spi.dmaOptionsTX.dmaChannel);
+            dma_channel_free(obj->spi.dmaOptionsRX.dmaChannel);
+            obj->spi.dmaOptionsTX.dmaUsageState = DMA_USAGE_OPPORTUNISTIC;
+        }
+
+        /* Wait transmit to complete, before user code is indicated*/
+        while(!(obj->spi.spi->STATUS & USART_STATUS_TXC));
+        unblockSleepMode(SPI_LEAST_ACTIVE_SLEEPMODE);
+        /* return to CPP land to say we're finished */
+        return SPI_EVENT_COMPLETE;
+    } else {
+        /* IRQ implementation */
+        if (spi_master_rx_int_flag(obj)) {
+            spi_master_read_asynch(obj);
+        }
+
+        if (spi_master_tx_int_flag(obj)) {
+            spi_master_write_asynch(obj);
+        }
+
+        uint32_t event = spi_event_check(obj);
+        if (event & SPI_EVENT_INTERNAL_TRANSFER_COMPLETE) {
+            /* disable interrupts */
+            spi_enable_interrupt(obj, (uint32_t)NULL, false);
+
+            unblockSleepMode(SPI_LEAST_ACTIVE_SLEEPMODE);
+            /* Return the event back to userland */
+            return event;
+        }
+
+        return 0;
+    }
+}
+#else
 uint32_t spi_irq_handler_asynch(spi_t* obj)
 {
 
@@ -1022,7 +1230,7 @@
                     DMA_CfgDescr(obj->spi.dmaOptionsTX.dmaChannel, true, &txDescrCfg);
 
                     /* Activate TX channel */
-                    DMA_ActivateBasic(	obj->spi.dmaOptionsTX.dmaChannel,
+                    DMA_ActivateBasic(  obj->spi.dmaOptionsTX.dmaChannel,
                                         true,
                                         false,
                                         (obj->spi.bits <= 8 ? (void *)&(obj->spi.spi->TXDATA) : (void *)&(obj->spi.spi->TXDOUBLE)), //When frame size > 9, point to TXDOUBLE
@@ -1038,7 +1246,7 @@
                     txDescrCfg.hprot = 0;
                     DMA_CfgDescr(obj->spi.dmaOptionsTX.dmaChannel, true, &txDescrCfg);
 
-                    DMA_ActivateBasic(	obj->spi.dmaOptionsTX.dmaChannel,
+                    DMA_ActivateBasic(  obj->spi.dmaOptionsTX.dmaChannel,
                                         true,
                                         false,
                                         (void *)&(obj->spi.spi->TXDATAX), //When frame size > 9, point to TXDOUBLE
@@ -1060,6 +1268,8 @@
             obj->spi.dmaOptionsTX.dmaUsageState = DMA_USAGE_OPPORTUNISTIC;
         }
 
+        /* Wait transmit to complete, before user code is indicated*/
+        while(!(obj->spi.spi->STATUS & USART_STATUS_TXC));
         unblockSleepMode(SPI_LEAST_ACTIVE_SLEEPMODE);
 
         /* return to CPP land to say we're finished */
@@ -1088,7 +1298,7 @@
         return 0;
     }
 }
-
+#endif // LDMA_PRESENT
 /** Abort an SPI transfer
  *
  * @param obj The SPI peripheral to stop
@@ -1101,9 +1311,13 @@
     // Determine whether we're running DMA or interrupt
     if (obj->spi.dmaOptionsTX.dmaUsageState == DMA_USAGE_ALLOCATED || obj->spi.dmaOptionsTX.dmaUsageState == DMA_USAGE_TEMPORARY_ALLOCATED) {
         // Cancel the DMA transfers
+#ifdef LDMA_PRESENT
+        LDMA_StopTransfer(obj->spi.dmaOptionsTX.dmaChannel);
+        LDMA_StopTransfer(obj->spi.dmaOptionsRX.dmaChannel);
+#else
         DMA_ChannelEnable(obj->spi.dmaOptionsTX.dmaChannel, false);
         DMA_ChannelEnable(obj->spi.dmaOptionsRX.dmaChannel, false);
-
+#endif
         /* Release the dma channels if they were opportunistically allocated */
         if (obj->spi.dmaOptionsTX.dmaUsageState == DMA_USAGE_TEMPORARY_ALLOCATED) {
             dma_channel_free(obj->spi.dmaOptionsTX.dmaChannel);