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Diff: targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_dma.h
- Revision:
- 157:ff67d9f36b67
- Parent:
- 149:156823d33999
diff -r 95d6b41a828b -r ff67d9f36b67 targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_dma.h
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_dma.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_dma.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_dma.h
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief Header file of DMA HAL module.
******************************************************************************
* @attention
@@ -84,33 +84,21 @@
uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
This parameter can be a value of @ref DMA_mode
@note The circular buffer mode cannot be used if the memory-to-memory
- data transfer is configured on the selected Channel */
+ data transfer is configured on the selected Channel */
uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
This parameter can be a value of @ref DMA_Priority_level */
} DMA_InitTypeDef;
-/**
- * @brief DMA Configuration enumeration values definition
- */
-typedef enum
-{
- DMA_MODE = 0, /*!< Control related DMA mode Parameter in DMA_InitTypeDef */
- DMA_PRIORITY = 1, /*!< Control related priority level Parameter in DMA_InitTypeDef */
-
-} DMA_ControlTypeDef;
-
/**
* @brief HAL DMA State structures definition
*/
typedef enum
{
- HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */
- HAL_DMA_STATE_READY = 0x01, /*!< DMA initialized and ready for use */
- HAL_DMA_STATE_READY_HALF = 0x11, /*!< DMA Half process success */
- HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */
- HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */
- HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */
+ HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */
+ HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */
+ HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */
+ HAL_DMA_STATE_TIMEOUT = 0x03 /*!< DMA timeout state */
}HAL_DMA_StateTypeDef;
/**
@@ -118,10 +106,22 @@
*/
typedef enum
{
- HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */
- HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */
-}HAL_DMA_LevelCompleteTypeDef;
-
+ HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */
+ HAL_DMA_HALF_TRANSFER = 0x01 /*!< Half Transfer */
+}HAL_DMA_LevelCompleteTypeDef;
+
+/**
+ * @brief HAL DMA Callback ID structure definition
+ */
+typedef enum
+{
+ HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */
+ HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */
+ HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */
+ HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */
+ HAL_DMA_XFER_ALL_CB_ID = 0x04 /*!< All */
+}HAL_DMA_CallbackIDTypeDef;
+
/**
* @brief DMA handle Structure definition
*/
@@ -143,9 +143,13 @@
void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
- void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */
+ void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */
__IO uint32_t ErrorCode; /*!< DMA Error code */
+
+ DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */
+
+ uint32_t ChannelIndex; /*!< DMA Channel Index */
} DMA_HandleTypeDef;
/**
* @}
@@ -160,10 +164,11 @@
/** @defgroup DMA_Error_Code DMA Error Code
* @{
*/
-#define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
-#define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */
-#define HAL_DMA_ERROR_NO_XFER ((uint32_t)0x00000004) /*!< no ongoin transfer */
-#define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
+#define HAL_DMA_ERROR_NONE (0x00000000U) /*!< No error */
+#define HAL_DMA_ERROR_TE (0x00000001U) /*!< Transfer error */
+#define HAL_DMA_ERROR_NO_XFER (0x00000004U) /*!< no ongoin transfer */
+#define HAL_DMA_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */
+#define HAL_DMA_ERROR_NOT_SUPPORTED (0x00000100U) /*!< Not supported mode */
/**
* @}
*/
@@ -171,19 +176,19 @@
/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
* @{
*/
-#define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */
+#define DMA_PERIPH_TO_MEMORY (0x00000000U) /*!< Peripheral to memory direction */
#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */
#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_CCR_MEM2MEM) /*!< Memory to memory direction */
/**
* @}
*/
-
+
/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
* @{
*/
#define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */
-#define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode Disable */
+#define DMA_PINC_DISABLE (0x00000000U) /*!< Peripheral increment mode Disable */
/**
* @}
*/
@@ -192,7 +197,7 @@
* @{
*/
#define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */
-#define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode Disable */
+#define DMA_MINC_DISABLE (0x00000000U) /*!< Memory increment mode Disable */
/**
* @}
*/
@@ -200,7 +205,7 @@
/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
* @{
*/
-#define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment : Byte */
+#define DMA_PDATAALIGN_BYTE (0x00000000U) /*!< Peripheral data alignment : Byte */
#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */
#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */
/**
@@ -210,7 +215,7 @@
/** @defgroup DMA_Memory_data_size DMA Memory data size
* @{
*/
-#define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment : Byte */
+#define DMA_MDATAALIGN_BYTE (0x00000000U) /*!< Memory data alignment : Byte */
#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */
#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */
/**
@@ -220,8 +225,8 @@
/** @defgroup DMA_mode DMA mode
* @{
*/
-#define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */
-#define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular mode */
+#define DMA_NORMAL (0x00000000U) /*!< Normal Mode */
+#define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular Mode */
/**
* @}
*/
@@ -229,7 +234,7 @@
/** @defgroup DMA_Priority_level DMA Priority level
* @{
*/
-#define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level : Low */
+#define DMA_PRIORITY_LOW (0x00000000U) /*!< Priority level : Low */
#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */
#define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */
#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */
@@ -251,34 +256,34 @@
/** @defgroup DMA_flag_definitions DMA flag definitions
* @{
*/
-#define DMA_FLAG_GL1 ((uint32_t)0x00000001)
-#define DMA_FLAG_TC1 ((uint32_t)0x00000002)
-#define DMA_FLAG_HT1 ((uint32_t)0x00000004)
-#define DMA_FLAG_TE1 ((uint32_t)0x00000008)
-#define DMA_FLAG_GL2 ((uint32_t)0x00000010)
-#define DMA_FLAG_TC2 ((uint32_t)0x00000020)
-#define DMA_FLAG_HT2 ((uint32_t)0x00000040)
-#define DMA_FLAG_TE2 ((uint32_t)0x00000080)
-#define DMA_FLAG_GL3 ((uint32_t)0x00000100)
-#define DMA_FLAG_TC3 ((uint32_t)0x00000200)
-#define DMA_FLAG_HT3 ((uint32_t)0x00000400)
-#define DMA_FLAG_TE3 ((uint32_t)0x00000800)
-#define DMA_FLAG_GL4 ((uint32_t)0x00001000)
-#define DMA_FLAG_TC4 ((uint32_t)0x00002000)
-#define DMA_FLAG_HT4 ((uint32_t)0x00004000)
-#define DMA_FLAG_TE4 ((uint32_t)0x00008000)
-#define DMA_FLAG_GL5 ((uint32_t)0x00010000)
-#define DMA_FLAG_TC5 ((uint32_t)0x00020000)
-#define DMA_FLAG_HT5 ((uint32_t)0x00040000)
-#define DMA_FLAG_TE5 ((uint32_t)0x00080000)
-#define DMA_FLAG_GL6 ((uint32_t)0x00100000)
-#define DMA_FLAG_TC6 ((uint32_t)0x00200000)
-#define DMA_FLAG_HT6 ((uint32_t)0x00400000)
-#define DMA_FLAG_TE6 ((uint32_t)0x00800000)
-#define DMA_FLAG_GL7 ((uint32_t)0x01000000)
-#define DMA_FLAG_TC7 ((uint32_t)0x02000000)
-#define DMA_FLAG_HT7 ((uint32_t)0x04000000)
-#define DMA_FLAG_TE7 ((uint32_t)0x08000000)
+#define DMA_FLAG_GL1 (0x00000001U)
+#define DMA_FLAG_TC1 (0x00000002U)
+#define DMA_FLAG_HT1 (0x00000004U)
+#define DMA_FLAG_TE1 (0x00000008U)
+#define DMA_FLAG_GL2 (0x00000010U)
+#define DMA_FLAG_TC2 (0x00000020U)
+#define DMA_FLAG_HT2 (0x00000040U)
+#define DMA_FLAG_TE2 (0x00000080U)
+#define DMA_FLAG_GL3 (0x00000100U)
+#define DMA_FLAG_TC3 (0x00000200U)
+#define DMA_FLAG_HT3 (0x00000400U)
+#define DMA_FLAG_TE3 (0x00000800U)
+#define DMA_FLAG_GL4 (0x00001000U)
+#define DMA_FLAG_TC4 (0x00002000U)
+#define DMA_FLAG_HT4 (0x00004000U)
+#define DMA_FLAG_TE4 (0x00008000U)
+#define DMA_FLAG_GL5 (0x00010000U)
+#define DMA_FLAG_TC5 (0x00020000U)
+#define DMA_FLAG_HT5 (0x00040000U)
+#define DMA_FLAG_TE5 (0x00080000U)
+#define DMA_FLAG_GL6 (0x00100000U)
+#define DMA_FLAG_TC6 (0x00200000U)
+#define DMA_FLAG_HT6 (0x00400000U)
+#define DMA_FLAG_TE6 (0x00800000U)
+#define DMA_FLAG_GL7 (0x01000000U)
+#define DMA_FLAG_TC7 (0x02000000U)
+#define DMA_FLAG_HT7 (0x04000000U)
+#define DMA_FLAG_TE7 (0x08000000U)
/**
* @}
*/
@@ -302,16 +307,16 @@
/**
* @brief Enable the specified DMA Channel.
* @param __HANDLE__: DMA handle
- * @retval None.
+ * @retval None
*/
-#define __HAL_DMA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
+#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)
/**
* @brief Disable the specified DMA Channel.
* @param __HANDLE__: DMA handle
- * @retval None.
+ * @retval None
*/
-#define __HAL_DMA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
+#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)
/* Interrupt & Flag management */
@@ -326,7 +331,7 @@
* @arg DMA_IT_TE: Transfer error interrupt mask
* @retval None
*/
-#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CCR, (__INTERRUPT__)))
+#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
/**
* @brief Disables the specified DMA Channel interrupts.
@@ -338,7 +343,7 @@
* @arg DMA_IT_TE: Transfer error interrupt mask
* @retval None
*/
-#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CCR , (__INTERRUPT__)))
+#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
/**
* @brief Checks whether the specified DMA Channel interrupt is enabled or disabled.
@@ -350,7 +355,7 @@
* @arg DMA_IT_TE: Transfer error interrupt mask
* @retval The state of DMA_IT (SET or RESET).
*/
-#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
/**
* @brief Returns the number of remaining data units in the current DMAy Channelx transfer.
@@ -368,7 +373,7 @@
#include "stm32f3xx_hal_dma_ex.h"
/* Exported functions --------------------------------------------------------*/
-/** @addtogroup DMA_Exported_Functions DMA Exported Functions
+/** @addtogroup DMA_Exported_Functions
* @{
*/
@@ -385,13 +390,15 @@
/** @addtogroup DMA_Exported_Functions_Group2 Input and Output operation functions
* @{
*/
-/* IO operation functions *****************************************************/
+/* Input and Output operation functions *****************************************************/
HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma));
+HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
/**
* @}
*/
@@ -415,7 +422,7 @@
* @{
*/
-#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
+#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U))
#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \