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targets/TARGET_Maxim/TARGET_MAX32630/device/owm_regs.h@157:ff67d9f36b67, 2017-02-02 (annotated)

Committer:
<>
Date:
Thu Feb 02 17:01:33 2017 +0000
Revision:
157:ff67d9f36b67
This updates the lib to the mbed lib v135

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 157:ff67d9f36b67 1 /**
<> 157:ff67d9f36b67 2 * @file
<> 157:ff67d9f36b67 3 * @brief Type definitions for the 1-Wire Master Interface
<> 157:ff67d9f36b67 4 */
<> 157:ff67d9f36b67 5 /* ****************************************************************************
<> 157:ff67d9f36b67 6 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
<> 157:ff67d9f36b67 7 *
<> 157:ff67d9f36b67 8 * Permission is hereby granted, free of charge, to any person obtaining a
<> 157:ff67d9f36b67 9 * copy of this software and associated documentation files (the "Software"),
<> 157:ff67d9f36b67 10 * to deal in the Software without restriction, including without limitation
<> 157:ff67d9f36b67 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 157:ff67d9f36b67 12 * and/or sell copies of the Software, and to permit persons to whom the
<> 157:ff67d9f36b67 13 * Software is furnished to do so, subject to the following conditions:
<> 157:ff67d9f36b67 14 *
<> 157:ff67d9f36b67 15 * The above copyright notice and this permission notice shall be included
<> 157:ff67d9f36b67 16 * in all copies or substantial portions of the Software.
<> 157:ff67d9f36b67 17 *
<> 157:ff67d9f36b67 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 157:ff67d9f36b67 19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 157:ff67d9f36b67 20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 157:ff67d9f36b67 21 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 157:ff67d9f36b67 22 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 157:ff67d9f36b67 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 157:ff67d9f36b67 24 * OTHER DEALINGS IN THE SOFTWARE.
<> 157:ff67d9f36b67 25 *
<> 157:ff67d9f36b67 26 * Except as contained in this notice, the name of Maxim Integrated
<> 157:ff67d9f36b67 27 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 157:ff67d9f36b67 28 * Products, Inc. Branding Policy.
<> 157:ff67d9f36b67 29 *
<> 157:ff67d9f36b67 30 * The mere transfer of this software does not imply any licenses
<> 157:ff67d9f36b67 31 * of trade secrets, proprietary technology, copyrights, patents,
<> 157:ff67d9f36b67 32 * trademarks, maskwork rights, or any other form of intellectual
<> 157:ff67d9f36b67 33 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 157:ff67d9f36b67 34 * ownership rights.
<> 157:ff67d9f36b67 35 *
<> 157:ff67d9f36b67 36 * $Date: 2016-10-10 19:22:03 -0500 (Mon, 10 Oct 2016) $
<> 157:ff67d9f36b67 37 * $Revision: 24666 $
<> 157:ff67d9f36b67 38 *
<> 157:ff67d9f36b67 39 **************************************************************************** */
<> 157:ff67d9f36b67 40
<> 157:ff67d9f36b67 41 /* Define to prevent redundant inclusion */
<> 157:ff67d9f36b67 42 #ifndef _MXC_OWM_REGS_H_
<> 157:ff67d9f36b67 43 #define _MXC_OWM_REGS_H_
<> 157:ff67d9f36b67 44
<> 157:ff67d9f36b67 45 #include <stdint.h>
<> 157:ff67d9f36b67 46
<> 157:ff67d9f36b67 47 #ifdef __cplusplus
<> 157:ff67d9f36b67 48 extern "C" {
<> 157:ff67d9f36b67 49 #endif
<> 157:ff67d9f36b67 50
<> 157:ff67d9f36b67 51 /*
<> 157:ff67d9f36b67 52 If types are not defined elsewhere (CMSIS) define them here
<> 157:ff67d9f36b67 53 */
<> 157:ff67d9f36b67 54 ///@cond
<> 157:ff67d9f36b67 55 #ifndef __IO
<> 157:ff67d9f36b67 56 #define __IO volatile
<> 157:ff67d9f36b67 57 #endif
<> 157:ff67d9f36b67 58 #ifndef __I
<> 157:ff67d9f36b67 59 #define __I volatile const
<> 157:ff67d9f36b67 60 #endif
<> 157:ff67d9f36b67 61 #ifndef __O
<> 157:ff67d9f36b67 62 #define __O volatile
<> 157:ff67d9f36b67 63 #endif
<> 157:ff67d9f36b67 64 #ifndef __RO
<> 157:ff67d9f36b67 65 #define __RO volatile const
<> 157:ff67d9f36b67 66 #endif
<> 157:ff67d9f36b67 67 ///@endcond
<> 157:ff67d9f36b67 68
<> 157:ff67d9f36b67 69
<> 157:ff67d9f36b67 70 /**
<> 157:ff67d9f36b67 71 * @ingroup owm
<> 157:ff67d9f36b67 72 * @defgroup owm_registers Registers
<> 157:ff67d9f36b67 73 * @brief Registers, Bit Masks and Bit Positions
<> 157:ff67d9f36b67 74 * @{
<> 157:ff67d9f36b67 75 */
<> 157:ff67d9f36b67 76 /**
<> 157:ff67d9f36b67 77 * Structure type for the 1-Wire Master module registers allowing direct 32-bit access to each register.
<> 157:ff67d9f36b67 78 */
<> 157:ff67d9f36b67 79 typedef struct {
<> 157:ff67d9f36b67 80 __IO uint32_t cfg; /**< <tt>\b 0x0000:</tt> OWM_CFG Register - 1-Wire Master Configuration */
<> 157:ff67d9f36b67 81 __IO uint32_t clk_div_1us; /**< <tt>\b 0x0004:</tt> OWM_CLK_DIV_1US Register - 1-Wire Master Clock Divisor */
<> 157:ff67d9f36b67 82 __IO uint32_t ctrl_stat; /**< <tt>\b 0x0008:</tt> OWM_CTRL_STAT Register - 1-Wire Master Control/Status */
<> 157:ff67d9f36b67 83 __IO uint32_t data; /**< <tt>\b 0x000C:</tt> OWM_DATA Register - 1-Wire Master Data Buffer */
<> 157:ff67d9f36b67 84 __IO uint32_t intfl; /**< <tt>\b 0x0010:</tt> OWM_INTFL Register - 1-Wire Master Interrupt Flags */
<> 157:ff67d9f36b67 85 __IO uint32_t inten; /**< <tt>\b 0x0014:</tt> OWM_INTEN Register - 1-Wire Master Interrupt Enables */
<> 157:ff67d9f36b67 86 } mxc_owm_regs_t;
<> 157:ff67d9f36b67 87 /**@} end of group owm_registers */
<> 157:ff67d9f36b67 88
<> 157:ff67d9f36b67 89 /**
<> 157:ff67d9f36b67 90 * @ingroup owm_registers
<> 157:ff67d9f36b67 91 * @defgroup OWM_Register_Offsets Register Offsets
<> 157:ff67d9f36b67 92 * @brief 1-Wire Master register offsets from the 1-Wire Master Base Peripheral Address.
<> 157:ff67d9f36b67 93 * @{
<> 157:ff67d9f36b67 94 */
<> 157:ff67d9f36b67 95 #define MXC_R_OWM_OFFS_CFG ((uint32_t)0x00000000UL) /**< Offset from the OWM Base Peripheral Address:<tt>\b 0x0000:</tt>*/
<> 157:ff67d9f36b67 96 #define MXC_R_OWM_OFFS_CLK_DIV_1US ((uint32_t)0x00000004UL) /**< Offset from the OWM Base Peripheral Address:<tt>\b 0x0004:</tt>*/
<> 157:ff67d9f36b67 97 #define MXC_R_OWM_OFFS_CTRL_STAT ((uint32_t)0x00000008UL) /**< Offset from the OWM Base Peripheral Address:<tt>\b 0x0008:</tt>*/
<> 157:ff67d9f36b67 98 #define MXC_R_OWM_OFFS_DATA ((uint32_t)0x0000000CUL) /**< Offset from the OWM Base Peripheral Address:<tt>\b 0x000C:</tt>*/
<> 157:ff67d9f36b67 99 #define MXC_R_OWM_OFFS_INTFL ((uint32_t)0x00000010UL) /**< Offset from the OWM Base Peripheral Address:<tt>\b 0x0010:</tt>*/
<> 157:ff67d9f36b67 100 #define MXC_R_OWM_OFFS_INTEN ((uint32_t)0x00000014UL) /**< Offset from the OWM Base Peripheral Address:<tt>\b 0x0014:</tt>*/
<> 157:ff67d9f36b67 101 /**@} end of group OWM_Register_Offsets */
<> 157:ff67d9f36b67 102
<> 157:ff67d9f36b67 103 /*
<> 157:ff67d9f36b67 104 Field positions and masks for module OWM.
<> 157:ff67d9f36b67 105 */
<> 157:ff67d9f36b67 106 /**
<> 157:ff67d9f36b67 107 * @ingroup owm_registers
<> 157:ff67d9f36b67 108 * @defgroup owm_cfg OWM_CFG
<> 157:ff67d9f36b67 109 * @brief Field Positions and Masks
<> 157:ff67d9f36b67 110 */
<> 157:ff67d9f36b67 111 #define MXC_F_OWM_CFG_LONG_LINE_MODE_POS 0 /**< LONG_LINE_MODE Position */
<> 157:ff67d9f36b67 112 #define MXC_F_OWM_CFG_LONG_LINE_MODE ((uint32_t)(0x00000001UL << MXC_F_OWM_CFG_LONG_LINE_MODE_POS)) /**< LONG_LINE_MODE Mask */
<> 157:ff67d9f36b67 113 #define MXC_F_OWM_CFG_FORCE_PRES_DET_POS 1 /**< FORCE_PRES_DET Position */
<> 157:ff67d9f36b67 114 #define MXC_F_OWM_CFG_FORCE_PRES_DET ((uint32_t)(0x00000001UL << MXC_F_OWM_CFG_FORCE_PRES_DET_POS)) /**< FORCE_PRES_DET Mask */
<> 157:ff67d9f36b67 115 #define MXC_F_OWM_CFG_BIT_BANG_EN_POS 2 /**< BIT_BANG_EN Position */
<> 157:ff67d9f36b67 116 #define MXC_F_OWM_CFG_BIT_BANG_EN ((uint32_t)(0x00000001UL << MXC_F_OWM_CFG_BIT_BANG_EN_POS)) /**< BIT_BANG_EN Mask */
<> 157:ff67d9f36b67 117 #define MXC_F_OWM_CFG_EXT_PULLUP_MODE_POS 3 /**< EXT_PULLUP_MODE Position */
<> 157:ff67d9f36b67 118 #define MXC_F_OWM_CFG_EXT_PULLUP_MODE ((uint32_t)(0x00000001UL << MXC_F_OWM_CFG_EXT_PULLUP_MODE_POS)) /**< EXT_PULLUP_MODE Mask */
<> 157:ff67d9f36b67 119 #define MXC_F_OWM_CFG_EXT_PULLUP_ENABLE_POS 4 /**< EXT_PULLUP_ENABLE Position */
<> 157:ff67d9f36b67 120 #define MXC_F_OWM_CFG_EXT_PULLUP_ENABLE ((uint32_t)(0x00000001UL << MXC_F_OWM_CFG_EXT_PULLUP_ENABLE_POS)) /**< EXT_PULLUP_ENABLE Mask */
<> 157:ff67d9f36b67 121 #define MXC_F_OWM_CFG_SINGLE_BIT_MODE_POS 5 /**< SINGLE_BIT_MODE Position */
<> 157:ff67d9f36b67 122 #define MXC_F_OWM_CFG_SINGLE_BIT_MODE ((uint32_t)(0x00000001UL << MXC_F_OWM_CFG_SINGLE_BIT_MODE_POS)) /**< SINGLE_BIT_MODE Mask */
<> 157:ff67d9f36b67 123 #define MXC_F_OWM_CFG_OVERDRIVE_POS 6 /**< OVERDRIVE Position */
<> 157:ff67d9f36b67 124 #define MXC_F_OWM_CFG_OVERDRIVE ((uint32_t)(0x00000001UL << MXC_F_OWM_CFG_OVERDRIVE_POS)) /**< OVERDRIVE Mask */
<> 157:ff67d9f36b67 125 #define MXC_F_OWM_CFG_INT_PULLUP_ENABLE_POS 7 /**< INT_PULLUP_ENABLE Position */
<> 157:ff67d9f36b67 126 #define MXC_F_OWM_CFG_INT_PULLUP_ENABLE ((uint32_t)(0x00000001UL << MXC_F_OWM_CFG_INT_PULLUP_ENABLE_POS)) /**< INT_PULLUP_ENABLE Mask */
<> 157:ff67d9f36b67 127 /**@} end of group owm_cfg*/
<> 157:ff67d9f36b67 128 /**
<> 157:ff67d9f36b67 129 * @ingroup owm_registers
<> 157:ff67d9f36b67 130 * @defgroup owm_clk_div OWM_CLK_DIV
<> 157:ff67d9f36b67 131 * @brief Field Positions and Masks
<> 157:ff67d9f36b67 132 */
<> 157:ff67d9f36b67 133 #define MXC_F_OWM_CLK_DIV_1US_DIVISOR_POS 0 /**< 1US_DIVISOR Position */
<> 157:ff67d9f36b67 134 #define MXC_F_OWM_CLK_DIV_1US_DIVISOR ((uint32_t)(0x000000FFUL << MXC_F_OWM_CLK_DIV_1US_DIVISOR_POS)) /**< 1US_DIVISOR Mask */
<> 157:ff67d9f36b67 135 /**@} end of group owm_clk_cfg*/
<> 157:ff67d9f36b67 136 /**
<> 157:ff67d9f36b67 137 * @ingroup owm_registers
<> 157:ff67d9f36b67 138 * @defgroup owm_ctrl_stat OWM_CTRL_STAT
<> 157:ff67d9f36b67 139 * @brief Field Positions and Masks
<> 157:ff67d9f36b67 140 */
<> 157:ff67d9f36b67 141 #define MXC_F_OWM_CTRL_STAT_START_OW_RESET_POS 0 /**< START_OW_RESET Position */
<> 157:ff67d9f36b67 142 #define MXC_F_OWM_CTRL_STAT_START_OW_RESET ((uint32_t)(0x00000001UL << MXC_F_OWM_CTRL_STAT_START_OW_RESET_POS)) /**< START_OW_RESET Mask */
<> 157:ff67d9f36b67 143 #define MXC_F_OWM_CTRL_STAT_SRA_MODE_POS 1 /**< SRA_MODE Position */
<> 157:ff67d9f36b67 144 #define MXC_F_OWM_CTRL_STAT_SRA_MODE ((uint32_t)(0x00000001UL << MXC_F_OWM_CTRL_STAT_SRA_MODE_POS)) /**< SRA_MODE Mask */
<> 157:ff67d9f36b67 145 #define MXC_F_OWM_CTRL_STAT_BIT_BANG_OE_POS 2 /**< BIT_BANG_OE Position */
<> 157:ff67d9f36b67 146 #define MXC_F_OWM_CTRL_STAT_BIT_BANG_OE ((uint32_t)(0x00000001UL << MXC_F_OWM_CTRL_STAT_BIT_BANG_OE_POS)) /**< BIT_BANG_OE Mask */
<> 157:ff67d9f36b67 147 #define MXC_F_OWM_CTRL_STAT_OW_INPUT_POS 3 /**< OW_INPUT Position */
<> 157:ff67d9f36b67 148 #define MXC_F_OWM_CTRL_STAT_OW_INPUT ((uint32_t)(0x00000001UL << MXC_F_OWM_CTRL_STAT_OW_INPUT_POS)) /**< OW_INPUT Mask */
<> 157:ff67d9f36b67 149 #define MXC_F_OWM_CTRL_STAT_OD_SPEC_MODE_POS 4 /**< OD_SPEC_MODE Position */
<> 157:ff67d9f36b67 150 #define MXC_F_OWM_CTRL_STAT_OD_SPEC_MODE ((uint32_t)(0x00000001UL << MXC_F_OWM_CTRL_STAT_OD_SPEC_MODE_POS)) /**< OD_SPEC_MODE Mask */
<> 157:ff67d9f36b67 151 #define MXC_F_OWM_CTRL_STAT_EXT_PULLUP_POL_POS 5 /**< EXT_PULLUP_POL Position */
<> 157:ff67d9f36b67 152 #define MXC_F_OWM_CTRL_STAT_EXT_PULLUP_POL ((uint32_t)(0x00000001UL << MXC_F_OWM_CTRL_STAT_EXT_PULLUP_POL_POS)) /**< EXT_PULLUP_POL Mask */
<> 157:ff67d9f36b67 153 #define MXC_F_OWM_CTRL_STAT_PRESENCE_DETECT_POS 7 /**< PRESENCE_DETECT Position */
<> 157:ff67d9f36b67 154 #define MXC_F_OWM_CTRL_STAT_PRESENCE_DETECT ((uint32_t)(0x00000001UL << MXC_F_OWM_CTRL_STAT_PRESENCE_DETECT_POS)) /**< PRESENCE_DETECT Mask */
<> 157:ff67d9f36b67 155 /**@} end of group owm_ctrl*/
<> 157:ff67d9f36b67 156 /**
<> 157:ff67d9f36b67 157 * @ingroup owm_registers
<> 157:ff67d9f36b67 158 * @defgroup owm_data OWM_DATA
<> 157:ff67d9f36b67 159 * @brief Field Positions and Masks
<> 157:ff67d9f36b67 160 */
<> 157:ff67d9f36b67 161 #define MXC_F_OWM_DATA_TX_RX_POS 0 /**< TX_RX Position */
<> 157:ff67d9f36b67 162 #define MXC_F_OWM_DATA_TX_RX ((uint32_t)(0x000000FFUL << MXC_F_OWM_DATA_TX_RX_POS)) /**< TX_RX Mask */
<> 157:ff67d9f36b67 163 /**@} end of group owm_data*/
<> 157:ff67d9f36b67 164 /**
<> 157:ff67d9f36b67 165 * @ingroup owm_registers
<> 157:ff67d9f36b67 166 * @defgroup owm_intfl OWM_INTFL
<> 157:ff67d9f36b67 167 * @brief Field Positions and Masks
<> 157:ff67d9f36b67 168 */
<> 157:ff67d9f36b67 169 #define MXC_F_OWM_INTFL_OW_RESET_DONE_POS 0 /**< OW_RESET_DONE Position */
<> 157:ff67d9f36b67 170 #define MXC_F_OWM_INTFL_OW_RESET_DONE ((uint32_t)(0x00000001UL << MXC_F_OWM_INTFL_OW_RESET_DONE_POS)) /**< OW_RESET_DONE Mask */
<> 157:ff67d9f36b67 171 #define MXC_F_OWM_INTFL_TX_DATA_EMPTY_POS 1 /**< TX_DATA_EMPTY Position */
<> 157:ff67d9f36b67 172 #define MXC_F_OWM_INTFL_TX_DATA_EMPTY ((uint32_t)(0x00000001UL << MXC_F_OWM_INTFL_TX_DATA_EMPTY_POS)) /**< TX_DATA_EMPTY Mask */
<> 157:ff67d9f36b67 173 #define MXC_F_OWM_INTFL_RX_DATA_READY_POS 2 /**< RX_DATA_READY Position */
<> 157:ff67d9f36b67 174 #define MXC_F_OWM_INTFL_RX_DATA_READY ((uint32_t)(0x00000001UL << MXC_F_OWM_INTFL_RX_DATA_READY_POS)) /**< RX_DATA_READY Mask */
<> 157:ff67d9f36b67 175 #define MXC_F_OWM_INTFL_LINE_SHORT_POS 3 /**< LINE_SHORT Position */
<> 157:ff67d9f36b67 176 #define MXC_F_OWM_INTFL_LINE_SHORT ((uint32_t)(0x00000001UL << MXC_F_OWM_INTFL_LINE_SHORT_POS)) /**< LINE_SHORT Mask */
<> 157:ff67d9f36b67 177 #define MXC_F_OWM_INTFL_LINE_LOW_POS 4 /**< LINE_LOW Position */
<> 157:ff67d9f36b67 178 #define MXC_F_OWM_INTFL_LINE_LOW ((uint32_t)(0x00000001UL << MXC_F_OWM_INTFL_LINE_LOW_POS)) /**< LINE_LOW Mask */
<> 157:ff67d9f36b67 179 /**@} end of group owm_intfl*/
<> 157:ff67d9f36b67 180 /**
<> 157:ff67d9f36b67 181 * @ingroup owm_registers
<> 157:ff67d9f36b67 182 * @defgroup owm_inten OWM_INTEN
<> 157:ff67d9f36b67 183 * @brief Field Positions and Masks
<> 157:ff67d9f36b67 184 */
<> 157:ff67d9f36b67 185 #define MXC_F_OWM_INTEN_OW_RESET_DONE_POS 0 /**< OW_RESET_DONE Position */
<> 157:ff67d9f36b67 186 #define MXC_F_OWM_INTEN_OW_RESET_DONE ((uint32_t)(0x00000001UL << MXC_F_OWM_INTEN_OW_RESET_DONE_POS)) /**< OW_RESET_DONE Mask */
<> 157:ff67d9f36b67 187 #define MXC_F_OWM_INTEN_TX_DATA_EMPTY_POS 1 /**< TX_DATA_EMPTY Position */
<> 157:ff67d9f36b67 188 #define MXC_F_OWM_INTEN_TX_DATA_EMPTY ((uint32_t)(0x00000001UL << MXC_F_OWM_INTEN_TX_DATA_EMPTY_POS)) /**< TX_DATA_EMPTY Mask */
<> 157:ff67d9f36b67 189 #define MXC_F_OWM_INTEN_RX_DATA_READY_POS 2 /**< RX_DATA_READY Position */
<> 157:ff67d9f36b67 190 #define MXC_F_OWM_INTEN_RX_DATA_READY ((uint32_t)(0x00000001UL << MXC_F_OWM_INTEN_RX_DATA_READY_POS)) /**< RX_DATA_READY Mask */
<> 157:ff67d9f36b67 191 #define MXC_F_OWM_INTEN_LINE_SHORT_POS 3 /**< LINE_SHORT Position */
<> 157:ff67d9f36b67 192 #define MXC_F_OWM_INTEN_LINE_SHORT ((uint32_t)(0x00000001UL << MXC_F_OWM_INTEN_LINE_SHORT_POS)) /**< LINE_SHORT Mask */
<> 157:ff67d9f36b67 193 #define MXC_F_OWM_INTEN_LINE_LOW_POS 4 /**< LINE_LOW Position */
<> 157:ff67d9f36b67 194 #define MXC_F_OWM_INTEN_LINE_LOW ((uint32_t)(0x00000001UL << MXC_F_OWM_INTEN_LINE_LOW_POS)) /**< LINE_LOW Mask */
<> 157:ff67d9f36b67 195 /**@} end of group owm_inten*/
<> 157:ff67d9f36b67 196 /**
<> 157:ff67d9f36b67 197 * @ingroup owm_cfg
<> 157:ff67d9f36b67 198 * @{
<> 157:ff67d9f36b67 199 */
<> 157:ff67d9f36b67 200 #define MXC_V_OWM_CFG_EXT_PULLUP_MODE_UNUSED ((uint32_t)(0x00000000UL)) /**< External Pullup Mode Value: Unused */
<> 157:ff67d9f36b67 201 #define MXC_V_OWM_CFG_EXT_PULLUP_MODE_USED ((uint32_t)(0x00000001UL)) /**< External Pullup Mode Value: Used */
<> 157:ff67d9f36b67 202 /**@}*/
<> 157:ff67d9f36b67 203 /**
<> 157:ff67d9f36b67 204 * @ingroup owm_ctrl_stat
<> 157:ff67d9f36b67 205 * @{
<> 157:ff67d9f36b67 206 */
<> 157:ff67d9f36b67 207 #define MXC_V_OWM_CTRL_STAT_OD_SPEC_MODE_12US ((uint32_t)(0x00000000UL)) /**< Overdrive speed setting 12us. */
<> 157:ff67d9f36b67 208 #define MXC_V_OWM_CTRL_STAT_OD_SPEC_MODE_10US ((uint32_t)(0x00000001UL)) /**< Overdrive speed setting 10us. */
<> 157:ff67d9f36b67 209
<> 157:ff67d9f36b67 210 #define MXC_V_OWM_CTRL_STAT_EXT_PULLUP_POL_ACT_HIGH ((uint32_t)(0x00000000UL)) /**< External Pullup Pin Polarity Active High */
<> 157:ff67d9f36b67 211 #define MXC_V_OWM_CTRL_STAT_EXT_PULLUP_POL_ACT_LOW ((uint32_t)(0x00000001UL)) /**< External Pullup Pin Polarity Active Low */
<> 157:ff67d9f36b67 212 /**@}*/
<> 157:ff67d9f36b67 213
<> 157:ff67d9f36b67 214 #ifdef __cplusplus
<> 157:ff67d9f36b67 215 }
<> 157:ff67d9f36b67 216 #endif
<> 157:ff67d9f36b67 217
<> 157:ff67d9f36b67 218 #endif /* _MXC_OWM_REGS_H_ */