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targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/mbed_overrides.c@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Child:
20:6bf7f0bb0f66
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /* mbed Microcontroller Library
bogdanm 0:9b334a45a8ff 2 * Copyright (c) 2006-2013 ARM Limited
bogdanm 0:9b334a45a8ff 3 *
bogdanm 0:9b334a45a8ff 4 * Licensed under the Apache License, Version 2.0 (the "License");
bogdanm 0:9b334a45a8ff 5 * you may not use this file except in compliance with the License.
bogdanm 0:9b334a45a8ff 6 * You may obtain a copy of the License at
bogdanm 0:9b334a45a8ff 7 *
bogdanm 0:9b334a45a8ff 8 * http://www.apache.org/licenses/LICENSE-2.0
bogdanm 0:9b334a45a8ff 9 *
bogdanm 0:9b334a45a8ff 10 * Unless required by applicable law or agreed to in writing, software
bogdanm 0:9b334a45a8ff 11 * distributed under the License is distributed on an "AS IS" BASIS,
bogdanm 0:9b334a45a8ff 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
bogdanm 0:9b334a45a8ff 13 * See the License for the specific language governing permissions and
bogdanm 0:9b334a45a8ff 14 * limitations under the License.
bogdanm 0:9b334a45a8ff 15 */
bogdanm 0:9b334a45a8ff 16
bogdanm 0:9b334a45a8ff 17 #include "cmsis.h"
bogdanm 0:9b334a45a8ff 18
bogdanm 0:9b334a45a8ff 19
bogdanm 0:9b334a45a8ff 20 #define SPIM1_SCK_PIN 11u /**< SPI clock GPIO pin number. */
bogdanm 0:9b334a45a8ff 21 #define SPIM1_MOSI_PIN 15u /**< SPI Master Out Slave In GPIO pin number. */
bogdanm 0:9b334a45a8ff 22 #define SPIM1_MISO_PIN 9u /**< SPI Master In Slave Out GPIO pin number. */
bogdanm 0:9b334a45a8ff 23 #define SPIM1_SS_PIN 28u /**< SPI Slave Select GPIO pin number. */
bogdanm 0:9b334a45a8ff 24
bogdanm 0:9b334a45a8ff 25 #define CMD_POWER_UP (0xAB)
bogdanm 0:9b334a45a8ff 26 #define CMD_POWER_DOWN (0xB9)
bogdanm 0:9b334a45a8ff 27
bogdanm 0:9b334a45a8ff 28 void flash_init(void)
bogdanm 0:9b334a45a8ff 29 {
bogdanm 0:9b334a45a8ff 30 NRF_GPIO->PIN_CNF[SPIM1_MOSI_PIN] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
bogdanm 0:9b334a45a8ff 31 | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
bogdanm 0:9b334a45a8ff 32 | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
bogdanm 0:9b334a45a8ff 33 | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
bogdanm 0:9b334a45a8ff 34 | (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos);
bogdanm 0:9b334a45a8ff 35 NRF_GPIO->PIN_CNF[SPIM1_MISO_PIN] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
bogdanm 0:9b334a45a8ff 36 | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
bogdanm 0:9b334a45a8ff 37 | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
bogdanm 0:9b334a45a8ff 38 | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
bogdanm 0:9b334a45a8ff 39 | (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos);
bogdanm 0:9b334a45a8ff 40 NRF_GPIO->PIN_CNF[SPIM1_SCK_PIN] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
bogdanm 0:9b334a45a8ff 41 | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
bogdanm 0:9b334a45a8ff 42 | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
bogdanm 0:9b334a45a8ff 43 | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
bogdanm 0:9b334a45a8ff 44 | (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos);
bogdanm 0:9b334a45a8ff 45
bogdanm 0:9b334a45a8ff 46 NRF_GPIO->PIN_CNF[SPIM1_SS_PIN] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
bogdanm 0:9b334a45a8ff 47 | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
bogdanm 0:9b334a45a8ff 48 | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
bogdanm 0:9b334a45a8ff 49 | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
bogdanm 0:9b334a45a8ff 50 | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
bogdanm 0:9b334a45a8ff 51 //cs = 1;
bogdanm 0:9b334a45a8ff 52 NRF_GPIO->OUTSET = (GPIO_OUTSET_PIN28_High << GPIO_OUTSET_PIN28_Pos);
bogdanm 0:9b334a45a8ff 53
bogdanm 0:9b334a45a8ff 54 NRF_SPI1->ENABLE = 1;
bogdanm 0:9b334a45a8ff 55 NRF_SPI1->PSELSCK = SPIM1_SCK_PIN;
bogdanm 0:9b334a45a8ff 56 NRF_SPI1->PSELMOSI = SPIM1_MISO_PIN;
bogdanm 0:9b334a45a8ff 57 NRF_SPI1->PSELMISO = SPIM1_MOSI_PIN;
bogdanm 0:9b334a45a8ff 58 //spi.frequency(1000000);
bogdanm 0:9b334a45a8ff 59 NRF_SPI1->FREQUENCY = 0x10000000; //1MHz
bogdanm 0:9b334a45a8ff 60
bogdanm 0:9b334a45a8ff 61 //spi.format(8,0);
bogdanm 0:9b334a45a8ff 62 uint32_t config_mode = 0;
bogdanm 0:9b334a45a8ff 63 config_mode = (SPI_CONFIG_CPHA_Leading << SPI_CONFIG_CPHA_Pos) | (SPI_CONFIG_CPOL_ActiveHigh << SPI_CONFIG_CPOL_Pos); //mode 0
bogdanm 0:9b334a45a8ff 64 NRF_SPI1->CONFIG = (config_mode | (SPI_CONFIG_ORDER_MsbFirst << SPI_CONFIG_ORDER_Pos));
bogdanm 0:9b334a45a8ff 65 //cs = 0;
bogdanm 0:9b334a45a8ff 66 NRF_GPIO->OUTCLR = (GPIO_OUTCLR_PIN28_Clear << GPIO_OUTCLR_PIN28_Pos);
bogdanm 0:9b334a45a8ff 67 //spi.write(CMD_POWER_UP);
bogdanm 0:9b334a45a8ff 68 while (!NRF_SPI1->EVENTS_READY == 0) {
bogdanm 0:9b334a45a8ff 69 }
bogdanm 0:9b334a45a8ff 70 NRF_SPI1->TXD = (uint32_t)CMD_POWER_UP;
bogdanm 0:9b334a45a8ff 71 while (!NRF_SPI1->EVENTS_READY == 1) {
bogdanm 0:9b334a45a8ff 72 }
bogdanm 0:9b334a45a8ff 73 NRF_SPI1->EVENTS_READY = 0;
bogdanm 0:9b334a45a8ff 74 NRF_SPI1->RXD;
bogdanm 0:9b334a45a8ff 75 //wait_ms(30);
bogdanm 0:9b334a45a8ff 76 // Deselect the device
bogdanm 0:9b334a45a8ff 77 //cs = 1;
bogdanm 0:9b334a45a8ff 78 NRF_GPIO->OUTSET = (GPIO_OUTSET_PIN28_High << GPIO_OUTSET_PIN28_Pos);
bogdanm 0:9b334a45a8ff 79
bogdanm 0:9b334a45a8ff 80 }
bogdanm 0:9b334a45a8ff 81
bogdanm 0:9b334a45a8ff 82 void flash_powerDown(void)
bogdanm 0:9b334a45a8ff 83 {
bogdanm 0:9b334a45a8ff 84 NRF_GPIO->OUTCLR = (GPIO_OUTCLR_PIN28_Clear << GPIO_OUTCLR_PIN28_Pos);
bogdanm 0:9b334a45a8ff 85 //spi.write(CMD_POWER_DOWN);
bogdanm 0:9b334a45a8ff 86 while (!NRF_SPI1->EVENTS_READY == 0) {
bogdanm 0:9b334a45a8ff 87 }
bogdanm 0:9b334a45a8ff 88 NRF_SPI1->TXD = (uint32_t)CMD_POWER_DOWN;
bogdanm 0:9b334a45a8ff 89 while (!NRF_SPI1->EVENTS_READY == 1) {
bogdanm 0:9b334a45a8ff 90 }
bogdanm 0:9b334a45a8ff 91 NRF_SPI1->EVENTS_READY = 0;
bogdanm 0:9b334a45a8ff 92 NRF_SPI1->RXD;
bogdanm 0:9b334a45a8ff 93 NRF_GPIO->OUTSET = (GPIO_OUTSET_PIN28_High << GPIO_OUTSET_PIN28_Pos);
bogdanm 0:9b334a45a8ff 94
bogdanm 0:9b334a45a8ff 95 //wait for sleep
bogdanm 0:9b334a45a8ff 96 //wait_us(3);
bogdanm 0:9b334a45a8ff 97 }
bogdanm 0:9b334a45a8ff 98
bogdanm 0:9b334a45a8ff 99 void mbed_sdk_init()
bogdanm 0:9b334a45a8ff 100 {
bogdanm 0:9b334a45a8ff 101 // Default SWIO setting, pull SWIO(p19) to low for turning antenna switch to BLE radiated path
bogdanm 0:9b334a45a8ff 102 NRF_GPIO->PIN_CNF[19] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
bogdanm 0:9b334a45a8ff 103 | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
bogdanm 0:9b334a45a8ff 104 | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
bogdanm 0:9b334a45a8ff 105 | (GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos)
bogdanm 0:9b334a45a8ff 106 | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
bogdanm 0:9b334a45a8ff 107
bogdanm 0:9b334a45a8ff 108 NRF_GPIO->OUTCLR = (GPIO_OUTCLR_PIN19_Clear << GPIO_OUTCLR_PIN19_Pos);
bogdanm 0:9b334a45a8ff 109
bogdanm 0:9b334a45a8ff 110 // Config External Crystal to 32MHz
bogdanm 0:9b334a45a8ff 111 NRF_CLOCK->XTALFREQ = 0x00;
bogdanm 0:9b334a45a8ff 112 NRF_CLOCK->EVENTS_HFCLKSTARTED = 0;
bogdanm 0:9b334a45a8ff 113 NRF_CLOCK->TASKS_HFCLKSTART = 1;
bogdanm 0:9b334a45a8ff 114 while (NRF_CLOCK->EVENTS_HFCLKSTARTED == 0)
bogdanm 0:9b334a45a8ff 115 {// Do nothing.
bogdanm 0:9b334a45a8ff 116 }
bogdanm 0:9b334a45a8ff 117
bogdanm 0:9b334a45a8ff 118 flash_init();
bogdanm 0:9b334a45a8ff 119
bogdanm 0:9b334a45a8ff 120 //nrf_delay_ms(10);
bogdanm 0:9b334a45a8ff 121 flash_powerDown();
bogdanm 0:9b334a45a8ff 122
bogdanm 0:9b334a45a8ff 123 }