Zeroday Hong / mbed-dev

Important changes to repositories hosted on mbed.com

Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.

To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.

It is also possible to export all your personal repositories from the account settings page.

Fork of mbed-dev by mbed official

targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/rspi_iodefine.h@162:16168a1438f3, 2017-04-08 (annotated)

Committer:
funshine
Date:
Sat Apr 08 17:03:55 2017 +0000
Revision:
162:16168a1438f3
Parent:
149:156823d33999 
add code to handle serial port rx error in uart_irq()

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*******************************************************************************
<> 144:ef7eb2e8f9f7 2 * DISCLAIMER
<> 144:ef7eb2e8f9f7 3 * This software is supplied by Renesas Electronics Corporation and is only
<> 144:ef7eb2e8f9f7 4 * intended for use with Renesas products. No other uses are authorized. This
<> 144:ef7eb2e8f9f7 5 * software is owned by Renesas Electronics Corporation and is protected under
<> 144:ef7eb2e8f9f7 6 * all applicable laws, including copyright laws.
<> 144:ef7eb2e8f9f7 7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
<> 144:ef7eb2e8f9f7 8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
<> 144:ef7eb2e8f9f7 9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
<> 144:ef7eb2e8f9f7 10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
<> 144:ef7eb2e8f9f7 11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
<> 144:ef7eb2e8f9f7 12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
<> 144:ef7eb2e8f9f7 13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
<> 144:ef7eb2e8f9f7 14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
<> 144:ef7eb2e8f9f7 15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
<> 144:ef7eb2e8f9f7 16 * Renesas reserves the right, without notice, to make changes to this software
<> 144:ef7eb2e8f9f7 17 * and to discontinue the availability of this software. By using this software,
<> 144:ef7eb2e8f9f7 18 * you agree to the additional terms and conditions found by accessing the
<> 144:ef7eb2e8f9f7 19 * following link:
<> 144:ef7eb2e8f9f7 20 * http://www.renesas.com/disclaimer*
<> 144:ef7eb2e8f9f7 21 * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
<> 144:ef7eb2e8f9f7 22 *******************************************************************************/
<> 144:ef7eb2e8f9f7 23 /*******************************************************************************
<> 144:ef7eb2e8f9f7 24 * File Name : rspi_iodefine.h
<> 144:ef7eb2e8f9f7 25 * $Rev: $
<> 144:ef7eb2e8f9f7 26 * $Date:: $
<> 144:ef7eb2e8f9f7 27 * Description : Definition of I/O Register (V1.00a)
<> 144:ef7eb2e8f9f7 28 ******************************************************************************/
<> 144:ef7eb2e8f9f7 29 #ifndef RSPI_IODEFINE_H
<> 144:ef7eb2e8f9f7 30 #define RSPI_IODEFINE_H
<> 144:ef7eb2e8f9f7 31 /* ->SEC M1.10.1 : Not magic number */
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 #include "reg32_t.h"
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35 struct st_rspi
<> 144:ef7eb2e8f9f7 36 { /* RSPI */
<> 144:ef7eb2e8f9f7 37 volatile uint8_t SPCR; /* SPCR */
<> 144:ef7eb2e8f9f7 38 volatile uint8_t SSLP; /* SSLP */
<> 144:ef7eb2e8f9f7 39 volatile uint8_t SPPCR; /* SPPCR */
<> 144:ef7eb2e8f9f7 40 volatile uint8_t SPSR; /* SPSR */
<> 144:ef7eb2e8f9f7 41 union reg32_t SPDR; /* SPDR */
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 volatile uint8_t SPSCR; /* SPSCR */
<> 144:ef7eb2e8f9f7 44 volatile uint8_t SPSSR; /* SPSSR */
<> 144:ef7eb2e8f9f7 45 volatile uint8_t SPBR; /* SPBR */
<> 144:ef7eb2e8f9f7 46 volatile uint8_t SPDCR; /* SPDCR */
<> 144:ef7eb2e8f9f7 47 volatile uint8_t SPCKD; /* SPCKD */
<> 144:ef7eb2e8f9f7 48 volatile uint8_t SSLND; /* SSLND */
<> 144:ef7eb2e8f9f7 49 volatile uint8_t SPND; /* SPND */
<> 144:ef7eb2e8f9f7 50 volatile uint8_t dummy1[1]; /* */
<> 144:ef7eb2e8f9f7 51 #define SPCMD_COUNT 4
<> 144:ef7eb2e8f9f7 52 volatile uint16_t SPCMD0; /* SPCMD0 */
<> 144:ef7eb2e8f9f7 53 volatile uint16_t SPCMD1; /* SPCMD1 */
<> 144:ef7eb2e8f9f7 54 volatile uint16_t SPCMD2; /* SPCMD2 */
<> 144:ef7eb2e8f9f7 55 volatile uint16_t SPCMD3; /* SPCMD3 */
<> 144:ef7eb2e8f9f7 56 volatile uint8_t dummy2[8]; /* */
<> 144:ef7eb2e8f9f7 57 volatile uint8_t SPBFCR; /* SPBFCR */
<> 144:ef7eb2e8f9f7 58 volatile uint8_t dummy3[1]; /* */
<> 144:ef7eb2e8f9f7 59 volatile uint16_t SPBFDR; /* SPBFDR */
<> 144:ef7eb2e8f9f7 60 };
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 #define RSPI0 (*(struct st_rspi *)0xE800C800uL) /* RSPI0 */
<> 144:ef7eb2e8f9f7 64 #define RSPI1 (*(struct st_rspi *)0xE800D000uL) /* RSPI1 */
<> 144:ef7eb2e8f9f7 65 #define RSPI2 (*(struct st_rspi *)0xE800D800uL) /* RSPI2 */
<> 144:ef7eb2e8f9f7 66 #define RSPI3 (*(struct st_rspi *)0xE800E000uL) /* RSPI3 */
<> 144:ef7eb2e8f9f7 67 #define RSPI4 (*(struct st_rspi *)0xE800E800uL) /* RSPI4 */
<> 144:ef7eb2e8f9f7 68
<> 144:ef7eb2e8f9f7 69
<> 144:ef7eb2e8f9f7 70 /* Start of channnel array defines of RSPI */
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72 /* Channnel array defines of RSPI */
<> 144:ef7eb2e8f9f7 73 /*(Sample) value = RSPI[ channel ]->SPCR; */
<> 144:ef7eb2e8f9f7 74 #define RSPI_COUNT 5
<> 144:ef7eb2e8f9f7 75 #define RSPI_ADDRESS_LIST \
<> 144:ef7eb2e8f9f7 76 { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
<> 144:ef7eb2e8f9f7 77 &RSPI0, &RSPI1, &RSPI2, &RSPI3, &RSPI4 \
<> 144:ef7eb2e8f9f7 78 } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80 /* End of channnel array defines of RSPI */
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 #define SPCR_0 RSPI0.SPCR
<> 144:ef7eb2e8f9f7 84 #define SSLP_0 RSPI0.SSLP
<> 144:ef7eb2e8f9f7 85 #define SPPCR_0 RSPI0.SPPCR
<> 144:ef7eb2e8f9f7 86 #define SPSR_0 RSPI0.SPSR
<> 144:ef7eb2e8f9f7 87 #define SPDR_0 RSPI0.SPDR.UINT32
<> 144:ef7eb2e8f9f7 88 #define SPDR_0L RSPI0.SPDR.UINT16[L]
<> 144:ef7eb2e8f9f7 89 #define SPDR_0H RSPI0.SPDR.UINT16[H]
<> 144:ef7eb2e8f9f7 90 #define SPDR_0LL RSPI0.SPDR.UINT8[LL]
<> 144:ef7eb2e8f9f7 91 #define SPDR_0LH RSPI0.SPDR.UINT8[LH]
<> 144:ef7eb2e8f9f7 92 #define SPDR_0HL RSPI0.SPDR.UINT8[HL]
<> 144:ef7eb2e8f9f7 93 #define SPDR_0HH RSPI0.SPDR.UINT8[HH]
<> 144:ef7eb2e8f9f7 94 #define SPSCR_0 RSPI0.SPSCR
<> 144:ef7eb2e8f9f7 95 #define SPSSR_0 RSPI0.SPSSR
<> 144:ef7eb2e8f9f7 96 #define SPBR_0 RSPI0.SPBR
<> 144:ef7eb2e8f9f7 97 #define SPDCR_0 RSPI0.SPDCR
<> 144:ef7eb2e8f9f7 98 #define SPCKD_0 RSPI0.SPCKD
<> 144:ef7eb2e8f9f7 99 #define SSLND_0 RSPI0.SSLND
<> 144:ef7eb2e8f9f7 100 #define SPND_0 RSPI0.SPND
<> 144:ef7eb2e8f9f7 101 #define SPCMD0_0 RSPI0.SPCMD0
<> 144:ef7eb2e8f9f7 102 #define SPCMD1_0 RSPI0.SPCMD1
<> 144:ef7eb2e8f9f7 103 #define SPCMD2_0 RSPI0.SPCMD2
<> 144:ef7eb2e8f9f7 104 #define SPCMD3_0 RSPI0.SPCMD3
<> 144:ef7eb2e8f9f7 105 #define SPBFCR_0 RSPI0.SPBFCR
<> 144:ef7eb2e8f9f7 106 #define SPBFDR_0 RSPI0.SPBFDR
<> 144:ef7eb2e8f9f7 107 #define SPCR_1 RSPI1.SPCR
<> 144:ef7eb2e8f9f7 108 #define SSLP_1 RSPI1.SSLP
<> 144:ef7eb2e8f9f7 109 #define SPPCR_1 RSPI1.SPPCR
<> 144:ef7eb2e8f9f7 110 #define SPSR_1 RSPI1.SPSR
<> 144:ef7eb2e8f9f7 111 #define SPDR_1 RSPI1.SPDR.UINT32
<> 144:ef7eb2e8f9f7 112 #define SPDR_1L RSPI1.SPDR.UINT16[L]
<> 144:ef7eb2e8f9f7 113 #define SPDR_1H RSPI1.SPDR.UINT16[H]
<> 144:ef7eb2e8f9f7 114 #define SPDR_1LL RSPI1.SPDR.UINT8[LL]
<> 144:ef7eb2e8f9f7 115 #define SPDR_1LH RSPI1.SPDR.UINT8[LH]
<> 144:ef7eb2e8f9f7 116 #define SPDR_1HL RSPI1.SPDR.UINT8[HL]
<> 144:ef7eb2e8f9f7 117 #define SPDR_1HH RSPI1.SPDR.UINT8[HH]
<> 144:ef7eb2e8f9f7 118 #define SPSCR_1 RSPI1.SPSCR
<> 144:ef7eb2e8f9f7 119 #define SPSSR_1 RSPI1.SPSSR
<> 144:ef7eb2e8f9f7 120 #define SPBR_1 RSPI1.SPBR
<> 144:ef7eb2e8f9f7 121 #define SPDCR_1 RSPI1.SPDCR
<> 144:ef7eb2e8f9f7 122 #define SPCKD_1 RSPI1.SPCKD
<> 144:ef7eb2e8f9f7 123 #define SSLND_1 RSPI1.SSLND
<> 144:ef7eb2e8f9f7 124 #define SPND_1 RSPI1.SPND
<> 144:ef7eb2e8f9f7 125 #define SPCMD0_1 RSPI1.SPCMD0
<> 144:ef7eb2e8f9f7 126 #define SPCMD1_1 RSPI1.SPCMD1
<> 144:ef7eb2e8f9f7 127 #define SPCMD2_1 RSPI1.SPCMD2
<> 144:ef7eb2e8f9f7 128 #define SPCMD3_1 RSPI1.SPCMD3
<> 144:ef7eb2e8f9f7 129 #define SPBFCR_1 RSPI1.SPBFCR
<> 144:ef7eb2e8f9f7 130 #define SPBFDR_1 RSPI1.SPBFDR
<> 144:ef7eb2e8f9f7 131 #define SPCR_2 RSPI2.SPCR
<> 144:ef7eb2e8f9f7 132 #define SSLP_2 RSPI2.SSLP
<> 144:ef7eb2e8f9f7 133 #define SPPCR_2 RSPI2.SPPCR
<> 144:ef7eb2e8f9f7 134 #define SPSR_2 RSPI2.SPSR
<> 144:ef7eb2e8f9f7 135 #define SPDR_2 RSPI2.SPDR.UINT32
<> 144:ef7eb2e8f9f7 136 #define SPDR_2L RSPI2.SPDR.UINT16[L]
<> 144:ef7eb2e8f9f7 137 #define SPDR_2H RSPI2.SPDR.UINT16[H]
<> 144:ef7eb2e8f9f7 138 #define SPDR_2LL RSPI2.SPDR.UINT8[LL]
<> 144:ef7eb2e8f9f7 139 #define SPDR_2LH RSPI2.SPDR.UINT8[LH]
<> 144:ef7eb2e8f9f7 140 #define SPDR_2HL RSPI2.SPDR.UINT8[HL]
<> 144:ef7eb2e8f9f7 141 #define SPDR_2HH RSPI2.SPDR.UINT8[HH]
<> 144:ef7eb2e8f9f7 142 #define SPSCR_2 RSPI2.SPSCR
<> 144:ef7eb2e8f9f7 143 #define SPSSR_2 RSPI2.SPSSR
<> 144:ef7eb2e8f9f7 144 #define SPBR_2 RSPI2.SPBR
<> 144:ef7eb2e8f9f7 145 #define SPDCR_2 RSPI2.SPDCR
<> 144:ef7eb2e8f9f7 146 #define SPCKD_2 RSPI2.SPCKD
<> 144:ef7eb2e8f9f7 147 #define SSLND_2 RSPI2.SSLND
<> 144:ef7eb2e8f9f7 148 #define SPND_2 RSPI2.SPND
<> 144:ef7eb2e8f9f7 149 #define SPCMD0_2 RSPI2.SPCMD0
<> 144:ef7eb2e8f9f7 150 #define SPCMD1_2 RSPI2.SPCMD1
<> 144:ef7eb2e8f9f7 151 #define SPCMD2_2 RSPI2.SPCMD2
<> 144:ef7eb2e8f9f7 152 #define SPCMD3_2 RSPI2.SPCMD3
<> 144:ef7eb2e8f9f7 153 #define SPBFCR_2 RSPI2.SPBFCR
<> 144:ef7eb2e8f9f7 154 #define SPBFDR_2 RSPI2.SPBFDR
<> 144:ef7eb2e8f9f7 155 #define SPCR_3 RSPI3.SPCR
<> 144:ef7eb2e8f9f7 156 #define SSLP_3 RSPI3.SSLP
<> 144:ef7eb2e8f9f7 157 #define SPPCR_3 RSPI3.SPPCR
<> 144:ef7eb2e8f9f7 158 #define SPSR_3 RSPI3.SPSR
<> 144:ef7eb2e8f9f7 159 #define SPDR_3 RSPI3.SPDR.UINT32
<> 144:ef7eb2e8f9f7 160 #define SPDR_3L RSPI3.SPDR.UINT16[L]
<> 144:ef7eb2e8f9f7 161 #define SPDR_3H RSPI3.SPDR.UINT16[H]
<> 144:ef7eb2e8f9f7 162 #define SPDR_3LL RSPI3.SPDR.UINT8[LL]
<> 144:ef7eb2e8f9f7 163 #define SPDR_3LH RSPI3.SPDR.UINT8[LH]
<> 144:ef7eb2e8f9f7 164 #define SPDR_3HL RSPI3.SPDR.UINT8[HL]
<> 144:ef7eb2e8f9f7 165 #define SPDR_3HH RSPI3.SPDR.UINT8[HH]
<> 144:ef7eb2e8f9f7 166 #define SPSCR_3 RSPI3.SPSCR
<> 144:ef7eb2e8f9f7 167 #define SPSSR_3 RSPI3.SPSSR
<> 144:ef7eb2e8f9f7 168 #define SPBR_3 RSPI3.SPBR
<> 144:ef7eb2e8f9f7 169 #define SPDCR_3 RSPI3.SPDCR
<> 144:ef7eb2e8f9f7 170 #define SPCKD_3 RSPI3.SPCKD
<> 144:ef7eb2e8f9f7 171 #define SSLND_3 RSPI3.SSLND
<> 144:ef7eb2e8f9f7 172 #define SPND_3 RSPI3.SPND
<> 144:ef7eb2e8f9f7 173 #define SPCMD0_3 RSPI3.SPCMD0
<> 144:ef7eb2e8f9f7 174 #define SPCMD1_3 RSPI3.SPCMD1
<> 144:ef7eb2e8f9f7 175 #define SPCMD2_3 RSPI3.SPCMD2
<> 144:ef7eb2e8f9f7 176 #define SPCMD3_3 RSPI3.SPCMD3
<> 144:ef7eb2e8f9f7 177 #define SPBFCR_3 RSPI3.SPBFCR
<> 144:ef7eb2e8f9f7 178 #define SPBFDR_3 RSPI3.SPBFDR
<> 144:ef7eb2e8f9f7 179 #define SPCR_4 RSPI4.SPCR
<> 144:ef7eb2e8f9f7 180 #define SSLP_4 RSPI4.SSLP
<> 144:ef7eb2e8f9f7 181 #define SPPCR_4 RSPI4.SPPCR
<> 144:ef7eb2e8f9f7 182 #define SPSR_4 RSPI4.SPSR
<> 144:ef7eb2e8f9f7 183 #define SPDR_4 RSPI4.SPDR.UINT32
<> 144:ef7eb2e8f9f7 184 #define SPDR_4L RSPI4.SPDR.UINT16[L]
<> 144:ef7eb2e8f9f7 185 #define SPDR_4H RSPI4.SPDR.UINT16[H]
<> 144:ef7eb2e8f9f7 186 #define SPDR_4LL RSPI4.SPDR.UINT8[LL]
<> 144:ef7eb2e8f9f7 187 #define SPDR_4LH RSPI4.SPDR.UINT8[LH]
<> 144:ef7eb2e8f9f7 188 #define SPDR_4HL RSPI4.SPDR.UINT8[HL]
<> 144:ef7eb2e8f9f7 189 #define SPDR_4HH RSPI4.SPDR.UINT8[HH]
<> 144:ef7eb2e8f9f7 190 #define SPSCR_4 RSPI4.SPSCR
<> 144:ef7eb2e8f9f7 191 #define SPSSR_4 RSPI4.SPSSR
<> 144:ef7eb2e8f9f7 192 #define SPBR_4 RSPI4.SPBR
<> 144:ef7eb2e8f9f7 193 #define SPDCR_4 RSPI4.SPDCR
<> 144:ef7eb2e8f9f7 194 #define SPCKD_4 RSPI4.SPCKD
<> 144:ef7eb2e8f9f7 195 #define SSLND_4 RSPI4.SSLND
<> 144:ef7eb2e8f9f7 196 #define SPND_4 RSPI4.SPND
<> 144:ef7eb2e8f9f7 197 #define SPCMD0_4 RSPI4.SPCMD0
<> 144:ef7eb2e8f9f7 198 #define SPCMD1_4 RSPI4.SPCMD1
<> 144:ef7eb2e8f9f7 199 #define SPCMD2_4 RSPI4.SPCMD2
<> 144:ef7eb2e8f9f7 200 #define SPCMD3_4 RSPI4.SPCMD3
<> 144:ef7eb2e8f9f7 201 #define SPBFCR_4 RSPI4.SPBFCR
<> 144:ef7eb2e8f9f7 202 #define SPBFDR_4 RSPI4.SPBFDR
<> 144:ef7eb2e8f9f7 203 /* <-SEC M1.10.1 */
<> 144:ef7eb2e8f9f7 204 #endif