Zeroday Hong / mbed-dev

Important changes to repositories hosted on mbed.com

Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.

To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.

It is also possible to export all your personal repositories from the account settings page.

Fork of mbed-dev by mbed official

targets/TARGET_RENESAS/TARGET_RZ_A1H/device/TOOLCHAIN_GCC_ARM/startup_RZ1AH.S@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Parent:
targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/TOOLCHAIN_GCC_ARM/startup_RZ1AH.S@144:ef7eb2e8f9f7 
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* File: startup_ARMCM3.s
<> 144:ef7eb2e8f9f7 2 * Purpose: startup file for Cortex-M3/M4 devices. Should use with
<> 144:ef7eb2e8f9f7 3 * GNU Tools for ARM Embedded Processors
<> 144:ef7eb2e8f9f7 4 * Version: V1.1
<> 144:ef7eb2e8f9f7 5 * Date: 17 June 2011
<> 144:ef7eb2e8f9f7 6 *
<> 144:ef7eb2e8f9f7 7 * Copyright (C) 2011 ARM Limited. All rights reserved.
<> 144:ef7eb2e8f9f7 8 * ARM Limited (ARM) is supplying this software for use with Cortex-M3/M4
<> 144:ef7eb2e8f9f7 9 * processor based microcontrollers. This file can be freely distributed
<> 144:ef7eb2e8f9f7 10 * within development tools that are supporting such ARM based processors.
<> 144:ef7eb2e8f9f7 11 *
<> 144:ef7eb2e8f9f7 12 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
<> 144:ef7eb2e8f9f7 13 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
<> 144:ef7eb2e8f9f7 14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
<> 144:ef7eb2e8f9f7 15 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
<> 144:ef7eb2e8f9f7 16 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
<> 144:ef7eb2e8f9f7 17 */
<> 144:ef7eb2e8f9f7 18 .syntax unified
<> 144:ef7eb2e8f9f7 19 .extern _start
<> 144:ef7eb2e8f9f7 20
<> 144:ef7eb2e8f9f7 21 @ Standard definitions of mode bits and interrupt (I & F) flags in PSRs
<> 144:ef7eb2e8f9f7 22 .equ USR_MODE , 0x10
<> 144:ef7eb2e8f9f7 23 .equ FIQ_MODE , 0x11
<> 144:ef7eb2e8f9f7 24 .equ IRQ_MODE , 0x12
<> 144:ef7eb2e8f9f7 25 .equ SVC_MODE , 0x13
<> 144:ef7eb2e8f9f7 26 .equ ABT_MODE , 0x17
<> 144:ef7eb2e8f9f7 27 .equ UND_MODE , 0x1b
<> 144:ef7eb2e8f9f7 28 .equ SYS_MODE , 0x1f
<> 144:ef7eb2e8f9f7 29 .equ Thum_bit , 0x20 @ CPSR/SPSR Thumb bit
<> 144:ef7eb2e8f9f7 30
<> 144:ef7eb2e8f9f7 31 .equ GICI_BASE , 0xe8202000
<> 144:ef7eb2e8f9f7 32 .equ ICCIAR_OFFSET , 0x0000000C
<> 144:ef7eb2e8f9f7 33 .equ ICCEOIR_OFFSET , 0x00000010
<> 144:ef7eb2e8f9f7 34 .equ ICCHPIR_OFFSET , 0x00000018
<> 144:ef7eb2e8f9f7 35 .equ GICD_BASE , 0xe8201000
<> 144:ef7eb2e8f9f7 36 .equ ICDISER0_OFFSET , 0x00000100
<> 144:ef7eb2e8f9f7 37 .equ ICDICER0_OFFSET , 0x00000180
<> 144:ef7eb2e8f9f7 38 .equ ICDISPR0_OFFSET , 0x00000200
<> 144:ef7eb2e8f9f7 39 .equ ICDABR0_OFFSET , 0x00000300
<> 144:ef7eb2e8f9f7 40 .equ ICDIPR0_OFFSET , 0x00000400
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 .equ Mode_USR , 0x10
<> 144:ef7eb2e8f9f7 43 .equ Mode_FIQ , 0x11
<> 144:ef7eb2e8f9f7 44 .equ Mode_IRQ , 0x12
<> 144:ef7eb2e8f9f7 45 .equ Mode_SVC , 0x13
<> 144:ef7eb2e8f9f7 46 .equ Mode_ABT , 0x17
<> 144:ef7eb2e8f9f7 47 .equ Mode_UND , 0x1B
<> 144:ef7eb2e8f9f7 48 .equ Mode_SYS , 0x1F
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 .equ I_Bit , 0x80 @ when I bit is set, IRQ is disabled
<> 144:ef7eb2e8f9f7 51 .equ F_Bit , 0x40 @ when F bit is set, FIQ is disabled
<> 144:ef7eb2e8f9f7 52 .equ T_Bit , 0x20 @ when T bit is set, core is in Thumb state
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54 .equ GIC_ERRATA_CHECK_1, 0x000003FE
<> 144:ef7eb2e8f9f7 55 .equ GIC_ERRATA_CHECK_2, 0x000003FF
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 .equ Sect_Normal , 0x00005c06 @ outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0
<> 144:ef7eb2e8f9f7 58 .equ Sect_Normal_Cod , 0x0000dc06 @ outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0
<> 144:ef7eb2e8f9f7 59 .equ Sect_Normal_RO , 0x0000dc16 @ as Sect_Normal_Cod, but not executable
<> 144:ef7eb2e8f9f7 60 .equ Sect_Normal_RW , 0x00005c16 @ as Sect_Normal_Cod, but writeable and not executable
<> 144:ef7eb2e8f9f7 61 .equ Sect_SO , 0x00000c12 @ strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0
<> 144:ef7eb2e8f9f7 62 .equ Sect_Device_RO , 0x00008c12 @ device, non-shareable, non-executable, ro, domain 0, base addr 0
<> 144:ef7eb2e8f9f7 63 .equ Sect_Device_RW , 0x00000c12 @ as Sect_Device_RO, but writeable
<> 144:ef7eb2e8f9f7 64 .equ Sect_Fault , 0x00000000 @ this translation will fault (the bottom 2 bits are important, the rest are ignored)
<> 144:ef7eb2e8f9f7 65
<> 144:ef7eb2e8f9f7 66 .equ RAM_BASE , 0x80000000
<> 144:ef7eb2e8f9f7 67 .equ VRAM_BASE , 0x18000000
<> 144:ef7eb2e8f9f7 68 .equ SRAM_BASE , 0x2e000000
<> 144:ef7eb2e8f9f7 69 .equ ETHERNET , 0x1a000000
<> 144:ef7eb2e8f9f7 70 .equ CS3_PERIPHERAL_BASE, 0x1c000000
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 @ Stack Configuration
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 .EQU UND_Stack_Size , 0x00000100
<> 144:ef7eb2e8f9f7 76 .EQU SVC_Stack_Size , 0x00008000
<> 144:ef7eb2e8f9f7 77 .EQU ABT_Stack_Size , 0x00000100
<> 144:ef7eb2e8f9f7 78 .EQU FIQ_Stack_Size , 0x00000100
<> 144:ef7eb2e8f9f7 79 .EQU IRQ_Stack_Size , 0x00008000
<> 144:ef7eb2e8f9f7 80 .EQU USR_Stack_Size , 0x00004000
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82 .EQU ISR_Stack_Size, (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + FIQ_Stack_Size + IRQ_Stack_Size)
<> 144:ef7eb2e8f9f7 83
<> 144:ef7eb2e8f9f7 84 .section .stack
<> 144:ef7eb2e8f9f7 85 .align 3
<> 144:ef7eb2e8f9f7 86 .globl __StackTop
<> 144:ef7eb2e8f9f7 87 .globl __StackLimit
<> 144:ef7eb2e8f9f7 88 __StackLimit:
<> 144:ef7eb2e8f9f7 89 .space ISR_Stack_Size
<> 144:ef7eb2e8f9f7 90 __initial_sp:
<> 144:ef7eb2e8f9f7 91 .space USR_Stack_Size
<> 144:ef7eb2e8f9f7 92 .size __StackLimit, . - __StackLimit
<> 144:ef7eb2e8f9f7 93 __StackTop:
<> 144:ef7eb2e8f9f7 94 .size __StackTop, . - __StackTop
<> 144:ef7eb2e8f9f7 95
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 @ Heap Configuration
<> 144:ef7eb2e8f9f7 98
<> 144:ef7eb2e8f9f7 99 .EQU Heap_Size , 0x00080000
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 .section .heap
<> 144:ef7eb2e8f9f7 102 .align 3
<> 144:ef7eb2e8f9f7 103 .globl __HeapBase
<> 144:ef7eb2e8f9f7 104 .globl __HeapLimit
<> 144:ef7eb2e8f9f7 105 __HeapBase:
<> 144:ef7eb2e8f9f7 106 .space Heap_Size
<> 144:ef7eb2e8f9f7 107 .size __HeapBase, . - __HeapBase
<> 144:ef7eb2e8f9f7 108 __HeapLimit:
<> 144:ef7eb2e8f9f7 109 .size __HeapLimit, . - __HeapLimit
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111
<> 144:ef7eb2e8f9f7 112 .section .isr_vector
<> 144:ef7eb2e8f9f7 113 .align 2
<> 144:ef7eb2e8f9f7 114 .globl __isr_vector
<> 144:ef7eb2e8f9f7 115 __isr_vector:
<> 144:ef7eb2e8f9f7 116 .long 0xe59ff018 /* 0x00 */
<> 144:ef7eb2e8f9f7 117 .long 0xe59ff018 /* 0x04 */
<> 144:ef7eb2e8f9f7 118 .long 0xe59ff018 /* 0x08 */
<> 144:ef7eb2e8f9f7 119 .long 0xe59ff018 /* 0x0c */
<> 144:ef7eb2e8f9f7 120 .long 0xe59ff018 /* 0x10 */
<> 144:ef7eb2e8f9f7 121 .long 0xe59ff018 /* 0x14 */
<> 144:ef7eb2e8f9f7 122 .long 0xe59ff018 /* 0x18 */
<> 144:ef7eb2e8f9f7 123 .long 0xe59ff018 /* 0x1c */
<> 144:ef7eb2e8f9f7 124
<> 144:ef7eb2e8f9f7 125 .long Reset_Handler /* 0x20 */
<> 144:ef7eb2e8f9f7 126 .long Undef_Handler /* 0x24 */
<> 144:ef7eb2e8f9f7 127 .long SVC_Handler /* 0x28 */
<> 144:ef7eb2e8f9f7 128 .long PAbt_Handler /* 0x2c */
<> 144:ef7eb2e8f9f7 129 .long DAbt_Handler /* 0x30 */
<> 144:ef7eb2e8f9f7 130 .long 0 /* Reserved */
<> 144:ef7eb2e8f9f7 131 .long IRQ_Handler /* IRQ */
<> 144:ef7eb2e8f9f7 132 .long FIQ_Handler /* FIQ */
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135 .size __isr_vector, . - __isr_vector
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 .text
<> 144:ef7eb2e8f9f7 138 .align 2
<> 144:ef7eb2e8f9f7 139 .globl Reset_Handler
<> 144:ef7eb2e8f9f7 140 .type Reset_Handler, %function
<> 144:ef7eb2e8f9f7 141 Reset_Handler:
<> 144:ef7eb2e8f9f7 142 @ Put any cores other than 0 to sleep
<> 144:ef7eb2e8f9f7 143 mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR
<> 144:ef7eb2e8f9f7 144 ands r0, r0, #3
<> 144:ef7eb2e8f9f7 145
<> 144:ef7eb2e8f9f7 146 goToSleep:
<> 144:ef7eb2e8f9f7 147 wfine
<> 144:ef7eb2e8f9f7 148 bne goToSleep
<> 144:ef7eb2e8f9f7 149
<> 144:ef7eb2e8f9f7 150 @ Enable access to NEON/VFP by enabling access to Coprocessors 10 and 11.
<> 144:ef7eb2e8f9f7 151 @ Enables Full Access i.e. in both privileged and non privileged modes
<> 144:ef7eb2e8f9f7 152 mrc p15, 0, r0, c1, c0, 2 @ Read Coprocessor Access Control Register (CPACR)
<> 144:ef7eb2e8f9f7 153 orr r0, r0, #(0xF << 20) @ Enable access to CP 10 & 11
<> 144:ef7eb2e8f9f7 154 mcr p15, 0, r0, c1, c0, 2 @ Write Coprocessor Access Control Register (CPACR)
<> 144:ef7eb2e8f9f7 155 isb
<> 144:ef7eb2e8f9f7 156
<> 144:ef7eb2e8f9f7 157 @ Switch on the VFP and NEON hardware
<> 144:ef7eb2e8f9f7 158 mov r0, #0x40000000
<> 144:ef7eb2e8f9f7 159 vmsr fpexc, r0 @ Write FPEXC register, EN bit set
<> 144:ef7eb2e8f9f7 160
<> 144:ef7eb2e8f9f7 161 mrc p15, 0, r0, c1, c0, 0 @ Read CP15 System Control register
<> 144:ef7eb2e8f9f7 162 bic r0, r0, #(0x1 << 12) @ Clear I bit 12 to disable I Cache
<> 144:ef7eb2e8f9f7 163 bic r0, r0, #(0x1 << 2) @ Clear C bit 2 to disable D Cache
<> 144:ef7eb2e8f9f7 164 bic r0, r0, #0x1 @ Clear M bit 0 to disable MMU
<> 144:ef7eb2e8f9f7 165 bic r0, r0, #(0x1 << 11) @ Clear Z bit 11 to disable branch prediction
<> 144:ef7eb2e8f9f7 166 bic r0, r0, #(0x1 << 13) @ Clear V bit 13 to disable hivecs
<> 144:ef7eb2e8f9f7 167 mcr p15, 0, r0, c1, c0, 0 @ Write value back to CP15 System Control register
<> 144:ef7eb2e8f9f7 168 isb
<> 144:ef7eb2e8f9f7 169
<> 144:ef7eb2e8f9f7 170 @ Set Vector Base Address Register (VBAR) to point to this application's vector table
<> 144:ef7eb2e8f9f7 171 ldr r0, =__isr_vector
<> 144:ef7eb2e8f9f7 172 mcr p15, 0, r0, c12, c0, 0
<> 144:ef7eb2e8f9f7 173
<> 144:ef7eb2e8f9f7 174 @ Setup Stack for each exceptional mode
<> 144:ef7eb2e8f9f7 175 /* ldr r0, =__StackTop */
<> 144:ef7eb2e8f9f7 176 ldr r0, =(__StackTop - USR_Stack_Size)
<> 144:ef7eb2e8f9f7 177
<> 144:ef7eb2e8f9f7 178 @ Enter Undefined Instruction Mode and set its Stack Pointer
<> 144:ef7eb2e8f9f7 179 msr cpsr_c, #(Mode_UND | I_Bit | F_Bit)
<> 144:ef7eb2e8f9f7 180 mov sp, r0
<> 144:ef7eb2e8f9f7 181 sub r0, r0, #UND_Stack_Size
<> 144:ef7eb2e8f9f7 182
<> 144:ef7eb2e8f9f7 183 @ Enter Abort Mode and set its Stack Pointer
<> 144:ef7eb2e8f9f7 184 msr cpsr_c, #(Mode_ABT | I_Bit | F_Bit)
<> 144:ef7eb2e8f9f7 185 mov sp, r0
<> 144:ef7eb2e8f9f7 186 sub r0, r0, #ABT_Stack_Size
<> 144:ef7eb2e8f9f7 187
<> 144:ef7eb2e8f9f7 188 @ Enter FIQ Mode and set its Stack Pointer
<> 144:ef7eb2e8f9f7 189 msr cpsr_c, #(Mode_FIQ | I_Bit | F_Bit)
<> 144:ef7eb2e8f9f7 190 mov sp, r0
<> 144:ef7eb2e8f9f7 191 sub r0, r0, #FIQ_Stack_Size
<> 144:ef7eb2e8f9f7 192
<> 144:ef7eb2e8f9f7 193 @ Enter IRQ Mode and set its Stack Pointer
<> 144:ef7eb2e8f9f7 194 msr cpsr_c, #(Mode_IRQ | I_Bit | F_Bit)
<> 144:ef7eb2e8f9f7 195 mov sp, r0
<> 144:ef7eb2e8f9f7 196 sub r0, r0, #IRQ_Stack_Size
<> 144:ef7eb2e8f9f7 197
<> 144:ef7eb2e8f9f7 198 @ Enter Supervisor Mode and set its Stack Pointer
<> 144:ef7eb2e8f9f7 199 msr cpsr_c, #(Mode_SVC | I_Bit | F_Bit)
<> 144:ef7eb2e8f9f7 200 mov sp, r0
<> 144:ef7eb2e8f9f7 201
<> 144:ef7eb2e8f9f7 202 @ Enter System Mode to complete initialization and enter kernel
<> 144:ef7eb2e8f9f7 203 msr cpsr_c, #(Mode_SYS | I_Bit | F_Bit)
<> 144:ef7eb2e8f9f7 204 mov sp, r0
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206 isb
<> 144:ef7eb2e8f9f7 207 ldr r0, =RZ_A1_SetSramWriteEnable
<> 144:ef7eb2e8f9f7 208 blx r0
<> 144:ef7eb2e8f9f7 209
<> 144:ef7eb2e8f9f7 210 .extern create_translation_table
<> 144:ef7eb2e8f9f7 211 bl create_translation_table
<> 144:ef7eb2e8f9f7 212
<> 144:ef7eb2e8f9f7 213 @ USR/SYS stack pointer will be set during kernel init
<> 144:ef7eb2e8f9f7 214 ldr r0, =SystemInit
<> 144:ef7eb2e8f9f7 215 blx r0
<> 144:ef7eb2e8f9f7 216 ldr r0, =InitMemorySubsystem
<> 144:ef7eb2e8f9f7 217 blx r0
<> 144:ef7eb2e8f9f7 218
<> 144:ef7eb2e8f9f7 219 @ fp_init
<> 144:ef7eb2e8f9f7 220 mov r0, #0x3000000
<> 144:ef7eb2e8f9f7 221 vmsr fpscr, r0
<> 144:ef7eb2e8f9f7 222
<> 144:ef7eb2e8f9f7 223
<> 144:ef7eb2e8f9f7 224 @ data sections copy
<> 144:ef7eb2e8f9f7 225 ldr r4, =__copy_table_start__
<> 144:ef7eb2e8f9f7 226 ldr r5, =__copy_table_end__
<> 144:ef7eb2e8f9f7 227
<> 144:ef7eb2e8f9f7 228 .L_loop0:
<> 144:ef7eb2e8f9f7 229 cmp r4, r5
<> 144:ef7eb2e8f9f7 230 bge .L_loop0_done
<> 144:ef7eb2e8f9f7 231 ldr r1, [r4]
<> 144:ef7eb2e8f9f7 232 ldr r2, [r4, #4]
<> 144:ef7eb2e8f9f7 233 ldr r3, [r4, #8]
<> 144:ef7eb2e8f9f7 234
<> 144:ef7eb2e8f9f7 235 .L_loop0_0:
<> 144:ef7eb2e8f9f7 236 subs r3, #4
<> 144:ef7eb2e8f9f7 237 ittt ge
<> 144:ef7eb2e8f9f7 238 ldrge r0, [r1, r3]
<> 144:ef7eb2e8f9f7 239 strge r0, [r2, r3]
<> 144:ef7eb2e8f9f7 240 bge .L_loop0_0
<> 144:ef7eb2e8f9f7 241
<> 144:ef7eb2e8f9f7 242 adds r4, #12
<> 144:ef7eb2e8f9f7 243 b .L_loop0
<> 144:ef7eb2e8f9f7 244
<> 144:ef7eb2e8f9f7 245 .L_loop0_done:
<> 144:ef7eb2e8f9f7 246
<> 144:ef7eb2e8f9f7 247 @ bss sections clear
<> 144:ef7eb2e8f9f7 248 ldr r3, =__zero_table_start__
<> 144:ef7eb2e8f9f7 249 ldr r4, =__zero_table_end__
<> 144:ef7eb2e8f9f7 250
<> 144:ef7eb2e8f9f7 251 .L_loop2:
<> 144:ef7eb2e8f9f7 252 cmp r3, r4
<> 144:ef7eb2e8f9f7 253 bge .L_loop2_done
<> 144:ef7eb2e8f9f7 254 ldr r1, [r3]
<> 144:ef7eb2e8f9f7 255 ldr r2, [r3, #4]
<> 144:ef7eb2e8f9f7 256 movs r0, 0
<> 144:ef7eb2e8f9f7 257
<> 144:ef7eb2e8f9f7 258 .L_loop2_0:
<> 144:ef7eb2e8f9f7 259 subs r2, #4
<> 144:ef7eb2e8f9f7 260 itt ge
<> 144:ef7eb2e8f9f7 261 strge r0, [r1, r2]
<> 144:ef7eb2e8f9f7 262 bge .L_loop2_0
<> 144:ef7eb2e8f9f7 263
<> 144:ef7eb2e8f9f7 264 adds r3, #8
<> 144:ef7eb2e8f9f7 265 b .L_loop2
<> 144:ef7eb2e8f9f7 266 .L_loop2_done:
<> 144:ef7eb2e8f9f7 267
<> 144:ef7eb2e8f9f7 268
<> 144:ef7eb2e8f9f7 269 ldr r0, =_start
<> 144:ef7eb2e8f9f7 270 bx r0
<> 144:ef7eb2e8f9f7 271
<> 144:ef7eb2e8f9f7 272 ldr r0, sf_boot @ dummy to keep boot loader area
<> 144:ef7eb2e8f9f7 273 loop_here:
<> 144:ef7eb2e8f9f7 274 b loop_here
<> 144:ef7eb2e8f9f7 275
<> 144:ef7eb2e8f9f7 276 sf_boot:
<> 144:ef7eb2e8f9f7 277 .word boot_loader
<> 144:ef7eb2e8f9f7 278
<> 144:ef7eb2e8f9f7 279 .pool
<> 144:ef7eb2e8f9f7 280 .size Reset_Handler, . - Reset_Handler
<> 144:ef7eb2e8f9f7 281
<> 144:ef7eb2e8f9f7 282
<> 144:ef7eb2e8f9f7 283 .text
<> 144:ef7eb2e8f9f7 284
<> 144:ef7eb2e8f9f7 285 Undef_Handler:
<> 144:ef7eb2e8f9f7 286 .global Undef_Handler
<> 144:ef7eb2e8f9f7 287 .func Undef_Handler
<> 144:ef7eb2e8f9f7 288 .extern CUndefHandler
<> 144:ef7eb2e8f9f7 289 SRSDB SP!, #Mode_UND
<> 144:ef7eb2e8f9f7 290 PUSH {R0-R4, R12} /* Save APCS corruptible registers to UND mode stack */
<> 144:ef7eb2e8f9f7 291
<> 144:ef7eb2e8f9f7 292 MRS R0, SPSR
<> 144:ef7eb2e8f9f7 293 TST R0, #T_Bit /* Check mode */
<> 144:ef7eb2e8f9f7 294 MOVEQ R1, #4 /* R1 = 4 ARM mode */
<> 144:ef7eb2e8f9f7 295 MOVNE R1, #2 /* R1 = 2 Thumb mode */
<> 144:ef7eb2e8f9f7 296 SUB R0, LR, R1
<> 144:ef7eb2e8f9f7 297 LDREQ R0, [R0] /* ARM mode - R0 points to offending instruction */
<> 144:ef7eb2e8f9f7 298 BEQ undef_cont
<> 144:ef7eb2e8f9f7 299
<> 144:ef7eb2e8f9f7 300 /* Thumb instruction */
<> 144:ef7eb2e8f9f7 301 /* Determine if it is a 32-bit Thumb instruction */
<> 144:ef7eb2e8f9f7 302 LDRH R0, [R0]
<> 144:ef7eb2e8f9f7 303 MOV R2, #0x1c
<> 144:ef7eb2e8f9f7 304 CMP R2, R0, LSR #11
<> 144:ef7eb2e8f9f7 305 BHS undef_cont /* 16-bit Thumb instruction */
<> 144:ef7eb2e8f9f7 306
<> 144:ef7eb2e8f9f7 307 /* 32-bit Thumb instruction. Unaligned - we need to reconstruct the offending instruction. */
<> 144:ef7eb2e8f9f7 308 LDRH R2, [LR]
<> 144:ef7eb2e8f9f7 309 ORR R0, R2, R0, LSL #16
<> 144:ef7eb2e8f9f7 310 undef_cont:
<> 144:ef7eb2e8f9f7 311 MOV R2, LR /* Set LR to third argument */
<> 144:ef7eb2e8f9f7 312
<> 144:ef7eb2e8f9f7 313 /* AND R12, SP, #4 */ /* Ensure stack is 8-byte aligned */
<> 144:ef7eb2e8f9f7 314 MOV R3, SP /* Ensure stack is 8-byte aligned */
<> 144:ef7eb2e8f9f7 315 AND R12, R3, #4
<> 144:ef7eb2e8f9f7 316 SUB SP, SP, R12 /* Adjust stack */
<> 144:ef7eb2e8f9f7 317 PUSH {R12, LR} /* Store stack adjustment and dummy LR */
<> 144:ef7eb2e8f9f7 318
<> 144:ef7eb2e8f9f7 319 /* R0 Offending instruction */
<> 144:ef7eb2e8f9f7 320 /* R1 =2 (Thumb) or =4 (ARM) */
<> 144:ef7eb2e8f9f7 321 BL CUndefHandler
<> 144:ef7eb2e8f9f7 322
<> 144:ef7eb2e8f9f7 323 POP {R12, LR} /* Get stack adjustment & discard dummy LR */
<> 144:ef7eb2e8f9f7 324 ADD SP, SP, R12 /* Unadjust stack */
<> 144:ef7eb2e8f9f7 325
<> 144:ef7eb2e8f9f7 326 LDR LR, [SP, #24] /* Restore stacked LR and possibly adjust for retry */
<> 144:ef7eb2e8f9f7 327 SUB LR, LR, R0
<> 144:ef7eb2e8f9f7 328 LDR R0, [SP, #28] /* Restore stacked SPSR */
<> 144:ef7eb2e8f9f7 329 MSR SPSR_cxsf, R0
<> 144:ef7eb2e8f9f7 330 POP {R0-R4, R12} /* Restore stacked APCS registers */
<> 144:ef7eb2e8f9f7 331 ADD SP, SP, #8 /* Adjust SP for already-restored banked registers */
<> 144:ef7eb2e8f9f7 332 MOVS PC, LR
<> 144:ef7eb2e8f9f7 333 .endfunc
<> 144:ef7eb2e8f9f7 334
<> 144:ef7eb2e8f9f7 335 PAbt_Handler:
<> 144:ef7eb2e8f9f7 336 .global PAbt_Handler
<> 144:ef7eb2e8f9f7 337 .func PAbt_Handler
<> 144:ef7eb2e8f9f7 338 .extern CPAbtHandler
<> 144:ef7eb2e8f9f7 339 SUB LR, LR, #4 /* Pre-adjust LR */
<> 144:ef7eb2e8f9f7 340 SRSDB SP!, #Mode_ABT /* Save LR and SPRS to ABT mode stack */
<> 144:ef7eb2e8f9f7 341 PUSH {R0-R4, R12} /* Save APCS corruptible registers to ABT mode stack */
<> 144:ef7eb2e8f9f7 342 MRC p15, 0, R0, c5, c0, 1 /* IFSR */
<> 144:ef7eb2e8f9f7 343 MRC p15, 0, R1, c6, c0, 2 /* IFAR */
<> 144:ef7eb2e8f9f7 344
<> 144:ef7eb2e8f9f7 345 MOV R2, LR /* Set LR to third argument */
<> 144:ef7eb2e8f9f7 346
<> 144:ef7eb2e8f9f7 347 /* AND R12, SP, #4 */ /* Ensure stack is 8-byte aligned */
<> 144:ef7eb2e8f9f7 348 MOV R3, SP /* Ensure stack is 8-byte aligned */
<> 144:ef7eb2e8f9f7 349 AND R12, R3, #4
<> 144:ef7eb2e8f9f7 350 SUB SP, SP, R12 /* Adjust stack */
<> 144:ef7eb2e8f9f7 351 PUSH {R12, LR} /* Store stack adjustment and dummy LR */
<> 144:ef7eb2e8f9f7 352
<> 144:ef7eb2e8f9f7 353 BL CPAbtHandler
<> 144:ef7eb2e8f9f7 354
<> 144:ef7eb2e8f9f7 355 POP {R12, LR} /* Get stack adjustment & discard dummy LR */
<> 144:ef7eb2e8f9f7 356 ADD SP, SP, R12 /* Unadjust stack */
<> 144:ef7eb2e8f9f7 357
<> 144:ef7eb2e8f9f7 358 POP {R0-R4, R12} /* Restore stack APCS registers */
<> 144:ef7eb2e8f9f7 359 RFEFD SP! /* Return from exception */
<> 144:ef7eb2e8f9f7 360 .endfunc
<> 144:ef7eb2e8f9f7 361
<> 144:ef7eb2e8f9f7 362 DAbt_Handler:
<> 144:ef7eb2e8f9f7 363 .global DAbt_Handler
<> 144:ef7eb2e8f9f7 364 .func DAbt_Handler
<> 144:ef7eb2e8f9f7 365 .extern CDAbtHandler
<> 144:ef7eb2e8f9f7 366 SUB LR, LR, #8 /* Pre-adjust LR */
<> 144:ef7eb2e8f9f7 367 SRSDB SP!, #Mode_ABT /* Save LR and SPRS to ABT mode stack */
<> 144:ef7eb2e8f9f7 368 PUSH {R0-R4, R12} /* Save APCS corruptible registers to ABT mode stack */
<> 144:ef7eb2e8f9f7 369 CLREX /* State of exclusive monitors unknown after taken data abort */
<> 144:ef7eb2e8f9f7 370 MRC p15, 0, R0, c5, c0, 0 /* DFSR */
<> 144:ef7eb2e8f9f7 371 MRC p15, 0, R1, c6, c0, 0 /* DFAR */
<> 144:ef7eb2e8f9f7 372
<> 144:ef7eb2e8f9f7 373 MOV R2, LR /* Set LR to third argument */
<> 144:ef7eb2e8f9f7 374
<> 144:ef7eb2e8f9f7 375 /* AND R12, SP, #4 */ /* Ensure stack is 8-byte aligned */
<> 144:ef7eb2e8f9f7 376 MOV R3, SP /* Ensure stack is 8-byte aligned */
<> 144:ef7eb2e8f9f7 377 AND R12, R3, #4
<> 144:ef7eb2e8f9f7 378 SUB SP, SP, R12 /* Adjust stack */
<> 144:ef7eb2e8f9f7 379 PUSH {R12, LR} /* Store stack adjustment and dummy LR */
<> 144:ef7eb2e8f9f7 380
<> 144:ef7eb2e8f9f7 381 BL CDAbtHandler
<> 144:ef7eb2e8f9f7 382
<> 144:ef7eb2e8f9f7 383 POP {R12, LR} /* Get stack adjustment & discard dummy LR */
<> 144:ef7eb2e8f9f7 384 ADD SP, SP, R12 /* Unadjust stack */
<> 144:ef7eb2e8f9f7 385
<> 144:ef7eb2e8f9f7 386 POP {R0-R4, R12} /* Restore stacked APCS registers */
<> 144:ef7eb2e8f9f7 387 RFEFD SP! /* Return from exception */
<> 144:ef7eb2e8f9f7 388 .endfunc
<> 144:ef7eb2e8f9f7 389
<> 144:ef7eb2e8f9f7 390 FIQ_Handler:
<> 144:ef7eb2e8f9f7 391 .global FIQ_Handler
<> 144:ef7eb2e8f9f7 392 .func FIQ_Handler
<> 144:ef7eb2e8f9f7 393 /* An FIQ might occur between the dummy read and the real read of the GIC in IRQ_Handler,
<> 144:ef7eb2e8f9f7 394 * so if a real FIQ Handler is implemented, this will be needed before returning:
<> 144:ef7eb2e8f9f7 395 */
<> 144:ef7eb2e8f9f7 396 /* LDR R1, =GICI_BASE
<> 144:ef7eb2e8f9f7 397 LDR R0, [R1, #ICCHPIR_OFFSET] ; Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120
<> 144:ef7eb2e8f9f7 398 */
<> 144:ef7eb2e8f9f7 399 B .
<> 144:ef7eb2e8f9f7 400 .endfunc
<> 144:ef7eb2e8f9f7 401
<> 144:ef7eb2e8f9f7 402 .extern SVC_Handler /* refer RTX function */
<> 144:ef7eb2e8f9f7 403
<> 144:ef7eb2e8f9f7 404 IRQ_Handler:
<> 144:ef7eb2e8f9f7 405 .global IRQ_Handler
<> 144:ef7eb2e8f9f7 406 .func IRQ_Handler
<> 144:ef7eb2e8f9f7 407 .extern IRQCount
<> 144:ef7eb2e8f9f7 408 .extern IRQTable
<> 144:ef7eb2e8f9f7 409 .extern IRQNestLevel
<> 144:ef7eb2e8f9f7 410
<> 144:ef7eb2e8f9f7 411 /* prologue */
<> 144:ef7eb2e8f9f7 412 SUB LR, LR, #4 /* Pre-adjust LR */
<> 144:ef7eb2e8f9f7 413 SRSDB SP!, #Mode_SVC /* Save LR_IRQ and SPRS_IRQ to SVC mode stack */
<> 144:ef7eb2e8f9f7 414 CPS #Mode_SVC /* Switch to SVC mode, to avoid a nested interrupt corrupting LR on a BL */
<> 144:ef7eb2e8f9f7 415 PUSH {R0-R3, R12} /* Save remaining APCS corruptible registers to SVC stack */
<> 144:ef7eb2e8f9f7 416
<> 144:ef7eb2e8f9f7 417 /* AND R1, SP, #4 */ /* Ensure stack is 8-byte aligned */
<> 144:ef7eb2e8f9f7 418 MOV R3, SP /* Ensure stack is 8-byte aligned */
<> 144:ef7eb2e8f9f7 419 AND R1, R3, #4
<> 144:ef7eb2e8f9f7 420 SUB SP, SP, R1 /* Adjust stack */
<> 144:ef7eb2e8f9f7 421 PUSH {R1, LR} /* Store stack adjustment and LR_SVC to SVC stack */
<> 144:ef7eb2e8f9f7 422
<> 144:ef7eb2e8f9f7 423 LDR R0, =IRQNestLevel /* Get address of nesting counter */
<> 144:ef7eb2e8f9f7 424 LDR R1, [R0]
<> 144:ef7eb2e8f9f7 425 ADD R1, R1, #1 /* Increment nesting counter */
<> 144:ef7eb2e8f9f7 426 STR R1, [R0]
<> 144:ef7eb2e8f9f7 427
<> 144:ef7eb2e8f9f7 428 /* identify and acknowledge interrupt */
<> 144:ef7eb2e8f9f7 429 LDR R1, =GICI_BASE
<> 144:ef7eb2e8f9f7 430 LDR R0, [R1, #ICCHPIR_OFFSET] /* Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120 */
<> 144:ef7eb2e8f9f7 431 LDR R0, [R1, #ICCIAR_OFFSET] /* Read ICCIAR (GIC CPU Interface register) */
<> 144:ef7eb2e8f9f7 432 DSB /* Ensure that interrupt acknowledge completes before re-enabling interrupts */
<> 144:ef7eb2e8f9f7 433
<> 144:ef7eb2e8f9f7 434 /* Workaround GIC 390 errata 733075
<> 144:ef7eb2e8f9f7 435 * If the ID is not 0, then service the interrupt as normal.
<> 144:ef7eb2e8f9f7 436 * If the ID is 0 and active, then service interrupt ID 0 as normal.
<> 144:ef7eb2e8f9f7 437 * If the ID is 0 but not active, then the GIC CPU interface may be locked-up, so unlock it
<> 144:ef7eb2e8f9f7 438 * with a dummy write to ICDIPR0. This interrupt should be treated as spurious and not serviced.
<> 144:ef7eb2e8f9f7 439 */
<> 144:ef7eb2e8f9f7 440 LDR R2, =GICD_BASE
<> 144:ef7eb2e8f9f7 441 LDR R3, =GIC_ERRATA_CHECK_1
<> 144:ef7eb2e8f9f7 442 CMP R0, R3
<> 144:ef7eb2e8f9f7 443 BEQ unlock_cpu
<> 144:ef7eb2e8f9f7 444 LDR R3, =GIC_ERRATA_CHECK_2
<> 144:ef7eb2e8f9f7 445 CMP R0, R3
<> 144:ef7eb2e8f9f7 446 BEQ unlock_cpu
<> 144:ef7eb2e8f9f7 447 CMP R0, #0
<> 144:ef7eb2e8f9f7 448 BNE int_active /* If the ID is not 0, then service the interrupt */
<> 144:ef7eb2e8f9f7 449 LDR R3, [R2, #ICDABR0_OFFSET] /* Get the interrupt state */
<> 144:ef7eb2e8f9f7 450 TST R3, #1
<> 144:ef7eb2e8f9f7 451 BNE int_active /* If active, then service the interrupt */
<> 144:ef7eb2e8f9f7 452 unlock_cpu:
<> 144:ef7eb2e8f9f7 453 LDR R3, [R2, #ICDIPR0_OFFSET] /* Not active, so unlock the CPU interface */
<> 144:ef7eb2e8f9f7 454 STR R3, [R2, #ICDIPR0_OFFSET] /* with a dummy write */
<> 144:ef7eb2e8f9f7 455 DSB /* Ensure the write completes before continuing */
<> 144:ef7eb2e8f9f7 456 B ret_irq /* Do not service the spurious interrupt */
<> 144:ef7eb2e8f9f7 457 /* End workaround */
<> 144:ef7eb2e8f9f7 458
<> 144:ef7eb2e8f9f7 459 int_active:
<> 144:ef7eb2e8f9f7 460 LDR R2, =IRQCount /* Read number of IRQs */
<> 144:ef7eb2e8f9f7 461 LDR R2, [R2]
<> 144:ef7eb2e8f9f7 462 CMP R0, R2 /* Clean up and return if no handler */
<> 144:ef7eb2e8f9f7 463 BHS ret_irq /* In a single-processor system, spurious interrupt ID 1023 does not need any special handling */
<> 144:ef7eb2e8f9f7 464 LDR R2, =IRQTable /* Get address of handler */
<> 144:ef7eb2e8f9f7 465 LDR R2, [R2, R0, LSL #2]
<> 144:ef7eb2e8f9f7 466 CMP R2, #0 /* Clean up and return if handler address is 0 */
<> 144:ef7eb2e8f9f7 467 BEQ ret_irq
<> 144:ef7eb2e8f9f7 468 PUSH {R0,R1}
<> 144:ef7eb2e8f9f7 469
<> 144:ef7eb2e8f9f7 470 CPSIE i /* Now safe to re-enable interrupts */
<> 144:ef7eb2e8f9f7 471 BLX R2 /* Call handler. R0 will be IRQ number */
<> 144:ef7eb2e8f9f7 472 CPSID i /* Disable interrupts again */
<> 144:ef7eb2e8f9f7 473
<> 144:ef7eb2e8f9f7 474 /* write EOIR (GIC CPU Interface register) */
<> 144:ef7eb2e8f9f7 475 POP {R0,R1}
<> 144:ef7eb2e8f9f7 476 DSB /* Ensure that interrupt source is cleared before we write the EOIR */
<> 144:ef7eb2e8f9f7 477 ret_irq:
<> 144:ef7eb2e8f9f7 478 /* epilogue */
<> 144:ef7eb2e8f9f7 479 STR R0, [R1, #ICCEOIR_OFFSET]
<> 144:ef7eb2e8f9f7 480
<> 144:ef7eb2e8f9f7 481 LDR R0, =IRQNestLevel /* Get address of nesting counter */
<> 144:ef7eb2e8f9f7 482 LDR R1, [R0]
<> 144:ef7eb2e8f9f7 483 SUB R1, R1, #1 /* Decrement nesting counter */
<> 144:ef7eb2e8f9f7 484 STR R1, [R0]
<> 144:ef7eb2e8f9f7 485
<> 144:ef7eb2e8f9f7 486 POP {R1, LR} /* Get stack adjustment and restore LR_SVC */
<> 144:ef7eb2e8f9f7 487 ADD SP, SP, R1 /* Unadjust stack */
<> 144:ef7eb2e8f9f7 488
<> 144:ef7eb2e8f9f7 489 POP {R0-R3,R12} /* Restore stacked APCS registers */
<> 144:ef7eb2e8f9f7 490 RFEFD SP! /* Return from exception */
<> 144:ef7eb2e8f9f7 491 .endfunc
<> 144:ef7eb2e8f9f7 492
<> 144:ef7eb2e8f9f7 493 /* Macro to define default handlers. Default handler
<> 144:ef7eb2e8f9f7 494 * will be weak symbol and just dead loops. They can be
<> 144:ef7eb2e8f9f7 495 * overwritten by other handlers */
<> 144:ef7eb2e8f9f7 496 .macro def_default_handler handler_name
<> 144:ef7eb2e8f9f7 497 .align 1
<> 144:ef7eb2e8f9f7 498 .thumb_func
<> 144:ef7eb2e8f9f7 499 .weak \handler_name
<> 144:ef7eb2e8f9f7 500 .type \handler_name, %function
<> 144:ef7eb2e8f9f7 501 \handler_name :
<> 144:ef7eb2e8f9f7 502 b .
<> 144:ef7eb2e8f9f7 503 .size \handler_name, . - \handler_name
<> 144:ef7eb2e8f9f7 504 .endm
<> 144:ef7eb2e8f9f7 505
<> 144:ef7eb2e8f9f7 506 def_default_handler SVC_Handler
<> 144:ef7eb2e8f9f7 507
<> 144:ef7eb2e8f9f7 508
<> 144:ef7eb2e8f9f7 509 /* User Initial Stack & Heap */
<> 144:ef7eb2e8f9f7 510
<> 144:ef7eb2e8f9f7 511 .ifdef __MICROLIB
<> 144:ef7eb2e8f9f7 512
<> 144:ef7eb2e8f9f7 513 .global __initial_sp
<> 144:ef7eb2e8f9f7 514 .global __heap_base
<> 144:ef7eb2e8f9f7 515 .global __heap_limit
<> 144:ef7eb2e8f9f7 516
<> 144:ef7eb2e8f9f7 517 .else
<> 144:ef7eb2e8f9f7 518
<> 144:ef7eb2e8f9f7 519 .extern __use_two_region_memory
<> 144:ef7eb2e8f9f7 520 .global __user_initial_stackheap
<> 144:ef7eb2e8f9f7 521 __user_initial_stackheap:
<> 144:ef7eb2e8f9f7 522
<> 144:ef7eb2e8f9f7 523 LDR R0, = __HeapBase
<> 144:ef7eb2e8f9f7 524 LDR R1, =(__StackTop)
<> 144:ef7eb2e8f9f7 525 LDR R2, = (__HeapBase + Heap_Size)
<> 144:ef7eb2e8f9f7 526 LDR R3, = (__StackTop - USR_Stack_Size)
<> 144:ef7eb2e8f9f7 527 BX LR
<> 144:ef7eb2e8f9f7 528
<> 144:ef7eb2e8f9f7 529 .endif
<> 144:ef7eb2e8f9f7 530
<> 144:ef7eb2e8f9f7 531
<> 144:ef7eb2e8f9f7 532 .END