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targets/cmsis/TARGET_STM/TARGET_STM32L4/stm32l4xx_ll_dac.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:: <>
Date:: Fri Sep 02 15:07:44 2016 +0100
Revision:: 144:ef7eb2e8f9f7

This updates the lib to the mbed lib v125

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	144:ef7eb2e8f9f7	1	/**
<>	144:ef7eb2e8f9f7	2	******************************************************************************
<>	144:ef7eb2e8f9f7	3	* @file stm32l4xx_ll_dac.h
<>	144:ef7eb2e8f9f7	4	* @author MCD Application Team
<>	144:ef7eb2e8f9f7	5	* @version V1.5.1
<>	144:ef7eb2e8f9f7	6	* @date 31-May-2016
<>	144:ef7eb2e8f9f7	7	* @brief Header file of DAC LL module.
<>	144:ef7eb2e8f9f7	8	******************************************************************************
<>	144:ef7eb2e8f9f7	9	* @attention
<>	144:ef7eb2e8f9f7	10	*
<>	144:ef7eb2e8f9f7	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	144:ef7eb2e8f9f7	12	*
<>	144:ef7eb2e8f9f7	13	* Redistribution and use in source and binary forms, with or without modification,
<>	144:ef7eb2e8f9f7	14	* are permitted provided that the following conditions are met:
<>	144:ef7eb2e8f9f7	15	* 1. Redistributions of source code must retain the above copyright notice,
<>	144:ef7eb2e8f9f7	16	* this list of conditions and the following disclaimer.
<>	144:ef7eb2e8f9f7	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	144:ef7eb2e8f9f7	18	* this list of conditions and the following disclaimer in the documentation
<>	144:ef7eb2e8f9f7	19	* and/or other materials provided with the distribution.
<>	144:ef7eb2e8f9f7	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	144:ef7eb2e8f9f7	21	* may be used to endorse or promote products derived from this software
<>	144:ef7eb2e8f9f7	22	* without specific prior written permission.
<>	144:ef7eb2e8f9f7	23	*
<>	144:ef7eb2e8f9f7	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	144:ef7eb2e8f9f7	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	144:ef7eb2e8f9f7	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	144:ef7eb2e8f9f7	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	144:ef7eb2e8f9f7	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	144:ef7eb2e8f9f7	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	144:ef7eb2e8f9f7	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	144:ef7eb2e8f9f7	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	144:ef7eb2e8f9f7	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	144:ef7eb2e8f9f7	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	144:ef7eb2e8f9f7	34	*
<>	144:ef7eb2e8f9f7	35	******************************************************************************
<>	144:ef7eb2e8f9f7	36	*/
<>	144:ef7eb2e8f9f7	37
<>	144:ef7eb2e8f9f7	38	/* Define to prevent recursive inclusion -------------------------------------*/
<>	144:ef7eb2e8f9f7	39	#ifndef __STM32L4xx_LL_DAC_H
<>	144:ef7eb2e8f9f7	40	#define __STM32L4xx_LL_DAC_H
<>	144:ef7eb2e8f9f7	41
<>	144:ef7eb2e8f9f7	42	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	43	extern "C" {
<>	144:ef7eb2e8f9f7	44	#endif
<>	144:ef7eb2e8f9f7	45
<>	144:ef7eb2e8f9f7	46	/* Includes ------------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	47	#include "stm32l4xx.h"
<>	144:ef7eb2e8f9f7	48
<>	144:ef7eb2e8f9f7	49	/** @addtogroup STM32L4xx_LL_Driver
<>	144:ef7eb2e8f9f7	50	* @{
<>	144:ef7eb2e8f9f7	51	*/
<>	144:ef7eb2e8f9f7	52
<>	144:ef7eb2e8f9f7	53	#if defined (DAC1)
<>	144:ef7eb2e8f9f7	54
<>	144:ef7eb2e8f9f7	55	/** @defgroup DAC_LL DAC
<>	144:ef7eb2e8f9f7	56	* @{
<>	144:ef7eb2e8f9f7	57	*/
<>	144:ef7eb2e8f9f7	58
<>	144:ef7eb2e8f9f7	59	/* Private types -------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	60	/* Private variables ---------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	61
<>	144:ef7eb2e8f9f7	62	/* Private constants ---------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	63	/** @defgroup DAC_LL_Private_Constants DAC Private Constants
<>	144:ef7eb2e8f9f7	64	* @{
<>	144:ef7eb2e8f9f7	65	*/
<>	144:ef7eb2e8f9f7	66
<>	144:ef7eb2e8f9f7	67	/* Internal masks for DAC channels definition */
<>	144:ef7eb2e8f9f7	68	/* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */
<>	144:ef7eb2e8f9f7	69	/* - channel bits position into registers CR, MCR, CCR, SHHR, SHRR */
<>	144:ef7eb2e8f9f7	70	/* - channel bits position into register SWTRIG */
<>	144:ef7eb2e8f9f7	71	/* - channel register offset of data holding register DHRx */
<>	144:ef7eb2e8f9f7	72	/* - channel register offset of data output register DORx */
<>	144:ef7eb2e8f9f7	73	/* - channel register offset of sample-and-hold sample time register SHSRx */
<>	144:ef7eb2e8f9f7	74
<>	144:ef7eb2e8f9f7	75	#define DAC_CR_CH1_BITOFFSET ((uint32_t) 0U) /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */
<>	144:ef7eb2e8f9f7	76	#define DAC_CR_CH2_BITOFFSET ((uint32_t)16U) /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */
<>	144:ef7eb2e8f9f7	77	#define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET \| DAC_CR_CH2_BITOFFSET)
<>	144:ef7eb2e8f9f7	78
<>	144:ef7eb2e8f9f7	79	#define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
<>	144:ef7eb2e8f9f7	80	#define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
<>	144:ef7eb2e8f9f7	81	#define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 \| DAC_SWTR_CH2)
<>	144:ef7eb2e8f9f7	82
<>	144:ef7eb2e8f9f7	83	#define DAC_REG_DHR12R1_REGOFFSET ((uint32_t)0x00000000U) /* Register DHR12Rx channel 1 taken as reference */
<>	144:ef7eb2e8f9f7	84	#define DAC_REG_DHR12L1_REGOFFSET ((uint32_t)0x00100000U) /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */
<>	144:ef7eb2e8f9f7	85	#define DAC_REG_DHR8R1_REGOFFSET ((uint32_t)0x02000000U) /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */
<>	144:ef7eb2e8f9f7	86	#define DAC_REG_DHR12R2_REGOFFSET ((uint32_t)0x00030000U) /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */
<>	144:ef7eb2e8f9f7	87	#define DAC_REG_DHR12L2_REGOFFSET ((uint32_t)0x00400000U) /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
<>	144:ef7eb2e8f9f7	88	#define DAC_REG_DHR8R2_REGOFFSET ((uint32_t)0x05000000U) /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
<>	144:ef7eb2e8f9f7	89	#define DAC_REG_DHR12RX_REGOFFSET_MASK ((uint32_t)0x000F0000U)
<>	144:ef7eb2e8f9f7	90	#define DAC_REG_DHR12LX_REGOFFSET_MASK ((uint32_t)0x00F00000U)
<>	144:ef7eb2e8f9f7	91	#define DAC_REG_DHR8RX_REGOFFSET_MASK ((uint32_t)0x0F000000U)
<>	144:ef7eb2e8f9f7	92	#define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK \| DAC_REG_DHR12LX_REGOFFSET_MASK \| DAC_REG_DHR8RX_REGOFFSET_MASK)
<>	144:ef7eb2e8f9f7	93
<>	144:ef7eb2e8f9f7	94	#define DAC_REG_DOR1_REGOFFSET ((uint32_t)0x00000000U) /* Register DORx channel 1 taken as reference */
<>	144:ef7eb2e8f9f7	95	#define DAC_REG_DOR2_REGOFFSET ((uint32_t)0x10000000U)/* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 28 bits) */
<>	144:ef7eb2e8f9f7	96	#define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET \| DAC_REG_DOR2_REGOFFSET)
<>	144:ef7eb2e8f9f7	97
<>	144:ef7eb2e8f9f7	98	#define DAC_REG_SHSR1_REGOFFSET ((uint32_t)0x00000000U) /* Register SHSRx channel 1 taken as reference */
<>	144:ef7eb2e8f9f7	99	#define DAC_REG_SHSR2_REGOFFSET ((uint32_t)0x00001000U) /* Register offset of SHSRx channel 1 versus SHSRx channel 2 (shifted left of 12 bits) */
<>	144:ef7eb2e8f9f7	100	#define DAC_REG_SHSRX_REGOFFSET_MASK (DAC_REG_SHSR1_REGOFFSET \| DAC_REG_SHSR2_REGOFFSET)
<>	144:ef7eb2e8f9f7	101
<>	144:ef7eb2e8f9f7	102	/* DAC registers bits positions */
<>	144:ef7eb2e8f9f7	103	#define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS ((uint32_t)16U) /* Value equivalent to POSITION_VAL(DAC_DHR12RD_DACC2DHR) */
<>	144:ef7eb2e8f9f7	104	#define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS ((uint32_t)20U) /* Value equivalent to POSITION_VAL(DAC_DHR12LD_DACC2DHR) */
<>	144:ef7eb2e8f9f7	105	#define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS ((uint32_t) 8U) /* Value equivalent to POSITION_VAL(DAC_DHR8RD_DACC2DHR) */
<>	144:ef7eb2e8f9f7	106
<>	144:ef7eb2e8f9f7	107	/* Miscellaneous data */
<>	144:ef7eb2e8f9f7	108	#define DAC_DIGITAL_SCALE_12BITS ((uint32_t)4095U) /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */
<>	144:ef7eb2e8f9f7	109
<>	144:ef7eb2e8f9f7	110	/**
<>	144:ef7eb2e8f9f7	111	* @}
<>	144:ef7eb2e8f9f7	112	*/
<>	144:ef7eb2e8f9f7	113
<>	144:ef7eb2e8f9f7	114
<>	144:ef7eb2e8f9f7	115	/* Private macros ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	116	/** @defgroup DAC_LL_Private_Macros DAC Private Macros
<>	144:ef7eb2e8f9f7	117	* @{
<>	144:ef7eb2e8f9f7	118	*/
<>	144:ef7eb2e8f9f7	119
<>	144:ef7eb2e8f9f7	120	/**
<>	144:ef7eb2e8f9f7	121	* @brief Driver macro reserved for internal use: isolate bits with the
<>	144:ef7eb2e8f9f7	122	* selected mask and shift them to the register LSB
<>	144:ef7eb2e8f9f7	123	* (shift mask on register position bit 0).
<>	144:ef7eb2e8f9f7	124	* @param __BITS__ Bits in register 32 bits
<>	144:ef7eb2e8f9f7	125	* @param __MASK__ Mask in register 32 bits
<>	144:ef7eb2e8f9f7	126	* @retval Bits in register 32 bits
<>	144:ef7eb2e8f9f7	127	*/
<>	144:ef7eb2e8f9f7	128	#define __DAC_MASK_SHIFT(__BITS__, __MASK__) \
<>	144:ef7eb2e8f9f7	129	(((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
<>	144:ef7eb2e8f9f7	130
<>	144:ef7eb2e8f9f7	131	/**
<>	144:ef7eb2e8f9f7	132	* @brief Driver macro reserved for internal use: set a pointer to
<>	144:ef7eb2e8f9f7	133	* a register from a register basis from which an offset
<>	144:ef7eb2e8f9f7	134	* is applied.
<>	144:ef7eb2e8f9f7	135	* @param __REG__ Register basis from which the offset is applied.
<>	144:ef7eb2e8f9f7	136	* @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
<>	144:ef7eb2e8f9f7	137	* @retval Pointer to register address
<>	144:ef7eb2e8f9f7	138	*/
<>	144:ef7eb2e8f9f7	139	#define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
<>	144:ef7eb2e8f9f7	140	((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
<>	144:ef7eb2e8f9f7	141
<>	144:ef7eb2e8f9f7	142	/**
<>	144:ef7eb2e8f9f7	143	* @}
<>	144:ef7eb2e8f9f7	144	*/
<>	144:ef7eb2e8f9f7	145
<>	144:ef7eb2e8f9f7	146
<>	144:ef7eb2e8f9f7	147	/* Exported types ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	148	#if defined(USE_FULL_LL_DRIVER)
<>	144:ef7eb2e8f9f7	149	/** @defgroup DAC_LL_ES_INIT DAC Exported Init structure
<>	144:ef7eb2e8f9f7	150	* @{
<>	144:ef7eb2e8f9f7	151	*/
<>	144:ef7eb2e8f9f7	152
<>	144:ef7eb2e8f9f7	153	/**
<>	144:ef7eb2e8f9f7	154	* @brief Structure definition of some features of DAC instance.
<>	144:ef7eb2e8f9f7	155	*/
<>	144:ef7eb2e8f9f7	156	typedef struct
<>	144:ef7eb2e8f9f7	157	{
<>	144:ef7eb2e8f9f7	158	uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external IP (timer event, external interrupt line).
<>	144:ef7eb2e8f9f7	159	This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
<>	144:ef7eb2e8f9f7	160
<>	144:ef7eb2e8f9f7	161	This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource(). */
<>	144:ef7eb2e8f9f7	162
<>	144:ef7eb2e8f9f7	163	uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel.
<>	144:ef7eb2e8f9f7	164	This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
<>	144:ef7eb2e8f9f7	165
<>	144:ef7eb2e8f9f7	166	This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveAutoGeneration(). */
<>	144:ef7eb2e8f9f7	167
<>	144:ef7eb2e8f9f7	168	uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel.
<>	144:ef7eb2e8f9f7	169	If waveform automatic generation mode is set to noise, this parameter can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
<>	144:ef7eb2e8f9f7	170	If waveform automatic generation mode is set to triangle, this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
<>	144:ef7eb2e8f9f7	171	@note If waveform automatic generation mode is disabled, this parameter is discarded.
<>	144:ef7eb2e8f9f7	172
<>	144:ef7eb2e8f9f7	173	This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveNoiseLFSR() or @ref LL_DAC_SetWaveTriangleAmplitude(), depending on the wave automatic generation selected. */
<>	144:ef7eb2e8f9f7	174
<>	144:ef7eb2e8f9f7	175	uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel.
<>	144:ef7eb2e8f9f7	176	This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
<>	144:ef7eb2e8f9f7	177
<>	144:ef7eb2e8f9f7	178	This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputBuffer(). */
<>	144:ef7eb2e8f9f7	179
<>	144:ef7eb2e8f9f7	180	uint32_t OutputConnection; /*!< Set the output connection for the selected DAC channel.
<>	144:ef7eb2e8f9f7	181	This parameter can be a value of @ref DAC_LL_EC_OUTPUT_CONNECTION
<>	144:ef7eb2e8f9f7	182
<>	144:ef7eb2e8f9f7	183	This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputConnection(). */
<>	144:ef7eb2e8f9f7	184
<>	144:ef7eb2e8f9f7	185	uint32_t OutputMode; /*!< Set the output mode normal or sample-and-hold for the selected DAC channel.
<>	144:ef7eb2e8f9f7	186	This parameter can be a value of @ref DAC_LL_EC_OUTPUT_MODE
<>	144:ef7eb2e8f9f7	187
<>	144:ef7eb2e8f9f7	188	This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputMode(). */
<>	144:ef7eb2e8f9f7	189
<>	144:ef7eb2e8f9f7	190	} LL_DAC_InitTypeDef;
<>	144:ef7eb2e8f9f7	191
<>	144:ef7eb2e8f9f7	192	/**
<>	144:ef7eb2e8f9f7	193	* @}
<>	144:ef7eb2e8f9f7	194	*/
<>	144:ef7eb2e8f9f7	195	#endif /* USE_FULL_LL_DRIVER */
<>	144:ef7eb2e8f9f7	196
<>	144:ef7eb2e8f9f7	197	/* Exported constants --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	198	/** @defgroup DAC_LL_Exported_Constants DAC Exported Constants
<>	144:ef7eb2e8f9f7	199	* @{
<>	144:ef7eb2e8f9f7	200	*/
<>	144:ef7eb2e8f9f7	201
<>	144:ef7eb2e8f9f7	202	/** @defgroup DAC_LL_EC_GET_FLAG DAC flags
<>	144:ef7eb2e8f9f7	203	* @brief Flags defines which can be used with LL_DAC_ReadReg function
<>	144:ef7eb2e8f9f7	204	* @{
<>	144:ef7eb2e8f9f7	205	*/
<>	144:ef7eb2e8f9f7	206	/* DAC channel 1 flags */
<>	144:ef7eb2e8f9f7	207	#define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /!< DAC channel 1 flag DMA underrun /
<>	144:ef7eb2e8f9f7	208	#define LL_DAC_FLAG_CAL1 (DAC_SR_CAL_FLAG1) /!< DAC channel 1 flag offset calibration status /
<>	144:ef7eb2e8f9f7	209	#define LL_DAC_FLAG_BWST1 (DAC_SR_BWST1) /!< DAC channel 1 flag busy writing sample time /
<>	144:ef7eb2e8f9f7	210
<>	144:ef7eb2e8f9f7	211	/* DAC channel 2 flags */
<>	144:ef7eb2e8f9f7	212	#define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /!< DAC channel 2 flag DMA underrun /
<>	144:ef7eb2e8f9f7	213	#define LL_DAC_FLAG_CAL2 (DAC_SR_CAL_FLAG2) /!< DAC channel 2 flag offset calibration status /
<>	144:ef7eb2e8f9f7	214	#define LL_DAC_FLAG_BWST2 (DAC_SR_BWST2) /!< DAC channel 2 flag busy writing sample time /
<>	144:ef7eb2e8f9f7	215	/**
<>	144:ef7eb2e8f9f7	216	* @}
<>	144:ef7eb2e8f9f7	217	*/
<>	144:ef7eb2e8f9f7	218
<>	144:ef7eb2e8f9f7	219	/** @defgroup DAC_LL_EC_IT DAC interruptions
<>	144:ef7eb2e8f9f7	220	* @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions
<>	144:ef7eb2e8f9f7	221	* @{
<>	144:ef7eb2e8f9f7	222	*/
<>	144:ef7eb2e8f9f7	223	#define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /!< DAC channel 1 interruption DMA underrun /
<>	144:ef7eb2e8f9f7	224	#define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /!< DAC channel 2 interruption DMA underrun /
<>	144:ef7eb2e8f9f7	225	/**
<>	144:ef7eb2e8f9f7	226	* @}
<>	144:ef7eb2e8f9f7	227	*/
<>	144:ef7eb2e8f9f7	228
<>	144:ef7eb2e8f9f7	229	/** @defgroup DAC_LL_EC_CHANNEL DAC channels
<>	144:ef7eb2e8f9f7	230	* @{
<>	144:ef7eb2e8f9f7	231	*/
<>	144:ef7eb2e8f9f7	232	#define LL_DAC_CHANNEL_1 (DAC_REG_SHSR1_REGOFFSET \| DAC_REG_DOR1_REGOFFSET \| DAC_REG_DHR12R1_REGOFFSET \| DAC_REG_DHR12L1_REGOFFSET \| DAC_REG_DHR8R1_REGOFFSET \| DAC_CR_CH1_BITOFFSET \| DAC_SWTR_CH1) /!< DAC channel 1 /
<>	144:ef7eb2e8f9f7	233	#define LL_DAC_CHANNEL_2 (DAC_REG_SHSR2_REGOFFSET \| DAC_REG_DOR2_REGOFFSET \| DAC_REG_DHR12R2_REGOFFSET \| DAC_REG_DHR12L2_REGOFFSET \| DAC_REG_DHR8R2_REGOFFSET \| DAC_CR_CH2_BITOFFSET \| DAC_SWTR_CH2) /!< DAC channel 2 /
<>	144:ef7eb2e8f9f7	234	/**
<>	144:ef7eb2e8f9f7	235	* @}
<>	144:ef7eb2e8f9f7	236	*/
<>	144:ef7eb2e8f9f7	237
<>	144:ef7eb2e8f9f7	238	/** @defgroup DAC_LL_EC_OPERATING_MODE DAC operating mode
<>	144:ef7eb2e8f9f7	239	* @{
<>	144:ef7eb2e8f9f7	240	*/
<>	144:ef7eb2e8f9f7	241	#define LL_DAC_MODE_NORMAL_OPERATION ((uint32_t)0x00000000U) /!< DAC channel in mode normal operation /
<>	144:ef7eb2e8f9f7	242	#define LL_DAC_MODE_CALIBRATION (DAC_CR_CEN1) /!< DAC channel in mode calibration /
<>	144:ef7eb2e8f9f7	243	/**
<>	144:ef7eb2e8f9f7	244	* @}
<>	144:ef7eb2e8f9f7	245	*/
<>	144:ef7eb2e8f9f7	246
<>	144:ef7eb2e8f9f7	247	/** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source
<>	144:ef7eb2e8f9f7	248	* @{
<>	144:ef7eb2e8f9f7	249	*/
<>	144:ef7eb2e8f9f7	250	#define LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 \| DAC_CR_TSEL1_1 \| DAC_CR_TSEL1_0) /!< DAC channel conversion trigger internal (SW start) /
<>	144:ef7eb2e8f9f7	251	#define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /!< DAC channel conversion trigger from external IP: TIM2 TRGO. /
<>	144:ef7eb2e8f9f7	252	#define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 \| DAC_CR_TSEL1_0) /!< DAC channel conversion trigger from external IP: TIM4 TRGO. /
<>	144:ef7eb2e8f9f7	253	#define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_1 \| DAC_CR_TSEL1_0) /!< DAC channel conversion trigger from external IP: TIM5 TRGO. /
<>	144:ef7eb2e8f9f7	254	#define LL_DAC_TRIG_EXT_TIM6_TRGO ((uint32_t)0x00000000U) /!< DAC channel conversion trigger from external IP: TIM6 TRGO. /
<>	144:ef7eb2e8f9f7	255	#define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /!< DAC channel conversion trigger from external IP: TIM7 TRGO. /
<>	144:ef7eb2e8f9f7	256	#define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_0) /!< DAC channel conversion trigger from external IP: TIM8 TRGO. /
<>	144:ef7eb2e8f9f7	257	#define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 \| DAC_CR_TSEL1_1 ) /!< DAC channel conversion trigger from external IP: external interrupt line 9. /
<>	144:ef7eb2e8f9f7	258	/**
<>	144:ef7eb2e8f9f7	259	* @}
<>	144:ef7eb2e8f9f7	260	*/
<>	144:ef7eb2e8f9f7	261
<>	144:ef7eb2e8f9f7	262	/** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
<>	144:ef7eb2e8f9f7	263	* @{
<>	144:ef7eb2e8f9f7	264	*/
<>	144:ef7eb2e8f9f7	265	#define LL_DAC_WAVE_AUTO_GENERATION_NONE ((uint32_t)0x00000000U) /!< DAC channel wave auto generation mode disabled. /
<>	144:ef7eb2e8f9f7	266	#define LL_DAC_WAVE_AUTO_GENERATION_NOISE (DAC_CR_WAVE1_0) /!< DAC channel wave auto generation mode enabled, set generated noise waveform. /
<>	144:ef7eb2e8f9f7	267	#define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1) /!< DAC channel wave auto generation mode enabled, set generated triangle waveform. /
<>	144:ef7eb2e8f9f7	268	/**
<>	144:ef7eb2e8f9f7	269	* @}
<>	144:ef7eb2e8f9f7	270	*/
<>	144:ef7eb2e8f9f7	271
<>	144:ef7eb2e8f9f7	272	/** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
<>	144:ef7eb2e8f9f7	273	* @{
<>	144:ef7eb2e8f9f7	274	*/
<>	144:ef7eb2e8f9f7	275	#define LL_DAC_NOISE_LFSR_UNMASK_BIT0 ((uint32_t)0x00000000U) /!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel /
<>	144:ef7eb2e8f9f7	276	#define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel /
<>	144:ef7eb2e8f9f7	277	#define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel /
<>	144:ef7eb2e8f9f7	278	#define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 \| DAC_CR_MAMP1_0) /!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel /
<>	144:ef7eb2e8f9f7	279	#define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel /
<>	144:ef7eb2e8f9f7	280	#define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 \| DAC_CR_MAMP1_0) /!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel /
<>	144:ef7eb2e8f9f7	281	#define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 \| DAC_CR_MAMP1_1 ) /!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel /
<>	144:ef7eb2e8f9f7	282	#define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 \| DAC_CR_MAMP1_1 \| DAC_CR_MAMP1_0) /!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel /
<>	144:ef7eb2e8f9f7	283	#define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel /
<>	144:ef7eb2e8f9f7	284	#define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 \| DAC_CR_MAMP1_0) /!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel /
<>	144:ef7eb2e8f9f7	285	#define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 \| DAC_CR_MAMP1_1 ) /!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel /
<>	144:ef7eb2e8f9f7	286	#define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 \| DAC_CR_MAMP1_1 \| DAC_CR_MAMP1_0) /!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel /
<>	144:ef7eb2e8f9f7	287	/**
<>	144:ef7eb2e8f9f7	288	* @}
<>	144:ef7eb2e8f9f7	289	*/
<>	144:ef7eb2e8f9f7	290
<>	144:ef7eb2e8f9f7	291	/** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
<>	144:ef7eb2e8f9f7	292	* @{
<>	144:ef7eb2e8f9f7	293	*/
<>	144:ef7eb2e8f9f7	294	#define LL_DAC_TRIANGLE_AMPLITUDE_1 ((uint32_t)0x00000000U) /!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel /
<>	144:ef7eb2e8f9f7	295	#define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel /
<>	144:ef7eb2e8f9f7	296	#define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel /
<>	144:ef7eb2e8f9f7	297	#define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 \| DAC_CR_MAMP1_0) /!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel /
<>	144:ef7eb2e8f9f7	298	#define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel /
<>	144:ef7eb2e8f9f7	299	#define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 \| DAC_CR_MAMP1_0) /!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel /
<>	144:ef7eb2e8f9f7	300	#define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 \| DAC_CR_MAMP1_1 ) /!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel /
<>	144:ef7eb2e8f9f7	301	#define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 \| DAC_CR_MAMP1_1 \| DAC_CR_MAMP1_0) /!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel /
<>	144:ef7eb2e8f9f7	302	#define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel /
<>	144:ef7eb2e8f9f7	303	#define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 \| DAC_CR_MAMP1_0) /!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel /
<>	144:ef7eb2e8f9f7	304	#define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 \| DAC_CR_MAMP1_1 ) /!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel /
<>	144:ef7eb2e8f9f7	305	#define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 \| DAC_CR_MAMP1_1 \| DAC_CR_MAMP1_0) /!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel /
<>	144:ef7eb2e8f9f7	306	/**
<>	144:ef7eb2e8f9f7	307	* @}
<>	144:ef7eb2e8f9f7	308	*/
<>	144:ef7eb2e8f9f7	309
<>	144:ef7eb2e8f9f7	310	/** @defgroup DAC_LL_EC_OUTPUT_MODE DAC channel output mode
<>	144:ef7eb2e8f9f7	311	* @{
<>	144:ef7eb2e8f9f7	312	*/
<>	144:ef7eb2e8f9f7	313	#define LL_DAC_OUTPUT_MODE_NORMAL ((uint32_t)0x00000000U) /!< The selected DAC channel output is on mode normal. /
<>	144:ef7eb2e8f9f7	314	#define LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD (DAC_MCR_MODE1_2) /!< The selected DAC channel output is on mode sample-and-hold. Mode sample-and-hold requires an external capacitor, refer to description of function @ref LL_DAC_ConfigOutput() or @ref LL_DAC_SetOutputMode(). /
<>	144:ef7eb2e8f9f7	315	/**
<>	144:ef7eb2e8f9f7	316	* @}
<>	144:ef7eb2e8f9f7	317	*/
<>	144:ef7eb2e8f9f7	318
<>	144:ef7eb2e8f9f7	319	/** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
<>	144:ef7eb2e8f9f7	320	* @{
<>	144:ef7eb2e8f9f7	321	*/
<>	144:ef7eb2e8f9f7	322	#define LL_DAC_OUTPUT_BUFFER_ENABLE ((uint32_t)0x00000000U) /!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption /
<>	144:ef7eb2e8f9f7	323	#define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_MCR_MODE1_1) /!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption /
<>	144:ef7eb2e8f9f7	324	/**
<>	144:ef7eb2e8f9f7	325	* @}
<>	144:ef7eb2e8f9f7	326	*/
<>	144:ef7eb2e8f9f7	327
<>	144:ef7eb2e8f9f7	328	/** @defgroup DAC_LL_EC_OUTPUT_CONNECTION DAC channel output connection
<>	144:ef7eb2e8f9f7	329	* @{
<>	144:ef7eb2e8f9f7	330	*/
<>	144:ef7eb2e8f9f7	331	#define LL_DAC_OUTPUT_CONNECT_GPIO ((uint32_t)0x00000000U) /!< The selected DAC channel output is connected to external pin /
<>	144:ef7eb2e8f9f7	332	#define LL_DAC_OUTPUT_CONNECT_INTERNAL (DAC_MCR_MODE1_0) /!< The selected DAC channel output is connected to on-chip peripherals via internal paths. On this STM32 serie, output connection depends on output mode (normal or sample and hold) and output buffer state. Refer to comments of function @ref LL_DAC_SetOutputConnection(). /
<>	144:ef7eb2e8f9f7	333	/**
<>	144:ef7eb2e8f9f7	334	* @}
<>	144:ef7eb2e8f9f7	335	*/
<>	144:ef7eb2e8f9f7	336
<>	144:ef7eb2e8f9f7	337	/** @defgroup DAC_LL_EC_LEGACY DAC literals legacy naming
<>	144:ef7eb2e8f9f7	338	* @{
<>	144:ef7eb2e8f9f7	339	*/
<>	144:ef7eb2e8f9f7	340	#define LL_DAC_TRIGGER_SOFTWARE (LL_DAC_TRIG_SOFTWARE)
<>	144:ef7eb2e8f9f7	341	#define LL_DAC_TRIGGER_TIM2_TRGO (LL_DAC_TRIG_EXT_TIM2_TRGO)
<>	144:ef7eb2e8f9f7	342	#define LL_DAC_TRIGGER_TIM4_TRGO (LL_DAC_TRIG_EXT_TIM4_TRGO)
<>	144:ef7eb2e8f9f7	343	#define LL_DAC_TRIGGER_TIM5_TRGO (LL_DAC_TRIG_EXT_TIM5_TRGO)
<>	144:ef7eb2e8f9f7	344	#define LL_DAC_TRIGGER_TIM6_TRGO (LL_DAC_TRIG_EXT_TIM6_TRGO)
<>	144:ef7eb2e8f9f7	345	#define LL_DAC_TRIGGER_TIM7_TRGO (LL_DAC_TRIG_EXT_TIM7_TRGO)
<>	144:ef7eb2e8f9f7	346	#define LL_DAC_TRIGGER_TIM8_TRGO (LL_DAC_TRIG_EXT_TIM8_TRGO)
<>	144:ef7eb2e8f9f7	347	#define LL_DAC_TRIGGER_EXT_IT9 (LL_DAC_TRIG_EXT_EXTI_LINE9)
<>	144:ef7eb2e8f9f7	348
<>	144:ef7eb2e8f9f7	349	#define LL_DAC_WAVEGENERATION_NONE (LL_DAC_WAVE_AUTO_GENERATION_NONE)
<>	144:ef7eb2e8f9f7	350	#define LL_DAC_WAVEGENERATION_NOISE (LL_DAC_WAVE_AUTO_GENERATION_NOISE)
<>	144:ef7eb2e8f9f7	351	#define LL_DAC_WAVEGENERATION_TRIANGLE (LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE)
<>	144:ef7eb2e8f9f7	352
<>	144:ef7eb2e8f9f7	353	#define LL_DAC_CONNECT_GPIO (LL_DAC_OUTPUT_CONNECT_GPIO)
<>	144:ef7eb2e8f9f7	354	#define LL_DAC_CONNECT_INTERNAL (LL_DAC_OUTPUT_CONNECT_INTERNAL)
<>	144:ef7eb2e8f9f7	355	/**
<>	144:ef7eb2e8f9f7	356	* @}
<>	144:ef7eb2e8f9f7	357	*/
<>	144:ef7eb2e8f9f7	358
<>	144:ef7eb2e8f9f7	359
<>	144:ef7eb2e8f9f7	360	/** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution
<>	144:ef7eb2e8f9f7	361	* @{
<>	144:ef7eb2e8f9f7	362	*/
<>	144:ef7eb2e8f9f7	363	#define LL_DAC_RESOLUTION_12B ((uint32_t)0x00000000U) /!< DAC channel resolution 12 bits /
<>	144:ef7eb2e8f9f7	364	#define LL_DAC_RESOLUTION_8B ((uint32_t)0x00000002U) /!< DAC channel resolution 8 bits /
<>	144:ef7eb2e8f9f7	365	/**
<>	144:ef7eb2e8f9f7	366	* @}
<>	144:ef7eb2e8f9f7	367	*/
<>	144:ef7eb2e8f9f7	368
<>	144:ef7eb2e8f9f7	369	/** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose
<>	144:ef7eb2e8f9f7	370	* @{
<>	144:ef7eb2e8f9f7	371	*/
<>	144:ef7eb2e8f9f7	372	/* List of DAC registers intended to be used (most commonly) with */
<>	144:ef7eb2e8f9f7	373	/* DMA transfer. */
<>	144:ef7eb2e8f9f7	374	/* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */
<>	144:ef7eb2e8f9f7	375	#define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_MASK /!< DAC channel data holding register 12 bits right aligned /
<>	144:ef7eb2e8f9f7	376	#define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_MASK /!< DAC channel data holding register 12 bits left aligned /
<>	144:ef7eb2e8f9f7	377	#define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_MASK /!< DAC channel data holding register 8 bits right aligned /
<>	144:ef7eb2e8f9f7	378	/**
<>	144:ef7eb2e8f9f7	379	* @}
<>	144:ef7eb2e8f9f7	380	*/
<>	144:ef7eb2e8f9f7	381
<>	144:ef7eb2e8f9f7	382	/** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays
<>	144:ef7eb2e8f9f7	383	* @note Only DAC IP HW delays are defined in DAC LL driver driver,
<>	144:ef7eb2e8f9f7	384	* not timeout values.
<>	144:ef7eb2e8f9f7	385	* For details on delays values, refer to descriptions in source code
<>	144:ef7eb2e8f9f7	386	* above each literal definition.
<>	144:ef7eb2e8f9f7	387	* @{
<>	144:ef7eb2e8f9f7	388	*/
<>	144:ef7eb2e8f9f7	389
<>	144:ef7eb2e8f9f7	390	/* Delay for DAC channel voltage settling time from DAC channel startup */
<>	144:ef7eb2e8f9f7	391	/* (transition from disable to enable). */
<>	144:ef7eb2e8f9f7	392	/* Note: DAC channel startup time depends on board application environment: */
<>	144:ef7eb2e8f9f7	393	/* impedance connected to DAC channel output. */
<>	144:ef7eb2e8f9f7	394	/* The delay below is specified under conditions: */
<>	144:ef7eb2e8f9f7	395	/* - voltage maximum transition (lowest to highest value) */
<>	144:ef7eb2e8f9f7	396	/* - until voltage reaches final value +-1LSB */
<>	144:ef7eb2e8f9f7	397	/* - DAC channel output buffer enabled */
<>	144:ef7eb2e8f9f7	398	/* - load impedance of 5kOhm (min), 50pF (max) */
<>	144:ef7eb2e8f9f7	399	/* Literal set to maximum value (refer to device datasheet, */
<>	144:ef7eb2e8f9f7	400	/* parameter "tWAKEUP"). */
<>	144:ef7eb2e8f9f7	401	/* Unit: us */
<>	144:ef7eb2e8f9f7	402	#define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US ((uint32_t) 8U) /!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) /
<>	144:ef7eb2e8f9f7	403
<>	144:ef7eb2e8f9f7	404
<>	144:ef7eb2e8f9f7	405	/* Delay for DAC channel voltage settling time. */
<>	144:ef7eb2e8f9f7	406	/* Note: DAC channel startup time depends on board application environment: */
<>	144:ef7eb2e8f9f7	407	/* impedance connected to DAC channel output. */
<>	144:ef7eb2e8f9f7	408	/* The delay below is specified under conditions: */
<>	144:ef7eb2e8f9f7	409	/* - voltage maximum transition (lowest to highest value) */
<>	144:ef7eb2e8f9f7	410	/* - until voltage reaches final value +-1LSB */
<>	144:ef7eb2e8f9f7	411	/* - DAC channel output buffer enabled */
<>	144:ef7eb2e8f9f7	412	/* - load impedance of 5kOhm min, 50pF max */
<>	144:ef7eb2e8f9f7	413	/* Literal set to maximum value (refer to device datasheet, */
<>	144:ef7eb2e8f9f7	414	/* parameter "tSETTLING"). */
<>	144:ef7eb2e8f9f7	415	/* Unit: us */
<>	144:ef7eb2e8f9f7	416	#define LL_DAC_DELAY_VOLTAGE_SETTLING_US ((uint32_t) 2U) /!< Delay for DAC channel voltage settling time /
<>	144:ef7eb2e8f9f7	417
<>	144:ef7eb2e8f9f7	418	/**
<>	144:ef7eb2e8f9f7	419	* @}
<>	144:ef7eb2e8f9f7	420	*/
<>	144:ef7eb2e8f9f7	421
<>	144:ef7eb2e8f9f7	422	/**
<>	144:ef7eb2e8f9f7	423	* @}
<>	144:ef7eb2e8f9f7	424	*/
<>	144:ef7eb2e8f9f7	425
<>	144:ef7eb2e8f9f7	426	/* Exported macro ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	427	/** @defgroup DAC_LL_Exported_Macros DAC Exported Macros
<>	144:ef7eb2e8f9f7	428	* @{
<>	144:ef7eb2e8f9f7	429	*/
<>	144:ef7eb2e8f9f7	430
<>	144:ef7eb2e8f9f7	431	/** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros
<>	144:ef7eb2e8f9f7	432	* @{
<>	144:ef7eb2e8f9f7	433	*/
<>	144:ef7eb2e8f9f7	434
<>	144:ef7eb2e8f9f7	435	/**
<>	144:ef7eb2e8f9f7	436	* @brief Write a value in DAC register
<>	144:ef7eb2e8f9f7	437	* @param __INSTANCE__ DAC Instance
<>	144:ef7eb2e8f9f7	438	* @param __REG__ Register to be written
<>	144:ef7eb2e8f9f7	439	* @param __VALUE__ Value to be written in the register
<>	144:ef7eb2e8f9f7	440	* @retval None
<>	144:ef7eb2e8f9f7	441	*/
<>	144:ef7eb2e8f9f7	442	#define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
<>	144:ef7eb2e8f9f7	443
<>	144:ef7eb2e8f9f7	444	/**
<>	144:ef7eb2e8f9f7	445	* @brief Read a value in DAC register
<>	144:ef7eb2e8f9f7	446	* @param __INSTANCE__ DAC Instance
<>	144:ef7eb2e8f9f7	447	* @param __REG__ Register to be read
<>	144:ef7eb2e8f9f7	448	* @retval Register value
<>	144:ef7eb2e8f9f7	449	*/
<>	144:ef7eb2e8f9f7	450	#define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
<>	144:ef7eb2e8f9f7	451
<>	144:ef7eb2e8f9f7	452	/**
<>	144:ef7eb2e8f9f7	453	* @}
<>	144:ef7eb2e8f9f7	454	*/
<>	144:ef7eb2e8f9f7	455
<>	144:ef7eb2e8f9f7	456	/** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro
<>	144:ef7eb2e8f9f7	457	* @{
<>	144:ef7eb2e8f9f7	458	*/
<>	144:ef7eb2e8f9f7	459
<>	144:ef7eb2e8f9f7	460	/**
<>	144:ef7eb2e8f9f7	461	* @brief Helper macro to get DAC channel number in decimal format
<>	144:ef7eb2e8f9f7	462	* from literals LL_DAC_CHANNEL_x.
<>	144:ef7eb2e8f9f7	463	* Example:
<>	144:ef7eb2e8f9f7	464	* __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1)
<>	144:ef7eb2e8f9f7	465	* will return decimal number "1".
<>	144:ef7eb2e8f9f7	466	* @note The input can be a value from functions where a channel
<>	144:ef7eb2e8f9f7	467	* number is returned.
<>	144:ef7eb2e8f9f7	468	* @param __CHANNEL__ This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	469	* @arg @ref LL_DAC_CHANNEL_1
<>	144:ef7eb2e8f9f7	470	* @arg @ref LL_DAC_CHANNEL_2
<>	144:ef7eb2e8f9f7	471	* @retval 1...2
<>	144:ef7eb2e8f9f7	472	*/
<>	144:ef7eb2e8f9f7	473	#define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
<>	144:ef7eb2e8f9f7	474	((__CHANNEL__) & DAC_SWTR_CHX_MASK)
<>	144:ef7eb2e8f9f7	475
<>	144:ef7eb2e8f9f7	476	/**
<>	144:ef7eb2e8f9f7	477	* @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x
<>	144:ef7eb2e8f9f7	478	* from number in decimal format.
<>	144:ef7eb2e8f9f7	479	* Example:
<>	144:ef7eb2e8f9f7	480	* __LL_DAC_DECIMAL_NB_TO_CHANNEL(1)
<>	144:ef7eb2e8f9f7	481	* will return a data equivalent to "LL_DAC_CHANNEL_1".
<>	144:ef7eb2e8f9f7	482	* @note If the input parameter does not correspond to a DAC channel,
<>	144:ef7eb2e8f9f7	483	* this macro returns value '0'.
<>	144:ef7eb2e8f9f7	484	* @param __DECIMAL_NB__ 1...2
<>	144:ef7eb2e8f9f7	485	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	486	* @arg @ref LL_DAC_CHANNEL_1
<>	144:ef7eb2e8f9f7	487	* @arg @ref LL_DAC_CHANNEL_2
<>	144:ef7eb2e8f9f7	488	*/
<>	144:ef7eb2e8f9f7	489	#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
<>	144:ef7eb2e8f9f7	490	(((__DECIMAL_NB__) == 1U) \
<>	144:ef7eb2e8f9f7	491	? ( \
<>	144:ef7eb2e8f9f7	492	LL_DAC_CHANNEL_1 \
<>	144:ef7eb2e8f9f7	493	) \
<>	144:ef7eb2e8f9f7	494	: \
<>	144:ef7eb2e8f9f7	495	(((__DECIMAL_NB__) == 2U) \
<>	144:ef7eb2e8f9f7	496	? ( \
<>	144:ef7eb2e8f9f7	497	LL_DAC_CHANNEL_2 \
<>	144:ef7eb2e8f9f7	498	) \
<>	144:ef7eb2e8f9f7	499	: \
<>	144:ef7eb2e8f9f7	500	( \
<>	144:ef7eb2e8f9f7	501	0 \
<>	144:ef7eb2e8f9f7	502	) \
<>	144:ef7eb2e8f9f7	503	) \
<>	144:ef7eb2e8f9f7	504	)
<>	144:ef7eb2e8f9f7	505
<>	144:ef7eb2e8f9f7	506	/**
<>	144:ef7eb2e8f9f7	507	* @brief Helper macro to define the DAC conversion data full-scale digital
<>	144:ef7eb2e8f9f7	508	* value corresponding to the selected DAC resolution.
<>	144:ef7eb2e8f9f7	509	* @note DAC conversion data full-scale corresponds to voltage range
<>	144:ef7eb2e8f9f7	510	* determined by analog voltage references Vref+ and Vref-
<>	144:ef7eb2e8f9f7	511	* (refer to reference manual).
<>	144:ef7eb2e8f9f7	512	* @param __DAC_RESOLUTION__ This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	513	* @arg @ref LL_DAC_RESOLUTION_12B
<>	144:ef7eb2e8f9f7	514	* @arg @ref LL_DAC_RESOLUTION_8B
<>	144:ef7eb2e8f9f7	515	* @retval ADC conversion data equivalent voltage value (unit: mVolt)
<>	144:ef7eb2e8f9f7	516	*/
<>	144:ef7eb2e8f9f7	517	#define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
<>	144:ef7eb2e8f9f7	518	(((uint32_t)0xFFFU) >> ((__DAC_RESOLUTION__) << 1U))
<>	144:ef7eb2e8f9f7	519
<>	144:ef7eb2e8f9f7	520	/**
<>	144:ef7eb2e8f9f7	521	* @brief Helper macro to calculate the DAC conversion data (unit: digital
<>	144:ef7eb2e8f9f7	522	* value) corresponding to a voltage (unit: mVolt).
<>	144:ef7eb2e8f9f7	523	* @note This helper macro is intended to provide input data in voltage
<>	144:ef7eb2e8f9f7	524	* rather than digital value,
<>	144:ef7eb2e8f9f7	525	* to be used with LL DAC functions such as
<>	144:ef7eb2e8f9f7	526	* @ref LL_DAC_ConvertData12RightAligned().
<>	144:ef7eb2e8f9f7	527	* @note Analog reference voltage (Vref+) must be either known from
<>	144:ef7eb2e8f9f7	528	* user board environment or can be calculated using ADC measurement
<>	144:ef7eb2e8f9f7	529	* and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
<>	144:ef7eb2e8f9f7	530	* @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
<>	144:ef7eb2e8f9f7	531	* @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel
<>	144:ef7eb2e8f9f7	532	* (unit: mVolt).
<>	144:ef7eb2e8f9f7	533	* @param __DAC_RESOLUTION__ This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	534	* @arg @ref LL_DAC_RESOLUTION_12B
<>	144:ef7eb2e8f9f7	535	* @arg @ref LL_DAC_RESOLUTION_8B
<>	144:ef7eb2e8f9f7	536	* @retval DAC conversion data (unit: digital value)
<>	144:ef7eb2e8f9f7	537	*/
<>	144:ef7eb2e8f9f7	538	#define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\
<>	144:ef7eb2e8f9f7	539	__DAC_VOLTAGE__,\
<>	144:ef7eb2e8f9f7	540	__DAC_RESOLUTION__) \
<>	144:ef7eb2e8f9f7	541	((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
<>	144:ef7eb2e8f9f7	542	/ (__VREFANALOG_VOLTAGE__) \
<>	144:ef7eb2e8f9f7	543	)
<>	144:ef7eb2e8f9f7	544
<>	144:ef7eb2e8f9f7	545	/**
<>	144:ef7eb2e8f9f7	546	* @}
<>	144:ef7eb2e8f9f7	547	*/
<>	144:ef7eb2e8f9f7	548
<>	144:ef7eb2e8f9f7	549	/**
<>	144:ef7eb2e8f9f7	550	* @}
<>	144:ef7eb2e8f9f7	551	*/
<>	144:ef7eb2e8f9f7	552
<>	144:ef7eb2e8f9f7	553
<>	144:ef7eb2e8f9f7	554	/* Exported functions --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	555	/** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
<>	144:ef7eb2e8f9f7	556	* @{
<>	144:ef7eb2e8f9f7	557	*/
<>	144:ef7eb2e8f9f7	558	/** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels
<>	144:ef7eb2e8f9f7	559	* @{
<>	144:ef7eb2e8f9f7	560	*/
<>	144:ef7eb2e8f9f7	561
<>	144:ef7eb2e8f9f7	562	/**
<>	144:ef7eb2e8f9f7	563	* @brief Set the operating mode for the selected DAC channel:
<>	144:ef7eb2e8f9f7	564	* calibration or normal operating mode.
<>	144:ef7eb2e8f9f7	565	* @rmtoll CR CEN1 LL_DAC_SetMode\n
<>	144:ef7eb2e8f9f7	566	* CR CEN2 LL_DAC_SetMode
<>	144:ef7eb2e8f9f7	567	* @param DACx DAC instance
<>	144:ef7eb2e8f9f7	568	* @param DAC_Channel This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	569	* @arg @ref LL_DAC_CHANNEL_1
<>	144:ef7eb2e8f9f7	570	* @arg @ref LL_DAC_CHANNEL_2
<>	144:ef7eb2e8f9f7	571	* @param ChannelMode This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	572	* @arg @ref LL_DAC_MODE_NORMAL_OPERATION
<>	144:ef7eb2e8f9f7	573	* @arg @ref LL_DAC_MODE_CALIBRATION
<>	144:ef7eb2e8f9f7	574	* @retval None
<>	144:ef7eb2e8f9f7	575	*/
<>	144:ef7eb2e8f9f7	576	__STATIC_INLINE void LL_DAC_SetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t ChannelMode)
<>	144:ef7eb2e8f9f7	577	{
<>	144:ef7eb2e8f9f7	578	MODIFY_REG(DACx->CR,
<>	144:ef7eb2e8f9f7	579	DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
<>	144:ef7eb2e8f9f7	580	ChannelMode << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
<>	144:ef7eb2e8f9f7	581	}
<>	144:ef7eb2e8f9f7	582
<>	144:ef7eb2e8f9f7	583	/**
<>	144:ef7eb2e8f9f7	584	* @brief Get the operating mode for the selected DAC channel:
<>	144:ef7eb2e8f9f7	585	* calibration or normal operating mode.
<>	144:ef7eb2e8f9f7	586	* @rmtoll CR CEN1 LL_DAC_GetMode\n
<>	144:ef7eb2e8f9f7	587	* CR CEN2 LL_DAC_GetMode
<>	144:ef7eb2e8f9f7	588	* @param DACx DAC instance
<>	144:ef7eb2e8f9f7	589	* @param DAC_Channel This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	590	* @arg @ref LL_DAC_CHANNEL_1
<>	144:ef7eb2e8f9f7	591	* @arg @ref LL_DAC_CHANNEL_2
<>	144:ef7eb2e8f9f7	592	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	593	* @arg @ref LL_DAC_MODE_NORMAL_OPERATION
<>	144:ef7eb2e8f9f7	594	* @arg @ref LL_DAC_MODE_CALIBRATION
<>	144:ef7eb2e8f9f7	595	*/
<>	144:ef7eb2e8f9f7	596	__STATIC_INLINE uint32_t LL_DAC_GetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<>	144:ef7eb2e8f9f7	597	{
<>	144:ef7eb2e8f9f7	598	return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
<>	144:ef7eb2e8f9f7	599	>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
<>	144:ef7eb2e8f9f7	600	);
<>	144:ef7eb2e8f9f7	601	}
<>	144:ef7eb2e8f9f7	602
<>	144:ef7eb2e8f9f7	603	/**
<>	144:ef7eb2e8f9f7	604	* @brief Set the offset trimming value for the selected DAC channel.
<>	144:ef7eb2e8f9f7	605	* Trimming has an impact when output buffer is enabled
<>	144:ef7eb2e8f9f7	606	* and is intended to replace factory calibration default values.
<>	144:ef7eb2e8f9f7	607	* @rmtoll CCR OTRIM1 LL_DAC_SetTrimmingValue\n
<>	144:ef7eb2e8f9f7	608	* CCR OTRIM2 LL_DAC_SetTrimmingValue
<>	144:ef7eb2e8f9f7	609	* @param DACx DAC instance
<>	144:ef7eb2e8f9f7	610	* @param DAC_Channel This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	611	* @arg @ref LL_DAC_CHANNEL_1
<>	144:ef7eb2e8f9f7	612	* @arg @ref LL_DAC_CHANNEL_2
<>	144:ef7eb2e8f9f7	613	* @param TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F
<>	144:ef7eb2e8f9f7	614	* @retval None
<>	144:ef7eb2e8f9f7	615	*/
<>	144:ef7eb2e8f9f7	616	__STATIC_INLINE void LL_DAC_SetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TrimmingValue)
<>	144:ef7eb2e8f9f7	617	{
<>	144:ef7eb2e8f9f7	618	MODIFY_REG(DACx->CCR,
<>	144:ef7eb2e8f9f7	619	DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
<>	144:ef7eb2e8f9f7	620	TrimmingValue << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
<>	144:ef7eb2e8f9f7	621	}
<>	144:ef7eb2e8f9f7	622
<>	144:ef7eb2e8f9f7	623	/**
<>	144:ef7eb2e8f9f7	624	* @brief Get the offset trimming value for the selected DAC channel.
<>	144:ef7eb2e8f9f7	625	* Trimming has an impact when output buffer is enabled
<>	144:ef7eb2e8f9f7	626	* and is intended to replace factory calibration default values.
<>	144:ef7eb2e8f9f7	627	* @rmtoll CCR OTRIM1 LL_DAC_GetTrimmingValue\n
<>	144:ef7eb2e8f9f7	628	* CCR OTRIM2 LL_DAC_GetTrimmingValue
<>	144:ef7eb2e8f9f7	629	* @param DACx DAC instance
<>	144:ef7eb2e8f9f7	630	* @param DAC_Channel This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	631	* @arg @ref LL_DAC_CHANNEL_1
<>	144:ef7eb2e8f9f7	632	* @arg @ref LL_DAC_CHANNEL_2
<>	144:ef7eb2e8f9f7	633	* @retval TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F
<>	144:ef7eb2e8f9f7	634	*/
<>	144:ef7eb2e8f9f7	635	__STATIC_INLINE uint32_t LL_DAC_GetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<>	144:ef7eb2e8f9f7	636	{
<>	144:ef7eb2e8f9f7	637	return (uint32_t)(READ_BIT(DACx->CCR, DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
<>	144:ef7eb2e8f9f7	638	>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
<>	144:ef7eb2e8f9f7	639	);
<>	144:ef7eb2e8f9f7	640	}
<>	144:ef7eb2e8f9f7	641
<>	144:ef7eb2e8f9f7	642	/**
<>	144:ef7eb2e8f9f7	643	* @brief Set the conversion trigger source for the selected DAC channel.
<>	144:ef7eb2e8f9f7	644	* @note For conversion trigger source to be effective, DAC trigger
<>	144:ef7eb2e8f9f7	645	* must be enabled using function @ref LL_DAC_EnableTrigger().
<>	144:ef7eb2e8f9f7	646	* @note To set conversion trigger source, DAC channel must be disabled.
<>	144:ef7eb2e8f9f7	647	* Otherwise, the setting is discarded.
<>	144:ef7eb2e8f9f7	648	* @note Availability of parameters of trigger sources from timer
<>	144:ef7eb2e8f9f7	649	* depends on timers availability on the selected device.
<>	144:ef7eb2e8f9f7	650	* @rmtoll CR TSEL1 LL_DAC_SetTriggerSource\n
<>	144:ef7eb2e8f9f7	651	* CR TSEL2 LL_DAC_SetTriggerSource
<>	144:ef7eb2e8f9f7	652	* @param DACx DAC instance
<>	144:ef7eb2e8f9f7	653	* @param DAC_Channel This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	654	* @arg @ref LL_DAC_CHANNEL_1
<>	144:ef7eb2e8f9f7	655	* @arg @ref LL_DAC_CHANNEL_2
<>	144:ef7eb2e8f9f7	656	* @param TriggerSource This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	657	* @arg @ref LL_DAC_TRIG_SOFTWARE
<>	144:ef7eb2e8f9f7	658	* @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
<>	144:ef7eb2e8f9f7	659	* @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
<>	144:ef7eb2e8f9f7	660	* @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO
<>	144:ef7eb2e8f9f7	661	* @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
<>	144:ef7eb2e8f9f7	662	* @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
<>	144:ef7eb2e8f9f7	663	* @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO
<>	144:ef7eb2e8f9f7	664	* @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
<>	144:ef7eb2e8f9f7	665	* @retval None
<>	144:ef7eb2e8f9f7	666	*/
<>	144:ef7eb2e8f9f7	667	__STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
<>	144:ef7eb2e8f9f7	668	{
<>	144:ef7eb2e8f9f7	669	MODIFY_REG(DACx->CR,
<>	144:ef7eb2e8f9f7	670	DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
<>	144:ef7eb2e8f9f7	671	TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
<>	144:ef7eb2e8f9f7	672	}
<>	144:ef7eb2e8f9f7	673
<>	144:ef7eb2e8f9f7	674	/**
<>	144:ef7eb2e8f9f7	675	* @brief Get the conversion trigger source for the selected DAC channel.
<>	144:ef7eb2e8f9f7	676	* @note For conversion trigger source to be effective, DAC trigger
<>	144:ef7eb2e8f9f7	677	* must be enabled using function @ref LL_DAC_EnableTrigger().
<>	144:ef7eb2e8f9f7	678	* @note Availability of parameters of trigger sources from timer
<>	144:ef7eb2e8f9f7	679	* depends on timers availability on the selected device.
<>	144:ef7eb2e8f9f7	680	* @rmtoll CR TSEL1 LL_DAC_GetTriggerSource\n
<>	144:ef7eb2e8f9f7	681	* CR TSEL2 LL_DAC_GetTriggerSource
<>	144:ef7eb2e8f9f7	682	* @param DACx DAC instance
<>	144:ef7eb2e8f9f7	683	* @param DAC_Channel This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	684	* @arg @ref LL_DAC_CHANNEL_1
<>	144:ef7eb2e8f9f7	685	* @arg @ref LL_DAC_CHANNEL_2
<>	144:ef7eb2e8f9f7	686	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	687	* @arg @ref LL_DAC_TRIG_SOFTWARE
<>	144:ef7eb2e8f9f7	688	* @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
<>	144:ef7eb2e8f9f7	689	* @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
<>	144:ef7eb2e8f9f7	690	* @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO
<>	144:ef7eb2e8f9f7	691	* @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
<>	144:ef7eb2e8f9f7	692	* @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
<>	144:ef7eb2e8f9f7	693	* @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO
<>	144:ef7eb2e8f9f7	694	* @arg @ref LL_DAC_TRIGGER_EXT_IT9
<>	144:ef7eb2e8f9f7	695	*/
<>	144:ef7eb2e8f9f7	696	__STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<>	144:ef7eb2e8f9f7	697	{
<>	144:ef7eb2e8f9f7	698	return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
<>	144:ef7eb2e8f9f7	699	>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
<>	144:ef7eb2e8f9f7	700	);
<>	144:ef7eb2e8f9f7	701	}
<>	144:ef7eb2e8f9f7	702
<>	144:ef7eb2e8f9f7	703	/**
<>	144:ef7eb2e8f9f7	704	* @brief Set the waveform automatic generation mode
<>	144:ef7eb2e8f9f7	705	* for the selected DAC channel.
<>	144:ef7eb2e8f9f7	706	* @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration\n
<>	144:ef7eb2e8f9f7	707	* CR WAVE2 LL_DAC_SetWaveAutoGeneration
<>	144:ef7eb2e8f9f7	708	* @param DACx DAC instance
<>	144:ef7eb2e8f9f7	709	* @param DAC_Channel This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	710	* @arg @ref LL_DAC_CHANNEL_1
<>	144:ef7eb2e8f9f7	711	* @arg @ref LL_DAC_CHANNEL_2
<>	144:ef7eb2e8f9f7	712	* @param WaveAutoGeneration This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	713	* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
<>	144:ef7eb2e8f9f7	714	* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
<>	144:ef7eb2e8f9f7	715	* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
<>	144:ef7eb2e8f9f7	716	* @retval None
<>	144:ef7eb2e8f9f7	717	*/
<>	144:ef7eb2e8f9f7	718	__STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
<>	144:ef7eb2e8f9f7	719	{
<>	144:ef7eb2e8f9f7	720	MODIFY_REG(DACx->CR,
<>	144:ef7eb2e8f9f7	721	DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
<>	144:ef7eb2e8f9f7	722	WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
<>	144:ef7eb2e8f9f7	723	}
<>	144:ef7eb2e8f9f7	724
<>	144:ef7eb2e8f9f7	725	/**
<>	144:ef7eb2e8f9f7	726	* @brief Get the waveform automatic generation mode
<>	144:ef7eb2e8f9f7	727	* for the selected DAC channel.
<>	144:ef7eb2e8f9f7	728	* @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration\n
<>	144:ef7eb2e8f9f7	729	* CR WAVE2 LL_DAC_GetWaveAutoGeneration
<>	144:ef7eb2e8f9f7	730	* @param DACx DAC instance
<>	144:ef7eb2e8f9f7	731	* @param DAC_Channel This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	732	* @arg @ref LL_DAC_CHANNEL_1
<>	144:ef7eb2e8f9f7	733	* @arg @ref LL_DAC_CHANNEL_2
<>	144:ef7eb2e8f9f7	734	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	735	* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
<>	144:ef7eb2e8f9f7	736	* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
<>	144:ef7eb2e8f9f7	737	* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
<>	144:ef7eb2e8f9f7	738	*/
<>	144:ef7eb2e8f9f7	739	__STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<>	144:ef7eb2e8f9f7	740	{
<>	144:ef7eb2e8f9f7	741	return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
<>	144:ef7eb2e8f9f7	742	>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
<>	144:ef7eb2e8f9f7	743	);
<>	144:ef7eb2e8f9f7	744	}
<>	144:ef7eb2e8f9f7	745
<>	144:ef7eb2e8f9f7	746	/**
<>	144:ef7eb2e8f9f7	747	* @brief Set the noise waveform generation for the selected DAC channel:
<>	144:ef7eb2e8f9f7	748	* Noise mode and parameters LFSR (linear feedback shift register).
<>	144:ef7eb2e8f9f7	749	* @note For wave generation to be effective, DAC channel
<>	144:ef7eb2e8f9f7	750	* wave generation mode must be enabled using
<>	144:ef7eb2e8f9f7	751	* function @ref LL_DAC_SetWaveAutoGeneration().
<>	144:ef7eb2e8f9f7	752	* @note This setting can be set when the selected DAC channel is disabled
<>	144:ef7eb2e8f9f7	753	* (otherwise, the setting operation is ignored).
<>	144:ef7eb2e8f9f7	754	* @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR\n
<>	144:ef7eb2e8f9f7	755	* CR MAMP2 LL_DAC_SetWaveNoiseLFSR
<>	144:ef7eb2e8f9f7	756	* @param DACx DAC instance
<>	144:ef7eb2e8f9f7	757	* @param DAC_Channel This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	758	* @arg @ref LL_DAC_CHANNEL_1
<>	144:ef7eb2e8f9f7	759	* @arg @ref LL_DAC_CHANNEL_2
<>	144:ef7eb2e8f9f7	760	* @param NoiseLFSRMask This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	761	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
<>	144:ef7eb2e8f9f7	762	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
<>	144:ef7eb2e8f9f7	763	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
<>	144:ef7eb2e8f9f7	764	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
<>	144:ef7eb2e8f9f7	765	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
<>	144:ef7eb2e8f9f7	766	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
<>	144:ef7eb2e8f9f7	767	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
<>	144:ef7eb2e8f9f7	768	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
<>	144:ef7eb2e8f9f7	769	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
<>	144:ef7eb2e8f9f7	770	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
<>	144:ef7eb2e8f9f7	771	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
<>	144:ef7eb2e8f9f7	772	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
<>	144:ef7eb2e8f9f7	773	* @retval None
<>	144:ef7eb2e8f9f7	774	*/
<>	144:ef7eb2e8f9f7	775	__STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
<>	144:ef7eb2e8f9f7	776	{
<>	144:ef7eb2e8f9f7	777	MODIFY_REG(DACx->CR,
<>	144:ef7eb2e8f9f7	778	DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
<>	144:ef7eb2e8f9f7	779	NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
<>	144:ef7eb2e8f9f7	780	}
<>	144:ef7eb2e8f9f7	781
<>	144:ef7eb2e8f9f7	782	/**
<>	144:ef7eb2e8f9f7	783	* @brief Set the noise waveform generation for the selected DAC channel:
<>	144:ef7eb2e8f9f7	784	* Noise mode and parameters LFSR (linear feedback shift register).
<>	144:ef7eb2e8f9f7	785	* @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n
<>	144:ef7eb2e8f9f7	786	* CR MAMP2 LL_DAC_GetWaveNoiseLFSR
<>	144:ef7eb2e8f9f7	787	* @param DACx DAC instance
<>	144:ef7eb2e8f9f7	788	* @param DAC_Channel This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	789	* @arg @ref LL_DAC_CHANNEL_1
<>	144:ef7eb2e8f9f7	790	* @arg @ref LL_DAC_CHANNEL_2
<>	144:ef7eb2e8f9f7	791	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	792	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
<>	144:ef7eb2e8f9f7	793	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
<>	144:ef7eb2e8f9f7	794	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
<>	144:ef7eb2e8f9f7	795	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
<>	144:ef7eb2e8f9f7	796	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
<>	144:ef7eb2e8f9f7	797	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
<>	144:ef7eb2e8f9f7	798	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
<>	144:ef7eb2e8f9f7	799	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
<>	144:ef7eb2e8f9f7	800	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
<>	144:ef7eb2e8f9f7	801	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
<>	144:ef7eb2e8f9f7	802	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
<>	144:ef7eb2e8f9f7	803	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
<>	144:ef7eb2e8f9f7	804	*/
<>	144:ef7eb2e8f9f7	805	__STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<>	144:ef7eb2e8f9f7	806	{
<>	144:ef7eb2e8f9f7	807	return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
<>	144:ef7eb2e8f9f7	808	>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
<>	144:ef7eb2e8f9f7	809	);
<>	144:ef7eb2e8f9f7	810	}
<>	144:ef7eb2e8f9f7	811
<>	144:ef7eb2e8f9f7	812	/**
<>	144:ef7eb2e8f9f7	813	* @brief Set the triangle waveform generation for the selected DAC channel:
<>	144:ef7eb2e8f9f7	814	* triangle mode and amplitude.
<>	144:ef7eb2e8f9f7	815	* @note For wave generation to be effective, DAC channel
<>	144:ef7eb2e8f9f7	816	* wave generation mode must be enabled using
<>	144:ef7eb2e8f9f7	817	* function @ref LL_DAC_SetWaveAutoGeneration().
<>	144:ef7eb2e8f9f7	818	* @note This setting can be set when the selected DAC channel is disabled
<>	144:ef7eb2e8f9f7	819	* (otherwise, the setting operation is ignored).
<>	144:ef7eb2e8f9f7	820	* @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude\n
<>	144:ef7eb2e8f9f7	821	* CR MAMP2 LL_DAC_SetWaveTriangleAmplitude
<>	144:ef7eb2e8f9f7	822	* @param DACx DAC instance
<>	144:ef7eb2e8f9f7	823	* @param DAC_Channel This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	824	* @arg @ref LL_DAC_CHANNEL_1
<>	144:ef7eb2e8f9f7	825	* @arg @ref LL_DAC_CHANNEL_2
<>	144:ef7eb2e8f9f7	826	* @param TriangleAmplitude This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	827	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
<>	144:ef7eb2e8f9f7	828	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
<>	144:ef7eb2e8f9f7	829	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
<>	144:ef7eb2e8f9f7	830	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
<>	144:ef7eb2e8f9f7	831	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
<>	144:ef7eb2e8f9f7	832	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
<>	144:ef7eb2e8f9f7	833	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
<>	144:ef7eb2e8f9f7	834	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
<>	144:ef7eb2e8f9f7	835	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
<>	144:ef7eb2e8f9f7	836	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
<>	144:ef7eb2e8f9f7	837	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
<>	144:ef7eb2e8f9f7	838	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
<>	144:ef7eb2e8f9f7	839	* @retval None
<>	144:ef7eb2e8f9f7	840	*/
<>	144:ef7eb2e8f9f7	841	__STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriangleAmplitude)
<>	144:ef7eb2e8f9f7	842	{
<>	144:ef7eb2e8f9f7	843	MODIFY_REG(DACx->CR,
<>	144:ef7eb2e8f9f7	844	DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
<>	144:ef7eb2e8f9f7	845	TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
<>	144:ef7eb2e8f9f7	846	}
<>	144:ef7eb2e8f9f7	847
<>	144:ef7eb2e8f9f7	848	/**
<>	144:ef7eb2e8f9f7	849	* @brief Set the triangle waveform generation for the selected DAC channel:
<>	144:ef7eb2e8f9f7	850	* triangle mode and amplitude.
<>	144:ef7eb2e8f9f7	851	* @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n
<>	144:ef7eb2e8f9f7	852	* CR MAMP2 LL_DAC_GetWaveTriangleAmplitude
<>	144:ef7eb2e8f9f7	853	* @param DACx DAC instance
<>	144:ef7eb2e8f9f7	854	* @param DAC_Channel This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	855	* @arg @ref LL_DAC_CHANNEL_1
<>	144:ef7eb2e8f9f7	856	* @arg @ref LL_DAC_CHANNEL_2
<>	144:ef7eb2e8f9f7	857	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	858	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
<>	144:ef7eb2e8f9f7	859	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
<>	144:ef7eb2e8f9f7	860	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
<>	144:ef7eb2e8f9f7	861	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
<>	144:ef7eb2e8f9f7	862	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
<>	144:ef7eb2e8f9f7	863	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
<>	144:ef7eb2e8f9f7	864	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
<>	144:ef7eb2e8f9f7	865	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
<>	144:ef7eb2e8f9f7	866	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
<>	144:ef7eb2e8f9f7	867	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
<>	144:ef7eb2e8f9f7	868	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
<>	144:ef7eb2e8f9f7	869	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
<>	144:ef7eb2e8f9f7	870	*/
<>	144:ef7eb2e8f9f7	871	__STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<>	144:ef7eb2e8f9f7	872	{
<>	144:ef7eb2e8f9f7	873	return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
<>	144:ef7eb2e8f9f7	874	>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
<>	144:ef7eb2e8f9f7	875	);
<>	144:ef7eb2e8f9f7	876	}
<>	144:ef7eb2e8f9f7	877
<>	144:ef7eb2e8f9f7	878	/**
<>	144:ef7eb2e8f9f7	879	* @brief Set the output for the selected DAC channel.
<>	144:ef7eb2e8f9f7	880	* @note This function set several features:
<>	144:ef7eb2e8f9f7	881	* - mode normal or sample-and-hold
<>	144:ef7eb2e8f9f7	882	* - buffer
<>	144:ef7eb2e8f9f7	883	* - connection to GPIO or internal path.
<>	144:ef7eb2e8f9f7	884	* These features can also be set individually using
<>	144:ef7eb2e8f9f7	885	* dedicated functions:
<>	144:ef7eb2e8f9f7	886	* - @ref LL_DAC_SetOutputBuffer()
<>	144:ef7eb2e8f9f7	887	* - @ref LL_DAC_SetOutputMode()
<>	144:ef7eb2e8f9f7	888	* - @ref LL_DAC_SetOutputConnection()
<>	144:ef7eb2e8f9f7	889	* @note On this STM32 serie, output connection depends on output mode
<>	144:ef7eb2e8f9f7	890	* (normal or sample and hold) and output buffer state.
<>	144:ef7eb2e8f9f7	891	* - if output connection is set to internal path and output buffer
<>	144:ef7eb2e8f9f7	892	* is enabled (whatever output mode):
<>	144:ef7eb2e8f9f7	893	* output connection is also connected to GPIO pin
<>	144:ef7eb2e8f9f7	894	* (both connections to GPIO pin and internal path).
<>	144:ef7eb2e8f9f7	895	* - if output connection is set to GPIO pin, output buffer
<>	144:ef7eb2e8f9f7	896	* is disabled, output mode set to sample and hold:
<>	144:ef7eb2e8f9f7	897	* output connection is also connected to internal path
<>	144:ef7eb2e8f9f7	898	* (both connections to GPIO pin and internal path).
<>	144:ef7eb2e8f9f7	899	* @note Mode sample-and-hold requires an external capacitor
<>	144:ef7eb2e8f9f7	900	* to be connected between DAC channel output and ground.
<>	144:ef7eb2e8f9f7	901	* Capacitor value depends on load on DAC channel output and
<>	144:ef7eb2e8f9f7	902	* sample-and-hold timings configured.
<>	144:ef7eb2e8f9f7	903	* As indication, capacitor typical value is 100nF
<>	144:ef7eb2e8f9f7	904	* (refer to device datasheet, parameter "CSH").
<>	144:ef7eb2e8f9f7	905	* @rmtoll CR MODE1 LL_DAC_ConfigOutput\n
<>	144:ef7eb2e8f9f7	906	* CR MODE2 LL_DAC_ConfigOutput
<>	144:ef7eb2e8f9f7	907	* @param DACx DAC instance
<>	144:ef7eb2e8f9f7	908	* @param DAC_Channel This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	909	* @arg @ref LL_DAC_CHANNEL_1
<>	144:ef7eb2e8f9f7	910	* @arg @ref LL_DAC_CHANNEL_2
<>	144:ef7eb2e8f9f7	911	* @param OutputMode This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	912	* @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
<>	144:ef7eb2e8f9f7	913	* @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
<>	144:ef7eb2e8f9f7	914	* @param OutputBuffer This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	915	* @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
<>	144:ef7eb2e8f9f7	916	* @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
<>	144:ef7eb2e8f9f7	917	* @param OutputConnection This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	918	* @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
<>	144:ef7eb2e8f9f7	919	* @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
<>	144:ef7eb2e8f9f7	920	* @retval None
<>	144:ef7eb2e8f9f7	921	*/
<>	144:ef7eb2e8f9f7	922	__STATIC_INLINE void LL_DAC_ConfigOutput(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode, uint32_t OutputBuffer, uint32_t OutputConnection)
<>	144:ef7eb2e8f9f7	923	{
<>	144:ef7eb2e8f9f7	924	MODIFY_REG(DACx->MCR,
<>	144:ef7eb2e8f9f7	925	(DAC_MCR_MODE1_2 \| DAC_MCR_MODE1_1 \| DAC_MCR_MODE1_0) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
<>	144:ef7eb2e8f9f7	926	(OutputMode \| OutputBuffer \| OutputConnection) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
<>	144:ef7eb2e8f9f7	927	}
<>	144:ef7eb2e8f9f7	928
<>	144:ef7eb2e8f9f7	929	/**
<>	144:ef7eb2e8f9f7	930	* @brief Set the output mode normal or sample-and-hold
<>	144:ef7eb2e8f9f7	931	* for the selected DAC channel.
<>	144:ef7eb2e8f9f7	932	* @note Mode sample-and-hold requires an external capacitor
<>	144:ef7eb2e8f9f7	933	* to be connected between DAC channel output and ground.
<>	144:ef7eb2e8f9f7	934	* Capacitor value depends on load on DAC channel output and
<>	144:ef7eb2e8f9f7	935	* sample-and-hold timings configured.
<>	144:ef7eb2e8f9f7	936	* As indication, capacitor typical value is 100nF
<>	144:ef7eb2e8f9f7	937	* (refer to device datasheet, parameter "CSH").
<>	144:ef7eb2e8f9f7	938	* @rmtoll CR MODE1 LL_DAC_SetOutputMode\n
<>	144:ef7eb2e8f9f7	939	* CR MODE2 LL_DAC_SetOutputMode
<>	144:ef7eb2e8f9f7	940	* @param DACx DAC instance
<>	144:ef7eb2e8f9f7	941	* @param DAC_Channel This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	942	* @arg @ref LL_DAC_CHANNEL_1
<>	144:ef7eb2e8f9f7	943	* @arg @ref LL_DAC_CHANNEL_2
<>	144:ef7eb2e8f9f7	944	* @param OutputMode This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	945	* @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
<>	144:ef7eb2e8f9f7	946	* @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
<>	144:ef7eb2e8f9f7	947	* @retval None
<>	144:ef7eb2e8f9f7	948	*/
<>	144:ef7eb2e8f9f7	949	__STATIC_INLINE void LL_DAC_SetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode)
<>	144:ef7eb2e8f9f7	950	{
<>	144:ef7eb2e8f9f7	951	MODIFY_REG(DACx->MCR,
<>	144:ef7eb2e8f9f7	952	DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
<>	144:ef7eb2e8f9f7	953	OutputMode << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
<>	144:ef7eb2e8f9f7	954	}
<>	144:ef7eb2e8f9f7	955
<>	144:ef7eb2e8f9f7	956	/**
<>	144:ef7eb2e8f9f7	957	* @brief Get the output mode normal or sample-and-hold for the selected DAC channel.
<>	144:ef7eb2e8f9f7	958	* @rmtoll CR MODE1 LL_DAC_GetOutputMode\n
<>	144:ef7eb2e8f9f7	959	* CR MODE2 LL_DAC_GetOutputMode
<>	144:ef7eb2e8f9f7	960	* @param DACx DAC instance
<>	144:ef7eb2e8f9f7	961	* @param DAC_Channel This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	962	* @arg @ref LL_DAC_CHANNEL_1
<>	144:ef7eb2e8f9f7	963	* @arg @ref LL_DAC_CHANNEL_2
<>	144:ef7eb2e8f9f7	964	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	965	* @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
<>	144:ef7eb2e8f9f7	966	* @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
<>	144:ef7eb2e8f9f7	967	*/
<>	144:ef7eb2e8f9f7	968	__STATIC_INLINE uint32_t LL_DAC_GetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<>	144:ef7eb2e8f9f7	969	{
<>	144:ef7eb2e8f9f7	970	return (uint32_t)(READ_BIT(DACx->MCR, DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
<>	144:ef7eb2e8f9f7	971	>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
<>	144:ef7eb2e8f9f7	972	);
<>	144:ef7eb2e8f9f7	973	}
<>	144:ef7eb2e8f9f7	974
<>	144:ef7eb2e8f9f7	975	/**
<>	144:ef7eb2e8f9f7	976	* @brief Set the output buffer for the selected DAC channel.
<>	144:ef7eb2e8f9f7	977	* @note On this STM32 serie, when buffer is enabled, its offset can be
<>	144:ef7eb2e8f9f7	978	* trimmed: factory calibration default values can be
<>	144:ef7eb2e8f9f7	979	* replaced by user trimming values, using function
<>	144:ef7eb2e8f9f7	980	* @ref LL_DAC_SetTrimmingValue().
<>	144:ef7eb2e8f9f7	981	* @rmtoll CR MODE1 LL_DAC_SetOutputBuffer\n
<>	144:ef7eb2e8f9f7	982	* CR MODE2 LL_DAC_SetOutputBuffer
<>	144:ef7eb2e8f9f7	983	* @param DACx DAC instance
<>	144:ef7eb2e8f9f7	984	* @param DAC_Channel This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	985	* @arg @ref LL_DAC_CHANNEL_1
<>	144:ef7eb2e8f9f7	986	* @arg @ref LL_DAC_CHANNEL_2
<>	144:ef7eb2e8f9f7	987	* @param OutputBuffer This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	988	* @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
<>	144:ef7eb2e8f9f7	989	* @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
<>	144:ef7eb2e8f9f7	990	* @retval None
<>	144:ef7eb2e8f9f7	991	*/
<>	144:ef7eb2e8f9f7	992	__STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
<>	144:ef7eb2e8f9f7	993	{
<>	144:ef7eb2e8f9f7	994	MODIFY_REG(DACx->MCR,
<>	144:ef7eb2e8f9f7	995	DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
<>	144:ef7eb2e8f9f7	996	OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
<>	144:ef7eb2e8f9f7	997	}
<>	144:ef7eb2e8f9f7	998
<>	144:ef7eb2e8f9f7	999	/**
<>	144:ef7eb2e8f9f7	1000	* @brief Get the output buffer state for the selected DAC channel.
<>	144:ef7eb2e8f9f7	1001	* @rmtoll CR MODE1 LL_DAC_GetOutputBuffer\n
<>	144:ef7eb2e8f9f7	1002	* CR MODE2 LL_DAC_GetOutputBuffer
<>	144:ef7eb2e8f9f7	1003	* @param DACx DAC instance
<>	144:ef7eb2e8f9f7	1004	* @param DAC_Channel This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1005	* @arg @ref LL_DAC_CHANNEL_1
<>	144:ef7eb2e8f9f7	1006	* @arg @ref LL_DAC_CHANNEL_2
<>	144:ef7eb2e8f9f7	1007	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	1008	* @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
<>	144:ef7eb2e8f9f7	1009	* @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
<>	144:ef7eb2e8f9f7	1010	*/
<>	144:ef7eb2e8f9f7	1011	__STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<>	144:ef7eb2e8f9f7	1012	{
<>	144:ef7eb2e8f9f7	1013	return (uint32_t)(READ_BIT(DACx->MCR, DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
<>	144:ef7eb2e8f9f7	1014	>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
<>	144:ef7eb2e8f9f7	1015	);
<>	144:ef7eb2e8f9f7	1016	}
<>	144:ef7eb2e8f9f7	1017
<>	144:ef7eb2e8f9f7	1018	/**
<>	144:ef7eb2e8f9f7	1019	* @brief Set the output connection for the selected DAC channel.
<>	144:ef7eb2e8f9f7	1020	* @note On this STM32 serie, output connection depends on output mode (normal or
<>	144:ef7eb2e8f9f7	1021	* sample and hold) and output buffer state.
<>	144:ef7eb2e8f9f7	1022	* - if output connection is set to internal path and output buffer
<>	144:ef7eb2e8f9f7	1023	* is enabled (whatever output mode):
<>	144:ef7eb2e8f9f7	1024	* output connection is also connected to GPIO pin
<>	144:ef7eb2e8f9f7	1025	* (both connections to GPIO pin and internal path).
<>	144:ef7eb2e8f9f7	1026	* - if output connection is set to GPIO pin, output buffer
<>	144:ef7eb2e8f9f7	1027	* is disabled, output mode set to sample and hold:
<>	144:ef7eb2e8f9f7	1028	* output connection is also connected to internal path
<>	144:ef7eb2e8f9f7	1029	* (both connections to GPIO pin and internal path).
<>	144:ef7eb2e8f9f7	1030	* @rmtoll CR MODE1 LL_DAC_SetOutputConnection\n
<>	144:ef7eb2e8f9f7	1031	* CR MODE2 LL_DAC_SetOutputConnection
<>	144:ef7eb2e8f9f7	1032	* @param DACx DAC instance
<>	144:ef7eb2e8f9f7	1033	* @param DAC_Channel This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1034	* @arg @ref LL_DAC_CHANNEL_1
<>	144:ef7eb2e8f9f7	1035	* @arg @ref LL_DAC_CHANNEL_2
<>	144:ef7eb2e8f9f7	1036	* @param OutputConnection This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1037	* @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
<>	144:ef7eb2e8f9f7	1038	* @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
<>	144:ef7eb2e8f9f7	1039	* @retval None
<>	144:ef7eb2e8f9f7	1040	*/
<>	144:ef7eb2e8f9f7	1041	__STATIC_INLINE void LL_DAC_SetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputConnection)
<>	144:ef7eb2e8f9f7	1042	{
<>	144:ef7eb2e8f9f7	1043	MODIFY_REG(DACx->MCR,
<>	144:ef7eb2e8f9f7	1044	DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
<>	144:ef7eb2e8f9f7	1045	OutputConnection << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
<>	144:ef7eb2e8f9f7	1046	}
<>	144:ef7eb2e8f9f7	1047
<>	144:ef7eb2e8f9f7	1048	/**
<>	144:ef7eb2e8f9f7	1049	* @brief Get the output connection for the selected DAC channel.
<>	144:ef7eb2e8f9f7	1050	* @note On this STM32 serie, output connection depends on output mode (normal or
<>	144:ef7eb2e8f9f7	1051	* sample and hold) and output buffer state.
<>	144:ef7eb2e8f9f7	1052	* - if output connection is set to internal path and output buffer
<>	144:ef7eb2e8f9f7	1053	* is enabled (whatever output mode):
<>	144:ef7eb2e8f9f7	1054	* output connection is also connected to GPIO pin
<>	144:ef7eb2e8f9f7	1055	* (both connections to GPIO pin and internal path).
<>	144:ef7eb2e8f9f7	1056	* - if output connection is set to GPIO pin, output buffer
<>	144:ef7eb2e8f9f7	1057	* is disabled, output mode set to sample and hold:
<>	144:ef7eb2e8f9f7	1058	* output connection is also connected to internal path
<>	144:ef7eb2e8f9f7	1059	* (both connections to GPIO pin and internal path).
<>	144:ef7eb2e8f9f7	1060	* @rmtoll CR MODE1 LL_DAC_GetOutputConnection\n
<>	144:ef7eb2e8f9f7	1061	* CR MODE2 LL_DAC_GetOutputConnection
<>	144:ef7eb2e8f9f7	1062	* @param DACx DAC instance
<>	144:ef7eb2e8f9f7	1063	* @param DAC_Channel This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1064	* @arg @ref LL_DAC_CHANNEL_1
<>	144:ef7eb2e8f9f7	1065	* @arg @ref LL_DAC_CHANNEL_2
<>	144:ef7eb2e8f9f7	1066	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	1067	* @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
<>	144:ef7eb2e8f9f7	1068	* @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
<>	144:ef7eb2e8f9f7	1069	*/
<>	144:ef7eb2e8f9f7	1070	__STATIC_INLINE uint32_t LL_DAC_GetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<>	144:ef7eb2e8f9f7	1071	{
<>	144:ef7eb2e8f9f7	1072	return (uint32_t)(READ_BIT(DACx->MCR, DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
<>	144:ef7eb2e8f9f7	1073	>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
<>	144:ef7eb2e8f9f7	1074	);
<>	144:ef7eb2e8f9f7	1075	}
<>	144:ef7eb2e8f9f7	1076
<>	144:ef7eb2e8f9f7	1077	/**
<>	144:ef7eb2e8f9f7	1078	* @brief Set the sample-and-hold timing for the selected DAC channel:
<>	144:ef7eb2e8f9f7	1079	* sample time
<>	144:ef7eb2e8f9f7	1080	* @note Sample time must be set when DAC channel is disabled
<>	144:ef7eb2e8f9f7	1081	* or during DAC operation when DAC channel flag BWSTx is reset,
<>	144:ef7eb2e8f9f7	1082	* otherwise the setting is ignored.
<>	144:ef7eb2e8f9f7	1083	* Check BWSTx flag state using function "LL_DAC_IsActiveFlag_BWSTx()".
<>	144:ef7eb2e8f9f7	1084	* @rmtoll SHSR1 TSAMPLE1 LL_DAC_SetSampleAndHoldSampleTime\n
<>	144:ef7eb2e8f9f7	1085	* SHSR2 TSAMPLE2 LL_DAC_SetSampleAndHoldSampleTime
<>	144:ef7eb2e8f9f7	1086	* @param DACx DAC instance
<>	144:ef7eb2e8f9f7	1087	* @param DAC_Channel This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1088	* @arg @ref LL_DAC_CHANNEL_1
<>	144:ef7eb2e8f9f7	1089	* @arg @ref LL_DAC_CHANNEL_2
<>	144:ef7eb2e8f9f7	1090	* @param SampleTime Value between Min_Data=0x000 and Max_Data=0x3FF
<>	144:ef7eb2e8f9f7	1091	* @retval None
<>	144:ef7eb2e8f9f7	1092	*/
<>	144:ef7eb2e8f9f7	1093	__STATIC_INLINE void LL_DAC_SetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t SampleTime)
<>	144:ef7eb2e8f9f7	1094	{
<>	144:ef7eb2e8f9f7	1095	register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_SHSRX_REGOFFSET_MASK));
<>	144:ef7eb2e8f9f7	1096
<>	144:ef7eb2e8f9f7	1097	MODIFY_REG(*preg,
<>	144:ef7eb2e8f9f7	1098	DAC_SHSR1_TSAMPLE1,
<>	144:ef7eb2e8f9f7	1099	SampleTime);
<>	144:ef7eb2e8f9f7	1100	}
<>	144:ef7eb2e8f9f7	1101
<>	144:ef7eb2e8f9f7	1102	/**
<>	144:ef7eb2e8f9f7	1103	* @brief Get the sample-and-hold timing for the selected DAC channel:
<>	144:ef7eb2e8f9f7	1104	* sample time
<>	144:ef7eb2e8f9f7	1105	* @rmtoll SHSR1 TSAMPLE1 LL_DAC_GetSampleAndHoldSampleTime\n
<>	144:ef7eb2e8f9f7	1106	* SHSR2 TSAMPLE2 LL_DAC_GetSampleAndHoldSampleTime
<>	144:ef7eb2e8f9f7	1107	* @param DACx DAC instance
<>	144:ef7eb2e8f9f7	1108	* @param DAC_Channel This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1109	* @arg @ref LL_DAC_CHANNEL_1
<>	144:ef7eb2e8f9f7	1110	* @arg @ref LL_DAC_CHANNEL_2
<>	144:ef7eb2e8f9f7	1111	* @retval Value between Min_Data=0x000 and Max_Data=0x3FF
<>	144:ef7eb2e8f9f7	1112	*/
<>	144:ef7eb2e8f9f7	1113	__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<>	144:ef7eb2e8f9f7	1114	{
<>	144:ef7eb2e8f9f7	1115	register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_SHSRX_REGOFFSET_MASK));
<>	144:ef7eb2e8f9f7	1116
<>	144:ef7eb2e8f9f7	1117	return (uint32_t) READ_BIT(*preg, DAC_SHSR1_TSAMPLE1);
<>	144:ef7eb2e8f9f7	1118	}
<>	144:ef7eb2e8f9f7	1119
<>	144:ef7eb2e8f9f7	1120	/**
<>	144:ef7eb2e8f9f7	1121	* @brief Set the sample-and-hold timing for the selected DAC channel:
<>	144:ef7eb2e8f9f7	1122	* hold time
<>	144:ef7eb2e8f9f7	1123	* @rmtoll SHHR THOLD1 LL_DAC_SetSampleAndHoldHoldTime\n
<>	144:ef7eb2e8f9f7	1124	* SHHR THOLD2 LL_DAC_SetSampleAndHoldHoldTime
<>	144:ef7eb2e8f9f7	1125	* @param DACx DAC instance
<>	144:ef7eb2e8f9f7	1126	* @param DAC_Channel This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1127	* @arg @ref LL_DAC_CHANNEL_1
<>	144:ef7eb2e8f9f7	1128	* @arg @ref LL_DAC_CHANNEL_2
<>	144:ef7eb2e8f9f7	1129	* @param HoldTime Value between Min_Data=0x000 and Max_Data=0x3FF
<>	144:ef7eb2e8f9f7	1130	* @retval None
<>	144:ef7eb2e8f9f7	1131	*/
<>	144:ef7eb2e8f9f7	1132	__STATIC_INLINE void LL_DAC_SetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t HoldTime)
<>	144:ef7eb2e8f9f7	1133	{
<>	144:ef7eb2e8f9f7	1134	MODIFY_REG(DACx->SHHR,
<>	144:ef7eb2e8f9f7	1135	DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
<>	144:ef7eb2e8f9f7	1136	HoldTime << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
<>	144:ef7eb2e8f9f7	1137	}
<>	144:ef7eb2e8f9f7	1138
<>	144:ef7eb2e8f9f7	1139	/**
<>	144:ef7eb2e8f9f7	1140	* @brief Get the sample-and-hold timing for the selected DAC channel:
<>	144:ef7eb2e8f9f7	1141	* hold time
<>	144:ef7eb2e8f9f7	1142	* @rmtoll SHHR THOLD1 LL_DAC_GetSampleAndHoldHoldTime\n
<>	144:ef7eb2e8f9f7	1143	* SHHR THOLD2 LL_DAC_GetSampleAndHoldHoldTime
<>	144:ef7eb2e8f9f7	1144	* @param DACx DAC instance
<>	144:ef7eb2e8f9f7	1145	* @param DAC_Channel This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1146	* @arg @ref LL_DAC_CHANNEL_1
<>	144:ef7eb2e8f9f7	1147	* @arg @ref LL_DAC_CHANNEL_2
<>	144:ef7eb2e8f9f7	1148	* @retval Value between Min_Data=0x000 and Max_Data=0x3FF
<>	144:ef7eb2e8f9f7	1149	*/
<>	144:ef7eb2e8f9f7	1150	__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<>	144:ef7eb2e8f9f7	1151	{
<>	144:ef7eb2e8f9f7	1152	return (uint32_t)(READ_BIT(DACx->SHHR, DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
<>	144:ef7eb2e8f9f7	1153	>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
<>	144:ef7eb2e8f9f7	1154	);
<>	144:ef7eb2e8f9f7	1155	}
<>	144:ef7eb2e8f9f7	1156
<>	144:ef7eb2e8f9f7	1157	/**
<>	144:ef7eb2e8f9f7	1158	* @brief Set the sample-and-hold timing for the selected DAC channel:
<>	144:ef7eb2e8f9f7	1159	* refresh time
<>	144:ef7eb2e8f9f7	1160	* @rmtoll SHRR TREFRESH1 LL_DAC_SetSampleAndHoldRefreshTime\n
<>	144:ef7eb2e8f9f7	1161	* SHRR TREFRESH2 LL_DAC_SetSampleAndHoldRefreshTime
<>	144:ef7eb2e8f9f7	1162	* @param DACx DAC instance
<>	144:ef7eb2e8f9f7	1163	* @param DAC_Channel This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1164	* @arg @ref LL_DAC_CHANNEL_1
<>	144:ef7eb2e8f9f7	1165	* @arg @ref LL_DAC_CHANNEL_2
<>	144:ef7eb2e8f9f7	1166	* @param RefreshTime Value between Min_Data=0x00 and Max_Data=0xFF
<>	144:ef7eb2e8f9f7	1167	* @retval None
<>	144:ef7eb2e8f9f7	1168	*/
<>	144:ef7eb2e8f9f7	1169	__STATIC_INLINE void LL_DAC_SetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t RefreshTime)
<>	144:ef7eb2e8f9f7	1170	{
<>	144:ef7eb2e8f9f7	1171	MODIFY_REG(DACx->SHRR,
<>	144:ef7eb2e8f9f7	1172	DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
<>	144:ef7eb2e8f9f7	1173	RefreshTime << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
<>	144:ef7eb2e8f9f7	1174	}
<>	144:ef7eb2e8f9f7	1175
<>	144:ef7eb2e8f9f7	1176	/**
<>	144:ef7eb2e8f9f7	1177	* @brief Get the sample-and-hold timing for the selected DAC channel:
<>	144:ef7eb2e8f9f7	1178	* refresh time
<>	144:ef7eb2e8f9f7	1179	* @rmtoll SHRR TREFRESH1 LL_DAC_GetSampleAndHoldRefreshTime\n
<>	144:ef7eb2e8f9f7	1180	* SHRR TREFRESH2 LL_DAC_GetSampleAndHoldRefreshTime
<>	144:ef7eb2e8f9f7	1181	* @param DACx DAC instance
<>	144:ef7eb2e8f9f7	1182	* @param DAC_Channel This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1183	* @arg @ref LL_DAC_CHANNEL_1
<>	144:ef7eb2e8f9f7	1184	* @arg @ref LL_DAC_CHANNEL_2
<>	144:ef7eb2e8f9f7	1185	* @retval Value between Min_Data=0x00 and Max_Data=0xFF
<>	144:ef7eb2e8f9f7	1186	*/
<>	144:ef7eb2e8f9f7	1187	__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<>	144:ef7eb2e8f9f7	1188	{
<>	144:ef7eb2e8f9f7	1189	return (uint32_t)(READ_BIT(DACx->SHRR, DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
<>	144:ef7eb2e8f9f7	1190	>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
<>	144:ef7eb2e8f9f7	1191	);
<>	144:ef7eb2e8f9f7	1192	}
<>	144:ef7eb2e8f9f7	1193
<>	144:ef7eb2e8f9f7	1194	/**
<>	144:ef7eb2e8f9f7	1195	* @}
<>	144:ef7eb2e8f9f7	1196	*/
<>	144:ef7eb2e8f9f7	1197
<>	144:ef7eb2e8f9f7	1198	/** @defgroup DAC_LL_EF_Configuration_Legacy_Functions DAC configuration, legacy functions name
<>	144:ef7eb2e8f9f7	1199	* @{
<>	144:ef7eb2e8f9f7	1200	*/
<>	144:ef7eb2e8f9f7	1201	/* Old functions name kept for legacy purpose, to be replaced by the */
<>	144:ef7eb2e8f9f7	1202	/* current functions name. */
<>	144:ef7eb2e8f9f7	1203	__STATIC_INLINE void LL_DAC_SetWaveMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveMode)
<>	144:ef7eb2e8f9f7	1204	{
<>	144:ef7eb2e8f9f7	1205	LL_DAC_SetWaveAutoGeneration(DACx, DAC_Channel, WaveMode);
<>	144:ef7eb2e8f9f7	1206	}
<>	144:ef7eb2e8f9f7	1207	__STATIC_INLINE uint32_t LL_DAC_GetWaveMode(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<>	144:ef7eb2e8f9f7	1208	{
<>	144:ef7eb2e8f9f7	1209	return LL_DAC_GetWaveAutoGeneration(DACx, DAC_Channel);
<>	144:ef7eb2e8f9f7	1210	}
<>	144:ef7eb2e8f9f7	1211
<>	144:ef7eb2e8f9f7	1212	/**
<>	144:ef7eb2e8f9f7	1213	* @}
<>	144:ef7eb2e8f9f7	1214	*/
<>	144:ef7eb2e8f9f7	1215
<>	144:ef7eb2e8f9f7	1216	/** @defgroup DAC_LL_EF_DMA_Management DMA Management
<>	144:ef7eb2e8f9f7	1217	* @{
<>	144:ef7eb2e8f9f7	1218	*/
<>	144:ef7eb2e8f9f7	1219
<>	144:ef7eb2e8f9f7	1220	/**
<>	144:ef7eb2e8f9f7	1221	* @brief Enable DAC DMA transfer request of the selected channel.
<>	144:ef7eb2e8f9f7	1222	* @note To configure DMA source address (peripheral address),
<>	144:ef7eb2e8f9f7	1223	* use function @ref LL_DAC_DMA_GetRegAddr().
<>	144:ef7eb2e8f9f7	1224	* @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq\n
<>	144:ef7eb2e8f9f7	1225	* CR DMAEN2 LL_DAC_EnableDMAReq
<>	144:ef7eb2e8f9f7	1226	* @param DACx DAC instance
<>	144:ef7eb2e8f9f7	1227	* @param DAC_Channel This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1228	* @arg @ref LL_DAC_CHANNEL_1
<>	144:ef7eb2e8f9f7	1229	* @arg @ref LL_DAC_CHANNEL_2
<>	144:ef7eb2e8f9f7	1230	* @retval None
<>	144:ef7eb2e8f9f7	1231	*/
<>	144:ef7eb2e8f9f7	1232	__STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<>	144:ef7eb2e8f9f7	1233	{
<>	144:ef7eb2e8f9f7	1234	SET_BIT(DACx->CR,
<>	144:ef7eb2e8f9f7	1235	DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
<>	144:ef7eb2e8f9f7	1236	}
<>	144:ef7eb2e8f9f7	1237
<>	144:ef7eb2e8f9f7	1238	/**
<>	144:ef7eb2e8f9f7	1239	* @brief Disable DAC DMA transfer request of the selected channel.
<>	144:ef7eb2e8f9f7	1240	* @note To configure DMA source address (peripheral address),
<>	144:ef7eb2e8f9f7	1241	* use function @ref LL_DAC_DMA_GetRegAddr().
<>	144:ef7eb2e8f9f7	1242	* @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq\n
<>	144:ef7eb2e8f9f7	1243	* CR DMAEN2 LL_DAC_DisableDMAReq
<>	144:ef7eb2e8f9f7	1244	* @param DACx DAC instance
<>	144:ef7eb2e8f9f7	1245	* @param DAC_Channel This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1246	* @arg @ref LL_DAC_CHANNEL_1
<>	144:ef7eb2e8f9f7	1247	* @arg @ref LL_DAC_CHANNEL_2
<>	144:ef7eb2e8f9f7	1248	* @retval None
<>	144:ef7eb2e8f9f7	1249	*/
<>	144:ef7eb2e8f9f7	1250	__STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<>	144:ef7eb2e8f9f7	1251	{
<>	144:ef7eb2e8f9f7	1252	CLEAR_BIT(DACx->CR,
<>	144:ef7eb2e8f9f7	1253	DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
<>	144:ef7eb2e8f9f7	1254	}
<>	144:ef7eb2e8f9f7	1255
<>	144:ef7eb2e8f9f7	1256	/**
<>	144:ef7eb2e8f9f7	1257	* @brief Get DAC DMA transfer request state of the selected channel.
<>	144:ef7eb2e8f9f7	1258	* (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled)
<>	144:ef7eb2e8f9f7	1259	* @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled\n
<>	144:ef7eb2e8f9f7	1260	* CR DMAEN2 LL_DAC_IsDMAReqEnabled
<>	144:ef7eb2e8f9f7	1261	* @param DACx DAC instance
<>	144:ef7eb2e8f9f7	1262	* @param DAC_Channel This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1263	* @arg @ref LL_DAC_CHANNEL_1
<>	144:ef7eb2e8f9f7	1264	* @arg @ref LL_DAC_CHANNEL_2
<>	144:ef7eb2e8f9f7	1265	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	1266	*/
<>	144:ef7eb2e8f9f7	1267	__STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<>	144:ef7eb2e8f9f7	1268	{
<>	144:ef7eb2e8f9f7	1269	return (READ_BIT(DACx->CR,
<>	144:ef7eb2e8f9f7	1270	DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
<>	144:ef7eb2e8f9f7	1271	== (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
<>	144:ef7eb2e8f9f7	1272	}
<>	144:ef7eb2e8f9f7	1273
<>	144:ef7eb2e8f9f7	1274	/**
<>	144:ef7eb2e8f9f7	1275	* @brief Function to help to configure DMA transfer to DAC: retrieve the
<>	144:ef7eb2e8f9f7	1276	* DAC register address from DAC instance and a list of DAC registers
<>	144:ef7eb2e8f9f7	1277	* intended to be used (most commonly) with DMA transfer.
<>	144:ef7eb2e8f9f7	1278	* @note These DAC registers are data holding registers:
<>	144:ef7eb2e8f9f7	1279	* when DAC conversion is requested, DAC generates a DMA transfer
<>	144:ef7eb2e8f9f7	1280	* request to have data available in DAC data holding registers.
<>	144:ef7eb2e8f9f7	1281	* @note This macro is intended to be used with LL DMA driver, refer to
<>	144:ef7eb2e8f9f7	1282	* function "LL_DMA_ConfigAddresses()".
<>	144:ef7eb2e8f9f7	1283	* Example:
<>	144:ef7eb2e8f9f7	1284	* LL_DMA_ConfigAddresses(DMA1,
<>	144:ef7eb2e8f9f7	1285	* LL_DMA_CHANNEL_1,
<>	144:ef7eb2e8f9f7	1286	* (uint32_t)&< array or variable >,
<>	144:ef7eb2e8f9f7	1287	* LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
<>	144:ef7eb2e8f9f7	1288	* LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
<>	144:ef7eb2e8f9f7	1289	* @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
<>	144:ef7eb2e8f9f7	1290	* DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
<>	144:ef7eb2e8f9f7	1291	* DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
<>	144:ef7eb2e8f9f7	1292	* DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
<>	144:ef7eb2e8f9f7	1293	* DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
<>	144:ef7eb2e8f9f7	1294	* DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr
<>	144:ef7eb2e8f9f7	1295	* @param DACx DAC instance
<>	144:ef7eb2e8f9f7	1296	* @param DAC_Channel This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1297	* @arg @ref LL_DAC_CHANNEL_1
<>	144:ef7eb2e8f9f7	1298	* @arg @ref LL_DAC_CHANNEL_2
<>	144:ef7eb2e8f9f7	1299	* @param Register This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1300	* @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
<>	144:ef7eb2e8f9f7	1301	* @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED
<>	144:ef7eb2e8f9f7	1302	* @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
<>	144:ef7eb2e8f9f7	1303	* @retval DAC register address
<>	144:ef7eb2e8f9f7	1304	*/
<>	144:ef7eb2e8f9f7	1305	__STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
<>	144:ef7eb2e8f9f7	1306	{
<>	144:ef7eb2e8f9f7	1307	/* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */
<>	144:ef7eb2e8f9f7	1308	/* DAC channel selected. */
<>	144:ef7eb2e8f9f7	1309	return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, Register))));
<>	144:ef7eb2e8f9f7	1310	}
<>	144:ef7eb2e8f9f7	1311	/**
<>	144:ef7eb2e8f9f7	1312	* @}
<>	144:ef7eb2e8f9f7	1313	*/
<>	144:ef7eb2e8f9f7	1314
<>	144:ef7eb2e8f9f7	1315	/** @defgroup DAC_LL_EF_Operation Operation on DAC channels
<>	144:ef7eb2e8f9f7	1316	* @{
<>	144:ef7eb2e8f9f7	1317	*/
<>	144:ef7eb2e8f9f7	1318
<>	144:ef7eb2e8f9f7	1319	/**
<>	144:ef7eb2e8f9f7	1320	* @brief Enable DAC selected channel.
<>	144:ef7eb2e8f9f7	1321	* @rmtoll CR EN1 LL_DAC_Enable\n
<>	144:ef7eb2e8f9f7	1322	* CR EN2 LL_DAC_Enable
<>	144:ef7eb2e8f9f7	1323	* @note After enable from off state, DAC channel requires a delay
<>	144:ef7eb2e8f9f7	1324	* for output voltage to reach accuracy +/- 1 LSB.
<>	144:ef7eb2e8f9f7	1325	* Refer to device datasheet, parameter "tWAKEUP".
<>	144:ef7eb2e8f9f7	1326	* @param DACx DAC instance
<>	144:ef7eb2e8f9f7	1327	* @param DAC_Channel This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1328	* @arg @ref LL_DAC_CHANNEL_1
<>	144:ef7eb2e8f9f7	1329	* @arg @ref LL_DAC_CHANNEL_2
<>	144:ef7eb2e8f9f7	1330	* @retval None
<>	144:ef7eb2e8f9f7	1331	*/
<>	144:ef7eb2e8f9f7	1332	__STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<>	144:ef7eb2e8f9f7	1333	{
<>	144:ef7eb2e8f9f7	1334	SET_BIT(DACx->CR,
<>	144:ef7eb2e8f9f7	1335	DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
<>	144:ef7eb2e8f9f7	1336	}
<>	144:ef7eb2e8f9f7	1337
<>	144:ef7eb2e8f9f7	1338	/**
<>	144:ef7eb2e8f9f7	1339	* @brief Disable DAC selected channel.
<>	144:ef7eb2e8f9f7	1340	* @rmtoll CR EN1 LL_DAC_Disable\n
<>	144:ef7eb2e8f9f7	1341	* CR EN2 LL_DAC_Disable
<>	144:ef7eb2e8f9f7	1342	* @param DACx DAC instance
<>	144:ef7eb2e8f9f7	1343	* @param DAC_Channel This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1344	* @arg @ref LL_DAC_CHANNEL_1
<>	144:ef7eb2e8f9f7	1345	* @arg @ref LL_DAC_CHANNEL_2
<>	144:ef7eb2e8f9f7	1346	* @retval None
<>	144:ef7eb2e8f9f7	1347	*/
<>	144:ef7eb2e8f9f7	1348	__STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<>	144:ef7eb2e8f9f7	1349	{
<>	144:ef7eb2e8f9f7	1350	CLEAR_BIT(DACx->CR,
<>	144:ef7eb2e8f9f7	1351	DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
<>	144:ef7eb2e8f9f7	1352	}
<>	144:ef7eb2e8f9f7	1353
<>	144:ef7eb2e8f9f7	1354	/**
<>	144:ef7eb2e8f9f7	1355	* @brief Get DAC enable state of the selected channel.
<>	144:ef7eb2e8f9f7	1356	* (0: DAC channel is disabled, 1: DAC channel is enabled)
<>	144:ef7eb2e8f9f7	1357	* @rmtoll CR EN1 LL_DAC_IsEnabled\n
<>	144:ef7eb2e8f9f7	1358	* CR EN2 LL_DAC_IsEnabled
<>	144:ef7eb2e8f9f7	1359	* @param DACx DAC instance
<>	144:ef7eb2e8f9f7	1360	* @param DAC_Channel This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1361	* @arg @ref LL_DAC_CHANNEL_1
<>	144:ef7eb2e8f9f7	1362	* @arg @ref LL_DAC_CHANNEL_2
<>	144:ef7eb2e8f9f7	1363	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	1364	*/
<>	144:ef7eb2e8f9f7	1365	__STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<>	144:ef7eb2e8f9f7	1366	{
<>	144:ef7eb2e8f9f7	1367	return (READ_BIT(DACx->CR,
<>	144:ef7eb2e8f9f7	1368	DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
<>	144:ef7eb2e8f9f7	1369	== (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
<>	144:ef7eb2e8f9f7	1370	}
<>	144:ef7eb2e8f9f7	1371
<>	144:ef7eb2e8f9f7	1372	/**
<>	144:ef7eb2e8f9f7	1373	* @brief Enable DAC trigger of the selected channel.
<>	144:ef7eb2e8f9f7	1374	* @note - If DAC trigger is disabled, DAC conversion is performed
<>	144:ef7eb2e8f9f7	1375	* automatically once the data holding register is updated,
<>	144:ef7eb2e8f9f7	1376	* using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
<>	144:ef7eb2e8f9f7	1377	* @ref LL_DAC_ConvertData12RightAligned(), ...
<>	144:ef7eb2e8f9f7	1378	* - If DAC trigger is enabled, DAC conversion is performed
<>	144:ef7eb2e8f9f7	1379	* only when a hardware of software trigger event is occurring.
<>	144:ef7eb2e8f9f7	1380	* Select trigger source using
<>	144:ef7eb2e8f9f7	1381	* function @ref LL_DAC_SetTriggerSource().
<>	144:ef7eb2e8f9f7	1382	* @rmtoll CR TEN1 LL_DAC_EnableTrigger\n
<>	144:ef7eb2e8f9f7	1383	* CR TEN2 LL_DAC_EnableTrigger
<>	144:ef7eb2e8f9f7	1384	* @param DACx DAC instance
<>	144:ef7eb2e8f9f7	1385	* @param DAC_Channel This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1386	* @arg @ref LL_DAC_CHANNEL_1
<>	144:ef7eb2e8f9f7	1387	* @arg @ref LL_DAC_CHANNEL_2
<>	144:ef7eb2e8f9f7	1388	* @retval None
<>	144:ef7eb2e8f9f7	1389	*/
<>	144:ef7eb2e8f9f7	1390	__STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<>	144:ef7eb2e8f9f7	1391	{
<>	144:ef7eb2e8f9f7	1392	SET_BIT(DACx->CR,
<>	144:ef7eb2e8f9f7	1393	DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
<>	144:ef7eb2e8f9f7	1394	}
<>	144:ef7eb2e8f9f7	1395
<>	144:ef7eb2e8f9f7	1396	/**
<>	144:ef7eb2e8f9f7	1397	* @brief Disable DAC trigger of the selected channel.
<>	144:ef7eb2e8f9f7	1398	* @rmtoll CR TEN1 LL_DAC_DisableTrigger\n
<>	144:ef7eb2e8f9f7	1399	* CR TEN2 LL_DAC_DisableTrigger
<>	144:ef7eb2e8f9f7	1400	* @param DACx DAC instance
<>	144:ef7eb2e8f9f7	1401	* @param DAC_Channel This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1402	* @arg @ref LL_DAC_CHANNEL_1
<>	144:ef7eb2e8f9f7	1403	* @arg @ref LL_DAC_CHANNEL_2
<>	144:ef7eb2e8f9f7	1404	* @retval None
<>	144:ef7eb2e8f9f7	1405	*/
<>	144:ef7eb2e8f9f7	1406	__STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<>	144:ef7eb2e8f9f7	1407	{
<>	144:ef7eb2e8f9f7	1408	CLEAR_BIT(DACx->CR,
<>	144:ef7eb2e8f9f7	1409	DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
<>	144:ef7eb2e8f9f7	1410	}
<>	144:ef7eb2e8f9f7	1411
<>	144:ef7eb2e8f9f7	1412	/**
<>	144:ef7eb2e8f9f7	1413	* @brief Get DAC trigger state of the selected channel.
<>	144:ef7eb2e8f9f7	1414	* (0: DAC trigger is disabled, 1: DAC trigger is enabled)
<>	144:ef7eb2e8f9f7	1415	* @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled\n
<>	144:ef7eb2e8f9f7	1416	* CR TEN2 LL_DAC_IsTriggerEnabled
<>	144:ef7eb2e8f9f7	1417	* @param DACx DAC instance
<>	144:ef7eb2e8f9f7	1418	* @param DAC_Channel This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1419	* @arg @ref LL_DAC_CHANNEL_1
<>	144:ef7eb2e8f9f7	1420	* @arg @ref LL_DAC_CHANNEL_2
<>	144:ef7eb2e8f9f7	1421	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	1422	*/
<>	144:ef7eb2e8f9f7	1423	__STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<>	144:ef7eb2e8f9f7	1424	{
<>	144:ef7eb2e8f9f7	1425	return (READ_BIT(DACx->CR,
<>	144:ef7eb2e8f9f7	1426	DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
<>	144:ef7eb2e8f9f7	1427	== (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
<>	144:ef7eb2e8f9f7	1428	}
<>	144:ef7eb2e8f9f7	1429
<>	144:ef7eb2e8f9f7	1430	/**
<>	144:ef7eb2e8f9f7	1431	* @brief Trig DAC conversion by software for the selected DAC channel.
<>	144:ef7eb2e8f9f7	1432	* @note Preliminarily, DAC trigger must be set to software trigger
<>	144:ef7eb2e8f9f7	1433	* using function @ref LL_DAC_SetTriggerSource()
<>	144:ef7eb2e8f9f7	1434	* with parameter "LL_DAC_TRIGGER_SOFTWARE".
<>	144:ef7eb2e8f9f7	1435	* and DAC trigger must be enabled using
<>	144:ef7eb2e8f9f7	1436	* function @ref LL_DAC_EnableTrigger().
<>	144:ef7eb2e8f9f7	1437	* @note For devices featuring DAC with 2 channels: this function
<>	144:ef7eb2e8f9f7	1438	* can perform a SW start of both DAC channels simultaneously.
<>	144:ef7eb2e8f9f7	1439	* Two channels can be selected as parameter.
<>	144:ef7eb2e8f9f7	1440	* Example: (LL_DAC_CHANNEL_1 \| LL_DAC_CHANNEL_2)
<>	144:ef7eb2e8f9f7	1441	* @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion\n
<>	144:ef7eb2e8f9f7	1442	* SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion
<>	144:ef7eb2e8f9f7	1443	* @param DACx DAC instance
<>	144:ef7eb2e8f9f7	1444	* @param DAC_Channel This parameter can a combination of the following values:
<>	144:ef7eb2e8f9f7	1445	* @arg @ref LL_DAC_CHANNEL_1
<>	144:ef7eb2e8f9f7	1446	* @arg @ref LL_DAC_CHANNEL_2
<>	144:ef7eb2e8f9f7	1447	* @retval None
<>	144:ef7eb2e8f9f7	1448	*/
<>	144:ef7eb2e8f9f7	1449	__STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<>	144:ef7eb2e8f9f7	1450	{
<>	144:ef7eb2e8f9f7	1451	SET_BIT(DACx->SWTRIGR,
<>	144:ef7eb2e8f9f7	1452	(DAC_Channel & DAC_SWTR_CHX_MASK));
<>	144:ef7eb2e8f9f7	1453	}
<>	144:ef7eb2e8f9f7	1454
<>	144:ef7eb2e8f9f7	1455	/**
<>	144:ef7eb2e8f9f7	1456	* @brief Set the data to be loaded in the data holding register
<>	144:ef7eb2e8f9f7	1457	* in format 12 bits left alignment (LSB aligned on bit 0),
<>	144:ef7eb2e8f9f7	1458	* for the selected DAC channel.
<>	144:ef7eb2e8f9f7	1459	* @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned\n
<>	144:ef7eb2e8f9f7	1460	* DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned
<>	144:ef7eb2e8f9f7	1461	* @param DACx DAC instance
<>	144:ef7eb2e8f9f7	1462	* @param DAC_Channel This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1463	* @arg @ref LL_DAC_CHANNEL_1
<>	144:ef7eb2e8f9f7	1464	* @arg @ref LL_DAC_CHANNEL_2
<>	144:ef7eb2e8f9f7	1465	* @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
<>	144:ef7eb2e8f9f7	1466	* @retval None
<>	144:ef7eb2e8f9f7	1467	*/
<>	144:ef7eb2e8f9f7	1468	__STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
<>	144:ef7eb2e8f9f7	1469	{
<>	144:ef7eb2e8f9f7	1470	register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12RX_REGOFFSET_MASK));
<>	144:ef7eb2e8f9f7	1471
<>	144:ef7eb2e8f9f7	1472	MODIFY_REG(*preg,
<>	144:ef7eb2e8f9f7	1473	DAC_DHR12R1_DACC1DHR,
<>	144:ef7eb2e8f9f7	1474	Data);
<>	144:ef7eb2e8f9f7	1475	}
<>	144:ef7eb2e8f9f7	1476
<>	144:ef7eb2e8f9f7	1477	/**
<>	144:ef7eb2e8f9f7	1478	* @brief Set the data to be loaded in the data holding register
<>	144:ef7eb2e8f9f7	1479	* in format 12 bits left alignment (MSB aligned on bit 15),
<>	144:ef7eb2e8f9f7	1480	* for the selected DAC channel.
<>	144:ef7eb2e8f9f7	1481	* @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned\n
<>	144:ef7eb2e8f9f7	1482	* DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned
<>	144:ef7eb2e8f9f7	1483	* @param DACx DAC instance
<>	144:ef7eb2e8f9f7	1484	* @param DAC_Channel This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1485	* @arg @ref LL_DAC_CHANNEL_1
<>	144:ef7eb2e8f9f7	1486	* @arg @ref LL_DAC_CHANNEL_2
<>	144:ef7eb2e8f9f7	1487	* @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
<>	144:ef7eb2e8f9f7	1488	* @retval None
<>	144:ef7eb2e8f9f7	1489	*/
<>	144:ef7eb2e8f9f7	1490	__STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
<>	144:ef7eb2e8f9f7	1491	{
<>	144:ef7eb2e8f9f7	1492	register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12LX_REGOFFSET_MASK));
<>	144:ef7eb2e8f9f7	1493
<>	144:ef7eb2e8f9f7	1494	MODIFY_REG(*preg,
<>	144:ef7eb2e8f9f7	1495	DAC_DHR12L1_DACC1DHR,
<>	144:ef7eb2e8f9f7	1496	Data);
<>	144:ef7eb2e8f9f7	1497	}
<>	144:ef7eb2e8f9f7	1498
<>	144:ef7eb2e8f9f7	1499	/**
<>	144:ef7eb2e8f9f7	1500	* @brief Set the data to be loaded in the data holding register
<>	144:ef7eb2e8f9f7	1501	* in format 8 bits left alignment (LSB aligned on bit 0),
<>	144:ef7eb2e8f9f7	1502	* for the selected DAC channel.
<>	144:ef7eb2e8f9f7	1503	* @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned\n
<>	144:ef7eb2e8f9f7	1504	* DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned
<>	144:ef7eb2e8f9f7	1505	* @param DACx DAC instance
<>	144:ef7eb2e8f9f7	1506	* @param DAC_Channel This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1507	* @arg @ref LL_DAC_CHANNEL_1
<>	144:ef7eb2e8f9f7	1508	* @arg @ref LL_DAC_CHANNEL_2
<>	144:ef7eb2e8f9f7	1509	* @param Data Value between Min_Data=0x00 and Max_Data=0xFF
<>	144:ef7eb2e8f9f7	1510	* @retval None
<>	144:ef7eb2e8f9f7	1511	*/
<>	144:ef7eb2e8f9f7	1512	__STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
<>	144:ef7eb2e8f9f7	1513	{
<>	144:ef7eb2e8f9f7	1514	register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR8RX_REGOFFSET_MASK));
<>	144:ef7eb2e8f9f7	1515
<>	144:ef7eb2e8f9f7	1516	MODIFY_REG(*preg,
<>	144:ef7eb2e8f9f7	1517	DAC_DHR8R1_DACC1DHR,
<>	144:ef7eb2e8f9f7	1518	Data);
<>	144:ef7eb2e8f9f7	1519	}
<>	144:ef7eb2e8f9f7	1520
<>	144:ef7eb2e8f9f7	1521	/**
<>	144:ef7eb2e8f9f7	1522	* @brief Set the data to be loaded in the data holding register
<>	144:ef7eb2e8f9f7	1523	* in format 12 bits left alignment (LSB aligned on bit 0),
<>	144:ef7eb2e8f9f7	1524	* for both DAC channels.
<>	144:ef7eb2e8f9f7	1525	* @rmtoll DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned\n
<>	144:ef7eb2e8f9f7	1526	* DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned
<>	144:ef7eb2e8f9f7	1527	* @param DACx DAC instance
<>	144:ef7eb2e8f9f7	1528	* @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
<>	144:ef7eb2e8f9f7	1529	* @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
<>	144:ef7eb2e8f9f7	1530	* @retval None
<>	144:ef7eb2e8f9f7	1531	*/
<>	144:ef7eb2e8f9f7	1532	__STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
<>	144:ef7eb2e8f9f7	1533	{
<>	144:ef7eb2e8f9f7	1534	MODIFY_REG(DACx->DHR12RD,
<>	144:ef7eb2e8f9f7	1535	(DAC_DHR12RD_DACC2DHR \| DAC_DHR12RD_DACC1DHR),
<>	144:ef7eb2e8f9f7	1536	((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) \| DataChannel1));
<>	144:ef7eb2e8f9f7	1537	}
<>	144:ef7eb2e8f9f7	1538
<>	144:ef7eb2e8f9f7	1539	/**
<>	144:ef7eb2e8f9f7	1540	* @brief Set the data to be loaded in the data holding register
<>	144:ef7eb2e8f9f7	1541	* in format 12 bits left alignment (MSB aligned on bit 15),
<>	144:ef7eb2e8f9f7	1542	* for both DAC channels.
<>	144:ef7eb2e8f9f7	1543	* @rmtoll DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned\n
<>	144:ef7eb2e8f9f7	1544	* DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned
<>	144:ef7eb2e8f9f7	1545	* @param DACx DAC instance
<>	144:ef7eb2e8f9f7	1546	* @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
<>	144:ef7eb2e8f9f7	1547	* @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
<>	144:ef7eb2e8f9f7	1548	* @retval None
<>	144:ef7eb2e8f9f7	1549	*/
<>	144:ef7eb2e8f9f7	1550	__STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
<>	144:ef7eb2e8f9f7	1551	{
<>	144:ef7eb2e8f9f7	1552	/* Note: Data of DAC channel 2 shift value subtracted of 4 because */
<>	144:ef7eb2e8f9f7	1553	/* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */
<>	144:ef7eb2e8f9f7	1554	/* the 4 LSB must be taken into account for the shift value. */
<>	144:ef7eb2e8f9f7	1555	MODIFY_REG(DACx->DHR12LD,
<>	144:ef7eb2e8f9f7	1556	(DAC_DHR12LD_DACC2DHR \| DAC_DHR12LD_DACC1DHR),
<>	144:ef7eb2e8f9f7	1557	((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) \| DataChannel1));
<>	144:ef7eb2e8f9f7	1558	}
<>	144:ef7eb2e8f9f7	1559
<>	144:ef7eb2e8f9f7	1560	/**
<>	144:ef7eb2e8f9f7	1561	* @brief Set the data to be loaded in the data holding register
<>	144:ef7eb2e8f9f7	1562	* in format 8 bits left alignment (LSB aligned on bit 0),
<>	144:ef7eb2e8f9f7	1563	* for both DAC channels.
<>	144:ef7eb2e8f9f7	1564	* @rmtoll DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned\n
<>	144:ef7eb2e8f9f7	1565	* DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned
<>	144:ef7eb2e8f9f7	1566	* @param DACx DAC instance
<>	144:ef7eb2e8f9f7	1567	* @param DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF
<>	144:ef7eb2e8f9f7	1568	* @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF
<>	144:ef7eb2e8f9f7	1569	* @retval None
<>	144:ef7eb2e8f9f7	1570	*/
<>	144:ef7eb2e8f9f7	1571	__STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
<>	144:ef7eb2e8f9f7	1572	{
<>	144:ef7eb2e8f9f7	1573	MODIFY_REG(DACx->DHR8RD,
<>	144:ef7eb2e8f9f7	1574	(DAC_DHR8RD_DACC2DHR \| DAC_DHR8RD_DACC1DHR),
<>	144:ef7eb2e8f9f7	1575	((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) \| DataChannel1));
<>	144:ef7eb2e8f9f7	1576	}
<>	144:ef7eb2e8f9f7	1577
<>	144:ef7eb2e8f9f7	1578	/**
<>	144:ef7eb2e8f9f7	1579	* @brief Retrieve output data currently generated for the selected DAC channel.
<>	144:ef7eb2e8f9f7	1580	* @note Whatever alignment and resolution settings
<>	144:ef7eb2e8f9f7	1581	* (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
<>	144:ef7eb2e8f9f7	1582	* @ref LL_DAC_ConvertData12RightAligned(), ...),
<>	144:ef7eb2e8f9f7	1583	* output data format is 12 bits right aligned (LSB aligned on bit 0).
<>	144:ef7eb2e8f9f7	1584	* @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData\n
<>	144:ef7eb2e8f9f7	1585	* DOR2 DACC2DOR LL_DAC_RetrieveOutputData
<>	144:ef7eb2e8f9f7	1586	* @param DACx DAC instance
<>	144:ef7eb2e8f9f7	1587	* @param DAC_Channel This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1588	* @arg @ref LL_DAC_CHANNEL_1
<>	144:ef7eb2e8f9f7	1589	* @arg @ref LL_DAC_CHANNEL_2
<>	144:ef7eb2e8f9f7	1590	* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
<>	144:ef7eb2e8f9f7	1591	*/
<>	144:ef7eb2e8f9f7	1592	__STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<>	144:ef7eb2e8f9f7	1593	{
<>	144:ef7eb2e8f9f7	1594	register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DORX_REGOFFSET_MASK));
<>	144:ef7eb2e8f9f7	1595
<>	144:ef7eb2e8f9f7	1596	return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
<>	144:ef7eb2e8f9f7	1597	}
<>	144:ef7eb2e8f9f7	1598
<>	144:ef7eb2e8f9f7	1599	/**
<>	144:ef7eb2e8f9f7	1600	* @}
<>	144:ef7eb2e8f9f7	1601	*/
<>	144:ef7eb2e8f9f7	1602
<>	144:ef7eb2e8f9f7	1603	/** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
<>	144:ef7eb2e8f9f7	1604	* @{
<>	144:ef7eb2e8f9f7	1605	*/
<>	144:ef7eb2e8f9f7	1606	/**
<>	144:ef7eb2e8f9f7	1607	* @brief Get DAC calibration offset flag for DAC channel 1
<>	144:ef7eb2e8f9f7	1608	* @rmtoll SR CAL_FLAG1 LL_DAC_IsActiveFlag_CAL1
<>	144:ef7eb2e8f9f7	1609	* @param DACx DAC instance
<>	144:ef7eb2e8f9f7	1610	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	1611	*/
<>	144:ef7eb2e8f9f7	1612	__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL1(DAC_TypeDef *DACx)
<>	144:ef7eb2e8f9f7	1613	{
<>	144:ef7eb2e8f9f7	1614	return (READ_BIT(DACx->SR, LL_DAC_FLAG_CAL1) == (LL_DAC_FLAG_CAL1));
<>	144:ef7eb2e8f9f7	1615	}
<>	144:ef7eb2e8f9f7	1616
<>	144:ef7eb2e8f9f7	1617	/**
<>	144:ef7eb2e8f9f7	1618	* @brief Get DAC calibration offset flag for DAC channel 2
<>	144:ef7eb2e8f9f7	1619	* @rmtoll SR CAL_FLAG2 LL_DAC_IsActiveFlag_CAL2
<>	144:ef7eb2e8f9f7	1620	* @param DACx DAC instance
<>	144:ef7eb2e8f9f7	1621	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	1622	*/
<>	144:ef7eb2e8f9f7	1623	__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL2(DAC_TypeDef *DACx)
<>	144:ef7eb2e8f9f7	1624	{
<>	144:ef7eb2e8f9f7	1625	return (READ_BIT(DACx->SR, LL_DAC_FLAG_CAL2) == (LL_DAC_FLAG_CAL2));
<>	144:ef7eb2e8f9f7	1626	}
<>	144:ef7eb2e8f9f7	1627
<>	144:ef7eb2e8f9f7	1628	/**
<>	144:ef7eb2e8f9f7	1629	* @brief Get DAC busy writing sample time flag for DAC channel 1
<>	144:ef7eb2e8f9f7	1630	* @rmtoll SR BWST1 LL_DAC_IsActiveFlag_BWST1
<>	144:ef7eb2e8f9f7	1631	* @param DACx DAC instance
<>	144:ef7eb2e8f9f7	1632	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	1633	*/
<>	144:ef7eb2e8f9f7	1634	__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST1(DAC_TypeDef *DACx)
<>	144:ef7eb2e8f9f7	1635	{
<>	144:ef7eb2e8f9f7	1636	return (READ_BIT(DACx->SR, LL_DAC_FLAG_BWST1) == (LL_DAC_FLAG_BWST1));
<>	144:ef7eb2e8f9f7	1637	}
<>	144:ef7eb2e8f9f7	1638
<>	144:ef7eb2e8f9f7	1639	/**
<>	144:ef7eb2e8f9f7	1640	* @brief Get DAC busy writing sample time flag for DAC channel 2
<>	144:ef7eb2e8f9f7	1641	* @rmtoll SR BWST2 LL_DAC_IsActiveFlag_BWST2
<>	144:ef7eb2e8f9f7	1642	* @param DACx DAC instance
<>	144:ef7eb2e8f9f7	1643	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	1644	*/
<>	144:ef7eb2e8f9f7	1645	__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST2(DAC_TypeDef *DACx)
<>	144:ef7eb2e8f9f7	1646	{
<>	144:ef7eb2e8f9f7	1647	return (READ_BIT(DACx->SR, LL_DAC_FLAG_BWST2) == (LL_DAC_FLAG_BWST2));
<>	144:ef7eb2e8f9f7	1648	}
<>	144:ef7eb2e8f9f7	1649
<>	144:ef7eb2e8f9f7	1650	/**
<>	144:ef7eb2e8f9f7	1651	* @brief Get DAC underrun flag for DAC channel 1
<>	144:ef7eb2e8f9f7	1652	* @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1
<>	144:ef7eb2e8f9f7	1653	* @param DACx DAC instance
<>	144:ef7eb2e8f9f7	1654	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	1655	*/
<>	144:ef7eb2e8f9f7	1656	__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx)
<>	144:ef7eb2e8f9f7	1657	{
<>	144:ef7eb2e8f9f7	1658	return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1));
<>	144:ef7eb2e8f9f7	1659	}
<>	144:ef7eb2e8f9f7	1660
<>	144:ef7eb2e8f9f7	1661	/**
<>	144:ef7eb2e8f9f7	1662	* @brief Get DAC underrun flag for DAC channel 2
<>	144:ef7eb2e8f9f7	1663	* @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2
<>	144:ef7eb2e8f9f7	1664	* @param DACx DAC instance
<>	144:ef7eb2e8f9f7	1665	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	1666	*/
<>	144:ef7eb2e8f9f7	1667	__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx)
<>	144:ef7eb2e8f9f7	1668	{
<>	144:ef7eb2e8f9f7	1669	return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2));
<>	144:ef7eb2e8f9f7	1670	}
<>	144:ef7eb2e8f9f7	1671
<>	144:ef7eb2e8f9f7	1672	/**
<>	144:ef7eb2e8f9f7	1673	* @brief Clear DAC underrun flag for DAC channel 1
<>	144:ef7eb2e8f9f7	1674	* @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1
<>	144:ef7eb2e8f9f7	1675	* @param DACx DAC instance
<>	144:ef7eb2e8f9f7	1676	* @retval None
<>	144:ef7eb2e8f9f7	1677	*/
<>	144:ef7eb2e8f9f7	1678	__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx)
<>	144:ef7eb2e8f9f7	1679	{
<>	144:ef7eb2e8f9f7	1680	WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1);
<>	144:ef7eb2e8f9f7	1681	}
<>	144:ef7eb2e8f9f7	1682
<>	144:ef7eb2e8f9f7	1683	/**
<>	144:ef7eb2e8f9f7	1684	* @brief Clear DAC underrun flag for DAC channel 2
<>	144:ef7eb2e8f9f7	1685	* @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2
<>	144:ef7eb2e8f9f7	1686	* @param DACx DAC instance
<>	144:ef7eb2e8f9f7	1687	* @retval None
<>	144:ef7eb2e8f9f7	1688	*/
<>	144:ef7eb2e8f9f7	1689	__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx)
<>	144:ef7eb2e8f9f7	1690	{
<>	144:ef7eb2e8f9f7	1691	WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2);
<>	144:ef7eb2e8f9f7	1692	}
<>	144:ef7eb2e8f9f7	1693
<>	144:ef7eb2e8f9f7	1694	/**
<>	144:ef7eb2e8f9f7	1695	* @}
<>	144:ef7eb2e8f9f7	1696	*/
<>	144:ef7eb2e8f9f7	1697
<>	144:ef7eb2e8f9f7	1698	/** @defgroup DAC_LL_EF_IT_Management IT management
<>	144:ef7eb2e8f9f7	1699	* @{
<>	144:ef7eb2e8f9f7	1700	*/
<>	144:ef7eb2e8f9f7	1701
<>	144:ef7eb2e8f9f7	1702	/**
<>	144:ef7eb2e8f9f7	1703	* @brief Enable DMA underrun interrupt for DAC channel 1
<>	144:ef7eb2e8f9f7	1704	* @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1
<>	144:ef7eb2e8f9f7	1705	* @param DACx DAC instance
<>	144:ef7eb2e8f9f7	1706	* @retval None
<>	144:ef7eb2e8f9f7	1707	*/
<>	144:ef7eb2e8f9f7	1708	__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx)
<>	144:ef7eb2e8f9f7	1709	{
<>	144:ef7eb2e8f9f7	1710	SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
<>	144:ef7eb2e8f9f7	1711	}
<>	144:ef7eb2e8f9f7	1712
<>	144:ef7eb2e8f9f7	1713	/**
<>	144:ef7eb2e8f9f7	1714	* @brief Enable DMA underrun interrupt for DAC channel 2
<>	144:ef7eb2e8f9f7	1715	* @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2
<>	144:ef7eb2e8f9f7	1716	* @param DACx DAC instance
<>	144:ef7eb2e8f9f7	1717	* @retval None
<>	144:ef7eb2e8f9f7	1718	*/
<>	144:ef7eb2e8f9f7	1719	__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx)
<>	144:ef7eb2e8f9f7	1720	{
<>	144:ef7eb2e8f9f7	1721	SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
<>	144:ef7eb2e8f9f7	1722	}
<>	144:ef7eb2e8f9f7	1723
<>	144:ef7eb2e8f9f7	1724	/**
<>	144:ef7eb2e8f9f7	1725	* @brief Disable DMA underrun interrupt for DAC channel 1
<>	144:ef7eb2e8f9f7	1726	* @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1
<>	144:ef7eb2e8f9f7	1727	* @param DACx DAC instance
<>	144:ef7eb2e8f9f7	1728	* @retval None
<>	144:ef7eb2e8f9f7	1729	*/
<>	144:ef7eb2e8f9f7	1730	__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx)
<>	144:ef7eb2e8f9f7	1731	{
<>	144:ef7eb2e8f9f7	1732	CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
<>	144:ef7eb2e8f9f7	1733	}
<>	144:ef7eb2e8f9f7	1734
<>	144:ef7eb2e8f9f7	1735	/**
<>	144:ef7eb2e8f9f7	1736	* @brief Disable DMA underrun interrupt for DAC channel 2
<>	144:ef7eb2e8f9f7	1737	* @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2
<>	144:ef7eb2e8f9f7	1738	* @param DACx DAC instance
<>	144:ef7eb2e8f9f7	1739	* @retval None
<>	144:ef7eb2e8f9f7	1740	*/
<>	144:ef7eb2e8f9f7	1741	__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
<>	144:ef7eb2e8f9f7	1742	{
<>	144:ef7eb2e8f9f7	1743	CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
<>	144:ef7eb2e8f9f7	1744	}
<>	144:ef7eb2e8f9f7	1745
<>	144:ef7eb2e8f9f7	1746	/**
<>	144:ef7eb2e8f9f7	1747	* @brief Get DMA underrun interrupt for DAC channel 1
<>	144:ef7eb2e8f9f7	1748	* @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1
<>	144:ef7eb2e8f9f7	1749	* @param DACx DAC instance
<>	144:ef7eb2e8f9f7	1750	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	1751	*/
<>	144:ef7eb2e8f9f7	1752	__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx)
<>	144:ef7eb2e8f9f7	1753	{
<>	144:ef7eb2e8f9f7	1754	return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1));
<>	144:ef7eb2e8f9f7	1755	}
<>	144:ef7eb2e8f9f7	1756
<>	144:ef7eb2e8f9f7	1757	/**
<>	144:ef7eb2e8f9f7	1758	* @brief Get DMA underrun interrupt for DAC channel 2
<>	144:ef7eb2e8f9f7	1759	* @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2
<>	144:ef7eb2e8f9f7	1760	* @param DACx DAC instance
<>	144:ef7eb2e8f9f7	1761	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	1762	*/
<>	144:ef7eb2e8f9f7	1763	__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx)
<>	144:ef7eb2e8f9f7	1764	{
<>	144:ef7eb2e8f9f7	1765	return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2));
<>	144:ef7eb2e8f9f7	1766	}
<>	144:ef7eb2e8f9f7	1767
<>	144:ef7eb2e8f9f7	1768	/**
<>	144:ef7eb2e8f9f7	1769	* @}
<>	144:ef7eb2e8f9f7	1770	*/
<>	144:ef7eb2e8f9f7	1771
<>	144:ef7eb2e8f9f7	1772	#if defined(USE_FULL_LL_DRIVER)
<>	144:ef7eb2e8f9f7	1773	/** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions
<>	144:ef7eb2e8f9f7	1774	* @{
<>	144:ef7eb2e8f9f7	1775	*/
<>	144:ef7eb2e8f9f7	1776
<>	144:ef7eb2e8f9f7	1777	ErrorStatus LL_DAC_DeInit(DAC_TypeDef* DACx);
<>	144:ef7eb2e8f9f7	1778	ErrorStatus LL_DAC_Init(DAC_TypeDef* DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef* DAC_InitStruct);
<>	144:ef7eb2e8f9f7	1779	void LL_DAC_StructInit(LL_DAC_InitTypeDef* DAC_InitStruct);
<>	144:ef7eb2e8f9f7	1780
<>	144:ef7eb2e8f9f7	1781	/**
<>	144:ef7eb2e8f9f7	1782	* @}
<>	144:ef7eb2e8f9f7	1783	*/
<>	144:ef7eb2e8f9f7	1784	#endif /* USE_FULL_LL_DRIVER */
<>	144:ef7eb2e8f9f7	1785
<>	144:ef7eb2e8f9f7	1786	/**
<>	144:ef7eb2e8f9f7	1787	* @}
<>	144:ef7eb2e8f9f7	1788	*/
<>	144:ef7eb2e8f9f7	1789
<>	144:ef7eb2e8f9f7	1790	/**
<>	144:ef7eb2e8f9f7	1791	* @}
<>	144:ef7eb2e8f9f7	1792	*/
<>	144:ef7eb2e8f9f7	1793
<>	144:ef7eb2e8f9f7	1794	#endif /* DAC1 */
<>	144:ef7eb2e8f9f7	1795
<>	144:ef7eb2e8f9f7	1796	/**
<>	144:ef7eb2e8f9f7	1797	* @}
<>	144:ef7eb2e8f9f7	1798	*/
<>	144:ef7eb2e8f9f7	1799
<>	144:ef7eb2e8f9f7	1800	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	1801	}
<>	144:ef7eb2e8f9f7	1802	#endif
<>	144:ef7eb2e8f9f7	1803
<>	144:ef7eb2e8f9f7	1804	#endif /* __STM32L4xx_LL_DAC_H */
<>	144:ef7eb2e8f9f7	1805
<>	144:ef7eb2e8f9f7	1806	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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