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targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_wdog.h@162:16168a1438f3, 2017-04-08 (annotated)

Committer:
funshine
Date:
Sat Apr 08 17:03:55 2017 +0000
Revision:
162:16168a1438f3
Parent:
161:2cc1468da177 
add code to handle serial port rx error in uart_irq()

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 161:2cc1468da177 1 /**************************************************************************//**
<> 161:2cc1468da177 2 * @file efr32mg12p_wdog.h
<> 161:2cc1468da177 3 * @brief EFR32MG12P_WDOG register and bit field definitions
<> 161:2cc1468da177 4 * @version 5.1.2
<> 161:2cc1468da177 5 ******************************************************************************
<> 161:2cc1468da177 6 * @section License
<> 161:2cc1468da177 7 * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
<> 161:2cc1468da177 8 ******************************************************************************
<> 161:2cc1468da177 9 *
<> 161:2cc1468da177 10 * Permission is granted to anyone to use this software for any purpose,
<> 161:2cc1468da177 11 * including commercial applications, and to alter it and redistribute it
<> 161:2cc1468da177 12 * freely, subject to the following restrictions:
<> 161:2cc1468da177 13 *
<> 161:2cc1468da177 14 * 1. The origin of this software must not be misrepresented; you must not
<> 161:2cc1468da177 15 * claim that you wrote the original software.@n
<> 161:2cc1468da177 16 * 2. Altered source versions must be plainly marked as such, and must not be
<> 161:2cc1468da177 17 * misrepresented as being the original software.@n
<> 161:2cc1468da177 18 * 3. This notice may not be removed or altered from any source distribution.
<> 161:2cc1468da177 19 *
<> 161:2cc1468da177 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
<> 161:2cc1468da177 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
<> 161:2cc1468da177 22 * providing the Software "AS IS", with no express or implied warranties of any
<> 161:2cc1468da177 23 * kind, including, but not limited to, any implied warranties of
<> 161:2cc1468da177 24 * merchantability or fitness for any particular purpose or warranties against
<> 161:2cc1468da177 25 * infringement of any proprietary rights of a third party.
<> 161:2cc1468da177 26 *
<> 161:2cc1468da177 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
<> 161:2cc1468da177 28 * incidental, or special damages, or any other relief, or for any claim by
<> 161:2cc1468da177 29 * any third party, arising from your use of this Software.
<> 161:2cc1468da177 30 *
<> 161:2cc1468da177 31 *****************************************************************************/
<> 161:2cc1468da177 32 /**************************************************************************//**
<> 161:2cc1468da177 33 * @addtogroup Parts
<> 161:2cc1468da177 34 * @{
<> 161:2cc1468da177 35 ******************************************************************************/
<> 161:2cc1468da177 36 /**************************************************************************//**
<> 161:2cc1468da177 37 * @defgroup EFR32MG12P_WDOG
<> 161:2cc1468da177 38 * @{
<> 161:2cc1468da177 39 * @brief EFR32MG12P_WDOG Register Declaration
<> 161:2cc1468da177 40 *****************************************************************************/
<> 161:2cc1468da177 41 typedef struct
<> 161:2cc1468da177 42 {
<> 161:2cc1468da177 43 __IOM uint32_t CTRL; /**< Control Register */
<> 161:2cc1468da177 44 __IOM uint32_t CMD; /**< Command Register */
<> 161:2cc1468da177 45
<> 161:2cc1468da177 46 __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
<> 161:2cc1468da177 47
<> 161:2cc1468da177 48 WDOG_PCH_TypeDef PCH[2]; /**< PCH */
<> 161:2cc1468da177 49
<> 161:2cc1468da177 50 uint32_t RESERVED0[2]; /**< Reserved for future use **/
<> 161:2cc1468da177 51 __IM uint32_t IF; /**< Watchdog Interrupt Flags */
<> 161:2cc1468da177 52 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
<> 161:2cc1468da177 53 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
<> 161:2cc1468da177 54 __IOM uint32_t IEN; /**< Interrupt Enable Register */
<> 161:2cc1468da177 55 } WDOG_TypeDef; /** @} */
<> 161:2cc1468da177 56
<> 161:2cc1468da177 57 /**************************************************************************//**
<> 161:2cc1468da177 58 * @defgroup EFR32MG12P_WDOG_BitFields
<> 161:2cc1468da177 59 * @{
<> 161:2cc1468da177 60 *****************************************************************************/
<> 161:2cc1468da177 61
<> 161:2cc1468da177 62 /* Bit fields for WDOG CTRL */
<> 161:2cc1468da177 63 #define _WDOG_CTRL_RESETVALUE 0x00000F00UL /**< Default value for WDOG_CTRL */
<> 161:2cc1468da177 64 #define _WDOG_CTRL_MASK 0xC7033F7FUL /**< Mask for WDOG_CTRL */
<> 161:2cc1468da177 65 #define WDOG_CTRL_EN (0x1UL << 0) /**< Watchdog Timer Enable */
<> 161:2cc1468da177 66 #define _WDOG_CTRL_EN_SHIFT 0 /**< Shift value for WDOG_EN */
<> 161:2cc1468da177 67 #define _WDOG_CTRL_EN_MASK 0x1UL /**< Bit mask for WDOG_EN */
<> 161:2cc1468da177 68 #define _WDOG_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
<> 161:2cc1468da177 69 #define WDOG_CTRL_EN_DEFAULT (_WDOG_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_CTRL */
<> 161:2cc1468da177 70 #define WDOG_CTRL_DEBUGRUN (0x1UL << 1) /**< Debug Mode Run Enable */
<> 161:2cc1468da177 71 #define _WDOG_CTRL_DEBUGRUN_SHIFT 1 /**< Shift value for WDOG_DEBUGRUN */
<> 161:2cc1468da177 72 #define _WDOG_CTRL_DEBUGRUN_MASK 0x2UL /**< Bit mask for WDOG_DEBUGRUN */
<> 161:2cc1468da177 73 #define _WDOG_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
<> 161:2cc1468da177 74 #define WDOG_CTRL_DEBUGRUN_DEFAULT (_WDOG_CTRL_DEBUGRUN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_CTRL */
<> 161:2cc1468da177 75 #define WDOG_CTRL_EM2RUN (0x1UL << 2) /**< Energy Mode 2 Run Enable */
<> 161:2cc1468da177 76 #define _WDOG_CTRL_EM2RUN_SHIFT 2 /**< Shift value for WDOG_EM2RUN */
<> 161:2cc1468da177 77 #define _WDOG_CTRL_EM2RUN_MASK 0x4UL /**< Bit mask for WDOG_EM2RUN */
<> 161:2cc1468da177 78 #define _WDOG_CTRL_EM2RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
<> 161:2cc1468da177 79 #define WDOG_CTRL_EM2RUN_DEFAULT (_WDOG_CTRL_EM2RUN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_CTRL */
<> 161:2cc1468da177 80 #define WDOG_CTRL_EM3RUN (0x1UL << 3) /**< Energy Mode 3 Run Enable */
<> 161:2cc1468da177 81 #define _WDOG_CTRL_EM3RUN_SHIFT 3 /**< Shift value for WDOG_EM3RUN */
<> 161:2cc1468da177 82 #define _WDOG_CTRL_EM3RUN_MASK 0x8UL /**< Bit mask for WDOG_EM3RUN */
<> 161:2cc1468da177 83 #define _WDOG_CTRL_EM3RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
<> 161:2cc1468da177 84 #define WDOG_CTRL_EM3RUN_DEFAULT (_WDOG_CTRL_EM3RUN_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_CTRL */
<> 161:2cc1468da177 85 #define WDOG_CTRL_LOCK (0x1UL << 4) /**< Configuration lock */
<> 161:2cc1468da177 86 #define _WDOG_CTRL_LOCK_SHIFT 4 /**< Shift value for WDOG_LOCK */
<> 161:2cc1468da177 87 #define _WDOG_CTRL_LOCK_MASK 0x10UL /**< Bit mask for WDOG_LOCK */
<> 161:2cc1468da177 88 #define _WDOG_CTRL_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
<> 161:2cc1468da177 89 #define WDOG_CTRL_LOCK_DEFAULT (_WDOG_CTRL_LOCK_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_CTRL */
<> 161:2cc1468da177 90 #define WDOG_CTRL_EM4BLOCK (0x1UL << 5) /**< Energy Mode 4 Block */
<> 161:2cc1468da177 91 #define _WDOG_CTRL_EM4BLOCK_SHIFT 5 /**< Shift value for WDOG_EM4BLOCK */
<> 161:2cc1468da177 92 #define _WDOG_CTRL_EM4BLOCK_MASK 0x20UL /**< Bit mask for WDOG_EM4BLOCK */
<> 161:2cc1468da177 93 #define _WDOG_CTRL_EM4BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
<> 161:2cc1468da177 94 #define WDOG_CTRL_EM4BLOCK_DEFAULT (_WDOG_CTRL_EM4BLOCK_DEFAULT << 5) /**< Shifted mode DEFAULT for WDOG_CTRL */
<> 161:2cc1468da177 95 #define WDOG_CTRL_SWOSCBLOCK (0x1UL << 6) /**< Software Oscillator Disable Block */
<> 161:2cc1468da177 96 #define _WDOG_CTRL_SWOSCBLOCK_SHIFT 6 /**< Shift value for WDOG_SWOSCBLOCK */
<> 161:2cc1468da177 97 #define _WDOG_CTRL_SWOSCBLOCK_MASK 0x40UL /**< Bit mask for WDOG_SWOSCBLOCK */
<> 161:2cc1468da177 98 #define _WDOG_CTRL_SWOSCBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
<> 161:2cc1468da177 99 #define WDOG_CTRL_SWOSCBLOCK_DEFAULT (_WDOG_CTRL_SWOSCBLOCK_DEFAULT << 6) /**< Shifted mode DEFAULT for WDOG_CTRL */
<> 161:2cc1468da177 100 #define _WDOG_CTRL_PERSEL_SHIFT 8 /**< Shift value for WDOG_PERSEL */
<> 161:2cc1468da177 101 #define _WDOG_CTRL_PERSEL_MASK 0xF00UL /**< Bit mask for WDOG_PERSEL */
<> 161:2cc1468da177 102 #define _WDOG_CTRL_PERSEL_DEFAULT 0x0000000FUL /**< Mode DEFAULT for WDOG_CTRL */
<> 161:2cc1468da177 103 #define WDOG_CTRL_PERSEL_DEFAULT (_WDOG_CTRL_PERSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WDOG_CTRL */
<> 161:2cc1468da177 104 #define _WDOG_CTRL_CLKSEL_SHIFT 12 /**< Shift value for WDOG_CLKSEL */
<> 161:2cc1468da177 105 #define _WDOG_CTRL_CLKSEL_MASK 0x3000UL /**< Bit mask for WDOG_CLKSEL */
<> 161:2cc1468da177 106 #define _WDOG_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
<> 161:2cc1468da177 107 #define _WDOG_CTRL_CLKSEL_ULFRCO 0x00000000UL /**< Mode ULFRCO for WDOG_CTRL */
<> 161:2cc1468da177 108 #define _WDOG_CTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for WDOG_CTRL */
<> 161:2cc1468da177 109 #define _WDOG_CTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for WDOG_CTRL */
<> 161:2cc1468da177 110 #define _WDOG_CTRL_CLKSEL_HFCORECLK 0x00000003UL /**< Mode HFCORECLK for WDOG_CTRL */
<> 161:2cc1468da177 111 #define WDOG_CTRL_CLKSEL_DEFAULT (_WDOG_CTRL_CLKSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for WDOG_CTRL */
<> 161:2cc1468da177 112 #define WDOG_CTRL_CLKSEL_ULFRCO (_WDOG_CTRL_CLKSEL_ULFRCO << 12) /**< Shifted mode ULFRCO for WDOG_CTRL */
<> 161:2cc1468da177 113 #define WDOG_CTRL_CLKSEL_LFRCO (_WDOG_CTRL_CLKSEL_LFRCO << 12) /**< Shifted mode LFRCO for WDOG_CTRL */
<> 161:2cc1468da177 114 #define WDOG_CTRL_CLKSEL_LFXO (_WDOG_CTRL_CLKSEL_LFXO << 12) /**< Shifted mode LFXO for WDOG_CTRL */
<> 161:2cc1468da177 115 #define WDOG_CTRL_CLKSEL_HFCORECLK (_WDOG_CTRL_CLKSEL_HFCORECLK << 12) /**< Shifted mode HFCORECLK for WDOG_CTRL */
<> 161:2cc1468da177 116 #define _WDOG_CTRL_WARNSEL_SHIFT 16 /**< Shift value for WDOG_WARNSEL */
<> 161:2cc1468da177 117 #define _WDOG_CTRL_WARNSEL_MASK 0x30000UL /**< Bit mask for WDOG_WARNSEL */
<> 161:2cc1468da177 118 #define _WDOG_CTRL_WARNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
<> 161:2cc1468da177 119 #define WDOG_CTRL_WARNSEL_DEFAULT (_WDOG_CTRL_WARNSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WDOG_CTRL */
<> 161:2cc1468da177 120 #define _WDOG_CTRL_WINSEL_SHIFT 24 /**< Shift value for WDOG_WINSEL */
<> 161:2cc1468da177 121 #define _WDOG_CTRL_WINSEL_MASK 0x7000000UL /**< Bit mask for WDOG_WINSEL */
<> 161:2cc1468da177 122 #define _WDOG_CTRL_WINSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
<> 161:2cc1468da177 123 #define WDOG_CTRL_WINSEL_DEFAULT (_WDOG_CTRL_WINSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for WDOG_CTRL */
<> 161:2cc1468da177 124 #define WDOG_CTRL_CLRSRC (0x1UL << 30) /**< Watchdog Clear Source */
<> 161:2cc1468da177 125 #define _WDOG_CTRL_CLRSRC_SHIFT 30 /**< Shift value for WDOG_CLRSRC */
<> 161:2cc1468da177 126 #define _WDOG_CTRL_CLRSRC_MASK 0x40000000UL /**< Bit mask for WDOG_CLRSRC */
<> 161:2cc1468da177 127 #define _WDOG_CTRL_CLRSRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
<> 161:2cc1468da177 128 #define _WDOG_CTRL_CLRSRC_SW 0x00000000UL /**< Mode SW for WDOG_CTRL */
<> 161:2cc1468da177 129 #define _WDOG_CTRL_CLRSRC_PCH0 0x00000001UL /**< Mode PCH0 for WDOG_CTRL */
<> 161:2cc1468da177 130 #define WDOG_CTRL_CLRSRC_DEFAULT (_WDOG_CTRL_CLRSRC_DEFAULT << 30) /**< Shifted mode DEFAULT for WDOG_CTRL */
<> 161:2cc1468da177 131 #define WDOG_CTRL_CLRSRC_SW (_WDOG_CTRL_CLRSRC_SW << 30) /**< Shifted mode SW for WDOG_CTRL */
<> 161:2cc1468da177 132 #define WDOG_CTRL_CLRSRC_PCH0 (_WDOG_CTRL_CLRSRC_PCH0 << 30) /**< Shifted mode PCH0 for WDOG_CTRL */
<> 161:2cc1468da177 133 #define WDOG_CTRL_WDOGRSTDIS (0x1UL << 31) /**< Watchdog Reset Disable */
<> 161:2cc1468da177 134 #define _WDOG_CTRL_WDOGRSTDIS_SHIFT 31 /**< Shift value for WDOG_WDOGRSTDIS */
<> 161:2cc1468da177 135 #define _WDOG_CTRL_WDOGRSTDIS_MASK 0x80000000UL /**< Bit mask for WDOG_WDOGRSTDIS */
<> 161:2cc1468da177 136 #define _WDOG_CTRL_WDOGRSTDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
<> 161:2cc1468da177 137 #define _WDOG_CTRL_WDOGRSTDIS_EN 0x00000000UL /**< Mode EN for WDOG_CTRL */
<> 161:2cc1468da177 138 #define _WDOG_CTRL_WDOGRSTDIS_DIS 0x00000001UL /**< Mode DIS for WDOG_CTRL */
<> 161:2cc1468da177 139 #define WDOG_CTRL_WDOGRSTDIS_DEFAULT (_WDOG_CTRL_WDOGRSTDIS_DEFAULT << 31) /**< Shifted mode DEFAULT for WDOG_CTRL */
<> 161:2cc1468da177 140 #define WDOG_CTRL_WDOGRSTDIS_EN (_WDOG_CTRL_WDOGRSTDIS_EN << 31) /**< Shifted mode EN for WDOG_CTRL */
<> 161:2cc1468da177 141 #define WDOG_CTRL_WDOGRSTDIS_DIS (_WDOG_CTRL_WDOGRSTDIS_DIS << 31) /**< Shifted mode DIS for WDOG_CTRL */
<> 161:2cc1468da177 142
<> 161:2cc1468da177 143 /* Bit fields for WDOG CMD */
<> 161:2cc1468da177 144 #define _WDOG_CMD_RESETVALUE 0x00000000UL /**< Default value for WDOG_CMD */
<> 161:2cc1468da177 145 #define _WDOG_CMD_MASK 0x00000001UL /**< Mask for WDOG_CMD */
<> 161:2cc1468da177 146 #define WDOG_CMD_CLEAR (0x1UL << 0) /**< Watchdog Timer Clear */
<> 161:2cc1468da177 147 #define _WDOG_CMD_CLEAR_SHIFT 0 /**< Shift value for WDOG_CLEAR */
<> 161:2cc1468da177 148 #define _WDOG_CMD_CLEAR_MASK 0x1UL /**< Bit mask for WDOG_CLEAR */
<> 161:2cc1468da177 149 #define _WDOG_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CMD */
<> 161:2cc1468da177 150 #define _WDOG_CMD_CLEAR_UNCHANGED 0x00000000UL /**< Mode UNCHANGED for WDOG_CMD */
<> 161:2cc1468da177 151 #define _WDOG_CMD_CLEAR_CLEARED 0x00000001UL /**< Mode CLEARED for WDOG_CMD */
<> 161:2cc1468da177 152 #define WDOG_CMD_CLEAR_DEFAULT (_WDOG_CMD_CLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_CMD */
<> 161:2cc1468da177 153 #define WDOG_CMD_CLEAR_UNCHANGED (_WDOG_CMD_CLEAR_UNCHANGED << 0) /**< Shifted mode UNCHANGED for WDOG_CMD */
<> 161:2cc1468da177 154 #define WDOG_CMD_CLEAR_CLEARED (_WDOG_CMD_CLEAR_CLEARED << 0) /**< Shifted mode CLEARED for WDOG_CMD */
<> 161:2cc1468da177 155
<> 161:2cc1468da177 156 /* Bit fields for WDOG SYNCBUSY */
<> 161:2cc1468da177 157 #define _WDOG_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for WDOG_SYNCBUSY */
<> 161:2cc1468da177 158 #define _WDOG_SYNCBUSY_MASK 0x0000000FUL /**< Mask for WDOG_SYNCBUSY */
<> 161:2cc1468da177 159 #define WDOG_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Register Busy */
<> 161:2cc1468da177 160 #define _WDOG_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for WDOG_CTRL */
<> 161:2cc1468da177 161 #define _WDOG_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for WDOG_CTRL */
<> 161:2cc1468da177 162 #define _WDOG_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */
<> 161:2cc1468da177 163 #define WDOG_SYNCBUSY_CTRL_DEFAULT (_WDOG_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */
<> 161:2cc1468da177 164 #define WDOG_SYNCBUSY_CMD (0x1UL << 1) /**< CMD Register Busy */
<> 161:2cc1468da177 165 #define _WDOG_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for WDOG_CMD */
<> 161:2cc1468da177 166 #define _WDOG_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for WDOG_CMD */
<> 161:2cc1468da177 167 #define _WDOG_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */
<> 161:2cc1468da177 168 #define WDOG_SYNCBUSY_CMD_DEFAULT (_WDOG_SYNCBUSY_CMD_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */
<> 161:2cc1468da177 169 #define WDOG_SYNCBUSY_PCH0_PRSCTRL (0x1UL << 2) /**< PCH0_PRSCTRL Register Busy */
<> 161:2cc1468da177 170 #define _WDOG_SYNCBUSY_PCH0_PRSCTRL_SHIFT 2 /**< Shift value for WDOG_PCH0_PRSCTRL */
<> 161:2cc1468da177 171 #define _WDOG_SYNCBUSY_PCH0_PRSCTRL_MASK 0x4UL /**< Bit mask for WDOG_PCH0_PRSCTRL */
<> 161:2cc1468da177 172 #define _WDOG_SYNCBUSY_PCH0_PRSCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */
<> 161:2cc1468da177 173 #define WDOG_SYNCBUSY_PCH0_PRSCTRL_DEFAULT (_WDOG_SYNCBUSY_PCH0_PRSCTRL_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */
<> 161:2cc1468da177 174 #define WDOG_SYNCBUSY_PCH1_PRSCTRL (0x1UL << 3) /**< PCH1_PRSCTRL Register Busy */
<> 161:2cc1468da177 175 #define _WDOG_SYNCBUSY_PCH1_PRSCTRL_SHIFT 3 /**< Shift value for WDOG_PCH1_PRSCTRL */
<> 161:2cc1468da177 176 #define _WDOG_SYNCBUSY_PCH1_PRSCTRL_MASK 0x8UL /**< Bit mask for WDOG_PCH1_PRSCTRL */
<> 161:2cc1468da177 177 #define _WDOG_SYNCBUSY_PCH1_PRSCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */
<> 161:2cc1468da177 178 #define WDOG_SYNCBUSY_PCH1_PRSCTRL_DEFAULT (_WDOG_SYNCBUSY_PCH1_PRSCTRL_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */
<> 161:2cc1468da177 179
<> 161:2cc1468da177 180 /* Bit fields for WDOG PCH_PRSCTRL */
<> 161:2cc1468da177 181 #define _WDOG_PCH_PRSCTRL_RESETVALUE 0x00000000UL /**< Default value for WDOG_PCH_PRSCTRL */
<> 161:2cc1468da177 182 #define _WDOG_PCH_PRSCTRL_MASK 0x0000010FUL /**< Mask for WDOG_PCH_PRSCTRL */
<> 161:2cc1468da177 183 #define _WDOG_PCH_PRSCTRL_PRSSEL_SHIFT 0 /**< Shift value for WDOG_PRSSEL */
<> 161:2cc1468da177 184 #define _WDOG_PCH_PRSCTRL_PRSSEL_MASK 0xFUL /**< Bit mask for WDOG_PRSSEL */
<> 161:2cc1468da177 185 #define _WDOG_PCH_PRSCTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_PCH_PRSCTRL */
<> 161:2cc1468da177 186 #define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WDOG_PCH_PRSCTRL */
<> 161:2cc1468da177 187 #define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WDOG_PCH_PRSCTRL */
<> 161:2cc1468da177 188 #define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WDOG_PCH_PRSCTRL */
<> 161:2cc1468da177 189 #define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WDOG_PCH_PRSCTRL */
<> 161:2cc1468da177 190 #define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WDOG_PCH_PRSCTRL */
<> 161:2cc1468da177 191 #define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WDOG_PCH_PRSCTRL */
<> 161:2cc1468da177 192 #define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WDOG_PCH_PRSCTRL */
<> 161:2cc1468da177 193 #define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WDOG_PCH_PRSCTRL */
<> 161:2cc1468da177 194 #define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WDOG_PCH_PRSCTRL */
<> 161:2cc1468da177 195 #define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WDOG_PCH_PRSCTRL */
<> 161:2cc1468da177 196 #define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WDOG_PCH_PRSCTRL */
<> 161:2cc1468da177 197 #define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WDOG_PCH_PRSCTRL */
<> 161:2cc1468da177 198 #define WDOG_PCH_PRSCTRL_PRSSEL_DEFAULT (_WDOG_PCH_PRSCTRL_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_PCH_PRSCTRL */
<> 161:2cc1468da177 199 #define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH0 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WDOG_PCH_PRSCTRL */
<> 161:2cc1468da177 200 #define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH1 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WDOG_PCH_PRSCTRL */
<> 161:2cc1468da177 201 #define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH2 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WDOG_PCH_PRSCTRL */
<> 161:2cc1468da177 202 #define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH3 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WDOG_PCH_PRSCTRL */
<> 161:2cc1468da177 203 #define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH4 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WDOG_PCH_PRSCTRL */
<> 161:2cc1468da177 204 #define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH5 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WDOG_PCH_PRSCTRL */
<> 161:2cc1468da177 205 #define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH6 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WDOG_PCH_PRSCTRL */
<> 161:2cc1468da177 206 #define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH7 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WDOG_PCH_PRSCTRL */
<> 161:2cc1468da177 207 #define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH8 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WDOG_PCH_PRSCTRL */
<> 161:2cc1468da177 208 #define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH9 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WDOG_PCH_PRSCTRL */
<> 161:2cc1468da177 209 #define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH10 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WDOG_PCH_PRSCTRL */
<> 161:2cc1468da177 210 #define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH11 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WDOG_PCH_PRSCTRL */
<> 161:2cc1468da177 211 #define WDOG_PCH_PRSCTRL_PRSMISSRSTEN (0x1UL << 8) /**< PRS missing event will trigger a watchdog reset */
<> 161:2cc1468da177 212 #define _WDOG_PCH_PRSCTRL_PRSMISSRSTEN_SHIFT 8 /**< Shift value for WDOG_PRSMISSRSTEN */
<> 161:2cc1468da177 213 #define _WDOG_PCH_PRSCTRL_PRSMISSRSTEN_MASK 0x100UL /**< Bit mask for WDOG_PRSMISSRSTEN */
<> 161:2cc1468da177 214 #define _WDOG_PCH_PRSCTRL_PRSMISSRSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_PCH_PRSCTRL */
<> 161:2cc1468da177 215 #define WDOG_PCH_PRSCTRL_PRSMISSRSTEN_DEFAULT (_WDOG_PCH_PRSCTRL_PRSMISSRSTEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WDOG_PCH_PRSCTRL */
<> 161:2cc1468da177 216
<> 161:2cc1468da177 217 /* Bit fields for WDOG IF */
<> 161:2cc1468da177 218 #define _WDOG_IF_RESETVALUE 0x00000000UL /**< Default value for WDOG_IF */
<> 161:2cc1468da177 219 #define _WDOG_IF_MASK 0x0000001FUL /**< Mask for WDOG_IF */
<> 161:2cc1468da177 220 #define WDOG_IF_TOUT (0x1UL << 0) /**< WDOG Timeout Interrupt Flag */
<> 161:2cc1468da177 221 #define _WDOG_IF_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */
<> 161:2cc1468da177 222 #define _WDOG_IF_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */
<> 161:2cc1468da177 223 #define _WDOG_IF_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */
<> 161:2cc1468da177 224 #define WDOG_IF_TOUT_DEFAULT (_WDOG_IF_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IF */
<> 161:2cc1468da177 225 #define WDOG_IF_WARN (0x1UL << 1) /**< WDOG Warning Timeout Interrupt Flag */
<> 161:2cc1468da177 226 #define _WDOG_IF_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */
<> 161:2cc1468da177 227 #define _WDOG_IF_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */
<> 161:2cc1468da177 228 #define _WDOG_IF_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */
<> 161:2cc1468da177 229 #define WDOG_IF_WARN_DEFAULT (_WDOG_IF_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IF */
<> 161:2cc1468da177 230 #define WDOG_IF_WIN (0x1UL << 2) /**< WDOG Window Interrupt Flag */
<> 161:2cc1468da177 231 #define _WDOG_IF_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */
<> 161:2cc1468da177 232 #define _WDOG_IF_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */
<> 161:2cc1468da177 233 #define _WDOG_IF_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */
<> 161:2cc1468da177 234 #define WDOG_IF_WIN_DEFAULT (_WDOG_IF_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IF */
<> 161:2cc1468da177 235 #define WDOG_IF_PEM0 (0x1UL << 3) /**< PRS Channel Zero Event Missing Interrupt Flag */
<> 161:2cc1468da177 236 #define _WDOG_IF_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */
<> 161:2cc1468da177 237 #define _WDOG_IF_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */
<> 161:2cc1468da177 238 #define _WDOG_IF_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */
<> 161:2cc1468da177 239 #define WDOG_IF_PEM0_DEFAULT (_WDOG_IF_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IF */
<> 161:2cc1468da177 240 #define WDOG_IF_PEM1 (0x1UL << 4) /**< PRS Channel One Event Missing Interrupt Flag */
<> 161:2cc1468da177 241 #define _WDOG_IF_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */
<> 161:2cc1468da177 242 #define _WDOG_IF_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */
<> 161:2cc1468da177 243 #define _WDOG_IF_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */
<> 161:2cc1468da177 244 #define WDOG_IF_PEM1_DEFAULT (_WDOG_IF_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IF */
<> 161:2cc1468da177 245
<> 161:2cc1468da177 246 /* Bit fields for WDOG IFS */
<> 161:2cc1468da177 247 #define _WDOG_IFS_RESETVALUE 0x00000000UL /**< Default value for WDOG_IFS */
<> 161:2cc1468da177 248 #define _WDOG_IFS_MASK 0x0000001FUL /**< Mask for WDOG_IFS */
<> 161:2cc1468da177 249 #define WDOG_IFS_TOUT (0x1UL << 0) /**< Set TOUT Interrupt Flag */
<> 161:2cc1468da177 250 #define _WDOG_IFS_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */
<> 161:2cc1468da177 251 #define _WDOG_IFS_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */
<> 161:2cc1468da177 252 #define _WDOG_IFS_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFS */
<> 161:2cc1468da177 253 #define WDOG_IFS_TOUT_DEFAULT (_WDOG_IFS_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IFS */
<> 161:2cc1468da177 254 #define WDOG_IFS_WARN (0x1UL << 1) /**< Set WARN Interrupt Flag */
<> 161:2cc1468da177 255 #define _WDOG_IFS_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */
<> 161:2cc1468da177 256 #define _WDOG_IFS_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */
<> 161:2cc1468da177 257 #define _WDOG_IFS_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFS */
<> 161:2cc1468da177 258 #define WDOG_IFS_WARN_DEFAULT (_WDOG_IFS_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IFS */
<> 161:2cc1468da177 259 #define WDOG_IFS_WIN (0x1UL << 2) /**< Set WIN Interrupt Flag */
<> 161:2cc1468da177 260 #define _WDOG_IFS_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */
<> 161:2cc1468da177 261 #define _WDOG_IFS_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */
<> 161:2cc1468da177 262 #define _WDOG_IFS_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFS */
<> 161:2cc1468da177 263 #define WDOG_IFS_WIN_DEFAULT (_WDOG_IFS_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IFS */
<> 161:2cc1468da177 264 #define WDOG_IFS_PEM0 (0x1UL << 3) /**< Set PEM0 Interrupt Flag */
<> 161:2cc1468da177 265 #define _WDOG_IFS_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */
<> 161:2cc1468da177 266 #define _WDOG_IFS_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */
<> 161:2cc1468da177 267 #define _WDOG_IFS_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFS */
<> 161:2cc1468da177 268 #define WDOG_IFS_PEM0_DEFAULT (_WDOG_IFS_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IFS */
<> 161:2cc1468da177 269 #define WDOG_IFS_PEM1 (0x1UL << 4) /**< Set PEM1 Interrupt Flag */
<> 161:2cc1468da177 270 #define _WDOG_IFS_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */
<> 161:2cc1468da177 271 #define _WDOG_IFS_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */
<> 161:2cc1468da177 272 #define _WDOG_IFS_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFS */
<> 161:2cc1468da177 273 #define WDOG_IFS_PEM1_DEFAULT (_WDOG_IFS_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IFS */
<> 161:2cc1468da177 274
<> 161:2cc1468da177 275 /* Bit fields for WDOG IFC */
<> 161:2cc1468da177 276 #define _WDOG_IFC_RESETVALUE 0x00000000UL /**< Default value for WDOG_IFC */
<> 161:2cc1468da177 277 #define _WDOG_IFC_MASK 0x0000001FUL /**< Mask for WDOG_IFC */
<> 161:2cc1468da177 278 #define WDOG_IFC_TOUT (0x1UL << 0) /**< Clear TOUT Interrupt Flag */
<> 161:2cc1468da177 279 #define _WDOG_IFC_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */
<> 161:2cc1468da177 280 #define _WDOG_IFC_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */
<> 161:2cc1468da177 281 #define _WDOG_IFC_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFC */
<> 161:2cc1468da177 282 #define WDOG_IFC_TOUT_DEFAULT (_WDOG_IFC_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IFC */
<> 161:2cc1468da177 283 #define WDOG_IFC_WARN (0x1UL << 1) /**< Clear WARN Interrupt Flag */
<> 161:2cc1468da177 284 #define _WDOG_IFC_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */
<> 161:2cc1468da177 285 #define _WDOG_IFC_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */
<> 161:2cc1468da177 286 #define _WDOG_IFC_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFC */
<> 161:2cc1468da177 287 #define WDOG_IFC_WARN_DEFAULT (_WDOG_IFC_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IFC */
<> 161:2cc1468da177 288 #define WDOG_IFC_WIN (0x1UL << 2) /**< Clear WIN Interrupt Flag */
<> 161:2cc1468da177 289 #define _WDOG_IFC_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */
<> 161:2cc1468da177 290 #define _WDOG_IFC_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */
<> 161:2cc1468da177 291 #define _WDOG_IFC_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFC */
<> 161:2cc1468da177 292 #define WDOG_IFC_WIN_DEFAULT (_WDOG_IFC_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IFC */
<> 161:2cc1468da177 293 #define WDOG_IFC_PEM0 (0x1UL << 3) /**< Clear PEM0 Interrupt Flag */
<> 161:2cc1468da177 294 #define _WDOG_IFC_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */
<> 161:2cc1468da177 295 #define _WDOG_IFC_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */
<> 161:2cc1468da177 296 #define _WDOG_IFC_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFC */
<> 161:2cc1468da177 297 #define WDOG_IFC_PEM0_DEFAULT (_WDOG_IFC_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IFC */
<> 161:2cc1468da177 298 #define WDOG_IFC_PEM1 (0x1UL << 4) /**< Clear PEM1 Interrupt Flag */
<> 161:2cc1468da177 299 #define _WDOG_IFC_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */
<> 161:2cc1468da177 300 #define _WDOG_IFC_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */
<> 161:2cc1468da177 301 #define _WDOG_IFC_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFC */
<> 161:2cc1468da177 302 #define WDOG_IFC_PEM1_DEFAULT (_WDOG_IFC_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IFC */
<> 161:2cc1468da177 303
<> 161:2cc1468da177 304 /* Bit fields for WDOG IEN */
<> 161:2cc1468da177 305 #define _WDOG_IEN_RESETVALUE 0x00000000UL /**< Default value for WDOG_IEN */
<> 161:2cc1468da177 306 #define _WDOG_IEN_MASK 0x0000001FUL /**< Mask for WDOG_IEN */
<> 161:2cc1468da177 307 #define WDOG_IEN_TOUT (0x1UL << 0) /**< TOUT Interrupt Enable */
<> 161:2cc1468da177 308 #define _WDOG_IEN_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */
<> 161:2cc1468da177 309 #define _WDOG_IEN_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */
<> 161:2cc1468da177 310 #define _WDOG_IEN_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */
<> 161:2cc1468da177 311 #define WDOG_IEN_TOUT_DEFAULT (_WDOG_IEN_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IEN */
<> 161:2cc1468da177 312 #define WDOG_IEN_WARN (0x1UL << 1) /**< WARN Interrupt Enable */
<> 161:2cc1468da177 313 #define _WDOG_IEN_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */
<> 161:2cc1468da177 314 #define _WDOG_IEN_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */
<> 161:2cc1468da177 315 #define _WDOG_IEN_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */
<> 161:2cc1468da177 316 #define WDOG_IEN_WARN_DEFAULT (_WDOG_IEN_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IEN */
<> 161:2cc1468da177 317 #define WDOG_IEN_WIN (0x1UL << 2) /**< WIN Interrupt Enable */
<> 161:2cc1468da177 318 #define _WDOG_IEN_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */
<> 161:2cc1468da177 319 #define _WDOG_IEN_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */
<> 161:2cc1468da177 320 #define _WDOG_IEN_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */
<> 161:2cc1468da177 321 #define WDOG_IEN_WIN_DEFAULT (_WDOG_IEN_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IEN */
<> 161:2cc1468da177 322 #define WDOG_IEN_PEM0 (0x1UL << 3) /**< PEM0 Interrupt Enable */
<> 161:2cc1468da177 323 #define _WDOG_IEN_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */
<> 161:2cc1468da177 324 #define _WDOG_IEN_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */
<> 161:2cc1468da177 325 #define _WDOG_IEN_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */
<> 161:2cc1468da177 326 #define WDOG_IEN_PEM0_DEFAULT (_WDOG_IEN_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IEN */
<> 161:2cc1468da177 327 #define WDOG_IEN_PEM1 (0x1UL << 4) /**< PEM1 Interrupt Enable */
<> 161:2cc1468da177 328 #define _WDOG_IEN_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */
<> 161:2cc1468da177 329 #define _WDOG_IEN_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */
<> 161:2cc1468da177 330 #define _WDOG_IEN_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */
<> 161:2cc1468da177 331 #define WDOG_IEN_PEM1_DEFAULT (_WDOG_IEN_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IEN */
<> 161:2cc1468da177 332
<> 161:2cc1468da177 333 /** @} End of group EFR32MG12P_WDOG */
<> 161:2cc1468da177 334 /** @} End of group Parts */
<> 161:2cc1468da177 335