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targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_flash_ex.c@162:16168a1438f3, 2017-04-08 (annotated)

Committer:
funshine
Date:
Sat Apr 08 17:03:55 2017 +0000
Revision:
162:16168a1438f3
Parent:
149:156823d33999 
add code to handle serial port rx error in uart_irq()

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f4xx_hal_flash_ex.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.5.0
<> 144:ef7eb2e8f9f7 6 * @date 06-May-2016
<> 144:ef7eb2e8f9f7 7 * @brief Extended FLASH HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 9 * functionalities of the FLASH extension peripheral:
<> 144:ef7eb2e8f9f7 10 * + Extended programming operations functions
<> 144:ef7eb2e8f9f7 11 *
<> 144:ef7eb2e8f9f7 12 @verbatim
<> 144:ef7eb2e8f9f7 13 ==============================================================================
<> 144:ef7eb2e8f9f7 14 ##### Flash Extension features #####
<> 144:ef7eb2e8f9f7 15 ==============================================================================
<> 144:ef7eb2e8f9f7 16
<> 144:ef7eb2e8f9f7 17 [..] Comparing to other previous devices, the FLASH interface for STM32F427xx/437xx and
<> 144:ef7eb2e8f9f7 18 STM32F429xx/439xx devices contains the following additional features
<> 144:ef7eb2e8f9f7 19
<> 144:ef7eb2e8f9f7 20 (+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write
<> 144:ef7eb2e8f9f7 21 capability (RWW)
<> 144:ef7eb2e8f9f7 22 (+) Dual bank memory organization
<> 144:ef7eb2e8f9f7 23 (+) PCROP protection for all banks
<> 144:ef7eb2e8f9f7 24
<> 144:ef7eb2e8f9f7 25 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 26 ==============================================================================
<> 144:ef7eb2e8f9f7 27 [..] This driver provides functions to configure and program the FLASH memory
<> 144:ef7eb2e8f9f7 28 of all STM32F427xx/437xx, STM32F429xx/439xx, STM32F469xx/479xx and STM32F446xx
<> 144:ef7eb2e8f9f7 29 devices. It includes
<> 144:ef7eb2e8f9f7 30 (#) FLASH Memory Erase functions:
<> 144:ef7eb2e8f9f7 31 (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
<> 144:ef7eb2e8f9f7 32 HAL_FLASH_Lock() functions
<> 144:ef7eb2e8f9f7 33 (++) Erase function: Erase sector, erase all sectors
<> 144:ef7eb2e8f9f7 34 (++) There are two modes of erase :
<> 144:ef7eb2e8f9f7 35 (+++) Polling Mode using HAL_FLASHEx_Erase()
<> 144:ef7eb2e8f9f7 36 (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT()
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 (#) Option Bytes Programming functions: Use HAL_FLASHEx_OBProgram() to :
<> 144:ef7eb2e8f9f7 39 (++) Set/Reset the write protection
<> 144:ef7eb2e8f9f7 40 (++) Set the Read protection Level
<> 144:ef7eb2e8f9f7 41 (++) Set the BOR level
<> 144:ef7eb2e8f9f7 42 (++) Program the user Option Bytes
<> 144:ef7eb2e8f9f7 43 (#) Advanced Option Bytes Programming functions: Use HAL_FLASHEx_AdvOBProgram() to :
<> 144:ef7eb2e8f9f7 44 (++) Extended space (bank 2) erase function
<> 144:ef7eb2e8f9f7 45 (++) Full FLASH space (2 Mo) erase (bank 1 and bank 2)
<> 144:ef7eb2e8f9f7 46 (++) Dual Boot activation
<> 144:ef7eb2e8f9f7 47 (++) Write protection configuration for bank 2
<> 144:ef7eb2e8f9f7 48 (++) PCROP protection configuration and control for both banks
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 @endverbatim
<> 144:ef7eb2e8f9f7 51 ******************************************************************************
<> 144:ef7eb2e8f9f7 52 * @attention
<> 144:ef7eb2e8f9f7 53 *
<> 144:ef7eb2e8f9f7 54 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 55 *
<> 144:ef7eb2e8f9f7 56 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 57 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 58 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 59 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 60 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 61 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 62 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 63 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 64 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 65 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 66 *
<> 144:ef7eb2e8f9f7 67 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 68 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 69 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 70 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 71 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 72 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 73 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 74 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 75 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 76 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 77 *
<> 144:ef7eb2e8f9f7 78 ******************************************************************************
<> 144:ef7eb2e8f9f7 79 */
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 82 #include "stm32f4xx_hal.h"
<> 144:ef7eb2e8f9f7 83
<> 144:ef7eb2e8f9f7 84 /** @addtogroup STM32F4xx_HAL_Driver
<> 144:ef7eb2e8f9f7 85 * @{
<> 144:ef7eb2e8f9f7 86 */
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 /** @defgroup FLASHEx FLASHEx
<> 144:ef7eb2e8f9f7 89 * @brief FLASH HAL Extension module driver
<> 144:ef7eb2e8f9f7 90 * @{
<> 144:ef7eb2e8f9f7 91 */
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 #ifdef HAL_FLASH_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 96 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 97 /** @addtogroup FLASHEx_Private_Constants
<> 144:ef7eb2e8f9f7 98 * @{
<> 144:ef7eb2e8f9f7 99 */
<> 144:ef7eb2e8f9f7 100 #define FLASH_TIMEOUT_VALUE ((uint32_t)50000U)/* 50 s */
<> 144:ef7eb2e8f9f7 101 /**
<> 144:ef7eb2e8f9f7 102 * @}
<> 144:ef7eb2e8f9f7 103 */
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 106 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 107 /** @addtogroup FLASHEx_Private_Variables
<> 144:ef7eb2e8f9f7 108 * @{
<> 144:ef7eb2e8f9f7 109 */
<> 144:ef7eb2e8f9f7 110 extern FLASH_ProcessTypeDef pFlash;
<> 144:ef7eb2e8f9f7 111 /**
<> 144:ef7eb2e8f9f7 112 * @}
<> 144:ef7eb2e8f9f7 113 */
<> 144:ef7eb2e8f9f7 114
<> 144:ef7eb2e8f9f7 115 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 116 /** @addtogroup FLASHEx_Private_Functions
<> 144:ef7eb2e8f9f7 117 * @{
<> 144:ef7eb2e8f9f7 118 */
<> 144:ef7eb2e8f9f7 119 /* Option bytes control */
<> 144:ef7eb2e8f9f7 120 static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks);
<> 144:ef7eb2e8f9f7 121 static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks);
<> 144:ef7eb2e8f9f7 122 static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks);
<> 144:ef7eb2e8f9f7 123 static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level);
<> 144:ef7eb2e8f9f7 124 static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t Iwdg, uint8_t Stop, uint8_t Stdby);
<> 144:ef7eb2e8f9f7 125 static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level);
<> 144:ef7eb2e8f9f7 126 static uint8_t FLASH_OB_GetUser(void);
<> 144:ef7eb2e8f9f7 127 static uint16_t FLASH_OB_GetWRP(void);
<> 144:ef7eb2e8f9f7 128 static uint8_t FLASH_OB_GetRDP(void);
<> 144:ef7eb2e8f9f7 129 static uint8_t FLASH_OB_GetBOR(void);
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 #if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) ||\
<> 144:ef7eb2e8f9f7 132 defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
<> 144:ef7eb2e8f9f7 133 static HAL_StatusTypeDef FLASH_OB_EnablePCROP(uint32_t Sector);
<> 144:ef7eb2e8f9f7 134 static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t Sector);
<> 144:ef7eb2e8f9f7 135 #endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
<> 144:ef7eb2e8f9f7 138 static HAL_StatusTypeDef FLASH_OB_EnablePCROP(uint32_t SectorBank1, uint32_t SectorBank2, uint32_t Banks);
<> 144:ef7eb2e8f9f7 139 static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t SectorBank1, uint32_t SectorBank2, uint32_t Banks);
<> 144:ef7eb2e8f9f7 140 static HAL_StatusTypeDef FLASH_OB_BootConfig(uint8_t BootConfig);
<> 144:ef7eb2e8f9f7 141 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
<> 144:ef7eb2e8f9f7 142
<> 144:ef7eb2e8f9f7 143 extern HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
<> 144:ef7eb2e8f9f7 144 /**
<> 144:ef7eb2e8f9f7 145 * @}
<> 144:ef7eb2e8f9f7 146 */
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 149 /** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions
<> 144:ef7eb2e8f9f7 150 * @{
<> 144:ef7eb2e8f9f7 151 */
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153 /** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions
<> 144:ef7eb2e8f9f7 154 * @brief Extended IO operation functions
<> 144:ef7eb2e8f9f7 155 *
<> 144:ef7eb2e8f9f7 156 @verbatim
<> 144:ef7eb2e8f9f7 157 ===============================================================================
<> 144:ef7eb2e8f9f7 158 ##### Extended programming operation functions #####
<> 144:ef7eb2e8f9f7 159 ===============================================================================
<> 144:ef7eb2e8f9f7 160 [..]
<> 144:ef7eb2e8f9f7 161 This subsection provides a set of functions allowing to manage the Extension FLASH
<> 144:ef7eb2e8f9f7 162 programming operations.
<> 144:ef7eb2e8f9f7 163
<> 144:ef7eb2e8f9f7 164 @endverbatim
<> 144:ef7eb2e8f9f7 165 * @{
<> 144:ef7eb2e8f9f7 166 */
<> 144:ef7eb2e8f9f7 167 /**
<> 144:ef7eb2e8f9f7 168 * @brief Perform a mass erase or erase the specified FLASH memory sectors
<> 144:ef7eb2e8f9f7 169 * @param[in] pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that
<> 144:ef7eb2e8f9f7 170 * contains the configuration information for the erasing.
<> 144:ef7eb2e8f9f7 171 *
<> 144:ef7eb2e8f9f7 172 * @param[out] SectorError: pointer to variable that
<> 144:ef7eb2e8f9f7 173 * contains the configuration information on faulty sector in case of error
<> 144:ef7eb2e8f9f7 174 * (0xFFFFFFFFU means that all the sectors have been correctly erased)
<> 144:ef7eb2e8f9f7 175 *
<> 144:ef7eb2e8f9f7 176 * @retval HAL Status
<> 144:ef7eb2e8f9f7 177 */
<> 144:ef7eb2e8f9f7 178 HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError)
<> 144:ef7eb2e8f9f7 179 {
<> 144:ef7eb2e8f9f7 180 HAL_StatusTypeDef status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 181 uint32_t index = 0U;
<> 144:ef7eb2e8f9f7 182
<> 144:ef7eb2e8f9f7 183 /* Process Locked */
<> 144:ef7eb2e8f9f7 184 __HAL_LOCK(&pFlash);
<> 144:ef7eb2e8f9f7 185
<> 144:ef7eb2e8f9f7 186 /* Check the parameters */
<> 144:ef7eb2e8f9f7 187 assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
<> 144:ef7eb2e8f9f7 188
<> 144:ef7eb2e8f9f7 189 /* Wait for last operation to be completed */
<> 144:ef7eb2e8f9f7 190 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
<> 144:ef7eb2e8f9f7 191
<> 144:ef7eb2e8f9f7 192 if(status == HAL_OK)
<> 144:ef7eb2e8f9f7 193 {
<> 144:ef7eb2e8f9f7 194 /*Initialization of SectorError variable*/
<> 144:ef7eb2e8f9f7 195 *SectorError = 0xFFFFFFFFU;
<> 144:ef7eb2e8f9f7 196
<> 144:ef7eb2e8f9f7 197 if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
<> 144:ef7eb2e8f9f7 198 {
<> 144:ef7eb2e8f9f7 199 /*Mass erase to be done*/
<> 144:ef7eb2e8f9f7 200 FLASH_MassErase((uint8_t) pEraseInit->VoltageRange, pEraseInit->Banks);
<> 144:ef7eb2e8f9f7 201
<> 144:ef7eb2e8f9f7 202 /* Wait for last operation to be completed */
<> 144:ef7eb2e8f9f7 203 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
<> 144:ef7eb2e8f9f7 204
<> 144:ef7eb2e8f9f7 205 /* if the erase operation is completed, disable the MER Bit */
<> 144:ef7eb2e8f9f7 206 FLASH->CR &= (~FLASH_MER_BIT);
<> 144:ef7eb2e8f9f7 207 }
<> 144:ef7eb2e8f9f7 208 else
<> 144:ef7eb2e8f9f7 209 {
<> 144:ef7eb2e8f9f7 210 /* Check the parameters */
<> 144:ef7eb2e8f9f7 211 assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector));
<> 144:ef7eb2e8f9f7 212
<> 144:ef7eb2e8f9f7 213 /* Erase by sector by sector to be done*/
<> 144:ef7eb2e8f9f7 214 for(index = pEraseInit->Sector; index < (pEraseInit->NbSectors + pEraseInit->Sector); index++)
<> 144:ef7eb2e8f9f7 215 {
<> 144:ef7eb2e8f9f7 216 FLASH_Erase_Sector(index, (uint8_t) pEraseInit->VoltageRange);
<> 144:ef7eb2e8f9f7 217
<> 144:ef7eb2e8f9f7 218 /* Wait for last operation to be completed */
<> 144:ef7eb2e8f9f7 219 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
<> 144:ef7eb2e8f9f7 220
<> 144:ef7eb2e8f9f7 221 /* If the erase operation is completed, disable the SER and SNB Bits */
<> 144:ef7eb2e8f9f7 222 CLEAR_BIT(FLASH->CR, (FLASH_CR_SER | FLASH_CR_SNB));
<> 144:ef7eb2e8f9f7 223
<> 144:ef7eb2e8f9f7 224 if(status != HAL_OK)
<> 144:ef7eb2e8f9f7 225 {
<> 144:ef7eb2e8f9f7 226 /* In case of error, stop erase procedure and return the faulty sector*/
<> 144:ef7eb2e8f9f7 227 *SectorError = index;
<> 144:ef7eb2e8f9f7 228 break;
<> 144:ef7eb2e8f9f7 229 }
<> 144:ef7eb2e8f9f7 230 }
<> 144:ef7eb2e8f9f7 231 }
<> 144:ef7eb2e8f9f7 232 /* Flush the caches to be sure of the data consistency */
<> 144:ef7eb2e8f9f7 233 FLASH_FlushCaches();
<> 144:ef7eb2e8f9f7 234 }
<> 144:ef7eb2e8f9f7 235
<> 144:ef7eb2e8f9f7 236 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 237 __HAL_UNLOCK(&pFlash);
<> 144:ef7eb2e8f9f7 238
<> 144:ef7eb2e8f9f7 239 return status;
<> 144:ef7eb2e8f9f7 240 }
<> 144:ef7eb2e8f9f7 241
<> 144:ef7eb2e8f9f7 242 /**
<> 144:ef7eb2e8f9f7 243 * @brief Perform a mass erase or erase the specified FLASH memory sectors with interrupt enabled
<> 144:ef7eb2e8f9f7 244 * @param pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that
<> 144:ef7eb2e8f9f7 245 * contains the configuration information for the erasing.
<> 144:ef7eb2e8f9f7 246 *
<> 144:ef7eb2e8f9f7 247 * @retval HAL Status
<> 144:ef7eb2e8f9f7 248 */
<> 144:ef7eb2e8f9f7 249 HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
<> 144:ef7eb2e8f9f7 250 {
<> 144:ef7eb2e8f9f7 251 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 252
<> 144:ef7eb2e8f9f7 253 /* Process Locked */
<> 144:ef7eb2e8f9f7 254 __HAL_LOCK(&pFlash);
<> 144:ef7eb2e8f9f7 255
<> 144:ef7eb2e8f9f7 256 /* Check the parameters */
<> 144:ef7eb2e8f9f7 257 assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
<> 144:ef7eb2e8f9f7 258
<> 144:ef7eb2e8f9f7 259 /* Enable End of FLASH Operation interrupt */
<> 144:ef7eb2e8f9f7 260 __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP);
<> 144:ef7eb2e8f9f7 261
<> 144:ef7eb2e8f9f7 262 /* Enable Error source interrupt */
<> 144:ef7eb2e8f9f7 263 __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR);
<> 144:ef7eb2e8f9f7 264
<> 144:ef7eb2e8f9f7 265 /* Clear pending flags (if any) */
<> 144:ef7eb2e8f9f7 266 __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR |\
<> 144:ef7eb2e8f9f7 267 FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR| FLASH_FLAG_PGSERR);
<> 144:ef7eb2e8f9f7 268
<> 144:ef7eb2e8f9f7 269 if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
<> 144:ef7eb2e8f9f7 270 {
<> 144:ef7eb2e8f9f7 271 /*Mass erase to be done*/
<> 144:ef7eb2e8f9f7 272 pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE;
<> 144:ef7eb2e8f9f7 273 pFlash.Bank = pEraseInit->Banks;
<> 144:ef7eb2e8f9f7 274 FLASH_MassErase((uint8_t) pEraseInit->VoltageRange, pEraseInit->Banks);
<> 144:ef7eb2e8f9f7 275 }
<> 144:ef7eb2e8f9f7 276 else
<> 144:ef7eb2e8f9f7 277 {
<> 144:ef7eb2e8f9f7 278 /* Erase by sector to be done*/
<> 144:ef7eb2e8f9f7 279
<> 144:ef7eb2e8f9f7 280 /* Check the parameters */
<> 144:ef7eb2e8f9f7 281 assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector));
<> 144:ef7eb2e8f9f7 282
<> 144:ef7eb2e8f9f7 283 pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE;
<> 144:ef7eb2e8f9f7 284 pFlash.NbSectorsToErase = pEraseInit->NbSectors;
<> 144:ef7eb2e8f9f7 285 pFlash.Sector = pEraseInit->Sector;
<> 144:ef7eb2e8f9f7 286 pFlash.VoltageForErase = (uint8_t)pEraseInit->VoltageRange;
<> 144:ef7eb2e8f9f7 287
<> 144:ef7eb2e8f9f7 288 /*Erase 1st sector and wait for IT*/
<> 144:ef7eb2e8f9f7 289 FLASH_Erase_Sector(pEraseInit->Sector, pEraseInit->VoltageRange);
<> 144:ef7eb2e8f9f7 290 }
<> 144:ef7eb2e8f9f7 291
<> 144:ef7eb2e8f9f7 292 return status;
<> 144:ef7eb2e8f9f7 293 }
<> 144:ef7eb2e8f9f7 294
<> 144:ef7eb2e8f9f7 295 /**
<> 144:ef7eb2e8f9f7 296 * @brief Program option bytes
<> 144:ef7eb2e8f9f7 297 * @param pOBInit: pointer to an FLASH_OBInitStruct structure that
<> 144:ef7eb2e8f9f7 298 * contains the configuration information for the programming.
<> 144:ef7eb2e8f9f7 299 *
<> 144:ef7eb2e8f9f7 300 * @retval HAL Status
<> 144:ef7eb2e8f9f7 301 */
<> 144:ef7eb2e8f9f7 302 HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
<> 144:ef7eb2e8f9f7 303 {
<> 144:ef7eb2e8f9f7 304 HAL_StatusTypeDef status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 305
<> 144:ef7eb2e8f9f7 306 /* Process Locked */
<> 144:ef7eb2e8f9f7 307 __HAL_LOCK(&pFlash);
<> 144:ef7eb2e8f9f7 308
<> 144:ef7eb2e8f9f7 309 /* Check the parameters */
<> 144:ef7eb2e8f9f7 310 assert_param(IS_OPTIONBYTE(pOBInit->OptionType));
<> 144:ef7eb2e8f9f7 311
<> 144:ef7eb2e8f9f7 312 /*Write protection configuration*/
<> 144:ef7eb2e8f9f7 313 if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP)
<> 144:ef7eb2e8f9f7 314 {
<> 144:ef7eb2e8f9f7 315 assert_param(IS_WRPSTATE(pOBInit->WRPState));
<> 144:ef7eb2e8f9f7 316 if(pOBInit->WRPState == OB_WRPSTATE_ENABLE)
<> 144:ef7eb2e8f9f7 317 {
<> 144:ef7eb2e8f9f7 318 /*Enable of Write protection on the selected Sector*/
<> 144:ef7eb2e8f9f7 319 status = FLASH_OB_EnableWRP(pOBInit->WRPSector, pOBInit->Banks);
<> 144:ef7eb2e8f9f7 320 }
<> 144:ef7eb2e8f9f7 321 else
<> 144:ef7eb2e8f9f7 322 {
<> 144:ef7eb2e8f9f7 323 /*Disable of Write protection on the selected Sector*/
<> 144:ef7eb2e8f9f7 324 status = FLASH_OB_DisableWRP(pOBInit->WRPSector, pOBInit->Banks);
<> 144:ef7eb2e8f9f7 325 }
<> 144:ef7eb2e8f9f7 326 }
<> 144:ef7eb2e8f9f7 327
<> 144:ef7eb2e8f9f7 328 /*Read protection configuration*/
<> 144:ef7eb2e8f9f7 329 if((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP)
<> 144:ef7eb2e8f9f7 330 {
<> 144:ef7eb2e8f9f7 331 status = FLASH_OB_RDP_LevelConfig(pOBInit->RDPLevel);
<> 144:ef7eb2e8f9f7 332 }
<> 144:ef7eb2e8f9f7 333
<> 144:ef7eb2e8f9f7 334 /*USER configuration*/
<> 144:ef7eb2e8f9f7 335 if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER)
<> 144:ef7eb2e8f9f7 336 {
<> 144:ef7eb2e8f9f7 337 status = FLASH_OB_UserConfig(pOBInit->USERConfig&OB_IWDG_SW,
<> 144:ef7eb2e8f9f7 338 pOBInit->USERConfig&OB_STOP_NO_RST,
<> 144:ef7eb2e8f9f7 339 pOBInit->USERConfig&OB_STDBY_NO_RST);
<> 144:ef7eb2e8f9f7 340 }
<> 144:ef7eb2e8f9f7 341
<> 144:ef7eb2e8f9f7 342 /*BOR Level configuration*/
<> 144:ef7eb2e8f9f7 343 if((pOBInit->OptionType & OPTIONBYTE_BOR) == OPTIONBYTE_BOR)
<> 144:ef7eb2e8f9f7 344 {
<> 144:ef7eb2e8f9f7 345 status = FLASH_OB_BOR_LevelConfig(pOBInit->BORLevel);
<> 144:ef7eb2e8f9f7 346 }
<> 144:ef7eb2e8f9f7 347
<> 144:ef7eb2e8f9f7 348 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 349 __HAL_UNLOCK(&pFlash);
<> 144:ef7eb2e8f9f7 350
<> 144:ef7eb2e8f9f7 351 return status;
<> 144:ef7eb2e8f9f7 352 }
<> 144:ef7eb2e8f9f7 353
<> 144:ef7eb2e8f9f7 354 /**
<> 144:ef7eb2e8f9f7 355 * @brief Get the Option byte configuration
<> 144:ef7eb2e8f9f7 356 * @param pOBInit: pointer to an FLASH_OBInitStruct structure that
<> 144:ef7eb2e8f9f7 357 * contains the configuration information for the programming.
<> 144:ef7eb2e8f9f7 358 *
<> 144:ef7eb2e8f9f7 359 * @retval None
<> 144:ef7eb2e8f9f7 360 */
<> 144:ef7eb2e8f9f7 361 void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
<> 144:ef7eb2e8f9f7 362 {
<> 144:ef7eb2e8f9f7 363 pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_BOR;
<> 144:ef7eb2e8f9f7 364
<> 144:ef7eb2e8f9f7 365 /*Get WRP*/
<> 144:ef7eb2e8f9f7 366 pOBInit->WRPSector = (uint32_t)FLASH_OB_GetWRP();
<> 144:ef7eb2e8f9f7 367
<> 144:ef7eb2e8f9f7 368 /*Get RDP Level*/
<> 144:ef7eb2e8f9f7 369 pOBInit->RDPLevel = (uint32_t)FLASH_OB_GetRDP();
<> 144:ef7eb2e8f9f7 370
<> 144:ef7eb2e8f9f7 371 /*Get USER*/
<> 144:ef7eb2e8f9f7 372 pOBInit->USERConfig = (uint8_t)FLASH_OB_GetUser();
<> 144:ef7eb2e8f9f7 373
<> 144:ef7eb2e8f9f7 374 /*Get BOR Level*/
<> 144:ef7eb2e8f9f7 375 pOBInit->BORLevel = (uint32_t)FLASH_OB_GetBOR();
<> 144:ef7eb2e8f9f7 376 }
<> 144:ef7eb2e8f9f7 377
<> 144:ef7eb2e8f9f7 378 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
<> 144:ef7eb2e8f9f7 379 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
<> 144:ef7eb2e8f9f7 380 defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
<> 144:ef7eb2e8f9f7 381 defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
<> 144:ef7eb2e8f9f7 382 defined(STM32F412Cx)
<> 144:ef7eb2e8f9f7 383 /**
<> 144:ef7eb2e8f9f7 384 * @brief Program option bytes
<> 144:ef7eb2e8f9f7 385 * @param pAdvOBInit: pointer to an FLASH_AdvOBProgramInitTypeDef structure that
<> 144:ef7eb2e8f9f7 386 * contains the configuration information for the programming.
<> 144:ef7eb2e8f9f7 387 *
<> 144:ef7eb2e8f9f7 388 * @retval HAL Status
<> 144:ef7eb2e8f9f7 389 */
<> 144:ef7eb2e8f9f7 390 HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvOBInit)
<> 144:ef7eb2e8f9f7 391 {
<> 144:ef7eb2e8f9f7 392 HAL_StatusTypeDef status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 393
<> 144:ef7eb2e8f9f7 394 /* Check the parameters */
<> 144:ef7eb2e8f9f7 395 assert_param(IS_OBEX(pAdvOBInit->OptionType));
<> 144:ef7eb2e8f9f7 396
<> 144:ef7eb2e8f9f7 397 /*Program PCROP option byte*/
<> 144:ef7eb2e8f9f7 398 if(((pAdvOBInit->OptionType) & OPTIONBYTE_PCROP) == OPTIONBYTE_PCROP)
<> 144:ef7eb2e8f9f7 399 {
<> 144:ef7eb2e8f9f7 400 /* Check the parameters */
<> 144:ef7eb2e8f9f7 401 assert_param(IS_PCROPSTATE(pAdvOBInit->PCROPState));
<> 144:ef7eb2e8f9f7 402 if((pAdvOBInit->PCROPState) == OB_PCROP_STATE_ENABLE)
<> 144:ef7eb2e8f9f7 403 {
<> 144:ef7eb2e8f9f7 404 /*Enable of Write protection on the selected Sector*/
<> 144:ef7eb2e8f9f7 405 #if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\
<> 144:ef7eb2e8f9f7 406 defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
<> 144:ef7eb2e8f9f7 407 defined(STM32F412Cx)
<> 144:ef7eb2e8f9f7 408 status = FLASH_OB_EnablePCROP(pAdvOBInit->Sectors);
<> 144:ef7eb2e8f9f7 409 #else /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
<> 144:ef7eb2e8f9f7 410 status = FLASH_OB_EnablePCROP(pAdvOBInit->SectorsBank1, pAdvOBInit->SectorsBank2, pAdvOBInit->Banks);
<> 144:ef7eb2e8f9f7 411 #endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
<> 144:ef7eb2e8f9f7 412 }
<> 144:ef7eb2e8f9f7 413 else
<> 144:ef7eb2e8f9f7 414 {
<> 144:ef7eb2e8f9f7 415 /*Disable of Write protection on the selected Sector*/
<> 144:ef7eb2e8f9f7 416 #if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\
<> 144:ef7eb2e8f9f7 417 defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
<> 144:ef7eb2e8f9f7 418 defined(STM32F412Cx)
<> 144:ef7eb2e8f9f7 419 status = FLASH_OB_DisablePCROP(pAdvOBInit->Sectors);
<> 144:ef7eb2e8f9f7 420 #else /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
<> 144:ef7eb2e8f9f7 421 status = FLASH_OB_DisablePCROP(pAdvOBInit->SectorsBank1, pAdvOBInit->SectorsBank2, pAdvOBInit->Banks);
<> 144:ef7eb2e8f9f7 422 #endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
<> 144:ef7eb2e8f9f7 423 }
<> 144:ef7eb2e8f9f7 424 }
<> 144:ef7eb2e8f9f7 425
<> 144:ef7eb2e8f9f7 426 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
<> 144:ef7eb2e8f9f7 427 /*Program BOOT config option byte*/
<> 144:ef7eb2e8f9f7 428 if(((pAdvOBInit->OptionType) & OPTIONBYTE_BOOTCONFIG) == OPTIONBYTE_BOOTCONFIG)
<> 144:ef7eb2e8f9f7 429 {
<> 144:ef7eb2e8f9f7 430 status = FLASH_OB_BootConfig(pAdvOBInit->BootConfig);
<> 144:ef7eb2e8f9f7 431 }
<> 144:ef7eb2e8f9f7 432 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
<> 144:ef7eb2e8f9f7 433
<> 144:ef7eb2e8f9f7 434 return status;
<> 144:ef7eb2e8f9f7 435 }
<> 144:ef7eb2e8f9f7 436
<> 144:ef7eb2e8f9f7 437 /**
<> 144:ef7eb2e8f9f7 438 * @brief Get the OBEX byte configuration
<> 144:ef7eb2e8f9f7 439 * @param pAdvOBInit: pointer to an FLASH_AdvOBProgramInitTypeDef structure that
<> 144:ef7eb2e8f9f7 440 * contains the configuration information for the programming.
<> 144:ef7eb2e8f9f7 441 *
<> 144:ef7eb2e8f9f7 442 * @retval None
<> 144:ef7eb2e8f9f7 443 */
<> 144:ef7eb2e8f9f7 444 void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit)
<> 144:ef7eb2e8f9f7 445 {
<> 144:ef7eb2e8f9f7 446 #if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\
<> 144:ef7eb2e8f9f7 447 defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
<> 144:ef7eb2e8f9f7 448 defined(STM32F412Cx)
<> 144:ef7eb2e8f9f7 449 /*Get Sector*/
<> 144:ef7eb2e8f9f7 450 pAdvOBInit->Sectors = (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS));
<> 144:ef7eb2e8f9f7 451 #else /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
<> 144:ef7eb2e8f9f7 452 /*Get Sector for Bank1*/
<> 144:ef7eb2e8f9f7 453 pAdvOBInit->SectorsBank1 = (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS));
<> 144:ef7eb2e8f9f7 454
<> 144:ef7eb2e8f9f7 455 /*Get Sector for Bank2*/
<> 144:ef7eb2e8f9f7 456 pAdvOBInit->SectorsBank2 = (*(__IO uint16_t *)(OPTCR1_BYTE2_ADDRESS));
<> 144:ef7eb2e8f9f7 457
<> 144:ef7eb2e8f9f7 458 /*Get Boot config OB*/
<> 144:ef7eb2e8f9f7 459 pAdvOBInit->BootConfig = *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS;
<> 144:ef7eb2e8f9f7 460 #endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
<> 144:ef7eb2e8f9f7 461 }
<> 144:ef7eb2e8f9f7 462
<> 144:ef7eb2e8f9f7 463 /**
<> 144:ef7eb2e8f9f7 464 * @brief Select the Protection Mode
<> 144:ef7eb2e8f9f7 465 *
<> 144:ef7eb2e8f9f7 466 * @note After PCROP activated Option Byte modification NOT POSSIBLE! excepted
<> 144:ef7eb2e8f9f7 467 * Global Read Out Protection modification (from level1 to level0)
<> 144:ef7eb2e8f9f7 468 * @note Once SPRMOD bit is active unprotection of a protected sector is not possible
<> 144:ef7eb2e8f9f7 469 * @note Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag
<> 144:ef7eb2e8f9f7 470 * @note This function can be used only for STM32F42xxx/STM32F43xxx/STM32F401xx/STM32F411xx/STM32F446xx/
<> 144:ef7eb2e8f9f7 471 * STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices.
<> 144:ef7eb2e8f9f7 472 *
<> 144:ef7eb2e8f9f7 473 * @retval HAL Status
<> 144:ef7eb2e8f9f7 474 */
<> 144:ef7eb2e8f9f7 475 HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void)
<> 144:ef7eb2e8f9f7 476 {
<> 144:ef7eb2e8f9f7 477 uint8_t optiontmp = 0xFFU;
<> 144:ef7eb2e8f9f7 478
<> 144:ef7eb2e8f9f7 479 /* Mask SPRMOD bit */
<> 144:ef7eb2e8f9f7 480 optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE3_ADDRESS) & (uint8_t)0x7FU);
<> 144:ef7eb2e8f9f7 481
<> 144:ef7eb2e8f9f7 482 /* Update Option Byte */
<> 144:ef7eb2e8f9f7 483 *(__IO uint8_t *)OPTCR_BYTE3_ADDRESS = (uint8_t)(OB_PCROP_SELECTED | optiontmp);
<> 144:ef7eb2e8f9f7 484
<> 144:ef7eb2e8f9f7 485 return HAL_OK;
<> 144:ef7eb2e8f9f7 486 }
<> 144:ef7eb2e8f9f7 487
<> 144:ef7eb2e8f9f7 488 /**
<> 144:ef7eb2e8f9f7 489 * @brief Deselect the Protection Mode
<> 144:ef7eb2e8f9f7 490 *
<> 144:ef7eb2e8f9f7 491 * @note After PCROP activated Option Byte modification NOT POSSIBLE! excepted
<> 144:ef7eb2e8f9f7 492 * Global Read Out Protection modification (from level1 to level0)
<> 144:ef7eb2e8f9f7 493 * @note Once SPRMOD bit is active unprotection of a protected sector is not possible
<> 144:ef7eb2e8f9f7 494 * @note Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag
<> 144:ef7eb2e8f9f7 495 * @note This function can be used only for STM32F42xxx/STM32F43xxx/STM32F401xx/STM32F411xx/STM32F446xx/
<> 144:ef7eb2e8f9f7 496 * STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices.
<> 144:ef7eb2e8f9f7 497 *
<> 144:ef7eb2e8f9f7 498 * @retval HAL Status
<> 144:ef7eb2e8f9f7 499 */
<> 144:ef7eb2e8f9f7 500 HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void)
<> 144:ef7eb2e8f9f7 501 {
<> 144:ef7eb2e8f9f7 502 uint8_t optiontmp = 0xFFU;
<> 144:ef7eb2e8f9f7 503
<> 144:ef7eb2e8f9f7 504 /* Mask SPRMOD bit */
<> 144:ef7eb2e8f9f7 505 optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE3_ADDRESS) & (uint8_t)0x7FU);
<> 144:ef7eb2e8f9f7 506
<> 144:ef7eb2e8f9f7 507 /* Update Option Byte */
<> 144:ef7eb2e8f9f7 508 *(__IO uint8_t *)OPTCR_BYTE3_ADDRESS = (uint8_t)(OB_PCROP_DESELECTED | optiontmp);
<> 144:ef7eb2e8f9f7 509
<> 144:ef7eb2e8f9f7 510 return HAL_OK;
<> 144:ef7eb2e8f9f7 511 }
<> 144:ef7eb2e8f9f7 512 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F410xx ||\
<> 144:ef7eb2e8f9f7 513 STM32F411xE || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
<> 144:ef7eb2e8f9f7 514
<> 144:ef7eb2e8f9f7 515 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
<> 144:ef7eb2e8f9f7 516 /**
<> 144:ef7eb2e8f9f7 517 * @brief Returns the FLASH Write Protection Option Bytes value for Bank 2
<> 144:ef7eb2e8f9f7 518 * @note This function can be used only for STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx devices.
<> 144:ef7eb2e8f9f7 519 * @retval The FLASH Write Protection Option Bytes value
<> 144:ef7eb2e8f9f7 520 */
<> 144:ef7eb2e8f9f7 521 uint16_t HAL_FLASHEx_OB_GetBank2WRP(void)
<> 144:ef7eb2e8f9f7 522 {
<> 144:ef7eb2e8f9f7 523 /* Return the FLASH write protection Register value */
<> 144:ef7eb2e8f9f7 524 return (*(__IO uint16_t *)(OPTCR1_BYTE2_ADDRESS));
<> 144:ef7eb2e8f9f7 525 }
<> 144:ef7eb2e8f9f7 526 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
<> 144:ef7eb2e8f9f7 527
<> 144:ef7eb2e8f9f7 528 /**
<> 144:ef7eb2e8f9f7 529 * @}
<> 144:ef7eb2e8f9f7 530 */
<> 144:ef7eb2e8f9f7 531
<> 144:ef7eb2e8f9f7 532 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
<> 144:ef7eb2e8f9f7 533 /**
<> 144:ef7eb2e8f9f7 534 * @brief Full erase of FLASH memory sectors
<> 144:ef7eb2e8f9f7 535 * @param VoltageRange: The device voltage range which defines the erase parallelism.
<> 144:ef7eb2e8f9f7 536 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 537 * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V,
<> 144:ef7eb2e8f9f7 538 * the operation will be done by byte (8-bit)
<> 144:ef7eb2e8f9f7 539 * @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
<> 144:ef7eb2e8f9f7 540 * the operation will be done by half word (16-bit)
<> 144:ef7eb2e8f9f7 541 * @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
<> 144:ef7eb2e8f9f7 542 * the operation will be done by word (32-bit)
<> 144:ef7eb2e8f9f7 543 * @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
<> 144:ef7eb2e8f9f7 544 * the operation will be done by double word (64-bit)
<> 144:ef7eb2e8f9f7 545 *
<> 144:ef7eb2e8f9f7 546 * @param Banks: Banks to be erased
<> 144:ef7eb2e8f9f7 547 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 548 * @arg FLASH_BANK_1: Bank1 to be erased
<> 144:ef7eb2e8f9f7 549 * @arg FLASH_BANK_2: Bank2 to be erased
<> 144:ef7eb2e8f9f7 550 * @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased
<> 144:ef7eb2e8f9f7 551 *
<> 144:ef7eb2e8f9f7 552 * @retval HAL Status
<> 144:ef7eb2e8f9f7 553 */
<> 144:ef7eb2e8f9f7 554 static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks)
<> 144:ef7eb2e8f9f7 555 {
<> 144:ef7eb2e8f9f7 556 /* Check the parameters */
<> 144:ef7eb2e8f9f7 557 assert_param(IS_VOLTAGERANGE(VoltageRange));
<> 144:ef7eb2e8f9f7 558 assert_param(IS_FLASH_BANK(Banks));
<> 144:ef7eb2e8f9f7 559
<> 144:ef7eb2e8f9f7 560 /* if the previous operation is completed, proceed to erase all sectors */
<> 144:ef7eb2e8f9f7 561 CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
<> 144:ef7eb2e8f9f7 562
<> 144:ef7eb2e8f9f7 563 if(Banks == FLASH_BANK_BOTH)
<> 144:ef7eb2e8f9f7 564 {
<> 144:ef7eb2e8f9f7 565 /* bank1 & bank2 will be erased*/
<> 144:ef7eb2e8f9f7 566 FLASH->CR |= FLASH_MER_BIT;
<> 144:ef7eb2e8f9f7 567 }
<> 144:ef7eb2e8f9f7 568 else if(Banks == FLASH_BANK_1)
<> 144:ef7eb2e8f9f7 569 {
<> 144:ef7eb2e8f9f7 570 /*Only bank1 will be erased*/
<> 144:ef7eb2e8f9f7 571 FLASH->CR |= FLASH_CR_MER1;
<> 144:ef7eb2e8f9f7 572 }
<> 144:ef7eb2e8f9f7 573 else
<> 144:ef7eb2e8f9f7 574 {
<> 144:ef7eb2e8f9f7 575 /*Only bank2 will be erased*/
<> 144:ef7eb2e8f9f7 576 FLASH->CR |= FLASH_CR_MER2;
<> 144:ef7eb2e8f9f7 577 }
<> 144:ef7eb2e8f9f7 578 FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange <<8U);
<> 144:ef7eb2e8f9f7 579 }
<> 144:ef7eb2e8f9f7 580
<> 144:ef7eb2e8f9f7 581 /**
<> 144:ef7eb2e8f9f7 582 * @brief Erase the specified FLASH memory sector
<> 144:ef7eb2e8f9f7 583 * @param Sector: FLASH sector to erase
<> 144:ef7eb2e8f9f7 584 * The value of this parameter depend on device used within the same series
<> 144:ef7eb2e8f9f7 585 * @param VoltageRange: The device voltage range which defines the erase parallelism.
<> 144:ef7eb2e8f9f7 586 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 587 * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V,
<> 144:ef7eb2e8f9f7 588 * the operation will be done by byte (8-bit)
<> 144:ef7eb2e8f9f7 589 * @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
<> 144:ef7eb2e8f9f7 590 * the operation will be done by half word (16-bit)
<> 144:ef7eb2e8f9f7 591 * @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
<> 144:ef7eb2e8f9f7 592 * the operation will be done by word (32-bit)
<> 144:ef7eb2e8f9f7 593 * @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
<> 144:ef7eb2e8f9f7 594 * the operation will be done by double word (64-bit)
<> 144:ef7eb2e8f9f7 595 *
<> 144:ef7eb2e8f9f7 596 * @retval None
<> 144:ef7eb2e8f9f7 597 */
<> 144:ef7eb2e8f9f7 598 void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange)
<> 144:ef7eb2e8f9f7 599 {
<> 144:ef7eb2e8f9f7 600 uint32_t tmp_psize = 0U;
<> 144:ef7eb2e8f9f7 601
<> 144:ef7eb2e8f9f7 602 /* Check the parameters */
<> 144:ef7eb2e8f9f7 603 assert_param(IS_FLASH_SECTOR(Sector));
<> 144:ef7eb2e8f9f7 604 assert_param(IS_VOLTAGERANGE(VoltageRange));
<> 144:ef7eb2e8f9f7 605
<> 144:ef7eb2e8f9f7 606 if(VoltageRange == FLASH_VOLTAGE_RANGE_1)
<> 144:ef7eb2e8f9f7 607 {
<> 144:ef7eb2e8f9f7 608 tmp_psize = FLASH_PSIZE_BYTE;
<> 144:ef7eb2e8f9f7 609 }
<> 144:ef7eb2e8f9f7 610 else if(VoltageRange == FLASH_VOLTAGE_RANGE_2)
<> 144:ef7eb2e8f9f7 611 {
<> 144:ef7eb2e8f9f7 612 tmp_psize = FLASH_PSIZE_HALF_WORD;
<> 144:ef7eb2e8f9f7 613 }
<> 144:ef7eb2e8f9f7 614 else if(VoltageRange == FLASH_VOLTAGE_RANGE_3)
<> 144:ef7eb2e8f9f7 615 {
<> 144:ef7eb2e8f9f7 616 tmp_psize = FLASH_PSIZE_WORD;
<> 144:ef7eb2e8f9f7 617 }
<> 144:ef7eb2e8f9f7 618 else
<> 144:ef7eb2e8f9f7 619 {
<> 144:ef7eb2e8f9f7 620 tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
<> 144:ef7eb2e8f9f7 621 }
<> 144:ef7eb2e8f9f7 622
<> 144:ef7eb2e8f9f7 623 /* Need to add offset of 4 when sector higher than FLASH_SECTOR_11 */
<> 144:ef7eb2e8f9f7 624 if(Sector > FLASH_SECTOR_11)
<> 144:ef7eb2e8f9f7 625 {
<> 144:ef7eb2e8f9f7 626 Sector += 4U;
<> 144:ef7eb2e8f9f7 627 }
<> 144:ef7eb2e8f9f7 628 /* If the previous operation is completed, proceed to erase the sector */
<> 144:ef7eb2e8f9f7 629 CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
<> 144:ef7eb2e8f9f7 630 FLASH->CR |= tmp_psize;
<> 144:ef7eb2e8f9f7 631 CLEAR_BIT(FLASH->CR, FLASH_CR_SNB);
<> 144:ef7eb2e8f9f7 632 FLASH->CR |= FLASH_CR_SER | (Sector << POSITION_VAL(FLASH_CR_SNB));
<> 144:ef7eb2e8f9f7 633 FLASH->CR |= FLASH_CR_STRT;
<> 144:ef7eb2e8f9f7 634 }
<> 144:ef7eb2e8f9f7 635
<> 144:ef7eb2e8f9f7 636 /**
<> 144:ef7eb2e8f9f7 637 * @brief Enable the write protection of the desired bank1 or bank 2 sectors
<> 144:ef7eb2e8f9f7 638 *
<> 144:ef7eb2e8f9f7 639 * @note When the memory read protection level is selected (RDP level = 1),
<> 144:ef7eb2e8f9f7 640 * it is not possible to program or erase the flash sector i if CortexM4
<> 144:ef7eb2e8f9f7 641 * debug features are connected or boot code is executed in RAM, even if nWRPi = 1
<> 144:ef7eb2e8f9f7 642 * @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1).
<> 144:ef7eb2e8f9f7 643 *
<> 144:ef7eb2e8f9f7 644 * @param WRPSector: specifies the sector(s) to be write protected.
<> 144:ef7eb2e8f9f7 645 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 646 * @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_23
<> 144:ef7eb2e8f9f7 647 * @arg OB_WRP_SECTOR_All
<> 144:ef7eb2e8f9f7 648 * @note BANK2 starts from OB_WRP_SECTOR_12
<> 144:ef7eb2e8f9f7 649 *
<> 144:ef7eb2e8f9f7 650 * @param Banks: Enable write protection on all the sectors for the specific bank
<> 144:ef7eb2e8f9f7 651 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 652 * @arg FLASH_BANK_1: WRP on all sectors of bank1
<> 144:ef7eb2e8f9f7 653 * @arg FLASH_BANK_2: WRP on all sectors of bank2
<> 144:ef7eb2e8f9f7 654 * @arg FLASH_BANK_BOTH: WRP on all sectors of bank1 & bank2
<> 144:ef7eb2e8f9f7 655 *
<> 144:ef7eb2e8f9f7 656 * @retval HAL FLASH State
<> 144:ef7eb2e8f9f7 657 */
<> 144:ef7eb2e8f9f7 658 static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks)
<> 144:ef7eb2e8f9f7 659 {
<> 144:ef7eb2e8f9f7 660 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 661
<> 144:ef7eb2e8f9f7 662 /* Check the parameters */
<> 144:ef7eb2e8f9f7 663 assert_param(IS_OB_WRP_SECTOR(WRPSector));
<> 144:ef7eb2e8f9f7 664 assert_param(IS_FLASH_BANK(Banks));
<> 144:ef7eb2e8f9f7 665
<> 144:ef7eb2e8f9f7 666 /* Wait for last operation to be completed */
<> 144:ef7eb2e8f9f7 667 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
<> 144:ef7eb2e8f9f7 668
<> 144:ef7eb2e8f9f7 669 if(status == HAL_OK)
<> 144:ef7eb2e8f9f7 670 {
<> 144:ef7eb2e8f9f7 671 if(((WRPSector == OB_WRP_SECTOR_All) && ((Banks == FLASH_BANK_1) || (Banks == FLASH_BANK_BOTH))) ||
<> 144:ef7eb2e8f9f7 672 (WRPSector < OB_WRP_SECTOR_12))
<> 144:ef7eb2e8f9f7 673 {
<> 144:ef7eb2e8f9f7 674 if(WRPSector == OB_WRP_SECTOR_All)
<> 144:ef7eb2e8f9f7 675 {
<> 144:ef7eb2e8f9f7 676 /*Write protection on all sector of BANK1*/
<> 144:ef7eb2e8f9f7 677 *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~(WRPSector>>12U));
<> 144:ef7eb2e8f9f7 678 }
<> 144:ef7eb2e8f9f7 679 else
<> 144:ef7eb2e8f9f7 680 {
<> 144:ef7eb2e8f9f7 681 /*Write protection done on sectors of BANK1*/
<> 144:ef7eb2e8f9f7 682 *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~WRPSector);
<> 144:ef7eb2e8f9f7 683 }
<> 144:ef7eb2e8f9f7 684 }
<> 144:ef7eb2e8f9f7 685 else
<> 144:ef7eb2e8f9f7 686 {
<> 144:ef7eb2e8f9f7 687 /*Write protection done on sectors of BANK2*/
<> 144:ef7eb2e8f9f7 688 *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS &= (~(WRPSector>>12U));
<> 144:ef7eb2e8f9f7 689 }
<> 144:ef7eb2e8f9f7 690
<> 144:ef7eb2e8f9f7 691 /*Write protection on all sector of BANK2*/
<> 144:ef7eb2e8f9f7 692 if((WRPSector == OB_WRP_SECTOR_All) && (Banks == FLASH_BANK_BOTH))
<> 144:ef7eb2e8f9f7 693 {
<> 144:ef7eb2e8f9f7 694 /* Wait for last operation to be completed */
<> 144:ef7eb2e8f9f7 695 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
<> 144:ef7eb2e8f9f7 696
<> 144:ef7eb2e8f9f7 697 if(status == HAL_OK)
<> 144:ef7eb2e8f9f7 698 {
<> 144:ef7eb2e8f9f7 699 *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS &= (~(WRPSector>>12U));
<> 144:ef7eb2e8f9f7 700 }
<> 144:ef7eb2e8f9f7 701 }
<> 144:ef7eb2e8f9f7 702
<> 144:ef7eb2e8f9f7 703 }
<> 144:ef7eb2e8f9f7 704 return status;
<> 144:ef7eb2e8f9f7 705 }
<> 144:ef7eb2e8f9f7 706
<> 144:ef7eb2e8f9f7 707 /**
<> 144:ef7eb2e8f9f7 708 * @brief Disable the write protection of the desired bank1 or bank 2 sectors
<> 144:ef7eb2e8f9f7 709 *
<> 144:ef7eb2e8f9f7 710 * @note When the memory read protection level is selected (RDP level = 1),
<> 144:ef7eb2e8f9f7 711 * it is not possible to program or erase the flash sector i if CortexM4
<> 144:ef7eb2e8f9f7 712 * debug features are connected or boot code is executed in RAM, even if nWRPi = 1
<> 144:ef7eb2e8f9f7 713 * @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1).
<> 144:ef7eb2e8f9f7 714 *
<> 144:ef7eb2e8f9f7 715 * @param WRPSector: specifies the sector(s) to be write protected.
<> 144:ef7eb2e8f9f7 716 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 717 * @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_23
<> 144:ef7eb2e8f9f7 718 * @arg OB_WRP_Sector_All
<> 144:ef7eb2e8f9f7 719 * @note BANK2 starts from OB_WRP_SECTOR_12
<> 144:ef7eb2e8f9f7 720 *
<> 144:ef7eb2e8f9f7 721 * @param Banks: Disable write protection on all the sectors for the specific bank
<> 144:ef7eb2e8f9f7 722 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 723 * @arg FLASH_BANK_1: Bank1 to be erased
<> 144:ef7eb2e8f9f7 724 * @arg FLASH_BANK_2: Bank2 to be erased
<> 144:ef7eb2e8f9f7 725 * @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased
<> 144:ef7eb2e8f9f7 726 *
<> 144:ef7eb2e8f9f7 727 * @retval HAL Status
<> 144:ef7eb2e8f9f7 728 */
<> 144:ef7eb2e8f9f7 729 static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks)
<> 144:ef7eb2e8f9f7 730 {
<> 144:ef7eb2e8f9f7 731 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 732
<> 144:ef7eb2e8f9f7 733 /* Check the parameters */
<> 144:ef7eb2e8f9f7 734 assert_param(IS_OB_WRP_SECTOR(WRPSector));
<> 144:ef7eb2e8f9f7 735 assert_param(IS_FLASH_BANK(Banks));
<> 144:ef7eb2e8f9f7 736
<> 144:ef7eb2e8f9f7 737 /* Wait for last operation to be completed */
<> 144:ef7eb2e8f9f7 738 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
<> 144:ef7eb2e8f9f7 739
<> 144:ef7eb2e8f9f7 740 if(status == HAL_OK)
<> 144:ef7eb2e8f9f7 741 {
<> 144:ef7eb2e8f9f7 742 if(((WRPSector == OB_WRP_SECTOR_All) && ((Banks == FLASH_BANK_1) || (Banks == FLASH_BANK_BOTH))) ||
<> 144:ef7eb2e8f9f7 743 (WRPSector < OB_WRP_SECTOR_12))
<> 144:ef7eb2e8f9f7 744 {
<> 144:ef7eb2e8f9f7 745 if(WRPSector == OB_WRP_SECTOR_All)
<> 144:ef7eb2e8f9f7 746 {
<> 144:ef7eb2e8f9f7 747 /*Write protection on all sector of BANK1*/
<> 144:ef7eb2e8f9f7 748 *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)(WRPSector>>12U);
<> 144:ef7eb2e8f9f7 749 }
<> 144:ef7eb2e8f9f7 750 else
<> 144:ef7eb2e8f9f7 751 {
<> 144:ef7eb2e8f9f7 752 /*Write protection done on sectors of BANK1*/
<> 144:ef7eb2e8f9f7 753 *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)WRPSector;
<> 144:ef7eb2e8f9f7 754 }
<> 144:ef7eb2e8f9f7 755 }
<> 144:ef7eb2e8f9f7 756 else
<> 144:ef7eb2e8f9f7 757 {
<> 144:ef7eb2e8f9f7 758 /*Write protection done on sectors of BANK2*/
<> 144:ef7eb2e8f9f7 759 *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS |= (uint16_t)(WRPSector>>12U);
<> 144:ef7eb2e8f9f7 760 }
<> 144:ef7eb2e8f9f7 761
<> 144:ef7eb2e8f9f7 762 /*Write protection on all sector of BANK2*/
<> 144:ef7eb2e8f9f7 763 if((WRPSector == OB_WRP_SECTOR_All) && (Banks == FLASH_BANK_BOTH))
<> 144:ef7eb2e8f9f7 764 {
<> 144:ef7eb2e8f9f7 765 /* Wait for last operation to be completed */
<> 144:ef7eb2e8f9f7 766 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
<> 144:ef7eb2e8f9f7 767
<> 144:ef7eb2e8f9f7 768 if(status == HAL_OK)
<> 144:ef7eb2e8f9f7 769 {
<> 144:ef7eb2e8f9f7 770 *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS |= (uint16_t)(WRPSector>>12U);
<> 144:ef7eb2e8f9f7 771 }
<> 144:ef7eb2e8f9f7 772 }
<> 144:ef7eb2e8f9f7 773
<> 144:ef7eb2e8f9f7 774 }
<> 144:ef7eb2e8f9f7 775
<> 144:ef7eb2e8f9f7 776 return status;
<> 144:ef7eb2e8f9f7 777 }
<> 144:ef7eb2e8f9f7 778
<> 144:ef7eb2e8f9f7 779 /**
<> 144:ef7eb2e8f9f7 780 * @brief Configure the Dual Bank Boot.
<> 144:ef7eb2e8f9f7 781 *
<> 144:ef7eb2e8f9f7 782 * @note This function can be used only for STM32F42xxx/43xxx devices.
<> 144:ef7eb2e8f9f7 783 *
<> 144:ef7eb2e8f9f7 784 * @param BootConfig specifies the Dual Bank Boot Option byte.
<> 144:ef7eb2e8f9f7 785 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 786 * @arg OB_Dual_BootEnabled: Dual Bank Boot Enable
<> 144:ef7eb2e8f9f7 787 * @arg OB_Dual_BootDisabled: Dual Bank Boot Disabled
<> 144:ef7eb2e8f9f7 788 * @retval None
<> 144:ef7eb2e8f9f7 789 */
<> 144:ef7eb2e8f9f7 790 static HAL_StatusTypeDef FLASH_OB_BootConfig(uint8_t BootConfig)
<> 144:ef7eb2e8f9f7 791 {
<> 144:ef7eb2e8f9f7 792 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 793
<> 144:ef7eb2e8f9f7 794 /* Check the parameters */
<> 144:ef7eb2e8f9f7 795 assert_param(IS_OB_BOOT(BootConfig));
<> 144:ef7eb2e8f9f7 796
<> 144:ef7eb2e8f9f7 797 /* Wait for last operation to be completed */
<> 144:ef7eb2e8f9f7 798 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
<> 144:ef7eb2e8f9f7 799
<> 144:ef7eb2e8f9f7 800 if(status == HAL_OK)
<> 144:ef7eb2e8f9f7 801 {
<> 144:ef7eb2e8f9f7 802 /* Set Dual Bank Boot */
<> 144:ef7eb2e8f9f7 803 *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS &= (~FLASH_OPTCR_BFB2);
<> 144:ef7eb2e8f9f7 804 *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= BootConfig;
<> 144:ef7eb2e8f9f7 805 }
<> 144:ef7eb2e8f9f7 806
<> 144:ef7eb2e8f9f7 807 return status;
<> 144:ef7eb2e8f9f7 808 }
<> 144:ef7eb2e8f9f7 809
<> 144:ef7eb2e8f9f7 810 /**
<> 144:ef7eb2e8f9f7 811 * @brief Enable the read/write protection (PCROP) of the desired
<> 144:ef7eb2e8f9f7 812 * sectors of Bank 1 and/or Bank 2.
<> 144:ef7eb2e8f9f7 813 * @note This function can be used only for STM32F42xxx/43xxx devices.
<> 144:ef7eb2e8f9f7 814 * @param SectorBank1 Specifies the sector(s) to be read/write protected or unprotected for bank1.
<> 144:ef7eb2e8f9f7 815 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 816 * @arg OB_PCROP: A value between OB_PCROP_SECTOR_0 and OB_PCROP_SECTOR_11
<> 144:ef7eb2e8f9f7 817 * @arg OB_PCROP_SECTOR__All
<> 144:ef7eb2e8f9f7 818 * @param SectorBank2 Specifies the sector(s) to be read/write protected or unprotected for bank2.
<> 144:ef7eb2e8f9f7 819 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 820 * @arg OB_PCROP: A value between OB_PCROP_SECTOR_12 and OB_PCROP_SECTOR_23
<> 144:ef7eb2e8f9f7 821 * @arg OB_PCROP_SECTOR__All
<> 144:ef7eb2e8f9f7 822 * @param Banks Enable PCROP protection on all the sectors for the specific bank
<> 144:ef7eb2e8f9f7 823 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 824 * @arg FLASH_BANK_1: WRP on all sectors of bank1
<> 144:ef7eb2e8f9f7 825 * @arg FLASH_BANK_2: WRP on all sectors of bank2
<> 144:ef7eb2e8f9f7 826 * @arg FLASH_BANK_BOTH: WRP on all sectors of bank1 & bank2
<> 144:ef7eb2e8f9f7 827 *
<> 144:ef7eb2e8f9f7 828 * @retval HAL Status
<> 144:ef7eb2e8f9f7 829 */
<> 144:ef7eb2e8f9f7 830 static HAL_StatusTypeDef FLASH_OB_EnablePCROP(uint32_t SectorBank1, uint32_t SectorBank2, uint32_t Banks)
<> 144:ef7eb2e8f9f7 831 {
<> 144:ef7eb2e8f9f7 832 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 833
<> 144:ef7eb2e8f9f7 834 assert_param(IS_FLASH_BANK(Banks));
<> 144:ef7eb2e8f9f7 835
<> 144:ef7eb2e8f9f7 836 /* Wait for last operation to be completed */
<> 144:ef7eb2e8f9f7 837 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
<> 144:ef7eb2e8f9f7 838
<> 144:ef7eb2e8f9f7 839 if(status == HAL_OK)
<> 144:ef7eb2e8f9f7 840 {
<> 144:ef7eb2e8f9f7 841 if((Banks == FLASH_BANK_1) || (Banks == FLASH_BANK_BOTH))
<> 144:ef7eb2e8f9f7 842 {
<> 144:ef7eb2e8f9f7 843 assert_param(IS_OB_PCROP(SectorBank1));
<> 144:ef7eb2e8f9f7 844 /*Write protection done on sectors of BANK1*/
<> 144:ef7eb2e8f9f7 845 *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)SectorBank1;
<> 144:ef7eb2e8f9f7 846 }
<> 144:ef7eb2e8f9f7 847 else
<> 144:ef7eb2e8f9f7 848 {
<> 144:ef7eb2e8f9f7 849 assert_param(IS_OB_PCROP(SectorBank2));
<> 144:ef7eb2e8f9f7 850 /*Write protection done on sectors of BANK2*/
<> 144:ef7eb2e8f9f7 851 *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS |= (uint16_t)SectorBank2;
<> 144:ef7eb2e8f9f7 852 }
<> 144:ef7eb2e8f9f7 853
<> 144:ef7eb2e8f9f7 854 /*Write protection on all sector of BANK2*/
<> 144:ef7eb2e8f9f7 855 if(Banks == FLASH_BANK_BOTH)
<> 144:ef7eb2e8f9f7 856 {
<> 144:ef7eb2e8f9f7 857 assert_param(IS_OB_PCROP(SectorBank2));
<> 144:ef7eb2e8f9f7 858 /* Wait for last operation to be completed */
<> 144:ef7eb2e8f9f7 859 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
<> 144:ef7eb2e8f9f7 860
<> 144:ef7eb2e8f9f7 861 if(status == HAL_OK)
<> 144:ef7eb2e8f9f7 862 {
<> 144:ef7eb2e8f9f7 863 /*Write protection done on sectors of BANK2*/
<> 144:ef7eb2e8f9f7 864 *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS |= (uint16_t)SectorBank2;
<> 144:ef7eb2e8f9f7 865 }
<> 144:ef7eb2e8f9f7 866 }
<> 144:ef7eb2e8f9f7 867
<> 144:ef7eb2e8f9f7 868 }
<> 144:ef7eb2e8f9f7 869
<> 144:ef7eb2e8f9f7 870 return status;
<> 144:ef7eb2e8f9f7 871 }
<> 144:ef7eb2e8f9f7 872
<> 144:ef7eb2e8f9f7 873
<> 144:ef7eb2e8f9f7 874 /**
<> 144:ef7eb2e8f9f7 875 * @brief Disable the read/write protection (PCROP) of the desired
<> 144:ef7eb2e8f9f7 876 * sectors of Bank 1 and/or Bank 2.
<> 144:ef7eb2e8f9f7 877 * @note This function can be used only for STM32F42xxx/43xxx devices.
<> 144:ef7eb2e8f9f7 878 * @param SectorBank1 specifies the sector(s) to be read/write protected or unprotected for bank1.
<> 144:ef7eb2e8f9f7 879 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 880 * @arg OB_PCROP: A value between OB_PCROP_SECTOR_0 and OB_PCROP_SECTOR_11
<> 144:ef7eb2e8f9f7 881 * @arg OB_PCROP_SECTOR__All
<> 144:ef7eb2e8f9f7 882 * @param SectorBank2 Specifies the sector(s) to be read/write protected or unprotected for bank2.
<> 144:ef7eb2e8f9f7 883 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 884 * @arg OB_PCROP: A value between OB_PCROP_SECTOR_12 and OB_PCROP_SECTOR_23
<> 144:ef7eb2e8f9f7 885 * @arg OB_PCROP_SECTOR__All
<> 144:ef7eb2e8f9f7 886 * @param Banks Disable PCROP protection on all the sectors for the specific bank
<> 144:ef7eb2e8f9f7 887 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 888 * @arg FLASH_BANK_1: WRP on all sectors of bank1
<> 144:ef7eb2e8f9f7 889 * @arg FLASH_BANK_2: WRP on all sectors of bank2
<> 144:ef7eb2e8f9f7 890 * @arg FLASH_BANK_BOTH: WRP on all sectors of bank1 & bank2
<> 144:ef7eb2e8f9f7 891 *
<> 144:ef7eb2e8f9f7 892 * @retval HAL Status
<> 144:ef7eb2e8f9f7 893 */
<> 144:ef7eb2e8f9f7 894 static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t SectorBank1, uint32_t SectorBank2, uint32_t Banks)
<> 144:ef7eb2e8f9f7 895 {
<> 144:ef7eb2e8f9f7 896 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 897
<> 144:ef7eb2e8f9f7 898 /* Check the parameters */
<> 144:ef7eb2e8f9f7 899 assert_param(IS_FLASH_BANK(Banks));
<> 144:ef7eb2e8f9f7 900
<> 144:ef7eb2e8f9f7 901 /* Wait for last operation to be completed */
<> 144:ef7eb2e8f9f7 902 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
<> 144:ef7eb2e8f9f7 903
<> 144:ef7eb2e8f9f7 904 if(status == HAL_OK)
<> 144:ef7eb2e8f9f7 905 {
<> 144:ef7eb2e8f9f7 906 if((Banks == FLASH_BANK_1) || (Banks == FLASH_BANK_BOTH))
<> 144:ef7eb2e8f9f7 907 {
<> 144:ef7eb2e8f9f7 908 assert_param(IS_OB_PCROP(SectorBank1));
<> 144:ef7eb2e8f9f7 909 /*Write protection done on sectors of BANK1*/
<> 144:ef7eb2e8f9f7 910 *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~SectorBank1);
<> 144:ef7eb2e8f9f7 911 }
<> 144:ef7eb2e8f9f7 912 else
<> 144:ef7eb2e8f9f7 913 {
<> 144:ef7eb2e8f9f7 914 /*Write protection done on sectors of BANK2*/
<> 144:ef7eb2e8f9f7 915 assert_param(IS_OB_PCROP(SectorBank2));
<> 144:ef7eb2e8f9f7 916 *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS &= (~SectorBank2);
<> 144:ef7eb2e8f9f7 917 }
<> 144:ef7eb2e8f9f7 918
<> 144:ef7eb2e8f9f7 919 /*Write protection on all sector of BANK2*/
<> 144:ef7eb2e8f9f7 920 if(Banks == FLASH_BANK_BOTH)
<> 144:ef7eb2e8f9f7 921 {
<> 144:ef7eb2e8f9f7 922 assert_param(IS_OB_PCROP(SectorBank2));
<> 144:ef7eb2e8f9f7 923 /* Wait for last operation to be completed */
<> 144:ef7eb2e8f9f7 924 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
<> 144:ef7eb2e8f9f7 925
<> 144:ef7eb2e8f9f7 926 if(status == HAL_OK)
<> 144:ef7eb2e8f9f7 927 {
<> 144:ef7eb2e8f9f7 928 /*Write protection done on sectors of BANK2*/
<> 144:ef7eb2e8f9f7 929 *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS &= (~SectorBank2);
<> 144:ef7eb2e8f9f7 930 }
<> 144:ef7eb2e8f9f7 931 }
<> 144:ef7eb2e8f9f7 932
<> 144:ef7eb2e8f9f7 933 }
<> 144:ef7eb2e8f9f7 934
<> 144:ef7eb2e8f9f7 935 return status;
<> 144:ef7eb2e8f9f7 936
<> 144:ef7eb2e8f9f7 937 }
<> 144:ef7eb2e8f9f7 938
<> 144:ef7eb2e8f9f7 939 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
<> 144:ef7eb2e8f9f7 940
<> 144:ef7eb2e8f9f7 941 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
<> 144:ef7eb2e8f9f7 942 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
<> 144:ef7eb2e8f9f7 943 defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\
<> 144:ef7eb2e8f9f7 944 defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
<> 144:ef7eb2e8f9f7 945 /**
<> 144:ef7eb2e8f9f7 946 * @brief Mass erase of FLASH memory
<> 144:ef7eb2e8f9f7 947 * @param VoltageRange: The device voltage range which defines the erase parallelism.
<> 144:ef7eb2e8f9f7 948 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 949 * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V,
<> 144:ef7eb2e8f9f7 950 * the operation will be done by byte (8-bit)
<> 144:ef7eb2e8f9f7 951 * @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
<> 144:ef7eb2e8f9f7 952 * the operation will be done by half word (16-bit)
<> 144:ef7eb2e8f9f7 953 * @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
<> 144:ef7eb2e8f9f7 954 * the operation will be done by word (32-bit)
<> 144:ef7eb2e8f9f7 955 * @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
<> 144:ef7eb2e8f9f7 956 * the operation will be done by double word (64-bit)
<> 144:ef7eb2e8f9f7 957 *
<> 144:ef7eb2e8f9f7 958 * @param Banks: Banks to be erased
<> 144:ef7eb2e8f9f7 959 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 960 * @arg FLASH_BANK_1: Bank1 to be erased
<> 144:ef7eb2e8f9f7 961 *
<> 144:ef7eb2e8f9f7 962 * @retval None
<> 144:ef7eb2e8f9f7 963 */
<> 144:ef7eb2e8f9f7 964 static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks)
<> 144:ef7eb2e8f9f7 965 {
<> 144:ef7eb2e8f9f7 966 /* Check the parameters */
<> 144:ef7eb2e8f9f7 967 assert_param(IS_VOLTAGERANGE(VoltageRange));
<> 144:ef7eb2e8f9f7 968 assert_param(IS_FLASH_BANK(Banks));
<> 144:ef7eb2e8f9f7 969
<> 144:ef7eb2e8f9f7 970 /* If the previous operation is completed, proceed to erase all sectors */
<> 144:ef7eb2e8f9f7 971 CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
<> 144:ef7eb2e8f9f7 972 FLASH->CR |= FLASH_CR_MER;
<> 144:ef7eb2e8f9f7 973 FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange <<8U);
<> 144:ef7eb2e8f9f7 974 }
<> 144:ef7eb2e8f9f7 975
<> 144:ef7eb2e8f9f7 976 /**
<> 144:ef7eb2e8f9f7 977 * @brief Erase the specified FLASH memory sector
<> 144:ef7eb2e8f9f7 978 * @param Sector: FLASH sector to erase
<> 144:ef7eb2e8f9f7 979 * The value of this parameter depend on device used within the same series
<> 144:ef7eb2e8f9f7 980 * @param VoltageRange: The device voltage range which defines the erase parallelism.
<> 144:ef7eb2e8f9f7 981 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 982 * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V,
<> 144:ef7eb2e8f9f7 983 * the operation will be done by byte (8-bit)
<> 144:ef7eb2e8f9f7 984 * @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
<> 144:ef7eb2e8f9f7 985 * the operation will be done by half word (16-bit)
<> 144:ef7eb2e8f9f7 986 * @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
<> 144:ef7eb2e8f9f7 987 * the operation will be done by word (32-bit)
<> 144:ef7eb2e8f9f7 988 * @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
<> 144:ef7eb2e8f9f7 989 * the operation will be done by double word (64-bit)
<> 144:ef7eb2e8f9f7 990 *
<> 144:ef7eb2e8f9f7 991 * @retval None
<> 144:ef7eb2e8f9f7 992 */
<> 144:ef7eb2e8f9f7 993 void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange)
<> 144:ef7eb2e8f9f7 994 {
<> 144:ef7eb2e8f9f7 995 uint32_t tmp_psize = 0U;
<> 144:ef7eb2e8f9f7 996
<> 144:ef7eb2e8f9f7 997 /* Check the parameters */
<> 144:ef7eb2e8f9f7 998 assert_param(IS_FLASH_SECTOR(Sector));
<> 144:ef7eb2e8f9f7 999 assert_param(IS_VOLTAGERANGE(VoltageRange));
<> 144:ef7eb2e8f9f7 1000
<> 144:ef7eb2e8f9f7 1001 if(VoltageRange == FLASH_VOLTAGE_RANGE_1)
<> 144:ef7eb2e8f9f7 1002 {
<> 144:ef7eb2e8f9f7 1003 tmp_psize = FLASH_PSIZE_BYTE;
<> 144:ef7eb2e8f9f7 1004 }
<> 144:ef7eb2e8f9f7 1005 else if(VoltageRange == FLASH_VOLTAGE_RANGE_2)
<> 144:ef7eb2e8f9f7 1006 {
<> 144:ef7eb2e8f9f7 1007 tmp_psize = FLASH_PSIZE_HALF_WORD;
<> 144:ef7eb2e8f9f7 1008 }
<> 144:ef7eb2e8f9f7 1009 else if(VoltageRange == FLASH_VOLTAGE_RANGE_3)
<> 144:ef7eb2e8f9f7 1010 {
<> 144:ef7eb2e8f9f7 1011 tmp_psize = FLASH_PSIZE_WORD;
<> 144:ef7eb2e8f9f7 1012 }
<> 144:ef7eb2e8f9f7 1013 else
<> 144:ef7eb2e8f9f7 1014 {
<> 144:ef7eb2e8f9f7 1015 tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
<> 144:ef7eb2e8f9f7 1016 }
<> 144:ef7eb2e8f9f7 1017
<> 144:ef7eb2e8f9f7 1018 /* If the previous operation is completed, proceed to erase the sector */
<> 144:ef7eb2e8f9f7 1019 CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
<> 144:ef7eb2e8f9f7 1020 FLASH->CR |= tmp_psize;
<> 144:ef7eb2e8f9f7 1021 CLEAR_BIT(FLASH->CR, FLASH_CR_SNB);
<> 144:ef7eb2e8f9f7 1022 FLASH->CR |= FLASH_CR_SER | (Sector << POSITION_VAL(FLASH_CR_SNB));
<> 144:ef7eb2e8f9f7 1023 FLASH->CR |= FLASH_CR_STRT;
<> 144:ef7eb2e8f9f7 1024 }
<> 144:ef7eb2e8f9f7 1025
<> 144:ef7eb2e8f9f7 1026 /**
<> 144:ef7eb2e8f9f7 1027 * @brief Enable the write protection of the desired bank 1 sectors
<> 144:ef7eb2e8f9f7 1028 *
<> 144:ef7eb2e8f9f7 1029 * @note When the memory read protection level is selected (RDP level = 1),
<> 144:ef7eb2e8f9f7 1030 * it is not possible to program or erase the flash sector i if CortexM4
<> 144:ef7eb2e8f9f7 1031 * debug features are connected or boot code is executed in RAM, even if nWRPi = 1
<> 144:ef7eb2e8f9f7 1032 * @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1).
<> 144:ef7eb2e8f9f7 1033 *
<> 144:ef7eb2e8f9f7 1034 * @param WRPSector: specifies the sector(s) to be write protected.
<> 144:ef7eb2e8f9f7 1035 * The value of this parameter depend on device used within the same series
<> 144:ef7eb2e8f9f7 1036 *
<> 144:ef7eb2e8f9f7 1037 * @param Banks: Enable write protection on all the sectors for the specific bank
<> 144:ef7eb2e8f9f7 1038 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1039 * @arg FLASH_BANK_1: WRP on all sectors of bank1
<> 144:ef7eb2e8f9f7 1040 *
<> 144:ef7eb2e8f9f7 1041 * @retval HAL Status
<> 144:ef7eb2e8f9f7 1042 */
<> 144:ef7eb2e8f9f7 1043 static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks)
<> 144:ef7eb2e8f9f7 1044 {
<> 144:ef7eb2e8f9f7 1045 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 1046
<> 144:ef7eb2e8f9f7 1047 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1048 assert_param(IS_OB_WRP_SECTOR(WRPSector));
<> 144:ef7eb2e8f9f7 1049 assert_param(IS_FLASH_BANK(Banks));
<> 144:ef7eb2e8f9f7 1050
<> 144:ef7eb2e8f9f7 1051 /* Wait for last operation to be completed */
<> 144:ef7eb2e8f9f7 1052 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
<> 144:ef7eb2e8f9f7 1053
<> 144:ef7eb2e8f9f7 1054 if(status == HAL_OK)
<> 144:ef7eb2e8f9f7 1055 {
<> 144:ef7eb2e8f9f7 1056 *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~WRPSector);
<> 144:ef7eb2e8f9f7 1057 }
<> 144:ef7eb2e8f9f7 1058
<> 144:ef7eb2e8f9f7 1059 return status;
<> 144:ef7eb2e8f9f7 1060 }
<> 144:ef7eb2e8f9f7 1061
<> 144:ef7eb2e8f9f7 1062 /**
<> 144:ef7eb2e8f9f7 1063 * @brief Disable the write protection of the desired bank 1 sectors
<> 144:ef7eb2e8f9f7 1064 *
<> 144:ef7eb2e8f9f7 1065 * @note When the memory read protection level is selected (RDP level = 1),
<> 144:ef7eb2e8f9f7 1066 * it is not possible to program or erase the flash sector i if CortexM4
<> 144:ef7eb2e8f9f7 1067 * debug features are connected or boot code is executed in RAM, even if nWRPi = 1
<> 144:ef7eb2e8f9f7 1068 * @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1).
<> 144:ef7eb2e8f9f7 1069 *
<> 144:ef7eb2e8f9f7 1070 * @param WRPSector: specifies the sector(s) to be write protected.
<> 144:ef7eb2e8f9f7 1071 * The value of this parameter depend on device used within the same series
<> 144:ef7eb2e8f9f7 1072 *
<> 144:ef7eb2e8f9f7 1073 * @param Banks: Enable write protection on all the sectors for the specific bank
<> 144:ef7eb2e8f9f7 1074 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1075 * @arg FLASH_BANK_1: WRP on all sectors of bank1
<> 144:ef7eb2e8f9f7 1076 *
<> 144:ef7eb2e8f9f7 1077 * @retval HAL Status
<> 144:ef7eb2e8f9f7 1078 */
<> 144:ef7eb2e8f9f7 1079 static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks)
<> 144:ef7eb2e8f9f7 1080 {
<> 144:ef7eb2e8f9f7 1081 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 1082
<> 144:ef7eb2e8f9f7 1083 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1084 assert_param(IS_OB_WRP_SECTOR(WRPSector));
<> 144:ef7eb2e8f9f7 1085 assert_param(IS_FLASH_BANK(Banks));
<> 144:ef7eb2e8f9f7 1086
<> 144:ef7eb2e8f9f7 1087 /* Wait for last operation to be completed */
<> 144:ef7eb2e8f9f7 1088 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
<> 144:ef7eb2e8f9f7 1089
<> 144:ef7eb2e8f9f7 1090 if(status == HAL_OK)
<> 144:ef7eb2e8f9f7 1091 {
<> 144:ef7eb2e8f9f7 1092 *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)WRPSector;
<> 144:ef7eb2e8f9f7 1093 }
<> 144:ef7eb2e8f9f7 1094
<> 144:ef7eb2e8f9f7 1095 return status;
<> 144:ef7eb2e8f9f7 1096 }
<> 144:ef7eb2e8f9f7 1097 #endif /* STM32F40xxx || STM32F41xxx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
<> 144:ef7eb2e8f9f7 1098
<> 144:ef7eb2e8f9f7 1099 #if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\
<> 144:ef7eb2e8f9f7 1100 defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
<> 144:ef7eb2e8f9f7 1101 defined(STM32F412Cx)
<> 144:ef7eb2e8f9f7 1102 /**
<> 144:ef7eb2e8f9f7 1103 * @brief Enable the read/write protection (PCROP) of the desired sectors.
<> 144:ef7eb2e8f9f7 1104 * @note This function can be used only for STM32F401xx devices.
<> 144:ef7eb2e8f9f7 1105 * @param Sector specifies the sector(s) to be read/write protected or unprotected.
<> 144:ef7eb2e8f9f7 1106 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1107 * @arg OB_PCROP: A value between OB_PCROP_Sector0 and OB_PCROP_Sector5
<> 144:ef7eb2e8f9f7 1108 * @arg OB_PCROP_Sector_All
<> 144:ef7eb2e8f9f7 1109 * @retval HAL Status
<> 144:ef7eb2e8f9f7 1110 */
<> 144:ef7eb2e8f9f7 1111 static HAL_StatusTypeDef FLASH_OB_EnablePCROP(uint32_t Sector)
<> 144:ef7eb2e8f9f7 1112 {
<> 144:ef7eb2e8f9f7 1113 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 1114
<> 144:ef7eb2e8f9f7 1115 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1116 assert_param(IS_OB_PCROP(Sector));
<> 144:ef7eb2e8f9f7 1117
<> 144:ef7eb2e8f9f7 1118 /* Wait for last operation to be completed */
<> 144:ef7eb2e8f9f7 1119 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
<> 144:ef7eb2e8f9f7 1120
<> 144:ef7eb2e8f9f7 1121 if(status == HAL_OK)
<> 144:ef7eb2e8f9f7 1122 {
<> 144:ef7eb2e8f9f7 1123 *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)Sector;
<> 144:ef7eb2e8f9f7 1124 }
<> 144:ef7eb2e8f9f7 1125
<> 144:ef7eb2e8f9f7 1126 return status;
<> 144:ef7eb2e8f9f7 1127 }
<> 144:ef7eb2e8f9f7 1128
<> 144:ef7eb2e8f9f7 1129
<> 144:ef7eb2e8f9f7 1130 /**
<> 144:ef7eb2e8f9f7 1131 * @brief Disable the read/write protection (PCROP) of the desired sectors.
<> 144:ef7eb2e8f9f7 1132 * @note This function can be used only for STM32F401xx devices.
<> 144:ef7eb2e8f9f7 1133 * @param Sector specifies the sector(s) to be read/write protected or unprotected.
<> 144:ef7eb2e8f9f7 1134 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1135 * @arg OB_PCROP: A value between OB_PCROP_Sector0 and OB_PCROP_Sector5
<> 144:ef7eb2e8f9f7 1136 * @arg OB_PCROP_Sector_All
<> 144:ef7eb2e8f9f7 1137 * @retval HAL Status
<> 144:ef7eb2e8f9f7 1138 */
<> 144:ef7eb2e8f9f7 1139 static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t Sector)
<> 144:ef7eb2e8f9f7 1140 {
<> 144:ef7eb2e8f9f7 1141 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 1142
<> 144:ef7eb2e8f9f7 1143 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1144 assert_param(IS_OB_PCROP(Sector));
<> 144:ef7eb2e8f9f7 1145
<> 144:ef7eb2e8f9f7 1146 /* Wait for last operation to be completed */
<> 144:ef7eb2e8f9f7 1147 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
<> 144:ef7eb2e8f9f7 1148
<> 144:ef7eb2e8f9f7 1149 if(status == HAL_OK)
<> 144:ef7eb2e8f9f7 1150 {
<> 144:ef7eb2e8f9f7 1151 *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~Sector);
<> 144:ef7eb2e8f9f7 1152 }
<> 144:ef7eb2e8f9f7 1153
<> 144:ef7eb2e8f9f7 1154 return status;
<> 144:ef7eb2e8f9f7 1155
<> 144:ef7eb2e8f9f7 1156 }
<> 144:ef7eb2e8f9f7 1157 #endif /* STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
<> 144:ef7eb2e8f9f7 1158
<> 144:ef7eb2e8f9f7 1159 /**
<> 144:ef7eb2e8f9f7 1160 * @brief Set the read protection level.
<> 144:ef7eb2e8f9f7 1161 * @param Level: specifies the read protection level.
<> 144:ef7eb2e8f9f7 1162 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1163 * @arg OB_RDP_LEVEL_0: No protection
<> 144:ef7eb2e8f9f7 1164 * @arg OB_RDP_LEVEL_1: Read protection of the memory
<> 144:ef7eb2e8f9f7 1165 * @arg OB_RDP_LEVEL_2: Full chip protection
<> 144:ef7eb2e8f9f7 1166 *
<> 144:ef7eb2e8f9f7 1167 * @note WARNING: When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0
<> 144:ef7eb2e8f9f7 1168 *
<> 144:ef7eb2e8f9f7 1169 * @retval HAL Status
<> 144:ef7eb2e8f9f7 1170 */
<> 144:ef7eb2e8f9f7 1171 static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level)
<> 144:ef7eb2e8f9f7 1172 {
<> 144:ef7eb2e8f9f7 1173 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 1174
<> 144:ef7eb2e8f9f7 1175 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1176 assert_param(IS_OB_RDP_LEVEL(Level));
<> 144:ef7eb2e8f9f7 1177
<> 144:ef7eb2e8f9f7 1178 /* Wait for last operation to be completed */
<> 144:ef7eb2e8f9f7 1179 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
<> 144:ef7eb2e8f9f7 1180
<> 144:ef7eb2e8f9f7 1181 if(status == HAL_OK)
<> 144:ef7eb2e8f9f7 1182 {
<> 144:ef7eb2e8f9f7 1183 *(__IO uint8_t*)OPTCR_BYTE1_ADDRESS = Level;
<> 144:ef7eb2e8f9f7 1184 }
<> 144:ef7eb2e8f9f7 1185
<> 144:ef7eb2e8f9f7 1186 return status;
<> 144:ef7eb2e8f9f7 1187 }
<> 144:ef7eb2e8f9f7 1188
<> 144:ef7eb2e8f9f7 1189 /**
<> 144:ef7eb2e8f9f7 1190 * @brief Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
<> 144:ef7eb2e8f9f7 1191 * @param Iwdg: Selects the IWDG mode
<> 144:ef7eb2e8f9f7 1192 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1193 * @arg OB_IWDG_SW: Software IWDG selected
<> 144:ef7eb2e8f9f7 1194 * @arg OB_IWDG_HW: Hardware IWDG selected
<> 144:ef7eb2e8f9f7 1195 * @param Stop: Reset event when entering STOP mode.
<> 144:ef7eb2e8f9f7 1196 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1197 * @arg OB_STOP_NO_RST: No reset generated when entering in STOP
<> 144:ef7eb2e8f9f7 1198 * @arg OB_STOP_RST: Reset generated when entering in STOP
<> 144:ef7eb2e8f9f7 1199 * @param Stdby: Reset event when entering Standby mode.
<> 144:ef7eb2e8f9f7 1200 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1201 * @arg OB_STDBY_NO_RST: No reset generated when entering in STANDBY
<> 144:ef7eb2e8f9f7 1202 * @arg OB_STDBY_RST: Reset generated when entering in STANDBY
<> 144:ef7eb2e8f9f7 1203 * @retval HAL Status
<> 144:ef7eb2e8f9f7 1204 */
<> 144:ef7eb2e8f9f7 1205 static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t Iwdg, uint8_t Stop, uint8_t Stdby)
<> 144:ef7eb2e8f9f7 1206 {
<> 144:ef7eb2e8f9f7 1207 uint8_t optiontmp = 0xFFU;
<> 144:ef7eb2e8f9f7 1208 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 1209
<> 144:ef7eb2e8f9f7 1210 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1211 assert_param(IS_OB_IWDG_SOURCE(Iwdg));
<> 144:ef7eb2e8f9f7 1212 assert_param(IS_OB_STOP_SOURCE(Stop));
<> 144:ef7eb2e8f9f7 1213 assert_param(IS_OB_STDBY_SOURCE(Stdby));
<> 144:ef7eb2e8f9f7 1214
<> 144:ef7eb2e8f9f7 1215 /* Wait for last operation to be completed */
<> 144:ef7eb2e8f9f7 1216 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
<> 144:ef7eb2e8f9f7 1217
<> 144:ef7eb2e8f9f7 1218 if(status == HAL_OK)
<> 144:ef7eb2e8f9f7 1219 {
<> 144:ef7eb2e8f9f7 1220 /* Mask OPTLOCK, OPTSTRT, BOR_LEV and BFB2 bits */
<> 144:ef7eb2e8f9f7 1221 optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS) & (uint8_t)0x1FU);
<> 144:ef7eb2e8f9f7 1222
<> 144:ef7eb2e8f9f7 1223 /* Update User Option Byte */
<> 144:ef7eb2e8f9f7 1224 *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS = Iwdg | (uint8_t)(Stdby | (uint8_t)(Stop | ((uint8_t)optiontmp)));
<> 144:ef7eb2e8f9f7 1225 }
<> 144:ef7eb2e8f9f7 1226
<> 144:ef7eb2e8f9f7 1227 return status;
<> 144:ef7eb2e8f9f7 1228 }
<> 144:ef7eb2e8f9f7 1229
<> 144:ef7eb2e8f9f7 1230 /**
<> 144:ef7eb2e8f9f7 1231 * @brief Set the BOR Level.
<> 144:ef7eb2e8f9f7 1232 * @param Level: specifies the Option Bytes BOR Reset Level.
<> 144:ef7eb2e8f9f7 1233 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1234 * @arg OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V
<> 144:ef7eb2e8f9f7 1235 * @arg OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V
<> 144:ef7eb2e8f9f7 1236 * @arg OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V
<> 144:ef7eb2e8f9f7 1237 * @arg OB_BOR_OFF: Supply voltage ranges from 1.62 to 2.1 V
<> 144:ef7eb2e8f9f7 1238 * @retval HAL Status
<> 144:ef7eb2e8f9f7 1239 */
<> 144:ef7eb2e8f9f7 1240 static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level)
<> 144:ef7eb2e8f9f7 1241 {
<> 144:ef7eb2e8f9f7 1242 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1243 assert_param(IS_OB_BOR_LEVEL(Level));
<> 144:ef7eb2e8f9f7 1244
<> 144:ef7eb2e8f9f7 1245 /* Set the BOR Level */
<> 144:ef7eb2e8f9f7 1246 *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS &= (~FLASH_OPTCR_BOR_LEV);
<> 144:ef7eb2e8f9f7 1247 *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= Level;
<> 144:ef7eb2e8f9f7 1248
<> 144:ef7eb2e8f9f7 1249 return HAL_OK;
<> 144:ef7eb2e8f9f7 1250
<> 144:ef7eb2e8f9f7 1251 }
<> 144:ef7eb2e8f9f7 1252
<> 144:ef7eb2e8f9f7 1253 /**
<> 144:ef7eb2e8f9f7 1254 * @brief Return the FLASH User Option Byte value.
<> 144:ef7eb2e8f9f7 1255 * @retval uint8_t FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1)
<> 144:ef7eb2e8f9f7 1256 * and RST_STDBY(Bit2).
<> 144:ef7eb2e8f9f7 1257 */
<> 144:ef7eb2e8f9f7 1258 static uint8_t FLASH_OB_GetUser(void)
<> 144:ef7eb2e8f9f7 1259 {
<> 144:ef7eb2e8f9f7 1260 /* Return the User Option Byte */
<> 144:ef7eb2e8f9f7 1261 return ((uint8_t)(FLASH->OPTCR & 0xE0U));
<> 144:ef7eb2e8f9f7 1262 }
<> 144:ef7eb2e8f9f7 1263
<> 144:ef7eb2e8f9f7 1264 /**
<> 144:ef7eb2e8f9f7 1265 * @brief Return the FLASH Write Protection Option Bytes value.
<> 144:ef7eb2e8f9f7 1266 * @retval uint16_t FLASH Write Protection Option Bytes value
<> 144:ef7eb2e8f9f7 1267 */
<> 144:ef7eb2e8f9f7 1268 static uint16_t FLASH_OB_GetWRP(void)
<> 144:ef7eb2e8f9f7 1269 {
<> 144:ef7eb2e8f9f7 1270 /* Return the FLASH write protection Register value */
<> 144:ef7eb2e8f9f7 1271 return (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS));
<> 144:ef7eb2e8f9f7 1272 }
<> 144:ef7eb2e8f9f7 1273
<> 144:ef7eb2e8f9f7 1274 /**
<> 144:ef7eb2e8f9f7 1275 * @brief Returns the FLASH Read Protection level.
<> 144:ef7eb2e8f9f7 1276 * @retval FLASH ReadOut Protection Status:
<> 144:ef7eb2e8f9f7 1277 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1278 * @arg OB_RDP_LEVEL_0: No protection
<> 144:ef7eb2e8f9f7 1279 * @arg OB_RDP_LEVEL_1: Read protection of the memory
<> 144:ef7eb2e8f9f7 1280 * @arg OB_RDP_LEVEL_2: Full chip protection
<> 144:ef7eb2e8f9f7 1281 */
<> 144:ef7eb2e8f9f7 1282 static uint8_t FLASH_OB_GetRDP(void)
<> 144:ef7eb2e8f9f7 1283 {
<> 144:ef7eb2e8f9f7 1284 uint8_t readstatus = OB_RDP_LEVEL_0;
<> 144:ef7eb2e8f9f7 1285
<> 144:ef7eb2e8f9f7 1286 if((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS) == (uint8_t)OB_RDP_LEVEL_2))
<> 144:ef7eb2e8f9f7 1287 {
<> 144:ef7eb2e8f9f7 1288 readstatus = OB_RDP_LEVEL_2;
<> 144:ef7eb2e8f9f7 1289 }
<> 144:ef7eb2e8f9f7 1290 else if((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS) == (uint8_t)OB_RDP_LEVEL_1))
<> 144:ef7eb2e8f9f7 1291 {
<> 144:ef7eb2e8f9f7 1292 readstatus = OB_RDP_LEVEL_1;
<> 144:ef7eb2e8f9f7 1293 }
<> 144:ef7eb2e8f9f7 1294 else
<> 144:ef7eb2e8f9f7 1295 {
<> 144:ef7eb2e8f9f7 1296 readstatus = OB_RDP_LEVEL_0;
<> 144:ef7eb2e8f9f7 1297 }
<> 144:ef7eb2e8f9f7 1298
<> 144:ef7eb2e8f9f7 1299 return readstatus;
<> 144:ef7eb2e8f9f7 1300 }
<> 144:ef7eb2e8f9f7 1301
<> 144:ef7eb2e8f9f7 1302 /**
<> 144:ef7eb2e8f9f7 1303 * @brief Returns the FLASH BOR level.
<> 144:ef7eb2e8f9f7 1304 * @retval uint8_t The FLASH BOR level:
<> 144:ef7eb2e8f9f7 1305 * - OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V
<> 144:ef7eb2e8f9f7 1306 * - OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V
<> 144:ef7eb2e8f9f7 1307 * - OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V
<> 144:ef7eb2e8f9f7 1308 * - OB_BOR_OFF : Supply voltage ranges from 1.62 to 2.1 V
<> 144:ef7eb2e8f9f7 1309 */
<> 144:ef7eb2e8f9f7 1310 static uint8_t FLASH_OB_GetBOR(void)
<> 144:ef7eb2e8f9f7 1311 {
<> 144:ef7eb2e8f9f7 1312 /* Return the FLASH BOR level */
<> 144:ef7eb2e8f9f7 1313 return (uint8_t)(*(__IO uint8_t *)(OPTCR_BYTE0_ADDRESS) & (uint8_t)0x0CU);
<> 144:ef7eb2e8f9f7 1314 }
<> 144:ef7eb2e8f9f7 1315
<> 144:ef7eb2e8f9f7 1316 /**
<> 144:ef7eb2e8f9f7 1317 * @brief Flush the instruction and data caches
<> 144:ef7eb2e8f9f7 1318 * @retval None
<> 144:ef7eb2e8f9f7 1319 */
<> 144:ef7eb2e8f9f7 1320 void FLASH_FlushCaches(void)
<> 144:ef7eb2e8f9f7 1321 {
<> 144:ef7eb2e8f9f7 1322 /* Flush instruction cache */
<> 144:ef7eb2e8f9f7 1323 if(READ_BIT(FLASH->ACR, FLASH_ACR_ICEN)!= RESET)
<> 144:ef7eb2e8f9f7 1324 {
<> 144:ef7eb2e8f9f7 1325 /* Disable instruction cache */
<> 144:ef7eb2e8f9f7 1326 __HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
<> 144:ef7eb2e8f9f7 1327 /* Reset instruction cache */
<> 144:ef7eb2e8f9f7 1328 __HAL_FLASH_INSTRUCTION_CACHE_RESET();
<> 144:ef7eb2e8f9f7 1329 /* Enable instruction cache */
<> 144:ef7eb2e8f9f7 1330 __HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
<> 144:ef7eb2e8f9f7 1331 }
<> 144:ef7eb2e8f9f7 1332
<> 144:ef7eb2e8f9f7 1333 /* Flush data cache */
<> 144:ef7eb2e8f9f7 1334 if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET)
<> 144:ef7eb2e8f9f7 1335 {
<> 144:ef7eb2e8f9f7 1336 /* Disable data cache */
<> 144:ef7eb2e8f9f7 1337 __HAL_FLASH_DATA_CACHE_DISABLE();
<> 144:ef7eb2e8f9f7 1338 /* Reset data cache */
<> 144:ef7eb2e8f9f7 1339 __HAL_FLASH_DATA_CACHE_RESET();
<> 144:ef7eb2e8f9f7 1340 /* Enable data cache */
<> 144:ef7eb2e8f9f7 1341 __HAL_FLASH_DATA_CACHE_ENABLE();
<> 144:ef7eb2e8f9f7 1342 }
<> 144:ef7eb2e8f9f7 1343 }
<> 144:ef7eb2e8f9f7 1344
<> 144:ef7eb2e8f9f7 1345 /**
<> 144:ef7eb2e8f9f7 1346 * @}
<> 144:ef7eb2e8f9f7 1347 */
<> 144:ef7eb2e8f9f7 1348
<> 144:ef7eb2e8f9f7 1349 #endif /* HAL_FLASH_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 1350
<> 144:ef7eb2e8f9f7 1351 /**
<> 144:ef7eb2e8f9f7 1352 * @}
<> 144:ef7eb2e8f9f7 1353 */
<> 144:ef7eb2e8f9f7 1354
<> 144:ef7eb2e8f9f7 1355 /**
<> 144:ef7eb2e8f9f7 1356 * @}
<> 144:ef7eb2e8f9f7 1357 */
<> 144:ef7eb2e8f9f7 1358
<> 144:ef7eb2e8f9f7 1359 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/