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targets/TARGET_Maxim/TARGET_MAX32620/device/clkman_regs.h@162:16168a1438f3, 2017-04-08 (annotated)

Committer:
funshine
Date:
Sat Apr 08 17:03:55 2017 +0000
Revision:
162:16168a1438f3
Parent:
149:156823d33999 
add code to handle serial port rx error in uart_irq()

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*******************************************************************************
<> 144:ef7eb2e8f9f7 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 144:ef7eb2e8f9f7 5 * copy of this software and associated documentation files (the "Software"),
<> 144:ef7eb2e8f9f7 6 * to deal in the Software without restriction, including without limitation
<> 144:ef7eb2e8f9f7 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 144:ef7eb2e8f9f7 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 144:ef7eb2e8f9f7 9 * Software is furnished to do so, subject to the following conditions:
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * The above copyright notice and this permission notice shall be included
<> 144:ef7eb2e8f9f7 12 * in all copies or substantial portions of the Software.
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 144:ef7eb2e8f9f7 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 144:ef7eb2e8f9f7 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 144:ef7eb2e8f9f7 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 144:ef7eb2e8f9f7 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 144:ef7eb2e8f9f7 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 144:ef7eb2e8f9f7 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * Except as contained in this notice, the name of Maxim Integrated
<> 144:ef7eb2e8f9f7 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 144:ef7eb2e8f9f7 24 * Products, Inc. Branding Policy.
<> 144:ef7eb2e8f9f7 25 *
<> 144:ef7eb2e8f9f7 26 * The mere transfer of this software does not imply any licenses
<> 144:ef7eb2e8f9f7 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 144:ef7eb2e8f9f7 28 * trademarks, maskwork rights, or any other form of intellectual
<> 144:ef7eb2e8f9f7 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 144:ef7eb2e8f9f7 30 * ownership rights.
<> 144:ef7eb2e8f9f7 31 *******************************************************************************
<> 144:ef7eb2e8f9f7 32 */
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 #ifndef _MXC_CLKMAN_REGS_H_
<> 144:ef7eb2e8f9f7 35 #define _MXC_CLKMAN_REGS_H_
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 38 extern "C" {
<> 144:ef7eb2e8f9f7 39 #endif
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 #include <stdint.h>
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 /*
<> 144:ef7eb2e8f9f7 44 If types are not defined elsewhere (CMSIS) define them here
<> 144:ef7eb2e8f9f7 45 */
<> 144:ef7eb2e8f9f7 46 #ifndef __IO
<> 144:ef7eb2e8f9f7 47 #define __IO volatile
<> 144:ef7eb2e8f9f7 48 #endif
<> 144:ef7eb2e8f9f7 49 #ifndef __I
<> 144:ef7eb2e8f9f7 50 #define __I volatile const
<> 144:ef7eb2e8f9f7 51 #endif
<> 144:ef7eb2e8f9f7 52 #ifndef __O
<> 144:ef7eb2e8f9f7 53 #define __O volatile
<> 144:ef7eb2e8f9f7 54 #endif
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /*
<> 144:ef7eb2e8f9f7 58 Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
<> 144:ef7eb2e8f9f7 59 access to each register in module.
<> 144:ef7eb2e8f9f7 60 */
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 /* Offset Register Description
<> 144:ef7eb2e8f9f7 63 ============= ============================================================================ */
<> 144:ef7eb2e8f9f7 64 typedef struct {
<> 144:ef7eb2e8f9f7 65 __IO uint32_t clk_config; /* 0x0000 System Clock Configuration */
<> 144:ef7eb2e8f9f7 66 __IO uint32_t clk_ctrl; /* 0x0004 System Clock Controls */
<> 144:ef7eb2e8f9f7 67 __IO uint32_t intfl; /* 0x0008 Interrupt Flags */
<> 144:ef7eb2e8f9f7 68 __IO uint32_t inten; /* 0x000C Interrupt Enable/Disable Controls */
<> 144:ef7eb2e8f9f7 69 __IO uint32_t trim_calc; /* 0x0010 Trim Calculation Controls */
<> 144:ef7eb2e8f9f7 70 __IO uint32_t i2c_timer_ctrl; /* 0x0014 I2C Timer Control */
<> 144:ef7eb2e8f9f7 71 __IO uint32_t cm4_start_clk_en0; /* 0x0018 CM4 Start Clock on Interrupt Enable 0 */
<> 144:ef7eb2e8f9f7 72 __IO uint32_t cm4_start_clk_en1; /* 0x001C CM4 Start Clock on Interrupt Enable 1 */
<> 144:ef7eb2e8f9f7 73 __I uint32_t rsv020[8]; /* 0x0020-0x003C */
<> 144:ef7eb2e8f9f7 74 __IO uint32_t sys_clk_ctrl_0_cm4; /* 0x0040 Control Settings for CLK0 - Cortex M4 Clock */
<> 144:ef7eb2e8f9f7 75 __IO uint32_t sys_clk_ctrl_1_sync; /* 0x0044 Control Settings for CLK1 - Synchronizer Clock */
<> 144:ef7eb2e8f9f7 76 __IO uint32_t sys_clk_ctrl_2_spix; /* 0x0048 Control Settings for CLK2 - SPI XIP Clock */
<> 144:ef7eb2e8f9f7 77 __IO uint32_t sys_clk_ctrl_3_prng; /* 0x004C Control Settings for CLK3 - PRNG Clock */
<> 144:ef7eb2e8f9f7 78 __IO uint32_t sys_clk_ctrl_4_wdt0; /* 0x0050 Control Settings for CLK4 - Watchdog Timer 0 */
<> 144:ef7eb2e8f9f7 79 __IO uint32_t sys_clk_ctrl_5_wdt1; /* 0x0054 Control Settings for CLK5 - Watchdog Timer 1 */
<> 144:ef7eb2e8f9f7 80 __IO uint32_t sys_clk_ctrl_6_gpio; /* 0x0058 Control Settings for CLK6 - Clock for GPIO Ports */
<> 144:ef7eb2e8f9f7 81 __IO uint32_t sys_clk_ctrl_7_pt; /* 0x005C Control Settings for CLK7 - Source Clock for All Pulse Trains */
<> 144:ef7eb2e8f9f7 82 __IO uint32_t sys_clk_ctrl_8_uart; /* 0x0060 Control Settings for CLK8 - Source Clock for All UARTs */
<> 144:ef7eb2e8f9f7 83 __IO uint32_t sys_clk_ctrl_9_i2cm; /* 0x0064 Control Settings for CLK9 - Source Clock for All I2C Masters */
<> 144:ef7eb2e8f9f7 84 __IO uint32_t sys_clk_ctrl_10_i2cs; /* 0x0068 Control Settings for CLK10 - Source Clock for I2C Slave */
<> 144:ef7eb2e8f9f7 85 __IO uint32_t sys_clk_ctrl_11_spi0; /* 0x006C Control Settings for CLK11 - SPI Master 0 */
<> 144:ef7eb2e8f9f7 86 __IO uint32_t sys_clk_ctrl_12_spi1; /* 0x0070 Control Settings for CLK12 - SPI Master 1 */
<> 144:ef7eb2e8f9f7 87 __IO uint32_t sys_clk_ctrl_13_spi2; /* 0x0074 Control Settings for CLK13 - SPI Master 2 */
<> 144:ef7eb2e8f9f7 88 __IO uint32_t sys_clk_ctrl_14_spib; /* 0x0078 Control Settings for CLK14 - SPI Bridge Clock */
<> 144:ef7eb2e8f9f7 89 __IO uint32_t sys_clk_ctrl_15_owm; /* 0x007C Control Settings for CLK15 - 1-Wire Master Clock */
<> 144:ef7eb2e8f9f7 90 __I uint32_t rsv080[32]; /* 0x0080-0x00FC */
<> 144:ef7eb2e8f9f7 91 __IO uint32_t crypt_clk_ctrl_0_aes; /* 0x0100 Control Settings for Crypto Clock 0 - AES */
<> 144:ef7eb2e8f9f7 92 __IO uint32_t crypt_clk_ctrl_1_maa; /* 0x0104 Control Settings for Crypto Clock 1 - MAA */
<> 144:ef7eb2e8f9f7 93 __IO uint32_t crypt_clk_ctrl_2_prng; /* 0x0108 Control Settings for Crypto Clock 2 - PRNG */
<> 144:ef7eb2e8f9f7 94 __I uint32_t rsv10C[13]; /* 0x010C-0x013C */
<> 144:ef7eb2e8f9f7 95 __IO uint32_t clk_gate_ctrl0; /* 0x0140 Dynamic Clock Gating Control Register 0 */
<> 144:ef7eb2e8f9f7 96 __IO uint32_t clk_gate_ctrl1; /* 0x0144 Dynamic Clock Gating Control Register 1 */
<> 144:ef7eb2e8f9f7 97 __IO uint32_t clk_gate_ctrl2; /* 0x0148 Dynamic Clock Gating Control Register 2 */
<> 144:ef7eb2e8f9f7 98 } mxc_clkman_regs_t;
<> 144:ef7eb2e8f9f7 99
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 /*
<> 144:ef7eb2e8f9f7 102 Register offsets for module CLKMAN.
<> 144:ef7eb2e8f9f7 103 */
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 #define MXC_R_CLKMAN_OFFS_CLK_CONFIG ((uint32_t)0x00000000UL)
<> 144:ef7eb2e8f9f7 106 #define MXC_R_CLKMAN_OFFS_CLK_CTRL ((uint32_t)0x00000004UL)
<> 144:ef7eb2e8f9f7 107 #define MXC_R_CLKMAN_OFFS_INTFL ((uint32_t)0x00000008UL)
<> 144:ef7eb2e8f9f7 108 #define MXC_R_CLKMAN_OFFS_INTEN ((uint32_t)0x0000000CUL)
<> 144:ef7eb2e8f9f7 109 #define MXC_R_CLKMAN_OFFS_TRIM_CALC ((uint32_t)0x00000010UL)
<> 144:ef7eb2e8f9f7 110 #define MXC_R_CLKMAN_OFFS_I2C_TIMER_CTRL ((uint32_t)0x00000014UL)
<> 144:ef7eb2e8f9f7 111 #define MXC_R_CLKMAN_OFFS_CM4_START_CLK_EN0 ((uint32_t)0x00000018UL)
<> 144:ef7eb2e8f9f7 112 #define MXC_R_CLKMAN_OFFS_CM4_START_CLK_EN1 ((uint32_t)0x0000001CUL)
<> 144:ef7eb2e8f9f7 113 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_0_CM4 ((uint32_t)0x00000040UL)
<> 144:ef7eb2e8f9f7 114 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_1_SYNC ((uint32_t)0x00000044UL)
<> 144:ef7eb2e8f9f7 115 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_2_SPIX ((uint32_t)0x00000048UL)
<> 144:ef7eb2e8f9f7 116 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_3_PRNG ((uint32_t)0x0000004CUL)
<> 144:ef7eb2e8f9f7 117 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_4_WDT0 ((uint32_t)0x00000050UL)
<> 144:ef7eb2e8f9f7 118 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_5_WDT1 ((uint32_t)0x00000054UL)
<> 144:ef7eb2e8f9f7 119 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_6_GPIO ((uint32_t)0x00000058UL)
<> 144:ef7eb2e8f9f7 120 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_7_PT ((uint32_t)0x0000005CUL)
<> 144:ef7eb2e8f9f7 121 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_8_UART ((uint32_t)0x00000060UL)
<> 144:ef7eb2e8f9f7 122 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_9_I2CM ((uint32_t)0x00000064UL)
<> 144:ef7eb2e8f9f7 123 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_10_I2CS ((uint32_t)0x00000068UL)
<> 144:ef7eb2e8f9f7 124 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_11_SPI0 ((uint32_t)0x0000006CUL)
<> 144:ef7eb2e8f9f7 125 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_12_SPI1 ((uint32_t)0x00000070UL)
<> 144:ef7eb2e8f9f7 126 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_13_SPI2 ((uint32_t)0x00000074UL)
<> 144:ef7eb2e8f9f7 127 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_14_SPIB ((uint32_t)0x00000078UL)
<> 144:ef7eb2e8f9f7 128 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_15_OWM ((uint32_t)0x0000007CUL)
<> 144:ef7eb2e8f9f7 129 #define MXC_R_CLKMAN_OFFS_CRYPT_CLK_CTRL_0_AES ((uint32_t)0x00000100UL)
<> 144:ef7eb2e8f9f7 130 #define MXC_R_CLKMAN_OFFS_CRYPT_CLK_CTRL_1_MAA ((uint32_t)0x00000104UL)
<> 144:ef7eb2e8f9f7 131 #define MXC_R_CLKMAN_OFFS_CRYPT_CLK_CTRL_2_PRNG ((uint32_t)0x00000108UL)
<> 144:ef7eb2e8f9f7 132 #define MXC_R_CLKMAN_OFFS_CLK_GATE_CTRL0 ((uint32_t)0x00000140UL)
<> 144:ef7eb2e8f9f7 133 #define MXC_R_CLKMAN_OFFS_CLK_GATE_CTRL1 ((uint32_t)0x00000144UL)
<> 144:ef7eb2e8f9f7 134 #define MXC_R_CLKMAN_OFFS_CLK_GATE_CTRL2 ((uint32_t)0x00000148UL)
<> 144:ef7eb2e8f9f7 135
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 /*
<> 144:ef7eb2e8f9f7 138 Field positions and masks for module CLKMAN.
<> 144:ef7eb2e8f9f7 139 */
<> 144:ef7eb2e8f9f7 140
<> 144:ef7eb2e8f9f7 141 #define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE_POS 0
<> 144:ef7eb2e8f9f7 142 #define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE_POS))
<> 144:ef7eb2e8f9f7 143 #define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS 4
<> 144:ef7eb2e8f9f7 144 #define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
<> 144:ef7eb2e8f9f7 145
<> 144:ef7eb2e8f9f7 146 #define MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS 0
<> 144:ef7eb2e8f9f7 147 #define MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS))
<> 144:ef7eb2e8f9f7 148 #define MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_ENABLE_POS 4
<> 144:ef7eb2e8f9f7 149 #define MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_ENABLE_POS))
<> 144:ef7eb2e8f9f7 150 #define MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_SELECT_POS 5
<> 144:ef7eb2e8f9f7 151 #define MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_SELECT ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_SELECT_POS))
<> 144:ef7eb2e8f9f7 152 #define MXC_F_CLKMAN_CLK_CTRL_CRYPTO_CLOCK_ENABLE_POS 8
<> 144:ef7eb2e8f9f7 153 #define MXC_F_CLKMAN_CLK_CTRL_CRYPTO_CLOCK_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_CRYPTO_CLOCK_ENABLE_POS))
<> 144:ef7eb2e8f9f7 154 #define MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE_POS 12
<> 144:ef7eb2e8f9f7 155 #define MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE_POS))
<> 144:ef7eb2e8f9f7 156 #define MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_ENABLE_POS 16
<> 144:ef7eb2e8f9f7 157 #define MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_ENABLE_POS))
<> 144:ef7eb2e8f9f7 158 #define MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT_POS 17
<> 144:ef7eb2e8f9f7 159 #define MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT_POS))
<> 144:ef7eb2e8f9f7 160 #define MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_ENABLE_POS 20
<> 144:ef7eb2e8f9f7 161 #define MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_ENABLE_POS))
<> 144:ef7eb2e8f9f7 162 #define MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT_POS 21
<> 144:ef7eb2e8f9f7 163 #define MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT_POS))
<> 144:ef7eb2e8f9f7 164 #define MXC_F_CLKMAN_CLK_CTRL_ADC_CLOCK_ENABLE_POS 24
<> 144:ef7eb2e8f9f7 165 #define MXC_F_CLKMAN_CLK_CTRL_ADC_CLOCK_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_ADC_CLOCK_ENABLE_POS))
<> 144:ef7eb2e8f9f7 166
<> 144:ef7eb2e8f9f7 167 #define MXC_F_CLKMAN_INTFL_CRYPTO_STABLE_POS 0
<> 144:ef7eb2e8f9f7 168 #define MXC_F_CLKMAN_INTFL_CRYPTO_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTFL_CRYPTO_STABLE_POS))
<> 144:ef7eb2e8f9f7 169
<> 144:ef7eb2e8f9f7 170 #define MXC_F_CLKMAN_INTEN_CRYPTO_STABLE_POS 0
<> 144:ef7eb2e8f9f7 171 #define MXC_F_CLKMAN_INTEN_CRYPTO_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTEN_CRYPTO_STABLE_POS))
<> 144:ef7eb2e8f9f7 172
<> 144:ef7eb2e8f9f7 173 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CLK_SEL_POS 0
<> 144:ef7eb2e8f9f7 174 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CLK_SEL ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CLK_SEL_POS))
<> 144:ef7eb2e8f9f7 175 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_START_POS 1
<> 144:ef7eb2e8f9f7 176 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_START ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_START_POS))
<> 144:ef7eb2e8f9f7 177 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_COMPLETED_POS 2
<> 144:ef7eb2e8f9f7 178 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_COMPLETED ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_COMPLETED_POS))
<> 144:ef7eb2e8f9f7 179 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_ENABLE_POS 3
<> 144:ef7eb2e8f9f7 180 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_ENABLE_POS))
<> 144:ef7eb2e8f9f7 181 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_RESULTS_POS 16
<> 144:ef7eb2e8f9f7 182 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_RESULTS ((uint32_t)(0x000003FFUL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_RESULTS_POS))
<> 144:ef7eb2e8f9f7 183
<> 144:ef7eb2e8f9f7 184 #define MXC_F_CLKMAN_I2C_TIMER_CTRL_I2C_1MS_TIMER_EN_POS 0
<> 144:ef7eb2e8f9f7 185 #define MXC_F_CLKMAN_I2C_TIMER_CTRL_I2C_1MS_TIMER_EN ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_I2C_TIMER_CTRL_I2C_1MS_TIMER_EN_POS))
<> 144:ef7eb2e8f9f7 186
<> 144:ef7eb2e8f9f7 187 #define MXC_F_CLKMAN_CM4_START_CLK_EN0_INTS_POS 0
<> 144:ef7eb2e8f9f7 188 #define MXC_F_CLKMAN_CM4_START_CLK_EN0_INTS ((uint32_t)(0xFFFFFFFFUL << MXC_F_CLKMAN_CM4_START_CLK_EN0_INTS_POS))
<> 144:ef7eb2e8f9f7 189
<> 144:ef7eb2e8f9f7 190 #define MXC_F_CLKMAN_CM4_START_CLK_EN1_INTS_POS 0
<> 144:ef7eb2e8f9f7 191 #define MXC_F_CLKMAN_CM4_START_CLK_EN1_INTS ((uint32_t)(0xFFFFFFFFUL << MXC_F_CLKMAN_CM4_START_CLK_EN1_INTS_POS))
<> 144:ef7eb2e8f9f7 192
<> 144:ef7eb2e8f9f7 193 #define MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS 0
<> 144:ef7eb2e8f9f7 194 #define MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
<> 144:ef7eb2e8f9f7 195
<> 144:ef7eb2e8f9f7 196 #define MXC_F_CLKMAN_SYS_CLK_CTRL_1_SYNC_SYNC_CLK_SCALE_POS 0
<> 144:ef7eb2e8f9f7 197 #define MXC_F_CLKMAN_SYS_CLK_CTRL_1_SYNC_SYNC_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_1_SYNC_SYNC_CLK_SCALE_POS))
<> 144:ef7eb2e8f9f7 198
<> 144:ef7eb2e8f9f7 199 #define MXC_F_CLKMAN_SYS_CLK_CTRL_2_SPIX_SPIX_CLK_SCALE_POS 0
<> 144:ef7eb2e8f9f7 200 #define MXC_F_CLKMAN_SYS_CLK_CTRL_2_SPIX_SPIX_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_2_SPIX_SPIX_CLK_SCALE_POS))
<> 144:ef7eb2e8f9f7 201
<> 144:ef7eb2e8f9f7 202 #define MXC_F_CLKMAN_SYS_CLK_CTRL_3_PRNG_PRNG_CLK_SCALE_POS 0
<> 144:ef7eb2e8f9f7 203 #define MXC_F_CLKMAN_SYS_CLK_CTRL_3_PRNG_PRNG_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_3_PRNG_PRNG_CLK_SCALE_POS))
<> 144:ef7eb2e8f9f7 204
<> 144:ef7eb2e8f9f7 205 #define MXC_F_CLKMAN_SYS_CLK_CTRL_4_WDT0_WATCHDOG0_CLK_SCALE_POS 0
<> 144:ef7eb2e8f9f7 206 #define MXC_F_CLKMAN_SYS_CLK_CTRL_4_WDT0_WATCHDOG0_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_4_WDT0_WATCHDOG0_CLK_SCALE_POS))
<> 144:ef7eb2e8f9f7 207
<> 144:ef7eb2e8f9f7 208 #define MXC_F_CLKMAN_SYS_CLK_CTRL_5_WDT1_WATCHDOG1_CLK_SCALE_POS 0
<> 144:ef7eb2e8f9f7 209 #define MXC_F_CLKMAN_SYS_CLK_CTRL_5_WDT1_WATCHDOG1_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_5_WDT1_WATCHDOG1_CLK_SCALE_POS))
<> 144:ef7eb2e8f9f7 210
<> 144:ef7eb2e8f9f7 211 #define MXC_F_CLKMAN_SYS_CLK_CTRL_6_GPIO_GPIO_CLK_SCALE_POS 0
<> 144:ef7eb2e8f9f7 212 #define MXC_F_CLKMAN_SYS_CLK_CTRL_6_GPIO_GPIO_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_6_GPIO_GPIO_CLK_SCALE_POS))
<> 144:ef7eb2e8f9f7 213
<> 144:ef7eb2e8f9f7 214 #define MXC_F_CLKMAN_SYS_CLK_CTRL_7_PT_PULSE_TRAIN_CLK_SCALE_POS 0
<> 144:ef7eb2e8f9f7 215 #define MXC_F_CLKMAN_SYS_CLK_CTRL_7_PT_PULSE_TRAIN_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_7_PT_PULSE_TRAIN_CLK_SCALE_POS))
<> 144:ef7eb2e8f9f7 216
<> 144:ef7eb2e8f9f7 217 #define MXC_F_CLKMAN_SYS_CLK_CTRL_8_UART_UART_CLK_SCALE_POS 0
<> 144:ef7eb2e8f9f7 218 #define MXC_F_CLKMAN_SYS_CLK_CTRL_8_UART_UART_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_8_UART_UART_CLK_SCALE_POS))
<> 144:ef7eb2e8f9f7 219
<> 144:ef7eb2e8f9f7 220 #define MXC_F_CLKMAN_SYS_CLK_CTRL_9_I2CM_I2CM_CLK_SCALE_POS 0
<> 144:ef7eb2e8f9f7 221 #define MXC_F_CLKMAN_SYS_CLK_CTRL_9_I2CM_I2CM_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_9_I2CM_I2CM_CLK_SCALE_POS))
<> 144:ef7eb2e8f9f7 222
<> 144:ef7eb2e8f9f7 223 #define MXC_F_CLKMAN_SYS_CLK_CTRL_10_I2CS_I2CS_CLK_SCALE_POS 0
<> 144:ef7eb2e8f9f7 224 #define MXC_F_CLKMAN_SYS_CLK_CTRL_10_I2CS_I2CS_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_10_I2CS_I2CS_CLK_SCALE_POS))
<> 144:ef7eb2e8f9f7 225
<> 144:ef7eb2e8f9f7 226 #define MXC_F_CLKMAN_SYS_CLK_CTRL_11_SPI0_SPI0_CLK_SCALE_POS 0
<> 144:ef7eb2e8f9f7 227 #define MXC_F_CLKMAN_SYS_CLK_CTRL_11_SPI0_SPI0_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_11_SPI0_SPI0_CLK_SCALE_POS))
<> 144:ef7eb2e8f9f7 228
<> 144:ef7eb2e8f9f7 229 #define MXC_F_CLKMAN_SYS_CLK_CTRL_12_SPI1_SPI1_CLK_SCALE_POS 0
<> 144:ef7eb2e8f9f7 230 #define MXC_F_CLKMAN_SYS_CLK_CTRL_12_SPI1_SPI1_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_12_SPI1_SPI1_CLK_SCALE_POS))
<> 144:ef7eb2e8f9f7 231
<> 144:ef7eb2e8f9f7 232 #define MXC_F_CLKMAN_SYS_CLK_CTRL_13_SPI2_SPI2_CLK_SCALE_POS 0
<> 144:ef7eb2e8f9f7 233 #define MXC_F_CLKMAN_SYS_CLK_CTRL_13_SPI2_SPI2_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_13_SPI2_SPI2_CLK_SCALE_POS))
<> 144:ef7eb2e8f9f7 234
<> 144:ef7eb2e8f9f7 235 #define MXC_F_CLKMAN_SYS_CLK_CTRL_14_SPIB_SPIB_CLK_SCALE_POS 0
<> 144:ef7eb2e8f9f7 236 #define MXC_F_CLKMAN_SYS_CLK_CTRL_14_SPIB_SPIB_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_14_SPIB_SPIB_CLK_SCALE_POS))
<> 144:ef7eb2e8f9f7 237
<> 144:ef7eb2e8f9f7 238 #define MXC_F_CLKMAN_SYS_CLK_CTRL_15_OWM_OWM_CLK_SCALE_POS 0
<> 144:ef7eb2e8f9f7 239 #define MXC_F_CLKMAN_SYS_CLK_CTRL_15_OWM_OWM_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_15_OWM_OWM_CLK_SCALE_POS))
<> 144:ef7eb2e8f9f7 240
<> 144:ef7eb2e8f9f7 241 #define MXC_F_CLKMAN_CRYPT_CLK_CTRL_0_AES_AES_CLK_SCALE_POS 0
<> 144:ef7eb2e8f9f7 242 #define MXC_F_CLKMAN_CRYPT_CLK_CTRL_0_AES_AES_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CRYPT_CLK_CTRL_0_AES_AES_CLK_SCALE_POS))
<> 144:ef7eb2e8f9f7 243
<> 144:ef7eb2e8f9f7 244 #define MXC_F_CLKMAN_CRYPT_CLK_CTRL_1_MAA_MAA_CLK_SCALE_POS 0
<> 144:ef7eb2e8f9f7 245 #define MXC_F_CLKMAN_CRYPT_CLK_CTRL_1_MAA_MAA_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CRYPT_CLK_CTRL_1_MAA_MAA_CLK_SCALE_POS))
<> 144:ef7eb2e8f9f7 246
<> 144:ef7eb2e8f9f7 247 #define MXC_F_CLKMAN_CRYPT_CLK_CTRL_2_PRNG_PRNG_CLK_SCALE_POS 0
<> 144:ef7eb2e8f9f7 248 #define MXC_F_CLKMAN_CRYPT_CLK_CTRL_2_PRNG_PRNG_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CRYPT_CLK_CTRL_2_PRNG_PRNG_CLK_SCALE_POS))
<> 144:ef7eb2e8f9f7 249
<> 144:ef7eb2e8f9f7 250 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_CM4_CLK_GATER_POS 0
<> 144:ef7eb2e8f9f7 251 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_CM4_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_CM4_CLK_GATER_POS))
<> 144:ef7eb2e8f9f7 252 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_AHB32_CLK_GATER_POS 2
<> 144:ef7eb2e8f9f7 253 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_AHB32_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_AHB32_CLK_GATER_POS))
<> 144:ef7eb2e8f9f7 254 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER_POS 4
<> 144:ef7eb2e8f9f7 255 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER_POS))
<> 144:ef7eb2e8f9f7 256 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_FLASH_CLK_GATER_POS 6
<> 144:ef7eb2e8f9f7 257 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_FLASH_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_FLASH_CLK_GATER_POS))
<> 144:ef7eb2e8f9f7 258 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SRAM_CLK_GATER_POS 8
<> 144:ef7eb2e8f9f7 259 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SRAM_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SRAM_CLK_GATER_POS))
<> 144:ef7eb2e8f9f7 260 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_APB_BRIDGE_CLK_GATER_POS 10
<> 144:ef7eb2e8f9f7 261 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_APB_BRIDGE_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_APB_BRIDGE_CLK_GATER_POS))
<> 144:ef7eb2e8f9f7 262 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSMAN_CLK_GATER_POS 12
<> 144:ef7eb2e8f9f7 263 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSMAN_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSMAN_CLK_GATER_POS))
<> 144:ef7eb2e8f9f7 264 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_PTP_CLK_GATER_POS 14
<> 144:ef7eb2e8f9f7 265 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_PTP_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_PTP_CLK_GATER_POS))
<> 144:ef7eb2e8f9f7 266 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SSB_MUX_CLK_GATER_POS 16
<> 144:ef7eb2e8f9f7 267 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SSB_MUX_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SSB_MUX_CLK_GATER_POS))
<> 144:ef7eb2e8f9f7 268 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_PAD_CLK_GATER_POS 18
<> 144:ef7eb2e8f9f7 269 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_PAD_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_PAD_CLK_GATER_POS))
<> 144:ef7eb2e8f9f7 270 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SPIX_CLK_GATER_POS 20
<> 144:ef7eb2e8f9f7 271 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SPIX_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SPIX_CLK_GATER_POS))
<> 144:ef7eb2e8f9f7 272 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_PMU_CLK_GATER_POS 22
<> 144:ef7eb2e8f9f7 273 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_PMU_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_PMU_CLK_GATER_POS))
<> 144:ef7eb2e8f9f7 274 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER_POS 24
<> 144:ef7eb2e8f9f7 275 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER_POS))
<> 144:ef7eb2e8f9f7 276 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_CRC_CLK_GATER_POS 26
<> 144:ef7eb2e8f9f7 277 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_CRC_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_CRC_CLK_GATER_POS))
<> 144:ef7eb2e8f9f7 278 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_TPU_CLK_GATER_POS 28
<> 144:ef7eb2e8f9f7 279 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_TPU_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_TPU_CLK_GATER_POS))
<> 144:ef7eb2e8f9f7 280 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG0_CLK_GATER_POS 30
<> 144:ef7eb2e8f9f7 281 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG0_CLK_GATER_POS))
<> 144:ef7eb2e8f9f7 282
<> 144:ef7eb2e8f9f7 283 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_WATCHDOG1_CLK_GATER_POS 0
<> 144:ef7eb2e8f9f7 284 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_WATCHDOG1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_WATCHDOG1_CLK_GATER_POS))
<> 144:ef7eb2e8f9f7 285 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER_POS 2
<> 144:ef7eb2e8f9f7 286 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER_POS))
<> 144:ef7eb2e8f9f7 287 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER0_CLK_GATER_POS 4
<> 144:ef7eb2e8f9f7 288 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER0_CLK_GATER_POS))
<> 144:ef7eb2e8f9f7 289 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER1_CLK_GATER_POS 6
<> 144:ef7eb2e8f9f7 290 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER1_CLK_GATER_POS))
<> 144:ef7eb2e8f9f7 291 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER2_CLK_GATER_POS 8
<> 144:ef7eb2e8f9f7 292 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER2_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER2_CLK_GATER_POS))
<> 144:ef7eb2e8f9f7 293 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER3_CLK_GATER_POS 10
<> 144:ef7eb2e8f9f7 294 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER3_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER3_CLK_GATER_POS))
<> 144:ef7eb2e8f9f7 295 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER4_CLK_GATER_POS 12
<> 144:ef7eb2e8f9f7 296 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER4_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER4_CLK_GATER_POS))
<> 144:ef7eb2e8f9f7 297 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER5_CLK_GATER_POS 14
<> 144:ef7eb2e8f9f7 298 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER5_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER5_CLK_GATER_POS))
<> 144:ef7eb2e8f9f7 299 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_PULSETRAIN_CLK_GATER_POS 16
<> 144:ef7eb2e8f9f7 300 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_PULSETRAIN_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_PULSETRAIN_CLK_GATER_POS))
<> 144:ef7eb2e8f9f7 301 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART0_CLK_GATER_POS 18
<> 144:ef7eb2e8f9f7 302 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_UART0_CLK_GATER_POS))
<> 144:ef7eb2e8f9f7 303 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART1_CLK_GATER_POS 20
<> 144:ef7eb2e8f9f7 304 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_UART1_CLK_GATER_POS))
<> 144:ef7eb2e8f9f7 305 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART2_CLK_GATER_POS 22
<> 144:ef7eb2e8f9f7 306 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART2_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_UART2_CLK_GATER_POS))
<> 144:ef7eb2e8f9f7 307 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART3_CLK_GATER_POS 24
<> 144:ef7eb2e8f9f7 308 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART3_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_UART3_CLK_GATER_POS))
<> 144:ef7eb2e8f9f7 309 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM0_CLK_GATER_POS 26
<> 144:ef7eb2e8f9f7 310 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM0_CLK_GATER_POS))
<> 144:ef7eb2e8f9f7 311 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM1_CLK_GATER_POS 28
<> 144:ef7eb2e8f9f7 312 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM1_CLK_GATER_POS))
<> 144:ef7eb2e8f9f7 313 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM2_CLK_GATER_POS 30
<> 144:ef7eb2e8f9f7 314 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM2_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM2_CLK_GATER_POS))
<> 144:ef7eb2e8f9f7 315
<> 144:ef7eb2e8f9f7 316 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_I2CS_CLK_GATER_POS 0
<> 144:ef7eb2e8f9f7 317 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_I2CS_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_I2CS_CLK_GATER_POS))
<> 144:ef7eb2e8f9f7 318 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI0_CLK_GATER_POS 2
<> 144:ef7eb2e8f9f7 319 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI0_CLK_GATER_POS))
<> 144:ef7eb2e8f9f7 320 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI1_CLK_GATER_POS 4
<> 144:ef7eb2e8f9f7 321 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI1_CLK_GATER_POS))
<> 144:ef7eb2e8f9f7 322 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI2_CLK_GATER_POS 6
<> 144:ef7eb2e8f9f7 323 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI2_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI2_CLK_GATER_POS))
<> 144:ef7eb2e8f9f7 324 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI_BRIDGE_CLK_GATER_POS 8
<> 144:ef7eb2e8f9f7 325 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI_BRIDGE_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI_BRIDGE_CLK_GATER_POS))
<> 144:ef7eb2e8f9f7 326 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_OWM_CLK_GATER_POS 10
<> 144:ef7eb2e8f9f7 327 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_OWM_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_OWM_CLK_GATER_POS))
<> 144:ef7eb2e8f9f7 328 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_ADC_CLK_GATER_POS 12
<> 144:ef7eb2e8f9f7 329 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_ADC_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_ADC_CLK_GATER_POS))
<> 144:ef7eb2e8f9f7 330
<> 144:ef7eb2e8f9f7 331
<> 144:ef7eb2e8f9f7 332
<> 144:ef7eb2e8f9f7 333 /*
<> 144:ef7eb2e8f9f7 334 Field values and shifted values for module CLKMAN.
<> 144:ef7eb2e8f9f7 335 */
<> 144:ef7eb2e8f9f7 336
<> 144:ef7eb2e8f9f7 337 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_8_CLOCKS ((uint32_t)(0x00000000UL))
<> 144:ef7eb2e8f9f7 338 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_9_CLOCKS ((uint32_t)(0x00000001UL))
<> 144:ef7eb2e8f9f7 339 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_10_CLOCKS ((uint32_t)(0x00000002UL))
<> 144:ef7eb2e8f9f7 340 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_11_CLOCKS ((uint32_t)(0x00000003UL))
<> 144:ef7eb2e8f9f7 341 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_12_CLOCKS ((uint32_t)(0x00000004UL))
<> 144:ef7eb2e8f9f7 342 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_13_CLOCKS ((uint32_t)(0x00000005UL))
<> 144:ef7eb2e8f9f7 343 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_14_CLOCKS ((uint32_t)(0x00000006UL))
<> 144:ef7eb2e8f9f7 344 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_15_CLOCKS ((uint32_t)(0x00000007UL))
<> 144:ef7eb2e8f9f7 345 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_16_CLOCKS ((uint32_t)(0x00000008UL))
<> 144:ef7eb2e8f9f7 346 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_17_CLOCKS ((uint32_t)(0x00000009UL))
<> 144:ef7eb2e8f9f7 347 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_18_CLOCKS ((uint32_t)(0x0000000AUL))
<> 144:ef7eb2e8f9f7 348 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_19_CLOCKS ((uint32_t)(0x0000000BUL))
<> 144:ef7eb2e8f9f7 349 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_20_CLOCKS ((uint32_t)(0x0000000CUL))
<> 144:ef7eb2e8f9f7 350 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_21_CLOCKS ((uint32_t)(0x0000000DUL))
<> 144:ef7eb2e8f9f7 351 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_22_CLOCKS ((uint32_t)(0x0000000EUL))
<> 144:ef7eb2e8f9f7 352 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_23_CLOCKS ((uint32_t)(0x0000000FUL))
<> 144:ef7eb2e8f9f7 353
<> 144:ef7eb2e8f9f7 354 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_8_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_8_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
<> 144:ef7eb2e8f9f7 355 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_9_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_9_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
<> 144:ef7eb2e8f9f7 356 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_10_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_10_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
<> 144:ef7eb2e8f9f7 357 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_11_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_11_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
<> 144:ef7eb2e8f9f7 358 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_12_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_12_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
<> 144:ef7eb2e8f9f7 359 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_13_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_13_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
<> 144:ef7eb2e8f9f7 360 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_14_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_14_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
<> 144:ef7eb2e8f9f7 361 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_15_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_15_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
<> 144:ef7eb2e8f9f7 362 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_16_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_16_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
<> 144:ef7eb2e8f9f7 363 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_17_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_17_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
<> 144:ef7eb2e8f9f7 364 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_18_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_18_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
<> 144:ef7eb2e8f9f7 365 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_19_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_19_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
<> 144:ef7eb2e8f9f7 366 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_20_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_20_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
<> 144:ef7eb2e8f9f7 367 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_21_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_21_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
<> 144:ef7eb2e8f9f7 368 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_22_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_22_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
<> 144:ef7eb2e8f9f7 369 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_23_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_23_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
<> 144:ef7eb2e8f9f7 370
<> 144:ef7eb2e8f9f7 371 #define MXC_V_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO_DIV_2 ((uint32_t)(0x00000000UL))
<> 144:ef7eb2e8f9f7 372 #define MXC_V_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO ((uint32_t)(0x00000001UL))
<> 144:ef7eb2e8f9f7 373
<> 144:ef7eb2e8f9f7 374 #define MXC_S_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO_DIV_2 ((uint32_t)(MXC_V_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO_DIV_2 << MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS))
<> 144:ef7eb2e8f9f7 375 #define MXC_S_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO ((uint32_t)(MXC_V_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO << MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS))
<> 144:ef7eb2e8f9f7 376
<> 144:ef7eb2e8f9f7 377 #define MXC_V_CLKMAN_WDT0_CLOCK_SELECT_SCALED_SYS_CLK_CTRL_4_WDT0 ((uint32_t)(0x00000000UL))
<> 144:ef7eb2e8f9f7 378 #define MXC_V_CLKMAN_WDT0_CLOCK_SELECT_32KHZ_RTC_OSCILLATOR ((uint32_t)(0x00000001UL))
<> 144:ef7eb2e8f9f7 379 #define MXC_V_CLKMAN_WDT0_CLOCK_SELECT_96MHZ_OSCILLATOR ((uint32_t)(0x00000002UL))
<> 144:ef7eb2e8f9f7 380 #define MXC_V_CLKMAN_WDT0_CLOCK_SELECT_NANO_RING_OSCILLATOR ((uint32_t)(0x00000003UL))
<> 144:ef7eb2e8f9f7 381
<> 144:ef7eb2e8f9f7 382 #define MXC_S_CLKMAN_WDT0_CLOCK_SELECT_SCALED_SYS_CLK_CTRL_4_WDT0 ((uint32_t)(MXC_V_CLKMAN_WDT0_CLOCK_SELECT_SCALED_SYS_CLK_CTRL_4_WDT0 << MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT_POS))
<> 144:ef7eb2e8f9f7 383 #define MXC_S_CLKMAN_WDT0_CLOCK_SELECT_32KHZ_RTC_OSCILLATOR ((uint32_t)(MXC_V_CLKMAN_WDT0_CLOCK_SELECT_32KHZ_RTC_OSCILLATOR << MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT_POS))
<> 144:ef7eb2e8f9f7 384 #define MXC_S_CLKMAN_WDT0_CLOCK_SELECT_96MHZ_OSCILLATOR ((uint32_t)(MXC_V_CLKMAN_WDT0_CLOCK_SELECT_96MHZ_OSCILLATOR << MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT_POS))
<> 144:ef7eb2e8f9f7 385 #define MXC_S_CLKMAN_WDT0_CLOCK_SELECT_NANO_RING_OSCILLATOR ((uint32_t)(MXC_V_CLKMAN_WDT0_CLOCK_SELECT_NANO_RING_OSCILLATOR << MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT_POS))
<> 144:ef7eb2e8f9f7 386
<> 144:ef7eb2e8f9f7 387 #define MXC_V_CLKMAN_WDT1_CLOCK_SELECT_SCALED_SYS_CLK_CTRL_4_WDT1 ((uint32_t)(0x00000000UL))
<> 144:ef7eb2e8f9f7 388 #define MXC_V_CLKMAN_WDT1_CLOCK_SELECT_32KHZ_RTC_OSCILLATOR ((uint32_t)(0x00000001UL))
<> 144:ef7eb2e8f9f7 389 #define MXC_V_CLKMAN_WDT1_CLOCK_SELECT_96MHZ_OSCILLATOR ((uint32_t)(0x00000002UL))
<> 144:ef7eb2e8f9f7 390 #define MXC_V_CLKMAN_WDT1_CLOCK_SELECT_NANO_RING_OSCILLATOR ((uint32_t)(0x00000003UL))
<> 144:ef7eb2e8f9f7 391
<> 144:ef7eb2e8f9f7 392 #define MXC_S_CLKMAN_WDT1_CLOCK_SELECT_SCALED_SYS_CLK_CTRL_4_WDT1 ((uint32_t)(MXC_V_CLKMAN_WDT1_CLOCK_SELECT_SCALED_SYS_CLK_CTRL_4_WDT1 << MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT_POS))
<> 144:ef7eb2e8f9f7 393 #define MXC_S_CLKMAN_WDT1_CLOCK_SELECT_32KHZ_RTC_OSCILLATOR ((uint32_t)(MXC_V_CLKMAN_WDT1_CLOCK_SELECT_32KHZ_RTC_OSCILLATOR << MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT_POS))
<> 144:ef7eb2e8f9f7 394 #define MXC_S_CLKMAN_WDT1_CLOCK_SELECT_96MHZ_OSCILLATOR ((uint32_t)(MXC_V_CLKMAN_WDT1_CLOCK_SELECT_96MHZ_OSCILLATOR << MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT_POS))
<> 144:ef7eb2e8f9f7 395 #define MXC_S_CLKMAN_WDT1_CLOCK_SELECT_NANO_RING_OSCILLATOR ((uint32_t)(MXC_V_CLKMAN_WDT1_CLOCK_SELECT_NANO_RING_OSCILLATOR << MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT_POS))
<> 144:ef7eb2e8f9f7 396
<> 144:ef7eb2e8f9f7 397 #define MXC_V_CLKMAN_CLK_SCALE_DISABLED ((uint32_t)(0x00000000UL))
<> 144:ef7eb2e8f9f7 398 #define MXC_V_CLKMAN_CLK_SCALE_DIV_1 ((uint32_t)(0x00000001UL))
<> 144:ef7eb2e8f9f7 399 #define MXC_V_CLKMAN_CLK_SCALE_DIV_2 ((uint32_t)(0x00000002UL))
<> 144:ef7eb2e8f9f7 400 #define MXC_V_CLKMAN_CLK_SCALE_DIV_4 ((uint32_t)(0x00000003UL))
<> 144:ef7eb2e8f9f7 401 #define MXC_V_CLKMAN_CLK_SCALE_DIV_8 ((uint32_t)(0x00000004UL))
<> 144:ef7eb2e8f9f7 402 #define MXC_V_CLKMAN_CLK_SCALE_DIV_16 ((uint32_t)(0x00000005UL))
<> 144:ef7eb2e8f9f7 403 #define MXC_V_CLKMAN_CLK_SCALE_DIV_32 ((uint32_t)(0x00000006UL))
<> 144:ef7eb2e8f9f7 404 #define MXC_V_CLKMAN_CLK_SCALE_DIV_64 ((uint32_t)(0x00000007UL))
<> 144:ef7eb2e8f9f7 405 #define MXC_V_CLKMAN_CLK_SCALE_DIV_128 ((uint32_t)(0x00000008UL))
<> 144:ef7eb2e8f9f7 406 #define MXC_V_CLKMAN_CLK_SCALE_DIV_256 ((uint32_t)(0x00000009UL))
<> 144:ef7eb2e8f9f7 407
<> 144:ef7eb2e8f9f7 408 #define MXC_S_CLKMAN_CLK_SCALE_DISABLED ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DISABLED << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
<> 144:ef7eb2e8f9f7 409 #define MXC_S_CLKMAN_CLK_SCALE_DIV_1 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_1 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
<> 144:ef7eb2e8f9f7 410 #define MXC_S_CLKMAN_CLK_SCALE_DIV_2 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_2 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
<> 144:ef7eb2e8f9f7 411 #define MXC_S_CLKMAN_CLK_SCALE_DIV_4 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_4 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
<> 144:ef7eb2e8f9f7 412 #define MXC_S_CLKMAN_CLK_SCALE_DIV_8 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_8 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
<> 144:ef7eb2e8f9f7 413 #define MXC_S_CLKMAN_CLK_SCALE_DIV_16 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_16 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
<> 144:ef7eb2e8f9f7 414 #define MXC_S_CLKMAN_CLK_SCALE_DIV_32 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_32 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
<> 144:ef7eb2e8f9f7 415 #define MXC_S_CLKMAN_CLK_SCALE_DIV_64 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_64 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
<> 144:ef7eb2e8f9f7 416 #define MXC_S_CLKMAN_CLK_SCALE_DIV_128 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_128 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
<> 144:ef7eb2e8f9f7 417 #define MXC_S_CLKMAN_CLK_SCALE_DIV_256 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_256 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
<> 144:ef7eb2e8f9f7 418
<> 144:ef7eb2e8f9f7 419
<> 144:ef7eb2e8f9f7 420
<> 144:ef7eb2e8f9f7 421 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 422 }
<> 144:ef7eb2e8f9f7 423 #endif
<> 144:ef7eb2e8f9f7 424
<> 144:ef7eb2e8f9f7 425 #endif /* _MXC_CLKMAN_REGS_H_ */
<> 144:ef7eb2e8f9f7 426