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targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_adc.h@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Parent:
targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_adc.h@144:ef7eb2e8f9f7
Child:
150:02e0a0aed4ec
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 2 * @file em_adc.h
<> 144:ef7eb2e8f9f7 3 * @brief Analog to Digital Converter (ADC) peripheral API
<> 144:ef7eb2e8f9f7 4 * @version 4.2.1
<> 144:ef7eb2e8f9f7 5 *******************************************************************************
<> 144:ef7eb2e8f9f7 6 * @section License
<> 144:ef7eb2e8f9f7 7 * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
<> 144:ef7eb2e8f9f7 8 *******************************************************************************
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Permission is granted to anyone to use this software for any purpose,
<> 144:ef7eb2e8f9f7 11 * including commercial applications, and to alter it and redistribute it
<> 144:ef7eb2e8f9f7 12 * freely, subject to the following restrictions:
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * 1. The origin of this software must not be misrepresented; you must not
<> 144:ef7eb2e8f9f7 15 * claim that you wrote the original software.
<> 144:ef7eb2e8f9f7 16 * 2. Altered source versions must be plainly marked as such, and must not be
<> 144:ef7eb2e8f9f7 17 * misrepresented as being the original software.
<> 144:ef7eb2e8f9f7 18 * 3. This notice may not be removed or altered from any source distribution.
<> 144:ef7eb2e8f9f7 19 *
<> 144:ef7eb2e8f9f7 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
<> 144:ef7eb2e8f9f7 21 * obligation to support this Software. Silicon Labs is providing the
<> 144:ef7eb2e8f9f7 22 * Software "AS IS", with no express or implied warranties of any kind,
<> 144:ef7eb2e8f9f7 23 * including, but not limited to, any implied warranties of merchantability
<> 144:ef7eb2e8f9f7 24 * or fitness for any particular purpose or warranties against infringement
<> 144:ef7eb2e8f9f7 25 * of any proprietary rights of a third party.
<> 144:ef7eb2e8f9f7 26 *
<> 144:ef7eb2e8f9f7 27 * Silicon Labs will not be liable for any consequential, incidental, or
<> 144:ef7eb2e8f9f7 28 * special damages, or any other relief, or for any claim by any third party,
<> 144:ef7eb2e8f9f7 29 * arising from your use of this Software.
<> 144:ef7eb2e8f9f7 30 *
<> 144:ef7eb2e8f9f7 31 ******************************************************************************/
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 #ifndef __SILICON_LABS_EM_ADC_H__
<> 144:ef7eb2e8f9f7 34 #define __SILICON_LABS_EM_ADC_H__
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 #include "em_device.h"
<> 144:ef7eb2e8f9f7 37 #if defined( ADC_COUNT ) && ( ADC_COUNT > 0 )
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39 #include <stdbool.h>
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 42 extern "C" {
<> 144:ef7eb2e8f9f7 43 #endif
<> 144:ef7eb2e8f9f7 44
<> 144:ef7eb2e8f9f7 45 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 46 * @addtogroup EM_Library
<> 144:ef7eb2e8f9f7 47 * @{
<> 144:ef7eb2e8f9f7 48 ******************************************************************************/
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 51 * @addtogroup ADC
<> 144:ef7eb2e8f9f7 52 * @{
<> 144:ef7eb2e8f9f7 53 ******************************************************************************/
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 /*******************************************************************************
<> 144:ef7eb2e8f9f7 56 ******************************** ENUMS ************************************
<> 144:ef7eb2e8f9f7 57 ******************************************************************************/
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 /** Acquisition time (in ADC clock cycles). */
<> 144:ef7eb2e8f9f7 60 typedef enum
<> 144:ef7eb2e8f9f7 61 {
<> 144:ef7eb2e8f9f7 62 adcAcqTime1 = _ADC_SINGLECTRL_AT_1CYCLE, /**< 1 clock cycle. */
<> 144:ef7eb2e8f9f7 63 adcAcqTime2 = _ADC_SINGLECTRL_AT_2CYCLES, /**< 2 clock cycles. */
<> 144:ef7eb2e8f9f7 64 adcAcqTime4 = _ADC_SINGLECTRL_AT_4CYCLES, /**< 4 clock cycles. */
<> 144:ef7eb2e8f9f7 65 adcAcqTime8 = _ADC_SINGLECTRL_AT_8CYCLES, /**< 8 clock cycles. */
<> 144:ef7eb2e8f9f7 66 adcAcqTime16 = _ADC_SINGLECTRL_AT_16CYCLES, /**< 16 clock cycles. */
<> 144:ef7eb2e8f9f7 67 adcAcqTime32 = _ADC_SINGLECTRL_AT_32CYCLES, /**< 32 clock cycles. */
<> 144:ef7eb2e8f9f7 68 adcAcqTime64 = _ADC_SINGLECTRL_AT_64CYCLES, /**< 64 clock cycles. */
<> 144:ef7eb2e8f9f7 69 adcAcqTime128 = _ADC_SINGLECTRL_AT_128CYCLES, /**< 128 clock cycles. */
<> 144:ef7eb2e8f9f7 70 adcAcqTime256 = _ADC_SINGLECTRL_AT_256CYCLES /**< 256 clock cycles. */
<> 144:ef7eb2e8f9f7 71 } ADC_AcqTime_TypeDef;
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 #if defined( _ADC_CTRL_LPFMODE_MASK )
<> 144:ef7eb2e8f9f7 74 /** Lowpass filter mode. */
<> 144:ef7eb2e8f9f7 75 typedef enum
<> 144:ef7eb2e8f9f7 76 {
<> 144:ef7eb2e8f9f7 77 /** No filter or decoupling capacitor. */
<> 144:ef7eb2e8f9f7 78 adcLPFilterBypass = _ADC_CTRL_LPFMODE_BYPASS,
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80 /** On-chip RC filter. */
<> 144:ef7eb2e8f9f7 81 adcLPFilterRC = _ADC_CTRL_LPFMODE_RCFILT,
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 /** On-chip decoupling capacitor. */
<> 144:ef7eb2e8f9f7 84 adcLPFilterDeCap = _ADC_CTRL_LPFMODE_DECAP
<> 144:ef7eb2e8f9f7 85 } ADC_LPFilter_TypeDef;
<> 144:ef7eb2e8f9f7 86 #endif
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 /** Oversample rate select. */
<> 144:ef7eb2e8f9f7 89 typedef enum
<> 144:ef7eb2e8f9f7 90 {
<> 144:ef7eb2e8f9f7 91 /** 2 samples per conversion result. */
<> 144:ef7eb2e8f9f7 92 adcOvsRateSel2 = _ADC_CTRL_OVSRSEL_X2,
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 /** 4 samples per conversion result. */
<> 144:ef7eb2e8f9f7 95 adcOvsRateSel4 = _ADC_CTRL_OVSRSEL_X4,
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 /** 8 samples per conversion result. */
<> 144:ef7eb2e8f9f7 98 adcOvsRateSel8 = _ADC_CTRL_OVSRSEL_X8,
<> 144:ef7eb2e8f9f7 99
<> 144:ef7eb2e8f9f7 100 /** 16 samples per conversion result. */
<> 144:ef7eb2e8f9f7 101 adcOvsRateSel16 = _ADC_CTRL_OVSRSEL_X16,
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 /** 32 samples per conversion result. */
<> 144:ef7eb2e8f9f7 104 adcOvsRateSel32 = _ADC_CTRL_OVSRSEL_X32,
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 /** 64 samples per conversion result. */
<> 144:ef7eb2e8f9f7 107 adcOvsRateSel64 = _ADC_CTRL_OVSRSEL_X64,
<> 144:ef7eb2e8f9f7 108
<> 144:ef7eb2e8f9f7 109 /** 128 samples per conversion result. */
<> 144:ef7eb2e8f9f7 110 adcOvsRateSel128 = _ADC_CTRL_OVSRSEL_X128,
<> 144:ef7eb2e8f9f7 111
<> 144:ef7eb2e8f9f7 112 /** 256 samples per conversion result. */
<> 144:ef7eb2e8f9f7 113 adcOvsRateSel256 = _ADC_CTRL_OVSRSEL_X256,
<> 144:ef7eb2e8f9f7 114
<> 144:ef7eb2e8f9f7 115 /** 512 samples per conversion result. */
<> 144:ef7eb2e8f9f7 116 adcOvsRateSel512 = _ADC_CTRL_OVSRSEL_X512,
<> 144:ef7eb2e8f9f7 117
<> 144:ef7eb2e8f9f7 118 /** 1024 samples per conversion result. */
<> 144:ef7eb2e8f9f7 119 adcOvsRateSel1024 = _ADC_CTRL_OVSRSEL_X1024,
<> 144:ef7eb2e8f9f7 120
<> 144:ef7eb2e8f9f7 121 /** 2048 samples per conversion result. */
<> 144:ef7eb2e8f9f7 122 adcOvsRateSel2048 = _ADC_CTRL_OVSRSEL_X2048,
<> 144:ef7eb2e8f9f7 123
<> 144:ef7eb2e8f9f7 124 /** 4096 samples per conversion result. */
<> 144:ef7eb2e8f9f7 125 adcOvsRateSel4096 = _ADC_CTRL_OVSRSEL_X4096
<> 144:ef7eb2e8f9f7 126 } ADC_OvsRateSel_TypeDef;
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128
<> 144:ef7eb2e8f9f7 129 /** Peripheral Reflex System signal used to trigger single sample. */
<> 144:ef7eb2e8f9f7 130 typedef enum
<> 144:ef7eb2e8f9f7 131 {
<> 144:ef7eb2e8f9f7 132 #if defined( _ADC_SINGLECTRL_PRSSEL_MASK )
<> 144:ef7eb2e8f9f7 133 adcPRSSELCh0 = _ADC_SINGLECTRL_PRSSEL_PRSCH0, /**< PRS channel 0. */
<> 144:ef7eb2e8f9f7 134 adcPRSSELCh1 = _ADC_SINGLECTRL_PRSSEL_PRSCH1, /**< PRS channel 1. */
<> 144:ef7eb2e8f9f7 135 adcPRSSELCh2 = _ADC_SINGLECTRL_PRSSEL_PRSCH2, /**< PRS channel 2. */
<> 144:ef7eb2e8f9f7 136 adcPRSSELCh3 = _ADC_SINGLECTRL_PRSSEL_PRSCH3, /**< PRS channel 3. */
<> 144:ef7eb2e8f9f7 137 #if defined( _ADC_SINGLECTRL_PRSSEL_PRSCH4 )
<> 144:ef7eb2e8f9f7 138 adcPRSSELCh4 = _ADC_SINGLECTRL_PRSSEL_PRSCH4, /**< PRS channel 4. */
<> 144:ef7eb2e8f9f7 139 #endif
<> 144:ef7eb2e8f9f7 140 #if defined( _ADC_SINGLECTRL_PRSSEL_PRSCH5 )
<> 144:ef7eb2e8f9f7 141 adcPRSSELCh5 = _ADC_SINGLECTRL_PRSSEL_PRSCH5, /**< PRS channel 5. */
<> 144:ef7eb2e8f9f7 142 #endif
<> 144:ef7eb2e8f9f7 143 #if defined( _ADC_SINGLECTRL_PRSSEL_PRSCH6 )
<> 144:ef7eb2e8f9f7 144 adcPRSSELCh6 = _ADC_SINGLECTRL_PRSSEL_PRSCH6, /**< PRS channel 6. */
<> 144:ef7eb2e8f9f7 145 #endif
<> 144:ef7eb2e8f9f7 146 #if defined( _ADC_SINGLECTRL_PRSSEL_PRSCH7 )
<> 144:ef7eb2e8f9f7 147 adcPRSSELCh7 = _ADC_SINGLECTRL_PRSSEL_PRSCH7, /**< PRS channel 7. */
<> 144:ef7eb2e8f9f7 148 #endif
<> 144:ef7eb2e8f9f7 149 #if defined( _ADC_SINGLECTRL_PRSSEL_PRSCH8 )
<> 144:ef7eb2e8f9f7 150 adcPRSSELCh8 = _ADC_SINGLECTRL_PRSSEL_PRSCH8, /**< PRS channel 8. */
<> 144:ef7eb2e8f9f7 151 #endif
<> 144:ef7eb2e8f9f7 152 #if defined( _ADC_SINGLECTRL_PRSSEL_PRSCH9 )
<> 144:ef7eb2e8f9f7 153 adcPRSSELCh9 = _ADC_SINGLECTRL_PRSSEL_PRSCH9, /**< PRS channel 9. */
<> 144:ef7eb2e8f9f7 154 #endif
<> 144:ef7eb2e8f9f7 155 #if defined( _ADC_SINGLECTRL_PRSSEL_PRSCH10 )
<> 144:ef7eb2e8f9f7 156 adcPRSSELCh10 = _ADC_SINGLECTRL_PRSSEL_PRSCH10, /**< PRS channel 10. */
<> 144:ef7eb2e8f9f7 157 #endif
<> 144:ef7eb2e8f9f7 158 #if defined( _ADC_SINGLECTRL_PRSSEL_PRSCH11 )
<> 144:ef7eb2e8f9f7 159 adcPRSSELCh11 = _ADC_SINGLECTRL_PRSSEL_PRSCH11, /**< PRS channel 11. */
<> 144:ef7eb2e8f9f7 160 #endif
<> 144:ef7eb2e8f9f7 161 #elif defined(_ADC_SINGLECTRLX_PRSSEL_MASK)
<> 144:ef7eb2e8f9f7 162 adcPRSSELCh0 = _ADC_SINGLECTRLX_PRSSEL_PRSCH0, /**< PRS channel 0. */
<> 144:ef7eb2e8f9f7 163 adcPRSSELCh1 = _ADC_SINGLECTRLX_PRSSEL_PRSCH1, /**< PRS channel 1. */
<> 144:ef7eb2e8f9f7 164 adcPRSSELCh2 = _ADC_SINGLECTRLX_PRSSEL_PRSCH2, /**< PRS channel 2. */
<> 144:ef7eb2e8f9f7 165 adcPRSSELCh3 = _ADC_SINGLECTRLX_PRSSEL_PRSCH3, /**< PRS channel 3. */
<> 144:ef7eb2e8f9f7 166 adcPRSSELCh4 = _ADC_SINGLECTRLX_PRSSEL_PRSCH4, /**< PRS channel 4. */
<> 144:ef7eb2e8f9f7 167 adcPRSSELCh5 = _ADC_SINGLECTRLX_PRSSEL_PRSCH5, /**< PRS channel 5. */
<> 144:ef7eb2e8f9f7 168 adcPRSSELCh6 = _ADC_SINGLECTRLX_PRSSEL_PRSCH6, /**< PRS channel 6. */
<> 144:ef7eb2e8f9f7 169 adcPRSSELCh7 = _ADC_SINGLECTRLX_PRSSEL_PRSCH7, /**< PRS channel 7. */
<> 144:ef7eb2e8f9f7 170 adcPRSSELCh8 = _ADC_SINGLECTRLX_PRSSEL_PRSCH8, /**< PRS channel 8. */
<> 144:ef7eb2e8f9f7 171 adcPRSSELCh9 = _ADC_SINGLECTRLX_PRSSEL_PRSCH9, /**< PRS channel 9. */
<> 144:ef7eb2e8f9f7 172 adcPRSSELCh10 = _ADC_SINGLECTRLX_PRSSEL_PRSCH10, /**< PRS channel 10. */
<> 144:ef7eb2e8f9f7 173 adcPRSSELCh11 = _ADC_SINGLECTRLX_PRSSEL_PRSCH11, /**< PRS channel 11. */
<> 144:ef7eb2e8f9f7 174 #if defined( _ADC_SINGLECTRLX_PRSSEL_PRSCH12 )
<> 144:ef7eb2e8f9f7 175 adcPRSSELCh12 = _ADC_SINGLECTRLX_PRSSEL_PRSCH12, /**< PRS channel 12. */
<> 144:ef7eb2e8f9f7 176 adcPRSSELCh13 = _ADC_SINGLECTRLX_PRSSEL_PRSCH13, /**< PRS channel 13. */
<> 144:ef7eb2e8f9f7 177 adcPRSSELCh14 = _ADC_SINGLECTRLX_PRSSEL_PRSCH14, /**< PRS channel 14. */
<> 144:ef7eb2e8f9f7 178 adcPRSSELCh15 = _ADC_SINGLECTRLX_PRSSEL_PRSCH15, /**< PRS channel 15. */
<> 144:ef7eb2e8f9f7 179 #endif
<> 144:ef7eb2e8f9f7 180 #endif
<> 144:ef7eb2e8f9f7 181 } ADC_PRSSEL_TypeDef;
<> 144:ef7eb2e8f9f7 182
<> 144:ef7eb2e8f9f7 183
<> 144:ef7eb2e8f9f7 184 /** Single and scan mode voltage references. Using unshifted enums and or
<> 144:ef7eb2e8f9f7 185 in ADC_CTRLX_VREFSEL_REG to select the extension register CTRLX_VREFSEL. */
<> 144:ef7eb2e8f9f7 186 #if defined( _ADC_SCANCTRLX_VREFSEL_MASK )
<> 144:ef7eb2e8f9f7 187 #define ADC_CTRLX_VREFSEL_REG 0x80
<> 144:ef7eb2e8f9f7 188 #endif
<> 144:ef7eb2e8f9f7 189 typedef enum
<> 144:ef7eb2e8f9f7 190 {
<> 144:ef7eb2e8f9f7 191 /** Internal 1.25V reference. */
<> 144:ef7eb2e8f9f7 192 adcRef1V25 = _ADC_SINGLECTRL_REF_1V25,
<> 144:ef7eb2e8f9f7 193
<> 144:ef7eb2e8f9f7 194 /** Internal 2.5V reference. */
<> 144:ef7eb2e8f9f7 195 adcRef2V5 = _ADC_SINGLECTRL_REF_2V5,
<> 144:ef7eb2e8f9f7 196
<> 144:ef7eb2e8f9f7 197 /** Buffered VDD. */
<> 144:ef7eb2e8f9f7 198 adcRefVDD = _ADC_SINGLECTRL_REF_VDD,
<> 144:ef7eb2e8f9f7 199
<> 144:ef7eb2e8f9f7 200 /** Internal differential 5V reference. */
<> 144:ef7eb2e8f9f7 201 adcRef5VDIFF = _ADC_SINGLECTRL_REF_5VDIFF,
<> 144:ef7eb2e8f9f7 202
<> 144:ef7eb2e8f9f7 203 /** Single ended external reference from pin 6. */
<> 144:ef7eb2e8f9f7 204 adcRefExtSingle = _ADC_SINGLECTRL_REF_EXTSINGLE,
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206 /** Differential external reference from pin 6 and 7. */
<> 144:ef7eb2e8f9f7 207 adcRef2xExtDiff = _ADC_SINGLECTRL_REF_2XEXTDIFF,
<> 144:ef7eb2e8f9f7 208
<> 144:ef7eb2e8f9f7 209 /** Unbuffered 2xVDD. */
<> 144:ef7eb2e8f9f7 210 adcRef2xVDD = _ADC_SINGLECTRL_REF_2XVDD,
<> 144:ef7eb2e8f9f7 211
<> 144:ef7eb2e8f9f7 212 #if defined( _ADC_SINGLECTRLX_VREFSEL_VBGR )
<> 144:ef7eb2e8f9f7 213 /** Custom VFS: Internal Bandgap reference */
<> 144:ef7eb2e8f9f7 214 adcRefVBGR = _ADC_SINGLECTRLX_VREFSEL_VBGR | ADC_CTRLX_VREFSEL_REG,
<> 144:ef7eb2e8f9f7 215 #endif
<> 144:ef7eb2e8f9f7 216
<> 144:ef7eb2e8f9f7 217 #if defined( _ADC_SINGLECTRLX_VREFSEL_VDDXWATT )
<> 144:ef7eb2e8f9f7 218 /** Custom VFS: Scaled AVDD: AVDD * VREFATT */
<> 144:ef7eb2e8f9f7 219 adcRefVddxAtt = _ADC_SINGLECTRLX_VREFSEL_VDDXWATT | ADC_CTRLX_VREFSEL_REG,
<> 144:ef7eb2e8f9f7 220 #endif
<> 144:ef7eb2e8f9f7 221
<> 144:ef7eb2e8f9f7 222 #if defined( _ADC_SINGLECTRLX_VREFSEL_VREFPWATT )
<> 144:ef7eb2e8f9f7 223 /** Custom VFS: Scaled singled ended external reference from pin 6:
<> 144:ef7eb2e8f9f7 224 VREFP * VREFATT */
<> 144:ef7eb2e8f9f7 225 adcRefVPxAtt = _ADC_SINGLECTRLX_VREFSEL_VREFPWATT | ADC_CTRLX_VREFSEL_REG,
<> 144:ef7eb2e8f9f7 226 #endif
<> 144:ef7eb2e8f9f7 227
<> 144:ef7eb2e8f9f7 228 #if defined( _ADC_SINGLECTRLX_VREFSEL_VREFP )
<> 144:ef7eb2e8f9f7 229 /** Custom VFS: Raw single ended external reference from pin 6. */
<> 144:ef7eb2e8f9f7 230 adcRefP = _ADC_SINGLECTRLX_VREFSEL_VREFP | ADC_CTRLX_VREFSEL_REG,
<> 144:ef7eb2e8f9f7 231 #endif
<> 144:ef7eb2e8f9f7 232
<> 144:ef7eb2e8f9f7 233 #if defined( _ADC_SINGLECTRLX_VREFSEL_VENTROPY )
<> 144:ef7eb2e8f9f7 234 /** Custom VFS: Special mode for entropy generation */
<> 144:ef7eb2e8f9f7 235 adcRefVEntropy = _ADC_SINGLECTRLX_VREFSEL_VENTROPY | ADC_CTRLX_VREFSEL_REG,
<> 144:ef7eb2e8f9f7 236 #endif
<> 144:ef7eb2e8f9f7 237
<> 144:ef7eb2e8f9f7 238 #if defined( _ADC_SINGLECTRLX_VREFSEL_VREFPNWATT )
<> 144:ef7eb2e8f9f7 239 /** Custom VFS: Scaled differential external Vref from pin 6 and 7:
<> 144:ef7eb2e8f9f7 240 (VREFP - VREFN) * VREFATT */
<> 144:ef7eb2e8f9f7 241 adcRefVPNxAtt = _ADC_SINGLECTRLX_VREFSEL_VREFPNWATT | ADC_CTRLX_VREFSEL_REG,
<> 144:ef7eb2e8f9f7 242 #endif
<> 144:ef7eb2e8f9f7 243
<> 144:ef7eb2e8f9f7 244 #if defined( _ADC_SINGLECTRLX_VREFSEL_VREFPN )
<> 144:ef7eb2e8f9f7 245 /** Custom VFS: Raw differential external Vref from pin 6 and 7:
<> 144:ef7eb2e8f9f7 246 VREFP - VREFN */
<> 144:ef7eb2e8f9f7 247 adcRefPN = _ADC_SINGLECTRLX_VREFSEL_VREFPN | ADC_CTRLX_VREFSEL_REG,
<> 144:ef7eb2e8f9f7 248 #endif
<> 144:ef7eb2e8f9f7 249 } ADC_Ref_TypeDef;
<> 144:ef7eb2e8f9f7 250
<> 144:ef7eb2e8f9f7 251
<> 144:ef7eb2e8f9f7 252 /** Sample resolution. */
<> 144:ef7eb2e8f9f7 253 typedef enum
<> 144:ef7eb2e8f9f7 254 {
<> 144:ef7eb2e8f9f7 255 adcRes12Bit = _ADC_SINGLECTRL_RES_12BIT, /**< 12 bit sampling. */
<> 144:ef7eb2e8f9f7 256 adcRes8Bit = _ADC_SINGLECTRL_RES_8BIT, /**< 8 bit sampling. */
<> 144:ef7eb2e8f9f7 257 adcRes6Bit = _ADC_SINGLECTRL_RES_6BIT, /**< 6 bit sampling. */
<> 144:ef7eb2e8f9f7 258 adcResOVS = _ADC_SINGLECTRL_RES_OVS /**< Oversampling. */
<> 144:ef7eb2e8f9f7 259 } ADC_Res_TypeDef;
<> 144:ef7eb2e8f9f7 260
<> 144:ef7eb2e8f9f7 261
<> 144:ef7eb2e8f9f7 262 #if defined( _ADC_SINGLECTRL_INPUTSEL_MASK )
<> 144:ef7eb2e8f9f7 263 /** Single sample input selection. */
<> 144:ef7eb2e8f9f7 264 typedef enum
<> 144:ef7eb2e8f9f7 265 {
<> 144:ef7eb2e8f9f7 266 /* Differential mode disabled */
<> 144:ef7eb2e8f9f7 267 adcSingleInputCh0 = _ADC_SINGLECTRL_INPUTSEL_CH0, /**< Channel 0. */
<> 144:ef7eb2e8f9f7 268 adcSingleInputCh1 = _ADC_SINGLECTRL_INPUTSEL_CH1, /**< Channel 1. */
<> 144:ef7eb2e8f9f7 269 adcSingleInputCh2 = _ADC_SINGLECTRL_INPUTSEL_CH2, /**< Channel 2. */
<> 144:ef7eb2e8f9f7 270 adcSingleInputCh3 = _ADC_SINGLECTRL_INPUTSEL_CH3, /**< Channel 3. */
<> 144:ef7eb2e8f9f7 271 adcSingleInputCh4 = _ADC_SINGLECTRL_INPUTSEL_CH4, /**< Channel 4. */
<> 144:ef7eb2e8f9f7 272 adcSingleInputCh5 = _ADC_SINGLECTRL_INPUTSEL_CH5, /**< Channel 5. */
<> 144:ef7eb2e8f9f7 273 adcSingleInputCh6 = _ADC_SINGLECTRL_INPUTSEL_CH6, /**< Channel 6. */
<> 144:ef7eb2e8f9f7 274 adcSingleInputCh7 = _ADC_SINGLECTRL_INPUTSEL_CH7, /**< Channel 7. */
<> 144:ef7eb2e8f9f7 275 adcSingleInputTemp = _ADC_SINGLECTRL_INPUTSEL_TEMP, /**< Temperature reference. */
<> 144:ef7eb2e8f9f7 276 adcSingleInputVDDDiv3 = _ADC_SINGLECTRL_INPUTSEL_VDDDIV3, /**< VDD divided by 3. */
<> 144:ef7eb2e8f9f7 277 adcSingleInputVDD = _ADC_SINGLECTRL_INPUTSEL_VDD, /**< VDD. */
<> 144:ef7eb2e8f9f7 278 adcSingleInputVSS = _ADC_SINGLECTRL_INPUTSEL_VSS, /**< VSS. */
<> 144:ef7eb2e8f9f7 279 adcSingleInputVrefDiv2 = _ADC_SINGLECTRL_INPUTSEL_VREFDIV2, /**< Vref divided by 2. */
<> 144:ef7eb2e8f9f7 280 adcSingleInputDACOut0 = _ADC_SINGLECTRL_INPUTSEL_DAC0OUT0, /**< DAC output 0. */
<> 144:ef7eb2e8f9f7 281 adcSingleInputDACOut1 = _ADC_SINGLECTRL_INPUTSEL_DAC0OUT1, /**< DAC output 1. */
<> 144:ef7eb2e8f9f7 282 /* TBD: Use define when available */
<> 144:ef7eb2e8f9f7 283 adcSingleInputATEST = 15, /**< ATEST. */
<> 144:ef7eb2e8f9f7 284
<> 144:ef7eb2e8f9f7 285 /* Differential mode enabled */
<> 144:ef7eb2e8f9f7 286 adcSingleInputCh0Ch1 = _ADC_SINGLECTRL_INPUTSEL_CH0CH1, /**< Positive Ch0, negative Ch1. */
<> 144:ef7eb2e8f9f7 287 adcSingleInputCh2Ch3 = _ADC_SINGLECTRL_INPUTSEL_CH2CH3, /**< Positive Ch2, negative Ch3. */
<> 144:ef7eb2e8f9f7 288 adcSingleInputCh4Ch5 = _ADC_SINGLECTRL_INPUTSEL_CH4CH5, /**< Positive Ch4, negative Ch5. */
<> 144:ef7eb2e8f9f7 289 adcSingleInputCh6Ch7 = _ADC_SINGLECTRL_INPUTSEL_CH6CH7, /**< Positive Ch6, negative Ch7. */
<> 144:ef7eb2e8f9f7 290 /* TBD: Use define when available */
<> 144:ef7eb2e8f9f7 291 adcSingleInputDiff0 = 4 /**< Differential 0. */
<> 144:ef7eb2e8f9f7 292 } ADC_SingleInput_TypeDef;
<> 144:ef7eb2e8f9f7 293
<> 144:ef7eb2e8f9f7 294 /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
<> 144:ef7eb2e8f9f7 295 /* Legacy enum names */
<> 144:ef7eb2e8f9f7 296 #define adcSingleInpCh0 adcSingleInputCh0
<> 144:ef7eb2e8f9f7 297 #define adcSingleInpCh1 adcSingleInputCh1
<> 144:ef7eb2e8f9f7 298 #define adcSingleInpCh2 adcSingleInputCh2
<> 144:ef7eb2e8f9f7 299 #define adcSingleInpCh3 adcSingleInputCh3
<> 144:ef7eb2e8f9f7 300 #define adcSingleInpCh4 adcSingleInputCh4
<> 144:ef7eb2e8f9f7 301 #define adcSingleInpCh5 adcSingleInputCh5
<> 144:ef7eb2e8f9f7 302 #define adcSingleInpCh6 adcSingleInputCh6
<> 144:ef7eb2e8f9f7 303 #define adcSingleInpCh7 adcSingleInputCh7
<> 144:ef7eb2e8f9f7 304 #define adcSingleInpTemp adcSingleInputTemp
<> 144:ef7eb2e8f9f7 305 #define adcSingleInpVDDDiv3 adcSingleInputVDDDiv3
<> 144:ef7eb2e8f9f7 306 #define adcSingleInpVDD adcSingleInputVDD
<> 144:ef7eb2e8f9f7 307 #define adcSingleInpVSS adcSingleInputVSS
<> 144:ef7eb2e8f9f7 308 #define adcSingleInpVrefDiv2 adcSingleInputVrefDiv2
<> 144:ef7eb2e8f9f7 309 #define adcSingleInpDACOut0 adcSingleInputDACOut0
<> 144:ef7eb2e8f9f7 310 #define adcSingleInpDACOut1 adcSingleInputDACOut1
<> 144:ef7eb2e8f9f7 311 #define adcSingleInpATEST adcSingleInputATEST
<> 144:ef7eb2e8f9f7 312 #define adcSingleInpCh0Ch1 adcSingleInputCh0Ch1
<> 144:ef7eb2e8f9f7 313 #define adcSingleInpCh2Ch3 adcSingleInputCh2Ch3
<> 144:ef7eb2e8f9f7 314 #define adcSingleInpCh4Ch5 adcSingleInputCh4Ch5
<> 144:ef7eb2e8f9f7 315 #define adcSingleInpCh6Ch7 adcSingleInputCh6Ch7
<> 144:ef7eb2e8f9f7 316 #define adcSingleInpDiff0 adcSingleInputDiff0
<> 144:ef7eb2e8f9f7 317 /** @endcond */
<> 144:ef7eb2e8f9f7 318 #endif
<> 144:ef7eb2e8f9f7 319
<> 144:ef7eb2e8f9f7 320 #if defined( _ADC_SINGLECTRL_POSSEL_MASK )
<> 144:ef7eb2e8f9f7 321 /** Positive input selection for single and scan coversion. */
<> 144:ef7eb2e8f9f7 322 typedef enum
<> 144:ef7eb2e8f9f7 323 {
<> 144:ef7eb2e8f9f7 324 adcPosSelAPORT0XCH0 = _ADC_SINGLECTRL_POSSEL_APORT0XCH0,
<> 144:ef7eb2e8f9f7 325 adcPosSelAPORT0XCH1 = _ADC_SINGLECTRL_POSSEL_APORT0XCH1,
<> 144:ef7eb2e8f9f7 326 adcPosSelAPORT0XCH2 = _ADC_SINGLECTRL_POSSEL_APORT0XCH2,
<> 144:ef7eb2e8f9f7 327 adcPosSelAPORT0XCH3 = _ADC_SINGLECTRL_POSSEL_APORT0XCH3,
<> 144:ef7eb2e8f9f7 328 adcPosSelAPORT0XCH4 = _ADC_SINGLECTRL_POSSEL_APORT0XCH4,
<> 144:ef7eb2e8f9f7 329 adcPosSelAPORT0XCH5 = _ADC_SINGLECTRL_POSSEL_APORT0XCH5,
<> 144:ef7eb2e8f9f7 330 adcPosSelAPORT0XCH6 = _ADC_SINGLECTRL_POSSEL_APORT0XCH6,
<> 144:ef7eb2e8f9f7 331 adcPosSelAPORT0XCH7 = _ADC_SINGLECTRL_POSSEL_APORT0XCH7,
<> 144:ef7eb2e8f9f7 332 adcPosSelAPORT0XCH8 = _ADC_SINGLECTRL_POSSEL_APORT0XCH8,
<> 144:ef7eb2e8f9f7 333 adcPosSelAPORT0XCH9 = _ADC_SINGLECTRL_POSSEL_APORT0XCH9,
<> 144:ef7eb2e8f9f7 334 adcPosSelAPORT0XCH10 = _ADC_SINGLECTRL_POSSEL_APORT0XCH10,
<> 144:ef7eb2e8f9f7 335 adcPosSelAPORT0XCH11 = _ADC_SINGLECTRL_POSSEL_APORT0XCH11,
<> 144:ef7eb2e8f9f7 336 adcPosSelAPORT0XCH12 = _ADC_SINGLECTRL_POSSEL_APORT0XCH12,
<> 144:ef7eb2e8f9f7 337 adcPosSelAPORT0XCH13 = _ADC_SINGLECTRL_POSSEL_APORT0XCH13,
<> 144:ef7eb2e8f9f7 338 adcPosSelAPORT0XCH14 = _ADC_SINGLECTRL_POSSEL_APORT0XCH14,
<> 144:ef7eb2e8f9f7 339 adcPosSelAPORT0XCH15 = _ADC_SINGLECTRL_POSSEL_APORT0XCH15,
<> 144:ef7eb2e8f9f7 340 adcPosSelAPORT0YCH0 = _ADC_SINGLECTRL_POSSEL_APORT0YCH0,
<> 144:ef7eb2e8f9f7 341 adcPosSelAPORT0YCH1 = _ADC_SINGLECTRL_POSSEL_APORT0YCH1,
<> 144:ef7eb2e8f9f7 342 adcPosSelAPORT0YCH2 = _ADC_SINGLECTRL_POSSEL_APORT0YCH2,
<> 144:ef7eb2e8f9f7 343 adcPosSelAPORT0YCH3 = _ADC_SINGLECTRL_POSSEL_APORT0YCH3,
<> 144:ef7eb2e8f9f7 344 adcPosSelAPORT0YCH4 = _ADC_SINGLECTRL_POSSEL_APORT0YCH4,
<> 144:ef7eb2e8f9f7 345 adcPosSelAPORT0YCH5 = _ADC_SINGLECTRL_POSSEL_APORT0YCH5,
<> 144:ef7eb2e8f9f7 346 adcPosSelAPORT0YCH6 = _ADC_SINGLECTRL_POSSEL_APORT0YCH6,
<> 144:ef7eb2e8f9f7 347 adcPosSelAPORT0YCH7 = _ADC_SINGLECTRL_POSSEL_APORT0YCH7,
<> 144:ef7eb2e8f9f7 348 adcPosSelAPORT0YCH8 = _ADC_SINGLECTRL_POSSEL_APORT0YCH8,
<> 144:ef7eb2e8f9f7 349 adcPosSelAPORT0YCH9 = _ADC_SINGLECTRL_POSSEL_APORT0YCH9,
<> 144:ef7eb2e8f9f7 350 adcPosSelAPORT0YCH10 = _ADC_SINGLECTRL_POSSEL_APORT0YCH10,
<> 144:ef7eb2e8f9f7 351 adcPosSelAPORT0YCH11 = _ADC_SINGLECTRL_POSSEL_APORT0YCH11,
<> 144:ef7eb2e8f9f7 352 adcPosSelAPORT0YCH12 = _ADC_SINGLECTRL_POSSEL_APORT0YCH12,
<> 144:ef7eb2e8f9f7 353 adcPosSelAPORT0YCH13 = _ADC_SINGLECTRL_POSSEL_APORT0YCH13,
<> 144:ef7eb2e8f9f7 354 adcPosSelAPORT0YCH14 = _ADC_SINGLECTRL_POSSEL_APORT0YCH14,
<> 144:ef7eb2e8f9f7 355 adcPosSelAPORT0YCH15 = _ADC_SINGLECTRL_POSSEL_APORT0YCH15,
<> 144:ef7eb2e8f9f7 356 adcPosSelAPORT1XCH0 = _ADC_SINGLECTRL_POSSEL_APORT1XCH0,
<> 144:ef7eb2e8f9f7 357 adcPosSelAPORT1YCH1 = _ADC_SINGLECTRL_POSSEL_APORT1YCH1,
<> 144:ef7eb2e8f9f7 358 adcPosSelAPORT1XCH2 = _ADC_SINGLECTRL_POSSEL_APORT1XCH2,
<> 144:ef7eb2e8f9f7 359 adcPosSelAPORT1YCH3 = _ADC_SINGLECTRL_POSSEL_APORT1YCH3,
<> 144:ef7eb2e8f9f7 360 adcPosSelAPORT1XCH4 = _ADC_SINGLECTRL_POSSEL_APORT1XCH4,
<> 144:ef7eb2e8f9f7 361 adcPosSelAPORT1YCH5 = _ADC_SINGLECTRL_POSSEL_APORT1YCH5,
<> 144:ef7eb2e8f9f7 362 adcPosSelAPORT1XCH6 = _ADC_SINGLECTRL_POSSEL_APORT1XCH6,
<> 144:ef7eb2e8f9f7 363 adcPosSelAPORT1YCH7 = _ADC_SINGLECTRL_POSSEL_APORT1YCH7,
<> 144:ef7eb2e8f9f7 364 adcPosSelAPORT1XCH8 = _ADC_SINGLECTRL_POSSEL_APORT1XCH8,
<> 144:ef7eb2e8f9f7 365 adcPosSelAPORT1YCH9 = _ADC_SINGLECTRL_POSSEL_APORT1YCH9,
<> 144:ef7eb2e8f9f7 366 adcPosSelAPORT1XCH10 = _ADC_SINGLECTRL_POSSEL_APORT1XCH10,
<> 144:ef7eb2e8f9f7 367 adcPosSelAPORT1YCH11 = _ADC_SINGLECTRL_POSSEL_APORT1YCH11,
<> 144:ef7eb2e8f9f7 368 adcPosSelAPORT1XCH12 = _ADC_SINGLECTRL_POSSEL_APORT1XCH12,
<> 144:ef7eb2e8f9f7 369 adcPosSelAPORT1YCH13 = _ADC_SINGLECTRL_POSSEL_APORT1YCH13,
<> 144:ef7eb2e8f9f7 370 adcPosSelAPORT1XCH14 = _ADC_SINGLECTRL_POSSEL_APORT1XCH14,
<> 144:ef7eb2e8f9f7 371 adcPosSelAPORT1YCH15 = _ADC_SINGLECTRL_POSSEL_APORT1YCH15,
<> 144:ef7eb2e8f9f7 372 adcPosSelAPORT1XCH16 = _ADC_SINGLECTRL_POSSEL_APORT1XCH16,
<> 144:ef7eb2e8f9f7 373 adcPosSelAPORT1YCH17 = _ADC_SINGLECTRL_POSSEL_APORT1YCH17,
<> 144:ef7eb2e8f9f7 374 adcPosSelAPORT1XCH18 = _ADC_SINGLECTRL_POSSEL_APORT1XCH18,
<> 144:ef7eb2e8f9f7 375 adcPosSelAPORT1YCH19 = _ADC_SINGLECTRL_POSSEL_APORT1YCH19,
<> 144:ef7eb2e8f9f7 376 adcPosSelAPORT1XCH20 = _ADC_SINGLECTRL_POSSEL_APORT1XCH20,
<> 144:ef7eb2e8f9f7 377 adcPosSelAPORT1YCH21 = _ADC_SINGLECTRL_POSSEL_APORT1YCH21,
<> 144:ef7eb2e8f9f7 378 adcPosSelAPORT1XCH22 = _ADC_SINGLECTRL_POSSEL_APORT1XCH22,
<> 144:ef7eb2e8f9f7 379 adcPosSelAPORT1YCH23 = _ADC_SINGLECTRL_POSSEL_APORT1YCH23,
<> 144:ef7eb2e8f9f7 380 adcPosSelAPORT1XCH24 = _ADC_SINGLECTRL_POSSEL_APORT1XCH24,
<> 144:ef7eb2e8f9f7 381 adcPosSelAPORT1YCH25 = _ADC_SINGLECTRL_POSSEL_APORT1YCH25,
<> 144:ef7eb2e8f9f7 382 adcPosSelAPORT1XCH26 = _ADC_SINGLECTRL_POSSEL_APORT1XCH26,
<> 144:ef7eb2e8f9f7 383 adcPosSelAPORT1YCH27 = _ADC_SINGLECTRL_POSSEL_APORT1YCH27,
<> 144:ef7eb2e8f9f7 384 adcPosSelAPORT1XCH28 = _ADC_SINGLECTRL_POSSEL_APORT1XCH28,
<> 144:ef7eb2e8f9f7 385 adcPosSelAPORT1YCH29 = _ADC_SINGLECTRL_POSSEL_APORT1YCH29,
<> 144:ef7eb2e8f9f7 386 adcPosSelAPORT1XCH30 = _ADC_SINGLECTRL_POSSEL_APORT1XCH30,
<> 144:ef7eb2e8f9f7 387 adcPosSelAPORT1YCH31 = _ADC_SINGLECTRL_POSSEL_APORT1YCH31,
<> 144:ef7eb2e8f9f7 388 adcPosSelAPORT2YCH0 = _ADC_SINGLECTRL_POSSEL_APORT2YCH0,
<> 144:ef7eb2e8f9f7 389 adcPosSelAPORT2XCH1 = _ADC_SINGLECTRL_POSSEL_APORT2XCH1,
<> 144:ef7eb2e8f9f7 390 adcPosSelAPORT2YCH2 = _ADC_SINGLECTRL_POSSEL_APORT2YCH2,
<> 144:ef7eb2e8f9f7 391 adcPosSelAPORT2XCH3 = _ADC_SINGLECTRL_POSSEL_APORT2XCH3,
<> 144:ef7eb2e8f9f7 392 adcPosSelAPORT2YCH4 = _ADC_SINGLECTRL_POSSEL_APORT2YCH4,
<> 144:ef7eb2e8f9f7 393 adcPosSelAPORT2XCH5 = _ADC_SINGLECTRL_POSSEL_APORT2XCH5,
<> 144:ef7eb2e8f9f7 394 adcPosSelAPORT2YCH6 = _ADC_SINGLECTRL_POSSEL_APORT2YCH6,
<> 144:ef7eb2e8f9f7 395 adcPosSelAPORT2XCH7 = _ADC_SINGLECTRL_POSSEL_APORT2XCH7,
<> 144:ef7eb2e8f9f7 396 adcPosSelAPORT2YCH8 = _ADC_SINGLECTRL_POSSEL_APORT2YCH8,
<> 144:ef7eb2e8f9f7 397 adcPosSelAPORT2XCH9 = _ADC_SINGLECTRL_POSSEL_APORT2XCH9,
<> 144:ef7eb2e8f9f7 398 adcPosSelAPORT2YCH10 = _ADC_SINGLECTRL_POSSEL_APORT2YCH10,
<> 144:ef7eb2e8f9f7 399 adcPosSelAPORT2XCH11 = _ADC_SINGLECTRL_POSSEL_APORT2XCH11,
<> 144:ef7eb2e8f9f7 400 adcPosSelAPORT2YCH12 = _ADC_SINGLECTRL_POSSEL_APORT2YCH12,
<> 144:ef7eb2e8f9f7 401 adcPosSelAPORT2XCH13 = _ADC_SINGLECTRL_POSSEL_APORT2XCH13,
<> 144:ef7eb2e8f9f7 402 adcPosSelAPORT2YCH14 = _ADC_SINGLECTRL_POSSEL_APORT2YCH14,
<> 144:ef7eb2e8f9f7 403 adcPosSelAPORT2XCH15 = _ADC_SINGLECTRL_POSSEL_APORT2XCH15,
<> 144:ef7eb2e8f9f7 404 adcPosSelAPORT2YCH16 = _ADC_SINGLECTRL_POSSEL_APORT2YCH16,
<> 144:ef7eb2e8f9f7 405 adcPosSelAPORT2XCH17 = _ADC_SINGLECTRL_POSSEL_APORT2XCH17,
<> 144:ef7eb2e8f9f7 406 adcPosSelAPORT2YCH18 = _ADC_SINGLECTRL_POSSEL_APORT2YCH18,
<> 144:ef7eb2e8f9f7 407 adcPosSelAPORT2XCH19 = _ADC_SINGLECTRL_POSSEL_APORT2XCH19,
<> 144:ef7eb2e8f9f7 408 adcPosSelAPORT2YCH20 = _ADC_SINGLECTRL_POSSEL_APORT2YCH20,
<> 144:ef7eb2e8f9f7 409 adcPosSelAPORT2XCH21 = _ADC_SINGLECTRL_POSSEL_APORT2XCH21,
<> 144:ef7eb2e8f9f7 410 adcPosSelAPORT2YCH22 = _ADC_SINGLECTRL_POSSEL_APORT2YCH22,
<> 144:ef7eb2e8f9f7 411 adcPosSelAPORT2XCH23 = _ADC_SINGLECTRL_POSSEL_APORT2XCH23,
<> 144:ef7eb2e8f9f7 412 adcPosSelAPORT2YCH24 = _ADC_SINGLECTRL_POSSEL_APORT2YCH24,
<> 144:ef7eb2e8f9f7 413 adcPosSelAPORT2XCH25 = _ADC_SINGLECTRL_POSSEL_APORT2XCH25,
<> 144:ef7eb2e8f9f7 414 adcPosSelAPORT2YCH26 = _ADC_SINGLECTRL_POSSEL_APORT2YCH26,
<> 144:ef7eb2e8f9f7 415 adcPosSelAPORT2XCH27 = _ADC_SINGLECTRL_POSSEL_APORT2XCH27,
<> 144:ef7eb2e8f9f7 416 adcPosSelAPORT2YCH28 = _ADC_SINGLECTRL_POSSEL_APORT2YCH28,
<> 144:ef7eb2e8f9f7 417 adcPosSelAPORT2XCH29 = _ADC_SINGLECTRL_POSSEL_APORT2XCH29,
<> 144:ef7eb2e8f9f7 418 adcPosSelAPORT2YCH30 = _ADC_SINGLECTRL_POSSEL_APORT2YCH30,
<> 144:ef7eb2e8f9f7 419 adcPosSelAPORT2XCH31 = _ADC_SINGLECTRL_POSSEL_APORT2XCH31,
<> 144:ef7eb2e8f9f7 420 adcPosSelAPORT3XCH0 = _ADC_SINGLECTRL_POSSEL_APORT3XCH0,
<> 144:ef7eb2e8f9f7 421 adcPosSelAPORT3YCH1 = _ADC_SINGLECTRL_POSSEL_APORT3YCH1,
<> 144:ef7eb2e8f9f7 422 adcPosSelAPORT3XCH2 = _ADC_SINGLECTRL_POSSEL_APORT3XCH2,
<> 144:ef7eb2e8f9f7 423 adcPosSelAPORT3YCH3 = _ADC_SINGLECTRL_POSSEL_APORT3YCH3,
<> 144:ef7eb2e8f9f7 424 adcPosSelAPORT3XCH4 = _ADC_SINGLECTRL_POSSEL_APORT3XCH4,
<> 144:ef7eb2e8f9f7 425 adcPosSelAPORT3YCH5 = _ADC_SINGLECTRL_POSSEL_APORT3YCH5,
<> 144:ef7eb2e8f9f7 426 adcPosSelAPORT3XCH6 = _ADC_SINGLECTRL_POSSEL_APORT3XCH6,
<> 144:ef7eb2e8f9f7 427 adcPosSelAPORT3YCH7 = _ADC_SINGLECTRL_POSSEL_APORT3YCH7,
<> 144:ef7eb2e8f9f7 428 adcPosSelAPORT3XCH8 = _ADC_SINGLECTRL_POSSEL_APORT3XCH8,
<> 144:ef7eb2e8f9f7 429 adcPosSelAPORT3YCH9 = _ADC_SINGLECTRL_POSSEL_APORT3YCH9,
<> 144:ef7eb2e8f9f7 430 adcPosSelAPORT3XCH10 = _ADC_SINGLECTRL_POSSEL_APORT3XCH10,
<> 144:ef7eb2e8f9f7 431 adcPosSelAPORT3YCH11 = _ADC_SINGLECTRL_POSSEL_APORT3YCH11,
<> 144:ef7eb2e8f9f7 432 adcPosSelAPORT3XCH12 = _ADC_SINGLECTRL_POSSEL_APORT3XCH12,
<> 144:ef7eb2e8f9f7 433 adcPosSelAPORT3YCH13 = _ADC_SINGLECTRL_POSSEL_APORT3YCH13,
<> 144:ef7eb2e8f9f7 434 adcPosSelAPORT3XCH14 = _ADC_SINGLECTRL_POSSEL_APORT3XCH14,
<> 144:ef7eb2e8f9f7 435 adcPosSelAPORT3YCH15 = _ADC_SINGLECTRL_POSSEL_APORT3YCH15,
<> 144:ef7eb2e8f9f7 436 adcPosSelAPORT3XCH16 = _ADC_SINGLECTRL_POSSEL_APORT3XCH16,
<> 144:ef7eb2e8f9f7 437 adcPosSelAPORT3YCH17 = _ADC_SINGLECTRL_POSSEL_APORT3YCH17,
<> 144:ef7eb2e8f9f7 438 adcPosSelAPORT3XCH18 = _ADC_SINGLECTRL_POSSEL_APORT3XCH18,
<> 144:ef7eb2e8f9f7 439 adcPosSelAPORT3YCH19 = _ADC_SINGLECTRL_POSSEL_APORT3YCH19,
<> 144:ef7eb2e8f9f7 440 adcPosSelAPORT3XCH20 = _ADC_SINGLECTRL_POSSEL_APORT3XCH20,
<> 144:ef7eb2e8f9f7 441 adcPosSelAPORT3YCH21 = _ADC_SINGLECTRL_POSSEL_APORT3YCH21,
<> 144:ef7eb2e8f9f7 442 adcPosSelAPORT3XCH22 = _ADC_SINGLECTRL_POSSEL_APORT3XCH22,
<> 144:ef7eb2e8f9f7 443 adcPosSelAPORT3YCH23 = _ADC_SINGLECTRL_POSSEL_APORT3YCH23,
<> 144:ef7eb2e8f9f7 444 adcPosSelAPORT3XCH24 = _ADC_SINGLECTRL_POSSEL_APORT3XCH24,
<> 144:ef7eb2e8f9f7 445 adcPosSelAPORT3YCH25 = _ADC_SINGLECTRL_POSSEL_APORT3YCH25,
<> 144:ef7eb2e8f9f7 446 adcPosSelAPORT3XCH26 = _ADC_SINGLECTRL_POSSEL_APORT3XCH26,
<> 144:ef7eb2e8f9f7 447 adcPosSelAPORT3YCH27 = _ADC_SINGLECTRL_POSSEL_APORT3YCH27,
<> 144:ef7eb2e8f9f7 448 adcPosSelAPORT3XCH28 = _ADC_SINGLECTRL_POSSEL_APORT3XCH28,
<> 144:ef7eb2e8f9f7 449 adcPosSelAPORT3YCH29 = _ADC_SINGLECTRL_POSSEL_APORT3YCH29,
<> 144:ef7eb2e8f9f7 450 adcPosSelAPORT3XCH30 = _ADC_SINGLECTRL_POSSEL_APORT3XCH30,
<> 144:ef7eb2e8f9f7 451 adcPosSelAPORT3YCH31 = _ADC_SINGLECTRL_POSSEL_APORT3YCH31,
<> 144:ef7eb2e8f9f7 452 adcPosSelAPORT4YCH0 = _ADC_SINGLECTRL_POSSEL_APORT4YCH0,
<> 144:ef7eb2e8f9f7 453 adcPosSelAPORT4XCH1 = _ADC_SINGLECTRL_POSSEL_APORT4XCH1,
<> 144:ef7eb2e8f9f7 454 adcPosSelAPORT4YCH2 = _ADC_SINGLECTRL_POSSEL_APORT4YCH2,
<> 144:ef7eb2e8f9f7 455 adcPosSelAPORT4XCH3 = _ADC_SINGLECTRL_POSSEL_APORT4XCH3,
<> 144:ef7eb2e8f9f7 456 adcPosSelAPORT4YCH4 = _ADC_SINGLECTRL_POSSEL_APORT4YCH4,
<> 144:ef7eb2e8f9f7 457 adcPosSelAPORT4XCH5 = _ADC_SINGLECTRL_POSSEL_APORT4XCH5,
<> 144:ef7eb2e8f9f7 458 adcPosSelAPORT4YCH6 = _ADC_SINGLECTRL_POSSEL_APORT4YCH6,
<> 144:ef7eb2e8f9f7 459 adcPosSelAPORT4XCH7 = _ADC_SINGLECTRL_POSSEL_APORT4XCH7,
<> 144:ef7eb2e8f9f7 460 adcPosSelAPORT4YCH8 = _ADC_SINGLECTRL_POSSEL_APORT4YCH8,
<> 144:ef7eb2e8f9f7 461 adcPosSelAPORT4XCH9 = _ADC_SINGLECTRL_POSSEL_APORT4XCH9,
<> 144:ef7eb2e8f9f7 462 adcPosSelAPORT4YCH10 = _ADC_SINGLECTRL_POSSEL_APORT4YCH10,
<> 144:ef7eb2e8f9f7 463 adcPosSelAPORT4XCH11 = _ADC_SINGLECTRL_POSSEL_APORT4XCH11,
<> 144:ef7eb2e8f9f7 464 adcPosSelAPORT4YCH12 = _ADC_SINGLECTRL_POSSEL_APORT4YCH12,
<> 144:ef7eb2e8f9f7 465 adcPosSelAPORT4XCH13 = _ADC_SINGLECTRL_POSSEL_APORT4XCH13,
<> 144:ef7eb2e8f9f7 466 adcPosSelAPORT4YCH14 = _ADC_SINGLECTRL_POSSEL_APORT4YCH14,
<> 144:ef7eb2e8f9f7 467 adcPosSelAPORT4XCH15 = _ADC_SINGLECTRL_POSSEL_APORT4XCH15,
<> 144:ef7eb2e8f9f7 468 adcPosSelAPORT4YCH16 = _ADC_SINGLECTRL_POSSEL_APORT4YCH16,
<> 144:ef7eb2e8f9f7 469 adcPosSelAPORT4XCH17 = _ADC_SINGLECTRL_POSSEL_APORT4XCH17,
<> 144:ef7eb2e8f9f7 470 adcPosSelAPORT4YCH18 = _ADC_SINGLECTRL_POSSEL_APORT4YCH18,
<> 144:ef7eb2e8f9f7 471 adcPosSelAPORT4XCH19 = _ADC_SINGLECTRL_POSSEL_APORT4XCH19,
<> 144:ef7eb2e8f9f7 472 adcPosSelAPORT4YCH20 = _ADC_SINGLECTRL_POSSEL_APORT4YCH20,
<> 144:ef7eb2e8f9f7 473 adcPosSelAPORT4XCH21 = _ADC_SINGLECTRL_POSSEL_APORT4XCH21,
<> 144:ef7eb2e8f9f7 474 adcPosSelAPORT4YCH22 = _ADC_SINGLECTRL_POSSEL_APORT4YCH22,
<> 144:ef7eb2e8f9f7 475 adcPosSelAPORT4XCH23 = _ADC_SINGLECTRL_POSSEL_APORT4XCH23,
<> 144:ef7eb2e8f9f7 476 adcPosSelAPORT4YCH24 = _ADC_SINGLECTRL_POSSEL_APORT4YCH24,
<> 144:ef7eb2e8f9f7 477 adcPosSelAPORT4XCH25 = _ADC_SINGLECTRL_POSSEL_APORT4XCH25,
<> 144:ef7eb2e8f9f7 478 adcPosSelAPORT4YCH26 = _ADC_SINGLECTRL_POSSEL_APORT4YCH26,
<> 144:ef7eb2e8f9f7 479 adcPosSelAPORT4XCH27 = _ADC_SINGLECTRL_POSSEL_APORT4XCH27,
<> 144:ef7eb2e8f9f7 480 adcPosSelAPORT4YCH28 = _ADC_SINGLECTRL_POSSEL_APORT4YCH28,
<> 144:ef7eb2e8f9f7 481 adcPosSelAPORT4XCH29 = _ADC_SINGLECTRL_POSSEL_APORT4XCH29,
<> 144:ef7eb2e8f9f7 482 adcPosSelAPORT4YCH30 = _ADC_SINGLECTRL_POSSEL_APORT4YCH30,
<> 144:ef7eb2e8f9f7 483 adcPosSelAPORT4XCH31 = _ADC_SINGLECTRL_POSSEL_APORT4XCH31,
<> 144:ef7eb2e8f9f7 484 adcPosSelAVDD = _ADC_SINGLECTRL_POSSEL_AVDD,
<> 144:ef7eb2e8f9f7 485 adcPosSelBU = _ADC_SINGLECTRL_POSSEL_BU,
<> 144:ef7eb2e8f9f7 486 adcPosSelAREG = _ADC_SINGLECTRL_POSSEL_AREG,
<> 144:ef7eb2e8f9f7 487 adcPosSelVREGOUTPA = _ADC_SINGLECTRL_POSSEL_VREGOUTPA,
<> 144:ef7eb2e8f9f7 488 adcPosSelPDBU = _ADC_SINGLECTRL_POSSEL_PDBU,
<> 144:ef7eb2e8f9f7 489 adcPosSelIO0 = _ADC_SINGLECTRL_POSSEL_IO0,
<> 144:ef7eb2e8f9f7 490 adcPosSelIO1 = _ADC_SINGLECTRL_POSSEL_IO1,
<> 144:ef7eb2e8f9f7 491 adcPosSelVSP = _ADC_SINGLECTRL_POSSEL_VSP,
<> 144:ef7eb2e8f9f7 492 adcPosSelSP0 = _ADC_SINGLECTRL_POSSEL_SP0,
<> 144:ef7eb2e8f9f7 493 adcPosSelTEMP = _ADC_SINGLECTRL_POSSEL_TEMP,
<> 144:ef7eb2e8f9f7 494 adcPosSelDAC0OUT0 = _ADC_SINGLECTRL_POSSEL_DAC0OUT0,
<> 144:ef7eb2e8f9f7 495 adcPosSelTESTP = _ADC_SINGLECTRL_POSSEL_TESTP,
<> 144:ef7eb2e8f9f7 496 adcPosSelSP1 = _ADC_SINGLECTRL_POSSEL_SP1,
<> 144:ef7eb2e8f9f7 497 adcPosSelSP2 = _ADC_SINGLECTRL_POSSEL_SP2,
<> 144:ef7eb2e8f9f7 498 adcPosSelDAC0OUT1 = _ADC_SINGLECTRL_POSSEL_DAC0OUT1,
<> 144:ef7eb2e8f9f7 499 adcPosSelSUBLSB = _ADC_SINGLECTRL_POSSEL_SUBLSB,
<> 144:ef7eb2e8f9f7 500 adcPosSelDEFAULT = _ADC_SINGLECTRL_POSSEL_DEFAULT,
<> 144:ef7eb2e8f9f7 501 adcPosSelVSS = _ADC_SINGLECTRL_POSSEL_VSS
<> 144:ef7eb2e8f9f7 502 } ADC_PosSel_TypeDef;
<> 144:ef7eb2e8f9f7 503 #endif
<> 144:ef7eb2e8f9f7 504
<> 144:ef7eb2e8f9f7 505
<> 144:ef7eb2e8f9f7 506 #if defined( _ADC_SINGLECTRL_NEGSEL_MASK )
<> 144:ef7eb2e8f9f7 507 /** Negative input selection for single and scan coversion. */
<> 144:ef7eb2e8f9f7 508 typedef enum
<> 144:ef7eb2e8f9f7 509 {
<> 144:ef7eb2e8f9f7 510 adcNegSelAPORT0XCH0 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH0,
<> 144:ef7eb2e8f9f7 511 adcNegSelAPORT0XCH1 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH1,
<> 144:ef7eb2e8f9f7 512 adcNegSelAPORT0XCH2 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH2,
<> 144:ef7eb2e8f9f7 513 adcNegSelAPORT0XCH3 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH3,
<> 144:ef7eb2e8f9f7 514 adcNegSelAPORT0XCH4 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH4,
<> 144:ef7eb2e8f9f7 515 adcNegSelAPORT0XCH5 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH5,
<> 144:ef7eb2e8f9f7 516 adcNegSelAPORT0XCH6 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH6,
<> 144:ef7eb2e8f9f7 517 adcNegSelAPORT0XCH7 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH7,
<> 144:ef7eb2e8f9f7 518 adcNegSelAPORT0XCH8 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH8,
<> 144:ef7eb2e8f9f7 519 adcNegSelAPORT0XCH9 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH9,
<> 144:ef7eb2e8f9f7 520 adcNegSelAPORT0XCH10 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH10,
<> 144:ef7eb2e8f9f7 521 adcNegSelAPORT0XCH11 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH11,
<> 144:ef7eb2e8f9f7 522 adcNegSelAPORT0XCH12 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH12,
<> 144:ef7eb2e8f9f7 523 adcNegSelAPORT0XCH13 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH13,
<> 144:ef7eb2e8f9f7 524 adcNegSelAPORT0XCH14 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH14,
<> 144:ef7eb2e8f9f7 525 adcNegSelAPORT0XCH15 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH15,
<> 144:ef7eb2e8f9f7 526 adcNegSelAPORT0YCH0 = _ADC_SINGLECTRL_NEGSEL_APORT0YCH0,
<> 144:ef7eb2e8f9f7 527 adcNegSelAPORT0YCH1 = _ADC_SINGLECTRL_NEGSEL_APORT0YCH1,
<> 144:ef7eb2e8f9f7 528 adcNegSelAPORT0YCH2 = _ADC_SINGLECTRL_NEGSEL_APORT0YCH2,
<> 144:ef7eb2e8f9f7 529 adcNegSelAPORT0YCH3 = _ADC_SINGLECTRL_NEGSEL_APORT0YCH3,
<> 144:ef7eb2e8f9f7 530 adcNegSelAPORT0YCH4 = _ADC_SINGLECTRL_NEGSEL_APORT0YCH4,
<> 144:ef7eb2e8f9f7 531 adcNegSelAPORT0YCH5 = _ADC_SINGLECTRL_NEGSEL_APORT0YCH5,
<> 144:ef7eb2e8f9f7 532 adcNegSelAPORT0YCH6 = _ADC_SINGLECTRL_NEGSEL_APORT0YCH6,
<> 144:ef7eb2e8f9f7 533 adcNegSelAPORT0YCH7 = _ADC_SINGLECTRL_NEGSEL_APORT0YCH7,
<> 144:ef7eb2e8f9f7 534 adcNegSelAPORT0YCH8 = _ADC_SINGLECTRL_NEGSEL_APORT0YCH8,
<> 144:ef7eb2e8f9f7 535 adcNegSelAPORT0YCH9 = _ADC_SINGLECTRL_NEGSEL_APORT0YCH9,
<> 144:ef7eb2e8f9f7 536 adcNegSelAPORT0YCH10 = _ADC_SINGLECTRL_NEGSEL_APORT0YCH10,
<> 144:ef7eb2e8f9f7 537 adcNegSelAPORT0YCH11 = _ADC_SINGLECTRL_NEGSEL_APORT0YCH11,
<> 144:ef7eb2e8f9f7 538 adcNegSelAPORT0YCH12 = _ADC_SINGLECTRL_NEGSEL_APORT0YCH12,
<> 144:ef7eb2e8f9f7 539 adcNegSelAPORT0YCH13 = _ADC_SINGLECTRL_NEGSEL_APORT0YCH13,
<> 144:ef7eb2e8f9f7 540 adcNegSelAPORT0YCH14 = _ADC_SINGLECTRL_NEGSEL_APORT0YCH14,
<> 144:ef7eb2e8f9f7 541 adcNegSelAPORT0YCH15 = _ADC_SINGLECTRL_NEGSEL_APORT0YCH15,
<> 144:ef7eb2e8f9f7 542 adcNegSelAPORT1XCH0 = _ADC_SINGLECTRL_NEGSEL_APORT1XCH0,
<> 144:ef7eb2e8f9f7 543 adcNegSelAPORT1YCH1 = _ADC_SINGLECTRL_NEGSEL_APORT1YCH1,
<> 144:ef7eb2e8f9f7 544 adcNegSelAPORT1XCH2 = _ADC_SINGLECTRL_NEGSEL_APORT1XCH2,
<> 144:ef7eb2e8f9f7 545 adcNegSelAPORT1YCH3 = _ADC_SINGLECTRL_NEGSEL_APORT1YCH3,
<> 144:ef7eb2e8f9f7 546 adcNegSelAPORT1XCH4 = _ADC_SINGLECTRL_NEGSEL_APORT1XCH4,
<> 144:ef7eb2e8f9f7 547 adcNegSelAPORT1YCH5 = _ADC_SINGLECTRL_NEGSEL_APORT1YCH5,
<> 144:ef7eb2e8f9f7 548 adcNegSelAPORT1XCH6 = _ADC_SINGLECTRL_NEGSEL_APORT1XCH6,
<> 144:ef7eb2e8f9f7 549 adcNegSelAPORT1YCH7 = _ADC_SINGLECTRL_NEGSEL_APORT1YCH7,
<> 144:ef7eb2e8f9f7 550 adcNegSelAPORT1XCH8 = _ADC_SINGLECTRL_NEGSEL_APORT1XCH8,
<> 144:ef7eb2e8f9f7 551 adcNegSelAPORT1YCH9 = _ADC_SINGLECTRL_NEGSEL_APORT1YCH9,
<> 144:ef7eb2e8f9f7 552 adcNegSelAPORT1XCH10 = _ADC_SINGLECTRL_NEGSEL_APORT1XCH10,
<> 144:ef7eb2e8f9f7 553 adcNegSelAPORT1YCH11 = _ADC_SINGLECTRL_NEGSEL_APORT1YCH11,
<> 144:ef7eb2e8f9f7 554 adcNegSelAPORT1XCH12 = _ADC_SINGLECTRL_NEGSEL_APORT1XCH12,
<> 144:ef7eb2e8f9f7 555 adcNegSelAPORT1YCH13 = _ADC_SINGLECTRL_NEGSEL_APORT1YCH13,
<> 144:ef7eb2e8f9f7 556 adcNegSelAPORT1XCH14 = _ADC_SINGLECTRL_NEGSEL_APORT1XCH14,
<> 144:ef7eb2e8f9f7 557 adcNegSelAPORT1YCH15 = _ADC_SINGLECTRL_NEGSEL_APORT1YCH15,
<> 144:ef7eb2e8f9f7 558 adcNegSelAPORT1XCH16 = _ADC_SINGLECTRL_NEGSEL_APORT1XCH16,
<> 144:ef7eb2e8f9f7 559 adcNegSelAPORT1YCH17 = _ADC_SINGLECTRL_NEGSEL_APORT1YCH17,
<> 144:ef7eb2e8f9f7 560 adcNegSelAPORT1XCH18 = _ADC_SINGLECTRL_NEGSEL_APORT1XCH18,
<> 144:ef7eb2e8f9f7 561 adcNegSelAPORT1YCH19 = _ADC_SINGLECTRL_NEGSEL_APORT1YCH19,
<> 144:ef7eb2e8f9f7 562 adcNegSelAPORT1XCH20 = _ADC_SINGLECTRL_NEGSEL_APORT1XCH20,
<> 144:ef7eb2e8f9f7 563 adcNegSelAPORT1YCH21 = _ADC_SINGLECTRL_NEGSEL_APORT1YCH21,
<> 144:ef7eb2e8f9f7 564 adcNegSelAPORT1XCH22 = _ADC_SINGLECTRL_NEGSEL_APORT1XCH22,
<> 144:ef7eb2e8f9f7 565 adcNegSelAPORT1YCH23 = _ADC_SINGLECTRL_NEGSEL_APORT1YCH23,
<> 144:ef7eb2e8f9f7 566 adcNegSelAPORT1XCH24 = _ADC_SINGLECTRL_NEGSEL_APORT1XCH24,
<> 144:ef7eb2e8f9f7 567 adcNegSelAPORT1YCH25 = _ADC_SINGLECTRL_NEGSEL_APORT1YCH25,
<> 144:ef7eb2e8f9f7 568 adcNegSelAPORT1XCH26 = _ADC_SINGLECTRL_NEGSEL_APORT1XCH26,
<> 144:ef7eb2e8f9f7 569 adcNegSelAPORT1YCH27 = _ADC_SINGLECTRL_NEGSEL_APORT1YCH27,
<> 144:ef7eb2e8f9f7 570 adcNegSelAPORT1XCH28 = _ADC_SINGLECTRL_NEGSEL_APORT1XCH28,
<> 144:ef7eb2e8f9f7 571 adcNegSelAPORT1YCH29 = _ADC_SINGLECTRL_NEGSEL_APORT1YCH29,
<> 144:ef7eb2e8f9f7 572 adcNegSelAPORT1XCH30 = _ADC_SINGLECTRL_NEGSEL_APORT1XCH30,
<> 144:ef7eb2e8f9f7 573 adcNegSelAPORT1YCH31 = _ADC_SINGLECTRL_NEGSEL_APORT1YCH31,
<> 144:ef7eb2e8f9f7 574 adcNegSelAPORT2YCH0 = _ADC_SINGLECTRL_NEGSEL_APORT2YCH0,
<> 144:ef7eb2e8f9f7 575 adcNegSelAPORT2XCH1 = _ADC_SINGLECTRL_NEGSEL_APORT2XCH1,
<> 144:ef7eb2e8f9f7 576 adcNegSelAPORT2YCH2 = _ADC_SINGLECTRL_NEGSEL_APORT2YCH2,
<> 144:ef7eb2e8f9f7 577 adcNegSelAPORT2XCH3 = _ADC_SINGLECTRL_NEGSEL_APORT2XCH3,
<> 144:ef7eb2e8f9f7 578 adcNegSelAPORT2YCH4 = _ADC_SINGLECTRL_NEGSEL_APORT2YCH4,
<> 144:ef7eb2e8f9f7 579 adcNegSelAPORT2XCH5 = _ADC_SINGLECTRL_NEGSEL_APORT2XCH5,
<> 144:ef7eb2e8f9f7 580 adcNegSelAPORT2YCH6 = _ADC_SINGLECTRL_NEGSEL_APORT2YCH6,
<> 144:ef7eb2e8f9f7 581 adcNegSelAPORT2XCH7 = _ADC_SINGLECTRL_NEGSEL_APORT2XCH7,
<> 144:ef7eb2e8f9f7 582 adcNegSelAPORT2YCH8 = _ADC_SINGLECTRL_NEGSEL_APORT2YCH8,
<> 144:ef7eb2e8f9f7 583 adcNegSelAPORT2XCH9 = _ADC_SINGLECTRL_NEGSEL_APORT2XCH9,
<> 144:ef7eb2e8f9f7 584 adcNegSelAPORT2YCH10 = _ADC_SINGLECTRL_NEGSEL_APORT2YCH10,
<> 144:ef7eb2e8f9f7 585 adcNegSelAPORT2XCH11 = _ADC_SINGLECTRL_NEGSEL_APORT2XCH11,
<> 144:ef7eb2e8f9f7 586 adcNegSelAPORT2YCH12 = _ADC_SINGLECTRL_NEGSEL_APORT2YCH12,
<> 144:ef7eb2e8f9f7 587 adcNegSelAPORT2XCH13 = _ADC_SINGLECTRL_NEGSEL_APORT2XCH13,
<> 144:ef7eb2e8f9f7 588 adcNegSelAPORT2YCH14 = _ADC_SINGLECTRL_NEGSEL_APORT2YCH14,
<> 144:ef7eb2e8f9f7 589 adcNegSelAPORT2XCH15 = _ADC_SINGLECTRL_NEGSEL_APORT2XCH15,
<> 144:ef7eb2e8f9f7 590 adcNegSelAPORT2YCH16 = _ADC_SINGLECTRL_NEGSEL_APORT2YCH16,
<> 144:ef7eb2e8f9f7 591 adcNegSelAPORT2XCH17 = _ADC_SINGLECTRL_NEGSEL_APORT2XCH17,
<> 144:ef7eb2e8f9f7 592 adcNegSelAPORT2YCH18 = _ADC_SINGLECTRL_NEGSEL_APORT2YCH18,
<> 144:ef7eb2e8f9f7 593 adcNegSelAPORT2XCH19 = _ADC_SINGLECTRL_NEGSEL_APORT2XCH19,
<> 144:ef7eb2e8f9f7 594 adcNegSelAPORT2YCH20 = _ADC_SINGLECTRL_NEGSEL_APORT2YCH20,
<> 144:ef7eb2e8f9f7 595 adcNegSelAPORT2XCH21 = _ADC_SINGLECTRL_NEGSEL_APORT2XCH21,
<> 144:ef7eb2e8f9f7 596 adcNegSelAPORT2YCH22 = _ADC_SINGLECTRL_NEGSEL_APORT2YCH22,
<> 144:ef7eb2e8f9f7 597 adcNegSelAPORT2XCH23 = _ADC_SINGLECTRL_NEGSEL_APORT2XCH23,
<> 144:ef7eb2e8f9f7 598 adcNegSelAPORT2YCH24 = _ADC_SINGLECTRL_NEGSEL_APORT2YCH24,
<> 144:ef7eb2e8f9f7 599 adcNegSelAPORT2XCH25 = _ADC_SINGLECTRL_NEGSEL_APORT2XCH25,
<> 144:ef7eb2e8f9f7 600 adcNegSelAPORT2YCH26 = _ADC_SINGLECTRL_NEGSEL_APORT2YCH26,
<> 144:ef7eb2e8f9f7 601 adcNegSelAPORT2XCH27 = _ADC_SINGLECTRL_NEGSEL_APORT2XCH27,
<> 144:ef7eb2e8f9f7 602 adcNegSelAPORT2YCH28 = _ADC_SINGLECTRL_NEGSEL_APORT2YCH28,
<> 144:ef7eb2e8f9f7 603 adcNegSelAPORT2XCH29 = _ADC_SINGLECTRL_NEGSEL_APORT2XCH29,
<> 144:ef7eb2e8f9f7 604 adcNegSelAPORT2YCH30 = _ADC_SINGLECTRL_NEGSEL_APORT2YCH30,
<> 144:ef7eb2e8f9f7 605 adcNegSelAPORT2XCH31 = _ADC_SINGLECTRL_NEGSEL_APORT2XCH31,
<> 144:ef7eb2e8f9f7 606 adcNegSelAPORT3XCH0 = _ADC_SINGLECTRL_NEGSEL_APORT3XCH0,
<> 144:ef7eb2e8f9f7 607 adcNegSelAPORT3YCH1 = _ADC_SINGLECTRL_NEGSEL_APORT3YCH1,
<> 144:ef7eb2e8f9f7 608 adcNegSelAPORT3XCH2 = _ADC_SINGLECTRL_NEGSEL_APORT3XCH2,
<> 144:ef7eb2e8f9f7 609 adcNegSelAPORT3YCH3 = _ADC_SINGLECTRL_NEGSEL_APORT3YCH3,
<> 144:ef7eb2e8f9f7 610 adcNegSelAPORT3XCH4 = _ADC_SINGLECTRL_NEGSEL_APORT3XCH4,
<> 144:ef7eb2e8f9f7 611 adcNegSelAPORT3YCH5 = _ADC_SINGLECTRL_NEGSEL_APORT3YCH5,
<> 144:ef7eb2e8f9f7 612 adcNegSelAPORT3XCH6 = _ADC_SINGLECTRL_NEGSEL_APORT3XCH6,
<> 144:ef7eb2e8f9f7 613 adcNegSelAPORT3YCH7 = _ADC_SINGLECTRL_NEGSEL_APORT3YCH7,
<> 144:ef7eb2e8f9f7 614 adcNegSelAPORT3XCH8 = _ADC_SINGLECTRL_NEGSEL_APORT3XCH8,
<> 144:ef7eb2e8f9f7 615 adcNegSelAPORT3YCH9 = _ADC_SINGLECTRL_NEGSEL_APORT3YCH9,
<> 144:ef7eb2e8f9f7 616 adcNegSelAPORT3XCH10 = _ADC_SINGLECTRL_NEGSEL_APORT3XCH10,
<> 144:ef7eb2e8f9f7 617 adcNegSelAPORT3YCH11 = _ADC_SINGLECTRL_NEGSEL_APORT3YCH11,
<> 144:ef7eb2e8f9f7 618 adcNegSelAPORT3XCH12 = _ADC_SINGLECTRL_NEGSEL_APORT3XCH12,
<> 144:ef7eb2e8f9f7 619 adcNegSelAPORT3YCH13 = _ADC_SINGLECTRL_NEGSEL_APORT3YCH13,
<> 144:ef7eb2e8f9f7 620 adcNegSelAPORT3XCH14 = _ADC_SINGLECTRL_NEGSEL_APORT3XCH14,
<> 144:ef7eb2e8f9f7 621 adcNegSelAPORT3YCH15 = _ADC_SINGLECTRL_NEGSEL_APORT3YCH15,
<> 144:ef7eb2e8f9f7 622 adcNegSelAPORT3XCH16 = _ADC_SINGLECTRL_NEGSEL_APORT3XCH16,
<> 144:ef7eb2e8f9f7 623 adcNegSelAPORT3YCH17 = _ADC_SINGLECTRL_NEGSEL_APORT3YCH17,
<> 144:ef7eb2e8f9f7 624 adcNegSelAPORT3XCH18 = _ADC_SINGLECTRL_NEGSEL_APORT3XCH18,
<> 144:ef7eb2e8f9f7 625 adcNegSelAPORT3YCH19 = _ADC_SINGLECTRL_NEGSEL_APORT3YCH19,
<> 144:ef7eb2e8f9f7 626 adcNegSelAPORT3XCH20 = _ADC_SINGLECTRL_NEGSEL_APORT3XCH20,
<> 144:ef7eb2e8f9f7 627 adcNegSelAPORT3YCH21 = _ADC_SINGLECTRL_NEGSEL_APORT3YCH21,
<> 144:ef7eb2e8f9f7 628 adcNegSelAPORT3XCH22 = _ADC_SINGLECTRL_NEGSEL_APORT3XCH22,
<> 144:ef7eb2e8f9f7 629 adcNegSelAPORT3YCH23 = _ADC_SINGLECTRL_NEGSEL_APORT3YCH23,
<> 144:ef7eb2e8f9f7 630 adcNegSelAPORT3XCH24 = _ADC_SINGLECTRL_NEGSEL_APORT3XCH24,
<> 144:ef7eb2e8f9f7 631 adcNegSelAPORT3YCH25 = _ADC_SINGLECTRL_NEGSEL_APORT3YCH25,
<> 144:ef7eb2e8f9f7 632 adcNegSelAPORT3XCH26 = _ADC_SINGLECTRL_NEGSEL_APORT3XCH26,
<> 144:ef7eb2e8f9f7 633 adcNegSelAPORT3YCH27 = _ADC_SINGLECTRL_NEGSEL_APORT3YCH27,
<> 144:ef7eb2e8f9f7 634 adcNegSelAPORT3XCH28 = _ADC_SINGLECTRL_NEGSEL_APORT3XCH28,
<> 144:ef7eb2e8f9f7 635 adcNegSelAPORT3YCH29 = _ADC_SINGLECTRL_NEGSEL_APORT3YCH29,
<> 144:ef7eb2e8f9f7 636 adcNegSelAPORT3XCH30 = _ADC_SINGLECTRL_NEGSEL_APORT3XCH30,
<> 144:ef7eb2e8f9f7 637 adcNegSelAPORT3YCH31 = _ADC_SINGLECTRL_NEGSEL_APORT3YCH31,
<> 144:ef7eb2e8f9f7 638 adcNegSelAPORT4YCH0 = _ADC_SINGLECTRL_NEGSEL_APORT4YCH0,
<> 144:ef7eb2e8f9f7 639 adcNegSelAPORT4XCH1 = _ADC_SINGLECTRL_NEGSEL_APORT4XCH1,
<> 144:ef7eb2e8f9f7 640 adcNegSelAPORT4YCH2 = _ADC_SINGLECTRL_NEGSEL_APORT4YCH2,
<> 144:ef7eb2e8f9f7 641 adcNegSelAPORT4XCH3 = _ADC_SINGLECTRL_NEGSEL_APORT4XCH3,
<> 144:ef7eb2e8f9f7 642 adcNegSelAPORT4YCH4 = _ADC_SINGLECTRL_NEGSEL_APORT4YCH4,
<> 144:ef7eb2e8f9f7 643 adcNegSelAPORT4XCH5 = _ADC_SINGLECTRL_NEGSEL_APORT4XCH5,
<> 144:ef7eb2e8f9f7 644 adcNegSelAPORT4YCH6 = _ADC_SINGLECTRL_NEGSEL_APORT4YCH6,
<> 144:ef7eb2e8f9f7 645 adcNegSelAPORT4XCH7 = _ADC_SINGLECTRL_NEGSEL_APORT4XCH7,
<> 144:ef7eb2e8f9f7 646 adcNegSelAPORT4YCH8 = _ADC_SINGLECTRL_NEGSEL_APORT4YCH8,
<> 144:ef7eb2e8f9f7 647 adcNegSelAPORT4XCH9 = _ADC_SINGLECTRL_NEGSEL_APORT4XCH9,
<> 144:ef7eb2e8f9f7 648 adcNegSelAPORT4YCH10 = _ADC_SINGLECTRL_NEGSEL_APORT4YCH10,
<> 144:ef7eb2e8f9f7 649 adcNegSelAPORT4XCH11 = _ADC_SINGLECTRL_NEGSEL_APORT4XCH11,
<> 144:ef7eb2e8f9f7 650 adcNegSelAPORT4YCH12 = _ADC_SINGLECTRL_NEGSEL_APORT4YCH12,
<> 144:ef7eb2e8f9f7 651 adcNegSelAPORT4XCH13 = _ADC_SINGLECTRL_NEGSEL_APORT4XCH13,
<> 144:ef7eb2e8f9f7 652 adcNegSelAPORT4YCH14 = _ADC_SINGLECTRL_NEGSEL_APORT4YCH14,
<> 144:ef7eb2e8f9f7 653 adcNegSelAPORT4XCH15 = _ADC_SINGLECTRL_NEGSEL_APORT4XCH15,
<> 144:ef7eb2e8f9f7 654 adcNegSelAPORT4YCH16 = _ADC_SINGLECTRL_NEGSEL_APORT4YCH16,
<> 144:ef7eb2e8f9f7 655 adcNegSelAPORT4XCH17 = _ADC_SINGLECTRL_NEGSEL_APORT4XCH17,
<> 144:ef7eb2e8f9f7 656 adcNegSelAPORT4YCH18 = _ADC_SINGLECTRL_NEGSEL_APORT4YCH18,
<> 144:ef7eb2e8f9f7 657 adcNegSelAPORT4XCH19 = _ADC_SINGLECTRL_NEGSEL_APORT4XCH19,
<> 144:ef7eb2e8f9f7 658 adcNegSelAPORT4YCH20 = _ADC_SINGLECTRL_NEGSEL_APORT4YCH20,
<> 144:ef7eb2e8f9f7 659 adcNegSelAPORT4XCH21 = _ADC_SINGLECTRL_NEGSEL_APORT4XCH21,
<> 144:ef7eb2e8f9f7 660 adcNegSelAPORT4YCH22 = _ADC_SINGLECTRL_NEGSEL_APORT4YCH22,
<> 144:ef7eb2e8f9f7 661 adcNegSelAPORT4XCH23 = _ADC_SINGLECTRL_NEGSEL_APORT4XCH23,
<> 144:ef7eb2e8f9f7 662 adcNegSelAPORT4YCH24 = _ADC_SINGLECTRL_NEGSEL_APORT4YCH24,
<> 144:ef7eb2e8f9f7 663 adcNegSelAPORT4XCH25 = _ADC_SINGLECTRL_NEGSEL_APORT4XCH25,
<> 144:ef7eb2e8f9f7 664 adcNegSelAPORT4YCH26 = _ADC_SINGLECTRL_NEGSEL_APORT4YCH26,
<> 144:ef7eb2e8f9f7 665 adcNegSelAPORT4XCH27 = _ADC_SINGLECTRL_NEGSEL_APORT4XCH27,
<> 144:ef7eb2e8f9f7 666 adcNegSelAPORT4YCH28 = _ADC_SINGLECTRL_NEGSEL_APORT4YCH28,
<> 144:ef7eb2e8f9f7 667 adcNegSelAPORT4XCH29 = _ADC_SINGLECTRL_NEGSEL_APORT4XCH29,
<> 144:ef7eb2e8f9f7 668 adcNegSelAPORT4YCH30 = _ADC_SINGLECTRL_NEGSEL_APORT4YCH30,
<> 144:ef7eb2e8f9f7 669 adcNegSelAPORT4XCH31 = _ADC_SINGLECTRL_NEGSEL_APORT4XCH31,
<> 144:ef7eb2e8f9f7 670 adcNegSelTESTN = _ADC_SINGLECTRL_NEGSEL_TESTN,
<> 144:ef7eb2e8f9f7 671 adcNegSelDEFAULT = _ADC_SINGLECTRL_NEGSEL_DEFAULT,
<> 144:ef7eb2e8f9f7 672 adcNegSelVSS = _ADC_SINGLECTRL_NEGSEL_VSS
<> 144:ef7eb2e8f9f7 673 } ADC_NegSel_TypeDef;
<> 144:ef7eb2e8f9f7 674 #endif
<> 144:ef7eb2e8f9f7 675
<> 144:ef7eb2e8f9f7 676
<> 144:ef7eb2e8f9f7 677 #if defined( _ADC_SCANINPUTSEL_MASK )
<> 144:ef7eb2e8f9f7 678 /* ADC scan input groups */
<> 144:ef7eb2e8f9f7 679 typedef enum
<> 144:ef7eb2e8f9f7 680 {
<> 144:ef7eb2e8f9f7 681 adcScanInputGroup0 = 0,
<> 144:ef7eb2e8f9f7 682 adcScanInputGroup1 = 1,
<> 144:ef7eb2e8f9f7 683 adcScanInputGroup2 = 2,
<> 144:ef7eb2e8f9f7 684 adcScanInputGroup3 = 3,
<> 144:ef7eb2e8f9f7 685 } ADC_ScanInputGroup_TypeDef;
<> 144:ef7eb2e8f9f7 686
<> 144:ef7eb2e8f9f7 687 /* ADC scan alternative negative inputs */
<> 144:ef7eb2e8f9f7 688 typedef enum
<> 144:ef7eb2e8f9f7 689 {
<> 144:ef7eb2e8f9f7 690 adcScanNegInput1 = 1,
<> 144:ef7eb2e8f9f7 691 adcScanNegInput3 = 3,
<> 144:ef7eb2e8f9f7 692 adcScanNegInput5 = 5,
<> 144:ef7eb2e8f9f7 693 adcScanNegInput7 = 7,
<> 144:ef7eb2e8f9f7 694 adcScanNegInput8 = 8,
<> 144:ef7eb2e8f9f7 695 adcScanNegInput10 = 10,
<> 144:ef7eb2e8f9f7 696 adcScanNegInput12 = 12,
<> 144:ef7eb2e8f9f7 697 adcScanNegInput14 = 14,
<> 144:ef7eb2e8f9f7 698 adcScanNegInputDefault = 0xFF,
<> 144:ef7eb2e8f9f7 699 } ADC_ScanNegInput_TypeDef;
<> 144:ef7eb2e8f9f7 700 #endif
<> 144:ef7eb2e8f9f7 701
<> 144:ef7eb2e8f9f7 702
<> 144:ef7eb2e8f9f7 703 /** ADC Start command. */
<> 144:ef7eb2e8f9f7 704 typedef enum
<> 144:ef7eb2e8f9f7 705 {
<> 144:ef7eb2e8f9f7 706 /** Start single conversion. */
<> 144:ef7eb2e8f9f7 707 adcStartSingle = ADC_CMD_SINGLESTART,
<> 144:ef7eb2e8f9f7 708
<> 144:ef7eb2e8f9f7 709 /** Start scan sequence. */
<> 144:ef7eb2e8f9f7 710 adcStartScan = ADC_CMD_SCANSTART,
<> 144:ef7eb2e8f9f7 711
<> 144:ef7eb2e8f9f7 712 /**
<> 144:ef7eb2e8f9f7 713 * Start scan sequence and single conversion, typically used when tailgating
<> 144:ef7eb2e8f9f7 714 * single conversion after scan sequence.
<> 144:ef7eb2e8f9f7 715 */
<> 144:ef7eb2e8f9f7 716 adcStartScanAndSingle = ADC_CMD_SCANSTART | ADC_CMD_SINGLESTART
<> 144:ef7eb2e8f9f7 717 } ADC_Start_TypeDef;
<> 144:ef7eb2e8f9f7 718
<> 144:ef7eb2e8f9f7 719
<> 144:ef7eb2e8f9f7 720 /** Warm-up mode. */
<> 144:ef7eb2e8f9f7 721 typedef enum
<> 144:ef7eb2e8f9f7 722 {
<> 144:ef7eb2e8f9f7 723 /** ADC shutdown after each conversion. */
<> 144:ef7eb2e8f9f7 724 adcWarmupNormal = _ADC_CTRL_WARMUPMODE_NORMAL,
<> 144:ef7eb2e8f9f7 725
<> 144:ef7eb2e8f9f7 726 #if defined( _ADC_CTRL_WARMUPMODE_FASTBG )
<> 144:ef7eb2e8f9f7 727 /** Do not warm-up bandgap references. */
<> 144:ef7eb2e8f9f7 728 adcWarmupFastBG = _ADC_CTRL_WARMUPMODE_FASTBG,
<> 144:ef7eb2e8f9f7 729 #endif
<> 144:ef7eb2e8f9f7 730
<> 144:ef7eb2e8f9f7 731 #if defined( _ADC_CTRL_WARMUPMODE_KEEPSCANREFWARM )
<> 144:ef7eb2e8f9f7 732 /** Reference selected for scan mode kept warm.*/
<> 144:ef7eb2e8f9f7 733 adcWarmupKeepScanRefWarm = _ADC_CTRL_WARMUPMODE_KEEPSCANREFWARM,
<> 144:ef7eb2e8f9f7 734 #endif
<> 144:ef7eb2e8f9f7 735
<> 144:ef7eb2e8f9f7 736 #if defined( _ADC_CTRL_WARMUPMODE_KEEPINSTANDBY )
<> 144:ef7eb2e8f9f7 737 /** ADC is kept in standby mode between conversion. 1us warmup time needed
<> 144:ef7eb2e8f9f7 738 before next conversion. */
<> 144:ef7eb2e8f9f7 739 adcWarmupKeepInStandby = _ADC_CTRL_WARMUPMODE_KEEPINSTANDBY,
<> 144:ef7eb2e8f9f7 740 #endif
<> 144:ef7eb2e8f9f7 741
<> 144:ef7eb2e8f9f7 742 #if defined( _ADC_CTRL_WARMUPMODE_KEEPINSLOWACC )
<> 144:ef7eb2e8f9f7 743 /** ADC is kept in slow acquisition mode between conversions. 1us warmup
<> 144:ef7eb2e8f9f7 744 time needed before next conversion. */
<> 144:ef7eb2e8f9f7 745 adcWarmupKeepInSlowAcq = _ADC_CTRL_WARMUPMODE_KEEPINSLOWACC,
<> 144:ef7eb2e8f9f7 746 #endif
<> 144:ef7eb2e8f9f7 747
<> 144:ef7eb2e8f9f7 748 /** ADC and reference selected for scan mode kept warmup, allowing
<> 144:ef7eb2e8f9f7 749 continuous conversion. */
<> 144:ef7eb2e8f9f7 750 adcWarmupKeepADCWarm = _ADC_CTRL_WARMUPMODE_KEEPADCWARM,
<> 144:ef7eb2e8f9f7 751
<> 144:ef7eb2e8f9f7 752 } ADC_Warmup_TypeDef;
<> 144:ef7eb2e8f9f7 753
<> 144:ef7eb2e8f9f7 754
<> 144:ef7eb2e8f9f7 755 #if defined( _ADC_CTRL_ADCCLKMODE_MASK )
<> 144:ef7eb2e8f9f7 756 /** ADC EM2 clock configuration */
<> 144:ef7eb2e8f9f7 757 typedef enum
<> 144:ef7eb2e8f9f7 758 {
<> 144:ef7eb2e8f9f7 759 adcEm2Disabled = 0,
<> 144:ef7eb2e8f9f7 760 adcEm2ClockOnDemand = _ADC_CTRL_ADCCLKMODE_ASYNC | _ADC_CTRL_ASYNCCLKEN_ASNEEDED,
<> 144:ef7eb2e8f9f7 761 adcEm2ClockAlwaysOn = _ADC_CTRL_ADCCLKMODE_ASYNC | _ADC_CTRL_ASYNCCLKEN_ALWAYSON,
<> 144:ef7eb2e8f9f7 762 } ADC_EM2ClockConfig_TypeDef;
<> 144:ef7eb2e8f9f7 763 #endif
<> 144:ef7eb2e8f9f7 764
<> 144:ef7eb2e8f9f7 765
<> 144:ef7eb2e8f9f7 766 /*******************************************************************************
<> 144:ef7eb2e8f9f7 767 ******************************* STRUCTS ***********************************
<> 144:ef7eb2e8f9f7 768 ******************************************************************************/
<> 144:ef7eb2e8f9f7 769
<> 144:ef7eb2e8f9f7 770 /** ADC init structure, common for single conversion and scan sequence. */
<> 144:ef7eb2e8f9f7 771 typedef struct
<> 144:ef7eb2e8f9f7 772 {
<> 144:ef7eb2e8f9f7 773 /**
<> 144:ef7eb2e8f9f7 774 * Oversampling rate select. In order to have any effect, oversampling must
<> 144:ef7eb2e8f9f7 775 * be enabled for single/scan mode.
<> 144:ef7eb2e8f9f7 776 */
<> 144:ef7eb2e8f9f7 777 ADC_OvsRateSel_TypeDef ovsRateSel;
<> 144:ef7eb2e8f9f7 778
<> 144:ef7eb2e8f9f7 779 #if defined( _ADC_CTRL_LPFMODE_MASK )
<> 144:ef7eb2e8f9f7 780 /** Lowpass or decoupling capacitor filter to use. */
<> 144:ef7eb2e8f9f7 781 ADC_LPFilter_TypeDef lpfMode;
<> 144:ef7eb2e8f9f7 782 #endif
<> 144:ef7eb2e8f9f7 783
<> 144:ef7eb2e8f9f7 784 /** Warm-up mode to use for ADC. */
<> 144:ef7eb2e8f9f7 785 ADC_Warmup_TypeDef warmUpMode;
<> 144:ef7eb2e8f9f7 786
<> 144:ef7eb2e8f9f7 787 /**
<> 144:ef7eb2e8f9f7 788 * Timebase used for ADC warm up. Select N to give (N+1)HFPERCLK cycles.
<> 144:ef7eb2e8f9f7 789 * (Additional delay is added for bandgap references, please refer to the
<> 144:ef7eb2e8f9f7 790 * reference manual.) Normally, N should be selected so that the timebase
<> 144:ef7eb2e8f9f7 791 * is at least 1 us. See ADC_TimebaseCalc() for a way to obtain
<> 144:ef7eb2e8f9f7 792 * a suggested timebase of at least 1 us.
<> 144:ef7eb2e8f9f7 793 */
<> 144:ef7eb2e8f9f7 794 uint8_t timebase;
<> 144:ef7eb2e8f9f7 795
<> 144:ef7eb2e8f9f7 796 /** Clock division factor N, ADC clock = HFPERCLK / (N + 1). */
<> 144:ef7eb2e8f9f7 797 uint8_t prescale;
<> 144:ef7eb2e8f9f7 798
<> 144:ef7eb2e8f9f7 799 /** Enable/disable conversion tailgating. */
<> 144:ef7eb2e8f9f7 800 bool tailgate;
<> 144:ef7eb2e8f9f7 801
<> 144:ef7eb2e8f9f7 802 /** ADC EM2 clock configuration */
<> 144:ef7eb2e8f9f7 803 #if defined( _ADC_CTRL_ADCCLKMODE_MASK )
<> 144:ef7eb2e8f9f7 804 ADC_EM2ClockConfig_TypeDef em2ClockConfig;
<> 144:ef7eb2e8f9f7 805 #endif
<> 144:ef7eb2e8f9f7 806 } ADC_Init_TypeDef;
<> 144:ef7eb2e8f9f7 807
<> 144:ef7eb2e8f9f7 808
<> 144:ef7eb2e8f9f7 809 /** Default config for ADC init structure. */
<> 144:ef7eb2e8f9f7 810 #if defined( _ADC_CTRL_LPFMODE_MASK ) && (!defined( _ADC_CTRL_ADCCLKMODE_MASK ))
<> 144:ef7eb2e8f9f7 811 #define ADC_INIT_DEFAULT \
<> 144:ef7eb2e8f9f7 812 { \
<> 144:ef7eb2e8f9f7 813 adcOvsRateSel2, /* 2x oversampling (if enabled). */ \
<> 144:ef7eb2e8f9f7 814 adcLPFilterBypass, /* No input filter selected. */ \
<> 144:ef7eb2e8f9f7 815 adcWarmupNormal, /* ADC shutdown after each conversion. */ \
<> 144:ef7eb2e8f9f7 816 _ADC_CTRL_TIMEBASE_DEFAULT, /* Use HW default value. */ \
<> 144:ef7eb2e8f9f7 817 _ADC_CTRL_PRESC_DEFAULT, /* Use HW default value. */ \
<> 144:ef7eb2e8f9f7 818 false /* Do not use tailgate. */ \
<> 144:ef7eb2e8f9f7 819 }
<> 144:ef7eb2e8f9f7 820 #elif (!defined( _ADC_CTRL_LPFMODE_MASK )) && (!defined( _ADC_CTRL_ADCCLKMODE_MASK ))
<> 144:ef7eb2e8f9f7 821 #define ADC_INIT_DEFAULT \
<> 144:ef7eb2e8f9f7 822 { \
<> 144:ef7eb2e8f9f7 823 adcOvsRateSel2, /* 2x oversampling (if enabled). */ \
<> 144:ef7eb2e8f9f7 824 adcWarmupNormal, /* ADC shutdown after each conversion. */ \
<> 144:ef7eb2e8f9f7 825 _ADC_CTRL_TIMEBASE_DEFAULT, /* Use HW default value. */ \
<> 144:ef7eb2e8f9f7 826 _ADC_CTRL_PRESC_DEFAULT, /* Use HW default value. */ \
<> 144:ef7eb2e8f9f7 827 false /* Do not use tailgate. */ \
<> 144:ef7eb2e8f9f7 828 }
<> 144:ef7eb2e8f9f7 829 #elif (!defined( _ADC_CTRL_LPFMODE_MASK )) && defined( _ADC_CTRL_ADCCLKMODE_MASK )
<> 144:ef7eb2e8f9f7 830 #define ADC_INIT_DEFAULT \
<> 144:ef7eb2e8f9f7 831 { \
<> 144:ef7eb2e8f9f7 832 adcOvsRateSel2, /* 2x oversampling (if enabled). */ \
<> 144:ef7eb2e8f9f7 833 adcWarmupNormal, /* ADC shutdown after each conversion. */ \
<> 144:ef7eb2e8f9f7 834 _ADC_CTRL_TIMEBASE_DEFAULT, /* Use HW default value. */ \
<> 144:ef7eb2e8f9f7 835 _ADC_CTRL_PRESC_DEFAULT, /* Use HW default value. */ \
<> 144:ef7eb2e8f9f7 836 false, /* Do not use tailgate. */ \
<> 144:ef7eb2e8f9f7 837 adcEm2Disabled /* ADC disabled in EM2 */ \
<> 144:ef7eb2e8f9f7 838 }
<> 144:ef7eb2e8f9f7 839 #endif
<> 144:ef7eb2e8f9f7 840
<> 144:ef7eb2e8f9f7 841
<> 144:ef7eb2e8f9f7 842 /** Scan input configuration */
<> 144:ef7eb2e8f9f7 843 typedef struct
<> 144:ef7eb2e8f9f7 844 {
<> 144:ef7eb2e8f9f7 845 /** Input range select to be applied to ADC_SCANCHCONF. */
<> 144:ef7eb2e8f9f7 846 int32_t scanInputSel;
<> 144:ef7eb2e8f9f7 847
<> 144:ef7eb2e8f9f7 848 /** Input enable mask */
<> 144:ef7eb2e8f9f7 849 uint32_t scanInputEn;
<> 144:ef7eb2e8f9f7 850
<> 144:ef7eb2e8f9f7 851 /** Alternative negative input */
<> 144:ef7eb2e8f9f7 852 uint32_t scanNegSel;
<> 144:ef7eb2e8f9f7 853 } ADC_InitScanInput_TypeDef;
<> 144:ef7eb2e8f9f7 854
<> 144:ef7eb2e8f9f7 855
<> 144:ef7eb2e8f9f7 856 /** Scan sequence init structure. */
<> 144:ef7eb2e8f9f7 857 typedef struct
<> 144:ef7eb2e8f9f7 858 {
<> 144:ef7eb2e8f9f7 859 /**
<> 144:ef7eb2e8f9f7 860 * Peripheral reflex system trigger selection. Only applicable if @p prsEnable
<> 144:ef7eb2e8f9f7 861 * is enabled.
<> 144:ef7eb2e8f9f7 862 */
<> 144:ef7eb2e8f9f7 863 ADC_PRSSEL_TypeDef prsSel;
<> 144:ef7eb2e8f9f7 864
<> 144:ef7eb2e8f9f7 865 /** Acquisition time (in ADC clock cycles). */
<> 144:ef7eb2e8f9f7 866 ADC_AcqTime_TypeDef acqTime;
<> 144:ef7eb2e8f9f7 867
<> 144:ef7eb2e8f9f7 868 /**
<> 144:ef7eb2e8f9f7 869 * Sample reference selection. Notice that for external references, the
<> 144:ef7eb2e8f9f7 870 * ADC calibration register must be set explicitly.
<> 144:ef7eb2e8f9f7 871 */
<> 144:ef7eb2e8f9f7 872 ADC_Ref_TypeDef reference;
<> 144:ef7eb2e8f9f7 873
<> 144:ef7eb2e8f9f7 874 /** Sample resolution. */
<> 144:ef7eb2e8f9f7 875 ADC_Res_TypeDef resolution;
<> 144:ef7eb2e8f9f7 876
<> 144:ef7eb2e8f9f7 877 #if defined( _ADC_SCANCTRL_INPUTMASK_MASK )
<> 144:ef7eb2e8f9f7 878 /**
<> 144:ef7eb2e8f9f7 879 * Scan input selection. If single ended (@p diff is false), use logical
<> 144:ef7eb2e8f9f7 880 * combination of ADC_SCANCTRL_INPUTMASK_CHx defines. If differential input
<> 144:ef7eb2e8f9f7 881 * (@p diff is true), use logical combination of ADC_SCANCTRL_INPUTMASK_CHxCHy
<> 144:ef7eb2e8f9f7 882 * defines. (Notice underscore prefix for defines used.)
<> 144:ef7eb2e8f9f7 883 */
<> 144:ef7eb2e8f9f7 884 uint32_t input;
<> 144:ef7eb2e8f9f7 885 #endif
<> 144:ef7eb2e8f9f7 886
<> 144:ef7eb2e8f9f7 887 #if defined( _ADC_SCANINPUTSEL_MASK )
<> 144:ef7eb2e8f9f7 888 /**
<> 144:ef7eb2e8f9f7 889 * Scan input configuration. Use ADC_ScanSingleEndedInit() or ADC_ScanDifferentialInit()
<> 144:ef7eb2e8f9f7 890 * to write this struct. Note that the diff variable is included in ADC_InitScanInput_TypeDef.
<> 144:ef7eb2e8f9f7 891 */
<> 144:ef7eb2e8f9f7 892 ADC_InitScanInput_TypeDef scanInputConfig;
<> 144:ef7eb2e8f9f7 893 #endif
<> 144:ef7eb2e8f9f7 894
<> 144:ef7eb2e8f9f7 895 /** Select if single ended or differential input. */
<> 144:ef7eb2e8f9f7 896 bool diff;
<> 144:ef7eb2e8f9f7 897
<> 144:ef7eb2e8f9f7 898 /** Peripheral reflex system trigger enable. */
<> 144:ef7eb2e8f9f7 899 bool prsEnable;
<> 144:ef7eb2e8f9f7 900
<> 144:ef7eb2e8f9f7 901 /** Select if left adjustment should be done. */
<> 144:ef7eb2e8f9f7 902 bool leftAdjust;
<> 144:ef7eb2e8f9f7 903
<> 144:ef7eb2e8f9f7 904 /** Select if continuous conversion until explicit stop. */
<> 144:ef7eb2e8f9f7 905 bool rep;
<> 144:ef7eb2e8f9f7 906
<> 144:ef7eb2e8f9f7 907 /** When true, DMA is available in EM2 for scan conversion */
<> 144:ef7eb2e8f9f7 908 #if defined( _ADC_CTRL_SCANDMAWU_MASK )
<> 144:ef7eb2e8f9f7 909 bool scanDmaEm2Wu;
<> 144:ef7eb2e8f9f7 910 #endif
<> 144:ef7eb2e8f9f7 911
<> 144:ef7eb2e8f9f7 912 #if defined( _ADC_SCANCTRLX_FIFOOFACT_MASK )
<> 144:ef7eb2e8f9f7 913 /** When true, the FIFO overwrites old data when full. If false, then the FIFO discards new data.
<> 144:ef7eb2e8f9f7 914 The SINGLEOF IRQ is triggered in both cases. */
<> 144:ef7eb2e8f9f7 915 bool fifoOverwrite;
<> 144:ef7eb2e8f9f7 916 #endif
<> 144:ef7eb2e8f9f7 917 } ADC_InitScan_TypeDef;
<> 144:ef7eb2e8f9f7 918
<> 144:ef7eb2e8f9f7 919 /** Default config for ADC scan init structure. */
<> 144:ef7eb2e8f9f7 920 #if defined( _ADC_SCANCTRL_INPUTMASK_MASK )
<> 144:ef7eb2e8f9f7 921 #define ADC_INITSCAN_DEFAULT \
<> 144:ef7eb2e8f9f7 922 { \
<> 144:ef7eb2e8f9f7 923 adcPRSSELCh0, /* PRS ch0 (if enabled). */ \
<> 144:ef7eb2e8f9f7 924 adcAcqTime1, /* 1 ADC_CLK cycle acquisition time. */ \
<> 144:ef7eb2e8f9f7 925 adcRef1V25, /* 1.25V internal reference. */ \
<> 144:ef7eb2e8f9f7 926 adcRes12Bit, /* 12 bit resolution. */ \
<> 144:ef7eb2e8f9f7 927 0, /* No input selected. */ \
<> 144:ef7eb2e8f9f7 928 false, /* Single-ended input. */ \
<> 144:ef7eb2e8f9f7 929 false, /* PRS disabled. */ \
<> 144:ef7eb2e8f9f7 930 false, /* Right adjust. */ \
<> 144:ef7eb2e8f9f7 931 false, /* Deactivate conversion after one scan sequence. */ \
<> 144:ef7eb2e8f9f7 932 }
<> 144:ef7eb2e8f9f7 933 #endif
<> 144:ef7eb2e8f9f7 934
<> 144:ef7eb2e8f9f7 935 #if defined( _ADC_SCANINPUTSEL_MASK )
<> 144:ef7eb2e8f9f7 936 #define ADC_INITSCAN_DEFAULT \
<> 144:ef7eb2e8f9f7 937 { \
<> 144:ef7eb2e8f9f7 938 adcPRSSELCh0, /* PRS ch0 (if enabled). */ \
<> 144:ef7eb2e8f9f7 939 adcAcqTime1, /* 1 ADC_CLK cycle acquisition time. */ \
<> 144:ef7eb2e8f9f7 940 adcRef1V25, /* 1.25V internal reference. */ \
<> 144:ef7eb2e8f9f7 941 adcRes12Bit, /* 12 bit resolution. */ \
<> 144:ef7eb2e8f9f7 942 0, /* Default ADC inputs */ \
<> 144:ef7eb2e8f9f7 943 0, /* Default input mask (all off) */ \
<> 144:ef7eb2e8f9f7 944 _ADC_SCANNEGSEL_RESETVALUE,/* Default negative select for positive ternimal */ \
<> 144:ef7eb2e8f9f7 945 false, /* Single-ended input. */ \
<> 144:ef7eb2e8f9f7 946 false, /* PRS disabled. */ \
<> 144:ef7eb2e8f9f7 947 false, /* Right adjust. */ \
<> 144:ef7eb2e8f9f7 948 false, /* Deactivate conversion after one scan sequence. */ \
<> 144:ef7eb2e8f9f7 949 false, /* No EM2 DMA wakeup from scan FIFO DVL */ \
<> 144:ef7eb2e8f9f7 950 false /* Discard new data on full FIFO. */ \
<> 144:ef7eb2e8f9f7 951 }
<> 144:ef7eb2e8f9f7 952 #endif
<> 144:ef7eb2e8f9f7 953
<> 144:ef7eb2e8f9f7 954
<> 144:ef7eb2e8f9f7 955 /** Single conversion init structure. */
<> 144:ef7eb2e8f9f7 956 typedef struct
<> 144:ef7eb2e8f9f7 957 {
<> 144:ef7eb2e8f9f7 958 /**
<> 144:ef7eb2e8f9f7 959 * Peripheral reflex system trigger selection. Only applicable if @p prsEnable
<> 144:ef7eb2e8f9f7 960 * is enabled.
<> 144:ef7eb2e8f9f7 961 */
<> 144:ef7eb2e8f9f7 962 ADC_PRSSEL_TypeDef prsSel;
<> 144:ef7eb2e8f9f7 963
<> 144:ef7eb2e8f9f7 964 /** Acquisition time (in ADC clock cycles). */
<> 144:ef7eb2e8f9f7 965 ADC_AcqTime_TypeDef acqTime;
<> 144:ef7eb2e8f9f7 966
<> 144:ef7eb2e8f9f7 967 /**
<> 144:ef7eb2e8f9f7 968 * Sample reference selection. Notice that for external references, the
<> 144:ef7eb2e8f9f7 969 * ADC calibration register must be set explicitly.
<> 144:ef7eb2e8f9f7 970 */
<> 144:ef7eb2e8f9f7 971 ADC_Ref_TypeDef reference;
<> 144:ef7eb2e8f9f7 972
<> 144:ef7eb2e8f9f7 973 /** Sample resolution. */
<> 144:ef7eb2e8f9f7 974 ADC_Res_TypeDef resolution;
<> 144:ef7eb2e8f9f7 975
<> 144:ef7eb2e8f9f7 976 #if defined( _ADC_SINGLECTRL_INPUTSEL_MASK )
<> 144:ef7eb2e8f9f7 977 /**
<> 144:ef7eb2e8f9f7 978 * Sample input selection, use single ended or differential input according
<> 144:ef7eb2e8f9f7 979 * to setting of @p diff.
<> 144:ef7eb2e8f9f7 980 */
<> 144:ef7eb2e8f9f7 981 ADC_SingleInput_TypeDef input;
<> 144:ef7eb2e8f9f7 982 #endif
<> 144:ef7eb2e8f9f7 983
<> 144:ef7eb2e8f9f7 984 #if defined( _ADC_SINGLECTRL_POSSEL_MASK )
<> 144:ef7eb2e8f9f7 985 /** Select positive input for for single channel conversion mode. */
<> 144:ef7eb2e8f9f7 986 ADC_PosSel_TypeDef posSel;
<> 144:ef7eb2e8f9f7 987 #endif
<> 144:ef7eb2e8f9f7 988
<> 144:ef7eb2e8f9f7 989 #if defined( _ADC_SINGLECTRL_NEGSEL_MASK )
<> 144:ef7eb2e8f9f7 990 /** Select negative input for single channel conversion mode. Negative input is grounded
<> 144:ef7eb2e8f9f7 991 for single ended (non-differential) converison. */
<> 144:ef7eb2e8f9f7 992 ADC_NegSel_TypeDef negSel;
<> 144:ef7eb2e8f9f7 993 #endif
<> 144:ef7eb2e8f9f7 994
<> 144:ef7eb2e8f9f7 995 /** Select if single ended or differential input. */
<> 144:ef7eb2e8f9f7 996 bool diff;
<> 144:ef7eb2e8f9f7 997
<> 144:ef7eb2e8f9f7 998 /** Peripheral reflex system trigger enable. */
<> 144:ef7eb2e8f9f7 999 bool prsEnable;
<> 144:ef7eb2e8f9f7 1000
<> 144:ef7eb2e8f9f7 1001 /** Select if left adjustment should be done. */
<> 144:ef7eb2e8f9f7 1002 bool leftAdjust;
<> 144:ef7eb2e8f9f7 1003
<> 144:ef7eb2e8f9f7 1004 /** Select if continuous conversion until explicit stop. */
<> 144:ef7eb2e8f9f7 1005 bool rep;
<> 144:ef7eb2e8f9f7 1006
<> 144:ef7eb2e8f9f7 1007 #if defined( _ADC_CTRL_SINGLEDMAWU_MASK )
<> 144:ef7eb2e8f9f7 1008 /** When true, DMA is available in EM2 for single conversion */
<> 144:ef7eb2e8f9f7 1009 bool singleDmaEm2Wu;
<> 144:ef7eb2e8f9f7 1010 #endif
<> 144:ef7eb2e8f9f7 1011
<> 144:ef7eb2e8f9f7 1012 #if defined( _ADC_SINGLECTRLX_FIFOOFACT_MASK )
<> 144:ef7eb2e8f9f7 1013 /** When true, the FIFO overwrites old data when full. If false, then the FIFO discards new data.
<> 144:ef7eb2e8f9f7 1014 The SCANOF IRQ is triggered in both cases. */
<> 144:ef7eb2e8f9f7 1015 bool fifoOverwrite;
<> 144:ef7eb2e8f9f7 1016 #endif
<> 144:ef7eb2e8f9f7 1017 } ADC_InitSingle_TypeDef;
<> 144:ef7eb2e8f9f7 1018
<> 144:ef7eb2e8f9f7 1019 /** Default config for ADC single conversion init structure. */
<> 144:ef7eb2e8f9f7 1020 #if defined( _ADC_SINGLECTRL_INPUTSEL_MASK )
<> 144:ef7eb2e8f9f7 1021 #define ADC_INITSINGLE_DEFAULT \
<> 144:ef7eb2e8f9f7 1022 { \
<> 144:ef7eb2e8f9f7 1023 adcPRSSELCh0, /* PRS ch0 (if enabled). */ \
<> 144:ef7eb2e8f9f7 1024 adcAcqTime1, /* 1 ADC_CLK cycle acquisition time. */ \
<> 144:ef7eb2e8f9f7 1025 adcRef1V25, /* 1.25V internal reference. */ \
<> 144:ef7eb2e8f9f7 1026 adcRes12Bit, /* 12 bit resolution. */ \
<> 144:ef7eb2e8f9f7 1027 adcSingleInpCh0, /* CH0 input selected. */ \
<> 144:ef7eb2e8f9f7 1028 false, /* Single ended input. */ \
<> 144:ef7eb2e8f9f7 1029 false, /* PRS disabled. */ \
<> 144:ef7eb2e8f9f7 1030 false, /* Right adjust. */ \
<> 144:ef7eb2e8f9f7 1031 false /* Deactivate conversion after one scan sequence. */ \
<> 144:ef7eb2e8f9f7 1032 }
<> 144:ef7eb2e8f9f7 1033 #else
<> 144:ef7eb2e8f9f7 1034 #define ADC_INITSINGLE_DEFAULT \
<> 144:ef7eb2e8f9f7 1035 { \
<> 144:ef7eb2e8f9f7 1036 adcPRSSELCh0, /* PRS ch0 (if enabled). */ \
<> 144:ef7eb2e8f9f7 1037 adcAcqTime1, /* 1 ADC_CLK cycle acquisition time. */ \
<> 144:ef7eb2e8f9f7 1038 adcRef1V25, /* 1.25V internal reference. */ \
<> 144:ef7eb2e8f9f7 1039 adcRes12Bit, /* 12 bit resolution. */ \
<> 144:ef7eb2e8f9f7 1040 adcPosSelAPORT0XCH0, /* Select node BUS0XCH0 as posSel */ \
<> 144:ef7eb2e8f9f7 1041 adcNegSelAPORT0XCH1, /* Select node BUS0XCH1 as negSel */ \
<> 144:ef7eb2e8f9f7 1042 false, /* Single ended input. */ \
<> 144:ef7eb2e8f9f7 1043 false, /* PRS disabled. */ \
<> 144:ef7eb2e8f9f7 1044 false, /* Right adjust. */ \
<> 144:ef7eb2e8f9f7 1045 false, /* Deactivate conversion after one scan sequence. */ \
<> 144:ef7eb2e8f9f7 1046 false, /* No EM2 DMA wakeup from single FIFO DVL */ \
<> 144:ef7eb2e8f9f7 1047 false /* Discard new data on full FIFO. */ \
<> 144:ef7eb2e8f9f7 1048 }
<> 144:ef7eb2e8f9f7 1049 #endif
<> 144:ef7eb2e8f9f7 1050
<> 144:ef7eb2e8f9f7 1051 /*******************************************************************************
<> 144:ef7eb2e8f9f7 1052 ***************************** PROTOTYPES **********************************
<> 144:ef7eb2e8f9f7 1053 ******************************************************************************/
<> 144:ef7eb2e8f9f7 1054
<> 144:ef7eb2e8f9f7 1055 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 1056 * @brief
<> 144:ef7eb2e8f9f7 1057 * Get single conversion result.
<> 144:ef7eb2e8f9f7 1058 *
<> 144:ef7eb2e8f9f7 1059 * @note
<> 144:ef7eb2e8f9f7 1060 * Check data valid flag before calling this function.
<> 144:ef7eb2e8f9f7 1061 *
<> 144:ef7eb2e8f9f7 1062 * @param[in] adc
<> 144:ef7eb2e8f9f7 1063 * Pointer to ADC peripheral register block.
<> 144:ef7eb2e8f9f7 1064 *
<> 144:ef7eb2e8f9f7 1065 * @return
<> 144:ef7eb2e8f9f7 1066 * Single conversion data.
<> 144:ef7eb2e8f9f7 1067 ******************************************************************************/
<> 144:ef7eb2e8f9f7 1068 __STATIC_INLINE uint32_t ADC_DataSingleGet(ADC_TypeDef *adc)
<> 144:ef7eb2e8f9f7 1069 {
<> 144:ef7eb2e8f9f7 1070 return adc->SINGLEDATA;
<> 144:ef7eb2e8f9f7 1071 }
<> 144:ef7eb2e8f9f7 1072
<> 144:ef7eb2e8f9f7 1073
<> 144:ef7eb2e8f9f7 1074 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 1075 * @brief
<> 144:ef7eb2e8f9f7 1076 * Peek single conversion result.
<> 144:ef7eb2e8f9f7 1077 *
<> 144:ef7eb2e8f9f7 1078 * @note
<> 144:ef7eb2e8f9f7 1079 * Check data valid flag before calling this function.
<> 144:ef7eb2e8f9f7 1080 *
<> 144:ef7eb2e8f9f7 1081 * @param[in] adc
<> 144:ef7eb2e8f9f7 1082 * Pointer to ADC peripheral register block.
<> 144:ef7eb2e8f9f7 1083 *
<> 144:ef7eb2e8f9f7 1084 * @return
<> 144:ef7eb2e8f9f7 1085 * Single conversion data.
<> 144:ef7eb2e8f9f7 1086 ******************************************************************************/
<> 144:ef7eb2e8f9f7 1087 __STATIC_INLINE uint32_t ADC_DataSinglePeek(ADC_TypeDef *adc)
<> 144:ef7eb2e8f9f7 1088 {
<> 144:ef7eb2e8f9f7 1089 return adc->SINGLEDATAP;
<> 144:ef7eb2e8f9f7 1090 }
<> 144:ef7eb2e8f9f7 1091
<> 144:ef7eb2e8f9f7 1092
<> 144:ef7eb2e8f9f7 1093 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 1094 * @brief
<> 144:ef7eb2e8f9f7 1095 * Get scan result.
<> 144:ef7eb2e8f9f7 1096 *
<> 144:ef7eb2e8f9f7 1097 * @note
<> 144:ef7eb2e8f9f7 1098 * Check data valid flag before calling this function.
<> 144:ef7eb2e8f9f7 1099 *
<> 144:ef7eb2e8f9f7 1100 * @param[in] adc
<> 144:ef7eb2e8f9f7 1101 * Pointer to ADC peripheral register block.
<> 144:ef7eb2e8f9f7 1102 *
<> 144:ef7eb2e8f9f7 1103 * @return
<> 144:ef7eb2e8f9f7 1104 * Scan conversion data.
<> 144:ef7eb2e8f9f7 1105 ******************************************************************************/
<> 144:ef7eb2e8f9f7 1106 __STATIC_INLINE uint32_t ADC_DataScanGet(ADC_TypeDef *adc)
<> 144:ef7eb2e8f9f7 1107 {
<> 144:ef7eb2e8f9f7 1108 return adc->SCANDATA;
<> 144:ef7eb2e8f9f7 1109 }
<> 144:ef7eb2e8f9f7 1110
<> 144:ef7eb2e8f9f7 1111
<> 144:ef7eb2e8f9f7 1112 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 1113 * @brief
<> 144:ef7eb2e8f9f7 1114 * Peek scan result.
<> 144:ef7eb2e8f9f7 1115 *
<> 144:ef7eb2e8f9f7 1116 * @note
<> 144:ef7eb2e8f9f7 1117 * Check data valid flag before calling this function.
<> 144:ef7eb2e8f9f7 1118 *
<> 144:ef7eb2e8f9f7 1119 * @param[in] adc
<> 144:ef7eb2e8f9f7 1120 * Pointer to ADC peripheral register block.
<> 144:ef7eb2e8f9f7 1121 *
<> 144:ef7eb2e8f9f7 1122 * @return
<> 144:ef7eb2e8f9f7 1123 * Scan conversion data.
<> 144:ef7eb2e8f9f7 1124 ******************************************************************************/
<> 144:ef7eb2e8f9f7 1125 __STATIC_INLINE uint32_t ADC_DataScanPeek(ADC_TypeDef *adc)
<> 144:ef7eb2e8f9f7 1126 {
<> 144:ef7eb2e8f9f7 1127 return adc->SCANDATAP;
<> 144:ef7eb2e8f9f7 1128 }
<> 144:ef7eb2e8f9f7 1129
<> 144:ef7eb2e8f9f7 1130
<> 144:ef7eb2e8f9f7 1131 #if defined( _ADC_SCANDATAX_MASK )
<> 144:ef7eb2e8f9f7 1132 uint32_t ADC_DataIdScanGet(ADC_TypeDef *adc, uint32_t *scanId);
<> 144:ef7eb2e8f9f7 1133 #endif
<> 144:ef7eb2e8f9f7 1134
<> 144:ef7eb2e8f9f7 1135 void ADC_Init(ADC_TypeDef *adc, const ADC_Init_TypeDef *init);
<> 144:ef7eb2e8f9f7 1136 void ADC_Reset(ADC_TypeDef *adc);
<> 144:ef7eb2e8f9f7 1137 void ADC_InitScan(ADC_TypeDef *adc, const ADC_InitScan_TypeDef *init);
<> 144:ef7eb2e8f9f7 1138
<> 144:ef7eb2e8f9f7 1139 #if defined( _ADC_SCANINPUTSEL_MASK )
<> 144:ef7eb2e8f9f7 1140 void ADC_ScanInputClear(ADC_InitScan_TypeDef *scanInit);
<> 144:ef7eb2e8f9f7 1141 uint32_t ADC_ScanSingleEndedInputAdd(ADC_InitScan_TypeDef *scanInit,
<> 144:ef7eb2e8f9f7 1142 ADC_ScanInputGroup_TypeDef inputGroup,
<> 144:ef7eb2e8f9f7 1143 ADC_PosSel_TypeDef singleEndedSel);
<> 144:ef7eb2e8f9f7 1144 uint32_t ADC_ScanDifferentialInputAdd(ADC_InitScan_TypeDef *scanInit,
<> 144:ef7eb2e8f9f7 1145 ADC_ScanInputGroup_TypeDef inputGroup,
<> 144:ef7eb2e8f9f7 1146 ADC_PosSel_TypeDef posSel,
<> 144:ef7eb2e8f9f7 1147 ADC_ScanNegInput_TypeDef adcScanNegInput);
<> 144:ef7eb2e8f9f7 1148 #endif
<> 144:ef7eb2e8f9f7 1149
<> 144:ef7eb2e8f9f7 1150 void ADC_InitSingle(ADC_TypeDef *adc, const ADC_InitSingle_TypeDef *init);
<> 144:ef7eb2e8f9f7 1151 uint8_t ADC_TimebaseCalc(uint32_t hfperFreq);
<> 144:ef7eb2e8f9f7 1152 uint8_t ADC_PrescaleCalc(uint32_t adcFreq, uint32_t hfperFreq);
<> 144:ef7eb2e8f9f7 1153
<> 144:ef7eb2e8f9f7 1154
<> 144:ef7eb2e8f9f7 1155 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 1156 * @brief
<> 144:ef7eb2e8f9f7 1157 * Clear one or more pending ADC interrupts.
<> 144:ef7eb2e8f9f7 1158 *
<> 144:ef7eb2e8f9f7 1159 * @param[in] adc
<> 144:ef7eb2e8f9f7 1160 * Pointer to ADC peripheral register block.
<> 144:ef7eb2e8f9f7 1161 *
<> 144:ef7eb2e8f9f7 1162 * @param[in] flags
<> 144:ef7eb2e8f9f7 1163 * Pending ADC interrupt source to clear. Use a bitwise logic OR combination
<> 144:ef7eb2e8f9f7 1164 * of valid interrupt flags for the ADC module (ADC_IF_nnn).
<> 144:ef7eb2e8f9f7 1165 ******************************************************************************/
<> 144:ef7eb2e8f9f7 1166 __STATIC_INLINE void ADC_IntClear(ADC_TypeDef *adc, uint32_t flags)
<> 144:ef7eb2e8f9f7 1167 {
<> 144:ef7eb2e8f9f7 1168 adc->IFC = flags;
<> 144:ef7eb2e8f9f7 1169 }
<> 144:ef7eb2e8f9f7 1170
<> 144:ef7eb2e8f9f7 1171
<> 144:ef7eb2e8f9f7 1172 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 1173 * @brief
<> 144:ef7eb2e8f9f7 1174 * Disable one or more ADC interrupts.
<> 144:ef7eb2e8f9f7 1175 *
<> 144:ef7eb2e8f9f7 1176 * @param[in] adc
<> 144:ef7eb2e8f9f7 1177 * Pointer to ADC peripheral register block.
<> 144:ef7eb2e8f9f7 1178 *
<> 144:ef7eb2e8f9f7 1179 * @param[in] flags
<> 144:ef7eb2e8f9f7 1180 * ADC interrupt sources to disable. Use a bitwise logic OR combination of
<> 144:ef7eb2e8f9f7 1181 * valid interrupt flags for the ADC module (ADC_IF_nnn).
<> 144:ef7eb2e8f9f7 1182 ******************************************************************************/
<> 144:ef7eb2e8f9f7 1183 __STATIC_INLINE void ADC_IntDisable(ADC_TypeDef *adc, uint32_t flags)
<> 144:ef7eb2e8f9f7 1184 {
<> 144:ef7eb2e8f9f7 1185 adc->IEN &= ~flags;
<> 144:ef7eb2e8f9f7 1186 }
<> 144:ef7eb2e8f9f7 1187
<> 144:ef7eb2e8f9f7 1188
<> 144:ef7eb2e8f9f7 1189 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 1190 * @brief
<> 144:ef7eb2e8f9f7 1191 * Enable one or more ADC interrupts.
<> 144:ef7eb2e8f9f7 1192 *
<> 144:ef7eb2e8f9f7 1193 * @note
<> 144:ef7eb2e8f9f7 1194 * Depending on the use, a pending interrupt may already be set prior to
<> 144:ef7eb2e8f9f7 1195 * enabling the interrupt. Consider using ADC_IntClear() prior to enabling
<> 144:ef7eb2e8f9f7 1196 * if such a pending interrupt should be ignored.
<> 144:ef7eb2e8f9f7 1197 *
<> 144:ef7eb2e8f9f7 1198 * @param[in] adc
<> 144:ef7eb2e8f9f7 1199 * Pointer to ADC peripheral register block.
<> 144:ef7eb2e8f9f7 1200 *
<> 144:ef7eb2e8f9f7 1201 * @param[in] flags
<> 144:ef7eb2e8f9f7 1202 * ADC interrupt sources to enable. Use a bitwise logic OR combination of
<> 144:ef7eb2e8f9f7 1203 * valid interrupt flags for the ADC module (ADC_IF_nnn).
<> 144:ef7eb2e8f9f7 1204 ******************************************************************************/
<> 144:ef7eb2e8f9f7 1205 __STATIC_INLINE void ADC_IntEnable(ADC_TypeDef *adc, uint32_t flags)
<> 144:ef7eb2e8f9f7 1206 {
<> 144:ef7eb2e8f9f7 1207 adc->IEN |= flags;
<> 144:ef7eb2e8f9f7 1208 }
<> 144:ef7eb2e8f9f7 1209
<> 144:ef7eb2e8f9f7 1210
<> 144:ef7eb2e8f9f7 1211 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 1212 * @brief
<> 144:ef7eb2e8f9f7 1213 * Get pending ADC interrupt flags.
<> 144:ef7eb2e8f9f7 1214 *
<> 144:ef7eb2e8f9f7 1215 * @note
<> 144:ef7eb2e8f9f7 1216 * The event bits are not cleared by the use of this function.
<> 144:ef7eb2e8f9f7 1217 *
<> 144:ef7eb2e8f9f7 1218 * @param[in] adc
<> 144:ef7eb2e8f9f7 1219 * Pointer to ADC peripheral register block.
<> 144:ef7eb2e8f9f7 1220 *
<> 144:ef7eb2e8f9f7 1221 * @return
<> 144:ef7eb2e8f9f7 1222 * ADC interrupt sources pending. A bitwise logic OR combination of valid
<> 144:ef7eb2e8f9f7 1223 * interrupt flags for the ADC module (ADC_IF_nnn).
<> 144:ef7eb2e8f9f7 1224 ******************************************************************************/
<> 144:ef7eb2e8f9f7 1225 __STATIC_INLINE uint32_t ADC_IntGet(ADC_TypeDef *adc)
<> 144:ef7eb2e8f9f7 1226 {
<> 144:ef7eb2e8f9f7 1227 return adc->IF;
<> 144:ef7eb2e8f9f7 1228 }
<> 144:ef7eb2e8f9f7 1229
<> 144:ef7eb2e8f9f7 1230
<> 144:ef7eb2e8f9f7 1231 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 1232 * @brief
<> 144:ef7eb2e8f9f7 1233 * Get enabled and pending ADC interrupt flags.
<> 144:ef7eb2e8f9f7 1234 * Useful for handling more interrupt sources in the same interrupt handler.
<> 144:ef7eb2e8f9f7 1235 *
<> 144:ef7eb2e8f9f7 1236 * @param[in] adc
<> 144:ef7eb2e8f9f7 1237 * Pointer to ADC peripheral register block.
<> 144:ef7eb2e8f9f7 1238 *
<> 144:ef7eb2e8f9f7 1239 * @note
<> 144:ef7eb2e8f9f7 1240 * Interrupt flags are not cleared by the use of this function.
<> 144:ef7eb2e8f9f7 1241 *
<> 144:ef7eb2e8f9f7 1242 * @return
<> 144:ef7eb2e8f9f7 1243 * Pending and enabled ADC interrupt sources.
<> 144:ef7eb2e8f9f7 1244 * The return value is the bitwise AND combination of
<> 144:ef7eb2e8f9f7 1245 * - the OR combination of enabled interrupt sources in ADCx_IEN_nnn
<> 144:ef7eb2e8f9f7 1246 * register (ADCx_IEN_nnn) and
<> 144:ef7eb2e8f9f7 1247 * - the OR combination of valid interrupt flags of the ADC module
<> 144:ef7eb2e8f9f7 1248 * (ADCx_IF_nnn).
<> 144:ef7eb2e8f9f7 1249 ******************************************************************************/
<> 144:ef7eb2e8f9f7 1250 __STATIC_INLINE uint32_t ADC_IntGetEnabled(ADC_TypeDef *adc)
<> 144:ef7eb2e8f9f7 1251 {
<> 144:ef7eb2e8f9f7 1252 uint32_t ien;
<> 144:ef7eb2e8f9f7 1253
<> 144:ef7eb2e8f9f7 1254 /* Store ADCx->IEN in temporary variable in order to define explicit order
<> 144:ef7eb2e8f9f7 1255 * of volatile accesses. */
<> 144:ef7eb2e8f9f7 1256 ien = adc->IEN;
<> 144:ef7eb2e8f9f7 1257
<> 144:ef7eb2e8f9f7 1258 /* Bitwise AND of pending and enabled interrupts */
<> 144:ef7eb2e8f9f7 1259 return adc->IF & ien;
<> 144:ef7eb2e8f9f7 1260 }
<> 144:ef7eb2e8f9f7 1261
<> 144:ef7eb2e8f9f7 1262
<> 144:ef7eb2e8f9f7 1263 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 1264 * @brief
<> 144:ef7eb2e8f9f7 1265 * Set one or more pending ADC interrupts from SW.
<> 144:ef7eb2e8f9f7 1266 *
<> 144:ef7eb2e8f9f7 1267 * @param[in] adc
<> 144:ef7eb2e8f9f7 1268 * Pointer to ADC peripheral register block.
<> 144:ef7eb2e8f9f7 1269 *
<> 144:ef7eb2e8f9f7 1270 * @param[in] flags
<> 144:ef7eb2e8f9f7 1271 * ADC interrupt sources to set to pending. Use a bitwise logic OR combination
<> 144:ef7eb2e8f9f7 1272 * of valid interrupt flags for the ADC module (ADC_IF_nnn).
<> 144:ef7eb2e8f9f7 1273 ******************************************************************************/
<> 144:ef7eb2e8f9f7 1274 __STATIC_INLINE void ADC_IntSet(ADC_TypeDef *adc, uint32_t flags)
<> 144:ef7eb2e8f9f7 1275 {
<> 144:ef7eb2e8f9f7 1276 adc->IFS = flags;
<> 144:ef7eb2e8f9f7 1277 }
<> 144:ef7eb2e8f9f7 1278
<> 144:ef7eb2e8f9f7 1279
<> 144:ef7eb2e8f9f7 1280 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 1281 * @brief
<> 144:ef7eb2e8f9f7 1282 * Start scan sequence and/or single conversion.
<> 144:ef7eb2e8f9f7 1283 *
<> 144:ef7eb2e8f9f7 1284 * @param[in] adc
<> 144:ef7eb2e8f9f7 1285 * Pointer to ADC peripheral register block.
<> 144:ef7eb2e8f9f7 1286 *
<> 144:ef7eb2e8f9f7 1287 * @param[in] cmd
<> 144:ef7eb2e8f9f7 1288 * Command indicating which type of sampling to start.
<> 144:ef7eb2e8f9f7 1289 ******************************************************************************/
<> 144:ef7eb2e8f9f7 1290 __STATIC_INLINE void ADC_Start(ADC_TypeDef *adc, ADC_Start_TypeDef cmd)
<> 144:ef7eb2e8f9f7 1291 {
<> 144:ef7eb2e8f9f7 1292 adc->CMD = (uint32_t)cmd;
<> 144:ef7eb2e8f9f7 1293 }
<> 144:ef7eb2e8f9f7 1294
<> 144:ef7eb2e8f9f7 1295
<> 144:ef7eb2e8f9f7 1296 /** @} (end addtogroup ADC) */
<> 144:ef7eb2e8f9f7 1297 /** @} (end addtogroup EM_Library) */
<> 144:ef7eb2e8f9f7 1298
<> 144:ef7eb2e8f9f7 1299 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 1300 }
<> 144:ef7eb2e8f9f7 1301 #endif
<> 144:ef7eb2e8f9f7 1302
<> 144:ef7eb2e8f9f7 1303 #endif /* defined(ADC_COUNT) && (ADC_COUNT > 0) */
<> 144:ef7eb2e8f9f7 1304 #endif /* __SILICON_LABS_EM_ADC_H__ */