wm8994.c

00001 /**
00002   ******************************************************************************
00003   * @file    wm8994.c
00004   * @author  MCD Application Team
00005   * @version V2.1.0
00006   * @date    22-February-2016
00007   * @brief   This file provides the WM8994 Audio Codec driver.   
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037 
00038 /* Includes ------------------------------------------------------------------*/
00039 #include "wm8994.h"
00040 
00041 /** @addtogroup BSP
00042   * @{
00043   */
00044   
00045 /** @addtogroup Components
00046   * @{
00047   */ 
00048 
00049 /** @addtogroup wm8994
00050   * @brief     This file provides a set of functions needed to drive the 
00051   *            WM8994 audio codec.
00052   * @{
00053   */
00054 
00055 /** @defgroup WM8994_Private_Types
00056   * @{
00057   */
00058 
00059 /**
00060   * @}
00061   */ 
00062   
00063 /** @defgroup WM8994_Private_Defines
00064   * @{
00065   */
00066 /* Uncomment this line to enable verifying data sent to codec after each write 
00067    operation (for debug purpose) */
00068 #if !defined (VERIFY_WRITTENDATA)  
00069 /*#define VERIFY_WRITTENDATA*/
00070 #endif /* VERIFY_WRITTENDATA */
00071 /**
00072   * @}
00073   */ 
00074 
00075 /** @defgroup WM8994_Private_Macros
00076   * @{
00077   */
00078 
00079 /**
00080   * @}
00081   */ 
00082   
00083 /** @defgroup WM8994_Private_Variables
00084   * @{
00085   */
00086 
00087 /* Audio codec driver structure initialization */  
00088 AUDIO_DrvTypeDef wm8994_drv = 
00089 {
00090   wm8994_Init,
00091   wm8994_DeInit,
00092   wm8994_ReadID,
00093 
00094   wm8994_Play,
00095   wm8994_Pause,
00096   wm8994_Resume,
00097   wm8994_Stop,  
00098 
00099   wm8994_SetFrequency,
00100   wm8994_SetVolume,
00101   wm8994_SetMute,  
00102   wm8994_SetOutputMode,
00103 
00104   wm8994_Reset
00105 };
00106 
00107 static uint32_t outputEnabled = 0;
00108 static uint32_t inputEnabled = 0;
00109 /**
00110   * @}
00111   */ 
00112 
00113 /** @defgroup WM8994_Function_Prototypes
00114   * @{
00115   */
00116 static uint8_t CODEC_IO_Write(uint8_t Addr, uint16_t Reg, uint16_t Value);
00117 /**
00118   * @}
00119   */ 
00120 
00121 /** @defgroup WM8994_Private_Functions
00122   * @{
00123   */ 
00124 
00125 /**
00126   * @brief Initializes the audio codec and the control interface.
00127   * @param DeviceAddr: Device address on communication Bus.   
00128   * @param OutputInputDevice: can be OUTPUT_DEVICE_SPEAKER, OUTPUT_DEVICE_HEADPHONE,
00129   *  OUTPUT_DEVICE_BOTH, OUTPUT_DEVICE_AUTO, INPUT_DEVICE_DIGITAL_MICROPHONE_1,
00130   *  INPUT_DEVICE_DIGITAL_MICROPHONE_2, INPUT_DEVICE_DIGITAL_MIC1_MIC2, 
00131   *  INPUT_DEVICE_INPUT_LINE_1 or INPUT_DEVICE_INPUT_LINE_2.
00132   * @param Volume: Initial volume level (from 0 (Mute) to 100 (Max))
00133   * @param AudioFreq: Audio Frequency 
00134   * @retval 0 if correct communication, else wrong communication
00135   */
00136 uint32_t wm8994_Init(uint16_t DeviceAddr, uint16_t OutputInputDevice, uint8_t Volume, uint32_t AudioFreq)
00137 {
00138   uint32_t counter = 0;
00139   uint16_t output_device = OutputInputDevice & 0xFF;
00140   uint16_t input_device = OutputInputDevice & 0xFF00;
00141   uint16_t power_mgnt_reg_1 = 0;
00142   
00143   /* Initialize the Control interface of the Audio Codec */
00144   AUDIO_IO_Init();
00145   /* wm8994 Errata Work-Arounds */
00146   counter += CODEC_IO_Write(DeviceAddr, 0x102, 0x0003);
00147   counter += CODEC_IO_Write(DeviceAddr, 0x817, 0x0000);
00148   counter += CODEC_IO_Write(DeviceAddr, 0x102, 0x0000);
00149   
00150   /* Enable VMID soft start (fast), Start-up Bias Current Enabled */
00151   counter += CODEC_IO_Write(DeviceAddr, 0x39, 0x006C);
00152   
00153     /* Enable bias generator, Enable VMID */
00154   if (input_device > 0)
00155   {
00156     counter += CODEC_IO_Write(DeviceAddr, 0x01, 0x0013);
00157   }
00158   else
00159   {
00160     counter += CODEC_IO_Write(DeviceAddr, 0x01, 0x0003);
00161   }
00162 
00163   /* Add Delay */
00164   AUDIO_IO_Delay(50);
00165 
00166   /* Path Configurations for output */
00167   if (output_device > 0)
00168   {
00169     outputEnabled = 1;
00170     switch (output_device)
00171     {
00172     case OUTPUT_DEVICE_SPEAKER:
00173       /* Enable DAC1 (Left), Enable DAC1 (Right),
00174       Disable DAC2 (Left), Disable DAC2 (Right)*/
00175       counter += CODEC_IO_Write(DeviceAddr, 0x05, 0x0C0C);
00176 
00177       /* Enable the AIF1 Timeslot 0 (Left) to DAC 1 (Left) mixer path */
00178       counter += CODEC_IO_Write(DeviceAddr, 0x601, 0x0000);
00179 
00180       /* Enable the AIF1 Timeslot 0 (Right) to DAC 1 (Right) mixer path */
00181       counter += CODEC_IO_Write(DeviceAddr, 0x602, 0x0000);
00182 
00183       /* Disable the AIF1 Timeslot 1 (Left) to DAC 2 (Left) mixer path */
00184       counter += CODEC_IO_Write(DeviceAddr, 0x604, 0x0002);
00185 
00186       /* Disable the AIF1 Timeslot 1 (Right) to DAC 2 (Right) mixer path */
00187       counter += CODEC_IO_Write(DeviceAddr, 0x605, 0x0002);
00188       break;
00189 
00190     case OUTPUT_DEVICE_HEADPHONE:
00191       /* Disable DAC1 (Left), Disable DAC1 (Right),
00192       Enable DAC2 (Left), Enable DAC2 (Right)*/
00193       counter += CODEC_IO_Write(DeviceAddr, 0x05, 0x0303);
00194 
00195       /* Enable the AIF1 Timeslot 0 (Left) to DAC 1 (Left) mixer path */
00196       counter += CODEC_IO_Write(DeviceAddr, 0x601, 0x0001);
00197 
00198       /* Enable the AIF1 Timeslot 0 (Right) to DAC 1 (Right) mixer path */
00199       counter += CODEC_IO_Write(DeviceAddr, 0x602, 0x0001);
00200 
00201       /* Disable the AIF1 Timeslot 1 (Left) to DAC 2 (Left) mixer path */
00202       counter += CODEC_IO_Write(DeviceAddr, 0x604, 0x0000);
00203 
00204       /* Disable the AIF1 Timeslot 1 (Right) to DAC 2 (Right) mixer path */
00205       counter += CODEC_IO_Write(DeviceAddr, 0x605, 0x0000);
00206       break;
00207 
00208     case OUTPUT_DEVICE_BOTH:
00209       if (input_device == INPUT_DEVICE_DIGITAL_MIC1_MIC2)
00210       {
00211         /* Enable DAC1 (Left), Enable DAC1 (Right),
00212         also Enable DAC2 (Left), Enable DAC2 (Right)*/
00213         counter += CODEC_IO_Write(DeviceAddr, 0x05, 0x0303 | 0x0C0C);
00214         
00215         /* Enable the AIF1 Timeslot 0 (Left) to DAC 1 (Left) mixer path
00216         Enable the AIF1 Timeslot 1 (Left) to DAC 1 (Left) mixer path */
00217         counter += CODEC_IO_Write(DeviceAddr, 0x601, 0x0003);
00218         
00219         /* Enable the AIF1 Timeslot 0 (Right) to DAC 1 (Right) mixer path
00220         Enable the AIF1 Timeslot 1 (Right) to DAC 1 (Right) mixer path */
00221         counter += CODEC_IO_Write(DeviceAddr, 0x602, 0x0003);
00222         
00223         /* Enable the AIF1 Timeslot 0 (Left) to DAC 2 (Left) mixer path
00224         Enable the AIF1 Timeslot 1 (Left) to DAC 2 (Left) mixer path  */
00225         counter += CODEC_IO_Write(DeviceAddr, 0x604, 0x0003);
00226         
00227         /* Enable the AIF1 Timeslot 0 (Right) to DAC 2 (Right) mixer path
00228         Enable the AIF1 Timeslot 1 (Right) to DAC 2 (Right) mixer path */
00229         counter += CODEC_IO_Write(DeviceAddr, 0x605, 0x0003);
00230       }
00231       else
00232       {
00233         /* Enable DAC1 (Left), Enable DAC1 (Right),
00234         also Enable DAC2 (Left), Enable DAC2 (Right)*/
00235         counter += CODEC_IO_Write(DeviceAddr, 0x05, 0x0303 | 0x0C0C);
00236         
00237         /* Enable the AIF1 Timeslot 0 (Left) to DAC 1 (Left) mixer path */
00238         counter += CODEC_IO_Write(DeviceAddr, 0x601, 0x0001);
00239         
00240         /* Enable the AIF1 Timeslot 0 (Right) to DAC 1 (Right) mixer path */
00241         counter += CODEC_IO_Write(DeviceAddr, 0x602, 0x0001);
00242         
00243         /* Enable the AIF1 Timeslot 1 (Left) to DAC 2 (Left) mixer path */
00244         counter += CODEC_IO_Write(DeviceAddr, 0x604, 0x0002);
00245         
00246         /* Enable the AIF1 Timeslot 1 (Right) to DAC 2 (Right) mixer path */
00247         counter += CODEC_IO_Write(DeviceAddr, 0x605, 0x0002);      
00248       }
00249       break;
00250 
00251     case OUTPUT_DEVICE_AUTO :
00252     default:
00253       /* Disable DAC1 (Left), Disable DAC1 (Right),
00254       Enable DAC2 (Left), Enable DAC2 (Right)*/
00255       counter += CODEC_IO_Write(DeviceAddr, 0x05, 0x0303);
00256 
00257       /* Enable the AIF1 Timeslot 0 (Left) to DAC 1 (Left) mixer path */
00258       counter += CODEC_IO_Write(DeviceAddr, 0x601, 0x0001);
00259 
00260       /* Enable the AIF1 Timeslot 0 (Right) to DAC 1 (Right) mixer path */
00261       counter += CODEC_IO_Write(DeviceAddr, 0x602, 0x0001);
00262 
00263       /* Disable the AIF1 Timeslot 1 (Left) to DAC 2 (Left) mixer path */
00264       counter += CODEC_IO_Write(DeviceAddr, 0x604, 0x0000);
00265 
00266       /* Disable the AIF1 Timeslot 1 (Right) to DAC 2 (Right) mixer path */
00267       counter += CODEC_IO_Write(DeviceAddr, 0x605, 0x0000);
00268       break;
00269     }
00270   }
00271   else
00272   {
00273     outputEnabled = 0;
00274   }
00275 
00276   /* Path Configurations for input */
00277   if (input_device > 0)
00278   {
00279     inputEnabled = 1;
00280     switch (input_device)
00281     {
00282     case INPUT_DEVICE_DIGITAL_MICROPHONE_2 :
00283       /* Enable AIF1ADC2 (Left), Enable AIF1ADC2 (Right)
00284        * Enable DMICDAT2 (Left), Enable DMICDAT2 (Right)
00285        * Enable Left ADC, Enable Right ADC */
00286       counter += CODEC_IO_Write(DeviceAddr, 0x04, 0x0C30);
00287 
00288       /* Enable AIF1 DRC2 Signal Detect & DRC in AIF1ADC2 Left/Right Timeslot 1 */
00289       counter += CODEC_IO_Write(DeviceAddr, 0x450, 0x00DB);
00290 
00291       /* Disable IN1L, IN1R, IN2L, IN2R, Enable Thermal sensor & shutdown */
00292       counter += CODEC_IO_Write(DeviceAddr, 0x02, 0x6000);
00293 
00294       /* Enable the DMIC2(Left) to AIF1 Timeslot 1 (Left) mixer path */
00295       counter += CODEC_IO_Write(DeviceAddr, 0x608, 0x0002);
00296 
00297       /* Enable the DMIC2(Right) to AIF1 Timeslot 1 (Right) mixer path */
00298       counter += CODEC_IO_Write(DeviceAddr, 0x609, 0x0002);
00299 
00300       /* GPIO1 pin configuration GP1_DIR = output, GP1_FN = AIF1 DRC2 signal detect */
00301       counter += CODEC_IO_Write(DeviceAddr, 0x700, 0x000E);
00302       break;
00303 
00304     case INPUT_DEVICE_INPUT_LINE_1 :
00305       /* IN1LN_TO_IN1L, IN1LP_TO_VMID, IN1RN_TO_IN1R, IN1RP_TO_VMID */
00306       counter += CODEC_IO_Write(DeviceAddr, 0x28, 0x0011);
00307 
00308       /* Disable mute on IN1L_TO_MIXINL and +30dB on IN1L PGA output */
00309       counter += CODEC_IO_Write(DeviceAddr, 0x29, 0x0035);
00310 
00311       /* Disable mute on IN1R_TO_MIXINL, Gain = +30dB */
00312       counter += CODEC_IO_Write(DeviceAddr, 0x2A, 0x0035);
00313 
00314       /* Enable AIF1ADC1 (Left), Enable AIF1ADC1 (Right)
00315        * Enable Left ADC, Enable Right ADC */
00316       counter += CODEC_IO_Write(DeviceAddr, 0x04, 0x0303);
00317 
00318       /* Enable AIF1 DRC1 Signal Detect & DRC in AIF1ADC1 Left/Right Timeslot 0 */
00319       counter += CODEC_IO_Write(DeviceAddr, 0x440, 0x00DB);
00320 
00321       /* Enable IN1L and IN1R, Disable IN2L and IN2R, Enable Thermal sensor & shutdown */
00322       counter += CODEC_IO_Write(DeviceAddr, 0x02, 0x6350);
00323 
00324       /* Enable the ADCL(Left) to AIF1 Timeslot 0 (Left) mixer path */
00325       counter += CODEC_IO_Write(DeviceAddr, 0x606, 0x0002);
00326 
00327       /* Enable the ADCR(Right) to AIF1 Timeslot 0 (Right) mixer path */
00328       counter += CODEC_IO_Write(DeviceAddr, 0x607, 0x0002);
00329 
00330       /* GPIO1 pin configuration GP1_DIR = output, GP1_FN = AIF1 DRC1 signal detect */
00331       counter += CODEC_IO_Write(DeviceAddr, 0x700, 0x000D);
00332       break;
00333 
00334     case INPUT_DEVICE_DIGITAL_MICROPHONE_1 :
00335       /* Enable AIF1ADC1 (Left), Enable AIF1ADC1 (Right)
00336        * Enable DMICDAT1 (Left), Enable DMICDAT1 (Right)
00337        * Enable Left ADC, Enable Right ADC */
00338       counter += CODEC_IO_Write(DeviceAddr, 0x04, 0x030C);
00339 
00340       /* Enable AIF1 DRC2 Signal Detect & DRC in AIF1ADC1 Left/Right Timeslot 0 */
00341       counter += CODEC_IO_Write(DeviceAddr, 0x440, 0x00DB);
00342 
00343       /* Disable IN1L, IN1R, IN2L, IN2R, Enable Thermal sensor & shutdown */
00344       counter += CODEC_IO_Write(DeviceAddr, 0x02, 0x6350);
00345 
00346       /* Enable the DMIC2(Left) to AIF1 Timeslot 0 (Left) mixer path */
00347       counter += CODEC_IO_Write(DeviceAddr, 0x606, 0x0002);
00348 
00349       /* Enable the DMIC2(Right) to AIF1 Timeslot 0 (Right) mixer path */
00350       counter += CODEC_IO_Write(DeviceAddr, 0x607, 0x0002);
00351 
00352       /* GPIO1 pin configuration GP1_DIR = output, GP1_FN = AIF1 DRC1 signal detect */
00353       counter += CODEC_IO_Write(DeviceAddr, 0x700, 0x000D);
00354       break; 
00355     case INPUT_DEVICE_DIGITAL_MIC1_MIC2 :
00356       /* Enable AIF1ADC1 (Left), Enable AIF1ADC1 (Right)
00357        * Enable DMICDAT1 (Left), Enable DMICDAT1 (Right)
00358        * Enable Left ADC, Enable Right ADC */
00359       counter += CODEC_IO_Write(DeviceAddr, 0x04, 0x0F3C);
00360 
00361       /* Enable AIF1 DRC2 Signal Detect & DRC in AIF1ADC2 Left/Right Timeslot 1 */
00362       counter += CODEC_IO_Write(DeviceAddr, 0x450, 0x00DB);
00363       
00364       /* Enable AIF1 DRC2 Signal Detect & DRC in AIF1ADC1 Left/Right Timeslot 0 */
00365       counter += CODEC_IO_Write(DeviceAddr, 0x440, 0x00DB);
00366 
00367       /* Disable IN1L, IN1R, Enable IN2L, IN2R, Thermal sensor & shutdown */
00368       counter += CODEC_IO_Write(DeviceAddr, 0x02, 0x63A0);
00369 
00370       /* Enable the DMIC2(Left) to AIF1 Timeslot 0 (Left) mixer path */
00371       counter += CODEC_IO_Write(DeviceAddr, 0x606, 0x0002);
00372 
00373       /* Enable the DMIC2(Right) to AIF1 Timeslot 0 (Right) mixer path */
00374       counter += CODEC_IO_Write(DeviceAddr, 0x607, 0x0002);
00375 
00376       /* Enable the DMIC2(Left) to AIF1 Timeslot 1 (Left) mixer path */
00377       counter += CODEC_IO_Write(DeviceAddr, 0x608, 0x0002);
00378 
00379       /* Enable the DMIC2(Right) to AIF1 Timeslot 1 (Right) mixer path */
00380       counter += CODEC_IO_Write(DeviceAddr, 0x609, 0x0002);
00381       
00382       /* GPIO1 pin configuration GP1_DIR = output, GP1_FN = AIF1 DRC1 signal detect */
00383       counter += CODEC_IO_Write(DeviceAddr, 0x700, 0x000D);
00384       break;    
00385     case INPUT_DEVICE_INPUT_LINE_2 :
00386     default:
00387       /* Actually, no other input devices supported */
00388       counter++;
00389       break;
00390     }
00391   }
00392   else
00393   {
00394     inputEnabled = 0;
00395   }
00396   
00397   /*  Clock Configurations */
00398   switch (AudioFreq)
00399   {
00400   case  AUDIO_FREQUENCY_8K:
00401     /* AIF1 Sample Rate = 8 (KHz), ratio=256 */ 
00402     counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0003);
00403     break;
00404     
00405   case  AUDIO_FREQUENCY_16K:
00406     /* AIF1 Sample Rate = 16 (KHz), ratio=256 */ 
00407     counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0033);
00408     break;
00409 
00410   case  AUDIO_FREQUENCY_32K:
00411     /* AIF1 Sample Rate = 32 (KHz), ratio=256 */ 
00412     counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0063);
00413     break;
00414     
00415   case  AUDIO_FREQUENCY_48K:
00416     /* AIF1 Sample Rate = 48 (KHz), ratio=256 */ 
00417     counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0083);
00418     break;
00419     
00420   case  AUDIO_FREQUENCY_96K:
00421     /* AIF1 Sample Rate = 96 (KHz), ratio=256 */ 
00422     counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x00A3);
00423     break;
00424     
00425   case  AUDIO_FREQUENCY_11K:
00426     /* AIF1 Sample Rate = 11.025 (KHz), ratio=256 */ 
00427     counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0013);
00428     break;
00429     
00430   case  AUDIO_FREQUENCY_22K:
00431     /* AIF1 Sample Rate = 22.050 (KHz), ratio=256 */ 
00432     counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0043);
00433     break;
00434     
00435   case  AUDIO_FREQUENCY_44K:
00436     /* AIF1 Sample Rate = 44.1 (KHz), ratio=256 */ 
00437     counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0073);
00438     break; 
00439     
00440   default:
00441     /* AIF1 Sample Rate = 48 (KHz), ratio=256 */ 
00442     counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0083);
00443     break; 
00444   }
00445 
00446   if(input_device == INPUT_DEVICE_DIGITAL_MIC1_MIC2)
00447   {
00448   /* AIF1 Word Length = 16-bits, AIF1 Format = DSP mode */
00449   counter += CODEC_IO_Write(DeviceAddr, 0x300, 0x4018);    
00450   }
00451   else
00452   {
00453   /* AIF1 Word Length = 16-bits, AIF1 Format = I2S (Default Register Value) */
00454   counter += CODEC_IO_Write(DeviceAddr, 0x300, 0x4010);
00455   }
00456   
00457   /* slave mode */
00458   counter += CODEC_IO_Write(DeviceAddr, 0x302, 0x0000);
00459   
00460   /* Enable the DSP processing clock for AIF1, Enable the core clock */
00461   counter += CODEC_IO_Write(DeviceAddr, 0x208, 0x000A);
00462   
00463   /* Enable AIF1 Clock, AIF1 Clock Source = MCLK1 pin */
00464   counter += CODEC_IO_Write(DeviceAddr, 0x200, 0x0001);
00465 
00466   if (output_device > 0)  /* Audio output selected */
00467   {
00468     /* Analog Output Configuration */
00469 
00470     /* Enable SPKRVOL PGA, Enable SPKMIXR, Enable SPKLVOL PGA, Enable SPKMIXL */
00471     counter += CODEC_IO_Write(DeviceAddr, 0x03, 0x0300);
00472 
00473     /* Left Speaker Mixer Volume = 0dB */
00474     counter += CODEC_IO_Write(DeviceAddr, 0x22, 0x0000);
00475 
00476     /* Speaker output mode = Class D, Right Speaker Mixer Volume = 0dB ((0x23, 0x0100) = class AB)*/
00477     counter += CODEC_IO_Write(DeviceAddr, 0x23, 0x0000);
00478 
00479     /* Unmute DAC2 (Left) to Left Speaker Mixer (SPKMIXL) path,
00480     Unmute DAC2 (Right) to Right Speaker Mixer (SPKMIXR) path */
00481     counter += CODEC_IO_Write(DeviceAddr, 0x36, 0x0300);
00482 
00483     /* Enable bias generator, Enable VMID, Enable SPKOUTL, Enable SPKOUTR */
00484     counter += CODEC_IO_Write(DeviceAddr, 0x01, 0x3003);
00485 
00486     /* Headphone/Speaker Enable */
00487 
00488     if (input_device == INPUT_DEVICE_DIGITAL_MIC1_MIC2)
00489     {
00490     /* Enable Class W, Class W Envelope Tracking = AIF1 Timeslots 0 and 1 */
00491     counter += CODEC_IO_Write(DeviceAddr, 0x51, 0x0205);
00492     }
00493     else
00494     {
00495     /* Enable Class W, Class W Envelope Tracking = AIF1 Timeslot 0 */
00496     counter += CODEC_IO_Write(DeviceAddr, 0x51, 0x0005);      
00497     }
00498 
00499     /* Enable bias generator, Enable VMID, Enable HPOUT1 (Left) and Enable HPOUT1 (Right) input stages */
00500     /* idem for Speaker */
00501     power_mgnt_reg_1 |= 0x0303 | 0x3003;
00502     counter += CODEC_IO_Write(DeviceAddr, 0x01, power_mgnt_reg_1);
00503 
00504     /* Enable HPOUT1 (Left) and HPOUT1 (Right) intermediate stages */
00505     counter += CODEC_IO_Write(DeviceAddr, 0x60, 0x0022);
00506 
00507     /* Enable Charge Pump */
00508     counter += CODEC_IO_Write(DeviceAddr, 0x4C, 0x9F25);
00509 
00510     /* Add Delay */
00511     AUDIO_IO_Delay(15);
00512 
00513     /* Select DAC1 (Left) to Left Headphone Output PGA (HPOUT1LVOL) path */
00514     counter += CODEC_IO_Write(DeviceAddr, 0x2D, 0x0001);
00515 
00516     /* Select DAC1 (Right) to Right Headphone Output PGA (HPOUT1RVOL) path */
00517     counter += CODEC_IO_Write(DeviceAddr, 0x2E, 0x0001);
00518 
00519     /* Enable Left Output Mixer (MIXOUTL), Enable Right Output Mixer (MIXOUTR) */
00520     /* idem for SPKOUTL and SPKOUTR */
00521     counter += CODEC_IO_Write(DeviceAddr, 0x03, 0x0030 | 0x0300);
00522 
00523     /* Enable DC Servo and trigger start-up mode on left and right channels */
00524     counter += CODEC_IO_Write(DeviceAddr, 0x54, 0x0033);
00525 
00526     /* Add Delay */
00527     AUDIO_IO_Delay(250);
00528 
00529     /* Enable HPOUT1 (Left) and HPOUT1 (Right) intermediate and output stages. Remove clamps */
00530     counter += CODEC_IO_Write(DeviceAddr, 0x60, 0x00EE);
00531 
00532     /* Unmutes */
00533 
00534     /* Unmute DAC 1 (Left) */
00535     counter += CODEC_IO_Write(DeviceAddr, 0x610, 0x00C0);
00536 
00537     /* Unmute DAC 1 (Right) */
00538     counter += CODEC_IO_Write(DeviceAddr, 0x611, 0x00C0);
00539 
00540     /* Unmute the AIF1 Timeslot 0 DAC path */
00541     counter += CODEC_IO_Write(DeviceAddr, 0x420, 0x0000);
00542 
00543     /* Unmute DAC 2 (Left) */
00544     counter += CODEC_IO_Write(DeviceAddr, 0x612, 0x00C0);
00545 
00546     /* Unmute DAC 2 (Right) */
00547     counter += CODEC_IO_Write(DeviceAddr, 0x613, 0x00C0);
00548 
00549     /* Unmute the AIF1 Timeslot 1 DAC2 path */
00550     counter += CODEC_IO_Write(DeviceAddr, 0x422, 0x0000);
00551     
00552     /* Volume Control */
00553     wm8994_SetVolume(DeviceAddr, Volume);
00554   }
00555 
00556   if (input_device > 0) /* Audio input selected */
00557   {
00558     if ((input_device == INPUT_DEVICE_DIGITAL_MICROPHONE_1) || (input_device == INPUT_DEVICE_DIGITAL_MICROPHONE_2))
00559     {
00560       /* Enable Microphone bias 1 generator, Enable VMID */
00561       power_mgnt_reg_1 |= 0x0013;
00562       counter += CODEC_IO_Write(DeviceAddr, 0x01, power_mgnt_reg_1);
00563 
00564       /* ADC oversample enable */
00565       counter += CODEC_IO_Write(DeviceAddr, 0x620, 0x0002);
00566 
00567       /* AIF ADC2 HPF enable, HPF cut = voice mode 1 fc=127Hz at fs=8kHz */
00568       counter += CODEC_IO_Write(DeviceAddr, 0x411, 0x3800);
00569     }
00570     else if(input_device == INPUT_DEVICE_DIGITAL_MIC1_MIC2)
00571     {
00572       /* Enable Microphone bias 1 generator, Enable VMID */
00573       power_mgnt_reg_1 |= 0x0013;
00574       counter += CODEC_IO_Write(DeviceAddr, 0x01, power_mgnt_reg_1);
00575 
00576       /* ADC oversample enable */
00577       counter += CODEC_IO_Write(DeviceAddr, 0x620, 0x0002);
00578     
00579       /* AIF ADC1 HPF enable, HPF cut = voice mode 1 fc=127Hz at fs=8kHz */
00580       counter += CODEC_IO_Write(DeviceAddr, 0x410, 0x1800);
00581       
00582       /* AIF ADC2 HPF enable, HPF cut = voice mode 1 fc=127Hz at fs=8kHz */
00583       counter += CODEC_IO_Write(DeviceAddr, 0x411, 0x1800);      
00584     }    
00585     else if ((input_device == INPUT_DEVICE_INPUT_LINE_1) || (input_device == INPUT_DEVICE_INPUT_LINE_2))
00586     {
00587 
00588       /* Disable mute on IN1L, IN1L Volume = +0dB */
00589       counter += CODEC_IO_Write(DeviceAddr, 0x18, 0x000B);
00590 
00591       /* Disable mute on IN1R, IN1R Volume = +0dB */
00592       counter += CODEC_IO_Write(DeviceAddr, 0x1A, 0x000B);
00593 
00594       /* AIF ADC1 HPF enable, HPF cut = hifi mode fc=4Hz at fs=48kHz */
00595       counter += CODEC_IO_Write(DeviceAddr, 0x410, 0x1800);
00596     }
00597     /* Volume Control */
00598     wm8994_SetVolume(DeviceAddr, Volume);
00599   }
00600   /* Return communication control value */
00601   return counter;  
00602 }
00603 
00604 /**
00605   * @brief  Deinitializes the audio codec.
00606   * @param  None
00607   * @retval  None
00608   */
00609 void wm8994_DeInit(void)
00610 {
00611   /* Deinitialize Audio Codec interface */
00612   AUDIO_IO_DeInit();
00613 }
00614 
00615 /**
00616   * @brief  Get the WM8994 ID.
00617   * @param DeviceAddr: Device address on communication Bus.
00618   * @retval The WM8994 ID 
00619   */
00620 uint32_t wm8994_ReadID(uint16_t DeviceAddr)
00621 {
00622   /* Initialize the Control interface of the Audio Codec */
00623   AUDIO_IO_Init();
00624 
00625   return ((uint32_t)AUDIO_IO_Read(DeviceAddr, WM8994_CHIPID_ADDR));
00626 }
00627 
00628 /**
00629   * @brief Start the audio Codec play feature.
00630   * @note For this codec no Play options are required.
00631   * @param DeviceAddr: Device address on communication Bus.   
00632   * @retval 0 if correct communication, else wrong communication
00633   */
00634 uint32_t wm8994_Play(uint16_t DeviceAddr, uint16_t* pBuffer, uint16_t Size)
00635 {
00636   uint32_t counter = 0;
00637  
00638   /* Resumes the audio file playing */  
00639   /* Unmute the output first */
00640   counter += wm8994_SetMute(DeviceAddr, AUDIO_MUTE_OFF);
00641   
00642   return counter;
00643 }
00644 
00645 /**
00646   * @brief Pauses playing on the audio codec.
00647   * @param DeviceAddr: Device address on communication Bus. 
00648   * @retval 0 if correct communication, else wrong communication
00649   */
00650 uint32_t wm8994_Pause(uint16_t DeviceAddr)
00651 {  
00652   uint32_t counter = 0;
00653  
00654   /* Pause the audio file playing */
00655   /* Mute the output first */
00656   counter += wm8994_SetMute(DeviceAddr, AUDIO_MUTE_ON);
00657   
00658   /* Put the Codec in Power save mode */
00659   counter += CODEC_IO_Write(DeviceAddr, 0x02, 0x01);
00660  
00661   return counter;
00662 }
00663 
00664 /**
00665   * @brief Resumes playing on the audio codec.
00666   * @param DeviceAddr: Device address on communication Bus. 
00667   * @retval 0 if correct communication, else wrong communication
00668   */
00669 uint32_t wm8994_Resume(uint16_t DeviceAddr)
00670 {
00671   uint32_t counter = 0;
00672  
00673   /* Resumes the audio file playing */  
00674   /* Unmute the output first */
00675   counter += wm8994_SetMute(DeviceAddr, AUDIO_MUTE_OFF);
00676   
00677   return counter;
00678 }
00679 
00680 /**
00681   * @brief Stops audio Codec playing. It powers down the codec.
00682   * @param DeviceAddr: Device address on communication Bus. 
00683   * @param CodecPdwnMode: selects the  power down mode.
00684   *          - CODEC_PDWN_SW: only mutes the audio codec. When resuming from this 
00685   *                           mode the codec keeps the previous initialization
00686   *                           (no need to re-Initialize the codec registers).
00687   *          - CODEC_PDWN_HW: Physically power down the codec. When resuming from this
00688   *                           mode, the codec is set to default configuration 
00689   *                           (user should re-Initialize the codec in order to 
00690   *                            play again the audio stream).
00691   * @retval 0 if correct communication, else wrong communication
00692   */
00693 uint32_t wm8994_Stop(uint16_t DeviceAddr, uint32_t CodecPdwnMode)
00694 {
00695   uint32_t counter = 0;
00696 
00697   if (outputEnabled != 0)
00698   {
00699     /* Mute the output first */
00700     counter += wm8994_SetMute(DeviceAddr, AUDIO_MUTE_ON);
00701 
00702     if (CodecPdwnMode == CODEC_PDWN_SW)
00703     {
00704        /* Only output mute required*/
00705     }
00706     else /* CODEC_PDWN_HW */
00707     {
00708       /* Mute the AIF1 Timeslot 0 DAC1 path */
00709       counter += CODEC_IO_Write(DeviceAddr, 0x420, 0x0200);
00710 
00711       /* Mute the AIF1 Timeslot 1 DAC2 path */
00712       counter += CODEC_IO_Write(DeviceAddr, 0x422, 0x0200);
00713 
00714       /* Disable DAC1L_TO_HPOUT1L */
00715       counter += CODEC_IO_Write(DeviceAddr, 0x2D, 0x0000);
00716 
00717       /* Disable DAC1R_TO_HPOUT1R */
00718       counter += CODEC_IO_Write(DeviceAddr, 0x2E, 0x0000);
00719 
00720       /* Disable DAC1 and DAC2 */
00721       counter += CODEC_IO_Write(DeviceAddr, 0x05, 0x0000);
00722 
00723       /* Reset Codec by writing in 0x0000 address register */
00724       counter += CODEC_IO_Write(DeviceAddr, 0x0000, 0x0000);
00725 
00726       outputEnabled = 0;
00727     }
00728   }
00729   return counter;
00730 }
00731 
00732 /**
00733   * @brief Sets higher or lower the codec volume level.
00734   * @param DeviceAddr: Device address on communication Bus.
00735   * @param Volume: a byte value from 0 to 255 (refer to codec registers 
00736   *         description for more details).
00737   * @retval 0 if correct communication, else wrong communication
00738   */
00739 uint32_t wm8994_SetVolume(uint16_t DeviceAddr, uint8_t Volume)
00740 {
00741   uint32_t counter = 0;
00742   uint8_t convertedvol = VOLUME_CONVERT(Volume);
00743 
00744   /* Output volume */
00745   if (outputEnabled != 0)
00746   {
00747     if(convertedvol > 0x3E)
00748     {
00749       /* Unmute audio codec */
00750       counter += wm8994_SetMute(DeviceAddr, AUDIO_MUTE_OFF);
00751 
00752       /* Left Headphone Volume */
00753       counter += CODEC_IO_Write(DeviceAddr, 0x1C, 0x3F | 0x140);
00754 
00755       /* Right Headphone Volume */
00756       counter += CODEC_IO_Write(DeviceAddr, 0x1D, 0x3F | 0x140);
00757 
00758       /* Left Speaker Volume */
00759       counter += CODEC_IO_Write(DeviceAddr, 0x26, 0x3F | 0x140);
00760 
00761       /* Right Speaker Volume */
00762       counter += CODEC_IO_Write(DeviceAddr, 0x27, 0x3F | 0x140);
00763     }
00764     else if (Volume == 0)
00765     {
00766       /* Mute audio codec */
00767       counter += wm8994_SetMute(DeviceAddr, AUDIO_MUTE_ON);
00768     }
00769     else
00770     {
00771       /* Unmute audio codec */
00772       counter += wm8994_SetMute(DeviceAddr, AUDIO_MUTE_OFF);
00773 
00774       /* Left Headphone Volume */
00775       counter += CODEC_IO_Write(DeviceAddr, 0x1C, convertedvol | 0x140);
00776 
00777       /* Right Headphone Volume */
00778       counter += CODEC_IO_Write(DeviceAddr, 0x1D, convertedvol | 0x140);
00779 
00780       /* Left Speaker Volume */
00781       counter += CODEC_IO_Write(DeviceAddr, 0x26, convertedvol | 0x140);
00782 
00783       /* Right Speaker Volume */
00784       counter += CODEC_IO_Write(DeviceAddr, 0x27, convertedvol | 0x140);
00785     }
00786   }
00787 
00788   /* Input volume */
00789   if (inputEnabled != 0)
00790   {
00791     convertedvol = VOLUME_IN_CONVERT(Volume);
00792 
00793     /* Left AIF1 ADC1 volume */
00794     counter += CODEC_IO_Write(DeviceAddr, 0x400, convertedvol | 0x100);
00795 
00796     /* Right AIF1 ADC1 volume */
00797     counter += CODEC_IO_Write(DeviceAddr, 0x401, convertedvol | 0x100);
00798 
00799     /* Left AIF1 ADC2 volume */
00800     counter += CODEC_IO_Write(DeviceAddr, 0x404, convertedvol | 0x100);
00801 
00802     /* Right AIF1 ADC2 volume */
00803     counter += CODEC_IO_Write(DeviceAddr, 0x405, convertedvol | 0x100);
00804   }
00805   return counter;
00806 }
00807 
00808 /**
00809   * @brief Enables or disables the mute feature on the audio codec.
00810   * @param DeviceAddr: Device address on communication Bus.   
00811   * @param Cmd: AUDIO_MUTE_ON to enable the mute or AUDIO_MUTE_OFF to disable the
00812   *             mute mode.
00813   * @retval 0 if correct communication, else wrong communication
00814   */
00815 uint32_t wm8994_SetMute(uint16_t DeviceAddr, uint32_t Cmd)
00816 {
00817   uint32_t counter = 0;
00818   
00819   if (outputEnabled != 0)
00820   {
00821     /* Set the Mute mode */
00822     if(Cmd == AUDIO_MUTE_ON)
00823     {
00824       /* Soft Mute the AIF1 Timeslot 0 DAC1 path L&R */
00825       counter += CODEC_IO_Write(DeviceAddr, 0x420, 0x0200);
00826 
00827       /* Soft Mute the AIF1 Timeslot 1 DAC2 path L&R */
00828       counter += CODEC_IO_Write(DeviceAddr, 0x422, 0x0200);
00829     }
00830     else /* AUDIO_MUTE_OFF Disable the Mute */
00831     {
00832       /* Unmute the AIF1 Timeslot 0 DAC1 path L&R */
00833       counter += CODEC_IO_Write(DeviceAddr, 0x420, 0x0000);
00834 
00835       /* Unmute the AIF1 Timeslot 1 DAC2 path L&R */
00836       counter += CODEC_IO_Write(DeviceAddr, 0x422, 0x0000);
00837     }
00838   }
00839   return counter;
00840 }
00841 
00842 /**
00843   * @brief Switch dynamically (while audio file is played) the output target 
00844   *         (speaker or headphone).
00845   * @param DeviceAddr: Device address on communication Bus.
00846   * @param Output: specifies the audio output target: OUTPUT_DEVICE_SPEAKER,
00847   *         OUTPUT_DEVICE_HEADPHONE, OUTPUT_DEVICE_BOTH or OUTPUT_DEVICE_AUTO 
00848   * @retval 0 if correct communication, else wrong communication
00849   */
00850 uint32_t wm8994_SetOutputMode(uint16_t DeviceAddr, uint8_t Output)
00851 {
00852   uint32_t counter = 0; 
00853   
00854   switch (Output) 
00855   {
00856   case OUTPUT_DEVICE_SPEAKER:
00857     /* Enable DAC1 (Left), Enable DAC1 (Right), 
00858     Disable DAC2 (Left), Disable DAC2 (Right)*/
00859     counter += CODEC_IO_Write(DeviceAddr, 0x05, 0x0C0C);
00860     
00861     /* Enable the AIF1 Timeslot 0 (Left) to DAC 1 (Left) mixer path */
00862     counter += CODEC_IO_Write(DeviceAddr, 0x601, 0x0000);
00863     
00864     /* Enable the AIF1 Timeslot 0 (Right) to DAC 1 (Right) mixer path */
00865     counter += CODEC_IO_Write(DeviceAddr, 0x602, 0x0000);
00866     
00867     /* Disable the AIF1 Timeslot 1 (Left) to DAC 2 (Left) mixer path */
00868     counter += CODEC_IO_Write(DeviceAddr, 0x604, 0x0002);
00869     
00870     /* Disable the AIF1 Timeslot 1 (Right) to DAC 2 (Right) mixer path */
00871     counter += CODEC_IO_Write(DeviceAddr, 0x605, 0x0002);
00872     break;
00873     
00874   case OUTPUT_DEVICE_HEADPHONE:
00875     /* Disable DAC1 (Left), Disable DAC1 (Right), 
00876     Enable DAC2 (Left), Enable DAC2 (Right)*/
00877     counter += CODEC_IO_Write(DeviceAddr, 0x05, 0x0303);
00878     
00879     /* Enable the AIF1 Timeslot 0 (Left) to DAC 1 (Left) mixer path */
00880     counter += CODEC_IO_Write(DeviceAddr, 0x601, 0x0001);
00881     
00882     /* Enable the AIF1 Timeslot 0 (Right) to DAC 1 (Right) mixer path */
00883     counter += CODEC_IO_Write(DeviceAddr, 0x602, 0x0001);
00884     
00885     /* Disable the AIF1 Timeslot 1 (Left) to DAC 2 (Left) mixer path */
00886     counter += CODEC_IO_Write(DeviceAddr, 0x604, 0x0000);
00887     
00888     /* Disable the AIF1 Timeslot 1 (Right) to DAC 2 (Right) mixer path */
00889     counter += CODEC_IO_Write(DeviceAddr, 0x605, 0x0000);
00890     break;
00891     
00892   case OUTPUT_DEVICE_BOTH:
00893     /* Enable DAC1 (Left), Enable DAC1 (Right), 
00894     also Enable DAC2 (Left), Enable DAC2 (Right)*/
00895     counter += CODEC_IO_Write(DeviceAddr, 0x05, 0x0303 | 0x0C0C);
00896     
00897     /* Enable the AIF1 Timeslot 0 (Left) to DAC 1 (Left) mixer path */
00898     counter += CODEC_IO_Write(DeviceAddr, 0x601, 0x0001);
00899     
00900     /* Enable the AIF1 Timeslot 0 (Right) to DAC 1 (Right) mixer path */
00901     counter += CODEC_IO_Write(DeviceAddr, 0x602, 0x0001);
00902     
00903     /* Enable the AIF1 Timeslot 1 (Left) to DAC 2 (Left) mixer path */
00904     counter += CODEC_IO_Write(DeviceAddr, 0x604, 0x0002);
00905     
00906     /* Enable the AIF1 Timeslot 1 (Right) to DAC 2 (Right) mixer path */
00907     counter += CODEC_IO_Write(DeviceAddr, 0x605, 0x0002);
00908     break;
00909     
00910   default:
00911     /* Disable DAC1 (Left), Disable DAC1 (Right), 
00912     Enable DAC2 (Left), Enable DAC2 (Right)*/
00913     counter += CODEC_IO_Write(DeviceAddr, 0x05, 0x0303);
00914     
00915     /* Enable the AIF1 Timeslot 0 (Left) to DAC 1 (Left) mixer path */
00916     counter += CODEC_IO_Write(DeviceAddr, 0x601, 0x0001);
00917     
00918     /* Enable the AIF1 Timeslot 0 (Right) to DAC 1 (Right) mixer path */
00919     counter += CODEC_IO_Write(DeviceAddr, 0x602, 0x0001);
00920     
00921     /* Disable the AIF1 Timeslot 1 (Left) to DAC 2 (Left) mixer path */
00922     counter += CODEC_IO_Write(DeviceAddr, 0x604, 0x0000);
00923     
00924     /* Disable the AIF1 Timeslot 1 (Right) to DAC 2 (Right) mixer path */
00925     counter += CODEC_IO_Write(DeviceAddr, 0x605, 0x0000);
00926     break;    
00927   }  
00928   return counter;
00929 }
00930 
00931 /**
00932   * @brief Sets new frequency.
00933   * @param DeviceAddr: Device address on communication Bus.
00934   * @param AudioFreq: Audio frequency used to play the audio stream.
00935   * @retval 0 if correct communication, else wrong communication
00936   */
00937 uint32_t wm8994_SetFrequency(uint16_t DeviceAddr, uint32_t AudioFreq)
00938 {
00939   uint32_t counter = 0;
00940  
00941   /*  Clock Configurations */
00942   switch (AudioFreq)
00943   {
00944   case  AUDIO_FREQUENCY_8K:
00945     /* AIF1 Sample Rate = 8 (KHz), ratio=256 */ 
00946     counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0003);
00947     break;
00948     
00949   case  AUDIO_FREQUENCY_16K:
00950     /* AIF1 Sample Rate = 16 (KHz), ratio=256 */ 
00951     counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0033);
00952     break;
00953     
00954   case  AUDIO_FREQUENCY_48K:
00955     /* AIF1 Sample Rate = 48 (KHz), ratio=256 */ 
00956     counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0083);
00957     break;
00958     
00959   case  AUDIO_FREQUENCY_96K:
00960     /* AIF1 Sample Rate = 96 (KHz), ratio=256 */ 
00961     counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x00A3);
00962     break;
00963     
00964   case  AUDIO_FREQUENCY_11K:
00965     /* AIF1 Sample Rate = 11.025 (KHz), ratio=256 */ 
00966     counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0013);
00967     break;
00968     
00969   case  AUDIO_FREQUENCY_22K:
00970     /* AIF1 Sample Rate = 22.050 (KHz), ratio=256 */ 
00971     counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0043);
00972     break;
00973     
00974   case  AUDIO_FREQUENCY_44K:
00975     /* AIF1 Sample Rate = 44.1 (KHz), ratio=256 */ 
00976     counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0073);
00977     break; 
00978     
00979   default:
00980     /* AIF1 Sample Rate = 48 (KHz), ratio=256 */ 
00981     counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0083);
00982     break; 
00983   }
00984   return counter;
00985 }
00986 
00987 /**
00988   * @brief Resets wm8994 registers.
00989   * @param DeviceAddr: Device address on communication Bus. 
00990   * @retval 0 if correct communication, else wrong communication
00991   */
00992 uint32_t wm8994_Reset(uint16_t DeviceAddr)
00993 {
00994   uint32_t counter = 0;
00995   
00996   /* Reset Codec by writing in 0x0000 address register */
00997   counter = CODEC_IO_Write(DeviceAddr, 0x0000, 0x0000);
00998   outputEnabled = 0;
00999   inputEnabled=0;
01000 
01001   return counter;
01002 }
01003 
01004 /**
01005   * @brief  Writes/Read a single data.
01006   * @param  Addr: I2C address
01007   * @param  Reg: Reg address 
01008   * @param  Value: Data to be written
01009   * @retval None
01010   */
01011 static uint8_t CODEC_IO_Write(uint8_t Addr, uint16_t Reg, uint16_t Value)
01012 {
01013   uint32_t result = 0;
01014   
01015  AUDIO_IO_Write(Addr, Reg, Value);
01016   
01017 #ifdef VERIFY_WRITTENDATA
01018   /* Verify that the data has been correctly written */
01019   result = (AUDIO_IO_Read(Addr, Reg) == Value)? 0:1;
01020 #endif /* VERIFY_WRITTENDATA */
01021   
01022   return result;
01023 }
01024 
01025 /**
01026   * @}
01027   */
01028 
01029 /**
01030   * @}
01031   */
01032 
01033 /**
01034   * @}
01035   */
01036 
01037 /**
01038   * @}
01039   */
01040 
01041 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/