Phung Tung / Mbed 2 deprecated BSP_DISCO_F746NG

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Dependencies:   mbed

Dependents:   LCD

Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_sdram.c@0:d05b765ea94c, 2019-06-07 (annotated)

Committer:
fundokukiri
Date:
Fri Jun 07 17:29:39 2019 +0000
Revision:
0:d05b765ea94c
LCD_BSP

Who changed what in which revision?

UserRevisionLine numberNew contents of line
fundokukiri 0:d05b765ea94c 1 /**
fundokukiri 0:d05b765ea94c 2 ******************************************************************************
fundokukiri 0:d05b765ea94c 3 * @file stm32746g_discovery_sdram.c
fundokukiri 0:d05b765ea94c 4 * @author MCD Application Team
fundokukiri 0:d05b765ea94c 5 * @version V2.0.0
fundokukiri 0:d05b765ea94c 6 * @date 30-December-2016
fundokukiri 0:d05b765ea94c 7 * @brief This file includes the SDRAM driver for the MT48LC4M32B2B5-7 memory
fundokukiri 0:d05b765ea94c 8 * device mounted on STM32746G-Discovery board.
fundokukiri 0:d05b765ea94c 9 @verbatim
fundokukiri 0:d05b765ea94c 10 1. How To use this driver:
fundokukiri 0:d05b765ea94c 11 --------------------------
fundokukiri 0:d05b765ea94c 12 - This driver is used to drive the MT48LC4M32B2B5-7 SDRAM external memory mounted
fundokukiri 0:d05b765ea94c 13 on STM32746G-Discovery board.
fundokukiri 0:d05b765ea94c 14 - This driver does not need a specific component driver for the SDRAM device
fundokukiri 0:d05b765ea94c 15 to be included with.
fundokukiri 0:d05b765ea94c 16
fundokukiri 0:d05b765ea94c 17 2. Driver description:
fundokukiri 0:d05b765ea94c 18 ---------------------
fundokukiri 0:d05b765ea94c 19 + Initialization steps:
fundokukiri 0:d05b765ea94c 20 o Initialize the SDRAM external memory using the BSP_SDRAM_Init() function. This
fundokukiri 0:d05b765ea94c 21 function includes the MSP layer hardware resources initialization and the
fundokukiri 0:d05b765ea94c 22 FMC controller configuration to interface with the external SDRAM memory.
fundokukiri 0:d05b765ea94c 23 o It contains the SDRAM initialization sequence to program the SDRAM external
fundokukiri 0:d05b765ea94c 24 device using the function BSP_SDRAM_Initialization_sequence(). Note that this
fundokukiri 0:d05b765ea94c 25 sequence is standard for all SDRAM devices, but can include some differences
fundokukiri 0:d05b765ea94c 26 from a device to another. If it is the case, the right sequence should be
fundokukiri 0:d05b765ea94c 27 implemented separately.
fundokukiri 0:d05b765ea94c 28
fundokukiri 0:d05b765ea94c 29 + SDRAM read/write operations
fundokukiri 0:d05b765ea94c 30 o SDRAM external memory can be accessed with read/write operations once it is
fundokukiri 0:d05b765ea94c 31 initialized.
fundokukiri 0:d05b765ea94c 32 Read/write operation can be performed with AHB access using the functions
fundokukiri 0:d05b765ea94c 33 BSP_SDRAM_ReadData()/BSP_SDRAM_WriteData(), or by DMA transfer using the functions
fundokukiri 0:d05b765ea94c 34 BSP_SDRAM_ReadData_DMA()/BSP_SDRAM_WriteData_DMA().
fundokukiri 0:d05b765ea94c 35 o The AHB access is performed with 32-bit width transaction, the DMA transfer
fundokukiri 0:d05b765ea94c 36 configuration is fixed at single (no burst) word transfer (see the
fundokukiri 0:d05b765ea94c 37 SDRAM_MspInit() static function).
fundokukiri 0:d05b765ea94c 38 o User can implement his own functions for read/write access with his desired
fundokukiri 0:d05b765ea94c 39 configurations.
fundokukiri 0:d05b765ea94c 40 o If interrupt mode is used for DMA transfer, the function BSP_SDRAM_DMA_IRQHandler()
fundokukiri 0:d05b765ea94c 41 is called in IRQ handler file, to serve the generated interrupt once the DMA
fundokukiri 0:d05b765ea94c 42 transfer is complete.
fundokukiri 0:d05b765ea94c 43 o You can send a command to the SDRAM device in runtime using the function
fundokukiri 0:d05b765ea94c 44 BSP_SDRAM_Sendcmd(), and giving the desired command as parameter chosen between
fundokukiri 0:d05b765ea94c 45 the predefined commands of the "FMC_SDRAM_CommandTypeDef" structure.
fundokukiri 0:d05b765ea94c 46
fundokukiri 0:d05b765ea94c 47 @endverbatim
fundokukiri 0:d05b765ea94c 48 ******************************************************************************
fundokukiri 0:d05b765ea94c 49 * @attention
fundokukiri 0:d05b765ea94c 50 *
fundokukiri 0:d05b765ea94c 51 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
fundokukiri 0:d05b765ea94c 52 *
fundokukiri 0:d05b765ea94c 53 * Redistribution and use in source and binary forms, with or without modification,
fundokukiri 0:d05b765ea94c 54 * are permitted provided that the following conditions are met:
fundokukiri 0:d05b765ea94c 55 * 1. Redistributions of source code must retain the above copyright notice,
fundokukiri 0:d05b765ea94c 56 * this list of conditions and the following disclaimer.
fundokukiri 0:d05b765ea94c 57 * 2. Redistributions in binary form must reproduce the above copyright notice,
fundokukiri 0:d05b765ea94c 58 * this list of conditions and the following disclaimer in the documentation
fundokukiri 0:d05b765ea94c 59 * and/or other materials provided with the distribution.
fundokukiri 0:d05b765ea94c 60 * 3. Neither the name of STMicroelectronics nor the names of its contributors
fundokukiri 0:d05b765ea94c 61 * may be used to endorse or promote products derived from this software
fundokukiri 0:d05b765ea94c 62 * without specific prior written permission.
fundokukiri 0:d05b765ea94c 63 *
fundokukiri 0:d05b765ea94c 64 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
fundokukiri 0:d05b765ea94c 65 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
fundokukiri 0:d05b765ea94c 66 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
fundokukiri 0:d05b765ea94c 67 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
fundokukiri 0:d05b765ea94c 68 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
fundokukiri 0:d05b765ea94c 69 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
fundokukiri 0:d05b765ea94c 70 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
fundokukiri 0:d05b765ea94c 71 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
fundokukiri 0:d05b765ea94c 72 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
fundokukiri 0:d05b765ea94c 73 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
fundokukiri 0:d05b765ea94c 74 *
fundokukiri 0:d05b765ea94c 75 ******************************************************************************
fundokukiri 0:d05b765ea94c 76 */
fundokukiri 0:d05b765ea94c 77
fundokukiri 0:d05b765ea94c 78 /* Includes ------------------------------------------------------------------*/
fundokukiri 0:d05b765ea94c 79 #include "stm32746g_discovery_sdram.h"
fundokukiri 0:d05b765ea94c 80
fundokukiri 0:d05b765ea94c 81 void wait_ms(int ms); // MBED to replace HAL_Delay function
fundokukiri 0:d05b765ea94c 82
fundokukiri 0:d05b765ea94c 83 /** @addtogroup BSP
fundokukiri 0:d05b765ea94c 84 * @{
fundokukiri 0:d05b765ea94c 85 */
fundokukiri 0:d05b765ea94c 86
fundokukiri 0:d05b765ea94c 87 /** @addtogroup STM32746G_DISCOVERY
fundokukiri 0:d05b765ea94c 88 * @{
fundokukiri 0:d05b765ea94c 89 */
fundokukiri 0:d05b765ea94c 90
fundokukiri 0:d05b765ea94c 91 /** @defgroup STM32746G_DISCOVERY_SDRAM STM32746G_DISCOVERY_SDRAM
fundokukiri 0:d05b765ea94c 92 * @{
fundokukiri 0:d05b765ea94c 93 */
fundokukiri 0:d05b765ea94c 94
fundokukiri 0:d05b765ea94c 95 /** @defgroup STM32746G_DISCOVERY_SDRAM_Private_Types_Definitions STM32746G_DISCOVERY_SDRAM Private Types Definitions
fundokukiri 0:d05b765ea94c 96 * @{
fundokukiri 0:d05b765ea94c 97 */
fundokukiri 0:d05b765ea94c 98 /**
fundokukiri 0:d05b765ea94c 99 * @}
fundokukiri 0:d05b765ea94c 100 */
fundokukiri 0:d05b765ea94c 101
fundokukiri 0:d05b765ea94c 102 /** @defgroup STM32746G_DISCOVERY_SDRAM_Private_Defines STM32746G_DISCOVERY_SDRAM Private Defines
fundokukiri 0:d05b765ea94c 103 * @{
fundokukiri 0:d05b765ea94c 104 */
fundokukiri 0:d05b765ea94c 105 /**
fundokukiri 0:d05b765ea94c 106 * @}
fundokukiri 0:d05b765ea94c 107 */
fundokukiri 0:d05b765ea94c 108
fundokukiri 0:d05b765ea94c 109 /** @defgroup STM32746G_DISCOVERY_SDRAM_Private_Macros STM32746G_DISCOVERY_SDRAM Private Macros
fundokukiri 0:d05b765ea94c 110 * @{
fundokukiri 0:d05b765ea94c 111 */
fundokukiri 0:d05b765ea94c 112 /**
fundokukiri 0:d05b765ea94c 113 * @}
fundokukiri 0:d05b765ea94c 114 */
fundokukiri 0:d05b765ea94c 115
fundokukiri 0:d05b765ea94c 116 /** @defgroup STM32746G_DISCOVERY_SDRAM_Private_Variables STM32746G_DISCOVERY_SDRAM Private Variables
fundokukiri 0:d05b765ea94c 117 * @{
fundokukiri 0:d05b765ea94c 118 */
fundokukiri 0:d05b765ea94c 119 SDRAM_HandleTypeDef sdramHandle;
fundokukiri 0:d05b765ea94c 120 static FMC_SDRAM_TimingTypeDef Timing;
fundokukiri 0:d05b765ea94c 121 static FMC_SDRAM_CommandTypeDef Command;
fundokukiri 0:d05b765ea94c 122 /**
fundokukiri 0:d05b765ea94c 123 * @}
fundokukiri 0:d05b765ea94c 124 */
fundokukiri 0:d05b765ea94c 125
fundokukiri 0:d05b765ea94c 126 /** @defgroup STM32746G_DISCOVERY_SDRAM_Private_Function_Prototypes STM32746G_DISCOVERY_SDRAM Private Function Prototypes
fundokukiri 0:d05b765ea94c 127 * @{
fundokukiri 0:d05b765ea94c 128 */
fundokukiri 0:d05b765ea94c 129 /**
fundokukiri 0:d05b765ea94c 130 * @}
fundokukiri 0:d05b765ea94c 131 */
fundokukiri 0:d05b765ea94c 132
fundokukiri 0:d05b765ea94c 133 /** @defgroup STM32746G_DISCOVERY_SDRAM_Exported_Functions STM32746G_DISCOVERY_SDRAM Exported Functions
fundokukiri 0:d05b765ea94c 134 * @{
fundokukiri 0:d05b765ea94c 135 */
fundokukiri 0:d05b765ea94c 136
fundokukiri 0:d05b765ea94c 137 /**
fundokukiri 0:d05b765ea94c 138 * @brief Initializes the SDRAM device.
fundokukiri 0:d05b765ea94c 139 * @retval SDRAM status
fundokukiri 0:d05b765ea94c 140 */
fundokukiri 0:d05b765ea94c 141 uint8_t BSP_SDRAM_Init(void)
fundokukiri 0:d05b765ea94c 142 {
fundokukiri 0:d05b765ea94c 143 static uint8_t sdramstatus = SDRAM_ERROR;
fundokukiri 0:d05b765ea94c 144 /* SDRAM device configuration */
fundokukiri 0:d05b765ea94c 145 sdramHandle.Instance = FMC_SDRAM_DEVICE;
fundokukiri 0:d05b765ea94c 146
fundokukiri 0:d05b765ea94c 147 /* Timing configuration for 100Mhz as SD clock frequency (System clock is up to 200Mhz) */
fundokukiri 0:d05b765ea94c 148 Timing.LoadToActiveDelay = 2;
fundokukiri 0:d05b765ea94c 149 Timing.ExitSelfRefreshDelay = 7;
fundokukiri 0:d05b765ea94c 150 Timing.SelfRefreshTime = 4;
fundokukiri 0:d05b765ea94c 151 Timing.RowCycleDelay = 7;
fundokukiri 0:d05b765ea94c 152 Timing.WriteRecoveryTime = 2;
fundokukiri 0:d05b765ea94c 153 Timing.RPDelay = 2;
fundokukiri 0:d05b765ea94c 154 Timing.RCDDelay = 2;
fundokukiri 0:d05b765ea94c 155
fundokukiri 0:d05b765ea94c 156 sdramHandle.Init.SDBank = FMC_SDRAM_BANK1;
fundokukiri 0:d05b765ea94c 157 sdramHandle.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_8;
fundokukiri 0:d05b765ea94c 158 sdramHandle.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12;
fundokukiri 0:d05b765ea94c 159 sdramHandle.Init.MemoryDataWidth = SDRAM_MEMORY_WIDTH;
fundokukiri 0:d05b765ea94c 160 sdramHandle.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4;
fundokukiri 0:d05b765ea94c 161 sdramHandle.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_2;
fundokukiri 0:d05b765ea94c 162 sdramHandle.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE;
fundokukiri 0:d05b765ea94c 163 sdramHandle.Init.SDClockPeriod = SDCLOCK_PERIOD;
fundokukiri 0:d05b765ea94c 164 sdramHandle.Init.ReadBurst = FMC_SDRAM_RBURST_ENABLE;
fundokukiri 0:d05b765ea94c 165 sdramHandle.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0;
fundokukiri 0:d05b765ea94c 166
fundokukiri 0:d05b765ea94c 167 /* SDRAM controller initialization */
fundokukiri 0:d05b765ea94c 168
fundokukiri 0:d05b765ea94c 169 BSP_SDRAM_MspInit(&sdramHandle, NULL); /* __weak function can be rewritten by the application */
fundokukiri 0:d05b765ea94c 170
fundokukiri 0:d05b765ea94c 171 if(HAL_SDRAM_Init(&sdramHandle, &Timing) != HAL_OK)
fundokukiri 0:d05b765ea94c 172 {
fundokukiri 0:d05b765ea94c 173 sdramstatus = SDRAM_ERROR;
fundokukiri 0:d05b765ea94c 174 }
fundokukiri 0:d05b765ea94c 175 else
fundokukiri 0:d05b765ea94c 176 {
fundokukiri 0:d05b765ea94c 177 sdramstatus = SDRAM_OK;
fundokukiri 0:d05b765ea94c 178 }
fundokukiri 0:d05b765ea94c 179
fundokukiri 0:d05b765ea94c 180 /* SDRAM initialization sequence */
fundokukiri 0:d05b765ea94c 181 BSP_SDRAM_Initialization_sequence(REFRESH_COUNT);
fundokukiri 0:d05b765ea94c 182
fundokukiri 0:d05b765ea94c 183 return sdramstatus;
fundokukiri 0:d05b765ea94c 184 }
fundokukiri 0:d05b765ea94c 185
fundokukiri 0:d05b765ea94c 186 /**
fundokukiri 0:d05b765ea94c 187 * @brief DeInitializes the SDRAM device.
fundokukiri 0:d05b765ea94c 188 * @retval SDRAM status
fundokukiri 0:d05b765ea94c 189 */
fundokukiri 0:d05b765ea94c 190 uint8_t BSP_SDRAM_DeInit(void)
fundokukiri 0:d05b765ea94c 191 {
fundokukiri 0:d05b765ea94c 192 static uint8_t sdramstatus = SDRAM_ERROR;
fundokukiri 0:d05b765ea94c 193 /* SDRAM device de-initialization */
fundokukiri 0:d05b765ea94c 194 sdramHandle.Instance = FMC_SDRAM_DEVICE;
fundokukiri 0:d05b765ea94c 195
fundokukiri 0:d05b765ea94c 196 if(HAL_SDRAM_DeInit(&sdramHandle) != HAL_OK)
fundokukiri 0:d05b765ea94c 197 {
fundokukiri 0:d05b765ea94c 198 sdramstatus = SDRAM_ERROR;
fundokukiri 0:d05b765ea94c 199 }
fundokukiri 0:d05b765ea94c 200 else
fundokukiri 0:d05b765ea94c 201 {
fundokukiri 0:d05b765ea94c 202 sdramstatus = SDRAM_OK;
fundokukiri 0:d05b765ea94c 203 }
fundokukiri 0:d05b765ea94c 204
fundokukiri 0:d05b765ea94c 205 /* SDRAM controller de-initialization */
fundokukiri 0:d05b765ea94c 206 BSP_SDRAM_MspDeInit(&sdramHandle, NULL);
fundokukiri 0:d05b765ea94c 207
fundokukiri 0:d05b765ea94c 208 return sdramstatus;
fundokukiri 0:d05b765ea94c 209 }
fundokukiri 0:d05b765ea94c 210
fundokukiri 0:d05b765ea94c 211 /**
fundokukiri 0:d05b765ea94c 212 * @brief Programs the SDRAM device.
fundokukiri 0:d05b765ea94c 213 * @param RefreshCount: SDRAM refresh counter value
fundokukiri 0:d05b765ea94c 214 * @retval None
fundokukiri 0:d05b765ea94c 215 */
fundokukiri 0:d05b765ea94c 216 void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount)
fundokukiri 0:d05b765ea94c 217 {
fundokukiri 0:d05b765ea94c 218 __IO uint32_t tmpmrd = 0;
fundokukiri 0:d05b765ea94c 219
fundokukiri 0:d05b765ea94c 220 /* Step 1: Configure a clock configuration enable command */
fundokukiri 0:d05b765ea94c 221 Command.CommandMode = FMC_SDRAM_CMD_CLK_ENABLE;
fundokukiri 0:d05b765ea94c 222 Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
fundokukiri 0:d05b765ea94c 223 Command.AutoRefreshNumber = 1;
fundokukiri 0:d05b765ea94c 224 Command.ModeRegisterDefinition = 0;
fundokukiri 0:d05b765ea94c 225
fundokukiri 0:d05b765ea94c 226 /* Send the command */
fundokukiri 0:d05b765ea94c 227 HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
fundokukiri 0:d05b765ea94c 228
fundokukiri 0:d05b765ea94c 229 /* Step 2: Insert 100 us minimum delay */
fundokukiri 0:d05b765ea94c 230 /* Inserted delay is equal to 1 ms due to systick time base unit (ms) */
fundokukiri 0:d05b765ea94c 231 //HAL_Delay(1); // MBED
fundokukiri 0:d05b765ea94c 232 wait_ms(1); // MBED
fundokukiri 0:d05b765ea94c 233
fundokukiri 0:d05b765ea94c 234 /* Step 3: Configure a PALL (precharge all) command */
fundokukiri 0:d05b765ea94c 235 Command.CommandMode = FMC_SDRAM_CMD_PALL;
fundokukiri 0:d05b765ea94c 236 Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
fundokukiri 0:d05b765ea94c 237 Command.AutoRefreshNumber = 1;
fundokukiri 0:d05b765ea94c 238 Command.ModeRegisterDefinition = 0;
fundokukiri 0:d05b765ea94c 239
fundokukiri 0:d05b765ea94c 240 /* Send the command */
fundokukiri 0:d05b765ea94c 241 HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
fundokukiri 0:d05b765ea94c 242
fundokukiri 0:d05b765ea94c 243 /* Step 4: Configure an Auto Refresh command */
fundokukiri 0:d05b765ea94c 244 Command.CommandMode = FMC_SDRAM_CMD_AUTOREFRESH_MODE;
fundokukiri 0:d05b765ea94c 245 Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
fundokukiri 0:d05b765ea94c 246 Command.AutoRefreshNumber = 8;
fundokukiri 0:d05b765ea94c 247 Command.ModeRegisterDefinition = 0;
fundokukiri 0:d05b765ea94c 248
fundokukiri 0:d05b765ea94c 249 /* Send the command */
fundokukiri 0:d05b765ea94c 250 HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
fundokukiri 0:d05b765ea94c 251
fundokukiri 0:d05b765ea94c 252 /* Step 5: Program the external memory mode register */
fundokukiri 0:d05b765ea94c 253 tmpmrd = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_1 |\
fundokukiri 0:d05b765ea94c 254 SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |\
fundokukiri 0:d05b765ea94c 255 SDRAM_MODEREG_CAS_LATENCY_2 |\
fundokukiri 0:d05b765ea94c 256 SDRAM_MODEREG_OPERATING_MODE_STANDARD |\
fundokukiri 0:d05b765ea94c 257 SDRAM_MODEREG_WRITEBURST_MODE_SINGLE;
fundokukiri 0:d05b765ea94c 258
fundokukiri 0:d05b765ea94c 259 Command.CommandMode = FMC_SDRAM_CMD_LOAD_MODE;
fundokukiri 0:d05b765ea94c 260 Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
fundokukiri 0:d05b765ea94c 261 Command.AutoRefreshNumber = 1;
fundokukiri 0:d05b765ea94c 262 Command.ModeRegisterDefinition = tmpmrd;
fundokukiri 0:d05b765ea94c 263
fundokukiri 0:d05b765ea94c 264 /* Send the command */
fundokukiri 0:d05b765ea94c 265 HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
fundokukiri 0:d05b765ea94c 266
fundokukiri 0:d05b765ea94c 267 /* Step 6: Set the refresh rate counter */
fundokukiri 0:d05b765ea94c 268 /* Set the device refresh rate */
fundokukiri 0:d05b765ea94c 269 HAL_SDRAM_ProgramRefreshRate(&sdramHandle, RefreshCount);
fundokukiri 0:d05b765ea94c 270 }
fundokukiri 0:d05b765ea94c 271
fundokukiri 0:d05b765ea94c 272 /**
fundokukiri 0:d05b765ea94c 273 * @brief Reads an amount of data from the SDRAM memory in polling mode.
fundokukiri 0:d05b765ea94c 274 * @param uwStartAddress: Read start address
fundokukiri 0:d05b765ea94c 275 * @param pData: Pointer to data to be read
fundokukiri 0:d05b765ea94c 276 * @param uwDataSize: Size of read data from the memory
fundokukiri 0:d05b765ea94c 277 * @retval SDRAM status
fundokukiri 0:d05b765ea94c 278 */
fundokukiri 0:d05b765ea94c 279 uint8_t BSP_SDRAM_ReadData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize)
fundokukiri 0:d05b765ea94c 280 {
fundokukiri 0:d05b765ea94c 281 if(HAL_SDRAM_Read_32b(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
fundokukiri 0:d05b765ea94c 282 {
fundokukiri 0:d05b765ea94c 283 return SDRAM_ERROR;
fundokukiri 0:d05b765ea94c 284 }
fundokukiri 0:d05b765ea94c 285 else
fundokukiri 0:d05b765ea94c 286 {
fundokukiri 0:d05b765ea94c 287 return SDRAM_OK;
fundokukiri 0:d05b765ea94c 288 }
fundokukiri 0:d05b765ea94c 289 }
fundokukiri 0:d05b765ea94c 290
fundokukiri 0:d05b765ea94c 291 /**
fundokukiri 0:d05b765ea94c 292 * @brief Reads an amount of data from the SDRAM memory in DMA mode.
fundokukiri 0:d05b765ea94c 293 * @param uwStartAddress: Read start address
fundokukiri 0:d05b765ea94c 294 * @param pData: Pointer to data to be read
fundokukiri 0:d05b765ea94c 295 * @param uwDataSize: Size of read data from the memory
fundokukiri 0:d05b765ea94c 296 * @retval SDRAM status
fundokukiri 0:d05b765ea94c 297 */
fundokukiri 0:d05b765ea94c 298 uint8_t BSP_SDRAM_ReadData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize)
fundokukiri 0:d05b765ea94c 299 {
fundokukiri 0:d05b765ea94c 300 if(HAL_SDRAM_Read_DMA(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
fundokukiri 0:d05b765ea94c 301 {
fundokukiri 0:d05b765ea94c 302 return SDRAM_ERROR;
fundokukiri 0:d05b765ea94c 303 }
fundokukiri 0:d05b765ea94c 304 else
fundokukiri 0:d05b765ea94c 305 {
fundokukiri 0:d05b765ea94c 306 return SDRAM_OK;
fundokukiri 0:d05b765ea94c 307 }
fundokukiri 0:d05b765ea94c 308 }
fundokukiri 0:d05b765ea94c 309
fundokukiri 0:d05b765ea94c 310 /**
fundokukiri 0:d05b765ea94c 311 * @brief Writes an amount of data to the SDRAM memory in polling mode.
fundokukiri 0:d05b765ea94c 312 * @param uwStartAddress: Write start address
fundokukiri 0:d05b765ea94c 313 * @param pData: Pointer to data to be written
fundokukiri 0:d05b765ea94c 314 * @param uwDataSize: Size of written data from the memory
fundokukiri 0:d05b765ea94c 315 * @retval SDRAM status
fundokukiri 0:d05b765ea94c 316 */
fundokukiri 0:d05b765ea94c 317 uint8_t BSP_SDRAM_WriteData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize)
fundokukiri 0:d05b765ea94c 318 {
fundokukiri 0:d05b765ea94c 319 if(HAL_SDRAM_Write_32b(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
fundokukiri 0:d05b765ea94c 320 {
fundokukiri 0:d05b765ea94c 321 return SDRAM_ERROR;
fundokukiri 0:d05b765ea94c 322 }
fundokukiri 0:d05b765ea94c 323 else
fundokukiri 0:d05b765ea94c 324 {
fundokukiri 0:d05b765ea94c 325 return SDRAM_OK;
fundokukiri 0:d05b765ea94c 326 }
fundokukiri 0:d05b765ea94c 327 }
fundokukiri 0:d05b765ea94c 328
fundokukiri 0:d05b765ea94c 329 /**
fundokukiri 0:d05b765ea94c 330 * @brief Writes an amount of data to the SDRAM memory in DMA mode.
fundokukiri 0:d05b765ea94c 331 * @param uwStartAddress: Write start address
fundokukiri 0:d05b765ea94c 332 * @param pData: Pointer to data to be written
fundokukiri 0:d05b765ea94c 333 * @param uwDataSize: Size of written data from the memory
fundokukiri 0:d05b765ea94c 334 * @retval SDRAM status
fundokukiri 0:d05b765ea94c 335 */
fundokukiri 0:d05b765ea94c 336 uint8_t BSP_SDRAM_WriteData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize)
fundokukiri 0:d05b765ea94c 337 {
fundokukiri 0:d05b765ea94c 338 if(HAL_SDRAM_Write_DMA(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
fundokukiri 0:d05b765ea94c 339 {
fundokukiri 0:d05b765ea94c 340 return SDRAM_ERROR;
fundokukiri 0:d05b765ea94c 341 }
fundokukiri 0:d05b765ea94c 342 else
fundokukiri 0:d05b765ea94c 343 {
fundokukiri 0:d05b765ea94c 344 return SDRAM_OK;
fundokukiri 0:d05b765ea94c 345 }
fundokukiri 0:d05b765ea94c 346 }
fundokukiri 0:d05b765ea94c 347
fundokukiri 0:d05b765ea94c 348 /**
fundokukiri 0:d05b765ea94c 349 * @brief Sends command to the SDRAM bank.
fundokukiri 0:d05b765ea94c 350 * @param SdramCmd: Pointer to SDRAM command structure
fundokukiri 0:d05b765ea94c 351 * @retval SDRAM status
fundokukiri 0:d05b765ea94c 352 */
fundokukiri 0:d05b765ea94c 353 uint8_t BSP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd)
fundokukiri 0:d05b765ea94c 354 {
fundokukiri 0:d05b765ea94c 355 if(HAL_SDRAM_SendCommand(&sdramHandle, SdramCmd, SDRAM_TIMEOUT) != HAL_OK)
fundokukiri 0:d05b765ea94c 356 {
fundokukiri 0:d05b765ea94c 357 return SDRAM_ERROR;
fundokukiri 0:d05b765ea94c 358 }
fundokukiri 0:d05b765ea94c 359 else
fundokukiri 0:d05b765ea94c 360 {
fundokukiri 0:d05b765ea94c 361 return SDRAM_OK;
fundokukiri 0:d05b765ea94c 362 }
fundokukiri 0:d05b765ea94c 363 }
fundokukiri 0:d05b765ea94c 364
fundokukiri 0:d05b765ea94c 365 /**
fundokukiri 0:d05b765ea94c 366 * @brief Initializes SDRAM MSP.
fundokukiri 0:d05b765ea94c 367 * @param hsdram: SDRAM handle
fundokukiri 0:d05b765ea94c 368 * @param Params
fundokukiri 0:d05b765ea94c 369 * @retval None
fundokukiri 0:d05b765ea94c 370 */
fundokukiri 0:d05b765ea94c 371 __weak void BSP_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram, void *Params)
fundokukiri 0:d05b765ea94c 372 {
fundokukiri 0:d05b765ea94c 373 static DMA_HandleTypeDef dma_handle;
fundokukiri 0:d05b765ea94c 374 GPIO_InitTypeDef gpio_init_structure;
fundokukiri 0:d05b765ea94c 375
fundokukiri 0:d05b765ea94c 376 /* Enable FMC clock */
fundokukiri 0:d05b765ea94c 377 __HAL_RCC_FMC_CLK_ENABLE();
fundokukiri 0:d05b765ea94c 378
fundokukiri 0:d05b765ea94c 379 /* Enable chosen DMAx clock */
fundokukiri 0:d05b765ea94c 380 __DMAx_CLK_ENABLE();
fundokukiri 0:d05b765ea94c 381
fundokukiri 0:d05b765ea94c 382 /* Enable GPIOs clock */
fundokukiri 0:d05b765ea94c 383 __HAL_RCC_GPIOC_CLK_ENABLE();
fundokukiri 0:d05b765ea94c 384 __HAL_RCC_GPIOD_CLK_ENABLE();
fundokukiri 0:d05b765ea94c 385 __HAL_RCC_GPIOE_CLK_ENABLE();
fundokukiri 0:d05b765ea94c 386 __HAL_RCC_GPIOF_CLK_ENABLE();
fundokukiri 0:d05b765ea94c 387 __HAL_RCC_GPIOG_CLK_ENABLE();
fundokukiri 0:d05b765ea94c 388 __HAL_RCC_GPIOH_CLK_ENABLE();
fundokukiri 0:d05b765ea94c 389
fundokukiri 0:d05b765ea94c 390 /* Common GPIO configuration */
fundokukiri 0:d05b765ea94c 391 gpio_init_structure.Mode = GPIO_MODE_AF_PP;
fundokukiri 0:d05b765ea94c 392 gpio_init_structure.Pull = GPIO_PULLUP;
fundokukiri 0:d05b765ea94c 393 gpio_init_structure.Speed = GPIO_SPEED_FAST;
fundokukiri 0:d05b765ea94c 394 gpio_init_structure.Alternate = GPIO_AF12_FMC;
fundokukiri 0:d05b765ea94c 395
fundokukiri 0:d05b765ea94c 396 /* GPIOC configuration */
fundokukiri 0:d05b765ea94c 397 gpio_init_structure.Pin = GPIO_PIN_3;
fundokukiri 0:d05b765ea94c 398 HAL_GPIO_Init(GPIOC, &gpio_init_structure);
fundokukiri 0:d05b765ea94c 399
fundokukiri 0:d05b765ea94c 400 /* GPIOD configuration */
fundokukiri 0:d05b765ea94c 401 gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_8 | GPIO_PIN_9 |
fundokukiri 0:d05b765ea94c 402 GPIO_PIN_10 | GPIO_PIN_14 | GPIO_PIN_15;
fundokukiri 0:d05b765ea94c 403 HAL_GPIO_Init(GPIOD, &gpio_init_structure);
fundokukiri 0:d05b765ea94c 404
fundokukiri 0:d05b765ea94c 405 /* GPIOE configuration */
fundokukiri 0:d05b765ea94c 406 gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_7| GPIO_PIN_8 | GPIO_PIN_9 |\
fundokukiri 0:d05b765ea94c 407 GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\
fundokukiri 0:d05b765ea94c 408 GPIO_PIN_15;
fundokukiri 0:d05b765ea94c 409 HAL_GPIO_Init(GPIOE, &gpio_init_structure);
fundokukiri 0:d05b765ea94c 410
fundokukiri 0:d05b765ea94c 411 /* GPIOF configuration */
fundokukiri 0:d05b765ea94c 412 gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2| GPIO_PIN_3 | GPIO_PIN_4 |\
fundokukiri 0:d05b765ea94c 413 GPIO_PIN_5 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\
fundokukiri 0:d05b765ea94c 414 GPIO_PIN_15;
fundokukiri 0:d05b765ea94c 415 HAL_GPIO_Init(GPIOF, &gpio_init_structure);
fundokukiri 0:d05b765ea94c 416
fundokukiri 0:d05b765ea94c 417 /* GPIOG configuration */
fundokukiri 0:d05b765ea94c 418 gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_4| GPIO_PIN_5 | GPIO_PIN_8 |\
fundokukiri 0:d05b765ea94c 419 GPIO_PIN_15;
fundokukiri 0:d05b765ea94c 420 HAL_GPIO_Init(GPIOG, &gpio_init_structure);
fundokukiri 0:d05b765ea94c 421
fundokukiri 0:d05b765ea94c 422 /* GPIOH configuration */
fundokukiri 0:d05b765ea94c 423 gpio_init_structure.Pin = GPIO_PIN_3 | GPIO_PIN_5;
fundokukiri 0:d05b765ea94c 424 HAL_GPIO_Init(GPIOH, &gpio_init_structure);
fundokukiri 0:d05b765ea94c 425
fundokukiri 0:d05b765ea94c 426 /* Configure common DMA parameters */
fundokukiri 0:d05b765ea94c 427 dma_handle.Init.Channel = SDRAM_DMAx_CHANNEL;
fundokukiri 0:d05b765ea94c 428 dma_handle.Init.Direction = DMA_MEMORY_TO_MEMORY;
fundokukiri 0:d05b765ea94c 429 dma_handle.Init.PeriphInc = DMA_PINC_ENABLE;
fundokukiri 0:d05b765ea94c 430 dma_handle.Init.MemInc = DMA_MINC_ENABLE;
fundokukiri 0:d05b765ea94c 431 dma_handle.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
fundokukiri 0:d05b765ea94c 432 dma_handle.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
fundokukiri 0:d05b765ea94c 433 dma_handle.Init.Mode = DMA_NORMAL;
fundokukiri 0:d05b765ea94c 434 dma_handle.Init.Priority = DMA_PRIORITY_HIGH;
fundokukiri 0:d05b765ea94c 435 dma_handle.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
fundokukiri 0:d05b765ea94c 436 dma_handle.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
fundokukiri 0:d05b765ea94c 437 dma_handle.Init.MemBurst = DMA_MBURST_SINGLE;
fundokukiri 0:d05b765ea94c 438 dma_handle.Init.PeriphBurst = DMA_PBURST_SINGLE;
fundokukiri 0:d05b765ea94c 439
fundokukiri 0:d05b765ea94c 440 dma_handle.Instance = SDRAM_DMAx_STREAM;
fundokukiri 0:d05b765ea94c 441
fundokukiri 0:d05b765ea94c 442 /* Associate the DMA handle */
fundokukiri 0:d05b765ea94c 443 __HAL_LINKDMA(hsdram, hdma, dma_handle);
fundokukiri 0:d05b765ea94c 444
fundokukiri 0:d05b765ea94c 445 /* Deinitialize the stream for new transfer */
fundokukiri 0:d05b765ea94c 446 HAL_DMA_DeInit(&dma_handle);
fundokukiri 0:d05b765ea94c 447
fundokukiri 0:d05b765ea94c 448 /* Configure the DMA stream */
fundokukiri 0:d05b765ea94c 449 HAL_DMA_Init(&dma_handle);
fundokukiri 0:d05b765ea94c 450
fundokukiri 0:d05b765ea94c 451 /* NVIC configuration for DMA transfer complete interrupt */
fundokukiri 0:d05b765ea94c 452 HAL_NVIC_SetPriority(SDRAM_DMAx_IRQn, 0x0F, 0);
fundokukiri 0:d05b765ea94c 453 HAL_NVIC_EnableIRQ(SDRAM_DMAx_IRQn);
fundokukiri 0:d05b765ea94c 454 }
fundokukiri 0:d05b765ea94c 455
fundokukiri 0:d05b765ea94c 456 /**
fundokukiri 0:d05b765ea94c 457 * @brief DeInitializes SDRAM MSP.
fundokukiri 0:d05b765ea94c 458 * @param hsdram: SDRAM handle
fundokukiri 0:d05b765ea94c 459 * @param Params
fundokukiri 0:d05b765ea94c 460 * @retval None
fundokukiri 0:d05b765ea94c 461 */
fundokukiri 0:d05b765ea94c 462 __weak void BSP_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram, void *Params)
fundokukiri 0:d05b765ea94c 463 {
fundokukiri 0:d05b765ea94c 464 static DMA_HandleTypeDef dma_handle;
fundokukiri 0:d05b765ea94c 465
fundokukiri 0:d05b765ea94c 466 /* Disable NVIC configuration for DMA interrupt */
fundokukiri 0:d05b765ea94c 467 HAL_NVIC_DisableIRQ(SDRAM_DMAx_IRQn);
fundokukiri 0:d05b765ea94c 468
fundokukiri 0:d05b765ea94c 469 /* Deinitialize the stream for new transfer */
fundokukiri 0:d05b765ea94c 470 dma_handle.Instance = SDRAM_DMAx_STREAM;
fundokukiri 0:d05b765ea94c 471 HAL_DMA_DeInit(&dma_handle);
fundokukiri 0:d05b765ea94c 472
fundokukiri 0:d05b765ea94c 473 /* GPIO pins clock, FMC clock and DMA clock can be shut down in the applications
fundokukiri 0:d05b765ea94c 474 by surcharging this __weak function */
fundokukiri 0:d05b765ea94c 475 }
fundokukiri 0:d05b765ea94c 476
fundokukiri 0:d05b765ea94c 477 /**
fundokukiri 0:d05b765ea94c 478 * @}
fundokukiri 0:d05b765ea94c 479 */
fundokukiri 0:d05b765ea94c 480
fundokukiri 0:d05b765ea94c 481 /**
fundokukiri 0:d05b765ea94c 482 * @}
fundokukiri 0:d05b765ea94c 483 */
fundokukiri 0:d05b765ea94c 484
fundokukiri 0:d05b765ea94c 485 /**
fundokukiri 0:d05b765ea94c 486 * @}
fundokukiri 0:d05b765ea94c 487 */
fundokukiri 0:d05b765ea94c 488
fundokukiri 0:d05b765ea94c 489 /**
fundokukiri 0:d05b765ea94c 490 * @}
fundokukiri 0:d05b765ea94c 491 */
fundokukiri 0:d05b765ea94c 492
fundokukiri 0:d05b765ea94c 493 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/