lpc17xx_i2c.h

00001 /***********************************************************************//**
00002  * @file        lpc17xx_i2c.h
00003  * @brief        Contains all macro definitions and function prototypes
00004  *                 support for I2C firmware library on LPC17xx
00005  * @version        2.0
00006  * @date        21. May. 2010
00007  * @author        NXP MCU SW Application Team
00008  **************************************************************************
00009  * Software that is described herein is for illustrative purposes only
00010  * which provides customers with programming information regarding the
00011  * products. This software is supplied "AS IS" without any warranties.
00012  * NXP Semiconductors assumes no responsibility or liability for the
00013  * use of the software, conveys no license or title under any patent,
00014  * copyright, or mask work right to the product. NXP Semiconductors
00015  * reserves the right to make changes in the software without
00016  * notification. NXP Semiconductors also make no representation or
00017  * warranty that such application will be suitable for the specified
00018  * use without further testing or modification.
00019  **************************************************************************/
00020 
00021 /* Peripheral group ----------------------------------------------------------- */
00022 /** @defgroup I2C I2C
00023  * @ingroup LPC1700CMSIS_FwLib_Drivers
00024  * @{
00025  */
00026 
00027 #ifndef LPC17XX_I2C_H_
00028 #define LPC17XX_I2C_H_
00029 
00030 /* Includes ------------------------------------------------------------------- */
00031 #include "LPC17xx.h"
00032 #include "lpc_types.h"
00033 
00034 
00035 #ifdef __cplusplus
00036 extern "C"
00037 {
00038 #endif
00039 
00040 
00041 /* Private Macros ------------------------------------------------------------- */
00042 /** @defgroup I2C_Private_Macros I2C Private Macros
00043  * @{
00044  */
00045 
00046 /* --------------------- BIT DEFINITIONS -------------------------------------- */
00047 /*******************************************************************//**
00048  * I2C Control Set register description
00049  *********************************************************************/
00050 #define I2C_I2CONSET_AA                ((0x04)) /*!< Assert acknowledge flag */
00051 #define I2C_I2CONSET_SI                ((0x08)) /*!< I2C interrupt flag */
00052 #define I2C_I2CONSET_STO            ((0x10)) /*!< STOP flag */
00053 #define I2C_I2CONSET_STA            ((0x20)) /*!< START flag */
00054 #define I2C_I2CONSET_I2EN            ((0x40)) /*!< I2C interface enable */
00055 
00056 /*******************************************************************//**
00057  * I2C Control Clear register description
00058  *********************************************************************/
00059 /** Assert acknowledge Clear bit */
00060 #define I2C_I2CONCLR_AAC            ((1<<2))
00061 /** I2C interrupt Clear bit */
00062 #define I2C_I2CONCLR_SIC            ((1<<3))
00063 /** START flag Clear bit */
00064 #define I2C_I2CONCLR_STAC            ((1<<5))
00065 /** I2C interface Disable bit */
00066 #define I2C_I2CONCLR_I2ENC            ((1<<6))
00067 
00068 /********************************************************************//**
00069  * I2C Status Code definition (I2C Status register)
00070  *********************************************************************/
00071 /* Return Code in I2C status register */
00072 #define I2C_STAT_CODE_BITMASK        ((0xF8))
00073 
00074 /* I2C return status code definitions ----------------------------- */
00075 
00076 /** No relevant information */
00077 #define I2C_I2STAT_NO_INF                        ((0xF8))
00078 
00079 /* Master transmit mode -------------------------------------------- */
00080 /** A start condition has been transmitted */
00081 #define I2C_I2STAT_M_TX_START                    ((0x08))
00082 /** A repeat start condition has been transmitted */
00083 #define I2C_I2STAT_M_TX_RESTART                    ((0x10))
00084 /** SLA+W has been transmitted, ACK has been received */
00085 #define I2C_I2STAT_M_TX_SLAW_ACK                ((0x18))
00086 /** SLA+W has been transmitted, NACK has been received */
00087 #define I2C_I2STAT_M_TX_SLAW_NACK                ((0x20))
00088 /** Data has been transmitted, ACK has been received */
00089 #define I2C_I2STAT_M_TX_DAT_ACK                    ((0x28))
00090 /** Data has been transmitted, NACK has been received */
00091 #define I2C_I2STAT_M_TX_DAT_NACK                ((0x30))
00092 /** Arbitration lost in SLA+R/W or Data bytes */
00093 #define I2C_I2STAT_M_TX_ARB_LOST                ((0x38))
00094 
00095 /* Master receive mode -------------------------------------------- */
00096 /** A start condition has been transmitted */
00097 #define I2C_I2STAT_M_RX_START                    ((0x08))
00098 /** A repeat start condition has been transmitted */
00099 #define I2C_I2STAT_M_RX_RESTART                    ((0x10))
00100 /** Arbitration lost */
00101 #define I2C_I2STAT_M_RX_ARB_LOST                ((0x38))
00102 /** SLA+R has been transmitted, ACK has been received */
00103 #define I2C_I2STAT_M_RX_SLAR_ACK                ((0x40))
00104 /** SLA+R has been transmitted, NACK has been received */
00105 #define I2C_I2STAT_M_RX_SLAR_NACK                ((0x48))
00106 /** Data has been received, ACK has been returned */
00107 #define I2C_I2STAT_M_RX_DAT_ACK                    ((0x50))
00108 /** Data has been received, NACK has been return */
00109 #define I2C_I2STAT_M_RX_DAT_NACK                ((0x58))
00110 
00111 /* Slave receive mode -------------------------------------------- */
00112 /** Own slave address has been received, ACK has been returned */
00113 #define I2C_I2STAT_S_RX_SLAW_ACK                ((0x60))
00114 
00115 /** Arbitration lost in SLA+R/W as master */
00116 #define I2C_I2STAT_S_RX_ARB_LOST_M_SLA            ((0x68))
00117 /** Own SLA+W has been received, ACK returned */
00118 //#define I2C_I2STAT_S_RX_SLAW_ACK                ((0x68))
00119 
00120 /** General call address has been received, ACK has been returned */
00121 #define I2C_I2STAT_S_RX_GENCALL_ACK                ((0x70))
00122 
00123 /** Arbitration lost in SLA+R/W (GENERAL CALL) as master */
00124 #define I2C_I2STAT_S_RX_ARB_LOST_M_GENCALL        ((0x78))
00125 /** General call address has been received, ACK has been returned */
00126 //#define I2C_I2STAT_S_RX_GENCALL_ACK                ((0x78))
00127 
00128 /** Previously addressed with own SLV address;
00129  * Data has been received, ACK has been return */
00130 #define I2C_I2STAT_S_RX_PRE_SLA_DAT_ACK            ((0x80))
00131 /** Previously addressed with own SLA;
00132  * Data has been received and NOT ACK has been return */
00133 #define I2C_I2STAT_S_RX_PRE_SLA_DAT_NACK        ((0x88))
00134 /** Previously addressed with General Call;
00135  * Data has been received and ACK has been return */
00136 #define I2C_I2STAT_S_RX_PRE_GENCALL_DAT_ACK        ((0x90))
00137 /** Previously addressed with General Call;
00138  * Data has been received and NOT ACK has been return */
00139 #define I2C_I2STAT_S_RX_PRE_GENCALL_DAT_NACK    ((0x98))
00140 /** A STOP condition or repeated START condition has
00141  * been received while still addressed as SLV/REC
00142  * (Slave Receive) or SLV/TRX (Slave Transmit) */
00143 #define I2C_I2STAT_S_RX_STA_STO_SLVREC_SLVTRX    ((0xA0))
00144 
00145 /** Slave transmit mode */
00146 /** Own SLA+R has been received, ACK has been returned */
00147 #define I2C_I2STAT_S_TX_SLAR_ACK                ((0xA8))
00148 
00149 /** Arbitration lost in SLA+R/W as master */
00150 #define I2C_I2STAT_S_TX_ARB_LOST_M_SLA            ((0xB0))
00151 /** Own SLA+R has been received, ACK has been returned */
00152 //#define I2C_I2STAT_S_TX_SLAR_ACK                ((0xB0))
00153 
00154 /** Data has been transmitted, ACK has been received */
00155 #define I2C_I2STAT_S_TX_DAT_ACK                    ((0xB8))
00156 /** Data has been transmitted, NACK has been received */
00157 #define I2C_I2STAT_S_TX_DAT_NACK                ((0xC0))
00158 /** Last data byte in I2DAT has been transmitted (AA = 0);
00159  ACK has been received */
00160 #define I2C_I2STAT_S_TX_LAST_DAT_ACK            ((0xC8))
00161 
00162 /** Time out in case of using I2C slave mode */
00163 #define I2C_SLAVE_TIME_OUT                        0x10000UL
00164 
00165 /********************************************************************//**
00166  * I2C Data register definition
00167  *********************************************************************/
00168 /** Mask for I2DAT register*/
00169 #define I2C_I2DAT_BITMASK            ((0xFF))
00170 
00171 /** Idle data value will be send out in slave mode in case of the actual
00172  * expecting data requested from the master is greater than its sending data
00173  * length that can be supported */
00174 #define I2C_I2DAT_IDLE_CHAR            (0xFF)
00175 
00176 /********************************************************************//**
00177  * I2C Monitor mode control register description
00178  *********************************************************************/
00179 #define I2C_I2MMCTRL_MM_ENA            ((1<<0))        /**< Monitor mode enable */
00180 #define I2C_I2MMCTRL_ENA_SCL        ((1<<1))        /**< SCL output enable */
00181 #define I2C_I2MMCTRL_MATCH_ALL        ((1<<2))        /**< Select interrupt register match */
00182 #define I2C_I2MMCTRL_BITMASK        ((0x07))        /**< Mask for I2MMCTRL register */
00183 
00184 /********************************************************************//**
00185  * I2C Data buffer register description
00186  *********************************************************************/
00187 /** I2C Data buffer register bit mask */
00188 #define I2DATA_BUFFER_BITMASK        ((0xFF))
00189 
00190 /********************************************************************//**
00191  * I2C Slave Address registers definition
00192  *********************************************************************/
00193 /** General Call enable bit */
00194 #define I2C_I2ADR_GC                ((1<<0))
00195 /** I2C Slave Address registers bit mask */
00196 #define I2C_I2ADR_BITMASK            ((0xFF))
00197 
00198 /********************************************************************//**
00199  * I2C Mask Register definition
00200  *********************************************************************/
00201 /** I2C Mask Register mask field */
00202 #define I2C_I2MASK_MASK(n)            ((n&0xFE))
00203 
00204 /********************************************************************//**
00205  * I2C SCL HIGH duty cycle Register definition
00206  *********************************************************************/
00207 /** I2C SCL HIGH duty cycle Register bit mask */
00208 #define I2C_I2SCLH_BITMASK            ((0xFFFF))
00209 
00210 /********************************************************************//**
00211  * I2C SCL LOW duty cycle Register definition
00212  *********************************************************************/
00213 /** I2C SCL LOW duty cycle Register bit mask */
00214 #define I2C_I2SCLL_BITMASK            ((0xFFFF))
00215 
00216 /* I2C status values */
00217 #define I2C_SETUP_STATUS_ARBF   (1<<8)    /**< Arbitration false */
00218 #define I2C_SETUP_STATUS_NOACKF (1<<9)    /**< No ACK returned */
00219 #define I2C_SETUP_STATUS_DONE   (1<<10)    /**< Status DONE */
00220 
00221 /*********************************************************************//**
00222  * I2C monitor control configuration defines
00223  **********************************************************************/
00224 #define I2C_MONITOR_CFG_SCL_OUTPUT    I2C_I2MMCTRL_ENA_SCL        /**< SCL output enable */
00225 #define I2C_MONITOR_CFG_MATCHALL    I2C_I2MMCTRL_MATCH_ALL        /**< Select interrupt register match */
00226 
00227 /* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
00228 /* Macros check I2C slave address */
00229 #define PARAM_I2C_SLAVEADDR_CH(n)    ((n)<=3)
00230 
00231 /** Macro to determine if it is valid SSP port number */
00232 #define PARAM_I2Cx(n)    ((((uint32_t *)n)==((uint32_t *)LPC_I2C0)) \
00233 || (((uint32_t *)n)==((uint32_t *)LPC_I2C1)) \
00234 || (((uint32_t *)n)==((uint32_t *)LPC_I2C2)))
00235 
00236 /* Macros check I2C monitor configuration type */
00237 #define PARAM_I2C_MONITOR_CFG(n) ((n==I2C_MONITOR_CFG_SCL_OUTPUT) || (I2C_MONITOR_CFG_MATCHALL))
00238 
00239 /**
00240  * @}
00241  */
00242 
00243 
00244 
00245 /* Public Types --------------------------------------------------------------- */
00246 /** @defgroup I2C_Public_Types I2C Public Types
00247  * @{
00248  */
00249 
00250 /**
00251  * @brief I2C Own slave address setting structure
00252  */
00253 typedef struct {
00254     uint8_t SlaveAddrChannel;    /**< Slave Address channel in I2C control,
00255                                 should be in range from 0..3
00256                                 */
00257     uint8_t SlaveAddr_7bit;        /**< Value of 7-bit slave address */
00258     uint8_t GeneralCallState;    /**< Enable/Disable General Call Functionality
00259                                 when I2C control being in Slave mode, should be:
00260                                 - ENABLE: Enable General Call function.
00261                                 - DISABLE: Disable General Call function.
00262                                 */
00263     uint8_t SlaveAddrMaskValue;    /**< Any bit in this 8-bit value (bit 7:1)
00264                                 which is set to '1' will cause an automatic compare on
00265                                 the corresponding bit of the received address when it
00266                                 is compared to the SlaveAddr_7bit value associated with this
00267                                 mask register. In other words, bits in SlaveAddr_7bit value
00268                                 which are masked are not taken into account in determining
00269                                 an address match
00270                                 */
00271 } I2C_OWNSLAVEADDR_CFG_Type;
00272 
00273 
00274 /**
00275  * @brief Master transfer setup data structure definitions
00276  */
00277 typedef struct
00278 {
00279   uint32_t          sl_addr7bit;                /**< Slave address in 7bit mode */
00280   uint8_t*          tx_data;                    /**< Pointer to Transmit data - NULL if data transmit
00281                                                       is not used */
00282   uint32_t          tx_length;                    /**< Transmit data length - 0 if data transmit
00283                                                       is not used*/
00284   uint32_t          tx_count;                    /**< Current Transmit data counter */
00285   uint8_t*          rx_data;                    /**< Pointer to Receive data - NULL if data receive
00286                                                       is not used */
00287   uint32_t          rx_length;                    /**< Receive data length - 0 if data receive is
00288                                                        not used */
00289   uint32_t          rx_count;                    /**< Current Receive data counter */
00290   uint32_t          retransmissions_max;        /**< Max Re-Transmission value */
00291   uint32_t          retransmissions_count;        /**< Current Re-Transmission counter */
00292   uint32_t          status;                        /**< Current status of I2C activity */
00293   void                 (*callback)(void);            /**< Pointer to Call back function when transmission complete
00294                                                     used in interrupt transfer mode */
00295 } I2C_M_SETUP_Type;
00296 
00297 
00298 /**
00299  * @brief Slave transfer setup data structure definitions
00300  */
00301 typedef struct
00302 {
00303   uint8_t*          tx_data;
00304   uint32_t          tx_length;
00305   uint32_t          tx_count;
00306   uint8_t*          rx_data;
00307   uint32_t          rx_length;
00308   uint32_t          rx_count;
00309   uint32_t          status;
00310   void                 (*callback)(void);
00311 } I2C_S_SETUP_Type;
00312 
00313 /**
00314  * @brief Transfer option type definitions
00315  */
00316 typedef enum {
00317     I2C_TRANSFER_POLLING = 0,        /**< Transfer in polling mode */
00318     I2C_TRANSFER_INTERRUPT            /**< Transfer in interrupt mode */
00319 } I2C_TRANSFER_OPT_Type;
00320 
00321 
00322 /**
00323  * @}
00324  */
00325 
00326 
00327 /* Public Functions ----------------------------------------------------------- */
00328 /** @defgroup I2C_Public_Functions I2C Public Functions
00329  * @{
00330  */
00331 
00332 /* I2C Init/DeInit functions ---------- */
00333 void I2C_Init(LPC_I2C_TypeDef *I2Cx, uint32_t clockrate);
00334 void I2C_DeInit(LPC_I2C_TypeDef* I2Cx);
00335 //void I2C_SetClock (LPC_I2C_TypeDef *I2Cx, uint32_t target_clock);
00336 void I2C_Cmd(LPC_I2C_TypeDef* I2Cx, FunctionalState NewState);
00337 
00338 /* I2C transfer data functions -------- */
00339 Status I2C_MasterTransferData(LPC_I2C_TypeDef *I2Cx, \
00340         I2C_M_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt);
00341 Status I2C_SlaveTransferData(LPC_I2C_TypeDef *I2Cx, \
00342         I2C_S_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt);
00343 uint32_t I2C_MasterTransferComplete(LPC_I2C_TypeDef *I2Cx);
00344 uint32_t I2C_SlaveTransferComplete(LPC_I2C_TypeDef *I2Cx);
00345 
00346 
00347 void I2C_SetOwnSlaveAddr(LPC_I2C_TypeDef *I2Cx, I2C_OWNSLAVEADDR_CFG_Type *OwnSlaveAddrConfigStruct);
00348 uint8_t I2C_GetLastStatusCode(LPC_I2C_TypeDef* I2Cx);
00349 
00350 /* I2C Monitor functions ---------------*/
00351 void I2C_MonitorModeConfig(LPC_I2C_TypeDef *I2Cx, uint32_t MonitorCfgType, FunctionalState NewState);
00352 void I2C_MonitorModeCmd(LPC_I2C_TypeDef *I2Cx, FunctionalState NewState);
00353 uint8_t I2C_MonitorGetDatabuffer(LPC_I2C_TypeDef *I2Cx);
00354 BOOL_8 I2C_MonitorHandler(LPC_I2C_TypeDef *I2Cx, uint8_t *buffer, uint32_t size);
00355 
00356 /* I2C Interrupt handler functions ------*/
00357 void I2C_IntCmd (LPC_I2C_TypeDef *I2Cx, Bool NewState);
00358 void I2C_MasterHandler (LPC_I2C_TypeDef *I2Cx);
00359 void I2C_SlaveHandler (LPC_I2C_TypeDef *I2Cx);
00360 
00361 
00362 /**
00363  * @}
00364  */
00365 
00366 
00367 #ifdef __cplusplus
00368 }
00369 #endif
00370 
00371 #endif /* LPC17XX_I2C_H_ */
00372 
00373 /**
00374  * @}
00375  */
00376 
00377 /* --------------------------------- End Of File ------------------------------ */