Frank 26080115
Date: March 20, 2011 This library is created from "LPC17xx CMSIS-Compliant Standard Peripheral Firmware Driver Library (GNU, Keil, IAR) (Jan 28, 2011)", available from NXP's website, under "All microcontrollers support documents" [[http://ics.nxp.com/support/documents/microcontrollers/?type=software]] You will need to follow [[/projects/libraries/svn/mbed/trunk/LPC1768/LPC17xx.h]] while using this library Examples provided here [[/users/frank26080115/programs/LPC1700CMSIS_Examples/]] The beautiful thing is that NXP does not place copyright protection on any of the files in here Only a few modifications are made to make it compile with the mbed online compiler, I fixed some warnings as well. This is untested as of March 20, 2011 Forum post about this library: [[/forum/mbed/topic/2030/]]
lpc17xx_i2s.h@0:84d7747641aa, 2011-03-20 (annotated)
- Committer:
- frank26080115
- Date:
- Sun Mar 20 18:45:15 2011 +0000
- Revision:
- 0:84d7747641aa
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| frank26080115 | 0:84d7747641aa | 1 | /***********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 2 | * @file lpc17xx_i2s.h |
| frank26080115 | 0:84d7747641aa | 3 | * @brief Contains all macro definitions and function prototypes |
| frank26080115 | 0:84d7747641aa | 4 | * support for I2S firmware library on LPC17xx |
| frank26080115 | 0:84d7747641aa | 5 | * @version 3.0 |
| frank26080115 | 0:84d7747641aa | 6 | * @date 18. June. 2010 |
| frank26080115 | 0:84d7747641aa | 7 | * @author NXP MCU SW Application Team |
| frank26080115 | 0:84d7747641aa | 8 | ************************************************************************** |
| frank26080115 | 0:84d7747641aa | 9 | * Software that is described herein is for illustrative purposes only |
| frank26080115 | 0:84d7747641aa | 10 | * which provides customers with programming information regarding the |
| frank26080115 | 0:84d7747641aa | 11 | * products. This software is supplied "AS IS" without any warranties. |
| frank26080115 | 0:84d7747641aa | 12 | * NXP Semiconductors assumes no responsibility or liability for the |
| frank26080115 | 0:84d7747641aa | 13 | * use of the software, conveys no license or title under any patent, |
| frank26080115 | 0:84d7747641aa | 14 | * copyright, or mask work right to the product. NXP Semiconductors |
| frank26080115 | 0:84d7747641aa | 15 | * reserves the right to make changes in the software without |
| frank26080115 | 0:84d7747641aa | 16 | * notification. NXP Semiconductors also make no representation or |
| frank26080115 | 0:84d7747641aa | 17 | * warranty that such application will be suitable for the specified |
| frank26080115 | 0:84d7747641aa | 18 | * use without further testing or modification. |
| frank26080115 | 0:84d7747641aa | 19 | **************************************************************************/ |
| frank26080115 | 0:84d7747641aa | 20 | |
| frank26080115 | 0:84d7747641aa | 21 | /* Peripheral group ----------------------------------------------------------- */ |
| frank26080115 | 0:84d7747641aa | 22 | /** @defgroup I2S I2S |
| frank26080115 | 0:84d7747641aa | 23 | * @ingroup LPC1700CMSIS_FwLib_Drivers |
| frank26080115 | 0:84d7747641aa | 24 | * @{ |
| frank26080115 | 0:84d7747641aa | 25 | */ |
| frank26080115 | 0:84d7747641aa | 26 | |
| frank26080115 | 0:84d7747641aa | 27 | #ifndef LPC17XX_I2S_H_ |
| frank26080115 | 0:84d7747641aa | 28 | #define LPC17XX_I2S_H_ |
| frank26080115 | 0:84d7747641aa | 29 | |
| frank26080115 | 0:84d7747641aa | 30 | /* Includes ------------------------------------------------------------------- */ |
| frank26080115 | 0:84d7747641aa | 31 | #include "LPC17xx.h" |
| frank26080115 | 0:84d7747641aa | 32 | #include "lpc_types.h" |
| frank26080115 | 0:84d7747641aa | 33 | |
| frank26080115 | 0:84d7747641aa | 34 | |
| frank26080115 | 0:84d7747641aa | 35 | #ifdef __cplusplus |
| frank26080115 | 0:84d7747641aa | 36 | extern "C" |
| frank26080115 | 0:84d7747641aa | 37 | { |
| frank26080115 | 0:84d7747641aa | 38 | #endif |
| frank26080115 | 0:84d7747641aa | 39 | |
| frank26080115 | 0:84d7747641aa | 40 | /* Public Macros -------------------------------------------------------------- */ |
| frank26080115 | 0:84d7747641aa | 41 | /** @defgroup I2S_Public_Macros I2S Public Macros |
| frank26080115 | 0:84d7747641aa | 42 | * @{ |
| frank26080115 | 0:84d7747641aa | 43 | */ |
| frank26080115 | 0:84d7747641aa | 44 | |
| frank26080115 | 0:84d7747641aa | 45 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 46 | * I2S configuration parameter defines |
| frank26080115 | 0:84d7747641aa | 47 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 48 | /** I2S Wordwidth bit */ |
| frank26080115 | 0:84d7747641aa | 49 | #define I2S_WORDWIDTH_8 ((uint32_t)(0)) |
| frank26080115 | 0:84d7747641aa | 50 | #define I2S_WORDWIDTH_16 ((uint32_t)(1)) |
| frank26080115 | 0:84d7747641aa | 51 | #define I2S_WORDWIDTH_32 ((uint32_t)(3)) |
| frank26080115 | 0:84d7747641aa | 52 | /** I2S Channel bit */ |
| frank26080115 | 0:84d7747641aa | 53 | #define I2S_STEREO ((uint32_t)(0)) |
| frank26080115 | 0:84d7747641aa | 54 | #define I2S_MONO ((uint32_t)(1)) |
| frank26080115 | 0:84d7747641aa | 55 | /** I2S Master/Slave mode bit */ |
| frank26080115 | 0:84d7747641aa | 56 | #define I2S_MASTER_MODE ((uint8_t)(0)) |
| frank26080115 | 0:84d7747641aa | 57 | #define I2S_SLAVE_MODE ((uint8_t)(1)) |
| frank26080115 | 0:84d7747641aa | 58 | /** I2S Stop bit */ |
| frank26080115 | 0:84d7747641aa | 59 | #define I2S_STOP_ENABLE ((uint8_t)(1)) |
| frank26080115 | 0:84d7747641aa | 60 | #define I2S_STOP_DISABLE ((uint8_t)(0)) |
| frank26080115 | 0:84d7747641aa | 61 | /** I2S Reset bit */ |
| frank26080115 | 0:84d7747641aa | 62 | #define I2S_RESET_ENABLE ((uint8_t)(1)) |
| frank26080115 | 0:84d7747641aa | 63 | #define I2S_RESET_DISABLE ((uint8_t)(0)) |
| frank26080115 | 0:84d7747641aa | 64 | /** I2S Mute bit */ |
| frank26080115 | 0:84d7747641aa | 65 | #define I2S_MUTE_ENABLE ((uint8_t)(1)) |
| frank26080115 | 0:84d7747641aa | 66 | #define I2S_MUTE_DISABLE ((uint8_t)(0)) |
| frank26080115 | 0:84d7747641aa | 67 | /** I2S Transmit/Receive bit */ |
| frank26080115 | 0:84d7747641aa | 68 | #define I2S_TX_MODE ((uint8_t)(0)) |
| frank26080115 | 0:84d7747641aa | 69 | #define I2S_RX_MODE ((uint8_t)(1)) |
| frank26080115 | 0:84d7747641aa | 70 | /** I2S Clock Select bit */ |
| frank26080115 | 0:84d7747641aa | 71 | #define I2S_CLKSEL_FRDCLK ((uint8_t)(0)) |
| frank26080115 | 0:84d7747641aa | 72 | #define I2S_CLKSEL_MCLK ((uint8_t)(2)) |
| frank26080115 | 0:84d7747641aa | 73 | /** I2S 4-pin Mode bit */ |
| frank26080115 | 0:84d7747641aa | 74 | #define I2S_4PIN_ENABLE ((uint8_t)(1)) |
| frank26080115 | 0:84d7747641aa | 75 | #define I2S_4PIN_DISABLE ((uint8_t)(0)) |
| frank26080115 | 0:84d7747641aa | 76 | /** I2S MCLK Enable bit */ |
| frank26080115 | 0:84d7747641aa | 77 | #define I2S_MCLK_ENABLE ((uint8_t)(1)) |
| frank26080115 | 0:84d7747641aa | 78 | #define I2S_MCLK_DISABLE ((uint8_t)(0)) |
| frank26080115 | 0:84d7747641aa | 79 | /** I2S select DMA bit */ |
| frank26080115 | 0:84d7747641aa | 80 | #define I2S_DMA_1 ((uint8_t)(0)) |
| frank26080115 | 0:84d7747641aa | 81 | #define I2S_DMA_2 ((uint8_t)(1)) |
| frank26080115 | 0:84d7747641aa | 82 | |
| frank26080115 | 0:84d7747641aa | 83 | /** |
| frank26080115 | 0:84d7747641aa | 84 | * @} |
| frank26080115 | 0:84d7747641aa | 85 | */ |
| frank26080115 | 0:84d7747641aa | 86 | |
| frank26080115 | 0:84d7747641aa | 87 | /* Private Macros ------------------------------------------------------------- */ |
| frank26080115 | 0:84d7747641aa | 88 | /** @defgroup I2S_Private_Macros I2S Private Macros |
| frank26080115 | 0:84d7747641aa | 89 | * @{ |
| frank26080115 | 0:84d7747641aa | 90 | */ |
| frank26080115 | 0:84d7747641aa | 91 | |
| frank26080115 | 0:84d7747641aa | 92 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 93 | * Macro defines for DAO-Digital Audio Output register |
| frank26080115 | 0:84d7747641aa | 94 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 95 | /** I2S wordwide - the number of bytes in data*/ |
| frank26080115 | 0:84d7747641aa | 96 | #define I2S_DAO_WORDWIDTH_8 ((uint32_t)(0)) /** 8 bit */ |
| frank26080115 | 0:84d7747641aa | 97 | #define I2S_DAO_WORDWIDTH_16 ((uint32_t)(1)) /** 16 bit */ |
| frank26080115 | 0:84d7747641aa | 98 | #define I2S_DAO_WORDWIDTH_32 ((uint32_t)(3)) /** 32 bit */ |
| frank26080115 | 0:84d7747641aa | 99 | /** I2S control mono or stereo format */ |
| frank26080115 | 0:84d7747641aa | 100 | #define I2S_DAO_MONO ((uint32_t)(1<<2)) |
| frank26080115 | 0:84d7747641aa | 101 | /** I2S control stop mode */ |
| frank26080115 | 0:84d7747641aa | 102 | #define I2S_DAO_STOP ((uint32_t)(1<<3)) |
| frank26080115 | 0:84d7747641aa | 103 | /** I2S control reset mode */ |
| frank26080115 | 0:84d7747641aa | 104 | #define I2S_DAO_RESET ((uint32_t)(1<<4)) |
| frank26080115 | 0:84d7747641aa | 105 | /** I2S control master/slave mode */ |
| frank26080115 | 0:84d7747641aa | 106 | #define I2S_DAO_SLAVE ((uint32_t)(1<<5)) |
| frank26080115 | 0:84d7747641aa | 107 | /** I2S word select half period minus one */ |
| frank26080115 | 0:84d7747641aa | 108 | #define I2S_DAO_WS_HALFPERIOD(n) ((uint32_t)(n<<6)) |
| frank26080115 | 0:84d7747641aa | 109 | /** I2S control mute mode */ |
| frank26080115 | 0:84d7747641aa | 110 | #define I2S_DAO_MUTE ((uint32_t)(1<<15)) |
| frank26080115 | 0:84d7747641aa | 111 | |
| frank26080115 | 0:84d7747641aa | 112 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 113 | * Macro defines for DAI-Digital Audio Input register |
| frank26080115 | 0:84d7747641aa | 114 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 115 | /** I2S wordwide - the number of bytes in data*/ |
| frank26080115 | 0:84d7747641aa | 116 | #define I2S_DAI_WORDWIDTH_8 ((uint32_t)(0)) /** 8 bit */ |
| frank26080115 | 0:84d7747641aa | 117 | #define I2S_DAI_WORDWIDTH_16 ((uint32_t)(1)) /** 16 bit */ |
| frank26080115 | 0:84d7747641aa | 118 | #define I2S_DAI_WORDWIDTH_32 ((uint32_t)(3)) /** 32 bit */ |
| frank26080115 | 0:84d7747641aa | 119 | /** I2S control mono or stereo format */ |
| frank26080115 | 0:84d7747641aa | 120 | #define I2S_DAI_MONO ((uint32_t)(1<<2)) |
| frank26080115 | 0:84d7747641aa | 121 | /** I2S control stop mode */ |
| frank26080115 | 0:84d7747641aa | 122 | #define I2S_DAI_STOP ((uint32_t)(1<<3)) |
| frank26080115 | 0:84d7747641aa | 123 | /** I2S control reset mode */ |
| frank26080115 | 0:84d7747641aa | 124 | #define I2S_DAI_RESET ((uint32_t)(1<<4)) |
| frank26080115 | 0:84d7747641aa | 125 | /** I2S control master/slave mode */ |
| frank26080115 | 0:84d7747641aa | 126 | #define I2S_DAI_SLAVE ((uint32_t)(1<<5)) |
| frank26080115 | 0:84d7747641aa | 127 | /** I2S word select half period minus one (9 bits)*/ |
| frank26080115 | 0:84d7747641aa | 128 | #define I2S_DAI_WS_HALFPERIOD(n) ((uint32_t)((n&0x1FF)<<6)) |
| frank26080115 | 0:84d7747641aa | 129 | /** I2S control mute mode */ |
| frank26080115 | 0:84d7747641aa | 130 | #define I2S_DAI_MUTE ((uint32_t)(1<<15)) |
| frank26080115 | 0:84d7747641aa | 131 | |
| frank26080115 | 0:84d7747641aa | 132 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 133 | * Macro defines for STAT register (Status Feedback register) |
| frank26080115 | 0:84d7747641aa | 134 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 135 | /** I2S Status Receive or Transmit Interrupt */ |
| frank26080115 | 0:84d7747641aa | 136 | #define I2S_STATE_IRQ ((uint32_t)(1)) |
| frank26080115 | 0:84d7747641aa | 137 | /** I2S Status Receive or Transmit DMA1 */ |
| frank26080115 | 0:84d7747641aa | 138 | #define I2S_STATE_DMA1 ((uint32_t)(1<<1)) |
| frank26080115 | 0:84d7747641aa | 139 | /** I2S Status Receive or Transmit DMA2 */ |
| frank26080115 | 0:84d7747641aa | 140 | #define I2S_STATE_DMA2 ((uint32_t)(1<<2)) |
| frank26080115 | 0:84d7747641aa | 141 | /** I2S Status Current level of the Receive FIFO (5 bits)*/ |
| frank26080115 | 0:84d7747641aa | 142 | #define I2S_STATE_RX_LEVEL(n) ((uint32_t)((n&1F)<<8)) |
| frank26080115 | 0:84d7747641aa | 143 | /** I2S Status Current level of the Transmit FIFO (5 bits)*/ |
| frank26080115 | 0:84d7747641aa | 144 | #define I2S_STATE_TX_LEVEL(n) ((uint32_t)((n&1F)<<16)) |
| frank26080115 | 0:84d7747641aa | 145 | |
| frank26080115 | 0:84d7747641aa | 146 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 147 | * Macro defines for DMA1 register (DMA1 Configuration register) |
| frank26080115 | 0:84d7747641aa | 148 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 149 | /** I2S control DMA1 for I2S receive */ |
| frank26080115 | 0:84d7747641aa | 150 | #define I2S_DMA1_RX_ENABLE ((uint32_t)(1)) |
| frank26080115 | 0:84d7747641aa | 151 | /** I2S control DMA1 for I2S transmit */ |
| frank26080115 | 0:84d7747641aa | 152 | #define I2S_DMA1_TX_ENABLE ((uint32_t)(1<<1)) |
| frank26080115 | 0:84d7747641aa | 153 | /** I2S set FIFO level that trigger a receive DMA request on DMA1 */ |
| frank26080115 | 0:84d7747641aa | 154 | #define I2S_DMA1_RX_DEPTH(n) ((uint32_t)((n&0x1F)<<8)) |
| frank26080115 | 0:84d7747641aa | 155 | /** I2S set FIFO level that trigger a transmit DMA request on DMA1 */ |
| frank26080115 | 0:84d7747641aa | 156 | #define I2S_DMA1_TX_DEPTH(n) ((uint32_t)((n&0x1F)<<16)) |
| frank26080115 | 0:84d7747641aa | 157 | |
| frank26080115 | 0:84d7747641aa | 158 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 159 | * Macro defines for DMA2 register (DMA2 Configuration register) |
| frank26080115 | 0:84d7747641aa | 160 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 161 | /** I2S control DMA2 for I2S receive */ |
| frank26080115 | 0:84d7747641aa | 162 | #define I2S_DMA2_RX_ENABLE ((uint32_t)(1)) |
| frank26080115 | 0:84d7747641aa | 163 | /** I2S control DMA1 for I2S transmit */ |
| frank26080115 | 0:84d7747641aa | 164 | #define I2S_DMA2_TX_ENABLE ((uint32_t)(1<<1)) |
| frank26080115 | 0:84d7747641aa | 165 | /** I2S set FIFO level that trigger a receive DMA request on DMA1 */ |
| frank26080115 | 0:84d7747641aa | 166 | #define I2S_DMA2_RX_DEPTH(n) ((uint32_t)((n&0x1F)<<8)) |
| frank26080115 | 0:84d7747641aa | 167 | /** I2S set FIFO level that trigger a transmit DMA request on DMA1 */ |
| frank26080115 | 0:84d7747641aa | 168 | #define I2S_DMA2_TX_DEPTH(n) ((uint32_t)((n&0x1F)<<16)) |
| frank26080115 | 0:84d7747641aa | 169 | |
| frank26080115 | 0:84d7747641aa | 170 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 171 | * Macro defines for IRQ register (Interrupt Request Control register) |
| frank26080115 | 0:84d7747641aa | 172 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 173 | /** I2S control I2S receive interrupt */ |
| frank26080115 | 0:84d7747641aa | 174 | #define I2S_IRQ_RX_ENABLE ((uint32_t)(1)) |
| frank26080115 | 0:84d7747641aa | 175 | /** I2S control I2S transmit interrupt */ |
| frank26080115 | 0:84d7747641aa | 176 | #define I2S_IRQ_TX_ENABLE ((uint32_t)(1<<1)) |
| frank26080115 | 0:84d7747641aa | 177 | /** I2S set the FIFO level on which to create an irq request */ |
| frank26080115 | 0:84d7747641aa | 178 | #define I2S_IRQ_RX_DEPTH(n) ((uint32_t)((n&0x1F)<<8)) |
| frank26080115 | 0:84d7747641aa | 179 | /** I2S set the FIFO level on which to create an irq request */ |
| frank26080115 | 0:84d7747641aa | 180 | #define I2S_IRQ_TX_DEPTH(n) ((uint32_t)((n&0x1F)<<16)) |
| frank26080115 | 0:84d7747641aa | 181 | |
| frank26080115 | 0:84d7747641aa | 182 | /********************************************************************************//** |
| frank26080115 | 0:84d7747641aa | 183 | * Macro defines for TXRATE/RXRATE register (Transmit/Receive Clock Rate register) |
| frank26080115 | 0:84d7747641aa | 184 | *********************************************************************************/ |
| frank26080115 | 0:84d7747641aa | 185 | /** I2S Transmit MCLK rate denominator */ |
| frank26080115 | 0:84d7747641aa | 186 | #define I2S_TXRATE_Y_DIVIDER(n) ((uint32_t)(n&0xFF)) |
| frank26080115 | 0:84d7747641aa | 187 | /** I2S Transmit MCLK rate denominator */ |
| frank26080115 | 0:84d7747641aa | 188 | #define I2S_TXRATE_X_DIVIDER(n) ((uint32_t)((n&0xFF)<<8)) |
| frank26080115 | 0:84d7747641aa | 189 | /** I2S Receive MCLK rate denominator */ |
| frank26080115 | 0:84d7747641aa | 190 | #define I2S_RXRATE_Y_DIVIDER(n) ((uint32_t)(n&0xFF)) |
| frank26080115 | 0:84d7747641aa | 191 | /** I2S Receive MCLK rate denominator */ |
| frank26080115 | 0:84d7747641aa | 192 | #define I2S_RXRATE_X_DIVIDER(n) ((uint32_t)((n&0xFF)<<8)) |
| frank26080115 | 0:84d7747641aa | 193 | |
| frank26080115 | 0:84d7747641aa | 194 | /*************************************************************************************//** |
| frank26080115 | 0:84d7747641aa | 195 | * Macro defines for TXBITRATE & RXBITRATE register (Transmit/Receive Bit Rate register) |
| frank26080115 | 0:84d7747641aa | 196 | **************************************************************************************/ |
| frank26080115 | 0:84d7747641aa | 197 | #define I2S_TXBITRATE(n) ((uint32_t)(n&0x3F)) |
| frank26080115 | 0:84d7747641aa | 198 | #define I2S_RXBITRATE(n) ((uint32_t)(n&0x3F)) |
| frank26080115 | 0:84d7747641aa | 199 | |
| frank26080115 | 0:84d7747641aa | 200 | /**********************************************************************************//** |
| frank26080115 | 0:84d7747641aa | 201 | * Macro defines for TXMODE/RXMODE register (Transmit/Receive Mode Control register) |
| frank26080115 | 0:84d7747641aa | 202 | ************************************************************************************/ |
| frank26080115 | 0:84d7747641aa | 203 | /** I2S Transmit select clock source (2 bits)*/ |
| frank26080115 | 0:84d7747641aa | 204 | #define I2S_TXMODE_CLKSEL(n) ((uint32_t)(n&0x03)) |
| frank26080115 | 0:84d7747641aa | 205 | /** I2S Transmit control 4-pin mode */ |
| frank26080115 | 0:84d7747641aa | 206 | #define I2S_TXMODE_4PIN_ENABLE ((uint32_t)(1<<2)) |
| frank26080115 | 0:84d7747641aa | 207 | /** I2S Transmit control the TX_MCLK output */ |
| frank26080115 | 0:84d7747641aa | 208 | #define I2S_TXMODE_MCENA ((uint32_t)(1<<3)) |
| frank26080115 | 0:84d7747641aa | 209 | /** I2S Receive select clock source */ |
| frank26080115 | 0:84d7747641aa | 210 | #define I2S_RXMODE_CLKSEL(n) ((uint32_t)(n&0x03)) |
| frank26080115 | 0:84d7747641aa | 211 | /** I2S Receive control 4-pin mode */ |
| frank26080115 | 0:84d7747641aa | 212 | #define I2S_RXMODE_4PIN_ENABLE ((uint32_t)(1<<2)) |
| frank26080115 | 0:84d7747641aa | 213 | /** I2S Receive control the TX_MCLK output */ |
| frank26080115 | 0:84d7747641aa | 214 | #define I2S_RXMODE_MCENA ((uint32_t)(1<<3)) |
| frank26080115 | 0:84d7747641aa | 215 | |
| frank26080115 | 0:84d7747641aa | 216 | |
| frank26080115 | 0:84d7747641aa | 217 | /* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */ |
| frank26080115 | 0:84d7747641aa | 218 | /** Macro to determine if it is valid I2S peripheral */ |
| frank26080115 | 0:84d7747641aa | 219 | #define PARAM_I2Sx(n) (((uint32_t *)n)==((uint32_t *)LPC_I2S)) |
| frank26080115 | 0:84d7747641aa | 220 | /** Macro to check Data to send valid */ |
| frank26080115 | 0:84d7747641aa | 221 | #define PRAM_I2S_FREQ(freq) ((freq>=16000)&&(freq <= 96000)) |
| frank26080115 | 0:84d7747641aa | 222 | /* Macro check I2S word width type */ |
| frank26080115 | 0:84d7747641aa | 223 | #define PARAM_I2S_WORDWIDTH(n) ((n==I2S_WORDWIDTH_8)||(n==I2S_WORDWIDTH_16)\ |
| frank26080115 | 0:84d7747641aa | 224 | ||(n==I2S_WORDWIDTH_32)) |
| frank26080115 | 0:84d7747641aa | 225 | /* Macro check I2S channel type */ |
| frank26080115 | 0:84d7747641aa | 226 | #define PARAM_I2S_CHANNEL(n) ((n==I2S_STEREO)||(n==I2S_MONO)) |
| frank26080115 | 0:84d7747641aa | 227 | /* Macro check I2S master/slave mode */ |
| frank26080115 | 0:84d7747641aa | 228 | #define PARAM_I2S_WS_SEL(n) ((n==I2S_MASTER_MODE)||(n==I2S_SLAVE_MODE)) |
| frank26080115 | 0:84d7747641aa | 229 | /* Macro check I2S stop mode */ |
| frank26080115 | 0:84d7747641aa | 230 | #define PARAM_I2S_STOP(n) ((n==I2S_STOP_ENABLE)||(n==I2S_STOP_DISABLE)) |
| frank26080115 | 0:84d7747641aa | 231 | /* Macro check I2S reset mode */ |
| frank26080115 | 0:84d7747641aa | 232 | #define PARAM_I2S_RESET(n) ((n==I2S_RESET_ENABLE)||(n==I2S_RESET_DISABLE)) |
| frank26080115 | 0:84d7747641aa | 233 | /* Macro check I2S reset mode */ |
| frank26080115 | 0:84d7747641aa | 234 | #define PARAM_I2S_MUTE(n) ((n==I2S_MUTE_ENABLE)||(n==I2S_MUTE_DISABLE)) |
| frank26080115 | 0:84d7747641aa | 235 | /* Macro check I2S transmit/receive mode */ |
| frank26080115 | 0:84d7747641aa | 236 | #define PARAM_I2S_TRX(n) ((n==I2S_TX_MODE)||(n==I2S_RX_MODE)) |
| frank26080115 | 0:84d7747641aa | 237 | /* Macro check I2S clock select mode */ |
| frank26080115 | 0:84d7747641aa | 238 | #define PARAM_I2S_CLKSEL(n) ((n==I2S_CLKSEL_FRDCLK)||(n==I2S_CLKSEL_MCLK)) |
| frank26080115 | 0:84d7747641aa | 239 | /* Macro check I2S 4-pin mode */ |
| frank26080115 | 0:84d7747641aa | 240 | #define PARAM_I2S_4PIN(n) ((n==I2S_4PIN_ENABLE)||(n==I2S_4PIN_DISABLE)) |
| frank26080115 | 0:84d7747641aa | 241 | /* Macro check I2S MCLK mode */ |
| frank26080115 | 0:84d7747641aa | 242 | #define PARAM_I2S_MCLK(n) ((n==I2S_MCLK_ENABLE)||(n==I2S_MCLK_DISABLE)) |
| frank26080115 | 0:84d7747641aa | 243 | /* Macro check I2S DMA mode */ |
| frank26080115 | 0:84d7747641aa | 244 | #define PARAM_I2S_DMA(n) ((n==I2S_DMA_1)||(n==I2S_DMA_2)) |
| frank26080115 | 0:84d7747641aa | 245 | /* Macro check I2S DMA depth value */ |
| frank26080115 | 0:84d7747641aa | 246 | #define PARAM_I2S_DMA_DEPTH(n) ((n)<=31) |
| frank26080115 | 0:84d7747641aa | 247 | /* Macro check I2S irq level value */ |
| frank26080115 | 0:84d7747641aa | 248 | #define PARAM_I2S_IRQ_LEVEL(n) ((n)<=31) |
| frank26080115 | 0:84d7747641aa | 249 | /* Macro check I2S half-period value */ |
| frank26080115 | 0:84d7747641aa | 250 | #define PARAM_I2S_HALFPERIOD(n) ((n>0)&&(n<512)) |
| frank26080115 | 0:84d7747641aa | 251 | /* Macro check I2S bit-rate value */ |
| frank26080115 | 0:84d7747641aa | 252 | #define PARAM_I2S_BITRATE(n) ((n)<=63) |
| frank26080115 | 0:84d7747641aa | 253 | /** |
| frank26080115 | 0:84d7747641aa | 254 | * @} |
| frank26080115 | 0:84d7747641aa | 255 | */ |
| frank26080115 | 0:84d7747641aa | 256 | |
| frank26080115 | 0:84d7747641aa | 257 | |
| frank26080115 | 0:84d7747641aa | 258 | |
| frank26080115 | 0:84d7747641aa | 259 | /* Public Types --------------------------------------------------------------- */ |
| frank26080115 | 0:84d7747641aa | 260 | /** @defgroup I2S_Public_Types I2S Public Types |
| frank26080115 | 0:84d7747641aa | 261 | * @{ |
| frank26080115 | 0:84d7747641aa | 262 | */ |
| frank26080115 | 0:84d7747641aa | 263 | |
| frank26080115 | 0:84d7747641aa | 264 | /** |
| frank26080115 | 0:84d7747641aa | 265 | * @brief I2S configuration structure definition |
| frank26080115 | 0:84d7747641aa | 266 | */ |
| frank26080115 | 0:84d7747641aa | 267 | typedef struct { |
| frank26080115 | 0:84d7747641aa | 268 | uint8_t wordwidth; /** the number of bytes in data as follow: |
| frank26080115 | 0:84d7747641aa | 269 | -I2S_WORDWIDTH_8: 8 bit data |
| frank26080115 | 0:84d7747641aa | 270 | -I2S_WORDWIDTH_16: 16 bit data |
| frank26080115 | 0:84d7747641aa | 271 | -I2S_WORDWIDTH_32: 32 bit data */ |
| frank26080115 | 0:84d7747641aa | 272 | uint8_t mono; /** Set mono/stereo mode, should be: |
| frank26080115 | 0:84d7747641aa | 273 | - I2S_STEREO: stereo mode |
| frank26080115 | 0:84d7747641aa | 274 | - I2S_MONO: mono mode */ |
| frank26080115 | 0:84d7747641aa | 275 | uint8_t stop; /** Disables accesses on FIFOs, should be: |
| frank26080115 | 0:84d7747641aa | 276 | - I2S_STOP_ENABLE: enable stop mode |
| frank26080115 | 0:84d7747641aa | 277 | - I2S_STOP_DISABLE: disable stop mode */ |
| frank26080115 | 0:84d7747641aa | 278 | uint8_t reset; /** Asynchronously reset tje transmit channel and FIFO, should be: |
| frank26080115 | 0:84d7747641aa | 279 | - I2S_RESET_ENABLE: enable reset mode |
| frank26080115 | 0:84d7747641aa | 280 | - I2S_RESET_DISABLE: disable reset mode */ |
| frank26080115 | 0:84d7747641aa | 281 | uint8_t ws_sel; /** Set Master/Slave mode, should be: |
| frank26080115 | 0:84d7747641aa | 282 | - I2S_MASTER_MODE: I2S master mode |
| frank26080115 | 0:84d7747641aa | 283 | - I2S_SLAVE_MODE: I2S slave mode */ |
| frank26080115 | 0:84d7747641aa | 284 | uint8_t mute; /** MUTE mode: when true, the transmit channel sends only zeroes, shoule be: |
| frank26080115 | 0:84d7747641aa | 285 | - I2S_MUTE_ENABLE: enable mute mode |
| frank26080115 | 0:84d7747641aa | 286 | - I2S_MUTE_DISABLE: disable mute mode */ |
| frank26080115 | 0:84d7747641aa | 287 | uint8_t Reserved0[2]; |
| frank26080115 | 0:84d7747641aa | 288 | } I2S_CFG_Type; |
| frank26080115 | 0:84d7747641aa | 289 | |
| frank26080115 | 0:84d7747641aa | 290 | /** |
| frank26080115 | 0:84d7747641aa | 291 | * @brief I2S DMA configuration structure definition |
| frank26080115 | 0:84d7747641aa | 292 | */ |
| frank26080115 | 0:84d7747641aa | 293 | typedef struct { |
| frank26080115 | 0:84d7747641aa | 294 | uint8_t DMAIndex; /** Select DMA1 or DMA2, should be: |
| frank26080115 | 0:84d7747641aa | 295 | - I2S_DMA_1: DMA1 |
| frank26080115 | 0:84d7747641aa | 296 | - I2S_DMA_2: DMA2 */ |
| frank26080115 | 0:84d7747641aa | 297 | uint8_t depth; /** FIFO level that triggers a DMA request */ |
| frank26080115 | 0:84d7747641aa | 298 | uint8_t Reserved0[2]; |
| frank26080115 | 0:84d7747641aa | 299 | }I2S_DMAConf_Type; |
| frank26080115 | 0:84d7747641aa | 300 | |
| frank26080115 | 0:84d7747641aa | 301 | /** |
| frank26080115 | 0:84d7747641aa | 302 | * @brief I2S mode configuration structure definition |
| frank26080115 | 0:84d7747641aa | 303 | */ |
| frank26080115 | 0:84d7747641aa | 304 | typedef struct{ |
| frank26080115 | 0:84d7747641aa | 305 | uint8_t clksel; /** Clock source selection, should be: |
| frank26080115 | 0:84d7747641aa | 306 | - I2S_CLKSEL_FRDCLK: Select the fractional rate divider clock output |
| frank26080115 | 0:84d7747641aa | 307 | - I2S_CLKSEL_MCLK: Select the MCLK signal as the clock source */ |
| frank26080115 | 0:84d7747641aa | 308 | uint8_t fpin; /** Select four pin mode, should be: |
| frank26080115 | 0:84d7747641aa | 309 | - I2S_4PIN_ENABLE: 4-pin enable |
| frank26080115 | 0:84d7747641aa | 310 | - I2S_4PIN_DISABLE: 4-pin disable */ |
| frank26080115 | 0:84d7747641aa | 311 | uint8_t mcena; /** Select MCLK mode, should be: |
| frank26080115 | 0:84d7747641aa | 312 | - I2S_MCLK_ENABLE: MCLK enable for output |
| frank26080115 | 0:84d7747641aa | 313 | - I2S_MCLK_DISABLE: MCLK disable for output */ |
| frank26080115 | 0:84d7747641aa | 314 | uint8_t Reserved; |
| frank26080115 | 0:84d7747641aa | 315 | }I2S_MODEConf_Type; |
| frank26080115 | 0:84d7747641aa | 316 | |
| frank26080115 | 0:84d7747641aa | 317 | |
| frank26080115 | 0:84d7747641aa | 318 | /** |
| frank26080115 | 0:84d7747641aa | 319 | * @} |
| frank26080115 | 0:84d7747641aa | 320 | */ |
| frank26080115 | 0:84d7747641aa | 321 | |
| frank26080115 | 0:84d7747641aa | 322 | |
| frank26080115 | 0:84d7747641aa | 323 | /* Public Functions ----------------------------------------------------------- */ |
| frank26080115 | 0:84d7747641aa | 324 | /** @defgroup I2S_Public_Functions I2S Public Functions |
| frank26080115 | 0:84d7747641aa | 325 | * @{ |
| frank26080115 | 0:84d7747641aa | 326 | */ |
| frank26080115 | 0:84d7747641aa | 327 | /* I2S Init/DeInit functions ---------*/ |
| frank26080115 | 0:84d7747641aa | 328 | void I2S_Init(LPC_I2S_TypeDef *I2Sx); |
| frank26080115 | 0:84d7747641aa | 329 | void I2S_DeInit(LPC_I2S_TypeDef *I2Sx); |
| frank26080115 | 0:84d7747641aa | 330 | |
| frank26080115 | 0:84d7747641aa | 331 | /* I2S configuration functions --------*/ |
| frank26080115 | 0:84d7747641aa | 332 | void I2S_Config(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode, I2S_CFG_Type* ConfigStruct); |
| frank26080115 | 0:84d7747641aa | 333 | Status I2S_FreqConfig(LPC_I2S_TypeDef *I2Sx, uint32_t Freq, uint8_t TRMode); |
| frank26080115 | 0:84d7747641aa | 334 | void I2S_SetBitRate(LPC_I2S_TypeDef *I2Sx, uint8_t bitrate, uint8_t TRMode); |
| frank26080115 | 0:84d7747641aa | 335 | void I2S_ModeConfig(LPC_I2S_TypeDef *I2Sx, I2S_MODEConf_Type* ModeConfig, uint8_t TRMode); |
| frank26080115 | 0:84d7747641aa | 336 | uint8_t I2S_GetLevel(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode); |
| frank26080115 | 0:84d7747641aa | 337 | |
| frank26080115 | 0:84d7747641aa | 338 | /* I2S operate functions -------------*/ |
| frank26080115 | 0:84d7747641aa | 339 | void I2S_Send(LPC_I2S_TypeDef *I2Sx, uint32_t BufferData); |
| frank26080115 | 0:84d7747641aa | 340 | uint32_t I2S_Receive(LPC_I2S_TypeDef* I2Sx); |
| frank26080115 | 0:84d7747641aa | 341 | void I2S_Start(LPC_I2S_TypeDef *I2Sx); |
| frank26080115 | 0:84d7747641aa | 342 | void I2S_Pause(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode); |
| frank26080115 | 0:84d7747641aa | 343 | void I2S_Mute(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode); |
| frank26080115 | 0:84d7747641aa | 344 | void I2S_Stop(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode); |
| frank26080115 | 0:84d7747641aa | 345 | |
| frank26080115 | 0:84d7747641aa | 346 | /* I2S DMA functions ----------------*/ |
| frank26080115 | 0:84d7747641aa | 347 | void I2S_DMAConfig(LPC_I2S_TypeDef *I2Sx, I2S_DMAConf_Type* DMAConfig, uint8_t TRMode); |
| frank26080115 | 0:84d7747641aa | 348 | void I2S_DMACmd(LPC_I2S_TypeDef *I2Sx, uint8_t DMAIndex,uint8_t TRMode, FunctionalState NewState); |
| frank26080115 | 0:84d7747641aa | 349 | |
| frank26080115 | 0:84d7747641aa | 350 | /* I2S IRQ functions ----------------*/ |
| frank26080115 | 0:84d7747641aa | 351 | void I2S_IRQCmd(LPC_I2S_TypeDef *I2Sx,uint8_t TRMode, FunctionalState NewState); |
| frank26080115 | 0:84d7747641aa | 352 | void I2S_IRQConfig(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode, uint8_t level); |
| frank26080115 | 0:84d7747641aa | 353 | FunctionalState I2S_GetIRQStatus(LPC_I2S_TypeDef *I2Sx,uint8_t TRMode); |
| frank26080115 | 0:84d7747641aa | 354 | uint8_t I2S_GetIRQDepth(LPC_I2S_TypeDef *I2Sx,uint8_t TRMode); |
| frank26080115 | 0:84d7747641aa | 355 | |
| frank26080115 | 0:84d7747641aa | 356 | /** |
| frank26080115 | 0:84d7747641aa | 357 | * @} |
| frank26080115 | 0:84d7747641aa | 358 | */ |
| frank26080115 | 0:84d7747641aa | 359 | |
| frank26080115 | 0:84d7747641aa | 360 | |
| frank26080115 | 0:84d7747641aa | 361 | #ifdef __cplusplus |
| frank26080115 | 0:84d7747641aa | 362 | } |
| frank26080115 | 0:84d7747641aa | 363 | #endif |
| frank26080115 | 0:84d7747641aa | 364 | |
| frank26080115 | 0:84d7747641aa | 365 | |
| frank26080115 | 0:84d7747641aa | 366 | #endif /* LPC17XX_SSP_H_ */ |
| frank26080115 | 0:84d7747641aa | 367 | |
| frank26080115 | 0:84d7747641aa | 368 | /** |
| frank26080115 | 0:84d7747641aa | 369 | * @} |
| frank26080115 | 0:84d7747641aa | 370 | */ |
| frank26080115 | 0:84d7747641aa | 371 | |
| frank26080115 | 0:84d7747641aa | 372 | /* --------------------------------- End Of File ------------------------------ */ |