Michael Fluck / Mbed 2 deprecated MyClass

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Dependencies:   mbed

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EncoderCounter.cpp@0:af3f2e5c9cd4, 2018-04-19 (annotated)

Committer:
fluckmi1
Date:
Thu Apr 19 11:53:52 2018 +0000
Revision:
0:af3f2e5c9cd4
peace

Who changed what in which revision?

UserRevisionLine numberNew contents of line
fluckmi1 0:af3f2e5c9cd4 1 /*
fluckmi1 0:af3f2e5c9cd4 2 * EncoderCounter.cpp
fluckmi1 0:af3f2e5c9cd4 3 * Copyright (c) 2018, ZHAW
fluckmi1 0:af3f2e5c9cd4 4 * All rights reserved.
fluckmi1 0:af3f2e5c9cd4 5 */
fluckmi1 0:af3f2e5c9cd4 6
fluckmi1 0:af3f2e5c9cd4 7 #include "EncoderCounter.h"
fluckmi1 0:af3f2e5c9cd4 8
fluckmi1 0:af3f2e5c9cd4 9 using namespace std;
fluckmi1 0:af3f2e5c9cd4 10
fluckmi1 0:af3f2e5c9cd4 11 /**
fluckmi1 0:af3f2e5c9cd4 12 * Creates and initializes the driver to read the quadrature
fluckmi1 0:af3f2e5c9cd4 13 * encoder counter of the STM32 microcontroller.
fluckmi1 0:af3f2e5c9cd4 14 * @param a the input pin for the channel A.
fluckmi1 0:af3f2e5c9cd4 15 * @param b the input pin for the channel B.
fluckmi1 0:af3f2e5c9cd4 16 */
fluckmi1 0:af3f2e5c9cd4 17 EncoderCounter::EncoderCounter(PinName a, PinName b) {
fluckmi1 0:af3f2e5c9cd4 18
fluckmi1 0:af3f2e5c9cd4 19 // check pins
fluckmi1 0:af3f2e5c9cd4 20
fluckmi1 0:af3f2e5c9cd4 21 if ((a == PA_0) && (b == PA_1)) {
fluckmi1 0:af3f2e5c9cd4 22
fluckmi1 0:af3f2e5c9cd4 23 // pinmap OK for TIM2 CH1 and CH2
fluckmi1 0:af3f2e5c9cd4 24
fluckmi1 0:af3f2e5c9cd4 25 TIM = TIM2;
fluckmi1 0:af3f2e5c9cd4 26
fluckmi1 0:af3f2e5c9cd4 27 // configure general purpose I/O registers
fluckmi1 0:af3f2e5c9cd4 28
fluckmi1 0:af3f2e5c9cd4 29 GPIOA->MODER &= ~GPIO_MODER_MODER0; // reset port A0
fluckmi1 0:af3f2e5c9cd4 30 GPIOA->MODER |= GPIO_MODER_MODER0_1; // set alternate mode of port A0
fluckmi1 0:af3f2e5c9cd4 31 GPIOA->PUPDR &= ~GPIO_PUPDR_PUPDR0; // reset pull-up/pull-down on port A0
fluckmi1 0:af3f2e5c9cd4 32 GPIOA->PUPDR |= GPIO_PUPDR_PUPDR0_1; // set input as pull-down
fluckmi1 0:af3f2e5c9cd4 33 GPIOA->AFR[0] &= ~(0xF << 4*0); // reset alternate function of port A0
fluckmi1 0:af3f2e5c9cd4 34 GPIOA->AFR[0] |= 1 << 4*0; // set alternate funtion 1 of port A0
fluckmi1 0:af3f2e5c9cd4 35
fluckmi1 0:af3f2e5c9cd4 36 GPIOA->MODER &= ~GPIO_MODER_MODER1; // reset port A1
fluckmi1 0:af3f2e5c9cd4 37 GPIOA->MODER |= GPIO_MODER_MODER1_1; // set alternate mode of port A1
fluckmi1 0:af3f2e5c9cd4 38 GPIOA->PUPDR &= ~GPIO_PUPDR_PUPDR1; // reset pull-up/pull-down on port A1
fluckmi1 0:af3f2e5c9cd4 39 GPIOA->PUPDR |= GPIO_PUPDR_PUPDR1_1; // set input as pull-down
fluckmi1 0:af3f2e5c9cd4 40 GPIOA->AFR[0] &= ~(0xF << 4*1); // reset alternate function of port A1
fluckmi1 0:af3f2e5c9cd4 41 GPIOA->AFR[0] |= 1 << 4*1; // set alternate funtion 1 of port A1
fluckmi1 0:af3f2e5c9cd4 42
fluckmi1 0:af3f2e5c9cd4 43 // configure reset and clock control registers
fluckmi1 0:af3f2e5c9cd4 44
fluckmi1 0:af3f2e5c9cd4 45 RCC->APB1RSTR |= RCC_APB1RSTR_TIM2RST; //reset TIM2 controller
fluckmi1 0:af3f2e5c9cd4 46 RCC->APB1RSTR &= ~RCC_APB1RSTR_TIM2RST;
fluckmi1 0:af3f2e5c9cd4 47
fluckmi1 0:af3f2e5c9cd4 48 RCC->APB1ENR |= RCC_APB1ENR_TIM2EN; // TIM2 clock enable
fluckmi1 0:af3f2e5c9cd4 49
fluckmi1 0:af3f2e5c9cd4 50 } else if ((a == PA_6) && (b == PC_7)) {
fluckmi1 0:af3f2e5c9cd4 51
fluckmi1 0:af3f2e5c9cd4 52 // pinmap OK for TIM3 CH1 and CH2
fluckmi1 0:af3f2e5c9cd4 53
fluckmi1 0:af3f2e5c9cd4 54 TIM = TIM3;
fluckmi1 0:af3f2e5c9cd4 55
fluckmi1 0:af3f2e5c9cd4 56 // configure reset and clock control registers
fluckmi1 0:af3f2e5c9cd4 57
fluckmi1 0:af3f2e5c9cd4 58 RCC->AHB1ENR |= RCC_AHB1ENR_GPIOCEN; // manually enable port C (port A enabled by mbed library)
fluckmi1 0:af3f2e5c9cd4 59
fluckmi1 0:af3f2e5c9cd4 60 // configure general purpose I/O registers
fluckmi1 0:af3f2e5c9cd4 61
fluckmi1 0:af3f2e5c9cd4 62 GPIOA->MODER &= ~GPIO_MODER_MODER6; // reset port A6
fluckmi1 0:af3f2e5c9cd4 63 GPIOA->MODER |= GPIO_MODER_MODER6_1; // set alternate mode of port A6
fluckmi1 0:af3f2e5c9cd4 64 GPIOA->PUPDR &= ~GPIO_PUPDR_PUPDR6; // reset pull-up/pull-down on port A6
fluckmi1 0:af3f2e5c9cd4 65 GPIOA->PUPDR |= GPIO_PUPDR_PUPDR6_1; // set input as pull-down
fluckmi1 0:af3f2e5c9cd4 66 GPIOA->AFR[0] &= ~(0xF << 4*6); // reset alternate function of port A6
fluckmi1 0:af3f2e5c9cd4 67 GPIOA->AFR[0] |= 2 << 4*6; // set alternate funtion 2 of port A6
fluckmi1 0:af3f2e5c9cd4 68
fluckmi1 0:af3f2e5c9cd4 69 GPIOC->MODER &= ~GPIO_MODER_MODER7; // reset port C7
fluckmi1 0:af3f2e5c9cd4 70 GPIOC->MODER |= GPIO_MODER_MODER7_1; // set alternate mode of port C7
fluckmi1 0:af3f2e5c9cd4 71 GPIOC->PUPDR &= ~GPIO_PUPDR_PUPDR7; // reset pull-up/pull-down on port C7
fluckmi1 0:af3f2e5c9cd4 72 GPIOC->PUPDR |= GPIO_PUPDR_PUPDR7_1; // set input as pull-down
fluckmi1 0:af3f2e5c9cd4 73 GPIOC->AFR[0] &= ~0xF0000000; // reset alternate function of port C7
fluckmi1 0:af3f2e5c9cd4 74 GPIOC->AFR[0] |= 2 << 4*7; // set alternate funtion 2 of port C7
fluckmi1 0:af3f2e5c9cd4 75
fluckmi1 0:af3f2e5c9cd4 76 // configure reset and clock control registers
fluckmi1 0:af3f2e5c9cd4 77
fluckmi1 0:af3f2e5c9cd4 78 RCC->APB1RSTR |= RCC_APB1RSTR_TIM3RST; //reset TIM3 controller
fluckmi1 0:af3f2e5c9cd4 79 RCC->APB1RSTR &= ~RCC_APB1RSTR_TIM3RST;
fluckmi1 0:af3f2e5c9cd4 80
fluckmi1 0:af3f2e5c9cd4 81 RCC->APB1ENR |= RCC_APB1ENR_TIM3EN; // TIM3 clock enable
fluckmi1 0:af3f2e5c9cd4 82
fluckmi1 0:af3f2e5c9cd4 83 } else if ((a == PB_6) && (b == PB_7)) {
fluckmi1 0:af3f2e5c9cd4 84
fluckmi1 0:af3f2e5c9cd4 85 // pinmap OK for TIM4 CH1 and CH2
fluckmi1 0:af3f2e5c9cd4 86
fluckmi1 0:af3f2e5c9cd4 87 TIM = TIM4;
fluckmi1 0:af3f2e5c9cd4 88
fluckmi1 0:af3f2e5c9cd4 89 // configure reset and clock control registers
fluckmi1 0:af3f2e5c9cd4 90
fluckmi1 0:af3f2e5c9cd4 91 RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN; // manually enable port B (port A enabled by mbed library)
fluckmi1 0:af3f2e5c9cd4 92
fluckmi1 0:af3f2e5c9cd4 93 // configure general purpose I/O registers
fluckmi1 0:af3f2e5c9cd4 94
fluckmi1 0:af3f2e5c9cd4 95 GPIOB->MODER &= ~GPIO_MODER_MODER6; // reset port B6
fluckmi1 0:af3f2e5c9cd4 96 GPIOB->MODER |= GPIO_MODER_MODER6_1; // set alternate mode of port B6
fluckmi1 0:af3f2e5c9cd4 97 GPIOB->PUPDR &= ~GPIO_PUPDR_PUPDR6; // reset pull-up/pull-down on port B6
fluckmi1 0:af3f2e5c9cd4 98 GPIOB->PUPDR |= GPIO_PUPDR_PUPDR6_1; // set input as pull-down
fluckmi1 0:af3f2e5c9cd4 99 GPIOB->AFR[0] &= ~(0xF << 4*6); // reset alternate function of port B6
fluckmi1 0:af3f2e5c9cd4 100 GPIOB->AFR[0] |= 2 << 4*6; // set alternate funtion 2 of port B6
fluckmi1 0:af3f2e5c9cd4 101
fluckmi1 0:af3f2e5c9cd4 102 GPIOB->MODER &= ~GPIO_MODER_MODER7; // reset port B7
fluckmi1 0:af3f2e5c9cd4 103 GPIOB->MODER |= GPIO_MODER_MODER7_1; // set alternate mode of port B7
fluckmi1 0:af3f2e5c9cd4 104 GPIOB->PUPDR &= ~GPIO_PUPDR_PUPDR7; // reset pull-up/pull-down on port B7
fluckmi1 0:af3f2e5c9cd4 105 GPIOB->PUPDR |= GPIO_PUPDR_PUPDR7_1; // set input as pull-down
fluckmi1 0:af3f2e5c9cd4 106 GPIOB->AFR[0] &= ~0xF0000000; // reset alternate function of port B7
fluckmi1 0:af3f2e5c9cd4 107 GPIOB->AFR[0] |= 2 << 4*7; // set alternate funtion 2 of port B7
fluckmi1 0:af3f2e5c9cd4 108
fluckmi1 0:af3f2e5c9cd4 109 // configure reset and clock control registers
fluckmi1 0:af3f2e5c9cd4 110
fluckmi1 0:af3f2e5c9cd4 111 RCC->APB1RSTR |= RCC_APB1RSTR_TIM4RST; //reset TIM4 controller
fluckmi1 0:af3f2e5c9cd4 112 RCC->APB1RSTR &= ~RCC_APB1RSTR_TIM4RST;
fluckmi1 0:af3f2e5c9cd4 113
fluckmi1 0:af3f2e5c9cd4 114 RCC->APB1ENR |= RCC_APB1ENR_TIM4EN; // TIM4 clock enable
fluckmi1 0:af3f2e5c9cd4 115
fluckmi1 0:af3f2e5c9cd4 116 } else {
fluckmi1 0:af3f2e5c9cd4 117
fluckmi1 0:af3f2e5c9cd4 118 printf("pinmap not found for peripheral\n");
fluckmi1 0:af3f2e5c9cd4 119 }
fluckmi1 0:af3f2e5c9cd4 120
fluckmi1 0:af3f2e5c9cd4 121 // configure general purpose timer 3 or 4
fluckmi1 0:af3f2e5c9cd4 122
fluckmi1 0:af3f2e5c9cd4 123 TIM->CR1 = 0x0000; // counter disable
fluckmi1 0:af3f2e5c9cd4 124 TIM->CR2 = 0x0000; // reset master mode selection
fluckmi1 0:af3f2e5c9cd4 125 TIM->SMCR = TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0; // counting on both TI1 & TI2 edges
fluckmi1 0:af3f2e5c9cd4 126 TIM->CCMR1 = TIM_CCMR1_CC2S_0 | TIM_CCMR1_CC1S_0;
fluckmi1 0:af3f2e5c9cd4 127 TIM->CCMR2 = 0x0000; // reset capture mode register 2
fluckmi1 0:af3f2e5c9cd4 128 TIM->CCER = TIM_CCER_CC2E | TIM_CCER_CC1E;
fluckmi1 0:af3f2e5c9cd4 129 TIM->CNT = 0x0000; // reset counter value
fluckmi1 0:af3f2e5c9cd4 130 TIM->ARR = 0xFFFF; // auto reload register
fluckmi1 0:af3f2e5c9cd4 131 TIM->CR1 = TIM_CR1_CEN; // counter enable
fluckmi1 0:af3f2e5c9cd4 132 }
fluckmi1 0:af3f2e5c9cd4 133
fluckmi1 0:af3f2e5c9cd4 134 EncoderCounter::~EncoderCounter() {}
fluckmi1 0:af3f2e5c9cd4 135
fluckmi1 0:af3f2e5c9cd4 136 /**
fluckmi1 0:af3f2e5c9cd4 137 * Resets the counter value to zero.
fluckmi1 0:af3f2e5c9cd4 138 */
fluckmi1 0:af3f2e5c9cd4 139 void EncoderCounter::reset() {
fluckmi1 0:af3f2e5c9cd4 140
fluckmi1 0:af3f2e5c9cd4 141 TIM->CNT = 0x0000;
fluckmi1 0:af3f2e5c9cd4 142 }
fluckmi1 0:af3f2e5c9cd4 143
fluckmi1 0:af3f2e5c9cd4 144 /**
fluckmi1 0:af3f2e5c9cd4 145 * Resets the counter value to a given offset value.
fluckmi1 0:af3f2e5c9cd4 146 * @param offset the offset value to reset the counter to.
fluckmi1 0:af3f2e5c9cd4 147 */
fluckmi1 0:af3f2e5c9cd4 148 void EncoderCounter::reset(short offset) {
fluckmi1 0:af3f2e5c9cd4 149
fluckmi1 0:af3f2e5c9cd4 150 TIM->CNT = -offset;
fluckmi1 0:af3f2e5c9cd4 151 }
fluckmi1 0:af3f2e5c9cd4 152
fluckmi1 0:af3f2e5c9cd4 153 /**
fluckmi1 0:af3f2e5c9cd4 154 * Reads the quadrature encoder counter value.
fluckmi1 0:af3f2e5c9cd4 155 * @return the quadrature encoder counter as a signed 16-bit integer value.
fluckmi1 0:af3f2e5c9cd4 156 */
fluckmi1 0:af3f2e5c9cd4 157 short EncoderCounter::read() {
fluckmi1 0:af3f2e5c9cd4 158
fluckmi1 0:af3f2e5c9cd4 159 return (short)(-TIM->CNT);
fluckmi1 0:af3f2e5c9cd4 160 }
fluckmi1 0:af3f2e5c9cd4 161
fluckmi1 0:af3f2e5c9cd4 162 /**
fluckmi1 0:af3f2e5c9cd4 163 * The empty operator is a shorthand notation of the <code>read()</code> method.
fluckmi1 0:af3f2e5c9cd4 164 */
fluckmi1 0:af3f2e5c9cd4 165 EncoderCounter::operator short() {
fluckmi1 0:af3f2e5c9cd4 166
fluckmi1 0:af3f2e5c9cd4 167 return read();
fluckmi1 0:af3f2e5c9cd4 168 }
fluckmi1 0:af3f2e5c9cd4 169
fluckmi1 0:af3f2e5c9cd4 170