stm32f4xx_nucleo_bluenrg.h

00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_nucleo_bluenrg.h
00004   * @author  CL
00005   * @version V1.0.0
00006   * @date    04-July-2014
00007   * @brief   This file contains definitions for SPI communication on
00008   *          STM32F4XX-Nucleo Kit from STMicroelectronics for BLE BlueNRG
00009   *          Expansion Board (reference X-NUCLEO-IDB04A1).
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
00014   *
00015   * Redistribution and use in source and binary forms, with or without modification,
00016   * are permitted provided that the following conditions are met:
00017   *   1. Redistributions of source code must retain the above copyright notice,
00018   *      this list of conditions and the following disclaimer.
00019   *   2. Redistributions in binary form must reproduce the above copyright notice,
00020   *      this list of conditions and the following disclaimer in the documentation
00021   *      and/or other materials provided with the distribution.
00022   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00023   *      may be used to endorse or promote products derived from this software
00024   *      without specific prior written permission.
00025   *
00026   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00027   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00028   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00029   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00030   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00031   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00032   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00033   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00034   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00035   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00036   *
00037   ******************************************************************************
00038   */ 
00039   
00040 /* Define to prevent recursive inclusion -------------------------------------*/
00041 #ifndef __STM32F4XX_NUCLEO_BLUENRG_H
00042 #define __STM32F4XX_NUCLEO_BLUENRG_H
00043 
00044 #ifdef __cplusplus
00045  extern "C" {
00046 #endif
00047 
00048 /* Includes ------------------------------------------------------------------*/
00049 #include "stm32f4xx_hal.h"
00050 #include "stm32f4xx_nucleo.h "
00051 
00052 
00053 /**
00054 * @brief SPI communication details between Nucleo F4 and BlueNRG
00055 *        Expansion Board.
00056 */
00057 // SPI Instance
00058 #define BNRG_SPI_INSTANCE               SPI1
00059 #define BNRG_SPI_CLK_ENABLE()           __SPI1_CLK_ENABLE()
00060 
00061 // SPI Configuration
00062 #define BNRG_SPI_MODE                   SPI_MODE_MASTER
00063 #define BNRG_SPI_DIRECTION              SPI_DIRECTION_2LINES
00064 #define BNRG_SPI_DATASIZE               SPI_DATASIZE_8BIT
00065 #define BNRG_SPI_CLKPOLARITY            SPI_POLARITY_LOW
00066 #define BNRG_SPI_CLKPHASE               SPI_PHASE_1EDGE
00067 #define BNRG_SPI_NSS                    SPI_NSS_SOFT
00068 #define BNRG_SPI_FIRSTBIT               SPI_FIRSTBIT_MSB
00069 #define BNRG_SPI_TIMODE                 SPI_TIMODE_DISABLED
00070 #define BNRG_SPI_CRCPOLYNOMIAL          7
00071 #define BNRG_SPI_BAUDRATEPRESCALER      SPI_BAUDRATEPRESCALER_4
00072 #define BNRG_SPI_CRCCALCULATION         SPI_CRCCALCULATION_DISABLED
00073 
00074 // SPI Reset Pin: PA.8
00075 #define BNRG_SPI_RESET_PIN              GPIO_PIN_8
00076 #define BNRG_SPI_RESET_MODE             GPIO_MODE_OUTPUT_PP
00077 #define BNRG_SPI_RESET_PULL             GPIO_PULLUP/*[RG:]fixme!!! GPIO_PULLUP (original GPIO_NOPULL)*/
00078 #define BNRG_SPI_RESET_SPEED            GPIO_SPEED_LOW
00079 #define BNRG_SPI_RESET_ALTERNATE        0
00080 #define BNRG_SPI_RESET_PORT             GPIOA
00081 #define BNRG_SPI_RESET_CLK_ENABLE()     __GPIOA_CLK_ENABLE()
00082 
00083 // SCLK: PB.3
00084 #define BNRG_SPI_SCLK_PIN               GPIO_PIN_3
00085 #define BNRG_SPI_SCLK_MODE              GPIO_MODE_AF_PP
00086 #define BNRG_SPI_SCLK_PULL              GPIO_PULLDOWN //[RG:] fixme!!! GPIO_PULLDOWN (original GPIO_PULLUP)
00087 #define BNRG_SPI_SCLK_SPEED             GPIO_SPEED_HIGH
00088 #define BNRG_SPI_SCLK_ALTERNATE         GPIO_AF5_SPI1
00089 #define BNRG_SPI_SCLK_PORT              GPIOB
00090 #define BNRG_SPI_SCLK_CLK_ENABLE()      __GPIOB_CLK_ENABLE()
00091 
00092 // MISO (Master Input Slave Output): PA.6
00093 #define BNRG_SPI_MISO_PIN               GPIO_PIN_6
00094 #define BNRG_SPI_MISO_MODE              GPIO_MODE_AF_PP
00095 #define BNRG_SPI_MISO_PULL              GPIO_NOPULL //[RG:] fixme!!! GPIO_NOPULL (original GPIO_PULLDOWN)
00096 #define BNRG_SPI_MISO_SPEED             GPIO_SPEED_HIGH
00097 #define BNRG_SPI_MISO_ALTERNATE         GPIO_AF5_SPI1
00098 #define BNRG_SPI_MISO_PORT              GPIOA
00099 #define BNRG_SPI_MISO_CLK_ENABLE()      __GPIOA_CLK_ENABLE()
00100 
00101 
00102 // MOSI (Master Output Slave Input): PA.7
00103 #define BNRG_SPI_MOSI_PIN           GPIO_PIN_7
00104 #define BNRG_SPI_MOSI_MODE          GPIO_MODE_AF_PP
00105 /*[RG:] sometimes at the end of a SPI receive phase MOSI is left high (even if the NCS rises)*/
00106 #define BNRG_SPI_MOSI_PULL          GPIO_NOPULL //[RG:] fixme!!! GPIO_PULLDOWN/GPIO_NOPULL (original GPIO_PULLUP)
00107 #define BNRG_SPI_MOSI_SPEED         GPIO_SPEED_HIGH
00108 #define BNRG_SPI_MOSI_ALTERNATE     GPIO_AF5_SPI1
00109 #define BNRG_SPI_MOSI_PORT          GPIOA
00110 #define BNRG_SPI_MOSI_CLK_ENABLE()  __GPIOA_CLK_ENABLE()
00111 
00112 // NSS/CSN/CS: PA.1
00113 #define BNRG_SPI_CS_PIN             GPIO_PIN_1
00114 #define BNRG_SPI_CS_MODE            GPIO_MODE_OUTPUT_PP
00115 #define BNRG_SPI_CS_PULL            GPIO_PULLUP/*[RG:]fixme!!! GPIO_PULLUP (original GPIO_NOPULL)*/
00116 #define BNRG_SPI_CS_SPEED           GPIO_SPEED_HIGH
00117 #define BNRG_SPI_CS_ALTERNATE       0
00118 #define BNRG_SPI_CS_PORT            GPIOA
00119 #define BNRG_SPI_CS_CLK_ENABLE()    __GPIOA_CLK_ENABLE()
00120 
00121 // IRQ: PA.0
00122 #define BNRG_SPI_IRQ_PIN            GPIO_PIN_0
00123 #define BNRG_SPI_IRQ_MODE           GPIO_MODE_IT_RISING
00124 #define BNRG_SPI_IRQ_PULL           GPIO_NOPULL
00125 #define BNRG_SPI_IRQ_SPEED          GPIO_SPEED_HIGH
00126 #define BNRG_SPI_IRQ_ALTERNATE      0
00127 #define BNRG_SPI_IRQ_PORT           GPIOA
00128 #define BNRG_SPI_IRQ_CLK_ENABLE()   __GPIOA_CLK_ENABLE()
00129 
00130 // EXTI External Interrupt for SPI
00131 // NOTE: if you change the IRQ pin remember to implement a corresponding handler
00132 // function like EXTI0_IRQHandler() in the user project
00133 #define BNRG_SPI_EXTI_IRQn          EXTI0_IRQn
00134 #define BNRG_SPI_EXTI_IRQHandler    EXTI0_IRQHandler
00135 #define BNRG_SPI_EXTI_PIN           BNRG_SPI_IRQ_PIN
00136 #define BNRG_SPI_EXTI_PORT          BNRG_SPI_IRQ_PORT
00137 #define RTC_WAKEUP_IRQHandler                   RTC_WKUP_IRQHandler
00138 
00139 void    Enable_SPI_IRQ(void);
00140 void    Disable_SPI_IRQ(void);
00141 void    Clear_SPI_IRQ(void);
00142 void    Clear_SPI_EXTI_Flag(void);
00143 /**
00144   * @}
00145   */
00146 
00147 #ifdef __cplusplus
00148 }
00149 #endif
00150 
00151 #endif /* __STM32F4XX_NUCLEO_BLUENRG_H */
00152 
00153     
00154 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
00155 
00156