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sx1276.cpp
00001 /* 00002 / _____) _ | | 00003 ( (____ _____ ____ _| |_ _____ ____| |__ 00004 \____ \| ___ | (_ _) ___ |/ ___) _ \ 00005 _____) ) ____| | | || |_| ____( (___| | | | 00006 (______/|_____)_|_|_| \__)_____)\____)_| |_| 00007 (C) 2014 Semtech 00008 00009 Description: Actual implementation of a SX1276 radio, inherits Radio 00010 00011 License: Revised BSD License, see LICENSE.TXT file include in the project 00012 00013 Maintainers: Miguel Luis, Gregory Cristian and Nicolas Huguenin 00014 */ 00015 #include "sx1276.h" 00016 #include "mbed.h" 00017 00018 00019 00020 # define DEBUG_PRINT(x) do {} while (0) 00021 const FskBandwidth_t SX1276::FskBandwidths[] = 00022 { 00023 { 2600 , 0x17 }, 00024 { 3100 , 0x0F }, 00025 { 3900 , 0x07 }, 00026 { 5200 , 0x16 }, 00027 { 6300 , 0x0E }, 00028 { 7800 , 0x06 }, 00029 { 10400 , 0x15 }, 00030 { 12500 , 0x0D }, 00031 { 15600 , 0x05 }, 00032 { 20800 , 0x14 }, 00033 { 25000 , 0x0C }, 00034 { 31300 , 0x04 }, 00035 { 41700 , 0x13 }, 00036 { 50000 , 0x0B }, 00037 { 62500 , 0x03 }, 00038 { 83333 , 0x12 }, 00039 { 100000, 0x0A }, 00040 { 125000, 0x02 }, 00041 { 166700, 0x11 }, 00042 { 200000, 0x09 }, 00043 { 250000, 0x01 }, 00044 { 300000, 0x00 }, // Invalid Badwidth 00045 }; 00046 00047 00048 SX1276::SX1276( RadioEvents_t *events, 00049 PinName mosi, PinName miso, PinName sclk, PinName nss, PinName reset, 00050 PinName dio0, PinName dio1, PinName dio2, PinName dio3, PinName dio4, PinName dio5 ) 00051 : Radio ( events ), 00052 spi( mosi, miso, sclk ), 00053 nss( nss ), 00054 reset( reset ), 00055 dio0( dio0 ), dio1( dio1 ), dio2( dio2 ), dio3( dio3 ), dio4( dio4 ), dio5( dio5 ), 00056 isRadioActive( false ) 00057 { 00058 wait_ms( 10 ); 00059 this->rxTx = 0; 00060 this->rxBuffer = new uint8_t[RX_BUFFER_SIZE]; 00061 previousOpMode = RF_OPMODE_STANDBY; 00062 00063 this->RadioEvents = events; 00064 00065 this->dioIrq = new DioIrqHandler[6]; 00066 00067 this->dioIrq [0] = &SX1276::OnDio0Irq; 00068 this->dioIrq [1] = &SX1276::OnDio1Irq; 00069 this->dioIrq [2] = &SX1276::OnDio2Irq; 00070 this->dioIrq [3] = &SX1276::OnDio3Irq; 00071 this->dioIrq [4] = &SX1276::OnDio4Irq; 00072 this->dioIrq [5] = NULL; 00073 00074 this->settings.State = RF_IDLE; 00075 } 00076 00077 SX1276::~SX1276( ) 00078 { 00079 delete this->rxBuffer; 00080 delete this->dioIrq ; 00081 } 00082 00083 void SX1276::Init( RadioEvents_t *events ) 00084 { 00085 this->RadioEvents = events; 00086 } 00087 00088 RadioState SX1276::GetStatus ( void ) 00089 { 00090 return this->settings.State; 00091 } 00092 00093 void SX1276::SetChannel( uint32_t freq ) 00094 { 00095 this->settings.Channel = freq; 00096 freq = ( uint32_t )( ( double )freq / ( double )FREQ_STEP ); 00097 Write( REG_FRFMSB, ( uint8_t )( ( freq >> 16 ) & 0xFF ) ); 00098 Write( REG_FRFMID, ( uint8_t )( ( freq >> 8 ) & 0xFF ) ); 00099 Write( REG_FRFLSB, ( uint8_t )( freq & 0xFF ) ); 00100 } 00101 00102 bool SX1276::IsChannelFree( RadioModems_t modem, uint32_t freq, int16_t rssiThresh ) 00103 { 00104 int16_t rssi = 0; 00105 00106 SetModem( modem ); 00107 00108 SetChannel( freq ); 00109 00110 SetOpMode( RF_OPMODE_RECEIVER ); 00111 00112 wait_ms( 1 ); 00113 00114 rssi = GetRssi( modem ); 00115 00116 Sleep( ); 00117 00118 if( rssi > rssiThresh ) 00119 { 00120 return false; 00121 } 00122 return true; 00123 } 00124 00125 uint32_t SX1276::Random( void ) 00126 { 00127 uint8_t i; 00128 uint32_t rnd = 0; 00129 00130 /* 00131 * Radio setup for random number generation 00132 */ 00133 // Set LoRa modem ON 00134 SetModem( MODEM_LORA ); 00135 00136 // Disable LoRa modem interrupts 00137 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT | 00138 RFLR_IRQFLAGS_RXDONE | 00139 RFLR_IRQFLAGS_PAYLOADCRCERROR | 00140 RFLR_IRQFLAGS_VALIDHEADER | 00141 RFLR_IRQFLAGS_TXDONE | 00142 RFLR_IRQFLAGS_CADDONE | 00143 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL | 00144 RFLR_IRQFLAGS_CADDETECTED ); 00145 00146 // Set radio in continuous reception 00147 SetOpMode( RF_OPMODE_RECEIVER ); 00148 00149 for( i = 0; i < 32; i++ ) 00150 { 00151 wait_ms( 1 ); 00152 // Unfiltered RSSI value reading. Only takes the LSB value 00153 rnd |= ( ( uint32_t )Read( REG_LR_RSSIWIDEBAND ) & 0x01 ) << i; 00154 } 00155 00156 Sleep( ); 00157 00158 return rnd; 00159 } 00160 00161 /*! 00162 * Performs the Rx chain calibration for LF and HF bands 00163 * \remark Must be called just after the reset so all registers are at their 00164 * default values 00165 */ 00166 void SX1276::RxChainCalibration ( void ) 00167 { 00168 uint8_t regPaConfigInitVal; 00169 uint32_t initialFreq; 00170 00171 // Save context 00172 regPaConfigInitVal = this->Read( REG_PACONFIG ); 00173 initialFreq = ( double )( ( ( uint32_t )this->Read( REG_FRFMSB ) << 16 ) | 00174 ( ( uint32_t )this->Read( REG_FRFMID ) << 8 ) | 00175 ( ( uint32_t )this->Read( REG_FRFLSB ) ) ) * ( double )FREQ_STEP; 00176 00177 // Cut the PA just in case, RFO output, power = -1 dBm 00178 this->Write( REG_PACONFIG, 0x00 ); 00179 00180 // Launch Rx chain calibration for LF band 00181 Write ( REG_IMAGECAL, ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_MASK ) | RF_IMAGECAL_IMAGECAL_START ); 00182 while( ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_RUNNING ) == RF_IMAGECAL_IMAGECAL_RUNNING ) 00183 { 00184 } 00185 00186 // Sets a Frequency in HF band 00187 SetChannel( 868000000 ); 00188 00189 // Launch Rx chain calibration for HF band 00190 Write ( REG_IMAGECAL, ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_MASK ) | RF_IMAGECAL_IMAGECAL_START ); 00191 while( ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_RUNNING ) == RF_IMAGECAL_IMAGECAL_RUNNING ) 00192 { 00193 } 00194 00195 // Restore context 00196 this->Write( REG_PACONFIG, regPaConfigInitVal ); 00197 SetChannel( initialFreq ); 00198 } 00199 00200 /*! 00201 * Returns the known FSK bandwidth registers value 00202 * 00203 * \param [IN] bandwidth Bandwidth value in Hz 00204 * \retval regValue Bandwidth register value. 00205 */ 00206 uint8_t SX1276::GetFskBandwidthRegValue ( uint32_t bandwidth ) 00207 { 00208 uint8_t i; 00209 00210 for( i = 0; i < ( sizeof( FskBandwidths ) / sizeof( FskBandwidth_t ) ) - 1; i++ ) 00211 { 00212 if( ( bandwidth >= FskBandwidths[i].bandwidth ) && ( bandwidth < FskBandwidths[i + 1].bandwidth ) ) 00213 { 00214 return FskBandwidths[i].RegValue; 00215 } 00216 } 00217 // ERROR: Value not found 00218 while( 1 ); 00219 } 00220 00221 void SX1276::SetRxConfig( RadioModems_t modem, uint32_t bandwidth, 00222 uint32_t datarate, uint8_t coderate, 00223 uint32_t bandwidthAfc, uint16_t preambleLen, 00224 uint16_t symbTimeout, bool fixLen, 00225 uint8_t payloadLen, 00226 bool crcOn, bool freqHopOn, uint8_t hopPeriod, 00227 bool iqInverted, bool rxContinuous ) 00228 { 00229 SetModem( modem ); 00230 00231 switch( modem ) 00232 { 00233 case MODEM_FSK: 00234 { 00235 this->settings.Fsk.Bandwidth = bandwidth; 00236 this->settings.Fsk.Datarate = datarate; 00237 this->settings.Fsk.BandwidthAfc = bandwidthAfc; 00238 this->settings.Fsk.FixLen = fixLen; 00239 this->settings.Fsk.PayloadLen = payloadLen; 00240 this->settings.Fsk.CrcOn = crcOn; 00241 this->settings.Fsk.IqInverted = iqInverted; 00242 this->settings.Fsk.RxContinuous = rxContinuous; 00243 this->settings.Fsk.PreambleLen = preambleLen; 00244 00245 datarate = ( uint16_t )( ( double )XTAL_FREQ / ( double )datarate ); 00246 Write( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) ); 00247 Write( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) ); 00248 00249 Write( REG_RXBW, GetFskBandwidthRegValue ( bandwidth ) ); 00250 Write( REG_AFCBW, GetFskBandwidthRegValue ( bandwidthAfc ) ); 00251 00252 Write( REG_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) ); 00253 Write( REG_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) ); 00254 00255 if( fixLen == 1 ) 00256 { 00257 Write( REG_PAYLOADLENGTH, payloadLen ); 00258 } 00259 00260 Write( REG_PACKETCONFIG1, 00261 ( Read( REG_PACKETCONFIG1 ) & 00262 RF_PACKETCONFIG1_CRC_MASK & 00263 RF_PACKETCONFIG1_PACKETFORMAT_MASK ) | 00264 ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) | 00265 ( crcOn << 4 ) ); 00266 } 00267 break; 00268 case MODEM_LORA: 00269 { 00270 if( bandwidth > 2 ) 00271 { 00272 // Fatal error: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported 00273 while( 1 ); 00274 } 00275 bandwidth += 7; 00276 this->settings.LoRa.Bandwidth = bandwidth; 00277 this->settings.LoRa.Datarate = datarate; 00278 this->settings.LoRa.Coderate = coderate; 00279 this->settings.LoRa.PreambleLen = preambleLen; 00280 this->settings.LoRa.FixLen = fixLen; 00281 this->settings.LoRa.PayloadLen = payloadLen; 00282 this->settings.LoRa.CrcOn = crcOn; 00283 this->settings.LoRa.FreqHopOn = freqHopOn; 00284 this->settings.LoRa.HopPeriod = hopPeriod; 00285 this->settings.LoRa.IqInverted = iqInverted; 00286 this->settings.LoRa.RxContinuous = rxContinuous; 00287 00288 if( datarate > 12 ) 00289 { 00290 datarate = 12; 00291 } 00292 else if( datarate < 6 ) 00293 { 00294 datarate = 6; 00295 } 00296 00297 if( ( ( bandwidth == 7 ) && ( ( datarate == 11 ) ||( datarate == 11 ) || ( datarate == 12 ) ) ) || 00298 ( ( bandwidth == 8 ) && (( datarate == 11 ) ||( datarate == 12 ) )) ) 00299 00300 { 00301 this->settings.LoRa.LowDatarateOptimize = 0x01; 00302 } 00303 else 00304 { 00305 this->settings.LoRa.LowDatarateOptimize = 0x00; 00306 } 00307 00308 Write( REG_LR_MODEMCONFIG1, 00309 ( Read( REG_LR_MODEMCONFIG1 ) & 00310 RFLR_MODEMCONFIG1_BW_MASK & 00311 RFLR_MODEMCONFIG1_CODINGRATE_MASK & 00312 RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK ) | 00313 ( bandwidth << 4 ) | ( coderate << 1 ) | 00314 fixLen ); 00315 00316 Write( REG_LR_MODEMCONFIG2, 00317 ( Read( REG_LR_MODEMCONFIG2 ) & 00318 RFLR_MODEMCONFIG2_SF_MASK & 00319 RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK & 00320 RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) | 00321 ( datarate << 4 ) | ( crcOn << 2 ) | 00322 ( ( symbTimeout >> 8 ) & ~RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) ); 00323 00324 Write( REG_LR_MODEMCONFIG3, 00325 ( Read( REG_LR_MODEMCONFIG3 ) & 00326 RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK ) | 00327 ( this->settings.LoRa.LowDatarateOptimize << 3 ) ); 00328 00329 Write( REG_LR_SYMBTIMEOUTLSB, ( uint8_t )( symbTimeout & 0xFF ) ); 00330 00331 Write( REG_LR_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) ); 00332 Write( REG_LR_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) ); 00333 00334 if( fixLen == 1 ) 00335 { 00336 Write( REG_LR_PAYLOADLENGTH, payloadLen ); 00337 } 00338 00339 if( this->settings.LoRa.FreqHopOn == true ) 00340 { 00341 Write( REG_LR_PLLHOP, ( Read( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MASK ) | RFLR_PLLHOP_FASTHOP_ON ); 00342 Write( REG_LR_HOPPERIOD, this->settings.LoRa.HopPeriod ); 00343 } 00344 00345 if( ( bandwidth == 9 ) && ( RF_MID_BAND_THRESH ) ) 00346 { 00347 // ERRATA 2.1 - Sensitivity Optimization with a 500 kHz Bandwidth 00348 Write( REG_LR_TEST36, 0x02 ); 00349 Write( REG_LR_TEST3A, 0x64 ); 00350 } 00351 else if( bandwidth == 9 ) 00352 { 00353 // ERRATA 2.1 - Sensitivity Optimization with a 500 kHz Bandwidth 00354 Write( REG_LR_TEST36, 0x02 ); 00355 Write( REG_LR_TEST3A, 0x7F ); 00356 } 00357 else 00358 { 00359 // ERRATA 2.1 - Sensitivity Optimization with a 500 kHz Bandwidth 00360 Write( REG_LR_TEST36, 0x03 ); 00361 } 00362 00363 if( datarate == 6 ) 00364 { 00365 Write( REG_LR_DETECTOPTIMIZE, 00366 ( Read( REG_LR_DETECTOPTIMIZE ) & 00367 RFLR_DETECTIONOPTIMIZE_MASK ) | 00368 RFLR_DETECTIONOPTIMIZE_SF6 ); 00369 Write( REG_LR_DETECTIONTHRESHOLD, 00370 RFLR_DETECTIONTHRESH_SF6 ); 00371 } 00372 else 00373 { 00374 Write( REG_LR_DETECTOPTIMIZE, 00375 ( Read( REG_LR_DETECTOPTIMIZE ) & 00376 RFLR_DETECTIONOPTIMIZE_MASK ) | 00377 RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 ); 00378 Write( REG_LR_DETECTIONTHRESHOLD, 00379 RFLR_DETECTIONTHRESH_SF7_TO_SF12 ); 00380 } 00381 } 00382 break; 00383 } 00384 } 00385 00386 void SX1276::SetTxConfig( RadioModems_t modem, int8_t power, uint32_t fdev, 00387 uint32_t bandwidth, uint32_t datarate, 00388 uint8_t coderate, uint16_t preambleLen, 00389 bool fixLen, bool crcOn, bool freqHopOn, 00390 uint8_t hopPeriod, bool iqInverted, uint32_t timeout ) 00391 { 00392 uint8_t paConfig = 0; 00393 uint8_t paDac = 0; 00394 00395 SetModem( modem ); 00396 00397 paConfig = Read( REG_PACONFIG ); 00398 paDac = Read( REG_PADAC ); 00399 00400 paConfig = ( paConfig & RF_PACONFIG_PASELECT_MASK ) | GetPaSelect( this->settings.Channel ); 00401 paConfig = ( paConfig & RF_PACONFIG_MAX_POWER_MASK ) | 0x70; 00402 00403 if( ( paConfig & RF_PACONFIG_PASELECT_PABOOST ) == RF_PACONFIG_PASELECT_PABOOST ) 00404 { 00405 if( power > 17 ) 00406 { 00407 paDac = ( paDac & RF_PADAC_20DBM_MASK ) | RF_PADAC_20DBM_ON; 00408 } 00409 else 00410 { 00411 paDac = ( paDac & RF_PADAC_20DBM_MASK ) | RF_PADAC_20DBM_OFF; 00412 } 00413 if( ( paDac & RF_PADAC_20DBM_ON ) == RF_PADAC_20DBM_ON ) 00414 { 00415 if( power < 5 ) 00416 { 00417 power = 5; 00418 } 00419 if( power > 20 ) 00420 { 00421 power = 20; 00422 } 00423 paConfig = ( paConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power - 5 ) & 0x0F ); 00424 } 00425 else 00426 { 00427 if( power < 2 ) 00428 { 00429 power = 2; 00430 } 00431 if( power > 17 ) 00432 { 00433 power = 17; 00434 } 00435 paConfig = ( paConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power - 2 ) & 0x0F ); 00436 } 00437 } 00438 else 00439 { 00440 if( power < -1 ) 00441 { 00442 power = -1; 00443 } 00444 if( power > 14 ) 00445 { 00446 power = 14; 00447 } 00448 paConfig = ( paConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power + 1 ) & 0x0F ); 00449 } 00450 Write( REG_PACONFIG, paConfig ); 00451 Write( REG_PADAC, paDac ); 00452 //pcsx.printf("Send in lora mode pa = %d \n",power); 00453 switch( modem ) 00454 { 00455 case MODEM_FSK: 00456 { 00457 this->settings.Fsk.Power = power; 00458 this->settings.Fsk.Fdev = fdev; 00459 this->settings.Fsk.Bandwidth = bandwidth; 00460 this->settings.Fsk.Datarate = datarate; 00461 this->settings.Fsk.PreambleLen = preambleLen; 00462 this->settings.Fsk.FixLen = fixLen; 00463 this->settings.Fsk.CrcOn = crcOn; 00464 this->settings.Fsk.IqInverted = iqInverted; 00465 this->settings.Fsk.TxTimeout = timeout; 00466 00467 fdev = ( uint16_t )( ( double )fdev / ( double )FREQ_STEP ); 00468 Write( REG_FDEVMSB, ( uint8_t )( fdev >> 8 ) ); 00469 Write( REG_FDEVLSB, ( uint8_t )( fdev & 0xFF ) ); 00470 00471 datarate = ( uint16_t )( ( double )XTAL_FREQ / ( double )datarate ); 00472 Write( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) ); 00473 Write( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) ); 00474 00475 Write( REG_PREAMBLEMSB, ( preambleLen >> 8 ) & 0x00FF ); 00476 Write( REG_PREAMBLELSB, preambleLen & 0xFF ); 00477 00478 Write( REG_PACKETCONFIG1, 00479 ( Read( REG_PACKETCONFIG1 ) & 00480 RF_PACKETCONFIG1_CRC_MASK & 00481 RF_PACKETCONFIG1_PACKETFORMAT_MASK ) | 00482 ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) | 00483 ( crcOn << 4 ) ); 00484 00485 } 00486 break; 00487 case MODEM_LORA: 00488 { 00489 this->settings.LoRa.Power = power; 00490 if( bandwidth > 2 ) 00491 { 00492 // Fatal error: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported 00493 while( 1 ); 00494 } 00495 bandwidth += 7; 00496 this->settings.LoRa.Bandwidth = bandwidth; 00497 this->settings.LoRa.Datarate = datarate; 00498 this->settings.LoRa.Coderate = coderate; 00499 this->settings.LoRa.PreambleLen = preambleLen; 00500 this->settings.LoRa.FixLen = fixLen; 00501 this->settings.LoRa.FreqHopOn = freqHopOn; 00502 this->settings.LoRa.HopPeriod = hopPeriod; 00503 this->settings.LoRa.CrcOn = crcOn; 00504 this->settings.LoRa.IqInverted = iqInverted; 00505 this->settings.LoRa.TxTimeout = timeout; 00506 00507 if( datarate > 12 ) 00508 { 00509 datarate = 12; 00510 } 00511 else if( datarate < 6 ) 00512 { 00513 datarate = 6; 00514 } 00515 if( ( ( bandwidth == 7 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) || 00516 ( ( bandwidth == 8 ) && ( datarate == 12 ) ) ) 00517 00518 { 00519 this->settings.LoRa.LowDatarateOptimize = 0x01; 00520 } 00521 else 00522 { 00523 this->settings.LoRa.LowDatarateOptimize = 0x00; 00524 } 00525 00526 if( this->settings.LoRa.FreqHopOn == true ) 00527 { 00528 // DEBUG_PRINT("Send freq hop mod!!!! \n"); 00529 Write( REG_LR_PLLHOP, ( Read( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MASK ) | RFLR_PLLHOP_FASTHOP_ON ); 00530 Write( REG_LR_HOPPERIOD, this->settings.LoRa.HopPeriod ); 00531 } 00532 00533 Write( REG_LR_MODEMCONFIG1, 00534 ( Read( REG_LR_MODEMCONFIG1 ) & 00535 RFLR_MODEMCONFIG1_BW_MASK & 00536 RFLR_MODEMCONFIG1_CODINGRATE_MASK & 00537 RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK ) | 00538 ( bandwidth << 4 ) | ( coderate << 1 ) | 00539 fixLen ); 00540 00541 Write( REG_LR_MODEMCONFIG2, 00542 ( Read( REG_LR_MODEMCONFIG2 ) & 00543 RFLR_MODEMCONFIG2_SF_MASK & 00544 RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK ) | 00545 ( datarate << 4 ) | ( crcOn << 2 ) ); 00546 00547 Write( REG_LR_MODEMCONFIG3, 00548 ( Read( REG_LR_MODEMCONFIG3 ) & 00549 RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK ) | 00550 ( this->settings.LoRa.LowDatarateOptimize << 3 ) ); 00551 00552 Write( REG_LR_PREAMBLEMSB, ( preambleLen >> 8 ) & 0x00FF ); 00553 Write( REG_LR_PREAMBLELSB, preambleLen & 0xFF ); 00554 00555 if( datarate == 6 ) 00556 { 00557 Write( REG_LR_DETECTOPTIMIZE, 00558 ( Read( REG_LR_DETECTOPTIMIZE ) & 00559 RFLR_DETECTIONOPTIMIZE_MASK ) | 00560 RFLR_DETECTIONOPTIMIZE_SF6 ); 00561 Write( REG_LR_DETECTIONTHRESHOLD, 00562 RFLR_DETECTIONTHRESH_SF6 ); 00563 } 00564 else 00565 { 00566 Write( REG_LR_DETECTOPTIMIZE, 00567 ( Read( REG_LR_DETECTOPTIMIZE ) & 00568 RFLR_DETECTIONOPTIMIZE_MASK ) | 00569 RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 ); 00570 Write( REG_LR_DETECTIONTHRESHOLD, 00571 RFLR_DETECTIONTHRESH_SF7_TO_SF12 ); 00572 } 00573 } 00574 break; 00575 } 00576 } 00577 00578 double SX1276::TimeOnAir( RadioModems_t modem, uint8_t pktLen ) 00579 { 00580 uint32_t airTime = 0; 00581 00582 switch( modem ) 00583 { 00584 case MODEM_FSK: 00585 { 00586 airTime = rint( ( 8 * ( this->settings.Fsk.PreambleLen + 00587 ( ( Read( REG_SYNCCONFIG ) & ~RF_SYNCCONFIG_SYNCSIZE_MASK ) + 1 ) + 00588 ( ( this->settings.Fsk.FixLen == 0x01 ) ? 0.0 : 1.0 ) + 00589 ( ( ( Read( REG_PACKETCONFIG1 ) & ~RF_PACKETCONFIG1_ADDRSFILTERING_MASK ) != 0x00 ) ? 1.0 : 0 ) + 00590 pktLen + 00591 ( ( this->settings.Fsk.CrcOn == 0x01 ) ? 2.0 : 0 ) ) / 00592 this->settings.Fsk.Datarate ) * 1e6 ); 00593 } 00594 break; 00595 case MODEM_LORA: 00596 { 00597 double bw = 0.0; 00598 // REMARK: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported 00599 switch( this->settings.LoRa.Bandwidth ) 00600 { 00601 //case 0: // 7.8 kHz 00602 // bw = 78e2; 00603 // break; 00604 //case 1: // 10.4 kHz 00605 // bw = 104e2; 00606 // break; 00607 //case 2: // 15.6 kHz 00608 // bw = 156e2; 00609 // break; 00610 //case 3: // 20.8 kHz 00611 // bw = 208e2; 00612 // break; 00613 //case 4: // 31.2 kHz 00614 // bw = 312e2; 00615 // break; 00616 //case 5: // 41.4 kHz 00617 // bw = 414e2; 00618 // break; 00619 //case 6: // 62.5 kHz 00620 // bw = 625e2; 00621 // break; 00622 case 7: // 125 kHz 00623 bw = 125e3; 00624 break; 00625 case 8: // 250 kHz 00626 bw = 250e3; 00627 break; 00628 case 9: // 500 kHz 00629 bw = 500e3; 00630 break; 00631 } 00632 00633 // Symbol rate : time for one symbol (secs) 00634 double rs = bw / ( 1 << this->settings.LoRa.Datarate ); 00635 double ts = 1 / rs; 00636 // time of preamble 00637 double tPreamble = ( this->settings.LoRa.PreambleLen + 4.25 ) * ts; 00638 // Symbol length of payload and time 00639 double tmp = ceil( ( 8 * pktLen - 4 * this->settings.LoRa.Datarate + 00640 28 + 16 * this->settings.LoRa.CrcOn - 00641 ( this->settings.LoRa.FixLen ? 20 : 0 ) ) / 00642 ( double )( 4 * this->settings.LoRa.Datarate - 00643 ( ( this->settings.LoRa.LowDatarateOptimize > 0 ) ? 2 : 0 ) ) ) * 00644 ( this->settings.LoRa.Coderate + 4 ); 00645 double nPayload = 8 + ( ( tmp > 0 ) ? tmp : 0 ); 00646 double tPayload = nPayload * ts; 00647 // Time on air 00648 double tOnAir = tPreamble + tPayload; 00649 // return us secs 00650 airTime = floor( tOnAir * 1e6 + 0.999 ); 00651 } 00652 break; 00653 } 00654 return airTime; 00655 } 00656 00657 void SX1276::Send( uint8_t *buffer, uint8_t size ) 00658 { 00659 uint32_t txTimeout = 0; 00660 // DEBUG_PRINT(("Send func enter \n")); 00661 //dio0.rise(this, &SX1276::OnDio0Irq); 00662 switch( this->settings.Modem ) 00663 { 00664 case MODEM_FSK: 00665 { 00666 this->settings.FskPacketHandler.NbBytes = 0; 00667 this->settings.FskPacketHandler.Size = size; 00668 00669 if( this->settings.Fsk.FixLen == false ) 00670 { 00671 WriteFifo( ( uint8_t* )&size, 1 ); 00672 } 00673 else 00674 { 00675 Write( REG_PAYLOADLENGTH, size ); 00676 } 00677 00678 if( ( size > 0 ) && ( size <= 64 ) ) 00679 { 00680 this->settings.FskPacketHandler.ChunkSize = size; 00681 } 00682 else 00683 { 00684 this->settings.FskPacketHandler.ChunkSize = 32; 00685 } 00686 00687 // Write payload buffer 00688 WriteFifo( buffer, this->settings.FskPacketHandler.ChunkSize ); 00689 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.ChunkSize; 00690 txTimeout = this->settings.Fsk.TxTimeout; 00691 } 00692 break; 00693 case MODEM_LORA: 00694 { 00695 00696 if( this->settings.LoRa.IqInverted == true ) 00697 { 00698 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_ON ) ); 00699 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON ); 00700 } 00701 else 00702 { 00703 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF ) ); 00704 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF ); 00705 } 00706 00707 this->settings.LoRaPacketHandler.Size = size; 00708 00709 // Initializes the payload size 00710 Write( REG_LR_PAYLOADLENGTH, size ); 00711 00712 // Full buffer used for Tx 00713 Write( REG_LR_FIFOTXBASEADDR, 0 ); 00714 Write( REG_LR_FIFOADDRPTR, 0 ); 00715 00716 // FIFO operations can not take place in Sleep mode 00717 if( ( Read( REG_OPMODE ) & ~RF_OPMODE_MASK ) == RF_OPMODE_SLEEP ) 00718 { 00719 Standby( ); 00720 wait_ms( 1 ); 00721 } 00722 // Write payload buffer 00723 WriteFifo( buffer, size ); 00724 txTimeout = this->settings.LoRa.TxTimeout; 00725 } 00726 break; 00727 } 00728 00729 Tx( txTimeout ); 00730 } 00731 00732 void SX1276::Sleep( void ) 00733 { 00734 txTimeoutTimer .detach( ); 00735 rxTimeoutTimer.detach( ); 00736 00737 SetOpMode( RF_OPMODE_SLEEP ); 00738 this->settings.State = RF_IDLE; 00739 } 00740 00741 void SX1276::Standby( void ) 00742 { 00743 txTimeoutTimer .detach( ); 00744 rxTimeoutTimer.detach( ); 00745 00746 SetOpMode( RF_OPMODE_STANDBY ); 00747 this->settings.State = RF_IDLE; 00748 } 00749 00750 void SX1276::Rx( uint32_t timeout ) 00751 { 00752 bool rxContinuous = false; 00753 00754 switch( this->settings.Modem ) 00755 { 00756 case MODEM_FSK: 00757 { 00758 rxContinuous = this->settings.Fsk.RxContinuous; 00759 00760 // DIO0=PayloadReady 00761 // DIO1=FifoLevel 00762 // DIO2=SyncAddr 00763 // DIO3=FifoEmpty 00764 // DIO4=Preamble 00765 // DIO5=ModeReady 00766 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MASK & 00767 RF_DIOMAPPING1_DIO2_MASK ) | 00768 RF_DIOMAPPING1_DIO0_00 | 00769 RF_DIOMAPPING1_DIO2_11 ); 00770 00771 Write( REG_DIOMAPPING2, ( Read( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MASK & 00772 RF_DIOMAPPING2_MAP_MASK ) | 00773 RF_DIOMAPPING2_DIO4_11 | 00774 RF_DIOMAPPING2_MAP_PREAMBLEDETECT ); 00775 00776 this->settings.FskPacketHandler.FifoThresh = Read( REG_FIFOTHRESH ) & 0x3F; 00777 00778 this->settings.FskPacketHandler.PreambleDetected = false; 00779 this->settings.FskPacketHandler.SyncWordDetected = false; 00780 this->settings.FskPacketHandler.NbBytes = 0; 00781 this->settings.FskPacketHandler.Size = 0; 00782 } 00783 break; 00784 case MODEM_LORA: 00785 { 00786 if( this->settings.LoRa.IqInverted == true ) 00787 { 00788 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_ON | RFLR_INVERTIQ_TX_OFF ) ); 00789 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON ); 00790 } 00791 else 00792 { 00793 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF ) ); 00794 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF ); 00795 } 00796 00797 00798 // ERRATA 2.3 - Receiver Spurious Reception of a LoRa Signal 00799 if( this->settings.LoRa.Bandwidth < 9 ) 00800 { 00801 Write( REG_LR_DETECTOPTIMIZE, Read( REG_LR_DETECTOPTIMIZE ) & 0x7F ); 00802 Write( REG_LR_TEST30, 0x00 ); 00803 switch( this->settings.LoRa.Bandwidth ) 00804 { 00805 case 0: // 7.8 kHz 00806 Write( REG_LR_TEST2F, 0x48 ); 00807 SetChannel(this->settings.Channel + 7.81e3 ); 00808 break; 00809 case 1: // 10.4 kHz 00810 Write( REG_LR_TEST2F, 0x44 ); 00811 SetChannel(this->settings.Channel + 10.42e3 ); 00812 break; 00813 case 2: // 15.6 kHz 00814 Write( REG_LR_TEST2F, 0x44 ); 00815 SetChannel(this->settings.Channel + 15.62e3 ); 00816 break; 00817 case 3: // 20.8 kHz 00818 Write( REG_LR_TEST2F, 0x44 ); 00819 SetChannel(this->settings.Channel + 20.83e3 ); 00820 break; 00821 case 4: // 31.2 kHz 00822 Write( REG_LR_TEST2F, 0x44 ); 00823 SetChannel(this->settings.Channel + 31.25e3 ); 00824 break; 00825 case 5: // 41.4 kHz 00826 Write( REG_LR_TEST2F, 0x44 ); 00827 SetChannel(this->settings.Channel + 41.67e3 ); 00828 break; 00829 case 6: // 62.5 kHz 00830 Write( REG_LR_TEST2F, 0x40 ); 00831 break; 00832 case 7: // 125 kHz 00833 Write( REG_LR_TEST2F, 0x40 ); 00834 break; 00835 case 8: // 250 kHz 00836 Write( REG_LR_TEST2F, 0x40 ); 00837 break; 00838 } 00839 } 00840 else 00841 { 00842 Write( REG_LR_DETECTOPTIMIZE, Read( REG_LR_DETECTOPTIMIZE ) | 0x80 ); 00843 } 00844 00845 rxContinuous = this->settings.LoRa.RxContinuous; 00846 00847 if( this->settings.LoRa.FreqHopOn == true ) 00848 { 00849 Write( REG_LR_IRQFLAGSMASK, //RFLR_IRQFLAGS_RXTIMEOUT | 00850 //RFLR_IRQFLAGS_RXDONE | 00851 RFLR_IRQFLAGS_PAYLOADCRCERROR | 00852 RFLR_IRQFLAGS_VALIDHEADER | 00853 RFLR_IRQFLAGS_TXDONE | 00854 RFLR_IRQFLAGS_CADDONE | 00855 //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL | 00856 RFLR_IRQFLAGS_CADDETECTED ); 00857 00858 // DIO0=RxDone, DIO2=FhssChangeChannel 00859 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK & RFLR_DIOMAPPING1_DIO2_MASK ) | RFLR_DIOMAPPING1_DIO0_00 | RFLR_DIOMAPPING1_DIO2_00 ); 00860 } 00861 else 00862 { 00863 Write( REG_LR_IRQFLAGSMASK, //RFLR_IRQFLAGS_RXTIMEOUT | 00864 //RFLR_IRQFLAGS_RXDONE | 00865 RFLR_IRQFLAGS_PAYLOADCRCERROR | 00866 RFLR_IRQFLAGS_VALIDHEADER | 00867 RFLR_IRQFLAGS_TXDONE | 00868 RFLR_IRQFLAGS_CADDONE | 00869 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL | 00870 RFLR_IRQFLAGS_CADDETECTED ); 00871 00872 // DIO0=RxDone @modify by fabien 00873 //Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_00 ); 00874 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK & RFLR_DIOMAPPING1_DIO1_MASK ) | RFLR_DIOMAPPING1_DIO0_00 | RFLR_DIOMAPPING1_DIO1_00 ); 00875 Write( REG_DIOMAPPING1,0); 00876 } 00877 Write( REG_LR_FIFORXBASEADDR, 0 ); 00878 Write( REG_LR_FIFOADDRPTR, 0 ); 00879 } 00880 break; 00881 } 00882 00883 memset( rxBuffer, 0, ( size_t )RX_BUFFER_SIZE ); 00884 00885 this->settings.State = RF_RX_RUNNING; 00886 if( timeout != 0 ) 00887 { 00888 rxTimeoutTimer.attach_us( this, &SX1276::OnTimeoutIrqtemp, timeout ); 00889 00890 } 00891 00892 if( this->settings.Modem == MODEM_FSK ) 00893 { 00894 SetOpMode( RF_OPMODE_RECEIVER ); 00895 00896 if( rxContinuous == false ) 00897 { 00898 rxTimeoutSyncWord.attach_us( this, &SX1276::OnTimeoutIrq, ( 8.0 * ( this->settings.Fsk.PreambleLen + 00899 ( ( Read( REG_SYNCCONFIG ) & 00900 ~RF_SYNCCONFIG_SYNCSIZE_MASK ) + 00901 1.0 ) + 10.0 ) / 00902 ( double )this->settings.Fsk.Datarate ) * 1e6 ); 00903 } 00904 } 00905 else 00906 { 00907 if( rxContinuous == true ) 00908 { 00909 00910 SetOpMode( RFLR_OPMODE_RECEIVER ); 00911 } 00912 else 00913 { 00914 SetOpMode( RFLR_OPMODE_RECEIVER_SINGLE ); 00915 00916 } 00917 } 00918 00919 00920 } 00921 00922 void SX1276::Tx( uint32_t timeout ) 00923 { 00924 // DEBUG_PRINT("TX func enter\n"); 00925 switch( this->settings.Modem ) 00926 { 00927 case MODEM_FSK: 00928 { 00929 // DIO0=PacketSent 00930 // DIO1=FifoLevel 00931 // DIO2=FifoFull 00932 // DIO3=FifoEmpty 00933 // DIO4=LowBat 00934 // DIO5=ModeReady 00935 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MASK & 00936 RF_DIOMAPPING1_DIO2_MASK ) ); 00937 00938 Write( REG_DIOMAPPING2, ( Read( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MASK & 00939 RF_DIOMAPPING2_MAP_MASK ) ); 00940 this->settings.FskPacketHandler.FifoThresh = Read( REG_FIFOTHRESH ) & 0x3F; 00941 } 00942 break; 00943 case MODEM_LORA: 00944 { 00945 //DEBUG_PRINT("TX func in lora mode enter\n"); 00946 if( this->settings.LoRa.FreqHopOn == true ) 00947 {//DEBUG_PRINT("TX func in lora freqhop enter\n"); 00948 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT | 00949 RFLR_IRQFLAGS_RXDONE | 00950 RFLR_IRQFLAGS_PAYLOADCRCERROR | 00951 RFLR_IRQFLAGS_VALIDHEADER | 00952 //RFLR_IRQFLAGS_TXDONE | 00953 RFLR_IRQFLAGS_CADDONE | 00954 //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL | 00955 RFLR_IRQFLAGS_CADDETECTED ); 00956 00957 // DIO0=TxDone, DIO2=FhssChangeChannel 00958 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK & RFLR_DIOMAPPING1_DIO2_MASK ) | RFLR_DIOMAPPING1_DIO0_01 | RFLR_DIOMAPPING1_DIO2_00 ); 00959 } 00960 else 00961 { 00962 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT | 00963 RFLR_IRQFLAGS_RXDONE | 00964 RFLR_IRQFLAGS_PAYLOADCRCERROR | 00965 RFLR_IRQFLAGS_VALIDHEADER | 00966 //RFLR_IRQFLAGS_TXDONE | 00967 RFLR_IRQFLAGS_CADDONE | 00968 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL | 00969 RFLR_IRQFLAGS_CADDETECTED ); 00970 00971 // DIO0=TxDone 00972 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_01 ); 00973 } 00974 } 00975 break; 00976 } 00977 00978 00979 uint8_t registers[] = { 0x01, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10, 0x11, 0x12, 0x13, 0x014, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,0x33,0x39}; 00980 00981 uint8_t i; 00982 for (i = 0; i < sizeof(registers); i++) 00983 { 00984 // pcsx.printf("registers[%x]", registers[i]); 00985 //pcsx.printf(": "); 00986 //pcsx.printf("%x\n",Read(registers[i])); 00987 } 00988 00989 00990 00991 this->settings.State = RF_TX_RUNNING; 00992 txTimeoutTimer .attach_us( this, &SX1276::OnTimeoutIrq, timeout ); 00993 SetOpMode( RF_OPMODE_TRANSMITTER ); 00994 } 00995 00996 void SX1276::StartCad( void ) 00997 { 00998 switch( this->settings.Modem ) 00999 { 01000 case MODEM_FSK: 01001 { 01002 01003 } 01004 break; 01005 case MODEM_LORA: 01006 { 01007 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT | 01008 RFLR_IRQFLAGS_RXDONE | 01009 RFLR_IRQFLAGS_PAYLOADCRCERROR | 01010 RFLR_IRQFLAGS_VALIDHEADER | 01011 RFLR_IRQFLAGS_TXDONE | 01012 //RFLR_IRQFLAGS_CADDONE | 01013 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL // | 01014 //RFLR_IRQFLAGS_CADDETECTED 01015 ); 01016 01017 // DIO3=CADDone 01018 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_00 ); 01019 01020 this->settings.State = RF_CAD; 01021 SetOpMode( RFLR_OPMODE_CAD ); 01022 } 01023 break; 01024 default: 01025 break; 01026 } 01027 } 01028 01029 int16_t SX1276::GetRssi( RadioModems_t modem ) 01030 { 01031 int16_t rssi = 0; 01032 01033 switch( modem ) 01034 { 01035 case MODEM_FSK: 01036 rssi = -( Read( REG_RSSIVALUE ) >> 1 ); 01037 break; 01038 case MODEM_LORA: 01039 if( this->settings.Channel > RF_MID_BAND_THRESH ) 01040 { 01041 rssi = RSSI_OFFSET_HF + Read( REG_LR_RSSIVALUE ); 01042 } 01043 else 01044 { 01045 rssi = RSSI_OFFSET_LF + Read( REG_LR_RSSIVALUE ); 01046 } 01047 break; 01048 default: 01049 rssi = -1; 01050 break; 01051 } 01052 return rssi; 01053 } 01054 01055 void SX1276::SetOpMode( uint8_t opMode ) 01056 { 01057 if( opMode != previousOpMode ) 01058 { 01059 previousOpMode = opMode; 01060 if( opMode == RF_OPMODE_SLEEP ) 01061 { 01062 SetAntSwLowPower( true ); 01063 } 01064 else 01065 { 01066 SetAntSwLowPower( false ); 01067 if( opMode == RF_OPMODE_TRANSMITTER ) 01068 { 01069 SetAntSw( 1 ); 01070 } 01071 else 01072 { 01073 SetAntSw( 0 ); 01074 } 01075 } 01076 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RF_OPMODE_MASK ) | opMode ); 01077 } 01078 } 01079 01080 void SX1276::SetModem( RadioModems_t modem ) 01081 { 01082 if( this->settings.Modem == modem ) 01083 { 01084 return; 01085 } 01086 01087 this->settings.Modem = modem; 01088 switch( this->settings.Modem ) 01089 { 01090 default: 01091 case MODEM_FSK: 01092 SetOpMode( RF_OPMODE_SLEEP ); 01093 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_OFF ); 01094 01095 Write( REG_DIOMAPPING1, 0x00 ); 01096 Write( REG_DIOMAPPING2, 0x30 ); // DIO5=ModeReady 01097 break; 01098 case MODEM_LORA: 01099 SetOpMode( RF_OPMODE_SLEEP ); 01100 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_ON ); 01101 01102 Write( REG_DIOMAPPING1, 0x00 ); 01103 Write( REG_DIOMAPPING2, 0x00 ); 01104 break; 01105 } 01106 } 01107 01108 void SX1276::SetMaxPayloadLength( RadioModems_t modem, uint8_t max ) 01109 { 01110 this->SetModem( modem ); 01111 01112 switch( modem ) 01113 { 01114 case MODEM_FSK: 01115 if( this->settings.Fsk.FixLen == false ) 01116 { 01117 this->Write( REG_PAYLOADLENGTH, max ); 01118 } 01119 break; 01120 case MODEM_LORA: 01121 this->Write( REG_LR_PAYLOADMAXLENGTH, max ); 01122 break; 01123 } 01124 } 01125 01126 void SX1276::OnTimeoutIrqtemp( void ) 01127 { 01128 // //pcsx.printf("status = %x\n",Read(0x18)); 01129 // if (Read(0x18)==0xF) 01130 // { 01131 // rxTimeoutTimer.detach(); 01132 // rxTimeoutTimer.attach_us( this, &SX1276::OnTimeoutIrq, 3e6 ); 01133 // } 01134 // else 01135 // OnTimeoutIrq(); 01136 } 01137 01138 void SX1276::OnTimeoutIrq( void ) 01139 { 01140 // //DEBUG_PRINT(("TX timeout func in enter irq flag %d\n", Read(REG_LR_IRQFLAGS)); 01141 // Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_TXDONE ); 01142 // // DEBUG_PRINT(("TX timeout func in enter irq flag %d\n", Read(REG_LR_IRQFLAGS)); 01143 // 01144 // switch( this->settings.State ) 01145 // { 01146 // case RF_RX_RUNNING: 01147 // if( this->settings.Modem == MODEM_FSK ) 01148 // { 01149 // this->settings.FskPacketHandler.PreambleDetected = false; 01150 // this->settings.FskPacketHandler.SyncWordDetected = false; 01151 // this->settings.FskPacketHandler.NbBytes = 0; 01152 // this->settings.FskPacketHandler.Size = 0; 01153 01154 // // Clear Irqs 01155 // Write( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI | 01156 // RF_IRQFLAGS1_PREAMBLEDETECT | 01157 // RF_IRQFLAGS1_SYNCADDRESSMATCH ); 01158 // Write( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN ); 01159 01160 // if( this->settings.Fsk.RxContinuous == true ) 01161 // { 01162 // // Continuous mode restart Rx chain 01163 // Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK ); 01164 // } 01165 // else 01166 // { 01167 // this->settings.State = RF_IDLE; 01168 // rxTimeoutSyncWord.detach( ); 01169 // } 01170 // } 01171 // if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxTimeout != NULL ) ) 01172 // { 01173 // this->RadioEvents->RxTimeout( ); 01174 // } 01175 // break; 01176 // case RF_TX_RUNNING: 01177 // this->settings.State = RF_IDLE; 01178 // if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->TxTimeout != NULL ) ) 01179 // { 01180 // this->RadioEvents->TxTimeout( ); 01181 // } 01182 // break; 01183 // default: 01184 // break; 01185 // } 01186 } 01187 01188 void SX1276::OnDio0Irq( void ) 01189 { 01190 volatile uint8_t irqFlags = 0; 01191 //pcsx.printf("TX interrupt func in enter irq flag %d\n", Read(REG_LR_IRQFLAGS)); 01192 switch( this->settings.State ) 01193 { 01194 case RF_RX_RUNNING: 01195 //TimerStop( &RxTimeoutTimer ); 01196 // RxDone interrupt 01197 switch( this->settings.Modem ) 01198 { 01199 case MODEM_FSK: 01200 if( this->settings.Fsk.CrcOn == true ) 01201 { 01202 irqFlags = Read( REG_IRQFLAGS2 ); 01203 if( ( irqFlags & RF_IRQFLAGS2_CRCOK ) != RF_IRQFLAGS2_CRCOK ) 01204 { 01205 // Clear Irqs 01206 Write( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI | 01207 RF_IRQFLAGS1_PREAMBLEDETECT | 01208 RF_IRQFLAGS1_SYNCADDRESSMATCH ); 01209 Write( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN ); 01210 01211 if( this->settings.Fsk.RxContinuous == false ) 01212 { 01213 this->settings.State = RF_IDLE; 01214 rxTimeoutSyncWord.attach_us( this, &SX1276::OnTimeoutIrq, ( 8.0 * ( this->settings.Fsk.PreambleLen + 01215 ( ( Read( REG_SYNCCONFIG ) & 01216 ~RF_SYNCCONFIG_SYNCSIZE_MASK ) + 01217 1.0 ) + 10.0 ) / 01218 ( double )this->settings.Fsk.Datarate ) * 1e6 ) ; 01219 } 01220 else 01221 { 01222 // Continuous mode restart Rx chain 01223 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK ); 01224 } 01225 rxTimeoutTimer.detach( ); 01226 01227 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxError != NULL ) ) 01228 { 01229 this->RadioEvents->RxError( ); 01230 } 01231 this->settings.FskPacketHandler.PreambleDetected = false; 01232 this->settings.FskPacketHandler.SyncWordDetected = false; 01233 this->settings.FskPacketHandler.NbBytes = 0; 01234 this->settings.FskPacketHandler.Size = 0; 01235 break; 01236 } 01237 } 01238 01239 // Read received packet size 01240 if( ( this->settings.FskPacketHandler.Size == 0 ) && ( this->settings.FskPacketHandler.NbBytes == 0 ) ) 01241 { 01242 if( this->settings.Fsk.FixLen == false ) 01243 { 01244 ReadFifo( ( uint8_t* )&this->settings.FskPacketHandler.Size, 1 ); 01245 } 01246 else 01247 { 01248 this->settings.FskPacketHandler.Size = Read( REG_PAYLOADLENGTH ); 01249 } 01250 ReadFifo( rxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ); 01251 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ); 01252 } 01253 else 01254 { 01255 ReadFifo( rxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ); 01256 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ); 01257 } 01258 01259 if( this->settings.Fsk.RxContinuous == false ) 01260 { 01261 this->settings.State = RF_IDLE; 01262 rxTimeoutSyncWord.attach_us( this, &SX1276::OnTimeoutIrq, ( 8.0 * ( this->settings.Fsk.PreambleLen + 01263 ( ( Read( REG_SYNCCONFIG ) & 01264 ~RF_SYNCCONFIG_SYNCSIZE_MASK ) + 01265 1.0 ) + 10.0 ) / 01266 ( double )this->settings.Fsk.Datarate ) * 1e6 ) ; 01267 } 01268 else 01269 { 01270 // Continuous mode restart Rx chain 01271 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK ); 01272 } 01273 rxTimeoutTimer.detach( ); 01274 01275 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxDone != NULL ) ) 01276 { 01277 this->RadioEvents->RxDone( rxBuffer, this->settings.FskPacketHandler.Size, this->settings.FskPacketHandler.RssiValue, 0 ); 01278 } 01279 this->settings.FskPacketHandler.PreambleDetected = false; 01280 this->settings.FskPacketHandler.SyncWordDetected = false; 01281 this->settings.FskPacketHandler.NbBytes = 0; 01282 this->settings.FskPacketHandler.Size = 0; 01283 break; 01284 case MODEM_LORA: 01285 { 01286 int8_t snr = 0; 01287 //pcsx.printf("RX interrupt func in enter irq flag %d\n", Read(REG_LR_IRQFLAGS)); 01288 // Clear Irq 01289 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_RXDONE ); 01290 01291 irqFlags = Read( REG_LR_IRQFLAGS ); 01292 if( ( irqFlags & RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK ) == RFLR_IRQFLAGS_PAYLOADCRCERROR ) 01293 { 01294 // Clear Irq 01295 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_PAYLOADCRCERROR ); 01296 01297 if( this->settings.LoRa.RxContinuous == false ) 01298 { 01299 this->settings.State = RF_IDLE; 01300 } 01301 rxTimeoutTimer.detach( ); 01302 01303 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxError != NULL ) ) 01304 { 01305 this->RadioEvents->RxError( ); 01306 } 01307 break; 01308 } 01309 01310 this->settings.LoRaPacketHandler.SnrValue = Read( REG_LR_PKTSNRVALUE ); 01311 if( this->settings.LoRaPacketHandler.SnrValue & 0x80 ) // The SNR sign bit is 1 01312 { 01313 // Invert and divide by 4 01314 snr = ( ( ~this->settings.LoRaPacketHandler.SnrValue + 1 ) & 0xFF ) >> 2; 01315 snr = -snr; 01316 } 01317 else 01318 { 01319 // Divide by 4 01320 snr = ( this->settings.LoRaPacketHandler.SnrValue & 0xFF ) >> 2; 01321 } 01322 01323 int16_t rssi = Read( REG_LR_PKTRSSIVALUE ); 01324 if( snr < 0 ) 01325 { 01326 if( this->settings.Channel > RF_MID_BAND_THRESH ) 01327 { 01328 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_HF + rssi + ( rssi >> 4 ) + 01329 snr; 01330 } 01331 else 01332 { 01333 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_LF + rssi + ( rssi >> 4 ) + 01334 snr; 01335 } 01336 } 01337 else 01338 { 01339 if( this->settings.Channel > RF_MID_BAND_THRESH ) 01340 { 01341 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_HF + rssi + ( rssi >> 4 ); 01342 } 01343 else 01344 { 01345 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_LF + rssi + ( rssi >> 4 ); 01346 } 01347 } 01348 01349 this->settings.LoRaPacketHandler.Size = Read( REG_LR_RXNBBYTES ); 01350 ReadFifo( rxBuffer, this->settings.LoRaPacketHandler.Size ); 01351 01352 if( this->settings.LoRa.RxContinuous == false ) 01353 { 01354 this->settings.State = RF_IDLE; 01355 } 01356 rxTimeoutTimer.detach( ); 01357 01358 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxDone != NULL ) ) 01359 { 01360 this->RadioEvents->RxDone( rxBuffer, this->settings.LoRaPacketHandler.Size, this->settings.LoRaPacketHandler.RssiValue, this->settings.LoRaPacketHandler.SnrValue ); 01361 } 01362 } 01363 break; 01364 default: 01365 break; 01366 } 01367 break; 01368 case RF_TX_RUNNING: 01369 txTimeoutTimer .detach( ); 01370 // TxDone interrupt 01371 switch( this->settings.Modem ) 01372 { 01373 case MODEM_LORA: 01374 // Clear Irq 01375 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_TXDONE ); 01376 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->TxDone != NULL ) ) 01377 { 01378 this->RadioEvents->TxDone( ); 01379 } 01380 case MODEM_FSK: 01381 default: 01382 this->settings.State = RF_IDLE; 01383 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->TxDone != NULL ) ) 01384 { 01385 this->RadioEvents->TxDone( ); 01386 } 01387 break; 01388 } 01389 break; 01390 default: 01391 01392 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->TxDone != NULL ) ) 01393 { 01394 this->RadioEvents->TxDone( ); 01395 } 01396 break; 01397 } 01398 } 01399 01400 void SX1276::OnDio1Irq( void ) 01401 { 01402 switch( this->settings.State ) 01403 { 01404 case RF_RX_RUNNING: 01405 switch( this->settings.Modem ) 01406 { 01407 case MODEM_FSK: 01408 // FifoLevel interrupt 01409 // Read received packet size 01410 if( ( this->settings.FskPacketHandler.Size == 0 ) && ( this->settings.FskPacketHandler.NbBytes == 0 ) ) 01411 { 01412 if( this->settings.Fsk.FixLen == false ) 01413 { 01414 ReadFifo( ( uint8_t* )&this->settings.FskPacketHandler.Size, 1 ); 01415 } 01416 else 01417 { 01418 this->settings.FskPacketHandler.Size = Read( REG_PAYLOADLENGTH ); 01419 } 01420 } 01421 01422 if( ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ) > this->settings.FskPacketHandler.FifoThresh ) 01423 { 01424 ReadFifo( ( rxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.FifoThresh ); 01425 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.FifoThresh; 01426 } 01427 else 01428 { 01429 ReadFifo( ( rxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ); 01430 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ); 01431 } 01432 break; 01433 case MODEM_LORA: 01434 // Sync time out 01435 rxTimeoutTimer.detach( ); 01436 this->settings.State = RF_IDLE; 01437 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxTimeout != NULL ) ) 01438 { 01439 this->RadioEvents->RxTimeout( ); 01440 } 01441 break; 01442 default: 01443 break; 01444 } 01445 break; 01446 case RF_TX_RUNNING: 01447 switch( this->settings.Modem ) 01448 { 01449 case MODEM_FSK: 01450 // FifoLevel interrupt 01451 if( ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ) > this->settings.FskPacketHandler.ChunkSize ) 01452 { 01453 WriteFifo( ( rxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.ChunkSize ); 01454 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.ChunkSize; 01455 } 01456 else 01457 { 01458 // Write the last chunk of data 01459 WriteFifo( rxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ); 01460 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes; 01461 } 01462 break; 01463 case MODEM_LORA: 01464 break; 01465 default: 01466 break; 01467 } 01468 break; 01469 default: 01470 break; 01471 } 01472 } 01473 01474 void SX1276::OnDio2Irq( void ) 01475 { 01476 switch( this->settings.State ) 01477 { 01478 case RF_RX_RUNNING: 01479 switch( this->settings.Modem ) 01480 { 01481 case MODEM_FSK: 01482 if( ( this->settings.FskPacketHandler.PreambleDetected == true ) && ( this->settings.FskPacketHandler.SyncWordDetected == false ) ) 01483 { 01484 rxTimeoutSyncWord.detach( ); 01485 01486 this->settings.FskPacketHandler.SyncWordDetected = true; 01487 01488 this->settings.FskPacketHandler.RssiValue = -( Read( REG_RSSIVALUE ) >> 1 ); 01489 01490 this->settings.FskPacketHandler.AfcValue = ( int32_t )( double )( ( ( uint16_t )Read( REG_AFCMSB ) << 8 ) | 01491 ( uint16_t )Read( REG_AFCLSB ) ) * 01492 ( double )FREQ_STEP; 01493 this->settings.FskPacketHandler.RxGain = ( Read( REG_LNA ) >> 5 ) & 0x07; 01494 } 01495 break; 01496 case MODEM_LORA: 01497 if( this->settings.LoRa.FreqHopOn == true ) 01498 { 01499 // Clear Irq 01500 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL ); 01501 01502 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->FhssChangeChannel != NULL ) ) 01503 { 01504 this->RadioEvents->FhssChangeChannel( ( Read( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ) ); 01505 } 01506 } 01507 break; 01508 default: 01509 break; 01510 } 01511 break; 01512 case RF_TX_RUNNING: 01513 switch( this->settings.Modem ) 01514 { 01515 case MODEM_FSK: 01516 break; 01517 case MODEM_LORA: 01518 if( this->settings.LoRa.FreqHopOn == true ) 01519 { 01520 // Clear Irq 01521 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL ); 01522 01523 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->FhssChangeChannel != NULL ) ) 01524 { 01525 this->RadioEvents->FhssChangeChannel( ( Read( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ) ); 01526 } 01527 } 01528 break; 01529 default: 01530 break; 01531 } 01532 break; 01533 default: 01534 break; 01535 } 01536 } 01537 01538 void SX1276::OnDio3Irq( void ) 01539 { 01540 switch( this->settings.Modem ) 01541 { 01542 case MODEM_FSK: 01543 break; 01544 case MODEM_LORA: 01545 if( ( Read( REG_LR_IRQFLAGS ) & RFLR_IRQFLAGS_CADDETECTED ) == RFLR_IRQFLAGS_CADDETECTED ) 01546 { 01547 // Clear Irq 01548 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDETECTED | RFLR_IRQFLAGS_CADDONE ); 01549 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->CadDone != NULL ) ) 01550 { 01551 this->RadioEvents->CadDone( true ); 01552 } 01553 } 01554 else 01555 { 01556 // Clear Irq 01557 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDONE ); 01558 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->CadDone != NULL ) ) 01559 { 01560 this->RadioEvents->CadDone( false ); 01561 } 01562 } 01563 break; 01564 default: 01565 break; 01566 } 01567 } 01568 01569 void SX1276::OnDio4Irq( void ) 01570 { 01571 switch( this->settings.Modem ) 01572 { 01573 case MODEM_FSK: 01574 { 01575 if( this->settings.FskPacketHandler.PreambleDetected == false ) 01576 { 01577 this->settings.FskPacketHandler.PreambleDetected = true; 01578 } 01579 } 01580 break; 01581 case MODEM_LORA: 01582 break; 01583 default: 01584 break; 01585 } 01586 } 01587 01588 void SX1276::OnDio5Irq( void ) 01589 { 01590 switch( this->settings.Modem ) 01591 { 01592 case MODEM_FSK: 01593 break; 01594 case MODEM_LORA: 01595 break; 01596 default: 01597 break; 01598 } 01599 }
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