Fabio Fumi / SDFileSystem

Library for SD card

Dependents:   SDFileSystem_HelloWorld Sharp_ce140f_emul

SDFileSystem.cpp@1:3488faedd0d1, 21 months ago (annotated)

Committer:
ffxx68
Date:
Fri Jul 15 09:04:31 2022 +0000
Revision:
1:3488faedd0d1
Parent:
0:3bdfc1556537
Child:
2:02f003d025a7
Initial revision

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AlexVC97 0:3bdfc1556537 1 /* mbed Microcontroller Library
AlexVC97 0:3bdfc1556537 2 * Copyright (c) 2006-2012 ARM Limited
AlexVC97 0:3bdfc1556537 3 *
AlexVC97 0:3bdfc1556537 4 * Permission is hereby granted, free of charge, to any person obtaining a copy
AlexVC97 0:3bdfc1556537 5 * of this software and associated documentation files (the "Software"), to deal
AlexVC97 0:3bdfc1556537 6 * in the Software without restriction, including without limitation the rights
AlexVC97 0:3bdfc1556537 7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
AlexVC97 0:3bdfc1556537 8 * copies of the Software, and to permit persons to whom the Software is
AlexVC97 0:3bdfc1556537 9 * furnished to do so, subject to the following conditions:
AlexVC97 0:3bdfc1556537 10 *
AlexVC97 0:3bdfc1556537 11 * The above copyright notice and this permission notice shall be included in
AlexVC97 0:3bdfc1556537 12 * all copies or substantial portions of the Software.
AlexVC97 0:3bdfc1556537 13 *
AlexVC97 0:3bdfc1556537 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
AlexVC97 0:3bdfc1556537 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
AlexVC97 0:3bdfc1556537 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AlexVC97 0:3bdfc1556537 17 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
AlexVC97 0:3bdfc1556537 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
AlexVC97 0:3bdfc1556537 19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
AlexVC97 0:3bdfc1556537 20 * SOFTWARE.
AlexVC97 0:3bdfc1556537 21 */
AlexVC97 0:3bdfc1556537 22 /* Introduction
AlexVC97 0:3bdfc1556537 23 * ------------
AlexVC97 0:3bdfc1556537 24 * SD and MMC cards support a number of interfaces, but common to them all
AlexVC97 0:3bdfc1556537 25 * is one based on SPI. This is the one I'm implmenting because it means
AlexVC97 0:3bdfc1556537 26 * it is much more portable even though not so performant, and we already
AlexVC97 0:3bdfc1556537 27 * have the mbed SPI Interface!
AlexVC97 0:3bdfc1556537 28 *
AlexVC97 0:3bdfc1556537 29 * The main reference I'm using is Chapter 7, "SPI Mode" of:
AlexVC97 0:3bdfc1556537 30 * http://www.sdcard.org/developers/tech/sdcard/pls/Simplified_Physical_Layer_Spec.pdf
AlexVC97 0:3bdfc1556537 31 *
ffxx68 1:3488faedd0d1 32 * SPI Startup
AlexVC97 0:3bdfc1556537 33 * -----------
ffxx68 1:3488faedd0d1 34 * The SD card powers up in SD mode. The start-up procedure is complicated
ffxx68 1:3488faedd0d1 35 * by the requirement to support older SDCards in a backwards compatible
ffxx68 1:3488faedd0d1 36 * way with the new higher capacity variants SDHC and SDHC.
ffxx68 1:3488faedd0d1 37 *
ffxx68 1:3488faedd0d1 38 * The following figures from the specification with associated text describe
ffxx68 1:3488faedd0d1 39 * the SPI mode initialisation process:
ffxx68 1:3488faedd0d1 40 * - Figure 7-1: SD Memory Card State Diagram (SPI mode)
ffxx68 1:3488faedd0d1 41 * - Figure 7-2: SPI Mode Initialization Flow
ffxx68 1:3488faedd0d1 42 *
ffxx68 1:3488faedd0d1 43 * Firstly, a low initial clock should be selected (in the range of 100-
ffxx68 1:3488faedd0d1 44 * 400kHZ). After initialisation has been completed, the switch to a
ffxx68 1:3488faedd0d1 45 * higher clock speed can be made (e.g. 1MHz). Newer cards will support
ffxx68 1:3488faedd0d1 46 * higher speeds than the default _transfer_sck defined here.
ffxx68 1:3488faedd0d1 47 *
ffxx68 1:3488faedd0d1 48 * After power up, we need to provide at least 1 msec delay and 74 clock cycles
ffxx68 1:3488faedd0d1 49 * before sending any command to an SD Card. Since we get 8 clock cycles with each byte,
ffxx68 1:3488faedd0d1 50 * we can send 10 bytes for a total of 80 clock cycles.
ffxx68 1:3488faedd0d1 51 * The SDCard spec also specifies that CS must be held high during this period.
ffxx68 1:3488faedd0d1 52 *
ffxx68 1:3488faedd0d1 53 * Next, note the following from the SDCard specification (note to
ffxx68 1:3488faedd0d1 54 * Figure 7-1):
ffxx68 1:3488faedd0d1 55 *
ffxx68 1:3488faedd0d1 56 * In any of the cases CMD1 is not recommended because it may be difficult for the host
ffxx68 1:3488faedd0d1 57 * to distinguish between MultiMediaCard and SD Memory Card
ffxx68 1:3488faedd0d1 58 *
ffxx68 1:3488faedd0d1 59 * Hence CMD1 is not used for the initialisation sequence.
ffxx68 1:3488faedd0d1 60 *
ffxx68 1:3488faedd0d1 61 * The SPI interface mode is selected by asserting CS low and sending the
ffxx68 1:3488faedd0d1 62 * reset command (CMD0). The card will respond with a (R1) response.
ffxx68 1:3488faedd0d1 63 * In practice many cards initially respond with 0xff or invalid data
ffxx68 1:3488faedd0d1 64 * which is ignored. Data is read until a valid response is received
ffxx68 1:3488faedd0d1 65 * or the number of re-reads has exceeded a maximim count. If a valid
ffxx68 1:3488faedd0d1 66 * response is not received then the CMD0 can be retried. This
ffxx68 1:3488faedd0d1 67 * has been found to successfully initialise cards where the SPI master
ffxx68 1:3488faedd0d1 68 * (on MCU) has been reset but the SDCard has not, so the first
ffxx68 1:3488faedd0d1 69 * CMD0 may be lost.
AlexVC97 0:3bdfc1556537 70 *
AlexVC97 0:3bdfc1556537 71 * CMD8 is optionally sent to determine the voltage range supported, and
AlexVC97 0:3bdfc1556537 72 * indirectly determine whether it is a version 1.x SD/non-SD card or
AlexVC97 0:3bdfc1556537 73 * version 2.x. I'll just ignore this for now.
AlexVC97 0:3bdfc1556537 74 *
AlexVC97 0:3bdfc1556537 75 * ACMD41 is repeatedly issued to initialise the card, until "in idle"
AlexVC97 0:3bdfc1556537 76 * (bit 0) of the R1 response goes to '0', indicating it is initialised.
AlexVC97 0:3bdfc1556537 77 *
AlexVC97 0:3bdfc1556537 78 * You should also indicate whether the host supports High Capicity cards,
AlexVC97 0:3bdfc1556537 79 * and check whether the card is high capacity - i'll also ignore this
AlexVC97 0:3bdfc1556537 80 *
AlexVC97 0:3bdfc1556537 81 * SPI Protocol
AlexVC97 0:3bdfc1556537 82 * ------------
AlexVC97 0:3bdfc1556537 83 * The SD SPI protocol is based on transactions made up of 8-bit words, with
AlexVC97 0:3bdfc1556537 84 * the host starting every bus transaction by asserting the CS signal low. The
AlexVC97 0:3bdfc1556537 85 * card always responds to commands, data blocks and errors.
AlexVC97 0:3bdfc1556537 86 *
AlexVC97 0:3bdfc1556537 87 * The protocol supports a CRC, but by default it is off (except for the
AlexVC97 0:3bdfc1556537 88 * first reset CMD0, where the CRC can just be pre-calculated, and CMD8)
AlexVC97 0:3bdfc1556537 89 * I'll leave the CRC off I think!
AlexVC97 0:3bdfc1556537 90 *
AlexVC97 0:3bdfc1556537 91 * Standard capacity cards have variable data block sizes, whereas High
AlexVC97 0:3bdfc1556537 92 * Capacity cards fix the size of data block to 512 bytes. I'll therefore
AlexVC97 0:3bdfc1556537 93 * just always use the Standard Capacity cards with a block size of 512 bytes.
AlexVC97 0:3bdfc1556537 94 * This is set with CMD16.
AlexVC97 0:3bdfc1556537 95 *
AlexVC97 0:3bdfc1556537 96 * You can read and write single blocks (CMD17, CMD25) or multiple blocks
AlexVC97 0:3bdfc1556537 97 * (CMD18, CMD25). For simplicity, I'll just use single block accesses. When
AlexVC97 0:3bdfc1556537 98 * the card gets a read command, it responds with a response token, and then
AlexVC97 0:3bdfc1556537 99 * a data token or an error.
AlexVC97 0:3bdfc1556537 100 *
AlexVC97 0:3bdfc1556537 101 * SPI Command Format
AlexVC97 0:3bdfc1556537 102 * ------------------
AlexVC97 0:3bdfc1556537 103 * Commands are 6-bytes long, containing the command, 32-bit argument, and CRC.
AlexVC97 0:3bdfc1556537 104 *
AlexVC97 0:3bdfc1556537 105 * +---------------+------------+------------+-----------+----------+--------------+
AlexVC97 0:3bdfc1556537 106 * | 01 | cmd[5:0] | arg[31:24] | arg[23:16] | arg[15:8] | arg[7:0] | crc[6:0] | 1 |
AlexVC97 0:3bdfc1556537 107 * +---------------+------------+------------+-----------+----------+--------------+
AlexVC97 0:3bdfc1556537 108 *
AlexVC97 0:3bdfc1556537 109 * As I'm not using CRC, I can fix that byte to what is needed for CMD0 (0x95)
AlexVC97 0:3bdfc1556537 110 *
AlexVC97 0:3bdfc1556537 111 * All Application Specific commands shall be preceded with APP_CMD (CMD55).
AlexVC97 0:3bdfc1556537 112 *
AlexVC97 0:3bdfc1556537 113 * SPI Response Format
AlexVC97 0:3bdfc1556537 114 * -------------------
AlexVC97 0:3bdfc1556537 115 * The main response format (R1) is a status byte (normally zero). Key flags:
AlexVC97 0:3bdfc1556537 116 * idle - 1 if the card is in an idle state/initialising
AlexVC97 0:3bdfc1556537 117 * cmd - 1 if an illegal command code was detected
AlexVC97 0:3bdfc1556537 118 *
AlexVC97 0:3bdfc1556537 119 * +-------------------------------------------------+
AlexVC97 0:3bdfc1556537 120 * R1 | 0 | arg | addr | seq | crc | cmd | erase | idle |
AlexVC97 0:3bdfc1556537 121 * +-------------------------------------------------+
AlexVC97 0:3bdfc1556537 122 *
AlexVC97 0:3bdfc1556537 123 * R1b is the same, except it is followed by a busy signal (zeros) until
AlexVC97 0:3bdfc1556537 124 * the first non-zero byte when it is ready again.
AlexVC97 0:3bdfc1556537 125 *
AlexVC97 0:3bdfc1556537 126 * Data Response Token
AlexVC97 0:3bdfc1556537 127 * -------------------
AlexVC97 0:3bdfc1556537 128 * Every data block written to the card is acknowledged by a byte
AlexVC97 0:3bdfc1556537 129 * response token
AlexVC97 0:3bdfc1556537 130 *
AlexVC97 0:3bdfc1556537 131 * +----------------------+
AlexVC97 0:3bdfc1556537 132 * | xxx | 0 | status | 1 |
AlexVC97 0:3bdfc1556537 133 * +----------------------+
AlexVC97 0:3bdfc1556537 134 * 010 - OK!
AlexVC97 0:3bdfc1556537 135 * 101 - CRC Error
AlexVC97 0:3bdfc1556537 136 * 110 - Write Error
AlexVC97 0:3bdfc1556537 137 *
AlexVC97 0:3bdfc1556537 138 * Single Block Read and Write
AlexVC97 0:3bdfc1556537 139 * ---------------------------
AlexVC97 0:3bdfc1556537 140 *
AlexVC97 0:3bdfc1556537 141 * Block transfers have a byte header, followed by the data, followed
AlexVC97 0:3bdfc1556537 142 * by a 16-bit CRC. In our case, the data will always be 512 bytes.
AlexVC97 0:3bdfc1556537 143 *
AlexVC97 0:3bdfc1556537 144 * +------+---------+---------+- - - -+---------+-----------+----------+
AlexVC97 0:3bdfc1556537 145 * | 0xFE | data[0] | data[1] | | data[n] | crc[15:8] | crc[7:0] |
AlexVC97 0:3bdfc1556537 146 * +------+---------+---------+- - - -+---------+-----------+----------+
ffxx68 1:3488faedd0d1 147 *
ffxx68 1:3488faedd0d1 148 *
ffxx68 1:3488faedd0d1 149 *
AlexVC97 0:3bdfc1556537 150 */
AlexVC97 0:3bdfc1556537 151 #include "SDFileSystem.h"
AlexVC97 0:3bdfc1556537 152 #include "mbed_debug.h"
AlexVC97 0:3bdfc1556537 153
ffxx68 1:3488faedd0d1 154 #define SD_COMMAND_TIMEOUT 0x10/*5000*/
ffxx68 1:3488faedd0d1 155 #define SD_CMD0_GO_IDLE_STATE_RETRIES 3
ffxx68 1:3488faedd0d1 156 #define SD_CMD0_GO_IDLE_STATE 0x00
ffxx68 1:3488faedd0d1 157 #define SD_DBG 1
AlexVC97 0:3bdfc1556537 158
AlexVC97 0:3bdfc1556537 159 SDFileSystem::SDFileSystem(PinName mosi, PinName miso, PinName sclk, PinName cs, const char* name) :
AlexVC97 0:3bdfc1556537 160 FATFileSystem(name), _spi(mosi, miso, sclk), _cs(cs), _is_initialized(0) {
AlexVC97 0:3bdfc1556537 161 _cs = 1;
AlexVC97 0:3bdfc1556537 162
ffxx68 1:3488faedd0d1 163 // Set default frquency, for initialisation and data transfer
ffxx68 1:3488faedd0d1 164 _init_sck = 400000;
AlexVC97 0:3bdfc1556537 165 _transfer_sck = 1000000;
AlexVC97 0:3bdfc1556537 166 }
AlexVC97 0:3bdfc1556537 167
ffxx68 1:3488faedd0d1 168 // R1 bits
AlexVC97 0:3bdfc1556537 169 #define R1_IDLE_STATE (1 << 0)
AlexVC97 0:3bdfc1556537 170 #define R1_ERASE_RESET (1 << 1)
AlexVC97 0:3bdfc1556537 171 #define R1_ILLEGAL_COMMAND (1 << 2)
AlexVC97 0:3bdfc1556537 172 #define R1_COM_CRC_ERROR (1 << 3)
AlexVC97 0:3bdfc1556537 173 #define R1_ERASE_SEQUENCE_ERROR (1 << 4)
AlexVC97 0:3bdfc1556537 174 #define R1_ADDRESS_ERROR (1 << 5)
AlexVC97 0:3bdfc1556537 175 #define R1_PARAMETER_ERROR (1 << 6)
AlexVC97 0:3bdfc1556537 176
AlexVC97 0:3bdfc1556537 177 // Types
AlexVC97 0:3bdfc1556537 178 // - v1.x Standard Capacity
AlexVC97 0:3bdfc1556537 179 // - v2.x Standard Capacity
AlexVC97 0:3bdfc1556537 180 // - v2.x High Capacity
AlexVC97 0:3bdfc1556537 181 // - Not recognised as an SD Card
AlexVC97 0:3bdfc1556537 182 #define SDCARD_FAIL 0
AlexVC97 0:3bdfc1556537 183 #define SDCARD_V1 1
AlexVC97 0:3bdfc1556537 184 #define SDCARD_V2 2
AlexVC97 0:3bdfc1556537 185 #define SDCARD_V2HC 3
AlexVC97 0:3bdfc1556537 186
ffxx68 1:3488faedd0d1 187 /* SDFileSystem::_go_idle_state()
ffxx68 1:3488faedd0d1 188 *
ffxx68 1:3488faedd0d1 189 * ARGUMENTS
ffxx68 1:3488faedd0d1 190 * None
ffxx68 1:3488faedd0d1 191 * DETAILS:
ffxx68 1:3488faedd0d1 192 * Put the SDCard into the SPI Mode idle state by sending the CMD0
ffxx68 1:3488faedd0d1 193 * (GO_IDLE_STATE) command. See the notes in the "SPI Startup" section
ffxx68 1:3488faedd0d1 194 * of the comments at the head of this file.
ffxx68 1:3488faedd0d1 195 *
ffxx68 1:3488faedd0d1 196 * RETURN:
ffxx68 1:3488faedd0d1 197 * -1 an error occured e.g. a valid response was not received.
ffxx68 1:3488faedd0d1 198 * R1_IDLE_STATE (0x1), the successful response from CMD0.
ffxx68 1:3488faedd0d1 199 */
ffxx68 1:3488faedd0d1 200 int SDFileSystem::_go_idle_state() {
ffxx68 1:3488faedd0d1 201 _spi.lock();
ffxx68 1:3488faedd0d1 202
ffxx68 1:3488faedd0d1 203
ffxx68 1:3488faedd0d1 204
ffxx68 1:3488faedd0d1 205 int cmd_arg = 0; /* CMD0 argument is just "stuff bits"*/
ffxx68 1:3488faedd0d1 206
ffxx68 1:3488faedd0d1 207 /* Resetting the MCU SPI master may not reset the on-board SDCard, in which
ffxx68 1:3488faedd0d1 208 * case when MCU power-on occurs the SDCard will resume operations as
ffxx68 1:3488faedd0d1 209 * though there was no reset. In this scenario the first CMD0 will
ffxx68 1:3488faedd0d1 210 * not be interpretted as a command and get lost. For some cards retrying
ffxx68 1:3488faedd0d1 211 * the command overcomes this situation. */
ffxx68 1:3488faedd0d1 212 for (int num_retries = 0; num_retries < SD_CMD0_GO_IDLE_STATE_RETRIES; num_retries++) {
ffxx68 1:3488faedd0d1 213
ffxx68 1:3488faedd0d1 214 // Set to SCK for initialisation, and clock card with cs = 1
ffxx68 1:3488faedd0d1 215 _cs = 1;
ffxx68 1:3488faedd0d1 216 // Initial delay
ffxx68 1:3488faedd0d1 217 wait_us (1000);
ffxx68 1:3488faedd0d1 218 // Initial 74 cycles required for few cards, before selecting SPI mode
ffxx68 1:3488faedd0d1 219 for (int i = 0; i < 16; i++) {
ffxx68 1:3488faedd0d1 220 _spi.write(0xFF);
ffxx68 1:3488faedd0d1 221 }
ffxx68 1:3488faedd0d1 222
ffxx68 1:3488faedd0d1 223 /* send a CMD0, with /CS asserted */
ffxx68 1:3488faedd0d1 224 _cs = 0;
ffxx68 1:3488faedd0d1 225 _spi.write(0x40 | SD_CMD0_GO_IDLE_STATE);
ffxx68 1:3488faedd0d1 226 _spi.write(cmd_arg >> 24);
ffxx68 1:3488faedd0d1 227 _spi.write(cmd_arg >> 16);
ffxx68 1:3488faedd0d1 228 _spi.write(cmd_arg >> 8);
ffxx68 1:3488faedd0d1 229 _spi.write(cmd_arg >> 0);
ffxx68 1:3488faedd0d1 230 _spi.write(0x95);
ffxx68 1:3488faedd0d1 231
ffxx68 1:3488faedd0d1 232 // wait for the response (response[7] == 0)
ffxx68 1:3488faedd0d1 233 for (int i = 0; i < SD_COMMAND_TIMEOUT; i++) {
ffxx68 1:3488faedd0d1 234 int response = _spi.write(0xFF);
ffxx68 1:3488faedd0d1 235 /* Explicitly check for the R1_IDLE_STATE response rather that most significant bit
ffxx68 1:3488faedd0d1 236 * being 0 because invalid data can be returned. */
ffxx68 1:3488faedd0d1 237 if (response != R1_IDLE_STATE)
ffxx68 1:3488faedd0d1 238 debug_if(SD_DBG, "CMD0 #%d (retry #%d) response: 0x%.2X\n", i, num_retries, response);
ffxx68 1:3488faedd0d1 239 else {
ffxx68 1:3488faedd0d1 240 _cs = 1;
ffxx68 1:3488faedd0d1 241 _spi.write(0xFF);
ffxx68 1:3488faedd0d1 242 _spi.unlock();
ffxx68 1:3488faedd0d1 243 return response;
ffxx68 1:3488faedd0d1 244 }
ffxx68 1:3488faedd0d1 245
ffxx68 1:3488faedd0d1 246 }
ffxx68 1:3488faedd0d1 247 }
ffxx68 1:3488faedd0d1 248 _cs = 1;
ffxx68 1:3488faedd0d1 249 _spi.write(0xFF);
ffxx68 1:3488faedd0d1 250 _spi.unlock();
ffxx68 1:3488faedd0d1 251 return -1; // timeout
ffxx68 1:3488faedd0d1 252 }
ffxx68 1:3488faedd0d1 253
AlexVC97 0:3bdfc1556537 254 int SDFileSystem::initialise_card() {
ffxx68 1:3488faedd0d1 255
ffxx68 1:3488faedd0d1 256 _spi.lock();
ffxx68 1:3488faedd0d1 257 _spi.format(8, 0);
AlexVC97 0:3bdfc1556537 258 _spi.frequency(_init_sck);
ffxx68 1:3488faedd0d1 259 _spi.unlock();
ffxx68 1:3488faedd0d1 260
ffxx68 1:3488faedd0d1 261 /* moved within _go_idle_state
AlexVC97 0:3bdfc1556537 262 _cs = 1;
ffxx68 1:3488faedd0d1 263 // Initial delay
ffxx68 1:3488faedd0d1 264 wait_us (1000);
ffxx68 1:3488faedd0d1 265 // Initial 74 cycles required for few cards, before selecting SPI mode
AlexVC97 0:3bdfc1556537 266 for (int i = 0; i < 16; i++) {
AlexVC97 0:3bdfc1556537 267 _spi.write(0xFF);
AlexVC97 0:3bdfc1556537 268 }
ffxx68 1:3488faedd0d1 269 */
ffxx68 1:3488faedd0d1 270
ffxx68 1:3488faedd0d1 271 /* Transition from SD Card mode to SPI mode by sending CMD0 GO_IDLE_STATE command */
ffxx68 1:3488faedd0d1 272 if (_go_idle_state() != R1_IDLE_STATE) {
ffxx68 1:3488faedd0d1 273 debug_if(SD_DBG, "No disk, or could not put SD card in to SPI idle state\n");
ffxx68 1:3488faedd0d1 274 return SDCARD_FAIL;
ffxx68 1:3488faedd0d1 275 }
ffxx68 1:3488faedd0d1 276 /* send CMD0, should return with all zeros except IDLE STATE set (bit 0)
AlexVC97 0:3bdfc1556537 277 if (_cmd(0, 0) != R1_IDLE_STATE) {
AlexVC97 0:3bdfc1556537 278 debug("No disk, or could not put SD card in to SPI idle state\n");
AlexVC97 0:3bdfc1556537 279 return SDCARD_FAIL;
AlexVC97 0:3bdfc1556537 280 }
ffxx68 1:3488faedd0d1 281 */
AlexVC97 0:3bdfc1556537 282
AlexVC97 0:3bdfc1556537 283 // send CMD8 to determine whther it is ver 2.x
AlexVC97 0:3bdfc1556537 284 int r = _cmd8();
AlexVC97 0:3bdfc1556537 285 if (r == R1_IDLE_STATE) {
AlexVC97 0:3bdfc1556537 286 return initialise_card_v2();
AlexVC97 0:3bdfc1556537 287 } else if (r == (R1_IDLE_STATE | R1_ILLEGAL_COMMAND)) {
AlexVC97 0:3bdfc1556537 288 return initialise_card_v1();
AlexVC97 0:3bdfc1556537 289 } else {
AlexVC97 0:3bdfc1556537 290 debug("Not in idle state after sending CMD8 (not an SD card?)\n");
AlexVC97 0:3bdfc1556537 291 return SDCARD_FAIL;
AlexVC97 0:3bdfc1556537 292 }
AlexVC97 0:3bdfc1556537 293 }
AlexVC97 0:3bdfc1556537 294
AlexVC97 0:3bdfc1556537 295 int SDFileSystem::initialise_card_v1() {
AlexVC97 0:3bdfc1556537 296 for (int i = 0; i < SD_COMMAND_TIMEOUT; i++) {
AlexVC97 0:3bdfc1556537 297 _cmd(55, 0);
AlexVC97 0:3bdfc1556537 298 if (_cmd(41, 0) == 0) {
AlexVC97 0:3bdfc1556537 299 cdv = 512;
AlexVC97 0:3bdfc1556537 300 debug_if(SD_DBG, "\n\rInit: SEDCARD_V1\n\r");
AlexVC97 0:3bdfc1556537 301 return SDCARD_V1;
AlexVC97 0:3bdfc1556537 302 }
AlexVC97 0:3bdfc1556537 303 }
AlexVC97 0:3bdfc1556537 304
AlexVC97 0:3bdfc1556537 305 debug("Timeout waiting for v1.x card\n");
AlexVC97 0:3bdfc1556537 306 return SDCARD_FAIL;
AlexVC97 0:3bdfc1556537 307 }
AlexVC97 0:3bdfc1556537 308
AlexVC97 0:3bdfc1556537 309 int SDFileSystem::initialise_card_v2() {
AlexVC97 0:3bdfc1556537 310 for (int i = 0; i < SD_COMMAND_TIMEOUT; i++) {
AlexVC97 0:3bdfc1556537 311 wait_ms(50);
AlexVC97 0:3bdfc1556537 312 _cmd58();
AlexVC97 0:3bdfc1556537 313 _cmd(55, 0);
AlexVC97 0:3bdfc1556537 314 if (_cmd(41, 0x40000000) == 0) {
AlexVC97 0:3bdfc1556537 315 _cmd58();
AlexVC97 0:3bdfc1556537 316 debug_if(SD_DBG, "\n\rInit: SDCARD_V2\n\r");
AlexVC97 0:3bdfc1556537 317 cdv = 1;
AlexVC97 0:3bdfc1556537 318 return SDCARD_V2;
AlexVC97 0:3bdfc1556537 319 }
AlexVC97 0:3bdfc1556537 320 }
AlexVC97 0:3bdfc1556537 321
AlexVC97 0:3bdfc1556537 322 debug("Timeout waiting for v2.x card\n");
AlexVC97 0:3bdfc1556537 323 return SDCARD_FAIL;
AlexVC97 0:3bdfc1556537 324 }
AlexVC97 0:3bdfc1556537 325
AlexVC97 0:3bdfc1556537 326 int SDFileSystem::disk_initialize() {
AlexVC97 0:3bdfc1556537 327 _is_initialized = initialise_card();
AlexVC97 0:3bdfc1556537 328 if (_is_initialized == 0) {
AlexVC97 0:3bdfc1556537 329 debug("Fail to initialize card\n");
AlexVC97 0:3bdfc1556537 330 return 1;
AlexVC97 0:3bdfc1556537 331 }
AlexVC97 0:3bdfc1556537 332 debug_if(SD_DBG, "init card = %d\n", _is_initialized);
AlexVC97 0:3bdfc1556537 333 _sectors = _sd_sectors();
AlexVC97 0:3bdfc1556537 334
AlexVC97 0:3bdfc1556537 335 // Set block length to 512 (CMD16)
AlexVC97 0:3bdfc1556537 336 if (_cmd(16, 512) != 0) {
AlexVC97 0:3bdfc1556537 337 debug("Set 512-byte block timed out\n");
AlexVC97 0:3bdfc1556537 338 return 1;
AlexVC97 0:3bdfc1556537 339 }
AlexVC97 0:3bdfc1556537 340
AlexVC97 0:3bdfc1556537 341 // Set SCK for data transfer
AlexVC97 0:3bdfc1556537 342 _spi.frequency(_transfer_sck);
AlexVC97 0:3bdfc1556537 343 return 0;
AlexVC97 0:3bdfc1556537 344 }
AlexVC97 0:3bdfc1556537 345
AlexVC97 0:3bdfc1556537 346 int SDFileSystem::disk_write(const uint8_t* buffer, uint32_t block_number, uint32_t count) {
AlexVC97 0:3bdfc1556537 347 if (!_is_initialized) {
AlexVC97 0:3bdfc1556537 348 return -1;
AlexVC97 0:3bdfc1556537 349 }
AlexVC97 0:3bdfc1556537 350
AlexVC97 0:3bdfc1556537 351 for (uint32_t b = block_number; b < block_number + count; b++) {
AlexVC97 0:3bdfc1556537 352 // set write address for single block (CMD24)
AlexVC97 0:3bdfc1556537 353 if (_cmd(24, b * cdv) != 0) {
AlexVC97 0:3bdfc1556537 354 return 1;
AlexVC97 0:3bdfc1556537 355 }
AlexVC97 0:3bdfc1556537 356
AlexVC97 0:3bdfc1556537 357 // send the data block
AlexVC97 0:3bdfc1556537 358 _write(buffer, 512);
AlexVC97 0:3bdfc1556537 359 buffer += 512;
AlexVC97 0:3bdfc1556537 360 }
AlexVC97 0:3bdfc1556537 361
AlexVC97 0:3bdfc1556537 362 return 0;
AlexVC97 0:3bdfc1556537 363 }
AlexVC97 0:3bdfc1556537 364
AlexVC97 0:3bdfc1556537 365 int SDFileSystem::disk_read(uint8_t* buffer, uint32_t block_number, uint32_t count) {
AlexVC97 0:3bdfc1556537 366 if (!_is_initialized) {
AlexVC97 0:3bdfc1556537 367 return -1;
AlexVC97 0:3bdfc1556537 368 }
AlexVC97 0:3bdfc1556537 369
AlexVC97 0:3bdfc1556537 370 for (uint32_t b = block_number; b < block_number + count; b++) {
AlexVC97 0:3bdfc1556537 371 // set read address for single block (CMD17)
AlexVC97 0:3bdfc1556537 372 if (_cmd(17, b * cdv) != 0) {
AlexVC97 0:3bdfc1556537 373 return 1;
AlexVC97 0:3bdfc1556537 374 }
AlexVC97 0:3bdfc1556537 375
AlexVC97 0:3bdfc1556537 376 // receive the data
AlexVC97 0:3bdfc1556537 377 _read(buffer, 512);
AlexVC97 0:3bdfc1556537 378 buffer += 512;
AlexVC97 0:3bdfc1556537 379 }
AlexVC97 0:3bdfc1556537 380
AlexVC97 0:3bdfc1556537 381 return 0;
AlexVC97 0:3bdfc1556537 382 }
AlexVC97 0:3bdfc1556537 383
AlexVC97 0:3bdfc1556537 384 int SDFileSystem::disk_status() {
AlexVC97 0:3bdfc1556537 385 // FATFileSystem::disk_status() returns 0 when initialized
AlexVC97 0:3bdfc1556537 386 if (_is_initialized) {
AlexVC97 0:3bdfc1556537 387 return 0;
AlexVC97 0:3bdfc1556537 388 } else {
AlexVC97 0:3bdfc1556537 389 return 1;
AlexVC97 0:3bdfc1556537 390 }
AlexVC97 0:3bdfc1556537 391 }
AlexVC97 0:3bdfc1556537 392
AlexVC97 0:3bdfc1556537 393 int SDFileSystem::disk_sync() { return 0; }
AlexVC97 0:3bdfc1556537 394 uint32_t SDFileSystem::disk_sectors() { return _sectors; }
AlexVC97 0:3bdfc1556537 395
AlexVC97 0:3bdfc1556537 396
AlexVC97 0:3bdfc1556537 397 // PRIVATE FUNCTIONS
AlexVC97 0:3bdfc1556537 398 int SDFileSystem::_cmd(int cmd, int arg) {
AlexVC97 0:3bdfc1556537 399 _cs = 0;
AlexVC97 0:3bdfc1556537 400
AlexVC97 0:3bdfc1556537 401 // send a command
AlexVC97 0:3bdfc1556537 402 _spi.write(0x40 | cmd);
AlexVC97 0:3bdfc1556537 403 _spi.write(arg >> 24);
AlexVC97 0:3bdfc1556537 404 _spi.write(arg >> 16);
AlexVC97 0:3bdfc1556537 405 _spi.write(arg >> 8);
AlexVC97 0:3bdfc1556537 406 _spi.write(arg >> 0);
AlexVC97 0:3bdfc1556537 407 _spi.write(0x95);
AlexVC97 0:3bdfc1556537 408
AlexVC97 0:3bdfc1556537 409 // wait for the repsonse (response[7] == 0)
AlexVC97 0:3bdfc1556537 410 for (int i = 0; i < SD_COMMAND_TIMEOUT; i++) {
AlexVC97 0:3bdfc1556537 411 int response = _spi.write(0xFF);
AlexVC97 0:3bdfc1556537 412 if (!(response & 0x80)) {
AlexVC97 0:3bdfc1556537 413 _cs = 1;
AlexVC97 0:3bdfc1556537 414 _spi.write(0xFF);
AlexVC97 0:3bdfc1556537 415 return response;
AlexVC97 0:3bdfc1556537 416 }
AlexVC97 0:3bdfc1556537 417 }
AlexVC97 0:3bdfc1556537 418 _cs = 1;
AlexVC97 0:3bdfc1556537 419 _spi.write(0xFF);
AlexVC97 0:3bdfc1556537 420 return -1; // timeout
AlexVC97 0:3bdfc1556537 421 }
AlexVC97 0:3bdfc1556537 422 int SDFileSystem::_cmdx(int cmd, int arg) {
AlexVC97 0:3bdfc1556537 423 _cs = 0;
AlexVC97 0:3bdfc1556537 424
AlexVC97 0:3bdfc1556537 425 // send a command
AlexVC97 0:3bdfc1556537 426 _spi.write(0x40 | cmd);
AlexVC97 0:3bdfc1556537 427 _spi.write(arg >> 24);
AlexVC97 0:3bdfc1556537 428 _spi.write(arg >> 16);
AlexVC97 0:3bdfc1556537 429 _spi.write(arg >> 8);
AlexVC97 0:3bdfc1556537 430 _spi.write(arg >> 0);
AlexVC97 0:3bdfc1556537 431 _spi.write(0x95);
AlexVC97 0:3bdfc1556537 432
AlexVC97 0:3bdfc1556537 433 // wait for the repsonse (response[7] == 0)
AlexVC97 0:3bdfc1556537 434 for (int i = 0; i < SD_COMMAND_TIMEOUT; i++) {
AlexVC97 0:3bdfc1556537 435 int response = _spi.write(0xFF);
AlexVC97 0:3bdfc1556537 436 if (!(response & 0x80)) {
AlexVC97 0:3bdfc1556537 437 return response;
AlexVC97 0:3bdfc1556537 438 }
AlexVC97 0:3bdfc1556537 439 }
AlexVC97 0:3bdfc1556537 440 _cs = 1;
AlexVC97 0:3bdfc1556537 441 _spi.write(0xFF);
AlexVC97 0:3bdfc1556537 442 return -1; // timeout
AlexVC97 0:3bdfc1556537 443 }
AlexVC97 0:3bdfc1556537 444
AlexVC97 0:3bdfc1556537 445
AlexVC97 0:3bdfc1556537 446 int SDFileSystem::_cmd58() {
AlexVC97 0:3bdfc1556537 447 _cs = 0;
AlexVC97 0:3bdfc1556537 448 int arg = 0;
AlexVC97 0:3bdfc1556537 449
AlexVC97 0:3bdfc1556537 450 // send a command
AlexVC97 0:3bdfc1556537 451 _spi.write(0x40 | 58);
AlexVC97 0:3bdfc1556537 452 _spi.write(arg >> 24);
AlexVC97 0:3bdfc1556537 453 _spi.write(arg >> 16);
AlexVC97 0:3bdfc1556537 454 _spi.write(arg >> 8);
AlexVC97 0:3bdfc1556537 455 _spi.write(arg >> 0);
AlexVC97 0:3bdfc1556537 456 _spi.write(0x95);
AlexVC97 0:3bdfc1556537 457
AlexVC97 0:3bdfc1556537 458 // wait for the repsonse (response[7] == 0)
AlexVC97 0:3bdfc1556537 459 for (int i = 0; i < SD_COMMAND_TIMEOUT; i++) {
AlexVC97 0:3bdfc1556537 460 int response = _spi.write(0xFF);
AlexVC97 0:3bdfc1556537 461 if (!(response & 0x80)) {
AlexVC97 0:3bdfc1556537 462 int ocr = _spi.write(0xFF) << 24;
AlexVC97 0:3bdfc1556537 463 ocr |= _spi.write(0xFF) << 16;
AlexVC97 0:3bdfc1556537 464 ocr |= _spi.write(0xFF) << 8;
AlexVC97 0:3bdfc1556537 465 ocr |= _spi.write(0xFF) << 0;
AlexVC97 0:3bdfc1556537 466 _cs = 1;
AlexVC97 0:3bdfc1556537 467 _spi.write(0xFF);
AlexVC97 0:3bdfc1556537 468 return response;
AlexVC97 0:3bdfc1556537 469 }
AlexVC97 0:3bdfc1556537 470 }
AlexVC97 0:3bdfc1556537 471 _cs = 1;
AlexVC97 0:3bdfc1556537 472 _spi.write(0xFF);
AlexVC97 0:3bdfc1556537 473 return -1; // timeout
AlexVC97 0:3bdfc1556537 474 }
AlexVC97 0:3bdfc1556537 475
AlexVC97 0:3bdfc1556537 476 int SDFileSystem::_cmd8() {
AlexVC97 0:3bdfc1556537 477 _cs = 0;
AlexVC97 0:3bdfc1556537 478
AlexVC97 0:3bdfc1556537 479 // send a command
AlexVC97 0:3bdfc1556537 480 _spi.write(0x40 | 8); // CMD8
AlexVC97 0:3bdfc1556537 481 _spi.write(0x00); // reserved
AlexVC97 0:3bdfc1556537 482 _spi.write(0x00); // reserved
AlexVC97 0:3bdfc1556537 483 _spi.write(0x01); // 3.3v
AlexVC97 0:3bdfc1556537 484 _spi.write(0xAA); // check pattern
AlexVC97 0:3bdfc1556537 485 _spi.write(0x87); // crc
AlexVC97 0:3bdfc1556537 486
AlexVC97 0:3bdfc1556537 487 // wait for the repsonse (response[7] == 0)
AlexVC97 0:3bdfc1556537 488 for (int i = 0; i < SD_COMMAND_TIMEOUT * 1000; i++) {
AlexVC97 0:3bdfc1556537 489 char response[5];
AlexVC97 0:3bdfc1556537 490 response[0] = _spi.write(0xFF);
AlexVC97 0:3bdfc1556537 491 if (!(response[0] & 0x80)) {
AlexVC97 0:3bdfc1556537 492 for (int j = 1; j < 5; j++) {
AlexVC97 0:3bdfc1556537 493 response[i] = _spi.write(0xFF);
AlexVC97 0:3bdfc1556537 494 }
AlexVC97 0:3bdfc1556537 495 _cs = 1;
AlexVC97 0:3bdfc1556537 496 _spi.write(0xFF);
AlexVC97 0:3bdfc1556537 497 return response[0];
AlexVC97 0:3bdfc1556537 498 }
AlexVC97 0:3bdfc1556537 499 }
AlexVC97 0:3bdfc1556537 500 _cs = 1;
AlexVC97 0:3bdfc1556537 501 _spi.write(0xFF);
AlexVC97 0:3bdfc1556537 502 return -1; // timeout
AlexVC97 0:3bdfc1556537 503 }
AlexVC97 0:3bdfc1556537 504
AlexVC97 0:3bdfc1556537 505 int SDFileSystem::_read(uint8_t *buffer, uint32_t length) {
AlexVC97 0:3bdfc1556537 506 _cs = 0;
AlexVC97 0:3bdfc1556537 507
AlexVC97 0:3bdfc1556537 508 // read until start byte (0xFF)
AlexVC97 0:3bdfc1556537 509 while (_spi.write(0xFF) != 0xFE);
AlexVC97 0:3bdfc1556537 510
AlexVC97 0:3bdfc1556537 511 // read data
AlexVC97 0:3bdfc1556537 512 for (uint32_t i = 0; i < length; i++) {
AlexVC97 0:3bdfc1556537 513 buffer[i] = _spi.write(0xFF);
AlexVC97 0:3bdfc1556537 514 }
AlexVC97 0:3bdfc1556537 515 _spi.write(0xFF); // checksum
AlexVC97 0:3bdfc1556537 516 _spi.write(0xFF);
AlexVC97 0:3bdfc1556537 517
AlexVC97 0:3bdfc1556537 518 _cs = 1;
AlexVC97 0:3bdfc1556537 519 _spi.write(0xFF);
AlexVC97 0:3bdfc1556537 520 return 0;
AlexVC97 0:3bdfc1556537 521 }
AlexVC97 0:3bdfc1556537 522
AlexVC97 0:3bdfc1556537 523 int SDFileSystem::_write(const uint8_t*buffer, uint32_t length) {
AlexVC97 0:3bdfc1556537 524 _cs = 0;
AlexVC97 0:3bdfc1556537 525
AlexVC97 0:3bdfc1556537 526 // indicate start of block
AlexVC97 0:3bdfc1556537 527 _spi.write(0xFE);
AlexVC97 0:3bdfc1556537 528
AlexVC97 0:3bdfc1556537 529 // write the data
AlexVC97 0:3bdfc1556537 530 for (uint32_t i = 0; i < length; i++) {
AlexVC97 0:3bdfc1556537 531 _spi.write(buffer[i]);
AlexVC97 0:3bdfc1556537 532 }
AlexVC97 0:3bdfc1556537 533
AlexVC97 0:3bdfc1556537 534 // write the checksum
AlexVC97 0:3bdfc1556537 535 _spi.write(0xFF);
AlexVC97 0:3bdfc1556537 536 _spi.write(0xFF);
AlexVC97 0:3bdfc1556537 537
AlexVC97 0:3bdfc1556537 538 // check the response token
AlexVC97 0:3bdfc1556537 539 if ((_spi.write(0xFF) & 0x1F) != 0x05) {
AlexVC97 0:3bdfc1556537 540 _cs = 1;
AlexVC97 0:3bdfc1556537 541 _spi.write(0xFF);
AlexVC97 0:3bdfc1556537 542 return 1;
AlexVC97 0:3bdfc1556537 543 }
AlexVC97 0:3bdfc1556537 544
AlexVC97 0:3bdfc1556537 545 // wait for write to finish
AlexVC97 0:3bdfc1556537 546 while (_spi.write(0xFF) == 0);
AlexVC97 0:3bdfc1556537 547
AlexVC97 0:3bdfc1556537 548 _cs = 1;
AlexVC97 0:3bdfc1556537 549 _spi.write(0xFF);
AlexVC97 0:3bdfc1556537 550 return 0;
AlexVC97 0:3bdfc1556537 551 }
AlexVC97 0:3bdfc1556537 552
AlexVC97 0:3bdfc1556537 553 static uint32_t ext_bits(unsigned char *data, int msb, int lsb) {
AlexVC97 0:3bdfc1556537 554 uint32_t bits = 0;
AlexVC97 0:3bdfc1556537 555 uint32_t size = 1 + msb - lsb;
AlexVC97 0:3bdfc1556537 556 for (uint32_t i = 0; i < size; i++) {
AlexVC97 0:3bdfc1556537 557 uint32_t position = lsb + i;
AlexVC97 0:3bdfc1556537 558 uint32_t byte = 15 - (position >> 3);
AlexVC97 0:3bdfc1556537 559 uint32_t bit = position & 0x7;
AlexVC97 0:3bdfc1556537 560 uint32_t value = (data[byte] >> bit) & 1;
AlexVC97 0:3bdfc1556537 561 bits |= value << i;
AlexVC97 0:3bdfc1556537 562 }
AlexVC97 0:3bdfc1556537 563 return bits;
AlexVC97 0:3bdfc1556537 564 }
AlexVC97 0:3bdfc1556537 565
AlexVC97 0:3bdfc1556537 566 uint32_t SDFileSystem::_sd_sectors() {
AlexVC97 0:3bdfc1556537 567 uint32_t c_size, c_size_mult, read_bl_len;
AlexVC97 0:3bdfc1556537 568 uint32_t block_len, mult, blocknr, capacity;
AlexVC97 0:3bdfc1556537 569 uint32_t hc_c_size;
AlexVC97 0:3bdfc1556537 570 uint32_t blocks;
AlexVC97 0:3bdfc1556537 571
AlexVC97 0:3bdfc1556537 572 // CMD9, Response R2 (R1 byte + 16-byte block read)
AlexVC97 0:3bdfc1556537 573 if (_cmdx(9, 0) != 0) {
AlexVC97 0:3bdfc1556537 574 debug("Didn't get a response from the disk\n");
AlexVC97 0:3bdfc1556537 575 return 0;
AlexVC97 0:3bdfc1556537 576 }
AlexVC97 0:3bdfc1556537 577
AlexVC97 0:3bdfc1556537 578 uint8_t csd[16];
AlexVC97 0:3bdfc1556537 579 if (_read(csd, 16) != 0) {
AlexVC97 0:3bdfc1556537 580 debug("Couldn't read csd response from disk\n");
AlexVC97 0:3bdfc1556537 581 return 0;
AlexVC97 0:3bdfc1556537 582 }
AlexVC97 0:3bdfc1556537 583
AlexVC97 0:3bdfc1556537 584 // csd_structure : csd[127:126]
AlexVC97 0:3bdfc1556537 585 // c_size : csd[73:62]
AlexVC97 0:3bdfc1556537 586 // c_size_mult : csd[49:47]
AlexVC97 0:3bdfc1556537 587 // read_bl_len : csd[83:80] - the *maximum* read block length
AlexVC97 0:3bdfc1556537 588
AlexVC97 0:3bdfc1556537 589 int csd_structure = ext_bits(csd, 127, 126);
AlexVC97 0:3bdfc1556537 590
AlexVC97 0:3bdfc1556537 591 switch (csd_structure) {
AlexVC97 0:3bdfc1556537 592 case 0:
AlexVC97 0:3bdfc1556537 593 cdv = 512;
AlexVC97 0:3bdfc1556537 594 c_size = ext_bits(csd, 73, 62);
AlexVC97 0:3bdfc1556537 595 c_size_mult = ext_bits(csd, 49, 47);
AlexVC97 0:3bdfc1556537 596 read_bl_len = ext_bits(csd, 83, 80);
AlexVC97 0:3bdfc1556537 597
AlexVC97 0:3bdfc1556537 598 block_len = 1 << read_bl_len;
AlexVC97 0:3bdfc1556537 599 mult = 1 << (c_size_mult + 2);
AlexVC97 0:3bdfc1556537 600 blocknr = (c_size + 1) * mult;
AlexVC97 0:3bdfc1556537 601 capacity = blocknr * block_len;
AlexVC97 0:3bdfc1556537 602 blocks = capacity / 512;
AlexVC97 0:3bdfc1556537 603 debug_if(SD_DBG, "\n\rSDCard\n\rc_size: %d \n\rcapacity: %ld \n\rsectors: %lld\n\r", c_size, capacity, blocks);
AlexVC97 0:3bdfc1556537 604 break;
AlexVC97 0:3bdfc1556537 605
AlexVC97 0:3bdfc1556537 606 case 1:
AlexVC97 0:3bdfc1556537 607 cdv = 1;
AlexVC97 0:3bdfc1556537 608 hc_c_size = ext_bits(csd, 63, 48);
AlexVC97 0:3bdfc1556537 609 blocks = (hc_c_size+1)*1024;
AlexVC97 0:3bdfc1556537 610 debug_if(SD_DBG, "\n\rSDHC Card \n\rhc_c_size: %d\n\rcapacity: %lld \n\rsectors: %lld\n\r", hc_c_size, blocks*512, blocks);
AlexVC97 0:3bdfc1556537 611 break;
AlexVC97 0:3bdfc1556537 612
AlexVC97 0:3bdfc1556537 613 default:
AlexVC97 0:3bdfc1556537 614 debug("CSD struct unsupported\r\n");
AlexVC97 0:3bdfc1556537 615 return 0;
AlexVC97 0:3bdfc1556537 616 };
AlexVC97 0:3bdfc1556537 617 return blocks;
AlexVC97 0:3bdfc1556537 618 }