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rtx/TARGET_ARM7/rt_HAL_CM.h@127:bf4dda6a6a1b, 2017-11-18 (annotated)

Committer:
feupos
Date:
Sat Nov 18 18:27:08 2017 +0000
Revision:
127:bf4dda6a6a1b
Parent:
80:2dab120a94c2 
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UserRevisionLine numberNew contents of line
mbed_official 80:2dab120a94c2 1 /*----------------------------------------------------------------------------
mbed_official 80:2dab120a94c2 2 * RL-ARM - RTX
mbed_official 80:2dab120a94c2 3 *----------------------------------------------------------------------------
mbed_official 80:2dab120a94c2 4 * Name: RT_HAL_CM.H
mbed_official 80:2dab120a94c2 5 * Purpose: Hardware Abstraction Layer for Cortex-M definitions
mbed_official 80:2dab120a94c2 6 * Rev.: V4.60
mbed_official 80:2dab120a94c2 7 *----------------------------------------------------------------------------
mbed_official 80:2dab120a94c2 8 *
mbed_official 80:2dab120a94c2 9 * Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
mbed_official 80:2dab120a94c2 10 * All rights reserved.
mbed_official 80:2dab120a94c2 11 * Redistribution and use in source and binary forms, with or without
mbed_official 80:2dab120a94c2 12 * modification, are permitted provided that the following conditions are met:
mbed_official 80:2dab120a94c2 13 * - Redistributions of source code must retain the above copyright
mbed_official 80:2dab120a94c2 14 * notice, this list of conditions and the following disclaimer.
mbed_official 80:2dab120a94c2 15 * - Redistributions in binary form must reproduce the above copyright
mbed_official 80:2dab120a94c2 16 * notice, this list of conditions and the following disclaimer in the
mbed_official 80:2dab120a94c2 17 * documentation and/or other materials provided with the distribution.
mbed_official 80:2dab120a94c2 18 * - Neither the name of ARM nor the names of its contributors may be used
mbed_official 80:2dab120a94c2 19 * to endorse or promote products derived from this software without
mbed_official 80:2dab120a94c2 20 * specific prior written permission.
mbed_official 80:2dab120a94c2 21 *
mbed_official 80:2dab120a94c2 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 80:2dab120a94c2 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 80:2dab120a94c2 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
mbed_official 80:2dab120a94c2 25 * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
mbed_official 80:2dab120a94c2 26 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
mbed_official 80:2dab120a94c2 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
mbed_official 80:2dab120a94c2 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mbed_official 80:2dab120a94c2 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mbed_official 80:2dab120a94c2 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
mbed_official 80:2dab120a94c2 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
mbed_official 80:2dab120a94c2 32 * POSSIBILITY OF SUCH DAMAGE.
mbed_official 80:2dab120a94c2 33 *---------------------------------------------------------------------------*/
mbed_official 80:2dab120a94c2 34
mbed_official 80:2dab120a94c2 35 #include "cmsis.h"
mbed_official 80:2dab120a94c2 36 /* Definitions */
mbed_official 80:2dab120a94c2 37 #define INITIAL_xPSR 0x10000000
mbed_official 80:2dab120a94c2 38 #define DEMCR_TRCENA 0x01000000
mbed_official 80:2dab120a94c2 39 #define ITM_ITMENA 0x00000001
mbed_official 80:2dab120a94c2 40 #define MAGIC_WORD 0xE25A2EA5
mbed_official 80:2dab120a94c2 41
mbed_official 80:2dab120a94c2 42 #define SYS_TICK_IRQn TIMER0_IRQn
mbed_official 80:2dab120a94c2 43
mbed_official 80:2dab120a94c2 44 extern void rt_set_PSP (U32 stack);
mbed_official 80:2dab120a94c2 45 extern U32 rt_get_PSP (void);
mbed_official 80:2dab120a94c2 46 extern void os_set_env (void);
mbed_official 80:2dab120a94c2 47 extern void SysTick_Handler (void);
mbed_official 80:2dab120a94c2 48 extern void *_alloc_box (void *box_mem);
mbed_official 80:2dab120a94c2 49 extern int _free_box (void *box_mem, void *box);
mbed_official 80:2dab120a94c2 50
mbed_official 80:2dab120a94c2 51 extern void rt_init_stack (P_TCB p_TCB, FUNCP task_body);
mbed_official 80:2dab120a94c2 52 extern void rt_ret_val (P_TCB p_TCB, U32 v0);
mbed_official 80:2dab120a94c2 53 extern void rt_ret_val2 (P_TCB p_TCB, U32 v0, U32 v1);
mbed_official 80:2dab120a94c2 54
mbed_official 80:2dab120a94c2 55 extern void dbg_init (void);
mbed_official 80:2dab120a94c2 56 extern void dbg_task_notify (P_TCB p_tcb, BOOL create);
mbed_official 80:2dab120a94c2 57 extern void dbg_task_switch (U32 task_id);
mbed_official 80:2dab120a94c2 58
mbed_official 80:2dab120a94c2 59
mbed_official 80:2dab120a94c2 60 #if defined (__CC_ARM) /* ARM Compiler */
mbed_official 80:2dab120a94c2 61
mbed_official 80:2dab120a94c2 62 #if ((__TARGET_ARCH_7_M || __TARGET_ARCH_7E_M) && !NO_EXCLUSIVE_ACCESS)
mbed_official 80:2dab120a94c2 63 #define __USE_EXCLUSIVE_ACCESS
mbed_official 80:2dab120a94c2 64 #else
mbed_official 80:2dab120a94c2 65 #undef __USE_EXCLUSIVE_ACCESS
mbed_official 80:2dab120a94c2 66 #endif
mbed_official 80:2dab120a94c2 67
mbed_official 80:2dab120a94c2 68 #elif defined (__GNUC__) /* GNU Compiler */
mbed_official 80:2dab120a94c2 69
mbed_official 80:2dab120a94c2 70 #undef __USE_EXCLUSIVE_ACCESS
mbed_official 80:2dab120a94c2 71
mbed_official 80:2dab120a94c2 72 #if defined (__CORTEX_M0) || defined (__CORTEX_M0PLUS)
mbed_official 80:2dab120a94c2 73 #define __TARGET_ARCH_6S_M 1
mbed_official 80:2dab120a94c2 74 #else
mbed_official 80:2dab120a94c2 75 #define __TARGET_ARCH_6S_M 0
mbed_official 80:2dab120a94c2 76 #endif
mbed_official 80:2dab120a94c2 77
mbed_official 80:2dab120a94c2 78 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
mbed_official 80:2dab120a94c2 79 #define __TARGET_FPU_VFP 1
mbed_official 80:2dab120a94c2 80 #else
mbed_official 80:2dab120a94c2 81 #define __TARGET_FPU_VFP 0
mbed_official 80:2dab120a94c2 82 #endif
mbed_official 80:2dab120a94c2 83
mbed_official 80:2dab120a94c2 84 #define __inline inline
mbed_official 80:2dab120a94c2 85 #define __weak __attribute__((weak))
mbed_official 80:2dab120a94c2 86
mbed_official 80:2dab120a94c2 87
mbed_official 80:2dab120a94c2 88 #elif defined (__ICCARM__) /* IAR Compiler */
mbed_official 80:2dab120a94c2 89
mbed_official 80:2dab120a94c2 90 #undef __USE_EXCLUSIVE_ACCESS
mbed_official 80:2dab120a94c2 91
mbed_official 80:2dab120a94c2 92 #if (__CORE__ == __ARM6M__)
mbed_official 80:2dab120a94c2 93 #define __TARGET_ARCH_6S_M 1
mbed_official 80:2dab120a94c2 94 #else
mbed_official 80:2dab120a94c2 95 #define __TARGET_ARCH_6S_M 0
mbed_official 80:2dab120a94c2 96 #endif
mbed_official 80:2dab120a94c2 97
mbed_official 80:2dab120a94c2 98 #if defined __ARMVFP__
mbed_official 80:2dab120a94c2 99 #define __TARGET_FPU_VFP 1
mbed_official 80:2dab120a94c2 100 #else
mbed_official 80:2dab120a94c2 101 #define __TARGET_FPU_VFP 0
mbed_official 80:2dab120a94c2 102 #endif
mbed_official 80:2dab120a94c2 103
mbed_official 80:2dab120a94c2 104 #define __inline inline
mbed_official 80:2dab120a94c2 105
mbed_official 80:2dab120a94c2 106 #endif
mbed_official 80:2dab120a94c2 107
mbed_official 80:2dab120a94c2 108
mbed_official 80:2dab120a94c2 109 /* NVIC registers */
mbed_official 80:2dab120a94c2 110
mbed_official 80:2dab120a94c2 111 #define OS_PEND_IRQ() NVIC_PendIRQ(SYS_TICK_IRQn)
mbed_official 80:2dab120a94c2 112 #define OS_PENDING NVIC_PendingIRQ(SYS_TICK_IRQn)
mbed_official 80:2dab120a94c2 113 #define OS_UNPEND(fl) NVIC_UnpendIRQ(SYS_TICK_IRQn)
mbed_official 80:2dab120a94c2 114 #define OS_PEND(fl,p) NVIC_PendIRQ(SYS_TICK_IRQn)
mbed_official 80:2dab120a94c2 115 #define OS_LOCK() NVIC_DisableIRQ(SYS_TICK_IRQn)
mbed_official 80:2dab120a94c2 116 #define OS_UNLOCK() NVIC_EnableIRQ(SYS_TICK_IRQn)
mbed_official 80:2dab120a94c2 117
mbed_official 80:2dab120a94c2 118 #define OS_X_PENDING NVIC_PendingIRQ(SYS_TICK_IRQn)
mbed_official 80:2dab120a94c2 119 #define OS_X_UNPEND(fl) NVIC_UnpendIRQ(SYS_TICK_IRQn)
mbed_official 80:2dab120a94c2 120 #define OS_X_PEND(fl,p) NVIC_PendIRQ(SYS_TICK_IRQn)
mbed_official 80:2dab120a94c2 121
mbed_official 80:2dab120a94c2 122 #define OS_X_INIT(n) NVIC_EnableIRQ(n)
mbed_official 80:2dab120a94c2 123 #define OS_X_LOCK(n) NVIC_DisableIRQ(n)
mbed_official 80:2dab120a94c2 124 #define OS_X_UNLOCK(n) NVIC_EnableIRQ(n)
mbed_official 80:2dab120a94c2 125
mbed_official 80:2dab120a94c2 126 /* Variables */
mbed_official 80:2dab120a94c2 127 extern BIT dbg_msg;
mbed_official 80:2dab120a94c2 128
mbed_official 80:2dab120a94c2 129 /* Functions */
mbed_official 80:2dab120a94c2 130 #ifdef __USE_EXCLUSIVE_ACCESS
mbed_official 80:2dab120a94c2 131 #define rt_inc(p) while(__strex((__ldrex(p)+1),p))
mbed_official 80:2dab120a94c2 132 #define rt_dec(p) while(__strex((__ldrex(p)-1),p))
mbed_official 80:2dab120a94c2 133 #else
mbed_official 80:2dab120a94c2 134 #define rt_inc(p) __disable_irq();(*p)++;__enable_irq();
mbed_official 80:2dab120a94c2 135 #define rt_dec(p) __disable_irq();(*p)--;__enable_irq();
mbed_official 80:2dab120a94c2 136 #endif
mbed_official 80:2dab120a94c2 137
mbed_official 80:2dab120a94c2 138 __inline static U32 rt_inc_qi (U32 size, U8 *count, U8 *first) {
mbed_official 80:2dab120a94c2 139 U32 cnt,c2;
mbed_official 80:2dab120a94c2 140 #ifdef __USE_EXCLUSIVE_ACCESS
mbed_official 80:2dab120a94c2 141 do {
mbed_official 80:2dab120a94c2 142 if ((cnt = __ldrex(count)) == size) {
mbed_official 80:2dab120a94c2 143 __clrex();
mbed_official 80:2dab120a94c2 144 return (cnt); }
mbed_official 80:2dab120a94c2 145 } while (__strex(cnt+1, count));
mbed_official 80:2dab120a94c2 146 do {
mbed_official 80:2dab120a94c2 147 c2 = (cnt = __ldrex(first)) + 1;
mbed_official 80:2dab120a94c2 148 if (c2 == size) c2 = 0;
mbed_official 80:2dab120a94c2 149 } while (__strex(c2, first));
mbed_official 80:2dab120a94c2 150 #else
mbed_official 80:2dab120a94c2 151 __disable_irq();
mbed_official 80:2dab120a94c2 152 if ((cnt = *count) < size) {
mbed_official 80:2dab120a94c2 153 *count = cnt+1;
mbed_official 80:2dab120a94c2 154 c2 = (cnt = *first) + 1;
mbed_official 80:2dab120a94c2 155 if (c2 == size) c2 = 0;
mbed_official 80:2dab120a94c2 156 *first = c2;
mbed_official 80:2dab120a94c2 157 }
mbed_official 80:2dab120a94c2 158 __enable_irq ();
mbed_official 80:2dab120a94c2 159 #endif
mbed_official 80:2dab120a94c2 160 return (cnt);
mbed_official 80:2dab120a94c2 161 }
mbed_official 80:2dab120a94c2 162
mbed_official 80:2dab120a94c2 163 __inline static void rt_systick_init (void) {
mbed_official 80:2dab120a94c2 164 #if SYS_TICK_IRQn == TIMER0_IRQn
mbed_official 80:2dab120a94c2 165 #define SYS_TICK_TIMER LPC_TIM0
mbed_official 80:2dab120a94c2 166 LPC_SC->PCONP |= (1 << PCTIM0);
mbed_official 80:2dab120a94c2 167 LPC_SC->PCLKSEL0 = (LPC_SC->PCLKSEL0 & (~(1<<3))) | (1<<2); //PCLK == CPUCLK
mbed_official 80:2dab120a94c2 168 #elif SYS_TICK_IRQn == TIMER1_IRQn
mbed_official 80:2dab120a94c2 169 #define SYS_TICK_TIMER LPC_TIM1
mbed_official 80:2dab120a94c2 170 LPC_SC->PCONP |= (1 << PCTIM1);
mbed_official 80:2dab120a94c2 171 LPC_SC->PCLKSEL0 = (LPC_SC->PCLKSEL0 & (~(1<<5))) | (1<<4); //PCLK == CPUCLK
mbed_official 80:2dab120a94c2 172 #elif SYS_TICK_IRQn == TIMER2_IRQn
mbed_official 80:2dab120a94c2 173 #define SYS_TICK_TIMER LPC_TIM2
mbed_official 80:2dab120a94c2 174 LPC_SC->PCONP |= (1 << PCTIM2);
mbed_official 80:2dab120a94c2 175 LPC_SC->PCLKSEL1 = (LPC_SC->PCLKSEL1 & (~(1<<13))) | (1<<12); //PCLK == CPUCLK
mbed_official 80:2dab120a94c2 176 #else
mbed_official 80:2dab120a94c2 177 #define SYS_TICK_TIMER LPC_TIM3
mbed_official 80:2dab120a94c2 178 LPC_SC->PCONP |= (1 << PCTIM3);
mbed_official 80:2dab120a94c2 179 LPC_SC->PCLKSEL1 = (LPC_SC->PCLKSEL1 & (~(1<<15))) | (1<<14); //PCLK == CPUCLK
mbed_official 80:2dab120a94c2 180 #endif
mbed_official 80:2dab120a94c2 181
mbed_official 80:2dab120a94c2 182 // setup Timer to count forever
mbed_official 80:2dab120a94c2 183 //interrupt_reg
mbed_official 80:2dab120a94c2 184 SYS_TICK_TIMER->TCR = 2; // reset & disable timer 0
mbed_official 80:2dab120a94c2 185 SYS_TICK_TIMER->TC = os_trv;
mbed_official 80:2dab120a94c2 186 SYS_TICK_TIMER->PR = 0; // set the prescale divider
mbed_official 80:2dab120a94c2 187 //Reset of TC and Interrupt when MR3 MR2 matches TC
mbed_official 80:2dab120a94c2 188 SYS_TICK_TIMER->MCR = (1 << 9) |(1 << 10); //TMCR_MR3_R_Msk | TMCR_MR3_I_Msk
mbed_official 80:2dab120a94c2 189 SYS_TICK_TIMER->MR3 = os_trv; // match registers
mbed_official 80:2dab120a94c2 190 SYS_TICK_TIMER->CCR = 0; // disable compare registers
mbed_official 80:2dab120a94c2 191 SYS_TICK_TIMER->EMR = 0; // disable external match register
mbed_official 80:2dab120a94c2 192 // initialize the interrupt vector
mbed_official 80:2dab120a94c2 193 NVIC_SetVector(SYS_TICK_IRQn, (uint32_t)&SysTick_Handler);
mbed_official 80:2dab120a94c2 194 SYS_TICK_TIMER->TCR = 1; // enable timer 0
mbed_official 80:2dab120a94c2 195 }
mbed_official 80:2dab120a94c2 196
mbed_official 80:2dab120a94c2 197 __inline static void rt_svc_init (void) {
mbed_official 80:2dab120a94c2 198 // TODO: add svcInit
mbed_official 80:2dab120a94c2 199
mbed_official 80:2dab120a94c2 200 }
mbed_official 80:2dab120a94c2 201
mbed_official 80:2dab120a94c2 202 #ifdef DBG_MSG
mbed_official 80:2dab120a94c2 203 #define DBG_INIT() dbg_init()
mbed_official 80:2dab120a94c2 204 #define DBG_TASK_NOTIFY(p_tcb,create) if (dbg_msg) dbg_task_notify(p_tcb,create)
mbed_official 80:2dab120a94c2 205 #define DBG_TASK_SWITCH(task_id) if (dbg_msg && (os_tsk.new_tsk != os_tsk.run)) \
mbed_official 80:2dab120a94c2 206 dbg_task_switch(task_id)
mbed_official 80:2dab120a94c2 207 #else
mbed_official 80:2dab120a94c2 208 #define DBG_INIT()
mbed_official 80:2dab120a94c2 209 #define DBG_TASK_NOTIFY(p_tcb,create)
mbed_official 80:2dab120a94c2 210 #define DBG_TASK_SWITCH(task_id)
mbed_official 80:2dab120a94c2 211 #endif
mbed_official 80:2dab120a94c2 212
mbed_official 80:2dab120a94c2 213 /*----------------------------------------------------------------------------
mbed_official 80:2dab120a94c2 214 * end of file
mbed_official 80:2dab120a94c2 215 *---------------------------------------------------------------------------*/
mbed_official 80:2dab120a94c2 216