Ethan Harstad
A library for the Invensense MPU9150
MPU9150.h@0:d6616b97605d, 2014-06-03 (annotated)
- Committer:
- ethanharstad
- Date:
- Tue Jun 03 00:04:09 2014 +0000
- Revision:
- 0:d6616b97605d
- Child:
- 1:1b0ada1695a7
Accel/Gyro register map defines
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| ethanharstad | 0:d6616b97605d | 1 | #ifndef MPU9150_H_ |
| ethanharstad | 0:d6616b97605d | 2 | #define MPU9150_H_ |
| ethanharstad | 0:d6616b97605d | 3 | |
| ethanharstad | 0:d6616b97605d | 4 | #define MPU9150_RA_SELF_TEST_X 0x0D |
| ethanharstad | 0:d6616b97605d | 5 | #define MPU9150_RA_SELF_TEST_Y 0x0E |
| ethanharstad | 0:d6616b97605d | 6 | #define MPU9150_RA_SELF_TEST_Z 0x0F |
| ethanharstad | 0:d6616b97605d | 7 | #define MPU9150_RA_SELF_TEST_A 0x10 |
| ethanharstad | 0:d6616b97605d | 8 | #define MPU9150_RA_SMPLRT_DIV 0x19 |
| ethanharstad | 0:d6616b97605d | 9 | #define MPU9150_RA_CONFIG 0x1A |
| ethanharstad | 0:d6616b97605d | 10 | #define MPU9150_RA_GYRO_CONFIG 0x1B |
| ethanharstad | 0:d6616b97605d | 11 | #define MPU9150_RA_ACCEL_CONFIG 0x1C |
| ethanharstad | 0:d6616b97605d | 12 | #define MPU9150_RA_FIFO_EN 0x23 |
| ethanharstad | 0:d6616b97605d | 13 | #define MPU9150_RA_I2C_MST_CTRL 0x24 |
| ethanharstad | 0:d6616b97605d | 14 | #define MPU9150_RA_I2C_SLV0_ADDR 0x25 |
| ethanharstad | 0:d6616b97605d | 15 | #define MPU9150_RA_I2C_SLV0_REG 0x26 |
| ethanharstad | 0:d6616b97605d | 16 | #define MPU9150_RA_I2C_SLV0_CTRL 0x27 |
| ethanharstad | 0:d6616b97605d | 17 | #define MPU9150_RA_I2C_SLV1_ADDR 0x28 |
| ethanharstad | 0:d6616b97605d | 18 | #define MPU9150_RA_I2C_SLV1_REG 0x29 |
| ethanharstad | 0:d6616b97605d | 19 | #define MPU9150_RA_I2C_SLV1_CTRL 0x2A |
| ethanharstad | 0:d6616b97605d | 20 | #define MPU9150_RA_I2C_SLV2_ADDR 0x2B |
| ethanharstad | 0:d6616b97605d | 21 | #define MPU9150_RA_I2C_SLV2_REG 0x2C |
| ethanharstad | 0:d6616b97605d | 22 | #define MPU9150_RA_I2C_SLV2_CTRL 0x2D |
| ethanharstad | 0:d6616b97605d | 23 | #define MPU9150_RA_I2C_SLV3_ADDR 0x2E |
| ethanharstad | 0:d6616b97605d | 24 | #define MPU9150_RA_I2C_SLV3_REG 0x2F |
| ethanharstad | 0:d6616b97605d | 25 | #define MPU9150_RA_I2C_SLV3_CTRL 0x30 |
| ethanharstad | 0:d6616b97605d | 26 | #define MPU9150_RA_I2C_SLV4_ADDR 0x31 |
| ethanharstad | 0:d6616b97605d | 27 | #define MPU9150_RA_I2C_SLV4_REG 0x32 |
| ethanharstad | 0:d6616b97605d | 28 | #define MPU9150_RA_I2C_SLV4_DO 0x33 |
| ethanharstad | 0:d6616b97605d | 29 | #define MPU9150_RA_I2C_SLV4_CTRL 0x34 |
| ethanharstad | 0:d6616b97605d | 30 | #define MPU9150_RA_I2C_SLV4_DI 0x35 |
| ethanharstad | 0:d6616b97605d | 31 | #define MPU9150_RA_I2C_MST_STATUS 0x36 |
| ethanharstad | 0:d6616b97605d | 32 | #define MPU9150_RA_INT_PIN_CFG 0x37 |
| ethanharstad | 0:d6616b97605d | 33 | #define MPU9150_RA_INT_ENABLE 0x38 |
| ethanharstad | 0:d6616b97605d | 34 | #define MPU9150_RA_INT_STATUS 0x3A |
| ethanharstad | 0:d6616b97605d | 35 | #define MPU9150_RA_ACCEL_XOUT_H 0x3B |
| ethanharstad | 0:d6616b97605d | 36 | #define MPU9150_RA_ACCEL_XOUT_L 0x3C |
| ethanharstad | 0:d6616b97605d | 37 | #define MPU9150_RA_ACCEL_YOUT_H 0x3D |
| ethanharstad | 0:d6616b97605d | 38 | #define MPU9150_RA_ACCEL_YOUT_L 0x3E |
| ethanharstad | 0:d6616b97605d | 39 | #define MPU9150_RA_ACCEL_ZOUT_H 0x3F |
| ethanharstad | 0:d6616b97605d | 40 | #define MPU9150_RA_ACCEL_ZOUT_L 0x40 |
| ethanharstad | 0:d6616b97605d | 41 | #define MPU9150_RA_TEMP_OUT_H 0x41 |
| ethanharstad | 0:d6616b97605d | 42 | #define MPU9150_RA_TEMP_OUT_L 0x42 |
| ethanharstad | 0:d6616b97605d | 43 | #define MPU9150_RA_GYRO_XOUT_H 0x43 |
| ethanharstad | 0:d6616b97605d | 44 | #define MPU9150_RA_GYRO_XOUT_L 0x44 |
| ethanharstad | 0:d6616b97605d | 45 | #define MPU9150_RA_GYRO_YOUT_H 0x45 |
| ethanharstad | 0:d6616b97605d | 46 | #define MPU9150_RA_GYRO_YOUT_L 0x46 |
| ethanharstad | 0:d6616b97605d | 47 | #define MPU9150_RA_GYRO_ZOUT_H 0x47 |
| ethanharstad | 0:d6616b97605d | 48 | #define MPU9150_RA_GYRO_ZOUT_L 0x48 |
| ethanharstad | 0:d6616b97605d | 49 | #define MPU9150_RA_EXT_SENS_DATA_00 0x49 |
| ethanharstad | 0:d6616b97605d | 50 | #define MPU9150_RA_EXT_SENS_DATA_01 0x4A |
| ethanharstad | 0:d6616b97605d | 51 | #define MPU9150_RA_EXT_SENS_DATA_02 0x4B |
| ethanharstad | 0:d6616b97605d | 52 | #define MPU9150_RA_EXT_SENS_DATA_03 0x4C |
| ethanharstad | 0:d6616b97605d | 53 | #define MPU9150_RA_EXT_SENS_DATA_04 0x4D |
| ethanharstad | 0:d6616b97605d | 54 | #define MPU9150_RA_EXT_SENS_DATA_05 0x4E |
| ethanharstad | 0:d6616b97605d | 55 | #define MPU9150_RA_EXT_SENS_DATA_06 0x4F |
| ethanharstad | 0:d6616b97605d | 56 | #define MPU9150_RA_EXT_SENS_DATA_07 0x50 |
| ethanharstad | 0:d6616b97605d | 57 | #define MPU9150_RA_EXT_SENS_DATA_08 0x51 |
| ethanharstad | 0:d6616b97605d | 58 | #define MPU9150_RA_EXT_SENS_DATA_09 0x52 |
| ethanharstad | 0:d6616b97605d | 59 | #define MPU9150_RA_EXT_SENS_DATA_10 0x53 |
| ethanharstad | 0:d6616b97605d | 60 | #define MPU9150_RA_EXT_SENS_DATA_11 0x54 |
| ethanharstad | 0:d6616b97605d | 61 | #define MPU9150_RA_EXT_SENS_DATA_12 0x55 |
| ethanharstad | 0:d6616b97605d | 62 | #define MPU9150_RA_EXT_SENS_DATA_13 0x56 |
| ethanharstad | 0:d6616b97605d | 63 | #define MPU9150_RA_EXT_SENS_DATA_14 0x57 |
| ethanharstad | 0:d6616b97605d | 64 | #define MPU9150_RA_EXT_SENS_DATA_15 0x58 |
| ethanharstad | 0:d6616b97605d | 65 | #define MPU9150_RA_EXT_SENS_DATA_16 0x59 |
| ethanharstad | 0:d6616b97605d | 66 | #define MPU9150_RA_EXT_SENS_DATA_17 0x5A |
| ethanharstad | 0:d6616b97605d | 67 | #define MPU9150_RA_EXT_SENS_DATA_18 0x5B |
| ethanharstad | 0:d6616b97605d | 68 | #define MPU9150_RA_EXT_SENS_DATA_19 0x5C |
| ethanharstad | 0:d6616b97605d | 69 | #define MPU9150_RA_EXT_SENS_DATA_20 0x5D |
| ethanharstad | 0:d6616b97605d | 70 | #define MPU9150_RA_EXT_SENS_DATA_21 0x5E |
| ethanharstad | 0:d6616b97605d | 71 | #define MPU9150_RA_EXT_SENS_DATA_22 0x5F |
| ethanharstad | 0:d6616b97605d | 72 | #define MPU9150_RA_EXT_SENS_DATA_23 0x60 |
| ethanharstad | 0:d6616b97605d | 73 | #define MPU9150_RA_I2C_SLV1_DO 0x63 |
| ethanharstad | 0:d6616b97605d | 74 | #define MPU9150_RA_I2C_SLV1_DO 0x64 |
| ethanharstad | 0:d6616b97605d | 75 | #define MPU9150_RA_I2C_SLV2_DO 0x65 |
| ethanharstad | 0:d6616b97605d | 76 | #define MPU9150_RA_I2C_SLV3_DO 0x66 |
| ethanharstad | 0:d6616b97605d | 77 | #define MPU9150_RA_I2C_MST_DELAY_CTRL 0x67 |
| ethanharstad | 0:d6616b97605d | 78 | #define MPU9150_RA_SIGNAL_PATH_RESET 0x68 |
| ethanharstad | 0:d6616b97605d | 79 | #define MPU9150_RA_USER_CTRL 0x6A |
| ethanharstad | 0:d6616b97605d | 80 | #define MPU9150_RA_PWR_MGMT_1 0x6B |
| ethanharstad | 0:d6616b97605d | 81 | #define MPU9150_RA_PWR_MGMT_2 0x6C |
| ethanharstad | 0:d6616b97605d | 82 | #define MPU9150_RA_FIFO_COUNTH 0x72 |
| ethanharstad | 0:d6616b97605d | 83 | #define MPU9150_RA_FIFO_COUNTL 0x73 |
| ethanharstad | 0:d6616b97605d | 84 | #define MPU9150_RA_FIFO_R_W 0x74 |
| ethanharstad | 0:d6616b97605d | 85 | #define MPU9150_RA_WHO_AM_I 0x75 |
| ethanharstad | 0:d6616b97605d | 86 | |
| ethanharstad | 0:d6616b97605d | 87 | class MPU9150 { |
| ethanharstad | 0:d6616b97605d | 88 | public: |
| ethanharstad | 0:d6616b97605d | 89 | MPU9150(); |
| ethanharstad | 0:d6616b97605d | 90 | explicit MPU9150(uint8_t address); |
| ethanharstad | 0:d6616b97605d | 91 | MPU9150(PinName sda, PinName scl, uint8_t address); |
| ethanharstad | 0:d6616b97605d | 92 | |
| ethanharstad | 0:d6616b97605d | 93 | private: |
| ethanharstad | 0:d6616b97605d | 94 | I2C i2c_; |
| ethanharstad | 0:d6616b97605d | 95 | uint8_t address_; |
| ethanharstad | 0:d6616b97605d | 96 | } |
| ethanharstad | 0:d6616b97605d | 97 | |
| ethanharstad | 0:d6616b97605d | 98 | #endif |