A library for the Invensense MPU9150
MPU9150.h@2:581fad93a809, 2014-06-09 (annotated)
- Committer:
- ethanharstad
- Date:
- Mon Jun 09 21:17:40 2014 +0000
- Revision:
- 2:581fad93a809
- Parent:
- 1:1b0ada1695a7
Untested implementation
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
ethanharstad | 0:d6616b97605d | 1 | #ifndef MPU9150_H_ |
ethanharstad | 0:d6616b97605d | 2 | #define MPU9150_H_ |
ethanharstad | 0:d6616b97605d | 3 | |
ethanharstad | 1:1b0ada1695a7 | 4 | #include "mbed.h" |
ethanharstad | 2:581fad93a809 | 5 | #include "I2CHelper.h" |
ethanharstad | 1:1b0ada1695a7 | 6 | |
ethanharstad | 1:1b0ada1695a7 | 7 | #define MPU9150_ADDRESS_AD0_LOW 0x68 |
ethanharstad | 1:1b0ada1695a7 | 8 | #define MPU9150_ADDRESS_AD0_HIGH 0x69 |
ethanharstad | 1:1b0ada1695a7 | 9 | #define MPU9150_ADDRESS_DEFAULT MPU9150_ADDRESS_AD0_LOW |
ethanharstad | 1:1b0ada1695a7 | 10 | |
ethanharstad | 0:d6616b97605d | 11 | #define MPU9150_RA_SELF_TEST_X 0x0D |
ethanharstad | 0:d6616b97605d | 12 | #define MPU9150_RA_SELF_TEST_Y 0x0E |
ethanharstad | 0:d6616b97605d | 13 | #define MPU9150_RA_SELF_TEST_Z 0x0F |
ethanharstad | 0:d6616b97605d | 14 | #define MPU9150_RA_SELF_TEST_A 0x10 |
ethanharstad | 2:581fad93a809 | 15 | #define MPU9150_RA_SMPRT_DIV 0x19 |
ethanharstad | 0:d6616b97605d | 16 | #define MPU9150_RA_CONFIG 0x1A |
ethanharstad | 0:d6616b97605d | 17 | #define MPU9150_RA_GYRO_CONFIG 0x1B |
ethanharstad | 0:d6616b97605d | 18 | #define MPU9150_RA_ACCEL_CONFIG 0x1C |
ethanharstad | 0:d6616b97605d | 19 | #define MPU9150_RA_FIFO_EN 0x23 |
ethanharstad | 0:d6616b97605d | 20 | #define MPU9150_RA_I2C_MST_CTRL 0x24 |
ethanharstad | 0:d6616b97605d | 21 | #define MPU9150_RA_I2C_SLV0_ADDR 0x25 |
ethanharstad | 0:d6616b97605d | 22 | #define MPU9150_RA_I2C_SLV0_REG 0x26 |
ethanharstad | 0:d6616b97605d | 23 | #define MPU9150_RA_I2C_SLV0_CTRL 0x27 |
ethanharstad | 0:d6616b97605d | 24 | #define MPU9150_RA_I2C_SLV1_ADDR 0x28 |
ethanharstad | 0:d6616b97605d | 25 | #define MPU9150_RA_I2C_SLV1_REG 0x29 |
ethanharstad | 0:d6616b97605d | 26 | #define MPU9150_RA_I2C_SLV1_CTRL 0x2A |
ethanharstad | 0:d6616b97605d | 27 | #define MPU9150_RA_I2C_SLV2_ADDR 0x2B |
ethanharstad | 0:d6616b97605d | 28 | #define MPU9150_RA_I2C_SLV2_REG 0x2C |
ethanharstad | 0:d6616b97605d | 29 | #define MPU9150_RA_I2C_SLV2_CTRL 0x2D |
ethanharstad | 0:d6616b97605d | 30 | #define MPU9150_RA_I2C_SLV3_ADDR 0x2E |
ethanharstad | 0:d6616b97605d | 31 | #define MPU9150_RA_I2C_SLV3_REG 0x2F |
ethanharstad | 0:d6616b97605d | 32 | #define MPU9150_RA_I2C_SLV3_CTRL 0x30 |
ethanharstad | 0:d6616b97605d | 33 | #define MPU9150_RA_I2C_SLV4_ADDR 0x31 |
ethanharstad | 0:d6616b97605d | 34 | #define MPU9150_RA_I2C_SLV4_REG 0x32 |
ethanharstad | 0:d6616b97605d | 35 | #define MPU9150_RA_I2C_SLV4_DO 0x33 |
ethanharstad | 0:d6616b97605d | 36 | #define MPU9150_RA_I2C_SLV4_CTRL 0x34 |
ethanharstad | 0:d6616b97605d | 37 | #define MPU9150_RA_I2C_SLV4_DI 0x35 |
ethanharstad | 0:d6616b97605d | 38 | #define MPU9150_RA_I2C_MST_STATUS 0x36 |
ethanharstad | 0:d6616b97605d | 39 | #define MPU9150_RA_INT_PIN_CFG 0x37 |
ethanharstad | 0:d6616b97605d | 40 | #define MPU9150_RA_INT_ENABLE 0x38 |
ethanharstad | 0:d6616b97605d | 41 | #define MPU9150_RA_INT_STATUS 0x3A |
ethanharstad | 0:d6616b97605d | 42 | #define MPU9150_RA_ACCEL_XOUT_H 0x3B |
ethanharstad | 0:d6616b97605d | 43 | #define MPU9150_RA_ACCEL_XOUT_L 0x3C |
ethanharstad | 0:d6616b97605d | 44 | #define MPU9150_RA_ACCEL_YOUT_H 0x3D |
ethanharstad | 0:d6616b97605d | 45 | #define MPU9150_RA_ACCEL_YOUT_L 0x3E |
ethanharstad | 0:d6616b97605d | 46 | #define MPU9150_RA_ACCEL_ZOUT_H 0x3F |
ethanharstad | 0:d6616b97605d | 47 | #define MPU9150_RA_ACCEL_ZOUT_L 0x40 |
ethanharstad | 0:d6616b97605d | 48 | #define MPU9150_RA_TEMP_OUT_H 0x41 |
ethanharstad | 0:d6616b97605d | 49 | #define MPU9150_RA_TEMP_OUT_L 0x42 |
ethanharstad | 0:d6616b97605d | 50 | #define MPU9150_RA_GYRO_XOUT_H 0x43 |
ethanharstad | 0:d6616b97605d | 51 | #define MPU9150_RA_GYRO_XOUT_L 0x44 |
ethanharstad | 0:d6616b97605d | 52 | #define MPU9150_RA_GYRO_YOUT_H 0x45 |
ethanharstad | 0:d6616b97605d | 53 | #define MPU9150_RA_GYRO_YOUT_L 0x46 |
ethanharstad | 0:d6616b97605d | 54 | #define MPU9150_RA_GYRO_ZOUT_H 0x47 |
ethanharstad | 0:d6616b97605d | 55 | #define MPU9150_RA_GYRO_ZOUT_L 0x48 |
ethanharstad | 0:d6616b97605d | 56 | #define MPU9150_RA_EXT_SENS_DATA_00 0x49 |
ethanharstad | 0:d6616b97605d | 57 | #define MPU9150_RA_EXT_SENS_DATA_01 0x4A |
ethanharstad | 0:d6616b97605d | 58 | #define MPU9150_RA_EXT_SENS_DATA_02 0x4B |
ethanharstad | 0:d6616b97605d | 59 | #define MPU9150_RA_EXT_SENS_DATA_03 0x4C |
ethanharstad | 0:d6616b97605d | 60 | #define MPU9150_RA_EXT_SENS_DATA_04 0x4D |
ethanharstad | 0:d6616b97605d | 61 | #define MPU9150_RA_EXT_SENS_DATA_05 0x4E |
ethanharstad | 0:d6616b97605d | 62 | #define MPU9150_RA_EXT_SENS_DATA_06 0x4F |
ethanharstad | 0:d6616b97605d | 63 | #define MPU9150_RA_EXT_SENS_DATA_07 0x50 |
ethanharstad | 0:d6616b97605d | 64 | #define MPU9150_RA_EXT_SENS_DATA_08 0x51 |
ethanharstad | 0:d6616b97605d | 65 | #define MPU9150_RA_EXT_SENS_DATA_09 0x52 |
ethanharstad | 0:d6616b97605d | 66 | #define MPU9150_RA_EXT_SENS_DATA_10 0x53 |
ethanharstad | 0:d6616b97605d | 67 | #define MPU9150_RA_EXT_SENS_DATA_11 0x54 |
ethanharstad | 0:d6616b97605d | 68 | #define MPU9150_RA_EXT_SENS_DATA_12 0x55 |
ethanharstad | 0:d6616b97605d | 69 | #define MPU9150_RA_EXT_SENS_DATA_13 0x56 |
ethanharstad | 0:d6616b97605d | 70 | #define MPU9150_RA_EXT_SENS_DATA_14 0x57 |
ethanharstad | 0:d6616b97605d | 71 | #define MPU9150_RA_EXT_SENS_DATA_15 0x58 |
ethanharstad | 0:d6616b97605d | 72 | #define MPU9150_RA_EXT_SENS_DATA_16 0x59 |
ethanharstad | 0:d6616b97605d | 73 | #define MPU9150_RA_EXT_SENS_DATA_17 0x5A |
ethanharstad | 0:d6616b97605d | 74 | #define MPU9150_RA_EXT_SENS_DATA_18 0x5B |
ethanharstad | 0:d6616b97605d | 75 | #define MPU9150_RA_EXT_SENS_DATA_19 0x5C |
ethanharstad | 0:d6616b97605d | 76 | #define MPU9150_RA_EXT_SENS_DATA_20 0x5D |
ethanharstad | 0:d6616b97605d | 77 | #define MPU9150_RA_EXT_SENS_DATA_21 0x5E |
ethanharstad | 0:d6616b97605d | 78 | #define MPU9150_RA_EXT_SENS_DATA_22 0x5F |
ethanharstad | 0:d6616b97605d | 79 | #define MPU9150_RA_EXT_SENS_DATA_23 0x60 |
ethanharstad | 1:1b0ada1695a7 | 80 | #define MPU9150_RA_I2C_SLV0_DO 0x63 |
ethanharstad | 0:d6616b97605d | 81 | #define MPU9150_RA_I2C_SLV1_DO 0x64 |
ethanharstad | 0:d6616b97605d | 82 | #define MPU9150_RA_I2C_SLV2_DO 0x65 |
ethanharstad | 0:d6616b97605d | 83 | #define MPU9150_RA_I2C_SLV3_DO 0x66 |
ethanharstad | 0:d6616b97605d | 84 | #define MPU9150_RA_I2C_MST_DELAY_CTRL 0x67 |
ethanharstad | 0:d6616b97605d | 85 | #define MPU9150_RA_SIGNAL_PATH_RESET 0x68 |
ethanharstad | 0:d6616b97605d | 86 | #define MPU9150_RA_USER_CTRL 0x6A |
ethanharstad | 0:d6616b97605d | 87 | #define MPU9150_RA_PWR_MGMT_1 0x6B |
ethanharstad | 0:d6616b97605d | 88 | #define MPU9150_RA_PWR_MGMT_2 0x6C |
ethanharstad | 0:d6616b97605d | 89 | #define MPU9150_RA_FIFO_COUNTH 0x72 |
ethanharstad | 0:d6616b97605d | 90 | #define MPU9150_RA_FIFO_COUNTL 0x73 |
ethanharstad | 0:d6616b97605d | 91 | #define MPU9150_RA_FIFO_R_W 0x74 |
ethanharstad | 0:d6616b97605d | 92 | #define MPU9150_RA_WHO_AM_I 0x75 |
ethanharstad | 0:d6616b97605d | 93 | |
ethanharstad | 2:581fad93a809 | 94 | // CONFIG Register |
ethanharstad | 1:1b0ada1695a7 | 95 | #define MPU9150_EXT_SYNC_DISABLED 0x00 |
ethanharstad | 1:1b0ada1695a7 | 96 | #define MPU9150_EXT_SYNC_TEMP_OUT_L 0x01 |
ethanharstad | 1:1b0ada1695a7 | 97 | #define MPU9150_EXT_SYNC_GYRO_XOUT_L 0x02 |
ethanharstad | 1:1b0ada1695a7 | 98 | #define MPU9150_EXT_SYNC_GYRO_YOUT_L 0x03 |
ethanharstad | 1:1b0ada1695a7 | 99 | #define MPU9150_EXT_SYNC_GYRO_ZOUT_L 0x04 |
ethanharstad | 1:1b0ada1695a7 | 100 | #define MPU9150_EXT_SYNC_ACCEL_XOUT_L 0x05 |
ethanharstad | 1:1b0ada1695a7 | 101 | #define MPU9150_EXT_SYNC_ACCEL_YOUT_L 0x06 |
ethanharstad | 1:1b0ada1695a7 | 102 | #define MPU9150_EXT_SYNC_ACCEL_ZOUT_L 0x07 |
ethanharstad | 1:1b0ada1695a7 | 103 | #define MPU9150_DLPF_BW_256 0x00 |
ethanharstad | 1:1b0ada1695a7 | 104 | #define MPU9150_DLPF_BW_188 0x01 |
ethanharstad | 1:1b0ada1695a7 | 105 | #define MPU9150_DLPF_BW_98 0x02 |
ethanharstad | 1:1b0ada1695a7 | 106 | #define MPU9150_DLPF_BW_42 0x03 |
ethanharstad | 1:1b0ada1695a7 | 107 | #define MPU9150_DLPF_BW_20 0x04 |
ethanharstad | 1:1b0ada1695a7 | 108 | #define MPU9150_DLPF_BW_10 0x05 |
ethanharstad | 1:1b0ada1695a7 | 109 | #define MPU9150_DLPF_BW_5 0x06 |
ethanharstad | 1:1b0ada1695a7 | 110 | |
ethanharstad | 2:581fad93a809 | 111 | // GYRO_CONFIG Register |
ethanharstad | 1:1b0ada1695a7 | 112 | #define MPU9150_GYRO_FS_250 0x00 |
ethanharstad | 1:1b0ada1695a7 | 113 | #define MPU9150_GYRO_FS_500 0x01 |
ethanharstad | 1:1b0ada1695a7 | 114 | #define MPU9150_GYRO_FS_1000 0x02 |
ethanharstad | 1:1b0ada1695a7 | 115 | #define MPU9150_GYRO_FS_2000 0x03 |
ethanharstad | 1:1b0ada1695a7 | 116 | |
ethanharstad | 2:581fad93a809 | 117 | // ACCEL_CONFIG Register |
ethanharstad | 1:1b0ada1695a7 | 118 | #define MPU9150_ACCEL_FS_2 0x00 |
ethanharstad | 1:1b0ada1695a7 | 119 | #define MPU9150_ACCEL_FS_4 0x01 |
ethanharstad | 1:1b0ada1695a7 | 120 | #define MPU9150_ACCEL_FS_8 0x02 |
ethanharstad | 1:1b0ada1695a7 | 121 | #define MPU9150_ACCEL_FS_16 0x03 |
ethanharstad | 1:1b0ada1695a7 | 122 | |
ethanharstad | 2:581fad93a809 | 123 | // SIGNAL_PATH_RESET Register |
ethanharstad | 2:581fad93a809 | 124 | #define MPU9150_SIGNAL_PATH_GYRO_RESET 0x04 |
ethanharstad | 2:581fad93a809 | 125 | #define MPU9150_SIGNAL_PATH_ACCEL_RESET 0x02 |
ethanharstad | 2:581fad93a809 | 126 | #define MPU9150_SIGNAL_PATH_TEMP_RESET 0x01 |
ethanharstad | 2:581fad93a809 | 127 | |
ethanharstad | 2:581fad93a809 | 128 | // USER_CTRL Register |
ethanharstad | 2:581fad93a809 | 129 | #define MPU9150_USER_CTRL_FIFO_EN 0x40 |
ethanharstad | 2:581fad93a809 | 130 | #define MPU9150_USER_CTRL_I2C_MST_EN 0x20 |
ethanharstad | 2:581fad93a809 | 131 | #define MPU9150_USER_CTRL_FIFO_RESET 0x04 |
ethanharstad | 2:581fad93a809 | 132 | #define MPU9150_USER_CTRL_I2C_MST_RESET 0x02 |
ethanharstad | 2:581fad93a809 | 133 | #define MPU9150_USER_CTRL_SIG_RESET 0x01 |
ethanharstad | 2:581fad93a809 | 134 | |
ethanharstad | 2:581fad93a809 | 135 | // PWR_MGMT_1 Register |
ethanharstad | 2:581fad93a809 | 136 | #define MPU9150_PWR_MGMT_DEVICE_RESET 0x80 |
ethanharstad | 2:581fad93a809 | 137 | #define MPU9150_PWR_MGMT_SLEEP 0x40 |
ethanharstad | 2:581fad93a809 | 138 | #define MPU9150_PWR_MGMT_CYCLE 0x20 |
ethanharstad | 2:581fad93a809 | 139 | #define MPU9150_PWR_MGMT_TEMP_DISABLE 0x08 |
ethanharstad | 2:581fad93a809 | 140 | #define MPU9150_PWR_MGMT_CLOCK_INTERNAL 0x00 |
ethanharstad | 2:581fad93a809 | 141 | #define MPU9150_PWR_MGMT_CLOCK_GYRO_X 0x01 |
ethanharstad | 2:581fad93a809 | 142 | #define MPU9150_PWR_MGMT_CLOCK_GYRO_Y 0x02 |
ethanharstad | 2:581fad93a809 | 143 | #define MPU9150_PWR_MGMT_CLOCK_GYRO_Z 0x03 |
ethanharstad | 2:581fad93a809 | 144 | #define MPU9150_PWR_MGMT_CLOCK_EXT_32k 0x04 |
ethanharstad | 2:581fad93a809 | 145 | #define MPU9150_PWR_MGMT_CLOCK_EXT_19M 0x05 |
ethanharstad | 2:581fad93a809 | 146 | #define MPU9150_PWR_MGMT_CLOCK_DISABLE 0x07 |
ethanharstad | 2:581fad93a809 | 147 | |
ethanharstad | 2:581fad93a809 | 148 | // PWR_MGMT_2 Register |
ethanharstad | 2:581fad93a809 | 149 | #define MPU9150_PWR_MGMT_STBY_GYRO_Z 0x01 |
ethanharstad | 2:581fad93a809 | 150 | #define MPU9150_PWR_MGMT_STBY_GYRO_Y 0x02 |
ethanharstad | 2:581fad93a809 | 151 | #define MPU9150_PWR_MGMT_STBY_GYRO_X 0x04 |
ethanharstad | 2:581fad93a809 | 152 | #define MPU9150_PWR_MGMT_STBY_ACCEL_Z 0x08 |
ethanharstad | 2:581fad93a809 | 153 | #define MPU9150_PWR_MGMT_STBY_ACCEL_Y 0x10 |
ethanharstad | 2:581fad93a809 | 154 | #define MPU9150_PWR_MGMT_STBY_ACCEL_X 0x20 |
ethanharstad | 2:581fad93a809 | 155 | #define MPU9150_PWR_MGMT_CYCLE_1_25HZ 0x00 |
ethanharstad | 2:581fad93a809 | 156 | #define MPU9150_PWR_MGMT_CYCLE_5HZ 0x01 |
ethanharstad | 2:581fad93a809 | 157 | #define MPU9150_PWR_MGMT_CYCLE_20HZ 0x02 |
ethanharstad | 2:581fad93a809 | 158 | #define MPU9150_PWR_MGMT_CYCLE_40HZ 0x03 |
ethanharstad | 2:581fad93a809 | 159 | |
ethanharstad | 0:d6616b97605d | 160 | class MPU9150 { |
ethanharstad | 0:d6616b97605d | 161 | public: |
ethanharstad | 0:d6616b97605d | 162 | MPU9150(); |
ethanharstad | 1:1b0ada1695a7 | 163 | explicit MPU9150(const bool AD0); |
ethanharstad | 1:1b0ada1695a7 | 164 | MPU9150(const PinName sda, const PinName scl, const bool AD0); |
ethanharstad | 1:1b0ada1695a7 | 165 | |
ethanharstad | 1:1b0ada1695a7 | 166 | void initialize(); |
ethanharstad | 1:1b0ada1695a7 | 167 | bool test(); |
ethanharstad | 1:1b0ada1695a7 | 168 | |
ethanharstad | 1:1b0ada1695a7 | 169 | // SMPRT_DIV Register |
ethanharstad | 1:1b0ada1695a7 | 170 | uint8_t getSampleRateDivider(); |
ethanharstad | 1:1b0ada1695a7 | 171 | void setSampleRateDivider(const uint8_t divider); |
ethanharstad | 1:1b0ada1695a7 | 172 | |
ethanharstad | 1:1b0ada1695a7 | 173 | // CONFIG Register |
ethanharstad | 1:1b0ada1695a7 | 174 | uint8_t getExternalFrameSync(); |
ethanharstad | 1:1b0ada1695a7 | 175 | void setExternalFrameSync(const uint8_t sync); |
ethanharstad | 1:1b0ada1695a7 | 176 | uint8_t getDLPFBandwidth(); |
ethanharstad | 2:581fad93a809 | 177 | void setDLPFBandwidth(const uint8_t bandwidth); |
ethanharstad | 1:1b0ada1695a7 | 178 | |
ethanharstad | 1:1b0ada1695a7 | 179 | // GYRO_CONFIG Register |
ethanharstad | 1:1b0ada1695a7 | 180 | uint8_t getGyroFullScaleRange(); |
ethanharstad | 1:1b0ada1695a7 | 181 | void setGyroFullScaleRange(const uint8_t range); |
ethanharstad | 1:1b0ada1695a7 | 182 | |
ethanharstad | 1:1b0ada1695a7 | 183 | // ACCEL_CONFIG Register |
ethanharstad | 1:1b0ada1695a7 | 184 | uint8_t getAccelFullScaleRange(); |
ethanharstad | 1:1b0ada1695a7 | 185 | void setAccelFullScaleRange(const uint8_t range); |
ethanharstad | 1:1b0ada1695a7 | 186 | |
ethanharstad | 1:1b0ada1695a7 | 187 | // ACCEL_OUT_* Registers |
ethanharstad | 1:1b0ada1695a7 | 188 | int16_t getAccelX(); |
ethanharstad | 1:1b0ada1695a7 | 189 | int16_t getAccelY(); |
ethanharstad | 1:1b0ada1695a7 | 190 | int16_t getAccelZ(); |
ethanharstad | 1:1b0ada1695a7 | 191 | |
ethanharstad | 1:1b0ada1695a7 | 192 | // TEMP_OUT_* Registers |
ethanharstad | 1:1b0ada1695a7 | 193 | int16_t getTemp(); |
ethanharstad | 1:1b0ada1695a7 | 194 | |
ethanharstad | 1:1b0ada1695a7 | 195 | // GYRO_OUT_* Registers |
ethanharstad | 1:1b0ada1695a7 | 196 | int16_t getGyroX(); |
ethanharstad | 1:1b0ada1695a7 | 197 | int16_t getGyroY(); |
ethanharstad | 1:1b0ada1695a7 | 198 | int16_t getGyroZ(); |
ethanharstad | 1:1b0ada1695a7 | 199 | |
ethanharstad | 1:1b0ada1695a7 | 200 | // SIGNAL_PATH_RESET Register |
ethanharstad | 1:1b0ada1695a7 | 201 | void resetGyroPath(); |
ethanharstad | 1:1b0ada1695a7 | 202 | void resetAccelPath(); |
ethanharstad | 1:1b0ada1695a7 | 203 | void resetTempPath(); |
ethanharstad | 1:1b0ada1695a7 | 204 | |
ethanharstad | 1:1b0ada1695a7 | 205 | // USER_CTRL Register |
ethanharstad | 1:1b0ada1695a7 | 206 | bool getFifoEnabled(); |
ethanharstad | 1:1b0ada1695a7 | 207 | void setFifoEnabled(const bool fifo); |
ethanharstad | 1:1b0ada1695a7 | 208 | bool getI2CMasterEnabled(); |
ethanharstad | 1:1b0ada1695a7 | 209 | void setI2CMasterEnabled(const bool master); |
ethanharstad | 1:1b0ada1695a7 | 210 | void resetFifo(); |
ethanharstad | 1:1b0ada1695a7 | 211 | void resetI2CMaster(); |
ethanharstad | 1:1b0ada1695a7 | 212 | void resetSensors(); |
ethanharstad | 1:1b0ada1695a7 | 213 | |
ethanharstad | 1:1b0ada1695a7 | 214 | // PWR_MGMT_1 Register |
ethanharstad | 1:1b0ada1695a7 | 215 | void reset(); |
ethanharstad | 1:1b0ada1695a7 | 216 | bool getSleepEnabled(); |
ethanharstad | 1:1b0ada1695a7 | 217 | void setSleepEnabled(const bool sleep); |
ethanharstad | 1:1b0ada1695a7 | 218 | bool getCycleEnabled(); |
ethanharstad | 1:1b0ada1695a7 | 219 | void setCycleEnabled(const bool cycle); |
ethanharstad | 1:1b0ada1695a7 | 220 | bool getTempEnabled(); |
ethanharstad | 1:1b0ada1695a7 | 221 | void setTempEnabled(const bool temp); |
ethanharstad | 1:1b0ada1695a7 | 222 | uint8_t getClockSource(); |
ethanharstad | 1:1b0ada1695a7 | 223 | void setClockSource(const uint8_t source); |
ethanharstad | 1:1b0ada1695a7 | 224 | |
ethanharstad | 1:1b0ada1695a7 | 225 | // PWR_MGMT_2 Register |
ethanharstad | 1:1b0ada1695a7 | 226 | uint8_t getCycleFrequency(); |
ethanharstad | 1:1b0ada1695a7 | 227 | void setCycleFrequency(const uint8_t frequency); |
ethanharstad | 1:1b0ada1695a7 | 228 | bool getStandbyAccelXEnabled(); |
ethanharstad | 1:1b0ada1695a7 | 229 | void setStandbyAccelXEnabled(const bool enabled); |
ethanharstad | 1:1b0ada1695a7 | 230 | bool getStandbyAccelYEnabled(); |
ethanharstad | 1:1b0ada1695a7 | 231 | void setStandbyAccelYEnabled(const bool enabled); |
ethanharstad | 1:1b0ada1695a7 | 232 | bool getStandbyAccelZEnabled(); |
ethanharstad | 1:1b0ada1695a7 | 233 | void setStandbyAccelZEnabled(const bool enabled); |
ethanharstad | 1:1b0ada1695a7 | 234 | bool getStandbyGyroXEnabled(); |
ethanharstad | 1:1b0ada1695a7 | 235 | void setStandbyGyroXEnabled(const bool enabled); |
ethanharstad | 1:1b0ada1695a7 | 236 | bool getStandbyGyroYEnabled(); |
ethanharstad | 1:1b0ada1695a7 | 237 | void setStandbyGyroYEnabled(const bool enabled); |
ethanharstad | 1:1b0ada1695a7 | 238 | bool getStandbyGyroZEnabled(); |
ethanharstad | 1:1b0ada1695a7 | 239 | void setStandbyGyroZEnabled(const bool enabled); |
ethanharstad | 1:1b0ada1695a7 | 240 | |
ethanharstad | 1:1b0ada1695a7 | 241 | // WHO_AM_I Register |
ethanharstad | 1:1b0ada1695a7 | 242 | uint8_t getDeviceID(); |
ethanharstad | 0:d6616b97605d | 243 | |
ethanharstad | 0:d6616b97605d | 244 | private: |
ethanharstad | 2:581fad93a809 | 245 | I2CHelper i2c_; |
ethanharstad | 2:581fad93a809 | 246 | uint8_t address_; |
ethanharstad | 2:581fad93a809 | 247 | uint8_t accelRange_; |
ethanharstad | 2:581fad93a809 | 248 | uint8_t gyroRange_; |
ethanharstad | 1:1b0ada1695a7 | 249 | }; |
ethanharstad | 0:d6616b97605d | 250 | |
ethanharstad | 0:d6616b97605d | 251 | #endif |