Emil Johnsen / mbed-src-STM32F030K6

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targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/stm32l0xx_hal_rtc_ex.c@5:a95fd30f2195, 2016-10-23 (annotated)

Committer:
emilj
Date:
Sun Oct 23 17:23:00 2016 +0000
Revision:
5:a95fd30f2195
Parent:
0:0a673c671a56 
n/a

Who changed what in which revision?

UserRevisionLine numberNew contents of line
ebrus 0:0a673c671a56 1 /**
ebrus 0:0a673c671a56 2 ******************************************************************************
ebrus 0:0a673c671a56 3 * @file stm32l0xx_hal_rtc_ex.c
ebrus 0:0a673c671a56 4 * @author MCD Application Team
ebrus 0:0a673c671a56 5 * @version V1.0.0
ebrus 0:0a673c671a56 6 * @date 22-April-2014
ebrus 0:0a673c671a56 7 * @brief Extended RTC HAL module driver.
ebrus 0:0a673c671a56 8 *
ebrus 0:0a673c671a56 9 * This file provides firmware functions to manage the following
ebrus 0:0a673c671a56 10 * functionalities of the Real Time Clock (RTC) Extension peripheral:
ebrus 0:0a673c671a56 11 * + RTC Time Stamp functions
ebrus 0:0a673c671a56 12 * + RTC Tamper functions
ebrus 0:0a673c671a56 13 * + RTC Wake-up functions
ebrus 0:0a673c671a56 14 * + Extension Control functions
ebrus 0:0a673c671a56 15 * + Extension RTC features functions
ebrus 0:0a673c671a56 16 *
ebrus 0:0a673c671a56 17 @verbatim
ebrus 0:0a673c671a56 18 ==============================================================================
ebrus 0:0a673c671a56 19 ##### Backup Domain Operating Condition #####
ebrus 0:0a673c671a56 20 ==============================================================================
ebrus 0:0a673c671a56 21 [..] As long as the supply voltage remains in the operating range,
ebrus 0:0a673c671a56 22 the RTC never stops, regardless of the device status (Run mode,
ebrus 0:0a673c671a56 23 low power modes or under reset).
ebrus 0:0a673c671a56 24
ebrus 0:0a673c671a56 25 ##### Backup Domain Reset #####
ebrus 0:0a673c671a56 26 ==================================================================
ebrus 0:0a673c671a56 27 [..] The backup domain reset sets all RTC registers and the RCC_CSR register
ebrus 0:0a673c671a56 28 to their reset values.
ebrus 0:0a673c671a56 29 [..] A backup domain reset is generated when one of the following events occurs:
ebrus 0:0a673c671a56 30 (+) Software reset, triggered by setting the RTCRST bit in the
ebrus 0:0a673c671a56 31 RCC Control Status register (RCC_CSR).
ebrus 0:0a673c671a56 32 (+) Power reset (BOR/POR/PDR).
ebrus 0:0a673c671a56 33
ebrus 0:0a673c671a56 34 ##### Backup Domain Access #####
ebrus 0:0a673c671a56 35 ==================================================================
ebrus 0:0a673c671a56 36 [..] After reset, the backup domain (RTC registers and RTC backup data registers)
ebrus 0:0a673c671a56 37 is protected against possible unwanted write accesses.
ebrus 0:0a673c671a56 38 [..] To enable access to the RTC Domain and RTC registers, proceed as follows:
ebrus 0:0a673c671a56 39 (+) Enable the Power Controller (PWR) APB1 interface clock using the
ebrus 0:0a673c671a56 40 __PWR_CLK_ENABLE() function.
ebrus 0:0a673c671a56 41 (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
ebrus 0:0a673c671a56 42 (+) Select the RTC clock source using the __HAL_RCC_RTC_CONFIG() function.
ebrus 0:0a673c671a56 43 (+) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() function.
ebrus 0:0a673c671a56 44
ebrus 0:0a673c671a56 45
ebrus 0:0a673c671a56 46 ##### How to use this driver #####
ebrus 0:0a673c671a56 47 ==============================================================================
ebrus 0:0a673c671a56 48 [..]
ebrus 0:0a673c671a56 49 (+) Enable the RTC domain access.
ebrus 0:0a673c671a56 50 (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
ebrus 0:0a673c671a56 51 format using the HAL_RTC_Init() function.
ebrus 0:0a673c671a56 52
ebrus 0:0a673c671a56 53 *** Time and Date configuration ***
ebrus 0:0a673c671a56 54 ===================================
ebrus 0:0a673c671a56 55 [..]
ebrus 0:0a673c671a56 56 (+) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime()
ebrus 0:0a673c671a56 57 and HAL_RTC_SetDate() functions.
ebrus 0:0a673c671a56 58 (+) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() functions.
ebrus 0:0a673c671a56 59
ebrus 0:0a673c671a56 60 *** Alarm configuration ***
ebrus 0:0a673c671a56 61 ===========================
ebrus 0:0a673c671a56 62 [..]
ebrus 0:0a673c671a56 63 (+) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function.
ebrus 0:0a673c671a56 64 You can also configure the RTC Alarm with interrupt mode using the HAL_RTC_SetAlarm_IT() function.
ebrus 0:0a673c671a56 65 (+) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function.
ebrus 0:0a673c671a56 66
ebrus 0:0a673c671a56 67 *** RTC Wakeup configuration ***
ebrus 0:0a673c671a56 68 ================================
ebrus 0:0a673c671a56 69 [..]
ebrus 0:0a673c671a56 70 (+) To configure the RTC Wakeup Clock source and Counter use the HAL_RTC_SetWakeUpTimer()
ebrus 0:0a673c671a56 71 function. You can also configure the RTC Wakeup timer in interrupt mode
ebrus 0:0a673c671a56 72 using the HAL_RTC_SetWakeUpTimer_IT() function.
ebrus 0:0a673c671a56 73 (+) To read the RTC WakeUp Counter register, use the HAL_RTC_GetWakeUpTimer()
ebrus 0:0a673c671a56 74 function.
ebrus 0:0a673c671a56 75
ebrus 0:0a673c671a56 76 *** Outputs configuration ***
ebrus 0:0a673c671a56 77 =============================
ebrus 0:0a673c671a56 78 [..] The RTC has 2 different outputs:
ebrus 0:0a673c671a56 79 (+) RTC_ALARM: this output is used to manage the RTC Alarm A, Alarm B
ebrus 0:0a673c671a56 80 and WaKeUp signals.
ebrus 0:0a673c671a56 81 To output the selected RTC signal, use the HAL_RTC_Init() function.
ebrus 0:0a673c671a56 82 (+) RTC_CALIB: this output is 512Hz signal or 1Hz.
ebrus 0:0a673c671a56 83 To enable the RTC_CALIB, use the HAL_RTCEx_SetCalibrationOutPut() function.
ebrus 0:0a673c671a56 84 (+) Two pins can be used as RTC_ALARM or RTC_CALIB (PC13, PB14) managed on
ebrus 0:0a673c671a56 85 the RTC_OR register.
ebrus 0:0a673c671a56 86 (+) When the RTC_CALIB or RTC_ALARM output is selected, the RTC_OUT pin is
ebrus 0:0a673c671a56 87 automatically configured in output alternate function.
ebrus 0:0a673c671a56 88
ebrus 0:0a673c671a56 89 *** Smooth digital Calibration configuration ***
ebrus 0:0a673c671a56 90 ================================================
ebrus 0:0a673c671a56 91 [..]
ebrus 0:0a673c671a56 92 (+) Configure the RTC Original Digital Calibration Value and the corresponding
ebrus 0:0a673c671a56 93 calibration cycle period (32s,16s and 8s) using the HAL_RTCEx_SetSmoothCalib()
ebrus 0:0a673c671a56 94 function.
ebrus 0:0a673c671a56 95
ebrus 0:0a673c671a56 96 *** TimeStamp configuration ***
ebrus 0:0a673c671a56 97 ===============================
ebrus 0:0a673c671a56 98 [..]
ebrus 0:0a673c671a56 99 (+) Enables the RTC TimeStamp using the HAL_RTC_SetTimeStamp() function.
ebrus 0:0a673c671a56 100 You can also configure the RTC TimeStamp with interrupt mode using the
ebrus 0:0a673c671a56 101 HAL_RTC_SetTimeStamp_IT() function.
ebrus 0:0a673c671a56 102 (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTC_GetTimeStamp()
ebrus 0:0a673c671a56 103 function.
ebrus 0:0a673c671a56 104
ebrus 0:0a673c671a56 105 *** Tamper configuration ***
ebrus 0:0a673c671a56 106 ============================
ebrus 0:0a673c671a56 107 [..]
ebrus 0:0a673c671a56 108 (+) Enable the RTC Tamper and Configure the Tamper filter count, trigger Edge
ebrus 0:0a673c671a56 109 or Level according to the Tamper filter (if equal to 0 Edge else Level)
ebrus 0:0a673c671a56 110 value, sampling frequency, NoErase, MaskFlag, precharge or discharge and
ebrus 0:0a673c671a56 111 Pull-UP using the HAL_RTC_SetTamper() function. You can configure RTC Tamper
ebrus 0:0a673c671a56 112 with interrupt mode using HAL_RTC_SetTamper_IT() function.
ebrus 0:0a673c671a56 113 (+) The default configuration of the Tamper erases the backup registers. To avoid
ebrus 0:0a673c671a56 114 erase, enable the NoErase field on the RTC_TAMPCR register.
ebrus 0:0a673c671a56 115
ebrus 0:0a673c671a56 116 *** Backup Data Registers configuration ***
ebrus 0:0a673c671a56 117 ===========================================
ebrus 0:0a673c671a56 118 [..]
ebrus 0:0a673c671a56 119 (+) To write to the RTC Backup Data registers, use the HAL_RTC_BKUPWrite()
ebrus 0:0a673c671a56 120 function.
ebrus 0:0a673c671a56 121 (+) To read the RTC Backup Data registers, use the HAL_RTC_BKUPRead()
ebrus 0:0a673c671a56 122 function.
ebrus 0:0a673c671a56 123 (+) The backup registers are reset when a tamper detection event occurs
ebrus 0:0a673c671a56 124
ebrus 0:0a673c671a56 125
ebrus 0:0a673c671a56 126 ##### RTC and low power modes #####
ebrus 0:0a673c671a56 127 ==================================================================
ebrus 0:0a673c671a56 128 [..] The MCU can be woken up from a low power mode by an RTC alternate
ebrus 0:0a673c671a56 129 function.
ebrus 0:0a673c671a56 130 [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B),
ebrus 0:0a673c671a56 131 RTC wakeup, RTC tamper event detection and RTC time stamp event detection.
ebrus 0:0a673c671a56 132 These RTC alternate functions can wake up the system from the Stop and
ebrus 0:0a673c671a56 133 Standby low power modes.
ebrus 0:0a673c671a56 134 [..] The system can also wake up from low power modes without depending
ebrus 0:0a673c671a56 135 on an external interrupt (Auto-wakeup mode), by using the RTC alarm
ebrus 0:0a673c671a56 136 or the RTC wakeup events.
ebrus 0:0a673c671a56 137 [..] The RTC provides a programmable time base for waking up from the
ebrus 0:0a673c671a56 138 Stop or Standby mode at regular intervals.
ebrus 0:0a673c671a56 139 Wakeup from STOP and Standby modes is possible only when the RTC clock source
ebrus 0:0a673c671a56 140 is LSE or LSI.
ebrus 0:0a673c671a56 141
ebrus 0:0a673c671a56 142 @endverbatim
ebrus 0:0a673c671a56 143 ******************************************************************************
ebrus 0:0a673c671a56 144 * @attention
ebrus 0:0a673c671a56 145 *
ebrus 0:0a673c671a56 146 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
ebrus 0:0a673c671a56 147 *
ebrus 0:0a673c671a56 148 * Redistribution and use in source and binary forms, with or without modification,
ebrus 0:0a673c671a56 149 * are permitted provided that the following conditions are met:
ebrus 0:0a673c671a56 150 * 1. Redistributions of source code must retain the above copyright notice,
ebrus 0:0a673c671a56 151 * this list of conditions and the following disclaimer.
ebrus 0:0a673c671a56 152 * 2. Redistributions in binary form must reproduce the above copyright notice,
ebrus 0:0a673c671a56 153 * this list of conditions and the following disclaimer in the documentation
ebrus 0:0a673c671a56 154 * and/or other materials provided with the distribution.
ebrus 0:0a673c671a56 155 * 3. Neither the name of STMicroelectronics nor the names of its contributors
ebrus 0:0a673c671a56 156 * may be used to endorse or promote products derived from this software
ebrus 0:0a673c671a56 157 * without specific prior written permission.
ebrus 0:0a673c671a56 158 *
ebrus 0:0a673c671a56 159 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
ebrus 0:0a673c671a56 160 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
ebrus 0:0a673c671a56 161 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
ebrus 0:0a673c671a56 162 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
ebrus 0:0a673c671a56 163 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
ebrus 0:0a673c671a56 164 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
ebrus 0:0a673c671a56 165 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
ebrus 0:0a673c671a56 166 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
ebrus 0:0a673c671a56 167 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
ebrus 0:0a673c671a56 168 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
ebrus 0:0a673c671a56 169 *
ebrus 0:0a673c671a56 170 ******************************************************************************
ebrus 0:0a673c671a56 171 */
ebrus 0:0a673c671a56 172
ebrus 0:0a673c671a56 173 /* Includes ------------------------------------------------------------------*/
ebrus 0:0a673c671a56 174 #include "stm32l0xx_hal.h"
ebrus 0:0a673c671a56 175
ebrus 0:0a673c671a56 176 /** @addtogroup STM32L0xx_HAL_Driver
ebrus 0:0a673c671a56 177 * @{
ebrus 0:0a673c671a56 178 */
ebrus 0:0a673c671a56 179
ebrus 0:0a673c671a56 180 /** @defgroup RTCEx
ebrus 0:0a673c671a56 181 * @brief RTC HAL module driver
ebrus 0:0a673c671a56 182 * @{
ebrus 0:0a673c671a56 183 */
ebrus 0:0a673c671a56 184
ebrus 0:0a673c671a56 185 #ifdef HAL_RTC_MODULE_ENABLED
ebrus 0:0a673c671a56 186
ebrus 0:0a673c671a56 187 /* Private typedef -----------------------------------------------------------*/
ebrus 0:0a673c671a56 188 /* Private define ------------------------------------------------------------*/
ebrus 0:0a673c671a56 189 /* Masks Definition */
ebrus 0:0a673c671a56 190 #define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F)
ebrus 0:0a673c671a56 191 #define RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3F)
ebrus 0:0a673c671a56 192 #define RTC_INIT_MASK ((uint32_t)0xFFFFFFFF)
ebrus 0:0a673c671a56 193 #define RTC_RSF_MASK ((uint32_t)0xFFFFFF5F)
ebrus 0:0a673c671a56 194 #define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_WUTF | \
ebrus 0:0a673c671a56 195 RTC_FLAG_ALRBF | RTC_FLAG_INITF | RTC_FLAG_RSF | \
ebrus 0:0a673c671a56 196 RTC_FLAG_INITS | RTC_FLAG_WUTWF | RTC_FLAG_ALRBWF | \
ebrus 0:0a673c671a56 197 RTC_FLAG_TAMP1F | RTC_FLAG_TAMP2F | \
ebrus 0:0a673c671a56 198 RTC_FLAG_RECALPF | RTC_FLAG_SHPF))
ebrus 0:0a673c671a56 199
ebrus 0:0a673c671a56 200 #define RTC_TIMEOUT_VALUE 1000
ebrus 0:0a673c671a56 201 /* Private macro -------------------------------------------------------------*/
ebrus 0:0a673c671a56 202 /* Private variables ---------------------------------------------------------*/
ebrus 0:0a673c671a56 203 /* Private function prototypes -----------------------------------------------*/
ebrus 0:0a673c671a56 204 /* Private functions ---------------------------------------------------------*/
ebrus 0:0a673c671a56 205
ebrus 0:0a673c671a56 206 /** @defgroup RTCEx_Private_Functions
ebrus 0:0a673c671a56 207 * @{
ebrus 0:0a673c671a56 208 */
ebrus 0:0a673c671a56 209
ebrus 0:0a673c671a56 210 /** @defgroup RTCEx_Group1 RTC TimeStamp and Tamper functions
ebrus 0:0a673c671a56 211 * @brief RTC TimeStamp and Tamper functions
ebrus 0:0a673c671a56 212 *
ebrus 0:0a673c671a56 213 @verbatim
ebrus 0:0a673c671a56 214 ===============================================================================
ebrus 0:0a673c671a56 215 ##### RTC TimeStamp and Tamper functions #####
ebrus 0:0a673c671a56 216 ===============================================================================
ebrus 0:0a673c671a56 217 @endverbatim
ebrus 0:0a673c671a56 218 * @{
ebrus 0:0a673c671a56 219 */
ebrus 0:0a673c671a56 220
ebrus 0:0a673c671a56 221 /**
ebrus 0:0a673c671a56 222 * @brief Sets TimeStamp.
ebrus 0:0a673c671a56 223 * @note This API must be called before enabling the TimeStamp feature.
ebrus 0:0a673c671a56 224 * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
ebrus 0:0a673c671a56 225 * the configuration information for RTC.
ebrus 0:0a673c671a56 226 * @param TimeStampEdge: Specifies the pin edge on which the TimeStamp is
ebrus 0:0a673c671a56 227 * activated.
ebrus 0:0a673c671a56 228 * This parameter can be one of the following values:
ebrus 0:0a673c671a56 229 * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the
ebrus 0:0a673c671a56 230 * rising edge of the related pin.
ebrus 0:0a673c671a56 231 * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the
ebrus 0:0a673c671a56 232 * falling edge of the related pin.
ebrus 0:0a673c671a56 233 * @param RTC_TimeStampPin: specifies the RTC TimeStamp Pin.
ebrus 0:0a673c671a56 234 * This parameter can be one of the following values:
ebrus 0:0a673c671a56 235 * @arg RTC_TIMESTAMPPIN_PC13: PC13 is selected as RTC TimeStamp Pin.
ebrus 0:0a673c671a56 236 * The RTC TimeStamp Pin is per default PC13, but for reasons of
ebrus 0:0a673c671a56 237 * compatibility, this parameter is used.
ebrus 0:0a673c671a56 238 * @retval HAL status
ebrus 0:0a673c671a56 239 */
ebrus 0:0a673c671a56 240 HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
ebrus 0:0a673c671a56 241 {
ebrus 0:0a673c671a56 242 uint32_t tmpreg = 0;
ebrus 0:0a673c671a56 243
ebrus 0:0a673c671a56 244 /* Check the parameters */
ebrus 0:0a673c671a56 245 assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge));
ebrus 0:0a673c671a56 246 assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin));
ebrus 0:0a673c671a56 247
ebrus 0:0a673c671a56 248 /* Process Locked */
ebrus 0:0a673c671a56 249 __HAL_LOCK(hrtc);
ebrus 0:0a673c671a56 250
ebrus 0:0a673c671a56 251 hrtc->State = HAL_RTC_STATE_BUSY;
ebrus 0:0a673c671a56 252
ebrus 0:0a673c671a56 253 /* Get the RTC_CR register and clear the bits to be configured */
ebrus 0:0a673c671a56 254 tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
ebrus 0:0a673c671a56 255
ebrus 0:0a673c671a56 256 tmpreg|= TimeStampEdge;
ebrus 0:0a673c671a56 257
ebrus 0:0a673c671a56 258 /* Disable the write protection for RTC registers */
ebrus 0:0a673c671a56 259 __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
ebrus 0:0a673c671a56 260
ebrus 0:0a673c671a56 261 /* Configure the Time Stamp TSEDGE and Enable bits */
ebrus 0:0a673c671a56 262 hrtc->Instance->CR = (uint32_t)tmpreg;
ebrus 0:0a673c671a56 263
ebrus 0:0a673c671a56 264 __HAL_RTC_TIMESTAMP_ENABLE(hrtc);
ebrus 0:0a673c671a56 265
ebrus 0:0a673c671a56 266 /* Enable the write protection for RTC registers */
ebrus 0:0a673c671a56 267 __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
ebrus 0:0a673c671a56 268
ebrus 0:0a673c671a56 269 /* Change RTC state */
ebrus 0:0a673c671a56 270 hrtc->State = HAL_RTC_STATE_READY;
ebrus 0:0a673c671a56 271
ebrus 0:0a673c671a56 272 /* Process Unlocked */
ebrus 0:0a673c671a56 273 __HAL_UNLOCK(hrtc);
ebrus 0:0a673c671a56 274
ebrus 0:0a673c671a56 275 return HAL_OK;
ebrus 0:0a673c671a56 276 }
ebrus 0:0a673c671a56 277
ebrus 0:0a673c671a56 278 /**
ebrus 0:0a673c671a56 279 * @brief Sets TimeStamp with Interrupt.
ebrus 0:0a673c671a56 280 * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
ebrus 0:0a673c671a56 281 * the configuration information for RTC.
ebrus 0:0a673c671a56 282 * @note This API must be called before enabling the TimeStamp feature.
ebrus 0:0a673c671a56 283 * @param TimeStampEdge: Specifies the pin edge on which the TimeStamp is
ebrus 0:0a673c671a56 284 * activated.
ebrus 0:0a673c671a56 285 * This parameter can be one of the following values:
ebrus 0:0a673c671a56 286 * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the
ebrus 0:0a673c671a56 287 * rising edge of the related pin.
ebrus 0:0a673c671a56 288 * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the
ebrus 0:0a673c671a56 289 * falling edge of the related pin.
ebrus 0:0a673c671a56 290 * @param RTC_TimeStampPin: Specifies the RTC TimeStamp Pin.
ebrus 0:0a673c671a56 291 * This parameter can be one of the following values:
ebrus 0:0a673c671a56 292 * @arg RTC_TIMESTAMPPIN_PC13: PC13 is selected as RTC TimeStamp Pin.
ebrus 0:0a673c671a56 293 * The RTC TimeStamp Pin is per default PC13, but for reasons of
ebrus 0:0a673c671a56 294 * compatibility, this parameter is used.
ebrus 0:0a673c671a56 295 * @retval HAL status
ebrus 0:0a673c671a56 296 */
ebrus 0:0a673c671a56 297 HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
ebrus 0:0a673c671a56 298 {
ebrus 0:0a673c671a56 299 uint32_t tmpreg = 0;
ebrus 0:0a673c671a56 300
ebrus 0:0a673c671a56 301 /* Check the parameters */
ebrus 0:0a673c671a56 302 assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge));
ebrus 0:0a673c671a56 303 assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin));
ebrus 0:0a673c671a56 304
ebrus 0:0a673c671a56 305 /* Process Locked */
ebrus 0:0a673c671a56 306 __HAL_LOCK(hrtc);
ebrus 0:0a673c671a56 307
ebrus 0:0a673c671a56 308 hrtc->State = HAL_RTC_STATE_BUSY;
ebrus 0:0a673c671a56 309
ebrus 0:0a673c671a56 310 /* Get the RTC_CR register and clear the bits to be configured */
ebrus 0:0a673c671a56 311 tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
ebrus 0:0a673c671a56 312
ebrus 0:0a673c671a56 313 tmpreg |= TimeStampEdge;
ebrus 0:0a673c671a56 314
ebrus 0:0a673c671a56 315 /* Disable the write protection for RTC registers */
ebrus 0:0a673c671a56 316 __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
ebrus 0:0a673c671a56 317
ebrus 0:0a673c671a56 318 /* Configure the Time Stamp TSEDGE and Enable bits */
ebrus 0:0a673c671a56 319 hrtc->Instance->CR = (uint32_t)tmpreg;
ebrus 0:0a673c671a56 320
ebrus 0:0a673c671a56 321 __HAL_RTC_TIMESTAMP_ENABLE(hrtc);
ebrus 0:0a673c671a56 322
ebrus 0:0a673c671a56 323 /* Enable IT timestamp */
ebrus 0:0a673c671a56 324 __HAL_RTC_TIMESTAMP_ENABLE_IT(hrtc,RTC_IT_TS);
ebrus 0:0a673c671a56 325
ebrus 0:0a673c671a56 326 /* RTC timestamp Interrupt Configuration: EXTI configuration */
ebrus 0:0a673c671a56 327 __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT);
ebrus 0:0a673c671a56 328
ebrus 0:0a673c671a56 329 EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT;
ebrus 0:0a673c671a56 330
ebrus 0:0a673c671a56 331 /* Enable the write protection for RTC registers */
ebrus 0:0a673c671a56 332 __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
ebrus 0:0a673c671a56 333
ebrus 0:0a673c671a56 334 hrtc->State = HAL_RTC_STATE_READY;
ebrus 0:0a673c671a56 335
ebrus 0:0a673c671a56 336 /* Process Unlocked */
ebrus 0:0a673c671a56 337 __HAL_UNLOCK(hrtc);
ebrus 0:0a673c671a56 338
ebrus 0:0a673c671a56 339 return HAL_OK;
ebrus 0:0a673c671a56 340 }
ebrus 0:0a673c671a56 341
ebrus 0:0a673c671a56 342 /**
ebrus 0:0a673c671a56 343 * @brief Deactivates TimeStamp.
ebrus 0:0a673c671a56 344 * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
ebrus 0:0a673c671a56 345 * the configuration information for RTC.
ebrus 0:0a673c671a56 346 * @retval HAL status
ebrus 0:0a673c671a56 347 */
ebrus 0:0a673c671a56 348 HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc)
ebrus 0:0a673c671a56 349 {
ebrus 0:0a673c671a56 350 uint32_t tmpreg = 0;
ebrus 0:0a673c671a56 351
ebrus 0:0a673c671a56 352 /* Process Locked */
ebrus 0:0a673c671a56 353 __HAL_LOCK(hrtc);
ebrus 0:0a673c671a56 354
ebrus 0:0a673c671a56 355 hrtc->State = HAL_RTC_STATE_BUSY;
ebrus 0:0a673c671a56 356
ebrus 0:0a673c671a56 357 /* Disable the write protection for RTC registers */
ebrus 0:0a673c671a56 358 __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
ebrus 0:0a673c671a56 359
ebrus 0:0a673c671a56 360 /* In case of interrupt mode is used, the interrupt source must disabled */
ebrus 0:0a673c671a56 361 __HAL_RTC_TIMESTAMP_DISABLE_IT(hrtc, RTC_IT_TS);
ebrus 0:0a673c671a56 362
ebrus 0:0a673c671a56 363 /* Get the RTC_CR register and clear the bits to be configured */
ebrus 0:0a673c671a56 364 tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
ebrus 0:0a673c671a56 365
ebrus 0:0a673c671a56 366 /* Configure the Time Stamp TSEDGE and Enable bits */
ebrus 0:0a673c671a56 367 hrtc->Instance->CR = (uint32_t)tmpreg;
ebrus 0:0a673c671a56 368
ebrus 0:0a673c671a56 369 /* Enable the write protection for RTC registers */
ebrus 0:0a673c671a56 370 __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
ebrus 0:0a673c671a56 371
ebrus 0:0a673c671a56 372 hrtc->State = HAL_RTC_STATE_READY;
ebrus 0:0a673c671a56 373
ebrus 0:0a673c671a56 374 /* Process Unlocked */
ebrus 0:0a673c671a56 375 __HAL_UNLOCK(hrtc);
ebrus 0:0a673c671a56 376
ebrus 0:0a673c671a56 377 return HAL_OK;
ebrus 0:0a673c671a56 378 }
ebrus 0:0a673c671a56 379
ebrus 0:0a673c671a56 380 /**
ebrus 0:0a673c671a56 381 * @brief Gets the RTC TimeStamp value.
ebrus 0:0a673c671a56 382 * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
ebrus 0:0a673c671a56 383 * the configuration information for RTC.
ebrus 0:0a673c671a56 384 * @param sTimeStamp: Pointer to Time structure
ebrus 0:0a673c671a56 385 * @param sTimeStampDate: Pointer to Date structure
ebrus 0:0a673c671a56 386 * @param Format: specifies the format of the entered parameters.
ebrus 0:0a673c671a56 387 * This parameter can be one of the following values:
ebrus 0:0a673c671a56 388 * FORMAT_BIN: Binary data format
ebrus 0:0a673c671a56 389 * FORMAT_BCD: BCD data format
ebrus 0:0a673c671a56 390 * @retval HAL status
ebrus 0:0a673c671a56 391 */
ebrus 0:0a673c671a56 392 HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef* sTimeStamp, RTC_DateTypeDef* sTimeStampDate, uint32_t Format)
ebrus 0:0a673c671a56 393 {
ebrus 0:0a673c671a56 394 uint32_t tmptime = 0, tmpdate = 0;
ebrus 0:0a673c671a56 395
ebrus 0:0a673c671a56 396 /* Check the parameters */
ebrus 0:0a673c671a56 397 assert_param(IS_RTC_FORMAT(Format));
ebrus 0:0a673c671a56 398
ebrus 0:0a673c671a56 399 /* Get the TimeStamp time and date registers values */
ebrus 0:0a673c671a56 400 tmptime = (uint32_t)(hrtc->Instance->TSTR & RTC_TR_RESERVED_MASK);
ebrus 0:0a673c671a56 401 tmpdate = (uint32_t)(hrtc->Instance->TSDR & RTC_DR_RESERVED_MASK);
ebrus 0:0a673c671a56 402
ebrus 0:0a673c671a56 403 /* Fill the Time structure fields with the read parameters */
ebrus 0:0a673c671a56 404 sTimeStamp->Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16);
ebrus 0:0a673c671a56 405 sTimeStamp->Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8);
ebrus 0:0a673c671a56 406 sTimeStamp->Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU));
ebrus 0:0a673c671a56 407 sTimeStamp->TimeFormat = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16);
ebrus 0:0a673c671a56 408 sTimeStamp->SubSeconds = (uint32_t) hrtc->Instance->TSSSR;
ebrus 0:0a673c671a56 409
ebrus 0:0a673c671a56 410 /* Fill the Date structure fields with the read parameters */
ebrus 0:0a673c671a56 411 sTimeStampDate->Year = 0;
ebrus 0:0a673c671a56 412 sTimeStampDate->Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8);
ebrus 0:0a673c671a56 413 sTimeStampDate->Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU));
ebrus 0:0a673c671a56 414 sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13);
ebrus 0:0a673c671a56 415
ebrus 0:0a673c671a56 416 /* Check the input parameters format */
ebrus 0:0a673c671a56 417 if(Format == FORMAT_BIN)
ebrus 0:0a673c671a56 418 {
ebrus 0:0a673c671a56 419 /* Convert the TimeStamp structure parameters to Binary format */
ebrus 0:0a673c671a56 420 sTimeStamp->Hours = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Hours);
ebrus 0:0a673c671a56 421 sTimeStamp->Minutes = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Minutes);
ebrus 0:0a673c671a56 422 sTimeStamp->Seconds = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Seconds);
ebrus 0:0a673c671a56 423
ebrus 0:0a673c671a56 424 /* Convert the DateTimeStamp structure parameters to Binary format */
ebrus 0:0a673c671a56 425 sTimeStampDate->Month = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Month);
ebrus 0:0a673c671a56 426 sTimeStampDate->Date = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Date);
ebrus 0:0a673c671a56 427 sTimeStampDate->WeekDay = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->WeekDay);
ebrus 0:0a673c671a56 428 }
ebrus 0:0a673c671a56 429
ebrus 0:0a673c671a56 430 /* Clear the TIMESTAMP Flag */
ebrus 0:0a673c671a56 431 __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF);
ebrus 0:0a673c671a56 432
ebrus 0:0a673c671a56 433 return HAL_OK;
ebrus 0:0a673c671a56 434 }
ebrus 0:0a673c671a56 435
ebrus 0:0a673c671a56 436 /**
ebrus 0:0a673c671a56 437 * @brief Sets Tamper
ebrus 0:0a673c671a56 438 * @note By calling this API we disable the tamper interrupt for all tampers.
ebrus 0:0a673c671a56 439 * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
ebrus 0:0a673c671a56 440 * the configuration information for RTC.
ebrus 0:0a673c671a56 441 * @param sTamper: Pointer to Tamper Structure.
ebrus 0:0a673c671a56 442 * @retval HAL status
ebrus 0:0a673c671a56 443 */
ebrus 0:0a673c671a56 444 HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper)
ebrus 0:0a673c671a56 445 {
ebrus 0:0a673c671a56 446 uint32_t tmpreg = 0;
ebrus 0:0a673c671a56 447
ebrus 0:0a673c671a56 448 /* Check the parameters */
ebrus 0:0a673c671a56 449 assert_param(IS_TAMPER(sTamper->Tamper));
ebrus 0:0a673c671a56 450 assert_param(IS_TAMPER_TRIGGER(sTamper->Trigger));
ebrus 0:0a673c671a56 451 assert_param(IS_TAMPER_ERASE_MODE(sTamper->NoErase));
ebrus 0:0a673c671a56 452 assert_param(IS_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag));
ebrus 0:0a673c671a56 453 assert_param(IS_TAMPER_FILTER(sTamper->Filter));
ebrus 0:0a673c671a56 454 assert_param(IS_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency));
ebrus 0:0a673c671a56 455 assert_param(IS_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));
ebrus 0:0a673c671a56 456 assert_param(IS_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));
ebrus 0:0a673c671a56 457 assert_param(IS_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection));
ebrus 0:0a673c671a56 458
ebrus 0:0a673c671a56 459 /* Process Locked */
ebrus 0:0a673c671a56 460 __HAL_LOCK(hrtc);
ebrus 0:0a673c671a56 461
ebrus 0:0a673c671a56 462 hrtc->State = HAL_RTC_STATE_BUSY;
ebrus 0:0a673c671a56 463
ebrus 0:0a673c671a56 464 /* Configure the tamper trigger */
ebrus 0:0a673c671a56 465 if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE)
ebrus 0:0a673c671a56 466 {
ebrus 0:0a673c671a56 467 sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1);
ebrus 0:0a673c671a56 468 }
ebrus 0:0a673c671a56 469
ebrus 0:0a673c671a56 470 if(sTamper->NoErase == RTC_TAMPERERASEBACKUP_ENABLED)
ebrus 0:0a673c671a56 471 {
ebrus 0:0a673c671a56 472 /* Configure the RTC_TAMPCR register */
ebrus 0:0a673c671a56 473 sTamper->NoErase = RTC_TAMPERERASEBACKUP_ENABLED;
ebrus 0:0a673c671a56 474 }
ebrus 0:0a673c671a56 475 else
ebrus 0:0a673c671a56 476 {
ebrus 0:0a673c671a56 477 sTamper->NoErase = (uint32_t)(sTamper->Tamper << 17);
ebrus 0:0a673c671a56 478 }
ebrus 0:0a673c671a56 479
ebrus 0:0a673c671a56 480 if(sTamper->MaskFlag == RTC_MASKTAMPERFLAG_DISABLED)
ebrus 0:0a673c671a56 481 {
ebrus 0:0a673c671a56 482 /* Configure the RTC_TAMPCR register */
ebrus 0:0a673c671a56 483 sTamper->MaskFlag = RTC_MASKTAMPERFLAG_DISABLED;
ebrus 0:0a673c671a56 484 }
ebrus 0:0a673c671a56 485 else
ebrus 0:0a673c671a56 486 {
ebrus 0:0a673c671a56 487 sTamper->MaskFlag = (uint32_t)(sTamper->Tamper << 18);
ebrus 0:0a673c671a56 488 }
ebrus 0:0a673c671a56 489
ebrus 0:0a673c671a56 490 tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Trigger | (uint32_t)sTamper->NoErase |\
ebrus 0:0a673c671a56 491 (uint32_t)sTamper->MaskFlag | (uint32_t)sTamper->Filter | (uint32_t)sTamper->SamplingFrequency |\
ebrus 0:0a673c671a56 492 (uint32_t)sTamper->PrechargeDuration | (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection);
ebrus 0:0a673c671a56 493
ebrus 0:0a673c671a56 494 hrtc->Instance->TAMPCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | (uint32_t)RTC_TAMPCR_TAMPTS |\
ebrus 0:0a673c671a56 495 (uint32_t)RTC_TAMPCR_TAMPFREQ | (uint32_t)RTC_TAMPCR_TAMPFLT | (uint32_t)RTC_TAMPCR_TAMPPRCH |\
ebrus 0:0a673c671a56 496 (uint32_t)RTC_TAMPCR_TAMPPUDIS | (uint32_t)RTC_TAMPCR_TAMPIE | (uint32_t)RTC_TAMPCR_TAMP1IE |\
ebrus 0:0a673c671a56 497 (uint32_t)RTC_TAMPCR_TAMP2IE);
ebrus 0:0a673c671a56 498
ebrus 0:0a673c671a56 499 hrtc->Instance->TAMPCR |= tmpreg;
ebrus 0:0a673c671a56 500
ebrus 0:0a673c671a56 501 hrtc->State = HAL_RTC_STATE_READY;
ebrus 0:0a673c671a56 502
ebrus 0:0a673c671a56 503 /* Process Unlocked */
ebrus 0:0a673c671a56 504 __HAL_UNLOCK(hrtc);
ebrus 0:0a673c671a56 505
ebrus 0:0a673c671a56 506 return HAL_OK;
ebrus 0:0a673c671a56 507 }
ebrus 0:0a673c671a56 508
ebrus 0:0a673c671a56 509 /**
ebrus 0:0a673c671a56 510 * @brief Sets Tamper with interrupt.
ebrus 0:0a673c671a56 511 * @note By calling this API we force the tamper interrupt for all tampers.
ebrus 0:0a673c671a56 512 * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
ebrus 0:0a673c671a56 513 * the configuration information for RTC.
ebrus 0:0a673c671a56 514 * @param sTamper: Pointer to RTC Tamper.
ebrus 0:0a673c671a56 515 * @retval HAL status
ebrus 0:0a673c671a56 516 */
ebrus 0:0a673c671a56 517 HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper)
ebrus 0:0a673c671a56 518 {
ebrus 0:0a673c671a56 519 uint32_t tmpreg = 0;
ebrus 0:0a673c671a56 520
ebrus 0:0a673c671a56 521 /* Check the parameters */
ebrus 0:0a673c671a56 522 assert_param(IS_TAMPER(sTamper->Tamper));
ebrus 0:0a673c671a56 523 assert_param(IS_TAMPER_INTERRUPT(sTamper->Interrupt));
ebrus 0:0a673c671a56 524 assert_param(IS_TAMPER_TRIGGER(sTamper->Trigger));
ebrus 0:0a673c671a56 525 assert_param(IS_TAMPER_ERASE_MODE(sTamper->NoErase));
ebrus 0:0a673c671a56 526 assert_param(IS_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag));
ebrus 0:0a673c671a56 527 assert_param(IS_TAMPER_FILTER(sTamper->Filter));
ebrus 0:0a673c671a56 528 assert_param(IS_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency));
ebrus 0:0a673c671a56 529 assert_param(IS_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));
ebrus 0:0a673c671a56 530 assert_param(IS_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));
ebrus 0:0a673c671a56 531 assert_param(IS_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection));
ebrus 0:0a673c671a56 532
ebrus 0:0a673c671a56 533 /* Process Locked */
ebrus 0:0a673c671a56 534 __HAL_LOCK(hrtc);
ebrus 0:0a673c671a56 535
ebrus 0:0a673c671a56 536 hrtc->State = HAL_RTC_STATE_BUSY;
ebrus 0:0a673c671a56 537
ebrus 0:0a673c671a56 538 /* Configure the tamper trigger */
ebrus 0:0a673c671a56 539 if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE)
ebrus 0:0a673c671a56 540 {
ebrus 0:0a673c671a56 541 sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1);
ebrus 0:0a673c671a56 542 }
ebrus 0:0a673c671a56 543
ebrus 0:0a673c671a56 544 if(sTamper->NoErase == RTC_TAMPERERASEBACKUP_ENABLED)
ebrus 0:0a673c671a56 545 {
ebrus 0:0a673c671a56 546 /* Configure the RTC_TAMPCR register */
ebrus 0:0a673c671a56 547 sTamper->NoErase = RTC_TAMPERERASEBACKUP_ENABLED;
ebrus 0:0a673c671a56 548 }
ebrus 0:0a673c671a56 549 else
ebrus 0:0a673c671a56 550 {
ebrus 0:0a673c671a56 551 sTamper->NoErase = (uint32_t)(sTamper->Tamper << 17);
ebrus 0:0a673c671a56 552 }
ebrus 0:0a673c671a56 553
ebrus 0:0a673c671a56 554 if(sTamper->MaskFlag == RTC_MASKTAMPERFLAG_DISABLED)
ebrus 0:0a673c671a56 555 {
ebrus 0:0a673c671a56 556 /* Configure the RTC_TAMPCR register */
ebrus 0:0a673c671a56 557 sTamper->MaskFlag = RTC_MASKTAMPERFLAG_DISABLED;
ebrus 0:0a673c671a56 558 }
ebrus 0:0a673c671a56 559 else
ebrus 0:0a673c671a56 560 {
ebrus 0:0a673c671a56 561 sTamper->MaskFlag = (uint32_t)(sTamper->Tamper << 18);
ebrus 0:0a673c671a56 562 }
ebrus 0:0a673c671a56 563
ebrus 0:0a673c671a56 564 tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Interrupt | (uint32_t)sTamper->Trigger | (uint32_t)sTamper->NoErase |\
ebrus 0:0a673c671a56 565 (uint32_t)sTamper->MaskFlag | (uint32_t)sTamper->Filter | (uint32_t)sTamper->SamplingFrequency |\
ebrus 0:0a673c671a56 566 (uint32_t)sTamper->PrechargeDuration | (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection);
ebrus 0:0a673c671a56 567
ebrus 0:0a673c671a56 568 hrtc->Instance->TAMPCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | (uint32_t)RTC_TAMPCR_TAMPTS |\
ebrus 0:0a673c671a56 569 (uint32_t)RTC_TAMPCR_TAMPFREQ | (uint32_t)RTC_TAMPCR_TAMPFLT | (uint32_t)RTC_TAMPCR_TAMPPRCH |\
ebrus 0:0a673c671a56 570 (uint32_t)RTC_TAMPCR_TAMPPUDIS | (uint32_t)RTC_TAMPCR_TAMPIE | (uint32_t)RTC_TAMPCR_TAMP1IE |\
ebrus 0:0a673c671a56 571 (uint32_t)RTC_TAMPCR_TAMP2IE);
ebrus 0:0a673c671a56 572
ebrus 0:0a673c671a56 573 hrtc->Instance->TAMPCR |= tmpreg;
ebrus 0:0a673c671a56 574
ebrus 0:0a673c671a56 575 /* RTC Tamper Interrupt Configuration: EXTI configuration */
ebrus 0:0a673c671a56 576 __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT);
ebrus 0:0a673c671a56 577
ebrus 0:0a673c671a56 578 EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT;
ebrus 0:0a673c671a56 579
ebrus 0:0a673c671a56 580 hrtc->State = HAL_RTC_STATE_READY;
ebrus 0:0a673c671a56 581
ebrus 0:0a673c671a56 582 /* Process Unlocked */
ebrus 0:0a673c671a56 583 __HAL_UNLOCK(hrtc);
ebrus 0:0a673c671a56 584
ebrus 0:0a673c671a56 585 return HAL_OK;
ebrus 0:0a673c671a56 586 }
ebrus 0:0a673c671a56 587
ebrus 0:0a673c671a56 588 /**
ebrus 0:0a673c671a56 589 * @brief Deactivates Tamper.
ebrus 0:0a673c671a56 590 * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
ebrus 0:0a673c671a56 591 * the configuration information for RTC.
ebrus 0:0a673c671a56 592 * @param Tamper: Selected tamper pin.
ebrus 0:0a673c671a56 593 * This parameter can be RTC_Tamper_1 and/or RTC_TAMPER_2.
ebrus 0:0a673c671a56 594 * @retval HAL status
ebrus 0:0a673c671a56 595 */
ebrus 0:0a673c671a56 596 HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper)
ebrus 0:0a673c671a56 597 {
ebrus 0:0a673c671a56 598 assert_param(IS_TAMPER(Tamper));
ebrus 0:0a673c671a56 599
ebrus 0:0a673c671a56 600 /* Process Locked */
ebrus 0:0a673c671a56 601 __HAL_LOCK(hrtc);
ebrus 0:0a673c671a56 602
ebrus 0:0a673c671a56 603 hrtc->State = HAL_RTC_STATE_BUSY;
ebrus 0:0a673c671a56 604
ebrus 0:0a673c671a56 605 /* Disable the selected Tamper pin */
ebrus 0:0a673c671a56 606 hrtc->Instance->TAMPCR &= (uint32_t)~Tamper;
ebrus 0:0a673c671a56 607
ebrus 0:0a673c671a56 608 if (Tamper == RTC_TAMPER_1)
ebrus 0:0a673c671a56 609 {
ebrus 0:0a673c671a56 610 /* Disable the Tamper1 interrupt */
ebrus 0:0a673c671a56 611 hrtc->Instance->TAMPCR &= (uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP1);
ebrus 0:0a673c671a56 612 }
ebrus 0:0a673c671a56 613 else
ebrus 0:0a673c671a56 614 {
ebrus 0:0a673c671a56 615 /* Disable the Tamper2 interrupt */
ebrus 0:0a673c671a56 616 hrtc->Instance->TAMPCR &= (uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP2);
ebrus 0:0a673c671a56 617 }
ebrus 0:0a673c671a56 618
ebrus 0:0a673c671a56 619 hrtc->State = HAL_RTC_STATE_READY;
ebrus 0:0a673c671a56 620
ebrus 0:0a673c671a56 621 /* Process Unlocked */
ebrus 0:0a673c671a56 622 __HAL_UNLOCK(hrtc);
ebrus 0:0a673c671a56 623
ebrus 0:0a673c671a56 624 return HAL_OK;
ebrus 0:0a673c671a56 625 }
ebrus 0:0a673c671a56 626
ebrus 0:0a673c671a56 627 /**
ebrus 0:0a673c671a56 628 * @brief Sets wake up timer.
ebrus 0:0a673c671a56 629 * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
ebrus 0:0a673c671a56 630 * the configuration information for RTC.
ebrus 0:0a673c671a56 631 * @param WakeUpCounter: Wake up counter
ebrus 0:0a673c671a56 632 * @param WakeUpClock: Wake up clock
ebrus 0:0a673c671a56 633 * @retval HAL status
ebrus 0:0a673c671a56 634 */
ebrus 0:0a673c671a56 635 HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
ebrus 0:0a673c671a56 636 {
ebrus 0:0a673c671a56 637 uint32_t tickstart;
ebrus 0:0a673c671a56 638
ebrus 0:0a673c671a56 639 /* Check the parameters */
ebrus 0:0a673c671a56 640 assert_param(IS_WAKEUP_CLOCK(WakeUpClock));
ebrus 0:0a673c671a56 641 assert_param(IS_WAKEUP_COUNTER(WakeUpCounter));
ebrus 0:0a673c671a56 642
ebrus 0:0a673c671a56 643 /* Process Locked */
ebrus 0:0a673c671a56 644 __HAL_LOCK(hrtc);
ebrus 0:0a673c671a56 645
ebrus 0:0a673c671a56 646 hrtc->State = HAL_RTC_STATE_BUSY;
ebrus 0:0a673c671a56 647
ebrus 0:0a673c671a56 648 /* Disable the write protection for RTC registers */
ebrus 0:0a673c671a56 649 __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
ebrus 0:0a673c671a56 650
ebrus 0:0a673c671a56 651 __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
ebrus 0:0a673c671a56 652
ebrus 0:0a673c671a56 653 tickstart = HAL_GetTick();
ebrus 0:0a673c671a56 654
ebrus 0:0a673c671a56 655 /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
ebrus 0:0a673c671a56 656 while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
ebrus 0:0a673c671a56 657 {
ebrus 0:0a673c671a56 658 if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
ebrus 0:0a673c671a56 659 {
ebrus 0:0a673c671a56 660 /* Enable the write protection for RTC registers */
ebrus 0:0a673c671a56 661 __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
ebrus 0:0a673c671a56 662
ebrus 0:0a673c671a56 663 hrtc->State = HAL_RTC_STATE_TIMEOUT;
ebrus 0:0a673c671a56 664
ebrus 0:0a673c671a56 665 /* Process Unlocked */
ebrus 0:0a673c671a56 666 __HAL_UNLOCK(hrtc);
ebrus 0:0a673c671a56 667
ebrus 0:0a673c671a56 668 return HAL_TIMEOUT;
ebrus 0:0a673c671a56 669 }
ebrus 0:0a673c671a56 670 }
ebrus 0:0a673c671a56 671
ebrus 0:0a673c671a56 672 /* Clear the Wakeup Timer clock source bits in CR register */
ebrus 0:0a673c671a56 673 hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;
ebrus 0:0a673c671a56 674
ebrus 0:0a673c671a56 675 /* Configure the clock source */
ebrus 0:0a673c671a56 676 hrtc->Instance->CR |= (uint32_t)WakeUpClock;
ebrus 0:0a673c671a56 677
ebrus 0:0a673c671a56 678 /* Configure the Wakeup Timer counter */
ebrus 0:0a673c671a56 679 hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;
ebrus 0:0a673c671a56 680
ebrus 0:0a673c671a56 681 /* Enable the Wakeup Timer */
ebrus 0:0a673c671a56 682 __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc);
ebrus 0:0a673c671a56 683
ebrus 0:0a673c671a56 684 /* Enable the write protection for RTC registers */
ebrus 0:0a673c671a56 685 __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
ebrus 0:0a673c671a56 686
ebrus 0:0a673c671a56 687 hrtc->State = HAL_RTC_STATE_READY;
ebrus 0:0a673c671a56 688
ebrus 0:0a673c671a56 689 /* Process Unlocked */
ebrus 0:0a673c671a56 690 __HAL_UNLOCK(hrtc);
ebrus 0:0a673c671a56 691
ebrus 0:0a673c671a56 692 return HAL_OK;
ebrus 0:0a673c671a56 693 }
ebrus 0:0a673c671a56 694
ebrus 0:0a673c671a56 695 /**
ebrus 0:0a673c671a56 696 * @brief Sets wake up timer with interrupt
ebrus 0:0a673c671a56 697 * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
ebrus 0:0a673c671a56 698 * the configuration information for RTC.
ebrus 0:0a673c671a56 699 * @param WakeUpCounter: Wake up counter
ebrus 0:0a673c671a56 700 * @param WakeUpClock: Wake up clock
ebrus 0:0a673c671a56 701 * @retval HAL status
ebrus 0:0a673c671a56 702 */
ebrus 0:0a673c671a56 703 HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
ebrus 0:0a673c671a56 704 {
ebrus 0:0a673c671a56 705 uint32_t tickstart;
ebrus 0:0a673c671a56 706
ebrus 0:0a673c671a56 707 /* Check the parameters */
ebrus 0:0a673c671a56 708 assert_param(IS_WAKEUP_CLOCK(WakeUpClock));
ebrus 0:0a673c671a56 709 assert_param(IS_WAKEUP_COUNTER(WakeUpCounter));
ebrus 0:0a673c671a56 710
ebrus 0:0a673c671a56 711 /* Process Locked */
ebrus 0:0a673c671a56 712 __HAL_LOCK(hrtc);
ebrus 0:0a673c671a56 713
ebrus 0:0a673c671a56 714 hrtc->State = HAL_RTC_STATE_BUSY;
ebrus 0:0a673c671a56 715
ebrus 0:0a673c671a56 716 /* Disable the write protection for RTC registers */
ebrus 0:0a673c671a56 717 __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
ebrus 0:0a673c671a56 718
ebrus 0:0a673c671a56 719 __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
ebrus 0:0a673c671a56 720
ebrus 0:0a673c671a56 721 tickstart = HAL_GetTick();
ebrus 0:0a673c671a56 722
ebrus 0:0a673c671a56 723 /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
ebrus 0:0a673c671a56 724 while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
ebrus 0:0a673c671a56 725 {
ebrus 0:0a673c671a56 726 if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
ebrus 0:0a673c671a56 727 {
ebrus 0:0a673c671a56 728 /* Enable the write protection for RTC registers */
ebrus 0:0a673c671a56 729 __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
ebrus 0:0a673c671a56 730
ebrus 0:0a673c671a56 731 hrtc->State = HAL_RTC_STATE_TIMEOUT;
ebrus 0:0a673c671a56 732
ebrus 0:0a673c671a56 733 /* Process Unlocked */
ebrus 0:0a673c671a56 734 __HAL_UNLOCK(hrtc);
ebrus 0:0a673c671a56 735
ebrus 0:0a673c671a56 736 return HAL_TIMEOUT;
ebrus 0:0a673c671a56 737 }
ebrus 0:0a673c671a56 738 }
ebrus 0:0a673c671a56 739
ebrus 0:0a673c671a56 740 /* Configure the Wakeup Timer counter */
ebrus 0:0a673c671a56 741 hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;
ebrus 0:0a673c671a56 742
ebrus 0:0a673c671a56 743 /* Clear the Wakeup Timer clock source bits in CR register */
ebrus 0:0a673c671a56 744 hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;
ebrus 0:0a673c671a56 745
ebrus 0:0a673c671a56 746 /* Configure the clock source */
ebrus 0:0a673c671a56 747 hrtc->Instance->CR |= (uint32_t)WakeUpClock;
ebrus 0:0a673c671a56 748
ebrus 0:0a673c671a56 749 /* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */
ebrus 0:0a673c671a56 750 __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_WAKEUPTIMER_EVENT);
ebrus 0:0a673c671a56 751
ebrus 0:0a673c671a56 752 EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT;
ebrus 0:0a673c671a56 753
ebrus 0:0a673c671a56 754 /* Configure the Interrupt in the RTC_CR register */
ebrus 0:0a673c671a56 755 __HAL_RTC_WAKEUPTIMER_ENABLE_IT(hrtc,RTC_IT_WUT);
ebrus 0:0a673c671a56 756
ebrus 0:0a673c671a56 757 /* Enable the Wakeup Timer */
ebrus 0:0a673c671a56 758 __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc);
ebrus 0:0a673c671a56 759
ebrus 0:0a673c671a56 760 /* Enable the write protection for RTC registers */
ebrus 0:0a673c671a56 761 __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
ebrus 0:0a673c671a56 762
ebrus 0:0a673c671a56 763 hrtc->State = HAL_RTC_STATE_READY;
ebrus 0:0a673c671a56 764
ebrus 0:0a673c671a56 765 /* Process Unlocked */
ebrus 0:0a673c671a56 766 __HAL_UNLOCK(hrtc);
ebrus 0:0a673c671a56 767
ebrus 0:0a673c671a56 768 return HAL_OK;
ebrus 0:0a673c671a56 769 }
ebrus 0:0a673c671a56 770
ebrus 0:0a673c671a56 771 /**
ebrus 0:0a673c671a56 772 * @brief Deactivates wake up timer counter.
ebrus 0:0a673c671a56 773 * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
ebrus 0:0a673c671a56 774 * the configuration information for RTC.
ebrus 0:0a673c671a56 775 * @retval HAL status
ebrus 0:0a673c671a56 776 */
ebrus 0:0a673c671a56 777 uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc)
ebrus 0:0a673c671a56 778 {
ebrus 0:0a673c671a56 779 uint32_t tickstart;
ebrus 0:0a673c671a56 780
ebrus 0:0a673c671a56 781 /* Process Locked */
ebrus 0:0a673c671a56 782 __HAL_LOCK(hrtc);
ebrus 0:0a673c671a56 783
ebrus 0:0a673c671a56 784 hrtc->State = HAL_RTC_STATE_BUSY;
ebrus 0:0a673c671a56 785
ebrus 0:0a673c671a56 786 /* Disable the write protection for RTC registers */
ebrus 0:0a673c671a56 787 __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
ebrus 0:0a673c671a56 788
ebrus 0:0a673c671a56 789 /* Disable the Wakeup Timer */
ebrus 0:0a673c671a56 790 __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
ebrus 0:0a673c671a56 791
ebrus 0:0a673c671a56 792 /* In case of interrupt mode is used, the interrupt source must disabled */
ebrus 0:0a673c671a56 793 __HAL_RTC_WAKEUPTIMER_DISABLE_IT(hrtc,RTC_IT_WUT);
ebrus 0:0a673c671a56 794
ebrus 0:0a673c671a56 795 tickstart = HAL_GetTick();
ebrus 0:0a673c671a56 796 /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
ebrus 0:0a673c671a56 797 while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
ebrus 0:0a673c671a56 798 {
ebrus 0:0a673c671a56 799 if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
ebrus 0:0a673c671a56 800 {
ebrus 0:0a673c671a56 801 /* Enable the write protection for RTC registers */
ebrus 0:0a673c671a56 802 __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
ebrus 0:0a673c671a56 803
ebrus 0:0a673c671a56 804 hrtc->State = HAL_RTC_STATE_TIMEOUT;
ebrus 0:0a673c671a56 805
ebrus 0:0a673c671a56 806 /* Process Unlocked */
ebrus 0:0a673c671a56 807 __HAL_UNLOCK(hrtc);
ebrus 0:0a673c671a56 808
ebrus 0:0a673c671a56 809 return HAL_TIMEOUT;
ebrus 0:0a673c671a56 810 }
ebrus 0:0a673c671a56 811 }
ebrus 0:0a673c671a56 812
ebrus 0:0a673c671a56 813 /* Enable the write protection for RTC registers */
ebrus 0:0a673c671a56 814 __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
ebrus 0:0a673c671a56 815
ebrus 0:0a673c671a56 816 hrtc->State = HAL_RTC_STATE_READY;
ebrus 0:0a673c671a56 817
ebrus 0:0a673c671a56 818 /* Process Unlocked */
ebrus 0:0a673c671a56 819 __HAL_UNLOCK(hrtc);
ebrus 0:0a673c671a56 820
ebrus 0:0a673c671a56 821 return HAL_OK;
ebrus 0:0a673c671a56 822 }
ebrus 0:0a673c671a56 823
ebrus 0:0a673c671a56 824 /**
ebrus 0:0a673c671a56 825 * @brief Gets wake up timer counter.
ebrus 0:0a673c671a56 826 * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
ebrus 0:0a673c671a56 827 * the configuration information for RTC.
ebrus 0:0a673c671a56 828 * @retval Counter value
ebrus 0:0a673c671a56 829 */
ebrus 0:0a673c671a56 830 uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc)
ebrus 0:0a673c671a56 831 {
ebrus 0:0a673c671a56 832 /* Get the counter value */
ebrus 0:0a673c671a56 833 return ((uint32_t)(hrtc->Instance->WUTR & RTC_WUTR_WUT));
ebrus 0:0a673c671a56 834 }
ebrus 0:0a673c671a56 835
ebrus 0:0a673c671a56 836 /**
ebrus 0:0a673c671a56 837 * @brief Writes a data in a specified RTC Backup data register.
ebrus 0:0a673c671a56 838 * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
ebrus 0:0a673c671a56 839 * the configuration information for RTC.
ebrus 0:0a673c671a56 840 * @param BackupRegister: RTC Backup data Register number.
ebrus 0:0a673c671a56 841 * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to
ebrus 0:0a673c671a56 842 * specify the register.
ebrus 0:0a673c671a56 843 * @param Data: Data to be written in the specified RTC Backup data register.
ebrus 0:0a673c671a56 844 * @retval None
ebrus 0:0a673c671a56 845 */
ebrus 0:0a673c671a56 846 void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)
ebrus 0:0a673c671a56 847 {
ebrus 0:0a673c671a56 848 uint32_t tmp = 0;
ebrus 0:0a673c671a56 849
ebrus 0:0a673c671a56 850 /* Check the parameters */
ebrus 0:0a673c671a56 851 assert_param(IS_RTC_BKP(BackupRegister));
ebrus 0:0a673c671a56 852
ebrus 0:0a673c671a56 853 tmp = (uint32_t)&(hrtc->Instance->BKP0R);
ebrus 0:0a673c671a56 854 tmp += (BackupRegister * 4);
ebrus 0:0a673c671a56 855
ebrus 0:0a673c671a56 856 /* Write the specified register */
ebrus 0:0a673c671a56 857 *(__IO uint32_t *)tmp = (uint32_t)Data;
ebrus 0:0a673c671a56 858 }
ebrus 0:0a673c671a56 859
ebrus 0:0a673c671a56 860 /**
ebrus 0:0a673c671a56 861 * @brief Reads data from the specified RTC Backup data Register.
ebrus 0:0a673c671a56 862 * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
ebrus 0:0a673c671a56 863 * the configuration information for RTC.
ebrus 0:0a673c671a56 864 * @param BackupRegister: RTC Backup data Register number.
ebrus 0:0a673c671a56 865 * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to
ebrus 0:0a673c671a56 866 * specify the register.
ebrus 0:0a673c671a56 867 * @retval Read value
ebrus 0:0a673c671a56 868 */
ebrus 0:0a673c671a56 869 uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
ebrus 0:0a673c671a56 870 {
ebrus 0:0a673c671a56 871 uint32_t tmp = 0;
ebrus 0:0a673c671a56 872
ebrus 0:0a673c671a56 873 /* Check the parameters */
ebrus 0:0a673c671a56 874 assert_param(IS_RTC_BKP(BackupRegister));
ebrus 0:0a673c671a56 875
ebrus 0:0a673c671a56 876 tmp = (uint32_t)&(hrtc->Instance->BKP0R);
ebrus 0:0a673c671a56 877 tmp += (BackupRegister * 4);
ebrus 0:0a673c671a56 878
ebrus 0:0a673c671a56 879 /* Read the specified register */
ebrus 0:0a673c671a56 880 return (*(__IO uint32_t *)tmp);
ebrus 0:0a673c671a56 881 }
ebrus 0:0a673c671a56 882
ebrus 0:0a673c671a56 883 /**
ebrus 0:0a673c671a56 884 * @brief Sets the Smooth calibration parameters.
ebrus 0:0a673c671a56 885 * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
ebrus 0:0a673c671a56 886 * the configuration information for RTC.
ebrus 0:0a673c671a56 887 * @param SmoothCalibPeriod: Select the Smooth Calibration Period.
ebrus 0:0a673c671a56 888 * This parameter can be can be one of the following values :
ebrus 0:0a673c671a56 889 * @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration periode is 32s.
ebrus 0:0a673c671a56 890 * @arg RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration periode is 16s.
ebrus 0:0a673c671a56 891 * @arg RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibartion periode is 8s.
ebrus 0:0a673c671a56 892 * @param SmoothCalibPlusPulses: Select to Set or reset the CALP bit.
ebrus 0:0a673c671a56 893 * This parameter can be one of the following values:
ebrus 0:0a673c671a56 894 * @arg RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK puls every 2*11 pulses.
ebrus 0:0a673c671a56 895 * @arg RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added.
ebrus 0:0a673c671a56 896 * @param SmouthCalibMinusPulsesValue: Select the value of CALM[8:0] bits.
ebrus 0:0a673c671a56 897 * This parameter can be one any value from 0 to 0x000001FF.
ebrus 0:0a673c671a56 898 * @note To deactivate the smooth calibration, the field SmoothCalibPlusPulses
ebrus 0:0a673c671a56 899 * must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field
ebrus 0:0a673c671a56 900 * SmouthCalibMinusPulsesValue mut be equal to 0.
ebrus 0:0a673c671a56 901 * @retval HAL status
ebrus 0:0a673c671a56 902 */
ebrus 0:0a673c671a56 903 HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue)
ebrus 0:0a673c671a56 904 {
ebrus 0:0a673c671a56 905 uint32_t tickstart;
ebrus 0:0a673c671a56 906
ebrus 0:0a673c671a56 907 /* Check the parameters */
ebrus 0:0a673c671a56 908 assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(SmoothCalibPeriod));
ebrus 0:0a673c671a56 909 assert_param(IS_RTC_SMOOTH_CALIB_PLUS(SmoothCalibPlusPulses));
ebrus 0:0a673c671a56 910 assert_param(IS_RTC_SMOOTH_CALIB_MINUS(SmouthCalibMinusPulsesValue));
ebrus 0:0a673c671a56 911
ebrus 0:0a673c671a56 912 /* Process Locked */
ebrus 0:0a673c671a56 913 __HAL_LOCK(hrtc);
ebrus 0:0a673c671a56 914
ebrus 0:0a673c671a56 915 hrtc->State = HAL_RTC_STATE_BUSY;
ebrus 0:0a673c671a56 916
ebrus 0:0a673c671a56 917 /* Disable the write protection for RTC registers */
ebrus 0:0a673c671a56 918 __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
ebrus 0:0a673c671a56 919
ebrus 0:0a673c671a56 920 /* check if a calibration is pending*/
ebrus 0:0a673c671a56 921 if((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET)
ebrus 0:0a673c671a56 922 {
ebrus 0:0a673c671a56 923 tickstart = HAL_GetTick();
ebrus 0:0a673c671a56 924
ebrus 0:0a673c671a56 925 /* check if a calibration is pending*/
ebrus 0:0a673c671a56 926 while((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET)
ebrus 0:0a673c671a56 927 {
ebrus 0:0a673c671a56 928 if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
ebrus 0:0a673c671a56 929 {
ebrus 0:0a673c671a56 930 /* Enable the write protection for RTC registers */
ebrus 0:0a673c671a56 931 __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
ebrus 0:0a673c671a56 932
ebrus 0:0a673c671a56 933 /* Change RTC state */
ebrus 0:0a673c671a56 934 hrtc->State = HAL_RTC_STATE_TIMEOUT;
ebrus 0:0a673c671a56 935
ebrus 0:0a673c671a56 936 /* Process Unlocked */
ebrus 0:0a673c671a56 937 __HAL_UNLOCK(hrtc);
ebrus 0:0a673c671a56 938
ebrus 0:0a673c671a56 939 return HAL_TIMEOUT;
ebrus 0:0a673c671a56 940 }
ebrus 0:0a673c671a56 941 }
ebrus 0:0a673c671a56 942 }
ebrus 0:0a673c671a56 943
ebrus 0:0a673c671a56 944 /* Configure the Smooth calibration settings */
ebrus 0:0a673c671a56 945 hrtc->Instance->CALR = (uint32_t)((uint32_t)SmoothCalibPeriod | (uint32_t)SmoothCalibPlusPulses | (uint32_t)SmouthCalibMinusPulsesValue);
ebrus 0:0a673c671a56 946
ebrus 0:0a673c671a56 947 /* Enable the write protection for RTC registers */
ebrus 0:0a673c671a56 948 __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
ebrus 0:0a673c671a56 949
ebrus 0:0a673c671a56 950 /* Change RTC state */
ebrus 0:0a673c671a56 951 hrtc->State = HAL_RTC_STATE_READY;
ebrus 0:0a673c671a56 952
ebrus 0:0a673c671a56 953 /* Process Unlocked */
ebrus 0:0a673c671a56 954 __HAL_UNLOCK(hrtc);
ebrus 0:0a673c671a56 955
ebrus 0:0a673c671a56 956 return HAL_OK;
ebrus 0:0a673c671a56 957 }
ebrus 0:0a673c671a56 958
ebrus 0:0a673c671a56 959 /**
ebrus 0:0a673c671a56 960 * @brief Configures the Synchronization Shift Control Settings.
ebrus 0:0a673c671a56 961 * @note When REFCKON is set, firmware must not write to Shift control register.
ebrus 0:0a673c671a56 962 * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
ebrus 0:0a673c671a56 963 * the configuration information for RTC.
ebrus 0:0a673c671a56 964 * @param ShiftAdd1S: Select to add or not 1 second to the time calendar.
ebrus 0:0a673c671a56 965 * This parameter can be one of the following values :
ebrus 0:0a673c671a56 966 * @arg RTC_SHIFTADD1S_SET: Add one second to the clock calendar.
ebrus 0:0a673c671a56 967 * @arg RTC_SHIFTADD1S_RESET: No effect.
ebrus 0:0a673c671a56 968 * @param ShiftSubFS: Select the number of Second Fractions to substitute.
ebrus 0:0a673c671a56 969 * This parameter can be one any value from 0 to 0x7FFF.
ebrus 0:0a673c671a56 970 * @retval HAL status
ebrus 0:0a673c671a56 971 */
ebrus 0:0a673c671a56 972 HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef* hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS)
ebrus 0:0a673c671a56 973 {
ebrus 0:0a673c671a56 974 uint32_t tickstart;
ebrus 0:0a673c671a56 975
ebrus 0:0a673c671a56 976 /* Check the parameters */
ebrus 0:0a673c671a56 977 assert_param(IS_RTC_SHIFT_ADD1S(ShiftAdd1S));
ebrus 0:0a673c671a56 978 assert_param(IS_RTC_SHIFT_SUBFS(ShiftSubFS));
ebrus 0:0a673c671a56 979
ebrus 0:0a673c671a56 980 /* Process Locked */
ebrus 0:0a673c671a56 981 __HAL_LOCK(hrtc);
ebrus 0:0a673c671a56 982
ebrus 0:0a673c671a56 983 hrtc->State = HAL_RTC_STATE_BUSY;
ebrus 0:0a673c671a56 984
ebrus 0:0a673c671a56 985 /* Disable the write protection for RTC registers */
ebrus 0:0a673c671a56 986 __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
ebrus 0:0a673c671a56 987
ebrus 0:0a673c671a56 988 tickstart = HAL_GetTick();
ebrus 0:0a673c671a56 989
ebrus 0:0a673c671a56 990 /* Wait until the shift is completed*/
ebrus 0:0a673c671a56 991 while((hrtc->Instance->ISR & RTC_ISR_SHPF) != RESET)
ebrus 0:0a673c671a56 992 {
ebrus 0:0a673c671a56 993 if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
ebrus 0:0a673c671a56 994 {
ebrus 0:0a673c671a56 995 /* Enable the write protection for RTC registers */
ebrus 0:0a673c671a56 996 __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
ebrus 0:0a673c671a56 997
ebrus 0:0a673c671a56 998 hrtc->State = HAL_RTC_STATE_TIMEOUT;
ebrus 0:0a673c671a56 999
ebrus 0:0a673c671a56 1000 /* Process Unlocked */
ebrus 0:0a673c671a56 1001 __HAL_UNLOCK(hrtc);
ebrus 0:0a673c671a56 1002
ebrus 0:0a673c671a56 1003 return HAL_TIMEOUT;
ebrus 0:0a673c671a56 1004 }
ebrus 0:0a673c671a56 1005 }
ebrus 0:0a673c671a56 1006
ebrus 0:0a673c671a56 1007 /* Check if the reference clock detection is disabled */
ebrus 0:0a673c671a56 1008 if((hrtc->Instance->CR & RTC_CR_REFCKON) == RESET)
ebrus 0:0a673c671a56 1009 {
ebrus 0:0a673c671a56 1010 /* Configure the Shift settings */
ebrus 0:0a673c671a56 1011 hrtc->Instance->SHIFTR = (uint32_t)(uint32_t)(ShiftSubFS) | (uint32_t)(ShiftAdd1S);
ebrus 0:0a673c671a56 1012
ebrus 0:0a673c671a56 1013 /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
ebrus 0:0a673c671a56 1014 if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
ebrus 0:0a673c671a56 1015 {
ebrus 0:0a673c671a56 1016 if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
ebrus 0:0a673c671a56 1017 {
ebrus 0:0a673c671a56 1018 /* Enable the write protection for RTC registers */
ebrus 0:0a673c671a56 1019 __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
ebrus 0:0a673c671a56 1020
ebrus 0:0a673c671a56 1021 hrtc->State = HAL_RTC_STATE_ERROR;
ebrus 0:0a673c671a56 1022
ebrus 0:0a673c671a56 1023 /* Process Unlocked */
ebrus 0:0a673c671a56 1024 __HAL_UNLOCK(hrtc);
ebrus 0:0a673c671a56 1025
ebrus 0:0a673c671a56 1026 return HAL_ERROR;
ebrus 0:0a673c671a56 1027 }
ebrus 0:0a673c671a56 1028 }
ebrus 0:0a673c671a56 1029 }
ebrus 0:0a673c671a56 1030 else
ebrus 0:0a673c671a56 1031 {
ebrus 0:0a673c671a56 1032 /* Enable the write protection for RTC registers */
ebrus 0:0a673c671a56 1033 __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
ebrus 0:0a673c671a56 1034
ebrus 0:0a673c671a56 1035 /* Change RTC state */
ebrus 0:0a673c671a56 1036 hrtc->State = HAL_RTC_STATE_ERROR;
ebrus 0:0a673c671a56 1037
ebrus 0:0a673c671a56 1038 /* Process Unlocked */
ebrus 0:0a673c671a56 1039 __HAL_UNLOCK(hrtc);
ebrus 0:0a673c671a56 1040
ebrus 0:0a673c671a56 1041 return HAL_ERROR;
ebrus 0:0a673c671a56 1042 }
ebrus 0:0a673c671a56 1043
ebrus 0:0a673c671a56 1044 /* Enable the write protection for RTC registers */
ebrus 0:0a673c671a56 1045 __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
ebrus 0:0a673c671a56 1046
ebrus 0:0a673c671a56 1047 /* Change RTC state */
ebrus 0:0a673c671a56 1048 hrtc->State = HAL_RTC_STATE_READY;
ebrus 0:0a673c671a56 1049
ebrus 0:0a673c671a56 1050 /* Process Unlocked */
ebrus 0:0a673c671a56 1051 __HAL_UNLOCK(hrtc);
ebrus 0:0a673c671a56 1052
ebrus 0:0a673c671a56 1053 return HAL_OK;
ebrus 0:0a673c671a56 1054 }
ebrus 0:0a673c671a56 1055
ebrus 0:0a673c671a56 1056 /**
ebrus 0:0a673c671a56 1057 * @brief Configures the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
ebrus 0:0a673c671a56 1058 * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
ebrus 0:0a673c671a56 1059 * the configuration information for RTC.
ebrus 0:0a673c671a56 1060 * @param CalibOutput : Select the Calibration output Selection .
ebrus 0:0a673c671a56 1061 * This parameter can be one of the following values:
ebrus 0:0a673c671a56 1062 * @arg RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz.
ebrus 0:0a673c671a56 1063 * @arg RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz.
ebrus 0:0a673c671a56 1064 * @retval HAL status
ebrus 0:0a673c671a56 1065 */
ebrus 0:0a673c671a56 1066 HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef* hrtc, uint32_t CalibOutput)
ebrus 0:0a673c671a56 1067 {
ebrus 0:0a673c671a56 1068 /* Check the parameters */
ebrus 0:0a673c671a56 1069 assert_param(IS_RTC_CALIB_OUTPUT(CalibOutput));
ebrus 0:0a673c671a56 1070
ebrus 0:0a673c671a56 1071 /* Process Locked */
ebrus 0:0a673c671a56 1072 __HAL_LOCK(hrtc);
ebrus 0:0a673c671a56 1073
ebrus 0:0a673c671a56 1074 hrtc->State = HAL_RTC_STATE_BUSY;
ebrus 0:0a673c671a56 1075
ebrus 0:0a673c671a56 1076 /* Disable the write protection for RTC registers */
ebrus 0:0a673c671a56 1077 __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
ebrus 0:0a673c671a56 1078
ebrus 0:0a673c671a56 1079 /* Clear flags before config */
ebrus 0:0a673c671a56 1080 hrtc->Instance->CR &= (uint32_t)~RTC_CR_COSEL;
ebrus 0:0a673c671a56 1081
ebrus 0:0a673c671a56 1082 /* Configure the RTC_CR register */
ebrus 0:0a673c671a56 1083 hrtc->Instance->CR |= (uint32_t)CalibOutput;
ebrus 0:0a673c671a56 1084
ebrus 0:0a673c671a56 1085 __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(hrtc);
ebrus 0:0a673c671a56 1086
ebrus 0:0a673c671a56 1087 /* Enable the write protection for RTC registers */
ebrus 0:0a673c671a56 1088 __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
ebrus 0:0a673c671a56 1089
ebrus 0:0a673c671a56 1090 /* Change RTC state */
ebrus 0:0a673c671a56 1091 hrtc->State = HAL_RTC_STATE_READY;
ebrus 0:0a673c671a56 1092
ebrus 0:0a673c671a56 1093 /* Process Unlocked */
ebrus 0:0a673c671a56 1094 __HAL_UNLOCK(hrtc);
ebrus 0:0a673c671a56 1095
ebrus 0:0a673c671a56 1096 return HAL_OK;
ebrus 0:0a673c671a56 1097 }
ebrus 0:0a673c671a56 1098
ebrus 0:0a673c671a56 1099 /**
ebrus 0:0a673c671a56 1100 * @brief Deactivates the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
ebrus 0:0a673c671a56 1101 * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
ebrus 0:0a673c671a56 1102 * the configuration information for RTC.
ebrus 0:0a673c671a56 1103 * @retval HAL status
ebrus 0:0a673c671a56 1104 */
ebrus 0:0a673c671a56 1105 HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef* hrtc)
ebrus 0:0a673c671a56 1106 {
ebrus 0:0a673c671a56 1107 /* Process Locked */
ebrus 0:0a673c671a56 1108 __HAL_LOCK(hrtc);
ebrus 0:0a673c671a56 1109
ebrus 0:0a673c671a56 1110 hrtc->State = HAL_RTC_STATE_BUSY;
ebrus 0:0a673c671a56 1111
ebrus 0:0a673c671a56 1112 /* Disable the write protection for RTC registers */
ebrus 0:0a673c671a56 1113 __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
ebrus 0:0a673c671a56 1114
ebrus 0:0a673c671a56 1115 __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(hrtc);
ebrus 0:0a673c671a56 1116
ebrus 0:0a673c671a56 1117 /* Enable the write protection for RTC registers */
ebrus 0:0a673c671a56 1118 __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
ebrus 0:0a673c671a56 1119
ebrus 0:0a673c671a56 1120 /* Change RTC state */
ebrus 0:0a673c671a56 1121 hrtc->State = HAL_RTC_STATE_READY;
ebrus 0:0a673c671a56 1122
ebrus 0:0a673c671a56 1123 /* Process Unlocked */
ebrus 0:0a673c671a56 1124 __HAL_UNLOCK(hrtc);
ebrus 0:0a673c671a56 1125
ebrus 0:0a673c671a56 1126 return HAL_OK;
ebrus 0:0a673c671a56 1127 }
ebrus 0:0a673c671a56 1128
ebrus 0:0a673c671a56 1129 /**
ebrus 0:0a673c671a56 1130 * @brief Enables the RTC reference clock detection.
ebrus 0:0a673c671a56 1131 * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
ebrus 0:0a673c671a56 1132 * the configuration information for RTC.
ebrus 0:0a673c671a56 1133 * @retval HAL status
ebrus 0:0a673c671a56 1134 */
ebrus 0:0a673c671a56 1135 HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef* hrtc)
ebrus 0:0a673c671a56 1136 {
ebrus 0:0a673c671a56 1137 /* Process Locked */
ebrus 0:0a673c671a56 1138 __HAL_LOCK(hrtc);
ebrus 0:0a673c671a56 1139
ebrus 0:0a673c671a56 1140 hrtc->State = HAL_RTC_STATE_BUSY;
ebrus 0:0a673c671a56 1141
ebrus 0:0a673c671a56 1142 /* Disable the write protection for RTC registers */
ebrus 0:0a673c671a56 1143 __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
ebrus 0:0a673c671a56 1144
ebrus 0:0a673c671a56 1145 /* Set Initialization mode */
ebrus 0:0a673c671a56 1146 if(RTC_EnterInitMode(hrtc) != HAL_OK)
ebrus 0:0a673c671a56 1147 {
ebrus 0:0a673c671a56 1148 /* Enable the write protection for RTC registers */
ebrus 0:0a673c671a56 1149 __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
ebrus 0:0a673c671a56 1150
ebrus 0:0a673c671a56 1151 /* Set RTC state*/
ebrus 0:0a673c671a56 1152 hrtc->State = HAL_RTC_STATE_ERROR;
ebrus 0:0a673c671a56 1153
ebrus 0:0a673c671a56 1154 /* Process Unlocked */
ebrus 0:0a673c671a56 1155 __HAL_UNLOCK(hrtc);
ebrus 0:0a673c671a56 1156
ebrus 0:0a673c671a56 1157 return HAL_ERROR;
ebrus 0:0a673c671a56 1158 }
ebrus 0:0a673c671a56 1159 else
ebrus 0:0a673c671a56 1160 {
ebrus 0:0a673c671a56 1161 __HAL_RTC_CLOCKREF_DETECTION_ENABLE(hrtc);
ebrus 0:0a673c671a56 1162
ebrus 0:0a673c671a56 1163 /* Exit Initialization mode */
ebrus 0:0a673c671a56 1164 hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
ebrus 0:0a673c671a56 1165 }
ebrus 0:0a673c671a56 1166
ebrus 0:0a673c671a56 1167 /* Enable the write protection for RTC registers */
ebrus 0:0a673c671a56 1168 __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
ebrus 0:0a673c671a56 1169
ebrus 0:0a673c671a56 1170 /* Change RTC state */
ebrus 0:0a673c671a56 1171 hrtc->State = HAL_RTC_STATE_READY;
ebrus 0:0a673c671a56 1172
ebrus 0:0a673c671a56 1173 /* Process Unlocked */
ebrus 0:0a673c671a56 1174 __HAL_UNLOCK(hrtc);
ebrus 0:0a673c671a56 1175
ebrus 0:0a673c671a56 1176 return HAL_OK;
ebrus 0:0a673c671a56 1177 }
ebrus 0:0a673c671a56 1178
ebrus 0:0a673c671a56 1179 /**
ebrus 0:0a673c671a56 1180 * @brief Disable the RTC reference clock detection.
ebrus 0:0a673c671a56 1181 * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
ebrus 0:0a673c671a56 1182 * the configuration information for RTC.
ebrus 0:0a673c671a56 1183 * @retval HAL status
ebrus 0:0a673c671a56 1184 */
ebrus 0:0a673c671a56 1185 HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef* hrtc)
ebrus 0:0a673c671a56 1186 {
ebrus 0:0a673c671a56 1187 /* Process Locked */
ebrus 0:0a673c671a56 1188 __HAL_LOCK(hrtc);
ebrus 0:0a673c671a56 1189
ebrus 0:0a673c671a56 1190 hrtc->State = HAL_RTC_STATE_BUSY;
ebrus 0:0a673c671a56 1191
ebrus 0:0a673c671a56 1192 /* Disable the write protection for RTC registers */
ebrus 0:0a673c671a56 1193 __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
ebrus 0:0a673c671a56 1194
ebrus 0:0a673c671a56 1195 /* Set Initialization mode */
ebrus 0:0a673c671a56 1196 if(RTC_EnterInitMode(hrtc) != HAL_OK)
ebrus 0:0a673c671a56 1197 {
ebrus 0:0a673c671a56 1198 /* Enable the write protection for RTC registers */
ebrus 0:0a673c671a56 1199 __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
ebrus 0:0a673c671a56 1200
ebrus 0:0a673c671a56 1201 /* Set RTC state*/
ebrus 0:0a673c671a56 1202 hrtc->State = HAL_RTC_STATE_ERROR;
ebrus 0:0a673c671a56 1203
ebrus 0:0a673c671a56 1204 /* Process Unlocked */
ebrus 0:0a673c671a56 1205 __HAL_UNLOCK(hrtc);
ebrus 0:0a673c671a56 1206
ebrus 0:0a673c671a56 1207 return HAL_ERROR;
ebrus 0:0a673c671a56 1208 }
ebrus 0:0a673c671a56 1209 else
ebrus 0:0a673c671a56 1210 {
ebrus 0:0a673c671a56 1211 __HAL_RTC_CLOCKREF_DETECTION_DISABLE(hrtc);
ebrus 0:0a673c671a56 1212
ebrus 0:0a673c671a56 1213 /* Exit Initialization mode */
ebrus 0:0a673c671a56 1214 hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
ebrus 0:0a673c671a56 1215 }
ebrus 0:0a673c671a56 1216
ebrus 0:0a673c671a56 1217 /* Enable the write protection for RTC registers */
ebrus 0:0a673c671a56 1218 __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
ebrus 0:0a673c671a56 1219
ebrus 0:0a673c671a56 1220 /* Change RTC state */
ebrus 0:0a673c671a56 1221 hrtc->State = HAL_RTC_STATE_READY;
ebrus 0:0a673c671a56 1222
ebrus 0:0a673c671a56 1223 /* Process Unlocked */
ebrus 0:0a673c671a56 1224 __HAL_UNLOCK(hrtc);
ebrus 0:0a673c671a56 1225
ebrus 0:0a673c671a56 1226 return HAL_OK;
ebrus 0:0a673c671a56 1227 }
ebrus 0:0a673c671a56 1228
ebrus 0:0a673c671a56 1229 /**
ebrus 0:0a673c671a56 1230 * @brief Enables the Bypass Shadow feature.
ebrus 0:0a673c671a56 1231 * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
ebrus 0:0a673c671a56 1232 * the configuration information for RTC.
ebrus 0:0a673c671a56 1233 * @note When the Bypass Shadow is enabled the calendar value are taken
ebrus 0:0a673c671a56 1234 * directly from the Calendar counter.
ebrus 0:0a673c671a56 1235 * @retval HAL status
ebrus 0:0a673c671a56 1236 */
ebrus 0:0a673c671a56 1237 HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef* hrtc)
ebrus 0:0a673c671a56 1238 {
ebrus 0:0a673c671a56 1239 /* Process Locked */
ebrus 0:0a673c671a56 1240 __HAL_LOCK(hrtc);
ebrus 0:0a673c671a56 1241
ebrus 0:0a673c671a56 1242 hrtc->State = HAL_RTC_STATE_BUSY;
ebrus 0:0a673c671a56 1243
ebrus 0:0a673c671a56 1244 /* Disable the write protection for RTC registers */
ebrus 0:0a673c671a56 1245 __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
ebrus 0:0a673c671a56 1246
ebrus 0:0a673c671a56 1247 /* Set the BYPSHAD bit */
ebrus 0:0a673c671a56 1248 hrtc->Instance->CR |= (uint8_t)RTC_CR_BYPSHAD;
ebrus 0:0a673c671a56 1249
ebrus 0:0a673c671a56 1250 /* Enable the write protection for RTC registers */
ebrus 0:0a673c671a56 1251 __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
ebrus 0:0a673c671a56 1252
ebrus 0:0a673c671a56 1253 /* Change RTC state */
ebrus 0:0a673c671a56 1254 hrtc->State = HAL_RTC_STATE_READY;
ebrus 0:0a673c671a56 1255
ebrus 0:0a673c671a56 1256 /* Process Unlocked */
ebrus 0:0a673c671a56 1257 __HAL_UNLOCK(hrtc);
ebrus 0:0a673c671a56 1258
ebrus 0:0a673c671a56 1259 return HAL_OK;
ebrus 0:0a673c671a56 1260 }
ebrus 0:0a673c671a56 1261
ebrus 0:0a673c671a56 1262 /**
ebrus 0:0a673c671a56 1263 * @brief Disables the Bypass Shadow feature.
ebrus 0:0a673c671a56 1264 * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
ebrus 0:0a673c671a56 1265 * the configuration information for RTC.
ebrus 0:0a673c671a56 1266 * @note When the Bypass Shadow is enabled the calendar value are taken
ebrus 0:0a673c671a56 1267 * directly from the Calendar counter.
ebrus 0:0a673c671a56 1268 * @retval HAL status
ebrus 0:0a673c671a56 1269 */
ebrus 0:0a673c671a56 1270 HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef* hrtc)
ebrus 0:0a673c671a56 1271 {
ebrus 0:0a673c671a56 1272 /* Process Locked */
ebrus 0:0a673c671a56 1273 __HAL_LOCK(hrtc);
ebrus 0:0a673c671a56 1274
ebrus 0:0a673c671a56 1275 hrtc->State = HAL_RTC_STATE_BUSY;
ebrus 0:0a673c671a56 1276
ebrus 0:0a673c671a56 1277 /* Disable the write protection for RTC registers */
ebrus 0:0a673c671a56 1278 __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
ebrus 0:0a673c671a56 1279
ebrus 0:0a673c671a56 1280 /* Reset the BYPSHAD bit */
ebrus 0:0a673c671a56 1281 hrtc->Instance->CR &= (uint8_t)~RTC_CR_BYPSHAD;
ebrus 0:0a673c671a56 1282
ebrus 0:0a673c671a56 1283 /* Enable the write protection for RTC registers */
ebrus 0:0a673c671a56 1284 __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
ebrus 0:0a673c671a56 1285
ebrus 0:0a673c671a56 1286 /* Change RTC state */
ebrus 0:0a673c671a56 1287 hrtc->State = HAL_RTC_STATE_READY;
ebrus 0:0a673c671a56 1288
ebrus 0:0a673c671a56 1289 /* Process Unlocked */
ebrus 0:0a673c671a56 1290 __HAL_UNLOCK(hrtc);
ebrus 0:0a673c671a56 1291
ebrus 0:0a673c671a56 1292 return HAL_OK;
ebrus 0:0a673c671a56 1293 }
ebrus 0:0a673c671a56 1294
ebrus 0:0a673c671a56 1295 /**
ebrus 0:0a673c671a56 1296 * @brief This function handles TimeStamp interrupt request.
ebrus 0:0a673c671a56 1297 * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
ebrus 0:0a673c671a56 1298 * the configuration information for RTC.
ebrus 0:0a673c671a56 1299 * @retval None
ebrus 0:0a673c671a56 1300 */
ebrus 0:0a673c671a56 1301 void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
ebrus 0:0a673c671a56 1302 {
ebrus 0:0a673c671a56 1303 if(__HAL_RTC_TIMESTAMP_GET_IT(hrtc, RTC_IT_TS))
ebrus 0:0a673c671a56 1304 {
ebrus 0:0a673c671a56 1305 /* Get the status of the Interrupt */
ebrus 0:0a673c671a56 1306 if((uint32_t)(hrtc->Instance->CR & RTC_IT_TS) != (uint32_t)RESET)
ebrus 0:0a673c671a56 1307 {
ebrus 0:0a673c671a56 1308 /* TIMESTAMP callback */
ebrus 0:0a673c671a56 1309 HAL_RTCEx_TimeStampEventCallback(hrtc);
ebrus 0:0a673c671a56 1310
ebrus 0:0a673c671a56 1311 /* Clear the TIMESTAMP interrupt pending bit */
ebrus 0:0a673c671a56 1312 __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc,RTC_FLAG_TSF);
ebrus 0:0a673c671a56 1313 }
ebrus 0:0a673c671a56 1314 }
ebrus 0:0a673c671a56 1315
ebrus 0:0a673c671a56 1316 /* Get the status of the Interrupt */
ebrus 0:0a673c671a56 1317 if(__HAL_RTC_TAMPER_GET_IT(hrtc,RTC_IT_TAMP1))
ebrus 0:0a673c671a56 1318 {
ebrus 0:0a673c671a56 1319 /* Get the TAMPER Interrupt enable bit and pending bit */
ebrus 0:0a673c671a56 1320 if(((hrtc->Instance->TAMPCR & (RTC_TAMPCR_TAMPIE))) != (uint32_t)RESET)
ebrus 0:0a673c671a56 1321 {
ebrus 0:0a673c671a56 1322 /* Tamper callback */
ebrus 0:0a673c671a56 1323 HAL_RTCEx_Tamper1EventCallback(hrtc);
ebrus 0:0a673c671a56 1324
ebrus 0:0a673c671a56 1325 /* Clear the Tamper interrupt pending bit */
ebrus 0:0a673c671a56 1326 __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP1F);
ebrus 0:0a673c671a56 1327 }
ebrus 0:0a673c671a56 1328 }
ebrus 0:0a673c671a56 1329
ebrus 0:0a673c671a56 1330 /* Get the status of the Interrupt */
ebrus 0:0a673c671a56 1331 if(__HAL_RTC_TAMPER_GET_IT(hrtc, RTC_IT_TAMP2))
ebrus 0:0a673c671a56 1332 {
ebrus 0:0a673c671a56 1333 /* Get the TAMPER Interrupt enable bit and pending bit */
ebrus 0:0a673c671a56 1334 if(((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMPIE)) != (uint32_t)RESET)
ebrus 0:0a673c671a56 1335 {
ebrus 0:0a673c671a56 1336 /* Tamper callback */
ebrus 0:0a673c671a56 1337 HAL_RTCEx_Tamper2EventCallback(hrtc);
ebrus 0:0a673c671a56 1338
ebrus 0:0a673c671a56 1339 /* Clear the Tamper interrupt pending bit */
ebrus 0:0a673c671a56 1340 __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F);
ebrus 0:0a673c671a56 1341 }
ebrus 0:0a673c671a56 1342 }
ebrus 0:0a673c671a56 1343 /* Clear the EXTI's Flag for RTC TimeStamp and Tamper */
ebrus 0:0a673c671a56 1344 __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT);
ebrus 0:0a673c671a56 1345
ebrus 0:0a673c671a56 1346 /* Change RTC state */
ebrus 0:0a673c671a56 1347 hrtc->State = HAL_RTC_STATE_READY;
ebrus 0:0a673c671a56 1348 }
ebrus 0:0a673c671a56 1349
ebrus 0:0a673c671a56 1350 /**
ebrus 0:0a673c671a56 1351 * @brief This function handles Wake Up Timer interrupt request.
ebrus 0:0a673c671a56 1352 * @param hrtc: RTC handle
ebrus 0:0a673c671a56 1353 * @retval None
ebrus 0:0a673c671a56 1354 */
ebrus 0:0a673c671a56 1355 void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc)
ebrus 0:0a673c671a56 1356 {
ebrus 0:0a673c671a56 1357 if(__HAL_RTC_WAKEUPTIMER_GET_IT(hrtc, RTC_IT_WUT))
ebrus 0:0a673c671a56 1358 {
ebrus 0:0a673c671a56 1359 /* Get the status of the Interrupt */
ebrus 0:0a673c671a56 1360 if((uint32_t)(hrtc->Instance->CR & RTC_IT_WUT) != (uint32_t)RESET)
ebrus 0:0a673c671a56 1361 {
ebrus 0:0a673c671a56 1362 /* WAKEUPTIMER callback */
ebrus 0:0a673c671a56 1363 HAL_RTCEx_WakeUpTimerEventCallback(hrtc);
ebrus 0:0a673c671a56 1364
ebrus 0:0a673c671a56 1365 /* Clear the WAKEUPTIMER interrupt pending bit */
ebrus 0:0a673c671a56 1366 __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
ebrus 0:0a673c671a56 1367 }
ebrus 0:0a673c671a56 1368 }
ebrus 0:0a673c671a56 1369
ebrus 0:0a673c671a56 1370 /* Clear the EXTI's line Flag for RTC WakeUpTimer */
ebrus 0:0a673c671a56 1371 __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_WAKEUPTIMER_EVENT);
ebrus 0:0a673c671a56 1372
ebrus 0:0a673c671a56 1373 /* Change RTC state */
ebrus 0:0a673c671a56 1374 hrtc->State = HAL_RTC_STATE_READY;
ebrus 0:0a673c671a56 1375 }
ebrus 0:0a673c671a56 1376
ebrus 0:0a673c671a56 1377 /**
ebrus 0:0a673c671a56 1378 * @brief Alarm B callback.
ebrus 0:0a673c671a56 1379 * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
ebrus 0:0a673c671a56 1380 * the configuration information for RTC.
ebrus 0:0a673c671a56 1381 * @retval None
ebrus 0:0a673c671a56 1382 */
ebrus 0:0a673c671a56 1383 __weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc)
ebrus 0:0a673c671a56 1384 {
ebrus 0:0a673c671a56 1385 /* NOTE : This function Should not be modified, when the callback is needed,
ebrus 0:0a673c671a56 1386 the HAL_RTC_AlarmBEventCallback could be implemented in the user file
ebrus 0:0a673c671a56 1387 */
ebrus 0:0a673c671a56 1388 }
ebrus 0:0a673c671a56 1389
ebrus 0:0a673c671a56 1390 /**
ebrus 0:0a673c671a56 1391 * @brief TimeStamp callback.
ebrus 0:0a673c671a56 1392 * @param hrtc: RTC handle
ebrus 0:0a673c671a56 1393 * @retval None
ebrus 0:0a673c671a56 1394 */
ebrus 0:0a673c671a56 1395 __weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc)
ebrus 0:0a673c671a56 1396 {
ebrus 0:0a673c671a56 1397 /* NOTE : This function Should not be modified, when the callback is needed,
ebrus 0:0a673c671a56 1398 the HAL_RTC_TimeStampEventCallback could be implemented in the user file
ebrus 0:0a673c671a56 1399 */
ebrus 0:0a673c671a56 1400 }
ebrus 0:0a673c671a56 1401
ebrus 0:0a673c671a56 1402 /**
ebrus 0:0a673c671a56 1403 * @brief Tamper 1 callback.
ebrus 0:0a673c671a56 1404 * @param hrtc: RTC handle
ebrus 0:0a673c671a56 1405 * @retval None
ebrus 0:0a673c671a56 1406 */
ebrus 0:0a673c671a56 1407 __weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc)
ebrus 0:0a673c671a56 1408 {
ebrus 0:0a673c671a56 1409 /* NOTE : This function Should not be modified, when the callback is needed,
ebrus 0:0a673c671a56 1410 the HAL_RTC_Tamper1EventCallback could be implemented in the user file
ebrus 0:0a673c671a56 1411 */
ebrus 0:0a673c671a56 1412 }
ebrus 0:0a673c671a56 1413
ebrus 0:0a673c671a56 1414 /**
ebrus 0:0a673c671a56 1415 * @brief Tamper 2 callback.
ebrus 0:0a673c671a56 1416 * @param hrtc: RTC handle
ebrus 0:0a673c671a56 1417 * @retval None
ebrus 0:0a673c671a56 1418 */
ebrus 0:0a673c671a56 1419 __weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc)
ebrus 0:0a673c671a56 1420 {
ebrus 0:0a673c671a56 1421 /* NOTE : This function Should not be modified, when the callback is needed,
ebrus 0:0a673c671a56 1422 the HAL_RTC_Tamper2EventCallback could be implemented in the user file
ebrus 0:0a673c671a56 1423 */
ebrus 0:0a673c671a56 1424 }
ebrus 0:0a673c671a56 1425
ebrus 0:0a673c671a56 1426 /**
ebrus 0:0a673c671a56 1427 * @brief Wake Up Timer callback.
ebrus 0:0a673c671a56 1428 * @param hrtc: RTC handle
ebrus 0:0a673c671a56 1429 * @retval None
ebrus 0:0a673c671a56 1430 */
ebrus 0:0a673c671a56 1431 __weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc)
ebrus 0:0a673c671a56 1432 {
ebrus 0:0a673c671a56 1433 /* NOTE : This function Should not be modified, when the callback is needed,
ebrus 0:0a673c671a56 1434 the HAL_RTC_WakeUpTimerEventCallback could be implemented in the user file
ebrus 0:0a673c671a56 1435 */
ebrus 0:0a673c671a56 1436 }
ebrus 0:0a673c671a56 1437
ebrus 0:0a673c671a56 1438 /**
ebrus 0:0a673c671a56 1439 * @brief This function handles AlarmB Polling request.
ebrus 0:0a673c671a56 1440 * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
ebrus 0:0a673c671a56 1441 * the configuration information for RTC.
ebrus 0:0a673c671a56 1442 * @param Timeout: Timeout duration
ebrus 0:0a673c671a56 1443 * @retval HAL status
ebrus 0:0a673c671a56 1444 */
ebrus 0:0a673c671a56 1445 HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
ebrus 0:0a673c671a56 1446 {
ebrus 0:0a673c671a56 1447 uint32_t tickstart;
ebrus 0:0a673c671a56 1448
ebrus 0:0a673c671a56 1449 /* Get Timeout value */
ebrus 0:0a673c671a56 1450 tickstart = HAL_GetTick();
ebrus 0:0a673c671a56 1451
ebrus 0:0a673c671a56 1452 while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) == RESET)
ebrus 0:0a673c671a56 1453 {
ebrus 0:0a673c671a56 1454 if(Timeout != HAL_MAX_DELAY)
ebrus 0:0a673c671a56 1455 {
ebrus 0:0a673c671a56 1456 if((int32_t) (HAL_GetTick() - tickstart ) >= Timeout)
ebrus 0:0a673c671a56 1457 {
ebrus 0:0a673c671a56 1458 hrtc->State = HAL_RTC_STATE_TIMEOUT;
ebrus 0:0a673c671a56 1459 return HAL_TIMEOUT;
ebrus 0:0a673c671a56 1460 }
ebrus 0:0a673c671a56 1461 }
ebrus 0:0a673c671a56 1462 }
ebrus 0:0a673c671a56 1463
ebrus 0:0a673c671a56 1464 /* Clear the Alarm Flag */
ebrus 0:0a673c671a56 1465 __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
ebrus 0:0a673c671a56 1466
ebrus 0:0a673c671a56 1467 /* Change RTC state */
ebrus 0:0a673c671a56 1468 hrtc->State = HAL_RTC_STATE_READY;
ebrus 0:0a673c671a56 1469
ebrus 0:0a673c671a56 1470 return HAL_OK;
ebrus 0:0a673c671a56 1471 }
ebrus 0:0a673c671a56 1472
ebrus 0:0a673c671a56 1473 /**
ebrus 0:0a673c671a56 1474 * @brief This function handles TimeStamp polling request.
ebrus 0:0a673c671a56 1475 * @param hrtc: RTC handle
ebrus 0:0a673c671a56 1476 * @param Timeout: Timeout duration
ebrus 0:0a673c671a56 1477 * @retval HAL status
ebrus 0:0a673c671a56 1478 */
ebrus 0:0a673c671a56 1479 HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
ebrus 0:0a673c671a56 1480 {
ebrus 0:0a673c671a56 1481 uint32_t tickstart;
ebrus 0:0a673c671a56 1482
ebrus 0:0a673c671a56 1483 /* Get Timeout value */
ebrus 0:0a673c671a56 1484 tickstart = HAL_GetTick();
ebrus 0:0a673c671a56 1485
ebrus 0:0a673c671a56 1486 while(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) == RESET)
ebrus 0:0a673c671a56 1487 {
ebrus 0:0a673c671a56 1488 if(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSOVF) != RESET)
ebrus 0:0a673c671a56 1489 {
ebrus 0:0a673c671a56 1490 /* Clear the TIMESTAMP OverRun Flag */
ebrus 0:0a673c671a56 1491 __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSOVF);
ebrus 0:0a673c671a56 1492
ebrus 0:0a673c671a56 1493 /* Change TIMESTAMP state */
ebrus 0:0a673c671a56 1494 hrtc->State = HAL_RTC_STATE_ERROR;
ebrus 0:0a673c671a56 1495
ebrus 0:0a673c671a56 1496 return HAL_ERROR;
ebrus 0:0a673c671a56 1497 }
ebrus 0:0a673c671a56 1498
ebrus 0:0a673c671a56 1499 if(Timeout != HAL_MAX_DELAY)
ebrus 0:0a673c671a56 1500 {
ebrus 0:0a673c671a56 1501 if((HAL_GetTick() - tickstart ) > Timeout)
ebrus 0:0a673c671a56 1502 {
ebrus 0:0a673c671a56 1503 hrtc->State = HAL_RTC_STATE_TIMEOUT;
ebrus 0:0a673c671a56 1504 return HAL_TIMEOUT;
ebrus 0:0a673c671a56 1505 }
ebrus 0:0a673c671a56 1506 }
ebrus 0:0a673c671a56 1507 }
ebrus 0:0a673c671a56 1508
ebrus 0:0a673c671a56 1509 /* Change RTC state */
ebrus 0:0a673c671a56 1510 hrtc->State = HAL_RTC_STATE_READY;
ebrus 0:0a673c671a56 1511
ebrus 0:0a673c671a56 1512 return HAL_OK;
ebrus 0:0a673c671a56 1513 }
ebrus 0:0a673c671a56 1514
ebrus 0:0a673c671a56 1515 /**
ebrus 0:0a673c671a56 1516 * @brief This function handles Tamper1 Polling.
ebrus 0:0a673c671a56 1517 * @param hrtc: RTC handle
ebrus 0:0a673c671a56 1518 * @param Timeout: Timeout duration
ebrus 0:0a673c671a56 1519 * @retval HAL status
ebrus 0:0a673c671a56 1520 */
ebrus 0:0a673c671a56 1521 HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
ebrus 0:0a673c671a56 1522 {
ebrus 0:0a673c671a56 1523 uint32_t tickstart;
ebrus 0:0a673c671a56 1524
ebrus 0:0a673c671a56 1525 /* Get Timeout value */
ebrus 0:0a673c671a56 1526 tickstart = HAL_GetTick();
ebrus 0:0a673c671a56 1527
ebrus 0:0a673c671a56 1528 /* Get the status of the Interrupt */
ebrus 0:0a673c671a56 1529 while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F)== RESET)
ebrus 0:0a673c671a56 1530 {
ebrus 0:0a673c671a56 1531 if(Timeout != HAL_MAX_DELAY)
ebrus 0:0a673c671a56 1532 {
ebrus 0:0a673c671a56 1533 if((HAL_GetTick() - tickstart ) > Timeout)
ebrus 0:0a673c671a56 1534 {
ebrus 0:0a673c671a56 1535 hrtc->State = HAL_RTC_STATE_TIMEOUT;
ebrus 0:0a673c671a56 1536 return HAL_TIMEOUT;
ebrus 0:0a673c671a56 1537 }
ebrus 0:0a673c671a56 1538 }
ebrus 0:0a673c671a56 1539 }
ebrus 0:0a673c671a56 1540
ebrus 0:0a673c671a56 1541 /* Clear the Tamper Flag */
ebrus 0:0a673c671a56 1542 __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP1F);
ebrus 0:0a673c671a56 1543
ebrus 0:0a673c671a56 1544 /* Change RTC state */
ebrus 0:0a673c671a56 1545 hrtc->State = HAL_RTC_STATE_READY;
ebrus 0:0a673c671a56 1546
ebrus 0:0a673c671a56 1547 return HAL_OK;
ebrus 0:0a673c671a56 1548 }
ebrus 0:0a673c671a56 1549
ebrus 0:0a673c671a56 1550 /**
ebrus 0:0a673c671a56 1551 * @brief This function handles Tamper2 Polling.
ebrus 0:0a673c671a56 1552 * @param hrtc: RTC handle
ebrus 0:0a673c671a56 1553 * @param Timeout: Timeout duration
ebrus 0:0a673c671a56 1554 * @retval HAL status
ebrus 0:0a673c671a56 1555 */
ebrus 0:0a673c671a56 1556 HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
ebrus 0:0a673c671a56 1557 {
ebrus 0:0a673c671a56 1558 uint32_t tickstart;
ebrus 0:0a673c671a56 1559
ebrus 0:0a673c671a56 1560 /* Get Timeout value */
ebrus 0:0a673c671a56 1561 tickstart = HAL_GetTick();
ebrus 0:0a673c671a56 1562
ebrus 0:0a673c671a56 1563 /* Get the status of the Interrupt */
ebrus 0:0a673c671a56 1564 while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) == RESET)
ebrus 0:0a673c671a56 1565 {
ebrus 0:0a673c671a56 1566 if(Timeout != HAL_MAX_DELAY)
ebrus 0:0a673c671a56 1567 {
ebrus 0:0a673c671a56 1568 if((HAL_GetTick() - tickstart ) > Timeout)
ebrus 0:0a673c671a56 1569 {
ebrus 0:0a673c671a56 1570 hrtc->State = HAL_RTC_STATE_TIMEOUT;
ebrus 0:0a673c671a56 1571 return HAL_TIMEOUT;
ebrus 0:0a673c671a56 1572 }
ebrus 0:0a673c671a56 1573 }
ebrus 0:0a673c671a56 1574 }
ebrus 0:0a673c671a56 1575
ebrus 0:0a673c671a56 1576 /* Clear the Tamper Flag */
ebrus 0:0a673c671a56 1577 __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP2F);
ebrus 0:0a673c671a56 1578
ebrus 0:0a673c671a56 1579 /* Change RTC state */
ebrus 0:0a673c671a56 1580 hrtc->State = HAL_RTC_STATE_READY;
ebrus 0:0a673c671a56 1581
ebrus 0:0a673c671a56 1582 return HAL_OK;
ebrus 0:0a673c671a56 1583 }
ebrus 0:0a673c671a56 1584
ebrus 0:0a673c671a56 1585
ebrus 0:0a673c671a56 1586 /**
ebrus 0:0a673c671a56 1587 * @brief This function handles Wake Up Timer Polling.
ebrus 0:0a673c671a56 1588 * @param hrtc: RTC handle
ebrus 0:0a673c671a56 1589 * @param Timeout: Timeout duration
ebrus 0:0a673c671a56 1590 * @retval HAL status
ebrus 0:0a673c671a56 1591 */
ebrus 0:0a673c671a56 1592 HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
ebrus 0:0a673c671a56 1593 {
ebrus 0:0a673c671a56 1594 uint32_t tickstart;
ebrus 0:0a673c671a56 1595
ebrus 0:0a673c671a56 1596 /* Get Timeout value */
ebrus 0:0a673c671a56 1597 tickstart = HAL_GetTick();
ebrus 0:0a673c671a56 1598
ebrus 0:0a673c671a56 1599 while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) == RESET)
ebrus 0:0a673c671a56 1600 {
ebrus 0:0a673c671a56 1601 if(Timeout != HAL_MAX_DELAY)
ebrus 0:0a673c671a56 1602 {
ebrus 0:0a673c671a56 1603 if((HAL_GetTick() - tickstart ) > Timeout)
ebrus 0:0a673c671a56 1604 {
ebrus 0:0a673c671a56 1605 hrtc->State = HAL_RTC_STATE_TIMEOUT;
ebrus 0:0a673c671a56 1606
ebrus 0:0a673c671a56 1607 return HAL_TIMEOUT;
ebrus 0:0a673c671a56 1608 }
ebrus 0:0a673c671a56 1609 }
ebrus 0:0a673c671a56 1610 }
ebrus 0:0a673c671a56 1611
ebrus 0:0a673c671a56 1612 /* Clear the WAKEUPTIMER Flag */
ebrus 0:0a673c671a56 1613 __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
ebrus 0:0a673c671a56 1614
ebrus 0:0a673c671a56 1615 /* Change RTC state */
ebrus 0:0a673c671a56 1616 hrtc->State = HAL_RTC_STATE_READY;
ebrus 0:0a673c671a56 1617
ebrus 0:0a673c671a56 1618 return HAL_OK;
ebrus 0:0a673c671a56 1619 }
ebrus 0:0a673c671a56 1620
ebrus 0:0a673c671a56 1621 /**
ebrus 0:0a673c671a56 1622 * @}
ebrus 0:0a673c671a56 1623 */
ebrus 0:0a673c671a56 1624
ebrus 0:0a673c671a56 1625 /**
ebrus 0:0a673c671a56 1626 * @}
ebrus 0:0a673c671a56 1627 */
ebrus 0:0a673c671a56 1628
ebrus 0:0a673c671a56 1629 #endif /* HAL_RTC_MODULE_ENABLED */
ebrus 0:0a673c671a56 1630 /**
ebrus 0:0a673c671a56 1631 * @}
ebrus 0:0a673c671a56 1632 */
ebrus 0:0a673c671a56 1633
ebrus 0:0a673c671a56 1634 /**
ebrus 0:0a673c671a56 1635 * @}
ebrus 0:0a673c671a56 1636 */
ebrus 0:0a673c671a56 1637
ebrus 0:0a673c671a56 1638 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/