Emil Johnsen / mbed-src-STM32F030K6

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targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/stm32l0xx_hal_crc.h@0:0a673c671a56, 2016-07-27 (annotated)

Committer:
ebrus
Date:
Wed Jul 27 18:35:32 2016 +0000
Revision:
0:0a673c671a56
4

Who changed what in which revision?

UserRevisionLine numberNew contents of line
ebrus 0:0a673c671a56 1 /**
ebrus 0:0a673c671a56 2 ******************************************************************************
ebrus 0:0a673c671a56 3 * @file stm32l0xx_hal_crc.h
ebrus 0:0a673c671a56 4 * @author MCD Application Team
ebrus 0:0a673c671a56 5 * @version V1.0.0
ebrus 0:0a673c671a56 6 * @date 22-April-2014
ebrus 0:0a673c671a56 7 * @brief Header file of CRC HAL module.
ebrus 0:0a673c671a56 8 ******************************************************************************
ebrus 0:0a673c671a56 9 * @attention
ebrus 0:0a673c671a56 10 *
ebrus 0:0a673c671a56 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
ebrus 0:0a673c671a56 12 *
ebrus 0:0a673c671a56 13 * Redistribution and use in source and binary forms, with or without modification,
ebrus 0:0a673c671a56 14 * are permitted provided that the following conditions are met:
ebrus 0:0a673c671a56 15 * 1. Redistributions of source code must retain the above copyright notice,
ebrus 0:0a673c671a56 16 * this list of conditions and the following disclaimer.
ebrus 0:0a673c671a56 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
ebrus 0:0a673c671a56 18 * this list of conditions and the following disclaimer in the documentation
ebrus 0:0a673c671a56 19 * and/or other materials provided with the distribution.
ebrus 0:0a673c671a56 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
ebrus 0:0a673c671a56 21 * may be used to endorse or promote products derived from this software
ebrus 0:0a673c671a56 22 * without specific prior written permission.
ebrus 0:0a673c671a56 23 *
ebrus 0:0a673c671a56 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
ebrus 0:0a673c671a56 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
ebrus 0:0a673c671a56 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
ebrus 0:0a673c671a56 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
ebrus 0:0a673c671a56 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
ebrus 0:0a673c671a56 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
ebrus 0:0a673c671a56 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
ebrus 0:0a673c671a56 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
ebrus 0:0a673c671a56 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
ebrus 0:0a673c671a56 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
ebrus 0:0a673c671a56 34 *
ebrus 0:0a673c671a56 35 ******************************************************************************
ebrus 0:0a673c671a56 36 */
ebrus 0:0a673c671a56 37
ebrus 0:0a673c671a56 38 /* Define to prevent recursive inclusion -------------------------------------*/
ebrus 0:0a673c671a56 39 #ifndef __STM32L0xx_HAL_CRC_H
ebrus 0:0a673c671a56 40 #define __STM32L0xx_HAL_CRC_H
ebrus 0:0a673c671a56 41
ebrus 0:0a673c671a56 42 #ifdef __cplusplus
ebrus 0:0a673c671a56 43 extern "C" {
ebrus 0:0a673c671a56 44 #endif
ebrus 0:0a673c671a56 45
ebrus 0:0a673c671a56 46 /* Includes ------------------------------------------------------------------*/
ebrus 0:0a673c671a56 47 #include "stm32l0xx_hal_def.h"
ebrus 0:0a673c671a56 48
ebrus 0:0a673c671a56 49 /** @addtogroup STM32L0xx_HAL_Driver
ebrus 0:0a673c671a56 50 * @{
ebrus 0:0a673c671a56 51 */
ebrus 0:0a673c671a56 52
ebrus 0:0a673c671a56 53 /** @addtogroup CRC
ebrus 0:0a673c671a56 54 * @{
ebrus 0:0a673c671a56 55 */
ebrus 0:0a673c671a56 56
ebrus 0:0a673c671a56 57 /* Exported types ------------------------------------------------------------*/
ebrus 0:0a673c671a56 58
ebrus 0:0a673c671a56 59 /**
ebrus 0:0a673c671a56 60 * @brief CRC HAL State Structure definition
ebrus 0:0a673c671a56 61 */
ebrus 0:0a673c671a56 62 typedef enum
ebrus 0:0a673c671a56 63 {
ebrus 0:0a673c671a56 64 HAL_CRC_STATE_RESET = 0x00, /*!< CRC Reset State */
ebrus 0:0a673c671a56 65 HAL_CRC_STATE_READY = 0x01, /*!< CRC Initialized and ready for use */
ebrus 0:0a673c671a56 66 HAL_CRC_STATE_BUSY = 0x02, /*!< CRC process is ongoing */
ebrus 0:0a673c671a56 67 HAL_CRC_STATE_TIMEOUT = 0x03, /*!< CRC Timeout State */
ebrus 0:0a673c671a56 68 HAL_CRC_STATE_ERROR = 0x04 /*!< CRC Error State */
ebrus 0:0a673c671a56 69 }HAL_CRC_StateTypeDef;
ebrus 0:0a673c671a56 70
ebrus 0:0a673c671a56 71 /**
ebrus 0:0a673c671a56 72 * @brief CRC Init Structure definition
ebrus 0:0a673c671a56 73 */
ebrus 0:0a673c671a56 74 typedef struct
ebrus 0:0a673c671a56 75 {
ebrus 0:0a673c671a56 76 uint8_t DefaultPolynomialUse; /*!< This parameter is a value of @ref CRC_Default_Polynomial and indicates if default polynomial is used.
ebrus 0:0a673c671a56 77 If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default
ebrus 0:0a673c671a56 78 X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1.
ebrus 0:0a673c671a56 79 In that case, there is no need to set GeneratingPolynomial field.
ebrus 0:0a673c671a56 80 If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and CRCLength fields must be set */
ebrus 0:0a673c671a56 81
ebrus 0:0a673c671a56 82 uint8_t DefaultInitValueUse; /*!< This parameter is a value of @ref CRC_Default_InitValue_Use and indicates if default init value is used.
ebrus 0:0a673c671a56 83 If set to DEFAULT_INIT_VALUE_ENABLE, resort to default
ebrus 0:0a673c671a56 84 0xFFFFFFFF value. In that case, there is no need to set InitValue field.
ebrus 0:0a673c671a56 85 If otherwise set to DEFAULT_INIT_VALUE_DISABLE, InitValue field must be set */
ebrus 0:0a673c671a56 86
ebrus 0:0a673c671a56 87 uint32_t GeneratingPolynomial; /*!< Set CRC generating polynomial. 7, 8, 16 or 32-bit long value for a polynomial degree
ebrus 0:0a673c671a56 88 respectively equal to 7, 8, 16 or 32. This field is written in normal representation,
ebrus 0:0a673c671a56 89 e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65.
ebrus 0:0a673c671a56 90 No need to specify it if DefaultPolynomialUse is set to DEFAULT_POLYNOMIAL_ENABLE */
ebrus 0:0a673c671a56 91
ebrus 0:0a673c671a56 92 uint32_t CRCLength; /*!< This parameter is a value of @ref CRC_Polynomial_Size_Definitions and indicates CRC length.
ebrus 0:0a673c671a56 93 Value can be either one of
ebrus 0:0a673c671a56 94 CRC_POLYLENGTH_32B (32-bit CRC)
ebrus 0:0a673c671a56 95 CRC_POLYLENGTH_16B (16-bit CRC)
ebrus 0:0a673c671a56 96 CRC_POLYLENGTH_8B (8-bit CRC)
ebrus 0:0a673c671a56 97 CRC_POLYLENGTH_7B (7-bit CRC) */
ebrus 0:0a673c671a56 98
ebrus 0:0a673c671a56 99 uint32_t InitValue; /*!< Init value to initiate CRC computation. No need to specify it if DefaultInitValueUse
ebrus 0:0a673c671a56 100 is set to DEFAULT_INIT_VALUE_ENABLE */
ebrus 0:0a673c671a56 101
ebrus 0:0a673c671a56 102 uint32_t InputDataInversionMode; /*!< This parameter is a value of @ref Input_Data_Inversion and specifies input data inversion mode.
ebrus 0:0a673c671a56 103 Can be either one of the following values
ebrus 0:0a673c671a56 104 CRC_INPUTDATA_INVERSION_NONE no input data inversion
ebrus 0:0a673c671a56 105 CRC_INPUTDATA_INVERSION_BYTE byte-wise inversion, 0x1A2B3C4D becomes 0x58D43CB2
ebrus 0:0a673c671a56 106 CRC_INPUTDATA_INVERSION_HALFWORD halfword-wise inversion, 0x1A2B3C4D becomes 0xD458B23C
ebrus 0:0a673c671a56 107 CRC_INPUTDATA_INVERSION_WORD word-wise inversion, 0x1A2B3C4D becomes 0xB23CD458 */
ebrus 0:0a673c671a56 108
ebrus 0:0a673c671a56 109 uint32_t OutputDataInversionMode; /*!< This parameter is a value of @ref Output_Data_Inversion and specifies output data (i.e. CRC) inversion mode.
ebrus 0:0a673c671a56 110 Can be either
ebrus 0:0a673c671a56 111 CRC_OUTPUTDATA_INVERSION_DISABLED no CRC inversion, or
ebrus 0:0a673c671a56 112 CRC_OUTPUTDATA_INVERSION_ENABLED CRC 0x11223344 is converted into 0x22CC4488 */
ebrus 0:0a673c671a56 113 }CRC_InitTypeDef;
ebrus 0:0a673c671a56 114
ebrus 0:0a673c671a56 115
ebrus 0:0a673c671a56 116 /**
ebrus 0:0a673c671a56 117 * @brief CRC Handle Structure definition
ebrus 0:0a673c671a56 118 */
ebrus 0:0a673c671a56 119 typedef struct
ebrus 0:0a673c671a56 120 {
ebrus 0:0a673c671a56 121 CRC_TypeDef *Instance; /*!< Register base address */
ebrus 0:0a673c671a56 122
ebrus 0:0a673c671a56 123 CRC_InitTypeDef Init; /*!< CRC configuration parameters */
ebrus 0:0a673c671a56 124
ebrus 0:0a673c671a56 125 HAL_LockTypeDef Lock; /*!< CRC Locking object */
ebrus 0:0a673c671a56 126
ebrus 0:0a673c671a56 127 __IO HAL_CRC_StateTypeDef State; /*!< CRC communication state */
ebrus 0:0a673c671a56 128
ebrus 0:0a673c671a56 129 uint32_t InputDataFormat; /*!< This parameter is a value of @ref Input_Buffer_Format and specifies input data format.
ebrus 0:0a673c671a56 130 Can be either
ebrus 0:0a673c671a56 131 CRC_INPUTDATA_FORMAT_BYTES input data is a stream of bytes (8-bit data)
ebrus 0:0a673c671a56 132 CRC_INPUTDATA_FORMAT_HALFWORDS input data is a stream of half-words (16-bit data)
ebrus 0:0a673c671a56 133 CRC_INPUTDATA_FORMAT_WORDS input data is a stream of words (32-bits data)
ebrus 0:0a673c671a56 134 Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization error
ebrus 0:0a673c671a56 135 must occur if InputBufferFormat is not one of the three values listed above */
ebrus 0:0a673c671a56 136 }CRC_HandleTypeDef;
ebrus 0:0a673c671a56 137
ebrus 0:0a673c671a56 138 /* Exported constants --------------------------------------------------------*/
ebrus 0:0a673c671a56 139
ebrus 0:0a673c671a56 140 /** @defgroup CRC_Default_Polynomial_Value Default CRC generating polynomial
ebrus 0:0a673c671a56 141 * @{
ebrus 0:0a673c671a56 142 */
ebrus 0:0a673c671a56 143 #define DEFAULT_CRC32_POLY 0x04C11DB7
ebrus 0:0a673c671a56 144
ebrus 0:0a673c671a56 145 /**
ebrus 0:0a673c671a56 146 * @}
ebrus 0:0a673c671a56 147 */
ebrus 0:0a673c671a56 148
ebrus 0:0a673c671a56 149 /** @defgroup CRC_Default_InitValue Default CRC computation initialization value
ebrus 0:0a673c671a56 150 * @{
ebrus 0:0a673c671a56 151 */
ebrus 0:0a673c671a56 152 #define DEFAULT_CRC_INITVALUE 0xFFFFFFFF
ebrus 0:0a673c671a56 153
ebrus 0:0a673c671a56 154 /**
ebrus 0:0a673c671a56 155 * @}
ebrus 0:0a673c671a56 156 */
ebrus 0:0a673c671a56 157
ebrus 0:0a673c671a56 158 /** @defgroup CRC_Default_Polynomial Indicates whether or not default polynomial is used
ebrus 0:0a673c671a56 159 * @{
ebrus 0:0a673c671a56 160 */
ebrus 0:0a673c671a56 161 #define DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00)
ebrus 0:0a673c671a56 162 #define DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01)
ebrus 0:0a673c671a56 163 #define IS_DEFAULT_POLYNOMIAL(DEFAULT) (((DEFAULT) == DEFAULT_POLYNOMIAL_ENABLE) || \
ebrus 0:0a673c671a56 164 ((DEFAULT) == DEFAULT_POLYNOMIAL_DISABLE))
ebrus 0:0a673c671a56 165
ebrus 0:0a673c671a56 166 /**
ebrus 0:0a673c671a56 167 * @}
ebrus 0:0a673c671a56 168 */
ebrus 0:0a673c671a56 169
ebrus 0:0a673c671a56 170 /** @defgroup CRC_Default_InitValue_Use Indicates whether or not default init value is used
ebrus 0:0a673c671a56 171 * @{
ebrus 0:0a673c671a56 172 */
ebrus 0:0a673c671a56 173 #define DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00)
ebrus 0:0a673c671a56 174 #define DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01)
ebrus 0:0a673c671a56 175 #define IS_DEFAULT_INIT_VALUE(VALUE) (((VALUE) == DEFAULT_INIT_VALUE_ENABLE) || \
ebrus 0:0a673c671a56 176 ((VALUE) == DEFAULT_INIT_VALUE_DISABLE))
ebrus 0:0a673c671a56 177
ebrus 0:0a673c671a56 178 /**
ebrus 0:0a673c671a56 179 * @}
ebrus 0:0a673c671a56 180 */
ebrus 0:0a673c671a56 181
ebrus 0:0a673c671a56 182 /** @defgroup CRC_Polynomial_Sizes Polynomial sizes to configure the IP
ebrus 0:0a673c671a56 183 * @{
ebrus 0:0a673c671a56 184 */
ebrus 0:0a673c671a56 185 #define CRC_POLYLENGTH_32B ((uint32_t)0x00000000)
ebrus 0:0a673c671a56 186 #define CRC_POLYLENGTH_16B ((uint32_t)CRC_CR_POLYSIZE_0)
ebrus 0:0a673c671a56 187 #define CRC_POLYLENGTH_8B ((uint32_t)CRC_CR_POLYSIZE_1)
ebrus 0:0a673c671a56 188 #define CRC_POLYLENGTH_7B ((uint32_t)CRC_CR_POLYSIZE)
ebrus 0:0a673c671a56 189 #define IS_CRC_POL_LENGTH(LENGTH) (((LENGTH) == CRC_POLYLENGTH_32B) || \
ebrus 0:0a673c671a56 190 ((LENGTH) == CRC_POLYLENGTH_16B) || \
ebrus 0:0a673c671a56 191 ((LENGTH) == CRC_POLYLENGTH_8B) || \
ebrus 0:0a673c671a56 192 ((LENGTH) == CRC_POLYLENGTH_7B))
ebrus 0:0a673c671a56 193 /**
ebrus 0:0a673c671a56 194 * @}
ebrus 0:0a673c671a56 195 */
ebrus 0:0a673c671a56 196
ebrus 0:0a673c671a56 197 /** @defgroup CRC_Polynomial_Size_Definitions CRC polynomial possible sizes actual definitions
ebrus 0:0a673c671a56 198 * @{
ebrus 0:0a673c671a56 199 */
ebrus 0:0a673c671a56 200 #define HAL_CRC_LENGTH_32B 32
ebrus 0:0a673c671a56 201 #define HAL_CRC_LENGTH_16B 16
ebrus 0:0a673c671a56 202 #define HAL_CRC_LENGTH_8B 8
ebrus 0:0a673c671a56 203 #define HAL_CRC_LENGTH_7B 7
ebrus 0:0a673c671a56 204
ebrus 0:0a673c671a56 205 /**
ebrus 0:0a673c671a56 206 * @}
ebrus 0:0a673c671a56 207 */
ebrus 0:0a673c671a56 208
ebrus 0:0a673c671a56 209 /** @defgroup Input_Data_Inversion Input Data Inversion Modes
ebrus 0:0a673c671a56 210 * @{
ebrus 0:0a673c671a56 211 */
ebrus 0:0a673c671a56 212 #define CRC_INPUTDATA_INVERSION_NONE ((uint32_t)0x00000000)
ebrus 0:0a673c671a56 213 #define CRC_INPUTDATA_INVERSION_BYTE ((uint32_t)CRC_CR_REV_IN_0)
ebrus 0:0a673c671a56 214 #define CRC_INPUTDATA_INVERSION_HALFWORD ((uint32_t)CRC_CR_REV_IN_1)
ebrus 0:0a673c671a56 215 #define CRC_INPUTDATA_INVERSION_WORD ((uint32_t)CRC_CR_REV_IN)
ebrus 0:0a673c671a56 216 #define IS_CRC_INPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_INPUTDATA_INVERSION_NONE) || \
ebrus 0:0a673c671a56 217 ((MODE) == CRC_INPUTDATA_INVERSION_BYTE) || \
ebrus 0:0a673c671a56 218 ((MODE) == CRC_INPUTDATA_INVERSION_HALFWORD) || \
ebrus 0:0a673c671a56 219 ((MODE) == CRC_INPUTDATA_INVERSION_WORD))
ebrus 0:0a673c671a56 220 /**
ebrus 0:0a673c671a56 221 * @}
ebrus 0:0a673c671a56 222 */
ebrus 0:0a673c671a56 223
ebrus 0:0a673c671a56 224 /** @defgroup Output_Data_Inversion Output Data Inversion Modes
ebrus 0:0a673c671a56 225 * @{
ebrus 0:0a673c671a56 226 */
ebrus 0:0a673c671a56 227 #define CRC_OUTPUTDATA_INVERSION_DISABLED ((uint32_t)0x00000000)
ebrus 0:0a673c671a56 228 #define CRC_OUTPUTDATA_INVERSION_ENABLED ((uint32_t)CRC_CR_REV_OUT)
ebrus 0:0a673c671a56 229 #define IS_CRC_OUTPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_OUTPUTDATA_INVERSION_DISABLED) || \
ebrus 0:0a673c671a56 230 ((MODE) == CRC_OUTPUTDATA_INVERSION_ENABLED))
ebrus 0:0a673c671a56 231 /**
ebrus 0:0a673c671a56 232 * @}
ebrus 0:0a673c671a56 233 */
ebrus 0:0a673c671a56 234
ebrus 0:0a673c671a56 235 /** @defgroup Input_Buffer_Format Input Buffer Format
ebrus 0:0a673c671a56 236 * @{
ebrus 0:0a673c671a56 237 */
ebrus 0:0a673c671a56 238 /* WARNING: CRC_INPUT_FORMAT_UNDEFINED is created for reference purposes but
ebrus 0:0a673c671a56 239 * an error is triggered in HAL_CRC_Init() if InputDataFormat field is set
ebrus 0:0a673c671a56 240 * to CRC_INPUT_FORMAT_UNDEFINED: the format MUST be defined by the user for
ebrus 0:0a673c671a56 241 * the CRC APIs to provide a correct result */
ebrus 0:0a673c671a56 242 #define CRC_INPUTDATA_FORMAT_UNDEFINED ((uint32_t)0x00000000)
ebrus 0:0a673c671a56 243 #define CRC_INPUTDATA_FORMAT_BYTES ((uint32_t)0x00000001)
ebrus 0:0a673c671a56 244 #define CRC_INPUTDATA_FORMAT_HALFWORDS ((uint32_t)0x00000002)
ebrus 0:0a673c671a56 245 #define CRC_INPUTDATA_FORMAT_WORDS ((uint32_t)0x00000003)
ebrus 0:0a673c671a56 246 #define IS_CRC_INPUTDATA_FORMAT(FORMAT) (((FORMAT) == CRC_INPUTDATA_FORMAT_BYTES) || \
ebrus 0:0a673c671a56 247 ((FORMAT) == CRC_INPUTDATA_FORMAT_HALFWORDS) || \
ebrus 0:0a673c671a56 248 ((FORMAT) == CRC_INPUTDATA_FORMAT_WORDS))
ebrus 0:0a673c671a56 249 /**
ebrus 0:0a673c671a56 250 * @}
ebrus 0:0a673c671a56 251 */
ebrus 0:0a673c671a56 252
ebrus 0:0a673c671a56 253 /* Exported macro ------------------------------------------------------------*/
ebrus 0:0a673c671a56 254
ebrus 0:0a673c671a56 255 /** @defgroup CRC_Exported_Macro
ebrus 0:0a673c671a56 256 * @{
ebrus 0:0a673c671a56 257 */
ebrus 0:0a673c671a56 258
ebrus 0:0a673c671a56 259 /** @brief Reset CRC handle state
ebrus 0:0a673c671a56 260 * @param __HANDLE__: CRC handle
ebrus 0:0a673c671a56 261 * @retval None
ebrus 0:0a673c671a56 262 */
ebrus 0:0a673c671a56 263 #define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
ebrus 0:0a673c671a56 264
ebrus 0:0a673c671a56 265 /**
ebrus 0:0a673c671a56 266 * @brief Check that instance is correctly set to CRC
ebrus 0:0a673c671a56 267 * @param __PERIPH__: CRC handle instance
ebrus 0:0a673c671a56 268 * @retval None.
ebrus 0:0a673c671a56 269 */
ebrus 0:0a673c671a56 270 #define IS_CRC_INSTANCE(__PERIPH__) ((__PERIPH__) == CRC)
ebrus 0:0a673c671a56 271
ebrus 0:0a673c671a56 272 /**
ebrus 0:0a673c671a56 273 * @brief Reset CRC Data Register.
ebrus 0:0a673c671a56 274 * @param __HANDLE__: CRC handle
ebrus 0:0a673c671a56 275 * @retval None.
ebrus 0:0a673c671a56 276 */
ebrus 0:0a673c671a56 277 #define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
ebrus 0:0a673c671a56 278
ebrus 0:0a673c671a56 279 /**
ebrus 0:0a673c671a56 280 * @brief Set CRC INIT non-default value
ebrus 0:0a673c671a56 281 * @param __HANDLE__ : CRC handle
ebrus 0:0a673c671a56 282 * @param __INIT__ : 32-bit initial value
ebrus 0:0a673c671a56 283 * @retval None.
ebrus 0:0a673c671a56 284 */
ebrus 0:0a673c671a56 285 #define __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__))
ebrus 0:0a673c671a56 286
ebrus 0:0a673c671a56 287
ebrus 0:0a673c671a56 288 /**
ebrus 0:0a673c671a56 289 * @brief Set CRC output reversal
ebrus 0:0a673c671a56 290 * @param __HANDLE__ : CRC handle
ebrus 0:0a673c671a56 291 * @retval None.
ebrus 0:0a673c671a56 292 */
ebrus 0:0a673c671a56 293 #define __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)
ebrus 0:0a673c671a56 294
ebrus 0:0a673c671a56 295
ebrus 0:0a673c671a56 296 /**
ebrus 0:0a673c671a56 297 * @brief Unset CRC output reversal
ebrus 0:0a673c671a56 298 * @param __HANDLE__ : CRC handle
ebrus 0:0a673c671a56 299 * @retval None.
ebrus 0:0a673c671a56 300 */
ebrus 0:0a673c671a56 301 #define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))
ebrus 0:0a673c671a56 302
ebrus 0:0a673c671a56 303
ebrus 0:0a673c671a56 304 /**
ebrus 0:0a673c671a56 305 * @}
ebrus 0:0a673c671a56 306 */
ebrus 0:0a673c671a56 307
ebrus 0:0a673c671a56 308
ebrus 0:0a673c671a56 309 /* Include CRC HAL Extension module */
ebrus 0:0a673c671a56 310 #include "stm32l0xx_hal_crc_ex.h"
ebrus 0:0a673c671a56 311
ebrus 0:0a673c671a56 312 /* Exported functions --------------------------------------------------------*/
ebrus 0:0a673c671a56 313
ebrus 0:0a673c671a56 314 /* Initialization and de-initialization functions ****************************/
ebrus 0:0a673c671a56 315 HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc);
ebrus 0:0a673c671a56 316 HAL_StatusTypeDef HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc);
ebrus 0:0a673c671a56 317 void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc);
ebrus 0:0a673c671a56 318 void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc);
ebrus 0:0a673c671a56 319 HAL_StatusTypeDef HAL_CRC_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode);
ebrus 0:0a673c671a56 320 HAL_StatusTypeDef HAL_CRC_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode);
ebrus 0:0a673c671a56 321
ebrus 0:0a673c671a56 322 /* Peripheral Control functions ***********************************************/
ebrus 0:0a673c671a56 323 uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
ebrus 0:0a673c671a56 324 uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
ebrus 0:0a673c671a56 325
ebrus 0:0a673c671a56 326 /* Peripheral State and Error functions ***************************************/
ebrus 0:0a673c671a56 327 HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);
ebrus 0:0a673c671a56 328
ebrus 0:0a673c671a56 329 /**
ebrus 0:0a673c671a56 330 * @}
ebrus 0:0a673c671a56 331 */
ebrus 0:0a673c671a56 332
ebrus 0:0a673c671a56 333 /**
ebrus 0:0a673c671a56 334 * @}
ebrus 0:0a673c671a56 335 */
ebrus 0:0a673c671a56 336
ebrus 0:0a673c671a56 337 #ifdef __cplusplus
ebrus 0:0a673c671a56 338 }
ebrus 0:0a673c671a56 339 #endif
ebrus 0:0a673c671a56 340
ebrus 0:0a673c671a56 341 #endif /* __STM32L0xx_HAL_CRC_H */
ebrus 0:0a673c671a56 342
ebrus 0:0a673c671a56 343 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/