Emil Johnsen / mbed-src-STM32F030K6

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targets/cmsis/TARGET_NXP/TARGET_LPC23XX/system_LPC23xx.c@0:0a673c671a56, 2016-07-27 (annotated)

Committer:
ebrus
Date:
Wed Jul 27 18:35:32 2016 +0000
Revision:
0:0a673c671a56
4

Who changed what in which revision?

UserRevisionLine numberNew contents of line
ebrus 0:0a673c671a56 1 /* mbed Microcontroller Library
ebrus 0:0a673c671a56 2 * Copyright (C) 2008-2009 ARM Limited. All rights reserved.
ebrus 0:0a673c671a56 3 *
ebrus 0:0a673c671a56 4 * ARM7 version of CMSIS-like functionality - not advised for use outside mbed!
ebrus 0:0a673c671a56 5 */
ebrus 0:0a673c671a56 6
ebrus 0:0a673c671a56 7 #include <stdint.h>
ebrus 0:0a673c671a56 8 #include "LPC23xx.h"
ebrus 0:0a673c671a56 9
ebrus 0:0a673c671a56 10 #define CLOCK_SETUP 1
ebrus 0:0a673c671a56 11 #define SCS_Val 0x00000020
ebrus 0:0a673c671a56 12 #define CLKSRCSEL_Val 0x00000001
ebrus 0:0a673c671a56 13
ebrus 0:0a673c671a56 14 #define PLL0_SETUP 1
ebrus 0:0a673c671a56 15 #define PLL0CFG_Val 0x00000013
ebrus 0:0a673c671a56 16 #define CCLKCFG_Val 0x00000007
ebrus 0:0a673c671a56 17 #define USBCLKCFG_Val 0x00000009
ebrus 0:0a673c671a56 18 #define PCLKSEL0_Val 0x00000000
ebrus 0:0a673c671a56 19 #define PCLKSEL1_Val 0x00000000
ebrus 0:0a673c671a56 20 #define PCONP_Val 0x042887DE
ebrus 0:0a673c671a56 21 #define CLKOUTCFG_Val 0x00000000
ebrus 0:0a673c671a56 22 #define MAMCR_Val 0x00000001 // there is a bug in the MAM so it should never be fully enabled (only disabled or partially enabled)
ebrus 0:0a673c671a56 23 #define MAMTIM_Val 0x00000004
ebrus 0:0a673c671a56 24
ebrus 0:0a673c671a56 25 /*----------------------------------------------------------------------------
ebrus 0:0a673c671a56 26 DEFINES
ebrus 0:0a673c671a56 27 *----------------------------------------------------------------------------*/
ebrus 0:0a673c671a56 28
ebrus 0:0a673c671a56 29 #define XTAL (12000000UL) /* Oscillator frequency */
ebrus 0:0a673c671a56 30 #define OSC_CLK ( XTAL) /* Main oscillator frequency */
ebrus 0:0a673c671a56 31 #define RTC_CLK ( 32000UL) /* RTC oscillator frequency */
ebrus 0:0a673c671a56 32 #define IRC_OSC ( 4000000UL) /* Internal RC oscillator frequency */
ebrus 0:0a673c671a56 33
ebrus 0:0a673c671a56 34 /* F_cco0 = (2 * M * F_in) / N */
ebrus 0:0a673c671a56 35 #define __M (((PLL0CFG_Val ) & 0x7FFF) + 1)
ebrus 0:0a673c671a56 36 #define __N (((PLL0CFG_Val >> 16) & 0x00FF) + 1)
ebrus 0:0a673c671a56 37 #define __FCCO(__F_IN) ((2 * __M * __F_IN) / __N)
ebrus 0:0a673c671a56 38 #define __CCLK_DIV (((CCLKCFG_Val ) & 0x00FF) + 1)
ebrus 0:0a673c671a56 39
ebrus 0:0a673c671a56 40 /* Determine core clock frequency according to settings */
ebrus 0:0a673c671a56 41 #if (PLL0_SETUP)
ebrus 0:0a673c671a56 42 #if ((CLKSRCSEL_Val & 0x03) == 1)
ebrus 0:0a673c671a56 43 #define __CORE_CLK (__FCCO(OSC_CLK) / __CCLK_DIV)
ebrus 0:0a673c671a56 44 #elif ((CLKSRCSEL_Val & 0x03) == 2)
ebrus 0:0a673c671a56 45 #define __CORE_CLK (__FCCO(RTC_CLK) / __CCLK_DIV)
ebrus 0:0a673c671a56 46 #else
ebrus 0:0a673c671a56 47 #define __CORE_CLK (__FCCO(IRC_OSC) / __CCLK_DIV)
ebrus 0:0a673c671a56 48 #endif
ebrus 0:0a673c671a56 49 #endif
ebrus 0:0a673c671a56 50
ebrus 0:0a673c671a56 51
ebrus 0:0a673c671a56 52 /*----------------------------------------------------------------------------
ebrus 0:0a673c671a56 53 Clock Variable definitions
ebrus 0:0a673c671a56 54 *----------------------------------------------------------------------------*/
ebrus 0:0a673c671a56 55 uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/
ebrus 0:0a673c671a56 56
ebrus 0:0a673c671a56 57 /*----------------------------------------------------------------------------
ebrus 0:0a673c671a56 58 Clock functions
ebrus 0:0a673c671a56 59 *----------------------------------------------------------------------------*/
ebrus 0:0a673c671a56 60 void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
ebrus 0:0a673c671a56 61 {
ebrus 0:0a673c671a56 62 /* Determine clock frequency according to clock register values */
ebrus 0:0a673c671a56 63 if (((LPC_SC->PLL0STAT >> 24) & 3) == 3) { /* If PLL0 enabled and connected */
ebrus 0:0a673c671a56 64 switch (LPC_SC->CLKSRCSEL & 0x03) {
ebrus 0:0a673c671a56 65 case 0: /* Int. RC oscillator => PLL0 */
ebrus 0:0a673c671a56 66 case 3: /* Reserved, default to Int. RC */
ebrus 0:0a673c671a56 67 SystemCoreClock = (IRC_OSC *
ebrus 0:0a673c671a56 68 (((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
ebrus 0:0a673c671a56 69 (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)) /
ebrus 0:0a673c671a56 70 ((LPC_SC->CCLKCFG & 0xFF)+ 1));
ebrus 0:0a673c671a56 71 break;
ebrus 0:0a673c671a56 72 case 1: /* Main oscillator => PLL0 */
ebrus 0:0a673c671a56 73 SystemCoreClock = (OSC_CLK *
ebrus 0:0a673c671a56 74 (((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
ebrus 0:0a673c671a56 75 (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)) /
ebrus 0:0a673c671a56 76 ((LPC_SC->CCLKCFG & 0xFF)+ 1));
ebrus 0:0a673c671a56 77 break;
ebrus 0:0a673c671a56 78 case 2: /* RTC oscillator => PLL0 */
ebrus 0:0a673c671a56 79 SystemCoreClock = (RTC_CLK *
ebrus 0:0a673c671a56 80 (((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
ebrus 0:0a673c671a56 81 (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)) /
ebrus 0:0a673c671a56 82 ((LPC_SC->CCLKCFG & 0xFF)+ 1));
ebrus 0:0a673c671a56 83 break;
ebrus 0:0a673c671a56 84 }
ebrus 0:0a673c671a56 85 } else {
ebrus 0:0a673c671a56 86 switch (LPC_SC->CLKSRCSEL & 0x03) {
ebrus 0:0a673c671a56 87 case 0: /* Int. RC oscillator => PLL0 */
ebrus 0:0a673c671a56 88 case 3: /* Reserved, default to Int. RC */
ebrus 0:0a673c671a56 89 SystemCoreClock = IRC_OSC / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
ebrus 0:0a673c671a56 90 break;
ebrus 0:0a673c671a56 91 case 1: /* Main oscillator => PLL0 */
ebrus 0:0a673c671a56 92 SystemCoreClock = OSC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
ebrus 0:0a673c671a56 93 break;
ebrus 0:0a673c671a56 94 case 2: /* RTC oscillator => PLL0 */
ebrus 0:0a673c671a56 95 SystemCoreClock = RTC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
ebrus 0:0a673c671a56 96 break;
ebrus 0:0a673c671a56 97 }
ebrus 0:0a673c671a56 98 }
ebrus 0:0a673c671a56 99 }
ebrus 0:0a673c671a56 100
ebrus 0:0a673c671a56 101 /**
ebrus 0:0a673c671a56 102 * Initialize the system
ebrus 0:0a673c671a56 103 *
ebrus 0:0a673c671a56 104 * @param none
ebrus 0:0a673c671a56 105 * @return none
ebrus 0:0a673c671a56 106 *
ebrus 0:0a673c671a56 107 * @brief Setup the microcontroller system.
ebrus 0:0a673c671a56 108 * Initialize the System and update the SystemFrequency variable.
ebrus 0:0a673c671a56 109 */
ebrus 0:0a673c671a56 110 void SystemInit (void)
ebrus 0:0a673c671a56 111 {
ebrus 0:0a673c671a56 112 #if (CLOCK_SETUP) /* Clock Setup */
ebrus 0:0a673c671a56 113 LPC_SC->SCS = SCS_Val;
ebrus 0:0a673c671a56 114 if (SCS_Val & (1 << 5)) { /* If Main Oscillator is enabled */
ebrus 0:0a673c671a56 115 while ((LPC_SC->SCS & (1 << 6)) == 0); /* Wait for Oscillator to be ready */
ebrus 0:0a673c671a56 116 }
ebrus 0:0a673c671a56 117
ebrus 0:0a673c671a56 118 LPC_SC->CCLKCFG = CCLKCFG_Val; /* Setup Clock Divider */
ebrus 0:0a673c671a56 119
ebrus 0:0a673c671a56 120 #if (PLL0_SETUP)
ebrus 0:0a673c671a56 121 LPC_SC->CLKSRCSEL = CLKSRCSEL_Val; /* Select Clock Source for PLL0 */
ebrus 0:0a673c671a56 122 LPC_SC->PLL0CFG = PLL0CFG_Val;
ebrus 0:0a673c671a56 123 LPC_SC->PLL0CON = 0x01; /* PLL0 Enable */
ebrus 0:0a673c671a56 124 LPC_SC->PLL0FEED = 0xAA;
ebrus 0:0a673c671a56 125 LPC_SC->PLL0FEED = 0x55;
ebrus 0:0a673c671a56 126 while (!(LPC_SC->PLL0STAT & (1 << 26))); /* Wait for PLOCK0 */
ebrus 0:0a673c671a56 127
ebrus 0:0a673c671a56 128 LPC_SC->PLL0CON = 0x03; /* PLL0 Enable & Connect */
ebrus 0:0a673c671a56 129 LPC_SC->PLL0FEED = 0xAA;
ebrus 0:0a673c671a56 130 LPC_SC->PLL0FEED = 0x55;
ebrus 0:0a673c671a56 131 #endif
ebrus 0:0a673c671a56 132
ebrus 0:0a673c671a56 133 LPC_SC->USBCLKCFG = USBCLKCFG_Val; /* Setup USB Clock Divider */
ebrus 0:0a673c671a56 134 #endif
ebrus 0:0a673c671a56 135
ebrus 0:0a673c671a56 136 LPC_SC->PCLKSEL0 = PCLKSEL0_Val; /* Peripheral Clock Selection */
ebrus 0:0a673c671a56 137 LPC_SC->PCLKSEL1 = PCLKSEL1_Val;
ebrus 0:0a673c671a56 138
ebrus 0:0a673c671a56 139 LPC_SC->PCONP = PCONP_Val; /* Power Control for Peripherals */
ebrus 0:0a673c671a56 140
ebrus 0:0a673c671a56 141 // Setup MAM
ebrus 0:0a673c671a56 142 LPC_SC->MAMTIM = MAMTIM_Val;
ebrus 0:0a673c671a56 143 LPC_SC->MAMCR = MAMCR_Val;
ebrus 0:0a673c671a56 144 }