Emil Johnsen / mbed-src-STM32F030K6

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targets/cmsis/core_cm4_simd.h@5:a95fd30f2195, 2016-10-23 (annotated)

Committer:
emilj
Date:
Sun Oct 23 17:23:00 2016 +0000
Revision:
5:a95fd30f2195
Parent:
0:0a673c671a56 
n/a

Who changed what in which revision?

UserRevisionLine numberNew contents of line
ebrus 0:0a673c671a56 1 /**************************************************************************//**
ebrus 0:0a673c671a56 2 * @file core_cm4_simd.h
ebrus 0:0a673c671a56 3 * @brief CMSIS Cortex-M4 SIMD Header File
ebrus 0:0a673c671a56 4 * @version V3.20
ebrus 0:0a673c671a56 5 * @date 25. February 2013
ebrus 0:0a673c671a56 6 *
ebrus 0:0a673c671a56 7 * @note
ebrus 0:0a673c671a56 8 *
ebrus 0:0a673c671a56 9 ******************************************************************************/
ebrus 0:0a673c671a56 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
ebrus 0:0a673c671a56 11
ebrus 0:0a673c671a56 12 All rights reserved.
ebrus 0:0a673c671a56 13 Redistribution and use in source and binary forms, with or without
ebrus 0:0a673c671a56 14 modification, are permitted provided that the following conditions are met:
ebrus 0:0a673c671a56 15 - Redistributions of source code must retain the above copyright
ebrus 0:0a673c671a56 16 notice, this list of conditions and the following disclaimer.
ebrus 0:0a673c671a56 17 - Redistributions in binary form must reproduce the above copyright
ebrus 0:0a673c671a56 18 notice, this list of conditions and the following disclaimer in the
ebrus 0:0a673c671a56 19 documentation and/or other materials provided with the distribution.
ebrus 0:0a673c671a56 20 - Neither the name of ARM nor the names of its contributors may be used
ebrus 0:0a673c671a56 21 to endorse or promote products derived from this software without
ebrus 0:0a673c671a56 22 specific prior written permission.
ebrus 0:0a673c671a56 23 *
ebrus 0:0a673c671a56 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
ebrus 0:0a673c671a56 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
ebrus 0:0a673c671a56 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ebrus 0:0a673c671a56 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
ebrus 0:0a673c671a56 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
ebrus 0:0a673c671a56 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
ebrus 0:0a673c671a56 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
ebrus 0:0a673c671a56 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
ebrus 0:0a673c671a56 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ebrus 0:0a673c671a56 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
ebrus 0:0a673c671a56 34 POSSIBILITY OF SUCH DAMAGE.
ebrus 0:0a673c671a56 35 ---------------------------------------------------------------------------*/
ebrus 0:0a673c671a56 36
ebrus 0:0a673c671a56 37
ebrus 0:0a673c671a56 38 #ifdef __cplusplus
ebrus 0:0a673c671a56 39 extern "C" {
ebrus 0:0a673c671a56 40 #endif
ebrus 0:0a673c671a56 41
ebrus 0:0a673c671a56 42 #ifndef __CORE_CM4_SIMD_H
ebrus 0:0a673c671a56 43 #define __CORE_CM4_SIMD_H
ebrus 0:0a673c671a56 44
ebrus 0:0a673c671a56 45
ebrus 0:0a673c671a56 46 /*******************************************************************************
ebrus 0:0a673c671a56 47 * Hardware Abstraction Layer
ebrus 0:0a673c671a56 48 ******************************************************************************/
ebrus 0:0a673c671a56 49
ebrus 0:0a673c671a56 50
ebrus 0:0a673c671a56 51 /* ################### Compiler specific Intrinsics ########################### */
ebrus 0:0a673c671a56 52 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
ebrus 0:0a673c671a56 53 Access to dedicated SIMD instructions
ebrus 0:0a673c671a56 54 @{
ebrus 0:0a673c671a56 55 */
ebrus 0:0a673c671a56 56
ebrus 0:0a673c671a56 57 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
ebrus 0:0a673c671a56 58 /* ARM armcc specific functions */
ebrus 0:0a673c671a56 59
ebrus 0:0a673c671a56 60 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
ebrus 0:0a673c671a56 61 #define __SADD8 __sadd8
ebrus 0:0a673c671a56 62 #define __QADD8 __qadd8
ebrus 0:0a673c671a56 63 #define __SHADD8 __shadd8
ebrus 0:0a673c671a56 64 #define __UADD8 __uadd8
ebrus 0:0a673c671a56 65 #define __UQADD8 __uqadd8
ebrus 0:0a673c671a56 66 #define __UHADD8 __uhadd8
ebrus 0:0a673c671a56 67 #define __SSUB8 __ssub8
ebrus 0:0a673c671a56 68 #define __QSUB8 __qsub8
ebrus 0:0a673c671a56 69 #define __SHSUB8 __shsub8
ebrus 0:0a673c671a56 70 #define __USUB8 __usub8
ebrus 0:0a673c671a56 71 #define __UQSUB8 __uqsub8
ebrus 0:0a673c671a56 72 #define __UHSUB8 __uhsub8
ebrus 0:0a673c671a56 73 #define __SADD16 __sadd16
ebrus 0:0a673c671a56 74 #define __QADD16 __qadd16
ebrus 0:0a673c671a56 75 #define __SHADD16 __shadd16
ebrus 0:0a673c671a56 76 #define __UADD16 __uadd16
ebrus 0:0a673c671a56 77 #define __UQADD16 __uqadd16
ebrus 0:0a673c671a56 78 #define __UHADD16 __uhadd16
ebrus 0:0a673c671a56 79 #define __SSUB16 __ssub16
ebrus 0:0a673c671a56 80 #define __QSUB16 __qsub16
ebrus 0:0a673c671a56 81 #define __SHSUB16 __shsub16
ebrus 0:0a673c671a56 82 #define __USUB16 __usub16
ebrus 0:0a673c671a56 83 #define __UQSUB16 __uqsub16
ebrus 0:0a673c671a56 84 #define __UHSUB16 __uhsub16
ebrus 0:0a673c671a56 85 #define __SASX __sasx
ebrus 0:0a673c671a56 86 #define __QASX __qasx
ebrus 0:0a673c671a56 87 #define __SHASX __shasx
ebrus 0:0a673c671a56 88 #define __UASX __uasx
ebrus 0:0a673c671a56 89 #define __UQASX __uqasx
ebrus 0:0a673c671a56 90 #define __UHASX __uhasx
ebrus 0:0a673c671a56 91 #define __SSAX __ssax
ebrus 0:0a673c671a56 92 #define __QSAX __qsax
ebrus 0:0a673c671a56 93 #define __SHSAX __shsax
ebrus 0:0a673c671a56 94 #define __USAX __usax
ebrus 0:0a673c671a56 95 #define __UQSAX __uqsax
ebrus 0:0a673c671a56 96 #define __UHSAX __uhsax
ebrus 0:0a673c671a56 97 #define __USAD8 __usad8
ebrus 0:0a673c671a56 98 #define __USADA8 __usada8
ebrus 0:0a673c671a56 99 #define __SSAT16 __ssat16
ebrus 0:0a673c671a56 100 #define __USAT16 __usat16
ebrus 0:0a673c671a56 101 #define __UXTB16 __uxtb16
ebrus 0:0a673c671a56 102 #define __UXTAB16 __uxtab16
ebrus 0:0a673c671a56 103 #define __SXTB16 __sxtb16
ebrus 0:0a673c671a56 104 #define __SXTAB16 __sxtab16
ebrus 0:0a673c671a56 105 #define __SMUAD __smuad
ebrus 0:0a673c671a56 106 #define __SMUADX __smuadx
ebrus 0:0a673c671a56 107 #define __SMLAD __smlad
ebrus 0:0a673c671a56 108 #define __SMLADX __smladx
ebrus 0:0a673c671a56 109 #define __SMLALD __smlald
ebrus 0:0a673c671a56 110 #define __SMLALDX __smlaldx
ebrus 0:0a673c671a56 111 #define __SMUSD __smusd
ebrus 0:0a673c671a56 112 #define __SMUSDX __smusdx
ebrus 0:0a673c671a56 113 #define __SMLSD __smlsd
ebrus 0:0a673c671a56 114 #define __SMLSDX __smlsdx
ebrus 0:0a673c671a56 115 #define __SMLSLD __smlsld
ebrus 0:0a673c671a56 116 #define __SMLSLDX __smlsldx
ebrus 0:0a673c671a56 117 #define __SEL __sel
ebrus 0:0a673c671a56 118 #define __QADD __qadd
ebrus 0:0a673c671a56 119 #define __QSUB __qsub
ebrus 0:0a673c671a56 120
ebrus 0:0a673c671a56 121 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
ebrus 0:0a673c671a56 122 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
ebrus 0:0a673c671a56 123
ebrus 0:0a673c671a56 124 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
ebrus 0:0a673c671a56 125 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
ebrus 0:0a673c671a56 126
ebrus 0:0a673c671a56 127 #define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
ebrus 0:0a673c671a56 128 ((int64_t)(ARG3) << 32) ) >> 32))
ebrus 0:0a673c671a56 129
ebrus 0:0a673c671a56 130 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
ebrus 0:0a673c671a56 131
ebrus 0:0a673c671a56 132
ebrus 0:0a673c671a56 133
ebrus 0:0a673c671a56 134 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
ebrus 0:0a673c671a56 135 /* IAR iccarm specific functions */
ebrus 0:0a673c671a56 136
ebrus 0:0a673c671a56 137 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
ebrus 0:0a673c671a56 138 #include <cmsis_iar.h>
ebrus 0:0a673c671a56 139
ebrus 0:0a673c671a56 140 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
ebrus 0:0a673c671a56 141
ebrus 0:0a673c671a56 142
ebrus 0:0a673c671a56 143
ebrus 0:0a673c671a56 144 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
ebrus 0:0a673c671a56 145 /* TI CCS specific functions */
ebrus 0:0a673c671a56 146
ebrus 0:0a673c671a56 147 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
ebrus 0:0a673c671a56 148 #include <cmsis_ccs.h>
ebrus 0:0a673c671a56 149
ebrus 0:0a673c671a56 150 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
ebrus 0:0a673c671a56 151
ebrus 0:0a673c671a56 152
ebrus 0:0a673c671a56 153
ebrus 0:0a673c671a56 154 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
ebrus 0:0a673c671a56 155 /* GNU gcc specific functions */
ebrus 0:0a673c671a56 156
ebrus 0:0a673c671a56 157 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
ebrus 0:0a673c671a56 158 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
ebrus 0:0a673c671a56 159 {
ebrus 0:0a673c671a56 160 uint32_t result;
ebrus 0:0a673c671a56 161
ebrus 0:0a673c671a56 162 __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ebrus 0:0a673c671a56 163 return(result);
ebrus 0:0a673c671a56 164 }
ebrus 0:0a673c671a56 165
ebrus 0:0a673c671a56 166 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
ebrus 0:0a673c671a56 167 {
ebrus 0:0a673c671a56 168 uint32_t result;
ebrus 0:0a673c671a56 169
ebrus 0:0a673c671a56 170 __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ebrus 0:0a673c671a56 171 return(result);
ebrus 0:0a673c671a56 172 }
ebrus 0:0a673c671a56 173
ebrus 0:0a673c671a56 174 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
ebrus 0:0a673c671a56 175 {
ebrus 0:0a673c671a56 176 uint32_t result;
ebrus 0:0a673c671a56 177
ebrus 0:0a673c671a56 178 __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ebrus 0:0a673c671a56 179 return(result);
ebrus 0:0a673c671a56 180 }
ebrus 0:0a673c671a56 181
ebrus 0:0a673c671a56 182 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
ebrus 0:0a673c671a56 183 {
ebrus 0:0a673c671a56 184 uint32_t result;
ebrus 0:0a673c671a56 185
ebrus 0:0a673c671a56 186 __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ebrus 0:0a673c671a56 187 return(result);
ebrus 0:0a673c671a56 188 }
ebrus 0:0a673c671a56 189
ebrus 0:0a673c671a56 190 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
ebrus 0:0a673c671a56 191 {
ebrus 0:0a673c671a56 192 uint32_t result;
ebrus 0:0a673c671a56 193
ebrus 0:0a673c671a56 194 __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ebrus 0:0a673c671a56 195 return(result);
ebrus 0:0a673c671a56 196 }
ebrus 0:0a673c671a56 197
ebrus 0:0a673c671a56 198 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
ebrus 0:0a673c671a56 199 {
ebrus 0:0a673c671a56 200 uint32_t result;
ebrus 0:0a673c671a56 201
ebrus 0:0a673c671a56 202 __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ebrus 0:0a673c671a56 203 return(result);
ebrus 0:0a673c671a56 204 }
ebrus 0:0a673c671a56 205
ebrus 0:0a673c671a56 206
ebrus 0:0a673c671a56 207 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
ebrus 0:0a673c671a56 208 {
ebrus 0:0a673c671a56 209 uint32_t result;
ebrus 0:0a673c671a56 210
ebrus 0:0a673c671a56 211 __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ebrus 0:0a673c671a56 212 return(result);
ebrus 0:0a673c671a56 213 }
ebrus 0:0a673c671a56 214
ebrus 0:0a673c671a56 215 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
ebrus 0:0a673c671a56 216 {
ebrus 0:0a673c671a56 217 uint32_t result;
ebrus 0:0a673c671a56 218
ebrus 0:0a673c671a56 219 __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ebrus 0:0a673c671a56 220 return(result);
ebrus 0:0a673c671a56 221 }
ebrus 0:0a673c671a56 222
ebrus 0:0a673c671a56 223 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
ebrus 0:0a673c671a56 224 {
ebrus 0:0a673c671a56 225 uint32_t result;
ebrus 0:0a673c671a56 226
ebrus 0:0a673c671a56 227 __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ebrus 0:0a673c671a56 228 return(result);
ebrus 0:0a673c671a56 229 }
ebrus 0:0a673c671a56 230
ebrus 0:0a673c671a56 231 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
ebrus 0:0a673c671a56 232 {
ebrus 0:0a673c671a56 233 uint32_t result;
ebrus 0:0a673c671a56 234
ebrus 0:0a673c671a56 235 __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ebrus 0:0a673c671a56 236 return(result);
ebrus 0:0a673c671a56 237 }
ebrus 0:0a673c671a56 238
ebrus 0:0a673c671a56 239 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
ebrus 0:0a673c671a56 240 {
ebrus 0:0a673c671a56 241 uint32_t result;
ebrus 0:0a673c671a56 242
ebrus 0:0a673c671a56 243 __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ebrus 0:0a673c671a56 244 return(result);
ebrus 0:0a673c671a56 245 }
ebrus 0:0a673c671a56 246
ebrus 0:0a673c671a56 247 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
ebrus 0:0a673c671a56 248 {
ebrus 0:0a673c671a56 249 uint32_t result;
ebrus 0:0a673c671a56 250
ebrus 0:0a673c671a56 251 __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ebrus 0:0a673c671a56 252 return(result);
ebrus 0:0a673c671a56 253 }
ebrus 0:0a673c671a56 254
ebrus 0:0a673c671a56 255
ebrus 0:0a673c671a56 256 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
ebrus 0:0a673c671a56 257 {
ebrus 0:0a673c671a56 258 uint32_t result;
ebrus 0:0a673c671a56 259
ebrus 0:0a673c671a56 260 __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ebrus 0:0a673c671a56 261 return(result);
ebrus 0:0a673c671a56 262 }
ebrus 0:0a673c671a56 263
ebrus 0:0a673c671a56 264 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
ebrus 0:0a673c671a56 265 {
ebrus 0:0a673c671a56 266 uint32_t result;
ebrus 0:0a673c671a56 267
ebrus 0:0a673c671a56 268 __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ebrus 0:0a673c671a56 269 return(result);
ebrus 0:0a673c671a56 270 }
ebrus 0:0a673c671a56 271
ebrus 0:0a673c671a56 272 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
ebrus 0:0a673c671a56 273 {
ebrus 0:0a673c671a56 274 uint32_t result;
ebrus 0:0a673c671a56 275
ebrus 0:0a673c671a56 276 __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ebrus 0:0a673c671a56 277 return(result);
ebrus 0:0a673c671a56 278 }
ebrus 0:0a673c671a56 279
ebrus 0:0a673c671a56 280 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
ebrus 0:0a673c671a56 281 {
ebrus 0:0a673c671a56 282 uint32_t result;
ebrus 0:0a673c671a56 283
ebrus 0:0a673c671a56 284 __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ebrus 0:0a673c671a56 285 return(result);
ebrus 0:0a673c671a56 286 }
ebrus 0:0a673c671a56 287
ebrus 0:0a673c671a56 288 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
ebrus 0:0a673c671a56 289 {
ebrus 0:0a673c671a56 290 uint32_t result;
ebrus 0:0a673c671a56 291
ebrus 0:0a673c671a56 292 __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ebrus 0:0a673c671a56 293 return(result);
ebrus 0:0a673c671a56 294 }
ebrus 0:0a673c671a56 295
ebrus 0:0a673c671a56 296 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
ebrus 0:0a673c671a56 297 {
ebrus 0:0a673c671a56 298 uint32_t result;
ebrus 0:0a673c671a56 299
ebrus 0:0a673c671a56 300 __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ebrus 0:0a673c671a56 301 return(result);
ebrus 0:0a673c671a56 302 }
ebrus 0:0a673c671a56 303
ebrus 0:0a673c671a56 304 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
ebrus 0:0a673c671a56 305 {
ebrus 0:0a673c671a56 306 uint32_t result;
ebrus 0:0a673c671a56 307
ebrus 0:0a673c671a56 308 __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ebrus 0:0a673c671a56 309 return(result);
ebrus 0:0a673c671a56 310 }
ebrus 0:0a673c671a56 311
ebrus 0:0a673c671a56 312 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
ebrus 0:0a673c671a56 313 {
ebrus 0:0a673c671a56 314 uint32_t result;
ebrus 0:0a673c671a56 315
ebrus 0:0a673c671a56 316 __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ebrus 0:0a673c671a56 317 return(result);
ebrus 0:0a673c671a56 318 }
ebrus 0:0a673c671a56 319
ebrus 0:0a673c671a56 320 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
ebrus 0:0a673c671a56 321 {
ebrus 0:0a673c671a56 322 uint32_t result;
ebrus 0:0a673c671a56 323
ebrus 0:0a673c671a56 324 __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ebrus 0:0a673c671a56 325 return(result);
ebrus 0:0a673c671a56 326 }
ebrus 0:0a673c671a56 327
ebrus 0:0a673c671a56 328 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
ebrus 0:0a673c671a56 329 {
ebrus 0:0a673c671a56 330 uint32_t result;
ebrus 0:0a673c671a56 331
ebrus 0:0a673c671a56 332 __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ebrus 0:0a673c671a56 333 return(result);
ebrus 0:0a673c671a56 334 }
ebrus 0:0a673c671a56 335
ebrus 0:0a673c671a56 336 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
ebrus 0:0a673c671a56 337 {
ebrus 0:0a673c671a56 338 uint32_t result;
ebrus 0:0a673c671a56 339
ebrus 0:0a673c671a56 340 __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ebrus 0:0a673c671a56 341 return(result);
ebrus 0:0a673c671a56 342 }
ebrus 0:0a673c671a56 343
ebrus 0:0a673c671a56 344 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
ebrus 0:0a673c671a56 345 {
ebrus 0:0a673c671a56 346 uint32_t result;
ebrus 0:0a673c671a56 347
ebrus 0:0a673c671a56 348 __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ebrus 0:0a673c671a56 349 return(result);
ebrus 0:0a673c671a56 350 }
ebrus 0:0a673c671a56 351
ebrus 0:0a673c671a56 352 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
ebrus 0:0a673c671a56 353 {
ebrus 0:0a673c671a56 354 uint32_t result;
ebrus 0:0a673c671a56 355
ebrus 0:0a673c671a56 356 __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ebrus 0:0a673c671a56 357 return(result);
ebrus 0:0a673c671a56 358 }
ebrus 0:0a673c671a56 359
ebrus 0:0a673c671a56 360 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
ebrus 0:0a673c671a56 361 {
ebrus 0:0a673c671a56 362 uint32_t result;
ebrus 0:0a673c671a56 363
ebrus 0:0a673c671a56 364 __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ebrus 0:0a673c671a56 365 return(result);
ebrus 0:0a673c671a56 366 }
ebrus 0:0a673c671a56 367
ebrus 0:0a673c671a56 368 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
ebrus 0:0a673c671a56 369 {
ebrus 0:0a673c671a56 370 uint32_t result;
ebrus 0:0a673c671a56 371
ebrus 0:0a673c671a56 372 __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ebrus 0:0a673c671a56 373 return(result);
ebrus 0:0a673c671a56 374 }
ebrus 0:0a673c671a56 375
ebrus 0:0a673c671a56 376 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
ebrus 0:0a673c671a56 377 {
ebrus 0:0a673c671a56 378 uint32_t result;
ebrus 0:0a673c671a56 379
ebrus 0:0a673c671a56 380 __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ebrus 0:0a673c671a56 381 return(result);
ebrus 0:0a673c671a56 382 }
ebrus 0:0a673c671a56 383
ebrus 0:0a673c671a56 384 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
ebrus 0:0a673c671a56 385 {
ebrus 0:0a673c671a56 386 uint32_t result;
ebrus 0:0a673c671a56 387
ebrus 0:0a673c671a56 388 __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ebrus 0:0a673c671a56 389 return(result);
ebrus 0:0a673c671a56 390 }
ebrus 0:0a673c671a56 391
ebrus 0:0a673c671a56 392 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
ebrus 0:0a673c671a56 393 {
ebrus 0:0a673c671a56 394 uint32_t result;
ebrus 0:0a673c671a56 395
ebrus 0:0a673c671a56 396 __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ebrus 0:0a673c671a56 397 return(result);
ebrus 0:0a673c671a56 398 }
ebrus 0:0a673c671a56 399
ebrus 0:0a673c671a56 400 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
ebrus 0:0a673c671a56 401 {
ebrus 0:0a673c671a56 402 uint32_t result;
ebrus 0:0a673c671a56 403
ebrus 0:0a673c671a56 404 __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ebrus 0:0a673c671a56 405 return(result);
ebrus 0:0a673c671a56 406 }
ebrus 0:0a673c671a56 407
ebrus 0:0a673c671a56 408 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
ebrus 0:0a673c671a56 409 {
ebrus 0:0a673c671a56 410 uint32_t result;
ebrus 0:0a673c671a56 411
ebrus 0:0a673c671a56 412 __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ebrus 0:0a673c671a56 413 return(result);
ebrus 0:0a673c671a56 414 }
ebrus 0:0a673c671a56 415
ebrus 0:0a673c671a56 416 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
ebrus 0:0a673c671a56 417 {
ebrus 0:0a673c671a56 418 uint32_t result;
ebrus 0:0a673c671a56 419
ebrus 0:0a673c671a56 420 __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ebrus 0:0a673c671a56 421 return(result);
ebrus 0:0a673c671a56 422 }
ebrus 0:0a673c671a56 423
ebrus 0:0a673c671a56 424 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
ebrus 0:0a673c671a56 425 {
ebrus 0:0a673c671a56 426 uint32_t result;
ebrus 0:0a673c671a56 427
ebrus 0:0a673c671a56 428 __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ebrus 0:0a673c671a56 429 return(result);
ebrus 0:0a673c671a56 430 }
ebrus 0:0a673c671a56 431
ebrus 0:0a673c671a56 432 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
ebrus 0:0a673c671a56 433 {
ebrus 0:0a673c671a56 434 uint32_t result;
ebrus 0:0a673c671a56 435
ebrus 0:0a673c671a56 436 __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ebrus 0:0a673c671a56 437 return(result);
ebrus 0:0a673c671a56 438 }
ebrus 0:0a673c671a56 439
ebrus 0:0a673c671a56 440 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
ebrus 0:0a673c671a56 441 {
ebrus 0:0a673c671a56 442 uint32_t result;
ebrus 0:0a673c671a56 443
ebrus 0:0a673c671a56 444 __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ebrus 0:0a673c671a56 445 return(result);
ebrus 0:0a673c671a56 446 }
ebrus 0:0a673c671a56 447
ebrus 0:0a673c671a56 448 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
ebrus 0:0a673c671a56 449 {
ebrus 0:0a673c671a56 450 uint32_t result;
ebrus 0:0a673c671a56 451
ebrus 0:0a673c671a56 452 __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ebrus 0:0a673c671a56 453 return(result);
ebrus 0:0a673c671a56 454 }
ebrus 0:0a673c671a56 455
ebrus 0:0a673c671a56 456 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
ebrus 0:0a673c671a56 457 {
ebrus 0:0a673c671a56 458 uint32_t result;
ebrus 0:0a673c671a56 459
ebrus 0:0a673c671a56 460 __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
ebrus 0:0a673c671a56 461 return(result);
ebrus 0:0a673c671a56 462 }
ebrus 0:0a673c671a56 463
ebrus 0:0a673c671a56 464 #define __SSAT16(ARG1,ARG2) \
ebrus 0:0a673c671a56 465 ({ \
ebrus 0:0a673c671a56 466 uint32_t __RES, __ARG1 = (ARG1); \
ebrus 0:0a673c671a56 467 __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
ebrus 0:0a673c671a56 468 __RES; \
ebrus 0:0a673c671a56 469 })
ebrus 0:0a673c671a56 470
ebrus 0:0a673c671a56 471 #define __USAT16(ARG1,ARG2) \
ebrus 0:0a673c671a56 472 ({ \
ebrus 0:0a673c671a56 473 uint32_t __RES, __ARG1 = (ARG1); \
ebrus 0:0a673c671a56 474 __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
ebrus 0:0a673c671a56 475 __RES; \
ebrus 0:0a673c671a56 476 })
ebrus 0:0a673c671a56 477
ebrus 0:0a673c671a56 478 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
ebrus 0:0a673c671a56 479 {
ebrus 0:0a673c671a56 480 uint32_t result;
ebrus 0:0a673c671a56 481
ebrus 0:0a673c671a56 482 __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
ebrus 0:0a673c671a56 483 return(result);
ebrus 0:0a673c671a56 484 }
ebrus 0:0a673c671a56 485
ebrus 0:0a673c671a56 486 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
ebrus 0:0a673c671a56 487 {
ebrus 0:0a673c671a56 488 uint32_t result;
ebrus 0:0a673c671a56 489
ebrus 0:0a673c671a56 490 __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ebrus 0:0a673c671a56 491 return(result);
ebrus 0:0a673c671a56 492 }
ebrus 0:0a673c671a56 493
ebrus 0:0a673c671a56 494 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
ebrus 0:0a673c671a56 495 {
ebrus 0:0a673c671a56 496 uint32_t result;
ebrus 0:0a673c671a56 497
ebrus 0:0a673c671a56 498 __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
ebrus 0:0a673c671a56 499 return(result);
ebrus 0:0a673c671a56 500 }
ebrus 0:0a673c671a56 501
ebrus 0:0a673c671a56 502 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
ebrus 0:0a673c671a56 503 {
ebrus 0:0a673c671a56 504 uint32_t result;
ebrus 0:0a673c671a56 505
ebrus 0:0a673c671a56 506 __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ebrus 0:0a673c671a56 507 return(result);
ebrus 0:0a673c671a56 508 }
ebrus 0:0a673c671a56 509
ebrus 0:0a673c671a56 510 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
ebrus 0:0a673c671a56 511 {
ebrus 0:0a673c671a56 512 uint32_t result;
ebrus 0:0a673c671a56 513
ebrus 0:0a673c671a56 514 __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ebrus 0:0a673c671a56 515 return(result);
ebrus 0:0a673c671a56 516 }
ebrus 0:0a673c671a56 517
ebrus 0:0a673c671a56 518 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
ebrus 0:0a673c671a56 519 {
ebrus 0:0a673c671a56 520 uint32_t result;
ebrus 0:0a673c671a56 521
ebrus 0:0a673c671a56 522 __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ebrus 0:0a673c671a56 523 return(result);
ebrus 0:0a673c671a56 524 }
ebrus 0:0a673c671a56 525
ebrus 0:0a673c671a56 526 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
ebrus 0:0a673c671a56 527 {
ebrus 0:0a673c671a56 528 uint32_t result;
ebrus 0:0a673c671a56 529
ebrus 0:0a673c671a56 530 __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
ebrus 0:0a673c671a56 531 return(result);
ebrus 0:0a673c671a56 532 }
ebrus 0:0a673c671a56 533
ebrus 0:0a673c671a56 534 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
ebrus 0:0a673c671a56 535 {
ebrus 0:0a673c671a56 536 uint32_t result;
ebrus 0:0a673c671a56 537
ebrus 0:0a673c671a56 538 __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
ebrus 0:0a673c671a56 539 return(result);
ebrus 0:0a673c671a56 540 }
ebrus 0:0a673c671a56 541
ebrus 0:0a673c671a56 542 #define __SMLALD(ARG1,ARG2,ARG3) \
ebrus 0:0a673c671a56 543 ({ \
ebrus 0:0a673c671a56 544 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
ebrus 0:0a673c671a56 545 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
ebrus 0:0a673c671a56 546 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
ebrus 0:0a673c671a56 547 })
ebrus 0:0a673c671a56 548
ebrus 0:0a673c671a56 549 #define __SMLALDX(ARG1,ARG2,ARG3) \
ebrus 0:0a673c671a56 550 ({ \
ebrus 0:0a673c671a56 551 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
ebrus 0:0a673c671a56 552 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
ebrus 0:0a673c671a56 553 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
ebrus 0:0a673c671a56 554 })
ebrus 0:0a673c671a56 555
ebrus 0:0a673c671a56 556 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
ebrus 0:0a673c671a56 557 {
ebrus 0:0a673c671a56 558 uint32_t result;
ebrus 0:0a673c671a56 559
ebrus 0:0a673c671a56 560 __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ebrus 0:0a673c671a56 561 return(result);
ebrus 0:0a673c671a56 562 }
ebrus 0:0a673c671a56 563
ebrus 0:0a673c671a56 564 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
ebrus 0:0a673c671a56 565 {
ebrus 0:0a673c671a56 566 uint32_t result;
ebrus 0:0a673c671a56 567
ebrus 0:0a673c671a56 568 __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ebrus 0:0a673c671a56 569 return(result);
ebrus 0:0a673c671a56 570 }
ebrus 0:0a673c671a56 571
ebrus 0:0a673c671a56 572 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
ebrus 0:0a673c671a56 573 {
ebrus 0:0a673c671a56 574 uint32_t result;
ebrus 0:0a673c671a56 575
ebrus 0:0a673c671a56 576 __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
ebrus 0:0a673c671a56 577 return(result);
ebrus 0:0a673c671a56 578 }
ebrus 0:0a673c671a56 579
ebrus 0:0a673c671a56 580 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
ebrus 0:0a673c671a56 581 {
ebrus 0:0a673c671a56 582 uint32_t result;
ebrus 0:0a673c671a56 583
ebrus 0:0a673c671a56 584 __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
ebrus 0:0a673c671a56 585 return(result);
ebrus 0:0a673c671a56 586 }
ebrus 0:0a673c671a56 587
ebrus 0:0a673c671a56 588 #define __SMLSLD(ARG1,ARG2,ARG3) \
ebrus 0:0a673c671a56 589 ({ \
ebrus 0:0a673c671a56 590 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
ebrus 0:0a673c671a56 591 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
ebrus 0:0a673c671a56 592 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
ebrus 0:0a673c671a56 593 })
ebrus 0:0a673c671a56 594
ebrus 0:0a673c671a56 595 #define __SMLSLDX(ARG1,ARG2,ARG3) \
ebrus 0:0a673c671a56 596 ({ \
ebrus 0:0a673c671a56 597 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
ebrus 0:0a673c671a56 598 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
ebrus 0:0a673c671a56 599 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
ebrus 0:0a673c671a56 600 })
ebrus 0:0a673c671a56 601
ebrus 0:0a673c671a56 602 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
ebrus 0:0a673c671a56 603 {
ebrus 0:0a673c671a56 604 uint32_t result;
ebrus 0:0a673c671a56 605
ebrus 0:0a673c671a56 606 __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ebrus 0:0a673c671a56 607 return(result);
ebrus 0:0a673c671a56 608 }
ebrus 0:0a673c671a56 609
ebrus 0:0a673c671a56 610 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
ebrus 0:0a673c671a56 611 {
ebrus 0:0a673c671a56 612 uint32_t result;
ebrus 0:0a673c671a56 613
ebrus 0:0a673c671a56 614 __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ebrus 0:0a673c671a56 615 return(result);
ebrus 0:0a673c671a56 616 }
ebrus 0:0a673c671a56 617
ebrus 0:0a673c671a56 618 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
ebrus 0:0a673c671a56 619 {
ebrus 0:0a673c671a56 620 uint32_t result;
ebrus 0:0a673c671a56 621
ebrus 0:0a673c671a56 622 __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ebrus 0:0a673c671a56 623 return(result);
ebrus 0:0a673c671a56 624 }
ebrus 0:0a673c671a56 625
ebrus 0:0a673c671a56 626 #define __PKHBT(ARG1,ARG2,ARG3) \
ebrus 0:0a673c671a56 627 ({ \
ebrus 0:0a673c671a56 628 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
ebrus 0:0a673c671a56 629 __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
ebrus 0:0a673c671a56 630 __RES; \
ebrus 0:0a673c671a56 631 })
ebrus 0:0a673c671a56 632
ebrus 0:0a673c671a56 633 #define __PKHTB(ARG1,ARG2,ARG3) \
ebrus 0:0a673c671a56 634 ({ \
ebrus 0:0a673c671a56 635 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
ebrus 0:0a673c671a56 636 if (ARG3 == 0) \
ebrus 0:0a673c671a56 637 __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
ebrus 0:0a673c671a56 638 else \
ebrus 0:0a673c671a56 639 __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
ebrus 0:0a673c671a56 640 __RES; \
ebrus 0:0a673c671a56 641 })
ebrus 0:0a673c671a56 642
ebrus 0:0a673c671a56 643 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
ebrus 0:0a673c671a56 644 {
ebrus 0:0a673c671a56 645 int32_t result;
ebrus 0:0a673c671a56 646
ebrus 0:0a673c671a56 647 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
ebrus 0:0a673c671a56 648 return(result);
ebrus 0:0a673c671a56 649 }
ebrus 0:0a673c671a56 650
ebrus 0:0a673c671a56 651 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
ebrus 0:0a673c671a56 652
ebrus 0:0a673c671a56 653
ebrus 0:0a673c671a56 654
ebrus 0:0a673c671a56 655 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
ebrus 0:0a673c671a56 656 /* TASKING carm specific functions */
ebrus 0:0a673c671a56 657
ebrus 0:0a673c671a56 658
ebrus 0:0a673c671a56 659 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
ebrus 0:0a673c671a56 660 /* not yet supported */
ebrus 0:0a673c671a56 661 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
ebrus 0:0a673c671a56 662
ebrus 0:0a673c671a56 663
ebrus 0:0a673c671a56 664 #endif
ebrus 0:0a673c671a56 665
ebrus 0:0a673c671a56 666 /*@} end of group CMSIS_SIMD_intrinsics */
ebrus 0:0a673c671a56 667
ebrus 0:0a673c671a56 668
ebrus 0:0a673c671a56 669 #endif /* __CORE_CM4_SIMD_H */
ebrus 0:0a673c671a56 670
ebrus 0:0a673c671a56 671 #ifdef __cplusplus
ebrus 0:0a673c671a56 672 }
ebrus 0:0a673c671a56 673 #endif