Emil Johnsen / mbed-src-STM32F030K6

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targets/cmsis/TARGET_STM/TARGET_NUCLEO_F334R8/stm32f3xx_hal_sdadc.c@5:a95fd30f2195, 2016-10-23 (annotated)

Committer:
emilj
Date:
Sun Oct 23 17:23:00 2016 +0000
Revision:
5:a95fd30f2195
Parent:
0:0a673c671a56 
n/a

Who changed what in which revision?

UserRevisionLine numberNew contents of line
ebrus 0:0a673c671a56 1 /**
ebrus 0:0a673c671a56 2 ******************************************************************************
ebrus 0:0a673c671a56 3 * @file stm32f3xx_hal_sdadc.c
ebrus 0:0a673c671a56 4 * @author MCD Application Team
ebrus 0:0a673c671a56 5 * @version V1.0.1
ebrus 0:0a673c671a56 6 * @date 18-June-2014
ebrus 0:0a673c671a56 7 * @brief This file provides firmware functions to manage the following
ebrus 0:0a673c671a56 8 * functionalities of the Sigma-Delta Analog to Digital Convertor
ebrus 0:0a673c671a56 9 * (SDADC) peripherals:
ebrus 0:0a673c671a56 10 * + Initialization and Configuration
ebrus 0:0a673c671a56 11 * + Regular Channels Configuration
ebrus 0:0a673c671a56 12 * + Injected channels Configuration
ebrus 0:0a673c671a56 13 * + Power saving
ebrus 0:0a673c671a56 14 * + Regular/Injected Channels DMA Configuration
ebrus 0:0a673c671a56 15 * + Interrupts and flags management
ebrus 0:0a673c671a56 16 *
ebrus 0:0a673c671a56 17 @verbatim
ebrus 0:0a673c671a56 18 ==============================================================================
ebrus 0:0a673c671a56 19 ##### SDADC specific features #####
ebrus 0:0a673c671a56 20 ==============================================================================
ebrus 0:0a673c671a56 21 [..]
ebrus 0:0a673c671a56 22 (#) 16-bit sigma delta architecture.
ebrus 0:0a673c671a56 23 (#) Self calibration.
ebrus 0:0a673c671a56 24 (#) Interrupt generation at the end of calibration, regular/injected conversion
ebrus 0:0a673c671a56 25 and in case of overrun events.
ebrus 0:0a673c671a56 26 (#) Single and continuous conversion modes.
ebrus 0:0a673c671a56 27 (#) External trigger option with configurable polarity for injected conversion.
ebrus 0:0a673c671a56 28 (#) Multi mode (synchronized another SDADC with SDADC1).
ebrus 0:0a673c671a56 29 (#) DMA request generation during regular or injected channel conversion.
ebrus 0:0a673c671a56 30
ebrus 0:0a673c671a56 31 ##### How to use this driver #####
ebrus 0:0a673c671a56 32 ==============================================================================
ebrus 0:0a673c671a56 33 [..]
ebrus 0:0a673c671a56 34 *** Initialization ***
ebrus 0:0a673c671a56 35 ======================
ebrus 0:0a673c671a56 36 [..]
ebrus 0:0a673c671a56 37 (#) As prerequisite, fill in the HAL_SDADC_MspInit() :
ebrus 0:0a673c671a56 38 (+) Enable SDADCx clock interface with __SDADCx_CLK_ENABLE().
ebrus 0:0a673c671a56 39 (+) Configure SDADCx clock divider with HAL_RCCEx_PeriphCLKConfig.
ebrus 0:0a673c671a56 40 (+) Enable power on SDADC with HAL_PWREx_EnableSDADCAnalog().
ebrus 0:0a673c671a56 41 (+) Enable the clocks for the SDADC GPIOS with __GPIOx_CLK_ENABLE().
ebrus 0:0a673c671a56 42 (+) Configure these SDADC pins in analog mode using HAL_GPIO_Init().
ebrus 0:0a673c671a56 43 (+) If interrupt mode is used, enable and configure SDADC global
ebrus 0:0a673c671a56 44 interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
ebrus 0:0a673c671a56 45 (+) If DMA mode is used, configure DMA with HAL_DMA_Init and link it
ebrus 0:0a673c671a56 46 with SDADC handle using __HAL_LINKDMA.
ebrus 0:0a673c671a56 47 (#) Configure the SDADC low power mode, fast conversion mode, slow clock
ebrus 0:0a673c671a56 48 mode and SDADC1 reference voltage using the HAL_ADC_Init() function.
ebrus 0:0a673c671a56 49 If multiple SDADC are used, please configure first SDADC1 with the
ebrus 0:0a673c671a56 50 common reference voltage.
ebrus 0:0a673c671a56 51 (#) Prepare channel configurations (input mode, common mode, gain and
ebrus 0:0a673c671a56 52 offset) using HAL_SDADC_PrepareChannelConfig and associate channel
ebrus 0:0a673c671a56 53 with one configuration using HAL_SDADC_AssociateChannelConfig.
ebrus 0:0a673c671a56 54
ebrus 0:0a673c671a56 55 *** Calibration ***
ebrus 0:0a673c671a56 56 ============================================
ebrus 0:0a673c671a56 57 [..]
ebrus 0:0a673c671a56 58 (#) Start calibration using HAL_SDADC_StartCalibration or
ebrus 0:0a673c671a56 59 HAL_SDADC_CalibrationStart_IT.
ebrus 0:0a673c671a56 60 (#) In polling mode, use HAL_SDADC_PollForCalibEvent to detect the end of
ebrus 0:0a673c671a56 61 calibration.
ebrus 0:0a673c671a56 62 (#) In interrupt mode, HAL_SDADC_CalibrationCpltCallback will be called at
ebrus 0:0a673c671a56 63 the end of calibration.
ebrus 0:0a673c671a56 64
ebrus 0:0a673c671a56 65 *** Regular channel conversion ***
ebrus 0:0a673c671a56 66 ============================================
ebrus 0:0a673c671a56 67 [..]
ebrus 0:0a673c671a56 68 (#) Select trigger for regular conversion using
ebrus 0:0a673c671a56 69 HAL_SDADC_SelectRegularTrigger.
ebrus 0:0a673c671a56 70 (#) Select regular channel and enable/disable continuous mode using
ebrus 0:0a673c671a56 71 HAL_SDADC_ConfigChannel.
ebrus 0:0a673c671a56 72 (#) Start regular conversion using HAL_SDADC_Start, HAL_SDADC_Start_IT
ebrus 0:0a673c671a56 73 or HAL_SDADC_Start_DMA.
ebrus 0:0a673c671a56 74 (#) In polling mode, use HAL_SDADC_PollForConversion to detect the end of
ebrus 0:0a673c671a56 75 regular conversion.
ebrus 0:0a673c671a56 76 (#) In interrupt mode, HAL_SDADC_ConvCpltCallback will be called at the
ebrus 0:0a673c671a56 77 end of regular conversion.
ebrus 0:0a673c671a56 78 (#) Get value of regular conversion using HAL_SDADC_GetValue.
ebrus 0:0a673c671a56 79 (#) In DMA mode, HAL_SDADC_ConvHalfCpltCallback and
ebrus 0:0a673c671a56 80 HAL_SDADC_ConvCpltCallback will be called respectively at the half
ebrus 0:0a673c671a56 81 tranfer and at the tranfer complete.
ebrus 0:0a673c671a56 82 (#) Stop regular conversion using HAL_SDADC_Stop, HAL_SDADC_Stop_IT
ebrus 0:0a673c671a56 83 or HAL_SDADC_Stop_DMA.
ebrus 0:0a673c671a56 84
ebrus 0:0a673c671a56 85 *** Injected channels conversion ***
ebrus 0:0a673c671a56 86 ============================================
ebrus 0:0a673c671a56 87 [..]
ebrus 0:0a673c671a56 88 (#) Enable/disable delay on injected conversion using
ebrus 0:0a673c671a56 89 HAL_SDADC_SelectInjectedDelay.
ebrus 0:0a673c671a56 90 (#) If external trigger is used for injected conversion, configure this
ebrus 0:0a673c671a56 91 trigger using HAL_SDADC_SelectInjectedExtTrigger.
ebrus 0:0a673c671a56 92 (#) Select trigger for injected conversion using
ebrus 0:0a673c671a56 93 HAL_SDADC_SelectInjectedTrigger.
ebrus 0:0a673c671a56 94 (#) Select injected channels and enable/disable continuous mode using
ebrus 0:0a673c671a56 95 HAL_SDADC_InjectedConfigChannel.
ebrus 0:0a673c671a56 96 (#) Start injected conversion using HAL_SDADC_InjectedStart,
ebrus 0:0a673c671a56 97 HAL_SDADC_InjectedStart_IT or HAL_SDADC_InjectedStart_DMA.
ebrus 0:0a673c671a56 98 (#) In polling mode, use HAL_SDADC_PollForInjectedConversion to detect the
ebrus 0:0a673c671a56 99 end of injected conversion.
ebrus 0:0a673c671a56 100 (#) In interrupt mode, HAL_SDADC_InjectedConvCpltCallback will be called
ebrus 0:0a673c671a56 101 at the end of injected conversion.
ebrus 0:0a673c671a56 102 (#) Get value of injected conversion and corresponding channel using
ebrus 0:0a673c671a56 103 HAL_SDADC_InjectedGetValue.
ebrus 0:0a673c671a56 104 (#) In DMA mode, HAL_SDADC_InjectedConvHalfCpltCallback and
ebrus 0:0a673c671a56 105 HAL_SDADC_InjectedConvCpltCallback will be called respectively at the
ebrus 0:0a673c671a56 106 half tranfer and at the tranfer complete.
ebrus 0:0a673c671a56 107 (#) Stop injected conversion using HAL_SDADC_InjectedStop,
ebrus 0:0a673c671a56 108 HAL_SDADC_InjectedStop_IT or HAL_SDADC_InjectedStop_DMA.
ebrus 0:0a673c671a56 109
ebrus 0:0a673c671a56 110 *** Multi mode regular channels conversions ***
ebrus 0:0a673c671a56 111 ======================================================
ebrus 0:0a673c671a56 112 [..]
ebrus 0:0a673c671a56 113 (#) Select type of multimode (SDADC1/SDADC2 or SDADC1/SDADC3) using
ebrus 0:0a673c671a56 114 HAL_SDADC_MultiModeConfigChannel.
ebrus 0:0a673c671a56 115 (#) Select software trigger for SDADC1 and synchronized trigger for
ebrus 0:0a673c671a56 116 SDADC2 (or SDADC3) using HAL_SDADC_SelectRegularTrigger.
ebrus 0:0a673c671a56 117 (#) Select regular channel for SDADC1 and SDADC2 (or SDADC3) using
ebrus 0:0a673c671a56 118 HAL_SDADC_ConfigChannel.
ebrus 0:0a673c671a56 119 (#) Start regular conversion for SDADC2 (or SDADC3) with HAL_SDADC_Start.
ebrus 0:0a673c671a56 120 (#) Start regular conversion for SDADC1 using HAL_SDADC_Start,
ebrus 0:0a673c671a56 121 HAL_SDADC_Start_IT or HAL_SDADC_MultiModeStart_DMA.
ebrus 0:0a673c671a56 122 (#) In polling mode, use HAL_SDADC_PollForConversion to detect the end of
ebrus 0:0a673c671a56 123 regular conversion for SDADC1.
ebrus 0:0a673c671a56 124 (#) In interrupt mode, HAL_SDADC_ConvCpltCallback will be called at the
ebrus 0:0a673c671a56 125 end of regular conversion for SDADC1.
ebrus 0:0a673c671a56 126 (#) Get value of regular conversions using HAL_SDADC_MultiModeGetValue.
ebrus 0:0a673c671a56 127 (#) In DMA mode, HAL_SDADC_ConvHalfCpltCallback and
ebrus 0:0a673c671a56 128 HAL_SDADC_ConvCpltCallback will be called respectively at the half
ebrus 0:0a673c671a56 129 tranfer and at the tranfer complete for SDADC1.
ebrus 0:0a673c671a56 130 (#) Stop regular conversion using HAL_SDADC_Stop, HAL_SDADC_Stop_IT
ebrus 0:0a673c671a56 131 or HAL_SDADC_MultiModeStop_DMA for SDADC1.
ebrus 0:0a673c671a56 132 (#) Stop regular conversion using HAL_SDADC_Stop for SDADC2 (or SDADC3).
ebrus 0:0a673c671a56 133
ebrus 0:0a673c671a56 134 *** Multi mode injected channels conversions ***
ebrus 0:0a673c671a56 135 ======================================================
ebrus 0:0a673c671a56 136 [..]
ebrus 0:0a673c671a56 137 (#) Select type of multimode (SDADC1/SDADC2 or SDADC1/SDADC3) using
ebrus 0:0a673c671a56 138 HAL_SDADC_InjectedMultiModeConfigChannel.
ebrus 0:0a673c671a56 139 (#) Select software or external trigger for SDADC1 and synchronized
ebrus 0:0a673c671a56 140 trigger for SDADC2 (or SDADC3) using HAL_SDADC_SelectInjectedTrigger.
ebrus 0:0a673c671a56 141 (#) Select injected channels for SDADC1 and SDADC2 (or SDADC3) using
ebrus 0:0a673c671a56 142 HAL_SDADC_InjectedConfigChannel.
ebrus 0:0a673c671a56 143 (#) Start injected conversion for SDADC2 (or SDADC3) with
ebrus 0:0a673c671a56 144 HAL_SDADC_InjectedStart.
ebrus 0:0a673c671a56 145 (#) Start injected conversion for SDADC1 using HAL_SDADC_InjectedStart,
ebrus 0:0a673c671a56 146 HAL_SDADC_InjectedStart_IT or HAL_SDADC_InjectedMultiModeStart_DMA.
ebrus 0:0a673c671a56 147 (#) In polling mode, use HAL_SDADC_InjectedPollForConversion to detect
ebrus 0:0a673c671a56 148 the end of injected conversion for SDADC1.
ebrus 0:0a673c671a56 149 (#) In interrupt mode, HAL_SDADC_InjectedConvCpltCallback will be called
ebrus 0:0a673c671a56 150 at the end of injected conversion for SDADC1.
ebrus 0:0a673c671a56 151 (#) Get value of injected conversions using
ebrus 0:0a673c671a56 152 HAL_SDADC_InjectedMultiModeGetValue.
ebrus 0:0a673c671a56 153 (#) In DMA mode, HAL_SDADC_InjectedConvHalfCpltCallback and
ebrus 0:0a673c671a56 154 HAL_SDADC_InjectedConvCpltCallback will be called respectively at the
ebrus 0:0a673c671a56 155 half tranfer and at the tranfer complete for SDADC1.
ebrus 0:0a673c671a56 156 (#) Stop injected conversion using HAL_SDADC_InjectedStop,
ebrus 0:0a673c671a56 157 HAL_SDADC_InjectedStop_IT or HAL_SDADC_InjecteddMultiModeStop_DMA
ebrus 0:0a673c671a56 158 for SDADC1.
ebrus 0:0a673c671a56 159 (#) Stop injected conversion using HAL_SDADC_InjectedStop for SDADC2
ebrus 0:0a673c671a56 160 (or SDADC3).
ebrus 0:0a673c671a56 161
ebrus 0:0a673c671a56 162 @endverbatim
ebrus 0:0a673c671a56 163 ******************************************************************************
ebrus 0:0a673c671a56 164 * @attention
ebrus 0:0a673c671a56 165 *
ebrus 0:0a673c671a56 166 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
ebrus 0:0a673c671a56 167 *
ebrus 0:0a673c671a56 168 * Redistribution and use in source and binary forms, with or without modification,
ebrus 0:0a673c671a56 169 * are permitted provided that the following conditions are met:
ebrus 0:0a673c671a56 170 * 1. Redistributions of source code must retain the above copyright notice,
ebrus 0:0a673c671a56 171 * this list of conditions and the following disclaimer.
ebrus 0:0a673c671a56 172 * 2. Redistributions in binary form must reproduce the above copyright notice,
ebrus 0:0a673c671a56 173 * this list of conditions and the following disclaimer in the documentation
ebrus 0:0a673c671a56 174 * and/or other materials provided with the distribution.
ebrus 0:0a673c671a56 175 * 3. Neither the name of STMicroelectronics nor the names of its contributors
ebrus 0:0a673c671a56 176 * may be used to endorse or promote products derived from this software
ebrus 0:0a673c671a56 177 * without specific prior written permission.
ebrus 0:0a673c671a56 178 *
ebrus 0:0a673c671a56 179 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
ebrus 0:0a673c671a56 180 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
ebrus 0:0a673c671a56 181 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
ebrus 0:0a673c671a56 182 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
ebrus 0:0a673c671a56 183 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
ebrus 0:0a673c671a56 184 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
ebrus 0:0a673c671a56 185 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
ebrus 0:0a673c671a56 186 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
ebrus 0:0a673c671a56 187 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
ebrus 0:0a673c671a56 188 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
ebrus 0:0a673c671a56 189 *
ebrus 0:0a673c671a56 190 ******************************************************************************
ebrus 0:0a673c671a56 191 */
ebrus 0:0a673c671a56 192
ebrus 0:0a673c671a56 193 /* Includes ------------------------------------------------------------------*/
ebrus 0:0a673c671a56 194 #include "stm32f3xx_hal.h"
ebrus 0:0a673c671a56 195
ebrus 0:0a673c671a56 196 /** @addtogroup STM32F3xx_HAL_Driver
ebrus 0:0a673c671a56 197 * @{
ebrus 0:0a673c671a56 198 */
ebrus 0:0a673c671a56 199
ebrus 0:0a673c671a56 200 /** @defgroup SDADC
ebrus 0:0a673c671a56 201 * @brief SDADC driver modules
ebrus 0:0a673c671a56 202 * @{
ebrus 0:0a673c671a56 203 */
ebrus 0:0a673c671a56 204
ebrus 0:0a673c671a56 205 #ifdef HAL_SDADC_MODULE_ENABLED
ebrus 0:0a673c671a56 206 #if defined(STM32F373xC) || defined(STM32F378xx)
ebrus 0:0a673c671a56 207
ebrus 0:0a673c671a56 208 /* Private typedef -----------------------------------------------------------*/
ebrus 0:0a673c671a56 209 /* Private define ------------------------------------------------------------*/
ebrus 0:0a673c671a56 210 #define SDADC_TIMEOUT 200
ebrus 0:0a673c671a56 211 #define SDADC_CONFREG_OFFSET 0x00000020
ebrus 0:0a673c671a56 212 #define SDADC_JDATAR_CH_OFFSET 24
ebrus 0:0a673c671a56 213 #define SDADC_MSB_MASK 0xFFFF0000
ebrus 0:0a673c671a56 214 #define SDADC_LSB_MASK 0x0000FFFF
ebrus 0:0a673c671a56 215 /* Private macro -------------------------------------------------------------*/
ebrus 0:0a673c671a56 216 /* Private variables ---------------------------------------------------------*/
ebrus 0:0a673c671a56 217 /* Private function prototypes -----------------------------------------------*/
ebrus 0:0a673c671a56 218 static HAL_StatusTypeDef SDADC_EnterInitMode(SDADC_HandleTypeDef* hsdadc);
ebrus 0:0a673c671a56 219 static void SDADC_ExitInitMode(SDADC_HandleTypeDef* hsdadc);
ebrus 0:0a673c671a56 220 static uint32_t SDADC_GetInjChannelsNbr(uint32_t Channels);
ebrus 0:0a673c671a56 221 static HAL_StatusTypeDef SDADC_RegConvStart(SDADC_HandleTypeDef* hsdadc);
ebrus 0:0a673c671a56 222 static HAL_StatusTypeDef SDADC_RegConvStop(SDADC_HandleTypeDef* hsdadc);
ebrus 0:0a673c671a56 223 static HAL_StatusTypeDef SDADC_InjConvStart(SDADC_HandleTypeDef* hsdadc);
ebrus 0:0a673c671a56 224 static HAL_StatusTypeDef SDADC_InjConvStop(SDADC_HandleTypeDef* hsdadc);
ebrus 0:0a673c671a56 225 static void SDADC_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma);
ebrus 0:0a673c671a56 226 static void SDADC_DMARegularConvCplt(DMA_HandleTypeDef *hdma);
ebrus 0:0a673c671a56 227 static void SDADC_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma);
ebrus 0:0a673c671a56 228 static void SDADC_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma);
ebrus 0:0a673c671a56 229 static void SDADC_DMAError(DMA_HandleTypeDef *hdma);
ebrus 0:0a673c671a56 230
ebrus 0:0a673c671a56 231 /* Private functions ---------------------------------------------------------*/
ebrus 0:0a673c671a56 232
ebrus 0:0a673c671a56 233 /** @defgroup SDADC_Private_Functions
ebrus 0:0a673c671a56 234 * @{
ebrus 0:0a673c671a56 235 */
ebrus 0:0a673c671a56 236
ebrus 0:0a673c671a56 237 /** @defgroup SDADC_Group1 Initialization/de-initialization functions
ebrus 0:0a673c671a56 238 * @brief Initialization and de-initialization functions
ebrus 0:0a673c671a56 239 *
ebrus 0:0a673c671a56 240 @verbatim
ebrus 0:0a673c671a56 241 ===============================================================================
ebrus 0:0a673c671a56 242 ##### Initialization and de-initialization functions #####
ebrus 0:0a673c671a56 243 ===============================================================================
ebrus 0:0a673c671a56 244 [..] This section provides functions allowing to:
ebrus 0:0a673c671a56 245 (+) Initialize the SDADC.
ebrus 0:0a673c671a56 246 (+) De-initialize the SDADC.
ebrus 0:0a673c671a56 247
ebrus 0:0a673c671a56 248 @endverbatim
ebrus 0:0a673c671a56 249 * @{
ebrus 0:0a673c671a56 250 */
ebrus 0:0a673c671a56 251
ebrus 0:0a673c671a56 252 /**
ebrus 0:0a673c671a56 253 * @brief Initializes the SDADC according to the specified
ebrus 0:0a673c671a56 254 * parameters in the SDADC_InitTypeDef structure.
ebrus 0:0a673c671a56 255 * @note If multiple SDADC are used, please configure first SDADC1 to set
ebrus 0:0a673c671a56 256 * the common reference voltage.
ebrus 0:0a673c671a56 257 * @param hsdadc : SDADC handle.
ebrus 0:0a673c671a56 258 * @retval HAL status.
ebrus 0:0a673c671a56 259 */
ebrus 0:0a673c671a56 260 HAL_StatusTypeDef HAL_SDADC_Init(SDADC_HandleTypeDef* hsdadc)
ebrus 0:0a673c671a56 261 {
ebrus 0:0a673c671a56 262 /* Check parameters */
ebrus 0:0a673c671a56 263 assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
ebrus 0:0a673c671a56 264 assert_param(IS_SDADC_LOWPOWER_MODE(hsdadc->Init.IdleLowPowerMode));
ebrus 0:0a673c671a56 265 assert_param(IS_SDADC_FAST_CONV_MODE(hsdadc->Init.FastConversionMode));
ebrus 0:0a673c671a56 266 assert_param(IS_SDADC_SLOW_CLOCK_MODE(hsdadc->Init.SlowClockMode));
ebrus 0:0a673c671a56 267 assert_param(IS_SDADC_VREF(hsdadc->Init.ReferenceVoltage));
ebrus 0:0a673c671a56 268
ebrus 0:0a673c671a56 269 /* Check SDADC handle */
ebrus 0:0a673c671a56 270 if(hsdadc == NULL)
ebrus 0:0a673c671a56 271 {
ebrus 0:0a673c671a56 272 return HAL_ERROR;
ebrus 0:0a673c671a56 273 }
ebrus 0:0a673c671a56 274
ebrus 0:0a673c671a56 275 /* Initialize SDADC variables with default values */
ebrus 0:0a673c671a56 276 hsdadc->RegularContMode = SDADC_CONTINUOUS_CONV_OFF;
ebrus 0:0a673c671a56 277 hsdadc->InjectedContMode = SDADC_CONTINUOUS_CONV_OFF;
ebrus 0:0a673c671a56 278 hsdadc->InjectedChannelsNbr = 1;
ebrus 0:0a673c671a56 279 hsdadc->InjConvRemaining = 1;
ebrus 0:0a673c671a56 280 hsdadc->RegularTrigger = SDADC_SOFTWARE_TRIGGER;
ebrus 0:0a673c671a56 281 hsdadc->InjectedTrigger = SDADC_SOFTWARE_TRIGGER;
ebrus 0:0a673c671a56 282 hsdadc->ExtTriggerEdge = SDADC_EXT_TRIG_RISING_EDGE;
ebrus 0:0a673c671a56 283 hsdadc->RegularMultimode = SDADC_MULTIMODE_SDADC1_SDADC2;
ebrus 0:0a673c671a56 284 hsdadc->InjectedMultimode = SDADC_MULTIMODE_SDADC1_SDADC2;
ebrus 0:0a673c671a56 285 hsdadc->ErrorCode = SDADC_ERROR_NONE;
ebrus 0:0a673c671a56 286
ebrus 0:0a673c671a56 287 /* Call MSP init function */
ebrus 0:0a673c671a56 288 HAL_SDADC_MspInit(hsdadc);
ebrus 0:0a673c671a56 289
ebrus 0:0a673c671a56 290 /* Set idle low power and slow clock modes */
ebrus 0:0a673c671a56 291 hsdadc->Instance->CR1 &= ~(SDADC_CR1_SBI|SDADC_CR1_PDI|SDADC_CR1_SLOWCK);
ebrus 0:0a673c671a56 292 hsdadc->Instance->CR1 |= (hsdadc->Init.IdleLowPowerMode | \
ebrus 0:0a673c671a56 293 hsdadc->Init.SlowClockMode);
ebrus 0:0a673c671a56 294
ebrus 0:0a673c671a56 295 /* Set fast conversion mode */
ebrus 0:0a673c671a56 296 hsdadc->Instance->CR2 &= ~(SDADC_CR2_FAST);
ebrus 0:0a673c671a56 297 hsdadc->Instance->CR2 |= hsdadc->Init.FastConversionMode;
ebrus 0:0a673c671a56 298
ebrus 0:0a673c671a56 299 /* Set reference voltage only for SDADC1 */
ebrus 0:0a673c671a56 300 if(hsdadc->Instance == SDADC1)
ebrus 0:0a673c671a56 301 {
ebrus 0:0a673c671a56 302 hsdadc->Instance->CR1 &= ~(SDADC_CR1_REFV);
ebrus 0:0a673c671a56 303 hsdadc->Instance->CR1 |= hsdadc->Init.ReferenceVoltage;
ebrus 0:0a673c671a56 304
ebrus 0:0a673c671a56 305 /* Wait at least 2ms before setting ADON */
ebrus 0:0a673c671a56 306 HAL_Delay(2);
ebrus 0:0a673c671a56 307 }
ebrus 0:0a673c671a56 308
ebrus 0:0a673c671a56 309 /* Enable SDADC */
ebrus 0:0a673c671a56 310 hsdadc->Instance->CR2 |= SDADC_CR2_ADON;
ebrus 0:0a673c671a56 311
ebrus 0:0a673c671a56 312 /* Wait end of stabilization */
ebrus 0:0a673c671a56 313 while((hsdadc->Instance->ISR & SDADC_ISR_STABIP) != 0);
ebrus 0:0a673c671a56 314
ebrus 0:0a673c671a56 315 /* Set SDADC to ready state */
ebrus 0:0a673c671a56 316 hsdadc->State = HAL_SDADC_STATE_READY;
ebrus 0:0a673c671a56 317
ebrus 0:0a673c671a56 318 /* Return HAL status */
ebrus 0:0a673c671a56 319 return HAL_OK;
ebrus 0:0a673c671a56 320 }
ebrus 0:0a673c671a56 321
ebrus 0:0a673c671a56 322 /**
ebrus 0:0a673c671a56 323 * @brief De-initializes the SDADC.
ebrus 0:0a673c671a56 324 * @param hsdadc : SDADC handle.
ebrus 0:0a673c671a56 325 * @retval HAL status.
ebrus 0:0a673c671a56 326 */
ebrus 0:0a673c671a56 327 HAL_StatusTypeDef HAL_SDADC_DeInit(SDADC_HandleTypeDef* hsdadc)
ebrus 0:0a673c671a56 328 {
ebrus 0:0a673c671a56 329 /* Check parameters */
ebrus 0:0a673c671a56 330 assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
ebrus 0:0a673c671a56 331
ebrus 0:0a673c671a56 332 /* Check SDADC handle */
ebrus 0:0a673c671a56 333 if(hsdadc == NULL)
ebrus 0:0a673c671a56 334 {
ebrus 0:0a673c671a56 335 return HAL_ERROR;
ebrus 0:0a673c671a56 336 }
ebrus 0:0a673c671a56 337
ebrus 0:0a673c671a56 338 /* Disable the SDADC */
ebrus 0:0a673c671a56 339 hsdadc->Instance->CR2 &= ~(SDADC_CR2_ADON);
ebrus 0:0a673c671a56 340
ebrus 0:0a673c671a56 341 /* Reset all registers */
ebrus 0:0a673c671a56 342 hsdadc->Instance->CR1 = 0x00000000;
ebrus 0:0a673c671a56 343 hsdadc->Instance->CR2 = 0x00000000;
ebrus 0:0a673c671a56 344 hsdadc->Instance->JCHGR = 0x00000001;
ebrus 0:0a673c671a56 345 hsdadc->Instance->CONF0R = 0x00000000;
ebrus 0:0a673c671a56 346 hsdadc->Instance->CONF1R = 0x00000000;
ebrus 0:0a673c671a56 347 hsdadc->Instance->CONF2R = 0x00000000;
ebrus 0:0a673c671a56 348 hsdadc->Instance->CONFCHR1 = 0x00000000;
ebrus 0:0a673c671a56 349 hsdadc->Instance->CONFCHR2 = 0x00000000;
ebrus 0:0a673c671a56 350
ebrus 0:0a673c671a56 351 /* Call MSP deinit function */
ebrus 0:0a673c671a56 352 HAL_SDADC_MspDeInit(hsdadc);
ebrus 0:0a673c671a56 353
ebrus 0:0a673c671a56 354 /* Set SDADC in reset state */
ebrus 0:0a673c671a56 355 hsdadc->State = HAL_SDADC_STATE_RESET;
ebrus 0:0a673c671a56 356
ebrus 0:0a673c671a56 357 /* Return function status */
ebrus 0:0a673c671a56 358 return HAL_OK;
ebrus 0:0a673c671a56 359 }
ebrus 0:0a673c671a56 360
ebrus 0:0a673c671a56 361 /**
ebrus 0:0a673c671a56 362 * @brief Initializes the SDADC MSP.
ebrus 0:0a673c671a56 363 * @param hsdadc : SDADC handle
ebrus 0:0a673c671a56 364 * @retval None
ebrus 0:0a673c671a56 365 */
ebrus 0:0a673c671a56 366 __weak void HAL_SDADC_MspInit(SDADC_HandleTypeDef* hsdadc)
ebrus 0:0a673c671a56 367 {
ebrus 0:0a673c671a56 368 /* NOTE : This function should not be modified, when the callback is needed,
ebrus 0:0a673c671a56 369 the HAL_SDADC_MspInit could be implemented in the user file.
ebrus 0:0a673c671a56 370 */
ebrus 0:0a673c671a56 371 }
ebrus 0:0a673c671a56 372
ebrus 0:0a673c671a56 373 /**
ebrus 0:0a673c671a56 374 * @brief De-initializes the SDADC MSP.
ebrus 0:0a673c671a56 375 * @param hsdadc : SDADC handle
ebrus 0:0a673c671a56 376 * @retval None
ebrus 0:0a673c671a56 377 */
ebrus 0:0a673c671a56 378 __weak void HAL_SDADC_MspDeInit(SDADC_HandleTypeDef* hsdadc)
ebrus 0:0a673c671a56 379 {
ebrus 0:0a673c671a56 380 /* NOTE : This function should not be modified, when the callback is needed,
ebrus 0:0a673c671a56 381 the HAL_SDADC_MspDeInit could be implemented in the user file.
ebrus 0:0a673c671a56 382 */
ebrus 0:0a673c671a56 383 }
ebrus 0:0a673c671a56 384
ebrus 0:0a673c671a56 385 /**
ebrus 0:0a673c671a56 386 * @}
ebrus 0:0a673c671a56 387 */
ebrus 0:0a673c671a56 388
ebrus 0:0a673c671a56 389 /** @defgroup SDADC_Group2 peripheral control functions
ebrus 0:0a673c671a56 390 * @brief Peripheral control functions
ebrus 0:0a673c671a56 391 *
ebrus 0:0a673c671a56 392 @verbatim
ebrus 0:0a673c671a56 393 ===============================================================================
ebrus 0:0a673c671a56 394 ##### Peripheral control functions #####
ebrus 0:0a673c671a56 395 ===============================================================================
ebrus 0:0a673c671a56 396 [..] This section provides functions allowing to:
ebrus 0:0a673c671a56 397 (+) Program on of the three different configurations for channels.
ebrus 0:0a673c671a56 398 (+) Associate channel to one of configurations.
ebrus 0:0a673c671a56 399 (+) Select regular and injected channels.
ebrus 0:0a673c671a56 400 (+) Enable/disable continuous mode for regular and injected conversions.
ebrus 0:0a673c671a56 401 (+) Select regular and injected triggers.
ebrus 0:0a673c671a56 402 (+) Select and configure injected external trigger.
ebrus 0:0a673c671a56 403 (+) Enable/disable delay addition for injected conversions.
ebrus 0:0a673c671a56 404 (+) Configure multimode.
ebrus 0:0a673c671a56 405
ebrus 0:0a673c671a56 406 @endverbatim
ebrus 0:0a673c671a56 407 * @{
ebrus 0:0a673c671a56 408 */
ebrus 0:0a673c671a56 409
ebrus 0:0a673c671a56 410 /**
ebrus 0:0a673c671a56 411 * @brief This function allows the user to set parameters for a configuration.
ebrus 0:0a673c671a56 412 * Parameters are input mode, common mode, gain and offset.
ebrus 0:0a673c671a56 413 * @note This function should be called only when SDADC instance is in idle state
ebrus 0:0a673c671a56 414 * (neither calibration nor regular or injected conversion ongoing)
ebrus 0:0a673c671a56 415 * @param hsdadc : SDADC handle.
ebrus 0:0a673c671a56 416 * @param ConfIndex : Index of configuration to modify.
ebrus 0:0a673c671a56 417 * This parameter can be a value of @ref SDADC_ConfIndex.
ebrus 0:0a673c671a56 418 * @param ConfParamStruct : Parameters to apply for this configuration.
ebrus 0:0a673c671a56 419 * @retval HAL status
ebrus 0:0a673c671a56 420 */
ebrus 0:0a673c671a56 421 HAL_StatusTypeDef HAL_SDADC_PrepareChannelConfig(SDADC_HandleTypeDef *hsdadc,
ebrus 0:0a673c671a56 422 uint32_t ConfIndex,
ebrus 0:0a673c671a56 423 SDADC_ConfParamTypeDef* ConfParamStruct)
ebrus 0:0a673c671a56 424 {
ebrus 0:0a673c671a56 425 HAL_StatusTypeDef status = HAL_OK;
ebrus 0:0a673c671a56 426 uint32_t tmp = 0;
ebrus 0:0a673c671a56 427
ebrus 0:0a673c671a56 428 /* Check parameters */
ebrus 0:0a673c671a56 429 assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
ebrus 0:0a673c671a56 430 assert_param(IS_SDADC_CONF_INDEX(ConfIndex));
ebrus 0:0a673c671a56 431 assert_param(ConfParamStruct != NULL);
ebrus 0:0a673c671a56 432 assert_param(IS_SDADC_INPUT_MODE(ConfParamStruct->InputMode));
ebrus 0:0a673c671a56 433 assert_param(IS_SDADC_GAIN(ConfParamStruct->Gain));
ebrus 0:0a673c671a56 434 assert_param(IS_SDADC_COMMON_MODE(ConfParamStruct->CommonMode));
ebrus 0:0a673c671a56 435 assert_param(IS_SDADC_OFFSET_VALUE(ConfParamStruct->Offset));
ebrus 0:0a673c671a56 436
ebrus 0:0a673c671a56 437 /* Check SDADC state is ready */
ebrus 0:0a673c671a56 438 if(hsdadc->State != HAL_SDADC_STATE_READY)
ebrus 0:0a673c671a56 439 {
ebrus 0:0a673c671a56 440 status = HAL_ERROR;
ebrus 0:0a673c671a56 441 }
ebrus 0:0a673c671a56 442 else
ebrus 0:0a673c671a56 443 {
ebrus 0:0a673c671a56 444 /* Enter init mode */
ebrus 0:0a673c671a56 445 if(SDADC_EnterInitMode(hsdadc) != HAL_OK)
ebrus 0:0a673c671a56 446 {
ebrus 0:0a673c671a56 447 /* Set SDADC in error state */
ebrus 0:0a673c671a56 448 hsdadc->State = HAL_SDADC_STATE_ERROR;
ebrus 0:0a673c671a56 449 status = HAL_TIMEOUT;
ebrus 0:0a673c671a56 450 }
ebrus 0:0a673c671a56 451 else
ebrus 0:0a673c671a56 452 {
ebrus 0:0a673c671a56 453 /* Program configuration register with parameters */
ebrus 0:0a673c671a56 454 tmp = (uint32_t)((uint32_t)(hsdadc->Instance) + \
ebrus 0:0a673c671a56 455 SDADC_CONFREG_OFFSET + \
ebrus 0:0a673c671a56 456 (uint32_t)(ConfIndex << 2));
ebrus 0:0a673c671a56 457 *(__IO uint32_t *) (tmp) = (uint32_t) (ConfParamStruct->InputMode | \
ebrus 0:0a673c671a56 458 ConfParamStruct->Gain | \
ebrus 0:0a673c671a56 459 ConfParamStruct->CommonMode | \
ebrus 0:0a673c671a56 460 ConfParamStruct->Offset);
ebrus 0:0a673c671a56 461 /* Exit init mode */
ebrus 0:0a673c671a56 462 SDADC_ExitInitMode(hsdadc);
ebrus 0:0a673c671a56 463 }
ebrus 0:0a673c671a56 464 }
ebrus 0:0a673c671a56 465 /* Return function status */
ebrus 0:0a673c671a56 466 return status;
ebrus 0:0a673c671a56 467 }
ebrus 0:0a673c671a56 468
ebrus 0:0a673c671a56 469 /**
ebrus 0:0a673c671a56 470 * @brief This function allows the user to associate a channel with one of the
ebrus 0:0a673c671a56 471 * available configurations.
ebrus 0:0a673c671a56 472 * @note This function should be called only when SDADC instance is in idle state
ebrus 0:0a673c671a56 473 * (neither calibration nor regular or injected conversion ongoing)
ebrus 0:0a673c671a56 474 * @param hsdadc : SDADC handle.
ebrus 0:0a673c671a56 475 * @param Channel : Channel to associate with configuration.
ebrus 0:0a673c671a56 476 * This parameter can be a value of @ref SDADC_Channel_Selection.
ebrus 0:0a673c671a56 477 * @param ConfIndex : Index of configuration to associate with channel.
ebrus 0:0a673c671a56 478 * This parameter can be a value of @ref SDADC_ConfIndex.
ebrus 0:0a673c671a56 479 * @retval HAL status
ebrus 0:0a673c671a56 480 */
ebrus 0:0a673c671a56 481 HAL_StatusTypeDef HAL_SDADC_AssociateChannelConfig(SDADC_HandleTypeDef *hsdadc,
ebrus 0:0a673c671a56 482 uint32_t Channel,
ebrus 0:0a673c671a56 483 uint32_t ConfIndex)
ebrus 0:0a673c671a56 484 {
ebrus 0:0a673c671a56 485 HAL_StatusTypeDef status = HAL_OK;
ebrus 0:0a673c671a56 486 uint32_t channelnum = 0;
ebrus 0:0a673c671a56 487
ebrus 0:0a673c671a56 488 /* Check parameters */
ebrus 0:0a673c671a56 489 assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
ebrus 0:0a673c671a56 490 assert_param(IS_SDADC_REGULAR_CHANNEL(Channel));
ebrus 0:0a673c671a56 491 assert_param(IS_SDADC_CONF_INDEX(ConfIndex));
ebrus 0:0a673c671a56 492
ebrus 0:0a673c671a56 493 /* Check SDADC state is ready */
ebrus 0:0a673c671a56 494 if(hsdadc->State != HAL_SDADC_STATE_READY)
ebrus 0:0a673c671a56 495 {
ebrus 0:0a673c671a56 496 status = HAL_ERROR;
ebrus 0:0a673c671a56 497 }
ebrus 0:0a673c671a56 498 else
ebrus 0:0a673c671a56 499 {
ebrus 0:0a673c671a56 500 /* Enter init mode */
ebrus 0:0a673c671a56 501 if(SDADC_EnterInitMode(hsdadc) != HAL_OK)
ebrus 0:0a673c671a56 502 {
ebrus 0:0a673c671a56 503 /* Set SDADC in error state */
ebrus 0:0a673c671a56 504 hsdadc->State = HAL_SDADC_STATE_ERROR;
ebrus 0:0a673c671a56 505 status = HAL_TIMEOUT;
ebrus 0:0a673c671a56 506 }
ebrus 0:0a673c671a56 507 else
ebrus 0:0a673c671a56 508 {
ebrus 0:0a673c671a56 509 /* Program channel configuration register according parameters */
ebrus 0:0a673c671a56 510 if(Channel != SDADC_CHANNEL_8)
ebrus 0:0a673c671a56 511 {
ebrus 0:0a673c671a56 512 /* Get channel number */
ebrus 0:0a673c671a56 513 channelnum = (uint32_t)(Channel>>16);
ebrus 0:0a673c671a56 514
ebrus 0:0a673c671a56 515 /* Set the channel configuration */
ebrus 0:0a673c671a56 516 hsdadc->Instance->CONFCHR1 &= (uint32_t) ~(SDADC_CONFCHR1_CONFCH0 << (channelnum << 2));
ebrus 0:0a673c671a56 517 hsdadc->Instance->CONFCHR1 |= (uint32_t) (ConfIndex << (channelnum << 2));
ebrus 0:0a673c671a56 518 }
ebrus 0:0a673c671a56 519 else
ebrus 0:0a673c671a56 520 {
ebrus 0:0a673c671a56 521 hsdadc->Instance->CONFCHR2 = (uint32_t) (ConfIndex);
ebrus 0:0a673c671a56 522 }
ebrus 0:0a673c671a56 523 /* Exit init mode */
ebrus 0:0a673c671a56 524 SDADC_ExitInitMode(hsdadc);
ebrus 0:0a673c671a56 525 }
ebrus 0:0a673c671a56 526 }
ebrus 0:0a673c671a56 527 /* Return function status */
ebrus 0:0a673c671a56 528 return status;
ebrus 0:0a673c671a56 529 }
ebrus 0:0a673c671a56 530
ebrus 0:0a673c671a56 531 /**
ebrus 0:0a673c671a56 532 * @brief This function allows to select channel for regular conversion and
ebrus 0:0a673c671a56 533 * to enable/disable continuous mode for regular conversion.
ebrus 0:0a673c671a56 534 * @param hsdadc : SDADC handle.
ebrus 0:0a673c671a56 535 * @param Channel : Channel for regular conversion.
ebrus 0:0a673c671a56 536 * This parameter can be a value of @ref SDADC_Channel_Selection.
ebrus 0:0a673c671a56 537 * @param ContinuousMode : Enable/disable continuous mode for regular conversion.
ebrus 0:0a673c671a56 538 * This parameter can be a value of @ref SDADC_ContinuousMode.
ebrus 0:0a673c671a56 539 * @retval HAL status
ebrus 0:0a673c671a56 540 */
ebrus 0:0a673c671a56 541 HAL_StatusTypeDef HAL_SDADC_ConfigChannel(SDADC_HandleTypeDef *hsdadc,
ebrus 0:0a673c671a56 542 uint32_t Channel,
ebrus 0:0a673c671a56 543 uint32_t ContinuousMode)
ebrus 0:0a673c671a56 544 {
ebrus 0:0a673c671a56 545 HAL_StatusTypeDef status = HAL_OK;
ebrus 0:0a673c671a56 546
ebrus 0:0a673c671a56 547 /* Check parameters */
ebrus 0:0a673c671a56 548 assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
ebrus 0:0a673c671a56 549 assert_param(IS_SDADC_REGULAR_CHANNEL(Channel));
ebrus 0:0a673c671a56 550 assert_param(IS_SDADC_CONTINUOUS_MODE(ContinuousMode));
ebrus 0:0a673c671a56 551
ebrus 0:0a673c671a56 552 /* Check SDADC state */
ebrus 0:0a673c671a56 553 if((hsdadc->State != HAL_SDADC_STATE_RESET) && (hsdadc->State != HAL_SDADC_STATE_ERROR))
ebrus 0:0a673c671a56 554 {
ebrus 0:0a673c671a56 555 /* Set RCH[3:0] and RCONT bits in SDADC_CR2 */
ebrus 0:0a673c671a56 556 hsdadc->Instance->CR2 &= (uint32_t) ~(SDADC_CR2_RCH | SDADC_CR2_RCONT);
ebrus 0:0a673c671a56 557 if(ContinuousMode == SDADC_CONTINUOUS_CONV_ON)
ebrus 0:0a673c671a56 558 {
ebrus 0:0a673c671a56 559 hsdadc->Instance->CR2 |= (uint32_t) ((Channel & SDADC_MSB_MASK) | SDADC_CR2_RCONT);
ebrus 0:0a673c671a56 560 }
ebrus 0:0a673c671a56 561 else
ebrus 0:0a673c671a56 562 {
ebrus 0:0a673c671a56 563 hsdadc->Instance->CR2 |= (uint32_t) ((Channel & SDADC_MSB_MASK));
ebrus 0:0a673c671a56 564 }
ebrus 0:0a673c671a56 565 /* Store continuous mode information */
ebrus 0:0a673c671a56 566 hsdadc->RegularContMode = ContinuousMode;
ebrus 0:0a673c671a56 567 }
ebrus 0:0a673c671a56 568 else
ebrus 0:0a673c671a56 569 {
ebrus 0:0a673c671a56 570 status = HAL_ERROR;
ebrus 0:0a673c671a56 571 }
ebrus 0:0a673c671a56 572 /* Return function status */
ebrus 0:0a673c671a56 573 return status;
ebrus 0:0a673c671a56 574 }
ebrus 0:0a673c671a56 575
ebrus 0:0a673c671a56 576 /**
ebrus 0:0a673c671a56 577 * @brief This function allows to select channels for injected conversion and
ebrus 0:0a673c671a56 578 * to enable/disable continuous mode for injected conversion.
ebrus 0:0a673c671a56 579 * @param hsdadc : SDADC handle.
ebrus 0:0a673c671a56 580 * @param Channel : Channels for injected conversion.
ebrus 0:0a673c671a56 581 * This parameter can be a values combination of @ref SDADC_Channel_Selection.
ebrus 0:0a673c671a56 582 * @param ContinuousMode : Enable/disable continuous mode for injected conversion.
ebrus 0:0a673c671a56 583 * This parameter can be a value of @ref SDADC_ContinuousMode.
ebrus 0:0a673c671a56 584 * @retval HAL status
ebrus 0:0a673c671a56 585 */
ebrus 0:0a673c671a56 586 HAL_StatusTypeDef HAL_SDADC_InjectedConfigChannel(SDADC_HandleTypeDef *hsdadc,
ebrus 0:0a673c671a56 587 uint32_t Channel,
ebrus 0:0a673c671a56 588 uint32_t ContinuousMode)
ebrus 0:0a673c671a56 589 {
ebrus 0:0a673c671a56 590 HAL_StatusTypeDef status = HAL_OK;
ebrus 0:0a673c671a56 591
ebrus 0:0a673c671a56 592 /* Check parameters */
ebrus 0:0a673c671a56 593 assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
ebrus 0:0a673c671a56 594 assert_param(IS_SDADC_INJECTED_CHANNEL(Channel));
ebrus 0:0a673c671a56 595 assert_param(IS_SDADC_CONTINUOUS_MODE(ContinuousMode));
ebrus 0:0a673c671a56 596
ebrus 0:0a673c671a56 597 /* Check SDADC state */
ebrus 0:0a673c671a56 598 if((hsdadc->State != HAL_SDADC_STATE_RESET) && (hsdadc->State != HAL_SDADC_STATE_ERROR))
ebrus 0:0a673c671a56 599 {
ebrus 0:0a673c671a56 600 /* Set JCHG[8:0] bits in SDADC_JCHG */
ebrus 0:0a673c671a56 601 hsdadc->Instance->JCHGR = (uint32_t) (Channel & SDADC_LSB_MASK);
ebrus 0:0a673c671a56 602 /* Set or clear JCONT bit in SDADC_CR2 */
ebrus 0:0a673c671a56 603 if(ContinuousMode == SDADC_CONTINUOUS_CONV_ON)
ebrus 0:0a673c671a56 604 {
ebrus 0:0a673c671a56 605 hsdadc->Instance->CR2 |= SDADC_CR2_JCONT;
ebrus 0:0a673c671a56 606 }
ebrus 0:0a673c671a56 607 else
ebrus 0:0a673c671a56 608 {
ebrus 0:0a673c671a56 609 hsdadc->Instance->CR2 &= ~(SDADC_CR2_JCONT);
ebrus 0:0a673c671a56 610 }
ebrus 0:0a673c671a56 611 /* Store continuous mode information */
ebrus 0:0a673c671a56 612 hsdadc->InjectedContMode = ContinuousMode;
ebrus 0:0a673c671a56 613 /* Store number of injected channels */
ebrus 0:0a673c671a56 614 hsdadc->InjectedChannelsNbr = SDADC_GetInjChannelsNbr(Channel);
ebrus 0:0a673c671a56 615 }
ebrus 0:0a673c671a56 616 else
ebrus 0:0a673c671a56 617 {
ebrus 0:0a673c671a56 618 status = HAL_ERROR;
ebrus 0:0a673c671a56 619 }
ebrus 0:0a673c671a56 620 /* Return function status */
ebrus 0:0a673c671a56 621 return status;
ebrus 0:0a673c671a56 622 }
ebrus 0:0a673c671a56 623
ebrus 0:0a673c671a56 624 /**
ebrus 0:0a673c671a56 625 * @brief This function allows to select trigger for regular conversions.
ebrus 0:0a673c671a56 626 * @note This function should not be called if regular conversion is ongoing.
ebrus 0:0a673c671a56 627 * @param hsdadc : SDADC handle.
ebrus 0:0a673c671a56 628 * @param Trigger : Trigger for regular conversions.
ebrus 0:0a673c671a56 629 * This parameter can be one of the following value :
ebrus 0:0a673c671a56 630 * @arg SDADC_SOFTWARE_TRIGGER : Software trigger.
ebrus 0:0a673c671a56 631 * @arg SDADC_SYNCHRONOUS_TRIGGER : Synchronous with SDADC1 (only for SDADC2 and SDADC3).
ebrus 0:0a673c671a56 632 * @retval HAL status
ebrus 0:0a673c671a56 633 */
ebrus 0:0a673c671a56 634 HAL_StatusTypeDef HAL_SDADC_SelectRegularTrigger(SDADC_HandleTypeDef *hsdadc, uint32_t Trigger)
ebrus 0:0a673c671a56 635 {
ebrus 0:0a673c671a56 636 HAL_StatusTypeDef status = HAL_OK;
ebrus 0:0a673c671a56 637
ebrus 0:0a673c671a56 638 /* Check parameters */
ebrus 0:0a673c671a56 639 assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
ebrus 0:0a673c671a56 640 assert_param(IS_SDADC_REGULAR_TRIGGER(Trigger));
ebrus 0:0a673c671a56 641
ebrus 0:0a673c671a56 642 /* Check parameters compatibility */
ebrus 0:0a673c671a56 643 if((hsdadc->Instance == SDADC1) && (Trigger == SDADC_SYNCHRONOUS_TRIGGER))
ebrus 0:0a673c671a56 644 {
ebrus 0:0a673c671a56 645 status = HAL_ERROR;
ebrus 0:0a673c671a56 646 }
ebrus 0:0a673c671a56 647 /* Check SDADC state */
ebrus 0:0a673c671a56 648 else if((hsdadc->State == HAL_SDADC_STATE_READY) || \
ebrus 0:0a673c671a56 649 (hsdadc->State == HAL_SDADC_STATE_CALIB) || \
ebrus 0:0a673c671a56 650 (hsdadc->State == HAL_SDADC_STATE_INJ))
ebrus 0:0a673c671a56 651 {
ebrus 0:0a673c671a56 652 /* Store regular trigger information */
ebrus 0:0a673c671a56 653 hsdadc->RegularTrigger = Trigger;
ebrus 0:0a673c671a56 654 }
ebrus 0:0a673c671a56 655 else
ebrus 0:0a673c671a56 656 {
ebrus 0:0a673c671a56 657 status = HAL_ERROR;
ebrus 0:0a673c671a56 658 }
ebrus 0:0a673c671a56 659 /* Return function status */
ebrus 0:0a673c671a56 660 return status;
ebrus 0:0a673c671a56 661 }
ebrus 0:0a673c671a56 662
ebrus 0:0a673c671a56 663 /**
ebrus 0:0a673c671a56 664 * @brief This function allows to select trigger for injected conversions.
ebrus 0:0a673c671a56 665 * @note This function should not be called if injected conversion is ongoing.
ebrus 0:0a673c671a56 666 * @param hsdadc : SDADC handle.
ebrus 0:0a673c671a56 667 * @param Trigger : Trigger for injected conversions.
ebrus 0:0a673c671a56 668 * This parameter can be one of the following value :
ebrus 0:0a673c671a56 669 * @arg SDADC_SOFTWARE_TRIGGER : Software trigger.
ebrus 0:0a673c671a56 670 * @arg SDADC_SYNCHRONOUS_TRIGGER : Synchronous with SDADC1 (only for SDADC2 and SDADC3).
ebrus 0:0a673c671a56 671 * @arg SDADC_EXTERNAL_TRIGGER : External trigger.
ebrus 0:0a673c671a56 672 * @retval HAL status
ebrus 0:0a673c671a56 673 */
ebrus 0:0a673c671a56 674 HAL_StatusTypeDef HAL_SDADC_SelectInjectedTrigger(SDADC_HandleTypeDef *hsdadc, uint32_t Trigger)
ebrus 0:0a673c671a56 675 {
ebrus 0:0a673c671a56 676 HAL_StatusTypeDef status = HAL_OK;
ebrus 0:0a673c671a56 677
ebrus 0:0a673c671a56 678 /* Check parameters */
ebrus 0:0a673c671a56 679 assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
ebrus 0:0a673c671a56 680 assert_param(IS_SDADC_INJECTED_TRIGGER(Trigger));
ebrus 0:0a673c671a56 681
ebrus 0:0a673c671a56 682 /* Check parameters compatibility */
ebrus 0:0a673c671a56 683 if((hsdadc->Instance == SDADC1) && (Trigger == SDADC_SYNCHRONOUS_TRIGGER))
ebrus 0:0a673c671a56 684 {
ebrus 0:0a673c671a56 685 status = HAL_ERROR;
ebrus 0:0a673c671a56 686 }
ebrus 0:0a673c671a56 687 /* Check SDADC state */
ebrus 0:0a673c671a56 688 else if((hsdadc->State == HAL_SDADC_STATE_READY) || \
ebrus 0:0a673c671a56 689 (hsdadc->State == HAL_SDADC_STATE_CALIB) || \
ebrus 0:0a673c671a56 690 (hsdadc->State == HAL_SDADC_STATE_REG))
ebrus 0:0a673c671a56 691 {
ebrus 0:0a673c671a56 692 /* Store regular trigger information */
ebrus 0:0a673c671a56 693 hsdadc->InjectedTrigger = Trigger;
ebrus 0:0a673c671a56 694 }
ebrus 0:0a673c671a56 695 else
ebrus 0:0a673c671a56 696 {
ebrus 0:0a673c671a56 697 status = HAL_ERROR;
ebrus 0:0a673c671a56 698 }
ebrus 0:0a673c671a56 699 /* Return function status */
ebrus 0:0a673c671a56 700 return status;
ebrus 0:0a673c671a56 701 }
ebrus 0:0a673c671a56 702
ebrus 0:0a673c671a56 703 /**
ebrus 0:0a673c671a56 704 * @brief This function allows to select and configure injected external trigger.
ebrus 0:0a673c671a56 705 * @note This function should be called only when SDADC instance is in idle state
ebrus 0:0a673c671a56 706 * (neither calibration nor regular or injected conversion ongoing)
ebrus 0:0a673c671a56 707 * @param hsdadc : SDADC handle.
ebrus 0:0a673c671a56 708 * @param InjectedExtTrigger : External trigger for injected conversions.
ebrus 0:0a673c671a56 709 * This parameter can be a value of @ref SDADC_InjectedExtTrigger.
ebrus 0:0a673c671a56 710 * @param ExtTriggerEdge : Edge of external injected trigger.
ebrus 0:0a673c671a56 711 * This parameter can be a value of @ref SDADC_ExtTriggerEdge.
ebrus 0:0a673c671a56 712 * @retval HAL status
ebrus 0:0a673c671a56 713 */
ebrus 0:0a673c671a56 714 HAL_StatusTypeDef HAL_SDADC_SelectInjectedExtTrigger(SDADC_HandleTypeDef *hsdadc,
ebrus 0:0a673c671a56 715 uint32_t InjectedExtTrigger,
ebrus 0:0a673c671a56 716 uint32_t ExtTriggerEdge)
ebrus 0:0a673c671a56 717 {
ebrus 0:0a673c671a56 718 HAL_StatusTypeDef status = HAL_OK;
ebrus 0:0a673c671a56 719
ebrus 0:0a673c671a56 720 /* Check parameters */
ebrus 0:0a673c671a56 721 assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
ebrus 0:0a673c671a56 722 assert_param(IS_SDADC_EXT_INJEC_TRIG(InjectedExtTrigger));
ebrus 0:0a673c671a56 723 assert_param(IS_SDADC_EXT_TRIG_EDGE(ExtTriggerEdge));
ebrus 0:0a673c671a56 724
ebrus 0:0a673c671a56 725 /* Check SDADC state */
ebrus 0:0a673c671a56 726 if(hsdadc->State == HAL_SDADC_STATE_READY)
ebrus 0:0a673c671a56 727 {
ebrus 0:0a673c671a56 728 /* Enter init mode */
ebrus 0:0a673c671a56 729 if(SDADC_EnterInitMode(hsdadc) != HAL_OK)
ebrus 0:0a673c671a56 730 {
ebrus 0:0a673c671a56 731 /* Set SDADC in error state */
ebrus 0:0a673c671a56 732 hsdadc->State = HAL_SDADC_STATE_ERROR;
ebrus 0:0a673c671a56 733 status = HAL_TIMEOUT;
ebrus 0:0a673c671a56 734 }
ebrus 0:0a673c671a56 735 else
ebrus 0:0a673c671a56 736 {
ebrus 0:0a673c671a56 737 /* Set JEXTSEL[2:0] bits in SDADC_CR2 register */
ebrus 0:0a673c671a56 738 hsdadc->Instance->CR2 &= ~(SDADC_CR2_JEXTSEL);
ebrus 0:0a673c671a56 739 hsdadc->Instance->CR2 |= InjectedExtTrigger;
ebrus 0:0a673c671a56 740
ebrus 0:0a673c671a56 741 /* Store external trigger edge information */
ebrus 0:0a673c671a56 742 hsdadc->ExtTriggerEdge = ExtTriggerEdge;
ebrus 0:0a673c671a56 743
ebrus 0:0a673c671a56 744 /* Exit init mode */
ebrus 0:0a673c671a56 745 SDADC_ExitInitMode(hsdadc);
ebrus 0:0a673c671a56 746 }
ebrus 0:0a673c671a56 747 }
ebrus 0:0a673c671a56 748 else
ebrus 0:0a673c671a56 749 {
ebrus 0:0a673c671a56 750 status = HAL_ERROR;
ebrus 0:0a673c671a56 751 }
ebrus 0:0a673c671a56 752 /* Return function status */
ebrus 0:0a673c671a56 753 return status;
ebrus 0:0a673c671a56 754 }
ebrus 0:0a673c671a56 755
ebrus 0:0a673c671a56 756 /**
ebrus 0:0a673c671a56 757 * @brief This function allows to enable/disable delay addition for injected conversions.
ebrus 0:0a673c671a56 758 * @note This function should be called only when SDADC instance is in idle state
ebrus 0:0a673c671a56 759 * (neither calibration nor regular or injected conversion ongoing)
ebrus 0:0a673c671a56 760 * @param hsdadc : SDADC handle.
ebrus 0:0a673c671a56 761 * @param InjectedDelay : Enable/disable delay for injected conversions.
ebrus 0:0a673c671a56 762 * This parameter can be a value of @ref SDADC_InjectedDelay.
ebrus 0:0a673c671a56 763 * @retval HAL status
ebrus 0:0a673c671a56 764 */
ebrus 0:0a673c671a56 765 HAL_StatusTypeDef HAL_SDADC_SelectInjectedDelay(SDADC_HandleTypeDef *hsdadc,
ebrus 0:0a673c671a56 766 uint32_t InjectedDelay)
ebrus 0:0a673c671a56 767 {
ebrus 0:0a673c671a56 768 HAL_StatusTypeDef status = HAL_OK;
ebrus 0:0a673c671a56 769
ebrus 0:0a673c671a56 770 /* Check parameters */
ebrus 0:0a673c671a56 771 assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
ebrus 0:0a673c671a56 772 assert_param(IS_SDADC_INJECTED_DELAY(InjectedDelay));
ebrus 0:0a673c671a56 773
ebrus 0:0a673c671a56 774 /* Check SDADC state */
ebrus 0:0a673c671a56 775 if(hsdadc->State == HAL_SDADC_STATE_READY)
ebrus 0:0a673c671a56 776 {
ebrus 0:0a673c671a56 777 /* Enter init mode */
ebrus 0:0a673c671a56 778 if(SDADC_EnterInitMode(hsdadc) != HAL_OK)
ebrus 0:0a673c671a56 779 {
ebrus 0:0a673c671a56 780 /* Set SDADC in error state */
ebrus 0:0a673c671a56 781 hsdadc->State = HAL_SDADC_STATE_ERROR;
ebrus 0:0a673c671a56 782 status = HAL_TIMEOUT;
ebrus 0:0a673c671a56 783 }
ebrus 0:0a673c671a56 784 else
ebrus 0:0a673c671a56 785 {
ebrus 0:0a673c671a56 786 /* Set JDS bit in SDADC_CR2 register */
ebrus 0:0a673c671a56 787 hsdadc->Instance->CR2 &= ~(SDADC_CR2_JDS);
ebrus 0:0a673c671a56 788 hsdadc->Instance->CR2 |= InjectedDelay;
ebrus 0:0a673c671a56 789
ebrus 0:0a673c671a56 790 /* Exit init mode */
ebrus 0:0a673c671a56 791 SDADC_ExitInitMode(hsdadc);
ebrus 0:0a673c671a56 792 }
ebrus 0:0a673c671a56 793 }
ebrus 0:0a673c671a56 794 else
ebrus 0:0a673c671a56 795 {
ebrus 0:0a673c671a56 796 status = HAL_ERROR;
ebrus 0:0a673c671a56 797 }
ebrus 0:0a673c671a56 798 /* Return function status */
ebrus 0:0a673c671a56 799 return status;
ebrus 0:0a673c671a56 800 }
ebrus 0:0a673c671a56 801
ebrus 0:0a673c671a56 802 /**
ebrus 0:0a673c671a56 803 * @brief This function allows to configure multimode for regular conversions.
ebrus 0:0a673c671a56 804 * @note This function should not be called if regular conversion is ongoing
ebrus 0:0a673c671a56 805 * and should be could only for SDADC1.
ebrus 0:0a673c671a56 806 * @param hsdadc : SDADC handle.
ebrus 0:0a673c671a56 807 * @param MultimodeType : Type of multimode for regular conversions.
ebrus 0:0a673c671a56 808 * This parameter can be a value of @ref SDADC_MultimodeType.
ebrus 0:0a673c671a56 809 * @retval HAL status
ebrus 0:0a673c671a56 810 */
ebrus 0:0a673c671a56 811 HAL_StatusTypeDef HAL_SDADC_MultiModeConfigChannel(SDADC_HandleTypeDef* hsdadc,
ebrus 0:0a673c671a56 812 uint32_t MultimodeType)
ebrus 0:0a673c671a56 813 {
ebrus 0:0a673c671a56 814 HAL_StatusTypeDef status = HAL_OK;
ebrus 0:0a673c671a56 815
ebrus 0:0a673c671a56 816 /* Check parameters */
ebrus 0:0a673c671a56 817 assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
ebrus 0:0a673c671a56 818 assert_param(IS_SDADC_MULTIMODE_TYPE(MultimodeType));
ebrus 0:0a673c671a56 819
ebrus 0:0a673c671a56 820 /* Check instance is SDADC1 */
ebrus 0:0a673c671a56 821 if(hsdadc->Instance != SDADC1)
ebrus 0:0a673c671a56 822 {
ebrus 0:0a673c671a56 823 status = HAL_ERROR;
ebrus 0:0a673c671a56 824 }
ebrus 0:0a673c671a56 825 /* Check SDADC state */
ebrus 0:0a673c671a56 826 else if((hsdadc->State == HAL_SDADC_STATE_READY) || \
ebrus 0:0a673c671a56 827 (hsdadc->State == HAL_SDADC_STATE_CALIB) || \
ebrus 0:0a673c671a56 828 (hsdadc->State == HAL_SDADC_STATE_INJ))
ebrus 0:0a673c671a56 829 {
ebrus 0:0a673c671a56 830 /* Store regular trigger information */
ebrus 0:0a673c671a56 831 hsdadc->RegularMultimode = MultimodeType;
ebrus 0:0a673c671a56 832 }
ebrus 0:0a673c671a56 833 else
ebrus 0:0a673c671a56 834 {
ebrus 0:0a673c671a56 835 status = HAL_ERROR;
ebrus 0:0a673c671a56 836 }
ebrus 0:0a673c671a56 837 /* Return function status */
ebrus 0:0a673c671a56 838 return status;
ebrus 0:0a673c671a56 839 }
ebrus 0:0a673c671a56 840
ebrus 0:0a673c671a56 841 /**
ebrus 0:0a673c671a56 842 * @brief This function allows to configure multimode for injected conversions.
ebrus 0:0a673c671a56 843 * @note This function should not be called if injected conversion is ongoing
ebrus 0:0a673c671a56 844 * and should be could only for SDADC1.
ebrus 0:0a673c671a56 845 * @param hsdadc : SDADC handle.
ebrus 0:0a673c671a56 846 * @param MultimodeType : Type of multimode for injected conversions.
ebrus 0:0a673c671a56 847 * This parameter can be a value of @ref SDADC_MultimodeType.
ebrus 0:0a673c671a56 848 * @retval HAL status
ebrus 0:0a673c671a56 849 */
ebrus 0:0a673c671a56 850 HAL_StatusTypeDef HAL_SDADC_InjectedMultiModeConfigChannel(SDADC_HandleTypeDef* hsdadc,
ebrus 0:0a673c671a56 851 uint32_t MultimodeType)
ebrus 0:0a673c671a56 852 {
ebrus 0:0a673c671a56 853 HAL_StatusTypeDef status = HAL_OK;
ebrus 0:0a673c671a56 854
ebrus 0:0a673c671a56 855 /* Check parameters */
ebrus 0:0a673c671a56 856 assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
ebrus 0:0a673c671a56 857 assert_param(IS_SDADC_MULTIMODE_TYPE(MultimodeType));
ebrus 0:0a673c671a56 858
ebrus 0:0a673c671a56 859 /* Check instance is SDADC1 */
ebrus 0:0a673c671a56 860 if(hsdadc->Instance != SDADC1)
ebrus 0:0a673c671a56 861 {
ebrus 0:0a673c671a56 862 status = HAL_ERROR;
ebrus 0:0a673c671a56 863 }
ebrus 0:0a673c671a56 864 /* Check SDADC state */
ebrus 0:0a673c671a56 865 else if((hsdadc->State == HAL_SDADC_STATE_READY) || \
ebrus 0:0a673c671a56 866 (hsdadc->State == HAL_SDADC_STATE_CALIB) || \
ebrus 0:0a673c671a56 867 (hsdadc->State == HAL_SDADC_STATE_REG))
ebrus 0:0a673c671a56 868 {
ebrus 0:0a673c671a56 869 /* Store regular trigger information */
ebrus 0:0a673c671a56 870 hsdadc->InjectedMultimode = MultimodeType;
ebrus 0:0a673c671a56 871 }
ebrus 0:0a673c671a56 872 else
ebrus 0:0a673c671a56 873 {
ebrus 0:0a673c671a56 874 status = HAL_ERROR;
ebrus 0:0a673c671a56 875 }
ebrus 0:0a673c671a56 876 /* Return function status */
ebrus 0:0a673c671a56 877 return status;
ebrus 0:0a673c671a56 878 }
ebrus 0:0a673c671a56 879
ebrus 0:0a673c671a56 880 /**
ebrus 0:0a673c671a56 881 * @}
ebrus 0:0a673c671a56 882 */
ebrus 0:0a673c671a56 883
ebrus 0:0a673c671a56 884 /** @defgroup SDADC_Group3 I/O operation functions
ebrus 0:0a673c671a56 885 * @brief I/O operation Control functions
ebrus 0:0a673c671a56 886 *
ebrus 0:0a673c671a56 887 @verbatim
ebrus 0:0a673c671a56 888 ===============================================================================
ebrus 0:0a673c671a56 889 ##### I/O operation functions #####
ebrus 0:0a673c671a56 890 ===============================================================================
ebrus 0:0a673c671a56 891 [..] This section provides functions allowing to:
ebrus 0:0a673c671a56 892 (+) Start calibration.
ebrus 0:0a673c671a56 893 (+) Poll for the end of calibration.
ebrus 0:0a673c671a56 894 (+) Start calibration and enable interrupt.
ebrus 0:0a673c671a56 895 (+) Start conversion of regular/injected channel.
ebrus 0:0a673c671a56 896 (+) Poll for the end of regular/injected conversion.
ebrus 0:0a673c671a56 897 (+) Stop conversion of regular/injected channel.
ebrus 0:0a673c671a56 898 (+) Start conversion of regular/injected channel and enable interrupt.
ebrus 0:0a673c671a56 899 (+) Stop conversion of regular/injected channel and disable interrupt.
ebrus 0:0a673c671a56 900 (+) Start conversion of regular/injected channel and enable DMA transfer.
ebrus 0:0a673c671a56 901 (+) Stop conversion of regular/injected channel and disable DMA transfer.
ebrus 0:0a673c671a56 902 (+) Start multimode and enable DMA transfer for regular/injected conversion.
ebrus 0:0a673c671a56 903 (+) Stop multimode and disable DMA transfer for regular/injected conversion..
ebrus 0:0a673c671a56 904 (+) Get result of regular channel conversion.
ebrus 0:0a673c671a56 905 (+) Get result of injected channel conversion.
ebrus 0:0a673c671a56 906 (+) Get result of multimode conversion.
ebrus 0:0a673c671a56 907 (+) Handle SDADC interrupt request.
ebrus 0:0a673c671a56 908 (+) Callbacks for calibration and regular/injected conversions.
ebrus 0:0a673c671a56 909
ebrus 0:0a673c671a56 910 @endverbatim
ebrus 0:0a673c671a56 911 * @{
ebrus 0:0a673c671a56 912 */
ebrus 0:0a673c671a56 913
ebrus 0:0a673c671a56 914 /**
ebrus 0:0a673c671a56 915 * @brief This function allows to start calibration in polling mode.
ebrus 0:0a673c671a56 916 * @note This function should be called only when SDADC instance is in idle state
ebrus 0:0a673c671a56 917 * (neither calibration nor regular or injected conversion ongoing).
ebrus 0:0a673c671a56 918 * @param hsdadc : SDADC handle.
ebrus 0:0a673c671a56 919 * @param CalibrationSequence : Calibration sequence.
ebrus 0:0a673c671a56 920 * This parameter can be a value of @ref SDADC_CalibrationSequence.
ebrus 0:0a673c671a56 921 * @retval HAL status
ebrus 0:0a673c671a56 922 */
ebrus 0:0a673c671a56 923 HAL_StatusTypeDef HAL_SDADC_CalibrationStart(SDADC_HandleTypeDef *hsdadc,
ebrus 0:0a673c671a56 924 uint32_t CalibrationSequence)
ebrus 0:0a673c671a56 925 {
ebrus 0:0a673c671a56 926 HAL_StatusTypeDef status = HAL_OK;
ebrus 0:0a673c671a56 927
ebrus 0:0a673c671a56 928 /* Check parameters */
ebrus 0:0a673c671a56 929 assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
ebrus 0:0a673c671a56 930 assert_param(IS_SDADC_CALIB_SEQUENCE(CalibrationSequence));
ebrus 0:0a673c671a56 931
ebrus 0:0a673c671a56 932 /* Check SDADC state */
ebrus 0:0a673c671a56 933 if(hsdadc->State == HAL_SDADC_STATE_READY)
ebrus 0:0a673c671a56 934 {
ebrus 0:0a673c671a56 935 /* Enter init mode */
ebrus 0:0a673c671a56 936 if(SDADC_EnterInitMode(hsdadc) != HAL_OK)
ebrus 0:0a673c671a56 937 {
ebrus 0:0a673c671a56 938 /* Set SDADC in error state */
ebrus 0:0a673c671a56 939 hsdadc->State = HAL_SDADC_STATE_ERROR;
ebrus 0:0a673c671a56 940 status = HAL_TIMEOUT;
ebrus 0:0a673c671a56 941 }
ebrus 0:0a673c671a56 942 else
ebrus 0:0a673c671a56 943 {
ebrus 0:0a673c671a56 944 /* Set CALIBCNT[1:0] bits in SDADC_CR2 register */
ebrus 0:0a673c671a56 945 hsdadc->Instance->CR2 &= ~(SDADC_CR2_CALIBCNT);
ebrus 0:0a673c671a56 946 hsdadc->Instance->CR2 |= CalibrationSequence;
ebrus 0:0a673c671a56 947
ebrus 0:0a673c671a56 948 /* Exit init mode */
ebrus 0:0a673c671a56 949 SDADC_ExitInitMode(hsdadc);
ebrus 0:0a673c671a56 950
ebrus 0:0a673c671a56 951 /* Set STARTCALIB in SDADC_CR2 */
ebrus 0:0a673c671a56 952 hsdadc->Instance->CR2 |= SDADC_CR2_STARTCALIB;
ebrus 0:0a673c671a56 953
ebrus 0:0a673c671a56 954 /* Set SDADC in calibration state */
ebrus 0:0a673c671a56 955 hsdadc->State = HAL_SDADC_STATE_CALIB;
ebrus 0:0a673c671a56 956 }
ebrus 0:0a673c671a56 957 }
ebrus 0:0a673c671a56 958 else
ebrus 0:0a673c671a56 959 {
ebrus 0:0a673c671a56 960 status = HAL_ERROR;
ebrus 0:0a673c671a56 961 }
ebrus 0:0a673c671a56 962 /* Return function status */
ebrus 0:0a673c671a56 963 return status;
ebrus 0:0a673c671a56 964 }
ebrus 0:0a673c671a56 965
ebrus 0:0a673c671a56 966 /**
ebrus 0:0a673c671a56 967 * @brief This function allows to poll for the end of calibration.
ebrus 0:0a673c671a56 968 * @note This function should be called only if calibration is ongoing.
ebrus 0:0a673c671a56 969 * @param hsdadc : SDADC handle.
ebrus 0:0a673c671a56 970 * @param Timeout : Timeout value in milliseconds.
ebrus 0:0a673c671a56 971 * @retval HAL status
ebrus 0:0a673c671a56 972 */
ebrus 0:0a673c671a56 973 HAL_StatusTypeDef HAL_SDADC_PollForCalibEvent(SDADC_HandleTypeDef* hsdadc, uint32_t Timeout)
ebrus 0:0a673c671a56 974 {
ebrus 0:0a673c671a56 975 uint32_t tickstart;
ebrus 0:0a673c671a56 976
ebrus 0:0a673c671a56 977 /* Check parameters */
ebrus 0:0a673c671a56 978 assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
ebrus 0:0a673c671a56 979
ebrus 0:0a673c671a56 980 /* Check SDADC state */
ebrus 0:0a673c671a56 981 if(hsdadc->State != HAL_SDADC_STATE_CALIB)
ebrus 0:0a673c671a56 982 {
ebrus 0:0a673c671a56 983 /* Return error status */
ebrus 0:0a673c671a56 984 return HAL_ERROR;
ebrus 0:0a673c671a56 985 }
ebrus 0:0a673c671a56 986 else
ebrus 0:0a673c671a56 987 {
ebrus 0:0a673c671a56 988 /* Get timeout */
ebrus 0:0a673c671a56 989 tickstart = HAL_GetTick();
ebrus 0:0a673c671a56 990
ebrus 0:0a673c671a56 991 /* Wait EOCALF bit in SDADC_ISR register */
ebrus 0:0a673c671a56 992 while((hsdadc->Instance->ISR & SDADC_ISR_EOCALF) != SDADC_ISR_EOCALF)
ebrus 0:0a673c671a56 993 {
ebrus 0:0a673c671a56 994 /* Check the Timeout */
ebrus 0:0a673c671a56 995 if(Timeout != HAL_MAX_DELAY)
ebrus 0:0a673c671a56 996 {
ebrus 0:0a673c671a56 997 if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
ebrus 0:0a673c671a56 998 {
ebrus 0:0a673c671a56 999 /* Return timeout status */
ebrus 0:0a673c671a56 1000 return HAL_TIMEOUT;
ebrus 0:0a673c671a56 1001 }
ebrus 0:0a673c671a56 1002 }
ebrus 0:0a673c671a56 1003 }
ebrus 0:0a673c671a56 1004 /* Set CLREOCALF bit in SDADC_CLRISR register */
ebrus 0:0a673c671a56 1005 hsdadc->Instance->CLRISR |= SDADC_ISR_CLREOCALF;
ebrus 0:0a673c671a56 1006
ebrus 0:0a673c671a56 1007 /* Set SDADC in ready state */
ebrus 0:0a673c671a56 1008 hsdadc->State = HAL_SDADC_STATE_READY;
ebrus 0:0a673c671a56 1009
ebrus 0:0a673c671a56 1010 /* Return function status */
ebrus 0:0a673c671a56 1011 return HAL_OK;
ebrus 0:0a673c671a56 1012 }
ebrus 0:0a673c671a56 1013 }
ebrus 0:0a673c671a56 1014
ebrus 0:0a673c671a56 1015 /**
ebrus 0:0a673c671a56 1016 * @brief This function allows to start calibration in interrupt mode.
ebrus 0:0a673c671a56 1017 * @note This function should be called only when SDADC instance is in idle state
ebrus 0:0a673c671a56 1018 * (neither calibration nor regular or injected conversion ongoing).
ebrus 0:0a673c671a56 1019 * @param hsdadc : SDADC handle.
ebrus 0:0a673c671a56 1020 * @param CalibrationSequence : Calibration sequence.
ebrus 0:0a673c671a56 1021 * This parameter can be a value of @ref SDADC_CalibrationSequence.
ebrus 0:0a673c671a56 1022 * @retval HAL status
ebrus 0:0a673c671a56 1023 */
ebrus 0:0a673c671a56 1024 HAL_StatusTypeDef HAL_SDADC_CalibrationStart_IT(SDADC_HandleTypeDef *hsdadc,
ebrus 0:0a673c671a56 1025 uint32_t CalibrationSequence)
ebrus 0:0a673c671a56 1026 {
ebrus 0:0a673c671a56 1027 HAL_StatusTypeDef status = HAL_OK;
ebrus 0:0a673c671a56 1028
ebrus 0:0a673c671a56 1029 /* Check parameters */
ebrus 0:0a673c671a56 1030 assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
ebrus 0:0a673c671a56 1031 assert_param(IS_SDADC_CALIB_SEQUENCE(CalibrationSequence));
ebrus 0:0a673c671a56 1032
ebrus 0:0a673c671a56 1033 /* Check SDADC state */
ebrus 0:0a673c671a56 1034 if(hsdadc->State == HAL_SDADC_STATE_READY)
ebrus 0:0a673c671a56 1035 {
ebrus 0:0a673c671a56 1036 /* Enter init mode */
ebrus 0:0a673c671a56 1037 if(SDADC_EnterInitMode(hsdadc) != HAL_OK)
ebrus 0:0a673c671a56 1038 {
ebrus 0:0a673c671a56 1039 /* Set SDADC in error state */
ebrus 0:0a673c671a56 1040 hsdadc->State = HAL_SDADC_STATE_ERROR;
ebrus 0:0a673c671a56 1041 status = HAL_TIMEOUT;
ebrus 0:0a673c671a56 1042 }
ebrus 0:0a673c671a56 1043 else
ebrus 0:0a673c671a56 1044 {
ebrus 0:0a673c671a56 1045 /* Set CALIBCNT[1:0] bits in SDADC_CR2 register */
ebrus 0:0a673c671a56 1046 hsdadc->Instance->CR2 &= ~(SDADC_CR2_CALIBCNT);
ebrus 0:0a673c671a56 1047 hsdadc->Instance->CR2 |= CalibrationSequence;
ebrus 0:0a673c671a56 1048
ebrus 0:0a673c671a56 1049 /* Exit init mode */
ebrus 0:0a673c671a56 1050 SDADC_ExitInitMode(hsdadc);
ebrus 0:0a673c671a56 1051
ebrus 0:0a673c671a56 1052 /* Set EOCALIE bit in SDADC_CR1 register */
ebrus 0:0a673c671a56 1053 hsdadc->Instance->CR1 |= SDADC_CR1_EOCALIE;
ebrus 0:0a673c671a56 1054
ebrus 0:0a673c671a56 1055 /* Set STARTCALIB in SDADC_CR2 */
ebrus 0:0a673c671a56 1056 hsdadc->Instance->CR2 |= SDADC_CR2_STARTCALIB;
ebrus 0:0a673c671a56 1057
ebrus 0:0a673c671a56 1058 /* Set SDADC in calibration state */
ebrus 0:0a673c671a56 1059 hsdadc->State = HAL_SDADC_STATE_CALIB;
ebrus 0:0a673c671a56 1060 }
ebrus 0:0a673c671a56 1061 }
ebrus 0:0a673c671a56 1062 else
ebrus 0:0a673c671a56 1063 {
ebrus 0:0a673c671a56 1064 status = HAL_ERROR;
ebrus 0:0a673c671a56 1065 }
ebrus 0:0a673c671a56 1066 /* Return function status */
ebrus 0:0a673c671a56 1067 return status;
ebrus 0:0a673c671a56 1068 }
ebrus 0:0a673c671a56 1069
ebrus 0:0a673c671a56 1070 /**
ebrus 0:0a673c671a56 1071 * @brief This function allows to start regular conversion in polling mode.
ebrus 0:0a673c671a56 1072 * @note This function should be called only when SDADC instance is in idle state
ebrus 0:0a673c671a56 1073 * or if injected conversion is ongoing.
ebrus 0:0a673c671a56 1074 * @param hsdadc : SDADC handle.
ebrus 0:0a673c671a56 1075 * @retval HAL status
ebrus 0:0a673c671a56 1076 */
ebrus 0:0a673c671a56 1077 HAL_StatusTypeDef HAL_SDADC_Start(SDADC_HandleTypeDef *hsdadc)
ebrus 0:0a673c671a56 1078 {
ebrus 0:0a673c671a56 1079 HAL_StatusTypeDef status = HAL_OK;
ebrus 0:0a673c671a56 1080
ebrus 0:0a673c671a56 1081 /* Check parameters */
ebrus 0:0a673c671a56 1082 assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
ebrus 0:0a673c671a56 1083
ebrus 0:0a673c671a56 1084 /* Check SDADC state */
ebrus 0:0a673c671a56 1085 if((hsdadc->State == HAL_SDADC_STATE_READY) || \
ebrus 0:0a673c671a56 1086 (hsdadc->State == HAL_SDADC_STATE_INJ))
ebrus 0:0a673c671a56 1087 {
ebrus 0:0a673c671a56 1088 /* Start regular conversion */
ebrus 0:0a673c671a56 1089 status = SDADC_RegConvStart(hsdadc);
ebrus 0:0a673c671a56 1090 }
ebrus 0:0a673c671a56 1091 else
ebrus 0:0a673c671a56 1092 {
ebrus 0:0a673c671a56 1093 status = HAL_ERROR;
ebrus 0:0a673c671a56 1094 }
ebrus 0:0a673c671a56 1095 /* Return function status */
ebrus 0:0a673c671a56 1096 return status;
ebrus 0:0a673c671a56 1097 }
ebrus 0:0a673c671a56 1098
ebrus 0:0a673c671a56 1099 /**
ebrus 0:0a673c671a56 1100 * @brief This function allows to poll for the end of regular conversion.
ebrus 0:0a673c671a56 1101 * @note This function should be called only if regular conversion is ongoing.
ebrus 0:0a673c671a56 1102 * @param hsdadc : SDADC handle.
ebrus 0:0a673c671a56 1103 * @param Timeout : Timeout value in milliseconds.
ebrus 0:0a673c671a56 1104 * @retval HAL status
ebrus 0:0a673c671a56 1105 */
ebrus 0:0a673c671a56 1106 HAL_StatusTypeDef HAL_SDADC_PollForConversion(SDADC_HandleTypeDef* hsdadc, uint32_t Timeout)
ebrus 0:0a673c671a56 1107 {
ebrus 0:0a673c671a56 1108 uint32_t tickstart;
ebrus 0:0a673c671a56 1109
ebrus 0:0a673c671a56 1110 /* Check parameters */
ebrus 0:0a673c671a56 1111 assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
ebrus 0:0a673c671a56 1112
ebrus 0:0a673c671a56 1113 /* Check SDADC state */
ebrus 0:0a673c671a56 1114 if((hsdadc->State != HAL_SDADC_STATE_REG) && \
ebrus 0:0a673c671a56 1115 (hsdadc->State != HAL_SDADC_STATE_REG_INJ))
ebrus 0:0a673c671a56 1116 {
ebrus 0:0a673c671a56 1117 /* Return error status */
ebrus 0:0a673c671a56 1118 return HAL_ERROR;
ebrus 0:0a673c671a56 1119 }
ebrus 0:0a673c671a56 1120 else
ebrus 0:0a673c671a56 1121 {
ebrus 0:0a673c671a56 1122 /* Get timeout */
ebrus 0:0a673c671a56 1123 tickstart = HAL_GetTick();
ebrus 0:0a673c671a56 1124
ebrus 0:0a673c671a56 1125 /* Wait REOCF bit in SDADC_ISR register */
ebrus 0:0a673c671a56 1126 while((hsdadc->Instance->ISR & SDADC_ISR_REOCF) != SDADC_ISR_REOCF)
ebrus 0:0a673c671a56 1127 {
ebrus 0:0a673c671a56 1128 /* Check the Timeout */
ebrus 0:0a673c671a56 1129 if(Timeout != HAL_MAX_DELAY)
ebrus 0:0a673c671a56 1130 {
ebrus 0:0a673c671a56 1131 if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
ebrus 0:0a673c671a56 1132 {
ebrus 0:0a673c671a56 1133 /* Return timeout status */
ebrus 0:0a673c671a56 1134 return HAL_TIMEOUT;
ebrus 0:0a673c671a56 1135 }
ebrus 0:0a673c671a56 1136 }
ebrus 0:0a673c671a56 1137 }
ebrus 0:0a673c671a56 1138 /* Check if overrun occurs */
ebrus 0:0a673c671a56 1139 if((hsdadc->Instance->ISR & SDADC_ISR_ROVRF) == SDADC_ISR_ROVRF)
ebrus 0:0a673c671a56 1140 {
ebrus 0:0a673c671a56 1141 /* Update error code and call error callback */
ebrus 0:0a673c671a56 1142 hsdadc->ErrorCode = SDADC_ERROR_REGULAR_OVERRUN;
ebrus 0:0a673c671a56 1143 HAL_SDADC_ErrorCallback(hsdadc);
ebrus 0:0a673c671a56 1144
ebrus 0:0a673c671a56 1145 /* Set CLRROVRF bit in SDADC_CLRISR register */
ebrus 0:0a673c671a56 1146 hsdadc->Instance->CLRISR |= SDADC_ISR_CLRROVRF;
ebrus 0:0a673c671a56 1147 }
ebrus 0:0a673c671a56 1148 /* Update SDADC state only if not continuous conversion and SW trigger */
ebrus 0:0a673c671a56 1149 if((hsdadc->RegularContMode == SDADC_CONTINUOUS_CONV_OFF) && \
ebrus 0:0a673c671a56 1150 (hsdadc->RegularTrigger == SDADC_SOFTWARE_TRIGGER))
ebrus 0:0a673c671a56 1151 {
ebrus 0:0a673c671a56 1152 hsdadc->State = (hsdadc->State == HAL_SDADC_STATE_REG) ? \
ebrus 0:0a673c671a56 1153 HAL_SDADC_STATE_READY : HAL_SDADC_STATE_INJ;
ebrus 0:0a673c671a56 1154 }
ebrus 0:0a673c671a56 1155 /* Return function status */
ebrus 0:0a673c671a56 1156 return HAL_OK;
ebrus 0:0a673c671a56 1157 }
ebrus 0:0a673c671a56 1158 }
ebrus 0:0a673c671a56 1159
ebrus 0:0a673c671a56 1160 /**
ebrus 0:0a673c671a56 1161 * @brief This function allows to stop regular conversion in polling mode.
ebrus 0:0a673c671a56 1162 * @note This function should be called only if regular conversion is ongoing.
ebrus 0:0a673c671a56 1163 * @param hsdadc : SDADC handle.
ebrus 0:0a673c671a56 1164 * @retval HAL status
ebrus 0:0a673c671a56 1165 */
ebrus 0:0a673c671a56 1166 HAL_StatusTypeDef HAL_SDADC_Stop(SDADC_HandleTypeDef *hsdadc)
ebrus 0:0a673c671a56 1167 {
ebrus 0:0a673c671a56 1168 HAL_StatusTypeDef status = HAL_OK;
ebrus 0:0a673c671a56 1169
ebrus 0:0a673c671a56 1170 /* Check parameters */
ebrus 0:0a673c671a56 1171 assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
ebrus 0:0a673c671a56 1172
ebrus 0:0a673c671a56 1173 /* Check SDADC state */
ebrus 0:0a673c671a56 1174 if((hsdadc->State != HAL_SDADC_STATE_REG) && \
ebrus 0:0a673c671a56 1175 (hsdadc->State != HAL_SDADC_STATE_REG_INJ))
ebrus 0:0a673c671a56 1176 {
ebrus 0:0a673c671a56 1177 /* Return error status */
ebrus 0:0a673c671a56 1178 status = HAL_ERROR;
ebrus 0:0a673c671a56 1179 }
ebrus 0:0a673c671a56 1180 else
ebrus 0:0a673c671a56 1181 {
ebrus 0:0a673c671a56 1182 /* Stop regular conversion */
ebrus 0:0a673c671a56 1183 status = SDADC_RegConvStop(hsdadc);
ebrus 0:0a673c671a56 1184 }
ebrus 0:0a673c671a56 1185 /* Return function status */
ebrus 0:0a673c671a56 1186 return status;
ebrus 0:0a673c671a56 1187 }
ebrus 0:0a673c671a56 1188
ebrus 0:0a673c671a56 1189 /**
ebrus 0:0a673c671a56 1190 * @brief This function allows to start regular conversion in interrupt mode.
ebrus 0:0a673c671a56 1191 * @note This function should be called only when SDADC instance is in idle state
ebrus 0:0a673c671a56 1192 * or if injected conversion is ongoing.
ebrus 0:0a673c671a56 1193 * @param hsdadc : SDADC handle.
ebrus 0:0a673c671a56 1194 * @retval HAL status
ebrus 0:0a673c671a56 1195 */
ebrus 0:0a673c671a56 1196 HAL_StatusTypeDef HAL_SDADC_Start_IT(SDADC_HandleTypeDef *hsdadc)
ebrus 0:0a673c671a56 1197 {
ebrus 0:0a673c671a56 1198 HAL_StatusTypeDef status = HAL_OK;
ebrus 0:0a673c671a56 1199
ebrus 0:0a673c671a56 1200 /* Check parameters */
ebrus 0:0a673c671a56 1201 assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
ebrus 0:0a673c671a56 1202
ebrus 0:0a673c671a56 1203 /* Check SDADC state */
ebrus 0:0a673c671a56 1204 if((hsdadc->State == HAL_SDADC_STATE_READY) || \
ebrus 0:0a673c671a56 1205 (hsdadc->State == HAL_SDADC_STATE_INJ))
ebrus 0:0a673c671a56 1206 {
ebrus 0:0a673c671a56 1207 /* Set REOCIE and ROVRIE bits in SDADC_CR1 register */
ebrus 0:0a673c671a56 1208 hsdadc->Instance->CR1 |= (uint32_t) (SDADC_CR1_REOCIE | SDADC_CR1_ROVRIE);
ebrus 0:0a673c671a56 1209
ebrus 0:0a673c671a56 1210 /* Start regular conversion */
ebrus 0:0a673c671a56 1211 status = SDADC_RegConvStart(hsdadc);
ebrus 0:0a673c671a56 1212 }
ebrus 0:0a673c671a56 1213 else
ebrus 0:0a673c671a56 1214 {
ebrus 0:0a673c671a56 1215 status = HAL_ERROR;
ebrus 0:0a673c671a56 1216 }
ebrus 0:0a673c671a56 1217 /* Return function status */
ebrus 0:0a673c671a56 1218 return status;
ebrus 0:0a673c671a56 1219 }
ebrus 0:0a673c671a56 1220
ebrus 0:0a673c671a56 1221 /**
ebrus 0:0a673c671a56 1222 * @brief This function allows to stop regular conversion in interrupt mode.
ebrus 0:0a673c671a56 1223 * @note This function should be called only if regular conversion is ongoing.
ebrus 0:0a673c671a56 1224 * @param hsdadc : SDADC handle.
ebrus 0:0a673c671a56 1225 * @retval HAL status
ebrus 0:0a673c671a56 1226 */
ebrus 0:0a673c671a56 1227 HAL_StatusTypeDef HAL_SDADC_Stop_IT(SDADC_HandleTypeDef *hsdadc)
ebrus 0:0a673c671a56 1228 {
ebrus 0:0a673c671a56 1229 HAL_StatusTypeDef status = HAL_OK;
ebrus 0:0a673c671a56 1230
ebrus 0:0a673c671a56 1231 /* Check parameters */
ebrus 0:0a673c671a56 1232 assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
ebrus 0:0a673c671a56 1233
ebrus 0:0a673c671a56 1234 /* Check SDADC state */
ebrus 0:0a673c671a56 1235 if((hsdadc->State != HAL_SDADC_STATE_REG) && \
ebrus 0:0a673c671a56 1236 (hsdadc->State != HAL_SDADC_STATE_REG_INJ))
ebrus 0:0a673c671a56 1237 {
ebrus 0:0a673c671a56 1238 /* Return error status */
ebrus 0:0a673c671a56 1239 status = HAL_ERROR;
ebrus 0:0a673c671a56 1240 }
ebrus 0:0a673c671a56 1241 else
ebrus 0:0a673c671a56 1242 {
ebrus 0:0a673c671a56 1243 /* Clear REOCIE and ROVRIE bits in SDADC_CR1 register */
ebrus 0:0a673c671a56 1244 hsdadc->Instance->CR1 &= (uint32_t) ~(SDADC_CR1_REOCIE | SDADC_CR1_ROVRIE);
ebrus 0:0a673c671a56 1245
ebrus 0:0a673c671a56 1246 /* Stop regular conversion */
ebrus 0:0a673c671a56 1247 status = SDADC_RegConvStop(hsdadc);
ebrus 0:0a673c671a56 1248 }
ebrus 0:0a673c671a56 1249 /* Return function status */
ebrus 0:0a673c671a56 1250 return status;
ebrus 0:0a673c671a56 1251 }
ebrus 0:0a673c671a56 1252
ebrus 0:0a673c671a56 1253 /**
ebrus 0:0a673c671a56 1254 * @brief This function allows to start regular conversion in DMA mode.
ebrus 0:0a673c671a56 1255 * @note This function should be called only when SDADC instance is in idle state
ebrus 0:0a673c671a56 1256 * or if injected conversion is ongoing.
ebrus 0:0a673c671a56 1257 * @param hsdadc : SDADC handle.
ebrus 0:0a673c671a56 1258 * @param pData : The destination buffer address.
ebrus 0:0a673c671a56 1259 * @param Length : The length of data to be transferred from SDADC peripheral to memory.
ebrus 0:0a673c671a56 1260 * @retval HAL status
ebrus 0:0a673c671a56 1261 */
ebrus 0:0a673c671a56 1262 HAL_StatusTypeDef HAL_SDADC_Start_DMA(SDADC_HandleTypeDef *hsdadc, uint32_t *pData,
ebrus 0:0a673c671a56 1263 uint32_t Length)
ebrus 0:0a673c671a56 1264 {
ebrus 0:0a673c671a56 1265 HAL_StatusTypeDef status = HAL_OK;
ebrus 0:0a673c671a56 1266
ebrus 0:0a673c671a56 1267 /* Check parameters */
ebrus 0:0a673c671a56 1268 assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
ebrus 0:0a673c671a56 1269 assert_param(pData != NULL);
ebrus 0:0a673c671a56 1270 assert_param(Length != 0);
ebrus 0:0a673c671a56 1271
ebrus 0:0a673c671a56 1272 /* Check that DMA is not enabled for injected conversion */
ebrus 0:0a673c671a56 1273 if((hsdadc->Instance->CR1 & SDADC_CR1_JDMAEN) == SDADC_CR1_JDMAEN)
ebrus 0:0a673c671a56 1274 {
ebrus 0:0a673c671a56 1275 status = HAL_ERROR;
ebrus 0:0a673c671a56 1276 }
ebrus 0:0a673c671a56 1277 /* Check parameters compatibility */
ebrus 0:0a673c671a56 1278 else if((hsdadc->RegularTrigger == SDADC_SOFTWARE_TRIGGER) && \
ebrus 0:0a673c671a56 1279 (hsdadc->RegularContMode == SDADC_CONTINUOUS_CONV_OFF) && \
ebrus 0:0a673c671a56 1280 (hsdadc->hdma->Init.Mode == DMA_NORMAL) && \
ebrus 0:0a673c671a56 1281 (Length != 1))
ebrus 0:0a673c671a56 1282 {
ebrus 0:0a673c671a56 1283 status = HAL_ERROR;
ebrus 0:0a673c671a56 1284 }
ebrus 0:0a673c671a56 1285 else if((hsdadc->RegularTrigger == SDADC_SOFTWARE_TRIGGER) && \
ebrus 0:0a673c671a56 1286 (hsdadc->RegularContMode == SDADC_CONTINUOUS_CONV_OFF) && \
ebrus 0:0a673c671a56 1287 (hsdadc->hdma->Init.Mode == DMA_CIRCULAR))
ebrus 0:0a673c671a56 1288 {
ebrus 0:0a673c671a56 1289 status = HAL_ERROR;
ebrus 0:0a673c671a56 1290 }
ebrus 0:0a673c671a56 1291 /* Check SDADC state */
ebrus 0:0a673c671a56 1292 else if((hsdadc->State == HAL_SDADC_STATE_READY) || \
ebrus 0:0a673c671a56 1293 (hsdadc->State == HAL_SDADC_STATE_INJ))
ebrus 0:0a673c671a56 1294 {
ebrus 0:0a673c671a56 1295 /* Set callbacks on DMA handler */
ebrus 0:0a673c671a56 1296 hsdadc->hdma->XferCpltCallback = SDADC_DMARegularConvCplt;
ebrus 0:0a673c671a56 1297 hsdadc->hdma->XferErrorCallback = SDADC_DMAError;
ebrus 0:0a673c671a56 1298 if(hsdadc->hdma->Init.Mode == DMA_CIRCULAR)
ebrus 0:0a673c671a56 1299 {
ebrus 0:0a673c671a56 1300 hsdadc->hdma->XferHalfCpltCallback = SDADC_DMARegularHalfConvCplt;
ebrus 0:0a673c671a56 1301 }
ebrus 0:0a673c671a56 1302
ebrus 0:0a673c671a56 1303 /* Set RDMAEN bit in SDADC_CR1 register */
ebrus 0:0a673c671a56 1304 hsdadc->Instance->CR1 |= SDADC_CR1_RDMAEN;
ebrus 0:0a673c671a56 1305
ebrus 0:0a673c671a56 1306 /* Start DMA in interrupt mode */
ebrus 0:0a673c671a56 1307 if(HAL_DMA_Start_IT(hsdadc->hdma, (uint32_t)&hsdadc->Instance->RDATAR, \
ebrus 0:0a673c671a56 1308 (uint32_t) pData, Length) != HAL_OK)
ebrus 0:0a673c671a56 1309 {
ebrus 0:0a673c671a56 1310 /* Set SDADC in error state */
ebrus 0:0a673c671a56 1311 hsdadc->State = HAL_SDADC_STATE_ERROR;
ebrus 0:0a673c671a56 1312 status = HAL_ERROR;
ebrus 0:0a673c671a56 1313 }
ebrus 0:0a673c671a56 1314 else
ebrus 0:0a673c671a56 1315 {
ebrus 0:0a673c671a56 1316 /* Start regular conversion */
ebrus 0:0a673c671a56 1317 status = SDADC_RegConvStart(hsdadc);
ebrus 0:0a673c671a56 1318 }
ebrus 0:0a673c671a56 1319 }
ebrus 0:0a673c671a56 1320 else
ebrus 0:0a673c671a56 1321 {
ebrus 0:0a673c671a56 1322 status = HAL_ERROR;
ebrus 0:0a673c671a56 1323 }
ebrus 0:0a673c671a56 1324 /* Return function status */
ebrus 0:0a673c671a56 1325 return status;
ebrus 0:0a673c671a56 1326 }
ebrus 0:0a673c671a56 1327
ebrus 0:0a673c671a56 1328 /**
ebrus 0:0a673c671a56 1329 * @brief This function allows to stop regular conversion in DMA mode.
ebrus 0:0a673c671a56 1330 * @note This function should be called only if regular conversion is ongoing.
ebrus 0:0a673c671a56 1331 * @param hsdadc : SDADC handle.
ebrus 0:0a673c671a56 1332 * @retval HAL status
ebrus 0:0a673c671a56 1333 */
ebrus 0:0a673c671a56 1334 HAL_StatusTypeDef HAL_SDADC_Stop_DMA(SDADC_HandleTypeDef *hsdadc)
ebrus 0:0a673c671a56 1335 {
ebrus 0:0a673c671a56 1336 HAL_StatusTypeDef status = HAL_OK;
ebrus 0:0a673c671a56 1337
ebrus 0:0a673c671a56 1338 /* Check parameters */
ebrus 0:0a673c671a56 1339 assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
ebrus 0:0a673c671a56 1340
ebrus 0:0a673c671a56 1341 /* Check SDADC state */
ebrus 0:0a673c671a56 1342 if((hsdadc->State != HAL_SDADC_STATE_REG) && \
ebrus 0:0a673c671a56 1343 (hsdadc->State != HAL_SDADC_STATE_REG_INJ))
ebrus 0:0a673c671a56 1344 {
ebrus 0:0a673c671a56 1345 /* Return error status */
ebrus 0:0a673c671a56 1346 status = HAL_ERROR;
ebrus 0:0a673c671a56 1347 }
ebrus 0:0a673c671a56 1348 else
ebrus 0:0a673c671a56 1349 {
ebrus 0:0a673c671a56 1350 /* Clear RDMAEN bit in SDADC_CR1 register */
ebrus 0:0a673c671a56 1351 hsdadc->Instance->CR1 &= ~(SDADC_CR1_RDMAEN);
ebrus 0:0a673c671a56 1352
ebrus 0:0a673c671a56 1353 /* Stop current DMA transfer */
ebrus 0:0a673c671a56 1354 if(HAL_DMA_Abort(hsdadc->hdma) != HAL_OK)
ebrus 0:0a673c671a56 1355 {
ebrus 0:0a673c671a56 1356 /* Set SDADC in error state */
ebrus 0:0a673c671a56 1357 hsdadc->State = HAL_SDADC_STATE_ERROR;
ebrus 0:0a673c671a56 1358 status = HAL_ERROR;
ebrus 0:0a673c671a56 1359 }
ebrus 0:0a673c671a56 1360 else
ebrus 0:0a673c671a56 1361 {
ebrus 0:0a673c671a56 1362 /* Stop regular conversion */
ebrus 0:0a673c671a56 1363 status = SDADC_RegConvStop(hsdadc);
ebrus 0:0a673c671a56 1364 }
ebrus 0:0a673c671a56 1365 }
ebrus 0:0a673c671a56 1366 /* Return function status */
ebrus 0:0a673c671a56 1367 return status;
ebrus 0:0a673c671a56 1368 }
ebrus 0:0a673c671a56 1369
ebrus 0:0a673c671a56 1370 /**
ebrus 0:0a673c671a56 1371 * @brief This function allows to get regular conversion value.
ebrus 0:0a673c671a56 1372 * @param hsdadc : SDADC handle.
ebrus 0:0a673c671a56 1373 * @retval Regular conversion value
ebrus 0:0a673c671a56 1374 */
ebrus 0:0a673c671a56 1375 uint32_t HAL_SDADC_GetValue(SDADC_HandleTypeDef *hsdadc)
ebrus 0:0a673c671a56 1376 {
ebrus 0:0a673c671a56 1377 /* Check parameters */
ebrus 0:0a673c671a56 1378 assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
ebrus 0:0a673c671a56 1379
ebrus 0:0a673c671a56 1380 /* Return regular conversion value */
ebrus 0:0a673c671a56 1381 return hsdadc->Instance->RDATAR;
ebrus 0:0a673c671a56 1382 }
ebrus 0:0a673c671a56 1383
ebrus 0:0a673c671a56 1384 /**
ebrus 0:0a673c671a56 1385 * @brief This function allows to start injected conversion in polling mode.
ebrus 0:0a673c671a56 1386 * @note This function should be called only when SDADC instance is in idle state
ebrus 0:0a673c671a56 1387 * or if regular conversion is ongoing.
ebrus 0:0a673c671a56 1388 * @param hsdadc : SDADC handle.
ebrus 0:0a673c671a56 1389 * @retval HAL status
ebrus 0:0a673c671a56 1390 */
ebrus 0:0a673c671a56 1391 HAL_StatusTypeDef HAL_SDADC_InjectedStart(SDADC_HandleTypeDef *hsdadc)
ebrus 0:0a673c671a56 1392 {
ebrus 0:0a673c671a56 1393 HAL_StatusTypeDef status = HAL_OK;
ebrus 0:0a673c671a56 1394
ebrus 0:0a673c671a56 1395 /* Check parameters */
ebrus 0:0a673c671a56 1396 assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
ebrus 0:0a673c671a56 1397
ebrus 0:0a673c671a56 1398 /* Check SDADC state */
ebrus 0:0a673c671a56 1399 if((hsdadc->State == HAL_SDADC_STATE_READY) || \
ebrus 0:0a673c671a56 1400 (hsdadc->State == HAL_SDADC_STATE_REG))
ebrus 0:0a673c671a56 1401 {
ebrus 0:0a673c671a56 1402 /* Start injected conversion */
ebrus 0:0a673c671a56 1403 status = SDADC_InjConvStart(hsdadc);
ebrus 0:0a673c671a56 1404 }
ebrus 0:0a673c671a56 1405 else
ebrus 0:0a673c671a56 1406 {
ebrus 0:0a673c671a56 1407 status = HAL_ERROR;
ebrus 0:0a673c671a56 1408 }
ebrus 0:0a673c671a56 1409 /* Return function status */
ebrus 0:0a673c671a56 1410 return status;
ebrus 0:0a673c671a56 1411 }
ebrus 0:0a673c671a56 1412
ebrus 0:0a673c671a56 1413 /**
ebrus 0:0a673c671a56 1414 * @brief This function allows to poll for the end of injected conversion.
ebrus 0:0a673c671a56 1415 * @note This function should be called only if injected conversion is ongoing.
ebrus 0:0a673c671a56 1416 * @param hsdadc : SDADC handle.
ebrus 0:0a673c671a56 1417 * @param Timeout : Timeout value in milliseconds.
ebrus 0:0a673c671a56 1418 * @retval HAL status
ebrus 0:0a673c671a56 1419 */
ebrus 0:0a673c671a56 1420 HAL_StatusTypeDef HAL_SDADC_PollForInjectedConversion(SDADC_HandleTypeDef* hsdadc,
ebrus 0:0a673c671a56 1421 uint32_t Timeout)
ebrus 0:0a673c671a56 1422 {
ebrus 0:0a673c671a56 1423 uint32_t tickstart;
ebrus 0:0a673c671a56 1424
ebrus 0:0a673c671a56 1425 /* Check parameters */
ebrus 0:0a673c671a56 1426 assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
ebrus 0:0a673c671a56 1427
ebrus 0:0a673c671a56 1428 /* Check SDADC state */
ebrus 0:0a673c671a56 1429 if((hsdadc->State != HAL_SDADC_STATE_INJ) && \
ebrus 0:0a673c671a56 1430 (hsdadc->State != HAL_SDADC_STATE_REG_INJ))
ebrus 0:0a673c671a56 1431 {
ebrus 0:0a673c671a56 1432 /* Return error status */
ebrus 0:0a673c671a56 1433 return HAL_ERROR;
ebrus 0:0a673c671a56 1434 }
ebrus 0:0a673c671a56 1435 else
ebrus 0:0a673c671a56 1436 {
ebrus 0:0a673c671a56 1437 /* Get timeout */
ebrus 0:0a673c671a56 1438 tickstart = HAL_GetTick();
ebrus 0:0a673c671a56 1439
ebrus 0:0a673c671a56 1440 /* Wait JEOCF bit in SDADC_ISR register */
ebrus 0:0a673c671a56 1441 while((hsdadc->Instance->ISR & SDADC_ISR_JEOCF) != SDADC_ISR_JEOCF)
ebrus 0:0a673c671a56 1442 {
ebrus 0:0a673c671a56 1443 /* Check the Timeout */
ebrus 0:0a673c671a56 1444 if(Timeout != HAL_MAX_DELAY)
ebrus 0:0a673c671a56 1445 {
ebrus 0:0a673c671a56 1446 if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
ebrus 0:0a673c671a56 1447 {
ebrus 0:0a673c671a56 1448 /* Return timeout status */
ebrus 0:0a673c671a56 1449 return HAL_TIMEOUT;
ebrus 0:0a673c671a56 1450 }
ebrus 0:0a673c671a56 1451 }
ebrus 0:0a673c671a56 1452 }
ebrus 0:0a673c671a56 1453 /* Check if overrun occurs */
ebrus 0:0a673c671a56 1454 if((hsdadc->Instance->ISR & SDADC_ISR_JOVRF) == SDADC_ISR_JOVRF)
ebrus 0:0a673c671a56 1455 {
ebrus 0:0a673c671a56 1456 /* Update error code and call error callback */
ebrus 0:0a673c671a56 1457 hsdadc->ErrorCode = SDADC_ERROR_INJECTED_OVERRUN;
ebrus 0:0a673c671a56 1458 HAL_SDADC_ErrorCallback(hsdadc);
ebrus 0:0a673c671a56 1459
ebrus 0:0a673c671a56 1460 /* Set CLRJOVRF bit in SDADC_CLRISR register */
ebrus 0:0a673c671a56 1461 hsdadc->Instance->CLRISR |= SDADC_ISR_CLRJOVRF;
ebrus 0:0a673c671a56 1462 }
ebrus 0:0a673c671a56 1463 /* Update remaining injected conversions */
ebrus 0:0a673c671a56 1464 hsdadc->InjConvRemaining--;
ebrus 0:0a673c671a56 1465 if(hsdadc->InjConvRemaining == 0)
ebrus 0:0a673c671a56 1466 {
ebrus 0:0a673c671a56 1467 /* end of injected sequence, reset the value */
ebrus 0:0a673c671a56 1468 hsdadc->InjConvRemaining = hsdadc->InjectedChannelsNbr;
ebrus 0:0a673c671a56 1469 }
ebrus 0:0a673c671a56 1470
ebrus 0:0a673c671a56 1471 /* Update SDADC state only if not continuous conversion, SW trigger */
ebrus 0:0a673c671a56 1472 /* and end of injected sequence */
ebrus 0:0a673c671a56 1473 if((hsdadc->InjectedContMode == SDADC_CONTINUOUS_CONV_OFF) && \
ebrus 0:0a673c671a56 1474 (hsdadc->InjectedTrigger == SDADC_SOFTWARE_TRIGGER) && \
ebrus 0:0a673c671a56 1475 (hsdadc->InjConvRemaining == hsdadc->InjectedChannelsNbr))
ebrus 0:0a673c671a56 1476 {
ebrus 0:0a673c671a56 1477 hsdadc->State = (hsdadc->State == HAL_SDADC_STATE_INJ) ? \
ebrus 0:0a673c671a56 1478 HAL_SDADC_STATE_READY : HAL_SDADC_STATE_REG;
ebrus 0:0a673c671a56 1479 }
ebrus 0:0a673c671a56 1480 /* Return function status */
ebrus 0:0a673c671a56 1481 return HAL_OK;
ebrus 0:0a673c671a56 1482 }
ebrus 0:0a673c671a56 1483 }
ebrus 0:0a673c671a56 1484
ebrus 0:0a673c671a56 1485 /**
ebrus 0:0a673c671a56 1486 * @brief This function allows to stop injected conversion in polling mode.
ebrus 0:0a673c671a56 1487 * @note This function should be called only if injected conversion is ongoing.
ebrus 0:0a673c671a56 1488 * @param hsdadc : SDADC handle.
ebrus 0:0a673c671a56 1489 * @retval HAL status
ebrus 0:0a673c671a56 1490 */
ebrus 0:0a673c671a56 1491 HAL_StatusTypeDef HAL_SDADC_InjectedStop(SDADC_HandleTypeDef *hsdadc)
ebrus 0:0a673c671a56 1492 {
ebrus 0:0a673c671a56 1493 HAL_StatusTypeDef status = HAL_OK;
ebrus 0:0a673c671a56 1494
ebrus 0:0a673c671a56 1495 /* Check parameters */
ebrus 0:0a673c671a56 1496 assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
ebrus 0:0a673c671a56 1497
ebrus 0:0a673c671a56 1498 /* Check SDADC state */
ebrus 0:0a673c671a56 1499 if((hsdadc->State != HAL_SDADC_STATE_INJ) && \
ebrus 0:0a673c671a56 1500 (hsdadc->State != HAL_SDADC_STATE_REG_INJ))
ebrus 0:0a673c671a56 1501 {
ebrus 0:0a673c671a56 1502 /* Return error status */
ebrus 0:0a673c671a56 1503 status = HAL_ERROR;
ebrus 0:0a673c671a56 1504 }
ebrus 0:0a673c671a56 1505 else
ebrus 0:0a673c671a56 1506 {
ebrus 0:0a673c671a56 1507 /* Stop injected conversion */
ebrus 0:0a673c671a56 1508 status = SDADC_InjConvStop(hsdadc);
ebrus 0:0a673c671a56 1509 }
ebrus 0:0a673c671a56 1510 /* Return function status */
ebrus 0:0a673c671a56 1511 return status;
ebrus 0:0a673c671a56 1512 }
ebrus 0:0a673c671a56 1513
ebrus 0:0a673c671a56 1514 /**
ebrus 0:0a673c671a56 1515 * @brief This function allows to start injected conversion in interrupt mode.
ebrus 0:0a673c671a56 1516 * @note This function should be called only when SDADC instance is in idle state
ebrus 0:0a673c671a56 1517 * or if regular conversion is ongoing.
ebrus 0:0a673c671a56 1518 * @param hsdadc : SDADC handle.
ebrus 0:0a673c671a56 1519 * @retval HAL status
ebrus 0:0a673c671a56 1520 */
ebrus 0:0a673c671a56 1521 HAL_StatusTypeDef HAL_SDADC_InjectedStart_IT(SDADC_HandleTypeDef *hsdadc)
ebrus 0:0a673c671a56 1522 {
ebrus 0:0a673c671a56 1523 HAL_StatusTypeDef status = HAL_OK;
ebrus 0:0a673c671a56 1524
ebrus 0:0a673c671a56 1525 /* Check parameters */
ebrus 0:0a673c671a56 1526 assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
ebrus 0:0a673c671a56 1527
ebrus 0:0a673c671a56 1528 /* Check SDADC state */
ebrus 0:0a673c671a56 1529 if((hsdadc->State == HAL_SDADC_STATE_READY) || \
ebrus 0:0a673c671a56 1530 (hsdadc->State == HAL_SDADC_STATE_REG))
ebrus 0:0a673c671a56 1531 {
ebrus 0:0a673c671a56 1532 /* Set JEOCIE and JOVRIE bits in SDADC_CR1 register */
ebrus 0:0a673c671a56 1533 hsdadc->Instance->CR1 |= (uint32_t) (SDADC_CR1_JEOCIE | SDADC_CR1_JOVRIE);
ebrus 0:0a673c671a56 1534
ebrus 0:0a673c671a56 1535 /* Start injected conversion */
ebrus 0:0a673c671a56 1536 status = SDADC_InjConvStart(hsdadc);
ebrus 0:0a673c671a56 1537 }
ebrus 0:0a673c671a56 1538 else
ebrus 0:0a673c671a56 1539 {
ebrus 0:0a673c671a56 1540 status = HAL_ERROR;
ebrus 0:0a673c671a56 1541 }
ebrus 0:0a673c671a56 1542 /* Return function status */
ebrus 0:0a673c671a56 1543 return status;
ebrus 0:0a673c671a56 1544 }
ebrus 0:0a673c671a56 1545
ebrus 0:0a673c671a56 1546 /**
ebrus 0:0a673c671a56 1547 * @brief This function allows to stop injected conversion in interrupt mode.
ebrus 0:0a673c671a56 1548 * @note This function should be called only if injected conversion is ongoing.
ebrus 0:0a673c671a56 1549 * @param hsdadc : SDADC handle.
ebrus 0:0a673c671a56 1550 * @retval HAL status
ebrus 0:0a673c671a56 1551 */
ebrus 0:0a673c671a56 1552 HAL_StatusTypeDef HAL_SDADC_InjectedStop_IT(SDADC_HandleTypeDef *hsdadc)
ebrus 0:0a673c671a56 1553 {
ebrus 0:0a673c671a56 1554 HAL_StatusTypeDef status = HAL_OK;
ebrus 0:0a673c671a56 1555
ebrus 0:0a673c671a56 1556 /* Check parameters */
ebrus 0:0a673c671a56 1557 assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
ebrus 0:0a673c671a56 1558
ebrus 0:0a673c671a56 1559 /* Check SDADC state */
ebrus 0:0a673c671a56 1560 if((hsdadc->State != HAL_SDADC_STATE_INJ) && \
ebrus 0:0a673c671a56 1561 (hsdadc->State != HAL_SDADC_STATE_REG_INJ))
ebrus 0:0a673c671a56 1562 {
ebrus 0:0a673c671a56 1563 /* Return error status */
ebrus 0:0a673c671a56 1564 status = HAL_ERROR;
ebrus 0:0a673c671a56 1565 }
ebrus 0:0a673c671a56 1566 else
ebrus 0:0a673c671a56 1567 {
ebrus 0:0a673c671a56 1568 /* Clear JEOCIE and JOVRIE bits in SDADC_CR1 register */
ebrus 0:0a673c671a56 1569 hsdadc->Instance->CR1 &= (uint32_t) ~(SDADC_CR1_JEOCIE | SDADC_CR1_JOVRIE);
ebrus 0:0a673c671a56 1570
ebrus 0:0a673c671a56 1571 /* Stop injected conversion */
ebrus 0:0a673c671a56 1572 status = SDADC_InjConvStop(hsdadc);
ebrus 0:0a673c671a56 1573 }
ebrus 0:0a673c671a56 1574 /* Return function status */
ebrus 0:0a673c671a56 1575 return status;
ebrus 0:0a673c671a56 1576 }
ebrus 0:0a673c671a56 1577
ebrus 0:0a673c671a56 1578 /**
ebrus 0:0a673c671a56 1579 * @brief This function allows to start injected conversion in DMA mode.
ebrus 0:0a673c671a56 1580 * @note This function should be called only when SDADC instance is in idle state
ebrus 0:0a673c671a56 1581 * or if regular conversion is ongoing.
ebrus 0:0a673c671a56 1582 * @param hsdadc : SDADC handle.
ebrus 0:0a673c671a56 1583 * @param pData : The destination buffer address.
ebrus 0:0a673c671a56 1584 * @param Length : The length of data to be transferred from SDADC peripheral to memory.
ebrus 0:0a673c671a56 1585 * @retval HAL status
ebrus 0:0a673c671a56 1586 */
ebrus 0:0a673c671a56 1587 HAL_StatusTypeDef HAL_SDADC_InjectedStart_DMA(SDADC_HandleTypeDef *hsdadc, uint32_t *pData,
ebrus 0:0a673c671a56 1588 uint32_t Length)
ebrus 0:0a673c671a56 1589 {
ebrus 0:0a673c671a56 1590 HAL_StatusTypeDef status = HAL_OK;
ebrus 0:0a673c671a56 1591
ebrus 0:0a673c671a56 1592 /* Check parameters */
ebrus 0:0a673c671a56 1593 assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
ebrus 0:0a673c671a56 1594 assert_param(pData != NULL);
ebrus 0:0a673c671a56 1595 assert_param(Length != 0);
ebrus 0:0a673c671a56 1596
ebrus 0:0a673c671a56 1597 /* Check that DMA is not enabled for regular conversion */
ebrus 0:0a673c671a56 1598 if((hsdadc->Instance->CR1 & SDADC_CR1_RDMAEN) == SDADC_CR1_RDMAEN)
ebrus 0:0a673c671a56 1599 {
ebrus 0:0a673c671a56 1600 status = HAL_ERROR;
ebrus 0:0a673c671a56 1601 }
ebrus 0:0a673c671a56 1602 /* Check parameters compatibility */
ebrus 0:0a673c671a56 1603 else if((hsdadc->InjectedTrigger == SDADC_SOFTWARE_TRIGGER) && \
ebrus 0:0a673c671a56 1604 (hsdadc->InjectedContMode == SDADC_CONTINUOUS_CONV_OFF) && \
ebrus 0:0a673c671a56 1605 (hsdadc->hdma->Init.Mode == DMA_NORMAL) && \
ebrus 0:0a673c671a56 1606 (Length > hsdadc->InjectedChannelsNbr))
ebrus 0:0a673c671a56 1607 {
ebrus 0:0a673c671a56 1608 status = HAL_ERROR;
ebrus 0:0a673c671a56 1609 }
ebrus 0:0a673c671a56 1610 else if((hsdadc->InjectedTrigger == SDADC_SOFTWARE_TRIGGER) && \
ebrus 0:0a673c671a56 1611 (hsdadc->InjectedContMode == SDADC_CONTINUOUS_CONV_OFF) && \
ebrus 0:0a673c671a56 1612 (hsdadc->hdma->Init.Mode == DMA_CIRCULAR))
ebrus 0:0a673c671a56 1613 {
ebrus 0:0a673c671a56 1614 status = HAL_ERROR;
ebrus 0:0a673c671a56 1615 }
ebrus 0:0a673c671a56 1616 /* Check SDADC state */
ebrus 0:0a673c671a56 1617 else if((hsdadc->State == HAL_SDADC_STATE_READY) || \
ebrus 0:0a673c671a56 1618 (hsdadc->State == HAL_SDADC_STATE_REG))
ebrus 0:0a673c671a56 1619 {
ebrus 0:0a673c671a56 1620 /* Set callbacks on DMA handler */
ebrus 0:0a673c671a56 1621 hsdadc->hdma->XferCpltCallback = SDADC_DMAInjectedConvCplt;
ebrus 0:0a673c671a56 1622 hsdadc->hdma->XferErrorCallback = SDADC_DMAError;
ebrus 0:0a673c671a56 1623 if(hsdadc->hdma->Init.Mode == DMA_CIRCULAR)
ebrus 0:0a673c671a56 1624 {
ebrus 0:0a673c671a56 1625 hsdadc->hdma->XferHalfCpltCallback = SDADC_DMAInjectedHalfConvCplt;
ebrus 0:0a673c671a56 1626 }
ebrus 0:0a673c671a56 1627
ebrus 0:0a673c671a56 1628 /* Set JDMAEN bit in SDADC_CR1 register */
ebrus 0:0a673c671a56 1629 hsdadc->Instance->CR1 |= SDADC_CR1_JDMAEN;
ebrus 0:0a673c671a56 1630
ebrus 0:0a673c671a56 1631 /* Start DMA in interrupt mode */
ebrus 0:0a673c671a56 1632 if(HAL_DMA_Start_IT(hsdadc->hdma, (uint32_t)&hsdadc->Instance->JDATAR, \
ebrus 0:0a673c671a56 1633 (uint32_t) pData, Length) != HAL_OK)
ebrus 0:0a673c671a56 1634 {
ebrus 0:0a673c671a56 1635 /* Set SDADC in error state */
ebrus 0:0a673c671a56 1636 hsdadc->State = HAL_SDADC_STATE_ERROR;
ebrus 0:0a673c671a56 1637 status = HAL_ERROR;
ebrus 0:0a673c671a56 1638 }
ebrus 0:0a673c671a56 1639 else
ebrus 0:0a673c671a56 1640 {
ebrus 0:0a673c671a56 1641 /* Start injected conversion */
ebrus 0:0a673c671a56 1642 status = SDADC_InjConvStart(hsdadc);
ebrus 0:0a673c671a56 1643 }
ebrus 0:0a673c671a56 1644 }
ebrus 0:0a673c671a56 1645 else
ebrus 0:0a673c671a56 1646 {
ebrus 0:0a673c671a56 1647 status = HAL_ERROR;
ebrus 0:0a673c671a56 1648 }
ebrus 0:0a673c671a56 1649 /* Return function status */
ebrus 0:0a673c671a56 1650 return status;
ebrus 0:0a673c671a56 1651 }
ebrus 0:0a673c671a56 1652
ebrus 0:0a673c671a56 1653 /**
ebrus 0:0a673c671a56 1654 * @brief This function allows to stop injected conversion in DMA mode.
ebrus 0:0a673c671a56 1655 * @note This function should be called only if injected conversion is ongoing.
ebrus 0:0a673c671a56 1656 * @param hsdadc : SDADC handle.
ebrus 0:0a673c671a56 1657 * @retval HAL status
ebrus 0:0a673c671a56 1658 */
ebrus 0:0a673c671a56 1659 HAL_StatusTypeDef HAL_SDADC_InjectedStop_DMA(SDADC_HandleTypeDef *hsdadc)
ebrus 0:0a673c671a56 1660 {
ebrus 0:0a673c671a56 1661 HAL_StatusTypeDef status = HAL_OK;
ebrus 0:0a673c671a56 1662
ebrus 0:0a673c671a56 1663 /* Check parameters */
ebrus 0:0a673c671a56 1664 assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
ebrus 0:0a673c671a56 1665
ebrus 0:0a673c671a56 1666 /* Check SDADC state */
ebrus 0:0a673c671a56 1667 if((hsdadc->State != HAL_SDADC_STATE_INJ) && \
ebrus 0:0a673c671a56 1668 (hsdadc->State != HAL_SDADC_STATE_REG_INJ))
ebrus 0:0a673c671a56 1669 {
ebrus 0:0a673c671a56 1670 /* Return error status */
ebrus 0:0a673c671a56 1671 status = HAL_ERROR;
ebrus 0:0a673c671a56 1672 }
ebrus 0:0a673c671a56 1673 else
ebrus 0:0a673c671a56 1674 {
ebrus 0:0a673c671a56 1675 /* Clear JDMAEN bit in SDADC_CR1 register */
ebrus 0:0a673c671a56 1676 hsdadc->Instance->CR1 &= ~(SDADC_CR1_JDMAEN);
ebrus 0:0a673c671a56 1677
ebrus 0:0a673c671a56 1678 /* Stop current DMA transfer */
ebrus 0:0a673c671a56 1679 if(HAL_DMA_Abort(hsdadc->hdma) != HAL_OK)
ebrus 0:0a673c671a56 1680 {
ebrus 0:0a673c671a56 1681 /* Set SDADC in error state */
ebrus 0:0a673c671a56 1682 hsdadc->State = HAL_SDADC_STATE_ERROR;
ebrus 0:0a673c671a56 1683 status = HAL_ERROR;
ebrus 0:0a673c671a56 1684 }
ebrus 0:0a673c671a56 1685 else
ebrus 0:0a673c671a56 1686 {
ebrus 0:0a673c671a56 1687 /* Stop injected conversion */
ebrus 0:0a673c671a56 1688 status = SDADC_InjConvStop(hsdadc);
ebrus 0:0a673c671a56 1689 }
ebrus 0:0a673c671a56 1690 }
ebrus 0:0a673c671a56 1691 /* Return function status */
ebrus 0:0a673c671a56 1692 return status;
ebrus 0:0a673c671a56 1693 }
ebrus 0:0a673c671a56 1694
ebrus 0:0a673c671a56 1695 /**
ebrus 0:0a673c671a56 1696 * @brief This function allows to get injected conversion value.
ebrus 0:0a673c671a56 1697 * @param hsdadc : SDADC handle.
ebrus 0:0a673c671a56 1698 * @param Channel : Corresponding channel of injected conversion.
ebrus 0:0a673c671a56 1699 * @retval Injected conversion value
ebrus 0:0a673c671a56 1700 */
ebrus 0:0a673c671a56 1701 uint32_t HAL_SDADC_InjectedGetValue(SDADC_HandleTypeDef *hsdadc, uint32_t* Channel)
ebrus 0:0a673c671a56 1702 {
ebrus 0:0a673c671a56 1703 uint32_t value = 0;
ebrus 0:0a673c671a56 1704
ebrus 0:0a673c671a56 1705 /* Check parameters */
ebrus 0:0a673c671a56 1706 assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
ebrus 0:0a673c671a56 1707 assert_param(Channel != NULL);
ebrus 0:0a673c671a56 1708
ebrus 0:0a673c671a56 1709 /* Read SDADC_JDATAR register and extract channel and conversion value */
ebrus 0:0a673c671a56 1710 value = hsdadc->Instance->JDATAR;
ebrus 0:0a673c671a56 1711 *Channel = ((value & SDADC_JDATAR_JDATACH) >> SDADC_JDATAR_CH_OFFSET);
ebrus 0:0a673c671a56 1712 value &= SDADC_JDATAR_JDATA;
ebrus 0:0a673c671a56 1713
ebrus 0:0a673c671a56 1714 /* Return injected conversion value */
ebrus 0:0a673c671a56 1715 return value;
ebrus 0:0a673c671a56 1716 }
ebrus 0:0a673c671a56 1717
ebrus 0:0a673c671a56 1718 /**
ebrus 0:0a673c671a56 1719 * @brief This function allows to start multimode regular conversions in DMA mode.
ebrus 0:0a673c671a56 1720 * @note This function should be called only when SDADC instance is in idle state
ebrus 0:0a673c671a56 1721 * or if injected conversion is ongoing.
ebrus 0:0a673c671a56 1722 * @param hsdadc : SDADC handle.
ebrus 0:0a673c671a56 1723 * @param pData : The destination buffer address.
ebrus 0:0a673c671a56 1724 * @param Length : The length of data to be transferred from SDADC peripheral to memory.
ebrus 0:0a673c671a56 1725 * @retval HAL status
ebrus 0:0a673c671a56 1726 */
ebrus 0:0a673c671a56 1727 HAL_StatusTypeDef HAL_SDADC_MultiModeStart_DMA(SDADC_HandleTypeDef* hsdadc, uint32_t* pData,
ebrus 0:0a673c671a56 1728 uint32_t Length)
ebrus 0:0a673c671a56 1729 {
ebrus 0:0a673c671a56 1730 HAL_StatusTypeDef status = HAL_OK;
ebrus 0:0a673c671a56 1731
ebrus 0:0a673c671a56 1732 /* Check parameters */
ebrus 0:0a673c671a56 1733 assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
ebrus 0:0a673c671a56 1734 assert_param(pData != NULL);
ebrus 0:0a673c671a56 1735 assert_param(Length != 0);
ebrus 0:0a673c671a56 1736
ebrus 0:0a673c671a56 1737 /* Check instance is SDADC1 */
ebrus 0:0a673c671a56 1738 if(hsdadc->Instance != SDADC1)
ebrus 0:0a673c671a56 1739 {
ebrus 0:0a673c671a56 1740 status = HAL_ERROR;
ebrus 0:0a673c671a56 1741 }
ebrus 0:0a673c671a56 1742 /* Check that DMA is not enabled for injected conversion */
ebrus 0:0a673c671a56 1743 else if((hsdadc->Instance->CR1 & SDADC_CR1_JDMAEN) == SDADC_CR1_JDMAEN)
ebrus 0:0a673c671a56 1744 {
ebrus 0:0a673c671a56 1745 status = HAL_ERROR;
ebrus 0:0a673c671a56 1746 }
ebrus 0:0a673c671a56 1747 /* Check parameters compatibility */
ebrus 0:0a673c671a56 1748 else if((hsdadc->RegularTrigger == SDADC_SOFTWARE_TRIGGER) && \
ebrus 0:0a673c671a56 1749 (hsdadc->RegularContMode == SDADC_CONTINUOUS_CONV_OFF) && \
ebrus 0:0a673c671a56 1750 (hsdadc->hdma->Init.Mode == DMA_NORMAL) && \
ebrus 0:0a673c671a56 1751 (Length != 1))
ebrus 0:0a673c671a56 1752 {
ebrus 0:0a673c671a56 1753 status = HAL_ERROR;
ebrus 0:0a673c671a56 1754 }
ebrus 0:0a673c671a56 1755 else if((hsdadc->RegularTrigger == SDADC_SOFTWARE_TRIGGER) && \
ebrus 0:0a673c671a56 1756 (hsdadc->RegularContMode == SDADC_CONTINUOUS_CONV_OFF) && \
ebrus 0:0a673c671a56 1757 (hsdadc->hdma->Init.Mode == DMA_CIRCULAR))
ebrus 0:0a673c671a56 1758 {
ebrus 0:0a673c671a56 1759 status = HAL_ERROR;
ebrus 0:0a673c671a56 1760 }
ebrus 0:0a673c671a56 1761 /* Check SDADC state */
ebrus 0:0a673c671a56 1762 else if((hsdadc->State == HAL_SDADC_STATE_READY) || \
ebrus 0:0a673c671a56 1763 (hsdadc->State == HAL_SDADC_STATE_INJ))
ebrus 0:0a673c671a56 1764 {
ebrus 0:0a673c671a56 1765 /* Set callbacks on DMA handler */
ebrus 0:0a673c671a56 1766 hsdadc->hdma->XferCpltCallback = SDADC_DMARegularConvCplt;
ebrus 0:0a673c671a56 1767 hsdadc->hdma->XferErrorCallback = SDADC_DMAError;
ebrus 0:0a673c671a56 1768 if(hsdadc->hdma->Init.Mode == DMA_CIRCULAR)
ebrus 0:0a673c671a56 1769 {
ebrus 0:0a673c671a56 1770 hsdadc->hdma->XferHalfCpltCallback = SDADC_DMARegularHalfConvCplt;
ebrus 0:0a673c671a56 1771 }
ebrus 0:0a673c671a56 1772 /* Set RDMAEN bit in SDADC_CR1 register */
ebrus 0:0a673c671a56 1773 hsdadc->Instance->CR1 |= SDADC_CR1_RDMAEN;
ebrus 0:0a673c671a56 1774
ebrus 0:0a673c671a56 1775 /* Start DMA in interrupt mode */
ebrus 0:0a673c671a56 1776 if(hsdadc->RegularMultimode == SDADC_MULTIMODE_SDADC1_SDADC2)
ebrus 0:0a673c671a56 1777 {
ebrus 0:0a673c671a56 1778 status = HAL_DMA_Start_IT(hsdadc->hdma, (uint32_t)&hsdadc->Instance->RDATA12R, \
ebrus 0:0a673c671a56 1779 (uint32_t) pData, Length);
ebrus 0:0a673c671a56 1780 }
ebrus 0:0a673c671a56 1781 else
ebrus 0:0a673c671a56 1782 {
ebrus 0:0a673c671a56 1783 status = HAL_DMA_Start_IT(hsdadc->hdma, (uint32_t)&hsdadc->Instance->RDATA13R, \
ebrus 0:0a673c671a56 1784 (uint32_t) pData, Length);
ebrus 0:0a673c671a56 1785 }
ebrus 0:0a673c671a56 1786 if(status != HAL_OK)
ebrus 0:0a673c671a56 1787 {
ebrus 0:0a673c671a56 1788 /* Set SDADC in error state */
ebrus 0:0a673c671a56 1789 hsdadc->State = HAL_SDADC_STATE_ERROR;
ebrus 0:0a673c671a56 1790 status = HAL_ERROR;
ebrus 0:0a673c671a56 1791 }
ebrus 0:0a673c671a56 1792 else
ebrus 0:0a673c671a56 1793 {
ebrus 0:0a673c671a56 1794 /* Start regular conversion */
ebrus 0:0a673c671a56 1795 status = SDADC_RegConvStart(hsdadc);
ebrus 0:0a673c671a56 1796 }
ebrus 0:0a673c671a56 1797 }
ebrus 0:0a673c671a56 1798 else
ebrus 0:0a673c671a56 1799 {
ebrus 0:0a673c671a56 1800 status = HAL_ERROR;
ebrus 0:0a673c671a56 1801 }
ebrus 0:0a673c671a56 1802 /* Return function status */
ebrus 0:0a673c671a56 1803 return status;
ebrus 0:0a673c671a56 1804 }
ebrus 0:0a673c671a56 1805
ebrus 0:0a673c671a56 1806 /**
ebrus 0:0a673c671a56 1807 * @brief This function allows to stop multimode regular conversions in DMA mode.
ebrus 0:0a673c671a56 1808 * @note This function should be called only if regular conversion is ongoing.
ebrus 0:0a673c671a56 1809 * @param hsdadc : SDADC handle.
ebrus 0:0a673c671a56 1810 * @retval HAL status
ebrus 0:0a673c671a56 1811 */
ebrus 0:0a673c671a56 1812 HAL_StatusTypeDef HAL_SDADC_MultiModeStop_DMA(SDADC_HandleTypeDef* hsdadc)
ebrus 0:0a673c671a56 1813 {
ebrus 0:0a673c671a56 1814 HAL_StatusTypeDef status = HAL_OK;
ebrus 0:0a673c671a56 1815
ebrus 0:0a673c671a56 1816 /* Check parameters */
ebrus 0:0a673c671a56 1817 assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
ebrus 0:0a673c671a56 1818
ebrus 0:0a673c671a56 1819 /* Check instance is SDADC1 */
ebrus 0:0a673c671a56 1820 if(hsdadc->Instance != SDADC1)
ebrus 0:0a673c671a56 1821 {
ebrus 0:0a673c671a56 1822 status = HAL_ERROR;
ebrus 0:0a673c671a56 1823 }
ebrus 0:0a673c671a56 1824 /* Check SDADC state */
ebrus 0:0a673c671a56 1825 else if((hsdadc->State != HAL_SDADC_STATE_REG) && \
ebrus 0:0a673c671a56 1826 (hsdadc->State != HAL_SDADC_STATE_REG_INJ))
ebrus 0:0a673c671a56 1827 {
ebrus 0:0a673c671a56 1828 /* Return error status */
ebrus 0:0a673c671a56 1829 status = HAL_ERROR;
ebrus 0:0a673c671a56 1830 }
ebrus 0:0a673c671a56 1831 else
ebrus 0:0a673c671a56 1832 {
ebrus 0:0a673c671a56 1833 /* Clear RDMAEN bit in SDADC_CR1 register */
ebrus 0:0a673c671a56 1834 hsdadc->Instance->CR1 &= ~(SDADC_CR1_RDMAEN);
ebrus 0:0a673c671a56 1835
ebrus 0:0a673c671a56 1836 /* Stop current DMA transfer */
ebrus 0:0a673c671a56 1837 if(HAL_DMA_Abort(hsdadc->hdma) != HAL_OK)
ebrus 0:0a673c671a56 1838 {
ebrus 0:0a673c671a56 1839 /* Set SDADC in error state */
ebrus 0:0a673c671a56 1840 hsdadc->State = HAL_SDADC_STATE_ERROR;
ebrus 0:0a673c671a56 1841 status = HAL_ERROR;
ebrus 0:0a673c671a56 1842 }
ebrus 0:0a673c671a56 1843 else
ebrus 0:0a673c671a56 1844 {
ebrus 0:0a673c671a56 1845 /* Stop regular conversion */
ebrus 0:0a673c671a56 1846 status = SDADC_RegConvStop(hsdadc);
ebrus 0:0a673c671a56 1847 }
ebrus 0:0a673c671a56 1848 }
ebrus 0:0a673c671a56 1849 /* Return function status */
ebrus 0:0a673c671a56 1850 return status;
ebrus 0:0a673c671a56 1851 }
ebrus 0:0a673c671a56 1852
ebrus 0:0a673c671a56 1853 /**
ebrus 0:0a673c671a56 1854 * @brief This function allows to get multimode regular conversion value.
ebrus 0:0a673c671a56 1855 * @param hsdadc : SDADC handle.
ebrus 0:0a673c671a56 1856 * @retval Multimode regular conversion value
ebrus 0:0a673c671a56 1857 */
ebrus 0:0a673c671a56 1858 uint32_t HAL_SDADC_MultiModeGetValue(SDADC_HandleTypeDef* hsdadc)
ebrus 0:0a673c671a56 1859 {
ebrus 0:0a673c671a56 1860 uint32_t value = 0;
ebrus 0:0a673c671a56 1861
ebrus 0:0a673c671a56 1862 /* Check parameters and check instance is SDADC1 */
ebrus 0:0a673c671a56 1863 assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
ebrus 0:0a673c671a56 1864 assert_param(hsdadc->Instance == SDADC1);
ebrus 0:0a673c671a56 1865
ebrus 0:0a673c671a56 1866 /* read multimode regular value */
ebrus 0:0a673c671a56 1867 value = (hsdadc->RegularMultimode == SDADC_MULTIMODE_SDADC1_SDADC2) ? \
ebrus 0:0a673c671a56 1868 hsdadc->Instance->RDATA12R : hsdadc->Instance->RDATA13R;
ebrus 0:0a673c671a56 1869
ebrus 0:0a673c671a56 1870 /* Return multimode regular conversions value */
ebrus 0:0a673c671a56 1871 return value;
ebrus 0:0a673c671a56 1872 }
ebrus 0:0a673c671a56 1873
ebrus 0:0a673c671a56 1874 /**
ebrus 0:0a673c671a56 1875 * @brief This function allows to start multimode injected conversions in DMA mode.
ebrus 0:0a673c671a56 1876 * @note This function should be called only when SDADC instance is in idle state
ebrus 0:0a673c671a56 1877 * or if regular conversion is ongoing.
ebrus 0:0a673c671a56 1878 * @param hsdadc : SDADC handle.
ebrus 0:0a673c671a56 1879 * @param pData : The destination buffer address.
ebrus 0:0a673c671a56 1880 * @param Length : The length of data to be transferred from SDADC peripheral to memory.
ebrus 0:0a673c671a56 1881 * @retval HAL status
ebrus 0:0a673c671a56 1882 */
ebrus 0:0a673c671a56 1883 HAL_StatusTypeDef HAL_SDADC_InjectedMultiModeStart_DMA(SDADC_HandleTypeDef* hsdadc,
ebrus 0:0a673c671a56 1884 uint32_t* pData, uint32_t Length)
ebrus 0:0a673c671a56 1885 {
ebrus 0:0a673c671a56 1886 HAL_StatusTypeDef status = HAL_OK;
ebrus 0:0a673c671a56 1887
ebrus 0:0a673c671a56 1888 /* Check parameters */
ebrus 0:0a673c671a56 1889 assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
ebrus 0:0a673c671a56 1890 assert_param(pData != NULL);
ebrus 0:0a673c671a56 1891 assert_param(Length != 0);
ebrus 0:0a673c671a56 1892
ebrus 0:0a673c671a56 1893 /* Check instance is SDADC1 */
ebrus 0:0a673c671a56 1894 if(hsdadc->Instance != SDADC1)
ebrus 0:0a673c671a56 1895 {
ebrus 0:0a673c671a56 1896 status = HAL_ERROR;
ebrus 0:0a673c671a56 1897 }
ebrus 0:0a673c671a56 1898 /* Check that DMA is not enabled for regular conversion */
ebrus 0:0a673c671a56 1899 else if((hsdadc->Instance->CR1 & SDADC_CR1_RDMAEN) == SDADC_CR1_RDMAEN)
ebrus 0:0a673c671a56 1900 {
ebrus 0:0a673c671a56 1901 status = HAL_ERROR;
ebrus 0:0a673c671a56 1902 }
ebrus 0:0a673c671a56 1903 /* Check parameters compatibility */
ebrus 0:0a673c671a56 1904 else if((hsdadc->InjectedTrigger == SDADC_SOFTWARE_TRIGGER) && \
ebrus 0:0a673c671a56 1905 (hsdadc->InjectedContMode == SDADC_CONTINUOUS_CONV_OFF) && \
ebrus 0:0a673c671a56 1906 (hsdadc->hdma->Init.Mode == DMA_NORMAL) && \
ebrus 0:0a673c671a56 1907 (Length > (hsdadc->InjectedChannelsNbr << 1)))
ebrus 0:0a673c671a56 1908 {
ebrus 0:0a673c671a56 1909 status = HAL_ERROR;
ebrus 0:0a673c671a56 1910 }
ebrus 0:0a673c671a56 1911 else if((hsdadc->InjectedTrigger == SDADC_SOFTWARE_TRIGGER) && \
ebrus 0:0a673c671a56 1912 (hsdadc->InjectedContMode == SDADC_CONTINUOUS_CONV_OFF) && \
ebrus 0:0a673c671a56 1913 (hsdadc->hdma->Init.Mode == DMA_CIRCULAR))
ebrus 0:0a673c671a56 1914 {
ebrus 0:0a673c671a56 1915 status = HAL_ERROR;
ebrus 0:0a673c671a56 1916 }
ebrus 0:0a673c671a56 1917 /* Check SDADC state */
ebrus 0:0a673c671a56 1918 else if((hsdadc->State == HAL_SDADC_STATE_READY) || \
ebrus 0:0a673c671a56 1919 (hsdadc->State == HAL_SDADC_STATE_REG))
ebrus 0:0a673c671a56 1920 {
ebrus 0:0a673c671a56 1921 /* Set callbacks on DMA handler */
ebrus 0:0a673c671a56 1922 hsdadc->hdma->XferCpltCallback = SDADC_DMAInjectedConvCplt;
ebrus 0:0a673c671a56 1923 hsdadc->hdma->XferErrorCallback = SDADC_DMAError;
ebrus 0:0a673c671a56 1924 if(hsdadc->hdma->Init.Mode == DMA_CIRCULAR)
ebrus 0:0a673c671a56 1925 {
ebrus 0:0a673c671a56 1926 hsdadc->hdma->XferHalfCpltCallback = SDADC_DMAInjectedHalfConvCplt;
ebrus 0:0a673c671a56 1927 }
ebrus 0:0a673c671a56 1928 /* Set JDMAEN bit in SDADC_CR1 register */
ebrus 0:0a673c671a56 1929 hsdadc->Instance->CR1 |= SDADC_CR1_JDMAEN;
ebrus 0:0a673c671a56 1930
ebrus 0:0a673c671a56 1931 /* Start DMA in interrupt mode */
ebrus 0:0a673c671a56 1932 if(hsdadc->InjectedMultimode == SDADC_MULTIMODE_SDADC1_SDADC2)
ebrus 0:0a673c671a56 1933 {
ebrus 0:0a673c671a56 1934 status = HAL_DMA_Start_IT(hsdadc->hdma, (uint32_t)&hsdadc->Instance->JDATA12R, \
ebrus 0:0a673c671a56 1935 (uint32_t) pData, Length);
ebrus 0:0a673c671a56 1936 }
ebrus 0:0a673c671a56 1937 else
ebrus 0:0a673c671a56 1938 {
ebrus 0:0a673c671a56 1939 status = HAL_DMA_Start_IT(hsdadc->hdma, (uint32_t)&hsdadc->Instance->JDATA13R, \
ebrus 0:0a673c671a56 1940 (uint32_t) pData, Length);
ebrus 0:0a673c671a56 1941 }
ebrus 0:0a673c671a56 1942 if(status != HAL_OK)
ebrus 0:0a673c671a56 1943 {
ebrus 0:0a673c671a56 1944 /* Set SDADC in error state */
ebrus 0:0a673c671a56 1945 hsdadc->State = HAL_SDADC_STATE_ERROR;
ebrus 0:0a673c671a56 1946 status = HAL_ERROR;
ebrus 0:0a673c671a56 1947 }
ebrus 0:0a673c671a56 1948 else
ebrus 0:0a673c671a56 1949 {
ebrus 0:0a673c671a56 1950 /* Start injected conversion */
ebrus 0:0a673c671a56 1951 status = SDADC_InjConvStart(hsdadc);
ebrus 0:0a673c671a56 1952 }
ebrus 0:0a673c671a56 1953 }
ebrus 0:0a673c671a56 1954 else
ebrus 0:0a673c671a56 1955 {
ebrus 0:0a673c671a56 1956 status = HAL_ERROR;
ebrus 0:0a673c671a56 1957 }
ebrus 0:0a673c671a56 1958 /* Return function status */
ebrus 0:0a673c671a56 1959 return status;
ebrus 0:0a673c671a56 1960 }
ebrus 0:0a673c671a56 1961
ebrus 0:0a673c671a56 1962 /**
ebrus 0:0a673c671a56 1963 * @brief This function allows to stop multimode injected conversions in DMA mode.
ebrus 0:0a673c671a56 1964 * @note This function should be called only if injected conversion is ongoing.
ebrus 0:0a673c671a56 1965 * @param hsdadc : SDADC handle.
ebrus 0:0a673c671a56 1966 * @retval HAL status
ebrus 0:0a673c671a56 1967 */
ebrus 0:0a673c671a56 1968 HAL_StatusTypeDef HAL_SDADC_InjectedMultiModeStop_DMA(SDADC_HandleTypeDef* hsdadc)
ebrus 0:0a673c671a56 1969 {
ebrus 0:0a673c671a56 1970 HAL_StatusTypeDef status = HAL_OK;
ebrus 0:0a673c671a56 1971
ebrus 0:0a673c671a56 1972 /* Check parameters */
ebrus 0:0a673c671a56 1973 assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
ebrus 0:0a673c671a56 1974
ebrus 0:0a673c671a56 1975 /* Check instance is SDADC1 */
ebrus 0:0a673c671a56 1976 if(hsdadc->Instance != SDADC1)
ebrus 0:0a673c671a56 1977 {
ebrus 0:0a673c671a56 1978 status = HAL_ERROR;
ebrus 0:0a673c671a56 1979 }
ebrus 0:0a673c671a56 1980 /* Check SDADC state */
ebrus 0:0a673c671a56 1981 else if((hsdadc->State != HAL_SDADC_STATE_INJ) && \
ebrus 0:0a673c671a56 1982 (hsdadc->State != HAL_SDADC_STATE_REG_INJ))
ebrus 0:0a673c671a56 1983 {
ebrus 0:0a673c671a56 1984 /* Return error status */
ebrus 0:0a673c671a56 1985 status = HAL_ERROR;
ebrus 0:0a673c671a56 1986 }
ebrus 0:0a673c671a56 1987 else
ebrus 0:0a673c671a56 1988 {
ebrus 0:0a673c671a56 1989 /* Clear JDMAEN bit in SDADC_CR1 register */
ebrus 0:0a673c671a56 1990 hsdadc->Instance->CR1 &= ~(SDADC_CR1_JDMAEN);
ebrus 0:0a673c671a56 1991
ebrus 0:0a673c671a56 1992 /* Stop current DMA transfer */
ebrus 0:0a673c671a56 1993 if(HAL_DMA_Abort(hsdadc->hdma) != HAL_OK)
ebrus 0:0a673c671a56 1994 {
ebrus 0:0a673c671a56 1995 /* Set SDADC in error state */
ebrus 0:0a673c671a56 1996 hsdadc->State = HAL_SDADC_STATE_ERROR;
ebrus 0:0a673c671a56 1997 status = HAL_ERROR;
ebrus 0:0a673c671a56 1998 }
ebrus 0:0a673c671a56 1999 else
ebrus 0:0a673c671a56 2000 {
ebrus 0:0a673c671a56 2001 /* Stop injected conversion */
ebrus 0:0a673c671a56 2002 status = SDADC_InjConvStop(hsdadc);
ebrus 0:0a673c671a56 2003 }
ebrus 0:0a673c671a56 2004 }
ebrus 0:0a673c671a56 2005 /* Return function status */
ebrus 0:0a673c671a56 2006 return status;
ebrus 0:0a673c671a56 2007 }
ebrus 0:0a673c671a56 2008
ebrus 0:0a673c671a56 2009 /**
ebrus 0:0a673c671a56 2010 * @brief This function allows to get multimode injected conversion value.
ebrus 0:0a673c671a56 2011 * @param hsdadc : SDADC handle.
ebrus 0:0a673c671a56 2012 * @retval Multimode injected conversion value
ebrus 0:0a673c671a56 2013 */
ebrus 0:0a673c671a56 2014 uint32_t HAL_SDADC_InjectedMultiModeGetValue(SDADC_HandleTypeDef* hsdadc)
ebrus 0:0a673c671a56 2015 {
ebrus 0:0a673c671a56 2016 uint32_t value = 0;
ebrus 0:0a673c671a56 2017
ebrus 0:0a673c671a56 2018 /* Check parameters and check instance is SDADC1 */
ebrus 0:0a673c671a56 2019 assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
ebrus 0:0a673c671a56 2020 assert_param(hsdadc->Instance == SDADC1);
ebrus 0:0a673c671a56 2021
ebrus 0:0a673c671a56 2022 /* read multimode injected value */
ebrus 0:0a673c671a56 2023 value = (hsdadc->InjectedMultimode == SDADC_MULTIMODE_SDADC1_SDADC2) ? \
ebrus 0:0a673c671a56 2024 hsdadc->Instance->JDATA12R : hsdadc->Instance->JDATA13R;
ebrus 0:0a673c671a56 2025
ebrus 0:0a673c671a56 2026 /* Return multimode injected conversions value */
ebrus 0:0a673c671a56 2027 return value;
ebrus 0:0a673c671a56 2028 }
ebrus 0:0a673c671a56 2029
ebrus 0:0a673c671a56 2030 /**
ebrus 0:0a673c671a56 2031 * @brief This function handles the SDADC interrupts.
ebrus 0:0a673c671a56 2032 * @param hsdadc : SDADC handle.
ebrus 0:0a673c671a56 2033 * @retval None
ebrus 0:0a673c671a56 2034 */
ebrus 0:0a673c671a56 2035 void HAL_SDADC_IRQHandler(SDADC_HandleTypeDef* hsdadc)
ebrus 0:0a673c671a56 2036 {
ebrus 0:0a673c671a56 2037 /* Check if end of regular conversion */
ebrus 0:0a673c671a56 2038 if(((hsdadc->Instance->ISR & SDADC_ISR_REOCF) == SDADC_ISR_REOCF) && \
ebrus 0:0a673c671a56 2039 ((hsdadc->Instance->CR1 & SDADC_CR1_REOCIE) == SDADC_CR1_REOCIE))
ebrus 0:0a673c671a56 2040 {
ebrus 0:0a673c671a56 2041 /* Call regular conversion complete callback */
ebrus 0:0a673c671a56 2042 HAL_SDADC_ConvCpltCallback(hsdadc);
ebrus 0:0a673c671a56 2043
ebrus 0:0a673c671a56 2044 /* End of conversion if mode is not continuous and software trigger */
ebrus 0:0a673c671a56 2045 if((hsdadc->RegularContMode == SDADC_CONTINUOUS_CONV_OFF) && \
ebrus 0:0a673c671a56 2046 (hsdadc->RegularTrigger == SDADC_SOFTWARE_TRIGGER))
ebrus 0:0a673c671a56 2047 {
ebrus 0:0a673c671a56 2048 /* Clear REOCIE and ROVRIE bits in SDADC_CR1 register */
ebrus 0:0a673c671a56 2049 hsdadc->Instance->CR1 &= ~(SDADC_CR1_REOCIE | SDADC_CR1_ROVRIE);
ebrus 0:0a673c671a56 2050
ebrus 0:0a673c671a56 2051 /* Update SDADC state */
ebrus 0:0a673c671a56 2052 hsdadc->State = (hsdadc->State == HAL_SDADC_STATE_REG) ? \
ebrus 0:0a673c671a56 2053 HAL_SDADC_STATE_READY : HAL_SDADC_STATE_INJ;
ebrus 0:0a673c671a56 2054 }
ebrus 0:0a673c671a56 2055 }
ebrus 0:0a673c671a56 2056 /* Check if end of injected conversion */
ebrus 0:0a673c671a56 2057 else if(((hsdadc->Instance->ISR & SDADC_ISR_JEOCF) == SDADC_ISR_JEOCF) && \
ebrus 0:0a673c671a56 2058 ((hsdadc->Instance->CR1 & SDADC_CR1_JEOCIE) == SDADC_CR1_JEOCIE))
ebrus 0:0a673c671a56 2059 {
ebrus 0:0a673c671a56 2060 /* Call injected conversion complete callback */
ebrus 0:0a673c671a56 2061 HAL_SDADC_InjectedConvCpltCallback(hsdadc);
ebrus 0:0a673c671a56 2062
ebrus 0:0a673c671a56 2063 /* Update remaining injected conversions */
ebrus 0:0a673c671a56 2064 hsdadc->InjConvRemaining--;
ebrus 0:0a673c671a56 2065 if(hsdadc->InjConvRemaining ==0)
ebrus 0:0a673c671a56 2066 {
ebrus 0:0a673c671a56 2067 /* end of injected sequence, reset the value */
ebrus 0:0a673c671a56 2068 hsdadc->InjConvRemaining = hsdadc->InjectedChannelsNbr;
ebrus 0:0a673c671a56 2069 }
ebrus 0:0a673c671a56 2070 /* End of conversion if mode is not continuous, software trigger */
ebrus 0:0a673c671a56 2071 /* and end of injected sequence */
ebrus 0:0a673c671a56 2072 if((hsdadc->InjectedContMode == SDADC_CONTINUOUS_CONV_OFF) && \
ebrus 0:0a673c671a56 2073 (hsdadc->InjectedTrigger == SDADC_SOFTWARE_TRIGGER) && \
ebrus 0:0a673c671a56 2074 (hsdadc->InjConvRemaining == hsdadc->InjectedChannelsNbr))
ebrus 0:0a673c671a56 2075 {
ebrus 0:0a673c671a56 2076 /* Clear JEOCIE and JOVRIE bits in SDADC_CR1 register */
ebrus 0:0a673c671a56 2077 hsdadc->Instance->CR1 &= ~(SDADC_CR1_JEOCIE | SDADC_CR1_JOVRIE);
ebrus 0:0a673c671a56 2078
ebrus 0:0a673c671a56 2079 /* Update SDADC state */
ebrus 0:0a673c671a56 2080 hsdadc->State = (hsdadc->State == HAL_SDADC_STATE_INJ) ? \
ebrus 0:0a673c671a56 2081 HAL_SDADC_STATE_READY : HAL_SDADC_STATE_REG;
ebrus 0:0a673c671a56 2082 }
ebrus 0:0a673c671a56 2083 }
ebrus 0:0a673c671a56 2084 /* Check if end of calibration */
ebrus 0:0a673c671a56 2085 else if(((hsdadc->Instance->ISR & SDADC_ISR_EOCALF) == SDADC_ISR_EOCALF) && \
ebrus 0:0a673c671a56 2086 ((hsdadc->Instance->CR1 & SDADC_CR1_EOCALIE) == SDADC_CR1_EOCALIE))
ebrus 0:0a673c671a56 2087 {
ebrus 0:0a673c671a56 2088 /* Clear EOCALIE bit in SDADC_CR1 register */
ebrus 0:0a673c671a56 2089 hsdadc->Instance->CR1 &= ~(SDADC_CR1_EOCALIE);
ebrus 0:0a673c671a56 2090
ebrus 0:0a673c671a56 2091 /* Set CLREOCALF bit in SDADC_CLRISR register */
ebrus 0:0a673c671a56 2092 hsdadc->Instance->CLRISR |= SDADC_ISR_CLREOCALF;
ebrus 0:0a673c671a56 2093
ebrus 0:0a673c671a56 2094 /* Call calibration callback */
ebrus 0:0a673c671a56 2095 HAL_SDADC_CalibrationCpltCallback(hsdadc);
ebrus 0:0a673c671a56 2096
ebrus 0:0a673c671a56 2097 /* Update SDADC state */
ebrus 0:0a673c671a56 2098 hsdadc->State = HAL_SDADC_STATE_READY;
ebrus 0:0a673c671a56 2099 }
ebrus 0:0a673c671a56 2100 /* Check if overrun occurs during regular conversion */
ebrus 0:0a673c671a56 2101 else if(((hsdadc->Instance->ISR & SDADC_ISR_ROVRF) == SDADC_ISR_ROVRF) && \
ebrus 0:0a673c671a56 2102 ((hsdadc->Instance->CR1 & SDADC_CR1_ROVRIE) == SDADC_CR1_ROVRIE))
ebrus 0:0a673c671a56 2103 {
ebrus 0:0a673c671a56 2104 /* Set CLRROVRF bit in SDADC_CLRISR register */
ebrus 0:0a673c671a56 2105 hsdadc->Instance->CLRISR |= SDADC_ISR_CLRROVRF;
ebrus 0:0a673c671a56 2106
ebrus 0:0a673c671a56 2107 /* Update error code */
ebrus 0:0a673c671a56 2108 hsdadc->ErrorCode = SDADC_ERROR_REGULAR_OVERRUN;
ebrus 0:0a673c671a56 2109
ebrus 0:0a673c671a56 2110 /* Call error callback */
ebrus 0:0a673c671a56 2111 HAL_SDADC_ErrorCallback(hsdadc);
ebrus 0:0a673c671a56 2112 }
ebrus 0:0a673c671a56 2113 /* Check if overrun occurs during injected conversion */
ebrus 0:0a673c671a56 2114 else if(((hsdadc->Instance->ISR & SDADC_ISR_JOVRF) == SDADC_ISR_JOVRF) && \
ebrus 0:0a673c671a56 2115 ((hsdadc->Instance->CR1 & SDADC_CR1_JOVRIE) == SDADC_CR1_JOVRIE))
ebrus 0:0a673c671a56 2116 {
ebrus 0:0a673c671a56 2117 /* Set CLRJOVRF bit in SDADC_CLRISR register */
ebrus 0:0a673c671a56 2118 hsdadc->Instance->CLRISR |= SDADC_ISR_CLRJOVRF;
ebrus 0:0a673c671a56 2119
ebrus 0:0a673c671a56 2120 /* Update error code */
ebrus 0:0a673c671a56 2121 hsdadc->ErrorCode = SDADC_ERROR_INJECTED_OVERRUN;
ebrus 0:0a673c671a56 2122
ebrus 0:0a673c671a56 2123 /* Call error callback */
ebrus 0:0a673c671a56 2124 HAL_SDADC_ErrorCallback(hsdadc);
ebrus 0:0a673c671a56 2125 }
ebrus 0:0a673c671a56 2126 return;
ebrus 0:0a673c671a56 2127 }
ebrus 0:0a673c671a56 2128
ebrus 0:0a673c671a56 2129 /**
ebrus 0:0a673c671a56 2130 * @brief Calibration complete callback.
ebrus 0:0a673c671a56 2131 * @param hsdadc : SDADC handle.
ebrus 0:0a673c671a56 2132 * @retval None
ebrus 0:0a673c671a56 2133 */
ebrus 0:0a673c671a56 2134 __weak void HAL_SDADC_CalibrationCpltCallback(SDADC_HandleTypeDef* hsdadc)
ebrus 0:0a673c671a56 2135 {
ebrus 0:0a673c671a56 2136 /* NOTE : This function should not be modified, when the callback is needed,
ebrus 0:0a673c671a56 2137 the HAL_SDADC_CalibrationCpltCallback could be implemented in the user file
ebrus 0:0a673c671a56 2138 */
ebrus 0:0a673c671a56 2139 }
ebrus 0:0a673c671a56 2140
ebrus 0:0a673c671a56 2141 /**
ebrus 0:0a673c671a56 2142 * @brief Half regular conversion complete callback.
ebrus 0:0a673c671a56 2143 * @param hsdadc : SDADC handle.
ebrus 0:0a673c671a56 2144 * @retval None
ebrus 0:0a673c671a56 2145 */
ebrus 0:0a673c671a56 2146 __weak void HAL_SDADC_ConvHalfCpltCallback(SDADC_HandleTypeDef* hsdadc)
ebrus 0:0a673c671a56 2147 {
ebrus 0:0a673c671a56 2148 /* NOTE : This function should not be modified, when the callback is needed,
ebrus 0:0a673c671a56 2149 the HAL_SDADC_ConvHalfCpltCallback could be implemented in the user file
ebrus 0:0a673c671a56 2150 */
ebrus 0:0a673c671a56 2151 }
ebrus 0:0a673c671a56 2152
ebrus 0:0a673c671a56 2153 /**
ebrus 0:0a673c671a56 2154 * @brief Regular conversion complete callback.
ebrus 0:0a673c671a56 2155 * @note In interrupt mode, user has to read conversion value in this function
ebrus 0:0a673c671a56 2156 using HAL_SDADC_GetValue or HAL_SDADC_MultiModeGetValue.
ebrus 0:0a673c671a56 2157 * @param hsdadc : SDADC handle.
ebrus 0:0a673c671a56 2158 * @retval None
ebrus 0:0a673c671a56 2159 */
ebrus 0:0a673c671a56 2160 __weak void HAL_SDADC_ConvCpltCallback(SDADC_HandleTypeDef* hsdadc)
ebrus 0:0a673c671a56 2161 {
ebrus 0:0a673c671a56 2162 /* NOTE : This function should not be modified, when the callback is needed,
ebrus 0:0a673c671a56 2163 the HAL_SDADC_ConvCpltCallback could be implemented in the user file.
ebrus 0:0a673c671a56 2164 */
ebrus 0:0a673c671a56 2165 }
ebrus 0:0a673c671a56 2166
ebrus 0:0a673c671a56 2167 /**
ebrus 0:0a673c671a56 2168 * @brief Half injected conversion complete callback.
ebrus 0:0a673c671a56 2169 * @param hsdadc : SDADC handle.
ebrus 0:0a673c671a56 2170 * @retval None
ebrus 0:0a673c671a56 2171 */
ebrus 0:0a673c671a56 2172 __weak void HAL_SDADC_InjectedConvHalfCpltCallback(SDADC_HandleTypeDef* hsdadc)
ebrus 0:0a673c671a56 2173 {
ebrus 0:0a673c671a56 2174 /* NOTE : This function should not be modified, when the callback is needed,
ebrus 0:0a673c671a56 2175 the HAL_SDADC_InjectedConvHalfCpltCallback could be implemented in the user file.
ebrus 0:0a673c671a56 2176 */
ebrus 0:0a673c671a56 2177 }
ebrus 0:0a673c671a56 2178
ebrus 0:0a673c671a56 2179 /**
ebrus 0:0a673c671a56 2180 * @brief Injected conversion complete callback.
ebrus 0:0a673c671a56 2181 * @note In interrupt mode, user has to read conversion value in this function
ebrus 0:0a673c671a56 2182 using HAL_SDADC_InjectedGetValue or HAL_SDADC_InjectedMultiModeGetValue.
ebrus 0:0a673c671a56 2183 * @param hsdadc : SDADC handle.
ebrus 0:0a673c671a56 2184 * @retval None
ebrus 0:0a673c671a56 2185 */
ebrus 0:0a673c671a56 2186 __weak void HAL_SDADC_InjectedConvCpltCallback(SDADC_HandleTypeDef* hsdadc)
ebrus 0:0a673c671a56 2187 {
ebrus 0:0a673c671a56 2188 /* NOTE : This function should not be modified, when the callback is needed,
ebrus 0:0a673c671a56 2189 the HAL_SDADC_InjectedConvCpltCallback could be implemented in the user file.
ebrus 0:0a673c671a56 2190 */
ebrus 0:0a673c671a56 2191 }
ebrus 0:0a673c671a56 2192
ebrus 0:0a673c671a56 2193 /**
ebrus 0:0a673c671a56 2194 * @brief Error callback.
ebrus 0:0a673c671a56 2195 * @param hsdadc : SDADC handle.
ebrus 0:0a673c671a56 2196 * @retval None
ebrus 0:0a673c671a56 2197 */
ebrus 0:0a673c671a56 2198 __weak void HAL_SDADC_ErrorCallback(SDADC_HandleTypeDef* hsdadc)
ebrus 0:0a673c671a56 2199 {
ebrus 0:0a673c671a56 2200 /* NOTE : This function should not be modified, when the callback is needed,
ebrus 0:0a673c671a56 2201 the HAL_SDADC_ErrorCallback could be implemented in the user file.
ebrus 0:0a673c671a56 2202 */
ebrus 0:0a673c671a56 2203 }
ebrus 0:0a673c671a56 2204
ebrus 0:0a673c671a56 2205 /**
ebrus 0:0a673c671a56 2206 * @brief DMA half transfer complete callback for regular conversion.
ebrus 0:0a673c671a56 2207 * @param hdma : DMA handle.
ebrus 0:0a673c671a56 2208 * @retval None
ebrus 0:0a673c671a56 2209 */
ebrus 0:0a673c671a56 2210 static void SDADC_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma)
ebrus 0:0a673c671a56 2211 {
ebrus 0:0a673c671a56 2212 /* Get SDADC handle */
ebrus 0:0a673c671a56 2213 SDADC_HandleTypeDef* hsdadc = (SDADC_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
ebrus 0:0a673c671a56 2214
ebrus 0:0a673c671a56 2215 /* Call regular half conversion complete callback */
ebrus 0:0a673c671a56 2216 HAL_SDADC_ConvHalfCpltCallback(hsdadc);
ebrus 0:0a673c671a56 2217 }
ebrus 0:0a673c671a56 2218
ebrus 0:0a673c671a56 2219 /**
ebrus 0:0a673c671a56 2220 * @brief DMA transfer complete callback for regular conversion.
ebrus 0:0a673c671a56 2221 * @param hdma : DMA handle.
ebrus 0:0a673c671a56 2222 * @retval None
ebrus 0:0a673c671a56 2223 */
ebrus 0:0a673c671a56 2224 static void SDADC_DMARegularConvCplt(DMA_HandleTypeDef *hdma)
ebrus 0:0a673c671a56 2225 {
ebrus 0:0a673c671a56 2226 /* Get SDADC handle */
ebrus 0:0a673c671a56 2227 SDADC_HandleTypeDef* hsdadc = (SDADC_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
ebrus 0:0a673c671a56 2228
ebrus 0:0a673c671a56 2229 /* Call regular conversion complete callback */
ebrus 0:0a673c671a56 2230 HAL_SDADC_ConvCpltCallback(hsdadc);
ebrus 0:0a673c671a56 2231 }
ebrus 0:0a673c671a56 2232
ebrus 0:0a673c671a56 2233 /**
ebrus 0:0a673c671a56 2234 * @brief DMA half transfer complete callback for injected conversion.
ebrus 0:0a673c671a56 2235 * @param hdma : DMA handle.
ebrus 0:0a673c671a56 2236 * @retval None
ebrus 0:0a673c671a56 2237 */
ebrus 0:0a673c671a56 2238 static void SDADC_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma)
ebrus 0:0a673c671a56 2239 {
ebrus 0:0a673c671a56 2240 /* Get SDADC handle */
ebrus 0:0a673c671a56 2241 SDADC_HandleTypeDef* hsdadc = (SDADC_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
ebrus 0:0a673c671a56 2242
ebrus 0:0a673c671a56 2243 /* Call injected half conversion complete callback */
ebrus 0:0a673c671a56 2244 HAL_SDADC_InjectedConvHalfCpltCallback(hsdadc);
ebrus 0:0a673c671a56 2245 }
ebrus 0:0a673c671a56 2246
ebrus 0:0a673c671a56 2247 /**
ebrus 0:0a673c671a56 2248 * @brief DMA transfer complete callback for injected conversion.
ebrus 0:0a673c671a56 2249 * @param hdma : DMA handle.
ebrus 0:0a673c671a56 2250 * @retval None
ebrus 0:0a673c671a56 2251 */
ebrus 0:0a673c671a56 2252 static void SDADC_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma)
ebrus 0:0a673c671a56 2253 {
ebrus 0:0a673c671a56 2254 /* Get SDADC handle */
ebrus 0:0a673c671a56 2255 SDADC_HandleTypeDef* hsdadc = (SDADC_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
ebrus 0:0a673c671a56 2256
ebrus 0:0a673c671a56 2257 /* Call injected conversion complete callback */
ebrus 0:0a673c671a56 2258 HAL_SDADC_InjectedConvCpltCallback(hsdadc);
ebrus 0:0a673c671a56 2259 }
ebrus 0:0a673c671a56 2260
ebrus 0:0a673c671a56 2261 /**
ebrus 0:0a673c671a56 2262 * @brief DMA error callback.
ebrus 0:0a673c671a56 2263 * @param hdma : DMA handle.
ebrus 0:0a673c671a56 2264 * @retval None
ebrus 0:0a673c671a56 2265 */
ebrus 0:0a673c671a56 2266 static void SDADC_DMAError(DMA_HandleTypeDef *hdma)
ebrus 0:0a673c671a56 2267 {
ebrus 0:0a673c671a56 2268 /* Get SDADC handle */
ebrus 0:0a673c671a56 2269 SDADC_HandleTypeDef* hsdadc = (SDADC_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
ebrus 0:0a673c671a56 2270
ebrus 0:0a673c671a56 2271 /* Update error code */
ebrus 0:0a673c671a56 2272 hsdadc->ErrorCode = SDADC_ERROR_DMA;
ebrus 0:0a673c671a56 2273
ebrus 0:0a673c671a56 2274 /* Call error callback */
ebrus 0:0a673c671a56 2275 HAL_SDADC_ErrorCallback(hsdadc);
ebrus 0:0a673c671a56 2276 }
ebrus 0:0a673c671a56 2277
ebrus 0:0a673c671a56 2278 /**
ebrus 0:0a673c671a56 2279 * @}
ebrus 0:0a673c671a56 2280 */
ebrus 0:0a673c671a56 2281
ebrus 0:0a673c671a56 2282 /** @defgroup SDADC_Group4 SDADC Peripheral State functions
ebrus 0:0a673c671a56 2283 * @brief SDADC Peripheral State functions
ebrus 0:0a673c671a56 2284 *
ebrus 0:0a673c671a56 2285 @verbatim
ebrus 0:0a673c671a56 2286 ===============================================================================
ebrus 0:0a673c671a56 2287 ##### ADC Peripheral State functions #####
ebrus 0:0a673c671a56 2288 ===============================================================================
ebrus 0:0a673c671a56 2289 [..] This subsection provides functions allowing to
ebrus 0:0a673c671a56 2290 (+) Get the SDADC state
ebrus 0:0a673c671a56 2291 (+) Get the SDADC Error
ebrus 0:0a673c671a56 2292
ebrus 0:0a673c671a56 2293 @endverbatim
ebrus 0:0a673c671a56 2294 * @{
ebrus 0:0a673c671a56 2295 */
ebrus 0:0a673c671a56 2296
ebrus 0:0a673c671a56 2297 /**
ebrus 0:0a673c671a56 2298 * @brief This function allows to get the current SDADC state.
ebrus 0:0a673c671a56 2299 * @param hsdadc : SDADC handle.
ebrus 0:0a673c671a56 2300 * @retval SDADC state.
ebrus 0:0a673c671a56 2301 */
ebrus 0:0a673c671a56 2302 HAL_SDADC_StateTypeDef HAL_SDADC_GetState(SDADC_HandleTypeDef* hsdadc)
ebrus 0:0a673c671a56 2303 {
ebrus 0:0a673c671a56 2304 return hsdadc->State;
ebrus 0:0a673c671a56 2305 }
ebrus 0:0a673c671a56 2306
ebrus 0:0a673c671a56 2307 /**
ebrus 0:0a673c671a56 2308 * @brief This function allows to get the current SDADC error code.
ebrus 0:0a673c671a56 2309 * @param hsdadc : SDADC handle.
ebrus 0:0a673c671a56 2310 * @retval SDADC error code.
ebrus 0:0a673c671a56 2311 */
ebrus 0:0a673c671a56 2312 uint32_t HAL_SDADC_GetError(SDADC_HandleTypeDef* hsdadc)
ebrus 0:0a673c671a56 2313 {
ebrus 0:0a673c671a56 2314 return hsdadc->ErrorCode;
ebrus 0:0a673c671a56 2315 }
ebrus 0:0a673c671a56 2316
ebrus 0:0a673c671a56 2317 /**
ebrus 0:0a673c671a56 2318 * @}
ebrus 0:0a673c671a56 2319 */
ebrus 0:0a673c671a56 2320
ebrus 0:0a673c671a56 2321 /**
ebrus 0:0a673c671a56 2322 * @brief This function allows to enter in init mode for SDADC instance.
ebrus 0:0a673c671a56 2323 * @param hsdadc : SDADC handle.
ebrus 0:0a673c671a56 2324 * @retval HAL status.
ebrus 0:0a673c671a56 2325 */
ebrus 0:0a673c671a56 2326 static HAL_StatusTypeDef SDADC_EnterInitMode(SDADC_HandleTypeDef* hsdadc)
ebrus 0:0a673c671a56 2327 {
ebrus 0:0a673c671a56 2328 uint32_t tickstart = 0;
ebrus 0:0a673c671a56 2329
ebrus 0:0a673c671a56 2330 /* Set INIT bit on SDADC_CR1 register */
ebrus 0:0a673c671a56 2331 hsdadc->Instance->CR1 |= SDADC_CR1_INIT;
ebrus 0:0a673c671a56 2332
ebrus 0:0a673c671a56 2333 /* Wait INITRDY bit on SDADC_ISR */
ebrus 0:0a673c671a56 2334 tickstart = HAL_GetTick();
ebrus 0:0a673c671a56 2335 while((hsdadc->Instance->ISR & SDADC_ISR_INITRDY) == (uint32_t)RESET)
ebrus 0:0a673c671a56 2336 {
ebrus 0:0a673c671a56 2337 if((HAL_GetTick()-tickstart) > SDADC_TIMEOUT)
ebrus 0:0a673c671a56 2338 {
ebrus 0:0a673c671a56 2339 return HAL_TIMEOUT;
ebrus 0:0a673c671a56 2340 }
ebrus 0:0a673c671a56 2341 }
ebrus 0:0a673c671a56 2342
ebrus 0:0a673c671a56 2343 /* Return HAL status */
ebrus 0:0a673c671a56 2344 return HAL_OK;
ebrus 0:0a673c671a56 2345 }
ebrus 0:0a673c671a56 2346
ebrus 0:0a673c671a56 2347 /**
ebrus 0:0a673c671a56 2348 * @brief This function allows to exit from init mode for SDADC instance.
ebrus 0:0a673c671a56 2349 * @param hsdadc : SDADC handle.
ebrus 0:0a673c671a56 2350 * @retval None.
ebrus 0:0a673c671a56 2351 */
ebrus 0:0a673c671a56 2352 static void SDADC_ExitInitMode(SDADC_HandleTypeDef* hsdadc)
ebrus 0:0a673c671a56 2353 {
ebrus 0:0a673c671a56 2354 /* Reset INIT bit in SDADC_CR1 register */
ebrus 0:0a673c671a56 2355 hsdadc->Instance->CR1 &= ~(SDADC_CR1_INIT);
ebrus 0:0a673c671a56 2356 }
ebrus 0:0a673c671a56 2357
ebrus 0:0a673c671a56 2358 /**
ebrus 0:0a673c671a56 2359 * @brief This function allows to get the number of injected channels.
ebrus 0:0a673c671a56 2360 * @param Channels : bitfield of injected channels.
ebrus 0:0a673c671a56 2361 * @retval Number of injected channels.
ebrus 0:0a673c671a56 2362 */
ebrus 0:0a673c671a56 2363 static uint32_t SDADC_GetInjChannelsNbr(uint32_t Channels)
ebrus 0:0a673c671a56 2364 {
ebrus 0:0a673c671a56 2365 uint32_t nbChannels = 0;
ebrus 0:0a673c671a56 2366 uint32_t tmp,i;
ebrus 0:0a673c671a56 2367
ebrus 0:0a673c671a56 2368 /* Get the number of channels from bitfield */
ebrus 0:0a673c671a56 2369 tmp = (uint32_t) (Channels & SDADC_LSB_MASK);
ebrus 0:0a673c671a56 2370 for(i = 0 ; i < 9 ; i++)
ebrus 0:0a673c671a56 2371 {
ebrus 0:0a673c671a56 2372 if(tmp & 1)
ebrus 0:0a673c671a56 2373 {
ebrus 0:0a673c671a56 2374 nbChannels++;
ebrus 0:0a673c671a56 2375 }
ebrus 0:0a673c671a56 2376 tmp = (uint32_t) (tmp >> 1);
ebrus 0:0a673c671a56 2377 }
ebrus 0:0a673c671a56 2378 return nbChannels;
ebrus 0:0a673c671a56 2379 }
ebrus 0:0a673c671a56 2380
ebrus 0:0a673c671a56 2381 /**
ebrus 0:0a673c671a56 2382 * @brief This function allows to really start regular conversion.
ebrus 0:0a673c671a56 2383 * @param hsdadc : SDADC handle.
ebrus 0:0a673c671a56 2384 * @retval HAL status.
ebrus 0:0a673c671a56 2385 */
ebrus 0:0a673c671a56 2386 static HAL_StatusTypeDef SDADC_RegConvStart(SDADC_HandleTypeDef* hsdadc)
ebrus 0:0a673c671a56 2387 {
ebrus 0:0a673c671a56 2388 HAL_StatusTypeDef status = HAL_OK;
ebrus 0:0a673c671a56 2389
ebrus 0:0a673c671a56 2390 /* Check regular trigger */
ebrus 0:0a673c671a56 2391 if(hsdadc->RegularTrigger == SDADC_SOFTWARE_TRIGGER)
ebrus 0:0a673c671a56 2392 {
ebrus 0:0a673c671a56 2393 /* Set RSWSTART bit in SDADC_CR2 register */
ebrus 0:0a673c671a56 2394 hsdadc->Instance->CR2 |= SDADC_CR2_RSWSTART;
ebrus 0:0a673c671a56 2395 }
ebrus 0:0a673c671a56 2396 else /* synchronuous trigger */
ebrus 0:0a673c671a56 2397 {
ebrus 0:0a673c671a56 2398 /* Enter init mode */
ebrus 0:0a673c671a56 2399 if(SDADC_EnterInitMode(hsdadc) != HAL_OK)
ebrus 0:0a673c671a56 2400 {
ebrus 0:0a673c671a56 2401 /* Set SDADC in error state */
ebrus 0:0a673c671a56 2402 hsdadc->State = HAL_SDADC_STATE_ERROR;
ebrus 0:0a673c671a56 2403 status = HAL_TIMEOUT;
ebrus 0:0a673c671a56 2404 }
ebrus 0:0a673c671a56 2405 else
ebrus 0:0a673c671a56 2406 {
ebrus 0:0a673c671a56 2407 /* Set RSYNC bit in SDADC_CR1 register */
ebrus 0:0a673c671a56 2408 hsdadc->Instance->CR1 |= SDADC_CR1_RSYNC;
ebrus 0:0a673c671a56 2409
ebrus 0:0a673c671a56 2410 /* Exit init mode */
ebrus 0:0a673c671a56 2411 SDADC_ExitInitMode(hsdadc);
ebrus 0:0a673c671a56 2412 }
ebrus 0:0a673c671a56 2413 }
ebrus 0:0a673c671a56 2414 /* Update SDADC state only if status is OK */
ebrus 0:0a673c671a56 2415 if(status == HAL_OK)
ebrus 0:0a673c671a56 2416 {
ebrus 0:0a673c671a56 2417 hsdadc->State = (hsdadc->State == HAL_SDADC_STATE_READY) ? \
ebrus 0:0a673c671a56 2418 HAL_SDADC_STATE_REG : HAL_SDADC_STATE_REG_INJ;
ebrus 0:0a673c671a56 2419 }
ebrus 0:0a673c671a56 2420 /* Return function status */
ebrus 0:0a673c671a56 2421 return status;
ebrus 0:0a673c671a56 2422 }
ebrus 0:0a673c671a56 2423
ebrus 0:0a673c671a56 2424 /**
ebrus 0:0a673c671a56 2425 * @brief This function allows to really stop regular conversion.
ebrus 0:0a673c671a56 2426 * @param hsdadc : SDADC handle.
ebrus 0:0a673c671a56 2427 * @retval HAL status.
ebrus 0:0a673c671a56 2428 */
ebrus 0:0a673c671a56 2429 static HAL_StatusTypeDef SDADC_RegConvStop(SDADC_HandleTypeDef* hsdadc)
ebrus 0:0a673c671a56 2430 {
ebrus 0:0a673c671a56 2431 uint32_t tickstart;
ebrus 0:0a673c671a56 2432
ebrus 0:0a673c671a56 2433 /* Check continuous mode */
ebrus 0:0a673c671a56 2434 if(hsdadc->RegularContMode == SDADC_CONTINUOUS_CONV_ON)
ebrus 0:0a673c671a56 2435 {
ebrus 0:0a673c671a56 2436 /* Clear REOCF by reading SDADC_RDATAR register */
ebrus 0:0a673c671a56 2437 hsdadc->Instance->RDATAR;
ebrus 0:0a673c671a56 2438
ebrus 0:0a673c671a56 2439 /* Clear RCONT bit in SDADC_CR2 register */
ebrus 0:0a673c671a56 2440 hsdadc->Instance->CR2 &= ~(SDADC_CR2_RCONT);
ebrus 0:0a673c671a56 2441 }
ebrus 0:0a673c671a56 2442 /* Wait for the end of regular conversion */
ebrus 0:0a673c671a56 2443 tickstart = HAL_GetTick();
ebrus 0:0a673c671a56 2444 while((hsdadc->Instance->ISR & SDADC_ISR_RCIP) != 0)
ebrus 0:0a673c671a56 2445 {
ebrus 0:0a673c671a56 2446 if((HAL_GetTick()-tickstart) > SDADC_TIMEOUT)
ebrus 0:0a673c671a56 2447 {
ebrus 0:0a673c671a56 2448 /* Set SDADC in error state and return timeout status */
ebrus 0:0a673c671a56 2449 hsdadc->State = HAL_SDADC_STATE_ERROR;
ebrus 0:0a673c671a56 2450 return HAL_TIMEOUT;
ebrus 0:0a673c671a56 2451 }
ebrus 0:0a673c671a56 2452 }
ebrus 0:0a673c671a56 2453 /* Check if trigger is synchronuous */
ebrus 0:0a673c671a56 2454 if(hsdadc->RegularTrigger == SDADC_SYNCHRONOUS_TRIGGER)
ebrus 0:0a673c671a56 2455 {
ebrus 0:0a673c671a56 2456 /* Enter init mode */
ebrus 0:0a673c671a56 2457 if(SDADC_EnterInitMode(hsdadc) != HAL_OK)
ebrus 0:0a673c671a56 2458 {
ebrus 0:0a673c671a56 2459 /* Set SDADC in error state and return timeout status */
ebrus 0:0a673c671a56 2460 hsdadc->State = HAL_SDADC_STATE_ERROR;
ebrus 0:0a673c671a56 2461 return HAL_TIMEOUT;
ebrus 0:0a673c671a56 2462 }
ebrus 0:0a673c671a56 2463 else
ebrus 0:0a673c671a56 2464 {
ebrus 0:0a673c671a56 2465 /* Clear RSYNC bit in SDADC_CR1 register */
ebrus 0:0a673c671a56 2466 hsdadc->Instance->CR1 &= ~(SDADC_CR1_RSYNC);
ebrus 0:0a673c671a56 2467
ebrus 0:0a673c671a56 2468 /* Exit init mode */
ebrus 0:0a673c671a56 2469 SDADC_ExitInitMode(hsdadc);
ebrus 0:0a673c671a56 2470 }
ebrus 0:0a673c671a56 2471 }
ebrus 0:0a673c671a56 2472 /* Check if continuous mode */
ebrus 0:0a673c671a56 2473 if(hsdadc->RegularContMode == SDADC_CONTINUOUS_CONV_ON)
ebrus 0:0a673c671a56 2474 {
ebrus 0:0a673c671a56 2475 /* Restore RCONT bit in SDADC_CR2 register */
ebrus 0:0a673c671a56 2476 hsdadc->Instance->CR2 |= SDADC_CR2_RCONT;
ebrus 0:0a673c671a56 2477 }
ebrus 0:0a673c671a56 2478 /* Clear REOCF by reading SDADC_RDATAR register */
ebrus 0:0a673c671a56 2479 hsdadc->Instance->RDATAR;
ebrus 0:0a673c671a56 2480
ebrus 0:0a673c671a56 2481 /* Set CLRROVRF bit in SDADC_CLRISR register */
ebrus 0:0a673c671a56 2482 hsdadc->Instance->CLRISR |= SDADC_ISR_CLRROVRF;
ebrus 0:0a673c671a56 2483
ebrus 0:0a673c671a56 2484 /* Update SDADC state */
ebrus 0:0a673c671a56 2485 hsdadc->State = (hsdadc->State == HAL_SDADC_STATE_REG) ? \
ebrus 0:0a673c671a56 2486 HAL_SDADC_STATE_READY : HAL_SDADC_STATE_INJ;
ebrus 0:0a673c671a56 2487
ebrus 0:0a673c671a56 2488 /* Return function status */
ebrus 0:0a673c671a56 2489 return HAL_OK;
ebrus 0:0a673c671a56 2490 }
ebrus 0:0a673c671a56 2491
ebrus 0:0a673c671a56 2492 /**
ebrus 0:0a673c671a56 2493 * @brief This function allows to really start injected conversion.
ebrus 0:0a673c671a56 2494 * @param hsdadc : SDADC handle.
ebrus 0:0a673c671a56 2495 * @retval HAL status.
ebrus 0:0a673c671a56 2496 */
ebrus 0:0a673c671a56 2497 static HAL_StatusTypeDef SDADC_InjConvStart(SDADC_HandleTypeDef* hsdadc)
ebrus 0:0a673c671a56 2498 {
ebrus 0:0a673c671a56 2499 HAL_StatusTypeDef status = HAL_OK;
ebrus 0:0a673c671a56 2500
ebrus 0:0a673c671a56 2501 /* Initialize number of injected conversions remaining */
ebrus 0:0a673c671a56 2502 hsdadc->InjConvRemaining = hsdadc->InjectedChannelsNbr;
ebrus 0:0a673c671a56 2503
ebrus 0:0a673c671a56 2504 /* Check injected trigger */
ebrus 0:0a673c671a56 2505 if(hsdadc->InjectedTrigger == SDADC_SOFTWARE_TRIGGER)
ebrus 0:0a673c671a56 2506 {
ebrus 0:0a673c671a56 2507 /* Set JSWSTART bit in SDADC_CR2 register */
ebrus 0:0a673c671a56 2508 hsdadc->Instance->CR2 |= SDADC_CR2_JSWSTART;
ebrus 0:0a673c671a56 2509 }
ebrus 0:0a673c671a56 2510 else /* external or synchronuous trigger */
ebrus 0:0a673c671a56 2511 {
ebrus 0:0a673c671a56 2512 /* Enter init mode */
ebrus 0:0a673c671a56 2513 if(SDADC_EnterInitMode(hsdadc) != HAL_OK)
ebrus 0:0a673c671a56 2514 {
ebrus 0:0a673c671a56 2515 /* Set SDADC in error state */
ebrus 0:0a673c671a56 2516 hsdadc->State = HAL_SDADC_STATE_ERROR;
ebrus 0:0a673c671a56 2517 status = HAL_TIMEOUT;
ebrus 0:0a673c671a56 2518 }
ebrus 0:0a673c671a56 2519 else
ebrus 0:0a673c671a56 2520 {
ebrus 0:0a673c671a56 2521 if(hsdadc->InjectedTrigger == SDADC_SYNCHRONOUS_TRIGGER)
ebrus 0:0a673c671a56 2522 {
ebrus 0:0a673c671a56 2523 /* Set JSYNC bit in SDADC_CR1 register */
ebrus 0:0a673c671a56 2524 hsdadc->Instance->CR1 |= SDADC_CR1_JSYNC;
ebrus 0:0a673c671a56 2525 }
ebrus 0:0a673c671a56 2526 else /* external trigger */
ebrus 0:0a673c671a56 2527 {
ebrus 0:0a673c671a56 2528 /* Set JEXTEN[1:0] bits in SDADC_CR2 register */
ebrus 0:0a673c671a56 2529 hsdadc->Instance->CR2 |= hsdadc->ExtTriggerEdge;
ebrus 0:0a673c671a56 2530 }
ebrus 0:0a673c671a56 2531 /* Exit init mode */
ebrus 0:0a673c671a56 2532 SDADC_ExitInitMode(hsdadc);
ebrus 0:0a673c671a56 2533 }
ebrus 0:0a673c671a56 2534 }
ebrus 0:0a673c671a56 2535 /* Update SDADC state only if status is OK */
ebrus 0:0a673c671a56 2536 if(status == HAL_OK)
ebrus 0:0a673c671a56 2537 {
ebrus 0:0a673c671a56 2538 hsdadc->State = (hsdadc->State == HAL_SDADC_STATE_READY) ? \
ebrus 0:0a673c671a56 2539 HAL_SDADC_STATE_INJ : HAL_SDADC_STATE_REG_INJ;
ebrus 0:0a673c671a56 2540 }
ebrus 0:0a673c671a56 2541 /* Return function status */
ebrus 0:0a673c671a56 2542 return status;
ebrus 0:0a673c671a56 2543 }
ebrus 0:0a673c671a56 2544
ebrus 0:0a673c671a56 2545 /**
ebrus 0:0a673c671a56 2546 * @brief This function allows to really stop injected conversion.
ebrus 0:0a673c671a56 2547 * @param hsdadc : SDADC handle.
ebrus 0:0a673c671a56 2548 * @retval HAL status.
ebrus 0:0a673c671a56 2549 */
ebrus 0:0a673c671a56 2550 static HAL_StatusTypeDef SDADC_InjConvStop(SDADC_HandleTypeDef* hsdadc)
ebrus 0:0a673c671a56 2551 {
ebrus 0:0a673c671a56 2552 uint32_t tickstart;
ebrus 0:0a673c671a56 2553
ebrus 0:0a673c671a56 2554 /* Check continuous mode */
ebrus 0:0a673c671a56 2555 if(hsdadc->InjectedContMode == SDADC_CONTINUOUS_CONV_ON)
ebrus 0:0a673c671a56 2556 {
ebrus 0:0a673c671a56 2557 /* Clear JEOCF by reading SDADC_JDATAR register */
ebrus 0:0a673c671a56 2558 hsdadc->Instance->JDATAR;
ebrus 0:0a673c671a56 2559
ebrus 0:0a673c671a56 2560 /* Clear JCONT bit in SDADC_CR2 register */
ebrus 0:0a673c671a56 2561 hsdadc->Instance->CR2 &= ~(SDADC_CR2_JCONT);
ebrus 0:0a673c671a56 2562 }
ebrus 0:0a673c671a56 2563 /* Wait for the end of injected conversion */
ebrus 0:0a673c671a56 2564 tickstart = HAL_GetTick();
ebrus 0:0a673c671a56 2565 while((hsdadc->Instance->ISR & SDADC_ISR_JCIP) != 0)
ebrus 0:0a673c671a56 2566 {
ebrus 0:0a673c671a56 2567 if((HAL_GetTick()-tickstart) > SDADC_TIMEOUT)
ebrus 0:0a673c671a56 2568 {
ebrus 0:0a673c671a56 2569 /* Set SDADC in error state and return timeout status */
ebrus 0:0a673c671a56 2570 hsdadc->State = HAL_SDADC_STATE_ERROR;
ebrus 0:0a673c671a56 2571 return HAL_TIMEOUT;
ebrus 0:0a673c671a56 2572 }
ebrus 0:0a673c671a56 2573 }
ebrus 0:0a673c671a56 2574 /* Check if trigger is not software */
ebrus 0:0a673c671a56 2575 if(hsdadc->InjectedTrigger != SDADC_SOFTWARE_TRIGGER)
ebrus 0:0a673c671a56 2576 {
ebrus 0:0a673c671a56 2577 /* Enter init mode */
ebrus 0:0a673c671a56 2578 if(SDADC_EnterInitMode(hsdadc) != HAL_OK)
ebrus 0:0a673c671a56 2579 {
ebrus 0:0a673c671a56 2580 /* Set SDADC in error state and return timeout status */
ebrus 0:0a673c671a56 2581 hsdadc->State = HAL_SDADC_STATE_ERROR;
ebrus 0:0a673c671a56 2582 return HAL_TIMEOUT;
ebrus 0:0a673c671a56 2583 }
ebrus 0:0a673c671a56 2584 else
ebrus 0:0a673c671a56 2585 {
ebrus 0:0a673c671a56 2586 /* Check if trigger is synchronuous */
ebrus 0:0a673c671a56 2587 if(hsdadc->InjectedTrigger == SDADC_SYNCHRONOUS_TRIGGER)
ebrus 0:0a673c671a56 2588 {
ebrus 0:0a673c671a56 2589 /* Clear JSYNC bit in SDADC_CR1 register */
ebrus 0:0a673c671a56 2590 hsdadc->Instance->CR1 &= ~(SDADC_CR1_JSYNC);
ebrus 0:0a673c671a56 2591 }
ebrus 0:0a673c671a56 2592 else /* external trigger */
ebrus 0:0a673c671a56 2593 {
ebrus 0:0a673c671a56 2594 /* Clear JEXTEN[1:0] bits in SDADC_CR2 register */
ebrus 0:0a673c671a56 2595 hsdadc->Instance->CR2 &= ~(SDADC_CR2_JEXTEN);
ebrus 0:0a673c671a56 2596 }
ebrus 0:0a673c671a56 2597 /* Exit init mode */
ebrus 0:0a673c671a56 2598 SDADC_ExitInitMode(hsdadc);
ebrus 0:0a673c671a56 2599 }
ebrus 0:0a673c671a56 2600 }
ebrus 0:0a673c671a56 2601 /* Check if continuous mode */
ebrus 0:0a673c671a56 2602 if(hsdadc->InjectedContMode == SDADC_CONTINUOUS_CONV_ON)
ebrus 0:0a673c671a56 2603 {
ebrus 0:0a673c671a56 2604 /* Restore JCONT bit in SDADC_CR2 register */
ebrus 0:0a673c671a56 2605 hsdadc->Instance->CR2 |= SDADC_CR2_JCONT;
ebrus 0:0a673c671a56 2606 }
ebrus 0:0a673c671a56 2607 /* Clear JEOCF by reading SDADC_JDATAR register */
ebrus 0:0a673c671a56 2608 hsdadc->Instance->JDATAR;
ebrus 0:0a673c671a56 2609
ebrus 0:0a673c671a56 2610 /* Set CLRJOVRF bit in SDADC_CLRISR register */
ebrus 0:0a673c671a56 2611 hsdadc->Instance->CLRISR |= SDADC_ISR_CLRJOVRF;
ebrus 0:0a673c671a56 2612
ebrus 0:0a673c671a56 2613 /* Update SDADC state */
ebrus 0:0a673c671a56 2614 hsdadc->State = (hsdadc->State == HAL_SDADC_STATE_INJ) ? \
ebrus 0:0a673c671a56 2615 HAL_SDADC_STATE_READY : HAL_SDADC_STATE_REG;
ebrus 0:0a673c671a56 2616
ebrus 0:0a673c671a56 2617 /* Return function status */
ebrus 0:0a673c671a56 2618 return HAL_OK;
ebrus 0:0a673c671a56 2619 }
ebrus 0:0a673c671a56 2620
ebrus 0:0a673c671a56 2621 /**
ebrus 0:0a673c671a56 2622 * @}
ebrus 0:0a673c671a56 2623 */
ebrus 0:0a673c671a56 2624
ebrus 0:0a673c671a56 2625 #endif /* defined(STM32F373xC) || defined(STM32F378xx) */
ebrus 0:0a673c671a56 2626 #endif /* HAL_SDADC_MODULE_ENABLED */
ebrus 0:0a673c671a56 2627 /**
ebrus 0:0a673c671a56 2628 * @}
ebrus 0:0a673c671a56 2629 */
ebrus 0:0a673c671a56 2630
ebrus 0:0a673c671a56 2631 /**
ebrus 0:0a673c671a56 2632 * @}
ebrus 0:0a673c671a56 2633 */
ebrus 0:0a673c671a56 2634
ebrus 0:0a673c671a56 2635 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/