Emil Johnsen / mbed-src-STM32F030K6

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Fork of mbed-src by Ermanno Brusadin

targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_fmc.c@0:0a673c671a56, 2016-07-27 (annotated)

Committer:
ebrus
Date:
Wed Jul 27 18:35:32 2016 +0000
Revision:
0:0a673c671a56
4

Who changed what in which revision?

UserRevisionLine numberNew contents of line
ebrus 0:0a673c671a56 1 /**
ebrus 0:0a673c671a56 2 ******************************************************************************
ebrus 0:0a673c671a56 3 * @file stm32f4xx_ll_fmc.c
ebrus 0:0a673c671a56 4 * @author MCD Application Team
ebrus 0:0a673c671a56 5 * @version V1.1.0RC2
ebrus 0:0a673c671a56 6 * @date 14-May-2014
ebrus 0:0a673c671a56 7 * @brief FMC Low Layer HAL module driver.
ebrus 0:0a673c671a56 8 *
ebrus 0:0a673c671a56 9 * This file provides firmware functions to manage the following
ebrus 0:0a673c671a56 10 * functionalities of the Flexible Memory Controller (FMC) peripheral memories:
ebrus 0:0a673c671a56 11 * + Initialization/de-initialization functions
ebrus 0:0a673c671a56 12 * + Peripheral Control functions
ebrus 0:0a673c671a56 13 * + Peripheral State functions
ebrus 0:0a673c671a56 14 *
ebrus 0:0a673c671a56 15 @verbatim
ebrus 0:0a673c671a56 16 ==============================================================================
ebrus 0:0a673c671a56 17 ##### FMC peripheral features #####
ebrus 0:0a673c671a56 18 ==============================================================================
ebrus 0:0a673c671a56 19 [..] The Flexible memory controller (FMC) includes three memory controllers:
ebrus 0:0a673c671a56 20 (+) The NOR/PSRAM memory controller
ebrus 0:0a673c671a56 21 (+) The NAND/PC Card memory controller
ebrus 0:0a673c671a56 22 (+) The Synchronous DRAM (SDRAM) controller
ebrus 0:0a673c671a56 23
ebrus 0:0a673c671a56 24 [..] The FMC functional block makes the interface with synchronous and asynchronous static
ebrus 0:0a673c671a56 25 memories, SDRAM memories, and 16-bit PC memory cards. Its main purposes are:
ebrus 0:0a673c671a56 26 (+) to translate AHB transactions into the appropriate external device protocol
ebrus 0:0a673c671a56 27 (+) to meet the access time requirements of the external memory devices
ebrus 0:0a673c671a56 28
ebrus 0:0a673c671a56 29 [..] All external memories share the addresses, data and control signals with the controller.
ebrus 0:0a673c671a56 30 Each external device is accessed by means of a unique Chip Select. The FMC performs
ebrus 0:0a673c671a56 31 only one access at a time to an external device.
ebrus 0:0a673c671a56 32 The main features of the FMC controller are the following:
ebrus 0:0a673c671a56 33 (+) Interface with static-memory mapped devices including:
ebrus 0:0a673c671a56 34 (++) Static random access memory (SRAM)
ebrus 0:0a673c671a56 35 (++) Read-only memory (ROM)
ebrus 0:0a673c671a56 36 (++) NOR Flash memory/OneNAND Flash memory
ebrus 0:0a673c671a56 37 (++) PSRAM (4 memory banks)
ebrus 0:0a673c671a56 38 (++) 16-bit PC Card compatible devices
ebrus 0:0a673c671a56 39 (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
ebrus 0:0a673c671a56 40 data
ebrus 0:0a673c671a56 41 (+) Interface with synchronous DRAM (SDRAM) memories
ebrus 0:0a673c671a56 42 (+) Independent Chip Select control for each memory bank
ebrus 0:0a673c671a56 43 (+) Independent configuration for each memory bank
ebrus 0:0a673c671a56 44
ebrus 0:0a673c671a56 45 @endverbatim
ebrus 0:0a673c671a56 46 ******************************************************************************
ebrus 0:0a673c671a56 47 * @attention
ebrus 0:0a673c671a56 48 *
ebrus 0:0a673c671a56 49 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
ebrus 0:0a673c671a56 50 *
ebrus 0:0a673c671a56 51 * Redistribution and use in source and binary forms, with or without modification,
ebrus 0:0a673c671a56 52 * are permitted provided that the following conditions are met:
ebrus 0:0a673c671a56 53 * 1. Redistributions of source code must retain the above copyright notice,
ebrus 0:0a673c671a56 54 * this list of conditions and the following disclaimer.
ebrus 0:0a673c671a56 55 * 2. Redistributions in binary form must reproduce the above copyright notice,
ebrus 0:0a673c671a56 56 * this list of conditions and the following disclaimer in the documentation
ebrus 0:0a673c671a56 57 * and/or other materials provided with the distribution.
ebrus 0:0a673c671a56 58 * 3. Neither the name of STMicroelectronics nor the names of its contributors
ebrus 0:0a673c671a56 59 * may be used to endorse or promote products derived from this software
ebrus 0:0a673c671a56 60 * without specific prior written permission.
ebrus 0:0a673c671a56 61 *
ebrus 0:0a673c671a56 62 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
ebrus 0:0a673c671a56 63 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
ebrus 0:0a673c671a56 64 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
ebrus 0:0a673c671a56 65 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
ebrus 0:0a673c671a56 66 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
ebrus 0:0a673c671a56 67 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
ebrus 0:0a673c671a56 68 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
ebrus 0:0a673c671a56 69 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
ebrus 0:0a673c671a56 70 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
ebrus 0:0a673c671a56 71 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
ebrus 0:0a673c671a56 72 *
ebrus 0:0a673c671a56 73 ******************************************************************************
ebrus 0:0a673c671a56 74 */
ebrus 0:0a673c671a56 75
ebrus 0:0a673c671a56 76 /* Includes ------------------------------------------------------------------*/
ebrus 0:0a673c671a56 77 #include "stm32f4xx_hal.h"
ebrus 0:0a673c671a56 78
ebrus 0:0a673c671a56 79 /** @addtogroup STM32F4xx_HAL_Driver
ebrus 0:0a673c671a56 80 * @{
ebrus 0:0a673c671a56 81 */
ebrus 0:0a673c671a56 82
ebrus 0:0a673c671a56 83 /** @defgroup FMC
ebrus 0:0a673c671a56 84 * @brief FMC driver modules
ebrus 0:0a673c671a56 85 * @{
ebrus 0:0a673c671a56 86 */
ebrus 0:0a673c671a56 87
ebrus 0:0a673c671a56 88 #if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) || defined(HAL_SDRAM_MODULE_ENABLED)
ebrus 0:0a673c671a56 89
ebrus 0:0a673c671a56 90 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
ebrus 0:0a673c671a56 91
ebrus 0:0a673c671a56 92 /* Private typedef -----------------------------------------------------------*/
ebrus 0:0a673c671a56 93 /* Private define ------------------------------------------------------------*/
ebrus 0:0a673c671a56 94 /* Private macro -------------------------------------------------------------*/
ebrus 0:0a673c671a56 95 /* Private variables ---------------------------------------------------------*/
ebrus 0:0a673c671a56 96 /* Private function prototypes -----------------------------------------------*/
ebrus 0:0a673c671a56 97 /* Private functions ---------------------------------------------------------*/
ebrus 0:0a673c671a56 98
ebrus 0:0a673c671a56 99 /** @defgroup FMC_Private_Functions
ebrus 0:0a673c671a56 100 * @{
ebrus 0:0a673c671a56 101 */
ebrus 0:0a673c671a56 102
ebrus 0:0a673c671a56 103 /** @defgroup FMC_NORSRAM Controller functions
ebrus 0:0a673c671a56 104 * @brief NORSRAM Controller functions
ebrus 0:0a673c671a56 105 *
ebrus 0:0a673c671a56 106 @verbatim
ebrus 0:0a673c671a56 107 ==============================================================================
ebrus 0:0a673c671a56 108 ##### How to use NORSRAM device driver #####
ebrus 0:0a673c671a56 109 ==============================================================================
ebrus 0:0a673c671a56 110
ebrus 0:0a673c671a56 111 [..]
ebrus 0:0a673c671a56 112 This driver contains a set of APIs to interface with the FMC NORSRAM banks in order
ebrus 0:0a673c671a56 113 to run the NORSRAM external devices.
ebrus 0:0a673c671a56 114
ebrus 0:0a673c671a56 115 (+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit()
ebrus 0:0a673c671a56 116 (+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init()
ebrus 0:0a673c671a56 117 (+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init()
ebrus 0:0a673c671a56 118 (+) FMC NORSRAM bank extended timing configuration using the function
ebrus 0:0a673c671a56 119 FMC_NORSRAM_Extended_Timing_Init()
ebrus 0:0a673c671a56 120 (+) FMC NORSRAM bank enable/disable write operation using the functions
ebrus 0:0a673c671a56 121 FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable()
ebrus 0:0a673c671a56 122
ebrus 0:0a673c671a56 123
ebrus 0:0a673c671a56 124 @endverbatim
ebrus 0:0a673c671a56 125 * @{
ebrus 0:0a673c671a56 126 */
ebrus 0:0a673c671a56 127
ebrus 0:0a673c671a56 128 /** @defgroup HAL_FMC_NORSRAM_Group1 Initialization/de-initialization functions
ebrus 0:0a673c671a56 129 * @brief Initialization and Configuration functions
ebrus 0:0a673c671a56 130 *
ebrus 0:0a673c671a56 131 @verbatim
ebrus 0:0a673c671a56 132 ==============================================================================
ebrus 0:0a673c671a56 133 ##### Initialization and de_initialization functions #####
ebrus 0:0a673c671a56 134 ==============================================================================
ebrus 0:0a673c671a56 135 [..]
ebrus 0:0a673c671a56 136 This section provides functions allowing to:
ebrus 0:0a673c671a56 137 (+) Initialize and configure the FMC NORSRAM interface
ebrus 0:0a673c671a56 138 (+) De-initialize the FMC NORSRAM interface
ebrus 0:0a673c671a56 139 (+) Configure the FMC clock and associated GPIOs
ebrus 0:0a673c671a56 140
ebrus 0:0a673c671a56 141 @endverbatim
ebrus 0:0a673c671a56 142 * @{
ebrus 0:0a673c671a56 143 */
ebrus 0:0a673c671a56 144
ebrus 0:0a673c671a56 145 /**
ebrus 0:0a673c671a56 146 * @brief Initialize the FMC_NORSRAM device according to the specified
ebrus 0:0a673c671a56 147 * control parameters in the FMC_NORSRAM_InitTypeDef
ebrus 0:0a673c671a56 148 * @param Device: Pointer to NORSRAM device instance
ebrus 0:0a673c671a56 149 * @param Init: Pointer to NORSRAM Initialization structure
ebrus 0:0a673c671a56 150 * @retval HAL status
ebrus 0:0a673c671a56 151 */
ebrus 0:0a673c671a56 152 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef* Init)
ebrus 0:0a673c671a56 153 {
ebrus 0:0a673c671a56 154 uint32_t tmpr = 0;
ebrus 0:0a673c671a56 155
ebrus 0:0a673c671a56 156 /* Check the parameters */
ebrus 0:0a673c671a56 157 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
ebrus 0:0a673c671a56 158 assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank));
ebrus 0:0a673c671a56 159 assert_param(IS_FMC_MUX(Init->DataAddressMux));
ebrus 0:0a673c671a56 160 assert_param(IS_FMC_MEMORY(Init->MemoryType));
ebrus 0:0a673c671a56 161 assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
ebrus 0:0a673c671a56 162 assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode));
ebrus 0:0a673c671a56 163 assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity));
ebrus 0:0a673c671a56 164 assert_param(IS_FMC_WRAP_MODE(Init->WrapMode));
ebrus 0:0a673c671a56 165 assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
ebrus 0:0a673c671a56 166 assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation));
ebrus 0:0a673c671a56 167 assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal));
ebrus 0:0a673c671a56 168 assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode));
ebrus 0:0a673c671a56 169 assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait));
ebrus 0:0a673c671a56 170 assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst));
ebrus 0:0a673c671a56 171 assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock));
ebrus 0:0a673c671a56 172
ebrus 0:0a673c671a56 173 /* Set NORSRAM device control parameters */
ebrus 0:0a673c671a56 174 tmpr = (uint32_t)(Init->DataAddressMux |\
ebrus 0:0a673c671a56 175 Init->MemoryType |\
ebrus 0:0a673c671a56 176 Init->MemoryDataWidth |\
ebrus 0:0a673c671a56 177 Init->BurstAccessMode |\
ebrus 0:0a673c671a56 178 Init->WaitSignalPolarity |\
ebrus 0:0a673c671a56 179 Init->WrapMode |\
ebrus 0:0a673c671a56 180 Init->WaitSignalActive |\
ebrus 0:0a673c671a56 181 Init->WriteOperation |\
ebrus 0:0a673c671a56 182 Init->WaitSignal |\
ebrus 0:0a673c671a56 183 Init->ExtendedMode |\
ebrus 0:0a673c671a56 184 Init->AsynchronousWait |\
ebrus 0:0a673c671a56 185 Init->WriteBurst |\
ebrus 0:0a673c671a56 186 Init->ContinuousClock
ebrus 0:0a673c671a56 187 );
ebrus 0:0a673c671a56 188
ebrus 0:0a673c671a56 189 if(Init->MemoryType == FMC_MEMORY_TYPE_NOR)
ebrus 0:0a673c671a56 190 {
ebrus 0:0a673c671a56 191 tmpr |= (uint32_t)FMC_NORSRAM_FLASH_ACCESS_ENABLE;
ebrus 0:0a673c671a56 192 }
ebrus 0:0a673c671a56 193
ebrus 0:0a673c671a56 194 Device->BTCR[Init->NSBank] = tmpr;
ebrus 0:0a673c671a56 195
ebrus 0:0a673c671a56 196 /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */
ebrus 0:0a673c671a56 197 if((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1))
ebrus 0:0a673c671a56 198 {
ebrus 0:0a673c671a56 199 Init->BurstAccessMode = FMC_BURST_ACCESS_MODE_ENABLE;
ebrus 0:0a673c671a56 200 Device->BTCR[FMC_NORSRAM_BANK1] |= (uint32_t)(Init->BurstAccessMode |\
ebrus 0:0a673c671a56 201 Init->ContinuousClock);
ebrus 0:0a673c671a56 202 }
ebrus 0:0a673c671a56 203
ebrus 0:0a673c671a56 204 return HAL_OK;
ebrus 0:0a673c671a56 205 }
ebrus 0:0a673c671a56 206
ebrus 0:0a673c671a56 207
ebrus 0:0a673c671a56 208 /**
ebrus 0:0a673c671a56 209 * @brief DeInitialize the FMC_NORSRAM peripheral
ebrus 0:0a673c671a56 210 * @param Device: Pointer to NORSRAM device instance
ebrus 0:0a673c671a56 211 * @param ExDevice: Pointer to NORSRAM extended mode device instance
ebrus 0:0a673c671a56 212 * @param Bank: NORSRAM bank number
ebrus 0:0a673c671a56 213 * @retval HAL status
ebrus 0:0a673c671a56 214 */
ebrus 0:0a673c671a56 215 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
ebrus 0:0a673c671a56 216 {
ebrus 0:0a673c671a56 217 /* Check the parameters */
ebrus 0:0a673c671a56 218 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
ebrus 0:0a673c671a56 219 assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
ebrus 0:0a673c671a56 220 assert_param(IS_FMC_NORSRAM_BANK(Bank));
ebrus 0:0a673c671a56 221
ebrus 0:0a673c671a56 222 /* Disable the FMC_NORSRAM device */
ebrus 0:0a673c671a56 223 __FMC_NORSRAM_DISABLE(Device, Bank);
ebrus 0:0a673c671a56 224
ebrus 0:0a673c671a56 225 /* De-initialize the FMC_NORSRAM device */
ebrus 0:0a673c671a56 226 /* FMC_NORSRAM_BANK1 */
ebrus 0:0a673c671a56 227 if(Bank == FMC_NORSRAM_BANK1)
ebrus 0:0a673c671a56 228 {
ebrus 0:0a673c671a56 229 Device->BTCR[Bank] = 0x000030DB;
ebrus 0:0a673c671a56 230 }
ebrus 0:0a673c671a56 231 /* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */
ebrus 0:0a673c671a56 232 else
ebrus 0:0a673c671a56 233 {
ebrus 0:0a673c671a56 234 Device->BTCR[Bank] = 0x000030D2;
ebrus 0:0a673c671a56 235 }
ebrus 0:0a673c671a56 236
ebrus 0:0a673c671a56 237 Device->BTCR[Bank + 1] = 0x0FFFFFFF;
ebrus 0:0a673c671a56 238 ExDevice->BWTR[Bank] = 0x0FFFFFFF;
ebrus 0:0a673c671a56 239
ebrus 0:0a673c671a56 240 return HAL_OK;
ebrus 0:0a673c671a56 241 }
ebrus 0:0a673c671a56 242
ebrus 0:0a673c671a56 243
ebrus 0:0a673c671a56 244 /**
ebrus 0:0a673c671a56 245 * @brief Initialize the FMC_NORSRAM Timing according to the specified
ebrus 0:0a673c671a56 246 * parameters in the FMC_NORSRAM_TimingTypeDef
ebrus 0:0a673c671a56 247 * @param Device: Pointer to NORSRAM device instance
ebrus 0:0a673c671a56 248 * @param Timing: Pointer to NORSRAM Timing structure
ebrus 0:0a673c671a56 249 * @param Bank: NORSRAM bank number
ebrus 0:0a673c671a56 250 * @retval HAL status
ebrus 0:0a673c671a56 251 */
ebrus 0:0a673c671a56 252 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
ebrus 0:0a673c671a56 253 {
ebrus 0:0a673c671a56 254 uint32_t tmpr = 0;
ebrus 0:0a673c671a56 255
ebrus 0:0a673c671a56 256 /* Check the parameters */
ebrus 0:0a673c671a56 257 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
ebrus 0:0a673c671a56 258 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
ebrus 0:0a673c671a56 259 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
ebrus 0:0a673c671a56 260 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
ebrus 0:0a673c671a56 261 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
ebrus 0:0a673c671a56 262 assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));
ebrus 0:0a673c671a56 263 assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));
ebrus 0:0a673c671a56 264 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
ebrus 0:0a673c671a56 265 assert_param(IS_FMC_NORSRAM_BANK(Bank));
ebrus 0:0a673c671a56 266
ebrus 0:0a673c671a56 267 /* Set FMC_NORSRAM device timing parameters */
ebrus 0:0a673c671a56 268 tmpr = (uint32_t)(Timing->AddressSetupTime |\
ebrus 0:0a673c671a56 269 ((Timing->AddressHoldTime) << 4) |\
ebrus 0:0a673c671a56 270 ((Timing->DataSetupTime) << 8) |\
ebrus 0:0a673c671a56 271 ((Timing->BusTurnAroundDuration) << 16) |\
ebrus 0:0a673c671a56 272 (((Timing->CLKDivision)-1) << 20) |\
ebrus 0:0a673c671a56 273 (((Timing->DataLatency)-2) << 24) |\
ebrus 0:0a673c671a56 274 (Timing->AccessMode)
ebrus 0:0a673c671a56 275 );
ebrus 0:0a673c671a56 276
ebrus 0:0a673c671a56 277 Device->BTCR[Bank + 1] = tmpr;
ebrus 0:0a673c671a56 278
ebrus 0:0a673c671a56 279 /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */
ebrus 0:0a673c671a56 280 if(HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN))
ebrus 0:0a673c671a56 281 {
ebrus 0:0a673c671a56 282 tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1] & ~(((uint32_t)0x0F) << 20));
ebrus 0:0a673c671a56 283 tmpr |= (uint32_t)(((Timing->CLKDivision)-1) << 20);
ebrus 0:0a673c671a56 284 Device->BTCR[FMC_NORSRAM_BANK1 + 1] = tmpr;
ebrus 0:0a673c671a56 285 }
ebrus 0:0a673c671a56 286
ebrus 0:0a673c671a56 287 return HAL_OK;
ebrus 0:0a673c671a56 288 }
ebrus 0:0a673c671a56 289
ebrus 0:0a673c671a56 290 /**
ebrus 0:0a673c671a56 291 * @brief Initialize the FMC_NORSRAM Extended mode Timing according to the specified
ebrus 0:0a673c671a56 292 * parameters in the FMC_NORSRAM_TimingTypeDef
ebrus 0:0a673c671a56 293 * @param Device: Pointer to NORSRAM device instance
ebrus 0:0a673c671a56 294 * @param Timing: Pointer to NORSRAM Timing structure
ebrus 0:0a673c671a56 295 * @param Bank: NORSRAM bank number
ebrus 0:0a673c671a56 296 * @retval HAL status
ebrus 0:0a673c671a56 297 */
ebrus 0:0a673c671a56 298 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
ebrus 0:0a673c671a56 299 {
ebrus 0:0a673c671a56 300 /* Check the parameters */
ebrus 0:0a673c671a56 301 assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode));
ebrus 0:0a673c671a56 302
ebrus 0:0a673c671a56 303 /* Set NORSRAM device timing register for write configuration, if extended mode is used */
ebrus 0:0a673c671a56 304 if(ExtendedMode == FMC_EXTENDED_MODE_ENABLE)
ebrus 0:0a673c671a56 305 {
ebrus 0:0a673c671a56 306 /* Check the parameters */
ebrus 0:0a673c671a56 307 assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device));
ebrus 0:0a673c671a56 308 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
ebrus 0:0a673c671a56 309 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
ebrus 0:0a673c671a56 310 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
ebrus 0:0a673c671a56 311 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
ebrus 0:0a673c671a56 312 assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));
ebrus 0:0a673c671a56 313 assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));
ebrus 0:0a673c671a56 314 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
ebrus 0:0a673c671a56 315 assert_param(IS_FMC_NORSRAM_BANK(Bank));
ebrus 0:0a673c671a56 316
ebrus 0:0a673c671a56 317 Device->BWTR[Bank] = (uint32_t)(Timing->AddressSetupTime |\
ebrus 0:0a673c671a56 318 ((Timing->AddressHoldTime) << 4) |\
ebrus 0:0a673c671a56 319 ((Timing->DataSetupTime) << 8) |\
ebrus 0:0a673c671a56 320 ((Timing->BusTurnAroundDuration) << 16) |\
ebrus 0:0a673c671a56 321 (((Timing->CLKDivision)-1) << 20) |\
ebrus 0:0a673c671a56 322 (((Timing->DataLatency)-2) << 24) |\
ebrus 0:0a673c671a56 323 (Timing->AccessMode));
ebrus 0:0a673c671a56 324 }
ebrus 0:0a673c671a56 325 else
ebrus 0:0a673c671a56 326 {
ebrus 0:0a673c671a56 327 Device->BWTR[Bank] = 0x0FFFFFFF;
ebrus 0:0a673c671a56 328 }
ebrus 0:0a673c671a56 329
ebrus 0:0a673c671a56 330 return HAL_OK;
ebrus 0:0a673c671a56 331 }
ebrus 0:0a673c671a56 332
ebrus 0:0a673c671a56 333
ebrus 0:0a673c671a56 334 /**
ebrus 0:0a673c671a56 335 * @}
ebrus 0:0a673c671a56 336 */
ebrus 0:0a673c671a56 337
ebrus 0:0a673c671a56 338
ebrus 0:0a673c671a56 339 /** @defgroup HAL_FMC_NORSRAM_Group3 Control functions
ebrus 0:0a673c671a56 340 * @brief management functions
ebrus 0:0a673c671a56 341 *
ebrus 0:0a673c671a56 342 @verbatim
ebrus 0:0a673c671a56 343 ==============================================================================
ebrus 0:0a673c671a56 344 ##### FMC_NORSRAM Control functions #####
ebrus 0:0a673c671a56 345 ==============================================================================
ebrus 0:0a673c671a56 346 [..]
ebrus 0:0a673c671a56 347 This subsection provides a set of functions allowing to control dynamically
ebrus 0:0a673c671a56 348 the FMC NORSRAM interface.
ebrus 0:0a673c671a56 349
ebrus 0:0a673c671a56 350 @endverbatim
ebrus 0:0a673c671a56 351 * @{
ebrus 0:0a673c671a56 352 */
ebrus 0:0a673c671a56 353
ebrus 0:0a673c671a56 354 /**
ebrus 0:0a673c671a56 355 * @brief Enables dynamically FMC_NORSRAM write operation.
ebrus 0:0a673c671a56 356 * @param Device: Pointer to NORSRAM device instance
ebrus 0:0a673c671a56 357 * @param Bank: NORSRAM bank number
ebrus 0:0a673c671a56 358 * @retval HAL status
ebrus 0:0a673c671a56 359 */
ebrus 0:0a673c671a56 360 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
ebrus 0:0a673c671a56 361 {
ebrus 0:0a673c671a56 362 /* Check the parameters */
ebrus 0:0a673c671a56 363 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
ebrus 0:0a673c671a56 364 assert_param(IS_FMC_NORSRAM_BANK(Bank));
ebrus 0:0a673c671a56 365
ebrus 0:0a673c671a56 366 /* Enable write operation */
ebrus 0:0a673c671a56 367 Device->BTCR[Bank] |= FMC_WRITE_OPERATION_ENABLE;
ebrus 0:0a673c671a56 368
ebrus 0:0a673c671a56 369 return HAL_OK;
ebrus 0:0a673c671a56 370 }
ebrus 0:0a673c671a56 371
ebrus 0:0a673c671a56 372 /**
ebrus 0:0a673c671a56 373 * @brief Disables dynamically FMC_NORSRAM write operation.
ebrus 0:0a673c671a56 374 * @param Device: Pointer to NORSRAM device instance
ebrus 0:0a673c671a56 375 * @param Bank: NORSRAM bank number
ebrus 0:0a673c671a56 376 * @retval HAL status
ebrus 0:0a673c671a56 377 */
ebrus 0:0a673c671a56 378 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
ebrus 0:0a673c671a56 379 {
ebrus 0:0a673c671a56 380 /* Check the parameters */
ebrus 0:0a673c671a56 381 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
ebrus 0:0a673c671a56 382 assert_param(IS_FMC_NORSRAM_BANK(Bank));
ebrus 0:0a673c671a56 383
ebrus 0:0a673c671a56 384 /* Disable write operation */
ebrus 0:0a673c671a56 385 Device->BTCR[Bank] &= ~FMC_WRITE_OPERATION_ENABLE;
ebrus 0:0a673c671a56 386
ebrus 0:0a673c671a56 387 return HAL_OK;
ebrus 0:0a673c671a56 388 }
ebrus 0:0a673c671a56 389
ebrus 0:0a673c671a56 390 /**
ebrus 0:0a673c671a56 391 * @}
ebrus 0:0a673c671a56 392 */
ebrus 0:0a673c671a56 393
ebrus 0:0a673c671a56 394 /**
ebrus 0:0a673c671a56 395 * @}
ebrus 0:0a673c671a56 396 */
ebrus 0:0a673c671a56 397
ebrus 0:0a673c671a56 398 /** @defgroup FMC_PCCARD Controller functions
ebrus 0:0a673c671a56 399 * @brief PCCARD Controller functions
ebrus 0:0a673c671a56 400 *
ebrus 0:0a673c671a56 401 @verbatim
ebrus 0:0a673c671a56 402 ==============================================================================
ebrus 0:0a673c671a56 403 ##### How to use NAND device driver #####
ebrus 0:0a673c671a56 404 ==============================================================================
ebrus 0:0a673c671a56 405 [..]
ebrus 0:0a673c671a56 406 This driver contains a set of APIs to interface with the FMC NAND banks in order
ebrus 0:0a673c671a56 407 to run the NAND external devices.
ebrus 0:0a673c671a56 408
ebrus 0:0a673c671a56 409 (+) FMC NAND bank reset using the function FMC_NAND_DeInit()
ebrus 0:0a673c671a56 410 (+) FMC NAND bank control configuration using the function FMC_NAND_Init()
ebrus 0:0a673c671a56 411 (+) FMC NAND bank common space timing configuration using the function
ebrus 0:0a673c671a56 412 FMC_NAND_CommonSpace_Timing_Init()
ebrus 0:0a673c671a56 413 (+) FMC NAND bank attribute space timing configuration using the function
ebrus 0:0a673c671a56 414 FMC_NAND_AttributeSpace_Timing_Init()
ebrus 0:0a673c671a56 415 (+) FMC NAND bank enable/disable ECC correction feature using the functions
ebrus 0:0a673c671a56 416 FMC_NAND_ECC_Enable()/FMC_NAND_ECC_Disable()
ebrus 0:0a673c671a56 417 (+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC()
ebrus 0:0a673c671a56 418
ebrus 0:0a673c671a56 419 @endverbatim
ebrus 0:0a673c671a56 420 * @{
ebrus 0:0a673c671a56 421 */
ebrus 0:0a673c671a56 422
ebrus 0:0a673c671a56 423 /** @defgroup HAL_FMC_NAND_Group1 Initialization/de-initialization functions
ebrus 0:0a673c671a56 424 * @brief Initialization and Configuration functions
ebrus 0:0a673c671a56 425 *
ebrus 0:0a673c671a56 426 @verbatim
ebrus 0:0a673c671a56 427 ==============================================================================
ebrus 0:0a673c671a56 428 ##### Initialization and de_initialization functions #####
ebrus 0:0a673c671a56 429 ==============================================================================
ebrus 0:0a673c671a56 430 [..]
ebrus 0:0a673c671a56 431 This section provides functions allowing to:
ebrus 0:0a673c671a56 432 (+) Initialize and configure the FMC NAND interface
ebrus 0:0a673c671a56 433 (+) De-initialize the FMC NAND interface
ebrus 0:0a673c671a56 434 (+) Configure the FMC clock and associated GPIOs
ebrus 0:0a673c671a56 435
ebrus 0:0a673c671a56 436 @endverbatim
ebrus 0:0a673c671a56 437 * @{
ebrus 0:0a673c671a56 438 */
ebrus 0:0a673c671a56 439
ebrus 0:0a673c671a56 440 /**
ebrus 0:0a673c671a56 441 * @brief Initializes the FMC_NAND device according to the specified
ebrus 0:0a673c671a56 442 * control parameters in the FMC_NAND_HandleTypeDef
ebrus 0:0a673c671a56 443 * @param Device: Pointer to NAND device instance
ebrus 0:0a673c671a56 444 * @param Init: Pointer to NAND Initialization structure
ebrus 0:0a673c671a56 445 * @retval HAL status
ebrus 0:0a673c671a56 446 */
ebrus 0:0a673c671a56 447 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init)
ebrus 0:0a673c671a56 448 {
ebrus 0:0a673c671a56 449 uint32_t tmppcr = 0;
ebrus 0:0a673c671a56 450
ebrus 0:0a673c671a56 451 /* Check the parameters */
ebrus 0:0a673c671a56 452 assert_param(IS_FMC_NAND_DEVICE(Device));
ebrus 0:0a673c671a56 453 assert_param(IS_FMC_NAND_BANK(Init->NandBank));
ebrus 0:0a673c671a56 454 assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
ebrus 0:0a673c671a56 455 assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
ebrus 0:0a673c671a56 456 assert_param(IS_FMC_ECC_STATE(Init->EccComputation));
ebrus 0:0a673c671a56 457 assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize));
ebrus 0:0a673c671a56 458 assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
ebrus 0:0a673c671a56 459 assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
ebrus 0:0a673c671a56 460
ebrus 0:0a673c671a56 461 /* Set NAND device control parameters */
ebrus 0:0a673c671a56 462 tmppcr = (uint32_t)(Init->Waitfeature |\
ebrus 0:0a673c671a56 463 FMC_PCR_MEMORY_TYPE_NAND |\
ebrus 0:0a673c671a56 464 Init->MemoryDataWidth |\
ebrus 0:0a673c671a56 465 Init->EccComputation |\
ebrus 0:0a673c671a56 466 Init->ECCPageSize |\
ebrus 0:0a673c671a56 467 ((Init->TCLRSetupTime) << 9) |\
ebrus 0:0a673c671a56 468 ((Init->TARSetupTime) << 13)
ebrus 0:0a673c671a56 469 );
ebrus 0:0a673c671a56 470
ebrus 0:0a673c671a56 471 if(Init->NandBank == FMC_NAND_BANK2)
ebrus 0:0a673c671a56 472 {
ebrus 0:0a673c671a56 473 /* NAND bank 2 registers configuration */
ebrus 0:0a673c671a56 474 Device->PCR2 = tmppcr;
ebrus 0:0a673c671a56 475 }
ebrus 0:0a673c671a56 476 else
ebrus 0:0a673c671a56 477 {
ebrus 0:0a673c671a56 478 /* NAND bank 3 registers configuration */
ebrus 0:0a673c671a56 479 Device->PCR3 = tmppcr;
ebrus 0:0a673c671a56 480 }
ebrus 0:0a673c671a56 481
ebrus 0:0a673c671a56 482 return HAL_OK;
ebrus 0:0a673c671a56 483
ebrus 0:0a673c671a56 484 }
ebrus 0:0a673c671a56 485
ebrus 0:0a673c671a56 486 /**
ebrus 0:0a673c671a56 487 * @brief Initializes the FMC_NAND Common space Timing according to the specified
ebrus 0:0a673c671a56 488 * parameters in the FMC_NAND_PCC_TimingTypeDef
ebrus 0:0a673c671a56 489 * @param Device: Pointer to NAND device instance
ebrus 0:0a673c671a56 490 * @param Timing: Pointer to NAND timing structure
ebrus 0:0a673c671a56 491 * @param Bank: NAND bank number
ebrus 0:0a673c671a56 492 * @retval HAL status
ebrus 0:0a673c671a56 493 */
ebrus 0:0a673c671a56 494 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
ebrus 0:0a673c671a56 495 {
ebrus 0:0a673c671a56 496 uint32_t tmppmem = 0;
ebrus 0:0a673c671a56 497
ebrus 0:0a673c671a56 498 /* Check the parameters */
ebrus 0:0a673c671a56 499 assert_param(IS_FMC_NAND_DEVICE(Device));
ebrus 0:0a673c671a56 500 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
ebrus 0:0a673c671a56 501 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
ebrus 0:0a673c671a56 502 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
ebrus 0:0a673c671a56 503 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
ebrus 0:0a673c671a56 504 assert_param(IS_FMC_NAND_BANK(Bank));
ebrus 0:0a673c671a56 505
ebrus 0:0a673c671a56 506 /* Set FMC_NAND device timing parameters */
ebrus 0:0a673c671a56 507 tmppmem = (uint32_t)(Timing->SetupTime |\
ebrus 0:0a673c671a56 508 ((Timing->WaitSetupTime) << 8) |\
ebrus 0:0a673c671a56 509 ((Timing->HoldSetupTime) << 16) |\
ebrus 0:0a673c671a56 510 ((Timing->HiZSetupTime) << 24)
ebrus 0:0a673c671a56 511 );
ebrus 0:0a673c671a56 512
ebrus 0:0a673c671a56 513 if(Bank == FMC_NAND_BANK2)
ebrus 0:0a673c671a56 514 {
ebrus 0:0a673c671a56 515 /* NAND bank 2 registers configuration */
ebrus 0:0a673c671a56 516 Device->PMEM2 = tmppmem;
ebrus 0:0a673c671a56 517 }
ebrus 0:0a673c671a56 518 else
ebrus 0:0a673c671a56 519 {
ebrus 0:0a673c671a56 520 /* NAND bank 3 registers configuration */
ebrus 0:0a673c671a56 521 Device->PMEM3 = tmppmem;
ebrus 0:0a673c671a56 522 }
ebrus 0:0a673c671a56 523
ebrus 0:0a673c671a56 524 return HAL_OK;
ebrus 0:0a673c671a56 525 }
ebrus 0:0a673c671a56 526
ebrus 0:0a673c671a56 527 /**
ebrus 0:0a673c671a56 528 * @brief Initializes the FMC_NAND Attribute space Timing according to the specified
ebrus 0:0a673c671a56 529 * parameters in the FMC_NAND_PCC_TimingTypeDef
ebrus 0:0a673c671a56 530 * @param Device: Pointer to NAND device instance
ebrus 0:0a673c671a56 531 * @param Timing: Pointer to NAND timing structure
ebrus 0:0a673c671a56 532 * @param Bank: NAND bank number
ebrus 0:0a673c671a56 533 * @retval HAL status
ebrus 0:0a673c671a56 534 */
ebrus 0:0a673c671a56 535 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
ebrus 0:0a673c671a56 536 {
ebrus 0:0a673c671a56 537 uint32_t tmppatt = 0;
ebrus 0:0a673c671a56 538
ebrus 0:0a673c671a56 539 /* Check the parameters */
ebrus 0:0a673c671a56 540 assert_param(IS_FMC_NAND_DEVICE(Device));
ebrus 0:0a673c671a56 541 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
ebrus 0:0a673c671a56 542 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
ebrus 0:0a673c671a56 543 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
ebrus 0:0a673c671a56 544 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
ebrus 0:0a673c671a56 545 assert_param(IS_FMC_NAND_BANK(Bank));
ebrus 0:0a673c671a56 546
ebrus 0:0a673c671a56 547 /* Set FMC_NAND device timing parameters */
ebrus 0:0a673c671a56 548 tmppatt = (uint32_t)(Timing->SetupTime |\
ebrus 0:0a673c671a56 549 ((Timing->WaitSetupTime) << 8) |\
ebrus 0:0a673c671a56 550 ((Timing->HoldSetupTime) << 16) |\
ebrus 0:0a673c671a56 551 ((Timing->HiZSetupTime) << 24)
ebrus 0:0a673c671a56 552 );
ebrus 0:0a673c671a56 553
ebrus 0:0a673c671a56 554 if(Bank == FMC_NAND_BANK2)
ebrus 0:0a673c671a56 555 {
ebrus 0:0a673c671a56 556 /* NAND bank 2 registers configuration */
ebrus 0:0a673c671a56 557 Device->PATT2 = tmppatt;
ebrus 0:0a673c671a56 558 }
ebrus 0:0a673c671a56 559 else
ebrus 0:0a673c671a56 560 {
ebrus 0:0a673c671a56 561 /* NAND bank 3 registers configuration */
ebrus 0:0a673c671a56 562 Device->PATT3 = tmppatt;
ebrus 0:0a673c671a56 563 }
ebrus 0:0a673c671a56 564
ebrus 0:0a673c671a56 565 return HAL_OK;
ebrus 0:0a673c671a56 566 }
ebrus 0:0a673c671a56 567
ebrus 0:0a673c671a56 568
ebrus 0:0a673c671a56 569 /**
ebrus 0:0a673c671a56 570 * @brief DeInitializes the FMC_NAND device
ebrus 0:0a673c671a56 571 * @param Device: Pointer to NAND device instance
ebrus 0:0a673c671a56 572 * @param Bank: NAND bank number
ebrus 0:0a673c671a56 573 * @retval HAL status
ebrus 0:0a673c671a56 574 */
ebrus 0:0a673c671a56 575 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)
ebrus 0:0a673c671a56 576 {
ebrus 0:0a673c671a56 577 /* Check the parameters */
ebrus 0:0a673c671a56 578 assert_param(IS_FMC_NAND_DEVICE(Device));
ebrus 0:0a673c671a56 579 assert_param(IS_FMC_NAND_BANK(Bank));
ebrus 0:0a673c671a56 580
ebrus 0:0a673c671a56 581 /* Disable the NAND Bank */
ebrus 0:0a673c671a56 582 __FMC_NAND_DISABLE(Device, Bank);
ebrus 0:0a673c671a56 583
ebrus 0:0a673c671a56 584 /* De-initialize the NAND Bank */
ebrus 0:0a673c671a56 585 if(Bank == FMC_NAND_BANK2)
ebrus 0:0a673c671a56 586 {
ebrus 0:0a673c671a56 587 /* Set the FMC_NAND_BANK2 registers to their reset values */
ebrus 0:0a673c671a56 588 Device->PCR2 = 0x00000018;
ebrus 0:0a673c671a56 589 Device->SR2 = 0x00000040;
ebrus 0:0a673c671a56 590 Device->PMEM2 = 0xFCFCFCFC;
ebrus 0:0a673c671a56 591 Device->PATT2 = 0xFCFCFCFC;
ebrus 0:0a673c671a56 592 }
ebrus 0:0a673c671a56 593 /* FMC_Bank3_NAND */
ebrus 0:0a673c671a56 594 else
ebrus 0:0a673c671a56 595 {
ebrus 0:0a673c671a56 596 /* Set the FMC_NAND_BANK3 registers to their reset values */
ebrus 0:0a673c671a56 597 Device->PCR3 = 0x00000018;
ebrus 0:0a673c671a56 598 Device->SR3 = 0x00000040;
ebrus 0:0a673c671a56 599 Device->PMEM3 = 0xFCFCFCFC;
ebrus 0:0a673c671a56 600 Device->PATT3 = 0xFCFCFCFC;
ebrus 0:0a673c671a56 601 }
ebrus 0:0a673c671a56 602
ebrus 0:0a673c671a56 603 return HAL_OK;
ebrus 0:0a673c671a56 604 }
ebrus 0:0a673c671a56 605
ebrus 0:0a673c671a56 606 /**
ebrus 0:0a673c671a56 607 * @}
ebrus 0:0a673c671a56 608 */
ebrus 0:0a673c671a56 609
ebrus 0:0a673c671a56 610
ebrus 0:0a673c671a56 611 /** @defgroup HAL_FMC_NAND_Group3 Control functions
ebrus 0:0a673c671a56 612 * @brief management functions
ebrus 0:0a673c671a56 613 *
ebrus 0:0a673c671a56 614 @verbatim
ebrus 0:0a673c671a56 615 ==============================================================================
ebrus 0:0a673c671a56 616 ##### FMC_NAND Control functions #####
ebrus 0:0a673c671a56 617 ==============================================================================
ebrus 0:0a673c671a56 618 [..]
ebrus 0:0a673c671a56 619 This subsection provides a set of functions allowing to control dynamically
ebrus 0:0a673c671a56 620 the FMC NAND interface.
ebrus 0:0a673c671a56 621
ebrus 0:0a673c671a56 622 @endverbatim
ebrus 0:0a673c671a56 623 * @{
ebrus 0:0a673c671a56 624 */
ebrus 0:0a673c671a56 625
ebrus 0:0a673c671a56 626
ebrus 0:0a673c671a56 627 /**
ebrus 0:0a673c671a56 628 * @brief Enables dynamically FMC_NAND ECC feature.
ebrus 0:0a673c671a56 629 * @param Device: Pointer to NAND device instance
ebrus 0:0a673c671a56 630 * @param Bank: NAND bank number
ebrus 0:0a673c671a56 631 * @retval HAL status
ebrus 0:0a673c671a56 632 */
ebrus 0:0a673c671a56 633 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)
ebrus 0:0a673c671a56 634 {
ebrus 0:0a673c671a56 635 /* Check the parameters */
ebrus 0:0a673c671a56 636 assert_param(IS_FMC_NAND_DEVICE(Device));
ebrus 0:0a673c671a56 637 assert_param(IS_FMC_NAND_BANK(Bank));
ebrus 0:0a673c671a56 638
ebrus 0:0a673c671a56 639 /* Enable ECC feature */
ebrus 0:0a673c671a56 640 if(Bank == FMC_NAND_BANK2)
ebrus 0:0a673c671a56 641 {
ebrus 0:0a673c671a56 642 Device->PCR2 |= FMC_PCR2_ECCEN;
ebrus 0:0a673c671a56 643 }
ebrus 0:0a673c671a56 644 else
ebrus 0:0a673c671a56 645 {
ebrus 0:0a673c671a56 646 Device->PCR3 |= FMC_PCR3_ECCEN;
ebrus 0:0a673c671a56 647 }
ebrus 0:0a673c671a56 648
ebrus 0:0a673c671a56 649 return HAL_OK;
ebrus 0:0a673c671a56 650 }
ebrus 0:0a673c671a56 651
ebrus 0:0a673c671a56 652
ebrus 0:0a673c671a56 653 /**
ebrus 0:0a673c671a56 654 * @brief Disables dynamically FMC_NAND ECC feature.
ebrus 0:0a673c671a56 655 * @param Device: Pointer to NAND device instance
ebrus 0:0a673c671a56 656 * @param Bank: NAND bank number
ebrus 0:0a673c671a56 657 * @retval HAL status
ebrus 0:0a673c671a56 658 */
ebrus 0:0a673c671a56 659 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)
ebrus 0:0a673c671a56 660 {
ebrus 0:0a673c671a56 661 /* Check the parameters */
ebrus 0:0a673c671a56 662 assert_param(IS_FMC_NAND_DEVICE(Device));
ebrus 0:0a673c671a56 663 assert_param(IS_FMC_NAND_BANK(Bank));
ebrus 0:0a673c671a56 664
ebrus 0:0a673c671a56 665 /* Disable ECC feature */
ebrus 0:0a673c671a56 666 if(Bank == FMC_NAND_BANK2)
ebrus 0:0a673c671a56 667 {
ebrus 0:0a673c671a56 668 Device->PCR2 &= ~FMC_PCR2_ECCEN;
ebrus 0:0a673c671a56 669 }
ebrus 0:0a673c671a56 670 else
ebrus 0:0a673c671a56 671 {
ebrus 0:0a673c671a56 672 Device->PCR3 &= ~FMC_PCR3_ECCEN;
ebrus 0:0a673c671a56 673 }
ebrus 0:0a673c671a56 674
ebrus 0:0a673c671a56 675 return HAL_OK;
ebrus 0:0a673c671a56 676 }
ebrus 0:0a673c671a56 677
ebrus 0:0a673c671a56 678 /**
ebrus 0:0a673c671a56 679 * @brief Disables dynamically FMC_NAND ECC feature.
ebrus 0:0a673c671a56 680 * @param Device: Pointer to NAND device instance
ebrus 0:0a673c671a56 681 * @param ECCval: Pointer to ECC value
ebrus 0:0a673c671a56 682 * @param Bank: NAND bank number
ebrus 0:0a673c671a56 683 * @param Timeout: Timeout wait value
ebrus 0:0a673c671a56 684 * @retval HAL status
ebrus 0:0a673c671a56 685 */
ebrus 0:0a673c671a56 686 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
ebrus 0:0a673c671a56 687 {
ebrus 0:0a673c671a56 688 uint32_t timeout = 0;
ebrus 0:0a673c671a56 689
ebrus 0:0a673c671a56 690 /* Check the parameters */
ebrus 0:0a673c671a56 691 assert_param(IS_FMC_NAND_DEVICE(Device));
ebrus 0:0a673c671a56 692 assert_param(IS_FMC_NAND_BANK(Bank));
ebrus 0:0a673c671a56 693
ebrus 0:0a673c671a56 694 timeout = HAL_GetTick() + Timeout;
ebrus 0:0a673c671a56 695
ebrus 0:0a673c671a56 696 /* Wait untill FIFO is empty */
ebrus 0:0a673c671a56 697 while(__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT))
ebrus 0:0a673c671a56 698 {
ebrus 0:0a673c671a56 699 /* Check for the Timeout */
ebrus 0:0a673c671a56 700 if(Timeout != HAL_MAX_DELAY)
ebrus 0:0a673c671a56 701 {
ebrus 0:0a673c671a56 702 if(HAL_GetTick() >= timeout)
ebrus 0:0a673c671a56 703 {
ebrus 0:0a673c671a56 704 return HAL_TIMEOUT;
ebrus 0:0a673c671a56 705 }
ebrus 0:0a673c671a56 706 }
ebrus 0:0a673c671a56 707 }
ebrus 0:0a673c671a56 708
ebrus 0:0a673c671a56 709 if(Bank == FMC_NAND_BANK2)
ebrus 0:0a673c671a56 710 {
ebrus 0:0a673c671a56 711 /* Get the ECCR2 register value */
ebrus 0:0a673c671a56 712 *ECCval = (uint32_t)Device->ECCR2;
ebrus 0:0a673c671a56 713 }
ebrus 0:0a673c671a56 714 else
ebrus 0:0a673c671a56 715 {
ebrus 0:0a673c671a56 716 /* Get the ECCR3 register value */
ebrus 0:0a673c671a56 717 *ECCval = (uint32_t)Device->ECCR3;
ebrus 0:0a673c671a56 718 }
ebrus 0:0a673c671a56 719
ebrus 0:0a673c671a56 720 return HAL_OK;
ebrus 0:0a673c671a56 721 }
ebrus 0:0a673c671a56 722
ebrus 0:0a673c671a56 723 /**
ebrus 0:0a673c671a56 724 * @}
ebrus 0:0a673c671a56 725 */
ebrus 0:0a673c671a56 726
ebrus 0:0a673c671a56 727 /**
ebrus 0:0a673c671a56 728 * @}
ebrus 0:0a673c671a56 729 */
ebrus 0:0a673c671a56 730
ebrus 0:0a673c671a56 731 /** @defgroup FMC_PCCARD Controller functions
ebrus 0:0a673c671a56 732 * @brief PCCARD Controller functions
ebrus 0:0a673c671a56 733 *
ebrus 0:0a673c671a56 734 @verbatim
ebrus 0:0a673c671a56 735 ==============================================================================
ebrus 0:0a673c671a56 736 ##### How to use PCCARD device driver #####
ebrus 0:0a673c671a56 737 ==============================================================================
ebrus 0:0a673c671a56 738 [..]
ebrus 0:0a673c671a56 739 This driver contains a set of APIs to interface with the FMC PCCARD bank in order
ebrus 0:0a673c671a56 740 to run the PCCARD/compact flash external devices.
ebrus 0:0a673c671a56 741
ebrus 0:0a673c671a56 742 (+) FMC PCCARD bank reset using the function FMC_PCCARD_DeInit()
ebrus 0:0a673c671a56 743 (+) FMC PCCARD bank control configuration using the function FMC_PCCARD_Init()
ebrus 0:0a673c671a56 744 (+) FMC PCCARD bank common space timing configuration using the function
ebrus 0:0a673c671a56 745 FMC_PCCARD_CommonSpace_Timing_Init()
ebrus 0:0a673c671a56 746 (+) FMC PCCARD bank attribute space timing configuration using the function
ebrus 0:0a673c671a56 747 FMC_PCCARD_AttributeSpace_Timing_Init()
ebrus 0:0a673c671a56 748 (+) FMC PCCARD bank IO space timing configuration using the function
ebrus 0:0a673c671a56 749 FMC_PCCARD_IOSpace_Timing_Init()
ebrus 0:0a673c671a56 750
ebrus 0:0a673c671a56 751
ebrus 0:0a673c671a56 752 @endverbatim
ebrus 0:0a673c671a56 753 * @{
ebrus 0:0a673c671a56 754 */
ebrus 0:0a673c671a56 755
ebrus 0:0a673c671a56 756 /** @defgroup HAL_FMC_PCCARD_Group1 Initialization/de-initialization functions
ebrus 0:0a673c671a56 757 * @brief Initialization and Configuration functions
ebrus 0:0a673c671a56 758 *
ebrus 0:0a673c671a56 759 @verbatim
ebrus 0:0a673c671a56 760 ==============================================================================
ebrus 0:0a673c671a56 761 ##### Initialization and de_initialization functions #####
ebrus 0:0a673c671a56 762 ==============================================================================
ebrus 0:0a673c671a56 763 [..]
ebrus 0:0a673c671a56 764 This section provides functions allowing to:
ebrus 0:0a673c671a56 765 (+) Initialize and configure the FMC PCCARD interface
ebrus 0:0a673c671a56 766 (+) De-initialize the FMC PCCARD interface
ebrus 0:0a673c671a56 767 (+) Configure the FMC clock and associated GPIOs
ebrus 0:0a673c671a56 768
ebrus 0:0a673c671a56 769 @endverbatim
ebrus 0:0a673c671a56 770 * @{
ebrus 0:0a673c671a56 771 */
ebrus 0:0a673c671a56 772
ebrus 0:0a673c671a56 773 /**
ebrus 0:0a673c671a56 774 * @brief Initializes the FMC_PCCARD device according to the specified
ebrus 0:0a673c671a56 775 * control parameters in the FMC_PCCARD_HandleTypeDef
ebrus 0:0a673c671a56 776 * @param Device: Pointer to PCCARD device instance
ebrus 0:0a673c671a56 777 * @param Init: Pointer to PCCARD Initialization structure
ebrus 0:0a673c671a56 778 * @retval HAL status
ebrus 0:0a673c671a56 779 */
ebrus 0:0a673c671a56 780 HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init)
ebrus 0:0a673c671a56 781 {
ebrus 0:0a673c671a56 782 /* Check the parameters */
ebrus 0:0a673c671a56 783 assert_param(IS_FMC_PCCARD_DEVICE(Device));
ebrus 0:0a673c671a56 784 assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
ebrus 0:0a673c671a56 785 assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
ebrus 0:0a673c671a56 786 assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
ebrus 0:0a673c671a56 787
ebrus 0:0a673c671a56 788 /* Set FMC_PCCARD device control parameters */
ebrus 0:0a673c671a56 789 Device->PCR4 = (uint32_t)(Init->Waitfeature |\
ebrus 0:0a673c671a56 790 FMC_NAND_PCC_MEM_BUS_WIDTH_16 |\
ebrus 0:0a673c671a56 791 (Init->TCLRSetupTime << 9) |\
ebrus 0:0a673c671a56 792 (Init->TARSetupTime << 13));
ebrus 0:0a673c671a56 793
ebrus 0:0a673c671a56 794 return HAL_OK;
ebrus 0:0a673c671a56 795
ebrus 0:0a673c671a56 796 }
ebrus 0:0a673c671a56 797
ebrus 0:0a673c671a56 798 /**
ebrus 0:0a673c671a56 799 * @brief Initializes the FMC_PCCARD Common space Timing according to the specified
ebrus 0:0a673c671a56 800 * parameters in the FMC_NAND_PCC_TimingTypeDef
ebrus 0:0a673c671a56 801 * @param Device: Pointer to PCCARD device instance
ebrus 0:0a673c671a56 802 * @param Timing: Pointer to PCCARD timing structure
ebrus 0:0a673c671a56 803 * @retval HAL status
ebrus 0:0a673c671a56 804 */
ebrus 0:0a673c671a56 805 HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing)
ebrus 0:0a673c671a56 806 {
ebrus 0:0a673c671a56 807 /* Check the parameters */
ebrus 0:0a673c671a56 808 assert_param(IS_FMC_PCCARD_DEVICE(Device));
ebrus 0:0a673c671a56 809 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
ebrus 0:0a673c671a56 810 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
ebrus 0:0a673c671a56 811 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
ebrus 0:0a673c671a56 812 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
ebrus 0:0a673c671a56 813
ebrus 0:0a673c671a56 814 /* Set PCCARD timing parameters */
ebrus 0:0a673c671a56 815 Device->PMEM4 = (uint32_t)((Timing->SetupTime |\
ebrus 0:0a673c671a56 816 ((Timing->WaitSetupTime) << 8) |\
ebrus 0:0a673c671a56 817 (Timing->HoldSetupTime) << 16) |\
ebrus 0:0a673c671a56 818 ((Timing->HiZSetupTime) << 24)
ebrus 0:0a673c671a56 819 );
ebrus 0:0a673c671a56 820
ebrus 0:0a673c671a56 821 return HAL_OK;
ebrus 0:0a673c671a56 822 }
ebrus 0:0a673c671a56 823
ebrus 0:0a673c671a56 824 /**
ebrus 0:0a673c671a56 825 * @brief Initializes the FMC_PCCARD Attribute space Timing according to the specified
ebrus 0:0a673c671a56 826 * parameters in the FMC_NAND_PCC_TimingTypeDef
ebrus 0:0a673c671a56 827 * @param Device: Pointer to PCCARD device instance
ebrus 0:0a673c671a56 828 * @param Timing: Pointer to PCCARD timing structure
ebrus 0:0a673c671a56 829 * @retval HAL status
ebrus 0:0a673c671a56 830 */
ebrus 0:0a673c671a56 831 HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing)
ebrus 0:0a673c671a56 832 {
ebrus 0:0a673c671a56 833 /* Check the parameters */
ebrus 0:0a673c671a56 834 assert_param(IS_FMC_PCCARD_DEVICE(Device));
ebrus 0:0a673c671a56 835 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
ebrus 0:0a673c671a56 836 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
ebrus 0:0a673c671a56 837 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
ebrus 0:0a673c671a56 838 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
ebrus 0:0a673c671a56 839
ebrus 0:0a673c671a56 840 /* Set PCCARD timing parameters */
ebrus 0:0a673c671a56 841 Device->PATT4 = (uint32_t)((Timing->SetupTime |\
ebrus 0:0a673c671a56 842 ((Timing->WaitSetupTime) << 8) |\
ebrus 0:0a673c671a56 843 (Timing->HoldSetupTime) << 16) |\
ebrus 0:0a673c671a56 844 ((Timing->HiZSetupTime) << 24)
ebrus 0:0a673c671a56 845 );
ebrus 0:0a673c671a56 846
ebrus 0:0a673c671a56 847 return HAL_OK;
ebrus 0:0a673c671a56 848 }
ebrus 0:0a673c671a56 849
ebrus 0:0a673c671a56 850 /**
ebrus 0:0a673c671a56 851 * @brief Initializes the FMC_PCCARD IO space Timing according to the specified
ebrus 0:0a673c671a56 852 * parameters in the FMC_NAND_PCC_TimingTypeDef
ebrus 0:0a673c671a56 853 * @param Device: Pointer to PCCARD device instance
ebrus 0:0a673c671a56 854 * @param Timing: Pointer to PCCARD timing structure
ebrus 0:0a673c671a56 855 * @retval HAL status
ebrus 0:0a673c671a56 856 */
ebrus 0:0a673c671a56 857 HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing)
ebrus 0:0a673c671a56 858 {
ebrus 0:0a673c671a56 859 /* Check the parameters */
ebrus 0:0a673c671a56 860 assert_param(IS_FMC_PCCARD_DEVICE(Device));
ebrus 0:0a673c671a56 861 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
ebrus 0:0a673c671a56 862 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
ebrus 0:0a673c671a56 863 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
ebrus 0:0a673c671a56 864 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
ebrus 0:0a673c671a56 865
ebrus 0:0a673c671a56 866 /* Set FMC_PCCARD device timing parameters */
ebrus 0:0a673c671a56 867 Device->PIO4 = (uint32_t)((Timing->SetupTime |\
ebrus 0:0a673c671a56 868 ((Timing->WaitSetupTime) << 8) |\
ebrus 0:0a673c671a56 869 (Timing->HoldSetupTime) << 16) |\
ebrus 0:0a673c671a56 870 ((Timing->HiZSetupTime) << 24)
ebrus 0:0a673c671a56 871 );
ebrus 0:0a673c671a56 872
ebrus 0:0a673c671a56 873 return HAL_OK;
ebrus 0:0a673c671a56 874 }
ebrus 0:0a673c671a56 875
ebrus 0:0a673c671a56 876 /**
ebrus 0:0a673c671a56 877 * @brief DeInitializes the FMC_PCCARD device
ebrus 0:0a673c671a56 878 * @param Device: Pointer to PCCARD device instance
ebrus 0:0a673c671a56 879 * @retval HAL status
ebrus 0:0a673c671a56 880 */
ebrus 0:0a673c671a56 881 HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device)
ebrus 0:0a673c671a56 882 {
ebrus 0:0a673c671a56 883 /* Check the parameters */
ebrus 0:0a673c671a56 884 assert_param(IS_FMC_PCCARD_DEVICE(Device));
ebrus 0:0a673c671a56 885
ebrus 0:0a673c671a56 886 /* Disable the FMC_PCCARD device */
ebrus 0:0a673c671a56 887 __FMC_PCCARD_DISABLE(Device);
ebrus 0:0a673c671a56 888
ebrus 0:0a673c671a56 889 /* De-initialize the FMC_PCCARD device */
ebrus 0:0a673c671a56 890 Device->PCR4 = 0x00000018;
ebrus 0:0a673c671a56 891 Device->SR4 = 0x00000000;
ebrus 0:0a673c671a56 892 Device->PMEM4 = 0xFCFCFCFC;
ebrus 0:0a673c671a56 893 Device->PATT4 = 0xFCFCFCFC;
ebrus 0:0a673c671a56 894 Device->PIO4 = 0xFCFCFCFC;
ebrus 0:0a673c671a56 895
ebrus 0:0a673c671a56 896 return HAL_OK;
ebrus 0:0a673c671a56 897 }
ebrus 0:0a673c671a56 898
ebrus 0:0a673c671a56 899 /**
ebrus 0:0a673c671a56 900 * @}
ebrus 0:0a673c671a56 901 */
ebrus 0:0a673c671a56 902
ebrus 0:0a673c671a56 903
ebrus 0:0a673c671a56 904 /** @defgroup FMC_SDRAM Controller functions
ebrus 0:0a673c671a56 905 * @brief SDRAM Controller functions
ebrus 0:0a673c671a56 906 *
ebrus 0:0a673c671a56 907 @verbatim
ebrus 0:0a673c671a56 908 ==============================================================================
ebrus 0:0a673c671a56 909 ##### How to use SDRAM device driver #####
ebrus 0:0a673c671a56 910 ==============================================================================
ebrus 0:0a673c671a56 911 [..]
ebrus 0:0a673c671a56 912 This driver contains a set of APIs to interface with the FMC SDRAM banks in order
ebrus 0:0a673c671a56 913 to run the SDRAM external devices.
ebrus 0:0a673c671a56 914
ebrus 0:0a673c671a56 915 (+) FMC SDRAM bank reset using the function FMC_SDRAM_DeInit()
ebrus 0:0a673c671a56 916 (+) FMC SDRAM bank control configuration using the function FMC_SDRAM_Init()
ebrus 0:0a673c671a56 917 (+) FMC SDRAM bank timing configuration using the function FMC_SDRAM_Timing_Init()
ebrus 0:0a673c671a56 918 (+) FMC SDRAM bank enable/disable write operation using the functions
ebrus 0:0a673c671a56 919 FMC_SDRAM_WriteOperation_Enable()/FMC_SDRAM_WriteOperation_Disable()
ebrus 0:0a673c671a56 920 (+) FMC SDRAM bank send command using the function FMC_SDRAM_SendCommand()
ebrus 0:0a673c671a56 921
ebrus 0:0a673c671a56 922 @endverbatim
ebrus 0:0a673c671a56 923 * @{
ebrus 0:0a673c671a56 924 */
ebrus 0:0a673c671a56 925
ebrus 0:0a673c671a56 926 /** @defgroup HAL_FMC_SDRAM_Group1 Initialization/de-initialization functions
ebrus 0:0a673c671a56 927 * @brief Initialization and Configuration functions
ebrus 0:0a673c671a56 928 *
ebrus 0:0a673c671a56 929 @verbatim
ebrus 0:0a673c671a56 930 ==============================================================================
ebrus 0:0a673c671a56 931 ##### Initialization and de_initialization functions #####
ebrus 0:0a673c671a56 932 ==============================================================================
ebrus 0:0a673c671a56 933 [..]
ebrus 0:0a673c671a56 934 This section provides functions allowing to:
ebrus 0:0a673c671a56 935 (+) Initialize and configure the FMC SDRAM interface
ebrus 0:0a673c671a56 936 (+) De-initialize the FMC SDRAM interface
ebrus 0:0a673c671a56 937 (+) Configure the FMC clock and associated GPIOs
ebrus 0:0a673c671a56 938
ebrus 0:0a673c671a56 939 @endverbatim
ebrus 0:0a673c671a56 940 * @{
ebrus 0:0a673c671a56 941 */
ebrus 0:0a673c671a56 942
ebrus 0:0a673c671a56 943 /**
ebrus 0:0a673c671a56 944 * @brief Initializes the FMC_SDRAM device according to the specified
ebrus 0:0a673c671a56 945 * control parameters in the FMC_SDRAM_InitTypeDef
ebrus 0:0a673c671a56 946 * @param Device: Pointer to SDRAM device instance
ebrus 0:0a673c671a56 947 * @param Init: Pointer to SDRAM Initialization structure
ebrus 0:0a673c671a56 948 * @retval HAL status
ebrus 0:0a673c671a56 949 */
ebrus 0:0a673c671a56 950 HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init)
ebrus 0:0a673c671a56 951 {
ebrus 0:0a673c671a56 952 uint32_t tmpr1 = 0;
ebrus 0:0a673c671a56 953 uint32_t tmpr2 = 0;
ebrus 0:0a673c671a56 954
ebrus 0:0a673c671a56 955 /* Check the parameters */
ebrus 0:0a673c671a56 956 assert_param(IS_FMC_SDRAM_DEVICE(Device));
ebrus 0:0a673c671a56 957 assert_param(IS_FMC_SDRAM_BANK(Init->SDBank));
ebrus 0:0a673c671a56 958 assert_param(IS_FMC_COLUMNBITS_NUMBER(Init->ColumnBitsNumber));
ebrus 0:0a673c671a56 959 assert_param(IS_FMC_ROWBITS_NUMBER(Init->RowBitsNumber));
ebrus 0:0a673c671a56 960 assert_param(IS_FMC_SDMEMORY_WIDTH(Init->MemoryDataWidth));
ebrus 0:0a673c671a56 961 assert_param(IS_FMC_INTERNALBANK_NUMBER(Init->InternalBankNumber));
ebrus 0:0a673c671a56 962 assert_param(IS_FMC_CAS_LATENCY(Init->CASLatency));
ebrus 0:0a673c671a56 963 assert_param(IS_FMC_WRITE_PROTECTION(Init->WriteProtection));
ebrus 0:0a673c671a56 964 assert_param(IS_FMC_SDCLOCK_PERIOD(Init->SDClockPeriod));
ebrus 0:0a673c671a56 965 assert_param(IS_FMC_READ_BURST(Init->ReadBurst));
ebrus 0:0a673c671a56 966 assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay));
ebrus 0:0a673c671a56 967
ebrus 0:0a673c671a56 968 /* Set SDRAM bank configuration parameters */
ebrus 0:0a673c671a56 969 if (Init->SDBank != FMC_SDRAM_BANK2)
ebrus 0:0a673c671a56 970 {
ebrus 0:0a673c671a56 971 Device->SDCR[FMC_SDRAM_BANK1] = (uint32_t)(Init->ColumnBitsNumber |\
ebrus 0:0a673c671a56 972 Init->RowBitsNumber |\
ebrus 0:0a673c671a56 973 Init->MemoryDataWidth |\
ebrus 0:0a673c671a56 974 Init->InternalBankNumber |\
ebrus 0:0a673c671a56 975 Init->CASLatency |\
ebrus 0:0a673c671a56 976 Init->WriteProtection |\
ebrus 0:0a673c671a56 977 Init->SDClockPeriod |\
ebrus 0:0a673c671a56 978 Init->ReadBurst |\
ebrus 0:0a673c671a56 979 Init->ReadPipeDelay
ebrus 0:0a673c671a56 980 );
ebrus 0:0a673c671a56 981 }
ebrus 0:0a673c671a56 982 else /* FMC_Bank2_SDRAM */
ebrus 0:0a673c671a56 983 {
ebrus 0:0a673c671a56 984 tmpr1 = (uint32_t)(Init->SDClockPeriod |\
ebrus 0:0a673c671a56 985 Init->ReadBurst |\
ebrus 0:0a673c671a56 986 Init->ReadPipeDelay
ebrus 0:0a673c671a56 987 );
ebrus 0:0a673c671a56 988
ebrus 0:0a673c671a56 989 tmpr2 = (uint32_t)(Init->ColumnBitsNumber |\
ebrus 0:0a673c671a56 990 Init->RowBitsNumber |\
ebrus 0:0a673c671a56 991 Init->MemoryDataWidth |\
ebrus 0:0a673c671a56 992 Init->InternalBankNumber |\
ebrus 0:0a673c671a56 993 Init->CASLatency |\
ebrus 0:0a673c671a56 994 Init->WriteProtection
ebrus 0:0a673c671a56 995 );
ebrus 0:0a673c671a56 996
ebrus 0:0a673c671a56 997 Device->SDCR[FMC_SDRAM_BANK1] = tmpr1;
ebrus 0:0a673c671a56 998 Device->SDCR[FMC_SDRAM_BANK2] = tmpr2;
ebrus 0:0a673c671a56 999 }
ebrus 0:0a673c671a56 1000
ebrus 0:0a673c671a56 1001 return HAL_OK;
ebrus 0:0a673c671a56 1002 }
ebrus 0:0a673c671a56 1003
ebrus 0:0a673c671a56 1004 /**
ebrus 0:0a673c671a56 1005 * @brief Initializes the FMC_SDRAM device timing according to the specified
ebrus 0:0a673c671a56 1006 * parameters in the FMC_SDRAM_TimingTypeDef
ebrus 0:0a673c671a56 1007 * @param Device: Pointer to SDRAM device instance
ebrus 0:0a673c671a56 1008 * @param Timing: Pointer to SDRAM Timing structure
ebrus 0:0a673c671a56 1009 * @param Bank: SDRAM bank number
ebrus 0:0a673c671a56 1010 * @retval HAL status
ebrus 0:0a673c671a56 1011 */
ebrus 0:0a673c671a56 1012 HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank)
ebrus 0:0a673c671a56 1013 {
ebrus 0:0a673c671a56 1014 uint32_t tmpr1 = 0;
ebrus 0:0a673c671a56 1015 uint32_t tmpr2 = 0;
ebrus 0:0a673c671a56 1016
ebrus 0:0a673c671a56 1017 /* Check the parameters */
ebrus 0:0a673c671a56 1018 assert_param(IS_FMC_SDRAM_DEVICE(Device));
ebrus 0:0a673c671a56 1019 assert_param(IS_FMC_LOADTOACTIVE_DELAY(Timing->LoadToActiveDelay));
ebrus 0:0a673c671a56 1020 assert_param(IS_FMC_EXITSELFREFRESH_DELAY(Timing->ExitSelfRefreshDelay));
ebrus 0:0a673c671a56 1021 assert_param(IS_FMC_SELFREFRESH_TIME(Timing->SelfRefreshTime));
ebrus 0:0a673c671a56 1022 assert_param(IS_FMC_ROWCYCLE_DELAY(Timing->RowCycleDelay));
ebrus 0:0a673c671a56 1023 assert_param(IS_FMC_WRITE_RECOVERY_TIME(Timing->WriteRecoveryTime));
ebrus 0:0a673c671a56 1024 assert_param(IS_FMC_RP_DELAY(Timing->RPDelay));
ebrus 0:0a673c671a56 1025 assert_param(IS_FMC_RCD_DELAY(Timing->RCDDelay));
ebrus 0:0a673c671a56 1026 assert_param(IS_FMC_SDRAM_BANK(Bank));
ebrus 0:0a673c671a56 1027
ebrus 0:0a673c671a56 1028 /* Set SDRAM device timing parameters */
ebrus 0:0a673c671a56 1029 if (Bank != FMC_SDRAM_BANK2)
ebrus 0:0a673c671a56 1030 {
ebrus 0:0a673c671a56 1031 Device->SDTR[FMC_SDRAM_BANK1] = (uint32_t)(((Timing->LoadToActiveDelay)-1) |\
ebrus 0:0a673c671a56 1032 (((Timing->ExitSelfRefreshDelay)-1) << 4) |\
ebrus 0:0a673c671a56 1033 (((Timing->SelfRefreshTime)-1) << 8) |\
ebrus 0:0a673c671a56 1034 (((Timing->RowCycleDelay)-1) << 12) |\
ebrus 0:0a673c671a56 1035 (((Timing->WriteRecoveryTime)-1) <<16) |\
ebrus 0:0a673c671a56 1036 (((Timing->RPDelay)-1) << 20) |\
ebrus 0:0a673c671a56 1037 (((Timing->RCDDelay)-1) << 24)
ebrus 0:0a673c671a56 1038 );
ebrus 0:0a673c671a56 1039 }
ebrus 0:0a673c671a56 1040 else /* FMC_Bank2_SDRAM */
ebrus 0:0a673c671a56 1041 {
ebrus 0:0a673c671a56 1042
ebrus 0:0a673c671a56 1043 tmpr1 = (uint32_t)(((Timing->LoadToActiveDelay)-1) |\
ebrus 0:0a673c671a56 1044 (((Timing->ExitSelfRefreshDelay)-1) << 4) |\
ebrus 0:0a673c671a56 1045 (((Timing->SelfRefreshTime)-1) << 8) |\
ebrus 0:0a673c671a56 1046 (((Timing->WriteRecoveryTime)-1) <<16) |\
ebrus 0:0a673c671a56 1047 (((Timing->RCDDelay)-1) << 24)
ebrus 0:0a673c671a56 1048 );
ebrus 0:0a673c671a56 1049
ebrus 0:0a673c671a56 1050 tmpr2 = (uint32_t)((((Timing->RowCycleDelay)-1) << 12) |\
ebrus 0:0a673c671a56 1051 (((Timing->RPDelay)-1) << 20)
ebrus 0:0a673c671a56 1052 );
ebrus 0:0a673c671a56 1053
ebrus 0:0a673c671a56 1054 Device->SDTR[FMC_SDRAM_BANK2] = tmpr1;
ebrus 0:0a673c671a56 1055 Device->SDTR[FMC_SDRAM_BANK1] = tmpr2;
ebrus 0:0a673c671a56 1056 }
ebrus 0:0a673c671a56 1057
ebrus 0:0a673c671a56 1058 return HAL_OK;
ebrus 0:0a673c671a56 1059 }
ebrus 0:0a673c671a56 1060
ebrus 0:0a673c671a56 1061 /**
ebrus 0:0a673c671a56 1062 * @brief DeInitializes the FMC_SDRAM peripheral
ebrus 0:0a673c671a56 1063 * @param Device: Pointer to SDRAM device instance
ebrus 0:0a673c671a56 1064 * @retval HAL status
ebrus 0:0a673c671a56 1065 */
ebrus 0:0a673c671a56 1066 HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
ebrus 0:0a673c671a56 1067 {
ebrus 0:0a673c671a56 1068 /* Check the parameters */
ebrus 0:0a673c671a56 1069 assert_param(IS_FMC_SDRAM_DEVICE(Device));
ebrus 0:0a673c671a56 1070 assert_param(IS_FMC_SDRAM_BANK(Bank));
ebrus 0:0a673c671a56 1071
ebrus 0:0a673c671a56 1072 /* De-initialize the SDRAM device */
ebrus 0:0a673c671a56 1073 Device->SDCR[Bank] = 0x000002D0;
ebrus 0:0a673c671a56 1074 Device->SDTR[Bank] = 0x0FFFFFFF;
ebrus 0:0a673c671a56 1075 Device->SDCMR = 0x00000000;
ebrus 0:0a673c671a56 1076 Device->SDRTR = 0x00000000;
ebrus 0:0a673c671a56 1077 Device->SDSR = 0x00000000;
ebrus 0:0a673c671a56 1078
ebrus 0:0a673c671a56 1079 return HAL_OK;
ebrus 0:0a673c671a56 1080 }
ebrus 0:0a673c671a56 1081
ebrus 0:0a673c671a56 1082 /**
ebrus 0:0a673c671a56 1083 * @}
ebrus 0:0a673c671a56 1084 */
ebrus 0:0a673c671a56 1085
ebrus 0:0a673c671a56 1086
ebrus 0:0a673c671a56 1087 /** @defgroup HAL_FMC_SDRAM_Group3 Control functions
ebrus 0:0a673c671a56 1088 * @brief management functions
ebrus 0:0a673c671a56 1089 *
ebrus 0:0a673c671a56 1090 @verbatim
ebrus 0:0a673c671a56 1091 ==============================================================================
ebrus 0:0a673c671a56 1092 ##### FMC_SDRAM Control functions #####
ebrus 0:0a673c671a56 1093 ==============================================================================
ebrus 0:0a673c671a56 1094 [..]
ebrus 0:0a673c671a56 1095 This subsection provides a set of functions allowing to control dynamically
ebrus 0:0a673c671a56 1096 the FMC SDRAM interface.
ebrus 0:0a673c671a56 1097
ebrus 0:0a673c671a56 1098 @endverbatim
ebrus 0:0a673c671a56 1099 * @{
ebrus 0:0a673c671a56 1100 */
ebrus 0:0a673c671a56 1101
ebrus 0:0a673c671a56 1102 /**
ebrus 0:0a673c671a56 1103 * @brief Enables dynamically FMC_SDRAM write protection.
ebrus 0:0a673c671a56 1104 * @param Device: Pointer to SDRAM device instance
ebrus 0:0a673c671a56 1105 * @param Bank: SDRAM bank number
ebrus 0:0a673c671a56 1106 * @retval HAL status
ebrus 0:0a673c671a56 1107 */
ebrus 0:0a673c671a56 1108 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
ebrus 0:0a673c671a56 1109 {
ebrus 0:0a673c671a56 1110 /* Check the parameters */
ebrus 0:0a673c671a56 1111 assert_param(IS_FMC_SDRAM_DEVICE(Device));
ebrus 0:0a673c671a56 1112 assert_param(IS_FMC_SDRAM_BANK(Bank));
ebrus 0:0a673c671a56 1113
ebrus 0:0a673c671a56 1114 /* Enable write protection */
ebrus 0:0a673c671a56 1115 Device->SDCR[Bank] |= FMC_SDRAM_WRITE_PROTECTION_ENABLE;
ebrus 0:0a673c671a56 1116
ebrus 0:0a673c671a56 1117 return HAL_OK;
ebrus 0:0a673c671a56 1118 }
ebrus 0:0a673c671a56 1119
ebrus 0:0a673c671a56 1120 /**
ebrus 0:0a673c671a56 1121 * @brief Disables dynamically FMC_SDRAM write protection.
ebrus 0:0a673c671a56 1122 * @param hsdram: FMC_SDRAM handle
ebrus 0:0a673c671a56 1123 * @retval HAL status
ebrus 0:0a673c671a56 1124 */
ebrus 0:0a673c671a56 1125 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
ebrus 0:0a673c671a56 1126 {
ebrus 0:0a673c671a56 1127 /* Check the parameters */
ebrus 0:0a673c671a56 1128 assert_param(IS_FMC_SDRAM_DEVICE(Device));
ebrus 0:0a673c671a56 1129 assert_param(IS_FMC_SDRAM_BANK(Bank));
ebrus 0:0a673c671a56 1130
ebrus 0:0a673c671a56 1131 /* Disable write protection */
ebrus 0:0a673c671a56 1132 Device->SDCR[Bank] &= ~FMC_SDRAM_WRITE_PROTECTION_ENABLE;
ebrus 0:0a673c671a56 1133
ebrus 0:0a673c671a56 1134 return HAL_OK;
ebrus 0:0a673c671a56 1135 }
ebrus 0:0a673c671a56 1136
ebrus 0:0a673c671a56 1137 /**
ebrus 0:0a673c671a56 1138 * @brief Send Command to the FMC SDRAM bank
ebrus 0:0a673c671a56 1139 * @param Device: Pointer to SDRAM device instance
ebrus 0:0a673c671a56 1140 * @param Command: Pointer to SDRAM command structure
ebrus 0:0a673c671a56 1141 * @param Timing: Pointer to SDRAM Timing structure
ebrus 0:0a673c671a56 1142 * @param Timeout: Timeout wait value
ebrus 0:0a673c671a56 1143 * @retval HAL state
ebrus 0:0a673c671a56 1144 */
ebrus 0:0a673c671a56 1145 HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
ebrus 0:0a673c671a56 1146 {
ebrus 0:0a673c671a56 1147 __IO uint32_t tmpr = 0;
ebrus 0:0a673c671a56 1148 uint32_t timeout = 0;
ebrus 0:0a673c671a56 1149
ebrus 0:0a673c671a56 1150 /* Check the parameters */
ebrus 0:0a673c671a56 1151 assert_param(IS_FMC_SDRAM_DEVICE(Device));
ebrus 0:0a673c671a56 1152 assert_param(IS_FMC_COMMAND_MODE(Command->CommandMode));
ebrus 0:0a673c671a56 1153 assert_param(IS_FMC_COMMAND_TARGET(Command->CommandTarget));
ebrus 0:0a673c671a56 1154 assert_param(IS_FMC_AUTOREFRESH_NUMBER(Command->AutoRefreshNumber));
ebrus 0:0a673c671a56 1155 assert_param(IS_FMC_MODE_REGISTER(Command->ModeRegisterDefinition));
ebrus 0:0a673c671a56 1156
ebrus 0:0a673c671a56 1157 /* Set command register */
ebrus 0:0a673c671a56 1158 tmpr = (uint32_t)((Command->CommandMode) |\
ebrus 0:0a673c671a56 1159 (Command->CommandTarget) |\
ebrus 0:0a673c671a56 1160 (((Command->AutoRefreshNumber)-1) << 5) |\
ebrus 0:0a673c671a56 1161 ((Command->ModeRegisterDefinition) << 9)
ebrus 0:0a673c671a56 1162 );
ebrus 0:0a673c671a56 1163
ebrus 0:0a673c671a56 1164 Device->SDCMR = tmpr;
ebrus 0:0a673c671a56 1165
ebrus 0:0a673c671a56 1166 timeout = HAL_GetTick() + Timeout;
ebrus 0:0a673c671a56 1167
ebrus 0:0a673c671a56 1168 /* wait until command is send */
ebrus 0:0a673c671a56 1169 while(HAL_IS_BIT_SET(Device->SDSR, FMC_SDSR_BUSY))
ebrus 0:0a673c671a56 1170 {
ebrus 0:0a673c671a56 1171 /* Check for the Timeout */
ebrus 0:0a673c671a56 1172 if(Timeout != HAL_MAX_DELAY)
ebrus 0:0a673c671a56 1173 {
ebrus 0:0a673c671a56 1174 if(HAL_GetTick() >= timeout)
ebrus 0:0a673c671a56 1175 {
ebrus 0:0a673c671a56 1176 return HAL_TIMEOUT;
ebrus 0:0a673c671a56 1177 }
ebrus 0:0a673c671a56 1178 }
ebrus 0:0a673c671a56 1179
ebrus 0:0a673c671a56 1180 return HAL_ERROR;
ebrus 0:0a673c671a56 1181 }
ebrus 0:0a673c671a56 1182
ebrus 0:0a673c671a56 1183 return HAL_OK;
ebrus 0:0a673c671a56 1184 }
ebrus 0:0a673c671a56 1185
ebrus 0:0a673c671a56 1186 /**
ebrus 0:0a673c671a56 1187 * @brief Program the SDRAM Memory Refresh rate.
ebrus 0:0a673c671a56 1188 * @param Device: Pointer to SDRAM device instance
ebrus 0:0a673c671a56 1189 * @param RefreshRate: The SDRAM refresh rate value.
ebrus 0:0a673c671a56 1190 * @retval HAL state
ebrus 0:0a673c671a56 1191 */
ebrus 0:0a673c671a56 1192 HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate)
ebrus 0:0a673c671a56 1193 {
ebrus 0:0a673c671a56 1194 /* Check the parameters */
ebrus 0:0a673c671a56 1195 assert_param(IS_FMC_SDRAM_DEVICE(Device));
ebrus 0:0a673c671a56 1196 assert_param(IS_FMC_REFRESH_RATE(RefreshRate));
ebrus 0:0a673c671a56 1197
ebrus 0:0a673c671a56 1198 /* Set the refresh rate in command register */
ebrus 0:0a673c671a56 1199 Device->SDRTR |= (RefreshRate<<1);
ebrus 0:0a673c671a56 1200
ebrus 0:0a673c671a56 1201 return HAL_OK;
ebrus 0:0a673c671a56 1202 }
ebrus 0:0a673c671a56 1203
ebrus 0:0a673c671a56 1204 /**
ebrus 0:0a673c671a56 1205 * @brief Set the Number of consecutive SDRAM Memory auto Refresh commands.
ebrus 0:0a673c671a56 1206 * @param Device: Pointer to SDRAM device instance
ebrus 0:0a673c671a56 1207 * @param AutoRefreshNumber: Specifies the auto Refresh number.
ebrus 0:0a673c671a56 1208 * @retval None
ebrus 0:0a673c671a56 1209 */
ebrus 0:0a673c671a56 1210 HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber)
ebrus 0:0a673c671a56 1211 {
ebrus 0:0a673c671a56 1212 /* Check the parameters */
ebrus 0:0a673c671a56 1213 assert_param(IS_FMC_SDRAM_DEVICE(Device));
ebrus 0:0a673c671a56 1214 assert_param(IS_FMC_AUTOREFRESH_NUMBER(AutoRefreshNumber));
ebrus 0:0a673c671a56 1215
ebrus 0:0a673c671a56 1216 /* Set the Auto-refresh number in command register */
ebrus 0:0a673c671a56 1217 Device->SDCMR |= (AutoRefreshNumber << 5);
ebrus 0:0a673c671a56 1218
ebrus 0:0a673c671a56 1219 return HAL_OK;
ebrus 0:0a673c671a56 1220 }
ebrus 0:0a673c671a56 1221
ebrus 0:0a673c671a56 1222 /**
ebrus 0:0a673c671a56 1223 * @brief Returns the indicated FMC SDRAM bank mode status.
ebrus 0:0a673c671a56 1224 * @param Device: Pointer to SDRAM device instance
ebrus 0:0a673c671a56 1225 * @param Bank: Defines the FMC SDRAM bank. This parameter can be
ebrus 0:0a673c671a56 1226 * FMC_Bank1_SDRAM or FMC_Bank2_SDRAM.
ebrus 0:0a673c671a56 1227 * @retval The FMC SDRAM bank mode status, could be on of the following values:
ebrus 0:0a673c671a56 1228 * FMC_SDRAM_NORMAL_MODE, FMC_SDRAM_SELF_REFRESH_MODE or
ebrus 0:0a673c671a56 1229 * FMC_SDRAM_POWER_DOWN_MODE.
ebrus 0:0a673c671a56 1230 */
ebrus 0:0a673c671a56 1231 uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
ebrus 0:0a673c671a56 1232 {
ebrus 0:0a673c671a56 1233 uint32_t tmpreg = 0;
ebrus 0:0a673c671a56 1234
ebrus 0:0a673c671a56 1235 /* Check the parameters */
ebrus 0:0a673c671a56 1236 assert_param(IS_FMC_SDRAM_DEVICE(Device));
ebrus 0:0a673c671a56 1237 assert_param(IS_FMC_SDRAM_BANK(Bank));
ebrus 0:0a673c671a56 1238
ebrus 0:0a673c671a56 1239 /* Get the corresponding bank mode */
ebrus 0:0a673c671a56 1240 if(Bank == FMC_SDRAM_BANK1)
ebrus 0:0a673c671a56 1241 {
ebrus 0:0a673c671a56 1242 tmpreg = (uint32_t)(Device->SDSR & FMC_SDSR_MODES1);
ebrus 0:0a673c671a56 1243 }
ebrus 0:0a673c671a56 1244 else
ebrus 0:0a673c671a56 1245 {
ebrus 0:0a673c671a56 1246 tmpreg = ((uint32_t)(Device->SDSR & FMC_SDSR_MODES2) >> 2);
ebrus 0:0a673c671a56 1247 }
ebrus 0:0a673c671a56 1248
ebrus 0:0a673c671a56 1249 /* Return the mode status */
ebrus 0:0a673c671a56 1250 return tmpreg;
ebrus 0:0a673c671a56 1251 }
ebrus 0:0a673c671a56 1252
ebrus 0:0a673c671a56 1253 /**
ebrus 0:0a673c671a56 1254 * @}
ebrus 0:0a673c671a56 1255 */
ebrus 0:0a673c671a56 1256
ebrus 0:0a673c671a56 1257 /**
ebrus 0:0a673c671a56 1258 * @}
ebrus 0:0a673c671a56 1259 */
ebrus 0:0a673c671a56 1260
ebrus 0:0a673c671a56 1261 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
ebrus 0:0a673c671a56 1262
ebrus 0:0a673c671a56 1263 #endif /* HAL_FMC_MODULE_ENABLED */
ebrus 0:0a673c671a56 1264
ebrus 0:0a673c671a56 1265 /**
ebrus 0:0a673c671a56 1266 * @}
ebrus 0:0a673c671a56 1267 */
ebrus 0:0a673c671a56 1268
ebrus 0:0a673c671a56 1269 /**
ebrus 0:0a673c671a56 1270 * @}
ebrus 0:0a673c671a56 1271 */
ebrus 0:0a673c671a56 1272
ebrus 0:0a673c671a56 1273 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/