Elijah Stanger-Jones / mbed-dev-f303

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cmsis/core_sc300.h@2:4364577b5ad8, 2020-11-09 (annotated)

Committer:
elijahsj
Date:
Mon Nov 09 00:33:19 2020 -0500
Revision:
2:4364577b5ad8
Parent:
1:8a094db1347f 
copied mbed library

Who changed what in which revision?

UserRevisionLine numberNew contents of line
elijahsj 1:8a094db1347f 1 /**************************************************************************//**
elijahsj 1:8a094db1347f 2 * @file core_sc300.h
elijahsj 1:8a094db1347f 3 * @brief CMSIS SC300 Core Peripheral Access Layer Header File
elijahsj 1:8a094db1347f 4 * @version V5.0.2
elijahsj 1:8a094db1347f 5 * @date 13. February 2017
elijahsj 1:8a094db1347f 6 ******************************************************************************/
elijahsj 1:8a094db1347f 7 /*
elijahsj 1:8a094db1347f 8 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
elijahsj 1:8a094db1347f 9 *
elijahsj 1:8a094db1347f 10 * SPDX-License-Identifier: Apache-2.0
elijahsj 1:8a094db1347f 11 *
elijahsj 1:8a094db1347f 12 * Licensed under the Apache License, Version 2.0 (the License); you may
elijahsj 1:8a094db1347f 13 * not use this file except in compliance with the License.
elijahsj 1:8a094db1347f 14 * You may obtain a copy of the License at
elijahsj 1:8a094db1347f 15 *
elijahsj 1:8a094db1347f 16 * www.apache.org/licenses/LICENSE-2.0
elijahsj 1:8a094db1347f 17 *
elijahsj 1:8a094db1347f 18 * Unless required by applicable law or agreed to in writing, software
elijahsj 1:8a094db1347f 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
elijahsj 1:8a094db1347f 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
elijahsj 1:8a094db1347f 21 * See the License for the specific language governing permissions and
elijahsj 1:8a094db1347f 22 * limitations under the License.
elijahsj 1:8a094db1347f 23 */
elijahsj 1:8a094db1347f 24
elijahsj 1:8a094db1347f 25 #if defined ( __ICCARM__ )
elijahsj 1:8a094db1347f 26 #pragma system_include /* treat file as system include file for MISRA check */
elijahsj 1:8a094db1347f 27 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
elijahsj 1:8a094db1347f 28 #pragma clang system_header /* treat file as system include file */
elijahsj 1:8a094db1347f 29 #endif
elijahsj 1:8a094db1347f 30
elijahsj 1:8a094db1347f 31 #ifndef __CORE_SC300_H_GENERIC
elijahsj 1:8a094db1347f 32 #define __CORE_SC300_H_GENERIC
elijahsj 1:8a094db1347f 33
elijahsj 1:8a094db1347f 34 #include <stdint.h>
elijahsj 1:8a094db1347f 35
elijahsj 1:8a094db1347f 36 #ifdef __cplusplus
elijahsj 1:8a094db1347f 37 extern "C" {
elijahsj 1:8a094db1347f 38 #endif
elijahsj 1:8a094db1347f 39
elijahsj 1:8a094db1347f 40 /**
elijahsj 1:8a094db1347f 41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
elijahsj 1:8a094db1347f 42 CMSIS violates the following MISRA-C:2004 rules:
elijahsj 1:8a094db1347f 43
elijahsj 1:8a094db1347f 44 \li Required Rule 8.5, object/function definition in header file.<br>
elijahsj 1:8a094db1347f 45 Function definitions in header files are used to allow 'inlining'.
elijahsj 1:8a094db1347f 46
elijahsj 1:8a094db1347f 47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
elijahsj 1:8a094db1347f 48 Unions are used for effective representation of core registers.
elijahsj 1:8a094db1347f 49
elijahsj 1:8a094db1347f 50 \li Advisory Rule 19.7, Function-like macro defined.<br>
elijahsj 1:8a094db1347f 51 Function-like macros are used to allow more efficient code.
elijahsj 1:8a094db1347f 52 */
elijahsj 1:8a094db1347f 53
elijahsj 1:8a094db1347f 54
elijahsj 1:8a094db1347f 55 /*******************************************************************************
elijahsj 1:8a094db1347f 56 * CMSIS definitions
elijahsj 1:8a094db1347f 57 ******************************************************************************/
elijahsj 1:8a094db1347f 58 /**
elijahsj 1:8a094db1347f 59 \ingroup SC3000
elijahsj 1:8a094db1347f 60 @{
elijahsj 1:8a094db1347f 61 */
elijahsj 1:8a094db1347f 62
elijahsj 1:8a094db1347f 63 /* CMSIS SC300 definitions */
elijahsj 1:8a094db1347f 64 #define __SC300_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
elijahsj 1:8a094db1347f 65 #define __SC300_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
elijahsj 1:8a094db1347f 66 #define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \
elijahsj 1:8a094db1347f 67 __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
elijahsj 1:8a094db1347f 68
elijahsj 1:8a094db1347f 69 #define __CORTEX_SC (300U) /*!< Cortex secure core */
elijahsj 1:8a094db1347f 70
elijahsj 1:8a094db1347f 71 /** __FPU_USED indicates whether an FPU is used or not.
elijahsj 1:8a094db1347f 72 This core does not support an FPU at all
elijahsj 1:8a094db1347f 73 */
elijahsj 1:8a094db1347f 74 #define __FPU_USED 0U
elijahsj 1:8a094db1347f 75
elijahsj 1:8a094db1347f 76 #if defined ( __CC_ARM )
elijahsj 1:8a094db1347f 77 #if defined __TARGET_FPU_VFP
elijahsj 1:8a094db1347f 78 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
elijahsj 1:8a094db1347f 79 #endif
elijahsj 1:8a094db1347f 80
elijahsj 1:8a094db1347f 81 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
elijahsj 1:8a094db1347f 82 #if defined __ARM_PCS_VFP
elijahsj 1:8a094db1347f 83 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
elijahsj 1:8a094db1347f 84 #endif
elijahsj 1:8a094db1347f 85
elijahsj 1:8a094db1347f 86 #elif defined ( __GNUC__ )
elijahsj 1:8a094db1347f 87 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
elijahsj 1:8a094db1347f 88 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
elijahsj 1:8a094db1347f 89 #endif
elijahsj 1:8a094db1347f 90
elijahsj 1:8a094db1347f 91 #elif defined ( __ICCARM__ )
elijahsj 1:8a094db1347f 92 #if defined __ARMVFP__
elijahsj 1:8a094db1347f 93 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
elijahsj 1:8a094db1347f 94 #endif
elijahsj 1:8a094db1347f 95
elijahsj 1:8a094db1347f 96 #elif defined ( __TI_ARM__ )
elijahsj 1:8a094db1347f 97 #if defined __TI_VFP_SUPPORT__
elijahsj 1:8a094db1347f 98 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
elijahsj 1:8a094db1347f 99 #endif
elijahsj 1:8a094db1347f 100
elijahsj 1:8a094db1347f 101 #elif defined ( __TASKING__ )
elijahsj 1:8a094db1347f 102 #if defined __FPU_VFP__
elijahsj 1:8a094db1347f 103 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
elijahsj 1:8a094db1347f 104 #endif
elijahsj 1:8a094db1347f 105
elijahsj 1:8a094db1347f 106 #elif defined ( __CSMC__ )
elijahsj 1:8a094db1347f 107 #if ( __CSMC__ & 0x400U)
elijahsj 1:8a094db1347f 108 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
elijahsj 1:8a094db1347f 109 #endif
elijahsj 1:8a094db1347f 110
elijahsj 1:8a094db1347f 111 #endif
elijahsj 1:8a094db1347f 112
elijahsj 1:8a094db1347f 113 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
elijahsj 1:8a094db1347f 114
elijahsj 1:8a094db1347f 115
elijahsj 1:8a094db1347f 116 #ifdef __cplusplus
elijahsj 1:8a094db1347f 117 }
elijahsj 1:8a094db1347f 118 #endif
elijahsj 1:8a094db1347f 119
elijahsj 1:8a094db1347f 120 #endif /* __CORE_SC300_H_GENERIC */
elijahsj 1:8a094db1347f 121
elijahsj 1:8a094db1347f 122 #ifndef __CMSIS_GENERIC
elijahsj 1:8a094db1347f 123
elijahsj 1:8a094db1347f 124 #ifndef __CORE_SC300_H_DEPENDANT
elijahsj 1:8a094db1347f 125 #define __CORE_SC300_H_DEPENDANT
elijahsj 1:8a094db1347f 126
elijahsj 1:8a094db1347f 127 #ifdef __cplusplus
elijahsj 1:8a094db1347f 128 extern "C" {
elijahsj 1:8a094db1347f 129 #endif
elijahsj 1:8a094db1347f 130
elijahsj 1:8a094db1347f 131 /* check device defines and use defaults */
elijahsj 1:8a094db1347f 132 #if defined __CHECK_DEVICE_DEFINES
elijahsj 1:8a094db1347f 133 #ifndef __SC300_REV
elijahsj 1:8a094db1347f 134 #define __SC300_REV 0x0000U
elijahsj 1:8a094db1347f 135 #warning "__SC300_REV not defined in device header file; using default!"
elijahsj 1:8a094db1347f 136 #endif
elijahsj 1:8a094db1347f 137
elijahsj 1:8a094db1347f 138 #ifndef __MPU_PRESENT
elijahsj 1:8a094db1347f 139 #define __MPU_PRESENT 0U
elijahsj 1:8a094db1347f 140 #warning "__MPU_PRESENT not defined in device header file; using default!"
elijahsj 1:8a094db1347f 141 #endif
elijahsj 1:8a094db1347f 142
elijahsj 1:8a094db1347f 143 #ifndef __NVIC_PRIO_BITS
elijahsj 1:8a094db1347f 144 #define __NVIC_PRIO_BITS 3U
elijahsj 1:8a094db1347f 145 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
elijahsj 1:8a094db1347f 146 #endif
elijahsj 1:8a094db1347f 147
elijahsj 1:8a094db1347f 148 #ifndef __Vendor_SysTickConfig
elijahsj 1:8a094db1347f 149 #define __Vendor_SysTickConfig 0U
elijahsj 1:8a094db1347f 150 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
elijahsj 1:8a094db1347f 151 #endif
elijahsj 1:8a094db1347f 152 #endif
elijahsj 1:8a094db1347f 153
elijahsj 1:8a094db1347f 154 /* IO definitions (access restrictions to peripheral registers) */
elijahsj 1:8a094db1347f 155 /**
elijahsj 1:8a094db1347f 156 \defgroup CMSIS_glob_defs CMSIS Global Defines
elijahsj 1:8a094db1347f 157
elijahsj 1:8a094db1347f 158 <strong>IO Type Qualifiers</strong> are used
elijahsj 1:8a094db1347f 159 \li to specify the access to peripheral variables.
elijahsj 1:8a094db1347f 160 \li for automatic generation of peripheral register debug information.
elijahsj 1:8a094db1347f 161 */
elijahsj 1:8a094db1347f 162 #ifdef __cplusplus
elijahsj 1:8a094db1347f 163 #define __I volatile /*!< Defines 'read only' permissions */
elijahsj 1:8a094db1347f 164 #else
elijahsj 1:8a094db1347f 165 #define __I volatile const /*!< Defines 'read only' permissions */
elijahsj 1:8a094db1347f 166 #endif
elijahsj 1:8a094db1347f 167 #define __O volatile /*!< Defines 'write only' permissions */
elijahsj 1:8a094db1347f 168 #define __IO volatile /*!< Defines 'read / write' permissions */
elijahsj 1:8a094db1347f 169
elijahsj 1:8a094db1347f 170 /* following defines should be used for structure members */
elijahsj 1:8a094db1347f 171 #define __IM volatile const /*! Defines 'read only' structure member permissions */
elijahsj 1:8a094db1347f 172 #define __OM volatile /*! Defines 'write only' structure member permissions */
elijahsj 1:8a094db1347f 173 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
elijahsj 1:8a094db1347f 174
elijahsj 1:8a094db1347f 175 /*@} end of group SC300 */
elijahsj 1:8a094db1347f 176
elijahsj 1:8a094db1347f 177
elijahsj 1:8a094db1347f 178
elijahsj 1:8a094db1347f 179 /*******************************************************************************
elijahsj 1:8a094db1347f 180 * Register Abstraction
elijahsj 1:8a094db1347f 181 Core Register contain:
elijahsj 1:8a094db1347f 182 - Core Register
elijahsj 1:8a094db1347f 183 - Core NVIC Register
elijahsj 1:8a094db1347f 184 - Core SCB Register
elijahsj 1:8a094db1347f 185 - Core SysTick Register
elijahsj 1:8a094db1347f 186 - Core Debug Register
elijahsj 1:8a094db1347f 187 - Core MPU Register
elijahsj 1:8a094db1347f 188 ******************************************************************************/
elijahsj 1:8a094db1347f 189 /**
elijahsj 1:8a094db1347f 190 \defgroup CMSIS_core_register Defines and Type Definitions
elijahsj 1:8a094db1347f 191 \brief Type definitions and defines for Cortex-M processor based devices.
elijahsj 1:8a094db1347f 192 */
elijahsj 1:8a094db1347f 193
elijahsj 1:8a094db1347f 194 /**
elijahsj 1:8a094db1347f 195 \ingroup CMSIS_core_register
elijahsj 1:8a094db1347f 196 \defgroup CMSIS_CORE Status and Control Registers
elijahsj 1:8a094db1347f 197 \brief Core Register type definitions.
elijahsj 1:8a094db1347f 198 @{
elijahsj 1:8a094db1347f 199 */
elijahsj 1:8a094db1347f 200
elijahsj 1:8a094db1347f 201 /**
elijahsj 1:8a094db1347f 202 \brief Union type to access the Application Program Status Register (APSR).
elijahsj 1:8a094db1347f 203 */
elijahsj 1:8a094db1347f 204 typedef union
elijahsj 1:8a094db1347f 205 {
elijahsj 1:8a094db1347f 206 struct
elijahsj 1:8a094db1347f 207 {
elijahsj 1:8a094db1347f 208 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
elijahsj 1:8a094db1347f 209 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
elijahsj 1:8a094db1347f 210 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
elijahsj 1:8a094db1347f 211 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
elijahsj 1:8a094db1347f 212 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
elijahsj 1:8a094db1347f 213 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
elijahsj 1:8a094db1347f 214 } b; /*!< Structure used for bit access */
elijahsj 1:8a094db1347f 215 uint32_t w; /*!< Type used for word access */
elijahsj 1:8a094db1347f 216 } APSR_Type;
elijahsj 1:8a094db1347f 217
elijahsj 1:8a094db1347f 218 /* APSR Register Definitions */
elijahsj 1:8a094db1347f 219 #define APSR_N_Pos 31U /*!< APSR: N Position */
elijahsj 1:8a094db1347f 220 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
elijahsj 1:8a094db1347f 221
elijahsj 1:8a094db1347f 222 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
elijahsj 1:8a094db1347f 223 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
elijahsj 1:8a094db1347f 224
elijahsj 1:8a094db1347f 225 #define APSR_C_Pos 29U /*!< APSR: C Position */
elijahsj 1:8a094db1347f 226 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
elijahsj 1:8a094db1347f 227
elijahsj 1:8a094db1347f 228 #define APSR_V_Pos 28U /*!< APSR: V Position */
elijahsj 1:8a094db1347f 229 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
elijahsj 1:8a094db1347f 230
elijahsj 1:8a094db1347f 231 #define APSR_Q_Pos 27U /*!< APSR: Q Position */
elijahsj 1:8a094db1347f 232 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
elijahsj 1:8a094db1347f 233
elijahsj 1:8a094db1347f 234
elijahsj 1:8a094db1347f 235 /**
elijahsj 1:8a094db1347f 236 \brief Union type to access the Interrupt Program Status Register (IPSR).
elijahsj 1:8a094db1347f 237 */
elijahsj 1:8a094db1347f 238 typedef union
elijahsj 1:8a094db1347f 239 {
elijahsj 1:8a094db1347f 240 struct
elijahsj 1:8a094db1347f 241 {
elijahsj 1:8a094db1347f 242 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
elijahsj 1:8a094db1347f 243 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
elijahsj 1:8a094db1347f 244 } b; /*!< Structure used for bit access */
elijahsj 1:8a094db1347f 245 uint32_t w; /*!< Type used for word access */
elijahsj 1:8a094db1347f 246 } IPSR_Type;
elijahsj 1:8a094db1347f 247
elijahsj 1:8a094db1347f 248 /* IPSR Register Definitions */
elijahsj 1:8a094db1347f 249 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
elijahsj 1:8a094db1347f 250 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
elijahsj 1:8a094db1347f 251
elijahsj 1:8a094db1347f 252
elijahsj 1:8a094db1347f 253 /**
elijahsj 1:8a094db1347f 254 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
elijahsj 1:8a094db1347f 255 */
elijahsj 1:8a094db1347f 256 typedef union
elijahsj 1:8a094db1347f 257 {
elijahsj 1:8a094db1347f 258 struct
elijahsj 1:8a094db1347f 259 {
elijahsj 1:8a094db1347f 260 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
elijahsj 1:8a094db1347f 261 uint32_t _reserved0:1; /*!< bit: 9 Reserved */
elijahsj 1:8a094db1347f 262 uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
elijahsj 1:8a094db1347f 263 uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */
elijahsj 1:8a094db1347f 264 uint32_t T:1; /*!< bit: 24 Thumb bit */
elijahsj 1:8a094db1347f 265 uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
elijahsj 1:8a094db1347f 266 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
elijahsj 1:8a094db1347f 267 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
elijahsj 1:8a094db1347f 268 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
elijahsj 1:8a094db1347f 269 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
elijahsj 1:8a094db1347f 270 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
elijahsj 1:8a094db1347f 271 } b; /*!< Structure used for bit access */
elijahsj 1:8a094db1347f 272 uint32_t w; /*!< Type used for word access */
elijahsj 1:8a094db1347f 273 } xPSR_Type;
elijahsj 1:8a094db1347f 274
elijahsj 1:8a094db1347f 275 /* xPSR Register Definitions */
elijahsj 1:8a094db1347f 276 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
elijahsj 1:8a094db1347f 277 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
elijahsj 1:8a094db1347f 278
elijahsj 1:8a094db1347f 279 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
elijahsj 1:8a094db1347f 280 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
elijahsj 1:8a094db1347f 281
elijahsj 1:8a094db1347f 282 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
elijahsj 1:8a094db1347f 283 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
elijahsj 1:8a094db1347f 284
elijahsj 1:8a094db1347f 285 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
elijahsj 1:8a094db1347f 286 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
elijahsj 1:8a094db1347f 287
elijahsj 1:8a094db1347f 288 #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
elijahsj 1:8a094db1347f 289 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
elijahsj 1:8a094db1347f 290
elijahsj 1:8a094db1347f 291 #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
elijahsj 1:8a094db1347f 292 #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
elijahsj 1:8a094db1347f 293
elijahsj 1:8a094db1347f 294 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
elijahsj 1:8a094db1347f 295 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
elijahsj 1:8a094db1347f 296
elijahsj 1:8a094db1347f 297 #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
elijahsj 1:8a094db1347f 298 #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
elijahsj 1:8a094db1347f 299
elijahsj 1:8a094db1347f 300 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
elijahsj 1:8a094db1347f 301 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
elijahsj 1:8a094db1347f 302
elijahsj 1:8a094db1347f 303
elijahsj 1:8a094db1347f 304 /**
elijahsj 1:8a094db1347f 305 \brief Union type to access the Control Registers (CONTROL).
elijahsj 1:8a094db1347f 306 */
elijahsj 1:8a094db1347f 307 typedef union
elijahsj 1:8a094db1347f 308 {
elijahsj 1:8a094db1347f 309 struct
elijahsj 1:8a094db1347f 310 {
elijahsj 1:8a094db1347f 311 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
elijahsj 1:8a094db1347f 312 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
elijahsj 1:8a094db1347f 313 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
elijahsj 1:8a094db1347f 314 } b; /*!< Structure used for bit access */
elijahsj 1:8a094db1347f 315 uint32_t w; /*!< Type used for word access */
elijahsj 1:8a094db1347f 316 } CONTROL_Type;
elijahsj 1:8a094db1347f 317
elijahsj 1:8a094db1347f 318 /* CONTROL Register Definitions */
elijahsj 1:8a094db1347f 319 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
elijahsj 1:8a094db1347f 320 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
elijahsj 1:8a094db1347f 321
elijahsj 1:8a094db1347f 322 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
elijahsj 1:8a094db1347f 323 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
elijahsj 1:8a094db1347f 324
elijahsj 1:8a094db1347f 325 /*@} end of group CMSIS_CORE */
elijahsj 1:8a094db1347f 326
elijahsj 1:8a094db1347f 327
elijahsj 1:8a094db1347f 328 /**
elijahsj 1:8a094db1347f 329 \ingroup CMSIS_core_register
elijahsj 1:8a094db1347f 330 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
elijahsj 1:8a094db1347f 331 \brief Type definitions for the NVIC Registers
elijahsj 1:8a094db1347f 332 @{
elijahsj 1:8a094db1347f 333 */
elijahsj 1:8a094db1347f 334
elijahsj 1:8a094db1347f 335 /**
elijahsj 1:8a094db1347f 336 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
elijahsj 1:8a094db1347f 337 */
elijahsj 1:8a094db1347f 338 typedef struct
elijahsj 1:8a094db1347f 339 {
elijahsj 1:8a094db1347f 340 __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
elijahsj 1:8a094db1347f 341 uint32_t RESERVED0[24U];
elijahsj 1:8a094db1347f 342 __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
elijahsj 1:8a094db1347f 343 uint32_t RSERVED1[24U];
elijahsj 1:8a094db1347f 344 __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
elijahsj 1:8a094db1347f 345 uint32_t RESERVED2[24U];
elijahsj 1:8a094db1347f 346 __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
elijahsj 1:8a094db1347f 347 uint32_t RESERVED3[24U];
elijahsj 1:8a094db1347f 348 __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
elijahsj 1:8a094db1347f 349 uint32_t RESERVED4[56U];
elijahsj 1:8a094db1347f 350 __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
elijahsj 1:8a094db1347f 351 uint32_t RESERVED5[644U];
elijahsj 1:8a094db1347f 352 __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
elijahsj 1:8a094db1347f 353 } NVIC_Type;
elijahsj 1:8a094db1347f 354
elijahsj 1:8a094db1347f 355 /* Software Triggered Interrupt Register Definitions */
elijahsj 1:8a094db1347f 356 #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
elijahsj 1:8a094db1347f 357 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
elijahsj 1:8a094db1347f 358
elijahsj 1:8a094db1347f 359 /*@} end of group CMSIS_NVIC */
elijahsj 1:8a094db1347f 360
elijahsj 1:8a094db1347f 361
elijahsj 1:8a094db1347f 362 /**
elijahsj 1:8a094db1347f 363 \ingroup CMSIS_core_register
elijahsj 1:8a094db1347f 364 \defgroup CMSIS_SCB System Control Block (SCB)
elijahsj 1:8a094db1347f 365 \brief Type definitions for the System Control Block Registers
elijahsj 1:8a094db1347f 366 @{
elijahsj 1:8a094db1347f 367 */
elijahsj 1:8a094db1347f 368
elijahsj 1:8a094db1347f 369 /**
elijahsj 1:8a094db1347f 370 \brief Structure type to access the System Control Block (SCB).
elijahsj 1:8a094db1347f 371 */
elijahsj 1:8a094db1347f 372 typedef struct
elijahsj 1:8a094db1347f 373 {
elijahsj 1:8a094db1347f 374 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
elijahsj 1:8a094db1347f 375 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
elijahsj 1:8a094db1347f 376 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
elijahsj 1:8a094db1347f 377 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
elijahsj 1:8a094db1347f 378 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
elijahsj 1:8a094db1347f 379 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
elijahsj 1:8a094db1347f 380 __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
elijahsj 1:8a094db1347f 381 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
elijahsj 1:8a094db1347f 382 __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
elijahsj 1:8a094db1347f 383 __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
elijahsj 1:8a094db1347f 384 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
elijahsj 1:8a094db1347f 385 __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
elijahsj 1:8a094db1347f 386 __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
elijahsj 1:8a094db1347f 387 __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
elijahsj 1:8a094db1347f 388 __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
elijahsj 1:8a094db1347f 389 __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
elijahsj 1:8a094db1347f 390 __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
elijahsj 1:8a094db1347f 391 __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
elijahsj 1:8a094db1347f 392 __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
elijahsj 1:8a094db1347f 393 uint32_t RESERVED0[5U];
elijahsj 1:8a094db1347f 394 __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
elijahsj 1:8a094db1347f 395 uint32_t RESERVED1[129U];
elijahsj 1:8a094db1347f 396 __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
elijahsj 1:8a094db1347f 397 } SCB_Type;
elijahsj 1:8a094db1347f 398
elijahsj 1:8a094db1347f 399 /* SCB CPUID Register Definitions */
elijahsj 1:8a094db1347f 400 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
elijahsj 1:8a094db1347f 401 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
elijahsj 1:8a094db1347f 402
elijahsj 1:8a094db1347f 403 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
elijahsj 1:8a094db1347f 404 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
elijahsj 1:8a094db1347f 405
elijahsj 1:8a094db1347f 406 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
elijahsj 1:8a094db1347f 407 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
elijahsj 1:8a094db1347f 408
elijahsj 1:8a094db1347f 409 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
elijahsj 1:8a094db1347f 410 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
elijahsj 1:8a094db1347f 411
elijahsj 1:8a094db1347f 412 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
elijahsj 1:8a094db1347f 413 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
elijahsj 1:8a094db1347f 414
elijahsj 1:8a094db1347f 415 /* SCB Interrupt Control State Register Definitions */
elijahsj 1:8a094db1347f 416 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
elijahsj 1:8a094db1347f 417 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
elijahsj 1:8a094db1347f 418
elijahsj 1:8a094db1347f 419 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
elijahsj 1:8a094db1347f 420 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
elijahsj 1:8a094db1347f 421
elijahsj 1:8a094db1347f 422 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
elijahsj 1:8a094db1347f 423 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
elijahsj 1:8a094db1347f 424
elijahsj 1:8a094db1347f 425 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
elijahsj 1:8a094db1347f 426 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
elijahsj 1:8a094db1347f 427
elijahsj 1:8a094db1347f 428 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
elijahsj 1:8a094db1347f 429 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
elijahsj 1:8a094db1347f 430
elijahsj 1:8a094db1347f 431 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
elijahsj 1:8a094db1347f 432 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
elijahsj 1:8a094db1347f 433
elijahsj 1:8a094db1347f 434 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
elijahsj 1:8a094db1347f 435 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
elijahsj 1:8a094db1347f 436
elijahsj 1:8a094db1347f 437 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
elijahsj 1:8a094db1347f 438 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
elijahsj 1:8a094db1347f 439
elijahsj 1:8a094db1347f 440 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
elijahsj 1:8a094db1347f 441 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
elijahsj 1:8a094db1347f 442
elijahsj 1:8a094db1347f 443 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
elijahsj 1:8a094db1347f 444 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
elijahsj 1:8a094db1347f 445
elijahsj 1:8a094db1347f 446 /* SCB Vector Table Offset Register Definitions */
elijahsj 1:8a094db1347f 447 #define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */
elijahsj 1:8a094db1347f 448 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
elijahsj 1:8a094db1347f 449
elijahsj 1:8a094db1347f 450 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
elijahsj 1:8a094db1347f 451 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
elijahsj 1:8a094db1347f 452
elijahsj 1:8a094db1347f 453 /* SCB Application Interrupt and Reset Control Register Definitions */
elijahsj 1:8a094db1347f 454 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
elijahsj 1:8a094db1347f 455 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
elijahsj 1:8a094db1347f 456
elijahsj 1:8a094db1347f 457 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
elijahsj 1:8a094db1347f 458 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
elijahsj 1:8a094db1347f 459
elijahsj 1:8a094db1347f 460 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
elijahsj 1:8a094db1347f 461 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
elijahsj 1:8a094db1347f 462
elijahsj 1:8a094db1347f 463 #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
elijahsj 1:8a094db1347f 464 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
elijahsj 1:8a094db1347f 465
elijahsj 1:8a094db1347f 466 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
elijahsj 1:8a094db1347f 467 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
elijahsj 1:8a094db1347f 468
elijahsj 1:8a094db1347f 469 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
elijahsj 1:8a094db1347f 470 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
elijahsj 1:8a094db1347f 471
elijahsj 1:8a094db1347f 472 #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
elijahsj 1:8a094db1347f 473 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
elijahsj 1:8a094db1347f 474
elijahsj 1:8a094db1347f 475 /* SCB System Control Register Definitions */
elijahsj 1:8a094db1347f 476 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
elijahsj 1:8a094db1347f 477 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
elijahsj 1:8a094db1347f 478
elijahsj 1:8a094db1347f 479 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
elijahsj 1:8a094db1347f 480 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
elijahsj 1:8a094db1347f 481
elijahsj 1:8a094db1347f 482 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
elijahsj 1:8a094db1347f 483 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
elijahsj 1:8a094db1347f 484
elijahsj 1:8a094db1347f 485 /* SCB Configuration Control Register Definitions */
elijahsj 1:8a094db1347f 486 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
elijahsj 1:8a094db1347f 487 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
elijahsj 1:8a094db1347f 488
elijahsj 1:8a094db1347f 489 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
elijahsj 1:8a094db1347f 490 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
elijahsj 1:8a094db1347f 491
elijahsj 1:8a094db1347f 492 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
elijahsj 1:8a094db1347f 493 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
elijahsj 1:8a094db1347f 494
elijahsj 1:8a094db1347f 495 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
elijahsj 1:8a094db1347f 496 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
elijahsj 1:8a094db1347f 497
elijahsj 1:8a094db1347f 498 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
elijahsj 1:8a094db1347f 499 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
elijahsj 1:8a094db1347f 500
elijahsj 1:8a094db1347f 501 #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
elijahsj 1:8a094db1347f 502 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
elijahsj 1:8a094db1347f 503
elijahsj 1:8a094db1347f 504 /* SCB System Handler Control and State Register Definitions */
elijahsj 1:8a094db1347f 505 #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
elijahsj 1:8a094db1347f 506 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
elijahsj 1:8a094db1347f 507
elijahsj 1:8a094db1347f 508 #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
elijahsj 1:8a094db1347f 509 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
elijahsj 1:8a094db1347f 510
elijahsj 1:8a094db1347f 511 #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
elijahsj 1:8a094db1347f 512 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
elijahsj 1:8a094db1347f 513
elijahsj 1:8a094db1347f 514 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
elijahsj 1:8a094db1347f 515 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
elijahsj 1:8a094db1347f 516
elijahsj 1:8a094db1347f 517 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
elijahsj 1:8a094db1347f 518 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
elijahsj 1:8a094db1347f 519
elijahsj 1:8a094db1347f 520 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
elijahsj 1:8a094db1347f 521 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
elijahsj 1:8a094db1347f 522
elijahsj 1:8a094db1347f 523 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
elijahsj 1:8a094db1347f 524 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
elijahsj 1:8a094db1347f 525
elijahsj 1:8a094db1347f 526 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
elijahsj 1:8a094db1347f 527 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
elijahsj 1:8a094db1347f 528
elijahsj 1:8a094db1347f 529 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
elijahsj 1:8a094db1347f 530 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
elijahsj 1:8a094db1347f 531
elijahsj 1:8a094db1347f 532 #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
elijahsj 1:8a094db1347f 533 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
elijahsj 1:8a094db1347f 534
elijahsj 1:8a094db1347f 535 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
elijahsj 1:8a094db1347f 536 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
elijahsj 1:8a094db1347f 537
elijahsj 1:8a094db1347f 538 #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
elijahsj 1:8a094db1347f 539 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
elijahsj 1:8a094db1347f 540
elijahsj 1:8a094db1347f 541 #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
elijahsj 1:8a094db1347f 542 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
elijahsj 1:8a094db1347f 543
elijahsj 1:8a094db1347f 544 #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
elijahsj 1:8a094db1347f 545 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
elijahsj 1:8a094db1347f 546
elijahsj 1:8a094db1347f 547 /* SCB Configurable Fault Status Register Definitions */
elijahsj 1:8a094db1347f 548 #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
elijahsj 1:8a094db1347f 549 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
elijahsj 1:8a094db1347f 550
elijahsj 1:8a094db1347f 551 #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
elijahsj 1:8a094db1347f 552 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
elijahsj 1:8a094db1347f 553
elijahsj 1:8a094db1347f 554 #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
elijahsj 1:8a094db1347f 555 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
elijahsj 1:8a094db1347f 556
elijahsj 1:8a094db1347f 557 /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
elijahsj 1:8a094db1347f 558 #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
elijahsj 1:8a094db1347f 559 #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
elijahsj 1:8a094db1347f 560
elijahsj 1:8a094db1347f 561 #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
elijahsj 1:8a094db1347f 562 #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
elijahsj 1:8a094db1347f 563
elijahsj 1:8a094db1347f 564 #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
elijahsj 1:8a094db1347f 565 #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
elijahsj 1:8a094db1347f 566
elijahsj 1:8a094db1347f 567 #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
elijahsj 1:8a094db1347f 568 #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
elijahsj 1:8a094db1347f 569
elijahsj 1:8a094db1347f 570 #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
elijahsj 1:8a094db1347f 571 #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
elijahsj 1:8a094db1347f 572
elijahsj 1:8a094db1347f 573 /* BusFault Status Register (part of SCB Configurable Fault Status Register) */
elijahsj 1:8a094db1347f 574 #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
elijahsj 1:8a094db1347f 575 #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
elijahsj 1:8a094db1347f 576
elijahsj 1:8a094db1347f 577 #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
elijahsj 1:8a094db1347f 578 #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
elijahsj 1:8a094db1347f 579
elijahsj 1:8a094db1347f 580 #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
elijahsj 1:8a094db1347f 581 #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
elijahsj 1:8a094db1347f 582
elijahsj 1:8a094db1347f 583 #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
elijahsj 1:8a094db1347f 584 #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
elijahsj 1:8a094db1347f 585
elijahsj 1:8a094db1347f 586 #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
elijahsj 1:8a094db1347f 587 #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
elijahsj 1:8a094db1347f 588
elijahsj 1:8a094db1347f 589 #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
elijahsj 1:8a094db1347f 590 #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
elijahsj 1:8a094db1347f 591
elijahsj 1:8a094db1347f 592 /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
elijahsj 1:8a094db1347f 593 #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
elijahsj 1:8a094db1347f 594 #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
elijahsj 1:8a094db1347f 595
elijahsj 1:8a094db1347f 596 #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
elijahsj 1:8a094db1347f 597 #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
elijahsj 1:8a094db1347f 598
elijahsj 1:8a094db1347f 599 #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
elijahsj 1:8a094db1347f 600 #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
elijahsj 1:8a094db1347f 601
elijahsj 1:8a094db1347f 602 #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
elijahsj 1:8a094db1347f 603 #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
elijahsj 1:8a094db1347f 604
elijahsj 1:8a094db1347f 605 #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
elijahsj 1:8a094db1347f 606 #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
elijahsj 1:8a094db1347f 607
elijahsj 1:8a094db1347f 608 #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
elijahsj 1:8a094db1347f 609 #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
elijahsj 1:8a094db1347f 610
elijahsj 1:8a094db1347f 611 /* SCB Hard Fault Status Register Definitions */
elijahsj 1:8a094db1347f 612 #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
elijahsj 1:8a094db1347f 613 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
elijahsj 1:8a094db1347f 614
elijahsj 1:8a094db1347f 615 #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
elijahsj 1:8a094db1347f 616 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
elijahsj 1:8a094db1347f 617
elijahsj 1:8a094db1347f 618 #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
elijahsj 1:8a094db1347f 619 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
elijahsj 1:8a094db1347f 620
elijahsj 1:8a094db1347f 621 /* SCB Debug Fault Status Register Definitions */
elijahsj 1:8a094db1347f 622 #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
elijahsj 1:8a094db1347f 623 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
elijahsj 1:8a094db1347f 624
elijahsj 1:8a094db1347f 625 #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
elijahsj 1:8a094db1347f 626 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
elijahsj 1:8a094db1347f 627
elijahsj 1:8a094db1347f 628 #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
elijahsj 1:8a094db1347f 629 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
elijahsj 1:8a094db1347f 630
elijahsj 1:8a094db1347f 631 #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
elijahsj 1:8a094db1347f 632 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
elijahsj 1:8a094db1347f 633
elijahsj 1:8a094db1347f 634 #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
elijahsj 1:8a094db1347f 635 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
elijahsj 1:8a094db1347f 636
elijahsj 1:8a094db1347f 637 /*@} end of group CMSIS_SCB */
elijahsj 1:8a094db1347f 638
elijahsj 1:8a094db1347f 639
elijahsj 1:8a094db1347f 640 /**
elijahsj 1:8a094db1347f 641 \ingroup CMSIS_core_register
elijahsj 1:8a094db1347f 642 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
elijahsj 1:8a094db1347f 643 \brief Type definitions for the System Control and ID Register not in the SCB
elijahsj 1:8a094db1347f 644 @{
elijahsj 1:8a094db1347f 645 */
elijahsj 1:8a094db1347f 646
elijahsj 1:8a094db1347f 647 /**
elijahsj 1:8a094db1347f 648 \brief Structure type to access the System Control and ID Register not in the SCB.
elijahsj 1:8a094db1347f 649 */
elijahsj 1:8a094db1347f 650 typedef struct
elijahsj 1:8a094db1347f 651 {
elijahsj 1:8a094db1347f 652 uint32_t RESERVED0[1U];
elijahsj 1:8a094db1347f 653 __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
elijahsj 1:8a094db1347f 654 uint32_t RESERVED1[1U];
elijahsj 1:8a094db1347f 655 } SCnSCB_Type;
elijahsj 1:8a094db1347f 656
elijahsj 1:8a094db1347f 657 /* Interrupt Controller Type Register Definitions */
elijahsj 1:8a094db1347f 658 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
elijahsj 1:8a094db1347f 659 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
elijahsj 1:8a094db1347f 660
elijahsj 1:8a094db1347f 661 /*@} end of group CMSIS_SCnotSCB */
elijahsj 1:8a094db1347f 662
elijahsj 1:8a094db1347f 663
elijahsj 1:8a094db1347f 664 /**
elijahsj 1:8a094db1347f 665 \ingroup CMSIS_core_register
elijahsj 1:8a094db1347f 666 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
elijahsj 1:8a094db1347f 667 \brief Type definitions for the System Timer Registers.
elijahsj 1:8a094db1347f 668 @{
elijahsj 1:8a094db1347f 669 */
elijahsj 1:8a094db1347f 670
elijahsj 1:8a094db1347f 671 /**
elijahsj 1:8a094db1347f 672 \brief Structure type to access the System Timer (SysTick).
elijahsj 1:8a094db1347f 673 */
elijahsj 1:8a094db1347f 674 typedef struct
elijahsj 1:8a094db1347f 675 {
elijahsj 1:8a094db1347f 676 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
elijahsj 1:8a094db1347f 677 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
elijahsj 1:8a094db1347f 678 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
elijahsj 1:8a094db1347f 679 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
elijahsj 1:8a094db1347f 680 } SysTick_Type;
elijahsj 1:8a094db1347f 681
elijahsj 1:8a094db1347f 682 /* SysTick Control / Status Register Definitions */
elijahsj 1:8a094db1347f 683 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
elijahsj 1:8a094db1347f 684 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
elijahsj 1:8a094db1347f 685
elijahsj 1:8a094db1347f 686 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
elijahsj 1:8a094db1347f 687 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
elijahsj 1:8a094db1347f 688
elijahsj 1:8a094db1347f 689 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
elijahsj 1:8a094db1347f 690 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
elijahsj 1:8a094db1347f 691
elijahsj 1:8a094db1347f 692 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
elijahsj 1:8a094db1347f 693 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
elijahsj 1:8a094db1347f 694
elijahsj 1:8a094db1347f 695 /* SysTick Reload Register Definitions */
elijahsj 1:8a094db1347f 696 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
elijahsj 1:8a094db1347f 697 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
elijahsj 1:8a094db1347f 698
elijahsj 1:8a094db1347f 699 /* SysTick Current Register Definitions */
elijahsj 1:8a094db1347f 700 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
elijahsj 1:8a094db1347f 701 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
elijahsj 1:8a094db1347f 702
elijahsj 1:8a094db1347f 703 /* SysTick Calibration Register Definitions */
elijahsj 1:8a094db1347f 704 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
elijahsj 1:8a094db1347f 705 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
elijahsj 1:8a094db1347f 706
elijahsj 1:8a094db1347f 707 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
elijahsj 1:8a094db1347f 708 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
elijahsj 1:8a094db1347f 709
elijahsj 1:8a094db1347f 710 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
elijahsj 1:8a094db1347f 711 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
elijahsj 1:8a094db1347f 712
elijahsj 1:8a094db1347f 713 /*@} end of group CMSIS_SysTick */
elijahsj 1:8a094db1347f 714
elijahsj 1:8a094db1347f 715
elijahsj 1:8a094db1347f 716 /**
elijahsj 1:8a094db1347f 717 \ingroup CMSIS_core_register
elijahsj 1:8a094db1347f 718 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
elijahsj 1:8a094db1347f 719 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
elijahsj 1:8a094db1347f 720 @{
elijahsj 1:8a094db1347f 721 */
elijahsj 1:8a094db1347f 722
elijahsj 1:8a094db1347f 723 /**
elijahsj 1:8a094db1347f 724 \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
elijahsj 1:8a094db1347f 725 */
elijahsj 1:8a094db1347f 726 typedef struct
elijahsj 1:8a094db1347f 727 {
elijahsj 1:8a094db1347f 728 __OM union
elijahsj 1:8a094db1347f 729 {
elijahsj 1:8a094db1347f 730 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
elijahsj 1:8a094db1347f 731 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
elijahsj 1:8a094db1347f 732 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
elijahsj 1:8a094db1347f 733 } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
elijahsj 1:8a094db1347f 734 uint32_t RESERVED0[864U];
elijahsj 1:8a094db1347f 735 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
elijahsj 1:8a094db1347f 736 uint32_t RESERVED1[15U];
elijahsj 1:8a094db1347f 737 __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
elijahsj 1:8a094db1347f 738 uint32_t RESERVED2[15U];
elijahsj 1:8a094db1347f 739 __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
elijahsj 1:8a094db1347f 740 uint32_t RESERVED3[29U];
elijahsj 1:8a094db1347f 741 __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
elijahsj 1:8a094db1347f 742 __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
elijahsj 1:8a094db1347f 743 __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
elijahsj 1:8a094db1347f 744 uint32_t RESERVED4[43U];
elijahsj 1:8a094db1347f 745 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
elijahsj 1:8a094db1347f 746 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
elijahsj 1:8a094db1347f 747 uint32_t RESERVED5[6U];
elijahsj 1:8a094db1347f 748 __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
elijahsj 1:8a094db1347f 749 __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
elijahsj 1:8a094db1347f 750 __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
elijahsj 1:8a094db1347f 751 __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
elijahsj 1:8a094db1347f 752 __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
elijahsj 1:8a094db1347f 753 __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
elijahsj 1:8a094db1347f 754 __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
elijahsj 1:8a094db1347f 755 __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
elijahsj 1:8a094db1347f 756 __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
elijahsj 1:8a094db1347f 757 __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
elijahsj 1:8a094db1347f 758 __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
elijahsj 1:8a094db1347f 759 __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
elijahsj 1:8a094db1347f 760 } ITM_Type;
elijahsj 1:8a094db1347f 761
elijahsj 1:8a094db1347f 762 /* ITM Trace Privilege Register Definitions */
elijahsj 1:8a094db1347f 763 #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
elijahsj 1:8a094db1347f 764 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
elijahsj 1:8a094db1347f 765
elijahsj 1:8a094db1347f 766 /* ITM Trace Control Register Definitions */
elijahsj 1:8a094db1347f 767 #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
elijahsj 1:8a094db1347f 768 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
elijahsj 1:8a094db1347f 769
elijahsj 1:8a094db1347f 770 #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
elijahsj 1:8a094db1347f 771 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
elijahsj 1:8a094db1347f 772
elijahsj 1:8a094db1347f 773 #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
elijahsj 1:8a094db1347f 774 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
elijahsj 1:8a094db1347f 775
elijahsj 1:8a094db1347f 776 #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
elijahsj 1:8a094db1347f 777 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
elijahsj 1:8a094db1347f 778
elijahsj 1:8a094db1347f 779 #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
elijahsj 1:8a094db1347f 780 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
elijahsj 1:8a094db1347f 781
elijahsj 1:8a094db1347f 782 #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
elijahsj 1:8a094db1347f 783 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
elijahsj 1:8a094db1347f 784
elijahsj 1:8a094db1347f 785 #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
elijahsj 1:8a094db1347f 786 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
elijahsj 1:8a094db1347f 787
elijahsj 1:8a094db1347f 788 #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
elijahsj 1:8a094db1347f 789 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
elijahsj 1:8a094db1347f 790
elijahsj 1:8a094db1347f 791 #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
elijahsj 1:8a094db1347f 792 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
elijahsj 1:8a094db1347f 793
elijahsj 1:8a094db1347f 794 /* ITM Integration Write Register Definitions */
elijahsj 1:8a094db1347f 795 #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
elijahsj 1:8a094db1347f 796 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
elijahsj 1:8a094db1347f 797
elijahsj 1:8a094db1347f 798 /* ITM Integration Read Register Definitions */
elijahsj 1:8a094db1347f 799 #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
elijahsj 1:8a094db1347f 800 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
elijahsj 1:8a094db1347f 801
elijahsj 1:8a094db1347f 802 /* ITM Integration Mode Control Register Definitions */
elijahsj 1:8a094db1347f 803 #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
elijahsj 1:8a094db1347f 804 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
elijahsj 1:8a094db1347f 805
elijahsj 1:8a094db1347f 806 /* ITM Lock Status Register Definitions */
elijahsj 1:8a094db1347f 807 #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
elijahsj 1:8a094db1347f 808 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
elijahsj 1:8a094db1347f 809
elijahsj 1:8a094db1347f 810 #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
elijahsj 1:8a094db1347f 811 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
elijahsj 1:8a094db1347f 812
elijahsj 1:8a094db1347f 813 #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
elijahsj 1:8a094db1347f 814 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
elijahsj 1:8a094db1347f 815
elijahsj 1:8a094db1347f 816 /*@}*/ /* end of group CMSIS_ITM */
elijahsj 1:8a094db1347f 817
elijahsj 1:8a094db1347f 818
elijahsj 1:8a094db1347f 819 /**
elijahsj 1:8a094db1347f 820 \ingroup CMSIS_core_register
elijahsj 1:8a094db1347f 821 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
elijahsj 1:8a094db1347f 822 \brief Type definitions for the Data Watchpoint and Trace (DWT)
elijahsj 1:8a094db1347f 823 @{
elijahsj 1:8a094db1347f 824 */
elijahsj 1:8a094db1347f 825
elijahsj 1:8a094db1347f 826 /**
elijahsj 1:8a094db1347f 827 \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
elijahsj 1:8a094db1347f 828 */
elijahsj 1:8a094db1347f 829 typedef struct
elijahsj 1:8a094db1347f 830 {
elijahsj 1:8a094db1347f 831 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
elijahsj 1:8a094db1347f 832 __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
elijahsj 1:8a094db1347f 833 __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
elijahsj 1:8a094db1347f 834 __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
elijahsj 1:8a094db1347f 835 __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
elijahsj 1:8a094db1347f 836 __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
elijahsj 1:8a094db1347f 837 __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
elijahsj 1:8a094db1347f 838 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
elijahsj 1:8a094db1347f 839 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
elijahsj 1:8a094db1347f 840 __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
elijahsj 1:8a094db1347f 841 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
elijahsj 1:8a094db1347f 842 uint32_t RESERVED0[1U];
elijahsj 1:8a094db1347f 843 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
elijahsj 1:8a094db1347f 844 __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
elijahsj 1:8a094db1347f 845 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
elijahsj 1:8a094db1347f 846 uint32_t RESERVED1[1U];
elijahsj 1:8a094db1347f 847 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
elijahsj 1:8a094db1347f 848 __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
elijahsj 1:8a094db1347f 849 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
elijahsj 1:8a094db1347f 850 uint32_t RESERVED2[1U];
elijahsj 1:8a094db1347f 851 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
elijahsj 1:8a094db1347f 852 __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
elijahsj 1:8a094db1347f 853 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
elijahsj 1:8a094db1347f 854 } DWT_Type;
elijahsj 1:8a094db1347f 855
elijahsj 1:8a094db1347f 856 /* DWT Control Register Definitions */
elijahsj 1:8a094db1347f 857 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
elijahsj 1:8a094db1347f 858 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
elijahsj 1:8a094db1347f 859
elijahsj 1:8a094db1347f 860 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
elijahsj 1:8a094db1347f 861 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
elijahsj 1:8a094db1347f 862
elijahsj 1:8a094db1347f 863 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
elijahsj 1:8a094db1347f 864 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
elijahsj 1:8a094db1347f 865
elijahsj 1:8a094db1347f 866 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
elijahsj 1:8a094db1347f 867 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
elijahsj 1:8a094db1347f 868
elijahsj 1:8a094db1347f 869 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
elijahsj 1:8a094db1347f 870 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
elijahsj 1:8a094db1347f 871
elijahsj 1:8a094db1347f 872 #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
elijahsj 1:8a094db1347f 873 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
elijahsj 1:8a094db1347f 874
elijahsj 1:8a094db1347f 875 #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
elijahsj 1:8a094db1347f 876 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
elijahsj 1:8a094db1347f 877
elijahsj 1:8a094db1347f 878 #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
elijahsj 1:8a094db1347f 879 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
elijahsj 1:8a094db1347f 880
elijahsj 1:8a094db1347f 881 #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
elijahsj 1:8a094db1347f 882 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
elijahsj 1:8a094db1347f 883
elijahsj 1:8a094db1347f 884 #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
elijahsj 1:8a094db1347f 885 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
elijahsj 1:8a094db1347f 886
elijahsj 1:8a094db1347f 887 #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
elijahsj 1:8a094db1347f 888 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
elijahsj 1:8a094db1347f 889
elijahsj 1:8a094db1347f 890 #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
elijahsj 1:8a094db1347f 891 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
elijahsj 1:8a094db1347f 892
elijahsj 1:8a094db1347f 893 #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
elijahsj 1:8a094db1347f 894 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
elijahsj 1:8a094db1347f 895
elijahsj 1:8a094db1347f 896 #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
elijahsj 1:8a094db1347f 897 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
elijahsj 1:8a094db1347f 898
elijahsj 1:8a094db1347f 899 #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
elijahsj 1:8a094db1347f 900 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
elijahsj 1:8a094db1347f 901
elijahsj 1:8a094db1347f 902 #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
elijahsj 1:8a094db1347f 903 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
elijahsj 1:8a094db1347f 904
elijahsj 1:8a094db1347f 905 #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
elijahsj 1:8a094db1347f 906 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
elijahsj 1:8a094db1347f 907
elijahsj 1:8a094db1347f 908 #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
elijahsj 1:8a094db1347f 909 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
elijahsj 1:8a094db1347f 910
elijahsj 1:8a094db1347f 911 /* DWT CPI Count Register Definitions */
elijahsj 1:8a094db1347f 912 #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
elijahsj 1:8a094db1347f 913 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
elijahsj 1:8a094db1347f 914
elijahsj 1:8a094db1347f 915 /* DWT Exception Overhead Count Register Definitions */
elijahsj 1:8a094db1347f 916 #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
elijahsj 1:8a094db1347f 917 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
elijahsj 1:8a094db1347f 918
elijahsj 1:8a094db1347f 919 /* DWT Sleep Count Register Definitions */
elijahsj 1:8a094db1347f 920 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
elijahsj 1:8a094db1347f 921 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
elijahsj 1:8a094db1347f 922
elijahsj 1:8a094db1347f 923 /* DWT LSU Count Register Definitions */
elijahsj 1:8a094db1347f 924 #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
elijahsj 1:8a094db1347f 925 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
elijahsj 1:8a094db1347f 926
elijahsj 1:8a094db1347f 927 /* DWT Folded-instruction Count Register Definitions */
elijahsj 1:8a094db1347f 928 #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
elijahsj 1:8a094db1347f 929 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
elijahsj 1:8a094db1347f 930
elijahsj 1:8a094db1347f 931 /* DWT Comparator Mask Register Definitions */
elijahsj 1:8a094db1347f 932 #define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
elijahsj 1:8a094db1347f 933 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
elijahsj 1:8a094db1347f 934
elijahsj 1:8a094db1347f 935 /* DWT Comparator Function Register Definitions */
elijahsj 1:8a094db1347f 936 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
elijahsj 1:8a094db1347f 937 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
elijahsj 1:8a094db1347f 938
elijahsj 1:8a094db1347f 939 #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
elijahsj 1:8a094db1347f 940 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
elijahsj 1:8a094db1347f 941
elijahsj 1:8a094db1347f 942 #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
elijahsj 1:8a094db1347f 943 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
elijahsj 1:8a094db1347f 944
elijahsj 1:8a094db1347f 945 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
elijahsj 1:8a094db1347f 946 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
elijahsj 1:8a094db1347f 947
elijahsj 1:8a094db1347f 948 #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
elijahsj 1:8a094db1347f 949 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
elijahsj 1:8a094db1347f 950
elijahsj 1:8a094db1347f 951 #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
elijahsj 1:8a094db1347f 952 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
elijahsj 1:8a094db1347f 953
elijahsj 1:8a094db1347f 954 #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
elijahsj 1:8a094db1347f 955 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
elijahsj 1:8a094db1347f 956
elijahsj 1:8a094db1347f 957 #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
elijahsj 1:8a094db1347f 958 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
elijahsj 1:8a094db1347f 959
elijahsj 1:8a094db1347f 960 #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
elijahsj 1:8a094db1347f 961 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
elijahsj 1:8a094db1347f 962
elijahsj 1:8a094db1347f 963 /*@}*/ /* end of group CMSIS_DWT */
elijahsj 1:8a094db1347f 964
elijahsj 1:8a094db1347f 965
elijahsj 1:8a094db1347f 966 /**
elijahsj 1:8a094db1347f 967 \ingroup CMSIS_core_register
elijahsj 1:8a094db1347f 968 \defgroup CMSIS_TPI Trace Port Interface (TPI)
elijahsj 1:8a094db1347f 969 \brief Type definitions for the Trace Port Interface (TPI)
elijahsj 1:8a094db1347f 970 @{
elijahsj 1:8a094db1347f 971 */
elijahsj 1:8a094db1347f 972
elijahsj 1:8a094db1347f 973 /**
elijahsj 1:8a094db1347f 974 \brief Structure type to access the Trace Port Interface Register (TPI).
elijahsj 1:8a094db1347f 975 */
elijahsj 1:8a094db1347f 976 typedef struct
elijahsj 1:8a094db1347f 977 {
elijahsj 1:8a094db1347f 978 __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
elijahsj 1:8a094db1347f 979 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
elijahsj 1:8a094db1347f 980 uint32_t RESERVED0[2U];
elijahsj 1:8a094db1347f 981 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
elijahsj 1:8a094db1347f 982 uint32_t RESERVED1[55U];
elijahsj 1:8a094db1347f 983 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
elijahsj 1:8a094db1347f 984 uint32_t RESERVED2[131U];
elijahsj 1:8a094db1347f 985 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
elijahsj 1:8a094db1347f 986 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
elijahsj 1:8a094db1347f 987 __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
elijahsj 1:8a094db1347f 988 uint32_t RESERVED3[759U];
elijahsj 1:8a094db1347f 989 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
elijahsj 1:8a094db1347f 990 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
elijahsj 1:8a094db1347f 991 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
elijahsj 1:8a094db1347f 992 uint32_t RESERVED4[1U];
elijahsj 1:8a094db1347f 993 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
elijahsj 1:8a094db1347f 994 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
elijahsj 1:8a094db1347f 995 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
elijahsj 1:8a094db1347f 996 uint32_t RESERVED5[39U];
elijahsj 1:8a094db1347f 997 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
elijahsj 1:8a094db1347f 998 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
elijahsj 1:8a094db1347f 999 uint32_t RESERVED7[8U];
elijahsj 1:8a094db1347f 1000 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
elijahsj 1:8a094db1347f 1001 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
elijahsj 1:8a094db1347f 1002 } TPI_Type;
elijahsj 1:8a094db1347f 1003
elijahsj 1:8a094db1347f 1004 /* TPI Asynchronous Clock Prescaler Register Definitions */
elijahsj 1:8a094db1347f 1005 #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
elijahsj 1:8a094db1347f 1006 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
elijahsj 1:8a094db1347f 1007
elijahsj 1:8a094db1347f 1008 /* TPI Selected Pin Protocol Register Definitions */
elijahsj 1:8a094db1347f 1009 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
elijahsj 1:8a094db1347f 1010 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
elijahsj 1:8a094db1347f 1011
elijahsj 1:8a094db1347f 1012 /* TPI Formatter and Flush Status Register Definitions */
elijahsj 1:8a094db1347f 1013 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
elijahsj 1:8a094db1347f 1014 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
elijahsj 1:8a094db1347f 1015
elijahsj 1:8a094db1347f 1016 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
elijahsj 1:8a094db1347f 1017 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
elijahsj 1:8a094db1347f 1018
elijahsj 1:8a094db1347f 1019 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
elijahsj 1:8a094db1347f 1020 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
elijahsj 1:8a094db1347f 1021
elijahsj 1:8a094db1347f 1022 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
elijahsj 1:8a094db1347f 1023 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
elijahsj 1:8a094db1347f 1024
elijahsj 1:8a094db1347f 1025 /* TPI Formatter and Flush Control Register Definitions */
elijahsj 1:8a094db1347f 1026 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
elijahsj 1:8a094db1347f 1027 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
elijahsj 1:8a094db1347f 1028
elijahsj 1:8a094db1347f 1029 #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
elijahsj 1:8a094db1347f 1030 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
elijahsj 1:8a094db1347f 1031
elijahsj 1:8a094db1347f 1032 /* TPI TRIGGER Register Definitions */
elijahsj 1:8a094db1347f 1033 #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
elijahsj 1:8a094db1347f 1034 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
elijahsj 1:8a094db1347f 1035
elijahsj 1:8a094db1347f 1036 /* TPI Integration ETM Data Register Definitions (FIFO0) */
elijahsj 1:8a094db1347f 1037 #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
elijahsj 1:8a094db1347f 1038 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
elijahsj 1:8a094db1347f 1039
elijahsj 1:8a094db1347f 1040 #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
elijahsj 1:8a094db1347f 1041 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
elijahsj 1:8a094db1347f 1042
elijahsj 1:8a094db1347f 1043 #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
elijahsj 1:8a094db1347f 1044 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
elijahsj 1:8a094db1347f 1045
elijahsj 1:8a094db1347f 1046 #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
elijahsj 1:8a094db1347f 1047 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
elijahsj 1:8a094db1347f 1048
elijahsj 1:8a094db1347f 1049 #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
elijahsj 1:8a094db1347f 1050 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
elijahsj 1:8a094db1347f 1051
elijahsj 1:8a094db1347f 1052 #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
elijahsj 1:8a094db1347f 1053 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
elijahsj 1:8a094db1347f 1054
elijahsj 1:8a094db1347f 1055 #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
elijahsj 1:8a094db1347f 1056 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
elijahsj 1:8a094db1347f 1057
elijahsj 1:8a094db1347f 1058 /* TPI ITATBCTR2 Register Definitions */
elijahsj 1:8a094db1347f 1059 #define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
elijahsj 1:8a094db1347f 1060 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
elijahsj 1:8a094db1347f 1061
elijahsj 1:8a094db1347f 1062 /* TPI Integration ITM Data Register Definitions (FIFO1) */
elijahsj 1:8a094db1347f 1063 #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
elijahsj 1:8a094db1347f 1064 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
elijahsj 1:8a094db1347f 1065
elijahsj 1:8a094db1347f 1066 #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
elijahsj 1:8a094db1347f 1067 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
elijahsj 1:8a094db1347f 1068
elijahsj 1:8a094db1347f 1069 #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
elijahsj 1:8a094db1347f 1070 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
elijahsj 1:8a094db1347f 1071
elijahsj 1:8a094db1347f 1072 #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
elijahsj 1:8a094db1347f 1073 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
elijahsj 1:8a094db1347f 1074
elijahsj 1:8a094db1347f 1075 #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
elijahsj 1:8a094db1347f 1076 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
elijahsj 1:8a094db1347f 1077
elijahsj 1:8a094db1347f 1078 #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
elijahsj 1:8a094db1347f 1079 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
elijahsj 1:8a094db1347f 1080
elijahsj 1:8a094db1347f 1081 #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
elijahsj 1:8a094db1347f 1082 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
elijahsj 1:8a094db1347f 1083
elijahsj 1:8a094db1347f 1084 /* TPI ITATBCTR0 Register Definitions */
elijahsj 1:8a094db1347f 1085 #define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
elijahsj 1:8a094db1347f 1086 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
elijahsj 1:8a094db1347f 1087
elijahsj 1:8a094db1347f 1088 /* TPI Integration Mode Control Register Definitions */
elijahsj 1:8a094db1347f 1089 #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
elijahsj 1:8a094db1347f 1090 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
elijahsj 1:8a094db1347f 1091
elijahsj 1:8a094db1347f 1092 /* TPI DEVID Register Definitions */
elijahsj 1:8a094db1347f 1093 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
elijahsj 1:8a094db1347f 1094 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
elijahsj 1:8a094db1347f 1095
elijahsj 1:8a094db1347f 1096 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
elijahsj 1:8a094db1347f 1097 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
elijahsj 1:8a094db1347f 1098
elijahsj 1:8a094db1347f 1099 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
elijahsj 1:8a094db1347f 1100 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
elijahsj 1:8a094db1347f 1101
elijahsj 1:8a094db1347f 1102 #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
elijahsj 1:8a094db1347f 1103 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
elijahsj 1:8a094db1347f 1104
elijahsj 1:8a094db1347f 1105 #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
elijahsj 1:8a094db1347f 1106 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
elijahsj 1:8a094db1347f 1107
elijahsj 1:8a094db1347f 1108 #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
elijahsj 1:8a094db1347f 1109 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
elijahsj 1:8a094db1347f 1110
elijahsj 1:8a094db1347f 1111 /* TPI DEVTYPE Register Definitions */
elijahsj 1:8a094db1347f 1112 #define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
elijahsj 1:8a094db1347f 1113 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
elijahsj 1:8a094db1347f 1114
elijahsj 1:8a094db1347f 1115 #define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
elijahsj 1:8a094db1347f 1116 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
elijahsj 1:8a094db1347f 1117
elijahsj 1:8a094db1347f 1118 /*@}*/ /* end of group CMSIS_TPI */
elijahsj 1:8a094db1347f 1119
elijahsj 1:8a094db1347f 1120
elijahsj 1:8a094db1347f 1121 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
elijahsj 1:8a094db1347f 1122 /**
elijahsj 1:8a094db1347f 1123 \ingroup CMSIS_core_register
elijahsj 1:8a094db1347f 1124 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
elijahsj 1:8a094db1347f 1125 \brief Type definitions for the Memory Protection Unit (MPU)
elijahsj 1:8a094db1347f 1126 @{
elijahsj 1:8a094db1347f 1127 */
elijahsj 1:8a094db1347f 1128
elijahsj 1:8a094db1347f 1129 /**
elijahsj 1:8a094db1347f 1130 \brief Structure type to access the Memory Protection Unit (MPU).
elijahsj 1:8a094db1347f 1131 */
elijahsj 1:8a094db1347f 1132 typedef struct
elijahsj 1:8a094db1347f 1133 {
elijahsj 1:8a094db1347f 1134 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
elijahsj 1:8a094db1347f 1135 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
elijahsj 1:8a094db1347f 1136 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
elijahsj 1:8a094db1347f 1137 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
elijahsj 1:8a094db1347f 1138 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
elijahsj 1:8a094db1347f 1139 __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
elijahsj 1:8a094db1347f 1140 __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
elijahsj 1:8a094db1347f 1141 __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
elijahsj 1:8a094db1347f 1142 __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
elijahsj 1:8a094db1347f 1143 __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
elijahsj 1:8a094db1347f 1144 __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
elijahsj 1:8a094db1347f 1145 } MPU_Type;
elijahsj 1:8a094db1347f 1146
elijahsj 1:8a094db1347f 1147 /* MPU Type Register Definitions */
elijahsj 1:8a094db1347f 1148 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
elijahsj 1:8a094db1347f 1149 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
elijahsj 1:8a094db1347f 1150
elijahsj 1:8a094db1347f 1151 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
elijahsj 1:8a094db1347f 1152 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
elijahsj 1:8a094db1347f 1153
elijahsj 1:8a094db1347f 1154 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
elijahsj 1:8a094db1347f 1155 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
elijahsj 1:8a094db1347f 1156
elijahsj 1:8a094db1347f 1157 /* MPU Control Register Definitions */
elijahsj 1:8a094db1347f 1158 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
elijahsj 1:8a094db1347f 1159 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
elijahsj 1:8a094db1347f 1160
elijahsj 1:8a094db1347f 1161 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
elijahsj 1:8a094db1347f 1162 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
elijahsj 1:8a094db1347f 1163
elijahsj 1:8a094db1347f 1164 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
elijahsj 1:8a094db1347f 1165 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
elijahsj 1:8a094db1347f 1166
elijahsj 1:8a094db1347f 1167 /* MPU Region Number Register Definitions */
elijahsj 1:8a094db1347f 1168 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
elijahsj 1:8a094db1347f 1169 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
elijahsj 1:8a094db1347f 1170
elijahsj 1:8a094db1347f 1171 /* MPU Region Base Address Register Definitions */
elijahsj 1:8a094db1347f 1172 #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
elijahsj 1:8a094db1347f 1173 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
elijahsj 1:8a094db1347f 1174
elijahsj 1:8a094db1347f 1175 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
elijahsj 1:8a094db1347f 1176 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
elijahsj 1:8a094db1347f 1177
elijahsj 1:8a094db1347f 1178 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
elijahsj 1:8a094db1347f 1179 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
elijahsj 1:8a094db1347f 1180
elijahsj 1:8a094db1347f 1181 /* MPU Region Attribute and Size Register Definitions */
elijahsj 1:8a094db1347f 1182 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
elijahsj 1:8a094db1347f 1183 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
elijahsj 1:8a094db1347f 1184
elijahsj 1:8a094db1347f 1185 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
elijahsj 1:8a094db1347f 1186 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
elijahsj 1:8a094db1347f 1187
elijahsj 1:8a094db1347f 1188 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
elijahsj 1:8a094db1347f 1189 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
elijahsj 1:8a094db1347f 1190
elijahsj 1:8a094db1347f 1191 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
elijahsj 1:8a094db1347f 1192 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
elijahsj 1:8a094db1347f 1193
elijahsj 1:8a094db1347f 1194 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
elijahsj 1:8a094db1347f 1195 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
elijahsj 1:8a094db1347f 1196
elijahsj 1:8a094db1347f 1197 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
elijahsj 1:8a094db1347f 1198 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
elijahsj 1:8a094db1347f 1199
elijahsj 1:8a094db1347f 1200 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
elijahsj 1:8a094db1347f 1201 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
elijahsj 1:8a094db1347f 1202
elijahsj 1:8a094db1347f 1203 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
elijahsj 1:8a094db1347f 1204 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
elijahsj 1:8a094db1347f 1205
elijahsj 1:8a094db1347f 1206 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
elijahsj 1:8a094db1347f 1207 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
elijahsj 1:8a094db1347f 1208
elijahsj 1:8a094db1347f 1209 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
elijahsj 1:8a094db1347f 1210 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
elijahsj 1:8a094db1347f 1211
elijahsj 1:8a094db1347f 1212 /*@} end of group CMSIS_MPU */
elijahsj 1:8a094db1347f 1213 #endif
elijahsj 1:8a094db1347f 1214
elijahsj 1:8a094db1347f 1215
elijahsj 1:8a094db1347f 1216 /**
elijahsj 1:8a094db1347f 1217 \ingroup CMSIS_core_register
elijahsj 1:8a094db1347f 1218 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
elijahsj 1:8a094db1347f 1219 \brief Type definitions for the Core Debug Registers
elijahsj 1:8a094db1347f 1220 @{
elijahsj 1:8a094db1347f 1221 */
elijahsj 1:8a094db1347f 1222
elijahsj 1:8a094db1347f 1223 /**
elijahsj 1:8a094db1347f 1224 \brief Structure type to access the Core Debug Register (CoreDebug).
elijahsj 1:8a094db1347f 1225 */
elijahsj 1:8a094db1347f 1226 typedef struct
elijahsj 1:8a094db1347f 1227 {
elijahsj 1:8a094db1347f 1228 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
elijahsj 1:8a094db1347f 1229 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
elijahsj 1:8a094db1347f 1230 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
elijahsj 1:8a094db1347f 1231 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
elijahsj 1:8a094db1347f 1232 } CoreDebug_Type;
elijahsj 1:8a094db1347f 1233
elijahsj 1:8a094db1347f 1234 /* Debug Halting Control and Status Register Definitions */
elijahsj 1:8a094db1347f 1235 #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
elijahsj 1:8a094db1347f 1236 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
elijahsj 1:8a094db1347f 1237
elijahsj 1:8a094db1347f 1238 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
elijahsj 1:8a094db1347f 1239 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
elijahsj 1:8a094db1347f 1240
elijahsj 1:8a094db1347f 1241 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
elijahsj 1:8a094db1347f 1242 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
elijahsj 1:8a094db1347f 1243
elijahsj 1:8a094db1347f 1244 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
elijahsj 1:8a094db1347f 1245 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
elijahsj 1:8a094db1347f 1246
elijahsj 1:8a094db1347f 1247 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
elijahsj 1:8a094db1347f 1248 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
elijahsj 1:8a094db1347f 1249
elijahsj 1:8a094db1347f 1250 #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
elijahsj 1:8a094db1347f 1251 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
elijahsj 1:8a094db1347f 1252
elijahsj 1:8a094db1347f 1253 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
elijahsj 1:8a094db1347f 1254 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
elijahsj 1:8a094db1347f 1255
elijahsj 1:8a094db1347f 1256 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
elijahsj 1:8a094db1347f 1257 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
elijahsj 1:8a094db1347f 1258
elijahsj 1:8a094db1347f 1259 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
elijahsj 1:8a094db1347f 1260 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
elijahsj 1:8a094db1347f 1261
elijahsj 1:8a094db1347f 1262 #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
elijahsj 1:8a094db1347f 1263 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
elijahsj 1:8a094db1347f 1264
elijahsj 1:8a094db1347f 1265 #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
elijahsj 1:8a094db1347f 1266 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
elijahsj 1:8a094db1347f 1267
elijahsj 1:8a094db1347f 1268 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
elijahsj 1:8a094db1347f 1269 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
elijahsj 1:8a094db1347f 1270
elijahsj 1:8a094db1347f 1271 /* Debug Core Register Selector Register Definitions */
elijahsj 1:8a094db1347f 1272 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
elijahsj 1:8a094db1347f 1273 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
elijahsj 1:8a094db1347f 1274
elijahsj 1:8a094db1347f 1275 #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
elijahsj 1:8a094db1347f 1276 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
elijahsj 1:8a094db1347f 1277
elijahsj 1:8a094db1347f 1278 /* Debug Exception and Monitor Control Register Definitions */
elijahsj 1:8a094db1347f 1279 #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
elijahsj 1:8a094db1347f 1280 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
elijahsj 1:8a094db1347f 1281
elijahsj 1:8a094db1347f 1282 #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
elijahsj 1:8a094db1347f 1283 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
elijahsj 1:8a094db1347f 1284
elijahsj 1:8a094db1347f 1285 #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
elijahsj 1:8a094db1347f 1286 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
elijahsj 1:8a094db1347f 1287
elijahsj 1:8a094db1347f 1288 #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
elijahsj 1:8a094db1347f 1289 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
elijahsj 1:8a094db1347f 1290
elijahsj 1:8a094db1347f 1291 #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
elijahsj 1:8a094db1347f 1292 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
elijahsj 1:8a094db1347f 1293
elijahsj 1:8a094db1347f 1294 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
elijahsj 1:8a094db1347f 1295 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
elijahsj 1:8a094db1347f 1296
elijahsj 1:8a094db1347f 1297 #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
elijahsj 1:8a094db1347f 1298 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
elijahsj 1:8a094db1347f 1299
elijahsj 1:8a094db1347f 1300 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
elijahsj 1:8a094db1347f 1301 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
elijahsj 1:8a094db1347f 1302
elijahsj 1:8a094db1347f 1303 #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
elijahsj 1:8a094db1347f 1304 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
elijahsj 1:8a094db1347f 1305
elijahsj 1:8a094db1347f 1306 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
elijahsj 1:8a094db1347f 1307 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
elijahsj 1:8a094db1347f 1308
elijahsj 1:8a094db1347f 1309 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
elijahsj 1:8a094db1347f 1310 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
elijahsj 1:8a094db1347f 1311
elijahsj 1:8a094db1347f 1312 #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
elijahsj 1:8a094db1347f 1313 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
elijahsj 1:8a094db1347f 1314
elijahsj 1:8a094db1347f 1315 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
elijahsj 1:8a094db1347f 1316 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
elijahsj 1:8a094db1347f 1317
elijahsj 1:8a094db1347f 1318 /*@} end of group CMSIS_CoreDebug */
elijahsj 1:8a094db1347f 1319
elijahsj 1:8a094db1347f 1320
elijahsj 1:8a094db1347f 1321 /**
elijahsj 1:8a094db1347f 1322 \ingroup CMSIS_core_register
elijahsj 1:8a094db1347f 1323 \defgroup CMSIS_core_bitfield Core register bit field macros
elijahsj 1:8a094db1347f 1324 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
elijahsj 1:8a094db1347f 1325 @{
elijahsj 1:8a094db1347f 1326 */
elijahsj 1:8a094db1347f 1327
elijahsj 1:8a094db1347f 1328 /**
elijahsj 1:8a094db1347f 1329 \brief Mask and shift a bit field value for use in a register bit range.
elijahsj 1:8a094db1347f 1330 \param[in] field Name of the register bit field.
elijahsj 1:8a094db1347f 1331 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
elijahsj 1:8a094db1347f 1332 \return Masked and shifted value.
elijahsj 1:8a094db1347f 1333 */
elijahsj 1:8a094db1347f 1334 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
elijahsj 1:8a094db1347f 1335
elijahsj 1:8a094db1347f 1336 /**
elijahsj 1:8a094db1347f 1337 \brief Mask and shift a register value to extract a bit filed value.
elijahsj 1:8a094db1347f 1338 \param[in] field Name of the register bit field.
elijahsj 1:8a094db1347f 1339 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
elijahsj 1:8a094db1347f 1340 \return Masked and shifted bit field value.
elijahsj 1:8a094db1347f 1341 */
elijahsj 1:8a094db1347f 1342 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
elijahsj 1:8a094db1347f 1343
elijahsj 1:8a094db1347f 1344 /*@} end of group CMSIS_core_bitfield */
elijahsj 1:8a094db1347f 1345
elijahsj 1:8a094db1347f 1346
elijahsj 1:8a094db1347f 1347 /**
elijahsj 1:8a094db1347f 1348 \ingroup CMSIS_core_register
elijahsj 1:8a094db1347f 1349 \defgroup CMSIS_core_base Core Definitions
elijahsj 1:8a094db1347f 1350 \brief Definitions for base addresses, unions, and structures.
elijahsj 1:8a094db1347f 1351 @{
elijahsj 1:8a094db1347f 1352 */
elijahsj 1:8a094db1347f 1353
elijahsj 1:8a094db1347f 1354 /* Memory mapping of Core Hardware */
elijahsj 1:8a094db1347f 1355 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
elijahsj 1:8a094db1347f 1356 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
elijahsj 1:8a094db1347f 1357 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
elijahsj 1:8a094db1347f 1358 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
elijahsj 1:8a094db1347f 1359 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
elijahsj 1:8a094db1347f 1360 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
elijahsj 1:8a094db1347f 1361 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
elijahsj 1:8a094db1347f 1362 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
elijahsj 1:8a094db1347f 1363
elijahsj 1:8a094db1347f 1364 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
elijahsj 1:8a094db1347f 1365 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
elijahsj 1:8a094db1347f 1366 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
elijahsj 1:8a094db1347f 1367 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
elijahsj 1:8a094db1347f 1368 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
elijahsj 1:8a094db1347f 1369 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
elijahsj 1:8a094db1347f 1370 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
elijahsj 1:8a094db1347f 1371 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
elijahsj 1:8a094db1347f 1372
elijahsj 1:8a094db1347f 1373 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
elijahsj 1:8a094db1347f 1374 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
elijahsj 1:8a094db1347f 1375 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
elijahsj 1:8a094db1347f 1376 #endif
elijahsj 1:8a094db1347f 1377
elijahsj 1:8a094db1347f 1378 /*@} */
elijahsj 1:8a094db1347f 1379
elijahsj 1:8a094db1347f 1380
elijahsj 1:8a094db1347f 1381
elijahsj 1:8a094db1347f 1382 /*******************************************************************************
elijahsj 1:8a094db1347f 1383 * Hardware Abstraction Layer
elijahsj 1:8a094db1347f 1384 Core Function Interface contains:
elijahsj 1:8a094db1347f 1385 - Core NVIC Functions
elijahsj 1:8a094db1347f 1386 - Core SysTick Functions
elijahsj 1:8a094db1347f 1387 - Core Debug Functions
elijahsj 1:8a094db1347f 1388 - Core Register Access Functions
elijahsj 1:8a094db1347f 1389 ******************************************************************************/
elijahsj 1:8a094db1347f 1390 /**
elijahsj 1:8a094db1347f 1391 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
elijahsj 1:8a094db1347f 1392 */
elijahsj 1:8a094db1347f 1393
elijahsj 1:8a094db1347f 1394
elijahsj 1:8a094db1347f 1395
elijahsj 1:8a094db1347f 1396 /* ########################## NVIC functions #################################### */
elijahsj 1:8a094db1347f 1397 /**
elijahsj 1:8a094db1347f 1398 \ingroup CMSIS_Core_FunctionInterface
elijahsj 1:8a094db1347f 1399 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
elijahsj 1:8a094db1347f 1400 \brief Functions that manage interrupts and exceptions via the NVIC.
elijahsj 1:8a094db1347f 1401 @{
elijahsj 1:8a094db1347f 1402 */
elijahsj 1:8a094db1347f 1403
elijahsj 1:8a094db1347f 1404 #ifdef CMSIS_NVIC_VIRTUAL
elijahsj 1:8a094db1347f 1405 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
elijahsj 1:8a094db1347f 1406 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
elijahsj 1:8a094db1347f 1407 #endif
elijahsj 1:8a094db1347f 1408 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
elijahsj 1:8a094db1347f 1409 #else
elijahsj 1:8a094db1347f 1410 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
elijahsj 1:8a094db1347f 1411 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
elijahsj 1:8a094db1347f 1412 #define NVIC_EnableIRQ __NVIC_EnableIRQ
elijahsj 1:8a094db1347f 1413 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
elijahsj 1:8a094db1347f 1414 #define NVIC_DisableIRQ __NVIC_DisableIRQ
elijahsj 1:8a094db1347f 1415 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
elijahsj 1:8a094db1347f 1416 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
elijahsj 1:8a094db1347f 1417 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
elijahsj 1:8a094db1347f 1418 #define NVIC_GetActive __NVIC_GetActive
elijahsj 1:8a094db1347f 1419 #define NVIC_SetPriority __NVIC_SetPriority
elijahsj 1:8a094db1347f 1420 #define NVIC_GetPriority __NVIC_GetPriority
elijahsj 1:8a094db1347f 1421 #define NVIC_SystemReset __NVIC_SystemReset
elijahsj 1:8a094db1347f 1422 #endif /* CMSIS_NVIC_VIRTUAL */
elijahsj 1:8a094db1347f 1423
elijahsj 1:8a094db1347f 1424 #ifdef CMSIS_VECTAB_VIRTUAL
elijahsj 1:8a094db1347f 1425 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
elijahsj 1:8a094db1347f 1426 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
elijahsj 1:8a094db1347f 1427 #endif
elijahsj 1:8a094db1347f 1428 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
elijahsj 1:8a094db1347f 1429 #else
elijahsj 1:8a094db1347f 1430 #define NVIC_SetVector __NVIC_SetVector
elijahsj 1:8a094db1347f 1431 #define NVIC_GetVector __NVIC_GetVector
elijahsj 1:8a094db1347f 1432 #endif /* (CMSIS_VECTAB_VIRTUAL) */
elijahsj 1:8a094db1347f 1433
elijahsj 1:8a094db1347f 1434 #define NVIC_USER_IRQ_OFFSET 16
elijahsj 1:8a094db1347f 1435
elijahsj 1:8a094db1347f 1436
elijahsj 1:8a094db1347f 1437
elijahsj 1:8a094db1347f 1438 /**
elijahsj 1:8a094db1347f 1439 \brief Set Priority Grouping
elijahsj 1:8a094db1347f 1440 \details Sets the priority grouping field using the required unlock sequence.
elijahsj 1:8a094db1347f 1441 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
elijahsj 1:8a094db1347f 1442 Only values from 0..7 are used.
elijahsj 1:8a094db1347f 1443 In case of a conflict between priority grouping and available
elijahsj 1:8a094db1347f 1444 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
elijahsj 1:8a094db1347f 1445 \param [in] PriorityGroup Priority grouping field.
elijahsj 1:8a094db1347f 1446 */
elijahsj 1:8a094db1347f 1447 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
elijahsj 1:8a094db1347f 1448 {
elijahsj 1:8a094db1347f 1449 uint32_t reg_value;
elijahsj 1:8a094db1347f 1450 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
elijahsj 1:8a094db1347f 1451
elijahsj 1:8a094db1347f 1452 reg_value = SCB->AIRCR; /* read old register configuration */
elijahsj 1:8a094db1347f 1453 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
elijahsj 1:8a094db1347f 1454 reg_value = (reg_value |
elijahsj 1:8a094db1347f 1455 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
elijahsj 1:8a094db1347f 1456 (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
elijahsj 1:8a094db1347f 1457 SCB->AIRCR = reg_value;
elijahsj 1:8a094db1347f 1458 }
elijahsj 1:8a094db1347f 1459
elijahsj 1:8a094db1347f 1460
elijahsj 1:8a094db1347f 1461 /**
elijahsj 1:8a094db1347f 1462 \brief Get Priority Grouping
elijahsj 1:8a094db1347f 1463 \details Reads the priority grouping field from the NVIC Interrupt Controller.
elijahsj 1:8a094db1347f 1464 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
elijahsj 1:8a094db1347f 1465 */
elijahsj 1:8a094db1347f 1466 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
elijahsj 1:8a094db1347f 1467 {
elijahsj 1:8a094db1347f 1468 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
elijahsj 1:8a094db1347f 1469 }
elijahsj 1:8a094db1347f 1470
elijahsj 1:8a094db1347f 1471
elijahsj 1:8a094db1347f 1472 /**
elijahsj 1:8a094db1347f 1473 \brief Enable Interrupt
elijahsj 1:8a094db1347f 1474 \details Enables a device specific interrupt in the NVIC interrupt controller.
elijahsj 1:8a094db1347f 1475 \param [in] IRQn Device specific interrupt number.
elijahsj 1:8a094db1347f 1476 \note IRQn must not be negative.
elijahsj 1:8a094db1347f 1477 */
elijahsj 1:8a094db1347f 1478 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
elijahsj 1:8a094db1347f 1479 {
elijahsj 1:8a094db1347f 1480 if ((int32_t)(IRQn) >= 0)
elijahsj 1:8a094db1347f 1481 {
elijahsj 1:8a094db1347f 1482 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
elijahsj 1:8a094db1347f 1483 }
elijahsj 1:8a094db1347f 1484 }
elijahsj 1:8a094db1347f 1485
elijahsj 1:8a094db1347f 1486
elijahsj 1:8a094db1347f 1487 /**
elijahsj 1:8a094db1347f 1488 \brief Get Interrupt Enable status
elijahsj 1:8a094db1347f 1489 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
elijahsj 1:8a094db1347f 1490 \param [in] IRQn Device specific interrupt number.
elijahsj 1:8a094db1347f 1491 \return 0 Interrupt is not enabled.
elijahsj 1:8a094db1347f 1492 \return 1 Interrupt is enabled.
elijahsj 1:8a094db1347f 1493 \note IRQn must not be negative.
elijahsj 1:8a094db1347f 1494 */
elijahsj 1:8a094db1347f 1495 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
elijahsj 1:8a094db1347f 1496 {
elijahsj 1:8a094db1347f 1497 if ((int32_t)(IRQn) >= 0)
elijahsj 1:8a094db1347f 1498 {
elijahsj 1:8a094db1347f 1499 return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
elijahsj 1:8a094db1347f 1500 }
elijahsj 1:8a094db1347f 1501 else
elijahsj 1:8a094db1347f 1502 {
elijahsj 1:8a094db1347f 1503 return(0U);
elijahsj 1:8a094db1347f 1504 }
elijahsj 1:8a094db1347f 1505 }
elijahsj 1:8a094db1347f 1506
elijahsj 1:8a094db1347f 1507
elijahsj 1:8a094db1347f 1508 /**
elijahsj 1:8a094db1347f 1509 \brief Disable Interrupt
elijahsj 1:8a094db1347f 1510 \details Disables a device specific interrupt in the NVIC interrupt controller.
elijahsj 1:8a094db1347f 1511 \param [in] IRQn Device specific interrupt number.
elijahsj 1:8a094db1347f 1512 \note IRQn must not be negative.
elijahsj 1:8a094db1347f 1513 */
elijahsj 1:8a094db1347f 1514 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
elijahsj 1:8a094db1347f 1515 {
elijahsj 1:8a094db1347f 1516 if ((int32_t)(IRQn) >= 0)
elijahsj 1:8a094db1347f 1517 {
elijahsj 1:8a094db1347f 1518 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
elijahsj 1:8a094db1347f 1519 __DSB();
elijahsj 1:8a094db1347f 1520 __ISB();
elijahsj 1:8a094db1347f 1521 }
elijahsj 1:8a094db1347f 1522 }
elijahsj 1:8a094db1347f 1523
elijahsj 1:8a094db1347f 1524
elijahsj 1:8a094db1347f 1525 /**
elijahsj 1:8a094db1347f 1526 \brief Get Pending Interrupt
elijahsj 1:8a094db1347f 1527 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
elijahsj 1:8a094db1347f 1528 \param [in] IRQn Device specific interrupt number.
elijahsj 1:8a094db1347f 1529 \return 0 Interrupt status is not pending.
elijahsj 1:8a094db1347f 1530 \return 1 Interrupt status is pending.
elijahsj 1:8a094db1347f 1531 \note IRQn must not be negative.
elijahsj 1:8a094db1347f 1532 */
elijahsj 1:8a094db1347f 1533 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
elijahsj 1:8a094db1347f 1534 {
elijahsj 1:8a094db1347f 1535 if ((int32_t)(IRQn) >= 0)
elijahsj 1:8a094db1347f 1536 {
elijahsj 1:8a094db1347f 1537 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
elijahsj 1:8a094db1347f 1538 }
elijahsj 1:8a094db1347f 1539 else
elijahsj 1:8a094db1347f 1540 {
elijahsj 1:8a094db1347f 1541 return(0U);
elijahsj 1:8a094db1347f 1542 }
elijahsj 1:8a094db1347f 1543 }
elijahsj 1:8a094db1347f 1544
elijahsj 1:8a094db1347f 1545
elijahsj 1:8a094db1347f 1546 /**
elijahsj 1:8a094db1347f 1547 \brief Set Pending Interrupt
elijahsj 1:8a094db1347f 1548 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
elijahsj 1:8a094db1347f 1549 \param [in] IRQn Device specific interrupt number.
elijahsj 1:8a094db1347f 1550 \note IRQn must not be negative.
elijahsj 1:8a094db1347f 1551 */
elijahsj 1:8a094db1347f 1552 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
elijahsj 1:8a094db1347f 1553 {
elijahsj 1:8a094db1347f 1554 if ((int32_t)(IRQn) >= 0)
elijahsj 1:8a094db1347f 1555 {
elijahsj 1:8a094db1347f 1556 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
elijahsj 1:8a094db1347f 1557 }
elijahsj 1:8a094db1347f 1558 }
elijahsj 1:8a094db1347f 1559
elijahsj 1:8a094db1347f 1560
elijahsj 1:8a094db1347f 1561 /**
elijahsj 1:8a094db1347f 1562 \brief Clear Pending Interrupt
elijahsj 1:8a094db1347f 1563 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
elijahsj 1:8a094db1347f 1564 \param [in] IRQn Device specific interrupt number.
elijahsj 1:8a094db1347f 1565 \note IRQn must not be negative.
elijahsj 1:8a094db1347f 1566 */
elijahsj 1:8a094db1347f 1567 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
elijahsj 1:8a094db1347f 1568 {
elijahsj 1:8a094db1347f 1569 if ((int32_t)(IRQn) >= 0)
elijahsj 1:8a094db1347f 1570 {
elijahsj 1:8a094db1347f 1571 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
elijahsj 1:8a094db1347f 1572 }
elijahsj 1:8a094db1347f 1573 }
elijahsj 1:8a094db1347f 1574
elijahsj 1:8a094db1347f 1575
elijahsj 1:8a094db1347f 1576 /**
elijahsj 1:8a094db1347f 1577 \brief Get Active Interrupt
elijahsj 1:8a094db1347f 1578 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
elijahsj 1:8a094db1347f 1579 \param [in] IRQn Device specific interrupt number.
elijahsj 1:8a094db1347f 1580 \return 0 Interrupt status is not active.
elijahsj 1:8a094db1347f 1581 \return 1 Interrupt status is active.
elijahsj 1:8a094db1347f 1582 \note IRQn must not be negative.
elijahsj 1:8a094db1347f 1583 */
elijahsj 1:8a094db1347f 1584 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
elijahsj 1:8a094db1347f 1585 {
elijahsj 1:8a094db1347f 1586 if ((int32_t)(IRQn) >= 0)
elijahsj 1:8a094db1347f 1587 {
elijahsj 1:8a094db1347f 1588 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
elijahsj 1:8a094db1347f 1589 }
elijahsj 1:8a094db1347f 1590 else
elijahsj 1:8a094db1347f 1591 {
elijahsj 1:8a094db1347f 1592 return(0U);
elijahsj 1:8a094db1347f 1593 }
elijahsj 1:8a094db1347f 1594 }
elijahsj 1:8a094db1347f 1595
elijahsj 1:8a094db1347f 1596
elijahsj 1:8a094db1347f 1597 /**
elijahsj 1:8a094db1347f 1598 \brief Set Interrupt Priority
elijahsj 1:8a094db1347f 1599 \details Sets the priority of a device specific interrupt or a processor exception.
elijahsj 1:8a094db1347f 1600 The interrupt number can be positive to specify a device specific interrupt,
elijahsj 1:8a094db1347f 1601 or negative to specify a processor exception.
elijahsj 1:8a094db1347f 1602 \param [in] IRQn Interrupt number.
elijahsj 1:8a094db1347f 1603 \param [in] priority Priority to set.
elijahsj 1:8a094db1347f 1604 \note The priority cannot be set for every processor exception.
elijahsj 1:8a094db1347f 1605 */
elijahsj 1:8a094db1347f 1606 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
elijahsj 1:8a094db1347f 1607 {
elijahsj 1:8a094db1347f 1608 if ((int32_t)(IRQn) >= 0)
elijahsj 1:8a094db1347f 1609 {
elijahsj 1:8a094db1347f 1610 NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
elijahsj 1:8a094db1347f 1611 }
elijahsj 1:8a094db1347f 1612 else
elijahsj 1:8a094db1347f 1613 {
elijahsj 1:8a094db1347f 1614 SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
elijahsj 1:8a094db1347f 1615 }
elijahsj 1:8a094db1347f 1616 }
elijahsj 1:8a094db1347f 1617
elijahsj 1:8a094db1347f 1618
elijahsj 1:8a094db1347f 1619 /**
elijahsj 1:8a094db1347f 1620 \brief Get Interrupt Priority
elijahsj 1:8a094db1347f 1621 \details Reads the priority of a device specific interrupt or a processor exception.
elijahsj 1:8a094db1347f 1622 The interrupt number can be positive to specify a device specific interrupt,
elijahsj 1:8a094db1347f 1623 or negative to specify a processor exception.
elijahsj 1:8a094db1347f 1624 \param [in] IRQn Interrupt number.
elijahsj 1:8a094db1347f 1625 \return Interrupt Priority.
elijahsj 1:8a094db1347f 1626 Value is aligned automatically to the implemented priority bits of the microcontroller.
elijahsj 1:8a094db1347f 1627 */
elijahsj 1:8a094db1347f 1628 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
elijahsj 1:8a094db1347f 1629 {
elijahsj 1:8a094db1347f 1630
elijahsj 1:8a094db1347f 1631 if ((int32_t)(IRQn) >= 0)
elijahsj 1:8a094db1347f 1632 {
elijahsj 1:8a094db1347f 1633 return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
elijahsj 1:8a094db1347f 1634 }
elijahsj 1:8a094db1347f 1635 else
elijahsj 1:8a094db1347f 1636 {
elijahsj 1:8a094db1347f 1637 return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
elijahsj 1:8a094db1347f 1638 }
elijahsj 1:8a094db1347f 1639 }
elijahsj 1:8a094db1347f 1640
elijahsj 1:8a094db1347f 1641
elijahsj 1:8a094db1347f 1642 /**
elijahsj 1:8a094db1347f 1643 \brief Encode Priority
elijahsj 1:8a094db1347f 1644 \details Encodes the priority for an interrupt with the given priority group,
elijahsj 1:8a094db1347f 1645 preemptive priority value, and subpriority value.
elijahsj 1:8a094db1347f 1646 In case of a conflict between priority grouping and available
elijahsj 1:8a094db1347f 1647 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
elijahsj 1:8a094db1347f 1648 \param [in] PriorityGroup Used priority group.
elijahsj 1:8a094db1347f 1649 \param [in] PreemptPriority Preemptive priority value (starting from 0).
elijahsj 1:8a094db1347f 1650 \param [in] SubPriority Subpriority value (starting from 0).
elijahsj 1:8a094db1347f 1651 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
elijahsj 1:8a094db1347f 1652 */
elijahsj 1:8a094db1347f 1653 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
elijahsj 1:8a094db1347f 1654 {
elijahsj 1:8a094db1347f 1655 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
elijahsj 1:8a094db1347f 1656 uint32_t PreemptPriorityBits;
elijahsj 1:8a094db1347f 1657 uint32_t SubPriorityBits;
elijahsj 1:8a094db1347f 1658
elijahsj 1:8a094db1347f 1659 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
elijahsj 1:8a094db1347f 1660 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
elijahsj 1:8a094db1347f 1661
elijahsj 1:8a094db1347f 1662 return (
elijahsj 1:8a094db1347f 1663 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
elijahsj 1:8a094db1347f 1664 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
elijahsj 1:8a094db1347f 1665 );
elijahsj 1:8a094db1347f 1666 }
elijahsj 1:8a094db1347f 1667
elijahsj 1:8a094db1347f 1668
elijahsj 1:8a094db1347f 1669 /**
elijahsj 1:8a094db1347f 1670 \brief Decode Priority
elijahsj 1:8a094db1347f 1671 \details Decodes an interrupt priority value with a given priority group to
elijahsj 1:8a094db1347f 1672 preemptive priority value and subpriority value.
elijahsj 1:8a094db1347f 1673 In case of a conflict between priority grouping and available
elijahsj 1:8a094db1347f 1674 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
elijahsj 1:8a094db1347f 1675 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
elijahsj 1:8a094db1347f 1676 \param [in] PriorityGroup Used priority group.
elijahsj 1:8a094db1347f 1677 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
elijahsj 1:8a094db1347f 1678 \param [out] pSubPriority Subpriority value (starting from 0).
elijahsj 1:8a094db1347f 1679 */
elijahsj 1:8a094db1347f 1680 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
elijahsj 1:8a094db1347f 1681 {
elijahsj 1:8a094db1347f 1682 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
elijahsj 1:8a094db1347f 1683 uint32_t PreemptPriorityBits;
elijahsj 1:8a094db1347f 1684 uint32_t SubPriorityBits;
elijahsj 1:8a094db1347f 1685
elijahsj 1:8a094db1347f 1686 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
elijahsj 1:8a094db1347f 1687 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
elijahsj 1:8a094db1347f 1688
elijahsj 1:8a094db1347f 1689 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
elijahsj 1:8a094db1347f 1690 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
elijahsj 1:8a094db1347f 1691 }
elijahsj 1:8a094db1347f 1692
elijahsj 1:8a094db1347f 1693
elijahsj 1:8a094db1347f 1694 /**
elijahsj 1:8a094db1347f 1695 \brief Set Interrupt Vector
elijahsj 1:8a094db1347f 1696 \details Sets an interrupt vector in SRAM based interrupt vector table.
elijahsj 1:8a094db1347f 1697 The interrupt number can be positive to specify a device specific interrupt,
elijahsj 1:8a094db1347f 1698 or negative to specify a processor exception.
elijahsj 1:8a094db1347f 1699 VTOR must been relocated to SRAM before.
elijahsj 1:8a094db1347f 1700 \param [in] IRQn Interrupt number
elijahsj 1:8a094db1347f 1701 \param [in] vector Address of interrupt handler function
elijahsj 1:8a094db1347f 1702 */
elijahsj 1:8a094db1347f 1703 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
elijahsj 1:8a094db1347f 1704 {
elijahsj 1:8a094db1347f 1705 uint32_t *vectors = (uint32_t *)SCB->VTOR;
elijahsj 1:8a094db1347f 1706 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
elijahsj 1:8a094db1347f 1707 }
elijahsj 1:8a094db1347f 1708
elijahsj 1:8a094db1347f 1709
elijahsj 1:8a094db1347f 1710 /**
elijahsj 1:8a094db1347f 1711 \brief Get Interrupt Vector
elijahsj 1:8a094db1347f 1712 \details Reads an interrupt vector from interrupt vector table.
elijahsj 1:8a094db1347f 1713 The interrupt number can be positive to specify a device specific interrupt,
elijahsj 1:8a094db1347f 1714 or negative to specify a processor exception.
elijahsj 1:8a094db1347f 1715 \param [in] IRQn Interrupt number.
elijahsj 1:8a094db1347f 1716 \return Address of interrupt handler function
elijahsj 1:8a094db1347f 1717 */
elijahsj 1:8a094db1347f 1718 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
elijahsj 1:8a094db1347f 1719 {
elijahsj 1:8a094db1347f 1720 uint32_t *vectors = (uint32_t *)SCB->VTOR;
elijahsj 1:8a094db1347f 1721 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
elijahsj 1:8a094db1347f 1722 }
elijahsj 1:8a094db1347f 1723
elijahsj 1:8a094db1347f 1724
elijahsj 1:8a094db1347f 1725 /**
elijahsj 1:8a094db1347f 1726 \brief System Reset
elijahsj 1:8a094db1347f 1727 \details Initiates a system reset request to reset the MCU.
elijahsj 1:8a094db1347f 1728 */
elijahsj 1:8a094db1347f 1729 __STATIC_INLINE void __NVIC_SystemReset(void)
elijahsj 1:8a094db1347f 1730 {
elijahsj 1:8a094db1347f 1731 __DSB(); /* Ensure all outstanding memory accesses included
elijahsj 1:8a094db1347f 1732 buffered write are completed before reset */
elijahsj 1:8a094db1347f 1733 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
elijahsj 1:8a094db1347f 1734 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
elijahsj 1:8a094db1347f 1735 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
elijahsj 1:8a094db1347f 1736 __DSB(); /* Ensure completion of memory access */
elijahsj 1:8a094db1347f 1737
elijahsj 1:8a094db1347f 1738 for(;;) /* wait until reset */
elijahsj 1:8a094db1347f 1739 {
elijahsj 1:8a094db1347f 1740 __NOP();
elijahsj 1:8a094db1347f 1741 }
elijahsj 1:8a094db1347f 1742 }
elijahsj 1:8a094db1347f 1743
elijahsj 1:8a094db1347f 1744 /*@} end of CMSIS_Core_NVICFunctions */
elijahsj 1:8a094db1347f 1745
elijahsj 1:8a094db1347f 1746
elijahsj 1:8a094db1347f 1747 /* ########################## FPU functions #################################### */
elijahsj 1:8a094db1347f 1748 /**
elijahsj 1:8a094db1347f 1749 \ingroup CMSIS_Core_FunctionInterface
elijahsj 1:8a094db1347f 1750 \defgroup CMSIS_Core_FpuFunctions FPU Functions
elijahsj 1:8a094db1347f 1751 \brief Function that provides FPU type.
elijahsj 1:8a094db1347f 1752 @{
elijahsj 1:8a094db1347f 1753 */
elijahsj 1:8a094db1347f 1754
elijahsj 1:8a094db1347f 1755 /**
elijahsj 1:8a094db1347f 1756 \brief get FPU type
elijahsj 1:8a094db1347f 1757 \details returns the FPU type
elijahsj 1:8a094db1347f 1758 \returns
elijahsj 1:8a094db1347f 1759 - \b 0: No FPU
elijahsj 1:8a094db1347f 1760 - \b 1: Single precision FPU
elijahsj 1:8a094db1347f 1761 - \b 2: Double + Single precision FPU
elijahsj 1:8a094db1347f 1762 */
elijahsj 1:8a094db1347f 1763 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
elijahsj 1:8a094db1347f 1764 {
elijahsj 1:8a094db1347f 1765 return 0U; /* No FPU */
elijahsj 1:8a094db1347f 1766 }
elijahsj 1:8a094db1347f 1767
elijahsj 1:8a094db1347f 1768
elijahsj 1:8a094db1347f 1769 /*@} end of CMSIS_Core_FpuFunctions */
elijahsj 1:8a094db1347f 1770
elijahsj 1:8a094db1347f 1771
elijahsj 1:8a094db1347f 1772
elijahsj 1:8a094db1347f 1773 /* ################################## SysTick function ############################################ */
elijahsj 1:8a094db1347f 1774 /**
elijahsj 1:8a094db1347f 1775 \ingroup CMSIS_Core_FunctionInterface
elijahsj 1:8a094db1347f 1776 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
elijahsj 1:8a094db1347f 1777 \brief Functions that configure the System.
elijahsj 1:8a094db1347f 1778 @{
elijahsj 1:8a094db1347f 1779 */
elijahsj 1:8a094db1347f 1780
elijahsj 1:8a094db1347f 1781 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
elijahsj 1:8a094db1347f 1782
elijahsj 1:8a094db1347f 1783 /**
elijahsj 1:8a094db1347f 1784 \brief System Tick Configuration
elijahsj 1:8a094db1347f 1785 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
elijahsj 1:8a094db1347f 1786 Counter is in free running mode to generate periodic interrupts.
elijahsj 1:8a094db1347f 1787 \param [in] ticks Number of ticks between two interrupts.
elijahsj 1:8a094db1347f 1788 \return 0 Function succeeded.
elijahsj 1:8a094db1347f 1789 \return 1 Function failed.
elijahsj 1:8a094db1347f 1790 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
elijahsj 1:8a094db1347f 1791 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
elijahsj 1:8a094db1347f 1792 must contain a vendor-specific implementation of this function.
elijahsj 1:8a094db1347f 1793 */
elijahsj 1:8a094db1347f 1794 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
elijahsj 1:8a094db1347f 1795 {
elijahsj 1:8a094db1347f 1796 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
elijahsj 1:8a094db1347f 1797 {
elijahsj 1:8a094db1347f 1798 return (1UL); /* Reload value impossible */
elijahsj 1:8a094db1347f 1799 }
elijahsj 1:8a094db1347f 1800
elijahsj 1:8a094db1347f 1801 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
elijahsj 1:8a094db1347f 1802 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
elijahsj 1:8a094db1347f 1803 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
elijahsj 1:8a094db1347f 1804 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
elijahsj 1:8a094db1347f 1805 SysTick_CTRL_TICKINT_Msk |
elijahsj 1:8a094db1347f 1806 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
elijahsj 1:8a094db1347f 1807 return (0UL); /* Function successful */
elijahsj 1:8a094db1347f 1808 }
elijahsj 1:8a094db1347f 1809
elijahsj 1:8a094db1347f 1810 #endif
elijahsj 1:8a094db1347f 1811
elijahsj 1:8a094db1347f 1812 /*@} end of CMSIS_Core_SysTickFunctions */
elijahsj 1:8a094db1347f 1813
elijahsj 1:8a094db1347f 1814
elijahsj 1:8a094db1347f 1815
elijahsj 1:8a094db1347f 1816 /* ##################################### Debug In/Output function ########################################### */
elijahsj 1:8a094db1347f 1817 /**
elijahsj 1:8a094db1347f 1818 \ingroup CMSIS_Core_FunctionInterface
elijahsj 1:8a094db1347f 1819 \defgroup CMSIS_core_DebugFunctions ITM Functions
elijahsj 1:8a094db1347f 1820 \brief Functions that access the ITM debug interface.
elijahsj 1:8a094db1347f 1821 @{
elijahsj 1:8a094db1347f 1822 */
elijahsj 1:8a094db1347f 1823
elijahsj 1:8a094db1347f 1824 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
elijahsj 1:8a094db1347f 1825 #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
elijahsj 1:8a094db1347f 1826
elijahsj 1:8a094db1347f 1827
elijahsj 1:8a094db1347f 1828 /**
elijahsj 1:8a094db1347f 1829 \brief ITM Send Character
elijahsj 1:8a094db1347f 1830 \details Transmits a character via the ITM channel 0, and
elijahsj 1:8a094db1347f 1831 \li Just returns when no debugger is connected that has booked the output.
elijahsj 1:8a094db1347f 1832 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
elijahsj 1:8a094db1347f 1833 \param [in] ch Character to transmit.
elijahsj 1:8a094db1347f 1834 \returns Character to transmit.
elijahsj 1:8a094db1347f 1835 */
elijahsj 1:8a094db1347f 1836 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
elijahsj 1:8a094db1347f 1837 {
elijahsj 1:8a094db1347f 1838 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
elijahsj 1:8a094db1347f 1839 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
elijahsj 1:8a094db1347f 1840 {
elijahsj 1:8a094db1347f 1841 while (ITM->PORT[0U].u32 == 0UL)
elijahsj 1:8a094db1347f 1842 {
elijahsj 1:8a094db1347f 1843 __NOP();
elijahsj 1:8a094db1347f 1844 }
elijahsj 1:8a094db1347f 1845 ITM->PORT[0U].u8 = (uint8_t)ch;
elijahsj 1:8a094db1347f 1846 }
elijahsj 1:8a094db1347f 1847 return (ch);
elijahsj 1:8a094db1347f 1848 }
elijahsj 1:8a094db1347f 1849
elijahsj 1:8a094db1347f 1850
elijahsj 1:8a094db1347f 1851 /**
elijahsj 1:8a094db1347f 1852 \brief ITM Receive Character
elijahsj 1:8a094db1347f 1853 \details Inputs a character via the external variable \ref ITM_RxBuffer.
elijahsj 1:8a094db1347f 1854 \return Received character.
elijahsj 1:8a094db1347f 1855 \return -1 No character pending.
elijahsj 1:8a094db1347f 1856 */
elijahsj 1:8a094db1347f 1857 __STATIC_INLINE int32_t ITM_ReceiveChar (void)
elijahsj 1:8a094db1347f 1858 {
elijahsj 1:8a094db1347f 1859 int32_t ch = -1; /* no character available */
elijahsj 1:8a094db1347f 1860
elijahsj 1:8a094db1347f 1861 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
elijahsj 1:8a094db1347f 1862 {
elijahsj 1:8a094db1347f 1863 ch = ITM_RxBuffer;
elijahsj 1:8a094db1347f 1864 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
elijahsj 1:8a094db1347f 1865 }
elijahsj 1:8a094db1347f 1866
elijahsj 1:8a094db1347f 1867 return (ch);
elijahsj 1:8a094db1347f 1868 }
elijahsj 1:8a094db1347f 1869
elijahsj 1:8a094db1347f 1870
elijahsj 1:8a094db1347f 1871 /**
elijahsj 1:8a094db1347f 1872 \brief ITM Check Character
elijahsj 1:8a094db1347f 1873 \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
elijahsj 1:8a094db1347f 1874 \return 0 No character available.
elijahsj 1:8a094db1347f 1875 \return 1 Character available.
elijahsj 1:8a094db1347f 1876 */
elijahsj 1:8a094db1347f 1877 __STATIC_INLINE int32_t ITM_CheckChar (void)
elijahsj 1:8a094db1347f 1878 {
elijahsj 1:8a094db1347f 1879
elijahsj 1:8a094db1347f 1880 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
elijahsj 1:8a094db1347f 1881 {
elijahsj 1:8a094db1347f 1882 return (0); /* no character available */
elijahsj 1:8a094db1347f 1883 }
elijahsj 1:8a094db1347f 1884 else
elijahsj 1:8a094db1347f 1885 {
elijahsj 1:8a094db1347f 1886 return (1); /* character available */
elijahsj 1:8a094db1347f 1887 }
elijahsj 1:8a094db1347f 1888 }
elijahsj 1:8a094db1347f 1889
elijahsj 1:8a094db1347f 1890 /*@} end of CMSIS_core_DebugFunctions */
elijahsj 1:8a094db1347f 1891
elijahsj 1:8a094db1347f 1892
elijahsj 1:8a094db1347f 1893
elijahsj 1:8a094db1347f 1894
elijahsj 1:8a094db1347f 1895 #ifdef __cplusplus
elijahsj 1:8a094db1347f 1896 }
elijahsj 1:8a094db1347f 1897 #endif
elijahsj 1:8a094db1347f 1898
elijahsj 1:8a094db1347f 1899 #endif /* __CORE_SC300_H_DEPENDANT */
elijahsj 1:8a094db1347f 1900
elijahsj 1:8a094db1347f 1901 #endif /* __CMSIS_GENERIC */