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TARGET_NUCLEO_L476RG/stm32l4xx_hal_pwr_ex.h@121:672067c3ada4, 2016-04-14 (annotated)
- Committer:
- elijahorr
- Date:
- Thu Apr 14 07:28:54 2016 +0000
- Revision:
- 121:672067c3ada4
- Parent:
- 107:4f6c30876dfa
.
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Kojto | 107:4f6c30876dfa | 1 | /** |
| Kojto | 107:4f6c30876dfa | 2 | ****************************************************************************** |
| Kojto | 107:4f6c30876dfa | 3 | * @file stm32l4xx_hal_pwr_ex.h |
| Kojto | 107:4f6c30876dfa | 4 | * @author MCD Application Team |
| Kojto | 107:4f6c30876dfa | 5 | * @version V1.0.0 |
| Kojto | 107:4f6c30876dfa | 6 | * @date 26-June-2015 |
| Kojto | 107:4f6c30876dfa | 7 | * @brief Header file of PWR HAL Extended module. |
| Kojto | 107:4f6c30876dfa | 8 | ****************************************************************************** |
| Kojto | 107:4f6c30876dfa | 9 | * @attention |
| Kojto | 107:4f6c30876dfa | 10 | * |
| Kojto | 107:4f6c30876dfa | 11 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> |
| Kojto | 107:4f6c30876dfa | 12 | * |
| Kojto | 107:4f6c30876dfa | 13 | * Redistribution and use in source and binary forms, with or without modification, |
| Kojto | 107:4f6c30876dfa | 14 | * are permitted provided that the following conditions are met: |
| Kojto | 107:4f6c30876dfa | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| Kojto | 107:4f6c30876dfa | 16 | * this list of conditions and the following disclaimer. |
| Kojto | 107:4f6c30876dfa | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| Kojto | 107:4f6c30876dfa | 18 | * this list of conditions and the following disclaimer in the documentation |
| Kojto | 107:4f6c30876dfa | 19 | * and/or other materials provided with the distribution. |
| Kojto | 107:4f6c30876dfa | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| Kojto | 107:4f6c30876dfa | 21 | * may be used to endorse or promote products derived from this software |
| Kojto | 107:4f6c30876dfa | 22 | * without specific prior written permission. |
| Kojto | 107:4f6c30876dfa | 23 | * |
| Kojto | 107:4f6c30876dfa | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| Kojto | 107:4f6c30876dfa | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| Kojto | 107:4f6c30876dfa | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| Kojto | 107:4f6c30876dfa | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| Kojto | 107:4f6c30876dfa | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| Kojto | 107:4f6c30876dfa | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| Kojto | 107:4f6c30876dfa | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| Kojto | 107:4f6c30876dfa | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| Kojto | 107:4f6c30876dfa | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| Kojto | 107:4f6c30876dfa | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| Kojto | 107:4f6c30876dfa | 34 | * |
| Kojto | 107:4f6c30876dfa | 35 | ****************************************************************************** |
| Kojto | 107:4f6c30876dfa | 36 | */ |
| Kojto | 107:4f6c30876dfa | 37 | |
| Kojto | 107:4f6c30876dfa | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| Kojto | 107:4f6c30876dfa | 39 | #ifndef __STM32L4xx_HAL_PWR_EX_H |
| Kojto | 107:4f6c30876dfa | 40 | #define __STM32L4xx_HAL_PWR_EX_H |
| Kojto | 107:4f6c30876dfa | 41 | |
| Kojto | 107:4f6c30876dfa | 42 | #ifdef __cplusplus |
| Kojto | 107:4f6c30876dfa | 43 | extern "C" { |
| Kojto | 107:4f6c30876dfa | 44 | #endif |
| Kojto | 107:4f6c30876dfa | 45 | |
| Kojto | 107:4f6c30876dfa | 46 | /* Includes ------------------------------------------------------------------*/ |
| Kojto | 107:4f6c30876dfa | 47 | #include "stm32l4xx_hal_def.h" |
| Kojto | 107:4f6c30876dfa | 48 | |
| Kojto | 107:4f6c30876dfa | 49 | /** @addtogroup STM32L4xx_HAL_Driver |
| Kojto | 107:4f6c30876dfa | 50 | * @{ |
| Kojto | 107:4f6c30876dfa | 51 | */ |
| Kojto | 107:4f6c30876dfa | 52 | |
| Kojto | 107:4f6c30876dfa | 53 | /** @addtogroup PWREx |
| Kojto | 107:4f6c30876dfa | 54 | * @{ |
| Kojto | 107:4f6c30876dfa | 55 | */ |
| Kojto | 107:4f6c30876dfa | 56 | |
| Kojto | 107:4f6c30876dfa | 57 | |
| Kojto | 107:4f6c30876dfa | 58 | /* Exported types ------------------------------------------------------------*/ |
| Kojto | 107:4f6c30876dfa | 59 | |
| Kojto | 107:4f6c30876dfa | 60 | /** @defgroup PWREx_Exported_Types PWR Extended Exported Types |
| Kojto | 107:4f6c30876dfa | 61 | * @{ |
| Kojto | 107:4f6c30876dfa | 62 | */ |
| Kojto | 107:4f6c30876dfa | 63 | |
| Kojto | 107:4f6c30876dfa | 64 | /** |
| Kojto | 107:4f6c30876dfa | 65 | * @brief PWR PVM configuration structure definition |
| Kojto | 107:4f6c30876dfa | 66 | */ |
| Kojto | 107:4f6c30876dfa | 67 | typedef struct |
| Kojto | 107:4f6c30876dfa | 68 | { |
| Kojto | 107:4f6c30876dfa | 69 | uint32_t PVMType; /*!< PVMType: Specifies which voltage is monitored and against which threshold. |
| Kojto | 107:4f6c30876dfa | 70 | This parameter can be a value of @ref PWREx_PVM_Type. |
| Kojto | 107:4f6c30876dfa | 71 | @arg PWR_PVM_1: Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported). |
| Kojto | 107:4f6c30876dfa | 72 | @arg PWR_PVM_2: Peripheral Voltage Monitoring 2 enable: VDDIO2 versus 0.9 V (applicable when VDDIO2 is present on device). |
| Kojto | 107:4f6c30876dfa | 73 | @arg PWR_PVM_3: Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V. |
| Kojto | 107:4f6c30876dfa | 74 | @arg PWR_PVM_4: Peripheral Voltage Monitoring 4 enable: VDDA versus 2.2 V. */ |
| Kojto | 107:4f6c30876dfa | 75 | |
| Kojto | 107:4f6c30876dfa | 76 | uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. |
| Kojto | 107:4f6c30876dfa | 77 | This parameter can be a value of @ref PWREx_PVM_Mode. */ |
| Kojto | 107:4f6c30876dfa | 78 | }PWR_PVMTypeDef; |
| Kojto | 107:4f6c30876dfa | 79 | |
| Kojto | 107:4f6c30876dfa | 80 | /** |
| Kojto | 107:4f6c30876dfa | 81 | * @} |
| Kojto | 107:4f6c30876dfa | 82 | */ |
| Kojto | 107:4f6c30876dfa | 83 | |
| Kojto | 107:4f6c30876dfa | 84 | /* Exported constants --------------------------------------------------------*/ |
| Kojto | 107:4f6c30876dfa | 85 | |
| Kojto | 107:4f6c30876dfa | 86 | /** @defgroup PWREx_Exported_Constants PWR Extended Exported Constants |
| Kojto | 107:4f6c30876dfa | 87 | * @{ |
| Kojto | 107:4f6c30876dfa | 88 | */ |
| Kojto | 107:4f6c30876dfa | 89 | |
| Kojto | 107:4f6c30876dfa | 90 | /** @defgroup PWREx_WUP_Polarity Shift to apply to retrieve polarity information from PWR_WAKEUP_PINy_xxx constants |
| Kojto | 107:4f6c30876dfa | 91 | * @{ |
| Kojto | 107:4f6c30876dfa | 92 | */ |
| Kojto | 107:4f6c30876dfa | 93 | #define PWR_WUP_POLARITY_SHIFT 0x05 /*!< Internal constant used to retrieve wakeup pin polariry */ |
| Kojto | 107:4f6c30876dfa | 94 | /** |
| Kojto | 107:4f6c30876dfa | 95 | * @} |
| Kojto | 107:4f6c30876dfa | 96 | */ |
| Kojto | 107:4f6c30876dfa | 97 | |
| Kojto | 107:4f6c30876dfa | 98 | |
| Kojto | 107:4f6c30876dfa | 99 | /** @defgroup PWREx_WakeUp_Pins PWR wake-up pins |
| Kojto | 107:4f6c30876dfa | 100 | * @{ |
| Kojto | 107:4f6c30876dfa | 101 | */ |
| Kojto | 107:4f6c30876dfa | 102 | #define PWR_WAKEUP_PIN1 PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level polarity) */ |
| Kojto | 107:4f6c30876dfa | 103 | #define PWR_WAKEUP_PIN2 PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level polarity) */ |
| Kojto | 107:4f6c30876dfa | 104 | #define PWR_WAKEUP_PIN3 PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level polarity) */ |
| Kojto | 107:4f6c30876dfa | 105 | #define PWR_WAKEUP_PIN4 PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level polarity) */ |
| Kojto | 107:4f6c30876dfa | 106 | #define PWR_WAKEUP_PIN5 PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level polarity) */ |
| Kojto | 107:4f6c30876dfa | 107 | #define PWR_WAKEUP_PIN1_HIGH PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level polarity) */ |
| Kojto | 107:4f6c30876dfa | 108 | #define PWR_WAKEUP_PIN2_HIGH PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level polarity) */ |
| Kojto | 107:4f6c30876dfa | 109 | #define PWR_WAKEUP_PIN3_HIGH PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level polarity) */ |
| Kojto | 107:4f6c30876dfa | 110 | #define PWR_WAKEUP_PIN4_HIGH PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level polarity) */ |
| Kojto | 107:4f6c30876dfa | 111 | #define PWR_WAKEUP_PIN5_HIGH PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level polarity) */ |
| Kojto | 107:4f6c30876dfa | 112 | #define PWR_WAKEUP_PIN1_LOW (uint32_t)((PWR_CR4_WP1<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP1) /*!< Wakeup pin 1 (with low level polarity) */ |
| Kojto | 107:4f6c30876dfa | 113 | #define PWR_WAKEUP_PIN2_LOW (uint32_t)((PWR_CR4_WP2<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP2) /*!< Wakeup pin 2 (with low level polarity) */ |
| Kojto | 107:4f6c30876dfa | 114 | #define PWR_WAKEUP_PIN3_LOW (uint32_t)((PWR_CR4_WP3<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP3) /*!< Wakeup pin 3 (with low level polarity) */ |
| Kojto | 107:4f6c30876dfa | 115 | #define PWR_WAKEUP_PIN4_LOW (uint32_t)((PWR_CR4_WP4<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP4) /*!< Wakeup pin 4 (with low level polarity) */ |
| Kojto | 107:4f6c30876dfa | 116 | #define PWR_WAKEUP_PIN5_LOW (uint32_t)((PWR_CR4_WP5<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP5) /*!< Wakeup pin 5 (with low level polarity) */ |
| Kojto | 107:4f6c30876dfa | 117 | /** |
| Kojto | 107:4f6c30876dfa | 118 | * @} |
| Kojto | 107:4f6c30876dfa | 119 | */ |
| Kojto | 107:4f6c30876dfa | 120 | |
| Kojto | 107:4f6c30876dfa | 121 | /** @defgroup PWREx_PVM_Type Peripheral Voltage Monitoring type |
| Kojto | 107:4f6c30876dfa | 122 | * @{ |
| Kojto | 107:4f6c30876dfa | 123 | */ |
| Kojto | 107:4f6c30876dfa | 124 | #if defined(STM32L475xx) || defined(STM32L476xx) || defined (STM32L485xx) || defined(STM32L486xx) |
| Kojto | 107:4f6c30876dfa | 125 | #define PWR_PVM_1 PWR_CR2_PVME1 /*!< Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported) */ |
| Kojto | 107:4f6c30876dfa | 126 | #endif /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ |
| Kojto | 107:4f6c30876dfa | 127 | #define PWR_PVM_2 PWR_CR2_PVME2 /*!< Peripheral Voltage Monitoring 2 enable: VDDIO2 versus 0.9 V (applicable when VDDIO2 is present on device) */ |
| Kojto | 107:4f6c30876dfa | 128 | #define PWR_PVM_3 PWR_CR2_PVME3 /*!< Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V */ |
| Kojto | 107:4f6c30876dfa | 129 | #define PWR_PVM_4 PWR_CR2_PVME4 /*!< Peripheral Voltage Monitoring 4 enable: VDDA versus 2.2 V */ |
| Kojto | 107:4f6c30876dfa | 130 | /** |
| Kojto | 107:4f6c30876dfa | 131 | * @} |
| Kojto | 107:4f6c30876dfa | 132 | */ |
| Kojto | 107:4f6c30876dfa | 133 | |
| Kojto | 107:4f6c30876dfa | 134 | /** @defgroup PWREx_PVM_Mode PWR PVM interrupt and event mode |
| Kojto | 107:4f6c30876dfa | 135 | * @{ |
| Kojto | 107:4f6c30876dfa | 136 | */ |
| Kojto | 107:4f6c30876dfa | 137 | #define PWR_PVM_MODE_NORMAL ((uint32_t)0x00000000) /*!< basic mode is used */ |
| Kojto | 107:4f6c30876dfa | 138 | #define PWR_PVM_MODE_IT_RISING ((uint32_t)0x00010001) /*!< External Interrupt Mode with Rising edge trigger detection */ |
| Kojto | 107:4f6c30876dfa | 139 | #define PWR_PVM_MODE_IT_FALLING ((uint32_t)0x00010002) /*!< External Interrupt Mode with Falling edge trigger detection */ |
| Kojto | 107:4f6c30876dfa | 140 | #define PWR_PVM_MODE_IT_RISING_FALLING ((uint32_t)0x00010003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ |
| Kojto | 107:4f6c30876dfa | 141 | #define PWR_PVM_MODE_EVENT_RISING ((uint32_t)0x00020001) /*!< Event Mode with Rising edge trigger detection */ |
| Kojto | 107:4f6c30876dfa | 142 | #define PWR_PVM_MODE_EVENT_FALLING ((uint32_t)0x00020002) /*!< Event Mode with Falling edge trigger detection */ |
| Kojto | 107:4f6c30876dfa | 143 | #define PWR_PVM_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger detection */ |
| Kojto | 107:4f6c30876dfa | 144 | /** |
| Kojto | 107:4f6c30876dfa | 145 | * @} |
| Kojto | 107:4f6c30876dfa | 146 | */ |
| Kojto | 107:4f6c30876dfa | 147 | |
| Kojto | 107:4f6c30876dfa | 148 | |
| Kojto | 107:4f6c30876dfa | 149 | |
| Kojto | 107:4f6c30876dfa | 150 | /** @defgroup PWREx_Regulator_Voltage_Scale PWR Regulator voltage scale |
| Kojto | 107:4f6c30876dfa | 151 | * @{ |
| Kojto | 107:4f6c30876dfa | 152 | */ |
| Kojto | 107:4f6c30876dfa | 153 | #define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR1_VOS_0 /*!< Voltage scaling range 1 */ |
| Kojto | 107:4f6c30876dfa | 154 | #define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR1_VOS_1 /*!< Voltage scaling range 2 */ |
| Kojto | 107:4f6c30876dfa | 155 | /** |
| Kojto | 107:4f6c30876dfa | 156 | * @} |
| Kojto | 107:4f6c30876dfa | 157 | */ |
| Kojto | 107:4f6c30876dfa | 158 | |
| Kojto | 107:4f6c30876dfa | 159 | |
| Kojto | 107:4f6c30876dfa | 160 | /** @defgroup PWREx_VBAT_Battery_Charging_Selection PWR battery charging resistor selection |
| Kojto | 107:4f6c30876dfa | 161 | * @{ |
| Kojto | 107:4f6c30876dfa | 162 | */ |
| Kojto | 107:4f6c30876dfa | 163 | #define PWR_BATTERY_CHARGING_RESISTOR_5 ((uint32_t)0x00000000) /*!< VBAT charging through a 5 kOhms resistor */ |
| Kojto | 107:4f6c30876dfa | 164 | #define PWR_BATTERY_CHARGING_RESISTOR_1_5 PWR_CR4_VBRS /*!< VBAT charging through a 1.5 kOhms resistor */ |
| Kojto | 107:4f6c30876dfa | 165 | /** |
| Kojto | 107:4f6c30876dfa | 166 | * @} |
| Kojto | 107:4f6c30876dfa | 167 | */ |
| Kojto | 107:4f6c30876dfa | 168 | |
| Kojto | 107:4f6c30876dfa | 169 | /** @defgroup PWREx_VBAT_Battery_Charging PWR battery charging |
| Kojto | 107:4f6c30876dfa | 170 | * @{ |
| Kojto | 107:4f6c30876dfa | 171 | */ |
| Kojto | 107:4f6c30876dfa | 172 | #define PWR_BATTERY_CHARGING_DISABLE ((uint32_t)0x00000000) |
| Kojto | 107:4f6c30876dfa | 173 | #define PWR_BATTERY_CHARGING_ENABLE PWR_CR4_VBE |
| Kojto | 107:4f6c30876dfa | 174 | /** |
| Kojto | 107:4f6c30876dfa | 175 | * @} |
| Kojto | 107:4f6c30876dfa | 176 | */ |
| Kojto | 107:4f6c30876dfa | 177 | |
| Kojto | 107:4f6c30876dfa | 178 | /** @defgroup PWREx_GPIO_Bit_Number GPIO bit number for I/O setting in standby/shutdown mode |
| Kojto | 107:4f6c30876dfa | 179 | * @{ |
| Kojto | 107:4f6c30876dfa | 180 | */ |
| Kojto | 107:4f6c30876dfa | 181 | #define PWR_GPIO_BIT_0 PWR_PUCRB_PB0 /*!< GPIO port I/O pin 0 */ |
| Kojto | 107:4f6c30876dfa | 182 | #define PWR_GPIO_BIT_1 PWR_PUCRB_PB1 /*!< GPIO port I/O pin 1 */ |
| Kojto | 107:4f6c30876dfa | 183 | #define PWR_GPIO_BIT_2 PWR_PUCRB_PB2 /*!< GPIO port I/O pin 2 */ |
| Kojto | 107:4f6c30876dfa | 184 | #define PWR_GPIO_BIT_3 PWR_PUCRB_PB3 /*!< GPIO port I/O pin 3 */ |
| Kojto | 107:4f6c30876dfa | 185 | #define PWR_GPIO_BIT_4 PWR_PUCRB_PB4 /*!< GPIO port I/O pin 4 */ |
| Kojto | 107:4f6c30876dfa | 186 | #define PWR_GPIO_BIT_5 PWR_PUCRB_PB5 /*!< GPIO port I/O pin 5 */ |
| Kojto | 107:4f6c30876dfa | 187 | #define PWR_GPIO_BIT_6 PWR_PUCRB_PB6 /*!< GPIO port I/O pin 6 */ |
| Kojto | 107:4f6c30876dfa | 188 | #define PWR_GPIO_BIT_7 PWR_PUCRB_PB7 /*!< GPIO port I/O pin 7 */ |
| Kojto | 107:4f6c30876dfa | 189 | #define PWR_GPIO_BIT_8 PWR_PUCRB_PB8 /*!< GPIO port I/O pin 8 */ |
| Kojto | 107:4f6c30876dfa | 190 | #define PWR_GPIO_BIT_9 PWR_PUCRB_PB9 /*!< GPIO port I/O pin 9 */ |
| Kojto | 107:4f6c30876dfa | 191 | #define PWR_GPIO_BIT_10 PWR_PUCRB_PB10 /*!< GPIO port I/O pin 10 */ |
| Kojto | 107:4f6c30876dfa | 192 | #define PWR_GPIO_BIT_11 PWR_PUCRB_PB11 /*!< GPIO port I/O pin 11 */ |
| Kojto | 107:4f6c30876dfa | 193 | #define PWR_GPIO_BIT_12 PWR_PUCRB_PB12 /*!< GPIO port I/O pin 12 */ |
| Kojto | 107:4f6c30876dfa | 194 | #define PWR_GPIO_BIT_13 PWR_PUCRB_PB13 /*!< GPIO port I/O pin 13 */ |
| Kojto | 107:4f6c30876dfa | 195 | #define PWR_GPIO_BIT_14 PWR_PUCRB_PB14 /*!< GPIO port I/O pin 14 */ |
| Kojto | 107:4f6c30876dfa | 196 | #define PWR_GPIO_BIT_15 PWR_PUCRB_PB15 /*!< GPIO port I/O pin15 */ |
| Kojto | 107:4f6c30876dfa | 197 | /** |
| Kojto | 107:4f6c30876dfa | 198 | * @} |
| Kojto | 107:4f6c30876dfa | 199 | */ |
| Kojto | 107:4f6c30876dfa | 200 | |
| Kojto | 107:4f6c30876dfa | 201 | /** @defgroup PWREx_GPIO GPIO port |
| Kojto | 107:4f6c30876dfa | 202 | * @{ |
| Kojto | 107:4f6c30876dfa | 203 | */ |
| Kojto | 107:4f6c30876dfa | 204 | #define PWR_GPIO_A 0x00000000 /*!< GPIO port A */ |
| Kojto | 107:4f6c30876dfa | 205 | #define PWR_GPIO_B 0x00000001 /*!< GPIO port B */ |
| Kojto | 107:4f6c30876dfa | 206 | #define PWR_GPIO_C 0x00000002 /*!< GPIO port C */ |
| Kojto | 107:4f6c30876dfa | 207 | #define PWR_GPIO_D 0x00000003 /*!< GPIO port D */ |
| Kojto | 107:4f6c30876dfa | 208 | #define PWR_GPIO_E 0x00000004 /*!< GPIO port E */ |
| Kojto | 107:4f6c30876dfa | 209 | #define PWR_GPIO_F 0x00000005 /*!< GPIO port F */ |
| Kojto | 107:4f6c30876dfa | 210 | #define PWR_GPIO_G 0x00000006 /*!< GPIO port G */ |
| Kojto | 107:4f6c30876dfa | 211 | #define PWR_GPIO_H 0x00000007 /*!< GPIO port H */ |
| Kojto | 107:4f6c30876dfa | 212 | /** |
| Kojto | 107:4f6c30876dfa | 213 | * @} |
| Kojto | 107:4f6c30876dfa | 214 | */ |
| Kojto | 107:4f6c30876dfa | 215 | |
| Kojto | 107:4f6c30876dfa | 216 | /** @defgroup PWREx_PVM_EXTI_LINE PWR PVM external interrupts lines |
| Kojto | 107:4f6c30876dfa | 217 | * @{ |
| Kojto | 107:4f6c30876dfa | 218 | */ |
| Kojto | 107:4f6c30876dfa | 219 | #if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) |
| Kojto | 107:4f6c30876dfa | 220 | #define PWR_EXTI_LINE_PVM1 ((uint32_t)0x00000008) /*!< External interrupt line 35 Connected to the PVM1 EXTI Line */ |
| Kojto | 107:4f6c30876dfa | 221 | #endif /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ |
| Kojto | 107:4f6c30876dfa | 222 | |
| Kojto | 107:4f6c30876dfa | 223 | #define PWR_EXTI_LINE_PVM2 ((uint32_t)0x00000010) /*!< External interrupt line 36 Connected to the PVM2 EXTI Line */ |
| Kojto | 107:4f6c30876dfa | 224 | #define PWR_EXTI_LINE_PVM3 ((uint32_t)0x00000020) /*!< External interrupt line 37 Connected to the PVM3 EXTI Line */ |
| Kojto | 107:4f6c30876dfa | 225 | #define PWR_EXTI_LINE_PVM4 ((uint32_t)0x00000040) /*!< External interrupt line 38 Connected to the PVM4 EXTI Line */ |
| Kojto | 107:4f6c30876dfa | 226 | /** |
| Kojto | 107:4f6c30876dfa | 227 | * @} |
| Kojto | 107:4f6c30876dfa | 228 | */ |
| Kojto | 107:4f6c30876dfa | 229 | |
| Kojto | 107:4f6c30876dfa | 230 | /** @defgroup PWREx_PVM_EVENT_LINE PWR PVM event lines |
| Kojto | 107:4f6c30876dfa | 231 | * @{ |
| Kojto | 107:4f6c30876dfa | 232 | */ |
| Kojto | 107:4f6c30876dfa | 233 | #if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) |
| Kojto | 107:4f6c30876dfa | 234 | #define PWR_EVENT_LINE_PVM1 ((uint32_t)0x00000008) /*!< Event line 35 Connected to the PVM1 EXTI Line */ |
| Kojto | 107:4f6c30876dfa | 235 | #endif /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ |
| Kojto | 107:4f6c30876dfa | 236 | #define PWR_EVENT_LINE_PVM2 ((uint32_t)0x00000010) /*!< Event line 36 Connected to the PVM2 EXTI Line */ |
| Kojto | 107:4f6c30876dfa | 237 | #define PWR_EVENT_LINE_PVM3 ((uint32_t)0x00000020) /*!< Event line 37 Connected to the PVM3 EXTI Line */ |
| Kojto | 107:4f6c30876dfa | 238 | #define PWR_EVENT_LINE_PVM4 ((uint32_t)0x00000040) /*!< Event line 38 Connected to the PVM4 EXTI Line */ |
| Kojto | 107:4f6c30876dfa | 239 | /** |
| Kojto | 107:4f6c30876dfa | 240 | * @} |
| Kojto | 107:4f6c30876dfa | 241 | */ |
| Kojto | 107:4f6c30876dfa | 242 | |
| Kojto | 107:4f6c30876dfa | 243 | /** @defgroup PWREx_Flag PWR Status Flags |
| Kojto | 107:4f6c30876dfa | 244 | * Elements values convention: 0000 0000 0XXY YYYYb |
| Kojto | 107:4f6c30876dfa | 245 | * - Y YYYY : Flag position in the XX register (5 bits) |
| Kojto | 107:4f6c30876dfa | 246 | * - XX : Status register (2 bits) |
| Kojto | 107:4f6c30876dfa | 247 | * - 01: SR1 register |
| Kojto | 107:4f6c30876dfa | 248 | * - 10: SR2 register |
| Kojto | 107:4f6c30876dfa | 249 | * The only exception is PWR_FLAG_WU, encompassing all |
| Kojto | 107:4f6c30876dfa | 250 | * wake-up flags and set to PWR_SR1_WUF. |
| Kojto | 107:4f6c30876dfa | 251 | * @{ |
| Kojto | 107:4f6c30876dfa | 252 | */ |
| Kojto | 107:4f6c30876dfa | 253 | #define PWR_FLAG_WUF1 ((uint32_t)0x0020) /*!< Wakeup event on wakeup pin 1 */ |
| Kojto | 107:4f6c30876dfa | 254 | #define PWR_FLAG_WUF2 ((uint32_t)0x0021) /*!< Wakeup event on wakeup pin 2 */ |
| Kojto | 107:4f6c30876dfa | 255 | #define PWR_FLAG_WUF3 ((uint32_t)0x0022) /*!< Wakeup event on wakeup pin 3 */ |
| Kojto | 107:4f6c30876dfa | 256 | #define PWR_FLAG_WUF4 ((uint32_t)0x0023) /*!< Wakeup event on wakeup pin 4 */ |
| Kojto | 107:4f6c30876dfa | 257 | #define PWR_FLAG_WUF5 ((uint32_t)0x0024) /*!< Wakeup event on wakeup pin 5 */ |
| Kojto | 107:4f6c30876dfa | 258 | #define PWR_FLAG_WU PWR_SR1_WUF /*!< Encompass wakeup event on all wakeup pins */ |
| Kojto | 107:4f6c30876dfa | 259 | #define PWR_FLAG_SB ((uint32_t)0x0028) /*!< Standby flag */ |
| Kojto | 107:4f6c30876dfa | 260 | #define PWR_FLAG_WUFI ((uint32_t)0x002F) /*!< Wakeup on internal wakeup line */ |
| Kojto | 107:4f6c30876dfa | 261 | |
| Kojto | 107:4f6c30876dfa | 262 | #define PWR_FLAG_REGLPS ((uint32_t)0x0048) /*!< Low-power regulator start flag */ |
| Kojto | 107:4f6c30876dfa | 263 | #define PWR_FLAG_REGLPF ((uint32_t)0x0049) /*!< Low-power regulator flag */ |
| Kojto | 107:4f6c30876dfa | 264 | #define PWR_FLAG_VOSF ((uint32_t)0x004A) /*!< Voltage scaling flag */ |
| Kojto | 107:4f6c30876dfa | 265 | #define PWR_FLAG_PVDO ((uint32_t)0x004B) /*!< Power Voltage Detector output flag */ |
| Kojto | 107:4f6c30876dfa | 266 | #if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) |
| Kojto | 107:4f6c30876dfa | 267 | #define PWR_FLAG_PVMO1 ((uint32_t)0x004C) /*!< Power Voltage Monitoring 1 output flag */ |
| Kojto | 107:4f6c30876dfa | 268 | #endif /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ |
| Kojto | 107:4f6c30876dfa | 269 | #define PWR_FLAG_PVMO2 ((uint32_t)0x004D) /*!< Power Voltage Monitoring 2 output flag */ |
| Kojto | 107:4f6c30876dfa | 270 | #define PWR_FLAG_PVMO3 ((uint32_t)0x004E) /*!< Power Voltage Monitoring 3 output flag */ |
| Kojto | 107:4f6c30876dfa | 271 | #define PWR_FLAG_PVMO4 ((uint32_t)0x004F) /*!< Power Voltage Monitoring 4 output flag */ |
| Kojto | 107:4f6c30876dfa | 272 | /** |
| Kojto | 107:4f6c30876dfa | 273 | * @} |
| Kojto | 107:4f6c30876dfa | 274 | */ |
| Kojto | 107:4f6c30876dfa | 275 | |
| Kojto | 107:4f6c30876dfa | 276 | /** |
| Kojto | 107:4f6c30876dfa | 277 | * @} |
| Kojto | 107:4f6c30876dfa | 278 | */ |
| Kojto | 107:4f6c30876dfa | 279 | |
| Kojto | 107:4f6c30876dfa | 280 | /* Exported macros -----------------------------------------------------------*/ |
| Kojto | 107:4f6c30876dfa | 281 | /** @defgroup PWREx_Exported_Macros PWR Extended Exported Macros |
| Kojto | 107:4f6c30876dfa | 282 | * @{ |
| Kojto | 107:4f6c30876dfa | 283 | */ |
| Kojto | 107:4f6c30876dfa | 284 | |
| Kojto | 107:4f6c30876dfa | 285 | #if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) |
| Kojto | 107:4f6c30876dfa | 286 | /** |
| Kojto | 107:4f6c30876dfa | 287 | * @brief Enable the PVM1 Extended Interrupt Line. |
| Kojto | 107:4f6c30876dfa | 288 | * @retval None |
| Kojto | 107:4f6c30876dfa | 289 | */ |
| Kojto | 107:4f6c30876dfa | 290 | #define __HAL_PWR_PVM1_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1) |
| Kojto | 107:4f6c30876dfa | 291 | |
| Kojto | 107:4f6c30876dfa | 292 | /** |
| Kojto | 107:4f6c30876dfa | 293 | * @brief Disable the PVM1 Extended Interrupt Line. |
| Kojto | 107:4f6c30876dfa | 294 | * @retval None |
| Kojto | 107:4f6c30876dfa | 295 | */ |
| Kojto | 107:4f6c30876dfa | 296 | #define __HAL_PWR_PVM1_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1) |
| Kojto | 107:4f6c30876dfa | 297 | |
| Kojto | 107:4f6c30876dfa | 298 | /** |
| Kojto | 107:4f6c30876dfa | 299 | * @brief Enable the PVM1 Event Line. |
| Kojto | 107:4f6c30876dfa | 300 | * @retval None |
| Kojto | 107:4f6c30876dfa | 301 | */ |
| Kojto | 107:4f6c30876dfa | 302 | #define __HAL_PWR_PVM1_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1) |
| Kojto | 107:4f6c30876dfa | 303 | |
| Kojto | 107:4f6c30876dfa | 304 | /** |
| Kojto | 107:4f6c30876dfa | 305 | * @brief Disable the PVM1 Event Line. |
| Kojto | 107:4f6c30876dfa | 306 | * @retval None |
| Kojto | 107:4f6c30876dfa | 307 | */ |
| Kojto | 107:4f6c30876dfa | 308 | #define __HAL_PWR_PVM1_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1) |
| Kojto | 107:4f6c30876dfa | 309 | |
| Kojto | 107:4f6c30876dfa | 310 | /** |
| Kojto | 107:4f6c30876dfa | 311 | * @brief Enable the PVM1 Extended Interrupt Rising Trigger. |
| Kojto | 107:4f6c30876dfa | 312 | * @retval None |
| Kojto | 107:4f6c30876dfa | 313 | */ |
| Kojto | 107:4f6c30876dfa | 314 | #define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1) |
| Kojto | 107:4f6c30876dfa | 315 | |
| Kojto | 107:4f6c30876dfa | 316 | /** |
| Kojto | 107:4f6c30876dfa | 317 | * @brief Disable the PVM1 Extended Interrupt Rising Trigger. |
| Kojto | 107:4f6c30876dfa | 318 | * @retval None |
| Kojto | 107:4f6c30876dfa | 319 | */ |
| Kojto | 107:4f6c30876dfa | 320 | #define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1) |
| Kojto | 107:4f6c30876dfa | 321 | |
| Kojto | 107:4f6c30876dfa | 322 | /** |
| Kojto | 107:4f6c30876dfa | 323 | * @brief Enable the PVM1 Extended Interrupt Falling Trigger. |
| Kojto | 107:4f6c30876dfa | 324 | * @retval None |
| Kojto | 107:4f6c30876dfa | 325 | */ |
| Kojto | 107:4f6c30876dfa | 326 | #define __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1) |
| Kojto | 107:4f6c30876dfa | 327 | |
| Kojto | 107:4f6c30876dfa | 328 | |
| Kojto | 107:4f6c30876dfa | 329 | /** |
| Kojto | 107:4f6c30876dfa | 330 | * @brief Disable the PVM1 Extended Interrupt Falling Trigger. |
| Kojto | 107:4f6c30876dfa | 331 | * @retval None |
| Kojto | 107:4f6c30876dfa | 332 | */ |
| Kojto | 107:4f6c30876dfa | 333 | #define __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1) |
| Kojto | 107:4f6c30876dfa | 334 | |
| Kojto | 107:4f6c30876dfa | 335 | |
| Kojto | 107:4f6c30876dfa | 336 | /** |
| Kojto | 107:4f6c30876dfa | 337 | * @brief PVM1 EXTI line configuration: set rising & falling edge trigger. |
| Kojto | 107:4f6c30876dfa | 338 | * @retval None |
| Kojto | 107:4f6c30876dfa | 339 | */ |
| Kojto | 107:4f6c30876dfa | 340 | #define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_FALLING_EDGE() \ |
| Kojto | 107:4f6c30876dfa | 341 | do { \ |
| Kojto | 107:4f6c30876dfa | 342 | __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE(); \ |
| Kojto | 107:4f6c30876dfa | 343 | __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE(); \ |
| Kojto | 107:4f6c30876dfa | 344 | } while(0) |
| Kojto | 107:4f6c30876dfa | 345 | |
| Kojto | 107:4f6c30876dfa | 346 | /** |
| Kojto | 107:4f6c30876dfa | 347 | * @brief Disable the PVM1 Extended Interrupt Rising & Falling Trigger. |
| Kojto | 107:4f6c30876dfa | 348 | * @retval None |
| Kojto | 107:4f6c30876dfa | 349 | */ |
| Kojto | 107:4f6c30876dfa | 350 | #define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_FALLING_EDGE() \ |
| Kojto | 107:4f6c30876dfa | 351 | do { \ |
| Kojto | 107:4f6c30876dfa | 352 | __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE(); \ |
| Kojto | 107:4f6c30876dfa | 353 | __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE(); \ |
| Kojto | 107:4f6c30876dfa | 354 | } while(0) |
| Kojto | 107:4f6c30876dfa | 355 | |
| Kojto | 107:4f6c30876dfa | 356 | /** |
| Kojto | 107:4f6c30876dfa | 357 | * @brief Generate a Software interrupt on selected EXTI line. |
| Kojto | 107:4f6c30876dfa | 358 | * @retval None |
| Kojto | 107:4f6c30876dfa | 359 | */ |
| Kojto | 107:4f6c30876dfa | 360 | #define __HAL_PWR_PVM1_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM1) |
| Kojto | 107:4f6c30876dfa | 361 | |
| Kojto | 107:4f6c30876dfa | 362 | /** |
| Kojto | 107:4f6c30876dfa | 363 | * @brief Check whether the specified PVM1 EXTI interrupt flag is set or not. |
| Kojto | 107:4f6c30876dfa | 364 | * @retval EXTI PVM1 Line Status. |
| Kojto | 107:4f6c30876dfa | 365 | */ |
| Kojto | 107:4f6c30876dfa | 366 | #define __HAL_PWR_PVM1_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM1) |
| Kojto | 107:4f6c30876dfa | 367 | |
| Kojto | 107:4f6c30876dfa | 368 | /** |
| Kojto | 107:4f6c30876dfa | 369 | * @brief Clear the PVM1 EXTI flag. |
| Kojto | 107:4f6c30876dfa | 370 | * @retval None |
| Kojto | 107:4f6c30876dfa | 371 | */ |
| Kojto | 107:4f6c30876dfa | 372 | #define __HAL_PWR_PVM1_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM1) |
| Kojto | 107:4f6c30876dfa | 373 | |
| Kojto | 107:4f6c30876dfa | 374 | #endif /* defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */ |
| Kojto | 107:4f6c30876dfa | 375 | |
| Kojto | 107:4f6c30876dfa | 376 | |
| Kojto | 107:4f6c30876dfa | 377 | /** |
| Kojto | 107:4f6c30876dfa | 378 | * @brief Enable the PVM2 Extended Interrupt Line. |
| Kojto | 107:4f6c30876dfa | 379 | * @retval None |
| Kojto | 107:4f6c30876dfa | 380 | */ |
| Kojto | 107:4f6c30876dfa | 381 | #define __HAL_PWR_PVM2_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2) |
| Kojto | 107:4f6c30876dfa | 382 | |
| Kojto | 107:4f6c30876dfa | 383 | /** |
| Kojto | 107:4f6c30876dfa | 384 | * @brief Disable the PVM2 Extended Interrupt Line. |
| Kojto | 107:4f6c30876dfa | 385 | * @retval None |
| Kojto | 107:4f6c30876dfa | 386 | */ |
| Kojto | 107:4f6c30876dfa | 387 | #define __HAL_PWR_PVM2_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2) |
| Kojto | 107:4f6c30876dfa | 388 | |
| Kojto | 107:4f6c30876dfa | 389 | /** |
| Kojto | 107:4f6c30876dfa | 390 | * @brief Enable the PVM2 Event Line. |
| Kojto | 107:4f6c30876dfa | 391 | * @retval None |
| Kojto | 107:4f6c30876dfa | 392 | */ |
| Kojto | 107:4f6c30876dfa | 393 | #define __HAL_PWR_PVM2_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2) |
| Kojto | 107:4f6c30876dfa | 394 | |
| Kojto | 107:4f6c30876dfa | 395 | /** |
| Kojto | 107:4f6c30876dfa | 396 | * @brief Disable the PVM2 Event Line. |
| Kojto | 107:4f6c30876dfa | 397 | * @retval None |
| Kojto | 107:4f6c30876dfa | 398 | */ |
| Kojto | 107:4f6c30876dfa | 399 | #define __HAL_PWR_PVM2_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2) |
| Kojto | 107:4f6c30876dfa | 400 | |
| Kojto | 107:4f6c30876dfa | 401 | /** |
| Kojto | 107:4f6c30876dfa | 402 | * @brief Enable the PVM2 Extended Interrupt Rising Trigger. |
| Kojto | 107:4f6c30876dfa | 403 | * @retval None |
| Kojto | 107:4f6c30876dfa | 404 | */ |
| Kojto | 107:4f6c30876dfa | 405 | #define __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2) |
| Kojto | 107:4f6c30876dfa | 406 | |
| Kojto | 107:4f6c30876dfa | 407 | /** |
| Kojto | 107:4f6c30876dfa | 408 | * @brief Disable the PVM2 Extended Interrupt Rising Trigger. |
| Kojto | 107:4f6c30876dfa | 409 | * @retval None |
| Kojto | 107:4f6c30876dfa | 410 | */ |
| Kojto | 107:4f6c30876dfa | 411 | #define __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2) |
| Kojto | 107:4f6c30876dfa | 412 | |
| Kojto | 107:4f6c30876dfa | 413 | /** |
| Kojto | 107:4f6c30876dfa | 414 | * @brief Enable the PVM2 Extended Interrupt Falling Trigger. |
| Kojto | 107:4f6c30876dfa | 415 | * @retval None |
| Kojto | 107:4f6c30876dfa | 416 | */ |
| Kojto | 107:4f6c30876dfa | 417 | #define __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2) |
| Kojto | 107:4f6c30876dfa | 418 | |
| Kojto | 107:4f6c30876dfa | 419 | |
| Kojto | 107:4f6c30876dfa | 420 | /** |
| Kojto | 107:4f6c30876dfa | 421 | * @brief Disable the PVM2 Extended Interrupt Falling Trigger. |
| Kojto | 107:4f6c30876dfa | 422 | * @retval None |
| Kojto | 107:4f6c30876dfa | 423 | */ |
| Kojto | 107:4f6c30876dfa | 424 | #define __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2) |
| Kojto | 107:4f6c30876dfa | 425 | |
| Kojto | 107:4f6c30876dfa | 426 | |
| Kojto | 107:4f6c30876dfa | 427 | /** |
| Kojto | 107:4f6c30876dfa | 428 | * @brief PVM2 EXTI line configuration: set rising & falling edge trigger. |
| Kojto | 107:4f6c30876dfa | 429 | * @retval None |
| Kojto | 107:4f6c30876dfa | 430 | */ |
| Kojto | 107:4f6c30876dfa | 431 | #define __HAL_PWR_PVM2_EXTI_ENABLE_RISING_FALLING_EDGE() \ |
| Kojto | 107:4f6c30876dfa | 432 | do { \ |
| Kojto | 107:4f6c30876dfa | 433 | __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE(); \ |
| Kojto | 107:4f6c30876dfa | 434 | __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE(); \ |
| Kojto | 107:4f6c30876dfa | 435 | } while(0) |
| Kojto | 107:4f6c30876dfa | 436 | |
| Kojto | 107:4f6c30876dfa | 437 | /** |
| Kojto | 107:4f6c30876dfa | 438 | * @brief Disable the PVM2 Extended Interrupt Rising & Falling Trigger. |
| Kojto | 107:4f6c30876dfa | 439 | * @retval None |
| Kojto | 107:4f6c30876dfa | 440 | */ |
| Kojto | 107:4f6c30876dfa | 441 | #define __HAL_PWR_PVM2_EXTI_DISABLE_RISING_FALLING_EDGE() \ |
| Kojto | 107:4f6c30876dfa | 442 | do { \ |
| Kojto | 107:4f6c30876dfa | 443 | __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE(); \ |
| Kojto | 107:4f6c30876dfa | 444 | __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE(); \ |
| Kojto | 107:4f6c30876dfa | 445 | } while(0) |
| Kojto | 107:4f6c30876dfa | 446 | |
| Kojto | 107:4f6c30876dfa | 447 | /** |
| Kojto | 107:4f6c30876dfa | 448 | * @brief Generate a Software interrupt on selected EXTI line. |
| Kojto | 107:4f6c30876dfa | 449 | * @retval None |
| Kojto | 107:4f6c30876dfa | 450 | */ |
| Kojto | 107:4f6c30876dfa | 451 | #define __HAL_PWR_PVM2_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM2) |
| Kojto | 107:4f6c30876dfa | 452 | |
| Kojto | 107:4f6c30876dfa | 453 | /** |
| Kojto | 107:4f6c30876dfa | 454 | * @brief Check whether the specified PVM2 EXTI interrupt flag is set or not. |
| Kojto | 107:4f6c30876dfa | 455 | * @retval EXTI PVM2 Line Status. |
| Kojto | 107:4f6c30876dfa | 456 | */ |
| Kojto | 107:4f6c30876dfa | 457 | #define __HAL_PWR_PVM2_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM2) |
| Kojto | 107:4f6c30876dfa | 458 | |
| Kojto | 107:4f6c30876dfa | 459 | /** |
| Kojto | 107:4f6c30876dfa | 460 | * @brief Clear the PVM2 EXTI flag. |
| Kojto | 107:4f6c30876dfa | 461 | * @retval None |
| Kojto | 107:4f6c30876dfa | 462 | */ |
| Kojto | 107:4f6c30876dfa | 463 | #define __HAL_PWR_PVM2_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM2) |
| Kojto | 107:4f6c30876dfa | 464 | |
| Kojto | 107:4f6c30876dfa | 465 | |
| Kojto | 107:4f6c30876dfa | 466 | |
| Kojto | 107:4f6c30876dfa | 467 | |
| Kojto | 107:4f6c30876dfa | 468 | /** |
| Kojto | 107:4f6c30876dfa | 469 | * @brief Enable the PVM3 Extended Interrupt Line. |
| Kojto | 107:4f6c30876dfa | 470 | * @retval None |
| Kojto | 107:4f6c30876dfa | 471 | */ |
| Kojto | 107:4f6c30876dfa | 472 | #define __HAL_PWR_PVM3_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3) |
| Kojto | 107:4f6c30876dfa | 473 | |
| Kojto | 107:4f6c30876dfa | 474 | /** |
| Kojto | 107:4f6c30876dfa | 475 | * @brief Disable the PVM3 Extended Interrupt Line. |
| Kojto | 107:4f6c30876dfa | 476 | * @retval None |
| Kojto | 107:4f6c30876dfa | 477 | */ |
| Kojto | 107:4f6c30876dfa | 478 | #define __HAL_PWR_PVM3_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3) |
| Kojto | 107:4f6c30876dfa | 479 | |
| Kojto | 107:4f6c30876dfa | 480 | /** |
| Kojto | 107:4f6c30876dfa | 481 | * @brief Enable the PVM3 Event Line. |
| Kojto | 107:4f6c30876dfa | 482 | * @retval None |
| Kojto | 107:4f6c30876dfa | 483 | */ |
| Kojto | 107:4f6c30876dfa | 484 | #define __HAL_PWR_PVM3_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3) |
| Kojto | 107:4f6c30876dfa | 485 | |
| Kojto | 107:4f6c30876dfa | 486 | /** |
| Kojto | 107:4f6c30876dfa | 487 | * @brief Disable the PVM3 Event Line. |
| Kojto | 107:4f6c30876dfa | 488 | * @retval None |
| Kojto | 107:4f6c30876dfa | 489 | */ |
| Kojto | 107:4f6c30876dfa | 490 | #define __HAL_PWR_PVM3_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3) |
| Kojto | 107:4f6c30876dfa | 491 | |
| Kojto | 107:4f6c30876dfa | 492 | /** |
| Kojto | 107:4f6c30876dfa | 493 | * @brief Enable the PVM3 Extended Interrupt Rising Trigger. |
| Kojto | 107:4f6c30876dfa | 494 | * @retval None |
| Kojto | 107:4f6c30876dfa | 495 | */ |
| Kojto | 107:4f6c30876dfa | 496 | #define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3) |
| Kojto | 107:4f6c30876dfa | 497 | |
| Kojto | 107:4f6c30876dfa | 498 | /** |
| Kojto | 107:4f6c30876dfa | 499 | * @brief Disable the PVM3 Extended Interrupt Rising Trigger. |
| Kojto | 107:4f6c30876dfa | 500 | * @retval None |
| Kojto | 107:4f6c30876dfa | 501 | */ |
| Kojto | 107:4f6c30876dfa | 502 | #define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3) |
| Kojto | 107:4f6c30876dfa | 503 | |
| Kojto | 107:4f6c30876dfa | 504 | /** |
| Kojto | 107:4f6c30876dfa | 505 | * @brief Enable the PVM3 Extended Interrupt Falling Trigger. |
| Kojto | 107:4f6c30876dfa | 506 | * @retval None |
| Kojto | 107:4f6c30876dfa | 507 | */ |
| Kojto | 107:4f6c30876dfa | 508 | #define __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3) |
| Kojto | 107:4f6c30876dfa | 509 | |
| Kojto | 107:4f6c30876dfa | 510 | |
| Kojto | 107:4f6c30876dfa | 511 | /** |
| Kojto | 107:4f6c30876dfa | 512 | * @brief Disable the PVM3 Extended Interrupt Falling Trigger. |
| Kojto | 107:4f6c30876dfa | 513 | * @retval None |
| Kojto | 107:4f6c30876dfa | 514 | */ |
| Kojto | 107:4f6c30876dfa | 515 | #define __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3) |
| Kojto | 107:4f6c30876dfa | 516 | |
| Kojto | 107:4f6c30876dfa | 517 | |
| Kojto | 107:4f6c30876dfa | 518 | /** |
| Kojto | 107:4f6c30876dfa | 519 | * @brief PVM3 EXTI line configuration: set rising & falling edge trigger. |
| Kojto | 107:4f6c30876dfa | 520 | * @retval None |
| Kojto | 107:4f6c30876dfa | 521 | */ |
| Kojto | 107:4f6c30876dfa | 522 | #define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_FALLING_EDGE() \ |
| Kojto | 107:4f6c30876dfa | 523 | do { \ |
| Kojto | 107:4f6c30876dfa | 524 | __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE(); \ |
| Kojto | 107:4f6c30876dfa | 525 | __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE(); \ |
| Kojto | 107:4f6c30876dfa | 526 | } while(0) |
| Kojto | 107:4f6c30876dfa | 527 | |
| Kojto | 107:4f6c30876dfa | 528 | /** |
| Kojto | 107:4f6c30876dfa | 529 | * @brief Disable the PVM3 Extended Interrupt Rising & Falling Trigger. |
| Kojto | 107:4f6c30876dfa | 530 | * @retval None |
| Kojto | 107:4f6c30876dfa | 531 | */ |
| Kojto | 107:4f6c30876dfa | 532 | #define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_FALLING_EDGE() \ |
| Kojto | 107:4f6c30876dfa | 533 | do { \ |
| Kojto | 107:4f6c30876dfa | 534 | __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE(); \ |
| Kojto | 107:4f6c30876dfa | 535 | __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE(); \ |
| Kojto | 107:4f6c30876dfa | 536 | } while(0) |
| Kojto | 107:4f6c30876dfa | 537 | |
| Kojto | 107:4f6c30876dfa | 538 | /** |
| Kojto | 107:4f6c30876dfa | 539 | * @brief Generate a Software interrupt on selected EXTI line. |
| Kojto | 107:4f6c30876dfa | 540 | * @retval None |
| Kojto | 107:4f6c30876dfa | 541 | */ |
| Kojto | 107:4f6c30876dfa | 542 | #define __HAL_PWR_PVM3_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM3) |
| Kojto | 107:4f6c30876dfa | 543 | |
| Kojto | 107:4f6c30876dfa | 544 | /** |
| Kojto | 107:4f6c30876dfa | 545 | * @brief Check whether the specified PVM3 EXTI interrupt flag is set or not. |
| Kojto | 107:4f6c30876dfa | 546 | * @retval EXTI PVM3 Line Status. |
| Kojto | 107:4f6c30876dfa | 547 | */ |
| Kojto | 107:4f6c30876dfa | 548 | #define __HAL_PWR_PVM3_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM3) |
| Kojto | 107:4f6c30876dfa | 549 | |
| Kojto | 107:4f6c30876dfa | 550 | /** |
| Kojto | 107:4f6c30876dfa | 551 | * @brief Clear the PVM3 EXTI flag. |
| Kojto | 107:4f6c30876dfa | 552 | * @retval None |
| Kojto | 107:4f6c30876dfa | 553 | */ |
| Kojto | 107:4f6c30876dfa | 554 | #define __HAL_PWR_PVM3_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM3) |
| Kojto | 107:4f6c30876dfa | 555 | |
| Kojto | 107:4f6c30876dfa | 556 | |
| Kojto | 107:4f6c30876dfa | 557 | |
| Kojto | 107:4f6c30876dfa | 558 | |
| Kojto | 107:4f6c30876dfa | 559 | /** |
| Kojto | 107:4f6c30876dfa | 560 | * @brief Enable the PVM4 Extended Interrupt Line. |
| Kojto | 107:4f6c30876dfa | 561 | * @retval None |
| Kojto | 107:4f6c30876dfa | 562 | */ |
| Kojto | 107:4f6c30876dfa | 563 | #define __HAL_PWR_PVM4_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4) |
| Kojto | 107:4f6c30876dfa | 564 | |
| Kojto | 107:4f6c30876dfa | 565 | /** |
| Kojto | 107:4f6c30876dfa | 566 | * @brief Disable the PVM4 Extended Interrupt Line. |
| Kojto | 107:4f6c30876dfa | 567 | * @retval None |
| Kojto | 107:4f6c30876dfa | 568 | */ |
| Kojto | 107:4f6c30876dfa | 569 | #define __HAL_PWR_PVM4_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4) |
| Kojto | 107:4f6c30876dfa | 570 | |
| Kojto | 107:4f6c30876dfa | 571 | /** |
| Kojto | 107:4f6c30876dfa | 572 | * @brief Enable the PVM4 Event Line. |
| Kojto | 107:4f6c30876dfa | 573 | * @retval None |
| Kojto | 107:4f6c30876dfa | 574 | */ |
| Kojto | 107:4f6c30876dfa | 575 | #define __HAL_PWR_PVM4_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4) |
| Kojto | 107:4f6c30876dfa | 576 | |
| Kojto | 107:4f6c30876dfa | 577 | /** |
| Kojto | 107:4f6c30876dfa | 578 | * @brief Disable the PVM4 Event Line. |
| Kojto | 107:4f6c30876dfa | 579 | * @retval None |
| Kojto | 107:4f6c30876dfa | 580 | */ |
| Kojto | 107:4f6c30876dfa | 581 | #define __HAL_PWR_PVM4_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4) |
| Kojto | 107:4f6c30876dfa | 582 | |
| Kojto | 107:4f6c30876dfa | 583 | /** |
| Kojto | 107:4f6c30876dfa | 584 | * @brief Enable the PVM4 Extended Interrupt Rising Trigger. |
| Kojto | 107:4f6c30876dfa | 585 | * @retval None |
| Kojto | 107:4f6c30876dfa | 586 | */ |
| Kojto | 107:4f6c30876dfa | 587 | #define __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4) |
| Kojto | 107:4f6c30876dfa | 588 | |
| Kojto | 107:4f6c30876dfa | 589 | /** |
| Kojto | 107:4f6c30876dfa | 590 | * @brief Disable the PVM4 Extended Interrupt Rising Trigger. |
| Kojto | 107:4f6c30876dfa | 591 | * @retval None |
| Kojto | 107:4f6c30876dfa | 592 | */ |
| Kojto | 107:4f6c30876dfa | 593 | #define __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4) |
| Kojto | 107:4f6c30876dfa | 594 | |
| Kojto | 107:4f6c30876dfa | 595 | /** |
| Kojto | 107:4f6c30876dfa | 596 | * @brief Enable the PVM4 Extended Interrupt Falling Trigger. |
| Kojto | 107:4f6c30876dfa | 597 | * @retval None |
| Kojto | 107:4f6c30876dfa | 598 | */ |
| Kojto | 107:4f6c30876dfa | 599 | #define __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4) |
| Kojto | 107:4f6c30876dfa | 600 | |
| Kojto | 107:4f6c30876dfa | 601 | |
| Kojto | 107:4f6c30876dfa | 602 | /** |
| Kojto | 107:4f6c30876dfa | 603 | * @brief Disable the PVM4 Extended Interrupt Falling Trigger. |
| Kojto | 107:4f6c30876dfa | 604 | * @retval None |
| Kojto | 107:4f6c30876dfa | 605 | */ |
| Kojto | 107:4f6c30876dfa | 606 | #define __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4) |
| Kojto | 107:4f6c30876dfa | 607 | |
| Kojto | 107:4f6c30876dfa | 608 | |
| Kojto | 107:4f6c30876dfa | 609 | /** |
| Kojto | 107:4f6c30876dfa | 610 | * @brief PVM4 EXTI line configuration: set rising & falling edge trigger. |
| Kojto | 107:4f6c30876dfa | 611 | * @retval None |
| Kojto | 107:4f6c30876dfa | 612 | */ |
| Kojto | 107:4f6c30876dfa | 613 | #define __HAL_PWR_PVM4_EXTI_ENABLE_RISING_FALLING_EDGE() \ |
| Kojto | 107:4f6c30876dfa | 614 | do { \ |
| Kojto | 107:4f6c30876dfa | 615 | __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE(); \ |
| Kojto | 107:4f6c30876dfa | 616 | __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE(); \ |
| Kojto | 107:4f6c30876dfa | 617 | } while(0) |
| Kojto | 107:4f6c30876dfa | 618 | |
| Kojto | 107:4f6c30876dfa | 619 | /** |
| Kojto | 107:4f6c30876dfa | 620 | * @brief Disable the PVM4 Extended Interrupt Rising & Falling Trigger. |
| Kojto | 107:4f6c30876dfa | 621 | * @retval None |
| Kojto | 107:4f6c30876dfa | 622 | */ |
| Kojto | 107:4f6c30876dfa | 623 | #define __HAL_PWR_PVM4_EXTI_DISABLE_RISING_FALLING_EDGE() \ |
| Kojto | 107:4f6c30876dfa | 624 | do { \ |
| Kojto | 107:4f6c30876dfa | 625 | __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE(); \ |
| Kojto | 107:4f6c30876dfa | 626 | __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE(); \ |
| Kojto | 107:4f6c30876dfa | 627 | } while(0) |
| Kojto | 107:4f6c30876dfa | 628 | |
| Kojto | 107:4f6c30876dfa | 629 | /** |
| Kojto | 107:4f6c30876dfa | 630 | * @brief Generate a Software interrupt on selected EXTI line. |
| Kojto | 107:4f6c30876dfa | 631 | * @retval None |
| Kojto | 107:4f6c30876dfa | 632 | */ |
| Kojto | 107:4f6c30876dfa | 633 | #define __HAL_PWR_PVM4_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM4) |
| Kojto | 107:4f6c30876dfa | 634 | |
| Kojto | 107:4f6c30876dfa | 635 | /** |
| Kojto | 107:4f6c30876dfa | 636 | * @brief Check whether or not the specified PVM4 EXTI interrupt flag is set. |
| Kojto | 107:4f6c30876dfa | 637 | * @retval EXTI PVM4 Line Status. |
| Kojto | 107:4f6c30876dfa | 638 | */ |
| Kojto | 107:4f6c30876dfa | 639 | #define __HAL_PWR_PVM4_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM4) |
| Kojto | 107:4f6c30876dfa | 640 | |
| Kojto | 107:4f6c30876dfa | 641 | /** |
| Kojto | 107:4f6c30876dfa | 642 | * @brief Clear the PVM4 EXTI flag. |
| Kojto | 107:4f6c30876dfa | 643 | * @retval None |
| Kojto | 107:4f6c30876dfa | 644 | */ |
| Kojto | 107:4f6c30876dfa | 645 | #define __HAL_PWR_PVM4_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM4) |
| Kojto | 107:4f6c30876dfa | 646 | |
| Kojto | 107:4f6c30876dfa | 647 | |
| Kojto | 107:4f6c30876dfa | 648 | /** |
| Kojto | 107:4f6c30876dfa | 649 | * @brief Configure the main internal regulator output voltage. |
| Kojto | 107:4f6c30876dfa | 650 | * @param __REGULATOR__: specifies the regulator output voltage to achieve |
| Kojto | 107:4f6c30876dfa | 651 | * a tradeoff between performance and power consumption. |
| Kojto | 107:4f6c30876dfa | 652 | * This parameter can be one of the following values: |
| Kojto | 107:4f6c30876dfa | 653 | * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode, |
| Kojto | 107:4f6c30876dfa | 654 | * typical output voltage at 1.2 V, |
| Kojto | 107:4f6c30876dfa | 655 | * system frequency up to 80 MHz. |
| Kojto | 107:4f6c30876dfa | 656 | * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode, |
| Kojto | 107:4f6c30876dfa | 657 | * typical output voltage at 1.0 V, |
| Kojto | 107:4f6c30876dfa | 658 | * system frequency up to 26 MHz. |
| Kojto | 107:4f6c30876dfa | 659 | * @note This macro is similar to HAL_PWREx_ControlVoltageScaling() API but doesn't check |
| Kojto | 107:4f6c30876dfa | 660 | * whether or not VOSF flag is cleared when moving from range 2 to range 1. User |
| Kojto | 107:4f6c30876dfa | 661 | * may resort to __HAL_PWR_GET_FLAG() macro to check VOSF bit resetting. |
| Kojto | 107:4f6c30876dfa | 662 | * @retval None |
| Kojto | 107:4f6c30876dfa | 663 | */ |
| Kojto | 107:4f6c30876dfa | 664 | #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \ |
| Kojto | 107:4f6c30876dfa | 665 | __IO uint32_t tmpreg; \ |
| Kojto | 107:4f6c30876dfa | 666 | MODIFY_REG(PWR->CR1, PWR_CR1_VOS, (__REGULATOR__)); \ |
| Kojto | 107:4f6c30876dfa | 667 | /* Delay after an RCC peripheral clock enabling */ \ |
| Kojto | 107:4f6c30876dfa | 668 | tmpreg = READ_BIT(PWR->CR1, PWR_CR1_VOS); \ |
| Kojto | 107:4f6c30876dfa | 669 | UNUSED(tmpreg); \ |
| Kojto | 107:4f6c30876dfa | 670 | } while(0) |
| Kojto | 107:4f6c30876dfa | 671 | |
| Kojto | 107:4f6c30876dfa | 672 | /** |
| Kojto | 107:4f6c30876dfa | 673 | * @} |
| Kojto | 107:4f6c30876dfa | 674 | */ |
| Kojto | 107:4f6c30876dfa | 675 | |
| Kojto | 107:4f6c30876dfa | 676 | /* Private macros --------------------------------------------------------*/ |
| Kojto | 107:4f6c30876dfa | 677 | /** @addtogroup PWREx_Private_Macros PWR Extended Private Macros |
| Kojto | 107:4f6c30876dfa | 678 | * @{ |
| Kojto | 107:4f6c30876dfa | 679 | */ |
| Kojto | 107:4f6c30876dfa | 680 | |
| Kojto | 107:4f6c30876dfa | 681 | #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ |
| Kojto | 107:4f6c30876dfa | 682 | ((PIN) == PWR_WAKEUP_PIN2) || \ |
| Kojto | 107:4f6c30876dfa | 683 | ((PIN) == PWR_WAKEUP_PIN3) || \ |
| Kojto | 107:4f6c30876dfa | 684 | ((PIN) == PWR_WAKEUP_PIN4) || \ |
| Kojto | 107:4f6c30876dfa | 685 | ((PIN) == PWR_WAKEUP_PIN5) || \ |
| Kojto | 107:4f6c30876dfa | 686 | ((PIN) == PWR_WAKEUP_PIN1_HIGH) || \ |
| Kojto | 107:4f6c30876dfa | 687 | ((PIN) == PWR_WAKEUP_PIN2_HIGH) || \ |
| Kojto | 107:4f6c30876dfa | 688 | ((PIN) == PWR_WAKEUP_PIN3_HIGH) || \ |
| Kojto | 107:4f6c30876dfa | 689 | ((PIN) == PWR_WAKEUP_PIN4_HIGH) || \ |
| Kojto | 107:4f6c30876dfa | 690 | ((PIN) == PWR_WAKEUP_PIN5_HIGH) || \ |
| Kojto | 107:4f6c30876dfa | 691 | ((PIN) == PWR_WAKEUP_PIN1_LOW) || \ |
| Kojto | 107:4f6c30876dfa | 692 | ((PIN) == PWR_WAKEUP_PIN2_LOW) || \ |
| Kojto | 107:4f6c30876dfa | 693 | ((PIN) == PWR_WAKEUP_PIN3_LOW) || \ |
| Kojto | 107:4f6c30876dfa | 694 | ((PIN) == PWR_WAKEUP_PIN4_LOW) || \ |
| Kojto | 107:4f6c30876dfa | 695 | ((PIN) == PWR_WAKEUP_PIN5_LOW)) |
| Kojto | 107:4f6c30876dfa | 696 | |
| Kojto | 107:4f6c30876dfa | 697 | #define IS_PWR_PVM_TYPE(TYPE) (((TYPE) & PWR_CR2_PVME) != RESET) |
| Kojto | 107:4f6c30876dfa | 698 | |
| Kojto | 107:4f6c30876dfa | 699 | #define IS_PWR_PVM_MODE(MODE) (((MODE) == PWR_PVM_MODE_NORMAL) ||\ |
| Kojto | 107:4f6c30876dfa | 700 | ((MODE) == PWR_PVM_MODE_IT_RISING) ||\ |
| Kojto | 107:4f6c30876dfa | 701 | ((MODE) == PWR_PVM_MODE_IT_FALLING) ||\ |
| Kojto | 107:4f6c30876dfa | 702 | ((MODE) == PWR_PVM_MODE_IT_RISING_FALLING) ||\ |
| Kojto | 107:4f6c30876dfa | 703 | ((MODE) == PWR_PVM_MODE_EVENT_RISING) ||\ |
| Kojto | 107:4f6c30876dfa | 704 | ((MODE) == PWR_PVM_MODE_EVENT_FALLING) ||\ |
| Kojto | 107:4f6c30876dfa | 705 | ((MODE) == PWR_PVM_MODE_EVENT_RISING_FALLING)) |
| Kojto | 107:4f6c30876dfa | 706 | |
| Kojto | 107:4f6c30876dfa | 707 | #define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ |
| Kojto | 107:4f6c30876dfa | 708 | ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2)) |
| Kojto | 107:4f6c30876dfa | 709 | |
| Kojto | 107:4f6c30876dfa | 710 | #define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\ |
| Kojto | 107:4f6c30876dfa | 711 | ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5)) |
| Kojto | 107:4f6c30876dfa | 712 | |
| Kojto | 107:4f6c30876dfa | 713 | #define IS_PWR_BATTERY_CHARGING(CHARGING) (((CHARGING) == PWR_BATTERY_CHARGING_DISABLE) ||\ |
| Kojto | 107:4f6c30876dfa | 714 | ((CHARGING) == PWR_BATTERY_CHARGING_ENABLE)) |
| Kojto | 107:4f6c30876dfa | 715 | |
| Kojto | 107:4f6c30876dfa | 716 | #define IS_PWR_GPIO_BIT_NUMBER(BIT_NUMBER) (((BIT_NUMBER) == PWR_GPIO_BIT_0) ||\ |
| Kojto | 107:4f6c30876dfa | 717 | ((BIT_NUMBER) == PWR_GPIO_BIT_1) ||\ |
| Kojto | 107:4f6c30876dfa | 718 | ((BIT_NUMBER) == PWR_GPIO_BIT_2) ||\ |
| Kojto | 107:4f6c30876dfa | 719 | ((BIT_NUMBER) == PWR_GPIO_BIT_3) ||\ |
| Kojto | 107:4f6c30876dfa | 720 | ((BIT_NUMBER) == PWR_GPIO_BIT_4) ||\ |
| Kojto | 107:4f6c30876dfa | 721 | ((BIT_NUMBER) == PWR_GPIO_BIT_5) ||\ |
| Kojto | 107:4f6c30876dfa | 722 | ((BIT_NUMBER) == PWR_GPIO_BIT_6) ||\ |
| Kojto | 107:4f6c30876dfa | 723 | ((BIT_NUMBER) == PWR_GPIO_BIT_7) ||\ |
| Kojto | 107:4f6c30876dfa | 724 | ((BIT_NUMBER) == PWR_GPIO_BIT_8) ||\ |
| Kojto | 107:4f6c30876dfa | 725 | ((BIT_NUMBER) == PWR_GPIO_BIT_9) ||\ |
| Kojto | 107:4f6c30876dfa | 726 | ((BIT_NUMBER) == PWR_GPIO_BIT_10) ||\ |
| Kojto | 107:4f6c30876dfa | 727 | ((BIT_NUMBER) == PWR_GPIO_BIT_11) ||\ |
| Kojto | 107:4f6c30876dfa | 728 | ((BIT_NUMBER) == PWR_GPIO_BIT_12) ||\ |
| Kojto | 107:4f6c30876dfa | 729 | ((BIT_NUMBER) == PWR_GPIO_BIT_13) ||\ |
| Kojto | 107:4f6c30876dfa | 730 | ((BIT_NUMBER) == PWR_GPIO_BIT_14) ||\ |
| Kojto | 107:4f6c30876dfa | 731 | ((BIT_NUMBER) == PWR_GPIO_BIT_15)) |
| Kojto | 107:4f6c30876dfa | 732 | |
| Kojto | 107:4f6c30876dfa | 733 | #define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\ |
| Kojto | 107:4f6c30876dfa | 734 | ((GPIO) == PWR_GPIO_B) ||\ |
| Kojto | 107:4f6c30876dfa | 735 | ((GPIO) == PWR_GPIO_C) ||\ |
| Kojto | 107:4f6c30876dfa | 736 | ((GPIO) == PWR_GPIO_D) ||\ |
| Kojto | 107:4f6c30876dfa | 737 | ((GPIO) == PWR_GPIO_E) ||\ |
| Kojto | 107:4f6c30876dfa | 738 | ((GPIO) == PWR_GPIO_F) ||\ |
| Kojto | 107:4f6c30876dfa | 739 | ((GPIO) == PWR_GPIO_G) ||\ |
| Kojto | 107:4f6c30876dfa | 740 | ((GPIO) == PWR_GPIO_H)) |
| Kojto | 107:4f6c30876dfa | 741 | |
| Kojto | 107:4f6c30876dfa | 742 | /** |
| Kojto | 107:4f6c30876dfa | 743 | * @} |
| Kojto | 107:4f6c30876dfa | 744 | */ |
| Kojto | 107:4f6c30876dfa | 745 | |
| Kojto | 107:4f6c30876dfa | 746 | |
| Kojto | 107:4f6c30876dfa | 747 | /** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions |
| Kojto | 107:4f6c30876dfa | 748 | * @{ |
| Kojto | 107:4f6c30876dfa | 749 | */ |
| Kojto | 107:4f6c30876dfa | 750 | |
| Kojto | 107:4f6c30876dfa | 751 | /** @addtogroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions |
| Kojto | 107:4f6c30876dfa | 752 | * @{ |
| Kojto | 107:4f6c30876dfa | 753 | */ |
| Kojto | 107:4f6c30876dfa | 754 | |
| Kojto | 107:4f6c30876dfa | 755 | |
| Kojto | 107:4f6c30876dfa | 756 | /* Peripheral Control functions **********************************************/ |
| Kojto | 107:4f6c30876dfa | 757 | uint32_t HAL_PWREx_GetVoltageRange(void); |
| Kojto | 107:4f6c30876dfa | 758 | HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling); |
| Kojto | 107:4f6c30876dfa | 759 | void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection); |
| Kojto | 107:4f6c30876dfa | 760 | void HAL_PWREx_DisableBatteryCharging(void); |
| Kojto | 107:4f6c30876dfa | 761 | #if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) |
| Kojto | 107:4f6c30876dfa | 762 | void HAL_PWREx_EnableVddUSB(void); |
| Kojto | 107:4f6c30876dfa | 763 | void HAL_PWREx_DisableVddUSB(void); |
| Kojto | 107:4f6c30876dfa | 764 | #endif /* defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */ |
| Kojto | 107:4f6c30876dfa | 765 | void HAL_PWREx_EnableVddIO2(void); |
| Kojto | 107:4f6c30876dfa | 766 | void HAL_PWREx_DisableVddIO2(void); |
| Kojto | 107:4f6c30876dfa | 767 | void HAL_PWREx_EnableInternalWakeUpLine(void); |
| Kojto | 107:4f6c30876dfa | 768 | void HAL_PWREx_DisableInternalWakeUpLine(void); |
| Kojto | 107:4f6c30876dfa | 769 | HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber); |
| Kojto | 107:4f6c30876dfa | 770 | HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber); |
| Kojto | 107:4f6c30876dfa | 771 | HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber); |
| Kojto | 107:4f6c30876dfa | 772 | HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber); |
| Kojto | 107:4f6c30876dfa | 773 | void HAL_PWREx_EnablePullUpPullDownConfig(void); |
| Kojto | 107:4f6c30876dfa | 774 | void HAL_PWREx_DisablePullUpPullDownConfig(void); |
| Kojto | 107:4f6c30876dfa | 775 | void HAL_PWREx_EnableSRAM2ContentRetention(void); |
| Kojto | 107:4f6c30876dfa | 776 | void HAL_PWREx_DisableSRAM2ContentRetention(void); |
| Kojto | 107:4f6c30876dfa | 777 | #if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) |
| Kojto | 107:4f6c30876dfa | 778 | void HAL_PWREx_EnablePVM1(void); |
| Kojto | 107:4f6c30876dfa | 779 | void HAL_PWREx_DisablePVM1(void); |
| Kojto | 107:4f6c30876dfa | 780 | #endif /* defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */ |
| Kojto | 107:4f6c30876dfa | 781 | void HAL_PWREx_EnablePVM2(void); |
| Kojto | 107:4f6c30876dfa | 782 | void HAL_PWREx_DisablePVM2(void); |
| Kojto | 107:4f6c30876dfa | 783 | void HAL_PWREx_EnablePVM3(void); |
| Kojto | 107:4f6c30876dfa | 784 | void HAL_PWREx_DisablePVM3(void); |
| Kojto | 107:4f6c30876dfa | 785 | void HAL_PWREx_EnablePVM4(void); |
| Kojto | 107:4f6c30876dfa | 786 | void HAL_PWREx_DisablePVM4(void); |
| Kojto | 107:4f6c30876dfa | 787 | HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM); |
| Kojto | 107:4f6c30876dfa | 788 | |
| Kojto | 107:4f6c30876dfa | 789 | |
| Kojto | 107:4f6c30876dfa | 790 | /* Low Power modes configuration functions ************************************/ |
| Kojto | 107:4f6c30876dfa | 791 | void HAL_PWREx_EnableLowPowerRunMode(void); |
| Kojto | 107:4f6c30876dfa | 792 | HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void); |
| Kojto | 107:4f6c30876dfa | 793 | void HAL_PWREx_EnterSTOP1Mode(uint32_t Regulator, uint8_t STOPEntry); |
| Kojto | 107:4f6c30876dfa | 794 | void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry); |
| Kojto | 107:4f6c30876dfa | 795 | void HAL_PWREx_EnterSHUTDOWNMode(void); |
| Kojto | 107:4f6c30876dfa | 796 | |
| Kojto | 107:4f6c30876dfa | 797 | void HAL_PWREx_PVD_PVM_IRQHandler(void); |
| Kojto | 107:4f6c30876dfa | 798 | #if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) |
| Kojto | 107:4f6c30876dfa | 799 | void HAL_PWREx_PVM1Callback(void); |
| Kojto | 107:4f6c30876dfa | 800 | #endif /* defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */ |
| Kojto | 107:4f6c30876dfa | 801 | void HAL_PWREx_PVM2Callback(void); |
| Kojto | 107:4f6c30876dfa | 802 | void HAL_PWREx_PVM3Callback(void); |
| Kojto | 107:4f6c30876dfa | 803 | void HAL_PWREx_PVM4Callback(void); |
| Kojto | 107:4f6c30876dfa | 804 | |
| Kojto | 107:4f6c30876dfa | 805 | |
| Kojto | 107:4f6c30876dfa | 806 | /** |
| Kojto | 107:4f6c30876dfa | 807 | * @} |
| Kojto | 107:4f6c30876dfa | 808 | */ |
| Kojto | 107:4f6c30876dfa | 809 | |
| Kojto | 107:4f6c30876dfa | 810 | /** |
| Kojto | 107:4f6c30876dfa | 811 | * @} |
| Kojto | 107:4f6c30876dfa | 812 | */ |
| Kojto | 107:4f6c30876dfa | 813 | |
| Kojto | 107:4f6c30876dfa | 814 | /** |
| Kojto | 107:4f6c30876dfa | 815 | * @} |
| Kojto | 107:4f6c30876dfa | 816 | */ |
| Kojto | 107:4f6c30876dfa | 817 | |
| Kojto | 107:4f6c30876dfa | 818 | /** |
| Kojto | 107:4f6c30876dfa | 819 | * @} |
| Kojto | 107:4f6c30876dfa | 820 | */ |
| Kojto | 107:4f6c30876dfa | 821 | |
| Kojto | 107:4f6c30876dfa | 822 | #ifdef __cplusplus |
| Kojto | 107:4f6c30876dfa | 823 | } |
| Kojto | 107:4f6c30876dfa | 824 | #endif |
| Kojto | 107:4f6c30876dfa | 825 | |
| Kojto | 107:4f6c30876dfa | 826 | |
| Kojto | 107:4f6c30876dfa | 827 | #endif /* __STM32L4xx_HAL_PWR_EX_H */ |
| Kojto | 107:4f6c30876dfa | 828 | |
| Kojto | 107:4f6c30876dfa | 829 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |