Elijah Orr / mbed-renbed

Important changes to repositories hosted on mbed.com

Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.

To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.

It is also possible to export all your personal repositories from the account settings page.

Dependents:   1-RenBuggyTimed RenBED_RGB RenBED_RGB_PWM RenBED_RGB

Fork of mbed by mbed official

TARGET_MAX32600MBED/ioman_regs.h@121:672067c3ada4, 2016-04-14 (annotated)

Committer:
elijahorr
Date:
Thu Apr 14 07:28:54 2016 +0000
Revision:
121:672067c3ada4
Parent:
101:7cff1c4259d7 
.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 101:7cff1c4259d7 1 /*******************************************************************************
Kojto 101:7cff1c4259d7 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
Kojto 101:7cff1c4259d7 3 *
Kojto 101:7cff1c4259d7 4 * Permission is hereby granted, free of charge, to any person obtaining a
Kojto 101:7cff1c4259d7 5 * copy of this software and associated documentation files (the "Software"),
Kojto 101:7cff1c4259d7 6 * to deal in the Software without restriction, including without limitation
Kojto 101:7cff1c4259d7 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
Kojto 101:7cff1c4259d7 8 * and/or sell copies of the Software, and to permit persons to whom the
Kojto 101:7cff1c4259d7 9 * Software is furnished to do so, subject to the following conditions:
Kojto 101:7cff1c4259d7 10 *
Kojto 101:7cff1c4259d7 11 * The above copyright notice and this permission notice shall be included
Kojto 101:7cff1c4259d7 12 * in all copies or substantial portions of the Software.
Kojto 101:7cff1c4259d7 13 *
Kojto 101:7cff1c4259d7 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
Kojto 101:7cff1c4259d7 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
Kojto 101:7cff1c4259d7 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
Kojto 101:7cff1c4259d7 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
Kojto 101:7cff1c4259d7 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
Kojto 101:7cff1c4259d7 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
Kojto 101:7cff1c4259d7 20 * OTHER DEALINGS IN THE SOFTWARE.
Kojto 101:7cff1c4259d7 21 *
Kojto 101:7cff1c4259d7 22 * Except as contained in this notice, the name of Maxim Integrated
Kojto 101:7cff1c4259d7 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
Kojto 101:7cff1c4259d7 24 * Products, Inc. Branding Policy.
Kojto 101:7cff1c4259d7 25 *
Kojto 101:7cff1c4259d7 26 * The mere transfer of this software does not imply any licenses
Kojto 101:7cff1c4259d7 27 * of trade secrets, proprietary technology, copyrights, patents,
Kojto 101:7cff1c4259d7 28 * trademarks, maskwork rights, or any other form of intellectual
Kojto 101:7cff1c4259d7 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
Kojto 101:7cff1c4259d7 30 * ownership rights.
Kojto 101:7cff1c4259d7 31 *******************************************************************************
Kojto 101:7cff1c4259d7 32 */
Kojto 101:7cff1c4259d7 33
Kojto 101:7cff1c4259d7 34 #ifndef _MXC_IOMAN_REGS_H_
Kojto 101:7cff1c4259d7 35 #define _MXC_IOMAN_REGS_H_
Kojto 101:7cff1c4259d7 36
Kojto 101:7cff1c4259d7 37 #ifdef __cplusplus
Kojto 101:7cff1c4259d7 38 extern "C" {
Kojto 101:7cff1c4259d7 39 #endif
Kojto 101:7cff1c4259d7 40
Kojto 101:7cff1c4259d7 41 #include <stdint.h>
Kojto 101:7cff1c4259d7 42
Kojto 101:7cff1c4259d7 43 /**
Kojto 101:7cff1c4259d7 44 * @file ioman_regs.h
Kojto 101:7cff1c4259d7 45 * @addtogroup ioman IO MUX Manager
Kojto 101:7cff1c4259d7 46 * @{
Kojto 101:7cff1c4259d7 47 */
Kojto 101:7cff1c4259d7 48
Kojto 101:7cff1c4259d7 49 typedef enum {
Kojto 101:7cff1c4259d7 50 /** Pin Mapping 'A' */
Kojto 101:7cff1c4259d7 51 MXC_E_IOMAN_MAPPING_A = 0,
Kojto 101:7cff1c4259d7 52 /** Pin Mapping 'B' */
Kojto 101:7cff1c4259d7 53 MXC_E_IOMAN_MAPPING_B,
Kojto 101:7cff1c4259d7 54 /** Pin Mapping 'C' */
Kojto 101:7cff1c4259d7 55 MXC_E_IOMAN_MAPPING_C,
Kojto 101:7cff1c4259d7 56 /** Pin Mapping 'D' */
Kojto 101:7cff1c4259d7 57 MXC_E_IOMAN_MAPPING_D,
Kojto 101:7cff1c4259d7 58 /** Pin Mapping 'E' */
Kojto 101:7cff1c4259d7 59 MXC_E_IOMAN_MAPPING_E,
Kojto 101:7cff1c4259d7 60 /** Pin Mapping 'F' */
Kojto 101:7cff1c4259d7 61 MXC_E_IOMAN_MAPPING_F,
Kojto 101:7cff1c4259d7 62 /** Pin Mapping 'G' */
Kojto 101:7cff1c4259d7 63 MXC_E_IOMAN_MAPPING_G,
Kojto 101:7cff1c4259d7 64 /** Pin Mapping 'H' */
Kojto 101:7cff1c4259d7 65 MXC_E_IOMAN_MAPPING_H,
Kojto 101:7cff1c4259d7 66 } ioman_mapping_t;
Kojto 101:7cff1c4259d7 67
Kojto 101:7cff1c4259d7 68 /* Offset Register Description
Kojto 101:7cff1c4259d7 69 ====== ========================================== */
Kojto 101:7cff1c4259d7 70 typedef struct {
Kojto 101:7cff1c4259d7 71 __IO uint32_t wud_req0; /* 0x0000 Wakeup Detect Mode Request Register 0 */
Kojto 101:7cff1c4259d7 72 __IO uint32_t wud_req1; /* 0x0004 Wakeup Detect Mode Request Register 1 */
Kojto 101:7cff1c4259d7 73 __IO uint32_t wud_ack0; /* 0x0008 Wakeup Detect Mode Acknowledge Register 0 */
Kojto 101:7cff1c4259d7 74 __IO uint32_t wud_ack1; /* 0x000C Wakeup Detect Mode Acknowledge Register 1 */
Kojto 101:7cff1c4259d7 75 __IO uint32_t ali_req0; /* 0x0010 Analog Input Request Register 0 */
Kojto 101:7cff1c4259d7 76 __IO uint32_t ali_req1; /* 0x0014 Analog Input Request Register 1 */
Kojto 101:7cff1c4259d7 77 __IO uint32_t ali_ack0; /* 0x0018 Analog Input Acknowledge Register 0 */
Kojto 101:7cff1c4259d7 78 __IO uint32_t ali_ack1; /* 0x001C Analog Input Acknowledge Register 1 */
Kojto 101:7cff1c4259d7 79 __IO uint32_t spi0_req; /* 0x0020 SPI0 I/O Mode Request */
Kojto 101:7cff1c4259d7 80 __IO uint32_t spi0_ack; /* 0x0024 SPI0 I/O Mode Acknowledge */
Kojto 101:7cff1c4259d7 81 __IO uint32_t spi1_req; /* 0x0028 SPI1 I/O Mode Request */
Kojto 101:7cff1c4259d7 82 __IO uint32_t spi1_ack; /* 0x002C SPI1 I/O Mode Acknowledge */
Kojto 101:7cff1c4259d7 83 __IO uint32_t spi2_req; /* 0x0030 SPI2 I/O Mode Request */
Kojto 101:7cff1c4259d7 84 __IO uint32_t spi2_ack; /* 0x0034 SPI2 I/O Mode Acknowledge */
Kojto 101:7cff1c4259d7 85 __IO uint32_t uart0_req; /* 0x0038 UART0 I/O Mode Request */
Kojto 101:7cff1c4259d7 86 __IO uint32_t uart0_ack; /* 0x003C UART0 I/O Mode Acknowledge */
Kojto 101:7cff1c4259d7 87 __IO uint32_t uart1_req; /* 0x0040 UART1 I/O Mode Request */
Kojto 101:7cff1c4259d7 88 __IO uint32_t uart1_ack; /* 0x0044 UART1 I/O Mode Acknowledge */
Kojto 101:7cff1c4259d7 89 __IO uint32_t i2cm0_req; /* 0x0048 I2C Master 0 I/O Request */
Kojto 101:7cff1c4259d7 90 __IO uint32_t i2cm0_ack; /* 0x004C I2C Master 0 I/O Acknowledge */
Kojto 101:7cff1c4259d7 91 __IO uint32_t i2cs0_req; /* 0x0050 I2C Slave 0 I/O Request */
Kojto 101:7cff1c4259d7 92 __IO uint32_t i2s0_ack; /* 0x0054 I2C Slave 0 I/O Acknowledge */
Kojto 101:7cff1c4259d7 93 __IO uint32_t lcd_com_req; /* 0x0058 LCD COM Driver I/O Request */
Kojto 101:7cff1c4259d7 94 __IO uint32_t lcd_com_ack; /* 0x005C LCD COM Driver I/O Acknowledge */
Kojto 101:7cff1c4259d7 95 __IO uint32_t lcd_seg_req0; /* 0x0060 LCD SEG Driver I/O Request Register 0 */
Kojto 101:7cff1c4259d7 96 __IO uint32_t lcd_seg_req1; /* 0x0064 LCD SEG Driver I/O Request Register 1 */
Kojto 101:7cff1c4259d7 97 __IO uint32_t lcd_seg_ack0; /* 0x0068 LCD SEG Driver I/O Acknowledge Register 0 */
Kojto 101:7cff1c4259d7 98 __IO uint32_t lcd_seg_ack1; /* 0x006C LCD SEG Driver I/O Acknowledge Register 1 */
Kojto 101:7cff1c4259d7 99 __IO uint32_t crnt_req; /* 0x0070 Current Drive I/O Request Register */
Kojto 101:7cff1c4259d7 100 __IO uint32_t io_crnt_ack; /* 0x0074 Current Drive I/O Acknowledge Register */
Kojto 101:7cff1c4259d7 101 __IO uint32_t crnt_mode; /* 0x0078 Current Drive I/O Mode Control */
Kojto 101:7cff1c4259d7 102 __IO uint32_t ali_connect0; /* 0x007C Analog I/O Connection Control Register 0 */
Kojto 101:7cff1c4259d7 103 __IO uint32_t ali_connect1; /* 0x0080 Analog I/O Connection Control Register 1 */
Kojto 101:7cff1c4259d7 104 __IO uint32_t i2cm1_req; /* 0x0084 I2C Master 1 I/O Request */
Kojto 101:7cff1c4259d7 105 __IO uint32_t i2cm1_ack; /* 0x0088 I2C Master 1 I/O Acknowledge */
Kojto 101:7cff1c4259d7 106 __IO uint32_t padx_control; /* 0x008C PADX Control */
Kojto 101:7cff1c4259d7 107 } mxc_ioman_regs_t;
Kojto 101:7cff1c4259d7 108
Kojto 101:7cff1c4259d7 109
Kojto 101:7cff1c4259d7 110 /*
Kojto 101:7cff1c4259d7 111 Register offsets for module IOMAN.
Kojto 101:7cff1c4259d7 112 */
Kojto 101:7cff1c4259d7 113 #define MXC_R_IOMAN_OFFS_WUD_REQ0 ((uint32_t)0x00000000UL)
Kojto 101:7cff1c4259d7 114 #define MXC_R_IOMAN_OFFS_WUD_REQ1 ((uint32_t)0x00000004UL)
Kojto 101:7cff1c4259d7 115 #define MXC_R_IOMAN_OFFS_WUD_ACK0 ((uint32_t)0x00000008UL)
Kojto 101:7cff1c4259d7 116 #define MXC_R_IOMAN_OFFS_WUD_ACK1 ((uint32_t)0x0000000CUL)
Kojto 101:7cff1c4259d7 117 #define MXC_R_IOMAN_OFFS_ALI_REQ0 ((uint32_t)0x00000010UL)
Kojto 101:7cff1c4259d7 118 #define MXC_R_IOMAN_OFFS_ALI_REQ1 ((uint32_t)0x00000014UL)
Kojto 101:7cff1c4259d7 119 #define MXC_R_IOMAN_OFFS_ALI_ACK0 ((uint32_t)0x00000018UL)
Kojto 101:7cff1c4259d7 120 #define MXC_R_IOMAN_OFFS_ALI_ACK1 ((uint32_t)0x0000001CUL)
Kojto 101:7cff1c4259d7 121 #define MXC_R_IOMAN_OFFS_SPI0_REQ ((uint32_t)0x00000020UL)
Kojto 101:7cff1c4259d7 122 #define MXC_R_IOMAN_OFFS_SPI0_ACK ((uint32_t)0x00000024UL)
Kojto 101:7cff1c4259d7 123 #define MXC_R_IOMAN_OFFS_SPI1_REQ ((uint32_t)0x00000028UL)
Kojto 101:7cff1c4259d7 124 #define MXC_R_IOMAN_OFFS_SPI1_ACK ((uint32_t)0x0000002CUL)
Kojto 101:7cff1c4259d7 125 #define MXC_R_IOMAN_OFFS_SPI2_REQ ((uint32_t)0x00000030UL)
Kojto 101:7cff1c4259d7 126 #define MXC_R_IOMAN_OFFS_SPI2_ACK ((uint32_t)0x00000034UL)
Kojto 101:7cff1c4259d7 127 #define MXC_R_IOMAN_OFFS_UART0_REQ ((uint32_t)0x00000038UL)
Kojto 101:7cff1c4259d7 128 #define MXC_R_IOMAN_OFFS_UART0_ACK ((uint32_t)0x0000003CUL)
Kojto 101:7cff1c4259d7 129 #define MXC_R_IOMAN_OFFS_UART1_REQ ((uint32_t)0x00000040UL)
Kojto 101:7cff1c4259d7 130 #define MXC_R_IOMAN_OFFS_UART1_ACK ((uint32_t)0x00000044UL)
Kojto 101:7cff1c4259d7 131 #define MXC_R_IOMAN_OFFS_I2CM0_REQ ((uint32_t)0x00000048UL)
Kojto 101:7cff1c4259d7 132 #define MXC_R_IOMAN_OFFS_I2CM0_ACK ((uint32_t)0x0000004CUL)
Kojto 101:7cff1c4259d7 133 #define MXC_R_IOMAN_OFFS_I2CS0_REQ ((uint32_t)0x00000050UL)
Kojto 101:7cff1c4259d7 134 #define MXC_R_IOMAN_OFFS_I2SC0_ACK ((uint32_t)0x00000054UL)
Kojto 101:7cff1c4259d7 135 #define MXC_R_IOMAN_OFFS_LCD_COM_REQ ((uint32_t)0x00000058UL)
Kojto 101:7cff1c4259d7 136 #define MXC_R_IOMAN_OFFS_LCD_COM_ACK ((uint32_t)0x0000005CUL)
Kojto 101:7cff1c4259d7 137 #define MXC_R_IOMAN_OFFS_LCD_SEG_REQ0 ((uint32_t)0x00000060UL)
Kojto 101:7cff1c4259d7 138 #define MXC_R_IOMAN_OFFS_LCD_SEG_REQ1 ((uint32_t)0x00000064UL)
Kojto 101:7cff1c4259d7 139 #define MXC_R_IOMAN_OFFS_LCD_SEG_ACK0 ((uint32_t)0x00000068UL)
Kojto 101:7cff1c4259d7 140 #define MXC_R_IOMAN_OFFS_LCD_SEG_ACK1 ((uint32_t)0x0000006CUL)
Kojto 101:7cff1c4259d7 141 #define MXC_R_IOMAN_OFFS_IO_CRNT_REQ ((uint32_t)0x00000070UL)
Kojto 101:7cff1c4259d7 142 #define MXC_R_IOMAN_OFFS_IO_CRNT_ACK ((uint32_t)0x00000074UL)
Kojto 101:7cff1c4259d7 143 #define MXC_R_IOMAN_OFFS_IO_CRNT_MODE ((uint32_t)0x00000078UL)
Kojto 101:7cff1c4259d7 144 #define MXC_R_IOMAN_OFFS_ALI_CONNECT0 ((uint32_t)0x0000007CUL)
Kojto 101:7cff1c4259d7 145 #define MXC_R_IOMAN_OFFS_ALI_CONNECT1 ((uint32_t)0x00000080UL)
Kojto 101:7cff1c4259d7 146 #define MXC_R_IOMAN_OFFS_I2CM1_REQ ((uint32_t)0x00000084UL)
Kojto 101:7cff1c4259d7 147 #define MXC_R_IOMAN_OFFS_I2CM1_ACK ((uint32_t)0x00000088UL)
Kojto 101:7cff1c4259d7 148 #define MXC_R_IOMAN_OFFS_PADX_CONTROL ((uint32_t)0x0000008CUL)
Kojto 101:7cff1c4259d7 149
Kojto 101:7cff1c4259d7 150
Kojto 101:7cff1c4259d7 151 /*
Kojto 101:7cff1c4259d7 152 Field positions and masks for module IOMAN.
Kojto 101:7cff1c4259d7 153 */
Kojto 101:7cff1c4259d7 154 #define MXC_F_IOMAN_WUD_REQ0_PORT0_POS 0
Kojto 101:7cff1c4259d7 155 #define MXC_F_IOMAN_WUD_REQ0_PORT0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_PORT0_POS))
Kojto 101:7cff1c4259d7 156 #define MXC_F_IOMAN_WUD_REQ0_PORT1_POS 8
Kojto 101:7cff1c4259d7 157 #define MXC_F_IOMAN_WUD_REQ0_PORT1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_PORT1_POS))
Kojto 101:7cff1c4259d7 158 #define MXC_F_IOMAN_WUD_REQ0_PORT2_POS 16
Kojto 101:7cff1c4259d7 159 #define MXC_F_IOMAN_WUD_REQ0_PORT2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_PORT2_POS))
Kojto 101:7cff1c4259d7 160 #define MXC_F_IOMAN_WUD_REQ0_PORT3_POS 24
Kojto 101:7cff1c4259d7 161 #define MXC_F_IOMAN_WUD_REQ0_PORT3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_PORT3_POS))
Kojto 101:7cff1c4259d7 162
Kojto 101:7cff1c4259d7 163 #define MXC_F_IOMAN_WUD_REQ1_PORT4_POS 0
Kojto 101:7cff1c4259d7 164 #define MXC_F_IOMAN_WUD_REQ1_PORT4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_PORT4_POS))
Kojto 101:7cff1c4259d7 165 #define MXC_F_IOMAN_WUD_REQ1_PORT5_POS 8
Kojto 101:7cff1c4259d7 166 #define MXC_F_IOMAN_WUD_REQ1_PORT5 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_PORT5_POS))
Kojto 101:7cff1c4259d7 167 #define MXC_F_IOMAN_WUD_REQ1_PORT6_POS 16
Kojto 101:7cff1c4259d7 168 #define MXC_F_IOMAN_WUD_REQ1_PORT6 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_PORT6_POS))
Kojto 101:7cff1c4259d7 169 #define MXC_F_IOMAN_WUD_REQ1_PORT7_POS 24
Kojto 101:7cff1c4259d7 170 #define MXC_F_IOMAN_WUD_REQ1_PORT7 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_PORT7_POS))
Kojto 101:7cff1c4259d7 171
Kojto 101:7cff1c4259d7 172 #define MXC_F_IOMAN_WUD_ACK0_PORT0_POS 0
Kojto 101:7cff1c4259d7 173 #define MXC_F_IOMAN_WUD_ACK0_PORT0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_PORT0_POS))
Kojto 101:7cff1c4259d7 174 #define MXC_F_IOMAN_WUD_ACK0_PORT1_POS 8
Kojto 101:7cff1c4259d7 175 #define MXC_F_IOMAN_WUD_ACK0_PORT1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_PORT1_POS))
Kojto 101:7cff1c4259d7 176 #define MXC_F_IOMAN_WUD_ACK0_PORT2_POS 16
Kojto 101:7cff1c4259d7 177 #define MXC_F_IOMAN_WUD_ACK0_PORT2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_PORT2_POS))
Kojto 101:7cff1c4259d7 178 #define MXC_F_IOMAN_WUD_ACK0_PORT3_POS 24
Kojto 101:7cff1c4259d7 179 #define MXC_F_IOMAN_WUD_ACK0_PORT3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_PORT3_POS))
Kojto 101:7cff1c4259d7 180
Kojto 101:7cff1c4259d7 181 #define MXC_F_IOMAN_WUD_ACK1_PORT4_POS 0
Kojto 101:7cff1c4259d7 182 #define MXC_F_IOMAN_WUD_ACK1_PORT4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_PORT4_POS))
Kojto 101:7cff1c4259d7 183 #define MXC_F_IOMAN_WUD_ACK1_PORT5_POS 8
Kojto 101:7cff1c4259d7 184 #define MXC_F_IOMAN_WUD_ACK1_PORT5 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_PORT5_POS))
Kojto 101:7cff1c4259d7 185 #define MXC_F_IOMAN_WUD_ACK1_PORT6_POS 16
Kojto 101:7cff1c4259d7 186 #define MXC_F_IOMAN_WUD_ACK1_PORT6 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_PORT6_POS))
Kojto 101:7cff1c4259d7 187 #define MXC_F_IOMAN_WUD_ACK1_PORT7_POS 24
Kojto 101:7cff1c4259d7 188 #define MXC_F_IOMAN_WUD_ACK1_PORT7 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_PORT7_POS))
Kojto 101:7cff1c4259d7 189
Kojto 101:7cff1c4259d7 190 #define MXC_F_IOMAN_ALI_REQ0_PORT0_POS 0
Kojto 101:7cff1c4259d7 191 #define MXC_F_IOMAN_ALI_REQ0_PORT0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_PORT0_POS))
Kojto 101:7cff1c4259d7 192 #define MXC_F_IOMAN_ALI_REQ0_PORT1_POS 8
Kojto 101:7cff1c4259d7 193 #define MXC_F_IOMAN_ALI_REQ0_PORT1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_PORT1_POS))
Kojto 101:7cff1c4259d7 194 #define MXC_F_IOMAN_ALI_REQ0_PORT2_POS 16
Kojto 101:7cff1c4259d7 195 #define MXC_F_IOMAN_ALI_REQ0_PORT2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_PORT2_POS))
Kojto 101:7cff1c4259d7 196 #define MXC_F_IOMAN_ALI_REQ0_PORT3_POS 24
Kojto 101:7cff1c4259d7 197 #define MXC_F_IOMAN_ALI_REQ0_PORT3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_PORT3_POS))
Kojto 101:7cff1c4259d7 198
Kojto 101:7cff1c4259d7 199 #define MXC_F_IOMAN_ALI_REQ1_PORT4_POS 0
Kojto 101:7cff1c4259d7 200 #define MXC_F_IOMAN_ALI_REQ1_PORT4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_PORT4_POS))
Kojto 101:7cff1c4259d7 201 #define MXC_F_IOMAN_ALI_REQ1_PORT5_POS 8
Kojto 101:7cff1c4259d7 202 #define MXC_F_IOMAN_ALI_REQ1_PORT5 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_PORT5_POS))
Kojto 101:7cff1c4259d7 203 #define MXC_F_IOMAN_ALI_REQ1_PORT6_POS 16
Kojto 101:7cff1c4259d7 204 #define MXC_F_IOMAN_ALI_REQ1_PORT6 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_PORT6_POS))
Kojto 101:7cff1c4259d7 205 #define MXC_F_IOMAN_ALI_REQ1_PORT7_POS 24
Kojto 101:7cff1c4259d7 206 #define MXC_F_IOMAN_ALI_REQ1_PORT7 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_PORT7_POS))
Kojto 101:7cff1c4259d7 207
Kojto 101:7cff1c4259d7 208 #define MXC_F_IOMAN_ALI_ACK0_PORT0_POS 0
Kojto 101:7cff1c4259d7 209 #define MXC_F_IOMAN_ALI_ACK0_PORT0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_PORT0_POS))
Kojto 101:7cff1c4259d7 210 #define MXC_F_IOMAN_ALI_ACK0_PORT1_POS 8
Kojto 101:7cff1c4259d7 211 #define MXC_F_IOMAN_ALI_ACK0_PORT1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_PORT1_POS))
Kojto 101:7cff1c4259d7 212 #define MXC_F_IOMAN_ALI_ACK0_PORT2_POS 16
Kojto 101:7cff1c4259d7 213 #define MXC_F_IOMAN_ALI_ACK0_PORT2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_PORT2_POS))
Kojto 101:7cff1c4259d7 214 #define MXC_F_IOMAN_ALI_ACK0_PORT3_POS 24
Kojto 101:7cff1c4259d7 215 #define MXC_F_IOMAN_ALI_ACK0_PORT3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_PORT3_POS))
Kojto 101:7cff1c4259d7 216
Kojto 101:7cff1c4259d7 217 #define MXC_F_IOMAN_ALI_ACK1_PORT4_POS 0
Kojto 101:7cff1c4259d7 218 #define MXC_F_IOMAN_ALI_ACK1_PORT4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_PORT4_POS))
Kojto 101:7cff1c4259d7 219 #define MXC_F_IOMAN_ALI_ACK1_PORT5_POS 8
Kojto 101:7cff1c4259d7 220 #define MXC_F_IOMAN_ALI_ACK1_PORT5 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_PORT5_POS))
Kojto 101:7cff1c4259d7 221 #define MXC_F_IOMAN_ALI_ACK1_PORT6_POS 16
Kojto 101:7cff1c4259d7 222 #define MXC_F_IOMAN_ALI_ACK1_PORT6 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_PORT6_POS))
Kojto 101:7cff1c4259d7 223 #define MXC_F_IOMAN_ALI_ACK1_PORT7_POS 24
Kojto 101:7cff1c4259d7 224 #define MXC_F_IOMAN_ALI_ACK1_PORT7 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_PORT7_POS))
Kojto 101:7cff1c4259d7 225
Kojto 101:7cff1c4259d7 226 #define MXC_F_IOMAN_SPI_MAPPING_POS 0
Kojto 101:7cff1c4259d7 227 #define MXC_F_IOMAN_SPI_MAPPING ((uint32_t)(0x00000003UL << MXC_F_IOMAN_SPI_MAPPING_POS))
Kojto 101:7cff1c4259d7 228 #define MXC_F_IOMAN_SPI_CORE_IO_POS 4
Kojto 101:7cff1c4259d7 229 #define MXC_F_IOMAN_SPI_CORE_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_CORE_IO_POS))
Kojto 101:7cff1c4259d7 230 #define MXC_F_IOMAN_SPI_SS0_IO_POS 8
Kojto 101:7cff1c4259d7 231 #define MXC_F_IOMAN_SPI_SS0_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SS0_IO_POS))
Kojto 101:7cff1c4259d7 232 #define MXC_F_IOMAN_SPI_SS1_IO_POS 9
Kojto 101:7cff1c4259d7 233 #define MXC_F_IOMAN_SPI_SS1_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SS1_IO_POS))
Kojto 101:7cff1c4259d7 234 #define MXC_F_IOMAN_SPI_SS2_IO_POS 10
Kojto 101:7cff1c4259d7 235 #define MXC_F_IOMAN_SPI_SS2_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SS2_IO_POS))
Kojto 101:7cff1c4259d7 236 #define MXC_F_IOMAN_SPI_SS3_IO_POS 11
Kojto 101:7cff1c4259d7 237 #define MXC_F_IOMAN_SPI_SS3_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SS3_IO_POS))
Kojto 101:7cff1c4259d7 238 #define MXC_F_IOMAN_SPI_SS4_IO_POS 12
Kojto 101:7cff1c4259d7 239 #define MXC_F_IOMAN_SPI_SS4_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SS4_IO_POS))
Kojto 101:7cff1c4259d7 240 #define MXC_F_IOMAN_SPI_SR0_IO_POS 16
Kojto 101:7cff1c4259d7 241 #define MXC_F_IOMAN_SPI_SR0_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SR0_IO_POS))
Kojto 101:7cff1c4259d7 242 #define MXC_F_IOMAN_SPI_SR1_IO_POS 17
Kojto 101:7cff1c4259d7 243 #define MXC_F_IOMAN_SPI_SR1_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SR1_IO_POS))
Kojto 101:7cff1c4259d7 244 #define MXC_F_IOMAN_SPI_QUAD_IO_POS 20
Kojto 101:7cff1c4259d7 245 #define MXC_F_IOMAN_SPI_QUAD_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_QUAD_IO_POS))
Kojto 101:7cff1c4259d7 246 #define MXC_F_IOMAN_SPI_FAST_MODE_POS 24
Kojto 101:7cff1c4259d7 247 #define MXC_F_IOMAN_SPI_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_FAST_MODE_POS))
Kojto 101:7cff1c4259d7 248
Kojto 101:7cff1c4259d7 249 #define MXC_F_IOMAN_UART_MAPPING_POS 0
Kojto 101:7cff1c4259d7 250 #define MXC_F_IOMAN_UART_MAPPING ((uint32_t)(0x00000003UL << MXC_F_IOMAN_UART_MAPPING_POS))
Kojto 101:7cff1c4259d7 251 #define MXC_F_IOMAN_UART_CORE_IO_POS 4
Kojto 101:7cff1c4259d7 252 #define MXC_F_IOMAN_UART_CORE_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART_CORE_IO_POS))
Kojto 101:7cff1c4259d7 253 #define MXC_F_IOMAN_UART_CTS_IO_POS 5
Kojto 101:7cff1c4259d7 254 #define MXC_F_IOMAN_UART_CTS_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART_CTS_IO_POS))
Kojto 101:7cff1c4259d7 255 #define MXC_F_IOMAN_UART_RTS_IO_POS 6
Kojto 101:7cff1c4259d7 256 #define MXC_F_IOMAN_UART_RTS_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART_RTS_IO_POS))
Kojto 101:7cff1c4259d7 257
Kojto 101:7cff1c4259d7 258 #define MXC_F_IOMAN_I2CM_MAPPING_POS 0
Kojto 101:7cff1c4259d7 259 #define MXC_F_IOMAN_I2CM_MAPPING ((uint32_t)(0x00000003UL << MXC_F_IOMAN_I2CM_MAPPING_POS))
Kojto 101:7cff1c4259d7 260 #define MXC_F_IOMAN_I2CM_CORE_IO_POS 4
Kojto 101:7cff1c4259d7 261 #define MXC_F_IOMAN_I2CM_CORE_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM_CORE_IO_POS))
Kojto 101:7cff1c4259d7 262
Kojto 101:7cff1c4259d7 263 #define MXC_F_IOMAN_I2CS_MAPPING_POS 0
Kojto 101:7cff1c4259d7 264 #define MXC_F_IOMAN_I2CS_MAPPING ((uint32_t)(0x00000003UL << MXC_F_IOMAN_I2CS_MAPPING_POS))
Kojto 101:7cff1c4259d7 265 #define MXC_F_IOMAN_I2CS_CORE_IO_POS 4
Kojto 101:7cff1c4259d7 266 #define MXC_F_IOMAN_I2CS_CORE_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CS_CORE_IO_POS))
Kojto 101:7cff1c4259d7 267
Kojto 101:7cff1c4259d7 268 #define MXC_F_IOMAN_LCD_COM_REQ_COM_IO_POS 0
Kojto 101:7cff1c4259d7 269 #define MXC_F_IOMAN_LCD_COM_REQ_COM_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_COM_REQ_COM_IO_POS))
Kojto 101:7cff1c4259d7 270
Kojto 101:7cff1c4259d7 271 #define MXC_F_IOMAN_LCD_COM_ACK_COM_IO_POS 0
Kojto 101:7cff1c4259d7 272 #define MXC_F_IOMAN_LCD_COM_ACK_COM_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_COM_ACK_COM_IO_POS))
Kojto 101:7cff1c4259d7 273
Kojto 101:7cff1c4259d7 274 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_24_POS 0
Kojto 101:7cff1c4259d7 275 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_24 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_24_POS))
Kojto 101:7cff1c4259d7 276 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_25_POS 1
Kojto 101:7cff1c4259d7 277 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_25 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_25_POS))
Kojto 101:7cff1c4259d7 278 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_26_POS 2
Kojto 101:7cff1c4259d7 279 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_26 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_26_POS))
Kojto 101:7cff1c4259d7 280 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_27_POS 3
Kojto 101:7cff1c4259d7 281 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_27 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_27_POS))
Kojto 101:7cff1c4259d7 282 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_28_POS 4
Kojto 101:7cff1c4259d7 283 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_28 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_28_POS))
Kojto 101:7cff1c4259d7 284 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_29_POS 5
Kojto 101:7cff1c4259d7 285 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_29 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_29_POS))
Kojto 101:7cff1c4259d7 286 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_30_POS 6
Kojto 101:7cff1c4259d7 287 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_30 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_30_POS))
Kojto 101:7cff1c4259d7 288 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_31_POS 7
Kojto 101:7cff1c4259d7 289 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_31 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_31_POS))
Kojto 101:7cff1c4259d7 290 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_32_POS 8
Kojto 101:7cff1c4259d7 291 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_32 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_32_POS))
Kojto 101:7cff1c4259d7 292 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_33_POS 9
Kojto 101:7cff1c4259d7 293 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_33 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_33_POS))
Kojto 101:7cff1c4259d7 294 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_34_POS 10
Kojto 101:7cff1c4259d7 295 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_34 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_34_POS))
Kojto 101:7cff1c4259d7 296 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_35_POS 11
Kojto 101:7cff1c4259d7 297 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_35 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_35_POS))
Kojto 101:7cff1c4259d7 298 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_36_POS 12
Kojto 101:7cff1c4259d7 299 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_36 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_36_POS))
Kojto 101:7cff1c4259d7 300 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_37_POS 13
Kojto 101:7cff1c4259d7 301 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_37 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_37_POS))
Kojto 101:7cff1c4259d7 302 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_38_POS 14
Kojto 101:7cff1c4259d7 303 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_38 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_38_POS))
Kojto 101:7cff1c4259d7 304 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_39_POS 15
Kojto 101:7cff1c4259d7 305 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_39 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_39_POS))
Kojto 101:7cff1c4259d7 306 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_40_POS 16
Kojto 101:7cff1c4259d7 307 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_40 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_40_POS))
Kojto 101:7cff1c4259d7 308 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_41_POS 17
Kojto 101:7cff1c4259d7 309 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_41 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_41_POS))
Kojto 101:7cff1c4259d7 310 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_42_POS 18
Kojto 101:7cff1c4259d7 311 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_42 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_42_POS))
Kojto 101:7cff1c4259d7 312 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_43_POS 19
Kojto 101:7cff1c4259d7 313 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_43 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_43_POS))
Kojto 101:7cff1c4259d7 314 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_44_POS 20
Kojto 101:7cff1c4259d7 315 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_44 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_44_POS))
Kojto 101:7cff1c4259d7 316 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_45_POS 21
Kojto 101:7cff1c4259d7 317 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_45 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_45_POS))
Kojto 101:7cff1c4259d7 318 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_46_POS 22
Kojto 101:7cff1c4259d7 319 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_46 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_46_POS))
Kojto 101:7cff1c4259d7 320 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_47_POS 23
Kojto 101:7cff1c4259d7 321 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_47 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_47_POS))
Kojto 101:7cff1c4259d7 322 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_48_POS 24
Kojto 101:7cff1c4259d7 323 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_48 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_48_POS))
Kojto 101:7cff1c4259d7 324 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_49_POS 25
Kojto 101:7cff1c4259d7 325 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_49 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_49_POS))
Kojto 101:7cff1c4259d7 326 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_50_POS 26
Kojto 101:7cff1c4259d7 327 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_50 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_50_POS))
Kojto 101:7cff1c4259d7 328 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_51_POS 27
Kojto 101:7cff1c4259d7 329 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_51 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_51_POS))
Kojto 101:7cff1c4259d7 330 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_52_POS 28
Kojto 101:7cff1c4259d7 331 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_52 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_52_POS))
Kojto 101:7cff1c4259d7 332 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_53_POS 29
Kojto 101:7cff1c4259d7 333 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_53 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_53_POS))
Kojto 101:7cff1c4259d7 334 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_54_POS 30
Kojto 101:7cff1c4259d7 335 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_54 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_54_POS))
Kojto 101:7cff1c4259d7 336 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_55_POS 31
Kojto 101:7cff1c4259d7 337 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_55 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_55_POS))
Kojto 101:7cff1c4259d7 338
Kojto 101:7cff1c4259d7 339 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_56_POS 0
Kojto 101:7cff1c4259d7 340 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_56 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_56_POS))
Kojto 101:7cff1c4259d7 341 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_57_POS 1
Kojto 101:7cff1c4259d7 342 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_57 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_57_POS))
Kojto 101:7cff1c4259d7 343 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_58_POS 2
Kojto 101:7cff1c4259d7 344 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_58 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_58_POS))
Kojto 101:7cff1c4259d7 345 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_59_POS 3
Kojto 101:7cff1c4259d7 346 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_59 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_59_POS))
Kojto 101:7cff1c4259d7 347 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_60_POS 4
Kojto 101:7cff1c4259d7 348 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_60 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_60_POS))
Kojto 101:7cff1c4259d7 349 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_61_POS 5
Kojto 101:7cff1c4259d7 350 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_61 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_61_POS))
Kojto 101:7cff1c4259d7 351 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_62_POS 6
Kojto 101:7cff1c4259d7 352 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_62 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_62_POS))
Kojto 101:7cff1c4259d7 353 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_63_POS 7
Kojto 101:7cff1c4259d7 354 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_63 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_63_POS))
Kojto 101:7cff1c4259d7 355
Kojto 101:7cff1c4259d7 356 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_24_POS 0
Kojto 101:7cff1c4259d7 357 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_24 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_24_POS))
Kojto 101:7cff1c4259d7 358 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_25_POS 1
Kojto 101:7cff1c4259d7 359 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_25 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_25_POS))
Kojto 101:7cff1c4259d7 360 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_26_POS 2
Kojto 101:7cff1c4259d7 361 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_26 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_26_POS))
Kojto 101:7cff1c4259d7 362 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_27_POS 3
Kojto 101:7cff1c4259d7 363 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_27 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_27_POS))
Kojto 101:7cff1c4259d7 364 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_28_POS 4
Kojto 101:7cff1c4259d7 365 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_28 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_28_POS))
Kojto 101:7cff1c4259d7 366 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_29_POS 5
Kojto 101:7cff1c4259d7 367 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_29 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_29_POS))
Kojto 101:7cff1c4259d7 368 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_30_POS 6
Kojto 101:7cff1c4259d7 369 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_30 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_30_POS))
Kojto 101:7cff1c4259d7 370 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_31_POS 7
Kojto 101:7cff1c4259d7 371 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_31 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_31_POS))
Kojto 101:7cff1c4259d7 372 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_32_POS 8
Kojto 101:7cff1c4259d7 373 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_32 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_32_POS))
Kojto 101:7cff1c4259d7 374 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_33_POS 9
Kojto 101:7cff1c4259d7 375 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_33 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_33_POS))
Kojto 101:7cff1c4259d7 376 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_34_POS 10
Kojto 101:7cff1c4259d7 377 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_34 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_34_POS))
Kojto 101:7cff1c4259d7 378 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_35_POS 11
Kojto 101:7cff1c4259d7 379 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_35 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_35_POS))
Kojto 101:7cff1c4259d7 380 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_36_POS 12
Kojto 101:7cff1c4259d7 381 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_36 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_36_POS))
Kojto 101:7cff1c4259d7 382 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_37_POS 13
Kojto 101:7cff1c4259d7 383 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_37 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_37_POS))
Kojto 101:7cff1c4259d7 384 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_38_POS 14
Kojto 101:7cff1c4259d7 385 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_38 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_38_POS))
Kojto 101:7cff1c4259d7 386 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_39_POS 15
Kojto 101:7cff1c4259d7 387 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_39 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_39_POS))
Kojto 101:7cff1c4259d7 388 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_40_POS 16
Kojto 101:7cff1c4259d7 389 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_40 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_40_POS))
Kojto 101:7cff1c4259d7 390 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_41_POS 17
Kojto 101:7cff1c4259d7 391 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_41 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_41_POS))
Kojto 101:7cff1c4259d7 392 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_42_POS 18
Kojto 101:7cff1c4259d7 393 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_42 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_42_POS))
Kojto 101:7cff1c4259d7 394 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_43_POS 19
Kojto 101:7cff1c4259d7 395 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_43 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_43_POS))
Kojto 101:7cff1c4259d7 396 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_44_POS 20
Kojto 101:7cff1c4259d7 397 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_44 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_44_POS))
Kojto 101:7cff1c4259d7 398 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_45_POS 21
Kojto 101:7cff1c4259d7 399 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_45 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_45_POS))
Kojto 101:7cff1c4259d7 400 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_46_POS 22
Kojto 101:7cff1c4259d7 401 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_46 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_46_POS))
Kojto 101:7cff1c4259d7 402 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_47_POS 23
Kojto 101:7cff1c4259d7 403 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_47 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_47_POS))
Kojto 101:7cff1c4259d7 404 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_48_POS 24
Kojto 101:7cff1c4259d7 405 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_48 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_48_POS))
Kojto 101:7cff1c4259d7 406 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_49_POS 25
Kojto 101:7cff1c4259d7 407 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_49 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_49_POS))
Kojto 101:7cff1c4259d7 408 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_50_POS 26
Kojto 101:7cff1c4259d7 409 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_50 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_50_POS))
Kojto 101:7cff1c4259d7 410 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_51_POS 27
Kojto 101:7cff1c4259d7 411 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_51 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_51_POS))
Kojto 101:7cff1c4259d7 412 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_52_POS 28
Kojto 101:7cff1c4259d7 413 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_52 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_52_POS))
Kojto 101:7cff1c4259d7 414 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_53_POS 29
Kojto 101:7cff1c4259d7 415 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_53 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_53_POS))
Kojto 101:7cff1c4259d7 416 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_54_POS 30
Kojto 101:7cff1c4259d7 417 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_54 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_54_POS))
Kojto 101:7cff1c4259d7 418 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_55_POS 31
Kojto 101:7cff1c4259d7 419 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_55 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_55_POS))
Kojto 101:7cff1c4259d7 420
Kojto 101:7cff1c4259d7 421 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_56_POS 0
Kojto 101:7cff1c4259d7 422 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_56 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_56_POS))
Kojto 101:7cff1c4259d7 423 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_57_POS 1
Kojto 101:7cff1c4259d7 424 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_57 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_57_POS))
Kojto 101:7cff1c4259d7 425 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_58_POS 2
Kojto 101:7cff1c4259d7 426 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_58 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_58_POS))
Kojto 101:7cff1c4259d7 427 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_59_POS 3
Kojto 101:7cff1c4259d7 428 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_59 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_59_POS))
Kojto 101:7cff1c4259d7 429 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_60_POS 4
Kojto 101:7cff1c4259d7 430 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_60 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_60_POS))
Kojto 101:7cff1c4259d7 431 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_61_POS 5
Kojto 101:7cff1c4259d7 432 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_61 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_61_POS))
Kojto 101:7cff1c4259d7 433 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_62_POS 6
Kojto 101:7cff1c4259d7 434 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_62 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_62_POS))
Kojto 101:7cff1c4259d7 435 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_63_POS 7
Kojto 101:7cff1c4259d7 436 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_63 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_63_POS))
Kojto 101:7cff1c4259d7 437
Kojto 101:7cff1c4259d7 438 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT0_POS 0
Kojto 101:7cff1c4259d7 439 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT0 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT0_POS))
Kojto 101:7cff1c4259d7 440 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT1_POS 1
Kojto 101:7cff1c4259d7 441 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT1 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT1_POS))
Kojto 101:7cff1c4259d7 442 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT2_POS 2
Kojto 101:7cff1c4259d7 443 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT2 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT2_POS))
Kojto 101:7cff1c4259d7 444 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT3_POS 3
Kojto 101:7cff1c4259d7 445 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT3 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT3_POS))
Kojto 101:7cff1c4259d7 446 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT4_POS 4
Kojto 101:7cff1c4259d7 447 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT4 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT4_POS))
Kojto 101:7cff1c4259d7 448 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT5_POS 5
Kojto 101:7cff1c4259d7 449 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT5 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT5_POS))
Kojto 101:7cff1c4259d7 450 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT6_POS 6
Kojto 101:7cff1c4259d7 451 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT6 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT6_POS))
Kojto 101:7cff1c4259d7 452 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT7_POS 7
Kojto 101:7cff1c4259d7 453 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT7 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT7_POS))
Kojto 101:7cff1c4259d7 454
Kojto 101:7cff1c4259d7 455 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT0_POS 0
Kojto 101:7cff1c4259d7 456 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT0 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT0_POS))
Kojto 101:7cff1c4259d7 457 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT1_POS 1
Kojto 101:7cff1c4259d7 458 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT1 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT1_POS))
Kojto 101:7cff1c4259d7 459 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT2_POS 2
Kojto 101:7cff1c4259d7 460 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT2 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT2_POS))
Kojto 101:7cff1c4259d7 461 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT3_POS 3
Kojto 101:7cff1c4259d7 462 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT3 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT3_POS))
Kojto 101:7cff1c4259d7 463 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT4_POS 4
Kojto 101:7cff1c4259d7 464 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT4 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT4_POS))
Kojto 101:7cff1c4259d7 465 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT5_POS 5
Kojto 101:7cff1c4259d7 466 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT5 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT5_POS))
Kojto 101:7cff1c4259d7 467 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT6_POS 6
Kojto 101:7cff1c4259d7 468 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT6 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT6_POS))
Kojto 101:7cff1c4259d7 469 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT7_POS 7
Kojto 101:7cff1c4259d7 470 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT7 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT7_POS))
Kojto 101:7cff1c4259d7 471
Kojto 101:7cff1c4259d7 472 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT0_POS 0
Kojto 101:7cff1c4259d7 473 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT0 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT0_POS))
Kojto 101:7cff1c4259d7 474 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT1_POS 4
Kojto 101:7cff1c4259d7 475 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT1 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT1_POS))
Kojto 101:7cff1c4259d7 476 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT2_POS 8
Kojto 101:7cff1c4259d7 477 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT2 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT2_POS))
Kojto 101:7cff1c4259d7 478 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT3_POS 12
Kojto 101:7cff1c4259d7 479 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT3 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT3_POS))
Kojto 101:7cff1c4259d7 480 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT4_POS 16
Kojto 101:7cff1c4259d7 481 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT4 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT4_POS))
Kojto 101:7cff1c4259d7 482 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT5_POS 20
Kojto 101:7cff1c4259d7 483 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT5 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT5_POS))
Kojto 101:7cff1c4259d7 484 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT6_POS 24
Kojto 101:7cff1c4259d7 485 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT6 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT6_POS))
Kojto 101:7cff1c4259d7 486 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT7_POS 28
Kojto 101:7cff1c4259d7 487 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT7 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT7_POS))
Kojto 101:7cff1c4259d7 488
Kojto 101:7cff1c4259d7 489 #define MXC_F_IOMAN_PADX_CONTROL_PADX_POWER_CONTROL_POS 0
Kojto 101:7cff1c4259d7 490 #define MXC_F_IOMAN_PADX_CONTROL_PADX_POWER_CONTROL ((uint32_t)(0x00000001UL << MXC_F_IOMAN_PADX_CONTROL_PADX_POWER_CONTROL_POS))
Kojto 101:7cff1c4259d7 491 #define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_OUT_MODE_POS 4
Kojto 101:7cff1c4259d7 492 #define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_OUT_MODE ((uint32_t)(0x00000003UL << MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_OUT_MODE_POS))
Kojto 101:7cff1c4259d7 493 #define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_INPUT_STATE_POS 6
Kojto 101:7cff1c4259d7 494 #define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_INPUT_STATE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_INPUT_STATE_POS))
Kojto 101:7cff1c4259d7 495 #define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_OUT_MODE_POS 8
Kojto 101:7cff1c4259d7 496 #define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_OUT_MODE ((uint32_t)(0x00000003UL << MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_OUT_MODE_POS))
Kojto 101:7cff1c4259d7 497 #define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_INPUT_STATE_POS 10
Kojto 101:7cff1c4259d7 498 #define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_INPUT_STATE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_INPUT_STATE_POS))
Kojto 101:7cff1c4259d7 499
Kojto 101:7cff1c4259d7 500 #ifdef __cplusplus
Kojto 101:7cff1c4259d7 501 }
Kojto 101:7cff1c4259d7 502 #endif
Kojto 101:7cff1c4259d7 503
Kojto 101:7cff1c4259d7 504 /**
Kojto 101:7cff1c4259d7 505 * @}
Kojto 101:7cff1c4259d7 506 */
Kojto 101:7cff1c4259d7 507
Kojto 101:7cff1c4259d7 508 #endif /* _MXC_IOMAN_REGS_H_ */