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TARGET_ELMO_F411RE/stm32f4xx_ll_fmc.h@108:34e6b704fe68, 2015-10-02 (annotated)

Committer:
Kojto
Date:
Fri Oct 02 07:35:07 2015 +0200
Revision:
108:34e6b704fe68
Child:
110:165afa46840b
Release 108  of the mbed library



Changes:

- new platforms - ELMO_F411RE, WIZNET_7500P, ARM_MPS2_BEID

- EFM32 - bugfixes in rtc, serial

- Cortex A cmsis - update files

- STML4 - RAM fixes

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 108:34e6b704fe68 1 /**
Kojto 108:34e6b704fe68 2 ******************************************************************************
Kojto 108:34e6b704fe68 3 * @file stm32f4xx_ll_fmc.h
Kojto 108:34e6b704fe68 4 * @author MCD Application Team
Kojto 108:34e6b704fe68 5 * @version V1.3.2
Kojto 108:34e6b704fe68 6 * @date 26-June-2015
Kojto 108:34e6b704fe68 7 * @brief Header file of FMC HAL module.
Kojto 108:34e6b704fe68 8 ******************************************************************************
Kojto 108:34e6b704fe68 9 * @attention
Kojto 108:34e6b704fe68 10 *
Kojto 108:34e6b704fe68 11 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
Kojto 108:34e6b704fe68 12 *
Kojto 108:34e6b704fe68 13 * Redistribution and use in source and binary forms, with or without modification,
Kojto 108:34e6b704fe68 14 * are permitted provided that the following conditions are met:
Kojto 108:34e6b704fe68 15 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 108:34e6b704fe68 16 * this list of conditions and the following disclaimer.
Kojto 108:34e6b704fe68 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 108:34e6b704fe68 18 * this list of conditions and the following disclaimer in the documentation
Kojto 108:34e6b704fe68 19 * and/or other materials provided with the distribution.
Kojto 108:34e6b704fe68 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto 108:34e6b704fe68 21 * may be used to endorse or promote products derived from this software
Kojto 108:34e6b704fe68 22 * without specific prior written permission.
Kojto 108:34e6b704fe68 23 *
Kojto 108:34e6b704fe68 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 108:34e6b704fe68 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 108:34e6b704fe68 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 108:34e6b704fe68 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto 108:34e6b704fe68 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 108:34e6b704fe68 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto 108:34e6b704fe68 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto 108:34e6b704fe68 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto 108:34e6b704fe68 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto 108:34e6b704fe68 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 108:34e6b704fe68 34 *
Kojto 108:34e6b704fe68 35 ******************************************************************************
Kojto 108:34e6b704fe68 36 */
Kojto 108:34e6b704fe68 37
Kojto 108:34e6b704fe68 38 /* Define to prevent recursive inclusion -------------------------------------*/
Kojto 108:34e6b704fe68 39 #ifndef __STM32F4xx_LL_FMC_H
Kojto 108:34e6b704fe68 40 #define __STM32F4xx_LL_FMC_H
Kojto 108:34e6b704fe68 41
Kojto 108:34e6b704fe68 42 #ifdef __cplusplus
Kojto 108:34e6b704fe68 43 extern "C" {
Kojto 108:34e6b704fe68 44 #endif
Kojto 108:34e6b704fe68 45
Kojto 108:34e6b704fe68 46 /* Includes ------------------------------------------------------------------*/
Kojto 108:34e6b704fe68 47 #include "stm32f4xx_hal_def.h"
Kojto 108:34e6b704fe68 48
Kojto 108:34e6b704fe68 49 /** @addtogroup STM32F4xx_HAL_Driver
Kojto 108:34e6b704fe68 50 * @{
Kojto 108:34e6b704fe68 51 */
Kojto 108:34e6b704fe68 52
Kojto 108:34e6b704fe68 53 /** @addtogroup FMC_LL
Kojto 108:34e6b704fe68 54 * @{
Kojto 108:34e6b704fe68 55 */
Kojto 108:34e6b704fe68 56 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx)
Kojto 108:34e6b704fe68 57 /* Private types -------------------------------------------------------------*/
Kojto 108:34e6b704fe68 58 /** @defgroup FMC_LL_Private_Types FMC Private Types
Kojto 108:34e6b704fe68 59 * @{
Kojto 108:34e6b704fe68 60 */
Kojto 108:34e6b704fe68 61
Kojto 108:34e6b704fe68 62 /**
Kojto 108:34e6b704fe68 63 * @brief FMC NORSRAM Configuration Structure definition
Kojto 108:34e6b704fe68 64 */
Kojto 108:34e6b704fe68 65 typedef struct
Kojto 108:34e6b704fe68 66 {
Kojto 108:34e6b704fe68 67 uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
Kojto 108:34e6b704fe68 68 This parameter can be a value of @ref FMC_NORSRAM_Bank */
Kojto 108:34e6b704fe68 69
Kojto 108:34e6b704fe68 70 uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
Kojto 108:34e6b704fe68 71 multiplexed on the data bus or not.
Kojto 108:34e6b704fe68 72 This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
Kojto 108:34e6b704fe68 73
Kojto 108:34e6b704fe68 74 uint32_t MemoryType; /*!< Specifies the type of external memory attached to
Kojto 108:34e6b704fe68 75 the corresponding memory device.
Kojto 108:34e6b704fe68 76 This parameter can be a value of @ref FMC_Memory_Type */
Kojto 108:34e6b704fe68 77
Kojto 108:34e6b704fe68 78 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
Kojto 108:34e6b704fe68 79 This parameter can be a value of @ref FMC_NORSRAM_Data_Width */
Kojto 108:34e6b704fe68 80
Kojto 108:34e6b704fe68 81 uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
Kojto 108:34e6b704fe68 82 valid only with synchronous burst Flash memories.
Kojto 108:34e6b704fe68 83 This parameter can be a value of @ref FMC_Burst_Access_Mode */
Kojto 108:34e6b704fe68 84
Kojto 108:34e6b704fe68 85 uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
Kojto 108:34e6b704fe68 86 the Flash memory in burst mode.
Kojto 108:34e6b704fe68 87 This parameter can be a value of @ref FMC_Wait_Signal_Polarity */
Kojto 108:34e6b704fe68 88
Kojto 108:34e6b704fe68 89 uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
Kojto 108:34e6b704fe68 90 memory, valid only when accessing Flash memories in burst mode.
Kojto 108:34e6b704fe68 91 This parameter can be a value of @ref FMC_Wrap_Mode
Kojto 108:34e6b704fe68 92 This mode is not available for the STM32F446xx devices */
Kojto 108:34e6b704fe68 93
Kojto 108:34e6b704fe68 94 uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
Kojto 108:34e6b704fe68 95 clock cycle before the wait state or during the wait state,
Kojto 108:34e6b704fe68 96 valid only when accessing memories in burst mode.
Kojto 108:34e6b704fe68 97 This parameter can be a value of @ref FMC_Wait_Timing */
Kojto 108:34e6b704fe68 98
Kojto 108:34e6b704fe68 99 uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC.
Kojto 108:34e6b704fe68 100 This parameter can be a value of @ref FMC_Write_Operation */
Kojto 108:34e6b704fe68 101
Kojto 108:34e6b704fe68 102 uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
Kojto 108:34e6b704fe68 103 signal, valid for Flash memory access in burst mode.
Kojto 108:34e6b704fe68 104 This parameter can be a value of @ref FMC_Wait_Signal */
Kojto 108:34e6b704fe68 105
Kojto 108:34e6b704fe68 106 uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
Kojto 108:34e6b704fe68 107 This parameter can be a value of @ref FMC_Extended_Mode */
Kojto 108:34e6b704fe68 108
Kojto 108:34e6b704fe68 109 uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
Kojto 108:34e6b704fe68 110 valid only with asynchronous Flash memories.
Kojto 108:34e6b704fe68 111 This parameter can be a value of @ref FMC_AsynchronousWait */
Kojto 108:34e6b704fe68 112
Kojto 108:34e6b704fe68 113 uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
Kojto 108:34e6b704fe68 114 This parameter can be a value of @ref FMC_Write_Burst */
Kojto 108:34e6b704fe68 115
Kojto 108:34e6b704fe68 116 uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
Kojto 108:34e6b704fe68 117 This parameter is only enabled through the FMC_BCR1 register, and don't care
Kojto 108:34e6b704fe68 118 through FMC_BCR2..4 registers.
Kojto 108:34e6b704fe68 119 This parameter can be a value of @ref FMC_Continous_Clock */
Kojto 108:34e6b704fe68 120
Kojto 108:34e6b704fe68 121 uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller.
Kojto 108:34e6b704fe68 122 This parameter is only enabled through the FMC_BCR1 register, and don't care
Kojto 108:34e6b704fe68 123 through FMC_BCR2..4 registers.
Kojto 108:34e6b704fe68 124 This parameter can be a value of @ref FMC_Write_FIFO
Kojto 108:34e6b704fe68 125 This mode is available only for the STM32F446xx devices */
Kojto 108:34e6b704fe68 126
Kojto 108:34e6b704fe68 127 uint32_t PageSize; /*!< Specifies the memory page size.
Kojto 108:34e6b704fe68 128 This parameter can be a value of @ref FMC_Page_Size
Kojto 108:34e6b704fe68 129 This mode is available only for the STM32F446xx devices */
Kojto 108:34e6b704fe68 130
Kojto 108:34e6b704fe68 131 }FMC_NORSRAM_InitTypeDef;
Kojto 108:34e6b704fe68 132
Kojto 108:34e6b704fe68 133 /**
Kojto 108:34e6b704fe68 134 * @brief FMC NORSRAM Timing parameters structure definition
Kojto 108:34e6b704fe68 135 */
Kojto 108:34e6b704fe68 136 typedef struct
Kojto 108:34e6b704fe68 137 {
Kojto 108:34e6b704fe68 138 uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
Kojto 108:34e6b704fe68 139 the duration of the address setup time.
Kojto 108:34e6b704fe68 140 This parameter can be a value between Min_Data = 0 and Max_Data = 15.
Kojto 108:34e6b704fe68 141 @note This parameter is not used with synchronous NOR Flash memories. */
Kojto 108:34e6b704fe68 142
Kojto 108:34e6b704fe68 143 uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
Kojto 108:34e6b704fe68 144 the duration of the address hold time.
Kojto 108:34e6b704fe68 145 This parameter can be a value between Min_Data = 1 and Max_Data = 15.
Kojto 108:34e6b704fe68 146 @note This parameter is not used with synchronous NOR Flash memories. */
Kojto 108:34e6b704fe68 147
Kojto 108:34e6b704fe68 148 uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
Kojto 108:34e6b704fe68 149 the duration of the data setup time.
Kojto 108:34e6b704fe68 150 This parameter can be a value between Min_Data = 1 and Max_Data = 255.
Kojto 108:34e6b704fe68 151 @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
Kojto 108:34e6b704fe68 152 NOR Flash memories. */
Kojto 108:34e6b704fe68 153
Kojto 108:34e6b704fe68 154 uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
Kojto 108:34e6b704fe68 155 the duration of the bus turnaround.
Kojto 108:34e6b704fe68 156 This parameter can be a value between Min_Data = 0 and Max_Data = 15.
Kojto 108:34e6b704fe68 157 @note This parameter is only used for multiplexed NOR Flash memories. */
Kojto 108:34e6b704fe68 158
Kojto 108:34e6b704fe68 159 uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
Kojto 108:34e6b704fe68 160 HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
Kojto 108:34e6b704fe68 161 @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
Kojto 108:34e6b704fe68 162 accesses. */
Kojto 108:34e6b704fe68 163
Kojto 108:34e6b704fe68 164 uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
Kojto 108:34e6b704fe68 165 to the memory before getting the first data.
Kojto 108:34e6b704fe68 166 The parameter value depends on the memory type as shown below:
Kojto 108:34e6b704fe68 167 - It must be set to 0 in case of a CRAM
Kojto 108:34e6b704fe68 168 - It is don't care in asynchronous NOR, SRAM or ROM accesses
Kojto 108:34e6b704fe68 169 - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
Kojto 108:34e6b704fe68 170 with synchronous burst mode enable */
Kojto 108:34e6b704fe68 171
Kojto 108:34e6b704fe68 172 uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
Kojto 108:34e6b704fe68 173 This parameter can be a value of @ref FMC_Access_Mode */
Kojto 108:34e6b704fe68 174 }FMC_NORSRAM_TimingTypeDef;
Kojto 108:34e6b704fe68 175
Kojto 108:34e6b704fe68 176 /**
Kojto 108:34e6b704fe68 177 * @brief FMC NAND Configuration Structure definition
Kojto 108:34e6b704fe68 178 */
Kojto 108:34e6b704fe68 179 typedef struct
Kojto 108:34e6b704fe68 180 {
Kojto 108:34e6b704fe68 181 uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
Kojto 108:34e6b704fe68 182 This parameter can be a value of @ref FMC_NAND_Bank */
Kojto 108:34e6b704fe68 183
Kojto 108:34e6b704fe68 184 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
Kojto 108:34e6b704fe68 185 This parameter can be any value of @ref FMC_Wait_feature */
Kojto 108:34e6b704fe68 186
Kojto 108:34e6b704fe68 187 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
Kojto 108:34e6b704fe68 188 This parameter can be any value of @ref FMC_NAND_Data_Width */
Kojto 108:34e6b704fe68 189
Kojto 108:34e6b704fe68 190 uint32_t EccComputation; /*!< Enables or disables the ECC computation.
Kojto 108:34e6b704fe68 191 This parameter can be any value of @ref FMC_ECC */
Kojto 108:34e6b704fe68 192
Kojto 108:34e6b704fe68 193 uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
Kojto 108:34e6b704fe68 194 This parameter can be any value of @ref FMC_ECC_Page_Size */
Kojto 108:34e6b704fe68 195
Kojto 108:34e6b704fe68 196 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
Kojto 108:34e6b704fe68 197 delay between CLE low and RE low.
Kojto 108:34e6b704fe68 198 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
Kojto 108:34e6b704fe68 199
Kojto 108:34e6b704fe68 200 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
Kojto 108:34e6b704fe68 201 delay between ALE low and RE low.
Kojto 108:34e6b704fe68 202 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
Kojto 108:34e6b704fe68 203 }FMC_NAND_InitTypeDef;
Kojto 108:34e6b704fe68 204
Kojto 108:34e6b704fe68 205 /**
Kojto 108:34e6b704fe68 206 * @brief FMC NAND/PCCARD Timing parameters structure definition
Kojto 108:34e6b704fe68 207 */
Kojto 108:34e6b704fe68 208 typedef struct
Kojto 108:34e6b704fe68 209 {
Kojto 108:34e6b704fe68 210 uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
Kojto 108:34e6b704fe68 211 the command assertion for NAND-Flash read or write access
Kojto 108:34e6b704fe68 212 to common/Attribute or I/O memory space (depending on
Kojto 108:34e6b704fe68 213 the memory space timing to be configured).
Kojto 108:34e6b704fe68 214 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
Kojto 108:34e6b704fe68 215
Kojto 108:34e6b704fe68 216 uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
Kojto 108:34e6b704fe68 217 command for NAND-Flash read or write access to
Kojto 108:34e6b704fe68 218 common/Attribute or I/O memory space (depending on the
Kojto 108:34e6b704fe68 219 memory space timing to be configured).
Kojto 108:34e6b704fe68 220 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
Kojto 108:34e6b704fe68 221
Kojto 108:34e6b704fe68 222 uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
Kojto 108:34e6b704fe68 223 (and data for write access) after the command de-assertion
Kojto 108:34e6b704fe68 224 for NAND-Flash read or write access to common/Attribute
Kojto 108:34e6b704fe68 225 or I/O memory space (depending on the memory space timing
Kojto 108:34e6b704fe68 226 to be configured).
Kojto 108:34e6b704fe68 227 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
Kojto 108:34e6b704fe68 228
Kojto 108:34e6b704fe68 229 uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
Kojto 108:34e6b704fe68 230 data bus is kept in HiZ after the start of a NAND-Flash
Kojto 108:34e6b704fe68 231 write access to common/Attribute or I/O memory space (depending
Kojto 108:34e6b704fe68 232 on the memory space timing to be configured).
Kojto 108:34e6b704fe68 233 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
Kojto 108:34e6b704fe68 234 }FMC_NAND_PCC_TimingTypeDef;
Kojto 108:34e6b704fe68 235
Kojto 108:34e6b704fe68 236 /**
Kojto 108:34e6b704fe68 237 * @brief FMC NAND Configuration Structure definition
Kojto 108:34e6b704fe68 238 */
Kojto 108:34e6b704fe68 239 typedef struct
Kojto 108:34e6b704fe68 240 {
Kojto 108:34e6b704fe68 241 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
Kojto 108:34e6b704fe68 242 This parameter can be any value of @ref FMC_Wait_feature */
Kojto 108:34e6b704fe68 243
Kojto 108:34e6b704fe68 244 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
Kojto 108:34e6b704fe68 245 delay between CLE low and RE low.
Kojto 108:34e6b704fe68 246 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
Kojto 108:34e6b704fe68 247
Kojto 108:34e6b704fe68 248 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
Kojto 108:34e6b704fe68 249 delay between ALE low and RE low.
Kojto 108:34e6b704fe68 250 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
Kojto 108:34e6b704fe68 251 }FMC_PCCARD_InitTypeDef;
Kojto 108:34e6b704fe68 252
Kojto 108:34e6b704fe68 253 /**
Kojto 108:34e6b704fe68 254 * @brief FMC SDRAM Configuration Structure definition
Kojto 108:34e6b704fe68 255 */
Kojto 108:34e6b704fe68 256 typedef struct
Kojto 108:34e6b704fe68 257 {
Kojto 108:34e6b704fe68 258 uint32_t SDBank; /*!< Specifies the SDRAM memory device that will be used.
Kojto 108:34e6b704fe68 259 This parameter can be a value of @ref FMC_SDRAM_Bank */
Kojto 108:34e6b704fe68 260
Kojto 108:34e6b704fe68 261 uint32_t ColumnBitsNumber; /*!< Defines the number of bits of column address.
Kojto 108:34e6b704fe68 262 This parameter can be a value of @ref FMC_SDRAM_Column_Bits_number. */
Kojto 108:34e6b704fe68 263
Kojto 108:34e6b704fe68 264 uint32_t RowBitsNumber; /*!< Defines the number of bits of column address.
Kojto 108:34e6b704fe68 265 This parameter can be a value of @ref FMC_SDRAM_Row_Bits_number. */
Kojto 108:34e6b704fe68 266
Kojto 108:34e6b704fe68 267 uint32_t MemoryDataWidth; /*!< Defines the memory device width.
Kojto 108:34e6b704fe68 268 This parameter can be a value of @ref FMC_SDRAM_Memory_Bus_Width. */
Kojto 108:34e6b704fe68 269
Kojto 108:34e6b704fe68 270 uint32_t InternalBankNumber; /*!< Defines the number of the device's internal banks.
Kojto 108:34e6b704fe68 271 This parameter can be of @ref FMC_SDRAM_Internal_Banks_Number. */
Kojto 108:34e6b704fe68 272
Kojto 108:34e6b704fe68 273 uint32_t CASLatency; /*!< Defines the SDRAM CAS latency in number of memory clock cycles.
Kojto 108:34e6b704fe68 274 This parameter can be a value of @ref FMC_SDRAM_CAS_Latency. */
Kojto 108:34e6b704fe68 275
Kojto 108:34e6b704fe68 276 uint32_t WriteProtection; /*!< Enables the SDRAM device to be accessed in write mode.
Kojto 108:34e6b704fe68 277 This parameter can be a value of @ref FMC_SDRAM_Write_Protection. */
Kojto 108:34e6b704fe68 278
Kojto 108:34e6b704fe68 279 uint32_t SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM devices and they allow
Kojto 108:34e6b704fe68 280 to disable the clock before changing frequency.
Kojto 108:34e6b704fe68 281 This parameter can be a value of @ref FMC_SDRAM_Clock_Period. */
Kojto 108:34e6b704fe68 282
Kojto 108:34e6b704fe68 283 uint32_t ReadBurst; /*!< This bit enable the SDRAM controller to anticipate the next read
Kojto 108:34e6b704fe68 284 commands during the CAS latency and stores data in the Read FIFO.
Kojto 108:34e6b704fe68 285 This parameter can be a value of @ref FMC_SDRAM_Read_Burst. */
Kojto 108:34e6b704fe68 286
Kojto 108:34e6b704fe68 287 uint32_t ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path.
Kojto 108:34e6b704fe68 288 This parameter can be a value of @ref FMC_SDRAM_Read_Pipe_Delay. */
Kojto 108:34e6b704fe68 289 }FMC_SDRAM_InitTypeDef;
Kojto 108:34e6b704fe68 290
Kojto 108:34e6b704fe68 291 /**
Kojto 108:34e6b704fe68 292 * @brief FMC SDRAM Timing parameters structure definition
Kojto 108:34e6b704fe68 293 */
Kojto 108:34e6b704fe68 294 typedef struct
Kojto 108:34e6b704fe68 295 {
Kojto 108:34e6b704fe68 296 uint32_t LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and
Kojto 108:34e6b704fe68 297 an active or Refresh command in number of memory clock cycles.
Kojto 108:34e6b704fe68 298 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
Kojto 108:34e6b704fe68 299
Kojto 108:34e6b704fe68 300 uint32_t ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to
Kojto 108:34e6b704fe68 301 issuing the Activate command in number of memory clock cycles.
Kojto 108:34e6b704fe68 302 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
Kojto 108:34e6b704fe68 303
Kojto 108:34e6b704fe68 304 uint32_t SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock
Kojto 108:34e6b704fe68 305 cycles.
Kojto 108:34e6b704fe68 306 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
Kojto 108:34e6b704fe68 307
Kojto 108:34e6b704fe68 308 uint32_t RowCycleDelay; /*!< Defines the delay between the Refresh command and the Activate command
Kojto 108:34e6b704fe68 309 and the delay between two consecutive Refresh commands in number of
Kojto 108:34e6b704fe68 310 memory clock cycles.
Kojto 108:34e6b704fe68 311 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
Kojto 108:34e6b704fe68 312
Kojto 108:34e6b704fe68 313 uint32_t WriteRecoveryTime; /*!< Defines the Write recovery Time in number of memory clock cycles.
Kojto 108:34e6b704fe68 314 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
Kojto 108:34e6b704fe68 315
Kojto 108:34e6b704fe68 316 uint32_t RPDelay; /*!< Defines the delay between a Precharge Command and an other command
Kojto 108:34e6b704fe68 317 in number of memory clock cycles.
Kojto 108:34e6b704fe68 318 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
Kojto 108:34e6b704fe68 319
Kojto 108:34e6b704fe68 320 uint32_t RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write
Kojto 108:34e6b704fe68 321 command in number of memory clock cycles.
Kojto 108:34e6b704fe68 322 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
Kojto 108:34e6b704fe68 323 }FMC_SDRAM_TimingTypeDef;
Kojto 108:34e6b704fe68 324
Kojto 108:34e6b704fe68 325 /**
Kojto 108:34e6b704fe68 326 * @brief SDRAM command parameters structure definition
Kojto 108:34e6b704fe68 327 */
Kojto 108:34e6b704fe68 328 typedef struct
Kojto 108:34e6b704fe68 329 {
Kojto 108:34e6b704fe68 330 uint32_t CommandMode; /*!< Defines the command issued to the SDRAM device.
Kojto 108:34e6b704fe68 331 This parameter can be a value of @ref FMC_SDRAM_Command_Mode. */
Kojto 108:34e6b704fe68 332
Kojto 108:34e6b704fe68 333 uint32_t CommandTarget; /*!< Defines which device (1 or 2) the command will be issued to.
Kojto 108:34e6b704fe68 334 This parameter can be a value of @ref FMC_SDRAM_Command_Target. */
Kojto 108:34e6b704fe68 335
Kojto 108:34e6b704fe68 336 uint32_t AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued
Kojto 108:34e6b704fe68 337 in auto refresh mode.
Kojto 108:34e6b704fe68 338 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
Kojto 108:34e6b704fe68 339 uint32_t ModeRegisterDefinition; /*!< Defines the SDRAM Mode register content */
Kojto 108:34e6b704fe68 340 }FMC_SDRAM_CommandTypeDef;
Kojto 108:34e6b704fe68 341 /**
Kojto 108:34e6b704fe68 342 * @}
Kojto 108:34e6b704fe68 343 */
Kojto 108:34e6b704fe68 344
Kojto 108:34e6b704fe68 345 /* Private constants ---------------------------------------------------------*/
Kojto 108:34e6b704fe68 346 /** @defgroup FMC_LL_Private_Constants FMC Private Constants
Kojto 108:34e6b704fe68 347 * @{
Kojto 108:34e6b704fe68 348 */
Kojto 108:34e6b704fe68 349
Kojto 108:34e6b704fe68 350 /** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller
Kojto 108:34e6b704fe68 351 * @{
Kojto 108:34e6b704fe68 352 */
Kojto 108:34e6b704fe68 353 /** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank
Kojto 108:34e6b704fe68 354 * @{
Kojto 108:34e6b704fe68 355 */
Kojto 108:34e6b704fe68 356 #define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000)
Kojto 108:34e6b704fe68 357 #define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002)
Kojto 108:34e6b704fe68 358 #define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004)
Kojto 108:34e6b704fe68 359 #define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006)
Kojto 108:34e6b704fe68 360 /**
Kojto 108:34e6b704fe68 361 * @}
Kojto 108:34e6b704fe68 362 */
Kojto 108:34e6b704fe68 363
Kojto 108:34e6b704fe68 364 /** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing
Kojto 108:34e6b704fe68 365 * @{
Kojto 108:34e6b704fe68 366 */
Kojto 108:34e6b704fe68 367 #define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000)
Kojto 108:34e6b704fe68 368 #define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002)
Kojto 108:34e6b704fe68 369 /**
Kojto 108:34e6b704fe68 370 * @}
Kojto 108:34e6b704fe68 371 */
Kojto 108:34e6b704fe68 372
Kojto 108:34e6b704fe68 373 /** @defgroup FMC_Memory_Type FMC Memory Type
Kojto 108:34e6b704fe68 374 * @{
Kojto 108:34e6b704fe68 375 */
Kojto 108:34e6b704fe68 376 #define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000)
Kojto 108:34e6b704fe68 377 #define FMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004)
Kojto 108:34e6b704fe68 378 #define FMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008)
Kojto 108:34e6b704fe68 379 /**
Kojto 108:34e6b704fe68 380 * @}
Kojto 108:34e6b704fe68 381 */
Kojto 108:34e6b704fe68 382
Kojto 108:34e6b704fe68 383 /** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width
Kojto 108:34e6b704fe68 384 * @{
Kojto 108:34e6b704fe68 385 */
Kojto 108:34e6b704fe68 386 #define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
Kojto 108:34e6b704fe68 387 #define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
Kojto 108:34e6b704fe68 388 #define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
Kojto 108:34e6b704fe68 389 /**
Kojto 108:34e6b704fe68 390 * @}
Kojto 108:34e6b704fe68 391 */
Kojto 108:34e6b704fe68 392
Kojto 108:34e6b704fe68 393 /** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access
Kojto 108:34e6b704fe68 394 * @{
Kojto 108:34e6b704fe68 395 */
Kojto 108:34e6b704fe68 396 #define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040)
Kojto 108:34e6b704fe68 397 #define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000)
Kojto 108:34e6b704fe68 398 /**
Kojto 108:34e6b704fe68 399 * @}
Kojto 108:34e6b704fe68 400 */
Kojto 108:34e6b704fe68 401
Kojto 108:34e6b704fe68 402 /** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode
Kojto 108:34e6b704fe68 403 * @{
Kojto 108:34e6b704fe68 404 */
Kojto 108:34e6b704fe68 405 #define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000)
Kojto 108:34e6b704fe68 406 #define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100)
Kojto 108:34e6b704fe68 407 /**
Kojto 108:34e6b704fe68 408 * @}
Kojto 108:34e6b704fe68 409 */
Kojto 108:34e6b704fe68 410
Kojto 108:34e6b704fe68 411 /** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity
Kojto 108:34e6b704fe68 412 * @{
Kojto 108:34e6b704fe68 413 */
Kojto 108:34e6b704fe68 414 #define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000)
Kojto 108:34e6b704fe68 415 #define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200)
Kojto 108:34e6b704fe68 416 /**
Kojto 108:34e6b704fe68 417 * @}
Kojto 108:34e6b704fe68 418 */
Kojto 108:34e6b704fe68 419
Kojto 108:34e6b704fe68 420 /** @defgroup FMC_Wrap_Mode FMC Wrap Mode
Kojto 108:34e6b704fe68 421 * @{
Kojto 108:34e6b704fe68 422 */
Kojto 108:34e6b704fe68 423 /** @note This mode is not available for the STM32F446xx devices
Kojto 108:34e6b704fe68 424 */
Kojto 108:34e6b704fe68 425 #define FMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000)
Kojto 108:34e6b704fe68 426 #define FMC_WRAP_MODE_ENABLE ((uint32_t)0x00000400)
Kojto 108:34e6b704fe68 427 /**
Kojto 108:34e6b704fe68 428 * @}
Kojto 108:34e6b704fe68 429 */
Kojto 108:34e6b704fe68 430
Kojto 108:34e6b704fe68 431 /** @defgroup FMC_Wait_Timing FMC Wait Timing
Kojto 108:34e6b704fe68 432 * @{
Kojto 108:34e6b704fe68 433 */
Kojto 108:34e6b704fe68 434 #define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000)
Kojto 108:34e6b704fe68 435 #define FMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800)
Kojto 108:34e6b704fe68 436 /**
Kojto 108:34e6b704fe68 437 * @}
Kojto 108:34e6b704fe68 438 */
Kojto 108:34e6b704fe68 439
Kojto 108:34e6b704fe68 440 /** @defgroup FMC_Write_Operation FMC Write Operation
Kojto 108:34e6b704fe68 441 * @{
Kojto 108:34e6b704fe68 442 */
Kojto 108:34e6b704fe68 443 #define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000)
Kojto 108:34e6b704fe68 444 #define FMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000)
Kojto 108:34e6b704fe68 445 /**
Kojto 108:34e6b704fe68 446 * @}
Kojto 108:34e6b704fe68 447 */
Kojto 108:34e6b704fe68 448
Kojto 108:34e6b704fe68 449 /** @defgroup FMC_Wait_Signal FMC Wait Signal
Kojto 108:34e6b704fe68 450 * @{
Kojto 108:34e6b704fe68 451 */
Kojto 108:34e6b704fe68 452 #define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000)
Kojto 108:34e6b704fe68 453 #define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000)
Kojto 108:34e6b704fe68 454 /**
Kojto 108:34e6b704fe68 455 * @}
Kojto 108:34e6b704fe68 456 */
Kojto 108:34e6b704fe68 457
Kojto 108:34e6b704fe68 458 /** @defgroup FMC_Extended_Mode FMC Extended Mode
Kojto 108:34e6b704fe68 459 * @{
Kojto 108:34e6b704fe68 460 */
Kojto 108:34e6b704fe68 461 #define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000)
Kojto 108:34e6b704fe68 462 #define FMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000)
Kojto 108:34e6b704fe68 463 /**
Kojto 108:34e6b704fe68 464 * @}
Kojto 108:34e6b704fe68 465 */
Kojto 108:34e6b704fe68 466
Kojto 108:34e6b704fe68 467 /** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait
Kojto 108:34e6b704fe68 468 * @{
Kojto 108:34e6b704fe68 469 */
Kojto 108:34e6b704fe68 470 #define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000)
Kojto 108:34e6b704fe68 471 #define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000)
Kojto 108:34e6b704fe68 472 /**
Kojto 108:34e6b704fe68 473 * @}
Kojto 108:34e6b704fe68 474 */
Kojto 108:34e6b704fe68 475
Kojto 108:34e6b704fe68 476 /** @defgroup FMC_Page_Size FMC Page Size
Kojto 108:34e6b704fe68 477 * @note These values are available only for the STM32F446xx devices.
Kojto 108:34e6b704fe68 478 * @{
Kojto 108:34e6b704fe68 479 */
Kojto 108:34e6b704fe68 480 #define FMC_PAGE_SIZE_NONE ((uint32_t)0x00000000)
Kojto 108:34e6b704fe68 481 #define FMC_PAGE_SIZE_128 ((uint32_t)FMC_BCR1_CPSIZE_0)
Kojto 108:34e6b704fe68 482 #define FMC_PAGE_SIZE_256 ((uint32_t)FMC_BCR1_CPSIZE_1)
Kojto 108:34e6b704fe68 483 #define FMC_PAGE_SIZE_1024 ((uint32_t)FMC_BCR1_CPSIZE_2)
Kojto 108:34e6b704fe68 484 /**
Kojto 108:34e6b704fe68 485 * @}
Kojto 108:34e6b704fe68 486 */
Kojto 108:34e6b704fe68 487
Kojto 108:34e6b704fe68 488 /** @defgroup FMC_Write_FIFO FMC Write FIFO
Kojto 108:34e6b704fe68 489 * @note These values are available only for the STM32F446xx devices.
Kojto 108:34e6b704fe68 490 * @{
Kojto 108:34e6b704fe68 491 */
Kojto 108:34e6b704fe68 492 #define FMC_WRITE_FIFO_DISABLE ((uint32_t)0x00000000)
Kojto 108:34e6b704fe68 493 #define FMC_WRITE_FIFO_ENABLE ((uint32_t)FMC_BCR1_WFDIS)
Kojto 108:34e6b704fe68 494 /**
Kojto 108:34e6b704fe68 495 * @}
Kojto 108:34e6b704fe68 496 */
Kojto 108:34e6b704fe68 497
Kojto 108:34e6b704fe68 498 /** @defgroup FMC_Write_Burst FMC Write Burst
Kojto 108:34e6b704fe68 499 * @{
Kojto 108:34e6b704fe68 500 */
Kojto 108:34e6b704fe68 501 #define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000)
Kojto 108:34e6b704fe68 502 #define FMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000)
Kojto 108:34e6b704fe68 503 /**
Kojto 108:34e6b704fe68 504 * @}
Kojto 108:34e6b704fe68 505 */
Kojto 108:34e6b704fe68 506
Kojto 108:34e6b704fe68 507 /** @defgroup FMC_Continous_Clock FMC Continuous Clock
Kojto 108:34e6b704fe68 508 * @{
Kojto 108:34e6b704fe68 509 */
Kojto 108:34e6b704fe68 510 #define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000)
Kojto 108:34e6b704fe68 511 #define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000)
Kojto 108:34e6b704fe68 512 /**
Kojto 108:34e6b704fe68 513 * @}
Kojto 108:34e6b704fe68 514 */
Kojto 108:34e6b704fe68 515
Kojto 108:34e6b704fe68 516 /** @defgroup FMC_Access_Mode FMC Access Mode
Kojto 108:34e6b704fe68 517 * @{
Kojto 108:34e6b704fe68 518 */
Kojto 108:34e6b704fe68 519 #define FMC_ACCESS_MODE_A ((uint32_t)0x00000000)
Kojto 108:34e6b704fe68 520 #define FMC_ACCESS_MODE_B ((uint32_t)0x10000000)
Kojto 108:34e6b704fe68 521 #define FMC_ACCESS_MODE_C ((uint32_t)0x20000000)
Kojto 108:34e6b704fe68 522 #define FMC_ACCESS_MODE_D ((uint32_t)0x30000000)
Kojto 108:34e6b704fe68 523 /**
Kojto 108:34e6b704fe68 524 * @}
Kojto 108:34e6b704fe68 525 */
Kojto 108:34e6b704fe68 526
Kojto 108:34e6b704fe68 527 /**
Kojto 108:34e6b704fe68 528 * @}
Kojto 108:34e6b704fe68 529 */
Kojto 108:34e6b704fe68 530
Kojto 108:34e6b704fe68 531 /** @defgroup FMC_LL_NAND_Controller FMC NAND Controller
Kojto 108:34e6b704fe68 532 * @{
Kojto 108:34e6b704fe68 533 */
Kojto 108:34e6b704fe68 534 /** @defgroup FMC_NAND_Bank FMC NAND Bank
Kojto 108:34e6b704fe68 535 * @{
Kojto 108:34e6b704fe68 536 */
Kojto 108:34e6b704fe68 537 #define FMC_NAND_BANK2 ((uint32_t)0x00000010)
Kojto 108:34e6b704fe68 538 #define FMC_NAND_BANK3 ((uint32_t)0x00000100)
Kojto 108:34e6b704fe68 539 /**
Kojto 108:34e6b704fe68 540 * @}
Kojto 108:34e6b704fe68 541 */
Kojto 108:34e6b704fe68 542
Kojto 108:34e6b704fe68 543 /** @defgroup FMC_Wait_feature FMC Wait feature
Kojto 108:34e6b704fe68 544 * @{
Kojto 108:34e6b704fe68 545 */
Kojto 108:34e6b704fe68 546 #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000)
Kojto 108:34e6b704fe68 547 #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002)
Kojto 108:34e6b704fe68 548 /**
Kojto 108:34e6b704fe68 549 * @}
Kojto 108:34e6b704fe68 550 */
Kojto 108:34e6b704fe68 551
Kojto 108:34e6b704fe68 552 /** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type
Kojto 108:34e6b704fe68 553 * @{
Kojto 108:34e6b704fe68 554 */
Kojto 108:34e6b704fe68 555 #define FMC_PCR_MEMORY_TYPE_PCCARD ((uint32_t)0x00000000)
Kojto 108:34e6b704fe68 556 #define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008)
Kojto 108:34e6b704fe68 557 /**
Kojto 108:34e6b704fe68 558 * @}
Kojto 108:34e6b704fe68 559 */
Kojto 108:34e6b704fe68 560
Kojto 108:34e6b704fe68 561 /** @defgroup FMC_NAND_Data_Width FMC NAND Data Width
Kojto 108:34e6b704fe68 562 * @{
Kojto 108:34e6b704fe68 563 */
Kojto 108:34e6b704fe68 564 #define FMC_NAND_PCC_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
Kojto 108:34e6b704fe68 565 #define FMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
Kojto 108:34e6b704fe68 566 /**
Kojto 108:34e6b704fe68 567 * @}
Kojto 108:34e6b704fe68 568 */
Kojto 108:34e6b704fe68 569
Kojto 108:34e6b704fe68 570 /** @defgroup FMC_ECC FMC ECC
Kojto 108:34e6b704fe68 571 * @{
Kojto 108:34e6b704fe68 572 */
Kojto 108:34e6b704fe68 573 #define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000)
Kojto 108:34e6b704fe68 574 #define FMC_NAND_ECC_ENABLE ((uint32_t)0x00000040)
Kojto 108:34e6b704fe68 575 /**
Kojto 108:34e6b704fe68 576 * @}
Kojto 108:34e6b704fe68 577 */
Kojto 108:34e6b704fe68 578
Kojto 108:34e6b704fe68 579 /** @defgroup FMC_ECC_Page_Size FMC ECC Page Size
Kojto 108:34e6b704fe68 580 * @{
Kojto 108:34e6b704fe68 581 */
Kojto 108:34e6b704fe68 582 #define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000)
Kojto 108:34e6b704fe68 583 #define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000)
Kojto 108:34e6b704fe68 584 #define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000)
Kojto 108:34e6b704fe68 585 #define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000)
Kojto 108:34e6b704fe68 586 #define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000)
Kojto 108:34e6b704fe68 587 #define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000)
Kojto 108:34e6b704fe68 588 /**
Kojto 108:34e6b704fe68 589 * @}
Kojto 108:34e6b704fe68 590 */
Kojto 108:34e6b704fe68 591
Kojto 108:34e6b704fe68 592 /**
Kojto 108:34e6b704fe68 593 * @}
Kojto 108:34e6b704fe68 594 */
Kojto 108:34e6b704fe68 595
Kojto 108:34e6b704fe68 596 /** @defgroup FMC_LL_SDRAM_Controller FMC SDRAM Controller
Kojto 108:34e6b704fe68 597 * @{
Kojto 108:34e6b704fe68 598 */
Kojto 108:34e6b704fe68 599 /** @defgroup FMC_SDRAM_Bank FMC SDRAM Bank
Kojto 108:34e6b704fe68 600 * @{
Kojto 108:34e6b704fe68 601 */
Kojto 108:34e6b704fe68 602 #define FMC_SDRAM_BANK1 ((uint32_t)0x00000000)
Kojto 108:34e6b704fe68 603 #define FMC_SDRAM_BANK2 ((uint32_t)0x00000001)
Kojto 108:34e6b704fe68 604 /**
Kojto 108:34e6b704fe68 605 * @}
Kojto 108:34e6b704fe68 606 */
Kojto 108:34e6b704fe68 607
Kojto 108:34e6b704fe68 608 /** @defgroup FMC_SDRAM_Column_Bits_number FMC SDRAM Column Bits number
Kojto 108:34e6b704fe68 609 * @{
Kojto 108:34e6b704fe68 610 */
Kojto 108:34e6b704fe68 611 #define FMC_SDRAM_COLUMN_BITS_NUM_8 ((uint32_t)0x00000000)
Kojto 108:34e6b704fe68 612 #define FMC_SDRAM_COLUMN_BITS_NUM_9 ((uint32_t)0x00000001)
Kojto 108:34e6b704fe68 613 #define FMC_SDRAM_COLUMN_BITS_NUM_10 ((uint32_t)0x00000002)
Kojto 108:34e6b704fe68 614 #define FMC_SDRAM_COLUMN_BITS_NUM_11 ((uint32_t)0x00000003)
Kojto 108:34e6b704fe68 615 /**
Kojto 108:34e6b704fe68 616 * @}
Kojto 108:34e6b704fe68 617 */
Kojto 108:34e6b704fe68 618
Kojto 108:34e6b704fe68 619 /** @defgroup FMC_SDRAM_Row_Bits_number FMC SDRAM Row Bits number
Kojto 108:34e6b704fe68 620 * @{
Kojto 108:34e6b704fe68 621 */
Kojto 108:34e6b704fe68 622 #define FMC_SDRAM_ROW_BITS_NUM_11 ((uint32_t)0x00000000)
Kojto 108:34e6b704fe68 623 #define FMC_SDRAM_ROW_BITS_NUM_12 ((uint32_t)0x00000004)
Kojto 108:34e6b704fe68 624 #define FMC_SDRAM_ROW_BITS_NUM_13 ((uint32_t)0x00000008)
Kojto 108:34e6b704fe68 625 /**
Kojto 108:34e6b704fe68 626 * @}
Kojto 108:34e6b704fe68 627 */
Kojto 108:34e6b704fe68 628
Kojto 108:34e6b704fe68 629 /** @defgroup FMC_SDRAM_Memory_Bus_Width FMC SDRAM Memory Bus Width
Kojto 108:34e6b704fe68 630 * @{
Kojto 108:34e6b704fe68 631 */
Kojto 108:34e6b704fe68 632 #define FMC_SDRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
Kojto 108:34e6b704fe68 633 #define FMC_SDRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
Kojto 108:34e6b704fe68 634 #define FMC_SDRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
Kojto 108:34e6b704fe68 635 /**
Kojto 108:34e6b704fe68 636 * @}
Kojto 108:34e6b704fe68 637 */
Kojto 108:34e6b704fe68 638
Kojto 108:34e6b704fe68 639 /** @defgroup FMC_SDRAM_Internal_Banks_Number FMC SDRAM Internal Banks Number
Kojto 108:34e6b704fe68 640 * @{
Kojto 108:34e6b704fe68 641 */
Kojto 108:34e6b704fe68 642 #define FMC_SDRAM_INTERN_BANKS_NUM_2 ((uint32_t)0x00000000)
Kojto 108:34e6b704fe68 643 #define FMC_SDRAM_INTERN_BANKS_NUM_4 ((uint32_t)0x00000040)
Kojto 108:34e6b704fe68 644 /**
Kojto 108:34e6b704fe68 645 * @}
Kojto 108:34e6b704fe68 646 */
Kojto 108:34e6b704fe68 647
Kojto 108:34e6b704fe68 648 /** @defgroup FMC_SDRAM_CAS_Latency FMC SDRAM CAS Latency
Kojto 108:34e6b704fe68 649 * @{
Kojto 108:34e6b704fe68 650 */
Kojto 108:34e6b704fe68 651 #define FMC_SDRAM_CAS_LATENCY_1 ((uint32_t)0x00000080)
Kojto 108:34e6b704fe68 652 #define FMC_SDRAM_CAS_LATENCY_2 ((uint32_t)0x00000100)
Kojto 108:34e6b704fe68 653 #define FMC_SDRAM_CAS_LATENCY_3 ((uint32_t)0x00000180)
Kojto 108:34e6b704fe68 654 /**
Kojto 108:34e6b704fe68 655 * @}
Kojto 108:34e6b704fe68 656 */
Kojto 108:34e6b704fe68 657
Kojto 108:34e6b704fe68 658 /** @defgroup FMC_SDRAM_Write_Protection FMC SDRAM Write Protection
Kojto 108:34e6b704fe68 659 * @{
Kojto 108:34e6b704fe68 660 */
Kojto 108:34e6b704fe68 661 #define FMC_SDRAM_WRITE_PROTECTION_DISABLE ((uint32_t)0x00000000)
Kojto 108:34e6b704fe68 662 #define FMC_SDRAM_WRITE_PROTECTION_ENABLE ((uint32_t)0x00000200)
Kojto 108:34e6b704fe68 663
Kojto 108:34e6b704fe68 664 /**
Kojto 108:34e6b704fe68 665 * @}
Kojto 108:34e6b704fe68 666 */
Kojto 108:34e6b704fe68 667
Kojto 108:34e6b704fe68 668 /** @defgroup FMC_SDRAM_Clock_Period FMC SDRAM Clock Period
Kojto 108:34e6b704fe68 669 * @{
Kojto 108:34e6b704fe68 670 */
Kojto 108:34e6b704fe68 671 #define FMC_SDRAM_CLOCK_DISABLE ((uint32_t)0x00000000)
Kojto 108:34e6b704fe68 672 #define FMC_SDRAM_CLOCK_PERIOD_2 ((uint32_t)0x00000800)
Kojto 108:34e6b704fe68 673 #define FMC_SDRAM_CLOCK_PERIOD_3 ((uint32_t)0x00000C00)
Kojto 108:34e6b704fe68 674 /**
Kojto 108:34e6b704fe68 675 * @}
Kojto 108:34e6b704fe68 676 */
Kojto 108:34e6b704fe68 677
Kojto 108:34e6b704fe68 678 /** @defgroup FMC_SDRAM_Read_Burst FMC SDRAM Read Burst
Kojto 108:34e6b704fe68 679 * @{
Kojto 108:34e6b704fe68 680 */
Kojto 108:34e6b704fe68 681 #define FMC_SDRAM_RBURST_DISABLE ((uint32_t)0x00000000)
Kojto 108:34e6b704fe68 682 #define FMC_SDRAM_RBURST_ENABLE ((uint32_t)0x00001000)
Kojto 108:34e6b704fe68 683 /**
Kojto 108:34e6b704fe68 684 * @}
Kojto 108:34e6b704fe68 685 */
Kojto 108:34e6b704fe68 686
Kojto 108:34e6b704fe68 687 /** @defgroup FMC_SDRAM_Read_Pipe_Delay FMC SDRAM Read Pipe Delay
Kojto 108:34e6b704fe68 688 * @{
Kojto 108:34e6b704fe68 689 */
Kojto 108:34e6b704fe68 690 #define FMC_SDRAM_RPIPE_DELAY_0 ((uint32_t)0x00000000)
Kojto 108:34e6b704fe68 691 #define FMC_SDRAM_RPIPE_DELAY_1 ((uint32_t)0x00002000)
Kojto 108:34e6b704fe68 692 #define FMC_SDRAM_RPIPE_DELAY_2 ((uint32_t)0x00004000)
Kojto 108:34e6b704fe68 693 /**
Kojto 108:34e6b704fe68 694 * @}
Kojto 108:34e6b704fe68 695 */
Kojto 108:34e6b704fe68 696
Kojto 108:34e6b704fe68 697 /** @defgroup FMC_SDRAM_Command_Mode FMC SDRAM Command Mode
Kojto 108:34e6b704fe68 698 * @{
Kojto 108:34e6b704fe68 699 */
Kojto 108:34e6b704fe68 700 #define FMC_SDRAM_CMD_NORMAL_MODE ((uint32_t)0x00000000)
Kojto 108:34e6b704fe68 701 #define FMC_SDRAM_CMD_CLK_ENABLE ((uint32_t)0x00000001)
Kojto 108:34e6b704fe68 702 #define FMC_SDRAM_CMD_PALL ((uint32_t)0x00000002)
Kojto 108:34e6b704fe68 703 #define FMC_SDRAM_CMD_AUTOREFRESH_MODE ((uint32_t)0x00000003)
Kojto 108:34e6b704fe68 704 #define FMC_SDRAM_CMD_LOAD_MODE ((uint32_t)0x00000004)
Kojto 108:34e6b704fe68 705 #define FMC_SDRAM_CMD_SELFREFRESH_MODE ((uint32_t)0x00000005)
Kojto 108:34e6b704fe68 706 #define FMC_SDRAM_CMD_POWERDOWN_MODE ((uint32_t)0x00000006)
Kojto 108:34e6b704fe68 707 /**
Kojto 108:34e6b704fe68 708 * @}
Kojto 108:34e6b704fe68 709 */
Kojto 108:34e6b704fe68 710
Kojto 108:34e6b704fe68 711 /** @defgroup FMC_SDRAM_Command_Target FMC SDRAM Command Target
Kojto 108:34e6b704fe68 712 * @{
Kojto 108:34e6b704fe68 713 */
Kojto 108:34e6b704fe68 714 #define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2
Kojto 108:34e6b704fe68 715 #define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1
Kojto 108:34e6b704fe68 716 #define FMC_SDRAM_CMD_TARGET_BANK1_2 ((uint32_t)0x00000018)
Kojto 108:34e6b704fe68 717 /**
Kojto 108:34e6b704fe68 718 * @}
Kojto 108:34e6b704fe68 719 */
Kojto 108:34e6b704fe68 720
Kojto 108:34e6b704fe68 721 /** @defgroup FMC_SDRAM_Mode_Status FMC SDRAM Mode Status
Kojto 108:34e6b704fe68 722 * @{
Kojto 108:34e6b704fe68 723 */
Kojto 108:34e6b704fe68 724 #define FMC_SDRAM_NORMAL_MODE ((uint32_t)0x00000000)
Kojto 108:34e6b704fe68 725 #define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0
Kojto 108:34e6b704fe68 726 #define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1
Kojto 108:34e6b704fe68 727 /**
Kojto 108:34e6b704fe68 728 * @}
Kojto 108:34e6b704fe68 729 */
Kojto 108:34e6b704fe68 730
Kojto 108:34e6b704fe68 731 /**
Kojto 108:34e6b704fe68 732 * @}
Kojto 108:34e6b704fe68 733 */
Kojto 108:34e6b704fe68 734
Kojto 108:34e6b704fe68 735 /** @defgroup FMC_LL_Interrupt_definition FMC Interrupt definition
Kojto 108:34e6b704fe68 736 * @{
Kojto 108:34e6b704fe68 737 */
Kojto 108:34e6b704fe68 738 #define FMC_IT_RISING_EDGE ((uint32_t)0x00000008)
Kojto 108:34e6b704fe68 739 #define FMC_IT_LEVEL ((uint32_t)0x00000010)
Kojto 108:34e6b704fe68 740 #define FMC_IT_FALLING_EDGE ((uint32_t)0x00000020)
Kojto 108:34e6b704fe68 741 #define FMC_IT_REFRESH_ERROR ((uint32_t)0x00004000)
Kojto 108:34e6b704fe68 742 /**
Kojto 108:34e6b704fe68 743 * @}
Kojto 108:34e6b704fe68 744 */
Kojto 108:34e6b704fe68 745
Kojto 108:34e6b704fe68 746 /** @defgroup FMC_LL_Flag_definition FMC Flag definition
Kojto 108:34e6b704fe68 747 * @{
Kojto 108:34e6b704fe68 748 */
Kojto 108:34e6b704fe68 749 #define FMC_FLAG_RISING_EDGE ((uint32_t)0x00000001)
Kojto 108:34e6b704fe68 750 #define FMC_FLAG_LEVEL ((uint32_t)0x00000002)
Kojto 108:34e6b704fe68 751 #define FMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004)
Kojto 108:34e6b704fe68 752 #define FMC_FLAG_FEMPT ((uint32_t)0x00000040)
Kojto 108:34e6b704fe68 753 #define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE
Kojto 108:34e6b704fe68 754 #define FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY
Kojto 108:34e6b704fe68 755 #define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE
Kojto 108:34e6b704fe68 756 /**
Kojto 108:34e6b704fe68 757 * @}
Kojto 108:34e6b704fe68 758 */
Kojto 108:34e6b704fe68 759
Kojto 108:34e6b704fe68 760 /** @defgroup FMC_LL_Alias_definition FMC Alias definition
Kojto 108:34e6b704fe68 761 * @{
Kojto 108:34e6b704fe68 762 */
Kojto 108:34e6b704fe68 763 #if defined(STM32F446xx)
Kojto 108:34e6b704fe68 764 #define FMC_NAND_TypeDef FMC_Bank3_TypeDef
Kojto 108:34e6b704fe68 765 #else
Kojto 108:34e6b704fe68 766 #define FMC_NAND_TypeDef FMC_Bank2_3_TypeDef
Kojto 108:34e6b704fe68 767 #define FMC_PCCARD_TypeDef FMC_Bank4_TypeDef
Kojto 108:34e6b704fe68 768 #endif /* defined(STM32F446xx) */
Kojto 108:34e6b704fe68 769 #define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef
Kojto 108:34e6b704fe68 770 #define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef
Kojto 108:34e6b704fe68 771 #define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef
Kojto 108:34e6b704fe68 772
Kojto 108:34e6b704fe68 773
Kojto 108:34e6b704fe68 774 #if defined(STM32F446xx)
Kojto 108:34e6b704fe68 775 #define FMC_NAND_DEVICE FMC_Bank3
Kojto 108:34e6b704fe68 776 #else
Kojto 108:34e6b704fe68 777 #define FMC_NAND_DEVICE FMC_Bank2_3
Kojto 108:34e6b704fe68 778 #define FMC_PCCARD_DEVICE FMC_Bank4
Kojto 108:34e6b704fe68 779 #endif /* defined(STM32F446xx) */
Kojto 108:34e6b704fe68 780 #define FMC_NORSRAM_DEVICE FMC_Bank1
Kojto 108:34e6b704fe68 781 #define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E
Kojto 108:34e6b704fe68 782 #define FMC_SDRAM_DEVICE FMC_Bank5_6
Kojto 108:34e6b704fe68 783 /**
Kojto 108:34e6b704fe68 784 * @}
Kojto 108:34e6b704fe68 785 */
Kojto 108:34e6b704fe68 786
Kojto 108:34e6b704fe68 787 /**
Kojto 108:34e6b704fe68 788 * @}
Kojto 108:34e6b704fe68 789 */
Kojto 108:34e6b704fe68 790
Kojto 108:34e6b704fe68 791 /* Private macro -------------------------------------------------------------*/
Kojto 108:34e6b704fe68 792 /** @defgroup FMC_LL_Private_Macros FMC Private Macros
Kojto 108:34e6b704fe68 793 * @{
Kojto 108:34e6b704fe68 794 */
Kojto 108:34e6b704fe68 795
Kojto 108:34e6b704fe68 796 /** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros
Kojto 108:34e6b704fe68 797 * @brief macros to handle NOR device enable/disable and read/write operations
Kojto 108:34e6b704fe68 798 * @{
Kojto 108:34e6b704fe68 799 */
Kojto 108:34e6b704fe68 800 /**
Kojto 108:34e6b704fe68 801 * @brief Enable the NORSRAM device access.
Kojto 108:34e6b704fe68 802 * @param __INSTANCE__: FMC_NORSRAM Instance
Kojto 108:34e6b704fe68 803 * @param __BANK__: FMC_NORSRAM Bank
Kojto 108:34e6b704fe68 804 * @retval None
Kojto 108:34e6b704fe68 805 */
Kojto 108:34e6b704fe68 806 #define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FMC_BCR1_MBKEN)
Kojto 108:34e6b704fe68 807
Kojto 108:34e6b704fe68 808 /**
Kojto 108:34e6b704fe68 809 * @brief Disable the NORSRAM device access.
Kojto 108:34e6b704fe68 810 * @param __INSTANCE__: FMC_NORSRAM Instance
Kojto 108:34e6b704fe68 811 * @param __BANK__: FMC_NORSRAM Bank
Kojto 108:34e6b704fe68 812 * @retval None
Kojto 108:34e6b704fe68 813 */
Kojto 108:34e6b704fe68 814 #define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCR1_MBKEN)
Kojto 108:34e6b704fe68 815 /**
Kojto 108:34e6b704fe68 816 * @}
Kojto 108:34e6b704fe68 817 */
Kojto 108:34e6b704fe68 818
Kojto 108:34e6b704fe68 819 /** @defgroup FMC_LL_NAND_Macros FMC NAND Macros
Kojto 108:34e6b704fe68 820 * @brief macros to handle NAND device enable/disable
Kojto 108:34e6b704fe68 821 * @{
Kojto 108:34e6b704fe68 822 */
Kojto 108:34e6b704fe68 823 #if defined(STM32F446xx)
Kojto 108:34e6b704fe68 824 /**
Kojto 108:34e6b704fe68 825 * @brief Enable the NAND device access.
Kojto 108:34e6b704fe68 826 * @param __INSTANCE__: FMC_NAND Instance
Kojto 108:34e6b704fe68 827 * @param __BANK__: FMC_NAND Bank
Kojto 108:34e6b704fe68 828 * @retval None
Kojto 108:34e6b704fe68 829 */
Kojto 108:34e6b704fe68 830 #define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->PCR |= FMC_PCR_PBKEN)
Kojto 108:34e6b704fe68 831
Kojto 108:34e6b704fe68 832 /**
Kojto 108:34e6b704fe68 833 * @brief Disable the NAND device access.
Kojto 108:34e6b704fe68 834 * @param __INSTANCE__: FMC_NAND Instance
Kojto 108:34e6b704fe68 835 * @param __BANK__: FMC_NAND Bank
Kojto 108:34e6b704fe68 836 * @retval None
Kojto 108:34e6b704fe68 837 */
Kojto 108:34e6b704fe68 838 #define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->PCR &= ~FMC_PCR_PBKEN)
Kojto 108:34e6b704fe68 839 #else /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */
Kojto 108:34e6b704fe68 840 /**
Kojto 108:34e6b704fe68 841 * @brief Enable the NAND device access.
Kojto 108:34e6b704fe68 842 * @param __INSTANCE__: FMC_NAND Instance
Kojto 108:34e6b704fe68 843 * @param __BANK__: FMC_NAND Bank
Kojto 108:34e6b704fe68 844 * @retval None
Kojto 108:34e6b704fe68 845 */
Kojto 108:34e6b704fe68 846 #define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FMC_PCR2_PBKEN): \
Kojto 108:34e6b704fe68 847 ((__INSTANCE__)->PCR3 |= FMC_PCR3_PBKEN))
Kojto 108:34e6b704fe68 848
Kojto 108:34e6b704fe68 849 /**
Kojto 108:34e6b704fe68 850 * @brief Disable the NAND device access.
Kojto 108:34e6b704fe68 851 * @param __INSTANCE__: FMC_NAND Instance
Kojto 108:34e6b704fe68 852 * @param __BANK__: FMC_NAND Bank
Kojto 108:34e6b704fe68 853 * @retval None
Kojto 108:34e6b704fe68 854 */
Kojto 108:34e6b704fe68 855 #define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FMC_PCR2_PBKEN): \
Kojto 108:34e6b704fe68 856 ((__INSTANCE__)->PCR3 &= ~FMC_PCR3_PBKEN))
Kojto 108:34e6b704fe68 857
Kojto 108:34e6b704fe68 858 #endif /* defined(STM32F446xx)*/
Kojto 108:34e6b704fe68 859 /**
Kojto 108:34e6b704fe68 860 * @}
Kojto 108:34e6b704fe68 861 */
Kojto 108:34e6b704fe68 862 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
Kojto 108:34e6b704fe68 863 /** @defgroup FMC_LL_PCCARD_Macros FMC PCCARD Macros
Kojto 108:34e6b704fe68 864 * @brief macros to handle SRAM read/write operations
Kojto 108:34e6b704fe68 865 * @{
Kojto 108:34e6b704fe68 866 */
Kojto 108:34e6b704fe68 867 /**
Kojto 108:34e6b704fe68 868 * @brief Enable the PCCARD device access.
Kojto 108:34e6b704fe68 869 * @param __INSTANCE__: FMC_PCCARD Instance
Kojto 108:34e6b704fe68 870 * @retval None
Kojto 108:34e6b704fe68 871 */
Kojto 108:34e6b704fe68 872 #define __FMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 |= FMC_PCR4_PBKEN)
Kojto 108:34e6b704fe68 873
Kojto 108:34e6b704fe68 874 /**
Kojto 108:34e6b704fe68 875 * @brief Disable the PCCARD device access.
Kojto 108:34e6b704fe68 876 * @param __INSTANCE__: FMC_PCCARD Instance
Kojto 108:34e6b704fe68 877 * @retval None
Kojto 108:34e6b704fe68 878 */
Kojto 108:34e6b704fe68 879 #define __FMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FMC_PCR4_PBKEN)
Kojto 108:34e6b704fe68 880 /**
Kojto 108:34e6b704fe68 881 * @}
Kojto 108:34e6b704fe68 882 */
Kojto 108:34e6b704fe68 883 #endif /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */
Kojto 108:34e6b704fe68 884
Kojto 108:34e6b704fe68 885 /** @defgroup FMC_LL_Flag_Interrupt_Macros FMC Flag&Interrupt Macros
Kojto 108:34e6b704fe68 886 * @brief macros to handle FMC flags and interrupts
Kojto 108:34e6b704fe68 887 * @{
Kojto 108:34e6b704fe68 888 */
Kojto 108:34e6b704fe68 889 #if defined(STM32F446xx)
Kojto 108:34e6b704fe68 890 /**
Kojto 108:34e6b704fe68 891 * @brief Enable the NAND device interrupt.
Kojto 108:34e6b704fe68 892 * @param __INSTANCE__: FMC_NAND instance
Kojto 108:34e6b704fe68 893 * @param __BANK__: FMC_NAND Bank
Kojto 108:34e6b704fe68 894 * @param __INTERRUPT__: FMC_NAND interrupt
Kojto 108:34e6b704fe68 895 * This parameter can be any combination of the following values:
Kojto 108:34e6b704fe68 896 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
Kojto 108:34e6b704fe68 897 * @arg FMC_IT_LEVEL: Interrupt level.
Kojto 108:34e6b704fe68 898 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
Kojto 108:34e6b704fe68 899 * @retval None
Kojto 108:34e6b704fe68 900 */
Kojto 108:34e6b704fe68 901 #define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) ((__INSTANCE__)->SR |= (__INTERRUPT__))
Kojto 108:34e6b704fe68 902
Kojto 108:34e6b704fe68 903 /**
Kojto 108:34e6b704fe68 904 * @brief Disable the NAND device interrupt.
Kojto 108:34e6b704fe68 905 * @param __INSTANCE__: FMC_NAND Instance
Kojto 108:34e6b704fe68 906 * @param __BANK__: FMC_NAND Bank
Kojto 108:34e6b704fe68 907 * @param __INTERRUPT__: FMC_NAND interrupt
Kojto 108:34e6b704fe68 908 * This parameter can be any combination of the following values:
Kojto 108:34e6b704fe68 909 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
Kojto 108:34e6b704fe68 910 * @arg FMC_IT_LEVEL: Interrupt level.
Kojto 108:34e6b704fe68 911 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
Kojto 108:34e6b704fe68 912 * @retval None
Kojto 108:34e6b704fe68 913 */
Kojto 108:34e6b704fe68 914 #define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__))
Kojto 108:34e6b704fe68 915
Kojto 108:34e6b704fe68 916 /**
Kojto 108:34e6b704fe68 917 * @brief Get flag status of the NAND device.
Kojto 108:34e6b704fe68 918 * @param __INSTANCE__: FMC_NAND Instance
Kojto 108:34e6b704fe68 919 * @param __BANK__: FMC_NAND Bank
Kojto 108:34e6b704fe68 920 * @param __FLAG__: FMC_NAND flag
Kojto 108:34e6b704fe68 921 * This parameter can be any combination of the following values:
Kojto 108:34e6b704fe68 922 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
Kojto 108:34e6b704fe68 923 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
Kojto 108:34e6b704fe68 924 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
Kojto 108:34e6b704fe68 925 * @arg FMC_FLAG_FEMPT: FIFO empty flag.
Kojto 108:34e6b704fe68 926 * @retval The state of FLAG (SET or RESET).
Kojto 108:34e6b704fe68 927 */
Kojto 108:34e6b704fe68 928 #define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__))
Kojto 108:34e6b704fe68 929 /**
Kojto 108:34e6b704fe68 930 * @brief Clear flag status of the NAND device.
Kojto 108:34e6b704fe68 931 * @param __INSTANCE__: FMC_NAND Instance
Kojto 108:34e6b704fe68 932 * @param __BANK__: FMC_NAND Bank
Kojto 108:34e6b704fe68 933 * @param __FLAG__: FMC_NAND flag
Kojto 108:34e6b704fe68 934 * This parameter can be any combination of the following values:
Kojto 108:34e6b704fe68 935 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
Kojto 108:34e6b704fe68 936 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
Kojto 108:34e6b704fe68 937 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
Kojto 108:34e6b704fe68 938 * @arg FMC_FLAG_FEMPT: FIFO empty flag.
Kojto 108:34e6b704fe68 939 * @retval None
Kojto 108:34e6b704fe68 940 */
Kojto 108:34e6b704fe68 941 #define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) ((__INSTANCE__)->SR &= ~(__FLAG__))
Kojto 108:34e6b704fe68 942 #else /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */
Kojto 108:34e6b704fe68 943 /**
Kojto 108:34e6b704fe68 944 * @brief Enable the NAND device interrupt.
Kojto 108:34e6b704fe68 945 * @param __INSTANCE__: FMC_NAND instance
Kojto 108:34e6b704fe68 946 * @param __BANK__: FMC_NAND Bank
Kojto 108:34e6b704fe68 947 * @param __INTERRUPT__: FMC_NAND interrupt
Kojto 108:34e6b704fe68 948 * This parameter can be any combination of the following values:
Kojto 108:34e6b704fe68 949 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
Kojto 108:34e6b704fe68 950 * @arg FMC_IT_LEVEL: Interrupt level.
Kojto 108:34e6b704fe68 951 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
Kojto 108:34e6b704fe68 952 * @retval None
Kojto 108:34e6b704fe68 953 */
Kojto 108:34e6b704fe68 954 #define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 |= (__INTERRUPT__)): \
Kojto 108:34e6b704fe68 955 ((__INSTANCE__)->SR3 |= (__INTERRUPT__)))
Kojto 108:34e6b704fe68 956
Kojto 108:34e6b704fe68 957 /**
Kojto 108:34e6b704fe68 958 * @brief Disable the NAND device interrupt.
Kojto 108:34e6b704fe68 959 * @param __INSTANCE__: FMC_NAND Instance
Kojto 108:34e6b704fe68 960 * @param __BANK__: FMC_NAND Bank
Kojto 108:34e6b704fe68 961 * @param __INTERRUPT__: FMC_NAND interrupt
Kojto 108:34e6b704fe68 962 * This parameter can be any combination of the following values:
Kojto 108:34e6b704fe68 963 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
Kojto 108:34e6b704fe68 964 * @arg FMC_IT_LEVEL: Interrupt level.
Kojto 108:34e6b704fe68 965 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
Kojto 108:34e6b704fe68 966 * @retval None
Kojto 108:34e6b704fe68 967 */
Kojto 108:34e6b704fe68 968 #define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
Kojto 108:34e6b704fe68 969 ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
Kojto 108:34e6b704fe68 970
Kojto 108:34e6b704fe68 971 /**
Kojto 108:34e6b704fe68 972 * @brief Get flag status of the NAND device.
Kojto 108:34e6b704fe68 973 * @param __INSTANCE__: FMC_NAND Instance
Kojto 108:34e6b704fe68 974 * @param __BANK__: FMC_NAND Bank
Kojto 108:34e6b704fe68 975 * @param __FLAG__: FMC_NAND flag
Kojto 108:34e6b704fe68 976 * This parameter can be any combination of the following values:
Kojto 108:34e6b704fe68 977 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
Kojto 108:34e6b704fe68 978 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
Kojto 108:34e6b704fe68 979 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
Kojto 108:34e6b704fe68 980 * @arg FMC_FLAG_FEMPT: FIFO empty flag.
Kojto 108:34e6b704fe68 981 * @retval The state of FLAG (SET or RESET).
Kojto 108:34e6b704fe68 982 */
Kojto 108:34e6b704fe68 983 #define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
Kojto 108:34e6b704fe68 984 (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
Kojto 108:34e6b704fe68 985 /**
Kojto 108:34e6b704fe68 986 * @brief Clear flag status of the NAND device.
Kojto 108:34e6b704fe68 987 * @param __INSTANCE__: FMC_NAND Instance
Kojto 108:34e6b704fe68 988 * @param __BANK__: FMC_NAND Bank
Kojto 108:34e6b704fe68 989 * @param __FLAG__: FMC_NAND flag
Kojto 108:34e6b704fe68 990 * This parameter can be any combination of the following values:
Kojto 108:34e6b704fe68 991 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
Kojto 108:34e6b704fe68 992 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
Kojto 108:34e6b704fe68 993 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
Kojto 108:34e6b704fe68 994 * @arg FMC_FLAG_FEMPT: FIFO empty flag.
Kojto 108:34e6b704fe68 995 * @retval None
Kojto 108:34e6b704fe68 996 */
Kojto 108:34e6b704fe68 997 #define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
Kojto 108:34e6b704fe68 998 ((__INSTANCE__)->SR3 &= ~(__FLAG__)))
Kojto 108:34e6b704fe68 999 #endif /* defined(STM32F446xx) */
Kojto 108:34e6b704fe68 1000
Kojto 108:34e6b704fe68 1001 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
Kojto 108:34e6b704fe68 1002 /**
Kojto 108:34e6b704fe68 1003 * @brief Enable the PCCARD device interrupt.
Kojto 108:34e6b704fe68 1004 * @param __INSTANCE__: FMC_PCCARD instance
Kojto 108:34e6b704fe68 1005 * @param __INTERRUPT__: FMC_PCCARD interrupt
Kojto 108:34e6b704fe68 1006 * This parameter can be any combination of the following values:
Kojto 108:34e6b704fe68 1007 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
Kojto 108:34e6b704fe68 1008 * @arg FMC_IT_LEVEL: Interrupt level.
Kojto 108:34e6b704fe68 1009 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
Kojto 108:34e6b704fe68 1010 * @retval None
Kojto 108:34e6b704fe68 1011 */
Kojto 108:34e6b704fe68 1012 #define __FMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 |= (__INTERRUPT__))
Kojto 108:34e6b704fe68 1013
Kojto 108:34e6b704fe68 1014 /**
Kojto 108:34e6b704fe68 1015 * @brief Disable the PCCARD device interrupt.
Kojto 108:34e6b704fe68 1016 * @param __INSTANCE__: FMC_PCCARD instance
Kojto 108:34e6b704fe68 1017 * @param __INTERRUPT__: FMC_PCCARD interrupt
Kojto 108:34e6b704fe68 1018 * This parameter can be any combination of the following values:
Kojto 108:34e6b704fe68 1019 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
Kojto 108:34e6b704fe68 1020 * @arg FMC_IT_LEVEL: Interrupt level.
Kojto 108:34e6b704fe68 1021 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
Kojto 108:34e6b704fe68 1022 * @retval None
Kojto 108:34e6b704fe68 1023 */
Kojto 108:34e6b704fe68 1024 #define __FMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
Kojto 108:34e6b704fe68 1025
Kojto 108:34e6b704fe68 1026 /**
Kojto 108:34e6b704fe68 1027 * @brief Get flag status of the PCCARD device.
Kojto 108:34e6b704fe68 1028 * @param __INSTANCE__: FMC_PCCARD instance
Kojto 108:34e6b704fe68 1029 * @param __FLAG__: FMC_PCCARD flag
Kojto 108:34e6b704fe68 1030 * This parameter can be any combination of the following values:
Kojto 108:34e6b704fe68 1031 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
Kojto 108:34e6b704fe68 1032 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
Kojto 108:34e6b704fe68 1033 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
Kojto 108:34e6b704fe68 1034 * @arg FMC_FLAG_FEMPT: FIFO empty flag.
Kojto 108:34e6b704fe68 1035 * @retval The state of FLAG (SET or RESET).
Kojto 108:34e6b704fe68 1036 */
Kojto 108:34e6b704fe68 1037 #define __FMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
Kojto 108:34e6b704fe68 1038
Kojto 108:34e6b704fe68 1039 /**
Kojto 108:34e6b704fe68 1040 * @brief Clear flag status of the PCCARD device.
Kojto 108:34e6b704fe68 1041 * @param __INSTANCE__: FMC_PCCARD instance
Kojto 108:34e6b704fe68 1042 * @param __FLAG__: FMC_PCCARD flag
Kojto 108:34e6b704fe68 1043 * This parameter can be any combination of the following values:
Kojto 108:34e6b704fe68 1044 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
Kojto 108:34e6b704fe68 1045 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
Kojto 108:34e6b704fe68 1046 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
Kojto 108:34e6b704fe68 1047 * @arg FMC_FLAG_FEMPT: FIFO empty flag.
Kojto 108:34e6b704fe68 1048 * @retval None
Kojto 108:34e6b704fe68 1049 */
Kojto 108:34e6b704fe68 1050 #define __FMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
Kojto 108:34e6b704fe68 1051 #endif /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */
Kojto 108:34e6b704fe68 1052
Kojto 108:34e6b704fe68 1053 /**
Kojto 108:34e6b704fe68 1054 * @brief Enable the SDRAM device interrupt.
Kojto 108:34e6b704fe68 1055 * @param __INSTANCE__: FMC_SDRAM instance
Kojto 108:34e6b704fe68 1056 * @param __INTERRUPT__: FMC_SDRAM interrupt
Kojto 108:34e6b704fe68 1057 * This parameter can be any combination of the following values:
Kojto 108:34e6b704fe68 1058 * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
Kojto 108:34e6b704fe68 1059 * @retval None
Kojto 108:34e6b704fe68 1060 */
Kojto 108:34e6b704fe68 1061 #define __FMC_SDRAM_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR |= (__INTERRUPT__))
Kojto 108:34e6b704fe68 1062
Kojto 108:34e6b704fe68 1063 /**
Kojto 108:34e6b704fe68 1064 * @brief Disable the SDRAM device interrupt.
Kojto 108:34e6b704fe68 1065 * @param __INSTANCE__: FMC_SDRAM instance
Kojto 108:34e6b704fe68 1066 * @param __INTERRUPT__: FMC_SDRAM interrupt
Kojto 108:34e6b704fe68 1067 * This parameter can be any combination of the following values:
Kojto 108:34e6b704fe68 1068 * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
Kojto 108:34e6b704fe68 1069 * @retval None
Kojto 108:34e6b704fe68 1070 */
Kojto 108:34e6b704fe68 1071 #define __FMC_SDRAM_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR &= ~(__INTERRUPT__))
Kojto 108:34e6b704fe68 1072
Kojto 108:34e6b704fe68 1073 /**
Kojto 108:34e6b704fe68 1074 * @brief Get flag status of the SDRAM device.
Kojto 108:34e6b704fe68 1075 * @param __INSTANCE__: FMC_SDRAM instance
Kojto 108:34e6b704fe68 1076 * @param __FLAG__: FMC_SDRAM flag
Kojto 108:34e6b704fe68 1077 * This parameter can be any combination of the following values:
Kojto 108:34e6b704fe68 1078 * @arg FMC_SDRAM_FLAG_REFRESH_IT: Interrupt refresh error.
Kojto 108:34e6b704fe68 1079 * @arg FMC_SDRAM_FLAG_BUSY: SDRAM busy flag.
Kojto 108:34e6b704fe68 1080 * @arg FMC_SDRAM_FLAG_REFRESH_ERROR: Refresh error flag.
Kojto 108:34e6b704fe68 1081 * @retval The state of FLAG (SET or RESET).
Kojto 108:34e6b704fe68 1082 */
Kojto 108:34e6b704fe68 1083 #define __FMC_SDRAM_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SDSR &(__FLAG__)) == (__FLAG__))
Kojto 108:34e6b704fe68 1084
Kojto 108:34e6b704fe68 1085 /**
Kojto 108:34e6b704fe68 1086 * @brief Clear flag status of the SDRAM device.
Kojto 108:34e6b704fe68 1087 * @param __INSTANCE__: FMC_SDRAM instance
Kojto 108:34e6b704fe68 1088 * @param __FLAG__: FMC_SDRAM flag
Kojto 108:34e6b704fe68 1089 * This parameter can be any combination of the following values:
Kojto 108:34e6b704fe68 1090 * @arg FMC_SDRAM_FLAG_REFRESH_ERROR
Kojto 108:34e6b704fe68 1091 * @retval None
Kojto 108:34e6b704fe68 1092 */
Kojto 108:34e6b704fe68 1093 #define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SDRTR |= (__FLAG__))
Kojto 108:34e6b704fe68 1094 /**
Kojto 108:34e6b704fe68 1095 * @}
Kojto 108:34e6b704fe68 1096 */
Kojto 108:34e6b704fe68 1097
Kojto 108:34e6b704fe68 1098 /** @defgroup FSMC_LL_Assert_Macros FSMC Assert Macros
Kojto 108:34e6b704fe68 1099 * @{
Kojto 108:34e6b704fe68 1100 */
Kojto 108:34e6b704fe68 1101 #define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_NORSRAM_BANK1) || \
Kojto 108:34e6b704fe68 1102 ((BANK) == FMC_NORSRAM_BANK2) || \
Kojto 108:34e6b704fe68 1103 ((BANK) == FMC_NORSRAM_BANK3) || \
Kojto 108:34e6b704fe68 1104 ((BANK) == FMC_NORSRAM_BANK4))
Kojto 108:34e6b704fe68 1105
Kojto 108:34e6b704fe68 1106 #define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \
Kojto 108:34e6b704fe68 1107 ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE))
Kojto 108:34e6b704fe68 1108
Kojto 108:34e6b704fe68 1109 #define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \
Kojto 108:34e6b704fe68 1110 ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \
Kojto 108:34e6b704fe68 1111 ((__MEMORY__) == FMC_MEMORY_TYPE_NOR))
Kojto 108:34e6b704fe68 1112
Kojto 108:34e6b704fe68 1113 #define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \
Kojto 108:34e6b704fe68 1114 ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \
Kojto 108:34e6b704fe68 1115 ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
Kojto 108:34e6b704fe68 1116
Kojto 108:34e6b704fe68 1117 #define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \
Kojto 108:34e6b704fe68 1118 ((__MODE__) == FMC_ACCESS_MODE_B) || \
Kojto 108:34e6b704fe68 1119 ((__MODE__) == FMC_ACCESS_MODE_C) || \
Kojto 108:34e6b704fe68 1120 ((__MODE__) == FMC_ACCESS_MODE_D))
Kojto 108:34e6b704fe68 1121
Kojto 108:34e6b704fe68 1122 #define IS_FMC_NAND_BANK(BANK) (((BANK) == FMC_NAND_BANK2) || \
Kojto 108:34e6b704fe68 1123 ((BANK) == FMC_NAND_BANK3))
Kojto 108:34e6b704fe68 1124
Kojto 108:34e6b704fe68 1125 #define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
Kojto 108:34e6b704fe68 1126 ((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_ENABLE))
Kojto 108:34e6b704fe68 1127
Kojto 108:34e6b704fe68 1128 #define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
Kojto 108:34e6b704fe68 1129 ((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_16))
Kojto 108:34e6b704fe68 1130
Kojto 108:34e6b704fe68 1131 #define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_NAND_ECC_DISABLE) || \
Kojto 108:34e6b704fe68 1132 ((STATE) == FMC_NAND_ECC_ENABLE))
Kojto 108:34e6b704fe68 1133
Kojto 108:34e6b704fe68 1134 #define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
Kojto 108:34e6b704fe68 1135 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
Kojto 108:34e6b704fe68 1136 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
Kojto 108:34e6b704fe68 1137 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
Kojto 108:34e6b704fe68 1138 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
Kojto 108:34e6b704fe68 1139 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
Kojto 108:34e6b704fe68 1140
Kojto 108:34e6b704fe68 1141 #define IS_FMC_TCLR_TIME(TIME) ((TIME) <= 255)
Kojto 108:34e6b704fe68 1142
Kojto 108:34e6b704fe68 1143 #define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255)
Kojto 108:34e6b704fe68 1144
Kojto 108:34e6b704fe68 1145 #define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 255)
Kojto 108:34e6b704fe68 1146
Kojto 108:34e6b704fe68 1147 #define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 255)
Kojto 108:34e6b704fe68 1148
Kojto 108:34e6b704fe68 1149 #define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 255)
Kojto 108:34e6b704fe68 1150
Kojto 108:34e6b704fe68 1151 #define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 255)
Kojto 108:34e6b704fe68 1152
Kojto 108:34e6b704fe68 1153 #define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE)
Kojto 108:34e6b704fe68 1154
Kojto 108:34e6b704fe68 1155 #define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE)
Kojto 108:34e6b704fe68 1156
Kojto 108:34e6b704fe68 1157 #define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE)
Kojto 108:34e6b704fe68 1158
Kojto 108:34e6b704fe68 1159 #define IS_FMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_PCCARD_DEVICE)
Kojto 108:34e6b704fe68 1160
Kojto 108:34e6b704fe68 1161 #define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \
Kojto 108:34e6b704fe68 1162 ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE))
Kojto 108:34e6b704fe68 1163
Kojto 108:34e6b704fe68 1164 #define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \
Kojto 108:34e6b704fe68 1165 ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
Kojto 108:34e6b704fe68 1166
Kojto 108:34e6b704fe68 1167 #if !defined (STM32F446xx)
Kojto 108:34e6b704fe68 1168 #define IS_FMC_WRAP_MODE(__MODE__) (((__MODE__) == FMC_WRAP_MODE_DISABLE) || \
Kojto 108:34e6b704fe68 1169 ((__MODE__) == FMC_WRAP_MODE_ENABLE))
Kojto 108:34e6b704fe68 1170 #endif /* !defined (STM32F446xx) */
Kojto 108:34e6b704fe68 1171
Kojto 108:34e6b704fe68 1172 #define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \
Kojto 108:34e6b704fe68 1173 ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS))
Kojto 108:34e6b704fe68 1174
Kojto 108:34e6b704fe68 1175 #define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \
Kojto 108:34e6b704fe68 1176 ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE))
Kojto 108:34e6b704fe68 1177
Kojto 108:34e6b704fe68 1178 #define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \
Kojto 108:34e6b704fe68 1179 ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE))
Kojto 108:34e6b704fe68 1180
Kojto 108:34e6b704fe68 1181 #define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \
Kojto 108:34e6b704fe68 1182 ((__MODE__) == FMC_EXTENDED_MODE_ENABLE))
Kojto 108:34e6b704fe68 1183
Kojto 108:34e6b704fe68 1184 #define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \
Kojto 108:34e6b704fe68 1185 ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
Kojto 108:34e6b704fe68 1186
Kojto 108:34e6b704fe68 1187 #define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \
Kojto 108:34e6b704fe68 1188 ((__BURST__) == FMC_WRITE_BURST_ENABLE))
Kojto 108:34e6b704fe68 1189
Kojto 108:34e6b704fe68 1190 #define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
Kojto 108:34e6b704fe68 1191 ((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
Kojto 108:34e6b704fe68 1192
Kojto 108:34e6b704fe68 1193 #define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15)
Kojto 108:34e6b704fe68 1194
Kojto 108:34e6b704fe68 1195 #define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15))
Kojto 108:34e6b704fe68 1196
Kojto 108:34e6b704fe68 1197 #define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255))
Kojto 108:34e6b704fe68 1198
Kojto 108:34e6b704fe68 1199 #define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15)
Kojto 108:34e6b704fe68 1200
Kojto 108:34e6b704fe68 1201 #define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17))
Kojto 108:34e6b704fe68 1202
Kojto 108:34e6b704fe68 1203 #define IS_FMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16))
Kojto 108:34e6b704fe68 1204
Kojto 108:34e6b704fe68 1205 #define IS_FMC_SDRAM_BANK(BANK) (((BANK) == FMC_SDRAM_BANK1) || \
Kojto 108:34e6b704fe68 1206 ((BANK) == FMC_SDRAM_BANK2))
Kojto 108:34e6b704fe68 1207
Kojto 108:34e6b704fe68 1208 #define IS_FMC_COLUMNBITS_NUMBER(COLUMN) (((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_8) || \
Kojto 108:34e6b704fe68 1209 ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_9) || \
Kojto 108:34e6b704fe68 1210 ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_10) || \
Kojto 108:34e6b704fe68 1211 ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_11))
Kojto 108:34e6b704fe68 1212
Kojto 108:34e6b704fe68 1213 #define IS_FMC_ROWBITS_NUMBER(ROW) (((ROW) == FMC_SDRAM_ROW_BITS_NUM_11) || \
Kojto 108:34e6b704fe68 1214 ((ROW) == FMC_SDRAM_ROW_BITS_NUM_12) || \
Kojto 108:34e6b704fe68 1215 ((ROW) == FMC_SDRAM_ROW_BITS_NUM_13))
Kojto 108:34e6b704fe68 1216
Kojto 108:34e6b704fe68 1217 #define IS_FMC_SDMEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_8) || \
Kojto 108:34e6b704fe68 1218 ((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_16) || \
Kojto 108:34e6b704fe68 1219 ((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_32))
Kojto 108:34e6b704fe68 1220
Kojto 108:34e6b704fe68 1221 #define IS_FMC_INTERNALBANK_NUMBER(NUMBER) (((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_2) || \
Kojto 108:34e6b704fe68 1222 ((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_4))
Kojto 108:34e6b704fe68 1223
Kojto 108:34e6b704fe68 1224
Kojto 108:34e6b704fe68 1225 #define IS_FMC_CAS_LATENCY(LATENCY) (((LATENCY) == FMC_SDRAM_CAS_LATENCY_1) || \
Kojto 108:34e6b704fe68 1226 ((LATENCY) == FMC_SDRAM_CAS_LATENCY_2) || \
Kojto 108:34e6b704fe68 1227 ((LATENCY) == FMC_SDRAM_CAS_LATENCY_3))
Kojto 108:34e6b704fe68 1228
Kojto 108:34e6b704fe68 1229 #define IS_FMC_SDCLOCK_PERIOD(PERIOD) (((PERIOD) == FMC_SDRAM_CLOCK_DISABLE) || \
Kojto 108:34e6b704fe68 1230 ((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_2) || \
Kojto 108:34e6b704fe68 1231 ((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_3))
Kojto 108:34e6b704fe68 1232
Kojto 108:34e6b704fe68 1233 #define IS_FMC_READ_BURST(RBURST) (((RBURST) == FMC_SDRAM_RBURST_DISABLE) || \
Kojto 108:34e6b704fe68 1234 ((RBURST) == FMC_SDRAM_RBURST_ENABLE))
Kojto 108:34e6b704fe68 1235
Kojto 108:34e6b704fe68 1236
Kojto 108:34e6b704fe68 1237 #define IS_FMC_READPIPE_DELAY(DELAY) (((DELAY) == FMC_SDRAM_RPIPE_DELAY_0) || \
Kojto 108:34e6b704fe68 1238 ((DELAY) == FMC_SDRAM_RPIPE_DELAY_1) || \
Kojto 108:34e6b704fe68 1239 ((DELAY) == FMC_SDRAM_RPIPE_DELAY_2))
Kojto 108:34e6b704fe68 1240
Kojto 108:34e6b704fe68 1241 #define IS_FMC_LOADTOACTIVE_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
Kojto 108:34e6b704fe68 1242
Kojto 108:34e6b704fe68 1243 #define IS_FMC_EXITSELFREFRESH_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
Kojto 108:34e6b704fe68 1244
Kojto 108:34e6b704fe68 1245 #define IS_FMC_SELFREFRESH_TIME(TIME) (((TIME) > 0) && ((TIME) <= 16))
Kojto 108:34e6b704fe68 1246
Kojto 108:34e6b704fe68 1247 #define IS_FMC_ROWCYCLE_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
Kojto 108:34e6b704fe68 1248
Kojto 108:34e6b704fe68 1249 #define IS_FMC_WRITE_RECOVERY_TIME(TIME) (((TIME) > 0) && ((TIME) <= 16))
Kojto 108:34e6b704fe68 1250
Kojto 108:34e6b704fe68 1251 #define IS_FMC_RP_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
Kojto 108:34e6b704fe68 1252
Kojto 108:34e6b704fe68 1253 #define IS_FMC_RCD_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
Kojto 108:34e6b704fe68 1254
Kojto 108:34e6b704fe68 1255 #define IS_FMC_COMMAND_MODE(COMMAND) (((COMMAND) == FMC_SDRAM_CMD_NORMAL_MODE) || \
Kojto 108:34e6b704fe68 1256 ((COMMAND) == FMC_SDRAM_CMD_CLK_ENABLE) || \
Kojto 108:34e6b704fe68 1257 ((COMMAND) == FMC_SDRAM_CMD_PALL) || \
Kojto 108:34e6b704fe68 1258 ((COMMAND) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) || \
Kojto 108:34e6b704fe68 1259 ((COMMAND) == FMC_SDRAM_CMD_LOAD_MODE) || \
Kojto 108:34e6b704fe68 1260 ((COMMAND) == FMC_SDRAM_CMD_SELFREFRESH_MODE) || \
Kojto 108:34e6b704fe68 1261 ((COMMAND) == FMC_SDRAM_CMD_POWERDOWN_MODE))
Kojto 108:34e6b704fe68 1262
Kojto 108:34e6b704fe68 1263 #define IS_FMC_COMMAND_TARGET(TARGET) (((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1) || \
Kojto 108:34e6b704fe68 1264 ((TARGET) == FMC_SDRAM_CMD_TARGET_BANK2) || \
Kojto 108:34e6b704fe68 1265 ((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1_2))
Kojto 108:34e6b704fe68 1266
Kojto 108:34e6b704fe68 1267 #define IS_FMC_AUTOREFRESH_NUMBER(NUMBER) (((NUMBER) > 0) && ((NUMBER) <= 16))
Kojto 108:34e6b704fe68 1268
Kojto 108:34e6b704fe68 1269 #define IS_FMC_MODE_REGISTER(CONTENT) ((CONTENT) <= 8191)
Kojto 108:34e6b704fe68 1270
Kojto 108:34e6b704fe68 1271 #define IS_FMC_REFRESH_RATE(RATE) ((RATE) <= 8191)
Kojto 108:34e6b704fe68 1272
Kojto 108:34e6b704fe68 1273 #define IS_FMC_SDRAM_DEVICE(INSTANCE) ((INSTANCE) == FMC_SDRAM_DEVICE)
Kojto 108:34e6b704fe68 1274
Kojto 108:34e6b704fe68 1275 #define IS_FMC_WRITE_PROTECTION(WRITE) (((WRITE) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) || \
Kojto 108:34e6b704fe68 1276 ((WRITE) == FMC_SDRAM_WRITE_PROTECTION_ENABLE))
Kojto 108:34e6b704fe68 1277
Kojto 108:34e6b704fe68 1278 #if defined (STM32F446xx)
Kojto 108:34e6b704fe68 1279 #define IS_FMC_PAGESIZE(SIZE) (((SIZE) == FMC_PAGE_SIZE_NONE) || \
Kojto 108:34e6b704fe68 1280 ((SIZE) == FMC_PAGE_SIZE_128) || \
Kojto 108:34e6b704fe68 1281 ((SIZE) == FMC_PAGE_SIZE_256) || \
Kojto 108:34e6b704fe68 1282 ((SIZE) == FMC_PAGE_SIZE_1024))
Kojto 108:34e6b704fe68 1283
Kojto 108:34e6b704fe68 1284 #define IS_FMC_WRITE_FIFO(FIFO) (((FIFO) == FMC_WRITE_FIFO_DISABLE) || \
Kojto 108:34e6b704fe68 1285 ((FIFO) == FMC_WRITE_FIFO_ENABLE))
Kojto 108:34e6b704fe68 1286 #endif /* defined (STM32F446xx) */
Kojto 108:34e6b704fe68 1287
Kojto 108:34e6b704fe68 1288 /**
Kojto 108:34e6b704fe68 1289 * @}
Kojto 108:34e6b704fe68 1290 */
Kojto 108:34e6b704fe68 1291
Kojto 108:34e6b704fe68 1292 /**
Kojto 108:34e6b704fe68 1293 * @}
Kojto 108:34e6b704fe68 1294 */
Kojto 108:34e6b704fe68 1295
Kojto 108:34e6b704fe68 1296 /* Private functions ---------------------------------------------------------*/
Kojto 108:34e6b704fe68 1297 /** @defgroup FMC_LL_Private_Functions FMC LL Private Functions
Kojto 108:34e6b704fe68 1298 * @{
Kojto 108:34e6b704fe68 1299 */
Kojto 108:34e6b704fe68 1300
Kojto 108:34e6b704fe68 1301 /** @defgroup FMC_LL_NORSRAM NOR SRAM
Kojto 108:34e6b704fe68 1302 * @{
Kojto 108:34e6b704fe68 1303 */
Kojto 108:34e6b704fe68 1304 /** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
Kojto 108:34e6b704fe68 1305 * @{
Kojto 108:34e6b704fe68 1306 */
Kojto 108:34e6b704fe68 1307 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init);
Kojto 108:34e6b704fe68 1308 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
Kojto 108:34e6b704fe68 1309 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
Kojto 108:34e6b704fe68 1310 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
Kojto 108:34e6b704fe68 1311 /**
Kojto 108:34e6b704fe68 1312 * @}
Kojto 108:34e6b704fe68 1313 */
Kojto 108:34e6b704fe68 1314
Kojto 108:34e6b704fe68 1315 /** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions
Kojto 108:34e6b704fe68 1316 * @{
Kojto 108:34e6b704fe68 1317 */
Kojto 108:34e6b704fe68 1318 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
Kojto 108:34e6b704fe68 1319 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
Kojto 108:34e6b704fe68 1320 /**
Kojto 108:34e6b704fe68 1321 * @}
Kojto 108:34e6b704fe68 1322 */
Kojto 108:34e6b704fe68 1323 /**
Kojto 108:34e6b704fe68 1324 * @}
Kojto 108:34e6b704fe68 1325 */
Kojto 108:34e6b704fe68 1326
Kojto 108:34e6b704fe68 1327 /** @defgroup FMC_LL_NAND NAND
Kojto 108:34e6b704fe68 1328 * @{
Kojto 108:34e6b704fe68 1329 */
Kojto 108:34e6b704fe68 1330 /** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
Kojto 108:34e6b704fe68 1331 * @{
Kojto 108:34e6b704fe68 1332 */
Kojto 108:34e6b704fe68 1333 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init);
Kojto 108:34e6b704fe68 1334 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
Kojto 108:34e6b704fe68 1335 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
Kojto 108:34e6b704fe68 1336 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
Kojto 108:34e6b704fe68 1337 /**
Kojto 108:34e6b704fe68 1338 * @}
Kojto 108:34e6b704fe68 1339 */
Kojto 108:34e6b704fe68 1340
Kojto 108:34e6b704fe68 1341 /** @defgroup FMC_LL_NAND_Private_Functions_Group2 NAND Control functions
Kojto 108:34e6b704fe68 1342 * @{
Kojto 108:34e6b704fe68 1343 */
Kojto 108:34e6b704fe68 1344 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
Kojto 108:34e6b704fe68 1345 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
Kojto 108:34e6b704fe68 1346 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);
Kojto 108:34e6b704fe68 1347
Kojto 108:34e6b704fe68 1348 /**
Kojto 108:34e6b704fe68 1349 * @}
Kojto 108:34e6b704fe68 1350 */
Kojto 108:34e6b704fe68 1351 /**
Kojto 108:34e6b704fe68 1352 * @}
Kojto 108:34e6b704fe68 1353 */
Kojto 108:34e6b704fe68 1354 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
Kojto 108:34e6b704fe68 1355 /** @defgroup FMC_LL_PCCARD PCCARD
Kojto 108:34e6b704fe68 1356 * @{
Kojto 108:34e6b704fe68 1357 */
Kojto 108:34e6b704fe68 1358 /** @defgroup FMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions
Kojto 108:34e6b704fe68 1359 * @{
Kojto 108:34e6b704fe68 1360 */
Kojto 108:34e6b704fe68 1361 HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init);
Kojto 108:34e6b704fe68 1362 HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
Kojto 108:34e6b704fe68 1363 HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
Kojto 108:34e6b704fe68 1364 HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
Kojto 108:34e6b704fe68 1365 HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device);
Kojto 108:34e6b704fe68 1366 /**
Kojto 108:34e6b704fe68 1367 * @}
Kojto 108:34e6b704fe68 1368 */
Kojto 108:34e6b704fe68 1369 /**
Kojto 108:34e6b704fe68 1370 * @}
Kojto 108:34e6b704fe68 1371 */
Kojto 108:34e6b704fe68 1372 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
Kojto 108:34e6b704fe68 1373
Kojto 108:34e6b704fe68 1374 /** @defgroup FMC_LL_SDRAM SDRAM
Kojto 108:34e6b704fe68 1375 * @{
Kojto 108:34e6b704fe68 1376 */
Kojto 108:34e6b704fe68 1377 /** @defgroup FMC_LL_SDRAM_Private_Functions_Group1 SDRAM Initialization/de-initialization functions
Kojto 108:34e6b704fe68 1378 * @{
Kojto 108:34e6b704fe68 1379 */
Kojto 108:34e6b704fe68 1380 HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init);
Kojto 108:34e6b704fe68 1381 HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank);
Kojto 108:34e6b704fe68 1382 HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
Kojto 108:34e6b704fe68 1383 /**
Kojto 108:34e6b704fe68 1384 * @}
Kojto 108:34e6b704fe68 1385 */
Kojto 108:34e6b704fe68 1386
Kojto 108:34e6b704fe68 1387 /** @defgroup FMC_LL_SDRAM_Private_Functions_Group2 SDRAM Control functions
Kojto 108:34e6b704fe68 1388 * @{
Kojto 108:34e6b704fe68 1389 */
Kojto 108:34e6b704fe68 1390 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
Kojto 108:34e6b704fe68 1391 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
Kojto 108:34e6b704fe68 1392 HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout);
Kojto 108:34e6b704fe68 1393 HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate);
Kojto 108:34e6b704fe68 1394 HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber);
Kojto 108:34e6b704fe68 1395 uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
Kojto 108:34e6b704fe68 1396 /**
Kojto 108:34e6b704fe68 1397 * @}
Kojto 108:34e6b704fe68 1398 */
Kojto 108:34e6b704fe68 1399 /**
Kojto 108:34e6b704fe68 1400 * @}
Kojto 108:34e6b704fe68 1401 */
Kojto 108:34e6b704fe68 1402
Kojto 108:34e6b704fe68 1403 /**
Kojto 108:34e6b704fe68 1404 * @}
Kojto 108:34e6b704fe68 1405 */
Kojto 108:34e6b704fe68 1406
Kojto 108:34e6b704fe68 1407 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */
Kojto 108:34e6b704fe68 1408 /**
Kojto 108:34e6b704fe68 1409 * @}
Kojto 108:34e6b704fe68 1410 */
Kojto 108:34e6b704fe68 1411
Kojto 108:34e6b704fe68 1412 /**
Kojto 108:34e6b704fe68 1413 * @}
Kojto 108:34e6b704fe68 1414 */
Kojto 108:34e6b704fe68 1415 #ifdef __cplusplus
Kojto 108:34e6b704fe68 1416 }
Kojto 108:34e6b704fe68 1417 #endif
Kojto 108:34e6b704fe68 1418
Kojto 108:34e6b704fe68 1419 #endif /* __STM32F4xx_LL_FMC_H */
Kojto 108:34e6b704fe68 1420
Kojto 108:34e6b704fe68 1421 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/