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Fork of the official mbed C/C SDK provides the software platform and libraries to build your applications for RenBED.

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Revision 33:5364839841bd, committed 2012-01-10

Comitter:: emilmont
Date:: Tue Jan 10 12:00:50 2012 +0000
Parent:: 32:3b05dd009342
Child:: 34:7495d544864f
Commit message:: [10 January 2012] CAN::attach template. CMSIS updates.

Changed in this revision

CAN.h	Show annotated file Show diff for this revision Revisions of this file
LPC11U24/ARM/capi.ar	Show annotated file Show diff for this revision Revisions of this file
LPC11U24/ARM/cmsis_nvic.o	Show annotated file Show diff for this revision Revisions of this file
LPC11U24/ARM/core_cm0.o	Show annotated file Show diff for this revision Revisions of this file
LPC11U24/ARM/core_cmFunc.h	Show annotated file Show diff for this revision Revisions of this file
LPC11U24/ARM/core_cmInstr.h	Show annotated file Show diff for this revision Revisions of this file
LPC11U24/ARM/mbed.ar	Show annotated file Show diff for this revision Revisions of this file
LPC11U24/ARM/sys.o	Show annotated file Show diff for this revision Revisions of this file
LPC11U24/ARM/system_LPC11Uxx.o	Show annotated file Show diff for this revision Revisions of this file
LPC11U24/GCC_ARM/core_cmFunc.h	Show annotated file Show diff for this revision Revisions of this file
LPC11U24/GCC_ARM/core_cmInstr.h	Show annotated file Show diff for this revision Revisions of this file
LPC11U24/GCC_ARM/libcapi.a	Show annotated file Show diff for this revision Revisions of this file
LPC11U24/GCC_ARM/libmbed.a	Show annotated file Show diff for this revision Revisions of this file
LPC11U24/GCC_CR/core_cmFunc.h	Show annotated file Show diff for this revision Revisions of this file
LPC11U24/GCC_CR/core_cmInstr.h	Show annotated file Show diff for this revision Revisions of this file
LPC11U24/GCC_CR/libcapi.a	Show annotated file Show diff for this revision Revisions of this file
LPC11U24/GCC_CR/libmbed.a	Show annotated file Show diff for this revision Revisions of this file
LPC11U24/GCC_CS/core_cmFunc.h	Show annotated file Show diff for this revision Revisions of this file
LPC11U24/GCC_CS/core_cmInstr.h	Show annotated file Show diff for this revision Revisions of this file
LPC11U24/GCC_CS/libcapi.a	Show annotated file Show diff for this revision Revisions of this file
LPC11U24/GCC_CS/libmbed.a	Show annotated file Show diff for this revision Revisions of this file
LPC11U24/uARM/capi.ar	Show annotated file Show diff for this revision Revisions of this file
LPC11U24/uARM/cmsis_nvic.o	Show annotated file Show diff for this revision Revisions of this file
LPC11U24/uARM/core_cm0.o	Show annotated file Show diff for this revision Revisions of this file
LPC11U24/uARM/core_cmFunc.h	Show annotated file Show diff for this revision Revisions of this file
LPC11U24/uARM/core_cmInstr.h	Show annotated file Show diff for this revision Revisions of this file
LPC11U24/uARM/mbed.ar	Show annotated file Show diff for this revision Revisions of this file
LPC11U24/uARM/sys.o	Show annotated file Show diff for this revision Revisions of this file
LPC11U24/uARM/system_LPC11Uxx.o	Show annotated file Show diff for this revision Revisions of this file
LPC1768/ARM/capi.ar	Show annotated file Show diff for this revision Revisions of this file
LPC1768/ARM/cmsis_nvic.o	Show annotated file Show diff for this revision Revisions of this file
LPC1768/ARM/core_cm3.h	Show annotated file Show diff for this revision Revisions of this file
LPC1768/ARM/core_cm3.o	Show annotated file Show diff for this revision Revisions of this file
LPC1768/ARM/core_cmFunc.h	Show annotated file Show diff for this revision Revisions of this file
LPC1768/ARM/core_cmInstr.h	Show annotated file Show diff for this revision Revisions of this file
LPC1768/ARM/mbed.ar	Show annotated file Show diff for this revision Revisions of this file
LPC1768/ARM/sys.o	Show annotated file Show diff for this revision Revisions of this file
LPC1768/ARM/system_LPC17xx.o	Show annotated file Show diff for this revision Revisions of this file
LPC1768/GCC_ARM/core_cm3.h	Show annotated file Show diff for this revision Revisions of this file
LPC1768/GCC_ARM/core_cmFunc.h	Show annotated file Show diff for this revision Revisions of this file
LPC1768/GCC_ARM/core_cmInstr.h	Show annotated file Show diff for this revision Revisions of this file
LPC1768/GCC_ARM/libcapi.a	Show annotated file Show diff for this revision Revisions of this file
LPC1768/GCC_ARM/libmbed.a	Show annotated file Show diff for this revision Revisions of this file
LPC1768/GCC_CR/core_cm3.h	Show annotated file Show diff for this revision Revisions of this file
LPC1768/GCC_CR/core_cmFunc.h	Show annotated file Show diff for this revision Revisions of this file
LPC1768/GCC_CR/core_cmInstr.h	Show annotated file Show diff for this revision Revisions of this file
LPC1768/GCC_CR/libcapi.a	Show annotated file Show diff for this revision Revisions of this file
LPC1768/GCC_CR/libmbed.a	Show annotated file Show diff for this revision Revisions of this file
LPC1768/GCC_CS/core_cm3.h	Show annotated file Show diff for this revision Revisions of this file
LPC1768/GCC_CS/core_cmFunc.h	Show annotated file Show diff for this revision Revisions of this file
LPC1768/GCC_CS/core_cmInstr.h	Show annotated file Show diff for this revision Revisions of this file
LPC1768/GCC_CS/libcapi.a	Show annotated file Show diff for this revision Revisions of this file
LPC1768/GCC_CS/libmbed.a	Show annotated file Show diff for this revision Revisions of this file
LPC1768/uARM/capi.ar	Show annotated file Show diff for this revision Revisions of this file
LPC1768/uARM/cmsis_nvic.o	Show annotated file Show diff for this revision Revisions of this file
LPC1768/uARM/core_cm3.h	Show annotated file Show diff for this revision Revisions of this file
LPC1768/uARM/core_cm3.o	Show annotated file Show diff for this revision Revisions of this file
LPC1768/uARM/core_cmFunc.h	Show annotated file Show diff for this revision Revisions of this file
LPC1768/uARM/core_cmInstr.h	Show annotated file Show diff for this revision Revisions of this file
LPC1768/uARM/mbed.ar	Show annotated file Show diff for this revision Revisions of this file
LPC1768/uARM/sys.o	Show annotated file Show diff for this revision Revisions of this file
LPC1768/uARM/system_LPC17xx.o	Show annotated file Show diff for this revision Revisions of this file
LPC2368/ARM/capi.ar	Show annotated file Show diff for this revision Revisions of this file
LPC2368/ARM/mbed.ar	Show annotated file Show diff for this revision Revisions of this file
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LPC2368/GCC_CR/libcapi.a	Show annotated file Show diff for this revision Revisions of this file
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--- a/CAN.h	Fri Jan 06 16:40:24 2012 +0000
+++ b/CAN.h	Tue Jan 10 12:00:50 2012 +0000
@@ -227,7 +227,14 @@
     *  mptr - pointer to the member function to be called
     */
    template<typename T>
-   void attach(T* tptr, void (T::*mptr)(void));
+   void attach(T* tptr, void (T::*mptr)(void)) {
+        if((mptr != NULL) && (tptr != NULL)) {
+            _rxirq.attach(tptr, mptr);
+            setup_interrupt();
+        } else {
+            remove_interrupt();
+        }
+    }
     
 private:

Binary file LPC11U24/ARM/capi.ar has changed

Binary file LPC11U24/ARM/cmsis_nvic.o has changed

Binary file LPC11U24/ARM/core_cm0.o has changed

--- a/LPC11U24/ARM/core_cmFunc.h	Fri Jan 06 16:40:24 2012 +0000
+++ b/LPC11U24/ARM/core_cmFunc.h	Tue Jan 10 12:00:50 2012 +0000
@@ -1,11 +1,11 @@
 /**************************************************************************//**
  * @file     core_cmFunc.h
  * @brief    CMSIS Cortex-M Core Function Access Header File
- * @version  V2.01
- * @date     06. December 2010
+ * @version  V3.00
+ * @date     09. December 2011
  *
  * @note
- * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
  *
  * @par
  * ARM Limited (ARM) is supplying this software for use with Cortex-M 
@@ -21,8 +21,9 @@
  *
  ******************************************************************************/
 
-#ifndef __CORE_CMFUNC_H__
-#define __CORE_CMFUNC_H__
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
 
 /* ###########################  Core Function Access  ########################### */
 /** \ingroup  CMSIS_Core_FunctionInterface   
@@ -30,9 +31,13 @@
   @{
  */
 
-#if defined ( __CC_ARM   ) /*------------------ RealView Compiler ----------------*/
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
 /* ARM armcc specific functions */
 
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
 /* intrinsic void __enable_irq();     */
 /* intrinsic void __disable_irq();    */
 
@@ -42,15 +47,11 @@
 
     \return               Control Register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_CONTROL(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_CONTROL(void)
 {
   register uint32_t __regControl         __ASM("control");
   return(__regControl);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Set Control Register
@@ -59,32 +60,24 @@
 
     \param [in]    control  Control Register value to set
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          void __set_CONTROL(uint32_t control);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE void __set_CONTROL(uint32_t control)
 {
   register uint32_t __regControl         __ASM("control");
   __regControl = control;
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
-/** \brief  Get ISPR Register
-
-    This function returns the content of the ISPR Register.
+/** \brief  Get IPSR Register
 
-    \return               ISPR Register value
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_IPSR(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_IPSR(void)
 {
   register uint32_t __regIPSR          __ASM("ipsr");
   return(__regIPSR);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Get APSR Register
@@ -93,15 +86,11 @@
 
     \return               APSR Register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_APSR(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_APSR(void)
 {
   register uint32_t __regAPSR          __ASM("apsr");
   return(__regAPSR);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Get xPSR Register
@@ -110,15 +99,11 @@
 
     \return               xPSR Register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_xPSR(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_xPSR(void)
 {
   register uint32_t __regXPSR          __ASM("xpsr");
   return(__regXPSR);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Get Process Stack Pointer
@@ -127,15 +112,11 @@
 
     \return               PSP Register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_PSP(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_PSP(void)
 {
   register uint32_t __regProcessStackPointer  __ASM("psp");
   return(__regProcessStackPointer);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Set Process Stack Pointer
@@ -144,15 +125,11 @@
 
     \param [in]    topOfProcStack  Process Stack Pointer value to set
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          void __set_PSP(uint32_t topOfProcStack);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE void __set_PSP(uint32_t topOfProcStack)
 {
   register uint32_t __regProcessStackPointer  __ASM("psp");
   __regProcessStackPointer = topOfProcStack;
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Get Main Stack Pointer
@@ -161,15 +138,11 @@
 
     \return               MSP Register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_MSP(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_MSP(void)
 {
   register uint32_t __regMainStackPointer     __ASM("msp");
   return(__regMainStackPointer);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Set Main Stack Pointer
@@ -178,15 +151,11 @@
 
     \param [in]    topOfMainStack  Main Stack Pointer value to set
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          void __set_MSP(uint32_t topOfMainStack);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE void __set_MSP(uint32_t topOfMainStack)
 {
   register uint32_t __regMainStackPointer     __ASM("msp");
   __regMainStackPointer = topOfMainStack;
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Get Priority Mask
@@ -195,15 +164,11 @@
 
     \return               Priority Mask value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_PRIMASK(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_PRIMASK(void)
 {
   register uint32_t __regPriMask         __ASM("primask");
   return(__regPriMask);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Set Priority Mask
@@ -212,15 +177,11 @@
 
     \param [in]    priMask  Priority Mask
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          void __set_PRIMASK(uint32_t priMask);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE void __set_PRIMASK(uint32_t priMask)
 {
   register uint32_t __regPriMask         __ASM("primask");
   __regPriMask = (priMask);
 }
-#endif /*  __ARMCC_VERSION  */ 
  
 
 #if       (__CORTEX_M >= 0x03)
@@ -247,15 +208,11 @@
 
     \return               Base Priority register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_BASEPRI(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t  __get_BASEPRI(void)
 {
   register uint32_t __regBasePri         __ASM("basepri");
   return(__regBasePri);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Set Base Priority
@@ -264,15 +221,11 @@
 
     \param [in]    basePri  Base Priority value to set
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          void __set_BASEPRI(uint32_t basePri);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE void __set_BASEPRI(uint32_t basePri)
 {
   register uint32_t __regBasePri         __ASM("basepri");
   __regBasePri = (basePri & 0xff);
 }
-#endif /*  __ARMCC_VERSION  */ 
  
 
 /** \brief  Get Fault Mask
@@ -281,15 +234,11 @@
 
     \return               Fault Mask register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_FAULTMASK(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_FAULTMASK(void)
 {
   register uint32_t __regFaultMask       __ASM("faultmask");
   return(__regFaultMask);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Set Fault Mask
@@ -298,15 +247,11 @@
 
     \param [in]    faultMask  Fault Mask value to set
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          void __set_FAULTMASK(uint32_t faultMask);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE void __set_FAULTMASK(uint32_t faultMask)
 {
   register uint32_t __regFaultMask       __ASM("faultmask");
-  __regFaultMask = (faultMask & 1);
+  __regFaultMask = (faultMask & (uint32_t)1);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 #endif /* (__CORTEX_M >= 0x03) */
 
@@ -321,7 +266,7 @@
  */
 static __INLINE uint32_t __get_FPSCR(void)
 {
-#if (__FPU_PRESENT == 1)
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
   register uint32_t __regfpscr         __ASM("fpscr");
   return(__regfpscr);
 #else
@@ -338,7 +283,7 @@
  */
 static __INLINE void __set_FPSCR(uint32_t fpscr)
 {
-#if (__FPU_PRESENT == 1)
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
   register uint32_t __regfpscr         __ASM("fpscr");
   __regfpscr = (fpscr);
 #endif
@@ -347,192 +292,12 @@
 #endif /* (__CORTEX_M == 0x04) */
 
 
- #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
 /* IAR iccarm specific functions */
 
-#if defined (__ICCARM__)
-  #include <intrinsics.h>                     /* IAR Intrinsics   */
-#endif
-
-#pragma diag_suppress=Pe940
-
-/** \brief  Enable IRQ Interrupts
-
-  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
-  Can only be executed in Privileged modes.
- */
-#define __enable_irq                              __enable_interrupt
-
-
-/** \brief  Disable IRQ Interrupts
-
-  This function disables IRQ interrupts by setting the I-bit in the CPSR.
-  Can only be executed in Privileged modes.
- */
-#define __disable_irq                             __disable_interrupt
-
-
-/* intrinsic unsigned long __get_CONTROL( void ); (see intrinsic.h) */
-/* intrinsic void __set_CONTROL( unsigned long ); (see intrinsic.h) */
-
-
-/** \brief  Get ISPR Register
-
-    This function returns the content of the ISPR Register.
-
-    \return               ISPR Register value
- */
-static uint32_t __get_IPSR(void)
-{
-  __ASM("mrs r0, ipsr");
-}
-
-
-/** \brief  Get APSR Register
-
-    This function returns the content of the APSR Register.
-
-    \return               APSR Register value
- */
-static uint32_t __get_APSR(void)
-{
-  __ASM("mrs r0, apsr");
-}
-
-
-/** \brief  Get xPSR Register
-
-    This function returns the content of the xPSR Register.
-
-    \return               xPSR Register value
- */
-static uint32_t __get_xPSR(void)
-{
-  __ASM("mrs r0, psr");           // assembler does not know "xpsr"
-}
-
-
-/** \brief  Get Process Stack Pointer
-
-    This function returns the current value of the Process Stack Pointer (PSP).
-
-    \return               PSP Register value
- */
-static uint32_t __get_PSP(void)
-{
-  __ASM("mrs r0, psp");
-}
- 
-
-/** \brief  Set Process Stack Pointer
-
-    This function assigns the given value to the Process Stack Pointer (PSP).
-
-    \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-static void __set_PSP(uint32_t topOfProcStack)
-{
-  __ASM("msr psp, r0");
-}
-
-
-/** \brief  Get Main Stack Pointer
-
-    This function returns the current value of the Main Stack Pointer (MSP).
+#include <cmsis_iar.h>
 
-    \return               MSP Register value
- */
-static uint32_t __get_MSP(void)
-{
-  __ASM("mrs r0, msp");
-}
- 
-
-/** \brief  Set Main Stack Pointer
-
-    This function assigns the given value to the Main Stack Pointer (MSP).
-
-    \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-static void __set_MSP(uint32_t topOfMainStack)
-{
-  __ASM("msr msp, r0");
-}
- 
-
-/* intrinsic unsigned long __get_PRIMASK( void ); (see intrinsic.h) */
-/* intrinsic void __set_PRIMASK( unsigned long ); (see intrinsic.h) */
- 
-
-#if       (__CORTEX_M >= 0x03)
-
-/** \brief  Enable FIQ
-
-    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-static __INLINE void __enable_fault_irq(void)
-{
-  __ASM ("cpsie f");
-}
-
-
-/** \brief  Disable FIQ
-
-    This function disables FIQ interrupts by setting the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-static __INLINE void __disable_fault_irq(void)
-{
-  __ASM ("cpsid f");
-}
-
-
-/* intrinsic unsigned long __get_BASEPRI( void );   (see intrinsic.h) */
-/* intrinsic void __set_BASEPRI( unsigned long );   (see intrinsic.h) */
-/* intrinsic unsigned long __get_FAULTMASK( void ); (see intrinsic.h) */
-/* intrinsic void __set_FAULTMASK(unsigned long);   (see intrinsic.h) */
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-#if       (__CORTEX_M == 0x04)
-
-/** \brief  Get FPSCR
-
-    This function returns the current value of the Floating Point Status/Control register.
-
-    \return               Floating Point Status/Control register value
- */
-static uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1)
-  __ASM("vmrs r0, fpscr"); 
-#else
-  return(0);
-#endif
-}
-
-
-/** \brief  Set FPSCR
-
-    This function assigns the given value to the Floating Point Status/Control register.
-
-    \param [in]    fpscr  Floating Point Status/Control value to set
- */
-static void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1)
-  __ASM("vmsr fpscr, r0");
-#endif
-}
-
-#endif /* (__CORTEX_M == 0x04) */
-
-#pragma diag_default=Pe940
-
-
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
 /* GNU gcc specific functions */
 
 /** \brief  Enable IRQ Interrupts
@@ -584,11 +349,11 @@
 }
 
 
-/** \brief  Get ISPR Register
+/** \brief  Get IPSR Register
 
-    This function returns the content of the ISPR Register.
+    This function returns the content of the IPSR Register.
 
-    \return               ISPR Register value
+    \return               IPSR Register value
  */
 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void)
 {
@@ -800,10 +565,10 @@
  */
 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void)
 {
-#if (__FPU_PRESENT == 1)
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
   uint32_t result;
 
-  __ASM volatile ("MRS %0, fpscr" : "=r" (result) );
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
   return(result);
 #else
    return(0);
@@ -819,15 +584,15 @@
  */
 __attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr)
 {
-#if (__FPU_PRESENT == 1)
-  __ASM volatile ("MSR fpscr, %0" : : "r" (fpscr) );
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );
 #endif
 }
 
 #endif /* (__CORTEX_M == 0x04) */
 
 
-#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
 /* TASKING carm specific functions */
 
 /*
@@ -841,4 +606,4 @@
 /*@} end of CMSIS_Core_RegAccFunctions */
 
 
-#endif /* __CORE_CMFUNC_H__ */
+#endif /* __CORE_CMFUNC_H */

--- a/LPC11U24/ARM/core_cmInstr.h	Fri Jan 06 16:40:24 2012 +0000
+++ b/LPC11U24/ARM/core_cmInstr.h	Tue Jan 10 12:00:50 2012 +0000
@@ -1,11 +1,11 @@
 /**************************************************************************//**
  * @file     core_cmInstr.h
  * @brief    CMSIS Cortex-M Core Instruction Access Header File
- * @version  V2.01
- * @date     06. December 2010
+ * @version  V3.00
+ * @date     09. December 2011
  *
  * @note
- * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
  *
  * @par
  * ARM Limited (ARM) is supplying this software for use with Cortex-M 
@@ -21,8 +21,8 @@
  *
  ******************************************************************************/
 
-#ifndef __CORE_CMINSTR_H__
-#define __CORE_CMINSTR_H__
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
 
 
 /* ##########################  Core Instruction Access  ######################### */
@@ -31,9 +31,14 @@
   @{
 */
 
-#if defined ( __CC_ARM   ) /*------------------ RealView Compiler ----------------*/
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
 /* ARM armcc specific functions */
 
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
 /** \brief  No Operation
 
     No Operation does nothing. This instruction can be used for code alignment purposes.
@@ -106,15 +111,11 @@
     \param [in]    value  Value to reverse
     \return               Reversed value
  */
-#if (__ARMCC_VERSION < 400677)
-extern uint32_t __REV16(uint32_t value);
-#else  /* (__ARMCC_VERSION >= 400677)  */
-static __INLINE __ASM uint32_t __REV16(uint32_t value)
+static __attribute__((section(".rev16_text"))) __INLINE __ASM uint32_t __REV16(uint32_t value)
 {
   rev16 r0, r0
   bx lr
 }
-#endif /* __ARMCC_VERSION  */ 
 
 
 /** \brief  Reverse byte order in signed short value
@@ -124,15 +125,11 @@
     \param [in]    value  Value to reverse
     \return               Reversed value
  */
-#if (__ARMCC_VERSION < 400677)
-extern int32_t __REVSH(int32_t value);
-#else  /* (__ARMCC_VERSION >= 400677)  */
-static __INLINE __ASM int32_t __REVSH(int32_t value)
+static __attribute__((section(".revsh_text"))) __INLINE __ASM int32_t __REVSH(int32_t value)
 {
   revsh r0, r0
   bx lr
 }
-#endif /* __ARMCC_VERSION  */ 
 
 
 #if       (__CORTEX_M >= 0x03)
@@ -218,11 +215,7 @@
     This function removes the exclusive lock which is created by LDREX.
 
  */
-#if (__ARMCC_VERSION < 400000)
-extern void __CLREX(void);
-#else  /* (__ARMCC_VERSION >= 400000)  */
 #define __CLREX                           __clrex
-#endif /* __ARMCC_VERSION  */ 
 
 
 /** \brief  Signed Saturate
@@ -260,196 +253,13 @@
 
 
 
-#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
 /* IAR iccarm specific functions */
 
-#include <intrinsics.h>                     /* IAR Intrinsics   */
-
-#pragma diag_suppress=Pe940
-
-/** \brief  No Operation
-
-    No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-#define __NOP                           __no_operation
-
-
-/** \brief  Wait For Interrupt
-
-    Wait For Interrupt is a hint instruction that suspends execution
-    until one of a number of events occurs.
- */
-static __INLINE  void __WFI(void)
-{
-  __ASM ("wfi");
-}
-
-
-/** \brief  Wait For Event
-
-    Wait For Event is a hint instruction that permits the processor to enter
-    a low-power state until one of a number of events occurs.
- */
-static __INLINE  void __WFE(void)
-{
-  __ASM ("wfe");
-}
-
-
-/** \brief  Send Event
-
-    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-static __INLINE  void __SEV(void)
-{
-  __ASM ("sev");
-}
-
-
-/* intrinsic     void __ISB(void)            (see intrinsics.h) */
-/* intrinsic     void __DSB(void)            (see intrinsics.h) */
-/* intrinsic     void __DMB(void)            (see intrinsics.h) */
-/* intrinsic uint32_t __REV(uint32_t value)  (see intrinsics.h) */
-/* intrinsic          __SSAT                 (see intrinsics.h) */
-/* intrinsic          __USAT                 (see intrinsics.h) */
-
-
-/** \brief  Reverse byte order (16 bit)
-
-    This function reverses the byte order in two unsigned short values.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-static uint32_t __REV16(uint32_t value)
-{
-  __ASM("rev16 r0, r0");
-}
-
-
-/* intrinsic uint32_t __REVSH(uint32_t value)  (see intrinsics.h */
-
-
-#if       (__CORTEX_M >= 0x03)
-
-/** \brief  Reverse bit order of value
-
-    This function reverses the bit order of the given value.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-static uint32_t __RBIT(uint32_t value)
-{
-  __ASM("rbit r0, r0");
-}
+#include <cmsis_iar.h>
 
 
-/** \brief  LDR Exclusive (8 bit)
-
-    This function performs a exclusive LDR command for 8 bit value.
-
-    \param [in]    ptr  Pointer to data
-    \return             value of type uint8_t at (*ptr)
- */
-static uint8_t __LDREXB(volatile uint8_t *addr)
-{
-  __ASM("ldrexb r0, [r0]");
-}
-
-
-/** \brief  LDR Exclusive (16 bit)
-
-    This function performs a exclusive LDR command for 16 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint16_t at (*ptr)
- */
-static uint16_t __LDREXH(volatile uint16_t *addr)
-{
-  __ASM("ldrexh r0, [r0]");
-}
-
-
-/** \brief  LDR Exclusive (32 bit)
-
-    This function performs a exclusive LDR command for 32 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint32_t at (*ptr)
- */
-/* intrinsic unsigned long __LDREX(unsigned long *)  (see intrinsics.h) */
-static uint32_t __LDREXW(volatile uint32_t *addr)
-{
-  __ASM("ldrex r0, [r0]");
-}
-
-
-/** \brief  STR Exclusive (8 bit)
-
-    This function performs a exclusive STR command for 8 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-static uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
-{
-  __ASM("strexb r0, r0, [r1]");
-}
-
-
-/** \brief  STR Exclusive (16 bit)
-
-    This function performs a exclusive STR command for 16 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-static uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
-{
-  __ASM("strexh r0, r0, [r1]");
-}
-
-
-/** \brief  STR Exclusive (32 bit)
-
-    This function performs a exclusive STR command for 32 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-/* intrinsic unsigned long __STREX(unsigned long, unsigned long)  (see intrinsics.h )*/
-static uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
-{
-  __ASM("strex r0, r0, [r1]");
-}
-
-
-/** \brief  Remove the exclusive lock
-
-    This function removes the exclusive lock which is created by LDREX.
-
- */
-static __INLINE void __CLREX(void)
-{
-  __ASM ("clrex");
-}
-
-/* intrinsic   unsigned char __CLZ( unsigned long )      (see intrinsics.h) */
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-#pragma diag_default=Pe940
-
-
-
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
 /* GNU gcc specific functions */
 
 /** \brief  No Operation
@@ -655,7 +465,7 @@
 {
    uint32_t result;
   
-   __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+   __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
    return(result);
 }
 
@@ -673,7 +483,7 @@
 {
    uint32_t result;
   
-   __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+   __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
    return(result);
 }
 
@@ -691,7 +501,7 @@
 {
    uint32_t result;
   
-   __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+   __ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
    return(result);
 }
 
@@ -759,12 +569,12 @@
 
 
 
-#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
 /* TASKING carm specific functions */
 
 /*
  * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
  * Including the CMSIS ones.
  */
 
@@ -772,4 +582,4 @@
 
 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
 
-#endif /* __CORE_CMINSTR_H__ */
+#endif /* __CORE_CMINSTR_H */

Binary file LPC11U24/ARM/mbed.ar has changed

Binary file LPC11U24/ARM/sys.o has changed

Binary file LPC11U24/ARM/system_LPC11Uxx.o has changed

--- a/LPC11U24/GCC_ARM/core_cmFunc.h	Fri Jan 06 16:40:24 2012 +0000
+++ b/LPC11U24/GCC_ARM/core_cmFunc.h	Tue Jan 10 12:00:50 2012 +0000
@@ -1,11 +1,11 @@
 /**************************************************************************//**
  * @file     core_cmFunc.h
  * @brief    CMSIS Cortex-M Core Function Access Header File
- * @version  V2.01
- * @date     06. December 2010
+ * @version  V3.00
+ * @date     09. December 2011
  *
  * @note
- * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
  *
  * @par
  * ARM Limited (ARM) is supplying this software for use with Cortex-M 
@@ -21,8 +21,9 @@
  *
  ******************************************************************************/
 
-#ifndef __CORE_CMFUNC_H__
-#define __CORE_CMFUNC_H__
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
 
 /* ###########################  Core Function Access  ########################### */
 /** \ingroup  CMSIS_Core_FunctionInterface   
@@ -30,9 +31,13 @@
   @{
  */
 
-#if defined ( __CC_ARM   ) /*------------------ RealView Compiler ----------------*/
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
 /* ARM armcc specific functions */
 
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
 /* intrinsic void __enable_irq();     */
 /* intrinsic void __disable_irq();    */
 
@@ -42,15 +47,11 @@
 
     \return               Control Register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_CONTROL(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_CONTROL(void)
 {
   register uint32_t __regControl         __ASM("control");
   return(__regControl);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Set Control Register
@@ -59,32 +60,24 @@
 
     \param [in]    control  Control Register value to set
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          void __set_CONTROL(uint32_t control);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE void __set_CONTROL(uint32_t control)
 {
   register uint32_t __regControl         __ASM("control");
   __regControl = control;
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
-/** \brief  Get ISPR Register
-
-    This function returns the content of the ISPR Register.
+/** \brief  Get IPSR Register
 
-    \return               ISPR Register value
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_IPSR(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_IPSR(void)
 {
   register uint32_t __regIPSR          __ASM("ipsr");
   return(__regIPSR);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Get APSR Register
@@ -93,15 +86,11 @@
 
     \return               APSR Register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_APSR(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_APSR(void)
 {
   register uint32_t __regAPSR          __ASM("apsr");
   return(__regAPSR);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Get xPSR Register
@@ -110,15 +99,11 @@
 
     \return               xPSR Register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_xPSR(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_xPSR(void)
 {
   register uint32_t __regXPSR          __ASM("xpsr");
   return(__regXPSR);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Get Process Stack Pointer
@@ -127,15 +112,11 @@
 
     \return               PSP Register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_PSP(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_PSP(void)
 {
   register uint32_t __regProcessStackPointer  __ASM("psp");
   return(__regProcessStackPointer);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Set Process Stack Pointer
@@ -144,15 +125,11 @@
 
     \param [in]    topOfProcStack  Process Stack Pointer value to set
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          void __set_PSP(uint32_t topOfProcStack);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE void __set_PSP(uint32_t topOfProcStack)
 {
   register uint32_t __regProcessStackPointer  __ASM("psp");
   __regProcessStackPointer = topOfProcStack;
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Get Main Stack Pointer
@@ -161,15 +138,11 @@
 
     \return               MSP Register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_MSP(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_MSP(void)
 {
   register uint32_t __regMainStackPointer     __ASM("msp");
   return(__regMainStackPointer);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Set Main Stack Pointer
@@ -178,15 +151,11 @@
 
     \param [in]    topOfMainStack  Main Stack Pointer value to set
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          void __set_MSP(uint32_t topOfMainStack);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE void __set_MSP(uint32_t topOfMainStack)
 {
   register uint32_t __regMainStackPointer     __ASM("msp");
   __regMainStackPointer = topOfMainStack;
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Get Priority Mask
@@ -195,15 +164,11 @@
 
     \return               Priority Mask value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_PRIMASK(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_PRIMASK(void)
 {
   register uint32_t __regPriMask         __ASM("primask");
   return(__regPriMask);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Set Priority Mask
@@ -212,15 +177,11 @@
 
     \param [in]    priMask  Priority Mask
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          void __set_PRIMASK(uint32_t priMask);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE void __set_PRIMASK(uint32_t priMask)
 {
   register uint32_t __regPriMask         __ASM("primask");
   __regPriMask = (priMask);
 }
-#endif /*  __ARMCC_VERSION  */ 
  
 
 #if       (__CORTEX_M >= 0x03)
@@ -247,15 +208,11 @@
 
     \return               Base Priority register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_BASEPRI(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t  __get_BASEPRI(void)
 {
   register uint32_t __regBasePri         __ASM("basepri");
   return(__regBasePri);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Set Base Priority
@@ -264,15 +221,11 @@
 
     \param [in]    basePri  Base Priority value to set
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          void __set_BASEPRI(uint32_t basePri);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE void __set_BASEPRI(uint32_t basePri)
 {
   register uint32_t __regBasePri         __ASM("basepri");
   __regBasePri = (basePri & 0xff);
 }
-#endif /*  __ARMCC_VERSION  */ 
  
 
 /** \brief  Get Fault Mask
@@ -281,15 +234,11 @@
 
     \return               Fault Mask register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_FAULTMASK(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_FAULTMASK(void)
 {
   register uint32_t __regFaultMask       __ASM("faultmask");
   return(__regFaultMask);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Set Fault Mask
@@ -298,15 +247,11 @@
 
     \param [in]    faultMask  Fault Mask value to set
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          void __set_FAULTMASK(uint32_t faultMask);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE void __set_FAULTMASK(uint32_t faultMask)
 {
   register uint32_t __regFaultMask       __ASM("faultmask");
-  __regFaultMask = (faultMask & 1);
+  __regFaultMask = (faultMask & (uint32_t)1);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 #endif /* (__CORTEX_M >= 0x03) */
 
@@ -321,7 +266,7 @@
  */
 static __INLINE uint32_t __get_FPSCR(void)
 {
-#if (__FPU_PRESENT == 1)
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
   register uint32_t __regfpscr         __ASM("fpscr");
   return(__regfpscr);
 #else
@@ -338,7 +283,7 @@
  */
 static __INLINE void __set_FPSCR(uint32_t fpscr)
 {
-#if (__FPU_PRESENT == 1)
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
   register uint32_t __regfpscr         __ASM("fpscr");
   __regfpscr = (fpscr);
 #endif
@@ -347,192 +292,12 @@
 #endif /* (__CORTEX_M == 0x04) */
 
 
- #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
 /* IAR iccarm specific functions */
 
-#if defined (__ICCARM__)
-  #include <intrinsics.h>                     /* IAR Intrinsics   */
-#endif
-
-#pragma diag_suppress=Pe940
-
-/** \brief  Enable IRQ Interrupts
-
-  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
-  Can only be executed in Privileged modes.
- */
-#define __enable_irq                              __enable_interrupt
-
-
-/** \brief  Disable IRQ Interrupts
-
-  This function disables IRQ interrupts by setting the I-bit in the CPSR.
-  Can only be executed in Privileged modes.
- */
-#define __disable_irq                             __disable_interrupt
-
-
-/* intrinsic unsigned long __get_CONTROL( void ); (see intrinsic.h) */
-/* intrinsic void __set_CONTROL( unsigned long ); (see intrinsic.h) */
-
-
-/** \brief  Get ISPR Register
-
-    This function returns the content of the ISPR Register.
-
-    \return               ISPR Register value
- */
-static uint32_t __get_IPSR(void)
-{
-  __ASM("mrs r0, ipsr");
-}
-
-
-/** \brief  Get APSR Register
-
-    This function returns the content of the APSR Register.
-
-    \return               APSR Register value
- */
-static uint32_t __get_APSR(void)
-{
-  __ASM("mrs r0, apsr");
-}
-
-
-/** \brief  Get xPSR Register
-
-    This function returns the content of the xPSR Register.
-
-    \return               xPSR Register value
- */
-static uint32_t __get_xPSR(void)
-{
-  __ASM("mrs r0, psr");           // assembler does not know "xpsr"
-}
-
-
-/** \brief  Get Process Stack Pointer
-
-    This function returns the current value of the Process Stack Pointer (PSP).
-
-    \return               PSP Register value
- */
-static uint32_t __get_PSP(void)
-{
-  __ASM("mrs r0, psp");
-}
- 
-
-/** \brief  Set Process Stack Pointer
-
-    This function assigns the given value to the Process Stack Pointer (PSP).
-
-    \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-static void __set_PSP(uint32_t topOfProcStack)
-{
-  __ASM("msr psp, r0");
-}
-
-
-/** \brief  Get Main Stack Pointer
-
-    This function returns the current value of the Main Stack Pointer (MSP).
+#include <cmsis_iar.h>
 
-    \return               MSP Register value
- */
-static uint32_t __get_MSP(void)
-{
-  __ASM("mrs r0, msp");
-}
- 
-
-/** \brief  Set Main Stack Pointer
-
-    This function assigns the given value to the Main Stack Pointer (MSP).
-
-    \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-static void __set_MSP(uint32_t topOfMainStack)
-{
-  __ASM("msr msp, r0");
-}
- 
-
-/* intrinsic unsigned long __get_PRIMASK( void ); (see intrinsic.h) */
-/* intrinsic void __set_PRIMASK( unsigned long ); (see intrinsic.h) */
- 
-
-#if       (__CORTEX_M >= 0x03)
-
-/** \brief  Enable FIQ
-
-    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-static __INLINE void __enable_fault_irq(void)
-{
-  __ASM ("cpsie f");
-}
-
-
-/** \brief  Disable FIQ
-
-    This function disables FIQ interrupts by setting the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-static __INLINE void __disable_fault_irq(void)
-{
-  __ASM ("cpsid f");
-}
-
-
-/* intrinsic unsigned long __get_BASEPRI( void );   (see intrinsic.h) */
-/* intrinsic void __set_BASEPRI( unsigned long );   (see intrinsic.h) */
-/* intrinsic unsigned long __get_FAULTMASK( void ); (see intrinsic.h) */
-/* intrinsic void __set_FAULTMASK(unsigned long);   (see intrinsic.h) */
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-#if       (__CORTEX_M == 0x04)
-
-/** \brief  Get FPSCR
-
-    This function returns the current value of the Floating Point Status/Control register.
-
-    \return               Floating Point Status/Control register value
- */
-static uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1)
-  __ASM("vmrs r0, fpscr"); 
-#else
-  return(0);
-#endif
-}
-
-
-/** \brief  Set FPSCR
-
-    This function assigns the given value to the Floating Point Status/Control register.
-
-    \param [in]    fpscr  Floating Point Status/Control value to set
- */
-static void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1)
-  __ASM("vmsr fpscr, r0");
-#endif
-}
-
-#endif /* (__CORTEX_M == 0x04) */
-
-#pragma diag_default=Pe940
-
-
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
 /* GNU gcc specific functions */
 
 /** \brief  Enable IRQ Interrupts
@@ -584,11 +349,11 @@
 }
 
 
-/** \brief  Get ISPR Register
+/** \brief  Get IPSR Register
 
-    This function returns the content of the ISPR Register.
+    This function returns the content of the IPSR Register.
 
-    \return               ISPR Register value
+    \return               IPSR Register value
  */
 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void)
 {
@@ -800,10 +565,10 @@
  */
 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void)
 {
-#if (__FPU_PRESENT == 1)
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
   uint32_t result;
 
-  __ASM volatile ("MRS %0, fpscr" : "=r" (result) );
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
   return(result);
 #else
    return(0);
@@ -819,15 +584,15 @@
  */
 __attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr)
 {
-#if (__FPU_PRESENT == 1)
-  __ASM volatile ("MSR fpscr, %0" : : "r" (fpscr) );
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );
 #endif
 }
 
 #endif /* (__CORTEX_M == 0x04) */
 
 
-#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
 /* TASKING carm specific functions */
 
 /*
@@ -841,4 +606,4 @@
 /*@} end of CMSIS_Core_RegAccFunctions */
 
 
-#endif /* __CORE_CMFUNC_H__ */
+#endif /* __CORE_CMFUNC_H */

--- a/LPC11U24/GCC_ARM/core_cmInstr.h	Fri Jan 06 16:40:24 2012 +0000
+++ b/LPC11U24/GCC_ARM/core_cmInstr.h	Tue Jan 10 12:00:50 2012 +0000
@@ -1,11 +1,11 @@
 /**************************************************************************//**
  * @file     core_cmInstr.h
  * @brief    CMSIS Cortex-M Core Instruction Access Header File
- * @version  V2.01
- * @date     06. December 2010
+ * @version  V3.00
+ * @date     09. December 2011
  *
  * @note
- * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
  *
  * @par
  * ARM Limited (ARM) is supplying this software for use with Cortex-M 
@@ -21,8 +21,8 @@
  *
  ******************************************************************************/
 
-#ifndef __CORE_CMINSTR_H__
-#define __CORE_CMINSTR_H__
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
 
 
 /* ##########################  Core Instruction Access  ######################### */
@@ -31,9 +31,14 @@
   @{
 */
 
-#if defined ( __CC_ARM   ) /*------------------ RealView Compiler ----------------*/
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
 /* ARM armcc specific functions */
 
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
 /** \brief  No Operation
 
     No Operation does nothing. This instruction can be used for code alignment purposes.
@@ -106,15 +111,11 @@
     \param [in]    value  Value to reverse
     \return               Reversed value
  */
-#if (__ARMCC_VERSION < 400677)
-extern uint32_t __REV16(uint32_t value);
-#else  /* (__ARMCC_VERSION >= 400677)  */
-static __INLINE __ASM uint32_t __REV16(uint32_t value)
+static __attribute__((section(".rev16_text"))) __INLINE __ASM uint32_t __REV16(uint32_t value)
 {
   rev16 r0, r0
   bx lr
 }
-#endif /* __ARMCC_VERSION  */ 
 
 
 /** \brief  Reverse byte order in signed short value
@@ -124,15 +125,11 @@
     \param [in]    value  Value to reverse
     \return               Reversed value
  */
-#if (__ARMCC_VERSION < 400677)
-extern int32_t __REVSH(int32_t value);
-#else  /* (__ARMCC_VERSION >= 400677)  */
-static __INLINE __ASM int32_t __REVSH(int32_t value)
+static __attribute__((section(".revsh_text"))) __INLINE __ASM int32_t __REVSH(int32_t value)
 {
   revsh r0, r0
   bx lr
 }
-#endif /* __ARMCC_VERSION  */ 
 
 
 #if       (__CORTEX_M >= 0x03)
@@ -218,11 +215,7 @@
     This function removes the exclusive lock which is created by LDREX.
 
  */
-#if (__ARMCC_VERSION < 400000)
-extern void __CLREX(void);
-#else  /* (__ARMCC_VERSION >= 400000)  */
 #define __CLREX                           __clrex
-#endif /* __ARMCC_VERSION  */ 
 
 
 /** \brief  Signed Saturate
@@ -260,196 +253,13 @@
 
 
 
-#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
 /* IAR iccarm specific functions */
 
-#include <intrinsics.h>                     /* IAR Intrinsics   */
-
-#pragma diag_suppress=Pe940
-
-/** \brief  No Operation
-
-    No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-#define __NOP                           __no_operation
-
-
-/** \brief  Wait For Interrupt
-
-    Wait For Interrupt is a hint instruction that suspends execution
-    until one of a number of events occurs.
- */
-static __INLINE  void __WFI(void)
-{
-  __ASM ("wfi");
-}
-
-
-/** \brief  Wait For Event
-
-    Wait For Event is a hint instruction that permits the processor to enter
-    a low-power state until one of a number of events occurs.
- */
-static __INLINE  void __WFE(void)
-{
-  __ASM ("wfe");
-}
-
-
-/** \brief  Send Event
-
-    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-static __INLINE  void __SEV(void)
-{
-  __ASM ("sev");
-}
-
-
-/* intrinsic     void __ISB(void)            (see intrinsics.h) */
-/* intrinsic     void __DSB(void)            (see intrinsics.h) */
-/* intrinsic     void __DMB(void)            (see intrinsics.h) */
-/* intrinsic uint32_t __REV(uint32_t value)  (see intrinsics.h) */
-/* intrinsic          __SSAT                 (see intrinsics.h) */
-/* intrinsic          __USAT                 (see intrinsics.h) */
-
-
-/** \brief  Reverse byte order (16 bit)
-
-    This function reverses the byte order in two unsigned short values.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-static uint32_t __REV16(uint32_t value)
-{
-  __ASM("rev16 r0, r0");
-}
-
-
-/* intrinsic uint32_t __REVSH(uint32_t value)  (see intrinsics.h */
-
-
-#if       (__CORTEX_M >= 0x03)
-
-/** \brief  Reverse bit order of value
-
-    This function reverses the bit order of the given value.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-static uint32_t __RBIT(uint32_t value)
-{
-  __ASM("rbit r0, r0");
-}
+#include <cmsis_iar.h>
 
 
-/** \brief  LDR Exclusive (8 bit)
-
-    This function performs a exclusive LDR command for 8 bit value.
-
-    \param [in]    ptr  Pointer to data
-    \return             value of type uint8_t at (*ptr)
- */
-static uint8_t __LDREXB(volatile uint8_t *addr)
-{
-  __ASM("ldrexb r0, [r0]");
-}
-
-
-/** \brief  LDR Exclusive (16 bit)
-
-    This function performs a exclusive LDR command for 16 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint16_t at (*ptr)
- */
-static uint16_t __LDREXH(volatile uint16_t *addr)
-{
-  __ASM("ldrexh r0, [r0]");
-}
-
-
-/** \brief  LDR Exclusive (32 bit)
-
-    This function performs a exclusive LDR command for 32 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint32_t at (*ptr)
- */
-/* intrinsic unsigned long __LDREX(unsigned long *)  (see intrinsics.h) */
-static uint32_t __LDREXW(volatile uint32_t *addr)
-{
-  __ASM("ldrex r0, [r0]");
-}
-
-
-/** \brief  STR Exclusive (8 bit)
-
-    This function performs a exclusive STR command for 8 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-static uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
-{
-  __ASM("strexb r0, r0, [r1]");
-}
-
-
-/** \brief  STR Exclusive (16 bit)
-
-    This function performs a exclusive STR command for 16 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-static uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
-{
-  __ASM("strexh r0, r0, [r1]");
-}
-
-
-/** \brief  STR Exclusive (32 bit)
-
-    This function performs a exclusive STR command for 32 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-/* intrinsic unsigned long __STREX(unsigned long, unsigned long)  (see intrinsics.h )*/
-static uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
-{
-  __ASM("strex r0, r0, [r1]");
-}
-
-
-/** \brief  Remove the exclusive lock
-
-    This function removes the exclusive lock which is created by LDREX.
-
- */
-static __INLINE void __CLREX(void)
-{
-  __ASM ("clrex");
-}
-
-/* intrinsic   unsigned char __CLZ( unsigned long )      (see intrinsics.h) */
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-#pragma diag_default=Pe940
-
-
-
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
 /* GNU gcc specific functions */
 
 /** \brief  No Operation
@@ -655,7 +465,7 @@
 {
    uint32_t result;
   
-   __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+   __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
    return(result);
 }
 
@@ -673,7 +483,7 @@
 {
    uint32_t result;
   
-   __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+   __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
    return(result);
 }
 
@@ -691,7 +501,7 @@
 {
    uint32_t result;
   
-   __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+   __ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
    return(result);
 }
 
@@ -759,12 +569,12 @@
 
 
 
-#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
 /* TASKING carm specific functions */
 
 /*
  * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
  * Including the CMSIS ones.
  */
 
@@ -772,4 +582,4 @@
 
 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
 
-#endif /* __CORE_CMINSTR_H__ */
+#endif /* __CORE_CMINSTR_H */

Binary file LPC11U24/GCC_ARM/libcapi.a has changed

Binary file LPC11U24/GCC_ARM/libmbed.a has changed

--- a/LPC11U24/GCC_CR/core_cmFunc.h	Fri Jan 06 16:40:24 2012 +0000
+++ b/LPC11U24/GCC_CR/core_cmFunc.h	Tue Jan 10 12:00:50 2012 +0000
@@ -1,11 +1,11 @@
 /**************************************************************************//**
  * @file     core_cmFunc.h
  * @brief    CMSIS Cortex-M Core Function Access Header File
- * @version  V2.01
- * @date     06. December 2010
+ * @version  V3.00
+ * @date     09. December 2011
  *
  * @note
- * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
  *
  * @par
  * ARM Limited (ARM) is supplying this software for use with Cortex-M 
@@ -21,8 +21,9 @@
  *
  ******************************************************************************/
 
-#ifndef __CORE_CMFUNC_H__
-#define __CORE_CMFUNC_H__
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
 
 /* ###########################  Core Function Access  ########################### */
 /** \ingroup  CMSIS_Core_FunctionInterface   
@@ -30,9 +31,13 @@
   @{
  */
 
-#if defined ( __CC_ARM   ) /*------------------ RealView Compiler ----------------*/
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
 /* ARM armcc specific functions */
 
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
 /* intrinsic void __enable_irq();     */
 /* intrinsic void __disable_irq();    */
 
@@ -42,15 +47,11 @@
 
     \return               Control Register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_CONTROL(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_CONTROL(void)
 {
   register uint32_t __regControl         __ASM("control");
   return(__regControl);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Set Control Register
@@ -59,32 +60,24 @@
 
     \param [in]    control  Control Register value to set
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          void __set_CONTROL(uint32_t control);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE void __set_CONTROL(uint32_t control)
 {
   register uint32_t __regControl         __ASM("control");
   __regControl = control;
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
-/** \brief  Get ISPR Register
-
-    This function returns the content of the ISPR Register.
+/** \brief  Get IPSR Register
 
-    \return               ISPR Register value
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_IPSR(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_IPSR(void)
 {
   register uint32_t __regIPSR          __ASM("ipsr");
   return(__regIPSR);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Get APSR Register
@@ -93,15 +86,11 @@
 
     \return               APSR Register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_APSR(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_APSR(void)
 {
   register uint32_t __regAPSR          __ASM("apsr");
   return(__regAPSR);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Get xPSR Register
@@ -110,15 +99,11 @@
 
     \return               xPSR Register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_xPSR(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_xPSR(void)
 {
   register uint32_t __regXPSR          __ASM("xpsr");
   return(__regXPSR);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Get Process Stack Pointer
@@ -127,15 +112,11 @@
 
     \return               PSP Register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_PSP(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_PSP(void)
 {
   register uint32_t __regProcessStackPointer  __ASM("psp");
   return(__regProcessStackPointer);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Set Process Stack Pointer
@@ -144,15 +125,11 @@
 
     \param [in]    topOfProcStack  Process Stack Pointer value to set
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          void __set_PSP(uint32_t topOfProcStack);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE void __set_PSP(uint32_t topOfProcStack)
 {
   register uint32_t __regProcessStackPointer  __ASM("psp");
   __regProcessStackPointer = topOfProcStack;
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Get Main Stack Pointer
@@ -161,15 +138,11 @@
 
     \return               MSP Register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_MSP(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_MSP(void)
 {
   register uint32_t __regMainStackPointer     __ASM("msp");
   return(__regMainStackPointer);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Set Main Stack Pointer
@@ -178,15 +151,11 @@
 
     \param [in]    topOfMainStack  Main Stack Pointer value to set
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          void __set_MSP(uint32_t topOfMainStack);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE void __set_MSP(uint32_t topOfMainStack)
 {
   register uint32_t __regMainStackPointer     __ASM("msp");
   __regMainStackPointer = topOfMainStack;
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Get Priority Mask
@@ -195,15 +164,11 @@
 
     \return               Priority Mask value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_PRIMASK(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_PRIMASK(void)
 {
   register uint32_t __regPriMask         __ASM("primask");
   return(__regPriMask);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Set Priority Mask
@@ -212,15 +177,11 @@
 
     \param [in]    priMask  Priority Mask
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          void __set_PRIMASK(uint32_t priMask);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE void __set_PRIMASK(uint32_t priMask)
 {
   register uint32_t __regPriMask         __ASM("primask");
   __regPriMask = (priMask);
 }
-#endif /*  __ARMCC_VERSION  */ 
  
 
 #if       (__CORTEX_M >= 0x03)
@@ -247,15 +208,11 @@
 
     \return               Base Priority register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_BASEPRI(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t  __get_BASEPRI(void)
 {
   register uint32_t __regBasePri         __ASM("basepri");
   return(__regBasePri);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Set Base Priority
@@ -264,15 +221,11 @@
 
     \param [in]    basePri  Base Priority value to set
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          void __set_BASEPRI(uint32_t basePri);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE void __set_BASEPRI(uint32_t basePri)
 {
   register uint32_t __regBasePri         __ASM("basepri");
   __regBasePri = (basePri & 0xff);
 }
-#endif /*  __ARMCC_VERSION  */ 
  
 
 /** \brief  Get Fault Mask
@@ -281,15 +234,11 @@
 
     \return               Fault Mask register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_FAULTMASK(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_FAULTMASK(void)
 {
   register uint32_t __regFaultMask       __ASM("faultmask");
   return(__regFaultMask);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Set Fault Mask
@@ -298,15 +247,11 @@
 
     \param [in]    faultMask  Fault Mask value to set
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          void __set_FAULTMASK(uint32_t faultMask);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE void __set_FAULTMASK(uint32_t faultMask)
 {
   register uint32_t __regFaultMask       __ASM("faultmask");
-  __regFaultMask = (faultMask & 1);
+  __regFaultMask = (faultMask & (uint32_t)1);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 #endif /* (__CORTEX_M >= 0x03) */
 
@@ -321,7 +266,7 @@
  */
 static __INLINE uint32_t __get_FPSCR(void)
 {
-#if (__FPU_PRESENT == 1)
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
   register uint32_t __regfpscr         __ASM("fpscr");
   return(__regfpscr);
 #else
@@ -338,7 +283,7 @@
  */
 static __INLINE void __set_FPSCR(uint32_t fpscr)
 {
-#if (__FPU_PRESENT == 1)
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
   register uint32_t __regfpscr         __ASM("fpscr");
   __regfpscr = (fpscr);
 #endif
@@ -347,192 +292,12 @@
 #endif /* (__CORTEX_M == 0x04) */
 
 
- #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
 /* IAR iccarm specific functions */
 
-#if defined (__ICCARM__)
-  #include <intrinsics.h>                     /* IAR Intrinsics   */
-#endif
-
-#pragma diag_suppress=Pe940
-
-/** \brief  Enable IRQ Interrupts
-
-  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
-  Can only be executed in Privileged modes.
- */
-#define __enable_irq                              __enable_interrupt
-
-
-/** \brief  Disable IRQ Interrupts
-
-  This function disables IRQ interrupts by setting the I-bit in the CPSR.
-  Can only be executed in Privileged modes.
- */
-#define __disable_irq                             __disable_interrupt
-
-
-/* intrinsic unsigned long __get_CONTROL( void ); (see intrinsic.h) */
-/* intrinsic void __set_CONTROL( unsigned long ); (see intrinsic.h) */
-
-
-/** \brief  Get ISPR Register
-
-    This function returns the content of the ISPR Register.
-
-    \return               ISPR Register value
- */
-static uint32_t __get_IPSR(void)
-{
-  __ASM("mrs r0, ipsr");
-}
-
-
-/** \brief  Get APSR Register
-
-    This function returns the content of the APSR Register.
-
-    \return               APSR Register value
- */
-static uint32_t __get_APSR(void)
-{
-  __ASM("mrs r0, apsr");
-}
-
-
-/** \brief  Get xPSR Register
-
-    This function returns the content of the xPSR Register.
-
-    \return               xPSR Register value
- */
-static uint32_t __get_xPSR(void)
-{
-  __ASM("mrs r0, psr");           // assembler does not know "xpsr"
-}
-
-
-/** \brief  Get Process Stack Pointer
-
-    This function returns the current value of the Process Stack Pointer (PSP).
-
-    \return               PSP Register value
- */
-static uint32_t __get_PSP(void)
-{
-  __ASM("mrs r0, psp");
-}
- 
-
-/** \brief  Set Process Stack Pointer
-
-    This function assigns the given value to the Process Stack Pointer (PSP).
-
-    \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-static void __set_PSP(uint32_t topOfProcStack)
-{
-  __ASM("msr psp, r0");
-}
-
-
-/** \brief  Get Main Stack Pointer
-
-    This function returns the current value of the Main Stack Pointer (MSP).
+#include <cmsis_iar.h>
 
-    \return               MSP Register value
- */
-static uint32_t __get_MSP(void)
-{
-  __ASM("mrs r0, msp");
-}
- 
-
-/** \brief  Set Main Stack Pointer
-
-    This function assigns the given value to the Main Stack Pointer (MSP).
-
-    \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-static void __set_MSP(uint32_t topOfMainStack)
-{
-  __ASM("msr msp, r0");
-}
- 
-
-/* intrinsic unsigned long __get_PRIMASK( void ); (see intrinsic.h) */
-/* intrinsic void __set_PRIMASK( unsigned long ); (see intrinsic.h) */
- 
-
-#if       (__CORTEX_M >= 0x03)
-
-/** \brief  Enable FIQ
-
-    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-static __INLINE void __enable_fault_irq(void)
-{
-  __ASM ("cpsie f");
-}
-
-
-/** \brief  Disable FIQ
-
-    This function disables FIQ interrupts by setting the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-static __INLINE void __disable_fault_irq(void)
-{
-  __ASM ("cpsid f");
-}
-
-
-/* intrinsic unsigned long __get_BASEPRI( void );   (see intrinsic.h) */
-/* intrinsic void __set_BASEPRI( unsigned long );   (see intrinsic.h) */
-/* intrinsic unsigned long __get_FAULTMASK( void ); (see intrinsic.h) */
-/* intrinsic void __set_FAULTMASK(unsigned long);   (see intrinsic.h) */
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-#if       (__CORTEX_M == 0x04)
-
-/** \brief  Get FPSCR
-
-    This function returns the current value of the Floating Point Status/Control register.
-
-    \return               Floating Point Status/Control register value
- */
-static uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1)
-  __ASM("vmrs r0, fpscr"); 
-#else
-  return(0);
-#endif
-}
-
-
-/** \brief  Set FPSCR
-
-    This function assigns the given value to the Floating Point Status/Control register.
-
-    \param [in]    fpscr  Floating Point Status/Control value to set
- */
-static void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1)
-  __ASM("vmsr fpscr, r0");
-#endif
-}
-
-#endif /* (__CORTEX_M == 0x04) */
-
-#pragma diag_default=Pe940
-
-
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
 /* GNU gcc specific functions */
 
 /** \brief  Enable IRQ Interrupts
@@ -584,11 +349,11 @@
 }
 
 
-/** \brief  Get ISPR Register
+/** \brief  Get IPSR Register
 
-    This function returns the content of the ISPR Register.
+    This function returns the content of the IPSR Register.
 
-    \return               ISPR Register value
+    \return               IPSR Register value
  */
 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void)
 {
@@ -800,10 +565,10 @@
  */
 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void)
 {
-#if (__FPU_PRESENT == 1)
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
   uint32_t result;
 
-  __ASM volatile ("MRS %0, fpscr" : "=r" (result) );
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
   return(result);
 #else
    return(0);
@@ -819,15 +584,15 @@
  */
 __attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr)
 {
-#if (__FPU_PRESENT == 1)
-  __ASM volatile ("MSR fpscr, %0" : : "r" (fpscr) );
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );
 #endif
 }
 
 #endif /* (__CORTEX_M == 0x04) */
 
 
-#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
 /* TASKING carm specific functions */
 
 /*
@@ -841,4 +606,4 @@
 /*@} end of CMSIS_Core_RegAccFunctions */
 
 
-#endif /* __CORE_CMFUNC_H__ */
+#endif /* __CORE_CMFUNC_H */

--- a/LPC11U24/GCC_CR/core_cmInstr.h	Fri Jan 06 16:40:24 2012 +0000
+++ b/LPC11U24/GCC_CR/core_cmInstr.h	Tue Jan 10 12:00:50 2012 +0000
@@ -1,11 +1,11 @@
 /**************************************************************************//**
  * @file     core_cmInstr.h
  * @brief    CMSIS Cortex-M Core Instruction Access Header File
- * @version  V2.01
- * @date     06. December 2010
+ * @version  V3.00
+ * @date     09. December 2011
  *
  * @note
- * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
  *
  * @par
  * ARM Limited (ARM) is supplying this software for use with Cortex-M 
@@ -21,8 +21,8 @@
  *
  ******************************************************************************/
 
-#ifndef __CORE_CMINSTR_H__
-#define __CORE_CMINSTR_H__
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
 
 
 /* ##########################  Core Instruction Access  ######################### */
@@ -31,9 +31,14 @@
   @{
 */
 
-#if defined ( __CC_ARM   ) /*------------------ RealView Compiler ----------------*/
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
 /* ARM armcc specific functions */
 
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
 /** \brief  No Operation
 
     No Operation does nothing. This instruction can be used for code alignment purposes.
@@ -106,15 +111,11 @@
     \param [in]    value  Value to reverse
     \return               Reversed value
  */
-#if (__ARMCC_VERSION < 400677)
-extern uint32_t __REV16(uint32_t value);
-#else  /* (__ARMCC_VERSION >= 400677)  */
-static __INLINE __ASM uint32_t __REV16(uint32_t value)
+static __attribute__((section(".rev16_text"))) __INLINE __ASM uint32_t __REV16(uint32_t value)
 {
   rev16 r0, r0
   bx lr
 }
-#endif /* __ARMCC_VERSION  */ 
 
 
 /** \brief  Reverse byte order in signed short value
@@ -124,15 +125,11 @@
     \param [in]    value  Value to reverse
     \return               Reversed value
  */
-#if (__ARMCC_VERSION < 400677)
-extern int32_t __REVSH(int32_t value);
-#else  /* (__ARMCC_VERSION >= 400677)  */
-static __INLINE __ASM int32_t __REVSH(int32_t value)
+static __attribute__((section(".revsh_text"))) __INLINE __ASM int32_t __REVSH(int32_t value)
 {
   revsh r0, r0
   bx lr
 }
-#endif /* __ARMCC_VERSION  */ 
 
 
 #if       (__CORTEX_M >= 0x03)
@@ -218,11 +215,7 @@
     This function removes the exclusive lock which is created by LDREX.
 
  */
-#if (__ARMCC_VERSION < 400000)
-extern void __CLREX(void);
-#else  /* (__ARMCC_VERSION >= 400000)  */
 #define __CLREX                           __clrex
-#endif /* __ARMCC_VERSION  */ 
 
 
 /** \brief  Signed Saturate
@@ -260,196 +253,13 @@
 
 
 
-#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
 /* IAR iccarm specific functions */
 
-#include <intrinsics.h>                     /* IAR Intrinsics   */
-
-#pragma diag_suppress=Pe940
-
-/** \brief  No Operation
-
-    No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-#define __NOP                           __no_operation
-
-
-/** \brief  Wait For Interrupt
-
-    Wait For Interrupt is a hint instruction that suspends execution
-    until one of a number of events occurs.
- */
-static __INLINE  void __WFI(void)
-{
-  __ASM ("wfi");
-}
-
-
-/** \brief  Wait For Event
-
-    Wait For Event is a hint instruction that permits the processor to enter
-    a low-power state until one of a number of events occurs.
- */
-static __INLINE  void __WFE(void)
-{
-  __ASM ("wfe");
-}
-
-
-/** \brief  Send Event
-
-    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-static __INLINE  void __SEV(void)
-{
-  __ASM ("sev");
-}
-
-
-/* intrinsic     void __ISB(void)            (see intrinsics.h) */
-/* intrinsic     void __DSB(void)            (see intrinsics.h) */
-/* intrinsic     void __DMB(void)            (see intrinsics.h) */
-/* intrinsic uint32_t __REV(uint32_t value)  (see intrinsics.h) */
-/* intrinsic          __SSAT                 (see intrinsics.h) */
-/* intrinsic          __USAT                 (see intrinsics.h) */
-
-
-/** \brief  Reverse byte order (16 bit)
-
-    This function reverses the byte order in two unsigned short values.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-static uint32_t __REV16(uint32_t value)
-{
-  __ASM("rev16 r0, r0");
-}
-
-
-/* intrinsic uint32_t __REVSH(uint32_t value)  (see intrinsics.h */
-
-
-#if       (__CORTEX_M >= 0x03)
-
-/** \brief  Reverse bit order of value
-
-    This function reverses the bit order of the given value.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-static uint32_t __RBIT(uint32_t value)
-{
-  __ASM("rbit r0, r0");
-}
+#include <cmsis_iar.h>
 
 
-/** \brief  LDR Exclusive (8 bit)
-
-    This function performs a exclusive LDR command for 8 bit value.
-
-    \param [in]    ptr  Pointer to data
-    \return             value of type uint8_t at (*ptr)
- */
-static uint8_t __LDREXB(volatile uint8_t *addr)
-{
-  __ASM("ldrexb r0, [r0]");
-}
-
-
-/** \brief  LDR Exclusive (16 bit)
-
-    This function performs a exclusive LDR command for 16 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint16_t at (*ptr)
- */
-static uint16_t __LDREXH(volatile uint16_t *addr)
-{
-  __ASM("ldrexh r0, [r0]");
-}
-
-
-/** \brief  LDR Exclusive (32 bit)
-
-    This function performs a exclusive LDR command for 32 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint32_t at (*ptr)
- */
-/* intrinsic unsigned long __LDREX(unsigned long *)  (see intrinsics.h) */
-static uint32_t __LDREXW(volatile uint32_t *addr)
-{
-  __ASM("ldrex r0, [r0]");
-}
-
-
-/** \brief  STR Exclusive (8 bit)
-
-    This function performs a exclusive STR command for 8 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-static uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
-{
-  __ASM("strexb r0, r0, [r1]");
-}
-
-
-/** \brief  STR Exclusive (16 bit)
-
-    This function performs a exclusive STR command for 16 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-static uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
-{
-  __ASM("strexh r0, r0, [r1]");
-}
-
-
-/** \brief  STR Exclusive (32 bit)
-
-    This function performs a exclusive STR command for 32 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-/* intrinsic unsigned long __STREX(unsigned long, unsigned long)  (see intrinsics.h )*/
-static uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
-{
-  __ASM("strex r0, r0, [r1]");
-}
-
-
-/** \brief  Remove the exclusive lock
-
-    This function removes the exclusive lock which is created by LDREX.
-
- */
-static __INLINE void __CLREX(void)
-{
-  __ASM ("clrex");
-}
-
-/* intrinsic   unsigned char __CLZ( unsigned long )      (see intrinsics.h) */
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-#pragma diag_default=Pe940
-
-
-
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
 /* GNU gcc specific functions */
 
 /** \brief  No Operation
@@ -655,7 +465,7 @@
 {
    uint32_t result;
   
-   __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+   __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
    return(result);
 }
 
@@ -673,7 +483,7 @@
 {
    uint32_t result;
   
-   __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+   __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
    return(result);
 }
 
@@ -691,7 +501,7 @@
 {
    uint32_t result;
   
-   __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+   __ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
    return(result);
 }
 
@@ -759,12 +569,12 @@
 
 
 
-#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
 /* TASKING carm specific functions */
 
 /*
  * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
  * Including the CMSIS ones.
  */
 
@@ -772,4 +582,4 @@
 
 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
 
-#endif /* __CORE_CMINSTR_H__ */
+#endif /* __CORE_CMINSTR_H */

Binary file LPC11U24/GCC_CR/libcapi.a has changed

Binary file LPC11U24/GCC_CR/libmbed.a has changed

--- a/LPC11U24/GCC_CS/core_cmFunc.h	Fri Jan 06 16:40:24 2012 +0000
+++ b/LPC11U24/GCC_CS/core_cmFunc.h	Tue Jan 10 12:00:50 2012 +0000
@@ -1,11 +1,11 @@
 /**************************************************************************//**
  * @file     core_cmFunc.h
  * @brief    CMSIS Cortex-M Core Function Access Header File
- * @version  V2.01
- * @date     06. December 2010
+ * @version  V3.00
+ * @date     09. December 2011
  *
  * @note
- * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
  *
  * @par
  * ARM Limited (ARM) is supplying this software for use with Cortex-M 
@@ -21,8 +21,9 @@
  *
  ******************************************************************************/
 
-#ifndef __CORE_CMFUNC_H__
-#define __CORE_CMFUNC_H__
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
 
 /* ###########################  Core Function Access  ########################### */
 /** \ingroup  CMSIS_Core_FunctionInterface   
@@ -30,9 +31,13 @@
   @{
  */
 
-#if defined ( __CC_ARM   ) /*------------------ RealView Compiler ----------------*/
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
 /* ARM armcc specific functions */
 
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
 /* intrinsic void __enable_irq();     */
 /* intrinsic void __disable_irq();    */
 
@@ -42,15 +47,11 @@
 
     \return               Control Register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_CONTROL(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_CONTROL(void)
 {
   register uint32_t __regControl         __ASM("control");
   return(__regControl);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Set Control Register
@@ -59,32 +60,24 @@
 
     \param [in]    control  Control Register value to set
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          void __set_CONTROL(uint32_t control);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE void __set_CONTROL(uint32_t control)
 {
   register uint32_t __regControl         __ASM("control");
   __regControl = control;
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
-/** \brief  Get ISPR Register
-
-    This function returns the content of the ISPR Register.
+/** \brief  Get IPSR Register
 
-    \return               ISPR Register value
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_IPSR(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_IPSR(void)
 {
   register uint32_t __regIPSR          __ASM("ipsr");
   return(__regIPSR);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Get APSR Register
@@ -93,15 +86,11 @@
 
     \return               APSR Register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_APSR(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_APSR(void)
 {
   register uint32_t __regAPSR          __ASM("apsr");
   return(__regAPSR);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Get xPSR Register
@@ -110,15 +99,11 @@
 
     \return               xPSR Register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_xPSR(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_xPSR(void)
 {
   register uint32_t __regXPSR          __ASM("xpsr");
   return(__regXPSR);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Get Process Stack Pointer
@@ -127,15 +112,11 @@
 
     \return               PSP Register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_PSP(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_PSP(void)
 {
   register uint32_t __regProcessStackPointer  __ASM("psp");
   return(__regProcessStackPointer);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Set Process Stack Pointer
@@ -144,15 +125,11 @@
 
     \param [in]    topOfProcStack  Process Stack Pointer value to set
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          void __set_PSP(uint32_t topOfProcStack);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE void __set_PSP(uint32_t topOfProcStack)
 {
   register uint32_t __regProcessStackPointer  __ASM("psp");
   __regProcessStackPointer = topOfProcStack;
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Get Main Stack Pointer
@@ -161,15 +138,11 @@
 
     \return               MSP Register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_MSP(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_MSP(void)
 {
   register uint32_t __regMainStackPointer     __ASM("msp");
   return(__regMainStackPointer);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Set Main Stack Pointer
@@ -178,15 +151,11 @@
 
     \param [in]    topOfMainStack  Main Stack Pointer value to set
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          void __set_MSP(uint32_t topOfMainStack);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE void __set_MSP(uint32_t topOfMainStack)
 {
   register uint32_t __regMainStackPointer     __ASM("msp");
   __regMainStackPointer = topOfMainStack;
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Get Priority Mask
@@ -195,15 +164,11 @@
 
     \return               Priority Mask value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_PRIMASK(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_PRIMASK(void)
 {
   register uint32_t __regPriMask         __ASM("primask");
   return(__regPriMask);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Set Priority Mask
@@ -212,15 +177,11 @@
 
     \param [in]    priMask  Priority Mask
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          void __set_PRIMASK(uint32_t priMask);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE void __set_PRIMASK(uint32_t priMask)
 {
   register uint32_t __regPriMask         __ASM("primask");
   __regPriMask = (priMask);
 }
-#endif /*  __ARMCC_VERSION  */ 
  
 
 #if       (__CORTEX_M >= 0x03)
@@ -247,15 +208,11 @@
 
     \return               Base Priority register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_BASEPRI(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t  __get_BASEPRI(void)
 {
   register uint32_t __regBasePri         __ASM("basepri");
   return(__regBasePri);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Set Base Priority
@@ -264,15 +221,11 @@
 
     \param [in]    basePri  Base Priority value to set
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          void __set_BASEPRI(uint32_t basePri);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE void __set_BASEPRI(uint32_t basePri)
 {
   register uint32_t __regBasePri         __ASM("basepri");
   __regBasePri = (basePri & 0xff);
 }
-#endif /*  __ARMCC_VERSION  */ 
  
 
 /** \brief  Get Fault Mask
@@ -281,15 +234,11 @@
 
     \return               Fault Mask register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_FAULTMASK(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_FAULTMASK(void)
 {
   register uint32_t __regFaultMask       __ASM("faultmask");
   return(__regFaultMask);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Set Fault Mask
@@ -298,15 +247,11 @@
 
     \param [in]    faultMask  Fault Mask value to set
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          void __set_FAULTMASK(uint32_t faultMask);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE void __set_FAULTMASK(uint32_t faultMask)
 {
   register uint32_t __regFaultMask       __ASM("faultmask");
-  __regFaultMask = (faultMask & 1);
+  __regFaultMask = (faultMask & (uint32_t)1);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 #endif /* (__CORTEX_M >= 0x03) */
 
@@ -321,7 +266,7 @@
  */
 static __INLINE uint32_t __get_FPSCR(void)
 {
-#if (__FPU_PRESENT == 1)
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
   register uint32_t __regfpscr         __ASM("fpscr");
   return(__regfpscr);
 #else
@@ -338,7 +283,7 @@
  */
 static __INLINE void __set_FPSCR(uint32_t fpscr)
 {
-#if (__FPU_PRESENT == 1)
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
   register uint32_t __regfpscr         __ASM("fpscr");
   __regfpscr = (fpscr);
 #endif
@@ -347,192 +292,12 @@
 #endif /* (__CORTEX_M == 0x04) */
 
 
- #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
 /* IAR iccarm specific functions */
 
-#if defined (__ICCARM__)
-  #include <intrinsics.h>                     /* IAR Intrinsics   */
-#endif
-
-#pragma diag_suppress=Pe940
-
-/** \brief  Enable IRQ Interrupts
-
-  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
-  Can only be executed in Privileged modes.
- */
-#define __enable_irq                              __enable_interrupt
-
-
-/** \brief  Disable IRQ Interrupts
-
-  This function disables IRQ interrupts by setting the I-bit in the CPSR.
-  Can only be executed in Privileged modes.
- */
-#define __disable_irq                             __disable_interrupt
-
-
-/* intrinsic unsigned long __get_CONTROL( void ); (see intrinsic.h) */
-/* intrinsic void __set_CONTROL( unsigned long ); (see intrinsic.h) */
-
-
-/** \brief  Get ISPR Register
-
-    This function returns the content of the ISPR Register.
-
-    \return               ISPR Register value
- */
-static uint32_t __get_IPSR(void)
-{
-  __ASM("mrs r0, ipsr");
-}
-
-
-/** \brief  Get APSR Register
-
-    This function returns the content of the APSR Register.
-
-    \return               APSR Register value
- */
-static uint32_t __get_APSR(void)
-{
-  __ASM("mrs r0, apsr");
-}
-
-
-/** \brief  Get xPSR Register
-
-    This function returns the content of the xPSR Register.
-
-    \return               xPSR Register value
- */
-static uint32_t __get_xPSR(void)
-{
-  __ASM("mrs r0, psr");           // assembler does not know "xpsr"
-}
-
-
-/** \brief  Get Process Stack Pointer
-
-    This function returns the current value of the Process Stack Pointer (PSP).
-
-    \return               PSP Register value
- */
-static uint32_t __get_PSP(void)
-{
-  __ASM("mrs r0, psp");
-}
- 
-
-/** \brief  Set Process Stack Pointer
-
-    This function assigns the given value to the Process Stack Pointer (PSP).
-
-    \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-static void __set_PSP(uint32_t topOfProcStack)
-{
-  __ASM("msr psp, r0");
-}
-
-
-/** \brief  Get Main Stack Pointer
-
-    This function returns the current value of the Main Stack Pointer (MSP).
+#include <cmsis_iar.h>
 
-    \return               MSP Register value
- */
-static uint32_t __get_MSP(void)
-{
-  __ASM("mrs r0, msp");
-}
- 
-
-/** \brief  Set Main Stack Pointer
-
-    This function assigns the given value to the Main Stack Pointer (MSP).
-
-    \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-static void __set_MSP(uint32_t topOfMainStack)
-{
-  __ASM("msr msp, r0");
-}
- 
-
-/* intrinsic unsigned long __get_PRIMASK( void ); (see intrinsic.h) */
-/* intrinsic void __set_PRIMASK( unsigned long ); (see intrinsic.h) */
- 
-
-#if       (__CORTEX_M >= 0x03)
-
-/** \brief  Enable FIQ
-
-    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-static __INLINE void __enable_fault_irq(void)
-{
-  __ASM ("cpsie f");
-}
-
-
-/** \brief  Disable FIQ
-
-    This function disables FIQ interrupts by setting the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-static __INLINE void __disable_fault_irq(void)
-{
-  __ASM ("cpsid f");
-}
-
-
-/* intrinsic unsigned long __get_BASEPRI( void );   (see intrinsic.h) */
-/* intrinsic void __set_BASEPRI( unsigned long );   (see intrinsic.h) */
-/* intrinsic unsigned long __get_FAULTMASK( void ); (see intrinsic.h) */
-/* intrinsic void __set_FAULTMASK(unsigned long);   (see intrinsic.h) */
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-#if       (__CORTEX_M == 0x04)
-
-/** \brief  Get FPSCR
-
-    This function returns the current value of the Floating Point Status/Control register.
-
-    \return               Floating Point Status/Control register value
- */
-static uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1)
-  __ASM("vmrs r0, fpscr"); 
-#else
-  return(0);
-#endif
-}
-
-
-/** \brief  Set FPSCR
-
-    This function assigns the given value to the Floating Point Status/Control register.
-
-    \param [in]    fpscr  Floating Point Status/Control value to set
- */
-static void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1)
-  __ASM("vmsr fpscr, r0");
-#endif
-}
-
-#endif /* (__CORTEX_M == 0x04) */
-
-#pragma diag_default=Pe940
-
-
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
 /* GNU gcc specific functions */
 
 /** \brief  Enable IRQ Interrupts
@@ -584,11 +349,11 @@
 }
 
 
-/** \brief  Get ISPR Register
+/** \brief  Get IPSR Register
 
-    This function returns the content of the ISPR Register.
+    This function returns the content of the IPSR Register.
 
-    \return               ISPR Register value
+    \return               IPSR Register value
  */
 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void)
 {
@@ -800,10 +565,10 @@
  */
 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void)
 {
-#if (__FPU_PRESENT == 1)
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
   uint32_t result;
 
-  __ASM volatile ("MRS %0, fpscr" : "=r" (result) );
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
   return(result);
 #else
    return(0);
@@ -819,15 +584,15 @@
  */
 __attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr)
 {
-#if (__FPU_PRESENT == 1)
-  __ASM volatile ("MSR fpscr, %0" : : "r" (fpscr) );
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );
 #endif
 }
 
 #endif /* (__CORTEX_M == 0x04) */
 
 
-#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
 /* TASKING carm specific functions */
 
 /*
@@ -841,4 +606,4 @@
 /*@} end of CMSIS_Core_RegAccFunctions */
 
 
-#endif /* __CORE_CMFUNC_H__ */
+#endif /* __CORE_CMFUNC_H */

--- a/LPC11U24/GCC_CS/core_cmInstr.h	Fri Jan 06 16:40:24 2012 +0000
+++ b/LPC11U24/GCC_CS/core_cmInstr.h	Tue Jan 10 12:00:50 2012 +0000
@@ -1,11 +1,11 @@
 /**************************************************************************//**
  * @file     core_cmInstr.h
  * @brief    CMSIS Cortex-M Core Instruction Access Header File
- * @version  V2.01
- * @date     06. December 2010
+ * @version  V3.00
+ * @date     09. December 2011
  *
  * @note
- * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
  *
  * @par
  * ARM Limited (ARM) is supplying this software for use with Cortex-M 
@@ -21,8 +21,8 @@
  *
  ******************************************************************************/
 
-#ifndef __CORE_CMINSTR_H__
-#define __CORE_CMINSTR_H__
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
 
 
 /* ##########################  Core Instruction Access  ######################### */
@@ -31,9 +31,14 @@
   @{
 */
 
-#if defined ( __CC_ARM   ) /*------------------ RealView Compiler ----------------*/
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
 /* ARM armcc specific functions */
 
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
 /** \brief  No Operation
 
     No Operation does nothing. This instruction can be used for code alignment purposes.
@@ -106,15 +111,11 @@
     \param [in]    value  Value to reverse
     \return               Reversed value
  */
-#if (__ARMCC_VERSION < 400677)
-extern uint32_t __REV16(uint32_t value);
-#else  /* (__ARMCC_VERSION >= 400677)  */
-static __INLINE __ASM uint32_t __REV16(uint32_t value)
+static __attribute__((section(".rev16_text"))) __INLINE __ASM uint32_t __REV16(uint32_t value)
 {
   rev16 r0, r0
   bx lr
 }
-#endif /* __ARMCC_VERSION  */ 
 
 
 /** \brief  Reverse byte order in signed short value
@@ -124,15 +125,11 @@
     \param [in]    value  Value to reverse
     \return               Reversed value
  */
-#if (__ARMCC_VERSION < 400677)
-extern int32_t __REVSH(int32_t value);
-#else  /* (__ARMCC_VERSION >= 400677)  */
-static __INLINE __ASM int32_t __REVSH(int32_t value)
+static __attribute__((section(".revsh_text"))) __INLINE __ASM int32_t __REVSH(int32_t value)
 {
   revsh r0, r0
   bx lr
 }
-#endif /* __ARMCC_VERSION  */ 
 
 
 #if       (__CORTEX_M >= 0x03)
@@ -218,11 +215,7 @@
     This function removes the exclusive lock which is created by LDREX.
 
  */
-#if (__ARMCC_VERSION < 400000)
-extern void __CLREX(void);
-#else  /* (__ARMCC_VERSION >= 400000)  */
 #define __CLREX                           __clrex
-#endif /* __ARMCC_VERSION  */ 
 
 
 /** \brief  Signed Saturate
@@ -260,196 +253,13 @@
 
 
 
-#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
 /* IAR iccarm specific functions */
 
-#include <intrinsics.h>                     /* IAR Intrinsics   */
-
-#pragma diag_suppress=Pe940
-
-/** \brief  No Operation
-
-    No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-#define __NOP                           __no_operation
-
-
-/** \brief  Wait For Interrupt
-
-    Wait For Interrupt is a hint instruction that suspends execution
-    until one of a number of events occurs.
- */
-static __INLINE  void __WFI(void)
-{
-  __ASM ("wfi");
-}
-
-
-/** \brief  Wait For Event
-
-    Wait For Event is a hint instruction that permits the processor to enter
-    a low-power state until one of a number of events occurs.
- */
-static __INLINE  void __WFE(void)
-{
-  __ASM ("wfe");
-}
-
-
-/** \brief  Send Event
-
-    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-static __INLINE  void __SEV(void)
-{
-  __ASM ("sev");
-}
-
-
-/* intrinsic     void __ISB(void)            (see intrinsics.h) */
-/* intrinsic     void __DSB(void)            (see intrinsics.h) */
-/* intrinsic     void __DMB(void)            (see intrinsics.h) */
-/* intrinsic uint32_t __REV(uint32_t value)  (see intrinsics.h) */
-/* intrinsic          __SSAT                 (see intrinsics.h) */
-/* intrinsic          __USAT                 (see intrinsics.h) */
-
-
-/** \brief  Reverse byte order (16 bit)
-
-    This function reverses the byte order in two unsigned short values.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-static uint32_t __REV16(uint32_t value)
-{
-  __ASM("rev16 r0, r0");
-}
-
-
-/* intrinsic uint32_t __REVSH(uint32_t value)  (see intrinsics.h */
-
-
-#if       (__CORTEX_M >= 0x03)
-
-/** \brief  Reverse bit order of value
-
-    This function reverses the bit order of the given value.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-static uint32_t __RBIT(uint32_t value)
-{
-  __ASM("rbit r0, r0");
-}
+#include <cmsis_iar.h>
 
 
-/** \brief  LDR Exclusive (8 bit)
-
-    This function performs a exclusive LDR command for 8 bit value.
-
-    \param [in]    ptr  Pointer to data
-    \return             value of type uint8_t at (*ptr)
- */
-static uint8_t __LDREXB(volatile uint8_t *addr)
-{
-  __ASM("ldrexb r0, [r0]");
-}
-
-
-/** \brief  LDR Exclusive (16 bit)
-
-    This function performs a exclusive LDR command for 16 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint16_t at (*ptr)
- */
-static uint16_t __LDREXH(volatile uint16_t *addr)
-{
-  __ASM("ldrexh r0, [r0]");
-}
-
-
-/** \brief  LDR Exclusive (32 bit)
-
-    This function performs a exclusive LDR command for 32 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint32_t at (*ptr)
- */
-/* intrinsic unsigned long __LDREX(unsigned long *)  (see intrinsics.h) */
-static uint32_t __LDREXW(volatile uint32_t *addr)
-{
-  __ASM("ldrex r0, [r0]");
-}
-
-
-/** \brief  STR Exclusive (8 bit)
-
-    This function performs a exclusive STR command for 8 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-static uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
-{
-  __ASM("strexb r0, r0, [r1]");
-}
-
-
-/** \brief  STR Exclusive (16 bit)
-
-    This function performs a exclusive STR command for 16 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-static uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
-{
-  __ASM("strexh r0, r0, [r1]");
-}
-
-
-/** \brief  STR Exclusive (32 bit)
-
-    This function performs a exclusive STR command for 32 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-/* intrinsic unsigned long __STREX(unsigned long, unsigned long)  (see intrinsics.h )*/
-static uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
-{
-  __ASM("strex r0, r0, [r1]");
-}
-
-
-/** \brief  Remove the exclusive lock
-
-    This function removes the exclusive lock which is created by LDREX.
-
- */
-static __INLINE void __CLREX(void)
-{
-  __ASM ("clrex");
-}
-
-/* intrinsic   unsigned char __CLZ( unsigned long )      (see intrinsics.h) */
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-#pragma diag_default=Pe940
-
-
-
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
 /* GNU gcc specific functions */
 
 /** \brief  No Operation
@@ -655,7 +465,7 @@
 {
    uint32_t result;
   
-   __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+   __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
    return(result);
 }
 
@@ -673,7 +483,7 @@
 {
    uint32_t result;
   
-   __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+   __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
    return(result);
 }
 
@@ -691,7 +501,7 @@
 {
    uint32_t result;
   
-   __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+   __ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
    return(result);
 }
 
@@ -759,12 +569,12 @@
 
 
 
-#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
 /* TASKING carm specific functions */
 
 /*
  * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
  * Including the CMSIS ones.
  */
 
@@ -772,4 +582,4 @@
 
 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
 
-#endif /* __CORE_CMINSTR_H__ */
+#endif /* __CORE_CMINSTR_H */

Binary file LPC11U24/GCC_CS/libcapi.a has changed

Binary file LPC11U24/GCC_CS/libmbed.a has changed

Binary file LPC11U24/uARM/capi.ar has changed

Binary file LPC11U24/uARM/cmsis_nvic.o has changed

Binary file LPC11U24/uARM/core_cm0.o has changed

--- a/LPC11U24/uARM/core_cmFunc.h	Fri Jan 06 16:40:24 2012 +0000
+++ b/LPC11U24/uARM/core_cmFunc.h	Tue Jan 10 12:00:50 2012 +0000
@@ -1,11 +1,11 @@
 /**************************************************************************//**
  * @file     core_cmFunc.h
  * @brief    CMSIS Cortex-M Core Function Access Header File
- * @version  V2.01
- * @date     06. December 2010
+ * @version  V3.00
+ * @date     09. December 2011
  *
  * @note
- * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
  *
  * @par
  * ARM Limited (ARM) is supplying this software for use with Cortex-M 
@@ -21,8 +21,9 @@
  *
  ******************************************************************************/
 
-#ifndef __CORE_CMFUNC_H__
-#define __CORE_CMFUNC_H__
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
 
 /* ###########################  Core Function Access  ########################### */
 /** \ingroup  CMSIS_Core_FunctionInterface   
@@ -30,9 +31,13 @@
   @{
  */
 
-#if defined ( __CC_ARM   ) /*------------------ RealView Compiler ----------------*/
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
 /* ARM armcc specific functions */
 
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
 /* intrinsic void __enable_irq();     */
 /* intrinsic void __disable_irq();    */
 
@@ -42,15 +47,11 @@
 
     \return               Control Register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_CONTROL(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_CONTROL(void)
 {
   register uint32_t __regControl         __ASM("control");
   return(__regControl);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Set Control Register
@@ -59,32 +60,24 @@
 
     \param [in]    control  Control Register value to set
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          void __set_CONTROL(uint32_t control);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE void __set_CONTROL(uint32_t control)
 {
   register uint32_t __regControl         __ASM("control");
   __regControl = control;
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
-/** \brief  Get ISPR Register
-
-    This function returns the content of the ISPR Register.
+/** \brief  Get IPSR Register
 
-    \return               ISPR Register value
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_IPSR(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_IPSR(void)
 {
   register uint32_t __regIPSR          __ASM("ipsr");
   return(__regIPSR);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Get APSR Register
@@ -93,15 +86,11 @@
 
     \return               APSR Register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_APSR(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_APSR(void)
 {
   register uint32_t __regAPSR          __ASM("apsr");
   return(__regAPSR);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Get xPSR Register
@@ -110,15 +99,11 @@
 
     \return               xPSR Register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_xPSR(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_xPSR(void)
 {
   register uint32_t __regXPSR          __ASM("xpsr");
   return(__regXPSR);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Get Process Stack Pointer
@@ -127,15 +112,11 @@
 
     \return               PSP Register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_PSP(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_PSP(void)
 {
   register uint32_t __regProcessStackPointer  __ASM("psp");
   return(__regProcessStackPointer);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Set Process Stack Pointer
@@ -144,15 +125,11 @@
 
     \param [in]    topOfProcStack  Process Stack Pointer value to set
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          void __set_PSP(uint32_t topOfProcStack);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE void __set_PSP(uint32_t topOfProcStack)
 {
   register uint32_t __regProcessStackPointer  __ASM("psp");
   __regProcessStackPointer = topOfProcStack;
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Get Main Stack Pointer
@@ -161,15 +138,11 @@
 
     \return               MSP Register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_MSP(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_MSP(void)
 {
   register uint32_t __regMainStackPointer     __ASM("msp");
   return(__regMainStackPointer);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Set Main Stack Pointer
@@ -178,15 +151,11 @@
 
     \param [in]    topOfMainStack  Main Stack Pointer value to set
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          void __set_MSP(uint32_t topOfMainStack);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE void __set_MSP(uint32_t topOfMainStack)
 {
   register uint32_t __regMainStackPointer     __ASM("msp");
   __regMainStackPointer = topOfMainStack;
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Get Priority Mask
@@ -195,15 +164,11 @@
 
     \return               Priority Mask value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_PRIMASK(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_PRIMASK(void)
 {
   register uint32_t __regPriMask         __ASM("primask");
   return(__regPriMask);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Set Priority Mask
@@ -212,15 +177,11 @@
 
     \param [in]    priMask  Priority Mask
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          void __set_PRIMASK(uint32_t priMask);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE void __set_PRIMASK(uint32_t priMask)
 {
   register uint32_t __regPriMask         __ASM("primask");
   __regPriMask = (priMask);
 }
-#endif /*  __ARMCC_VERSION  */ 
  
 
 #if       (__CORTEX_M >= 0x03)
@@ -247,15 +208,11 @@
 
     \return               Base Priority register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_BASEPRI(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t  __get_BASEPRI(void)
 {
   register uint32_t __regBasePri         __ASM("basepri");
   return(__regBasePri);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Set Base Priority
@@ -264,15 +221,11 @@
 
     \param [in]    basePri  Base Priority value to set
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          void __set_BASEPRI(uint32_t basePri);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE void __set_BASEPRI(uint32_t basePri)
 {
   register uint32_t __regBasePri         __ASM("basepri");
   __regBasePri = (basePri & 0xff);
 }
-#endif /*  __ARMCC_VERSION  */ 
  
 
 /** \brief  Get Fault Mask
@@ -281,15 +234,11 @@
 
     \return               Fault Mask register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_FAULTMASK(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_FAULTMASK(void)
 {
   register uint32_t __regFaultMask       __ASM("faultmask");
   return(__regFaultMask);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Set Fault Mask
@@ -298,15 +247,11 @@
 
     \param [in]    faultMask  Fault Mask value to set
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          void __set_FAULTMASK(uint32_t faultMask);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE void __set_FAULTMASK(uint32_t faultMask)
 {
   register uint32_t __regFaultMask       __ASM("faultmask");
-  __regFaultMask = (faultMask & 1);
+  __regFaultMask = (faultMask & (uint32_t)1);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 #endif /* (__CORTEX_M >= 0x03) */
 
@@ -321,7 +266,7 @@
  */
 static __INLINE uint32_t __get_FPSCR(void)
 {
-#if (__FPU_PRESENT == 1)
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
   register uint32_t __regfpscr         __ASM("fpscr");
   return(__regfpscr);
 #else
@@ -338,7 +283,7 @@
  */
 static __INLINE void __set_FPSCR(uint32_t fpscr)
 {
-#if (__FPU_PRESENT == 1)
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
   register uint32_t __regfpscr         __ASM("fpscr");
   __regfpscr = (fpscr);
 #endif
@@ -347,192 +292,12 @@
 #endif /* (__CORTEX_M == 0x04) */
 
 
- #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
 /* IAR iccarm specific functions */
 
-#if defined (__ICCARM__)
-  #include <intrinsics.h>                     /* IAR Intrinsics   */
-#endif
-
-#pragma diag_suppress=Pe940
-
-/** \brief  Enable IRQ Interrupts
-
-  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
-  Can only be executed in Privileged modes.
- */
-#define __enable_irq                              __enable_interrupt
-
-
-/** \brief  Disable IRQ Interrupts
-
-  This function disables IRQ interrupts by setting the I-bit in the CPSR.
-  Can only be executed in Privileged modes.
- */
-#define __disable_irq                             __disable_interrupt
-
-
-/* intrinsic unsigned long __get_CONTROL( void ); (see intrinsic.h) */
-/* intrinsic void __set_CONTROL( unsigned long ); (see intrinsic.h) */
-
-
-/** \brief  Get ISPR Register
-
-    This function returns the content of the ISPR Register.
-
-    \return               ISPR Register value
- */
-static uint32_t __get_IPSR(void)
-{
-  __ASM("mrs r0, ipsr");
-}
-
-
-/** \brief  Get APSR Register
-
-    This function returns the content of the APSR Register.
-
-    \return               APSR Register value
- */
-static uint32_t __get_APSR(void)
-{
-  __ASM("mrs r0, apsr");
-}
-
-
-/** \brief  Get xPSR Register
-
-    This function returns the content of the xPSR Register.
-
-    \return               xPSR Register value
- */
-static uint32_t __get_xPSR(void)
-{
-  __ASM("mrs r0, psr");           // assembler does not know "xpsr"
-}
-
-
-/** \brief  Get Process Stack Pointer
-
-    This function returns the current value of the Process Stack Pointer (PSP).
-
-    \return               PSP Register value
- */
-static uint32_t __get_PSP(void)
-{
-  __ASM("mrs r0, psp");
-}
- 
-
-/** \brief  Set Process Stack Pointer
-
-    This function assigns the given value to the Process Stack Pointer (PSP).
-
-    \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-static void __set_PSP(uint32_t topOfProcStack)
-{
-  __ASM("msr psp, r0");
-}
-
-
-/** \brief  Get Main Stack Pointer
-
-    This function returns the current value of the Main Stack Pointer (MSP).
+#include <cmsis_iar.h>
 
-    \return               MSP Register value
- */
-static uint32_t __get_MSP(void)
-{
-  __ASM("mrs r0, msp");
-}
- 
-
-/** \brief  Set Main Stack Pointer
-
-    This function assigns the given value to the Main Stack Pointer (MSP).
-
-    \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-static void __set_MSP(uint32_t topOfMainStack)
-{
-  __ASM("msr msp, r0");
-}
- 
-
-/* intrinsic unsigned long __get_PRIMASK( void ); (see intrinsic.h) */
-/* intrinsic void __set_PRIMASK( unsigned long ); (see intrinsic.h) */
- 
-
-#if       (__CORTEX_M >= 0x03)
-
-/** \brief  Enable FIQ
-
-    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-static __INLINE void __enable_fault_irq(void)
-{
-  __ASM ("cpsie f");
-}
-
-
-/** \brief  Disable FIQ
-
-    This function disables FIQ interrupts by setting the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-static __INLINE void __disable_fault_irq(void)
-{
-  __ASM ("cpsid f");
-}
-
-
-/* intrinsic unsigned long __get_BASEPRI( void );   (see intrinsic.h) */
-/* intrinsic void __set_BASEPRI( unsigned long );   (see intrinsic.h) */
-/* intrinsic unsigned long __get_FAULTMASK( void ); (see intrinsic.h) */
-/* intrinsic void __set_FAULTMASK(unsigned long);   (see intrinsic.h) */
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-#if       (__CORTEX_M == 0x04)
-
-/** \brief  Get FPSCR
-
-    This function returns the current value of the Floating Point Status/Control register.
-
-    \return               Floating Point Status/Control register value
- */
-static uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1)
-  __ASM("vmrs r0, fpscr"); 
-#else
-  return(0);
-#endif
-}
-
-
-/** \brief  Set FPSCR
-
-    This function assigns the given value to the Floating Point Status/Control register.
-
-    \param [in]    fpscr  Floating Point Status/Control value to set
- */
-static void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1)
-  __ASM("vmsr fpscr, r0");
-#endif
-}
-
-#endif /* (__CORTEX_M == 0x04) */
-
-#pragma diag_default=Pe940
-
-
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
 /* GNU gcc specific functions */
 
 /** \brief  Enable IRQ Interrupts
@@ -584,11 +349,11 @@
 }
 
 
-/** \brief  Get ISPR Register
+/** \brief  Get IPSR Register
 
-    This function returns the content of the ISPR Register.
+    This function returns the content of the IPSR Register.
 
-    \return               ISPR Register value
+    \return               IPSR Register value
  */
 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void)
 {
@@ -800,10 +565,10 @@
  */
 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void)
 {
-#if (__FPU_PRESENT == 1)
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
   uint32_t result;
 
-  __ASM volatile ("MRS %0, fpscr" : "=r" (result) );
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
   return(result);
 #else
    return(0);
@@ -819,15 +584,15 @@
  */
 __attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr)
 {
-#if (__FPU_PRESENT == 1)
-  __ASM volatile ("MSR fpscr, %0" : : "r" (fpscr) );
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );
 #endif
 }
 
 #endif /* (__CORTEX_M == 0x04) */
 
 
-#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
 /* TASKING carm specific functions */
 
 /*
@@ -841,4 +606,4 @@
 /*@} end of CMSIS_Core_RegAccFunctions */
 
 
-#endif /* __CORE_CMFUNC_H__ */
+#endif /* __CORE_CMFUNC_H */

--- a/LPC11U24/uARM/core_cmInstr.h	Fri Jan 06 16:40:24 2012 +0000
+++ b/LPC11U24/uARM/core_cmInstr.h	Tue Jan 10 12:00:50 2012 +0000
@@ -1,11 +1,11 @@
 /**************************************************************************//**
  * @file     core_cmInstr.h
  * @brief    CMSIS Cortex-M Core Instruction Access Header File
- * @version  V2.01
- * @date     06. December 2010
+ * @version  V3.00
+ * @date     09. December 2011
  *
  * @note
- * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
  *
  * @par
  * ARM Limited (ARM) is supplying this software for use with Cortex-M 
@@ -21,8 +21,8 @@
  *
  ******************************************************************************/
 
-#ifndef __CORE_CMINSTR_H__
-#define __CORE_CMINSTR_H__
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
 
 
 /* ##########################  Core Instruction Access  ######################### */
@@ -31,9 +31,14 @@
   @{
 */
 
-#if defined ( __CC_ARM   ) /*------------------ RealView Compiler ----------------*/
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
 /* ARM armcc specific functions */
 
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
 /** \brief  No Operation
 
     No Operation does nothing. This instruction can be used for code alignment purposes.
@@ -106,15 +111,11 @@
     \param [in]    value  Value to reverse
     \return               Reversed value
  */
-#if (__ARMCC_VERSION < 400677)
-extern uint32_t __REV16(uint32_t value);
-#else  /* (__ARMCC_VERSION >= 400677)  */
-static __INLINE __ASM uint32_t __REV16(uint32_t value)
+static __attribute__((section(".rev16_text"))) __INLINE __ASM uint32_t __REV16(uint32_t value)
 {
   rev16 r0, r0
   bx lr
 }
-#endif /* __ARMCC_VERSION  */ 
 
 
 /** \brief  Reverse byte order in signed short value
@@ -124,15 +125,11 @@
     \param [in]    value  Value to reverse
     \return               Reversed value
  */
-#if (__ARMCC_VERSION < 400677)
-extern int32_t __REVSH(int32_t value);
-#else  /* (__ARMCC_VERSION >= 400677)  */
-static __INLINE __ASM int32_t __REVSH(int32_t value)
+static __attribute__((section(".revsh_text"))) __INLINE __ASM int32_t __REVSH(int32_t value)
 {
   revsh r0, r0
   bx lr
 }
-#endif /* __ARMCC_VERSION  */ 
 
 
 #if       (__CORTEX_M >= 0x03)
@@ -218,11 +215,7 @@
     This function removes the exclusive lock which is created by LDREX.
 
  */
-#if (__ARMCC_VERSION < 400000)
-extern void __CLREX(void);
-#else  /* (__ARMCC_VERSION >= 400000)  */
 #define __CLREX                           __clrex
-#endif /* __ARMCC_VERSION  */ 
 
 
 /** \brief  Signed Saturate
@@ -260,196 +253,13 @@
 
 
 
-#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
 /* IAR iccarm specific functions */
 
-#include <intrinsics.h>                     /* IAR Intrinsics   */
-
-#pragma diag_suppress=Pe940
-
-/** \brief  No Operation
-
-    No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-#define __NOP                           __no_operation
-
-
-/** \brief  Wait For Interrupt
-
-    Wait For Interrupt is a hint instruction that suspends execution
-    until one of a number of events occurs.
- */
-static __INLINE  void __WFI(void)
-{
-  __ASM ("wfi");
-}
-
-
-/** \brief  Wait For Event
-
-    Wait For Event is a hint instruction that permits the processor to enter
-    a low-power state until one of a number of events occurs.
- */
-static __INLINE  void __WFE(void)
-{
-  __ASM ("wfe");
-}
-
-
-/** \brief  Send Event
-
-    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-static __INLINE  void __SEV(void)
-{
-  __ASM ("sev");
-}
-
-
-/* intrinsic     void __ISB(void)            (see intrinsics.h) */
-/* intrinsic     void __DSB(void)            (see intrinsics.h) */
-/* intrinsic     void __DMB(void)            (see intrinsics.h) */
-/* intrinsic uint32_t __REV(uint32_t value)  (see intrinsics.h) */
-/* intrinsic          __SSAT                 (see intrinsics.h) */
-/* intrinsic          __USAT                 (see intrinsics.h) */
-
-
-/** \brief  Reverse byte order (16 bit)
-
-    This function reverses the byte order in two unsigned short values.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-static uint32_t __REV16(uint32_t value)
-{
-  __ASM("rev16 r0, r0");
-}
-
-
-/* intrinsic uint32_t __REVSH(uint32_t value)  (see intrinsics.h */
-
-
-#if       (__CORTEX_M >= 0x03)
-
-/** \brief  Reverse bit order of value
-
-    This function reverses the bit order of the given value.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-static uint32_t __RBIT(uint32_t value)
-{
-  __ASM("rbit r0, r0");
-}
+#include <cmsis_iar.h>
 
 
-/** \brief  LDR Exclusive (8 bit)
-
-    This function performs a exclusive LDR command for 8 bit value.
-
-    \param [in]    ptr  Pointer to data
-    \return             value of type uint8_t at (*ptr)
- */
-static uint8_t __LDREXB(volatile uint8_t *addr)
-{
-  __ASM("ldrexb r0, [r0]");
-}
-
-
-/** \brief  LDR Exclusive (16 bit)
-
-    This function performs a exclusive LDR command for 16 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint16_t at (*ptr)
- */
-static uint16_t __LDREXH(volatile uint16_t *addr)
-{
-  __ASM("ldrexh r0, [r0]");
-}
-
-
-/** \brief  LDR Exclusive (32 bit)
-
-    This function performs a exclusive LDR command for 32 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint32_t at (*ptr)
- */
-/* intrinsic unsigned long __LDREX(unsigned long *)  (see intrinsics.h) */
-static uint32_t __LDREXW(volatile uint32_t *addr)
-{
-  __ASM("ldrex r0, [r0]");
-}
-
-
-/** \brief  STR Exclusive (8 bit)
-
-    This function performs a exclusive STR command for 8 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-static uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
-{
-  __ASM("strexb r0, r0, [r1]");
-}
-
-
-/** \brief  STR Exclusive (16 bit)
-
-    This function performs a exclusive STR command for 16 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-static uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
-{
-  __ASM("strexh r0, r0, [r1]");
-}
-
-
-/** \brief  STR Exclusive (32 bit)
-
-    This function performs a exclusive STR command for 32 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-/* intrinsic unsigned long __STREX(unsigned long, unsigned long)  (see intrinsics.h )*/
-static uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
-{
-  __ASM("strex r0, r0, [r1]");
-}
-
-
-/** \brief  Remove the exclusive lock
-
-    This function removes the exclusive lock which is created by LDREX.
-
- */
-static __INLINE void __CLREX(void)
-{
-  __ASM ("clrex");
-}
-
-/* intrinsic   unsigned char __CLZ( unsigned long )      (see intrinsics.h) */
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-#pragma diag_default=Pe940
-
-
-
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
 /* GNU gcc specific functions */
 
 /** \brief  No Operation
@@ -655,7 +465,7 @@
 {
    uint32_t result;
   
-   __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+   __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
    return(result);
 }
 
@@ -673,7 +483,7 @@
 {
    uint32_t result;
   
-   __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+   __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
    return(result);
 }
 
@@ -691,7 +501,7 @@
 {
    uint32_t result;
   
-   __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+   __ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
    return(result);
 }
 
@@ -759,12 +569,12 @@
 
 
 
-#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
 /* TASKING carm specific functions */
 
 /*
  * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
  * Including the CMSIS ones.
  */
 
@@ -772,4 +582,4 @@
 
 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
 
-#endif /* __CORE_CMINSTR_H__ */
+#endif /* __CORE_CMINSTR_H */

Binary file LPC11U24/uARM/mbed.ar has changed

Binary file LPC11U24/uARM/sys.o has changed

Binary file LPC11U24/uARM/system_LPC11Uxx.o has changed

Binary file LPC1768/ARM/capi.ar has changed

Binary file LPC1768/ARM/cmsis_nvic.o has changed

--- a/LPC1768/ARM/core_cm3.h	Fri Jan 06 16:40:24 2012 +0000
+++ b/LPC1768/ARM/core_cm3.h	Tue Jan 10 12:00:50 2012 +0000
@@ -1,16 +1,16 @@
 /**************************************************************************//**
  * @file     core_cm3.h
  * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
- * @version  V2.01
- * @date     06. December 2010
+ * @version  V3.00
+ * @date     09. December 2011
  *
  * @note
- * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
  *
  * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M 
- * processor based microcontrollers.  This file can be freely distributed 
- * within development tools that are supporting such ARM based processors. 
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers.  This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
  *
  * @par
  * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
@@ -20,106 +20,144 @@
  * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
  *
  ******************************************************************************/
-#if defined ( __ICCARM__ )                   
+#if defined ( __ICCARM__ )
  #pragma system_include  /* treat file as system include file for MISRA check */
 #endif
 
 #ifdef __cplusplus
  extern "C" {
-#endif 
+#endif
 
 #ifndef __CORE_CM3_H_GENERIC
 #define __CORE_CM3_H_GENERIC
 
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+  
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'. 
 
-/** \mainpage CMSIS Cortex-M3
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
    
-  This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer.
-  It consists of:
- 
-     - Cortex-M Core Register Definitions
-     - Cortex-M functions
-     - Cortex-M instructions
- 
-  The CMSIS Cortex-M3 Core Peripheral Access Layer contains C and assembly functions that ease 
-  access to the Cortex-M Core
- */ 
-
-/** \defgroup CMSIS_LintCinfiguration CMSIS Lint Configuration
-  List of Lint messages which will be suppressed and not shown:
-    - not yet checked
-  .
-  Note:  To re-enable a Message, insert a space before 'lint' *
- 
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code. 
  */
 
 
 /*******************************************************************************
  *                 CMSIS definitions
  ******************************************************************************/
-/** \defgroup CMSIS_core_definitions CMSIS Core Definitions
-  This file defines all structures and symbols for CMSIS core:
-   - CMSIS version number
-   - Cortex-M core 
-   - Cortex-M core Revision Number
+/** \ingroup Cortex_M3
   @{
  */
 
 /*  CMSIS CM3 definitions */
-#define __CM3_CMSIS_VERSION_MAIN  (0x02)                                                       /*!< [31:16] CMSIS HAL main version */
-#define __CM3_CMSIS_VERSION_SUB   (0x00)                                                       /*!< [15:0]  CMSIS HAL sub version  */
-#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number       */
+#define __CM3_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM3_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | \
+                                    __CM3_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
 
-#define __CORTEX_M                (0x03)                                                       /*!< Cortex core                    */
+#define __CORTEX_M                (0x03)                                   /*!< Cortex-M Core                    */
 
 
-#if defined ( __CC_ARM   )
+#if   defined ( __CC_ARM )
   #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
   #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
 
 #elif defined ( __ICCARM__ )
   #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */
-  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
+  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
 
-#elif defined   (  __GNUC__  )
+#elif defined ( __GNUC__ )
   #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
   #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
 
-#elif defined   (  __TASKING__  )
+#elif defined ( __TASKING__ )
   #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
   #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
 
 #endif
 
-#include <stdint.h>                      /*!< standard types definitions                      */
-#include "core_cmInstr.h"                /*!< Core Instruction Access                         */
-#include "core_cmFunc.h"                 /*!< Core Function Access                            */
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+    /* add preprocessor checks */
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
 
 #endif /* __CORE_CM3_H_GENERIC */
 
-
 #ifndef __CMSIS_GENERIC
 
 #ifndef __CORE_CM3_H_DEPENDANT
 #define __CORE_CM3_H_DEPENDANT
 
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM3_REV
+    #define __CM3_REV               0x0200
+    #warning "__CM3_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          4
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
 /* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+ 
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
 #ifdef __cplusplus
-  #define     __I     volatile           /*!< defines 'read only' permissions                 */
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
 #else
-  #define     __I     volatile const     /*!< defines 'read only' permissions                 */
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
 #endif
-#define     __O     volatile             /*!< defines 'write only' permissions                */
-#define     __IO    volatile             /*!< defines 'read / write' permissions              */
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
 
-/*@} end of group CMSIS_core_definitions */
+/*@} end of group Cortex_M3 */
 
 
 
 /*******************************************************************************
  *                 Register Abstraction
- ******************************************************************************/
-/** \defgroup CMSIS_core_register CMSIS Core Register
   Core Register contain:
   - Core Register
   - Core NVIC Register
@@ -127,11 +165,14 @@
   - Core SysTick Register
   - Core Debug Register
   - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
 */
 
-/** \ingroup  CMSIS_core_register   
-    \defgroup CMSIS_CORE CMSIS Core
-  Type definitions for the Cortex-M Core Registers
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
   @{
  */
 
@@ -154,7 +195,7 @@
     uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
     uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
   } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */ 
+  uint32_t w;                            /*!< Type      used for word access                  */
 } APSR_Type;
 
 
@@ -214,9 +255,9 @@
 /*@} end of group CMSIS_CORE */
 
 
-/** \ingroup  CMSIS_core_register   
-    \defgroup CMSIS_NVIC CMSIS NVIC
-  Type definitions for the Cortex-M NVIC Registers
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
   @{
  */
 
@@ -225,26 +266,30 @@
 typedef struct
 {
   __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
-       uint32_t RESERVED0[24];                                   
+       uint32_t RESERVED0[24];
   __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
-       uint32_t RSERVED1[24];                                    
+       uint32_t RSERVED1[24];
   __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
-       uint32_t RESERVED2[24];                                   
+       uint32_t RESERVED2[24];
   __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
-       uint32_t RESERVED3[24];                                   
+       uint32_t RESERVED3[24];
   __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
-       uint32_t RESERVED4[56];                                   
+       uint32_t RESERVED4[56];
   __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
-       uint32_t RESERVED5[644];                                  
+       uint32_t RESERVED5[644];
   __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
-}  NVIC_Type;                                               
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
 
 /*@} end of group CMSIS_NVIC */
 
 
-/** \ingroup  CMSIS_core_register   
-    \defgroup CMSIS_SCB CMSIS SCB
-  Type definitions for the Cortex-M System Control Block Registers
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
   @{
  */
 
@@ -252,26 +297,28 @@
  */
 typedef struct
 {
-  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPU ID Base Register                                  */
-  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control State Register                      */
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
   __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
-  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt / Reset Control Register        */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
   __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
   __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
   __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
   __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
   __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
-  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  Hard Fault Status Register                            */
+  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
   __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
-  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  Mem Manage Address Register                           */
-  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  Bus Fault Address Register                            */
+  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
   __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
   __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
   __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
   __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
   __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
-  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  ISA Feature Register                                  */
-} SCB_Type;                                                
+  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+       uint32_t RESERVED0[5];
+  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+} SCB_Type;
 
 /* SCB CPUID Register Definitions */
 #define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
@@ -280,6 +327,9 @@
 #define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
 #define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
 
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
 #define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
 #define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
 
@@ -317,12 +367,17 @@
 #define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
 #define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
 
-/* SCB Interrupt Control State Register Definitions */
+/* SCB Vector Table Offset Register Definitions */
+#if (__CM3_REV < 0x0201)                   /* core r2p1 */
 #define SCB_VTOR_TBLBASE_Pos               29                                             /*!< SCB VTOR: TBLBASE Position */
 #define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
 
 #define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
 #define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+#endif
 
 /* SCB Application Interrupt and Reset Control Register Definitions */
 #define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
@@ -408,7 +463,7 @@
 
 #define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
 #define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
-                                     
+
 #define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
 #define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
 
@@ -457,9 +512,46 @@
 /*@} end of group CMSIS_SCB */
 
 
-/** \ingroup  CMSIS_core_register   
-    \defgroup CMSIS_SysTick CMSIS SysTick
-  Type definitions for the Cortex-M System Timer Registers
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register      */
+#else
+       uint32_t RESERVED1[1];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
   @{
  */
 
@@ -507,9 +599,9 @@
 /*@} end of group CMSIS_SysTick */
 
 
-/** \ingroup  CMSIS_core_register   
-    \defgroup CMSIS_ITM CMSIS ITM
-  Type definitions for the Cortex-M Instrumentation Trace Macrocell (ITM)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
   @{
  */
 
@@ -517,134 +609,59 @@
  */
 typedef struct
 {
-  __O  union  
+  __O  union
   {
     __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
     __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
     __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
   }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
-       uint32_t RESERVED0[864];                                 
-  __IO uint32_t TER;                     /*!< Offset:       (R/W)  ITM Trace Enable Register                 */
-       uint32_t RESERVED1[15];                                  
-  __IO uint32_t TPR;                     /*!< Offset:       (R/W)  ITM Trace Privilege Register              */
-       uint32_t RESERVED2[15];                                  
-  __IO uint32_t TCR;                     /*!< Offset:       (R/W)  ITM Trace Control Register                */
-       uint32_t RESERVED3[29];                                  
-  __IO uint32_t IWR;                     /*!< Offset:       (R/W)  ITM Integration Write Register            */
-  __IO uint32_t IRR;                     /*!< Offset:       (R/W)  ITM Integration Read Register             */
-  __IO uint32_t IMCR;                    /*!< Offset:       (R/W)  ITM Integration Mode Control Register     */
-       uint32_t RESERVED4[43];                                  
-  __IO uint32_t LAR;                     /*!< Offset:       (R/W)  ITM Lock Access Register                  */
-  __IO uint32_t LSR;                     /*!< Offset:       (R/W)  ITM Lock Status Register                  */
-       uint32_t RESERVED5[6];                                   
-  __I  uint32_t PID4;                    /*!< Offset:       (R/ )  ITM Peripheral Identification Register #4 */
-  __I  uint32_t PID5;                    /*!< Offset:       (R/ )  ITM Peripheral Identification Register #5 */
-  __I  uint32_t PID6;                    /*!< Offset:       (R/ )  ITM Peripheral Identification Register #6 */
-  __I  uint32_t PID7;                    /*!< Offset:       (R/ )  ITM Peripheral Identification Register #7 */
-  __I  uint32_t PID0;                    /*!< Offset:       (R/ )  ITM Peripheral Identification Register #0 */
-  __I  uint32_t PID1;                    /*!< Offset:       (R/ )  ITM Peripheral Identification Register #1 */
-  __I  uint32_t PID2;                    /*!< Offset:       (R/ )  ITM Peripheral Identification Register #2 */
-  __I  uint32_t PID3;                    /*!< Offset:       (R/ )  ITM Peripheral Identification Register #3 */
-  __I  uint32_t CID0;                    /*!< Offset:       (R/ )  ITM Component  Identification Register #0 */
-  __I  uint32_t CID1;                    /*!< Offset:       (R/ )  ITM Component  Identification Register #1 */
-  __I  uint32_t CID2;                    /*!< Offset:       (R/ )  ITM Component  Identification Register #2 */
-  __I  uint32_t CID3;                    /*!< Offset:       (R/ )  ITM Component  Identification Register #3 */
-} ITM_Type;                                                
+       uint32_t RESERVED0[864];
+  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+       uint32_t RESERVED1[15];
+  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+       uint32_t RESERVED2[15];
+  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+} ITM_Type;
 
 /* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
+#define ITM_TPR_PRIVMASK_Pos                0                                          /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)             /*!< ITM TPR: PRIVMASK Mask */
 
 /* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+#define ITM_TCR_BUSY_Pos                   23                                          /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                   /*!< ITM TCR: BUSY Mask */
 
-#define ITM_TCR_ATBID_Pos                  16                                             /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_ATBID_Msk                  (0x7FUL << ITM_TCR_ATBID_Pos)                  /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+#define ITM_TCR_TraceBusID_Pos             16                                          /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)          /*!< ITM TCR: ATBID Mask */
 
-#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+#define ITM_TCR_GTSFREQ_Pos                10                                          /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                /*!< ITM TCR: Global timestamp frequency Mask */
 
-#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+#define ITM_TCR_TSPrescale_Pos              8                                          /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)             /*!< ITM TCR: TSPrescale Mask */
 
-#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
+#define ITM_TCR_SWOENA_Pos                  4                                          /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                 /*!< ITM TCR: SWOENA Mask */
 
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
+#define ITM_TCR_TXENA_Pos                   3                                          /*!< ITM TCR: TXENA Position */
+#define ITM_TCR_TXENA_Msk                  (1UL << ITM_TCR_TXENA_Pos)                  /*!< ITM TCR: TXENA Mask */
 
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
+#define ITM_TCR_SYNCENA_Pos                 2                                          /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                /*!< ITM TCR: SYNCENA Mask */
 
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+#define ITM_TCR_TSENA_Pos                   1                                          /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                  /*!< ITM TCR: TSENA Mask */
 
-#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
+#define ITM_TCR_ITMENA_Pos                  0                                          /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                 /*!< ITM TCR: ITM Enable bit Mask */
 
 /*@}*/ /* end of group CMSIS_ITM */
 
 
-/** \ingroup  CMSIS_core_register   
-    \defgroup CMSIS_InterruptType CMSIS Interrupt Type
-  Type definitions for the Cortex-M Interrupt Type Register
-  @{
- */
-
-/** \brief  Structure type to access the Interrupt Type Register.
- */
-typedef struct
-{
-       uint32_t RESERVED0;
-  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Control Type Register */
-#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
-  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register      */
-#else
-       uint32_t RESERVED1;
-#endif
-} InterruptType_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define IntType_ICTR_INTLINESNUM_Pos  0                                                   /*!< InterruptType ICTR: INTLINESNUM Position */
-#define IntType_ICTR_INTLINESNUM_Msk (0x1FUL << IntType_ICTR_INTLINESNUM_Pos)             /*!< InterruptType ICTR: INTLINESNUM Mask */
-
-/* Auxiliary Control Register Definitions */
-#define IntType_ACTLR_DISFOLD_Pos     2                                                   /*!< InterruptType ACTLR: DISFOLD Position */
-#define IntType_ACTLR_DISFOLD_Msk    (1UL << IntType_ACTLR_DISFOLD_Pos)                   /*!< InterruptType ACTLR: DISFOLD Mask */
-
-#define IntType_ACTLR_DISDEFWBUF_Pos  1                                                   /*!< InterruptType ACTLR: DISDEFWBUF Position */
-#define IntType_ACTLR_DISDEFWBUF_Msk (1UL << IntType_ACTLR_DISDEFWBUF_Pos)                /*!< InterruptType ACTLR: DISDEFWBUF Mask */
-
-#define IntType_ACTLR_DISMCYCINT_Pos  0                                                   /*!< InterruptType ACTLR: DISMCYCINT Position */
-#define IntType_ACTLR_DISMCYCINT_Msk (1UL << IntType_ACTLR_DISMCYCINT_Pos)                /*!< InterruptType ACTLR: DISMCYCINT Mask */
-
-/*@}*/ /* end of group CMSIS_InterruptType */
-
-
 #if (__MPU_PRESENT == 1)
-/** \ingroup  CMSIS_core_register   
-    \defgroup CMSIS_MPU CMSIS MPU
-  Type definitions for the Cortex-M Memory Protection Unit (MPU)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
   @{
  */
 
@@ -663,7 +680,7 @@
   __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
   __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
   __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;                                                
+} MPU_Type;
 
 /* MPU Type Register */
 #define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
@@ -700,23 +717,8 @@
 #define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
 
 /* MPU Region Attribute and Size Register */
-#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: XN Position */
-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: XN Mask */
-
-#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: AP Position */
-#define MPU_RASR_AP_Msk                    (7UL << MPU_RASR_AP_Pos)                       /*!< MPU RASR: AP Mask */
-
-#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: TEX Position */
-#define MPU_RASR_TEX_Msk                   (7UL << MPU_RASR_TEX_Pos)                      /*!< MPU RASR: TEX Mask */
-
-#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: Shareable bit Position */
-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: Shareable bit Mask */
-
-#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: Cacheable bit Position */
-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: Cacheable bit Mask */
-
-#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: Bufferable bit Position */
-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: Bufferable bit Mask */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
 
 #define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
 #define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
@@ -724,16 +726,16 @@
 #define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
 #define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
 
-#define MPU_RASR_ENA_Pos                     0                                            /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENA_Msk                    (0x1UL << MPU_RASR_ENA_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
 
 /*@} end of group CMSIS_MPU */
 #endif
 
 
-/** \ingroup  CMSIS_core_register   
-    \defgroup CMSIS_CoreDebug CMSIS Core Debug
-  Type definitions for the Cortex-M Core Debug Registers
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Type definitions for the Core Debug Registers
   @{
  */
 
@@ -834,28 +836,30 @@
 /*@} end of group CMSIS_CoreDebug */
 
 
-/** \ingroup  CMSIS_core_register   
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
   @{
  */
- 
+
 /* Memory mapping of Cortex-M3 Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
-#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                  */
-#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address           */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
 
-#define InterruptType       ((InterruptType_Type *) SCS_BASE)         /*!< Interrupt Type Register           */
-#define SCB                 ((SCB_Type *)           SCB_BASE)         /*!< SCB configuration struct          */
-#define SysTick             ((SysTick_Type *)       SysTick_BASE)     /*!< SysTick configuration struct      */
-#define NVIC                ((NVIC_Type *)          NVIC_BASE)        /*!< NVIC configuration struct         */
-#define ITM                 ((ITM_Type *)           ITM_BASE)         /*!< ITM configuration struct          */
-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct   */
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
 
 #if (__MPU_PRESENT == 1)
-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit            */
-  #define MPU               ((MPU_Type*)            MPU_BASE)         /*!< Memory Protection Unit            */
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
 #endif
 
 /*@} */
@@ -864,42 +868,43 @@
 
 /*******************************************************************************
  *                Hardware Abstraction Layer
- ******************************************************************************/
-/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface
   Core Function Interface contains:
   - Core NVIC Functions
   - Core SysTick Functions
   - Core Debug Functions
   - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
 */
 
 
 
 /* ##########################   NVIC functions  #################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface   
-    \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions
-  @{
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
  */
 
 /** \brief  Set Priority Grouping
 
-  This function sets the priority grouping field using the required unlock sequence.
+  The function sets the priority grouping field using the required unlock sequence.
   The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
   Only values from 0..7 are used.
   In case of a conflict between priority grouping and available
-  priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
 
-    \param [in]      PriorityGroup  Priority grouping field
+    \param [in]      PriorityGroup  Priority grouping field.
  */
 static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
 {
   uint32_t reg_value;
-  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);                         /* only values 0..7 are used          */
-  
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
+
   reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
   reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
-  reg_value  =  (reg_value                       |
-                (0x5FA << SCB_AIRCR_VECTKEY_Pos) | 
+  reg_value  =  (reg_value                                 |
+                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
                 (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
   SCB->AIRCR =  reg_value;
 }
@@ -907,10 +912,9 @@
 
 /** \brief  Get Priority Grouping
 
-  This function gets the priority grouping from NVIC Interrupt Controller.
-  Priority grouping is SCB->AIRCR [10:8] PRIGROUP field.
+  The function reads the priority grouping field from the NVIC Interrupt Controller.
 
-    \return                Priority grouping field
+    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
  */
 static __INLINE uint32_t NVIC_GetPriorityGrouping(void)
 {
@@ -920,10 +924,9 @@
 
 /** \brief  Enable External Interrupt
 
-    This function enables a device specific interupt in the NVIC interrupt controller.
-    The interrupt number cannot be a negative value. 
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
 
-    \param [in]      IRQn  Number of the external interrupt to enable
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
  */
 static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
 {
@@ -933,10 +936,9 @@
 
 /** \brief  Disable External Interrupt
 
-    This function disables a device specific interupt in the NVIC interrupt controller.
-    The interrupt number cannot be a negative value. 
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
 
-    \param [in]      IRQn  Number of the external interrupt to disable
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
  */
 static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
 {
@@ -946,12 +948,13 @@
 
 /** \brief  Get Pending Interrupt
 
-    This function reads the pending register in the NVIC and returns the pending bit
-    for the specified interrupt. 
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
 
-    \param [in]      IRQn  Number of the interrupt for get pending
-    \return             0  Interrupt status is not pending
-    \return             1  Interrupt status is pending
+    \param [in]      IRQn  Interrupt number.
+    
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
  */
 static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
 {
@@ -961,10 +964,9 @@
 
 /** \brief  Set Pending Interrupt
 
-    This function sets the pending bit for the specified interrupt. 
-    The interrupt number cannot be a negative value.
+    The function sets the pending bit of an external interrupt.
 
-    \param [in]      IRQn  Number of the interrupt for set pending
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
  */
 static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
 {
@@ -974,10 +976,9 @@
 
 /** \brief  Clear Pending Interrupt
 
-    This function clears the pending bit for the specified interrupt. 
-    The interrupt number cannot be a negative value.
+    The function clears the pending bit of an external interrupt.
 
-    \param [in]      IRQn  Number of the interrupt for clear pending
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
  */
 static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
 {
@@ -987,10 +988,12 @@
 
 /** \brief  Get Active Interrupt
 
-    This function reads the active register in NVIC and returns the active bit. 
-    \param [in]      IRQn  Number of the interrupt for get active
-    \return             0  Interrupt status is not active
-    \return             1  Interrupt status is active
+    The function reads the active register in NVIC and returns the active bit.
+    
+    \param [in]      IRQn  Interrupt number.
+    
+    \return             0  Interrupt status is not active.
+    \return             1  Interrupt status is active.
  */
 static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
 {
@@ -1000,14 +1003,12 @@
 
 /** \brief  Set Interrupt Priority
 
-    This function sets the priority for the specified interrupt. The interrupt 
-    number can be positive to specify an external (device specific) 
-    interrupt, or negative to specify an internal (core) interrupt.
+    The function sets the priority of an interrupt. 
 
-    Note: The priority cannot be set for every core interrupt.
+    \note The priority cannot be set for every core interrupt.
 
-    \param [in]      IRQn  Number of the interrupt for set priority
-    \param [in]  priority  Priority to set
+    \param [in]      IRQn  Interrupt number. 
+    \param [in]  priority  Priority to set.
  */
 static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
 {
@@ -1020,15 +1021,14 @@
 
 /** \brief  Get Interrupt Priority
 
-    This function reads the priority for the specified interrupt. The interrupt 
-    number can be positive to specify an external (device specific) 
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
     interrupt, or negative to specify an internal (core) interrupt.
 
-    The returned priority value is automatically aligned to the implemented
-    priority bits of the microcontroller.
 
-    \param [in]   IRQn  Number of the interrupt for get priority
-    \return             Interrupt Priority
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
  */
 static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
 {
@@ -1042,17 +1042,15 @@
 
 /** \brief  Encode Priority
 
-    This function encodes the priority for an interrupt with the given priority group,
-    preemptive priority value and sub priority value.
+    The function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value, and subpriority value.
     In case of a conflict between priority grouping and available
-    priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
- 
-    The returned priority value can be used for NVIC_SetPriority(...) function
+    priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
 
-    \param [in]     PriorityGroup  Used priority group
-    \param [in]   PreemptPriority  Preemptive priority value (starting from 0)
-    \param [in]       SubPriority  Sub priority value (starting from 0)
-    \return                        Encoded priority for the interrupt
+    \param [in]     PriorityGroup  Used priority group.
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+    \param [in]       SubPriority  Subpriority value (starting from 0).
+    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
  */
 static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
 {
@@ -1062,7 +1060,7 @@
 
   PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
   SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
- 
+
   return (
            ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
            ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
@@ -1072,17 +1070,15 @@
 
 /** \brief  Decode Priority
 
-    This function decodes an interrupt priority value with the given priority group to 
-    preemptive priority value and sub priority value.
+    The function decodes an interrupt priority value with a given priority group to
+    preemptive priority value and subpriority value.
     In case of a conflict between priority grouping and available
     priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
- 
-    The priority value can be retrieved with NVIC_GetPriority(...) function
- 
-    \param [in]         Priority   Priority value
-    \param [in]     PriorityGroup  Used priority group
-    \param [out] pPreemptPriority  Preemptive priority value (starting from 0)
-    \param [out]     pSubPriority  Sub priority value (starting from 0)
+
+    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+    \param [in]     PriorityGroup  Used priority group.
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+    \param [out]     pSubPriority  Subpriority value (starting from 0).
  */
 static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
 {
@@ -1092,7 +1088,7 @@
 
   PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
   SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-  
+
   *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
   *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
 }
@@ -1100,16 +1096,16 @@
 
 /** \brief  System Reset
 
-    This function initiate a system reset request to reset the MCU.
+    The function initiates a system reset request to reset the MCU.
  */
 static __INLINE void NVIC_SystemReset(void)
 {
   __DSB();                                                     /* Ensure all outstanding memory accesses included
-                                                                  buffered write are completed before reset */              
-  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      | 
-                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
                  SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
-  __DSB();                                                     /* Ensure completion of memory access */              
+  __DSB();                                                     /* Ensure completion of memory access */
   while(1);                                                    /* wait until reset */
 }
 
@@ -1118,8 +1114,9 @@
 
 
 /* ##################################    SysTick function  ############################################ */
-/** \ingroup  CMSIS_Core_FunctionInterface   
-    \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
   @{
  */
 
@@ -1127,22 +1124,28 @@
 
 /** \brief  System Tick Configuration
 
-    This function initialises the system tick timer and its interrupt and start the system tick timer.
-    Counter is in free running mode to generate periodical interrupts.
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.   
 
-    \param [in]  ticks  Number of ticks between two interrupts
-    \return          0  Function succeeded
-    \return          1  Function failed
+    \param [in]  ticks  Number of ticks between two interrupts.
+    
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+    
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the 
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> 
+    must contain a vendor-specific implementation of this function.
+
  */
 static __INLINE uint32_t SysTick_Config(uint32_t ticks)
-{ 
+{
   if (ticks > SysTick_LOAD_RELOAD_Msk)  return (1);            /* Reload value impossible */
-                                                               
+
   SysTick->LOAD  = (ticks & SysTick_LOAD_RELOAD_Msk) - 1;      /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Cortex-M0 System Interrupts */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
   SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk | 
-                   SysTick_CTRL_TICKINT_Msk   | 
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
                    SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
   return (0);                                                  /* Function successful */
 }
@@ -1154,45 +1157,44 @@
 
 
 /* ##################################### Debug In/Output function ########################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface   
-    \defgroup CMSIS_core_DebugFunctions CMSIS Core Debug Functions
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions ITM Functions
+    \brief   Functions that access the ITM debug interface.
   @{
  */
 
-extern volatile int32_t ITM_RxBuffer;                    /*!< external variable to receive characters                    */
-#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
 
 
 /** \brief  ITM Send Character
 
-    This function transmits a character via the ITM channel 0. 
-    It just returns when no debugger is connected that has booked the output.  
-    It is blocking when a debugger is connected, but the previous character send is not transmitted. 
+    The function transmits a character via the ITM channel 0, and
+    \li Just returns when no debugger is connected that has booked the output.
+    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
 
-    \param [in]     ch  Character to transmit
-    \return             Character to transmit
+    \param [in]     ch  Character to transmit.
+    
+    \returns            Character to transmit.
  */
 static __INLINE uint32_t ITM_SendChar (uint32_t ch)
 {
-  if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk)  &&      /* Trace enabled */
-      (ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
+  if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
       (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
   {
     while (ITM->PORT[0].u32 == 0);
     ITM->PORT[0].u8 = (uint8_t) ch;
-  }  
+  }
   return (ch);
 }
 
 
 /** \brief  ITM Receive Character
 
-    This function inputs a character via external variable ITM_RxBuffer. 
-    It just returns when no debugger is connected that has booked the output.  
-    It is blocking when a debugger is connected, but the previous character send is not transmitted. 
+    The function inputs a character via the external variable \ref ITM_RxBuffer.
 
-    \return             Received character
-    \return         -1  No character received
+    \return             Received character.
+    \return         -1  No character pending.
  */
 static __INLINE int32_t ITM_ReceiveChar (void) {
   int32_t ch = -1;                           /* no character available */
@@ -1201,18 +1203,17 @@
     ch = ITM_RxBuffer;
     ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
   }
-  
-  return (ch); 
+
+  return (ch);
 }
 
 
 /** \brief  ITM Check Character
 
-    This function checks external variable ITM_RxBuffer whether a character is available or not. 
-    It returns '1' if a character is available and '0' if no character is available. 
+    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
 
-    \return          0  No character available
-    \return          1  Character available
+    \return          0  No character available.
+    \return          1  Character available.
  */
 static __INLINE int32_t ITM_CheckChar (void) {
 
@@ -1232,5 +1233,3 @@
 #ifdef __cplusplus
 }
 #endif
-
-/*lint -restore */

Binary file LPC1768/ARM/core_cm3.o has changed

--- a/LPC1768/ARM/core_cmFunc.h	Fri Jan 06 16:40:24 2012 +0000
+++ b/LPC1768/ARM/core_cmFunc.h	Tue Jan 10 12:00:50 2012 +0000
@@ -1,11 +1,11 @@
 /**************************************************************************//**
  * @file     core_cmFunc.h
  * @brief    CMSIS Cortex-M Core Function Access Header File
- * @version  V2.01
- * @date     06. December 2010
+ * @version  V3.00
+ * @date     09. December 2011
  *
  * @note
- * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
  *
  * @par
  * ARM Limited (ARM) is supplying this software for use with Cortex-M 
@@ -21,8 +21,9 @@
  *
  ******************************************************************************/
 
-#ifndef __CORE_CMFUNC_H__
-#define __CORE_CMFUNC_H__
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
 
 /* ###########################  Core Function Access  ########################### */
 /** \ingroup  CMSIS_Core_FunctionInterface   
@@ -30,9 +31,13 @@
   @{
  */
 
-#if defined ( __CC_ARM   ) /*------------------ RealView Compiler ----------------*/
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
 /* ARM armcc specific functions */
 
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
 /* intrinsic void __enable_irq();     */
 /* intrinsic void __disable_irq();    */
 
@@ -42,15 +47,11 @@
 
     \return               Control Register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_CONTROL(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_CONTROL(void)
 {
   register uint32_t __regControl         __ASM("control");
   return(__regControl);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Set Control Register
@@ -59,32 +60,24 @@
 
     \param [in]    control  Control Register value to set
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          void __set_CONTROL(uint32_t control);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE void __set_CONTROL(uint32_t control)
 {
   register uint32_t __regControl         __ASM("control");
   __regControl = control;
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
-/** \brief  Get ISPR Register
-
-    This function returns the content of the ISPR Register.
+/** \brief  Get IPSR Register
 
-    \return               ISPR Register value
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_IPSR(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_IPSR(void)
 {
   register uint32_t __regIPSR          __ASM("ipsr");
   return(__regIPSR);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Get APSR Register
@@ -93,15 +86,11 @@
 
     \return               APSR Register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_APSR(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_APSR(void)
 {
   register uint32_t __regAPSR          __ASM("apsr");
   return(__regAPSR);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Get xPSR Register
@@ -110,15 +99,11 @@
 
     \return               xPSR Register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_xPSR(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_xPSR(void)
 {
   register uint32_t __regXPSR          __ASM("xpsr");
   return(__regXPSR);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Get Process Stack Pointer
@@ -127,15 +112,11 @@
 
     \return               PSP Register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_PSP(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_PSP(void)
 {
   register uint32_t __regProcessStackPointer  __ASM("psp");
   return(__regProcessStackPointer);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Set Process Stack Pointer
@@ -144,15 +125,11 @@
 
     \param [in]    topOfProcStack  Process Stack Pointer value to set
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          void __set_PSP(uint32_t topOfProcStack);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE void __set_PSP(uint32_t topOfProcStack)
 {
   register uint32_t __regProcessStackPointer  __ASM("psp");
   __regProcessStackPointer = topOfProcStack;
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Get Main Stack Pointer
@@ -161,15 +138,11 @@
 
     \return               MSP Register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_MSP(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_MSP(void)
 {
   register uint32_t __regMainStackPointer     __ASM("msp");
   return(__regMainStackPointer);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Set Main Stack Pointer
@@ -178,15 +151,11 @@
 
     \param [in]    topOfMainStack  Main Stack Pointer value to set
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          void __set_MSP(uint32_t topOfMainStack);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE void __set_MSP(uint32_t topOfMainStack)
 {
   register uint32_t __regMainStackPointer     __ASM("msp");
   __regMainStackPointer = topOfMainStack;
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Get Priority Mask
@@ -195,15 +164,11 @@
 
     \return               Priority Mask value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_PRIMASK(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_PRIMASK(void)
 {
   register uint32_t __regPriMask         __ASM("primask");
   return(__regPriMask);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Set Priority Mask
@@ -212,15 +177,11 @@
 
     \param [in]    priMask  Priority Mask
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          void __set_PRIMASK(uint32_t priMask);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE void __set_PRIMASK(uint32_t priMask)
 {
   register uint32_t __regPriMask         __ASM("primask");
   __regPriMask = (priMask);
 }
-#endif /*  __ARMCC_VERSION  */ 
  
 
 #if       (__CORTEX_M >= 0x03)
@@ -247,15 +208,11 @@
 
     \return               Base Priority register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_BASEPRI(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t  __get_BASEPRI(void)
 {
   register uint32_t __regBasePri         __ASM("basepri");
   return(__regBasePri);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Set Base Priority
@@ -264,15 +221,11 @@
 
     \param [in]    basePri  Base Priority value to set
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          void __set_BASEPRI(uint32_t basePri);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE void __set_BASEPRI(uint32_t basePri)
 {
   register uint32_t __regBasePri         __ASM("basepri");
   __regBasePri = (basePri & 0xff);
 }
-#endif /*  __ARMCC_VERSION  */ 
  
 
 /** \brief  Get Fault Mask
@@ -281,15 +234,11 @@
 
     \return               Fault Mask register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_FAULTMASK(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_FAULTMASK(void)
 {
   register uint32_t __regFaultMask       __ASM("faultmask");
   return(__regFaultMask);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Set Fault Mask
@@ -298,15 +247,11 @@
 
     \param [in]    faultMask  Fault Mask value to set
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          void __set_FAULTMASK(uint32_t faultMask);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE void __set_FAULTMASK(uint32_t faultMask)
 {
   register uint32_t __regFaultMask       __ASM("faultmask");
-  __regFaultMask = (faultMask & 1);
+  __regFaultMask = (faultMask & (uint32_t)1);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 #endif /* (__CORTEX_M >= 0x03) */
 
@@ -321,7 +266,7 @@
  */
 static __INLINE uint32_t __get_FPSCR(void)
 {
-#if (__FPU_PRESENT == 1)
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
   register uint32_t __regfpscr         __ASM("fpscr");
   return(__regfpscr);
 #else
@@ -338,7 +283,7 @@
  */
 static __INLINE void __set_FPSCR(uint32_t fpscr)
 {
-#if (__FPU_PRESENT == 1)
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
   register uint32_t __regfpscr         __ASM("fpscr");
   __regfpscr = (fpscr);
 #endif
@@ -347,192 +292,12 @@
 #endif /* (__CORTEX_M == 0x04) */
 
 
- #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
 /* IAR iccarm specific functions */
 
-#if defined (__ICCARM__)
-  #include <intrinsics.h>                     /* IAR Intrinsics   */
-#endif
-
-#pragma diag_suppress=Pe940
-
-/** \brief  Enable IRQ Interrupts
-
-  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
-  Can only be executed in Privileged modes.
- */
-#define __enable_irq                              __enable_interrupt
-
-
-/** \brief  Disable IRQ Interrupts
-
-  This function disables IRQ interrupts by setting the I-bit in the CPSR.
-  Can only be executed in Privileged modes.
- */
-#define __disable_irq                             __disable_interrupt
-
-
-/* intrinsic unsigned long __get_CONTROL( void ); (see intrinsic.h) */
-/* intrinsic void __set_CONTROL( unsigned long ); (see intrinsic.h) */
-
-
-/** \brief  Get ISPR Register
-
-    This function returns the content of the ISPR Register.
-
-    \return               ISPR Register value
- */
-static uint32_t __get_IPSR(void)
-{
-  __ASM("mrs r0, ipsr");
-}
-
-
-/** \brief  Get APSR Register
-
-    This function returns the content of the APSR Register.
-
-    \return               APSR Register value
- */
-static uint32_t __get_APSR(void)
-{
-  __ASM("mrs r0, apsr");
-}
-
-
-/** \brief  Get xPSR Register
-
-    This function returns the content of the xPSR Register.
-
-    \return               xPSR Register value
- */
-static uint32_t __get_xPSR(void)
-{
-  __ASM("mrs r0, psr");           // assembler does not know "xpsr"
-}
-
-
-/** \brief  Get Process Stack Pointer
-
-    This function returns the current value of the Process Stack Pointer (PSP).
-
-    \return               PSP Register value
- */
-static uint32_t __get_PSP(void)
-{
-  __ASM("mrs r0, psp");
-}
- 
-
-/** \brief  Set Process Stack Pointer
-
-    This function assigns the given value to the Process Stack Pointer (PSP).
-
-    \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-static void __set_PSP(uint32_t topOfProcStack)
-{
-  __ASM("msr psp, r0");
-}
-
-
-/** \brief  Get Main Stack Pointer
-
-    This function returns the current value of the Main Stack Pointer (MSP).
+#include <cmsis_iar.h>
 
-    \return               MSP Register value
- */
-static uint32_t __get_MSP(void)
-{
-  __ASM("mrs r0, msp");
-}
- 
-
-/** \brief  Set Main Stack Pointer
-
-    This function assigns the given value to the Main Stack Pointer (MSP).
-
-    \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-static void __set_MSP(uint32_t topOfMainStack)
-{
-  __ASM("msr msp, r0");
-}
- 
-
-/* intrinsic unsigned long __get_PRIMASK( void ); (see intrinsic.h) */
-/* intrinsic void __set_PRIMASK( unsigned long ); (see intrinsic.h) */
- 
-
-#if       (__CORTEX_M >= 0x03)
-
-/** \brief  Enable FIQ
-
-    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-static __INLINE void __enable_fault_irq(void)
-{
-  __ASM ("cpsie f");
-}
-
-
-/** \brief  Disable FIQ
-
-    This function disables FIQ interrupts by setting the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-static __INLINE void __disable_fault_irq(void)
-{
-  __ASM ("cpsid f");
-}
-
-
-/* intrinsic unsigned long __get_BASEPRI( void );   (see intrinsic.h) */
-/* intrinsic void __set_BASEPRI( unsigned long );   (see intrinsic.h) */
-/* intrinsic unsigned long __get_FAULTMASK( void ); (see intrinsic.h) */
-/* intrinsic void __set_FAULTMASK(unsigned long);   (see intrinsic.h) */
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-#if       (__CORTEX_M == 0x04)
-
-/** \brief  Get FPSCR
-
-    This function returns the current value of the Floating Point Status/Control register.
-
-    \return               Floating Point Status/Control register value
- */
-static uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1)
-  __ASM("vmrs r0, fpscr"); 
-#else
-  return(0);
-#endif
-}
-
-
-/** \brief  Set FPSCR
-
-    This function assigns the given value to the Floating Point Status/Control register.
-
-    \param [in]    fpscr  Floating Point Status/Control value to set
- */
-static void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1)
-  __ASM("vmsr fpscr, r0");
-#endif
-}
-
-#endif /* (__CORTEX_M == 0x04) */
-
-#pragma diag_default=Pe940
-
-
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
 /* GNU gcc specific functions */
 
 /** \brief  Enable IRQ Interrupts
@@ -584,11 +349,11 @@
 }
 
 
-/** \brief  Get ISPR Register
+/** \brief  Get IPSR Register
 
-    This function returns the content of the ISPR Register.
+    This function returns the content of the IPSR Register.
 
-    \return               ISPR Register value
+    \return               IPSR Register value
  */
 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void)
 {
@@ -800,10 +565,10 @@
  */
 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void)
 {
-#if (__FPU_PRESENT == 1)
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
   uint32_t result;
 
-  __ASM volatile ("MRS %0, fpscr" : "=r" (result) );
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
   return(result);
 #else
    return(0);
@@ -819,15 +584,15 @@
  */
 __attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr)
 {
-#if (__FPU_PRESENT == 1)
-  __ASM volatile ("MSR fpscr, %0" : : "r" (fpscr) );
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );
 #endif
 }
 
 #endif /* (__CORTEX_M == 0x04) */
 
 
-#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
 /* TASKING carm specific functions */
 
 /*
@@ -841,4 +606,4 @@
 /*@} end of CMSIS_Core_RegAccFunctions */
 
 
-#endif /* __CORE_CMFUNC_H__ */
+#endif /* __CORE_CMFUNC_H */

--- a/LPC1768/ARM/core_cmInstr.h	Fri Jan 06 16:40:24 2012 +0000
+++ b/LPC1768/ARM/core_cmInstr.h	Tue Jan 10 12:00:50 2012 +0000
@@ -1,11 +1,11 @@
 /**************************************************************************//**
  * @file     core_cmInstr.h
  * @brief    CMSIS Cortex-M Core Instruction Access Header File
- * @version  V2.01
- * @date     06. December 2010
+ * @version  V3.00
+ * @date     09. December 2011
  *
  * @note
- * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
  *
  * @par
  * ARM Limited (ARM) is supplying this software for use with Cortex-M 
@@ -21,8 +21,8 @@
  *
  ******************************************************************************/
 
-#ifndef __CORE_CMINSTR_H__
-#define __CORE_CMINSTR_H__
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
 
 
 /* ##########################  Core Instruction Access  ######################### */
@@ -31,9 +31,14 @@
   @{
 */
 
-#if defined ( __CC_ARM   ) /*------------------ RealView Compiler ----------------*/
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
 /* ARM armcc specific functions */
 
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
 /** \brief  No Operation
 
     No Operation does nothing. This instruction can be used for code alignment purposes.
@@ -106,15 +111,11 @@
     \param [in]    value  Value to reverse
     \return               Reversed value
  */
-#if (__ARMCC_VERSION < 400677)
-extern uint32_t __REV16(uint32_t value);
-#else  /* (__ARMCC_VERSION >= 400677)  */
-static __INLINE __ASM uint32_t __REV16(uint32_t value)
+static __attribute__((section(".rev16_text"))) __INLINE __ASM uint32_t __REV16(uint32_t value)
 {
   rev16 r0, r0
   bx lr
 }
-#endif /* __ARMCC_VERSION  */ 
 
 
 /** \brief  Reverse byte order in signed short value
@@ -124,15 +125,11 @@
     \param [in]    value  Value to reverse
     \return               Reversed value
  */
-#if (__ARMCC_VERSION < 400677)
-extern int32_t __REVSH(int32_t value);
-#else  /* (__ARMCC_VERSION >= 400677)  */
-static __INLINE __ASM int32_t __REVSH(int32_t value)
+static __attribute__((section(".revsh_text"))) __INLINE __ASM int32_t __REVSH(int32_t value)
 {
   revsh r0, r0
   bx lr
 }
-#endif /* __ARMCC_VERSION  */ 
 
 
 #if       (__CORTEX_M >= 0x03)
@@ -218,11 +215,7 @@
     This function removes the exclusive lock which is created by LDREX.
 
  */
-#if (__ARMCC_VERSION < 400000)
-extern void __CLREX(void);
-#else  /* (__ARMCC_VERSION >= 400000)  */
 #define __CLREX                           __clrex
-#endif /* __ARMCC_VERSION  */ 
 
 
 /** \brief  Signed Saturate
@@ -260,196 +253,13 @@
 
 
 
-#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
 /* IAR iccarm specific functions */
 
-#include <intrinsics.h>                     /* IAR Intrinsics   */
-
-#pragma diag_suppress=Pe940
-
-/** \brief  No Operation
-
-    No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-#define __NOP                           __no_operation
-
-
-/** \brief  Wait For Interrupt
-
-    Wait For Interrupt is a hint instruction that suspends execution
-    until one of a number of events occurs.
- */
-static __INLINE  void __WFI(void)
-{
-  __ASM ("wfi");
-}
-
-
-/** \brief  Wait For Event
-
-    Wait For Event is a hint instruction that permits the processor to enter
-    a low-power state until one of a number of events occurs.
- */
-static __INLINE  void __WFE(void)
-{
-  __ASM ("wfe");
-}
-
-
-/** \brief  Send Event
-
-    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-static __INLINE  void __SEV(void)
-{
-  __ASM ("sev");
-}
-
-
-/* intrinsic     void __ISB(void)            (see intrinsics.h) */
-/* intrinsic     void __DSB(void)            (see intrinsics.h) */
-/* intrinsic     void __DMB(void)            (see intrinsics.h) */
-/* intrinsic uint32_t __REV(uint32_t value)  (see intrinsics.h) */
-/* intrinsic          __SSAT                 (see intrinsics.h) */
-/* intrinsic          __USAT                 (see intrinsics.h) */
-
-
-/** \brief  Reverse byte order (16 bit)
-
-    This function reverses the byte order in two unsigned short values.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-static uint32_t __REV16(uint32_t value)
-{
-  __ASM("rev16 r0, r0");
-}
-
-
-/* intrinsic uint32_t __REVSH(uint32_t value)  (see intrinsics.h */
-
-
-#if       (__CORTEX_M >= 0x03)
-
-/** \brief  Reverse bit order of value
-
-    This function reverses the bit order of the given value.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-static uint32_t __RBIT(uint32_t value)
-{
-  __ASM("rbit r0, r0");
-}
+#include <cmsis_iar.h>
 
 
-/** \brief  LDR Exclusive (8 bit)
-
-    This function performs a exclusive LDR command for 8 bit value.
-
-    \param [in]    ptr  Pointer to data
-    \return             value of type uint8_t at (*ptr)
- */
-static uint8_t __LDREXB(volatile uint8_t *addr)
-{
-  __ASM("ldrexb r0, [r0]");
-}
-
-
-/** \brief  LDR Exclusive (16 bit)
-
-    This function performs a exclusive LDR command for 16 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint16_t at (*ptr)
- */
-static uint16_t __LDREXH(volatile uint16_t *addr)
-{
-  __ASM("ldrexh r0, [r0]");
-}
-
-
-/** \brief  LDR Exclusive (32 bit)
-
-    This function performs a exclusive LDR command for 32 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint32_t at (*ptr)
- */
-/* intrinsic unsigned long __LDREX(unsigned long *)  (see intrinsics.h) */
-static uint32_t __LDREXW(volatile uint32_t *addr)
-{
-  __ASM("ldrex r0, [r0]");
-}
-
-
-/** \brief  STR Exclusive (8 bit)
-
-    This function performs a exclusive STR command for 8 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-static uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
-{
-  __ASM("strexb r0, r0, [r1]");
-}
-
-
-/** \brief  STR Exclusive (16 bit)
-
-    This function performs a exclusive STR command for 16 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-static uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
-{
-  __ASM("strexh r0, r0, [r1]");
-}
-
-
-/** \brief  STR Exclusive (32 bit)
-
-    This function performs a exclusive STR command for 32 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-/* intrinsic unsigned long __STREX(unsigned long, unsigned long)  (see intrinsics.h )*/
-static uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
-{
-  __ASM("strex r0, r0, [r1]");
-}
-
-
-/** \brief  Remove the exclusive lock
-
-    This function removes the exclusive lock which is created by LDREX.
-
- */
-static __INLINE void __CLREX(void)
-{
-  __ASM ("clrex");
-}
-
-/* intrinsic   unsigned char __CLZ( unsigned long )      (see intrinsics.h) */
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-#pragma diag_default=Pe940
-
-
-
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
 /* GNU gcc specific functions */
 
 /** \brief  No Operation
@@ -655,7 +465,7 @@
 {
    uint32_t result;
   
-   __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+   __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
    return(result);
 }
 
@@ -673,7 +483,7 @@
 {
    uint32_t result;
   
-   __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+   __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
    return(result);
 }
 
@@ -691,7 +501,7 @@
 {
    uint32_t result;
   
-   __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+   __ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
    return(result);
 }
 
@@ -759,12 +569,12 @@
 
 
 
-#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
 /* TASKING carm specific functions */
 
 /*
  * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
  * Including the CMSIS ones.
  */
 
@@ -772,4 +582,4 @@
 
 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
 
-#endif /* __CORE_CMINSTR_H__ */
+#endif /* __CORE_CMINSTR_H */

Binary file LPC1768/ARM/mbed.ar has changed

Binary file LPC1768/ARM/sys.o has changed

Binary file LPC1768/ARM/system_LPC17xx.o has changed

--- a/LPC1768/GCC_ARM/core_cm3.h	Fri Jan 06 16:40:24 2012 +0000
+++ b/LPC1768/GCC_ARM/core_cm3.h	Tue Jan 10 12:00:50 2012 +0000
@@ -1,16 +1,16 @@
 /**************************************************************************//**
  * @file     core_cm3.h
  * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
- * @version  V2.01
- * @date     06. December 2010
+ * @version  V3.00
+ * @date     09. December 2011
  *
  * @note
- * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
  *
  * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M 
- * processor based microcontrollers.  This file can be freely distributed 
- * within development tools that are supporting such ARM based processors. 
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers.  This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
  *
  * @par
  * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
@@ -20,106 +20,144 @@
  * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
  *
  ******************************************************************************/
-#if defined ( __ICCARM__ )                   
+#if defined ( __ICCARM__ )
  #pragma system_include  /* treat file as system include file for MISRA check */
 #endif
 
 #ifdef __cplusplus
  extern "C" {
-#endif 
+#endif
 
 #ifndef __CORE_CM3_H_GENERIC
 #define __CORE_CM3_H_GENERIC
 
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+  
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'. 
 
-/** \mainpage CMSIS Cortex-M3
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
    
-  This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer.
-  It consists of:
- 
-     - Cortex-M Core Register Definitions
-     - Cortex-M functions
-     - Cortex-M instructions
- 
-  The CMSIS Cortex-M3 Core Peripheral Access Layer contains C and assembly functions that ease 
-  access to the Cortex-M Core
- */ 
-
-/** \defgroup CMSIS_LintCinfiguration CMSIS Lint Configuration
-  List of Lint messages which will be suppressed and not shown:
-    - not yet checked
-  .
-  Note:  To re-enable a Message, insert a space before 'lint' *
- 
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code. 
  */
 
 
 /*******************************************************************************
  *                 CMSIS definitions
  ******************************************************************************/
-/** \defgroup CMSIS_core_definitions CMSIS Core Definitions
-  This file defines all structures and symbols for CMSIS core:
-   - CMSIS version number
-   - Cortex-M core 
-   - Cortex-M core Revision Number
+/** \ingroup Cortex_M3
   @{
  */
 
 /*  CMSIS CM3 definitions */
-#define __CM3_CMSIS_VERSION_MAIN  (0x02)                                                       /*!< [31:16] CMSIS HAL main version */
-#define __CM3_CMSIS_VERSION_SUB   (0x00)                                                       /*!< [15:0]  CMSIS HAL sub version  */
-#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number       */
+#define __CM3_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM3_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | \
+                                    __CM3_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
 
-#define __CORTEX_M                (0x03)                                                       /*!< Cortex core                    */
+#define __CORTEX_M                (0x03)                                   /*!< Cortex-M Core                    */
 
 
-#if defined ( __CC_ARM   )
+#if   defined ( __CC_ARM )
   #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
   #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
 
 #elif defined ( __ICCARM__ )
   #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */
-  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
+  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
 
-#elif defined   (  __GNUC__  )
+#elif defined ( __GNUC__ )
   #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
   #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
 
-#elif defined   (  __TASKING__  )
+#elif defined ( __TASKING__ )
   #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
   #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
 
 #endif
 
-#include <stdint.h>                      /*!< standard types definitions                      */
-#include "core_cmInstr.h"                /*!< Core Instruction Access                         */
-#include "core_cmFunc.h"                 /*!< Core Function Access                            */
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+    /* add preprocessor checks */
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
 
 #endif /* __CORE_CM3_H_GENERIC */
 
-
 #ifndef __CMSIS_GENERIC
 
 #ifndef __CORE_CM3_H_DEPENDANT
 #define __CORE_CM3_H_DEPENDANT
 
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM3_REV
+    #define __CM3_REV               0x0200
+    #warning "__CM3_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          4
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
 /* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+ 
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
 #ifdef __cplusplus
-  #define     __I     volatile           /*!< defines 'read only' permissions                 */
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
 #else
-  #define     __I     volatile const     /*!< defines 'read only' permissions                 */
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
 #endif
-#define     __O     volatile             /*!< defines 'write only' permissions                */
-#define     __IO    volatile             /*!< defines 'read / write' permissions              */
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
 
-/*@} end of group CMSIS_core_definitions */
+/*@} end of group Cortex_M3 */
 
 
 
 /*******************************************************************************
  *                 Register Abstraction
- ******************************************************************************/
-/** \defgroup CMSIS_core_register CMSIS Core Register
   Core Register contain:
   - Core Register
   - Core NVIC Register
@@ -127,11 +165,14 @@
   - Core SysTick Register
   - Core Debug Register
   - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
 */
 
-/** \ingroup  CMSIS_core_register   
-    \defgroup CMSIS_CORE CMSIS Core
-  Type definitions for the Cortex-M Core Registers
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
   @{
  */
 
@@ -154,7 +195,7 @@
     uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
     uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
   } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */ 
+  uint32_t w;                            /*!< Type      used for word access                  */
 } APSR_Type;
 
 
@@ -214,9 +255,9 @@
 /*@} end of group CMSIS_CORE */
 
 
-/** \ingroup  CMSIS_core_register   
-    \defgroup CMSIS_NVIC CMSIS NVIC
-  Type definitions for the Cortex-M NVIC Registers
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
   @{
  */
 
@@ -225,26 +266,30 @@
 typedef struct
 {
   __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
-       uint32_t RESERVED0[24];                                   
+       uint32_t RESERVED0[24];
   __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
-       uint32_t RSERVED1[24];                                    
+       uint32_t RSERVED1[24];
   __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
-       uint32_t RESERVED2[24];                                   
+       uint32_t RESERVED2[24];
   __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
-       uint32_t RESERVED3[24];                                   
+       uint32_t RESERVED3[24];
   __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
-       uint32_t RESERVED4[56];                                   
+       uint32_t RESERVED4[56];
   __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
-       uint32_t RESERVED5[644];                                  
+       uint32_t RESERVED5[644];
   __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
-}  NVIC_Type;                                               
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
 
 /*@} end of group CMSIS_NVIC */
 
 
-/** \ingroup  CMSIS_core_register   
-    \defgroup CMSIS_SCB CMSIS SCB
-  Type definitions for the Cortex-M System Control Block Registers
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
   @{
  */
 
@@ -252,26 +297,28 @@
  */
 typedef struct
 {
-  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPU ID Base Register                                  */
-  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control State Register                      */
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
   __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
-  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt / Reset Control Register        */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
   __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
   __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
   __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
   __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
   __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
-  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  Hard Fault Status Register                            */
+  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
   __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
-  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  Mem Manage Address Register                           */
-  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  Bus Fault Address Register                            */
+  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
   __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
   __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
   __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
   __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
   __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
-  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  ISA Feature Register                                  */
-} SCB_Type;                                                
+  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+       uint32_t RESERVED0[5];
+  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+} SCB_Type;
 
 /* SCB CPUID Register Definitions */
 #define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
@@ -280,6 +327,9 @@
 #define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
 #define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
 
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
 #define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
 #define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
 
@@ -317,12 +367,17 @@
 #define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
 #define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
 
-/* SCB Interrupt Control State Register Definitions */
+/* SCB Vector Table Offset Register Definitions */
+#if (__CM3_REV < 0x0201)                   /* core r2p1 */
 #define SCB_VTOR_TBLBASE_Pos               29                                             /*!< SCB VTOR: TBLBASE Position */
 #define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
 
 #define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
 #define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+#endif
 
 /* SCB Application Interrupt and Reset Control Register Definitions */
 #define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
@@ -408,7 +463,7 @@
 
 #define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
 #define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
-                                     
+
 #define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
 #define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
 
@@ -457,9 +512,46 @@
 /*@} end of group CMSIS_SCB */
 
 
-/** \ingroup  CMSIS_core_register   
-    \defgroup CMSIS_SysTick CMSIS SysTick
-  Type definitions for the Cortex-M System Timer Registers
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register      */
+#else
+       uint32_t RESERVED1[1];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
   @{
  */
 
@@ -507,9 +599,9 @@
 /*@} end of group CMSIS_SysTick */
 
 
-/** \ingroup  CMSIS_core_register   
-    \defgroup CMSIS_ITM CMSIS ITM
-  Type definitions for the Cortex-M Instrumentation Trace Macrocell (ITM)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
   @{
  */
 
@@ -517,134 +609,59 @@
  */
 typedef struct
 {
-  __O  union  
+  __O  union
   {
     __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
     __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
     __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
   }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
-       uint32_t RESERVED0[864];                                 
-  __IO uint32_t TER;                     /*!< Offset:       (R/W)  ITM Trace Enable Register                 */
-       uint32_t RESERVED1[15];                                  
-  __IO uint32_t TPR;                     /*!< Offset:       (R/W)  ITM Trace Privilege Register              */
-       uint32_t RESERVED2[15];                                  
-  __IO uint32_t TCR;                     /*!< Offset:       (R/W)  ITM Trace Control Register                */
-       uint32_t RESERVED3[29];                                  
-  __IO uint32_t IWR;                     /*!< Offset:       (R/W)  ITM Integration Write Register            */
-  __IO uint32_t IRR;                     /*!< Offset:       (R/W)  ITM Integration Read Register             */
-  __IO uint32_t IMCR;                    /*!< Offset:       (R/W)  ITM Integration Mode Control Register     */
-       uint32_t RESERVED4[43];                                  
-  __IO uint32_t LAR;                     /*!< Offset:       (R/W)  ITM Lock Access Register                  */
-  __IO uint32_t LSR;                     /*!< Offset:       (R/W)  ITM Lock Status Register                  */
-       uint32_t RESERVED5[6];                                   
-  __I  uint32_t PID4;                    /*!< Offset:       (R/ )  ITM Peripheral Identification Register #4 */
-  __I  uint32_t PID5;                    /*!< Offset:       (R/ )  ITM Peripheral Identification Register #5 */
-  __I  uint32_t PID6;                    /*!< Offset:       (R/ )  ITM Peripheral Identification Register #6 */
-  __I  uint32_t PID7;                    /*!< Offset:       (R/ )  ITM Peripheral Identification Register #7 */
-  __I  uint32_t PID0;                    /*!< Offset:       (R/ )  ITM Peripheral Identification Register #0 */
-  __I  uint32_t PID1;                    /*!< Offset:       (R/ )  ITM Peripheral Identification Register #1 */
-  __I  uint32_t PID2;                    /*!< Offset:       (R/ )  ITM Peripheral Identification Register #2 */
-  __I  uint32_t PID3;                    /*!< Offset:       (R/ )  ITM Peripheral Identification Register #3 */
-  __I  uint32_t CID0;                    /*!< Offset:       (R/ )  ITM Component  Identification Register #0 */
-  __I  uint32_t CID1;                    /*!< Offset:       (R/ )  ITM Component  Identification Register #1 */
-  __I  uint32_t CID2;                    /*!< Offset:       (R/ )  ITM Component  Identification Register #2 */
-  __I  uint32_t CID3;                    /*!< Offset:       (R/ )  ITM Component  Identification Register #3 */
-} ITM_Type;                                                
+       uint32_t RESERVED0[864];
+  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+       uint32_t RESERVED1[15];
+  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+       uint32_t RESERVED2[15];
+  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+} ITM_Type;
 
 /* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
+#define ITM_TPR_PRIVMASK_Pos                0                                          /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)             /*!< ITM TPR: PRIVMASK Mask */
 
 /* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+#define ITM_TCR_BUSY_Pos                   23                                          /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                   /*!< ITM TCR: BUSY Mask */
 
-#define ITM_TCR_ATBID_Pos                  16                                             /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_ATBID_Msk                  (0x7FUL << ITM_TCR_ATBID_Pos)                  /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+#define ITM_TCR_TraceBusID_Pos             16                                          /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)          /*!< ITM TCR: ATBID Mask */
 
-#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+#define ITM_TCR_GTSFREQ_Pos                10                                          /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                /*!< ITM TCR: Global timestamp frequency Mask */
 
-#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+#define ITM_TCR_TSPrescale_Pos              8                                          /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)             /*!< ITM TCR: TSPrescale Mask */
 
-#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
+#define ITM_TCR_SWOENA_Pos                  4                                          /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                 /*!< ITM TCR: SWOENA Mask */
 
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
+#define ITM_TCR_TXENA_Pos                   3                                          /*!< ITM TCR: TXENA Position */
+#define ITM_TCR_TXENA_Msk                  (1UL << ITM_TCR_TXENA_Pos)                  /*!< ITM TCR: TXENA Mask */
 
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
+#define ITM_TCR_SYNCENA_Pos                 2                                          /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                /*!< ITM TCR: SYNCENA Mask */
 
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+#define ITM_TCR_TSENA_Pos                   1                                          /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                  /*!< ITM TCR: TSENA Mask */
 
-#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
+#define ITM_TCR_ITMENA_Pos                  0                                          /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                 /*!< ITM TCR: ITM Enable bit Mask */
 
 /*@}*/ /* end of group CMSIS_ITM */
 
 
-/** \ingroup  CMSIS_core_register   
-    \defgroup CMSIS_InterruptType CMSIS Interrupt Type
-  Type definitions for the Cortex-M Interrupt Type Register
-  @{
- */
-
-/** \brief  Structure type to access the Interrupt Type Register.
- */
-typedef struct
-{
-       uint32_t RESERVED0;
-  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Control Type Register */
-#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
-  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register      */
-#else
-       uint32_t RESERVED1;
-#endif
-} InterruptType_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define IntType_ICTR_INTLINESNUM_Pos  0                                                   /*!< InterruptType ICTR: INTLINESNUM Position */
-#define IntType_ICTR_INTLINESNUM_Msk (0x1FUL << IntType_ICTR_INTLINESNUM_Pos)             /*!< InterruptType ICTR: INTLINESNUM Mask */
-
-/* Auxiliary Control Register Definitions */
-#define IntType_ACTLR_DISFOLD_Pos     2                                                   /*!< InterruptType ACTLR: DISFOLD Position */
-#define IntType_ACTLR_DISFOLD_Msk    (1UL << IntType_ACTLR_DISFOLD_Pos)                   /*!< InterruptType ACTLR: DISFOLD Mask */
-
-#define IntType_ACTLR_DISDEFWBUF_Pos  1                                                   /*!< InterruptType ACTLR: DISDEFWBUF Position */
-#define IntType_ACTLR_DISDEFWBUF_Msk (1UL << IntType_ACTLR_DISDEFWBUF_Pos)                /*!< InterruptType ACTLR: DISDEFWBUF Mask */
-
-#define IntType_ACTLR_DISMCYCINT_Pos  0                                                   /*!< InterruptType ACTLR: DISMCYCINT Position */
-#define IntType_ACTLR_DISMCYCINT_Msk (1UL << IntType_ACTLR_DISMCYCINT_Pos)                /*!< InterruptType ACTLR: DISMCYCINT Mask */
-
-/*@}*/ /* end of group CMSIS_InterruptType */
-
-
 #if (__MPU_PRESENT == 1)
-/** \ingroup  CMSIS_core_register   
-    \defgroup CMSIS_MPU CMSIS MPU
-  Type definitions for the Cortex-M Memory Protection Unit (MPU)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
   @{
  */
 
@@ -663,7 +680,7 @@
   __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
   __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
   __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;                                                
+} MPU_Type;
 
 /* MPU Type Register */
 #define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
@@ -700,23 +717,8 @@
 #define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
 
 /* MPU Region Attribute and Size Register */
-#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: XN Position */
-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: XN Mask */
-
-#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: AP Position */
-#define MPU_RASR_AP_Msk                    (7UL << MPU_RASR_AP_Pos)                       /*!< MPU RASR: AP Mask */
-
-#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: TEX Position */
-#define MPU_RASR_TEX_Msk                   (7UL << MPU_RASR_TEX_Pos)                      /*!< MPU RASR: TEX Mask */
-
-#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: Shareable bit Position */
-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: Shareable bit Mask */
-
-#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: Cacheable bit Position */
-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: Cacheable bit Mask */
-
-#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: Bufferable bit Position */
-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: Bufferable bit Mask */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
 
 #define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
 #define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
@@ -724,16 +726,16 @@
 #define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
 #define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
 
-#define MPU_RASR_ENA_Pos                     0                                            /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENA_Msk                    (0x1UL << MPU_RASR_ENA_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
 
 /*@} end of group CMSIS_MPU */
 #endif
 
 
-/** \ingroup  CMSIS_core_register   
-    \defgroup CMSIS_CoreDebug CMSIS Core Debug
-  Type definitions for the Cortex-M Core Debug Registers
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Type definitions for the Core Debug Registers
   @{
  */
 
@@ -834,28 +836,30 @@
 /*@} end of group CMSIS_CoreDebug */
 
 
-/** \ingroup  CMSIS_core_register   
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
   @{
  */
- 
+
 /* Memory mapping of Cortex-M3 Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
-#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                  */
-#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address           */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
 
-#define InterruptType       ((InterruptType_Type *) SCS_BASE)         /*!< Interrupt Type Register           */
-#define SCB                 ((SCB_Type *)           SCB_BASE)         /*!< SCB configuration struct          */
-#define SysTick             ((SysTick_Type *)       SysTick_BASE)     /*!< SysTick configuration struct      */
-#define NVIC                ((NVIC_Type *)          NVIC_BASE)        /*!< NVIC configuration struct         */
-#define ITM                 ((ITM_Type *)           ITM_BASE)         /*!< ITM configuration struct          */
-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct   */
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
 
 #if (__MPU_PRESENT == 1)
-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit            */
-  #define MPU               ((MPU_Type*)            MPU_BASE)         /*!< Memory Protection Unit            */
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
 #endif
 
 /*@} */
@@ -864,42 +868,43 @@
 
 /*******************************************************************************
  *                Hardware Abstraction Layer
- ******************************************************************************/
-/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface
   Core Function Interface contains:
   - Core NVIC Functions
   - Core SysTick Functions
   - Core Debug Functions
   - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
 */
 
 
 
 /* ##########################   NVIC functions  #################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface   
-    \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions
-  @{
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
  */
 
 /** \brief  Set Priority Grouping
 
-  This function sets the priority grouping field using the required unlock sequence.
+  The function sets the priority grouping field using the required unlock sequence.
   The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
   Only values from 0..7 are used.
   In case of a conflict between priority grouping and available
-  priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
 
-    \param [in]      PriorityGroup  Priority grouping field
+    \param [in]      PriorityGroup  Priority grouping field.
  */
 static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
 {
   uint32_t reg_value;
-  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);                         /* only values 0..7 are used          */
-  
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
+
   reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
   reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
-  reg_value  =  (reg_value                       |
-                (0x5FA << SCB_AIRCR_VECTKEY_Pos) | 
+  reg_value  =  (reg_value                                 |
+                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
                 (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
   SCB->AIRCR =  reg_value;
 }
@@ -907,10 +912,9 @@
 
 /** \brief  Get Priority Grouping
 
-  This function gets the priority grouping from NVIC Interrupt Controller.
-  Priority grouping is SCB->AIRCR [10:8] PRIGROUP field.
+  The function reads the priority grouping field from the NVIC Interrupt Controller.
 
-    \return                Priority grouping field
+    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
  */
 static __INLINE uint32_t NVIC_GetPriorityGrouping(void)
 {
@@ -920,10 +924,9 @@
 
 /** \brief  Enable External Interrupt
 
-    This function enables a device specific interupt in the NVIC interrupt controller.
-    The interrupt number cannot be a negative value. 
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
 
-    \param [in]      IRQn  Number of the external interrupt to enable
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
  */
 static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
 {
@@ -933,10 +936,9 @@
 
 /** \brief  Disable External Interrupt
 
-    This function disables a device specific interupt in the NVIC interrupt controller.
-    The interrupt number cannot be a negative value. 
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
 
-    \param [in]      IRQn  Number of the external interrupt to disable
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
  */
 static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
 {
@@ -946,12 +948,13 @@
 
 /** \brief  Get Pending Interrupt
 
-    This function reads the pending register in the NVIC and returns the pending bit
-    for the specified interrupt. 
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
 
-    \param [in]      IRQn  Number of the interrupt for get pending
-    \return             0  Interrupt status is not pending
-    \return             1  Interrupt status is pending
+    \param [in]      IRQn  Interrupt number.
+    
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
  */
 static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
 {
@@ -961,10 +964,9 @@
 
 /** \brief  Set Pending Interrupt
 
-    This function sets the pending bit for the specified interrupt. 
-    The interrupt number cannot be a negative value.
+    The function sets the pending bit of an external interrupt.
 
-    \param [in]      IRQn  Number of the interrupt for set pending
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
  */
 static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
 {
@@ -974,10 +976,9 @@
 
 /** \brief  Clear Pending Interrupt
 
-    This function clears the pending bit for the specified interrupt. 
-    The interrupt number cannot be a negative value.
+    The function clears the pending bit of an external interrupt.
 
-    \param [in]      IRQn  Number of the interrupt for clear pending
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
  */
 static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
 {
@@ -987,10 +988,12 @@
 
 /** \brief  Get Active Interrupt
 
-    This function reads the active register in NVIC and returns the active bit. 
-    \param [in]      IRQn  Number of the interrupt for get active
-    \return             0  Interrupt status is not active
-    \return             1  Interrupt status is active
+    The function reads the active register in NVIC and returns the active bit.
+    
+    \param [in]      IRQn  Interrupt number.
+    
+    \return             0  Interrupt status is not active.
+    \return             1  Interrupt status is active.
  */
 static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
 {
@@ -1000,14 +1003,12 @@
 
 /** \brief  Set Interrupt Priority
 
-    This function sets the priority for the specified interrupt. The interrupt 
-    number can be positive to specify an external (device specific) 
-    interrupt, or negative to specify an internal (core) interrupt.
+    The function sets the priority of an interrupt. 
 
-    Note: The priority cannot be set for every core interrupt.
+    \note The priority cannot be set for every core interrupt.
 
-    \param [in]      IRQn  Number of the interrupt for set priority
-    \param [in]  priority  Priority to set
+    \param [in]      IRQn  Interrupt number. 
+    \param [in]  priority  Priority to set.
  */
 static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
 {
@@ -1020,15 +1021,14 @@
 
 /** \brief  Get Interrupt Priority
 
-    This function reads the priority for the specified interrupt. The interrupt 
-    number can be positive to specify an external (device specific) 
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
     interrupt, or negative to specify an internal (core) interrupt.
 
-    The returned priority value is automatically aligned to the implemented
-    priority bits of the microcontroller.
 
-    \param [in]   IRQn  Number of the interrupt for get priority
-    \return             Interrupt Priority
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
  */
 static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
 {
@@ -1042,17 +1042,15 @@
 
 /** \brief  Encode Priority
 
-    This function encodes the priority for an interrupt with the given priority group,
-    preemptive priority value and sub priority value.
+    The function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value, and subpriority value.
     In case of a conflict between priority grouping and available
-    priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
- 
-    The returned priority value can be used for NVIC_SetPriority(...) function
+    priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
 
-    \param [in]     PriorityGroup  Used priority group
-    \param [in]   PreemptPriority  Preemptive priority value (starting from 0)
-    \param [in]       SubPriority  Sub priority value (starting from 0)
-    \return                        Encoded priority for the interrupt
+    \param [in]     PriorityGroup  Used priority group.
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+    \param [in]       SubPriority  Subpriority value (starting from 0).
+    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
  */
 static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
 {
@@ -1062,7 +1060,7 @@
 
   PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
   SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
- 
+
   return (
            ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
            ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
@@ -1072,17 +1070,15 @@
 
 /** \brief  Decode Priority
 
-    This function decodes an interrupt priority value with the given priority group to 
-    preemptive priority value and sub priority value.
+    The function decodes an interrupt priority value with a given priority group to
+    preemptive priority value and subpriority value.
     In case of a conflict between priority grouping and available
     priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
- 
-    The priority value can be retrieved with NVIC_GetPriority(...) function
- 
-    \param [in]         Priority   Priority value
-    \param [in]     PriorityGroup  Used priority group
-    \param [out] pPreemptPriority  Preemptive priority value (starting from 0)
-    \param [out]     pSubPriority  Sub priority value (starting from 0)
+
+    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+    \param [in]     PriorityGroup  Used priority group.
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+    \param [out]     pSubPriority  Subpriority value (starting from 0).
  */
 static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
 {
@@ -1092,7 +1088,7 @@
 
   PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
   SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-  
+
   *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
   *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
 }
@@ -1100,16 +1096,16 @@
 
 /** \brief  System Reset
 
-    This function initiate a system reset request to reset the MCU.
+    The function initiates a system reset request to reset the MCU.
  */
 static __INLINE void NVIC_SystemReset(void)
 {
   __DSB();                                                     /* Ensure all outstanding memory accesses included
-                                                                  buffered write are completed before reset */              
-  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      | 
-                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
                  SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
-  __DSB();                                                     /* Ensure completion of memory access */              
+  __DSB();                                                     /* Ensure completion of memory access */
   while(1);                                                    /* wait until reset */
 }
 
@@ -1118,8 +1114,9 @@
 
 
 /* ##################################    SysTick function  ############################################ */
-/** \ingroup  CMSIS_Core_FunctionInterface   
-    \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
   @{
  */
 
@@ -1127,22 +1124,28 @@
 
 /** \brief  System Tick Configuration
 
-    This function initialises the system tick timer and its interrupt and start the system tick timer.
-    Counter is in free running mode to generate periodical interrupts.
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.   
 
-    \param [in]  ticks  Number of ticks between two interrupts
-    \return          0  Function succeeded
-    \return          1  Function failed
+    \param [in]  ticks  Number of ticks between two interrupts.
+    
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+    
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the 
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> 
+    must contain a vendor-specific implementation of this function.
+
  */
 static __INLINE uint32_t SysTick_Config(uint32_t ticks)
-{ 
+{
   if (ticks > SysTick_LOAD_RELOAD_Msk)  return (1);            /* Reload value impossible */
-                                                               
+
   SysTick->LOAD  = (ticks & SysTick_LOAD_RELOAD_Msk) - 1;      /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Cortex-M0 System Interrupts */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
   SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk | 
-                   SysTick_CTRL_TICKINT_Msk   | 
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
                    SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
   return (0);                                                  /* Function successful */
 }
@@ -1154,45 +1157,44 @@
 
 
 /* ##################################### Debug In/Output function ########################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface   
-    \defgroup CMSIS_core_DebugFunctions CMSIS Core Debug Functions
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions ITM Functions
+    \brief   Functions that access the ITM debug interface.
   @{
  */
 
-extern volatile int32_t ITM_RxBuffer;                    /*!< external variable to receive characters                    */
-#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
 
 
 /** \brief  ITM Send Character
 
-    This function transmits a character via the ITM channel 0. 
-    It just returns when no debugger is connected that has booked the output.  
-    It is blocking when a debugger is connected, but the previous character send is not transmitted. 
+    The function transmits a character via the ITM channel 0, and
+    \li Just returns when no debugger is connected that has booked the output.
+    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
 
-    \param [in]     ch  Character to transmit
-    \return             Character to transmit
+    \param [in]     ch  Character to transmit.
+    
+    \returns            Character to transmit.
  */
 static __INLINE uint32_t ITM_SendChar (uint32_t ch)
 {
-  if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk)  &&      /* Trace enabled */
-      (ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
+  if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
       (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
   {
     while (ITM->PORT[0].u32 == 0);
     ITM->PORT[0].u8 = (uint8_t) ch;
-  }  
+  }
   return (ch);
 }
 
 
 /** \brief  ITM Receive Character
 
-    This function inputs a character via external variable ITM_RxBuffer. 
-    It just returns when no debugger is connected that has booked the output.  
-    It is blocking when a debugger is connected, but the previous character send is not transmitted. 
+    The function inputs a character via the external variable \ref ITM_RxBuffer.
 
-    \return             Received character
-    \return         -1  No character received
+    \return             Received character.
+    \return         -1  No character pending.
  */
 static __INLINE int32_t ITM_ReceiveChar (void) {
   int32_t ch = -1;                           /* no character available */
@@ -1201,18 +1203,17 @@
     ch = ITM_RxBuffer;
     ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
   }
-  
-  return (ch); 
+
+  return (ch);
 }
 
 
 /** \brief  ITM Check Character
 
-    This function checks external variable ITM_RxBuffer whether a character is available or not. 
-    It returns '1' if a character is available and '0' if no character is available. 
+    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
 
-    \return          0  No character available
-    \return          1  Character available
+    \return          0  No character available.
+    \return          1  Character available.
  */
 static __INLINE int32_t ITM_CheckChar (void) {
 
@@ -1232,5 +1233,3 @@
 #ifdef __cplusplus
 }
 #endif
-
-/*lint -restore */

--- a/LPC1768/GCC_ARM/core_cmFunc.h	Fri Jan 06 16:40:24 2012 +0000
+++ b/LPC1768/GCC_ARM/core_cmFunc.h	Tue Jan 10 12:00:50 2012 +0000
@@ -1,11 +1,11 @@
 /**************************************************************************//**
  * @file     core_cmFunc.h
  * @brief    CMSIS Cortex-M Core Function Access Header File
- * @version  V2.01
- * @date     06. December 2010
+ * @version  V3.00
+ * @date     09. December 2011
  *
  * @note
- * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
  *
  * @par
  * ARM Limited (ARM) is supplying this software for use with Cortex-M 
@@ -21,8 +21,9 @@
  *
  ******************************************************************************/
 
-#ifndef __CORE_CMFUNC_H__
-#define __CORE_CMFUNC_H__
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
 
 /* ###########################  Core Function Access  ########################### */
 /** \ingroup  CMSIS_Core_FunctionInterface   
@@ -30,9 +31,13 @@
   @{
  */
 
-#if defined ( __CC_ARM   ) /*------------------ RealView Compiler ----------------*/
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
 /* ARM armcc specific functions */
 
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
 /* intrinsic void __enable_irq();     */
 /* intrinsic void __disable_irq();    */
 
@@ -42,15 +47,11 @@
 
     \return               Control Register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_CONTROL(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_CONTROL(void)
 {
   register uint32_t __regControl         __ASM("control");
   return(__regControl);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Set Control Register
@@ -59,32 +60,24 @@
 
     \param [in]    control  Control Register value to set
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          void __set_CONTROL(uint32_t control);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE void __set_CONTROL(uint32_t control)
 {
   register uint32_t __regControl         __ASM("control");
   __regControl = control;
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
-/** \brief  Get ISPR Register
-
-    This function returns the content of the ISPR Register.
+/** \brief  Get IPSR Register
 
-    \return               ISPR Register value
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_IPSR(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_IPSR(void)
 {
   register uint32_t __regIPSR          __ASM("ipsr");
   return(__regIPSR);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Get APSR Register
@@ -93,15 +86,11 @@
 
     \return               APSR Register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_APSR(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_APSR(void)
 {
   register uint32_t __regAPSR          __ASM("apsr");
   return(__regAPSR);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Get xPSR Register
@@ -110,15 +99,11 @@
 
     \return               xPSR Register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_xPSR(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_xPSR(void)
 {
   register uint32_t __regXPSR          __ASM("xpsr");
   return(__regXPSR);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Get Process Stack Pointer
@@ -127,15 +112,11 @@
 
     \return               PSP Register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_PSP(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_PSP(void)
 {
   register uint32_t __regProcessStackPointer  __ASM("psp");
   return(__regProcessStackPointer);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Set Process Stack Pointer
@@ -144,15 +125,11 @@
 
     \param [in]    topOfProcStack  Process Stack Pointer value to set
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          void __set_PSP(uint32_t topOfProcStack);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE void __set_PSP(uint32_t topOfProcStack)
 {
   register uint32_t __regProcessStackPointer  __ASM("psp");
   __regProcessStackPointer = topOfProcStack;
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Get Main Stack Pointer
@@ -161,15 +138,11 @@
 
     \return               MSP Register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_MSP(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_MSP(void)
 {
   register uint32_t __regMainStackPointer     __ASM("msp");
   return(__regMainStackPointer);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Set Main Stack Pointer
@@ -178,15 +151,11 @@
 
     \param [in]    topOfMainStack  Main Stack Pointer value to set
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          void __set_MSP(uint32_t topOfMainStack);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE void __set_MSP(uint32_t topOfMainStack)
 {
   register uint32_t __regMainStackPointer     __ASM("msp");
   __regMainStackPointer = topOfMainStack;
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Get Priority Mask
@@ -195,15 +164,11 @@
 
     \return               Priority Mask value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_PRIMASK(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_PRIMASK(void)
 {
   register uint32_t __regPriMask         __ASM("primask");
   return(__regPriMask);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Set Priority Mask
@@ -212,15 +177,11 @@
 
     \param [in]    priMask  Priority Mask
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          void __set_PRIMASK(uint32_t priMask);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE void __set_PRIMASK(uint32_t priMask)
 {
   register uint32_t __regPriMask         __ASM("primask");
   __regPriMask = (priMask);
 }
-#endif /*  __ARMCC_VERSION  */ 
  
 
 #if       (__CORTEX_M >= 0x03)
@@ -247,15 +208,11 @@
 
     \return               Base Priority register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_BASEPRI(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t  __get_BASEPRI(void)
 {
   register uint32_t __regBasePri         __ASM("basepri");
   return(__regBasePri);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Set Base Priority
@@ -264,15 +221,11 @@
 
     \param [in]    basePri  Base Priority value to set
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          void __set_BASEPRI(uint32_t basePri);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE void __set_BASEPRI(uint32_t basePri)
 {
   register uint32_t __regBasePri         __ASM("basepri");
   __regBasePri = (basePri & 0xff);
 }
-#endif /*  __ARMCC_VERSION  */ 
  
 
 /** \brief  Get Fault Mask
@@ -281,15 +234,11 @@
 
     \return               Fault Mask register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_FAULTMASK(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_FAULTMASK(void)
 {
   register uint32_t __regFaultMask       __ASM("faultmask");
   return(__regFaultMask);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Set Fault Mask
@@ -298,15 +247,11 @@
 
     \param [in]    faultMask  Fault Mask value to set
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          void __set_FAULTMASK(uint32_t faultMask);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE void __set_FAULTMASK(uint32_t faultMask)
 {
   register uint32_t __regFaultMask       __ASM("faultmask");
-  __regFaultMask = (faultMask & 1);
+  __regFaultMask = (faultMask & (uint32_t)1);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 #endif /* (__CORTEX_M >= 0x03) */
 
@@ -321,7 +266,7 @@
  */
 static __INLINE uint32_t __get_FPSCR(void)
 {
-#if (__FPU_PRESENT == 1)
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
   register uint32_t __regfpscr         __ASM("fpscr");
   return(__regfpscr);
 #else
@@ -338,7 +283,7 @@
  */
 static __INLINE void __set_FPSCR(uint32_t fpscr)
 {
-#if (__FPU_PRESENT == 1)
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
   register uint32_t __regfpscr         __ASM("fpscr");
   __regfpscr = (fpscr);
 #endif
@@ -347,192 +292,12 @@
 #endif /* (__CORTEX_M == 0x04) */
 
 
- #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
 /* IAR iccarm specific functions */
 
-#if defined (__ICCARM__)
-  #include <intrinsics.h>                     /* IAR Intrinsics   */
-#endif
-
-#pragma diag_suppress=Pe940
-
-/** \brief  Enable IRQ Interrupts
-
-  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
-  Can only be executed in Privileged modes.
- */
-#define __enable_irq                              __enable_interrupt
-
-
-/** \brief  Disable IRQ Interrupts
-
-  This function disables IRQ interrupts by setting the I-bit in the CPSR.
-  Can only be executed in Privileged modes.
- */
-#define __disable_irq                             __disable_interrupt
-
-
-/* intrinsic unsigned long __get_CONTROL( void ); (see intrinsic.h) */
-/* intrinsic void __set_CONTROL( unsigned long ); (see intrinsic.h) */
-
-
-/** \brief  Get ISPR Register
-
-    This function returns the content of the ISPR Register.
-
-    \return               ISPR Register value
- */
-static uint32_t __get_IPSR(void)
-{
-  __ASM("mrs r0, ipsr");
-}
-
-
-/** \brief  Get APSR Register
-
-    This function returns the content of the APSR Register.
-
-    \return               APSR Register value
- */
-static uint32_t __get_APSR(void)
-{
-  __ASM("mrs r0, apsr");
-}
-
-
-/** \brief  Get xPSR Register
-
-    This function returns the content of the xPSR Register.
-
-    \return               xPSR Register value
- */
-static uint32_t __get_xPSR(void)
-{
-  __ASM("mrs r0, psr");           // assembler does not know "xpsr"
-}
-
-
-/** \brief  Get Process Stack Pointer
-
-    This function returns the current value of the Process Stack Pointer (PSP).
-
-    \return               PSP Register value
- */
-static uint32_t __get_PSP(void)
-{
-  __ASM("mrs r0, psp");
-}
- 
-
-/** \brief  Set Process Stack Pointer
-
-    This function assigns the given value to the Process Stack Pointer (PSP).
-
-    \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-static void __set_PSP(uint32_t topOfProcStack)
-{
-  __ASM("msr psp, r0");
-}
-
-
-/** \brief  Get Main Stack Pointer
-
-    This function returns the current value of the Main Stack Pointer (MSP).
+#include <cmsis_iar.h>
 
-    \return               MSP Register value
- */
-static uint32_t __get_MSP(void)
-{
-  __ASM("mrs r0, msp");
-}
- 
-
-/** \brief  Set Main Stack Pointer
-
-    This function assigns the given value to the Main Stack Pointer (MSP).
-
-    \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-static void __set_MSP(uint32_t topOfMainStack)
-{
-  __ASM("msr msp, r0");
-}
- 
-
-/* intrinsic unsigned long __get_PRIMASK( void ); (see intrinsic.h) */
-/* intrinsic void __set_PRIMASK( unsigned long ); (see intrinsic.h) */
- 
-
-#if       (__CORTEX_M >= 0x03)
-
-/** \brief  Enable FIQ
-
-    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-static __INLINE void __enable_fault_irq(void)
-{
-  __ASM ("cpsie f");
-}
-
-
-/** \brief  Disable FIQ
-
-    This function disables FIQ interrupts by setting the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-static __INLINE void __disable_fault_irq(void)
-{
-  __ASM ("cpsid f");
-}
-
-
-/* intrinsic unsigned long __get_BASEPRI( void );   (see intrinsic.h) */
-/* intrinsic void __set_BASEPRI( unsigned long );   (see intrinsic.h) */
-/* intrinsic unsigned long __get_FAULTMASK( void ); (see intrinsic.h) */
-/* intrinsic void __set_FAULTMASK(unsigned long);   (see intrinsic.h) */
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-#if       (__CORTEX_M == 0x04)
-
-/** \brief  Get FPSCR
-
-    This function returns the current value of the Floating Point Status/Control register.
-
-    \return               Floating Point Status/Control register value
- */
-static uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1)
-  __ASM("vmrs r0, fpscr"); 
-#else
-  return(0);
-#endif
-}
-
-
-/** \brief  Set FPSCR
-
-    This function assigns the given value to the Floating Point Status/Control register.
-
-    \param [in]    fpscr  Floating Point Status/Control value to set
- */
-static void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1)
-  __ASM("vmsr fpscr, r0");
-#endif
-}
-
-#endif /* (__CORTEX_M == 0x04) */
-
-#pragma diag_default=Pe940
-
-
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
 /* GNU gcc specific functions */
 
 /** \brief  Enable IRQ Interrupts
@@ -584,11 +349,11 @@
 }
 
 
-/** \brief  Get ISPR Register
+/** \brief  Get IPSR Register
 
-    This function returns the content of the ISPR Register.
+    This function returns the content of the IPSR Register.
 
-    \return               ISPR Register value
+    \return               IPSR Register value
  */
 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void)
 {
@@ -800,10 +565,10 @@
  */
 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void)
 {
-#if (__FPU_PRESENT == 1)
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
   uint32_t result;
 
-  __ASM volatile ("MRS %0, fpscr" : "=r" (result) );
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
   return(result);
 #else
    return(0);
@@ -819,15 +584,15 @@
  */
 __attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr)
 {
-#if (__FPU_PRESENT == 1)
-  __ASM volatile ("MSR fpscr, %0" : : "r" (fpscr) );
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );
 #endif
 }
 
 #endif /* (__CORTEX_M == 0x04) */
 
 
-#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
 /* TASKING carm specific functions */
 
 /*
@@ -841,4 +606,4 @@
 /*@} end of CMSIS_Core_RegAccFunctions */
 
 
-#endif /* __CORE_CMFUNC_H__ */
+#endif /* __CORE_CMFUNC_H */

--- a/LPC1768/GCC_ARM/core_cmInstr.h	Fri Jan 06 16:40:24 2012 +0000
+++ b/LPC1768/GCC_ARM/core_cmInstr.h	Tue Jan 10 12:00:50 2012 +0000
@@ -1,11 +1,11 @@
 /**************************************************************************//**
  * @file     core_cmInstr.h
  * @brief    CMSIS Cortex-M Core Instruction Access Header File
- * @version  V2.01
- * @date     06. December 2010
+ * @version  V3.00
+ * @date     09. December 2011
  *
  * @note
- * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
  *
  * @par
  * ARM Limited (ARM) is supplying this software for use with Cortex-M 
@@ -21,8 +21,8 @@
  *
  ******************************************************************************/
 
-#ifndef __CORE_CMINSTR_H__
-#define __CORE_CMINSTR_H__
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
 
 
 /* ##########################  Core Instruction Access  ######################### */
@@ -31,9 +31,14 @@
   @{
 */
 
-#if defined ( __CC_ARM   ) /*------------------ RealView Compiler ----------------*/
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
 /* ARM armcc specific functions */
 
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
 /** \brief  No Operation
 
     No Operation does nothing. This instruction can be used for code alignment purposes.
@@ -106,15 +111,11 @@
     \param [in]    value  Value to reverse
     \return               Reversed value
  */
-#if (__ARMCC_VERSION < 400677)
-extern uint32_t __REV16(uint32_t value);
-#else  /* (__ARMCC_VERSION >= 400677)  */
-static __INLINE __ASM uint32_t __REV16(uint32_t value)
+static __attribute__((section(".rev16_text"))) __INLINE __ASM uint32_t __REV16(uint32_t value)
 {
   rev16 r0, r0
   bx lr
 }
-#endif /* __ARMCC_VERSION  */ 
 
 
 /** \brief  Reverse byte order in signed short value
@@ -124,15 +125,11 @@
     \param [in]    value  Value to reverse
     \return               Reversed value
  */
-#if (__ARMCC_VERSION < 400677)
-extern int32_t __REVSH(int32_t value);
-#else  /* (__ARMCC_VERSION >= 400677)  */
-static __INLINE __ASM int32_t __REVSH(int32_t value)
+static __attribute__((section(".revsh_text"))) __INLINE __ASM int32_t __REVSH(int32_t value)
 {
   revsh r0, r0
   bx lr
 }
-#endif /* __ARMCC_VERSION  */ 
 
 
 #if       (__CORTEX_M >= 0x03)
@@ -218,11 +215,7 @@
     This function removes the exclusive lock which is created by LDREX.
 
  */
-#if (__ARMCC_VERSION < 400000)
-extern void __CLREX(void);
-#else  /* (__ARMCC_VERSION >= 400000)  */
 #define __CLREX                           __clrex
-#endif /* __ARMCC_VERSION  */ 
 
 
 /** \brief  Signed Saturate
@@ -260,196 +253,13 @@
 
 
 
-#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
 /* IAR iccarm specific functions */
 
-#include <intrinsics.h>                     /* IAR Intrinsics   */
-
-#pragma diag_suppress=Pe940
-
-/** \brief  No Operation
-
-    No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-#define __NOP                           __no_operation
-
-
-/** \brief  Wait For Interrupt
-
-    Wait For Interrupt is a hint instruction that suspends execution
-    until one of a number of events occurs.
- */
-static __INLINE  void __WFI(void)
-{
-  __ASM ("wfi");
-}
-
-
-/** \brief  Wait For Event
-
-    Wait For Event is a hint instruction that permits the processor to enter
-    a low-power state until one of a number of events occurs.
- */
-static __INLINE  void __WFE(void)
-{
-  __ASM ("wfe");
-}
-
-
-/** \brief  Send Event
-
-    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-static __INLINE  void __SEV(void)
-{
-  __ASM ("sev");
-}
-
-
-/* intrinsic     void __ISB(void)            (see intrinsics.h) */
-/* intrinsic     void __DSB(void)            (see intrinsics.h) */
-/* intrinsic     void __DMB(void)            (see intrinsics.h) */
-/* intrinsic uint32_t __REV(uint32_t value)  (see intrinsics.h) */
-/* intrinsic          __SSAT                 (see intrinsics.h) */
-/* intrinsic          __USAT                 (see intrinsics.h) */
-
-
-/** \brief  Reverse byte order (16 bit)
-
-    This function reverses the byte order in two unsigned short values.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-static uint32_t __REV16(uint32_t value)
-{
-  __ASM("rev16 r0, r0");
-}
-
-
-/* intrinsic uint32_t __REVSH(uint32_t value)  (see intrinsics.h */
-
-
-#if       (__CORTEX_M >= 0x03)
-
-/** \brief  Reverse bit order of value
-
-    This function reverses the bit order of the given value.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-static uint32_t __RBIT(uint32_t value)
-{
-  __ASM("rbit r0, r0");
-}
+#include <cmsis_iar.h>
 
 
-/** \brief  LDR Exclusive (8 bit)
-
-    This function performs a exclusive LDR command for 8 bit value.
-
-    \param [in]    ptr  Pointer to data
-    \return             value of type uint8_t at (*ptr)
- */
-static uint8_t __LDREXB(volatile uint8_t *addr)
-{
-  __ASM("ldrexb r0, [r0]");
-}
-
-
-/** \brief  LDR Exclusive (16 bit)
-
-    This function performs a exclusive LDR command for 16 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint16_t at (*ptr)
- */
-static uint16_t __LDREXH(volatile uint16_t *addr)
-{
-  __ASM("ldrexh r0, [r0]");
-}
-
-
-/** \brief  LDR Exclusive (32 bit)
-
-    This function performs a exclusive LDR command for 32 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint32_t at (*ptr)
- */
-/* intrinsic unsigned long __LDREX(unsigned long *)  (see intrinsics.h) */
-static uint32_t __LDREXW(volatile uint32_t *addr)
-{
-  __ASM("ldrex r0, [r0]");
-}
-
-
-/** \brief  STR Exclusive (8 bit)
-
-    This function performs a exclusive STR command for 8 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-static uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
-{
-  __ASM("strexb r0, r0, [r1]");
-}
-
-
-/** \brief  STR Exclusive (16 bit)
-
-    This function performs a exclusive STR command for 16 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-static uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
-{
-  __ASM("strexh r0, r0, [r1]");
-}
-
-
-/** \brief  STR Exclusive (32 bit)
-
-    This function performs a exclusive STR command for 32 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-/* intrinsic unsigned long __STREX(unsigned long, unsigned long)  (see intrinsics.h )*/
-static uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
-{
-  __ASM("strex r0, r0, [r1]");
-}
-
-
-/** \brief  Remove the exclusive lock
-
-    This function removes the exclusive lock which is created by LDREX.
-
- */
-static __INLINE void __CLREX(void)
-{
-  __ASM ("clrex");
-}
-
-/* intrinsic   unsigned char __CLZ( unsigned long )      (see intrinsics.h) */
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-#pragma diag_default=Pe940
-
-
-
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
 /* GNU gcc specific functions */
 
 /** \brief  No Operation
@@ -655,7 +465,7 @@
 {
    uint32_t result;
   
-   __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+   __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
    return(result);
 }
 
@@ -673,7 +483,7 @@
 {
    uint32_t result;
   
-   __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+   __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
    return(result);
 }
 
@@ -691,7 +501,7 @@
 {
    uint32_t result;
   
-   __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+   __ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
    return(result);
 }
 
@@ -759,12 +569,12 @@
 
 
 
-#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
 /* TASKING carm specific functions */
 
 /*
  * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
  * Including the CMSIS ones.
  */
 
@@ -772,4 +582,4 @@
 
 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
 
-#endif /* __CORE_CMINSTR_H__ */
+#endif /* __CORE_CMINSTR_H */

Binary file LPC1768/GCC_ARM/libcapi.a has changed

Binary file LPC1768/GCC_ARM/libmbed.a has changed

--- a/LPC1768/GCC_CR/core_cm3.h	Fri Jan 06 16:40:24 2012 +0000
+++ b/LPC1768/GCC_CR/core_cm3.h	Tue Jan 10 12:00:50 2012 +0000
@@ -1,16 +1,16 @@
 /**************************************************************************//**
  * @file     core_cm3.h
  * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
- * @version  V2.01
- * @date     06. December 2010
+ * @version  V3.00
+ * @date     09. December 2011
  *
  * @note
- * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
  *
  * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M 
- * processor based microcontrollers.  This file can be freely distributed 
- * within development tools that are supporting such ARM based processors. 
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers.  This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
  *
  * @par
  * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
@@ -20,106 +20,144 @@
  * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
  *
  ******************************************************************************/
-#if defined ( __ICCARM__ )                   
+#if defined ( __ICCARM__ )
  #pragma system_include  /* treat file as system include file for MISRA check */
 #endif
 
 #ifdef __cplusplus
  extern "C" {
-#endif 
+#endif
 
 #ifndef __CORE_CM3_H_GENERIC
 #define __CORE_CM3_H_GENERIC
 
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+  
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'. 
 
-/** \mainpage CMSIS Cortex-M3
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
    
-  This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer.
-  It consists of:
- 
-     - Cortex-M Core Register Definitions
-     - Cortex-M functions
-     - Cortex-M instructions
- 
-  The CMSIS Cortex-M3 Core Peripheral Access Layer contains C and assembly functions that ease 
-  access to the Cortex-M Core
- */ 
-
-/** \defgroup CMSIS_LintCinfiguration CMSIS Lint Configuration
-  List of Lint messages which will be suppressed and not shown:
-    - not yet checked
-  .
-  Note:  To re-enable a Message, insert a space before 'lint' *
- 
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code. 
  */
 
 
 /*******************************************************************************
  *                 CMSIS definitions
  ******************************************************************************/
-/** \defgroup CMSIS_core_definitions CMSIS Core Definitions
-  This file defines all structures and symbols for CMSIS core:
-   - CMSIS version number
-   - Cortex-M core 
-   - Cortex-M core Revision Number
+/** \ingroup Cortex_M3
   @{
  */
 
 /*  CMSIS CM3 definitions */
-#define __CM3_CMSIS_VERSION_MAIN  (0x02)                                                       /*!< [31:16] CMSIS HAL main version */
-#define __CM3_CMSIS_VERSION_SUB   (0x00)                                                       /*!< [15:0]  CMSIS HAL sub version  */
-#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number       */
+#define __CM3_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM3_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | \
+                                    __CM3_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
 
-#define __CORTEX_M                (0x03)                                                       /*!< Cortex core                    */
+#define __CORTEX_M                (0x03)                                   /*!< Cortex-M Core                    */
 
 
-#if defined ( __CC_ARM   )
+#if   defined ( __CC_ARM )
   #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
   #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
 
 #elif defined ( __ICCARM__ )
   #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */
-  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
+  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
 
-#elif defined   (  __GNUC__  )
+#elif defined ( __GNUC__ )
   #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
   #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
 
-#elif defined   (  __TASKING__  )
+#elif defined ( __TASKING__ )
   #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
   #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
 
 #endif
 
-#include <stdint.h>                      /*!< standard types definitions                      */
-#include "core_cmInstr.h"                /*!< Core Instruction Access                         */
-#include "core_cmFunc.h"                 /*!< Core Function Access                            */
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+    /* add preprocessor checks */
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
 
 #endif /* __CORE_CM3_H_GENERIC */
 
-
 #ifndef __CMSIS_GENERIC
 
 #ifndef __CORE_CM3_H_DEPENDANT
 #define __CORE_CM3_H_DEPENDANT
 
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM3_REV
+    #define __CM3_REV               0x0200
+    #warning "__CM3_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          4
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
 /* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+ 
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
 #ifdef __cplusplus
-  #define     __I     volatile           /*!< defines 'read only' permissions                 */
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
 #else
-  #define     __I     volatile const     /*!< defines 'read only' permissions                 */
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
 #endif
-#define     __O     volatile             /*!< defines 'write only' permissions                */
-#define     __IO    volatile             /*!< defines 'read / write' permissions              */
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
 
-/*@} end of group CMSIS_core_definitions */
+/*@} end of group Cortex_M3 */
 
 
 
 /*******************************************************************************
  *                 Register Abstraction
- ******************************************************************************/
-/** \defgroup CMSIS_core_register CMSIS Core Register
   Core Register contain:
   - Core Register
   - Core NVIC Register
@@ -127,11 +165,14 @@
   - Core SysTick Register
   - Core Debug Register
   - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
 */
 
-/** \ingroup  CMSIS_core_register   
-    \defgroup CMSIS_CORE CMSIS Core
-  Type definitions for the Cortex-M Core Registers
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
   @{
  */
 
@@ -154,7 +195,7 @@
     uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
     uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
   } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */ 
+  uint32_t w;                            /*!< Type      used for word access                  */
 } APSR_Type;
 
 
@@ -214,9 +255,9 @@
 /*@} end of group CMSIS_CORE */
 
 
-/** \ingroup  CMSIS_core_register   
-    \defgroup CMSIS_NVIC CMSIS NVIC
-  Type definitions for the Cortex-M NVIC Registers
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
   @{
  */
 
@@ -225,26 +266,30 @@
 typedef struct
 {
   __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
-       uint32_t RESERVED0[24];                                   
+       uint32_t RESERVED0[24];
   __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
-       uint32_t RSERVED1[24];                                    
+       uint32_t RSERVED1[24];
   __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
-       uint32_t RESERVED2[24];                                   
+       uint32_t RESERVED2[24];
   __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
-       uint32_t RESERVED3[24];                                   
+       uint32_t RESERVED3[24];
   __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
-       uint32_t RESERVED4[56];                                   
+       uint32_t RESERVED4[56];
   __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
-       uint32_t RESERVED5[644];                                  
+       uint32_t RESERVED5[644];
   __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
-}  NVIC_Type;                                               
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
 
 /*@} end of group CMSIS_NVIC */
 
 
-/** \ingroup  CMSIS_core_register   
-    \defgroup CMSIS_SCB CMSIS SCB
-  Type definitions for the Cortex-M System Control Block Registers
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
   @{
  */
 
@@ -252,26 +297,28 @@
  */
 typedef struct
 {
-  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPU ID Base Register                                  */
-  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control State Register                      */
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
   __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
-  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt / Reset Control Register        */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
   __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
   __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
   __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
   __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
   __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
-  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  Hard Fault Status Register                            */
+  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
   __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
-  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  Mem Manage Address Register                           */
-  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  Bus Fault Address Register                            */
+  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
   __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
   __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
   __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
   __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
   __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
-  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  ISA Feature Register                                  */
-} SCB_Type;                                                
+  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+       uint32_t RESERVED0[5];
+  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+} SCB_Type;
 
 /* SCB CPUID Register Definitions */
 #define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
@@ -280,6 +327,9 @@
 #define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
 #define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
 
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
 #define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
 #define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
 
@@ -317,12 +367,17 @@
 #define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
 #define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
 
-/* SCB Interrupt Control State Register Definitions */
+/* SCB Vector Table Offset Register Definitions */
+#if (__CM3_REV < 0x0201)                   /* core r2p1 */
 #define SCB_VTOR_TBLBASE_Pos               29                                             /*!< SCB VTOR: TBLBASE Position */
 #define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
 
 #define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
 #define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+#endif
 
 /* SCB Application Interrupt and Reset Control Register Definitions */
 #define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
@@ -408,7 +463,7 @@
 
 #define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
 #define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
-                                     
+
 #define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
 #define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
 
@@ -457,9 +512,46 @@
 /*@} end of group CMSIS_SCB */
 
 
-/** \ingroup  CMSIS_core_register   
-    \defgroup CMSIS_SysTick CMSIS SysTick
-  Type definitions for the Cortex-M System Timer Registers
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register      */
+#else
+       uint32_t RESERVED1[1];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
   @{
  */
 
@@ -507,9 +599,9 @@
 /*@} end of group CMSIS_SysTick */
 
 
-/** \ingroup  CMSIS_core_register   
-    \defgroup CMSIS_ITM CMSIS ITM
-  Type definitions for the Cortex-M Instrumentation Trace Macrocell (ITM)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
   @{
  */
 
@@ -517,134 +609,59 @@
  */
 typedef struct
 {
-  __O  union  
+  __O  union
   {
     __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
     __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
     __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
   }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
-       uint32_t RESERVED0[864];                                 
-  __IO uint32_t TER;                     /*!< Offset:       (R/W)  ITM Trace Enable Register                 */
-       uint32_t RESERVED1[15];                                  
-  __IO uint32_t TPR;                     /*!< Offset:       (R/W)  ITM Trace Privilege Register              */
-       uint32_t RESERVED2[15];                                  
-  __IO uint32_t TCR;                     /*!< Offset:       (R/W)  ITM Trace Control Register                */
-       uint32_t RESERVED3[29];                                  
-  __IO uint32_t IWR;                     /*!< Offset:       (R/W)  ITM Integration Write Register            */
-  __IO uint32_t IRR;                     /*!< Offset:       (R/W)  ITM Integration Read Register             */
-  __IO uint32_t IMCR;                    /*!< Offset:       (R/W)  ITM Integration Mode Control Register     */
-       uint32_t RESERVED4[43];                                  
-  __IO uint32_t LAR;                     /*!< Offset:       (R/W)  ITM Lock Access Register                  */
-  __IO uint32_t LSR;                     /*!< Offset:       (R/W)  ITM Lock Status Register                  */
-       uint32_t RESERVED5[6];                                   
-  __I  uint32_t PID4;                    /*!< Offset:       (R/ )  ITM Peripheral Identification Register #4 */
-  __I  uint32_t PID5;                    /*!< Offset:       (R/ )  ITM Peripheral Identification Register #5 */
-  __I  uint32_t PID6;                    /*!< Offset:       (R/ )  ITM Peripheral Identification Register #6 */
-  __I  uint32_t PID7;                    /*!< Offset:       (R/ )  ITM Peripheral Identification Register #7 */
-  __I  uint32_t PID0;                    /*!< Offset:       (R/ )  ITM Peripheral Identification Register #0 */
-  __I  uint32_t PID1;                    /*!< Offset:       (R/ )  ITM Peripheral Identification Register #1 */
-  __I  uint32_t PID2;                    /*!< Offset:       (R/ )  ITM Peripheral Identification Register #2 */
-  __I  uint32_t PID3;                    /*!< Offset:       (R/ )  ITM Peripheral Identification Register #3 */
-  __I  uint32_t CID0;                    /*!< Offset:       (R/ )  ITM Component  Identification Register #0 */
-  __I  uint32_t CID1;                    /*!< Offset:       (R/ )  ITM Component  Identification Register #1 */
-  __I  uint32_t CID2;                    /*!< Offset:       (R/ )  ITM Component  Identification Register #2 */
-  __I  uint32_t CID3;                    /*!< Offset:       (R/ )  ITM Component  Identification Register #3 */
-} ITM_Type;                                                
+       uint32_t RESERVED0[864];
+  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+       uint32_t RESERVED1[15];
+  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+       uint32_t RESERVED2[15];
+  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+} ITM_Type;
 
 /* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
+#define ITM_TPR_PRIVMASK_Pos                0                                          /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)             /*!< ITM TPR: PRIVMASK Mask */
 
 /* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+#define ITM_TCR_BUSY_Pos                   23                                          /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                   /*!< ITM TCR: BUSY Mask */
 
-#define ITM_TCR_ATBID_Pos                  16                                             /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_ATBID_Msk                  (0x7FUL << ITM_TCR_ATBID_Pos)                  /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+#define ITM_TCR_TraceBusID_Pos             16                                          /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)          /*!< ITM TCR: ATBID Mask */
 
-#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+#define ITM_TCR_GTSFREQ_Pos                10                                          /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                /*!< ITM TCR: Global timestamp frequency Mask */
 
-#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+#define ITM_TCR_TSPrescale_Pos              8                                          /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)             /*!< ITM TCR: TSPrescale Mask */
 
-#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
+#define ITM_TCR_SWOENA_Pos                  4                                          /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                 /*!< ITM TCR: SWOENA Mask */
 
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
+#define ITM_TCR_TXENA_Pos                   3                                          /*!< ITM TCR: TXENA Position */
+#define ITM_TCR_TXENA_Msk                  (1UL << ITM_TCR_TXENA_Pos)                  /*!< ITM TCR: TXENA Mask */
 
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
+#define ITM_TCR_SYNCENA_Pos                 2                                          /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                /*!< ITM TCR: SYNCENA Mask */
 
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+#define ITM_TCR_TSENA_Pos                   1                                          /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                  /*!< ITM TCR: TSENA Mask */
 
-#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
+#define ITM_TCR_ITMENA_Pos                  0                                          /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                 /*!< ITM TCR: ITM Enable bit Mask */
 
 /*@}*/ /* end of group CMSIS_ITM */
 
 
-/** \ingroup  CMSIS_core_register   
-    \defgroup CMSIS_InterruptType CMSIS Interrupt Type
-  Type definitions for the Cortex-M Interrupt Type Register
-  @{
- */
-
-/** \brief  Structure type to access the Interrupt Type Register.
- */
-typedef struct
-{
-       uint32_t RESERVED0;
-  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Control Type Register */
-#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
-  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register      */
-#else
-       uint32_t RESERVED1;
-#endif
-} InterruptType_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define IntType_ICTR_INTLINESNUM_Pos  0                                                   /*!< InterruptType ICTR: INTLINESNUM Position */
-#define IntType_ICTR_INTLINESNUM_Msk (0x1FUL << IntType_ICTR_INTLINESNUM_Pos)             /*!< InterruptType ICTR: INTLINESNUM Mask */
-
-/* Auxiliary Control Register Definitions */
-#define IntType_ACTLR_DISFOLD_Pos     2                                                   /*!< InterruptType ACTLR: DISFOLD Position */
-#define IntType_ACTLR_DISFOLD_Msk    (1UL << IntType_ACTLR_DISFOLD_Pos)                   /*!< InterruptType ACTLR: DISFOLD Mask */
-
-#define IntType_ACTLR_DISDEFWBUF_Pos  1                                                   /*!< InterruptType ACTLR: DISDEFWBUF Position */
-#define IntType_ACTLR_DISDEFWBUF_Msk (1UL << IntType_ACTLR_DISDEFWBUF_Pos)                /*!< InterruptType ACTLR: DISDEFWBUF Mask */
-
-#define IntType_ACTLR_DISMCYCINT_Pos  0                                                   /*!< InterruptType ACTLR: DISMCYCINT Position */
-#define IntType_ACTLR_DISMCYCINT_Msk (1UL << IntType_ACTLR_DISMCYCINT_Pos)                /*!< InterruptType ACTLR: DISMCYCINT Mask */
-
-/*@}*/ /* end of group CMSIS_InterruptType */
-
-
 #if (__MPU_PRESENT == 1)
-/** \ingroup  CMSIS_core_register   
-    \defgroup CMSIS_MPU CMSIS MPU
-  Type definitions for the Cortex-M Memory Protection Unit (MPU)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
   @{
  */
 
@@ -663,7 +680,7 @@
   __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
   __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
   __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;                                                
+} MPU_Type;
 
 /* MPU Type Register */
 #define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
@@ -700,23 +717,8 @@
 #define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
 
 /* MPU Region Attribute and Size Register */
-#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: XN Position */
-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: XN Mask */
-
-#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: AP Position */
-#define MPU_RASR_AP_Msk                    (7UL << MPU_RASR_AP_Pos)                       /*!< MPU RASR: AP Mask */
-
-#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: TEX Position */
-#define MPU_RASR_TEX_Msk                   (7UL << MPU_RASR_TEX_Pos)                      /*!< MPU RASR: TEX Mask */
-
-#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: Shareable bit Position */
-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: Shareable bit Mask */
-
-#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: Cacheable bit Position */
-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: Cacheable bit Mask */
-
-#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: Bufferable bit Position */
-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: Bufferable bit Mask */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
 
 #define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
 #define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
@@ -724,16 +726,16 @@
 #define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
 #define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
 
-#define MPU_RASR_ENA_Pos                     0                                            /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENA_Msk                    (0x1UL << MPU_RASR_ENA_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
 
 /*@} end of group CMSIS_MPU */
 #endif
 
 
-/** \ingroup  CMSIS_core_register   
-    \defgroup CMSIS_CoreDebug CMSIS Core Debug
-  Type definitions for the Cortex-M Core Debug Registers
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Type definitions for the Core Debug Registers
   @{
  */
 
@@ -834,28 +836,30 @@
 /*@} end of group CMSIS_CoreDebug */
 
 
-/** \ingroup  CMSIS_core_register   
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
   @{
  */
- 
+
 /* Memory mapping of Cortex-M3 Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
-#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                  */
-#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address           */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
 
-#define InterruptType       ((InterruptType_Type *) SCS_BASE)         /*!< Interrupt Type Register           */
-#define SCB                 ((SCB_Type *)           SCB_BASE)         /*!< SCB configuration struct          */
-#define SysTick             ((SysTick_Type *)       SysTick_BASE)     /*!< SysTick configuration struct      */
-#define NVIC                ((NVIC_Type *)          NVIC_BASE)        /*!< NVIC configuration struct         */
-#define ITM                 ((ITM_Type *)           ITM_BASE)         /*!< ITM configuration struct          */
-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct   */
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
 
 #if (__MPU_PRESENT == 1)
-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit            */
-  #define MPU               ((MPU_Type*)            MPU_BASE)         /*!< Memory Protection Unit            */
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
 #endif
 
 /*@} */
@@ -864,42 +868,43 @@
 
 /*******************************************************************************
  *                Hardware Abstraction Layer
- ******************************************************************************/
-/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface
   Core Function Interface contains:
   - Core NVIC Functions
   - Core SysTick Functions
   - Core Debug Functions
   - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
 */
 
 
 
 /* ##########################   NVIC functions  #################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface   
-    \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions
-  @{
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
  */
 
 /** \brief  Set Priority Grouping
 
-  This function sets the priority grouping field using the required unlock sequence.
+  The function sets the priority grouping field using the required unlock sequence.
   The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
   Only values from 0..7 are used.
   In case of a conflict between priority grouping and available
-  priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
 
-    \param [in]      PriorityGroup  Priority grouping field
+    \param [in]      PriorityGroup  Priority grouping field.
  */
 static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
 {
   uint32_t reg_value;
-  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);                         /* only values 0..7 are used          */
-  
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
+
   reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
   reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
-  reg_value  =  (reg_value                       |
-                (0x5FA << SCB_AIRCR_VECTKEY_Pos) | 
+  reg_value  =  (reg_value                                 |
+                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
                 (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
   SCB->AIRCR =  reg_value;
 }
@@ -907,10 +912,9 @@
 
 /** \brief  Get Priority Grouping
 
-  This function gets the priority grouping from NVIC Interrupt Controller.
-  Priority grouping is SCB->AIRCR [10:8] PRIGROUP field.
+  The function reads the priority grouping field from the NVIC Interrupt Controller.
 
-    \return                Priority grouping field
+    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
  */
 static __INLINE uint32_t NVIC_GetPriorityGrouping(void)
 {
@@ -920,10 +924,9 @@
 
 /** \brief  Enable External Interrupt
 
-    This function enables a device specific interupt in the NVIC interrupt controller.
-    The interrupt number cannot be a negative value. 
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
 
-    \param [in]      IRQn  Number of the external interrupt to enable
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
  */
 static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
 {
@@ -933,10 +936,9 @@
 
 /** \brief  Disable External Interrupt
 
-    This function disables a device specific interupt in the NVIC interrupt controller.
-    The interrupt number cannot be a negative value. 
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
 
-    \param [in]      IRQn  Number of the external interrupt to disable
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
  */
 static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
 {
@@ -946,12 +948,13 @@
 
 /** \brief  Get Pending Interrupt
 
-    This function reads the pending register in the NVIC and returns the pending bit
-    for the specified interrupt. 
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
 
-    \param [in]      IRQn  Number of the interrupt for get pending
-    \return             0  Interrupt status is not pending
-    \return             1  Interrupt status is pending
+    \param [in]      IRQn  Interrupt number.
+    
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
  */
 static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
 {
@@ -961,10 +964,9 @@
 
 /** \brief  Set Pending Interrupt
 
-    This function sets the pending bit for the specified interrupt. 
-    The interrupt number cannot be a negative value.
+    The function sets the pending bit of an external interrupt.
 
-    \param [in]      IRQn  Number of the interrupt for set pending
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
  */
 static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
 {
@@ -974,10 +976,9 @@
 
 /** \brief  Clear Pending Interrupt
 
-    This function clears the pending bit for the specified interrupt. 
-    The interrupt number cannot be a negative value.
+    The function clears the pending bit of an external interrupt.
 
-    \param [in]      IRQn  Number of the interrupt for clear pending
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
  */
 static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
 {
@@ -987,10 +988,12 @@
 
 /** \brief  Get Active Interrupt
 
-    This function reads the active register in NVIC and returns the active bit. 
-    \param [in]      IRQn  Number of the interrupt for get active
-    \return             0  Interrupt status is not active
-    \return             1  Interrupt status is active
+    The function reads the active register in NVIC and returns the active bit.
+    
+    \param [in]      IRQn  Interrupt number.
+    
+    \return             0  Interrupt status is not active.
+    \return             1  Interrupt status is active.
  */
 static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
 {
@@ -1000,14 +1003,12 @@
 
 /** \brief  Set Interrupt Priority
 
-    This function sets the priority for the specified interrupt. The interrupt 
-    number can be positive to specify an external (device specific) 
-    interrupt, or negative to specify an internal (core) interrupt.
+    The function sets the priority of an interrupt. 
 
-    Note: The priority cannot be set for every core interrupt.
+    \note The priority cannot be set for every core interrupt.
 
-    \param [in]      IRQn  Number of the interrupt for set priority
-    \param [in]  priority  Priority to set
+    \param [in]      IRQn  Interrupt number. 
+    \param [in]  priority  Priority to set.
  */
 static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
 {
@@ -1020,15 +1021,14 @@
 
 /** \brief  Get Interrupt Priority
 
-    This function reads the priority for the specified interrupt. The interrupt 
-    number can be positive to specify an external (device specific) 
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
     interrupt, or negative to specify an internal (core) interrupt.
 
-    The returned priority value is automatically aligned to the implemented
-    priority bits of the microcontroller.
 
-    \param [in]   IRQn  Number of the interrupt for get priority
-    \return             Interrupt Priority
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
  */
 static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
 {
@@ -1042,17 +1042,15 @@
 
 /** \brief  Encode Priority
 
-    This function encodes the priority for an interrupt with the given priority group,
-    preemptive priority value and sub priority value.
+    The function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value, and subpriority value.
     In case of a conflict between priority grouping and available
-    priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
- 
-    The returned priority value can be used for NVIC_SetPriority(...) function
+    priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
 
-    \param [in]     PriorityGroup  Used priority group
-    \param [in]   PreemptPriority  Preemptive priority value (starting from 0)
-    \param [in]       SubPriority  Sub priority value (starting from 0)
-    \return                        Encoded priority for the interrupt
+    \param [in]     PriorityGroup  Used priority group.
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+    \param [in]       SubPriority  Subpriority value (starting from 0).
+    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
  */
 static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
 {
@@ -1062,7 +1060,7 @@
 
   PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
   SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
- 
+
   return (
            ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
            ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
@@ -1072,17 +1070,15 @@
 
 /** \brief  Decode Priority
 
-    This function decodes an interrupt priority value with the given priority group to 
-    preemptive priority value and sub priority value.
+    The function decodes an interrupt priority value with a given priority group to
+    preemptive priority value and subpriority value.
     In case of a conflict between priority grouping and available
     priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
- 
-    The priority value can be retrieved with NVIC_GetPriority(...) function
- 
-    \param [in]         Priority   Priority value
-    \param [in]     PriorityGroup  Used priority group
-    \param [out] pPreemptPriority  Preemptive priority value (starting from 0)
-    \param [out]     pSubPriority  Sub priority value (starting from 0)
+
+    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+    \param [in]     PriorityGroup  Used priority group.
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+    \param [out]     pSubPriority  Subpriority value (starting from 0).
  */
 static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
 {
@@ -1092,7 +1088,7 @@
 
   PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
   SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-  
+
   *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
   *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
 }
@@ -1100,16 +1096,16 @@
 
 /** \brief  System Reset
 
-    This function initiate a system reset request to reset the MCU.
+    The function initiates a system reset request to reset the MCU.
  */
 static __INLINE void NVIC_SystemReset(void)
 {
   __DSB();                                                     /* Ensure all outstanding memory accesses included
-                                                                  buffered write are completed before reset */              
-  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      | 
-                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
                  SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
-  __DSB();                                                     /* Ensure completion of memory access */              
+  __DSB();                                                     /* Ensure completion of memory access */
   while(1);                                                    /* wait until reset */
 }
 
@@ -1118,8 +1114,9 @@
 
 
 /* ##################################    SysTick function  ############################################ */
-/** \ingroup  CMSIS_Core_FunctionInterface   
-    \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
   @{
  */
 
@@ -1127,22 +1124,28 @@
 
 /** \brief  System Tick Configuration
 
-    This function initialises the system tick timer and its interrupt and start the system tick timer.
-    Counter is in free running mode to generate periodical interrupts.
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.   
 
-    \param [in]  ticks  Number of ticks between two interrupts
-    \return          0  Function succeeded
-    \return          1  Function failed
+    \param [in]  ticks  Number of ticks between two interrupts.
+    
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+    
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the 
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> 
+    must contain a vendor-specific implementation of this function.
+
  */
 static __INLINE uint32_t SysTick_Config(uint32_t ticks)
-{ 
+{
   if (ticks > SysTick_LOAD_RELOAD_Msk)  return (1);            /* Reload value impossible */
-                                                               
+
   SysTick->LOAD  = (ticks & SysTick_LOAD_RELOAD_Msk) - 1;      /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Cortex-M0 System Interrupts */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
   SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk | 
-                   SysTick_CTRL_TICKINT_Msk   | 
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
                    SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
   return (0);                                                  /* Function successful */
 }
@@ -1154,45 +1157,44 @@
 
 
 /* ##################################### Debug In/Output function ########################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface   
-    \defgroup CMSIS_core_DebugFunctions CMSIS Core Debug Functions
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions ITM Functions
+    \brief   Functions that access the ITM debug interface.
   @{
  */
 
-extern volatile int32_t ITM_RxBuffer;                    /*!< external variable to receive characters                    */
-#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
 
 
 /** \brief  ITM Send Character
 
-    This function transmits a character via the ITM channel 0. 
-    It just returns when no debugger is connected that has booked the output.  
-    It is blocking when a debugger is connected, but the previous character send is not transmitted. 
+    The function transmits a character via the ITM channel 0, and
+    \li Just returns when no debugger is connected that has booked the output.
+    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
 
-    \param [in]     ch  Character to transmit
-    \return             Character to transmit
+    \param [in]     ch  Character to transmit.
+    
+    \returns            Character to transmit.
  */
 static __INLINE uint32_t ITM_SendChar (uint32_t ch)
 {
-  if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk)  &&      /* Trace enabled */
-      (ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
+  if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
       (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
   {
     while (ITM->PORT[0].u32 == 0);
     ITM->PORT[0].u8 = (uint8_t) ch;
-  }  
+  }
   return (ch);
 }
 
 
 /** \brief  ITM Receive Character
 
-    This function inputs a character via external variable ITM_RxBuffer. 
-    It just returns when no debugger is connected that has booked the output.  
-    It is blocking when a debugger is connected, but the previous character send is not transmitted. 
+    The function inputs a character via the external variable \ref ITM_RxBuffer.
 
-    \return             Received character
-    \return         -1  No character received
+    \return             Received character.
+    \return         -1  No character pending.
  */
 static __INLINE int32_t ITM_ReceiveChar (void) {
   int32_t ch = -1;                           /* no character available */
@@ -1201,18 +1203,17 @@
     ch = ITM_RxBuffer;
     ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
   }
-  
-  return (ch); 
+
+  return (ch);
 }
 
 
 /** \brief  ITM Check Character
 
-    This function checks external variable ITM_RxBuffer whether a character is available or not. 
-    It returns '1' if a character is available and '0' if no character is available. 
+    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
 
-    \return          0  No character available
-    \return          1  Character available
+    \return          0  No character available.
+    \return          1  Character available.
  */
 static __INLINE int32_t ITM_CheckChar (void) {
 
@@ -1232,5 +1233,3 @@
 #ifdef __cplusplus
 }
 #endif
-
-/*lint -restore */

--- a/LPC1768/GCC_CR/core_cmFunc.h	Fri Jan 06 16:40:24 2012 +0000
+++ b/LPC1768/GCC_CR/core_cmFunc.h	Tue Jan 10 12:00:50 2012 +0000
@@ -1,11 +1,11 @@
 /**************************************************************************//**
  * @file     core_cmFunc.h
  * @brief    CMSIS Cortex-M Core Function Access Header File
- * @version  V2.01
- * @date     06. December 2010
+ * @version  V3.00
+ * @date     09. December 2011
  *
  * @note
- * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
  *
  * @par
  * ARM Limited (ARM) is supplying this software for use with Cortex-M 
@@ -21,8 +21,9 @@
  *
  ******************************************************************************/
 
-#ifndef __CORE_CMFUNC_H__
-#define __CORE_CMFUNC_H__
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
 
 /* ###########################  Core Function Access  ########################### */
 /** \ingroup  CMSIS_Core_FunctionInterface   
@@ -30,9 +31,13 @@
   @{
  */
 
-#if defined ( __CC_ARM   ) /*------------------ RealView Compiler ----------------*/
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
 /* ARM armcc specific functions */
 
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
 /* intrinsic void __enable_irq();     */
 /* intrinsic void __disable_irq();    */
 
@@ -42,15 +47,11 @@
 
     \return               Control Register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_CONTROL(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_CONTROL(void)
 {
   register uint32_t __regControl         __ASM("control");
   return(__regControl);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Set Control Register
@@ -59,32 +60,24 @@
 
     \param [in]    control  Control Register value to set
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          void __set_CONTROL(uint32_t control);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE void __set_CONTROL(uint32_t control)
 {
   register uint32_t __regControl         __ASM("control");
   __regControl = control;
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
-/** \brief  Get ISPR Register
-
-    This function returns the content of the ISPR Register.
+/** \brief  Get IPSR Register
 
-    \return               ISPR Register value
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_IPSR(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_IPSR(void)
 {
   register uint32_t __regIPSR          __ASM("ipsr");
   return(__regIPSR);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Get APSR Register
@@ -93,15 +86,11 @@
 
     \return               APSR Register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_APSR(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_APSR(void)
 {
   register uint32_t __regAPSR          __ASM("apsr");
   return(__regAPSR);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Get xPSR Register
@@ -110,15 +99,11 @@
 
     \return               xPSR Register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_xPSR(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_xPSR(void)
 {
   register uint32_t __regXPSR          __ASM("xpsr");
   return(__regXPSR);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Get Process Stack Pointer
@@ -127,15 +112,11 @@
 
     \return               PSP Register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_PSP(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_PSP(void)
 {
   register uint32_t __regProcessStackPointer  __ASM("psp");
   return(__regProcessStackPointer);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Set Process Stack Pointer
@@ -144,15 +125,11 @@
 
     \param [in]    topOfProcStack  Process Stack Pointer value to set
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          void __set_PSP(uint32_t topOfProcStack);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE void __set_PSP(uint32_t topOfProcStack)
 {
   register uint32_t __regProcessStackPointer  __ASM("psp");
   __regProcessStackPointer = topOfProcStack;
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Get Main Stack Pointer
@@ -161,15 +138,11 @@
 
     \return               MSP Register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_MSP(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_MSP(void)
 {
   register uint32_t __regMainStackPointer     __ASM("msp");
   return(__regMainStackPointer);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Set Main Stack Pointer
@@ -178,15 +151,11 @@
 
     \param [in]    topOfMainStack  Main Stack Pointer value to set
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          void __set_MSP(uint32_t topOfMainStack);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE void __set_MSP(uint32_t topOfMainStack)
 {
   register uint32_t __regMainStackPointer     __ASM("msp");
   __regMainStackPointer = topOfMainStack;
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Get Priority Mask
@@ -195,15 +164,11 @@
 
     \return               Priority Mask value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_PRIMASK(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_PRIMASK(void)
 {
   register uint32_t __regPriMask         __ASM("primask");
   return(__regPriMask);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Set Priority Mask
@@ -212,15 +177,11 @@
 
     \param [in]    priMask  Priority Mask
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          void __set_PRIMASK(uint32_t priMask);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE void __set_PRIMASK(uint32_t priMask)
 {
   register uint32_t __regPriMask         __ASM("primask");
   __regPriMask = (priMask);
 }
-#endif /*  __ARMCC_VERSION  */ 
  
 
 #if       (__CORTEX_M >= 0x03)
@@ -247,15 +208,11 @@
 
     \return               Base Priority register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_BASEPRI(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t  __get_BASEPRI(void)
 {
   register uint32_t __regBasePri         __ASM("basepri");
   return(__regBasePri);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Set Base Priority
@@ -264,15 +221,11 @@
 
     \param [in]    basePri  Base Priority value to set
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          void __set_BASEPRI(uint32_t basePri);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE void __set_BASEPRI(uint32_t basePri)
 {
   register uint32_t __regBasePri         __ASM("basepri");
   __regBasePri = (basePri & 0xff);
 }
-#endif /*  __ARMCC_VERSION  */ 
  
 
 /** \brief  Get Fault Mask
@@ -281,15 +234,11 @@
 
     \return               Fault Mask register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_FAULTMASK(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_FAULTMASK(void)
 {
   register uint32_t __regFaultMask       __ASM("faultmask");
   return(__regFaultMask);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Set Fault Mask
@@ -298,15 +247,11 @@
 
     \param [in]    faultMask  Fault Mask value to set
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          void __set_FAULTMASK(uint32_t faultMask);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE void __set_FAULTMASK(uint32_t faultMask)
 {
   register uint32_t __regFaultMask       __ASM("faultmask");
-  __regFaultMask = (faultMask & 1);
+  __regFaultMask = (faultMask & (uint32_t)1);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 #endif /* (__CORTEX_M >= 0x03) */
 
@@ -321,7 +266,7 @@
  */
 static __INLINE uint32_t __get_FPSCR(void)
 {
-#if (__FPU_PRESENT == 1)
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
   register uint32_t __regfpscr         __ASM("fpscr");
   return(__regfpscr);
 #else
@@ -338,7 +283,7 @@
  */
 static __INLINE void __set_FPSCR(uint32_t fpscr)
 {
-#if (__FPU_PRESENT == 1)
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
   register uint32_t __regfpscr         __ASM("fpscr");
   __regfpscr = (fpscr);
 #endif
@@ -347,192 +292,12 @@
 #endif /* (__CORTEX_M == 0x04) */
 
 
- #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
 /* IAR iccarm specific functions */
 
-#if defined (__ICCARM__)
-  #include <intrinsics.h>                     /* IAR Intrinsics   */
-#endif
-
-#pragma diag_suppress=Pe940
-
-/** \brief  Enable IRQ Interrupts
-
-  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
-  Can only be executed in Privileged modes.
- */
-#define __enable_irq                              __enable_interrupt
-
-
-/** \brief  Disable IRQ Interrupts
-
-  This function disables IRQ interrupts by setting the I-bit in the CPSR.
-  Can only be executed in Privileged modes.
- */
-#define __disable_irq                             __disable_interrupt
-
-
-/* intrinsic unsigned long __get_CONTROL( void ); (see intrinsic.h) */
-/* intrinsic void __set_CONTROL( unsigned long ); (see intrinsic.h) */
-
-
-/** \brief  Get ISPR Register
-
-    This function returns the content of the ISPR Register.
-
-    \return               ISPR Register value
- */
-static uint32_t __get_IPSR(void)
-{
-  __ASM("mrs r0, ipsr");
-}
-
-
-/** \brief  Get APSR Register
-
-    This function returns the content of the APSR Register.
-
-    \return               APSR Register value
- */
-static uint32_t __get_APSR(void)
-{
-  __ASM("mrs r0, apsr");
-}
-
-
-/** \brief  Get xPSR Register
-
-    This function returns the content of the xPSR Register.
-
-    \return               xPSR Register value
- */
-static uint32_t __get_xPSR(void)
-{
-  __ASM("mrs r0, psr");           // assembler does not know "xpsr"
-}
-
-
-/** \brief  Get Process Stack Pointer
-
-    This function returns the current value of the Process Stack Pointer (PSP).
-
-    \return               PSP Register value
- */
-static uint32_t __get_PSP(void)
-{
-  __ASM("mrs r0, psp");
-}
- 
-
-/** \brief  Set Process Stack Pointer
-
-    This function assigns the given value to the Process Stack Pointer (PSP).
-
-    \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-static void __set_PSP(uint32_t topOfProcStack)
-{
-  __ASM("msr psp, r0");
-}
-
-
-/** \brief  Get Main Stack Pointer
-
-    This function returns the current value of the Main Stack Pointer (MSP).
+#include <cmsis_iar.h>
 
-    \return               MSP Register value
- */
-static uint32_t __get_MSP(void)
-{
-  __ASM("mrs r0, msp");
-}
- 
-
-/** \brief  Set Main Stack Pointer
-
-    This function assigns the given value to the Main Stack Pointer (MSP).
-
-    \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-static void __set_MSP(uint32_t topOfMainStack)
-{
-  __ASM("msr msp, r0");
-}
- 
-
-/* intrinsic unsigned long __get_PRIMASK( void ); (see intrinsic.h) */
-/* intrinsic void __set_PRIMASK( unsigned long ); (see intrinsic.h) */
- 
-
-#if       (__CORTEX_M >= 0x03)
-
-/** \brief  Enable FIQ
-
-    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-static __INLINE void __enable_fault_irq(void)
-{
-  __ASM ("cpsie f");
-}
-
-
-/** \brief  Disable FIQ
-
-    This function disables FIQ interrupts by setting the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-static __INLINE void __disable_fault_irq(void)
-{
-  __ASM ("cpsid f");
-}
-
-
-/* intrinsic unsigned long __get_BASEPRI( void );   (see intrinsic.h) */
-/* intrinsic void __set_BASEPRI( unsigned long );   (see intrinsic.h) */
-/* intrinsic unsigned long __get_FAULTMASK( void ); (see intrinsic.h) */
-/* intrinsic void __set_FAULTMASK(unsigned long);   (see intrinsic.h) */
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-#if       (__CORTEX_M == 0x04)
-
-/** \brief  Get FPSCR
-
-    This function returns the current value of the Floating Point Status/Control register.
-
-    \return               Floating Point Status/Control register value
- */
-static uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1)
-  __ASM("vmrs r0, fpscr"); 
-#else
-  return(0);
-#endif
-}
-
-
-/** \brief  Set FPSCR
-
-    This function assigns the given value to the Floating Point Status/Control register.
-
-    \param [in]    fpscr  Floating Point Status/Control value to set
- */
-static void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1)
-  __ASM("vmsr fpscr, r0");
-#endif
-}
-
-#endif /* (__CORTEX_M == 0x04) */
-
-#pragma diag_default=Pe940
-
-
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
 /* GNU gcc specific functions */
 
 /** \brief  Enable IRQ Interrupts
@@ -584,11 +349,11 @@
 }
 
 
-/** \brief  Get ISPR Register
+/** \brief  Get IPSR Register
 
-    This function returns the content of the ISPR Register.
+    This function returns the content of the IPSR Register.
 
-    \return               ISPR Register value
+    \return               IPSR Register value
  */
 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void)
 {
@@ -800,10 +565,10 @@
  */
 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void)
 {
-#if (__FPU_PRESENT == 1)
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
   uint32_t result;
 
-  __ASM volatile ("MRS %0, fpscr" : "=r" (result) );
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
   return(result);
 #else
    return(0);
@@ -819,15 +584,15 @@
  */
 __attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr)
 {
-#if (__FPU_PRESENT == 1)
-  __ASM volatile ("MSR fpscr, %0" : : "r" (fpscr) );
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );
 #endif
 }
 
 #endif /* (__CORTEX_M == 0x04) */
 
 
-#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
 /* TASKING carm specific functions */
 
 /*
@@ -841,4 +606,4 @@
 /*@} end of CMSIS_Core_RegAccFunctions */
 
 
-#endif /* __CORE_CMFUNC_H__ */
+#endif /* __CORE_CMFUNC_H */

--- a/LPC1768/GCC_CR/core_cmInstr.h	Fri Jan 06 16:40:24 2012 +0000
+++ b/LPC1768/GCC_CR/core_cmInstr.h	Tue Jan 10 12:00:50 2012 +0000
@@ -1,11 +1,11 @@
 /**************************************************************************//**
  * @file     core_cmInstr.h
  * @brief    CMSIS Cortex-M Core Instruction Access Header File
- * @version  V2.01
- * @date     06. December 2010
+ * @version  V3.00
+ * @date     09. December 2011
  *
  * @note
- * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
  *
  * @par
  * ARM Limited (ARM) is supplying this software for use with Cortex-M 
@@ -21,8 +21,8 @@
  *
  ******************************************************************************/
 
-#ifndef __CORE_CMINSTR_H__
-#define __CORE_CMINSTR_H__
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
 
 
 /* ##########################  Core Instruction Access  ######################### */
@@ -31,9 +31,14 @@
   @{
 */
 
-#if defined ( __CC_ARM   ) /*------------------ RealView Compiler ----------------*/
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
 /* ARM armcc specific functions */
 
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
 /** \brief  No Operation
 
     No Operation does nothing. This instruction can be used for code alignment purposes.
@@ -106,15 +111,11 @@
     \param [in]    value  Value to reverse
     \return               Reversed value
  */
-#if (__ARMCC_VERSION < 400677)
-extern uint32_t __REV16(uint32_t value);
-#else  /* (__ARMCC_VERSION >= 400677)  */
-static __INLINE __ASM uint32_t __REV16(uint32_t value)
+static __attribute__((section(".rev16_text"))) __INLINE __ASM uint32_t __REV16(uint32_t value)
 {
   rev16 r0, r0
   bx lr
 }
-#endif /* __ARMCC_VERSION  */ 
 
 
 /** \brief  Reverse byte order in signed short value
@@ -124,15 +125,11 @@
     \param [in]    value  Value to reverse
     \return               Reversed value
  */
-#if (__ARMCC_VERSION < 400677)
-extern int32_t __REVSH(int32_t value);
-#else  /* (__ARMCC_VERSION >= 400677)  */
-static __INLINE __ASM int32_t __REVSH(int32_t value)
+static __attribute__((section(".revsh_text"))) __INLINE __ASM int32_t __REVSH(int32_t value)
 {
   revsh r0, r0
   bx lr
 }
-#endif /* __ARMCC_VERSION  */ 
 
 
 #if       (__CORTEX_M >= 0x03)
@@ -218,11 +215,7 @@
     This function removes the exclusive lock which is created by LDREX.
 
  */
-#if (__ARMCC_VERSION < 400000)
-extern void __CLREX(void);
-#else  /* (__ARMCC_VERSION >= 400000)  */
 #define __CLREX                           __clrex
-#endif /* __ARMCC_VERSION  */ 
 
 
 /** \brief  Signed Saturate
@@ -260,196 +253,13 @@
 
 
 
-#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
 /* IAR iccarm specific functions */
 
-#include <intrinsics.h>                     /* IAR Intrinsics   */
-
-#pragma diag_suppress=Pe940
-
-/** \brief  No Operation
-
-    No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-#define __NOP                           __no_operation
-
-
-/** \brief  Wait For Interrupt
-
-    Wait For Interrupt is a hint instruction that suspends execution
-    until one of a number of events occurs.
- */
-static __INLINE  void __WFI(void)
-{
-  __ASM ("wfi");
-}
-
-
-/** \brief  Wait For Event
-
-    Wait For Event is a hint instruction that permits the processor to enter
-    a low-power state until one of a number of events occurs.
- */
-static __INLINE  void __WFE(void)
-{
-  __ASM ("wfe");
-}
-
-
-/** \brief  Send Event
-
-    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-static __INLINE  void __SEV(void)
-{
-  __ASM ("sev");
-}
-
-
-/* intrinsic     void __ISB(void)            (see intrinsics.h) */
-/* intrinsic     void __DSB(void)            (see intrinsics.h) */
-/* intrinsic     void __DMB(void)            (see intrinsics.h) */
-/* intrinsic uint32_t __REV(uint32_t value)  (see intrinsics.h) */
-/* intrinsic          __SSAT                 (see intrinsics.h) */
-/* intrinsic          __USAT                 (see intrinsics.h) */
-
-
-/** \brief  Reverse byte order (16 bit)
-
-    This function reverses the byte order in two unsigned short values.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-static uint32_t __REV16(uint32_t value)
-{
-  __ASM("rev16 r0, r0");
-}
-
-
-/* intrinsic uint32_t __REVSH(uint32_t value)  (see intrinsics.h */
-
-
-#if       (__CORTEX_M >= 0x03)
-
-/** \brief  Reverse bit order of value
-
-    This function reverses the bit order of the given value.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-static uint32_t __RBIT(uint32_t value)
-{
-  __ASM("rbit r0, r0");
-}
+#include <cmsis_iar.h>
 
 
-/** \brief  LDR Exclusive (8 bit)
-
-    This function performs a exclusive LDR command for 8 bit value.
-
-    \param [in]    ptr  Pointer to data
-    \return             value of type uint8_t at (*ptr)
- */
-static uint8_t __LDREXB(volatile uint8_t *addr)
-{
-  __ASM("ldrexb r0, [r0]");
-}
-
-
-/** \brief  LDR Exclusive (16 bit)
-
-    This function performs a exclusive LDR command for 16 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint16_t at (*ptr)
- */
-static uint16_t __LDREXH(volatile uint16_t *addr)
-{
-  __ASM("ldrexh r0, [r0]");
-}
-
-
-/** \brief  LDR Exclusive (32 bit)
-
-    This function performs a exclusive LDR command for 32 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint32_t at (*ptr)
- */
-/* intrinsic unsigned long __LDREX(unsigned long *)  (see intrinsics.h) */
-static uint32_t __LDREXW(volatile uint32_t *addr)
-{
-  __ASM("ldrex r0, [r0]");
-}
-
-
-/** \brief  STR Exclusive (8 bit)
-
-    This function performs a exclusive STR command for 8 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-static uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
-{
-  __ASM("strexb r0, r0, [r1]");
-}
-
-
-/** \brief  STR Exclusive (16 bit)
-
-    This function performs a exclusive STR command for 16 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-static uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
-{
-  __ASM("strexh r0, r0, [r1]");
-}
-
-
-/** \brief  STR Exclusive (32 bit)
-
-    This function performs a exclusive STR command for 32 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-/* intrinsic unsigned long __STREX(unsigned long, unsigned long)  (see intrinsics.h )*/
-static uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
-{
-  __ASM("strex r0, r0, [r1]");
-}
-
-
-/** \brief  Remove the exclusive lock
-
-    This function removes the exclusive lock which is created by LDREX.
-
- */
-static __INLINE void __CLREX(void)
-{
-  __ASM ("clrex");
-}
-
-/* intrinsic   unsigned char __CLZ( unsigned long )      (see intrinsics.h) */
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-#pragma diag_default=Pe940
-
-
-
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
 /* GNU gcc specific functions */
 
 /** \brief  No Operation
@@ -655,7 +465,7 @@
 {
    uint32_t result;
   
-   __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+   __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
    return(result);
 }
 
@@ -673,7 +483,7 @@
 {
    uint32_t result;
   
-   __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+   __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
    return(result);
 }
 
@@ -691,7 +501,7 @@
 {
    uint32_t result;
   
-   __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+   __ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
    return(result);
 }
 
@@ -759,12 +569,12 @@
 
 
 
-#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
 /* TASKING carm specific functions */
 
 /*
  * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
  * Including the CMSIS ones.
  */
 
@@ -772,4 +582,4 @@
 
 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
 
-#endif /* __CORE_CMINSTR_H__ */
+#endif /* __CORE_CMINSTR_H */

Binary file LPC1768/GCC_CR/libcapi.a has changed

Binary file LPC1768/GCC_CR/libmbed.a has changed

--- a/LPC1768/GCC_CS/core_cm3.h	Fri Jan 06 16:40:24 2012 +0000
+++ b/LPC1768/GCC_CS/core_cm3.h	Tue Jan 10 12:00:50 2012 +0000
@@ -1,16 +1,16 @@
 /**************************************************************************//**
  * @file     core_cm3.h
  * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
- * @version  V2.01
- * @date     06. December 2010
+ * @version  V3.00
+ * @date     09. December 2011
  *
  * @note
- * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
  *
  * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M 
- * processor based microcontrollers.  This file can be freely distributed 
- * within development tools that are supporting such ARM based processors. 
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers.  This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
  *
  * @par
  * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
@@ -20,106 +20,144 @@
  * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
  *
  ******************************************************************************/
-#if defined ( __ICCARM__ )                   
+#if defined ( __ICCARM__ )
  #pragma system_include  /* treat file as system include file for MISRA check */
 #endif
 
 #ifdef __cplusplus
  extern "C" {
-#endif 
+#endif
 
 #ifndef __CORE_CM3_H_GENERIC
 #define __CORE_CM3_H_GENERIC
 
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+  
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'. 
 
-/** \mainpage CMSIS Cortex-M3
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
    
-  This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer.
-  It consists of:
- 
-     - Cortex-M Core Register Definitions
-     - Cortex-M functions
-     - Cortex-M instructions
- 
-  The CMSIS Cortex-M3 Core Peripheral Access Layer contains C and assembly functions that ease 
-  access to the Cortex-M Core
- */ 
-
-/** \defgroup CMSIS_LintCinfiguration CMSIS Lint Configuration
-  List of Lint messages which will be suppressed and not shown:
-    - not yet checked
-  .
-  Note:  To re-enable a Message, insert a space before 'lint' *
- 
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code. 
  */
 
 
 /*******************************************************************************
  *                 CMSIS definitions
  ******************************************************************************/
-/** \defgroup CMSIS_core_definitions CMSIS Core Definitions
-  This file defines all structures and symbols for CMSIS core:
-   - CMSIS version number
-   - Cortex-M core 
-   - Cortex-M core Revision Number
+/** \ingroup Cortex_M3
   @{
  */
 
 /*  CMSIS CM3 definitions */
-#define __CM3_CMSIS_VERSION_MAIN  (0x02)                                                       /*!< [31:16] CMSIS HAL main version */
-#define __CM3_CMSIS_VERSION_SUB   (0x00)                                                       /*!< [15:0]  CMSIS HAL sub version  */
-#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number       */
+#define __CM3_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM3_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | \
+                                    __CM3_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
 
-#define __CORTEX_M                (0x03)                                                       /*!< Cortex core                    */
+#define __CORTEX_M                (0x03)                                   /*!< Cortex-M Core                    */
 
 
-#if defined ( __CC_ARM   )
+#if   defined ( __CC_ARM )
   #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
   #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
 
 #elif defined ( __ICCARM__ )
   #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */
-  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
+  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
 
-#elif defined   (  __GNUC__  )
+#elif defined ( __GNUC__ )
   #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
   #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
 
-#elif defined   (  __TASKING__  )
+#elif defined ( __TASKING__ )
   #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
   #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
 
 #endif
 
-#include <stdint.h>                      /*!< standard types definitions                      */
-#include "core_cmInstr.h"                /*!< Core Instruction Access                         */
-#include "core_cmFunc.h"                 /*!< Core Function Access                            */
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+    /* add preprocessor checks */
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
 
 #endif /* __CORE_CM3_H_GENERIC */
 
-
 #ifndef __CMSIS_GENERIC
 
 #ifndef __CORE_CM3_H_DEPENDANT
 #define __CORE_CM3_H_DEPENDANT
 
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM3_REV
+    #define __CM3_REV               0x0200
+    #warning "__CM3_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          4
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
 /* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+ 
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
 #ifdef __cplusplus
-  #define     __I     volatile           /*!< defines 'read only' permissions                 */
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
 #else
-  #define     __I     volatile const     /*!< defines 'read only' permissions                 */
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
 #endif
-#define     __O     volatile             /*!< defines 'write only' permissions                */
-#define     __IO    volatile             /*!< defines 'read / write' permissions              */
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
 
-/*@} end of group CMSIS_core_definitions */
+/*@} end of group Cortex_M3 */
 
 
 
 /*******************************************************************************
  *                 Register Abstraction
- ******************************************************************************/
-/** \defgroup CMSIS_core_register CMSIS Core Register
   Core Register contain:
   - Core Register
   - Core NVIC Register
@@ -127,11 +165,14 @@
   - Core SysTick Register
   - Core Debug Register
   - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
 */
 
-/** \ingroup  CMSIS_core_register   
-    \defgroup CMSIS_CORE CMSIS Core
-  Type definitions for the Cortex-M Core Registers
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
   @{
  */
 
@@ -154,7 +195,7 @@
     uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
     uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
   } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */ 
+  uint32_t w;                            /*!< Type      used for word access                  */
 } APSR_Type;
 
 
@@ -214,9 +255,9 @@
 /*@} end of group CMSIS_CORE */
 
 
-/** \ingroup  CMSIS_core_register   
-    \defgroup CMSIS_NVIC CMSIS NVIC
-  Type definitions for the Cortex-M NVIC Registers
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
   @{
  */
 
@@ -225,26 +266,30 @@
 typedef struct
 {
   __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
-       uint32_t RESERVED0[24];                                   
+       uint32_t RESERVED0[24];
   __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
-       uint32_t RSERVED1[24];                                    
+       uint32_t RSERVED1[24];
   __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
-       uint32_t RESERVED2[24];                                   
+       uint32_t RESERVED2[24];
   __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
-       uint32_t RESERVED3[24];                                   
+       uint32_t RESERVED3[24];
   __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
-       uint32_t RESERVED4[56];                                   
+       uint32_t RESERVED4[56];
   __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
-       uint32_t RESERVED5[644];                                  
+       uint32_t RESERVED5[644];
   __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
-}  NVIC_Type;                                               
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
 
 /*@} end of group CMSIS_NVIC */
 
 
-/** \ingroup  CMSIS_core_register   
-    \defgroup CMSIS_SCB CMSIS SCB
-  Type definitions for the Cortex-M System Control Block Registers
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
   @{
  */
 
@@ -252,26 +297,28 @@
  */
 typedef struct
 {
-  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPU ID Base Register                                  */
-  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control State Register                      */
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
   __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
-  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt / Reset Control Register        */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
   __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
   __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
   __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
   __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
   __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
-  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  Hard Fault Status Register                            */
+  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
   __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
-  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  Mem Manage Address Register                           */
-  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  Bus Fault Address Register                            */
+  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
   __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
   __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
   __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
   __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
   __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
-  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  ISA Feature Register                                  */
-} SCB_Type;                                                
+  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+       uint32_t RESERVED0[5];
+  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+} SCB_Type;
 
 /* SCB CPUID Register Definitions */
 #define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
@@ -280,6 +327,9 @@
 #define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
 #define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
 
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
 #define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
 #define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
 
@@ -317,12 +367,17 @@
 #define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
 #define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
 
-/* SCB Interrupt Control State Register Definitions */
+/* SCB Vector Table Offset Register Definitions */
+#if (__CM3_REV < 0x0201)                   /* core r2p1 */
 #define SCB_VTOR_TBLBASE_Pos               29                                             /*!< SCB VTOR: TBLBASE Position */
 #define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
 
 #define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
 #define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+#endif
 
 /* SCB Application Interrupt and Reset Control Register Definitions */
 #define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
@@ -408,7 +463,7 @@
 
 #define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
 #define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
-                                     
+
 #define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
 #define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
 
@@ -457,9 +512,46 @@
 /*@} end of group CMSIS_SCB */
 
 
-/** \ingroup  CMSIS_core_register   
-    \defgroup CMSIS_SysTick CMSIS SysTick
-  Type definitions for the Cortex-M System Timer Registers
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register      */
+#else
+       uint32_t RESERVED1[1];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
   @{
  */
 
@@ -507,9 +599,9 @@
 /*@} end of group CMSIS_SysTick */
 
 
-/** \ingroup  CMSIS_core_register   
-    \defgroup CMSIS_ITM CMSIS ITM
-  Type definitions for the Cortex-M Instrumentation Trace Macrocell (ITM)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
   @{
  */
 
@@ -517,134 +609,59 @@
  */
 typedef struct
 {
-  __O  union  
+  __O  union
   {
     __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
     __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
     __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
   }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
-       uint32_t RESERVED0[864];                                 
-  __IO uint32_t TER;                     /*!< Offset:       (R/W)  ITM Trace Enable Register                 */
-       uint32_t RESERVED1[15];                                  
-  __IO uint32_t TPR;                     /*!< Offset:       (R/W)  ITM Trace Privilege Register              */
-       uint32_t RESERVED2[15];                                  
-  __IO uint32_t TCR;                     /*!< Offset:       (R/W)  ITM Trace Control Register                */
-       uint32_t RESERVED3[29];                                  
-  __IO uint32_t IWR;                     /*!< Offset:       (R/W)  ITM Integration Write Register            */
-  __IO uint32_t IRR;                     /*!< Offset:       (R/W)  ITM Integration Read Register             */
-  __IO uint32_t IMCR;                    /*!< Offset:       (R/W)  ITM Integration Mode Control Register     */
-       uint32_t RESERVED4[43];                                  
-  __IO uint32_t LAR;                     /*!< Offset:       (R/W)  ITM Lock Access Register                  */
-  __IO uint32_t LSR;                     /*!< Offset:       (R/W)  ITM Lock Status Register                  */
-       uint32_t RESERVED5[6];                                   
-  __I  uint32_t PID4;                    /*!< Offset:       (R/ )  ITM Peripheral Identification Register #4 */
-  __I  uint32_t PID5;                    /*!< Offset:       (R/ )  ITM Peripheral Identification Register #5 */
-  __I  uint32_t PID6;                    /*!< Offset:       (R/ )  ITM Peripheral Identification Register #6 */
-  __I  uint32_t PID7;                    /*!< Offset:       (R/ )  ITM Peripheral Identification Register #7 */
-  __I  uint32_t PID0;                    /*!< Offset:       (R/ )  ITM Peripheral Identification Register #0 */
-  __I  uint32_t PID1;                    /*!< Offset:       (R/ )  ITM Peripheral Identification Register #1 */
-  __I  uint32_t PID2;                    /*!< Offset:       (R/ )  ITM Peripheral Identification Register #2 */
-  __I  uint32_t PID3;                    /*!< Offset:       (R/ )  ITM Peripheral Identification Register #3 */
-  __I  uint32_t CID0;                    /*!< Offset:       (R/ )  ITM Component  Identification Register #0 */
-  __I  uint32_t CID1;                    /*!< Offset:       (R/ )  ITM Component  Identification Register #1 */
-  __I  uint32_t CID2;                    /*!< Offset:       (R/ )  ITM Component  Identification Register #2 */
-  __I  uint32_t CID3;                    /*!< Offset:       (R/ )  ITM Component  Identification Register #3 */
-} ITM_Type;                                                
+       uint32_t RESERVED0[864];
+  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+       uint32_t RESERVED1[15];
+  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+       uint32_t RESERVED2[15];
+  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+} ITM_Type;
 
 /* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
+#define ITM_TPR_PRIVMASK_Pos                0                                          /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)             /*!< ITM TPR: PRIVMASK Mask */
 
 /* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+#define ITM_TCR_BUSY_Pos                   23                                          /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                   /*!< ITM TCR: BUSY Mask */
 
-#define ITM_TCR_ATBID_Pos                  16                                             /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_ATBID_Msk                  (0x7FUL << ITM_TCR_ATBID_Pos)                  /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+#define ITM_TCR_TraceBusID_Pos             16                                          /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)          /*!< ITM TCR: ATBID Mask */
 
-#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+#define ITM_TCR_GTSFREQ_Pos                10                                          /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                /*!< ITM TCR: Global timestamp frequency Mask */
 
-#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+#define ITM_TCR_TSPrescale_Pos              8                                          /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)             /*!< ITM TCR: TSPrescale Mask */
 
-#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
+#define ITM_TCR_SWOENA_Pos                  4                                          /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                 /*!< ITM TCR: SWOENA Mask */
 
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
+#define ITM_TCR_TXENA_Pos                   3                                          /*!< ITM TCR: TXENA Position */
+#define ITM_TCR_TXENA_Msk                  (1UL << ITM_TCR_TXENA_Pos)                  /*!< ITM TCR: TXENA Mask */
 
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
+#define ITM_TCR_SYNCENA_Pos                 2                                          /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                /*!< ITM TCR: SYNCENA Mask */
 
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+#define ITM_TCR_TSENA_Pos                   1                                          /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                  /*!< ITM TCR: TSENA Mask */
 
-#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
+#define ITM_TCR_ITMENA_Pos                  0                                          /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                 /*!< ITM TCR: ITM Enable bit Mask */
 
 /*@}*/ /* end of group CMSIS_ITM */
 
 
-/** \ingroup  CMSIS_core_register   
-    \defgroup CMSIS_InterruptType CMSIS Interrupt Type
-  Type definitions for the Cortex-M Interrupt Type Register
-  @{
- */
-
-/** \brief  Structure type to access the Interrupt Type Register.
- */
-typedef struct
-{
-       uint32_t RESERVED0;
-  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Control Type Register */
-#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
-  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register      */
-#else
-       uint32_t RESERVED1;
-#endif
-} InterruptType_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define IntType_ICTR_INTLINESNUM_Pos  0                                                   /*!< InterruptType ICTR: INTLINESNUM Position */
-#define IntType_ICTR_INTLINESNUM_Msk (0x1FUL << IntType_ICTR_INTLINESNUM_Pos)             /*!< InterruptType ICTR: INTLINESNUM Mask */
-
-/* Auxiliary Control Register Definitions */
-#define IntType_ACTLR_DISFOLD_Pos     2                                                   /*!< InterruptType ACTLR: DISFOLD Position */
-#define IntType_ACTLR_DISFOLD_Msk    (1UL << IntType_ACTLR_DISFOLD_Pos)                   /*!< InterruptType ACTLR: DISFOLD Mask */
-
-#define IntType_ACTLR_DISDEFWBUF_Pos  1                                                   /*!< InterruptType ACTLR: DISDEFWBUF Position */
-#define IntType_ACTLR_DISDEFWBUF_Msk (1UL << IntType_ACTLR_DISDEFWBUF_Pos)                /*!< InterruptType ACTLR: DISDEFWBUF Mask */
-
-#define IntType_ACTLR_DISMCYCINT_Pos  0                                                   /*!< InterruptType ACTLR: DISMCYCINT Position */
-#define IntType_ACTLR_DISMCYCINT_Msk (1UL << IntType_ACTLR_DISMCYCINT_Pos)                /*!< InterruptType ACTLR: DISMCYCINT Mask */
-
-/*@}*/ /* end of group CMSIS_InterruptType */
-
-
 #if (__MPU_PRESENT == 1)
-/** \ingroup  CMSIS_core_register   
-    \defgroup CMSIS_MPU CMSIS MPU
-  Type definitions for the Cortex-M Memory Protection Unit (MPU)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
   @{
  */
 
@@ -663,7 +680,7 @@
   __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
   __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
   __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;                                                
+} MPU_Type;
 
 /* MPU Type Register */
 #define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
@@ -700,23 +717,8 @@
 #define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
 
 /* MPU Region Attribute and Size Register */
-#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: XN Position */
-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: XN Mask */
-
-#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: AP Position */
-#define MPU_RASR_AP_Msk                    (7UL << MPU_RASR_AP_Pos)                       /*!< MPU RASR: AP Mask */
-
-#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: TEX Position */
-#define MPU_RASR_TEX_Msk                   (7UL << MPU_RASR_TEX_Pos)                      /*!< MPU RASR: TEX Mask */
-
-#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: Shareable bit Position */
-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: Shareable bit Mask */
-
-#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: Cacheable bit Position */
-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: Cacheable bit Mask */
-
-#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: Bufferable bit Position */
-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: Bufferable bit Mask */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
 
 #define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
 #define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
@@ -724,16 +726,16 @@
 #define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
 #define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
 
-#define MPU_RASR_ENA_Pos                     0                                            /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENA_Msk                    (0x1UL << MPU_RASR_ENA_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
 
 /*@} end of group CMSIS_MPU */
 #endif
 
 
-/** \ingroup  CMSIS_core_register   
-    \defgroup CMSIS_CoreDebug CMSIS Core Debug
-  Type definitions for the Cortex-M Core Debug Registers
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Type definitions for the Core Debug Registers
   @{
  */
 
@@ -834,28 +836,30 @@
 /*@} end of group CMSIS_CoreDebug */
 
 
-/** \ingroup  CMSIS_core_register   
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
   @{
  */
- 
+
 /* Memory mapping of Cortex-M3 Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
-#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                  */
-#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address           */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
 
-#define InterruptType       ((InterruptType_Type *) SCS_BASE)         /*!< Interrupt Type Register           */
-#define SCB                 ((SCB_Type *)           SCB_BASE)         /*!< SCB configuration struct          */
-#define SysTick             ((SysTick_Type *)       SysTick_BASE)     /*!< SysTick configuration struct      */
-#define NVIC                ((NVIC_Type *)          NVIC_BASE)        /*!< NVIC configuration struct         */
-#define ITM                 ((ITM_Type *)           ITM_BASE)         /*!< ITM configuration struct          */
-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct   */
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
 
 #if (__MPU_PRESENT == 1)
-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit            */
-  #define MPU               ((MPU_Type*)            MPU_BASE)         /*!< Memory Protection Unit            */
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
 #endif
 
 /*@} */
@@ -864,42 +868,43 @@
 
 /*******************************************************************************
  *                Hardware Abstraction Layer
- ******************************************************************************/
-/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface
   Core Function Interface contains:
   - Core NVIC Functions
   - Core SysTick Functions
   - Core Debug Functions
   - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
 */
 
 
 
 /* ##########################   NVIC functions  #################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface   
-    \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions
-  @{
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
  */
 
 /** \brief  Set Priority Grouping
 
-  This function sets the priority grouping field using the required unlock sequence.
+  The function sets the priority grouping field using the required unlock sequence.
   The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
   Only values from 0..7 are used.
   In case of a conflict between priority grouping and available
-  priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
 
-    \param [in]      PriorityGroup  Priority grouping field
+    \param [in]      PriorityGroup  Priority grouping field.
  */
 static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
 {
   uint32_t reg_value;
-  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);                         /* only values 0..7 are used          */
-  
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
+
   reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
   reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
-  reg_value  =  (reg_value                       |
-                (0x5FA << SCB_AIRCR_VECTKEY_Pos) | 
+  reg_value  =  (reg_value                                 |
+                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
                 (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
   SCB->AIRCR =  reg_value;
 }
@@ -907,10 +912,9 @@
 
 /** \brief  Get Priority Grouping
 
-  This function gets the priority grouping from NVIC Interrupt Controller.
-  Priority grouping is SCB->AIRCR [10:8] PRIGROUP field.
+  The function reads the priority grouping field from the NVIC Interrupt Controller.
 
-    \return                Priority grouping field
+    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
  */
 static __INLINE uint32_t NVIC_GetPriorityGrouping(void)
 {
@@ -920,10 +924,9 @@
 
 /** \brief  Enable External Interrupt
 
-    This function enables a device specific interupt in the NVIC interrupt controller.
-    The interrupt number cannot be a negative value. 
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
 
-    \param [in]      IRQn  Number of the external interrupt to enable
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
  */
 static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
 {
@@ -933,10 +936,9 @@
 
 /** \brief  Disable External Interrupt
 
-    This function disables a device specific interupt in the NVIC interrupt controller.
-    The interrupt number cannot be a negative value. 
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
 
-    \param [in]      IRQn  Number of the external interrupt to disable
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
  */
 static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
 {
@@ -946,12 +948,13 @@
 
 /** \brief  Get Pending Interrupt
 
-    This function reads the pending register in the NVIC and returns the pending bit
-    for the specified interrupt. 
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
 
-    \param [in]      IRQn  Number of the interrupt for get pending
-    \return             0  Interrupt status is not pending
-    \return             1  Interrupt status is pending
+    \param [in]      IRQn  Interrupt number.
+    
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
  */
 static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
 {
@@ -961,10 +964,9 @@
 
 /** \brief  Set Pending Interrupt
 
-    This function sets the pending bit for the specified interrupt. 
-    The interrupt number cannot be a negative value.
+    The function sets the pending bit of an external interrupt.
 
-    \param [in]      IRQn  Number of the interrupt for set pending
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
  */
 static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
 {
@@ -974,10 +976,9 @@
 
 /** \brief  Clear Pending Interrupt
 
-    This function clears the pending bit for the specified interrupt. 
-    The interrupt number cannot be a negative value.
+    The function clears the pending bit of an external interrupt.
 
-    \param [in]      IRQn  Number of the interrupt for clear pending
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
  */
 static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
 {
@@ -987,10 +988,12 @@
 
 /** \brief  Get Active Interrupt
 
-    This function reads the active register in NVIC and returns the active bit. 
-    \param [in]      IRQn  Number of the interrupt for get active
-    \return             0  Interrupt status is not active
-    \return             1  Interrupt status is active
+    The function reads the active register in NVIC and returns the active bit.
+    
+    \param [in]      IRQn  Interrupt number.
+    
+    \return             0  Interrupt status is not active.
+    \return             1  Interrupt status is active.
  */
 static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
 {
@@ -1000,14 +1003,12 @@
 
 /** \brief  Set Interrupt Priority
 
-    This function sets the priority for the specified interrupt. The interrupt 
-    number can be positive to specify an external (device specific) 
-    interrupt, or negative to specify an internal (core) interrupt.
+    The function sets the priority of an interrupt. 
 
-    Note: The priority cannot be set for every core interrupt.
+    \note The priority cannot be set for every core interrupt.
 
-    \param [in]      IRQn  Number of the interrupt for set priority
-    \param [in]  priority  Priority to set
+    \param [in]      IRQn  Interrupt number. 
+    \param [in]  priority  Priority to set.
  */
 static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
 {
@@ -1020,15 +1021,14 @@
 
 /** \brief  Get Interrupt Priority
 
-    This function reads the priority for the specified interrupt. The interrupt 
-    number can be positive to specify an external (device specific) 
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
     interrupt, or negative to specify an internal (core) interrupt.
 
-    The returned priority value is automatically aligned to the implemented
-    priority bits of the microcontroller.
 
-    \param [in]   IRQn  Number of the interrupt for get priority
-    \return             Interrupt Priority
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
  */
 static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
 {
@@ -1042,17 +1042,15 @@
 
 /** \brief  Encode Priority
 
-    This function encodes the priority for an interrupt with the given priority group,
-    preemptive priority value and sub priority value.
+    The function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value, and subpriority value.
     In case of a conflict between priority grouping and available
-    priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
- 
-    The returned priority value can be used for NVIC_SetPriority(...) function
+    priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
 
-    \param [in]     PriorityGroup  Used priority group
-    \param [in]   PreemptPriority  Preemptive priority value (starting from 0)
-    \param [in]       SubPriority  Sub priority value (starting from 0)
-    \return                        Encoded priority for the interrupt
+    \param [in]     PriorityGroup  Used priority group.
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+    \param [in]       SubPriority  Subpriority value (starting from 0).
+    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
  */
 static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
 {
@@ -1062,7 +1060,7 @@
 
   PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
   SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
- 
+
   return (
            ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
            ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
@@ -1072,17 +1070,15 @@
 
 /** \brief  Decode Priority
 
-    This function decodes an interrupt priority value with the given priority group to 
-    preemptive priority value and sub priority value.
+    The function decodes an interrupt priority value with a given priority group to
+    preemptive priority value and subpriority value.
     In case of a conflict between priority grouping and available
     priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
- 
-    The priority value can be retrieved with NVIC_GetPriority(...) function
- 
-    \param [in]         Priority   Priority value
-    \param [in]     PriorityGroup  Used priority group
-    \param [out] pPreemptPriority  Preemptive priority value (starting from 0)
-    \param [out]     pSubPriority  Sub priority value (starting from 0)
+
+    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+    \param [in]     PriorityGroup  Used priority group.
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+    \param [out]     pSubPriority  Subpriority value (starting from 0).
  */
 static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
 {
@@ -1092,7 +1088,7 @@
 
   PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
   SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-  
+
   *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
   *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
 }
@@ -1100,16 +1096,16 @@
 
 /** \brief  System Reset
 
-    This function initiate a system reset request to reset the MCU.
+    The function initiates a system reset request to reset the MCU.
  */
 static __INLINE void NVIC_SystemReset(void)
 {
   __DSB();                                                     /* Ensure all outstanding memory accesses included
-                                                                  buffered write are completed before reset */              
-  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      | 
-                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
                  SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
-  __DSB();                                                     /* Ensure completion of memory access */              
+  __DSB();                                                     /* Ensure completion of memory access */
   while(1);                                                    /* wait until reset */
 }
 
@@ -1118,8 +1114,9 @@
 
 
 /* ##################################    SysTick function  ############################################ */
-/** \ingroup  CMSIS_Core_FunctionInterface   
-    \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
   @{
  */
 
@@ -1127,22 +1124,28 @@
 
 /** \brief  System Tick Configuration
 
-    This function initialises the system tick timer and its interrupt and start the system tick timer.
-    Counter is in free running mode to generate periodical interrupts.
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.   
 
-    \param [in]  ticks  Number of ticks between two interrupts
-    \return          0  Function succeeded
-    \return          1  Function failed
+    \param [in]  ticks  Number of ticks between two interrupts.
+    
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+    
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the 
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> 
+    must contain a vendor-specific implementation of this function.
+
  */
 static __INLINE uint32_t SysTick_Config(uint32_t ticks)
-{ 
+{
   if (ticks > SysTick_LOAD_RELOAD_Msk)  return (1);            /* Reload value impossible */
-                                                               
+
   SysTick->LOAD  = (ticks & SysTick_LOAD_RELOAD_Msk) - 1;      /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Cortex-M0 System Interrupts */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
   SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk | 
-                   SysTick_CTRL_TICKINT_Msk   | 
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
                    SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
   return (0);                                                  /* Function successful */
 }
@@ -1154,45 +1157,44 @@
 
 
 /* ##################################### Debug In/Output function ########################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface   
-    \defgroup CMSIS_core_DebugFunctions CMSIS Core Debug Functions
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions ITM Functions
+    \brief   Functions that access the ITM debug interface.
   @{
  */
 
-extern volatile int32_t ITM_RxBuffer;                    /*!< external variable to receive characters                    */
-#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
 
 
 /** \brief  ITM Send Character
 
-    This function transmits a character via the ITM channel 0. 
-    It just returns when no debugger is connected that has booked the output.  
-    It is blocking when a debugger is connected, but the previous character send is not transmitted. 
+    The function transmits a character via the ITM channel 0, and
+    \li Just returns when no debugger is connected that has booked the output.
+    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
 
-    \param [in]     ch  Character to transmit
-    \return             Character to transmit
+    \param [in]     ch  Character to transmit.
+    
+    \returns            Character to transmit.
  */
 static __INLINE uint32_t ITM_SendChar (uint32_t ch)
 {
-  if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk)  &&      /* Trace enabled */
-      (ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
+  if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
       (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
   {
     while (ITM->PORT[0].u32 == 0);
     ITM->PORT[0].u8 = (uint8_t) ch;
-  }  
+  }
   return (ch);
 }
 
 
 /** \brief  ITM Receive Character
 
-    This function inputs a character via external variable ITM_RxBuffer. 
-    It just returns when no debugger is connected that has booked the output.  
-    It is blocking when a debugger is connected, but the previous character send is not transmitted. 
+    The function inputs a character via the external variable \ref ITM_RxBuffer.
 
-    \return             Received character
-    \return         -1  No character received
+    \return             Received character.
+    \return         -1  No character pending.
  */
 static __INLINE int32_t ITM_ReceiveChar (void) {
   int32_t ch = -1;                           /* no character available */
@@ -1201,18 +1203,17 @@
     ch = ITM_RxBuffer;
     ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
   }
-  
-  return (ch); 
+
+  return (ch);
 }
 
 
 /** \brief  ITM Check Character
 
-    This function checks external variable ITM_RxBuffer whether a character is available or not. 
-    It returns '1' if a character is available and '0' if no character is available. 
+    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
 
-    \return          0  No character available
-    \return          1  Character available
+    \return          0  No character available.
+    \return          1  Character available.
  */
 static __INLINE int32_t ITM_CheckChar (void) {
 
@@ -1232,5 +1233,3 @@
 #ifdef __cplusplus
 }
 #endif
-
-/*lint -restore */

--- a/LPC1768/GCC_CS/core_cmFunc.h	Fri Jan 06 16:40:24 2012 +0000
+++ b/LPC1768/GCC_CS/core_cmFunc.h	Tue Jan 10 12:00:50 2012 +0000
@@ -1,11 +1,11 @@
 /**************************************************************************//**
  * @file     core_cmFunc.h
  * @brief    CMSIS Cortex-M Core Function Access Header File
- * @version  V2.01
- * @date     06. December 2010
+ * @version  V3.00
+ * @date     09. December 2011
  *
  * @note
- * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
  *
  * @par
  * ARM Limited (ARM) is supplying this software for use with Cortex-M 
@@ -21,8 +21,9 @@
  *
  ******************************************************************************/
 
-#ifndef __CORE_CMFUNC_H__
-#define __CORE_CMFUNC_H__
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
 
 /* ###########################  Core Function Access  ########################### */
 /** \ingroup  CMSIS_Core_FunctionInterface   
@@ -30,9 +31,13 @@
   @{
  */
 
-#if defined ( __CC_ARM   ) /*------------------ RealView Compiler ----------------*/
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
 /* ARM armcc specific functions */
 
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
 /* intrinsic void __enable_irq();     */
 /* intrinsic void __disable_irq();    */
 
@@ -42,15 +47,11 @@
 
     \return               Control Register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_CONTROL(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_CONTROL(void)
 {
   register uint32_t __regControl         __ASM("control");
   return(__regControl);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Set Control Register
@@ -59,32 +60,24 @@
 
     \param [in]    control  Control Register value to set
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          void __set_CONTROL(uint32_t control);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE void __set_CONTROL(uint32_t control)
 {
   register uint32_t __regControl         __ASM("control");
   __regControl = control;
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
-/** \brief  Get ISPR Register
-
-    This function returns the content of the ISPR Register.
+/** \brief  Get IPSR Register
 
-    \return               ISPR Register value
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_IPSR(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_IPSR(void)
 {
   register uint32_t __regIPSR          __ASM("ipsr");
   return(__regIPSR);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Get APSR Register
@@ -93,15 +86,11 @@
 
     \return               APSR Register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_APSR(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_APSR(void)
 {
   register uint32_t __regAPSR          __ASM("apsr");
   return(__regAPSR);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Get xPSR Register
@@ -110,15 +99,11 @@
 
     \return               xPSR Register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_xPSR(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_xPSR(void)
 {
   register uint32_t __regXPSR          __ASM("xpsr");
   return(__regXPSR);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Get Process Stack Pointer
@@ -127,15 +112,11 @@
 
     \return               PSP Register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_PSP(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_PSP(void)
 {
   register uint32_t __regProcessStackPointer  __ASM("psp");
   return(__regProcessStackPointer);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Set Process Stack Pointer
@@ -144,15 +125,11 @@
 
     \param [in]    topOfProcStack  Process Stack Pointer value to set
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          void __set_PSP(uint32_t topOfProcStack);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE void __set_PSP(uint32_t topOfProcStack)
 {
   register uint32_t __regProcessStackPointer  __ASM("psp");
   __regProcessStackPointer = topOfProcStack;
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Get Main Stack Pointer
@@ -161,15 +138,11 @@
 
     \return               MSP Register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_MSP(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_MSP(void)
 {
   register uint32_t __regMainStackPointer     __ASM("msp");
   return(__regMainStackPointer);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Set Main Stack Pointer
@@ -178,15 +151,11 @@
 
     \param [in]    topOfMainStack  Main Stack Pointer value to set
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          void __set_MSP(uint32_t topOfMainStack);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE void __set_MSP(uint32_t topOfMainStack)
 {
   register uint32_t __regMainStackPointer     __ASM("msp");
   __regMainStackPointer = topOfMainStack;
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Get Priority Mask
@@ -195,15 +164,11 @@
 
     \return               Priority Mask value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_PRIMASK(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_PRIMASK(void)
 {
   register uint32_t __regPriMask         __ASM("primask");
   return(__regPriMask);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Set Priority Mask
@@ -212,15 +177,11 @@
 
     \param [in]    priMask  Priority Mask
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          void __set_PRIMASK(uint32_t priMask);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE void __set_PRIMASK(uint32_t priMask)
 {
   register uint32_t __regPriMask         __ASM("primask");
   __regPriMask = (priMask);
 }
-#endif /*  __ARMCC_VERSION  */ 
  
 
 #if       (__CORTEX_M >= 0x03)
@@ -247,15 +208,11 @@
 
     \return               Base Priority register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_BASEPRI(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t  __get_BASEPRI(void)
 {
   register uint32_t __regBasePri         __ASM("basepri");
   return(__regBasePri);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Set Base Priority
@@ -264,15 +221,11 @@
 
     \param [in]    basePri  Base Priority value to set
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          void __set_BASEPRI(uint32_t basePri);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE void __set_BASEPRI(uint32_t basePri)
 {
   register uint32_t __regBasePri         __ASM("basepri");
   __regBasePri = (basePri & 0xff);
 }
-#endif /*  __ARMCC_VERSION  */ 
  
 
 /** \brief  Get Fault Mask
@@ -281,15 +234,11 @@
 
     \return               Fault Mask register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_FAULTMASK(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_FAULTMASK(void)
 {
   register uint32_t __regFaultMask       __ASM("faultmask");
   return(__regFaultMask);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Set Fault Mask
@@ -298,15 +247,11 @@
 
     \param [in]    faultMask  Fault Mask value to set
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          void __set_FAULTMASK(uint32_t faultMask);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE void __set_FAULTMASK(uint32_t faultMask)
 {
   register uint32_t __regFaultMask       __ASM("faultmask");
-  __regFaultMask = (faultMask & 1);
+  __regFaultMask = (faultMask & (uint32_t)1);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 #endif /* (__CORTEX_M >= 0x03) */
 
@@ -321,7 +266,7 @@
  */
 static __INLINE uint32_t __get_FPSCR(void)
 {
-#if (__FPU_PRESENT == 1)
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
   register uint32_t __regfpscr         __ASM("fpscr");
   return(__regfpscr);
 #else
@@ -338,7 +283,7 @@
  */
 static __INLINE void __set_FPSCR(uint32_t fpscr)
 {
-#if (__FPU_PRESENT == 1)
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
   register uint32_t __regfpscr         __ASM("fpscr");
   __regfpscr = (fpscr);
 #endif
@@ -347,192 +292,12 @@
 #endif /* (__CORTEX_M == 0x04) */
 
 
- #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
 /* IAR iccarm specific functions */
 
-#if defined (__ICCARM__)
-  #include <intrinsics.h>                     /* IAR Intrinsics   */
-#endif
-
-#pragma diag_suppress=Pe940
-
-/** \brief  Enable IRQ Interrupts
-
-  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
-  Can only be executed in Privileged modes.
- */
-#define __enable_irq                              __enable_interrupt
-
-
-/** \brief  Disable IRQ Interrupts
-
-  This function disables IRQ interrupts by setting the I-bit in the CPSR.
-  Can only be executed in Privileged modes.
- */
-#define __disable_irq                             __disable_interrupt
-
-
-/* intrinsic unsigned long __get_CONTROL( void ); (see intrinsic.h) */
-/* intrinsic void __set_CONTROL( unsigned long ); (see intrinsic.h) */
-
-
-/** \brief  Get ISPR Register
-
-    This function returns the content of the ISPR Register.
-
-    \return               ISPR Register value
- */
-static uint32_t __get_IPSR(void)
-{
-  __ASM("mrs r0, ipsr");
-}
-
-
-/** \brief  Get APSR Register
-
-    This function returns the content of the APSR Register.
-
-    \return               APSR Register value
- */
-static uint32_t __get_APSR(void)
-{
-  __ASM("mrs r0, apsr");
-}
-
-
-/** \brief  Get xPSR Register
-
-    This function returns the content of the xPSR Register.
-
-    \return               xPSR Register value
- */
-static uint32_t __get_xPSR(void)
-{
-  __ASM("mrs r0, psr");           // assembler does not know "xpsr"
-}
-
-
-/** \brief  Get Process Stack Pointer
-
-    This function returns the current value of the Process Stack Pointer (PSP).
-
-    \return               PSP Register value
- */
-static uint32_t __get_PSP(void)
-{
-  __ASM("mrs r0, psp");
-}
- 
-
-/** \brief  Set Process Stack Pointer
-
-    This function assigns the given value to the Process Stack Pointer (PSP).
-
-    \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-static void __set_PSP(uint32_t topOfProcStack)
-{
-  __ASM("msr psp, r0");
-}
-
-
-/** \brief  Get Main Stack Pointer
-
-    This function returns the current value of the Main Stack Pointer (MSP).
+#include <cmsis_iar.h>
 
-    \return               MSP Register value
- */
-static uint32_t __get_MSP(void)
-{
-  __ASM("mrs r0, msp");
-}
- 
-
-/** \brief  Set Main Stack Pointer
-
-    This function assigns the given value to the Main Stack Pointer (MSP).
-
-    \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-static void __set_MSP(uint32_t topOfMainStack)
-{
-  __ASM("msr msp, r0");
-}
- 
-
-/* intrinsic unsigned long __get_PRIMASK( void ); (see intrinsic.h) */
-/* intrinsic void __set_PRIMASK( unsigned long ); (see intrinsic.h) */
- 
-
-#if       (__CORTEX_M >= 0x03)
-
-/** \brief  Enable FIQ
-
-    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-static __INLINE void __enable_fault_irq(void)
-{
-  __ASM ("cpsie f");
-}
-
-
-/** \brief  Disable FIQ
-
-    This function disables FIQ interrupts by setting the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-static __INLINE void __disable_fault_irq(void)
-{
-  __ASM ("cpsid f");
-}
-
-
-/* intrinsic unsigned long __get_BASEPRI( void );   (see intrinsic.h) */
-/* intrinsic void __set_BASEPRI( unsigned long );   (see intrinsic.h) */
-/* intrinsic unsigned long __get_FAULTMASK( void ); (see intrinsic.h) */
-/* intrinsic void __set_FAULTMASK(unsigned long);   (see intrinsic.h) */
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-#if       (__CORTEX_M == 0x04)
-
-/** \brief  Get FPSCR
-
-    This function returns the current value of the Floating Point Status/Control register.
-
-    \return               Floating Point Status/Control register value
- */
-static uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1)
-  __ASM("vmrs r0, fpscr"); 
-#else
-  return(0);
-#endif
-}
-
-
-/** \brief  Set FPSCR
-
-    This function assigns the given value to the Floating Point Status/Control register.
-
-    \param [in]    fpscr  Floating Point Status/Control value to set
- */
-static void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1)
-  __ASM("vmsr fpscr, r0");
-#endif
-}
-
-#endif /* (__CORTEX_M == 0x04) */
-
-#pragma diag_default=Pe940
-
-
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
 /* GNU gcc specific functions */
 
 /** \brief  Enable IRQ Interrupts
@@ -584,11 +349,11 @@
 }
 
 
-/** \brief  Get ISPR Register
+/** \brief  Get IPSR Register
 
-    This function returns the content of the ISPR Register.
+    This function returns the content of the IPSR Register.
 
-    \return               ISPR Register value
+    \return               IPSR Register value
  */
 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void)
 {
@@ -800,10 +565,10 @@
  */
 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void)
 {
-#if (__FPU_PRESENT == 1)
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
   uint32_t result;
 
-  __ASM volatile ("MRS %0, fpscr" : "=r" (result) );
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
   return(result);
 #else
    return(0);
@@ -819,15 +584,15 @@
  */
 __attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr)
 {
-#if (__FPU_PRESENT == 1)
-  __ASM volatile ("MSR fpscr, %0" : : "r" (fpscr) );
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );
 #endif
 }
 
 #endif /* (__CORTEX_M == 0x04) */
 
 
-#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
 /* TASKING carm specific functions */
 
 /*
@@ -841,4 +606,4 @@
 /*@} end of CMSIS_Core_RegAccFunctions */
 
 
-#endif /* __CORE_CMFUNC_H__ */
+#endif /* __CORE_CMFUNC_H */

--- a/LPC1768/GCC_CS/core_cmInstr.h	Fri Jan 06 16:40:24 2012 +0000
+++ b/LPC1768/GCC_CS/core_cmInstr.h	Tue Jan 10 12:00:50 2012 +0000
@@ -1,11 +1,11 @@
 /**************************************************************************//**
  * @file     core_cmInstr.h
  * @brief    CMSIS Cortex-M Core Instruction Access Header File
- * @version  V2.01
- * @date     06. December 2010
+ * @version  V3.00
+ * @date     09. December 2011
  *
  * @note
- * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
  *
  * @par
  * ARM Limited (ARM) is supplying this software for use with Cortex-M 
@@ -21,8 +21,8 @@
  *
  ******************************************************************************/
 
-#ifndef __CORE_CMINSTR_H__
-#define __CORE_CMINSTR_H__
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
 
 
 /* ##########################  Core Instruction Access  ######################### */
@@ -31,9 +31,14 @@
   @{
 */
 
-#if defined ( __CC_ARM   ) /*------------------ RealView Compiler ----------------*/
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
 /* ARM armcc specific functions */
 
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
 /** \brief  No Operation
 
     No Operation does nothing. This instruction can be used for code alignment purposes.
@@ -106,15 +111,11 @@
     \param [in]    value  Value to reverse
     \return               Reversed value
  */
-#if (__ARMCC_VERSION < 400677)
-extern uint32_t __REV16(uint32_t value);
-#else  /* (__ARMCC_VERSION >= 400677)  */
-static __INLINE __ASM uint32_t __REV16(uint32_t value)
+static __attribute__((section(".rev16_text"))) __INLINE __ASM uint32_t __REV16(uint32_t value)
 {
   rev16 r0, r0
   bx lr
 }
-#endif /* __ARMCC_VERSION  */ 
 
 
 /** \brief  Reverse byte order in signed short value
@@ -124,15 +125,11 @@
     \param [in]    value  Value to reverse
     \return               Reversed value
  */
-#if (__ARMCC_VERSION < 400677)
-extern int32_t __REVSH(int32_t value);
-#else  /* (__ARMCC_VERSION >= 400677)  */
-static __INLINE __ASM int32_t __REVSH(int32_t value)
+static __attribute__((section(".revsh_text"))) __INLINE __ASM int32_t __REVSH(int32_t value)
 {
   revsh r0, r0
   bx lr
 }
-#endif /* __ARMCC_VERSION  */ 
 
 
 #if       (__CORTEX_M >= 0x03)
@@ -218,11 +215,7 @@
     This function removes the exclusive lock which is created by LDREX.
 
  */
-#if (__ARMCC_VERSION < 400000)
-extern void __CLREX(void);
-#else  /* (__ARMCC_VERSION >= 400000)  */
 #define __CLREX                           __clrex
-#endif /* __ARMCC_VERSION  */ 
 
 
 /** \brief  Signed Saturate
@@ -260,196 +253,13 @@
 
 
 
-#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
 /* IAR iccarm specific functions */
 
-#include <intrinsics.h>                     /* IAR Intrinsics   */
-
-#pragma diag_suppress=Pe940
-
-/** \brief  No Operation
-
-    No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-#define __NOP                           __no_operation
-
-
-/** \brief  Wait For Interrupt
-
-    Wait For Interrupt is a hint instruction that suspends execution
-    until one of a number of events occurs.
- */
-static __INLINE  void __WFI(void)
-{
-  __ASM ("wfi");
-}
-
-
-/** \brief  Wait For Event
-
-    Wait For Event is a hint instruction that permits the processor to enter
-    a low-power state until one of a number of events occurs.
- */
-static __INLINE  void __WFE(void)
-{
-  __ASM ("wfe");
-}
-
-
-/** \brief  Send Event
-
-    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-static __INLINE  void __SEV(void)
-{
-  __ASM ("sev");
-}
-
-
-/* intrinsic     void __ISB(void)            (see intrinsics.h) */
-/* intrinsic     void __DSB(void)            (see intrinsics.h) */
-/* intrinsic     void __DMB(void)            (see intrinsics.h) */
-/* intrinsic uint32_t __REV(uint32_t value)  (see intrinsics.h) */
-/* intrinsic          __SSAT                 (see intrinsics.h) */
-/* intrinsic          __USAT                 (see intrinsics.h) */
-
-
-/** \brief  Reverse byte order (16 bit)
-
-    This function reverses the byte order in two unsigned short values.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-static uint32_t __REV16(uint32_t value)
-{
-  __ASM("rev16 r0, r0");
-}
-
-
-/* intrinsic uint32_t __REVSH(uint32_t value)  (see intrinsics.h */
-
-
-#if       (__CORTEX_M >= 0x03)
-
-/** \brief  Reverse bit order of value
-
-    This function reverses the bit order of the given value.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-static uint32_t __RBIT(uint32_t value)
-{
-  __ASM("rbit r0, r0");
-}
+#include <cmsis_iar.h>
 
 
-/** \brief  LDR Exclusive (8 bit)
-
-    This function performs a exclusive LDR command for 8 bit value.
-
-    \param [in]    ptr  Pointer to data
-    \return             value of type uint8_t at (*ptr)
- */
-static uint8_t __LDREXB(volatile uint8_t *addr)
-{
-  __ASM("ldrexb r0, [r0]");
-}
-
-
-/** \brief  LDR Exclusive (16 bit)
-
-    This function performs a exclusive LDR command for 16 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint16_t at (*ptr)
- */
-static uint16_t __LDREXH(volatile uint16_t *addr)
-{
-  __ASM("ldrexh r0, [r0]");
-}
-
-
-/** \brief  LDR Exclusive (32 bit)
-
-    This function performs a exclusive LDR command for 32 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint32_t at (*ptr)
- */
-/* intrinsic unsigned long __LDREX(unsigned long *)  (see intrinsics.h) */
-static uint32_t __LDREXW(volatile uint32_t *addr)
-{
-  __ASM("ldrex r0, [r0]");
-}
-
-
-/** \brief  STR Exclusive (8 bit)
-
-    This function performs a exclusive STR command for 8 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-static uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
-{
-  __ASM("strexb r0, r0, [r1]");
-}
-
-
-/** \brief  STR Exclusive (16 bit)
-
-    This function performs a exclusive STR command for 16 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-static uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
-{
-  __ASM("strexh r0, r0, [r1]");
-}
-
-
-/** \brief  STR Exclusive (32 bit)
-
-    This function performs a exclusive STR command for 32 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-/* intrinsic unsigned long __STREX(unsigned long, unsigned long)  (see intrinsics.h )*/
-static uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
-{
-  __ASM("strex r0, r0, [r1]");
-}
-
-
-/** \brief  Remove the exclusive lock
-
-    This function removes the exclusive lock which is created by LDREX.
-
- */
-static __INLINE void __CLREX(void)
-{
-  __ASM ("clrex");
-}
-
-/* intrinsic   unsigned char __CLZ( unsigned long )      (see intrinsics.h) */
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-#pragma diag_default=Pe940
-
-
-
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
 /* GNU gcc specific functions */
 
 /** \brief  No Operation
@@ -655,7 +465,7 @@
 {
    uint32_t result;
   
-   __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+   __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
    return(result);
 }
 
@@ -673,7 +483,7 @@
 {
    uint32_t result;
   
-   __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+   __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
    return(result);
 }
 
@@ -691,7 +501,7 @@
 {
    uint32_t result;
   
-   __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+   __ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
    return(result);
 }
 
@@ -759,12 +569,12 @@
 
 
 
-#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
 /* TASKING carm specific functions */
 
 /*
  * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
  * Including the CMSIS ones.
  */
 
@@ -772,4 +582,4 @@
 
 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
 
-#endif /* __CORE_CMINSTR_H__ */
+#endif /* __CORE_CMINSTR_H */

Binary file LPC1768/GCC_CS/libcapi.a has changed

Binary file LPC1768/GCC_CS/libmbed.a has changed

Binary file LPC1768/uARM/capi.ar has changed

Binary file LPC1768/uARM/cmsis_nvic.o has changed

--- a/LPC1768/uARM/core_cm3.h	Fri Jan 06 16:40:24 2012 +0000
+++ b/LPC1768/uARM/core_cm3.h	Tue Jan 10 12:00:50 2012 +0000
@@ -1,16 +1,16 @@
 /**************************************************************************//**
  * @file     core_cm3.h
  * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
- * @version  V2.01
- * @date     06. December 2010
+ * @version  V3.00
+ * @date     09. December 2011
  *
  * @note
- * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
  *
  * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M 
- * processor based microcontrollers.  This file can be freely distributed 
- * within development tools that are supporting such ARM based processors. 
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers.  This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
  *
  * @par
  * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
@@ -20,106 +20,144 @@
  * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
  *
  ******************************************************************************/
-#if defined ( __ICCARM__ )                   
+#if defined ( __ICCARM__ )
  #pragma system_include  /* treat file as system include file for MISRA check */
 #endif
 
 #ifdef __cplusplus
  extern "C" {
-#endif 
+#endif
 
 #ifndef __CORE_CM3_H_GENERIC
 #define __CORE_CM3_H_GENERIC
 
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+  
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'. 
 
-/** \mainpage CMSIS Cortex-M3
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
    
-  This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer.
-  It consists of:
- 
-     - Cortex-M Core Register Definitions
-     - Cortex-M functions
-     - Cortex-M instructions
- 
-  The CMSIS Cortex-M3 Core Peripheral Access Layer contains C and assembly functions that ease 
-  access to the Cortex-M Core
- */ 
-
-/** \defgroup CMSIS_LintCinfiguration CMSIS Lint Configuration
-  List of Lint messages which will be suppressed and not shown:
-    - not yet checked
-  .
-  Note:  To re-enable a Message, insert a space before 'lint' *
- 
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code. 
  */
 
 
 /*******************************************************************************
  *                 CMSIS definitions
  ******************************************************************************/
-/** \defgroup CMSIS_core_definitions CMSIS Core Definitions
-  This file defines all structures and symbols for CMSIS core:
-   - CMSIS version number
-   - Cortex-M core 
-   - Cortex-M core Revision Number
+/** \ingroup Cortex_M3
   @{
  */
 
 /*  CMSIS CM3 definitions */
-#define __CM3_CMSIS_VERSION_MAIN  (0x02)                                                       /*!< [31:16] CMSIS HAL main version */
-#define __CM3_CMSIS_VERSION_SUB   (0x00)                                                       /*!< [15:0]  CMSIS HAL sub version  */
-#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number       */
+#define __CM3_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM3_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | \
+                                    __CM3_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
 
-#define __CORTEX_M                (0x03)                                                       /*!< Cortex core                    */
+#define __CORTEX_M                (0x03)                                   /*!< Cortex-M Core                    */
 
 
-#if defined ( __CC_ARM   )
+#if   defined ( __CC_ARM )
   #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
   #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
 
 #elif defined ( __ICCARM__ )
   #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */
-  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
+  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
 
-#elif defined   (  __GNUC__  )
+#elif defined ( __GNUC__ )
   #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
   #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
 
-#elif defined   (  __TASKING__  )
+#elif defined ( __TASKING__ )
   #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
   #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
 
 #endif
 
-#include <stdint.h>                      /*!< standard types definitions                      */
-#include "core_cmInstr.h"                /*!< Core Instruction Access                         */
-#include "core_cmFunc.h"                 /*!< Core Function Access                            */
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+    /* add preprocessor checks */
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
 
 #endif /* __CORE_CM3_H_GENERIC */
 
-
 #ifndef __CMSIS_GENERIC
 
 #ifndef __CORE_CM3_H_DEPENDANT
 #define __CORE_CM3_H_DEPENDANT
 
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM3_REV
+    #define __CM3_REV               0x0200
+    #warning "__CM3_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          4
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
 /* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+ 
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
 #ifdef __cplusplus
-  #define     __I     volatile           /*!< defines 'read only' permissions                 */
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
 #else
-  #define     __I     volatile const     /*!< defines 'read only' permissions                 */
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
 #endif
-#define     __O     volatile             /*!< defines 'write only' permissions                */
-#define     __IO    volatile             /*!< defines 'read / write' permissions              */
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
 
-/*@} end of group CMSIS_core_definitions */
+/*@} end of group Cortex_M3 */
 
 
 
 /*******************************************************************************
  *                 Register Abstraction
- ******************************************************************************/
-/** \defgroup CMSIS_core_register CMSIS Core Register
   Core Register contain:
   - Core Register
   - Core NVIC Register
@@ -127,11 +165,14 @@
   - Core SysTick Register
   - Core Debug Register
   - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
 */
 
-/** \ingroup  CMSIS_core_register   
-    \defgroup CMSIS_CORE CMSIS Core
-  Type definitions for the Cortex-M Core Registers
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
   @{
  */
 
@@ -154,7 +195,7 @@
     uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
     uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
   } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */ 
+  uint32_t w;                            /*!< Type      used for word access                  */
 } APSR_Type;
 
 
@@ -214,9 +255,9 @@
 /*@} end of group CMSIS_CORE */
 
 
-/** \ingroup  CMSIS_core_register   
-    \defgroup CMSIS_NVIC CMSIS NVIC
-  Type definitions for the Cortex-M NVIC Registers
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
   @{
  */
 
@@ -225,26 +266,30 @@
 typedef struct
 {
   __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
-       uint32_t RESERVED0[24];                                   
+       uint32_t RESERVED0[24];
   __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
-       uint32_t RSERVED1[24];                                    
+       uint32_t RSERVED1[24];
   __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
-       uint32_t RESERVED2[24];                                   
+       uint32_t RESERVED2[24];
   __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
-       uint32_t RESERVED3[24];                                   
+       uint32_t RESERVED3[24];
   __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
-       uint32_t RESERVED4[56];                                   
+       uint32_t RESERVED4[56];
   __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
-       uint32_t RESERVED5[644];                                  
+       uint32_t RESERVED5[644];
   __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
-}  NVIC_Type;                                               
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
 
 /*@} end of group CMSIS_NVIC */
 
 
-/** \ingroup  CMSIS_core_register   
-    \defgroup CMSIS_SCB CMSIS SCB
-  Type definitions for the Cortex-M System Control Block Registers
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
   @{
  */
 
@@ -252,26 +297,28 @@
  */
 typedef struct
 {
-  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPU ID Base Register                                  */
-  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control State Register                      */
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
   __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
-  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt / Reset Control Register        */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
   __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
   __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
   __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
   __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
   __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
-  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  Hard Fault Status Register                            */
+  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
   __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
-  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  Mem Manage Address Register                           */
-  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  Bus Fault Address Register                            */
+  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
   __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
   __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
   __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
   __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
   __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
-  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  ISA Feature Register                                  */
-} SCB_Type;                                                
+  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+       uint32_t RESERVED0[5];
+  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+} SCB_Type;
 
 /* SCB CPUID Register Definitions */
 #define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
@@ -280,6 +327,9 @@
 #define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
 #define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
 
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
 #define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
 #define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
 
@@ -317,12 +367,17 @@
 #define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
 #define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
 
-/* SCB Interrupt Control State Register Definitions */
+/* SCB Vector Table Offset Register Definitions */
+#if (__CM3_REV < 0x0201)                   /* core r2p1 */
 #define SCB_VTOR_TBLBASE_Pos               29                                             /*!< SCB VTOR: TBLBASE Position */
 #define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
 
 #define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
 #define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+#endif
 
 /* SCB Application Interrupt and Reset Control Register Definitions */
 #define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
@@ -408,7 +463,7 @@
 
 #define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
 #define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
-                                     
+
 #define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
 #define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
 
@@ -457,9 +512,46 @@
 /*@} end of group CMSIS_SCB */
 
 
-/** \ingroup  CMSIS_core_register   
-    \defgroup CMSIS_SysTick CMSIS SysTick
-  Type definitions for the Cortex-M System Timer Registers
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register      */
+#else
+       uint32_t RESERVED1[1];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
   @{
  */
 
@@ -507,9 +599,9 @@
 /*@} end of group CMSIS_SysTick */
 
 
-/** \ingroup  CMSIS_core_register   
-    \defgroup CMSIS_ITM CMSIS ITM
-  Type definitions for the Cortex-M Instrumentation Trace Macrocell (ITM)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
   @{
  */
 
@@ -517,134 +609,59 @@
  */
 typedef struct
 {
-  __O  union  
+  __O  union
   {
     __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
     __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
     __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
   }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
-       uint32_t RESERVED0[864];                                 
-  __IO uint32_t TER;                     /*!< Offset:       (R/W)  ITM Trace Enable Register                 */
-       uint32_t RESERVED1[15];                                  
-  __IO uint32_t TPR;                     /*!< Offset:       (R/W)  ITM Trace Privilege Register              */
-       uint32_t RESERVED2[15];                                  
-  __IO uint32_t TCR;                     /*!< Offset:       (R/W)  ITM Trace Control Register                */
-       uint32_t RESERVED3[29];                                  
-  __IO uint32_t IWR;                     /*!< Offset:       (R/W)  ITM Integration Write Register            */
-  __IO uint32_t IRR;                     /*!< Offset:       (R/W)  ITM Integration Read Register             */
-  __IO uint32_t IMCR;                    /*!< Offset:       (R/W)  ITM Integration Mode Control Register     */
-       uint32_t RESERVED4[43];                                  
-  __IO uint32_t LAR;                     /*!< Offset:       (R/W)  ITM Lock Access Register                  */
-  __IO uint32_t LSR;                     /*!< Offset:       (R/W)  ITM Lock Status Register                  */
-       uint32_t RESERVED5[6];                                   
-  __I  uint32_t PID4;                    /*!< Offset:       (R/ )  ITM Peripheral Identification Register #4 */
-  __I  uint32_t PID5;                    /*!< Offset:       (R/ )  ITM Peripheral Identification Register #5 */
-  __I  uint32_t PID6;                    /*!< Offset:       (R/ )  ITM Peripheral Identification Register #6 */
-  __I  uint32_t PID7;                    /*!< Offset:       (R/ )  ITM Peripheral Identification Register #7 */
-  __I  uint32_t PID0;                    /*!< Offset:       (R/ )  ITM Peripheral Identification Register #0 */
-  __I  uint32_t PID1;                    /*!< Offset:       (R/ )  ITM Peripheral Identification Register #1 */
-  __I  uint32_t PID2;                    /*!< Offset:       (R/ )  ITM Peripheral Identification Register #2 */
-  __I  uint32_t PID3;                    /*!< Offset:       (R/ )  ITM Peripheral Identification Register #3 */
-  __I  uint32_t CID0;                    /*!< Offset:       (R/ )  ITM Component  Identification Register #0 */
-  __I  uint32_t CID1;                    /*!< Offset:       (R/ )  ITM Component  Identification Register #1 */
-  __I  uint32_t CID2;                    /*!< Offset:       (R/ )  ITM Component  Identification Register #2 */
-  __I  uint32_t CID3;                    /*!< Offset:       (R/ )  ITM Component  Identification Register #3 */
-} ITM_Type;                                                
+       uint32_t RESERVED0[864];
+  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+       uint32_t RESERVED1[15];
+  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+       uint32_t RESERVED2[15];
+  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+} ITM_Type;
 
 /* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
+#define ITM_TPR_PRIVMASK_Pos                0                                          /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)             /*!< ITM TPR: PRIVMASK Mask */
 
 /* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+#define ITM_TCR_BUSY_Pos                   23                                          /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                   /*!< ITM TCR: BUSY Mask */
 
-#define ITM_TCR_ATBID_Pos                  16                                             /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_ATBID_Msk                  (0x7FUL << ITM_TCR_ATBID_Pos)                  /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+#define ITM_TCR_TraceBusID_Pos             16                                          /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)          /*!< ITM TCR: ATBID Mask */
 
-#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+#define ITM_TCR_GTSFREQ_Pos                10                                          /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                /*!< ITM TCR: Global timestamp frequency Mask */
 
-#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+#define ITM_TCR_TSPrescale_Pos              8                                          /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)             /*!< ITM TCR: TSPrescale Mask */
 
-#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
+#define ITM_TCR_SWOENA_Pos                  4                                          /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                 /*!< ITM TCR: SWOENA Mask */
 
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
+#define ITM_TCR_TXENA_Pos                   3                                          /*!< ITM TCR: TXENA Position */
+#define ITM_TCR_TXENA_Msk                  (1UL << ITM_TCR_TXENA_Pos)                  /*!< ITM TCR: TXENA Mask */
 
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
+#define ITM_TCR_SYNCENA_Pos                 2                                          /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                /*!< ITM TCR: SYNCENA Mask */
 
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+#define ITM_TCR_TSENA_Pos                   1                                          /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                  /*!< ITM TCR: TSENA Mask */
 
-#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
+#define ITM_TCR_ITMENA_Pos                  0                                          /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                 /*!< ITM TCR: ITM Enable bit Mask */
 
 /*@}*/ /* end of group CMSIS_ITM */
 
 
-/** \ingroup  CMSIS_core_register   
-    \defgroup CMSIS_InterruptType CMSIS Interrupt Type
-  Type definitions for the Cortex-M Interrupt Type Register
-  @{
- */
-
-/** \brief  Structure type to access the Interrupt Type Register.
- */
-typedef struct
-{
-       uint32_t RESERVED0;
-  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Control Type Register */
-#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
-  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register      */
-#else
-       uint32_t RESERVED1;
-#endif
-} InterruptType_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define IntType_ICTR_INTLINESNUM_Pos  0                                                   /*!< InterruptType ICTR: INTLINESNUM Position */
-#define IntType_ICTR_INTLINESNUM_Msk (0x1FUL << IntType_ICTR_INTLINESNUM_Pos)             /*!< InterruptType ICTR: INTLINESNUM Mask */
-
-/* Auxiliary Control Register Definitions */
-#define IntType_ACTLR_DISFOLD_Pos     2                                                   /*!< InterruptType ACTLR: DISFOLD Position */
-#define IntType_ACTLR_DISFOLD_Msk    (1UL << IntType_ACTLR_DISFOLD_Pos)                   /*!< InterruptType ACTLR: DISFOLD Mask */
-
-#define IntType_ACTLR_DISDEFWBUF_Pos  1                                                   /*!< InterruptType ACTLR: DISDEFWBUF Position */
-#define IntType_ACTLR_DISDEFWBUF_Msk (1UL << IntType_ACTLR_DISDEFWBUF_Pos)                /*!< InterruptType ACTLR: DISDEFWBUF Mask */
-
-#define IntType_ACTLR_DISMCYCINT_Pos  0                                                   /*!< InterruptType ACTLR: DISMCYCINT Position */
-#define IntType_ACTLR_DISMCYCINT_Msk (1UL << IntType_ACTLR_DISMCYCINT_Pos)                /*!< InterruptType ACTLR: DISMCYCINT Mask */
-
-/*@}*/ /* end of group CMSIS_InterruptType */
-
-
 #if (__MPU_PRESENT == 1)
-/** \ingroup  CMSIS_core_register   
-    \defgroup CMSIS_MPU CMSIS MPU
-  Type definitions for the Cortex-M Memory Protection Unit (MPU)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
   @{
  */
 
@@ -663,7 +680,7 @@
   __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
   __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
   __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;                                                
+} MPU_Type;
 
 /* MPU Type Register */
 #define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
@@ -700,23 +717,8 @@
 #define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
 
 /* MPU Region Attribute and Size Register */
-#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: XN Position */
-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: XN Mask */
-
-#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: AP Position */
-#define MPU_RASR_AP_Msk                    (7UL << MPU_RASR_AP_Pos)                       /*!< MPU RASR: AP Mask */
-
-#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: TEX Position */
-#define MPU_RASR_TEX_Msk                   (7UL << MPU_RASR_TEX_Pos)                      /*!< MPU RASR: TEX Mask */
-
-#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: Shareable bit Position */
-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: Shareable bit Mask */
-
-#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: Cacheable bit Position */
-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: Cacheable bit Mask */
-
-#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: Bufferable bit Position */
-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: Bufferable bit Mask */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
 
 #define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
 #define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
@@ -724,16 +726,16 @@
 #define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
 #define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
 
-#define MPU_RASR_ENA_Pos                     0                                            /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENA_Msk                    (0x1UL << MPU_RASR_ENA_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
 
 /*@} end of group CMSIS_MPU */
 #endif
 
 
-/** \ingroup  CMSIS_core_register   
-    \defgroup CMSIS_CoreDebug CMSIS Core Debug
-  Type definitions for the Cortex-M Core Debug Registers
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Type definitions for the Core Debug Registers
   @{
  */
 
@@ -834,28 +836,30 @@
 /*@} end of group CMSIS_CoreDebug */
 
 
-/** \ingroup  CMSIS_core_register   
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
   @{
  */
- 
+
 /* Memory mapping of Cortex-M3 Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
-#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                  */
-#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address           */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
 
-#define InterruptType       ((InterruptType_Type *) SCS_BASE)         /*!< Interrupt Type Register           */
-#define SCB                 ((SCB_Type *)           SCB_BASE)         /*!< SCB configuration struct          */
-#define SysTick             ((SysTick_Type *)       SysTick_BASE)     /*!< SysTick configuration struct      */
-#define NVIC                ((NVIC_Type *)          NVIC_BASE)        /*!< NVIC configuration struct         */
-#define ITM                 ((ITM_Type *)           ITM_BASE)         /*!< ITM configuration struct          */
-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct   */
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
 
 #if (__MPU_PRESENT == 1)
-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit            */
-  #define MPU               ((MPU_Type*)            MPU_BASE)         /*!< Memory Protection Unit            */
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
 #endif
 
 /*@} */
@@ -864,42 +868,43 @@
 
 /*******************************************************************************
  *                Hardware Abstraction Layer
- ******************************************************************************/
-/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface
   Core Function Interface contains:
   - Core NVIC Functions
   - Core SysTick Functions
   - Core Debug Functions
   - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
 */
 
 
 
 /* ##########################   NVIC functions  #################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface   
-    \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions
-  @{
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
  */
 
 /** \brief  Set Priority Grouping
 
-  This function sets the priority grouping field using the required unlock sequence.
+  The function sets the priority grouping field using the required unlock sequence.
   The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
   Only values from 0..7 are used.
   In case of a conflict between priority grouping and available
-  priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
 
-    \param [in]      PriorityGroup  Priority grouping field
+    \param [in]      PriorityGroup  Priority grouping field.
  */
 static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
 {
   uint32_t reg_value;
-  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);                         /* only values 0..7 are used          */
-  
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
+
   reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
   reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
-  reg_value  =  (reg_value                       |
-                (0x5FA << SCB_AIRCR_VECTKEY_Pos) | 
+  reg_value  =  (reg_value                                 |
+                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
                 (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
   SCB->AIRCR =  reg_value;
 }
@@ -907,10 +912,9 @@
 
 /** \brief  Get Priority Grouping
 
-  This function gets the priority grouping from NVIC Interrupt Controller.
-  Priority grouping is SCB->AIRCR [10:8] PRIGROUP field.
+  The function reads the priority grouping field from the NVIC Interrupt Controller.
 
-    \return                Priority grouping field
+    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
  */
 static __INLINE uint32_t NVIC_GetPriorityGrouping(void)
 {
@@ -920,10 +924,9 @@
 
 /** \brief  Enable External Interrupt
 
-    This function enables a device specific interupt in the NVIC interrupt controller.
-    The interrupt number cannot be a negative value. 
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
 
-    \param [in]      IRQn  Number of the external interrupt to enable
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
  */
 static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
 {
@@ -933,10 +936,9 @@
 
 /** \brief  Disable External Interrupt
 
-    This function disables a device specific interupt in the NVIC interrupt controller.
-    The interrupt number cannot be a negative value. 
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
 
-    \param [in]      IRQn  Number of the external interrupt to disable
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
  */
 static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
 {
@@ -946,12 +948,13 @@
 
 /** \brief  Get Pending Interrupt
 
-    This function reads the pending register in the NVIC and returns the pending bit
-    for the specified interrupt. 
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
 
-    \param [in]      IRQn  Number of the interrupt for get pending
-    \return             0  Interrupt status is not pending
-    \return             1  Interrupt status is pending
+    \param [in]      IRQn  Interrupt number.
+    
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
  */
 static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
 {
@@ -961,10 +964,9 @@
 
 /** \brief  Set Pending Interrupt
 
-    This function sets the pending bit for the specified interrupt. 
-    The interrupt number cannot be a negative value.
+    The function sets the pending bit of an external interrupt.
 
-    \param [in]      IRQn  Number of the interrupt for set pending
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
  */
 static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
 {
@@ -974,10 +976,9 @@
 
 /** \brief  Clear Pending Interrupt
 
-    This function clears the pending bit for the specified interrupt. 
-    The interrupt number cannot be a negative value.
+    The function clears the pending bit of an external interrupt.
 
-    \param [in]      IRQn  Number of the interrupt for clear pending
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
  */
 static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
 {
@@ -987,10 +988,12 @@
 
 /** \brief  Get Active Interrupt
 
-    This function reads the active register in NVIC and returns the active bit. 
-    \param [in]      IRQn  Number of the interrupt for get active
-    \return             0  Interrupt status is not active
-    \return             1  Interrupt status is active
+    The function reads the active register in NVIC and returns the active bit.
+    
+    \param [in]      IRQn  Interrupt number.
+    
+    \return             0  Interrupt status is not active.
+    \return             1  Interrupt status is active.
  */
 static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
 {
@@ -1000,14 +1003,12 @@
 
 /** \brief  Set Interrupt Priority
 
-    This function sets the priority for the specified interrupt. The interrupt 
-    number can be positive to specify an external (device specific) 
-    interrupt, or negative to specify an internal (core) interrupt.
+    The function sets the priority of an interrupt. 
 
-    Note: The priority cannot be set for every core interrupt.
+    \note The priority cannot be set for every core interrupt.
 
-    \param [in]      IRQn  Number of the interrupt for set priority
-    \param [in]  priority  Priority to set
+    \param [in]      IRQn  Interrupt number. 
+    \param [in]  priority  Priority to set.
  */
 static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
 {
@@ -1020,15 +1021,14 @@
 
 /** \brief  Get Interrupt Priority
 
-    This function reads the priority for the specified interrupt. The interrupt 
-    number can be positive to specify an external (device specific) 
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
     interrupt, or negative to specify an internal (core) interrupt.
 
-    The returned priority value is automatically aligned to the implemented
-    priority bits of the microcontroller.
 
-    \param [in]   IRQn  Number of the interrupt for get priority
-    \return             Interrupt Priority
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
  */
 static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
 {
@@ -1042,17 +1042,15 @@
 
 /** \brief  Encode Priority
 
-    This function encodes the priority for an interrupt with the given priority group,
-    preemptive priority value and sub priority value.
+    The function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value, and subpriority value.
     In case of a conflict between priority grouping and available
-    priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
- 
-    The returned priority value can be used for NVIC_SetPriority(...) function
+    priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
 
-    \param [in]     PriorityGroup  Used priority group
-    \param [in]   PreemptPriority  Preemptive priority value (starting from 0)
-    \param [in]       SubPriority  Sub priority value (starting from 0)
-    \return                        Encoded priority for the interrupt
+    \param [in]     PriorityGroup  Used priority group.
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+    \param [in]       SubPriority  Subpriority value (starting from 0).
+    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
  */
 static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
 {
@@ -1062,7 +1060,7 @@
 
   PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
   SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
- 
+
   return (
            ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
            ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
@@ -1072,17 +1070,15 @@
 
 /** \brief  Decode Priority
 
-    This function decodes an interrupt priority value with the given priority group to 
-    preemptive priority value and sub priority value.
+    The function decodes an interrupt priority value with a given priority group to
+    preemptive priority value and subpriority value.
     In case of a conflict between priority grouping and available
     priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
- 
-    The priority value can be retrieved with NVIC_GetPriority(...) function
- 
-    \param [in]         Priority   Priority value
-    \param [in]     PriorityGroup  Used priority group
-    \param [out] pPreemptPriority  Preemptive priority value (starting from 0)
-    \param [out]     pSubPriority  Sub priority value (starting from 0)
+
+    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+    \param [in]     PriorityGroup  Used priority group.
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+    \param [out]     pSubPriority  Subpriority value (starting from 0).
  */
 static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
 {
@@ -1092,7 +1088,7 @@
 
   PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
   SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-  
+
   *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
   *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
 }
@@ -1100,16 +1096,16 @@
 
 /** \brief  System Reset
 
-    This function initiate a system reset request to reset the MCU.
+    The function initiates a system reset request to reset the MCU.
  */
 static __INLINE void NVIC_SystemReset(void)
 {
   __DSB();                                                     /* Ensure all outstanding memory accesses included
-                                                                  buffered write are completed before reset */              
-  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      | 
-                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
                  SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
-  __DSB();                                                     /* Ensure completion of memory access */              
+  __DSB();                                                     /* Ensure completion of memory access */
   while(1);                                                    /* wait until reset */
 }
 
@@ -1118,8 +1114,9 @@
 
 
 /* ##################################    SysTick function  ############################################ */
-/** \ingroup  CMSIS_Core_FunctionInterface   
-    \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
   @{
  */
 
@@ -1127,22 +1124,28 @@
 
 /** \brief  System Tick Configuration
 
-    This function initialises the system tick timer and its interrupt and start the system tick timer.
-    Counter is in free running mode to generate periodical interrupts.
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.   
 
-    \param [in]  ticks  Number of ticks between two interrupts
-    \return          0  Function succeeded
-    \return          1  Function failed
+    \param [in]  ticks  Number of ticks between two interrupts.
+    
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+    
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the 
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> 
+    must contain a vendor-specific implementation of this function.
+
  */
 static __INLINE uint32_t SysTick_Config(uint32_t ticks)
-{ 
+{
   if (ticks > SysTick_LOAD_RELOAD_Msk)  return (1);            /* Reload value impossible */
-                                                               
+
   SysTick->LOAD  = (ticks & SysTick_LOAD_RELOAD_Msk) - 1;      /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Cortex-M0 System Interrupts */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
   SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk | 
-                   SysTick_CTRL_TICKINT_Msk   | 
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
                    SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
   return (0);                                                  /* Function successful */
 }
@@ -1154,45 +1157,44 @@
 
 
 /* ##################################### Debug In/Output function ########################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface   
-    \defgroup CMSIS_core_DebugFunctions CMSIS Core Debug Functions
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions ITM Functions
+    \brief   Functions that access the ITM debug interface.
   @{
  */
 
-extern volatile int32_t ITM_RxBuffer;                    /*!< external variable to receive characters                    */
-#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
 
 
 /** \brief  ITM Send Character
 
-    This function transmits a character via the ITM channel 0. 
-    It just returns when no debugger is connected that has booked the output.  
-    It is blocking when a debugger is connected, but the previous character send is not transmitted. 
+    The function transmits a character via the ITM channel 0, and
+    \li Just returns when no debugger is connected that has booked the output.
+    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
 
-    \param [in]     ch  Character to transmit
-    \return             Character to transmit
+    \param [in]     ch  Character to transmit.
+    
+    \returns            Character to transmit.
  */
 static __INLINE uint32_t ITM_SendChar (uint32_t ch)
 {
-  if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk)  &&      /* Trace enabled */
-      (ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
+  if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
       (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
   {
     while (ITM->PORT[0].u32 == 0);
     ITM->PORT[0].u8 = (uint8_t) ch;
-  }  
+  }
   return (ch);
 }
 
 
 /** \brief  ITM Receive Character
 
-    This function inputs a character via external variable ITM_RxBuffer. 
-    It just returns when no debugger is connected that has booked the output.  
-    It is blocking when a debugger is connected, but the previous character send is not transmitted. 
+    The function inputs a character via the external variable \ref ITM_RxBuffer.
 
-    \return             Received character
-    \return         -1  No character received
+    \return             Received character.
+    \return         -1  No character pending.
  */
 static __INLINE int32_t ITM_ReceiveChar (void) {
   int32_t ch = -1;                           /* no character available */
@@ -1201,18 +1203,17 @@
     ch = ITM_RxBuffer;
     ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
   }
-  
-  return (ch); 
+
+  return (ch);
 }
 
 
 /** \brief  ITM Check Character
 
-    This function checks external variable ITM_RxBuffer whether a character is available or not. 
-    It returns '1' if a character is available and '0' if no character is available. 
+    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
 
-    \return          0  No character available
-    \return          1  Character available
+    \return          0  No character available.
+    \return          1  Character available.
  */
 static __INLINE int32_t ITM_CheckChar (void) {
 
@@ -1232,5 +1233,3 @@
 #ifdef __cplusplus
 }
 #endif
-
-/*lint -restore */

Binary file LPC1768/uARM/core_cm3.o has changed

--- a/LPC1768/uARM/core_cmFunc.h	Fri Jan 06 16:40:24 2012 +0000
+++ b/LPC1768/uARM/core_cmFunc.h	Tue Jan 10 12:00:50 2012 +0000
@@ -1,11 +1,11 @@
 /**************************************************************************//**
  * @file     core_cmFunc.h
  * @brief    CMSIS Cortex-M Core Function Access Header File
- * @version  V2.01
- * @date     06. December 2010
+ * @version  V3.00
+ * @date     09. December 2011
  *
  * @note
- * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
  *
  * @par
  * ARM Limited (ARM) is supplying this software for use with Cortex-M 
@@ -21,8 +21,9 @@
  *
  ******************************************************************************/
 
-#ifndef __CORE_CMFUNC_H__
-#define __CORE_CMFUNC_H__
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
 
 /* ###########################  Core Function Access  ########################### */
 /** \ingroup  CMSIS_Core_FunctionInterface   
@@ -30,9 +31,13 @@
   @{
  */
 
-#if defined ( __CC_ARM   ) /*------------------ RealView Compiler ----------------*/
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
 /* ARM armcc specific functions */
 
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
 /* intrinsic void __enable_irq();     */
 /* intrinsic void __disable_irq();    */
 
@@ -42,15 +47,11 @@
 
     \return               Control Register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_CONTROL(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_CONTROL(void)
 {
   register uint32_t __regControl         __ASM("control");
   return(__regControl);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Set Control Register
@@ -59,32 +60,24 @@
 
     \param [in]    control  Control Register value to set
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          void __set_CONTROL(uint32_t control);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE void __set_CONTROL(uint32_t control)
 {
   register uint32_t __regControl         __ASM("control");
   __regControl = control;
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
-/** \brief  Get ISPR Register
-
-    This function returns the content of the ISPR Register.
+/** \brief  Get IPSR Register
 
-    \return               ISPR Register value
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_IPSR(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_IPSR(void)
 {
   register uint32_t __regIPSR          __ASM("ipsr");
   return(__regIPSR);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Get APSR Register
@@ -93,15 +86,11 @@
 
     \return               APSR Register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_APSR(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_APSR(void)
 {
   register uint32_t __regAPSR          __ASM("apsr");
   return(__regAPSR);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Get xPSR Register
@@ -110,15 +99,11 @@
 
     \return               xPSR Register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_xPSR(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_xPSR(void)
 {
   register uint32_t __regXPSR          __ASM("xpsr");
   return(__regXPSR);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Get Process Stack Pointer
@@ -127,15 +112,11 @@
 
     \return               PSP Register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_PSP(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_PSP(void)
 {
   register uint32_t __regProcessStackPointer  __ASM("psp");
   return(__regProcessStackPointer);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Set Process Stack Pointer
@@ -144,15 +125,11 @@
 
     \param [in]    topOfProcStack  Process Stack Pointer value to set
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          void __set_PSP(uint32_t topOfProcStack);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE void __set_PSP(uint32_t topOfProcStack)
 {
   register uint32_t __regProcessStackPointer  __ASM("psp");
   __regProcessStackPointer = topOfProcStack;
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Get Main Stack Pointer
@@ -161,15 +138,11 @@
 
     \return               MSP Register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_MSP(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_MSP(void)
 {
   register uint32_t __regMainStackPointer     __ASM("msp");
   return(__regMainStackPointer);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Set Main Stack Pointer
@@ -178,15 +151,11 @@
 
     \param [in]    topOfMainStack  Main Stack Pointer value to set
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          void __set_MSP(uint32_t topOfMainStack);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE void __set_MSP(uint32_t topOfMainStack)
 {
   register uint32_t __regMainStackPointer     __ASM("msp");
   __regMainStackPointer = topOfMainStack;
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Get Priority Mask
@@ -195,15 +164,11 @@
 
     \return               Priority Mask value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_PRIMASK(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_PRIMASK(void)
 {
   register uint32_t __regPriMask         __ASM("primask");
   return(__regPriMask);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Set Priority Mask
@@ -212,15 +177,11 @@
 
     \param [in]    priMask  Priority Mask
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          void __set_PRIMASK(uint32_t priMask);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE void __set_PRIMASK(uint32_t priMask)
 {
   register uint32_t __regPriMask         __ASM("primask");
   __regPriMask = (priMask);
 }
-#endif /*  __ARMCC_VERSION  */ 
  
 
 #if       (__CORTEX_M >= 0x03)
@@ -247,15 +208,11 @@
 
     \return               Base Priority register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_BASEPRI(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t  __get_BASEPRI(void)
 {
   register uint32_t __regBasePri         __ASM("basepri");
   return(__regBasePri);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Set Base Priority
@@ -264,15 +221,11 @@
 
     \param [in]    basePri  Base Priority value to set
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          void __set_BASEPRI(uint32_t basePri);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE void __set_BASEPRI(uint32_t basePri)
 {
   register uint32_t __regBasePri         __ASM("basepri");
   __regBasePri = (basePri & 0xff);
 }
-#endif /*  __ARMCC_VERSION  */ 
  
 
 /** \brief  Get Fault Mask
@@ -281,15 +234,11 @@
 
     \return               Fault Mask register value
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_FAULTMASK(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE uint32_t __get_FAULTMASK(void)
 {
   register uint32_t __regFaultMask       __ASM("faultmask");
   return(__regFaultMask);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 
 /** \brief  Set Fault Mask
@@ -298,15 +247,11 @@
 
     \param [in]    faultMask  Fault Mask value to set
  */
-#if       (__ARMCC_VERSION <  400000)
-extern          void __set_FAULTMASK(uint32_t faultMask);
-#else  /* (__ARMCC_VERSION >= 400000) */
 static __INLINE void __set_FAULTMASK(uint32_t faultMask)
 {
   register uint32_t __regFaultMask       __ASM("faultmask");
-  __regFaultMask = (faultMask & 1);
+  __regFaultMask = (faultMask & (uint32_t)1);
 }
-#endif /*  __ARMCC_VERSION  */ 
 
 #endif /* (__CORTEX_M >= 0x03) */
 
@@ -321,7 +266,7 @@
  */
 static __INLINE uint32_t __get_FPSCR(void)
 {
-#if (__FPU_PRESENT == 1)
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
   register uint32_t __regfpscr         __ASM("fpscr");
   return(__regfpscr);
 #else
@@ -338,7 +283,7 @@
  */
 static __INLINE void __set_FPSCR(uint32_t fpscr)
 {
-#if (__FPU_PRESENT == 1)
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
   register uint32_t __regfpscr         __ASM("fpscr");
   __regfpscr = (fpscr);
 #endif
@@ -347,192 +292,12 @@
 #endif /* (__CORTEX_M == 0x04) */
 
 
- #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
 /* IAR iccarm specific functions */
 
-#if defined (__ICCARM__)
-  #include <intrinsics.h>                     /* IAR Intrinsics   */
-#endif
-
-#pragma diag_suppress=Pe940
-
-/** \brief  Enable IRQ Interrupts
-
-  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
-  Can only be executed in Privileged modes.
- */
-#define __enable_irq                              __enable_interrupt
-
-
-/** \brief  Disable IRQ Interrupts
-
-  This function disables IRQ interrupts by setting the I-bit in the CPSR.
-  Can only be executed in Privileged modes.
- */
-#define __disable_irq                             __disable_interrupt
-
-
-/* intrinsic unsigned long __get_CONTROL( void ); (see intrinsic.h) */
-/* intrinsic void __set_CONTROL( unsigned long ); (see intrinsic.h) */
-
-
-/** \brief  Get ISPR Register
-
-    This function returns the content of the ISPR Register.
-
-    \return               ISPR Register value
- */
-static uint32_t __get_IPSR(void)
-{
-  __ASM("mrs r0, ipsr");
-}
-
-
-/** \brief  Get APSR Register
-
-    This function returns the content of the APSR Register.
-
-    \return               APSR Register value
- */
-static uint32_t __get_APSR(void)
-{
-  __ASM("mrs r0, apsr");
-}
-
-
-/** \brief  Get xPSR Register
-
-    This function returns the content of the xPSR Register.
-
-    \return               xPSR Register value
- */
-static uint32_t __get_xPSR(void)
-{
-  __ASM("mrs r0, psr");           // assembler does not know "xpsr"
-}
-
-
-/** \brief  Get Process Stack Pointer
-
-    This function returns the current value of the Process Stack Pointer (PSP).
-
-    \return               PSP Register value
- */
-static uint32_t __get_PSP(void)
-{
-  __ASM("mrs r0, psp");
-}
- 
-
-/** \brief  Set Process Stack Pointer
-
-    This function assigns the given value to the Process Stack Pointer (PSP).
-
-    \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-static void __set_PSP(uint32_t topOfProcStack)
-{
-  __ASM("msr psp, r0");
-}
-
-
-/** \brief  Get Main Stack Pointer
-
-    This function returns the current value of the Main Stack Pointer (MSP).
+#include <cmsis_iar.h>
 
-    \return               MSP Register value
- */
-static uint32_t __get_MSP(void)
-{
-  __ASM("mrs r0, msp");
-}
- 
-
-/** \brief  Set Main Stack Pointer
-
-    This function assigns the given value to the Main Stack Pointer (MSP).
-
-    \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-static void __set_MSP(uint32_t topOfMainStack)
-{
-  __ASM("msr msp, r0");
-}
- 
-
-/* intrinsic unsigned long __get_PRIMASK( void ); (see intrinsic.h) */
-/* intrinsic void __set_PRIMASK( unsigned long ); (see intrinsic.h) */
- 
-
-#if       (__CORTEX_M >= 0x03)
-
-/** \brief  Enable FIQ
-
-    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-static __INLINE void __enable_fault_irq(void)
-{
-  __ASM ("cpsie f");
-}
-
-
-/** \brief  Disable FIQ
-
-    This function disables FIQ interrupts by setting the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-static __INLINE void __disable_fault_irq(void)
-{
-  __ASM ("cpsid f");
-}
-
-
-/* intrinsic unsigned long __get_BASEPRI( void );   (see intrinsic.h) */
-/* intrinsic void __set_BASEPRI( unsigned long );   (see intrinsic.h) */
-/* intrinsic unsigned long __get_FAULTMASK( void ); (see intrinsic.h) */
-/* intrinsic void __set_FAULTMASK(unsigned long);   (see intrinsic.h) */
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-#if       (__CORTEX_M == 0x04)
-
-/** \brief  Get FPSCR
-
-    This function returns the current value of the Floating Point Status/Control register.
-
-    \return               Floating Point Status/Control register value
- */
-static uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1)
-  __ASM("vmrs r0, fpscr"); 
-#else
-  return(0);
-#endif
-}
-
-
-/** \brief  Set FPSCR
-
-    This function assigns the given value to the Floating Point Status/Control register.
-
-    \param [in]    fpscr  Floating Point Status/Control value to set
- */
-static void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1)
-  __ASM("vmsr fpscr, r0");
-#endif
-}
-
-#endif /* (__CORTEX_M == 0x04) */
-
-#pragma diag_default=Pe940
-
-
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
 /* GNU gcc specific functions */
 
 /** \brief  Enable IRQ Interrupts
@@ -584,11 +349,11 @@
 }
 
 
-/** \brief  Get ISPR Register
+/** \brief  Get IPSR Register
 
-    This function returns the content of the ISPR Register.
+    This function returns the content of the IPSR Register.
 
-    \return               ISPR Register value
+    \return               IPSR Register value
  */
 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void)
 {
@@ -800,10 +565,10 @@
  */
 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void)
 {
-#if (__FPU_PRESENT == 1)
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
   uint32_t result;
 
-  __ASM volatile ("MRS %0, fpscr" : "=r" (result) );
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
   return(result);
 #else
    return(0);
@@ -819,15 +584,15 @@
  */
 __attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr)
 {
-#if (__FPU_PRESENT == 1)
-  __ASM volatile ("MSR fpscr, %0" : : "r" (fpscr) );
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );
 #endif
 }
 
 #endif /* (__CORTEX_M == 0x04) */
 
 
-#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
 /* TASKING carm specific functions */
 
 /*
@@ -841,4 +606,4 @@
 /*@} end of CMSIS_Core_RegAccFunctions */
 
 
-#endif /* __CORE_CMFUNC_H__ */
+#endif /* __CORE_CMFUNC_H */

--- a/LPC1768/uARM/core_cmInstr.h	Fri Jan 06 16:40:24 2012 +0000
+++ b/LPC1768/uARM/core_cmInstr.h	Tue Jan 10 12:00:50 2012 +0000
@@ -1,11 +1,11 @@
 /**************************************************************************//**
  * @file     core_cmInstr.h
  * @brief    CMSIS Cortex-M Core Instruction Access Header File
- * @version  V2.01
- * @date     06. December 2010
+ * @version  V3.00
+ * @date     09. December 2011
  *
  * @note
- * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
  *
  * @par
  * ARM Limited (ARM) is supplying this software for use with Cortex-M 
@@ -21,8 +21,8 @@
  *
  ******************************************************************************/
 
-#ifndef __CORE_CMINSTR_H__
-#define __CORE_CMINSTR_H__
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
 
 
 /* ##########################  Core Instruction Access  ######################### */
@@ -31,9 +31,14 @@
   @{
 */
 
-#if defined ( __CC_ARM   ) /*------------------ RealView Compiler ----------------*/
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
 /* ARM armcc specific functions */
 
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
 /** \brief  No Operation
 
     No Operation does nothing. This instruction can be used for code alignment purposes.
@@ -106,15 +111,11 @@
     \param [in]    value  Value to reverse
     \return               Reversed value
  */
-#if (__ARMCC_VERSION < 400677)
-extern uint32_t __REV16(uint32_t value);
-#else  /* (__ARMCC_VERSION >= 400677)  */
-static __INLINE __ASM uint32_t __REV16(uint32_t value)
+static __attribute__((section(".rev16_text"))) __INLINE __ASM uint32_t __REV16(uint32_t value)
 {
   rev16 r0, r0
   bx lr
 }
-#endif /* __ARMCC_VERSION  */ 
 
 
 /** \brief  Reverse byte order in signed short value
@@ -124,15 +125,11 @@
     \param [in]    value  Value to reverse
     \return               Reversed value
  */
-#if (__ARMCC_VERSION < 400677)
-extern int32_t __REVSH(int32_t value);
-#else  /* (__ARMCC_VERSION >= 400677)  */
-static __INLINE __ASM int32_t __REVSH(int32_t value)
+static __attribute__((section(".revsh_text"))) __INLINE __ASM int32_t __REVSH(int32_t value)
 {
   revsh r0, r0
   bx lr
 }
-#endif /* __ARMCC_VERSION  */ 
 
 
 #if       (__CORTEX_M >= 0x03)
@@ -218,11 +215,7 @@
     This function removes the exclusive lock which is created by LDREX.
 
  */
-#if (__ARMCC_VERSION < 400000)
-extern void __CLREX(void);
-#else  /* (__ARMCC_VERSION >= 400000)  */
 #define __CLREX                           __clrex
-#endif /* __ARMCC_VERSION  */ 
 
 
 /** \brief  Signed Saturate
@@ -260,196 +253,13 @@
 
 
 
-#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
 /* IAR iccarm specific functions */
 
-#include <intrinsics.h>                     /* IAR Intrinsics   */
-
-#pragma diag_suppress=Pe940
-
-/** \brief  No Operation
-
-    No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-#define __NOP                           __no_operation
-
-
-/** \brief  Wait For Interrupt
-
-    Wait For Interrupt is a hint instruction that suspends execution
-    until one of a number of events occurs.
- */
-static __INLINE  void __WFI(void)
-{
-  __ASM ("wfi");
-}
-
-
-/** \brief  Wait For Event
-
-    Wait For Event is a hint instruction that permits the processor to enter
-    a low-power state until one of a number of events occurs.
- */
-static __INLINE  void __WFE(void)
-{
-  __ASM ("wfe");
-}
-
-
-/** \brief  Send Event
-
-    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-static __INLINE  void __SEV(void)
-{
-  __ASM ("sev");
-}
-
-
-/* intrinsic     void __ISB(void)            (see intrinsics.h) */
-/* intrinsic     void __DSB(void)            (see intrinsics.h) */
-/* intrinsic     void __DMB(void)            (see intrinsics.h) */
-/* intrinsic uint32_t __REV(uint32_t value)  (see intrinsics.h) */
-/* intrinsic          __SSAT                 (see intrinsics.h) */
-/* intrinsic          __USAT                 (see intrinsics.h) */
-
-
-/** \brief  Reverse byte order (16 bit)
-
-    This function reverses the byte order in two unsigned short values.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-static uint32_t __REV16(uint32_t value)
-{
-  __ASM("rev16 r0, r0");
-}
-
-
-/* intrinsic uint32_t __REVSH(uint32_t value)  (see intrinsics.h */
-
-
-#if       (__CORTEX_M >= 0x03)
-
-/** \brief  Reverse bit order of value
-
-    This function reverses the bit order of the given value.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-static uint32_t __RBIT(uint32_t value)
-{
-  __ASM("rbit r0, r0");
-}
+#include <cmsis_iar.h>
 
 
-/** \brief  LDR Exclusive (8 bit)
-
-    This function performs a exclusive LDR command for 8 bit value.
-
-    \param [in]    ptr  Pointer to data
-    \return             value of type uint8_t at (*ptr)
- */
-static uint8_t __LDREXB(volatile uint8_t *addr)
-{
-  __ASM("ldrexb r0, [r0]");
-}
-
-
-/** \brief  LDR Exclusive (16 bit)
-
-    This function performs a exclusive LDR command for 16 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint16_t at (*ptr)
- */
-static uint16_t __LDREXH(volatile uint16_t *addr)
-{
-  __ASM("ldrexh r0, [r0]");
-}
-
-
-/** \brief  LDR Exclusive (32 bit)
-
-    This function performs a exclusive LDR command for 32 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint32_t at (*ptr)
- */
-/* intrinsic unsigned long __LDREX(unsigned long *)  (see intrinsics.h) */
-static uint32_t __LDREXW(volatile uint32_t *addr)
-{
-  __ASM("ldrex r0, [r0]");
-}
-
-
-/** \brief  STR Exclusive (8 bit)
-
-    This function performs a exclusive STR command for 8 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-static uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
-{
-  __ASM("strexb r0, r0, [r1]");
-}
-
-
-/** \brief  STR Exclusive (16 bit)
-
-    This function performs a exclusive STR command for 16 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-static uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
-{
-  __ASM("strexh r0, r0, [r1]");
-}
-
-
-/** \brief  STR Exclusive (32 bit)
-
-    This function performs a exclusive STR command for 32 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-/* intrinsic unsigned long __STREX(unsigned long, unsigned long)  (see intrinsics.h )*/
-static uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
-{
-  __ASM("strex r0, r0, [r1]");
-}
-
-
-/** \brief  Remove the exclusive lock
-
-    This function removes the exclusive lock which is created by LDREX.
-
- */
-static __INLINE void __CLREX(void)
-{
-  __ASM ("clrex");
-}
-
-/* intrinsic   unsigned char __CLZ( unsigned long )      (see intrinsics.h) */
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-#pragma diag_default=Pe940
-
-
-
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
 /* GNU gcc specific functions */
 
 /** \brief  No Operation
@@ -655,7 +465,7 @@
 {
    uint32_t result;
   
-   __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+   __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
    return(result);
 }
 
@@ -673,7 +483,7 @@
 {
    uint32_t result;
   
-   __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+   __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
    return(result);
 }
 
@@ -691,7 +501,7 @@
 {
    uint32_t result;
   
-   __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+   __ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
    return(result);
 }
 
@@ -759,12 +569,12 @@
 
 
 
-#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
 /* TASKING carm specific functions */
 
 /*
  * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
  * Including the CMSIS ones.
  */
 
@@ -772,4 +582,4 @@
 
 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
 
-#endif /* __CORE_CMINSTR_H__ */
+#endif /* __CORE_CMINSTR_H */

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Type:	Library
Created:	04 Apr 2016
Imports:	4
Forks:	0
Commits:	122
Dependents:	4
Dependencies:	0
Followers:	1

The code in this repository is Apache licensed.

Revision 33:5364839841bd, committed 2012-01-10

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