Elijah Orr / mbed-renbed

Fork of the official mbed C/C SDK provides the software platform and libraries to build your applications for RenBED.

Dependents:   1-RenBuggyTimed RenBED_RGB RenBED_RGB_PWM RenBED_RGB

Fork of mbed by mbed official

TARGET_ARM_MPS2_M0P/CMSDK_CM0plus.h@102:da0ca467f8b5, 2015-07-08 (annotated)

Committer:
Kojto
Date:
Wed Jul 08 11:22:30 2015 +0100
Revision:
102:da0ca467f8b5
Child:
116:c0f6e94411f5
Release 102 of the mbed library



Changes:

- new platform: MPS2

- K64f - mac address fix

- Freescale Kinetis - Serial NC handling fix

- Asynch constnes fixes

- startup files .s - change extension to .S

- APPNEARME_MICRONFCBOARD rename to MICRONFCBOARD

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 102:da0ca467f8b5 1 /* MPS2 CMSIS Library
Kojto 102:da0ca467f8b5 2 *
Kojto 102:da0ca467f8b5 3 * Copyright (c) 2006-2015 ARM Limited
Kojto 102:da0ca467f8b5 4 * All rights reserved.
Kojto 102:da0ca467f8b5 5 *
Kojto 102:da0ca467f8b5 6 * Redistribution and use in source and binary forms, with or without
Kojto 102:da0ca467f8b5 7 * modification, are permitted provided that the following conditions are met:
Kojto 102:da0ca467f8b5 8 *
Kojto 102:da0ca467f8b5 9 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 102:da0ca467f8b5 10 * this list of conditions and the following disclaimer.
Kojto 102:da0ca467f8b5 11 *
Kojto 102:da0ca467f8b5 12 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 102:da0ca467f8b5 13 * this list of conditions and the following disclaimer in the documentation
Kojto 102:da0ca467f8b5 14 * and/or other materials provided with the distribution.
Kojto 102:da0ca467f8b5 15 *
Kojto 102:da0ca467f8b5 16 * 3. Neither the name of the copyright holder nor the names of its contributors
Kojto 102:da0ca467f8b5 17 * may be used to endorse or promote products derived from this software without
Kojto 102:da0ca467f8b5 18 * specific prior written permission.
Kojto 102:da0ca467f8b5 19 *
Kojto 102:da0ca467f8b5 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 102:da0ca467f8b5 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 102:da0ca467f8b5 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Kojto 102:da0ca467f8b5 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
Kojto 102:da0ca467f8b5 24 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Kojto 102:da0ca467f8b5 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Kojto 102:da0ca467f8b5 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Kojto 102:da0ca467f8b5 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Kojto 102:da0ca467f8b5 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Kojto 102:da0ca467f8b5 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto 102:da0ca467f8b5 30 * POSSIBILITY OF SUCH DAMAGE.
Kojto 102:da0ca467f8b5 31 *******************************************************************************
Kojto 102:da0ca467f8b5 32 * @file CMSDK_CM0plus.h
Kojto 102:da0ca467f8b5 33 * @brief CMSIS Core Peripheral Access Layer Header File for
Kojto 102:da0ca467f8b5 34 * CMSDK_CM0plus Device
Kojto 102:da0ca467f8b5 35 * @version V3.02
Kojto 102:da0ca467f8b5 36 * @date 15. November 2013
Kojto 102:da0ca467f8b5 37 *
Kojto 102:da0ca467f8b5 38 * @note configured for CM7 without FPU
Kojto 102:da0ca467f8b5 39 *
Kojto 102:da0ca467f8b5 40 *******************************************************************************/
Kojto 102:da0ca467f8b5 41
Kojto 102:da0ca467f8b5 42
Kojto 102:da0ca467f8b5 43 #ifndef CMSDK_CM0plus_H
Kojto 102:da0ca467f8b5 44 #define CMSDK_CM0plus_H
Kojto 102:da0ca467f8b5 45
Kojto 102:da0ca467f8b5 46 #ifdef __cplusplus
Kojto 102:da0ca467f8b5 47 extern "C" {
Kojto 102:da0ca467f8b5 48 #endif
Kojto 102:da0ca467f8b5 49
Kojto 102:da0ca467f8b5 50
Kojto 102:da0ca467f8b5 51 /* ------------------------- Interrupt Number Definition ------------------------ */
Kojto 102:da0ca467f8b5 52
Kojto 102:da0ca467f8b5 53 typedef enum IRQn
Kojto 102:da0ca467f8b5 54 {
Kojto 102:da0ca467f8b5 55 /* ------------------- Cortex-M0+ Processor Exceptions Numbers ------------------ */
Kojto 102:da0ca467f8b5 56 NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
Kojto 102:da0ca467f8b5 57 HardFault_IRQn = -13, /* 3 HardFault Interrupt */
Kojto 102:da0ca467f8b5 58
Kojto 102:da0ca467f8b5 59
Kojto 102:da0ca467f8b5 60
Kojto 102:da0ca467f8b5 61 SVCall_IRQn = -5, /* 11 SV Call Interrupt */
Kojto 102:da0ca467f8b5 62
Kojto 102:da0ca467f8b5 63 PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
Kojto 102:da0ca467f8b5 64 SysTick_IRQn = -1, /* 15 System Tick Interrupt */
Kojto 102:da0ca467f8b5 65
Kojto 102:da0ca467f8b5 66 /* ---------------------- CMSDK_CM0plus Specific Interrupt Numbers -------------- */
Kojto 102:da0ca467f8b5 67 UARTRX0_IRQn = 0, /* UART 0 RX Interrupt */
Kojto 102:da0ca467f8b5 68 UARTTX0_IRQn = 1, /* UART 0 TX Interrupt */
Kojto 102:da0ca467f8b5 69 UARTRX1_IRQn = 2, /* UART 1 RX Interrupt */
Kojto 102:da0ca467f8b5 70 UARTTX1_IRQn = 3, /* UART 1 TX Interrupt */
Kojto 102:da0ca467f8b5 71 UARTRX2_IRQn = 4, /* UART 2 RX Interrupt */
Kojto 102:da0ca467f8b5 72 UARTTX2_IRQn = 5, /* UART 2 TX Interrupt */
Kojto 102:da0ca467f8b5 73 PORT0_ALL_IRQn = 6, /* Port 1 combined Interrupt */
Kojto 102:da0ca467f8b5 74 PORT1_ALL_IRQn = 7, /* Port 1 combined Interrupt */
Kojto 102:da0ca467f8b5 75 TIMER0_IRQn = 8, /* TIMER 0 Interrupt */
Kojto 102:da0ca467f8b5 76 TIMER1_IRQn = 9, /* TIMER 1 Interrupt */
Kojto 102:da0ca467f8b5 77 DUALTIMER_IRQn = 10, /* Dual Timer Interrupt */
Kojto 102:da0ca467f8b5 78 SPI_IRQn = 11, /* SPI Interrupt */
Kojto 102:da0ca467f8b5 79 UARTOVF_IRQn = 12, /* UART 0,1,2 Overflow Interrupt */
Kojto 102:da0ca467f8b5 80 ETHERNET_IRQn = 13, /* Ethernet Interrupt */
Kojto 102:da0ca467f8b5 81 I2S_IRQn = 14, /* I2S Interrupt */
Kojto 102:da0ca467f8b5 82 TSC_IRQn = 15, /* Touch Screen Interrupt */
Kojto 102:da0ca467f8b5 83 // DMA_IRQn = 15, /* PL230 DMA Done + Error Interrupt */
Kojto 102:da0ca467f8b5 84 PORT0_0_IRQn = 16, /* All P0 I/O pins used as irq source */
Kojto 102:da0ca467f8b5 85 PORT0_1_IRQn = 17, /* There are 16 pins in total */
Kojto 102:da0ca467f8b5 86 PORT0_2_IRQn = 18,
Kojto 102:da0ca467f8b5 87 PORT0_3_IRQn = 19,
Kojto 102:da0ca467f8b5 88 PORT0_4_IRQn = 20,
Kojto 102:da0ca467f8b5 89 PORT0_5_IRQn = 21,
Kojto 102:da0ca467f8b5 90 PORT0_6_IRQn = 22,
Kojto 102:da0ca467f8b5 91 PORT0_7_IRQn = 23,
Kojto 102:da0ca467f8b5 92 PORT0_8_IRQn = 24,
Kojto 102:da0ca467f8b5 93 PORT0_9_IRQn = 25,
Kojto 102:da0ca467f8b5 94 PORT0_10_IRQn = 26,
Kojto 102:da0ca467f8b5 95 PORT0_11_IRQn = 27,
Kojto 102:da0ca467f8b5 96 PORT0_12_IRQn = 28,
Kojto 102:da0ca467f8b5 97 PORT0_13_IRQn = 29,
Kojto 102:da0ca467f8b5 98 PORT0_14_IRQn = 30,
Kojto 102:da0ca467f8b5 99 PORT0_15_IRQn = 31,
Kojto 102:da0ca467f8b5 100 } IRQn_Type;
Kojto 102:da0ca467f8b5 101
Kojto 102:da0ca467f8b5 102
Kojto 102:da0ca467f8b5 103 /* ================================================================================ */
Kojto 102:da0ca467f8b5 104 /* ================ Processor and Core Peripheral Section ================ */
Kojto 102:da0ca467f8b5 105 /* ================================================================================ */
Kojto 102:da0ca467f8b5 106
Kojto 102:da0ca467f8b5 107 /* -------- Configuration of the Cortex-M0+ Processor and Core Peripherals ------ */
Kojto 102:da0ca467f8b5 108 #define __CM0PLUS_REV 0x0000 /* Core revision r0p0 */
Kojto 102:da0ca467f8b5 109 #define __MPU_PRESENT 1 /* MPU present or not */
Kojto 102:da0ca467f8b5 110 #define __VTOR_PRESENT 1 /* VTOR present or not */
Kojto 102:da0ca467f8b5 111 #define __NVIC_PRIO_BITS 2 /* Number of Bits used for Priority Levels */
Kojto 102:da0ca467f8b5 112 #define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
Kojto 102:da0ca467f8b5 113
Kojto 102:da0ca467f8b5 114 #include <core_cm0plus.h> /* Processor and core peripherals */
Kojto 102:da0ca467f8b5 115 #include "system_CMSDK_CM0plus.h" /* System Header */
Kojto 102:da0ca467f8b5 116
Kojto 102:da0ca467f8b5 117
Kojto 102:da0ca467f8b5 118 /* ================================================================================ */
Kojto 102:da0ca467f8b5 119 /* ================ Device Specific Peripheral Section ================ */
Kojto 102:da0ca467f8b5 120 /* ================================================================================ */
Kojto 102:da0ca467f8b5 121
Kojto 102:da0ca467f8b5 122 /* ------------------- Start of section using anonymous unions ------------------ */
Kojto 102:da0ca467f8b5 123 #if defined ( __CC_ARM )
Kojto 102:da0ca467f8b5 124 #pragma push
Kojto 102:da0ca467f8b5 125 #pragma anon_unions
Kojto 102:da0ca467f8b5 126 #elif defined(__ICCARM__)
Kojto 102:da0ca467f8b5 127 #pragma language=extended
Kojto 102:da0ca467f8b5 128 #elif defined(__GNUC__)
Kojto 102:da0ca467f8b5 129 /* anonymous unions are enabled by default */
Kojto 102:da0ca467f8b5 130 #elif defined(__TMS470__)
Kojto 102:da0ca467f8b5 131 /* anonymous unions are enabled by default */
Kojto 102:da0ca467f8b5 132 #elif defined(__TASKING__)
Kojto 102:da0ca467f8b5 133 #pragma warning 586
Kojto 102:da0ca467f8b5 134 #else
Kojto 102:da0ca467f8b5 135 #warning Not supported compiler type
Kojto 102:da0ca467f8b5 136 #endif
Kojto 102:da0ca467f8b5 137
Kojto 102:da0ca467f8b5 138 /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
Kojto 102:da0ca467f8b5 139 typedef struct
Kojto 102:da0ca467f8b5 140 {
Kojto 102:da0ca467f8b5 141 __IO uint32_t DATA; /* Offset: 0x000 (R/W) Data Register */
Kojto 102:da0ca467f8b5 142 __IO uint32_t STATE; /* Offset: 0x004 (R/W) Status Register */
Kojto 102:da0ca467f8b5 143 __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register */
Kojto 102:da0ca467f8b5 144 union {
Kojto 102:da0ca467f8b5 145 __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */
Kojto 102:da0ca467f8b5 146 __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */
Kojto 102:da0ca467f8b5 147 };
Kojto 102:da0ca467f8b5 148 __IO uint32_t BAUDDIV; /* Offset: 0x010 (R/W) Baudrate Divider Register */
Kojto 102:da0ca467f8b5 149
Kojto 102:da0ca467f8b5 150 } CMSDK_UART_TypeDef;
Kojto 102:da0ca467f8b5 151
Kojto 102:da0ca467f8b5 152 /* CMSDK_UART DATA Register Definitions */
Kojto 102:da0ca467f8b5 153
Kojto 102:da0ca467f8b5 154 #define CMSDK_UART_DATA_Pos 0 /* CMSDK_UART_DATA_Pos: DATA Position */
Kojto 102:da0ca467f8b5 155 #define CMSDK_UART_DATA_Msk (0xFFul << CMSDK_UART_DATA_Pos) /* CMSDK_UART DATA: DATA Mask */
Kojto 102:da0ca467f8b5 156
Kojto 102:da0ca467f8b5 157 #define CMSDK_UART_STATE_RXOR_Pos 3 /* CMSDK_UART STATE: RXOR Position */
Kojto 102:da0ca467f8b5 158 #define CMSDK_UART_STATE_RXOR_Msk (0x1ul << CMSDK_UART_STATE_RXOR_Pos) /* CMSDK_UART STATE: RXOR Mask */
Kojto 102:da0ca467f8b5 159
Kojto 102:da0ca467f8b5 160 #define CMSDK_UART_STATE_TXOR_Pos 2 /* CMSDK_UART STATE: TXOR Position */
Kojto 102:da0ca467f8b5 161 #define CMSDK_UART_STATE_TXOR_Msk (0x1ul << CMSDK_UART_STATE_TXOR_Pos) /* CMSDK_UART STATE: TXOR Mask */
Kojto 102:da0ca467f8b5 162
Kojto 102:da0ca467f8b5 163 #define CMSDK_UART_STATE_RXBF_Pos 1 /* CMSDK_UART STATE: RXBF Position */
Kojto 102:da0ca467f8b5 164 #define CMSDK_UART_STATE_RXBF_Msk (0x1ul << CMSDK_UART_STATE_RXBF_Pos) /* CMSDK_UART STATE: RXBF Mask */
Kojto 102:da0ca467f8b5 165
Kojto 102:da0ca467f8b5 166 #define CMSDK_UART_STATE_TXBF_Pos 0 /* CMSDK_UART STATE: TXBF Position */
Kojto 102:da0ca467f8b5 167 #define CMSDK_UART_STATE_TXBF_Msk (0x1ul << CMSDK_UART_STATE_TXBF_Pos ) /* CMSDK_UART STATE: TXBF Mask */
Kojto 102:da0ca467f8b5 168
Kojto 102:da0ca467f8b5 169 #define CMSDK_UART_CTRL_HSTM_Pos 6 /* CMSDK_UART CTRL: HSTM Position */
Kojto 102:da0ca467f8b5 170 #define CMSDK_UART_CTRL_HSTM_Msk (0x01ul << CMSDK_UART_CTRL_HSTM_Pos) /* CMSDK_UART CTRL: HSTM Mask */
Kojto 102:da0ca467f8b5 171
Kojto 102:da0ca467f8b5 172 #define CMSDK_UART_CTRL_RXORIRQEN_Pos 5 /* CMSDK_UART CTRL: RXORIRQEN Position */
Kojto 102:da0ca467f8b5 173 #define CMSDK_UART_CTRL_RXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXORIRQEN_Pos) /* CMSDK_UART CTRL: RXORIRQEN Mask */
Kojto 102:da0ca467f8b5 174
Kojto 102:da0ca467f8b5 175 #define CMSDK_UART_CTRL_TXORIRQEN_Pos 4 /* CMSDK_UART CTRL: TXORIRQEN Position */
Kojto 102:da0ca467f8b5 176 #define CMSDK_UART_CTRL_TXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQEN_Pos) /* CMSDK_UART CTRL: TXORIRQEN Mask */
Kojto 102:da0ca467f8b5 177
Kojto 102:da0ca467f8b5 178 #define CMSDK_UART_CTRL_RXIRQEN_Pos 3 /* CMSDK_UART CTRL: RXIRQEN Position */
Kojto 102:da0ca467f8b5 179 #define CMSDK_UART_CTRL_RXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQEN_Pos) /* CMSDK_UART CTRL: RXIRQEN Mask */
Kojto 102:da0ca467f8b5 180
Kojto 102:da0ca467f8b5 181 #define CMSDK_UART_CTRL_TXIRQEN_Pos 2 /* CMSDK_UART CTRL: TXIRQEN Position */
Kojto 102:da0ca467f8b5 182 #define CMSDK_UART_CTRL_TXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQEN_Pos) /* CMSDK_UART CTRL: TXIRQEN Mask */
Kojto 102:da0ca467f8b5 183
Kojto 102:da0ca467f8b5 184 #define CMSDK_UART_CTRL_RXEN_Pos 1 /* CMSDK_UART CTRL: RXEN Position */
Kojto 102:da0ca467f8b5 185 #define CMSDK_UART_CTRL_RXEN_Msk (0x01ul << CMSDK_UART_CTRL_RXEN_Pos) /* CMSDK_UART CTRL: RXEN Mask */
Kojto 102:da0ca467f8b5 186
Kojto 102:da0ca467f8b5 187 #define CMSDK_UART_CTRL_TXEN_Pos 0 /* CMSDK_UART CTRL: TXEN Position */
Kojto 102:da0ca467f8b5 188 #define CMSDK_UART_CTRL_TXEN_Msk (0x01ul << CMSDK_UART_CTRL_TXEN_Pos) /* CMSDK_UART CTRL: TXEN Mask */
Kojto 102:da0ca467f8b5 189
Kojto 102:da0ca467f8b5 190 #define CMSDK_UART_INTSTATUS_RXORIRQ_Pos 3 /* CMSDK_UART CTRL: RXORIRQ Position */
Kojto 102:da0ca467f8b5 191 #define CMSDK_UART_CTRL_RXORIRQ_Msk (0x01ul << CMSDK_UART_INTSTATUS_RXORIRQ_Pos) /* CMSDK_UART CTRL: RXORIRQ Mask */
Kojto 102:da0ca467f8b5 192
Kojto 102:da0ca467f8b5 193 #define CMSDK_UART_CTRL_TXORIRQ_Pos 2 /* CMSDK_UART CTRL: TXORIRQ Position */
Kojto 102:da0ca467f8b5 194 #define CMSDK_UART_CTRL_TXORIRQ_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQ_Pos) /* CMSDK_UART CTRL: TXORIRQ Mask */
Kojto 102:da0ca467f8b5 195
Kojto 102:da0ca467f8b5 196 #define CMSDK_UART_CTRL_RXIRQ_Pos 1 /* CMSDK_UART CTRL: RXIRQ Position */
Kojto 102:da0ca467f8b5 197 #define CMSDK_UART_CTRL_RXIRQ_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQ_Pos) /* CMSDK_UART CTRL: RXIRQ Mask */
Kojto 102:da0ca467f8b5 198
Kojto 102:da0ca467f8b5 199 #define CMSDK_UART_CTRL_TXIRQ_Pos 0 /* CMSDK_UART CTRL: TXIRQ Position */
Kojto 102:da0ca467f8b5 200 #define CMSDK_UART_CTRL_TXIRQ_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQ_Pos) /* CMSDK_UART CTRL: TXIRQ Mask */
Kojto 102:da0ca467f8b5 201
Kojto 102:da0ca467f8b5 202 #define CMSDK_UART_BAUDDIV_Pos 0 /* CMSDK_UART BAUDDIV: BAUDDIV Position */
Kojto 102:da0ca467f8b5 203 #define CMSDK_UART_BAUDDIV_Msk (0xFFFFFul << CMSDK_UART_BAUDDIV_Pos) /* CMSDK_UART BAUDDIV: BAUDDIV Mask */
Kojto 102:da0ca467f8b5 204
Kojto 102:da0ca467f8b5 205
Kojto 102:da0ca467f8b5 206 /*----------------------------- Timer (TIMER) -------------------------------*/
Kojto 102:da0ca467f8b5 207 typedef struct
Kojto 102:da0ca467f8b5 208 {
Kojto 102:da0ca467f8b5 209 __IO uint32_t CTRL; /* Offset: 0x000 (R/W) Control Register */
Kojto 102:da0ca467f8b5 210 __IO uint32_t VALUE; /* Offset: 0x004 (R/W) Current Value Register */
Kojto 102:da0ca467f8b5 211 __IO uint32_t RELOAD; /* Offset: 0x008 (R/W) Reload Value Register */
Kojto 102:da0ca467f8b5 212 union {
Kojto 102:da0ca467f8b5 213 __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */
Kojto 102:da0ca467f8b5 214 __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */
Kojto 102:da0ca467f8b5 215 };
Kojto 102:da0ca467f8b5 216
Kojto 102:da0ca467f8b5 217 } CMSDK_TIMER_TypeDef;
Kojto 102:da0ca467f8b5 218
Kojto 102:da0ca467f8b5 219 /* CMSDK_TIMER CTRL Register Definitions */
Kojto 102:da0ca467f8b5 220
Kojto 102:da0ca467f8b5 221 #define CMSDK_TIMER_CTRL_IRQEN_Pos 3 /* CMSDK_TIMER CTRL: IRQEN Position */
Kojto 102:da0ca467f8b5 222 #define CMSDK_TIMER_CTRL_IRQEN_Msk (0x01ul << CMSDK_TIMER_CTRL_IRQEN_Pos) /* CMSDK_TIMER CTRL: IRQEN Mask */
Kojto 102:da0ca467f8b5 223
Kojto 102:da0ca467f8b5 224 #define CMSDK_TIMER_CTRL_SELEXTCLK_Pos 2 /* CMSDK_TIMER CTRL: SELEXTCLK Position */
Kojto 102:da0ca467f8b5 225 #define CMSDK_TIMER_CTRL_SELEXTCLK_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTCLK_Pos) /* CMSDK_TIMER CTRL: SELEXTCLK Mask */
Kojto 102:da0ca467f8b5 226
Kojto 102:da0ca467f8b5 227 #define CMSDK_TIMER_CTRL_SELEXTEN_Pos 1 /* CMSDK_TIMER CTRL: SELEXTEN Position */
Kojto 102:da0ca467f8b5 228 #define CMSDK_TIMER_CTRL_SELEXTEN_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTEN_Pos) /* CMSDK_TIMER CTRL: SELEXTEN Mask */
Kojto 102:da0ca467f8b5 229
Kojto 102:da0ca467f8b5 230 #define CMSDK_TIMER_CTRL_EN_Pos 0 /* CMSDK_TIMER CTRL: EN Position */
Kojto 102:da0ca467f8b5 231 #define CMSDK_TIMER_CTRL_EN_Msk (0x01ul << CMSDK_TIMER_CTRL_EN_Pos) /* CMSDK_TIMER CTRL: EN Mask */
Kojto 102:da0ca467f8b5 232
Kojto 102:da0ca467f8b5 233 #define CMSDK_TIMER_VAL_CURRENT_Pos 0 /* CMSDK_TIMER VALUE: CURRENT Position */
Kojto 102:da0ca467f8b5 234 #define CMSDK_TIMER_VAL_CURRENT_Msk (0xFFFFFFFFul << CMSDK_TIMER_VAL_CURRENT_Pos) /* CMSDK_TIMER VALUE: CURRENT Mask */
Kojto 102:da0ca467f8b5 235
Kojto 102:da0ca467f8b5 236 #define CMSDK_TIMER_RELOAD_VAL_Pos 0 /* CMSDK_TIMER RELOAD: RELOAD Position */
Kojto 102:da0ca467f8b5 237 #define CMSDK_TIMER_RELOAD_VAL_Msk (0xFFFFFFFFul << CMSDK_TIMER_RELOAD_VAL_Pos) /* CMSDK_TIMER RELOAD: RELOAD Mask */
Kojto 102:da0ca467f8b5 238
Kojto 102:da0ca467f8b5 239 #define CMSDK_TIMER_INTSTATUS_Pos 0 /* CMSDK_TIMER INTSTATUS: INTSTATUSPosition */
Kojto 102:da0ca467f8b5 240 #define CMSDK_TIMER_INTSTATUS_Msk (0x01ul << CMSDK_TIMER_INTSTATUS_Pos) /* CMSDK_TIMER INTSTATUS: INTSTATUSMask */
Kojto 102:da0ca467f8b5 241
Kojto 102:da0ca467f8b5 242 #define CMSDK_TIMER_INTCLEAR_Pos 0 /* CMSDK_TIMER INTCLEAR: INTCLEAR Position */
Kojto 102:da0ca467f8b5 243 #define CMSDK_TIMER_INTCLEAR_Msk (0x01ul << CMSDK_TIMER_INTCLEAR_Pos) /* CMSDK_TIMER INTCLEAR: INTCLEAR Mask */
Kojto 102:da0ca467f8b5 244
Kojto 102:da0ca467f8b5 245
Kojto 102:da0ca467f8b5 246 /*------------- Timer (TIM) --------------------------------------------------*/
Kojto 102:da0ca467f8b5 247 typedef struct
Kojto 102:da0ca467f8b5 248 {
Kojto 102:da0ca467f8b5 249 __IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */
Kojto 102:da0ca467f8b5 250 __I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
Kojto 102:da0ca467f8b5 251 __IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */
Kojto 102:da0ca467f8b5 252 __O uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */
Kojto 102:da0ca467f8b5 253 __I uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */
Kojto 102:da0ca467f8b5 254 __I uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */
Kojto 102:da0ca467f8b5 255 __IO uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */
Kojto 102:da0ca467f8b5 256 uint32_t RESERVED0;
Kojto 102:da0ca467f8b5 257 __IO uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */
Kojto 102:da0ca467f8b5 258 __I uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */
Kojto 102:da0ca467f8b5 259 __IO uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */
Kojto 102:da0ca467f8b5 260 __O uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */
Kojto 102:da0ca467f8b5 261 __I uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */
Kojto 102:da0ca467f8b5 262 __I uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */
Kojto 102:da0ca467f8b5 263 __IO uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */
Kojto 102:da0ca467f8b5 264 uint32_t RESERVED1[945];
Kojto 102:da0ca467f8b5 265 __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Integration Test Control Register */
Kojto 102:da0ca467f8b5 266 __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Integration Test Output Set Register */
Kojto 102:da0ca467f8b5 267 } CMSDK_DUALTIMER_BOTH_TypeDef;
Kojto 102:da0ca467f8b5 268
Kojto 102:da0ca467f8b5 269 #define CMSDK_DUALTIMER1_LOAD_Pos 0 /* CMSDK_DUALTIMER1 LOAD: LOAD Position */
Kojto 102:da0ca467f8b5 270 #define CMSDK_DUALTIMER1_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_LOAD_Pos) /* CMSDK_DUALTIMER1 LOAD: LOAD Mask */
Kojto 102:da0ca467f8b5 271
Kojto 102:da0ca467f8b5 272 #define CMSDK_DUALTIMER1_VALUE_Pos 0 /* CMSDK_DUALTIMER1 VALUE: VALUE Position */
Kojto 102:da0ca467f8b5 273 #define CMSDK_DUALTIMER1_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_VALUE_Pos) /* CMSDK_DUALTIMER1 VALUE: VALUE Mask */
Kojto 102:da0ca467f8b5 274
Kojto 102:da0ca467f8b5 275 #define CMSDK_DUALTIMER1_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Position */
Kojto 102:da0ca467f8b5 276 #define CMSDK_DUALTIMER1_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_EN_Pos) /* CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Mask */
Kojto 102:da0ca467f8b5 277
Kojto 102:da0ca467f8b5 278 #define CMSDK_DUALTIMER1_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Position */
Kojto 102:da0ca467f8b5 279 #define CMSDK_DUALTIMER1_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_MODE_Pos) /* CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Mask */
Kojto 102:da0ca467f8b5 280
Kojto 102:da0ca467f8b5 281 #define CMSDK_DUALTIMER1_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Position */
Kojto 102:da0ca467f8b5 282 #define CMSDK_DUALTIMER1_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Mask */
Kojto 102:da0ca467f8b5 283
Kojto 102:da0ca467f8b5 284 #define CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Position */
Kojto 102:da0ca467f8b5 285 #define CMSDK_DUALTIMER1_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Mask */
Kojto 102:da0ca467f8b5 286
Kojto 102:da0ca467f8b5 287 #define CMSDK_DUALTIMER1_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Position */
Kojto 102:da0ca467f8b5 288 #define CMSDK_DUALTIMER1_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Mask */
Kojto 102:da0ca467f8b5 289
Kojto 102:da0ca467f8b5 290 #define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Position */
Kojto 102:da0ca467f8b5 291 #define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Mask */
Kojto 102:da0ca467f8b5 292
Kojto 102:da0ca467f8b5 293 #define CMSDK_DUALTIMER1_INTCLR_Pos 0 /* CMSDK_DUALTIMER1 INTCLR: INT Clear Position */
Kojto 102:da0ca467f8b5 294 #define CMSDK_DUALTIMER1_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER1_INTCLR_Pos) /* CMSDK_DUALTIMER1 INTCLR: INT Clear Mask */
Kojto 102:da0ca467f8b5 295
Kojto 102:da0ca467f8b5 296 #define CMSDK_DUALTIMER1_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Position */
Kojto 102:da0ca467f8b5 297 #define CMSDK_DUALTIMER1_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Mask */
Kojto 102:da0ca467f8b5 298
Kojto 102:da0ca467f8b5 299 #define CMSDK_DUALTIMER1_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Position */
Kojto 102:da0ca467f8b5 300 #define CMSDK_DUALTIMER1_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Mask */
Kojto 102:da0ca467f8b5 301
Kojto 102:da0ca467f8b5 302 #define CMSDK_DUALTIMER1_BGLOAD_Pos 0 /* CMSDK_DUALTIMER1 BGLOAD: Background Load Position */
Kojto 102:da0ca467f8b5 303 #define CMSDK_DUALTIMER1_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_BGLOAD_Pos) /* CMSDK_DUALTIMER1 BGLOAD: Background Load Mask */
Kojto 102:da0ca467f8b5 304
Kojto 102:da0ca467f8b5 305 #define CMSDK_DUALTIMER2_LOAD_Pos 0 /* CMSDK_DUALTIMER2 LOAD: LOAD Position */
Kojto 102:da0ca467f8b5 306 #define CMSDK_DUALTIMER2_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_LOAD_Pos) /* CMSDK_DUALTIMER2 LOAD: LOAD Mask */
Kojto 102:da0ca467f8b5 307
Kojto 102:da0ca467f8b5 308 #define CMSDK_DUALTIMER2_VALUE_Pos 0 /* CMSDK_DUALTIMER2 VALUE: VALUE Position */
Kojto 102:da0ca467f8b5 309 #define CMSDK_DUALTIMER2_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_VALUE_Pos) /* CMSDK_DUALTIMER2 VALUE: VALUE Mask */
Kojto 102:da0ca467f8b5 310
Kojto 102:da0ca467f8b5 311 #define CMSDK_DUALTIMER2_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Position */
Kojto 102:da0ca467f8b5 312 #define CMSDK_DUALTIMER2_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_EN_Pos) /* CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Mask */
Kojto 102:da0ca467f8b5 313
Kojto 102:da0ca467f8b5 314 #define CMSDK_DUALTIMER2_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Position */
Kojto 102:da0ca467f8b5 315 #define CMSDK_DUALTIMER2_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_MODE_Pos) /* CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Mask */
Kojto 102:da0ca467f8b5 316
Kojto 102:da0ca467f8b5 317 #define CMSDK_DUALTIMER2_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Position */
Kojto 102:da0ca467f8b5 318 #define CMSDK_DUALTIMER2_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Mask */
Kojto 102:da0ca467f8b5 319
Kojto 102:da0ca467f8b5 320 #define CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Position */
Kojto 102:da0ca467f8b5 321 #define CMSDK_DUALTIMER2_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Mask */
Kojto 102:da0ca467f8b5 322
Kojto 102:da0ca467f8b5 323 #define CMSDK_DUALTIMER2_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Position */
Kojto 102:da0ca467f8b5 324 #define CMSDK_DUALTIMER2_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Mask */
Kojto 102:da0ca467f8b5 325
Kojto 102:da0ca467f8b5 326 #define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Position */
Kojto 102:da0ca467f8b5 327 #define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Mask */
Kojto 102:da0ca467f8b5 328
Kojto 102:da0ca467f8b5 329 #define CMSDK_DUALTIMER2_INTCLR_Pos 0 /* CMSDK_DUALTIMER2 INTCLR: INT Clear Position */
Kojto 102:da0ca467f8b5 330 #define CMSDK_DUALTIMER2_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER2_INTCLR_Pos) /* CMSDK_DUALTIMER2 INTCLR: INT Clear Mask */
Kojto 102:da0ca467f8b5 331
Kojto 102:da0ca467f8b5 332 #define CMSDK_DUALTIMER2_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Position */
Kojto 102:da0ca467f8b5 333 #define CMSDK_DUALTIMER2_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Mask */
Kojto 102:da0ca467f8b5 334
Kojto 102:da0ca467f8b5 335 #define CMSDK_DUALTIMER2_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Position */
Kojto 102:da0ca467f8b5 336 #define CMSDK_DUALTIMER2_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Mask */
Kojto 102:da0ca467f8b5 337
Kojto 102:da0ca467f8b5 338 #define CMSDK_DUALTIMER2_BGLOAD_Pos 0 /* CMSDK_DUALTIMER2 BGLOAD: Background Load Position */
Kojto 102:da0ca467f8b5 339 #define CMSDK_DUALTIMER2_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_BGLOAD_Pos) /* CMSDK_DUALTIMER2 BGLOAD: Background Load Mask */
Kojto 102:da0ca467f8b5 340
Kojto 102:da0ca467f8b5 341
Kojto 102:da0ca467f8b5 342 typedef struct
Kojto 102:da0ca467f8b5 343 {
Kojto 102:da0ca467f8b5 344 __IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */
Kojto 102:da0ca467f8b5 345 __I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */
Kojto 102:da0ca467f8b5 346 __IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */
Kojto 102:da0ca467f8b5 347 __O uint32_t TimerIntClr; /* Offset: 0x000 (R/W) Timer Interrupt Clear */
Kojto 102:da0ca467f8b5 348 __I uint32_t TimerRIS; /* Offset: 0x000 (R/W) Timer Raw Interrupt Status */
Kojto 102:da0ca467f8b5 349 __I uint32_t TimerMIS; /* Offset: 0x000 (R/W) Timer Masked Interrupt Status */
Kojto 102:da0ca467f8b5 350 __IO uint32_t TimerBGLoad; /* Offset: 0x000 (R/W) Background Load Register */
Kojto 102:da0ca467f8b5 351 } CMSDK_DUALTIMER_SINGLE_TypeDef;
Kojto 102:da0ca467f8b5 352
Kojto 102:da0ca467f8b5 353 #define CMSDK_DUALTIMER_LOAD_Pos 0 /* CMSDK_DUALTIMER LOAD: LOAD Position */
Kojto 102:da0ca467f8b5 354 #define CMSDK_DUALTIMER_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_LOAD_Pos) /* CMSDK_DUALTIMER LOAD: LOAD Mask */
Kojto 102:da0ca467f8b5 355
Kojto 102:da0ca467f8b5 356 #define CMSDK_DUALTIMER_VALUE_Pos 0 /* CMSDK_DUALTIMER VALUE: VALUE Position */
Kojto 102:da0ca467f8b5 357 #define CMSDK_DUALTIMER_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_VALUE_Pos) /* CMSDK_DUALTIMER VALUE: VALUE Mask */
Kojto 102:da0ca467f8b5 358
Kojto 102:da0ca467f8b5 359 #define CMSDK_DUALTIMER_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Position */
Kojto 102:da0ca467f8b5 360 #define CMSDK_DUALTIMER_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_EN_Pos) /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Mask */
Kojto 102:da0ca467f8b5 361
Kojto 102:da0ca467f8b5 362 #define CMSDK_DUALTIMER_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Position */
Kojto 102:da0ca467f8b5 363 #define CMSDK_DUALTIMER_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_MODE_Pos) /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Mask */
Kojto 102:da0ca467f8b5 364
Kojto 102:da0ca467f8b5 365 #define CMSDK_DUALTIMER_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Position */
Kojto 102:da0ca467f8b5 366 #define CMSDK_DUALTIMER_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Mask */
Kojto 102:da0ca467f8b5 367
Kojto 102:da0ca467f8b5 368 #define CMSDK_DUALTIMER_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Position */
Kojto 102:da0ca467f8b5 369 #define CMSDK_DUALTIMER_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Mask */
Kojto 102:da0ca467f8b5 370
Kojto 102:da0ca467f8b5 371 #define CMSDK_DUALTIMER_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Position */
Kojto 102:da0ca467f8b5 372 #define CMSDK_DUALTIMER_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Mask */
Kojto 102:da0ca467f8b5 373
Kojto 102:da0ca467f8b5 374 #define CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Position */
Kojto 102:da0ca467f8b5 375 #define CMSDK_DUALTIMER_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Mask */
Kojto 102:da0ca467f8b5 376
Kojto 102:da0ca467f8b5 377 #define CMSDK_DUALTIMER_INTCLR_Pos 0 /* CMSDK_DUALTIMER INTCLR: INT Clear Position */
Kojto 102:da0ca467f8b5 378 #define CMSDK_DUALTIMER_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER_INTCLR_Pos) /* CMSDK_DUALTIMER INTCLR: INT Clear Mask */
Kojto 102:da0ca467f8b5 379
Kojto 102:da0ca467f8b5 380 #define CMSDK_DUALTIMER_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Position */
Kojto 102:da0ca467f8b5 381 #define CMSDK_DUALTIMER_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Mask */
Kojto 102:da0ca467f8b5 382
Kojto 102:da0ca467f8b5 383 #define CMSDK_DUALTIMER_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Position */
Kojto 102:da0ca467f8b5 384 #define CMSDK_DUALTIMER_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Mask */
Kojto 102:da0ca467f8b5 385
Kojto 102:da0ca467f8b5 386 #define CMSDK_DUALTIMER_BGLOAD_Pos 0 /* CMSDK_DUALTIMER BGLOAD: Background Load Position */
Kojto 102:da0ca467f8b5 387 #define CMSDK_DUALTIMER_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_BGLOAD_Pos) /* CMSDK_DUALTIMER BGLOAD: Background Load Mask */
Kojto 102:da0ca467f8b5 388
Kojto 102:da0ca467f8b5 389
Kojto 102:da0ca467f8b5 390 /*-------------------- General Purpose Input Output (GPIO) -------------------*/
Kojto 102:da0ca467f8b5 391 typedef struct
Kojto 102:da0ca467f8b5 392 {
Kojto 102:da0ca467f8b5 393 __IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */
Kojto 102:da0ca467f8b5 394 __IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */
Kojto 102:da0ca467f8b5 395 uint32_t RESERVED0[2];
Kojto 102:da0ca467f8b5 396 __IO uint32_t OUTENABLESET; /* Offset: 0x010 (R/W) Output Enable Set Register */
Kojto 102:da0ca467f8b5 397 __IO uint32_t OUTENABLECLR; /* Offset: 0x014 (R/W) Output Enable Clear Register */
Kojto 102:da0ca467f8b5 398 __IO uint32_t ALTFUNCSET; /* Offset: 0x018 (R/W) Alternate Function Set Register */
Kojto 102:da0ca467f8b5 399 __IO uint32_t ALTFUNCCLR; /* Offset: 0x01C (R/W) Alternate Function Clear Register */
Kojto 102:da0ca467f8b5 400 __IO uint32_t INTENSET; /* Offset: 0x020 (R/W) Interrupt Enable Set Register */
Kojto 102:da0ca467f8b5 401 __IO uint32_t INTENCLR; /* Offset: 0x024 (R/W) Interrupt Enable Clear Register */
Kojto 102:da0ca467f8b5 402 __IO uint32_t INTTYPESET; /* Offset: 0x028 (R/W) Interrupt Type Set Register */
Kojto 102:da0ca467f8b5 403 __IO uint32_t INTTYPECLR; /* Offset: 0x02C (R/W) Interrupt Type Clear Register */
Kojto 102:da0ca467f8b5 404 __IO uint32_t INTPOLSET; /* Offset: 0x030 (R/W) Interrupt Polarity Set Register */
Kojto 102:da0ca467f8b5 405 __IO uint32_t INTPOLCLR; /* Offset: 0x034 (R/W) Interrupt Polarity Clear Register */
Kojto 102:da0ca467f8b5 406 union {
Kojto 102:da0ca467f8b5 407 __I uint32_t INTSTATUS; /* Offset: 0x038 (R/ ) Interrupt Status Register */
Kojto 102:da0ca467f8b5 408 __O uint32_t INTCLEAR; /* Offset: 0x038 ( /W) Interrupt Clear Register */
Kojto 102:da0ca467f8b5 409 };
Kojto 102:da0ca467f8b5 410 uint32_t RESERVED1[241];
Kojto 102:da0ca467f8b5 411 __IO uint32_t LB_MASKED[256]; /* Offset: 0x400 - 0x7FC Lower byte Masked Access Register (R/W) */
Kojto 102:da0ca467f8b5 412 __IO uint32_t UB_MASKED[256]; /* Offset: 0x800 - 0xBFC Upper byte Masked Access Register (R/W) */
Kojto 102:da0ca467f8b5 413 } CMSDK_GPIO_TypeDef;
Kojto 102:da0ca467f8b5 414
Kojto 102:da0ca467f8b5 415 #define CMSDK_GPIO_DATA_Pos 0 /* CMSDK_GPIO DATA: DATA Position */
Kojto 102:da0ca467f8b5 416 #define CMSDK_GPIO_DATA_Msk (0xFFFFul << CMSDK_GPIO_DATA_Pos) /* CMSDK_GPIO DATA: DATA Mask */
Kojto 102:da0ca467f8b5 417
Kojto 102:da0ca467f8b5 418 #define CMSDK_GPIO_DATAOUT_Pos 0 /* CMSDK_GPIO DATAOUT: DATAOUT Position */
Kojto 102:da0ca467f8b5 419 #define CMSDK_GPIO_DATAOUT_Msk (0xFFFFul << CMSDK_GPIO_DATAOUT_Pos) /* CMSDK_GPIO DATAOUT: DATAOUT Mask */
Kojto 102:da0ca467f8b5 420
Kojto 102:da0ca467f8b5 421 #define CMSDK_GPIO_OUTENSET_Pos 0 /* CMSDK_GPIO OUTEN: OUTEN Position */
Kojto 102:da0ca467f8b5 422 #define CMSDK_GPIO_OUTENSET_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /* CMSDK_GPIO OUTEN: OUTEN Mask */
Kojto 102:da0ca467f8b5 423
Kojto 102:da0ca467f8b5 424 #define CMSDK_GPIO_OUTENCLR_Pos 0 /* CMSDK_GPIO OUTEN: OUTEN Position */
Kojto 102:da0ca467f8b5 425 #define CMSDK_GPIO_OUTENCLR_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /* CMSDK_GPIO OUTEN: OUTEN Mask */
Kojto 102:da0ca467f8b5 426
Kojto 102:da0ca467f8b5 427 #define CMSDK_GPIO_ALTFUNCSET_Pos 0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */
Kojto 102:da0ca467f8b5 428 #define CMSDK_GPIO_ALTFUNCSET_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */
Kojto 102:da0ca467f8b5 429
Kojto 102:da0ca467f8b5 430 #define CMSDK_GPIO_ALTFUNCCLR_Pos 0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */
Kojto 102:da0ca467f8b5 431 #define CMSDK_GPIO_ALTFUNCCLR_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */
Kojto 102:da0ca467f8b5 432
Kojto 102:da0ca467f8b5 433 #define CMSDK_GPIO_INTENSET_Pos 0 /* CMSDK_GPIO INTEN: INTEN Position */
Kojto 102:da0ca467f8b5 434 #define CMSDK_GPIO_INTENSET_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /* CMSDK_GPIO INTEN: INTEN Mask */
Kojto 102:da0ca467f8b5 435
Kojto 102:da0ca467f8b5 436 #define CMSDK_GPIO_INTENCLR_Pos 0 /* CMSDK_GPIO INTEN: INTEN Position */
Kojto 102:da0ca467f8b5 437 #define CMSDK_GPIO_INTENCLR_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /* CMSDK_GPIO INTEN: INTEN Mask */
Kojto 102:da0ca467f8b5 438
Kojto 102:da0ca467f8b5 439 #define CMSDK_GPIO_INTTYPESET_Pos 0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */
Kojto 102:da0ca467f8b5 440 #define CMSDK_GPIO_INTTYPESET_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */
Kojto 102:da0ca467f8b5 441
Kojto 102:da0ca467f8b5 442 #define CMSDK_GPIO_INTTYPECLR_Pos 0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */
Kojto 102:da0ca467f8b5 443 #define CMSDK_GPIO_INTTYPECLR_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */
Kojto 102:da0ca467f8b5 444
Kojto 102:da0ca467f8b5 445 #define CMSDK_GPIO_INTPOLSET_Pos 0 /* CMSDK_GPIO INTPOL: INTPOL Position */
Kojto 102:da0ca467f8b5 446 #define CMSDK_GPIO_INTPOLSET_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /* CMSDK_GPIO INTPOL: INTPOL Mask */
Kojto 102:da0ca467f8b5 447
Kojto 102:da0ca467f8b5 448 #define CMSDK_GPIO_INTPOLCLR_Pos 0 /* CMSDK_GPIO INTPOL: INTPOL Position */
Kojto 102:da0ca467f8b5 449 #define CMSDK_GPIO_INTPOLCLR_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /* CMSDK_GPIO INTPOL: INTPOL Mask */
Kojto 102:da0ca467f8b5 450
Kojto 102:da0ca467f8b5 451 #define CMSDK_GPIO_INTSTATUS_Pos 0 /* CMSDK_GPIO INTSTATUS: INTSTATUS Position */
Kojto 102:da0ca467f8b5 452 #define CMSDK_GPIO_INTSTATUS_Msk (0xFFul << CMSDK_GPIO_INTSTATUS_Pos) /* CMSDK_GPIO INTSTATUS: INTSTATUS Mask */
Kojto 102:da0ca467f8b5 453
Kojto 102:da0ca467f8b5 454 #define CMSDK_GPIO_INTCLEAR_Pos 0 /* CMSDK_GPIO INTCLEAR: INTCLEAR Position */
Kojto 102:da0ca467f8b5 455 #define CMSDK_GPIO_INTCLEAR_Msk (0xFFul << CMSDK_GPIO_INTCLEAR_Pos) /* CMSDK_GPIO INTCLEAR: INTCLEAR Mask */
Kojto 102:da0ca467f8b5 456
Kojto 102:da0ca467f8b5 457 #define CMSDK_GPIO_MASKLOWBYTE_Pos 0 /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Position */
Kojto 102:da0ca467f8b5 458 #define CMSDK_GPIO_MASKLOWBYTE_Msk (0x00FFul << CMSDK_GPIO_MASKLOWBYTE_Pos) /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Mask */
Kojto 102:da0ca467f8b5 459
Kojto 102:da0ca467f8b5 460 #define CMSDK_GPIO_MASKHIGHBYTE_Pos 0 /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Position */
Kojto 102:da0ca467f8b5 461 #define CMSDK_GPIO_MASKHIGHBYTE_Msk (0xFF00ul << CMSDK_GPIO_MASKHIGHBYTE_Pos) /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Mask */
Kojto 102:da0ca467f8b5 462
Kojto 102:da0ca467f8b5 463
Kojto 102:da0ca467f8b5 464 /*------------- System Control (SYSCON) --------------------------------------*/
Kojto 102:da0ca467f8b5 465 typedef struct
Kojto 102:da0ca467f8b5 466 {
Kojto 102:da0ca467f8b5 467 __IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */
Kojto 102:da0ca467f8b5 468 __IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */
Kojto 102:da0ca467f8b5 469 __IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */
Kojto 102:da0ca467f8b5 470 __IO uint32_t EMICTRL; /* Offset: 0x00C (R/W) EMI Control Register */
Kojto 102:da0ca467f8b5 471 __IO uint32_t RSTINFO; /* Offset: 0x010 (R/W) Reset Information Register */
Kojto 102:da0ca467f8b5 472 } CMSDK_SYSCON_TypeDef;
Kojto 102:da0ca467f8b5 473
Kojto 102:da0ca467f8b5 474 #define CMSDK_SYSCON_REMAP_Pos 0
Kojto 102:da0ca467f8b5 475 #define CMSDK_SYSCON_REMAP_Msk (0x01ul << CMSDK_SYSCON_REMAP_Pos) /* CMSDK_SYSCON MEME_CTRL: REMAP Mask */
Kojto 102:da0ca467f8b5 476
Kojto 102:da0ca467f8b5 477 #define CMSDK_SYSCON_PMUCTRL_EN_Pos 0
Kojto 102:da0ca467f8b5 478 #define CMSDK_SYSCON_PMUCTRL_EN_Msk (0x01ul << CMSDK_SYSCON_PMUCTRL_EN_Pos) /* CMSDK_SYSCON PMUCTRL: PMUCTRL ENABLE Mask */
Kojto 102:da0ca467f8b5 479
Kojto 102:da0ca467f8b5 480 #define CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos 0
Kojto 102:da0ca467f8b5 481 #define CMSDK_SYSCON_LOCKUPRST_RESETOP_Msk (0x01ul << CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos) /* CMSDK_SYSCON SYS_CTRL: LOCKUP RESET ENABLE Mask */
Kojto 102:da0ca467f8b5 482
Kojto 102:da0ca467f8b5 483 #define CMSDK_SYSCON_EMICTRL_SIZE_Pos 24
Kojto 102:da0ca467f8b5 484 #define CMSDK_SYSCON_EMICTRL_SIZE_Msk (0x00001ul << CMSDK_SYSCON_EMICTRL_SIZE_Pos) /* CMSDK_SYSCON EMICTRL: SIZE Mask */
Kojto 102:da0ca467f8b5 485
Kojto 102:da0ca467f8b5 486 #define CMSDK_SYSCON_EMICTRL_TACYC_Pos 16
Kojto 102:da0ca467f8b5 487 #define CMSDK_SYSCON_EMICTRL_TACYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_TACYC_Pos) /* CMSDK_SYSCON EMICTRL: TURNAROUNDCYCLE Mask */
Kojto 102:da0ca467f8b5 488
Kojto 102:da0ca467f8b5 489 #define CMSDK_SYSCON_EMICTRL_WCYC_Pos 8
Kojto 102:da0ca467f8b5 490 #define CMSDK_SYSCON_EMICTRL_WCYC_Msk (0x00003ul << CMSDK_SYSCON_EMICTRL_WCYC_Pos) /* CMSDK_SYSCON EMICTRL: WRITECYCLE Mask */
Kojto 102:da0ca467f8b5 491
Kojto 102:da0ca467f8b5 492 #define CMSDK_SYSCON_EMICTRL_RCYC_Pos 0
Kojto 102:da0ca467f8b5 493 #define CMSDK_SYSCON_EMICTRL_RCYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_RCYC_Pos) /* CMSDK_SYSCON EMICTRL: READCYCLE Mask */
Kojto 102:da0ca467f8b5 494
Kojto 102:da0ca467f8b5 495 #define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos 0
Kojto 102:da0ca467f8b5 496 #define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos) /* CMSDK_SYSCON RSTINFO: SYSRESETREQ Mask */
Kojto 102:da0ca467f8b5 497
Kojto 102:da0ca467f8b5 498 #define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos 1
Kojto 102:da0ca467f8b5 499 #define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos) /* CMSDK_SYSCON RSTINFO: WDOGRESETREQ Mask */
Kojto 102:da0ca467f8b5 500
Kojto 102:da0ca467f8b5 501 #define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos 2
Kojto 102:da0ca467f8b5 502 #define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos) /* CMSDK_SYSCON RSTINFO: LOCKUPRESET Mask */
Kojto 102:da0ca467f8b5 503
Kojto 102:da0ca467f8b5 504
Kojto 102:da0ca467f8b5 505 /*------------- PL230 uDMA (PL230) --------------------------------------*/
Kojto 102:da0ca467f8b5 506 typedef struct
Kojto 102:da0ca467f8b5 507 {
Kojto 102:da0ca467f8b5 508 __I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */
Kojto 102:da0ca467f8b5 509 __O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */
Kojto 102:da0ca467f8b5 510 __IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */
Kojto 102:da0ca467f8b5 511 __I uint32_t ALT_CTRL_BASE_PTR; /* Offset: 0x00C (R/ ) Channel Alternate Control Data Base Pointer Register */
Kojto 102:da0ca467f8b5 512 __I uint32_t DMA_WAITONREQ_STATUS; /* Offset: 0x010 (R/ ) Channel Wait On Request Status Register */
Kojto 102:da0ca467f8b5 513 __O uint32_t CHNL_SW_REQUEST; /* Offset: 0x014 ( /W) Channel Software Request Register */
Kojto 102:da0ca467f8b5 514 __IO uint32_t CHNL_USEBURST_SET; /* Offset: 0x018 (R/W) Channel UseBurst Set Register */
Kojto 102:da0ca467f8b5 515 __O uint32_t CHNL_USEBURST_CLR; /* Offset: 0x01C ( /W) Channel UseBurst Clear Register */
Kojto 102:da0ca467f8b5 516 __IO uint32_t CHNL_REQ_MASK_SET; /* Offset: 0x020 (R/W) Channel Request Mask Set Register */
Kojto 102:da0ca467f8b5 517 __O uint32_t CHNL_REQ_MASK_CLR; /* Offset: 0x024 ( /W) Channel Request Mask Clear Register */
Kojto 102:da0ca467f8b5 518 __IO uint32_t CHNL_ENABLE_SET; /* Offset: 0x028 (R/W) Channel Enable Set Register */
Kojto 102:da0ca467f8b5 519 __O uint32_t CHNL_ENABLE_CLR; /* Offset: 0x02C ( /W) Channel Enable Clear Register */
Kojto 102:da0ca467f8b5 520 __IO uint32_t CHNL_PRI_ALT_SET; /* Offset: 0x030 (R/W) Channel Primary-Alterante Set Register */
Kojto 102:da0ca467f8b5 521 __O uint32_t CHNL_PRI_ALT_CLR; /* Offset: 0x034 ( /W) Channel Primary-Alterante Clear Register */
Kojto 102:da0ca467f8b5 522 __IO uint32_t CHNL_PRIORITY_SET; /* Offset: 0x038 (R/W) Channel Priority Set Register */
Kojto 102:da0ca467f8b5 523 __O uint32_t CHNL_PRIORITY_CLR; /* Offset: 0x03C ( /W) Channel Priority Clear Register */
Kojto 102:da0ca467f8b5 524 uint32_t RESERVED0[3];
Kojto 102:da0ca467f8b5 525 __IO uint32_t ERR_CLR; /* Offset: 0x04C Bus Error Clear Register (R/W) */
Kojto 102:da0ca467f8b5 526
Kojto 102:da0ca467f8b5 527 } CMSDK_PL230_TypeDef;
Kojto 102:da0ca467f8b5 528
Kojto 102:da0ca467f8b5 529 #define PL230_DMA_CHNL_BITS 0
Kojto 102:da0ca467f8b5 530
Kojto 102:da0ca467f8b5 531 #define CMSDK_PL230_DMA_STATUS_MSTREN_Pos 0 /* CMSDK_PL230 DMA STATUS: MSTREN Position */
Kojto 102:da0ca467f8b5 532 #define CMSDK_PL230_DMA_STATUS_MSTREN_Msk (0x00000001ul << CMSDK_PL230_DMA_STATUS_MSTREN_Pos) /* CMSDK_PL230 DMA STATUS: MSTREN Mask */
Kojto 102:da0ca467f8b5 533
Kojto 102:da0ca467f8b5 534 #define CMSDK_PL230_DMA_STATUS_STATE_Pos 0 /* CMSDK_PL230 DMA STATUS: STATE Position */
Kojto 102:da0ca467f8b5 535 #define CMSDK_PL230_DMA_STATUS_STATE_Msk (0x0000000Ful << CMSDK_PL230_DMA_STATUS_STATE_Pos) /* CMSDK_PL230 DMA STATUS: STATE Mask */
Kojto 102:da0ca467f8b5 536
Kojto 102:da0ca467f8b5 537 #define CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Pos 0 /* CMSDK_PL230 DMA STATUS: CHNLS_MINUS1 Position */
Kojto 102:da0ca467f8b5 538 #define CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Msk (0x0000001Ful << CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Pos) /* CMSDK_PL230 DMA STATUS: CHNLS_MINUS1 Mask */
Kojto 102:da0ca467f8b5 539
Kojto 102:da0ca467f8b5 540 #define CMSDK_PL230_DMA_STATUS_TEST_STATUS_Pos 0 /* CMSDK_PL230 DMA STATUS: TEST_STATUS Position */
Kojto 102:da0ca467f8b5 541 #define CMSDK_PL230_DMA_STATUS_TEST_STATUS_Msk (0x00000001ul << CMSDK_PL230_DMA_STATUS_TEST_STATUS_Pos) /* CMSDK_PL230 DMA STATUS: TEST_STATUS Mask */
Kojto 102:da0ca467f8b5 542
Kojto 102:da0ca467f8b5 543 #define CMSDK_PL230_DMA_CFG_MSTREN_Pos 0 /* CMSDK_PL230 DMA CFG: MSTREN Position */
Kojto 102:da0ca467f8b5 544 #define CMSDK_PL230_DMA_CFG_MSTREN_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_MSTREN_Pos) /* CMSDK_PL230 DMA CFG: MSTREN Mask */
Kojto 102:da0ca467f8b5 545
Kojto 102:da0ca467f8b5 546 #define CMSDK_PL230_DMA_CFG_CPCCACHE_Pos 2 /* CMSDK_PL230 DMA CFG: CPCCACHE Position */
Kojto 102:da0ca467f8b5 547 #define CMSDK_PL230_DMA_CFG_CPCCACHE_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCCACHE_Pos) /* CMSDK_PL230 DMA CFG: CPCCACHE Mask */
Kojto 102:da0ca467f8b5 548
Kojto 102:da0ca467f8b5 549 #define CMSDK_PL230_DMA_CFG_CPCBUF_Pos 1 /* CMSDK_PL230 DMA CFG: CPCBUF Position */
Kojto 102:da0ca467f8b5 550 #define CMSDK_PL230_DMA_CFG_CPCBUF_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCBUF_Pos) /* CMSDK_PL230 DMA CFG: CPCBUF Mask */
Kojto 102:da0ca467f8b5 551
Kojto 102:da0ca467f8b5 552 #define CMSDK_PL230_DMA_CFG_CPCPRIV_Pos 0 /* CMSDK_PL230 DMA CFG: CPCPRIV Position */
Kojto 102:da0ca467f8b5 553 #define CMSDK_PL230_DMA_CFG_CPCPRIV_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCPRIV_Pos) /* CMSDK_PL230 DMA CFG: CPCPRIV Mask */
Kojto 102:da0ca467f8b5 554
Kojto 102:da0ca467f8b5 555 #define CMSDK_PL230_CTRL_BASE_PTR_Pos PL230_DMA_CHNL_BITS + 5 /* CMSDK_PL230 STATUS: BASE_PTR Position */
Kojto 102:da0ca467f8b5 556 #define CMSDK_PL230_CTRL_BASE_PTR_Msk (0x0FFFFFFFul << CMSDK_PL230_CTRL_BASE_PTR_Pos) /* CMSDK_PL230 STATUS: BASE_PTR Mask */
Kojto 102:da0ca467f8b5 557
Kojto 102:da0ca467f8b5 558 #define CMSDK_PL230_ALT_CTRL_BASE_PTR_Pos 0 /* CMSDK_PL230 STATUS: MSTREN Position */
Kojto 102:da0ca467f8b5 559 #define CMSDK_PL230_ALT_CTRL_BASE_PTR_Msk (0xFFFFFFFFul << CMSDK_PL230_ALT_CTRL_BASE_PTR_Pos) /* CMSDK_PL230 STATUS: MSTREN Mask */
Kojto 102:da0ca467f8b5 560
Kojto 102:da0ca467f8b5 561 #define CMSDK_PL230_DMA_WAITONREQ_STATUS_Pos 0 /* CMSDK_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Position */
Kojto 102:da0ca467f8b5 562 #define CMSDK_PL230_DMA_WAITONREQ_STATUS_Msk (0xFFFFFFFFul << CMSDK_PL230_DMA_WAITONREQ_STATUS_Pos) /* CMSDK_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Mask */
Kojto 102:da0ca467f8b5 563
Kojto 102:da0ca467f8b5 564 #define CMSDK_PL230_CHNL_SW_REQUEST_Pos 0 /* CMSDK_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Position */
Kojto 102:da0ca467f8b5 565 #define CMSDK_PL230_CHNL_SW_REQUEST_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_SW_REQUEST_Pos) /* CMSDK_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Mask */
Kojto 102:da0ca467f8b5 566
Kojto 102:da0ca467f8b5 567 #define CMSDK_PL230_CHNL_USEBURST_SET_Pos 0 /* CMSDK_PL230 CHNL_USEBURST: SET Position */
Kojto 102:da0ca467f8b5 568 #define CMSDK_PL230_CHNL_USEBURST_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_USEBURST_SET_Pos) /* CMSDK_PL230 CHNL_USEBURST: SET Mask */
Kojto 102:da0ca467f8b5 569
Kojto 102:da0ca467f8b5 570 #define CMSDK_PL230_CHNL_USEBURST_CLR_Pos 0 /* CMSDK_PL230 CHNL_USEBURST: CLR Position */
Kojto 102:da0ca467f8b5 571 #define CMSDK_PL230_CHNL_USEBURST_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_USEBURST_CLR_Pos) /* CMSDK_PL230 CHNL_USEBURST: CLR Mask */
Kojto 102:da0ca467f8b5 572
Kojto 102:da0ca467f8b5 573 #define CMSDK_PL230_CHNL_REQ_MASK_SET_Pos 0 /* CMSDK_PL230 CHNL_REQ_MASK: SET Position */
Kojto 102:da0ca467f8b5 574 #define CMSDK_PL230_CHNL_REQ_MASK_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_REQ_MASK_SET_Pos) /* CMSDK_PL230 CHNL_REQ_MASK: SET Mask */
Kojto 102:da0ca467f8b5 575
Kojto 102:da0ca467f8b5 576 #define CMSDK_PL230_CHNL_REQ_MASK_CLR_Pos 0 /* CMSDK_PL230 CHNL_REQ_MASK: CLR Position */
Kojto 102:da0ca467f8b5 577 #define CMSDK_PL230_CHNL_REQ_MASK_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_REQ_MASK_CLR_Pos) /* CMSDK_PL230 CHNL_REQ_MASK: CLR Mask */
Kojto 102:da0ca467f8b5 578
Kojto 102:da0ca467f8b5 579 #define CMSDK_PL230_CHNL_ENABLE_SET_Pos 0 /* CMSDK_PL230 CHNL_ENABLE: SET Position */
Kojto 102:da0ca467f8b5 580 #define CMSDK_PL230_CHNL_ENABLE_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_ENABLE_SET_Pos) /* CMSDK_PL230 CHNL_ENABLE: SET Mask */
Kojto 102:da0ca467f8b5 581
Kojto 102:da0ca467f8b5 582 #define CMSDK_PL230_CHNL_ENABLE_CLR_Pos 0 /* CMSDK_PL230 CHNL_ENABLE: CLR Position */
Kojto 102:da0ca467f8b5 583 #define CMSDK_PL230_CHNL_ENABLE_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_ENABLE_CLR_Pos) /* CMSDK_PL230 CHNL_ENABLE: CLR Mask */
Kojto 102:da0ca467f8b5 584
Kojto 102:da0ca467f8b5 585 #define CMSDK_PL230_CHNL_PRI_ALT_SET_Pos 0 /* CMSDK_PL230 CHNL_PRI_ALT: SET Position */
Kojto 102:da0ca467f8b5 586 #define CMSDK_PL230_CHNL_PRI_ALT_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRI_ALT_SET_Pos) /* CMSDK_PL230 CHNL_PRI_ALT: SET Mask */
Kojto 102:da0ca467f8b5 587
Kojto 102:da0ca467f8b5 588 #define CMSDK_PL230_CHNL_PRI_ALT_CLR_Pos 0 /* CMSDK_PL230 CHNL_PRI_ALT: CLR Position */
Kojto 102:da0ca467f8b5 589 #define CMSDK_PL230_CHNL_PRI_ALT_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRI_ALT_CLR_Pos) /* CMSDK_PL230 CHNL_PRI_ALT: CLR Mask */
Kojto 102:da0ca467f8b5 590
Kojto 102:da0ca467f8b5 591 #define CMSDK_PL230_CHNL_PRIORITY_SET_Pos 0 /* CMSDK_PL230 CHNL_PRIORITY: SET Position */
Kojto 102:da0ca467f8b5 592 #define CMSDK_PL230_CHNL_PRIORITY_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRIORITY_SET_Pos) /* CMSDK_PL230 CHNL_PRIORITY: SET Mask */
Kojto 102:da0ca467f8b5 593
Kojto 102:da0ca467f8b5 594 #define CMSDK_PL230_CHNL_PRIORITY_CLR_Pos 0 /* CMSDK_PL230 CHNL_PRIORITY: CLR Position */
Kojto 102:da0ca467f8b5 595 #define CMSDK_PL230_CHNL_PRIORITY_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRIORITY_CLR_Pos) /* CMSDK_PL230 CHNL_PRIORITY: CLR Mask */
Kojto 102:da0ca467f8b5 596
Kojto 102:da0ca467f8b5 597 #define CMSDK_PL230_ERR_CLR_Pos 0 /* CMSDK_PL230 ERR: CLR Position */
Kojto 102:da0ca467f8b5 598 #define CMSDK_PL230_ERR_CLR_Msk (0x00000001ul << CMSDK_PL230_ERR_CLR_Pos) /* CMSDK_PL230 ERR: CLR Mask */
Kojto 102:da0ca467f8b5 599
Kojto 102:da0ca467f8b5 600
Kojto 102:da0ca467f8b5 601 /*------------------- Watchdog ----------------------------------------------*/
Kojto 102:da0ca467f8b5 602 typedef struct
Kojto 102:da0ca467f8b5 603 {
Kojto 102:da0ca467f8b5 604
Kojto 102:da0ca467f8b5 605 __IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */
Kojto 102:da0ca467f8b5 606 __I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */
Kojto 102:da0ca467f8b5 607 __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Watchdog Control Register */
Kojto 102:da0ca467f8b5 608 __O uint32_t INTCLR; /* Offset: 0x00C ( /W) Watchdog Clear Interrupt Register */
Kojto 102:da0ca467f8b5 609 __I uint32_t RAWINTSTAT; /* Offset: 0x010 (R/ ) Watchdog Raw Interrupt Status Register */
Kojto 102:da0ca467f8b5 610 __I uint32_t MASKINTSTAT; /* Offset: 0x014 (R/ ) Watchdog Interrupt Status Register */
Kojto 102:da0ca467f8b5 611 uint32_t RESERVED0[762];
Kojto 102:da0ca467f8b5 612 __IO uint32_t LOCK; /* Offset: 0xC00 (R/W) Watchdog Lock Register */
Kojto 102:da0ca467f8b5 613 uint32_t RESERVED1[191];
Kojto 102:da0ca467f8b5 614 __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Watchdog Integration Test Control Register */
Kojto 102:da0ca467f8b5 615 __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Watchdog Integration Test Output Set Register */
Kojto 102:da0ca467f8b5 616 }CMSDK_WATCHDOG_TypeDef;
Kojto 102:da0ca467f8b5 617
Kojto 102:da0ca467f8b5 618 #define CMSDK_Watchdog_LOAD_Pos 0 /* CMSDK_Watchdog LOAD: LOAD Position */
Kojto 102:da0ca467f8b5 619 #define CMSDK_Watchdog_LOAD_Msk (0xFFFFFFFFul << CMSDK_Watchdog_LOAD_Pos) /* CMSDK_Watchdog LOAD: LOAD Mask */
Kojto 102:da0ca467f8b5 620
Kojto 102:da0ca467f8b5 621 #define CMSDK_Watchdog_VALUE_Pos 0 /* CMSDK_Watchdog VALUE: VALUE Position */
Kojto 102:da0ca467f8b5 622 #define CMSDK_Watchdog_VALUE_Msk (0xFFFFFFFFul << CMSDK_Watchdog_VALUE_Pos) /* CMSDK_Watchdog VALUE: VALUE Mask */
Kojto 102:da0ca467f8b5 623
Kojto 102:da0ca467f8b5 624 #define CMSDK_Watchdog_CTRL_RESEN_Pos 1 /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Position */
Kojto 102:da0ca467f8b5 625 #define CMSDK_Watchdog_CTRL_RESEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_RESEN_Pos) /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Mask */
Kojto 102:da0ca467f8b5 626
Kojto 102:da0ca467f8b5 627 #define CMSDK_Watchdog_CTRL_INTEN_Pos 0 /* CMSDK_Watchdog CTRL_INTEN: Int Enable Position */
Kojto 102:da0ca467f8b5 628 #define CMSDK_Watchdog_CTRL_INTEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_INTEN_Pos) /* CMSDK_Watchdog CTRL_INTEN: Int Enable Mask */
Kojto 102:da0ca467f8b5 629
Kojto 102:da0ca467f8b5 630 #define CMSDK_Watchdog_INTCLR_Pos 0 /* CMSDK_Watchdog INTCLR: Int Clear Position */
Kojto 102:da0ca467f8b5 631 #define CMSDK_Watchdog_INTCLR_Msk (0x1ul << CMSDK_Watchdog_INTCLR_Pos) /* CMSDK_Watchdog INTCLR: Int Clear Mask */
Kojto 102:da0ca467f8b5 632
Kojto 102:da0ca467f8b5 633 #define CMSDK_Watchdog_RAWINTSTAT_Pos 0 /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Position */
Kojto 102:da0ca467f8b5 634 #define CMSDK_Watchdog_RAWINTSTAT_Msk (0x1ul << CMSDK_Watchdog_RAWINTSTAT_Pos) /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Mask */
Kojto 102:da0ca467f8b5 635
Kojto 102:da0ca467f8b5 636 #define CMSDK_Watchdog_MASKINTSTAT_Pos 0 /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Position */
Kojto 102:da0ca467f8b5 637 #define CMSDK_Watchdog_MASKINTSTAT_Msk (0x1ul << CMSDK_Watchdog_MASKINTSTAT_Pos) /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Mask */
Kojto 102:da0ca467f8b5 638
Kojto 102:da0ca467f8b5 639 #define CMSDK_Watchdog_LOCK_Pos 0 /* CMSDK_Watchdog LOCK: LOCK Position */
Kojto 102:da0ca467f8b5 640 #define CMSDK_Watchdog_LOCK_Msk (0x1ul << CMSDK_Watchdog_LOCK_Pos) /* CMSDK_Watchdog LOCK: LOCK Mask */
Kojto 102:da0ca467f8b5 641
Kojto 102:da0ca467f8b5 642 #define CMSDK_Watchdog_INTEGTESTEN_Pos 0 /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Position */
Kojto 102:da0ca467f8b5 643 #define CMSDK_Watchdog_INTEGTESTEN_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTEN_Pos) /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Mask */
Kojto 102:da0ca467f8b5 644
Kojto 102:da0ca467f8b5 645 #define CMSDK_Watchdog_INTEGTESTOUTSET_Pos 1 /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Position */
Kojto 102:da0ca467f8b5 646 #define CMSDK_Watchdog_INTEGTESTOUTSET_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTOUTSET_Pos) /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Mask */
Kojto 102:da0ca467f8b5 647
Kojto 102:da0ca467f8b5 648
Kojto 102:da0ca467f8b5 649
Kojto 102:da0ca467f8b5 650 /* -------------------- End of section using anonymous unions ------------------- */
Kojto 102:da0ca467f8b5 651 #if defined ( __CC_ARM )
Kojto 102:da0ca467f8b5 652 #pragma pop
Kojto 102:da0ca467f8b5 653 #elif defined(__ICCARM__)
Kojto 102:da0ca467f8b5 654 /* leave anonymous unions enabled */
Kojto 102:da0ca467f8b5 655 #elif defined(__GNUC__)
Kojto 102:da0ca467f8b5 656 /* anonymous unions are enabled by default */
Kojto 102:da0ca467f8b5 657 #elif defined(__TMS470__)
Kojto 102:da0ca467f8b5 658 /* anonymous unions are enabled by default */
Kojto 102:da0ca467f8b5 659 #elif defined(__TASKING__)
Kojto 102:da0ca467f8b5 660 #pragma warning restore
Kojto 102:da0ca467f8b5 661 #else
Kojto 102:da0ca467f8b5 662 #warning Not supported compiler type
Kojto 102:da0ca467f8b5 663 #endif
Kojto 102:da0ca467f8b5 664
Kojto 102:da0ca467f8b5 665
Kojto 102:da0ca467f8b5 666
Kojto 102:da0ca467f8b5 667
Kojto 102:da0ca467f8b5 668 /* ================================================================================ */
Kojto 102:da0ca467f8b5 669 /* ================ Peripheral memory map ================ */
Kojto 102:da0ca467f8b5 670 /* ================================================================================ */
Kojto 102:da0ca467f8b5 671
Kojto 102:da0ca467f8b5 672 /* Peripheral and SRAM base address */
Kojto 102:da0ca467f8b5 673 #define CMSDK_FLASH_BASE (0x00000000UL)
Kojto 102:da0ca467f8b5 674 #define CMSDK_SRAM_BASE (0x20000000UL)
Kojto 102:da0ca467f8b5 675 #define CMSDK_PERIPH_BASE (0x40000000UL)
Kojto 102:da0ca467f8b5 676
Kojto 102:da0ca467f8b5 677 #define CMSDK_RAM_BASE (0x20000000UL)
Kojto 102:da0ca467f8b5 678 #define CMSDK_APB_BASE (0x40000000UL)
Kojto 102:da0ca467f8b5 679 #define CMSDK_AHB_BASE (0x40010000UL)
Kojto 102:da0ca467f8b5 680
Kojto 102:da0ca467f8b5 681 /* APB peripherals */
Kojto 102:da0ca467f8b5 682 #define CMSDK_TIMER0_BASE (CMSDK_APB_BASE + 0x0000UL)
Kojto 102:da0ca467f8b5 683 #define CMSDK_TIMER1_BASE (CMSDK_APB_BASE + 0x1000UL)
Kojto 102:da0ca467f8b5 684 #define CMSDK_DUALTIMER_BASE (CMSDK_APB_BASE + 0x2000UL)
Kojto 102:da0ca467f8b5 685 #define CMSDK_DUALTIMER_1_BASE (CMSDK_DUALTIMER_BASE)
Kojto 102:da0ca467f8b5 686 #define CMSDK_DUALTIMER_2_BASE (CMSDK_DUALTIMER_BASE + 0x20UL)
Kojto 102:da0ca467f8b5 687 #define CMSDK_UART0_BASE (CMSDK_APB_BASE + 0x4000UL)
Kojto 102:da0ca467f8b5 688 #define CMSDK_UART1_BASE (CMSDK_APB_BASE + 0x5000UL)
Kojto 102:da0ca467f8b5 689 #define CMSDK_UART2_BASE (CMSDK_APB_BASE + 0x6000UL)
Kojto 102:da0ca467f8b5 690 #define CMSDK_WATCHDOG_BASE (CMSDK_APB_BASE + 0x8000UL)
Kojto 102:da0ca467f8b5 691 #define CMSDK_PL230_BASE (CMSDK_APB_BASE + 0xF000UL)
Kojto 102:da0ca467f8b5 692
Kojto 102:da0ca467f8b5 693 /* AHB peripherals */
Kojto 102:da0ca467f8b5 694 #define CMSDK_GPIO0_BASE (CMSDK_AHB_BASE + 0x0000UL)
Kojto 102:da0ca467f8b5 695 #define CMSDK_GPIO1_BASE (CMSDK_AHB_BASE + 0x1000UL)
Kojto 102:da0ca467f8b5 696 #define CMSDK_GPIO2_BASE (CMSDK_AHB_BASE + 0x2000UL)
Kojto 102:da0ca467f8b5 697 #define CMSDK_GPIO3_BASE (CMSDK_AHB_BASE + 0x3000UL)
Kojto 102:da0ca467f8b5 698 #define CMSDK_SYSCTRL_BASE (CMSDK_AHB_BASE + 0xF000UL)
Kojto 102:da0ca467f8b5 699
Kojto 102:da0ca467f8b5 700
Kojto 102:da0ca467f8b5 701 /* ================================================================================ */
Kojto 102:da0ca467f8b5 702 /* ================ Peripheral declaration ================ */
Kojto 102:da0ca467f8b5 703 /* ================================================================================ */
Kojto 102:da0ca467f8b5 704
Kojto 102:da0ca467f8b5 705 #define CMSDK_UART0 ((CMSDK_UART_TypeDef *) CMSDK_UART0_BASE )
Kojto 102:da0ca467f8b5 706 #define CMSDK_UART1 ((CMSDK_UART_TypeDef *) CMSDK_UART1_BASE )
Kojto 102:da0ca467f8b5 707 #define CMSDK_UART2 ((CMSDK_UART_TypeDef *) CMSDK_UART2_BASE )
Kojto 102:da0ca467f8b5 708 #define CMSDK_TIMER0 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER0_BASE )
Kojto 102:da0ca467f8b5 709 #define CMSDK_TIMER1 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER1_BASE )
Kojto 102:da0ca467f8b5 710 #define CMSDK_DUALTIMER ((CMSDK_DUALTIMER_BOTH_TypeDef *) CMSDK_DUALTIMER_BASE )
Kojto 102:da0ca467f8b5 711 #define CMSDK_DUALTIMER1 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_1_BASE )
Kojto 102:da0ca467f8b5 712 #define CMSDK_DUALTIMER2 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_2_BASE )
Kojto 102:da0ca467f8b5 713 #define CMSDK_WATCHDOG ((CMSDK_WATCHDOG_TypeDef *) CMSDK_WATCHDOG_BASE )
Kojto 102:da0ca467f8b5 714 #define CMSDK_DMA ((CMSDK_PL230_TypeDef *) CMSDK_PL230_BASE )
Kojto 102:da0ca467f8b5 715 #define CMSDK_GPIO0 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO0_BASE )
Kojto 102:da0ca467f8b5 716 #define CMSDK_GPIO1 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO1_BASE )
Kojto 102:da0ca467f8b5 717 #define CMSDK_GPIO2 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO2_BASE )
Kojto 102:da0ca467f8b5 718 #define CMSDK_GPIO3 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO3_BASE )
Kojto 102:da0ca467f8b5 719 #define CMSDK_SYSCON ((CMSDK_SYSCON_TypeDef *) CMSDK_SYSCTRL_BASE )
Kojto 102:da0ca467f8b5 720
Kojto 102:da0ca467f8b5 721
Kojto 102:da0ca467f8b5 722 #ifdef __cplusplus
Kojto 102:da0ca467f8b5 723 }
Kojto 102:da0ca467f8b5 724 #endif
Kojto 102:da0ca467f8b5 725
Kojto 102:da0ca467f8b5 726 #endif /* CMSDK_CM0plus_H */