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TARGET_MOTE_L152RC/stm32l152xc.h@112:6f327212ef96, 2016-01-13 (annotated)

Committer:: Kojto
Date:: Wed Jan 13 09:48:29 2016 +0000
Revision:: 112:6f327212ef96

Release 112 of the mbed library



Changes:

- new platforms - STM32 B96B F446, MOTE_L152RC

- nrf51 - fix serial init bug (character sent)

- stm all devices - fix RTC clocking in the init

- stm f0 - SystemInit clock fix, for SetVector()

- RawSerial - fix for microlib (vsnprintf with size 0)

Who changed what in which revision?

User	Revision	Line number	New contents of line
Kojto	112:6f327212ef96	1	/**
Kojto	112:6f327212ef96	2	******************************************************************************
Kojto	112:6f327212ef96	3	* @file stm32l152xc.h
Kojto	112:6f327212ef96	4	* @author MCD Application Team
Kojto	112:6f327212ef96	5	* @version V2.0.0
Kojto	112:6f327212ef96	6	* @date 5-September-2014
Kojto	112:6f327212ef96	7	* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
Kojto	112:6f327212ef96	8	* This file contains all the peripheral register's definitions, bits
Kojto	112:6f327212ef96	9	* definitions and memory mapping for STM32L1xx devices.
Kojto	112:6f327212ef96	10	*
Kojto	112:6f327212ef96	11	* This file contains:
Kojto	112:6f327212ef96	12	* - Data structures and the address mapping for all peripherals
Kojto	112:6f327212ef96	13	* - Peripheral's registers declarations and bits definition
Kojto	112:6f327212ef96	14	* - Macros to access peripherals registers hardware
Kojto	112:6f327212ef96	15	*
Kojto	112:6f327212ef96	16	******************************************************************************
Kojto	112:6f327212ef96	17	* @attention
Kojto	112:6f327212ef96	18	*
Kojto	112:6f327212ef96	19	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
Kojto	112:6f327212ef96	20	*
Kojto	112:6f327212ef96	21	* Redistribution and use in source and binary forms, with or without modification,
Kojto	112:6f327212ef96	22	* are permitted provided that the following conditions are met:
Kojto	112:6f327212ef96	23	* 1. Redistributions of source code must retain the above copyright notice,
Kojto	112:6f327212ef96	24	* this list of conditions and the following disclaimer.
Kojto	112:6f327212ef96	25	* 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto	112:6f327212ef96	26	* this list of conditions and the following disclaimer in the documentation
Kojto	112:6f327212ef96	27	* and/or other materials provided with the distribution.
Kojto	112:6f327212ef96	28	* 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto	112:6f327212ef96	29	* may be used to endorse or promote products derived from this software
Kojto	112:6f327212ef96	30	* without specific prior written permission.
Kojto	112:6f327212ef96	31	*
Kojto	112:6f327212ef96	32	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto	112:6f327212ef96	33	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto	112:6f327212ef96	34	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto	112:6f327212ef96	35	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto	112:6f327212ef96	36	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto	112:6f327212ef96	37	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto	112:6f327212ef96	38	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto	112:6f327212ef96	39	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto	112:6f327212ef96	40	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto	112:6f327212ef96	41	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto	112:6f327212ef96	42	*
Kojto	112:6f327212ef96	43	******************************************************************************
Kojto	112:6f327212ef96	44	*/
Kojto	112:6f327212ef96	45
Kojto	112:6f327212ef96	46	/** @addtogroup CMSIS
Kojto	112:6f327212ef96	47	* @{
Kojto	112:6f327212ef96	48	*/
Kojto	112:6f327212ef96	49
Kojto	112:6f327212ef96	50	/** @addtogroup stm32l152xc
Kojto	112:6f327212ef96	51	* @{
Kojto	112:6f327212ef96	52	*/
Kojto	112:6f327212ef96	53
Kojto	112:6f327212ef96	54	#ifndef __STM32L152xC_H
Kojto	112:6f327212ef96	55	#define __STM32L152xC_H
Kojto	112:6f327212ef96	56
Kojto	112:6f327212ef96	57	#ifdef __cplusplus
Kojto	112:6f327212ef96	58	extern "C" {
Kojto	112:6f327212ef96	59	#endif
Kojto	112:6f327212ef96	60
Kojto	112:6f327212ef96	61
Kojto	112:6f327212ef96	62	/** @addtogroup Configuration_section_for_CMSIS
Kojto	112:6f327212ef96	63	* @{
Kojto	112:6f327212ef96	64	*/
Kojto	112:6f327212ef96	65	/**
Kojto	112:6f327212ef96	66	* @brief Configuration of the Cortex-M3 Processor and Core Peripherals
Kojto	112:6f327212ef96	67	*/
Kojto	112:6f327212ef96	68	#define __CM3_REV 0x200 /!< Cortex-M3 Revision r2p0 /
Kojto	112:6f327212ef96	69	#define __MPU_PRESENT 1 /!< STM32L1xx provides MPU /
Kojto	112:6f327212ef96	70	#define __NVIC_PRIO_BITS 4 /!< STM32L1xx uses 4 Bits for the Priority Levels /
Kojto	112:6f327212ef96	71	#define __Vendor_SysTickConfig 0 /!< Set to 1 if different SysTick Config is used /
Kojto	112:6f327212ef96	72
Kojto	112:6f327212ef96	73	/**
Kojto	112:6f327212ef96	74	* @}
Kojto	112:6f327212ef96	75	*/
Kojto	112:6f327212ef96	76
Kojto	112:6f327212ef96	77	/** @addtogroup Peripheral_interrupt_number_definition
Kojto	112:6f327212ef96	78	* @{
Kojto	112:6f327212ef96	79	*/
Kojto	112:6f327212ef96	80
Kojto	112:6f327212ef96	81	/**
Kojto	112:6f327212ef96	82	* @brief STM32L1xx Interrupt Number Definition, according to the selected device
Kojto	112:6f327212ef96	83	* in @ref Library_configuration_section
Kojto	112:6f327212ef96	84	*/
Kojto	112:6f327212ef96	85
Kojto	112:6f327212ef96	86	/!< Interrupt Number Definition /
Kojto	112:6f327212ef96	87	typedef enum
Kojto	112:6f327212ef96	88	{
Kojto	112:6f327212ef96	89	/**** Cortex-M3 Processor Exceptions Numbers ****************************************************/
Kojto	112:6f327212ef96	90	NonMaskableInt_IRQn = -14, /!< 2 Non Maskable Interrupt /
Kojto	112:6f327212ef96	91	MemoryManagement_IRQn = -12, /!< 4 Cortex-M3 Memory Management Interrupt /
Kojto	112:6f327212ef96	92	BusFault_IRQn = -11, /!< 5 Cortex-M3 Bus Fault Interrupt /
Kojto	112:6f327212ef96	93	UsageFault_IRQn = -10, /!< 6 Cortex-M3 Usage Fault Interrupt /
Kojto	112:6f327212ef96	94	SVC_IRQn = -5, /!< 11 Cortex-M3 SV Call Interrupt /
Kojto	112:6f327212ef96	95	DebugMonitor_IRQn = -4, /!< 12 Cortex-M3 Debug Monitor Interrupt /
Kojto	112:6f327212ef96	96	PendSV_IRQn = -2, /!< 14 Cortex-M3 Pend SV Interrupt /
Kojto	112:6f327212ef96	97	SysTick_IRQn = -1, /!< 15 Cortex-M3 System Tick Interrupt /
Kojto	112:6f327212ef96	98
Kojto	112:6f327212ef96	99	/**** STM32L specific Interrupt Numbers *********************************************************/
Kojto	112:6f327212ef96	100	WWDG_IRQn = 0, /!< Window WatchDog Interrupt /
Kojto	112:6f327212ef96	101	PVD_IRQn = 1, /!< PVD through EXTI Line detection Interrupt /
Kojto	112:6f327212ef96	102	TAMPER_STAMP_IRQn = 2, /!< Tamper and TimeStamp interrupts through the EXTI line /
Kojto	112:6f327212ef96	103	RTC_WKUP_IRQn = 3, /!< RTC Wakeup Timer through EXTI Line Interrupt /
Kojto	112:6f327212ef96	104	FLASH_IRQn = 4, /!< FLASH global Interrupt /
Kojto	112:6f327212ef96	105	RCC_IRQn = 5, /!< RCC global Interrupt /
Kojto	112:6f327212ef96	106	EXTI0_IRQn = 6, /!< EXTI Line0 Interrupt /
Kojto	112:6f327212ef96	107	EXTI1_IRQn = 7, /!< EXTI Line1 Interrupt /
Kojto	112:6f327212ef96	108	EXTI2_IRQn = 8, /!< EXTI Line2 Interrupt /
Kojto	112:6f327212ef96	109	EXTI3_IRQn = 9, /!< EXTI Line3 Interrupt /
Kojto	112:6f327212ef96	110	EXTI4_IRQn = 10, /!< EXTI Line4 Interrupt /
Kojto	112:6f327212ef96	111	DMA1_Channel1_IRQn = 11, /!< DMA1 Channel 1 global Interrupt /
Kojto	112:6f327212ef96	112	DMA1_Channel2_IRQn = 12, /!< DMA1 Channel 2 global Interrupt /
Kojto	112:6f327212ef96	113	DMA1_Channel3_IRQn = 13, /!< DMA1 Channel 3 global Interrupt /
Kojto	112:6f327212ef96	114	DMA1_Channel4_IRQn = 14, /!< DMA1 Channel 4 global Interrupt /
Kojto	112:6f327212ef96	115	DMA1_Channel5_IRQn = 15, /!< DMA1 Channel 5 global Interrupt /
Kojto	112:6f327212ef96	116	DMA1_Channel6_IRQn = 16, /!< DMA1 Channel 6 global Interrupt /
Kojto	112:6f327212ef96	117	DMA1_Channel7_IRQn = 17, /!< DMA1 Channel 7 global Interrupt /
Kojto	112:6f327212ef96	118	ADC1_IRQn = 18, /!< ADC1 global Interrupt /
Kojto	112:6f327212ef96	119	USB_HP_IRQn = 19, /!< USB High Priority Interrupt /
Kojto	112:6f327212ef96	120	USB_LP_IRQn = 20, /!< USB Low Priority Interrupt /
Kojto	112:6f327212ef96	121	DAC_IRQn = 21, /!< DAC Interrupt /
Kojto	112:6f327212ef96	122	COMP_IRQn = 22, /!< Comparator through EXTI Line Interrupt /
Kojto	112:6f327212ef96	123	EXTI9_5_IRQn = 23, /!< External Line[9:5] Interrupts /
Kojto	112:6f327212ef96	124	LCD_IRQn = 24, /!< LCD Interrupt /
Kojto	112:6f327212ef96	125	TIM9_IRQn = 25, /!< TIM9 global Interrupt /
Kojto	112:6f327212ef96	126	TIM10_IRQn = 26, /!< TIM10 global Interrupt /
Kojto	112:6f327212ef96	127	TIM11_IRQn = 27, /!< TIM11 global Interrupt /
Kojto	112:6f327212ef96	128	TIM2_IRQn = 28, /!< TIM2 global Interrupt /
Kojto	112:6f327212ef96	129	TIM3_IRQn = 29, /!< TIM3 global Interrupt /
Kojto	112:6f327212ef96	130	TIM4_IRQn = 30, /!< TIM4 global Interrupt /
Kojto	112:6f327212ef96	131	I2C1_EV_IRQn = 31, /!< I2C1 Event Interrupt /
Kojto	112:6f327212ef96	132	I2C1_ER_IRQn = 32, /!< I2C1 Error Interrupt /
Kojto	112:6f327212ef96	133	I2C2_EV_IRQn = 33, /!< I2C2 Event Interrupt /
Kojto	112:6f327212ef96	134	I2C2_ER_IRQn = 34, /!< I2C2 Error Interrupt /
Kojto	112:6f327212ef96	135	SPI1_IRQn = 35, /!< SPI1 global Interrupt /
Kojto	112:6f327212ef96	136	SPI2_IRQn = 36, /!< SPI2 global Interrupt /
Kojto	112:6f327212ef96	137	USART1_IRQn = 37, /!< USART1 global Interrupt /
Kojto	112:6f327212ef96	138	USART2_IRQn = 38, /!< USART2 global Interrupt /
Kojto	112:6f327212ef96	139	USART3_IRQn = 39, /!< USART3 global Interrupt /
Kojto	112:6f327212ef96	140	EXTI15_10_IRQn = 40, /!< External Line[15:10] Interrupts /
Kojto	112:6f327212ef96	141	RTC_Alarm_IRQn = 41, /!< RTC Alarm through EXTI Line Interrupt /
Kojto	112:6f327212ef96	142	USB_FS_WKUP_IRQn = 42, /!< USB FS WakeUp from suspend through EXTI Line Interrupt /
Kojto	112:6f327212ef96	143	TIM6_IRQn = 43, /!< TIM6 global Interrupt /
Kojto	112:6f327212ef96	144	TIM7_IRQn = 44, /!< TIM7 global Interrupt /
Kojto	112:6f327212ef96	145	TIM5_IRQn = 46, /!< TIM5 global Interrupt /
Kojto	112:6f327212ef96	146	SPI3_IRQn = 47, /!< SPI3 global Interrupt /
Kojto	112:6f327212ef96	147	DMA2_Channel1_IRQn = 50, /!< DMA2 Channel 1 global Interrupt /
Kojto	112:6f327212ef96	148	DMA2_Channel2_IRQn = 51, /!< DMA2 Channel 2 global Interrupt /
Kojto	112:6f327212ef96	149	DMA2_Channel3_IRQn = 52, /!< DMA2 Channel 3 global Interrupt /
Kojto	112:6f327212ef96	150	DMA2_Channel4_IRQn = 53, /!< DMA2 Channel 4 global Interrupt /
Kojto	112:6f327212ef96	151	DMA2_Channel5_IRQn = 54, /!< DMA2 Channel 5 global Interrupt /
Kojto	112:6f327212ef96	152	COMP_ACQ_IRQn = 56 /!< Comparator Channel Acquisition global Interrupt /
Kojto	112:6f327212ef96	153	} IRQn_Type;
Kojto	112:6f327212ef96	154
Kojto	112:6f327212ef96	155	/**
Kojto	112:6f327212ef96	156	* @}
Kojto	112:6f327212ef96	157	*/
Kojto	112:6f327212ef96	158
Kojto	112:6f327212ef96	159	#include "core_cm3.h"
Kojto	112:6f327212ef96	160	#include "system_stm32l1xx.h"
Kojto	112:6f327212ef96	161	#include <stdint.h>
Kojto	112:6f327212ef96	162
Kojto	112:6f327212ef96	163	/** @addtogroup Peripheral_registers_structures
Kojto	112:6f327212ef96	164	* @{
Kojto	112:6f327212ef96	165	*/
Kojto	112:6f327212ef96	166
Kojto	112:6f327212ef96	167	/**
Kojto	112:6f327212ef96	168	* @brief Analog to Digital Converter
Kojto	112:6f327212ef96	169	*/
Kojto	112:6f327212ef96	170
Kojto	112:6f327212ef96	171	typedef struct
Kojto	112:6f327212ef96	172	{
Kojto	112:6f327212ef96	173	__IO uint32_t SR; /!< ADC status register, Address offset: 0x00 /
Kojto	112:6f327212ef96	174	__IO uint32_t CR1; /!< ADC control register 1, Address offset: 0x04 /
Kojto	112:6f327212ef96	175	__IO uint32_t CR2; /!< ADC control register 2, Address offset: 0x08 /
Kojto	112:6f327212ef96	176	__IO uint32_t SMPR1; /!< ADC sample time register 1, Address offset: 0x0C /
Kojto	112:6f327212ef96	177	__IO uint32_t SMPR2; /!< ADC sample time register 2, Address offset: 0x10 /
Kojto	112:6f327212ef96	178	__IO uint32_t SMPR3; /!< ADC sample time register 3, Address offset: 0x14 /
Kojto	112:6f327212ef96	179	__IO uint32_t JOFR1; /!< ADC injected channel data offset register 1, Address offset: 0x18 /
Kojto	112:6f327212ef96	180	__IO uint32_t JOFR2; /!< ADC injected channel data offset register 2, Address offset: 0x1C /
Kojto	112:6f327212ef96	181	__IO uint32_t JOFR3; /!< ADC injected channel data offset register 3, Address offset: 0x20 /
Kojto	112:6f327212ef96	182	__IO uint32_t JOFR4; /!< ADC injected channel data offset register 4, Address offset: 0x24 /
Kojto	112:6f327212ef96	183	__IO uint32_t HTR; /!< ADC watchdog higher threshold register, Address offset: 0x28 /
Kojto	112:6f327212ef96	184	__IO uint32_t LTR; /!< ADC watchdog lower threshold register, Address offset: 0x2C /
Kojto	112:6f327212ef96	185	__IO uint32_t SQR1; /!< ADC regular sequence register 1, Address offset: 0x30 /
Kojto	112:6f327212ef96	186	__IO uint32_t SQR2; /!< ADC regular sequence register 2, Address offset: 0x34 /
Kojto	112:6f327212ef96	187	__IO uint32_t SQR3; /!< ADC regular sequence register 3, Address offset: 0x38 /
Kojto	112:6f327212ef96	188	__IO uint32_t SQR4; /!< ADC regular sequence register 4, Address offset: 0x3C /
Kojto	112:6f327212ef96	189	__IO uint32_t SQR5; /!< ADC regular sequence register 5, Address offset: 0x40 /
Kojto	112:6f327212ef96	190	__IO uint32_t JSQR; /!< ADC injected sequence register, Address offset: 0x44 /
Kojto	112:6f327212ef96	191	__IO uint32_t JDR1; /!< ADC injected data register 1, Address offset: 0x48 /
Kojto	112:6f327212ef96	192	__IO uint32_t JDR2; /!< ADC injected data register 2, Address offset: 0x4C /
Kojto	112:6f327212ef96	193	__IO uint32_t JDR3; /!< ADC injected data register 3, Address offset: 0x50 /
Kojto	112:6f327212ef96	194	__IO uint32_t JDR4; /!< ADC injected data register 4, Address offset: 0x54 /
Kojto	112:6f327212ef96	195	__IO uint32_t DR; /!< ADC regular data register, Address offset: 0x58 /
Kojto	112:6f327212ef96	196	uint32_t RESERVED; /!< Reserved, Address offset: 0x5C /
Kojto	112:6f327212ef96	197	} ADC_TypeDef;
Kojto	112:6f327212ef96	198
Kojto	112:6f327212ef96	199	typedef struct
Kojto	112:6f327212ef96	200	{
Kojto	112:6f327212ef96	201	__IO uint32_t CSR; /!< ADC common status register, Address offset: ADC1 base address + 0x300 /
Kojto	112:6f327212ef96	202	__IO uint32_t CCR; /!< ADC common control register, Address offset: ADC1 base address + 0x304 /
Kojto	112:6f327212ef96	203	} ADC_Common_TypeDef;
Kojto	112:6f327212ef96	204
Kojto	112:6f327212ef96	205	/**
Kojto	112:6f327212ef96	206	* @brief Comparator
Kojto	112:6f327212ef96	207	*/
Kojto	112:6f327212ef96	208
Kojto	112:6f327212ef96	209	typedef struct
Kojto	112:6f327212ef96	210	{
Kojto	112:6f327212ef96	211	__IO uint32_t CSR; /!< COMP comparator control and status register, Address offset: 0x00 /
Kojto	112:6f327212ef96	212	} COMP_TypeDef;
Kojto	112:6f327212ef96	213
Kojto	112:6f327212ef96	214	/**
Kojto	112:6f327212ef96	215	* @brief CRC calculation unit
Kojto	112:6f327212ef96	216	*/
Kojto	112:6f327212ef96	217
Kojto	112:6f327212ef96	218	typedef struct
Kojto	112:6f327212ef96	219	{
Kojto	112:6f327212ef96	220	__IO uint32_t DR; /!< CRC Data register, Address offset: 0x00 /
Kojto	112:6f327212ef96	221	__IO uint32_t IDR; /!< CRC Independent data register, Address offset: 0x04 /
Kojto	112:6f327212ef96	222	__IO uint32_t CR; /!< CRC Control register, Address offset: 0x08 /
Kojto	112:6f327212ef96	223	} CRC_TypeDef;
Kojto	112:6f327212ef96	224
Kojto	112:6f327212ef96	225	/**
Kojto	112:6f327212ef96	226	* @brief Digital to Analog Converter
Kojto	112:6f327212ef96	227	*/
Kojto	112:6f327212ef96	228
Kojto	112:6f327212ef96	229	typedef struct
Kojto	112:6f327212ef96	230	{
Kojto	112:6f327212ef96	231	__IO uint32_t CR; /!< DAC control register, Address offset: 0x00 /
Kojto	112:6f327212ef96	232	__IO uint32_t SWTRIGR; /!< DAC software trigger register, Address offset: 0x04 /
Kojto	112:6f327212ef96	233	__IO uint32_t DHR12R1; /!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 /
Kojto	112:6f327212ef96	234	__IO uint32_t DHR12L1; /!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C /
Kojto	112:6f327212ef96	235	__IO uint32_t DHR8R1; /!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 /
Kojto	112:6f327212ef96	236	__IO uint32_t DHR12R2; /!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 /
Kojto	112:6f327212ef96	237	__IO uint32_t DHR12L2; /!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 /
Kojto	112:6f327212ef96	238	__IO uint32_t DHR8R2; /!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C /
Kojto	112:6f327212ef96	239	__IO uint32_t DHR12RD; /!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 /
Kojto	112:6f327212ef96	240	__IO uint32_t DHR12LD; /!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 /
Kojto	112:6f327212ef96	241	__IO uint32_t DHR8RD; /!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 /
Kojto	112:6f327212ef96	242	__IO uint32_t DOR1; /!< DAC channel1 data output register, Address offset: 0x2C /
Kojto	112:6f327212ef96	243	__IO uint32_t DOR2; /!< DAC channel2 data output register, Address offset: 0x30 /
Kojto	112:6f327212ef96	244	__IO uint32_t SR; /!< DAC status register, Address offset: 0x34 /
Kojto	112:6f327212ef96	245	} DAC_TypeDef;
Kojto	112:6f327212ef96	246
Kojto	112:6f327212ef96	247	/**
Kojto	112:6f327212ef96	248	* @brief Debug MCU
Kojto	112:6f327212ef96	249	*/
Kojto	112:6f327212ef96	250
Kojto	112:6f327212ef96	251	typedef struct
Kojto	112:6f327212ef96	252	{
Kojto	112:6f327212ef96	253	__IO uint32_t IDCODE; /!< MCU device ID code, Address offset: 0x00 /
Kojto	112:6f327212ef96	254	__IO uint32_t CR; /!< Debug MCU configuration register, Address offset: 0x04 /
Kojto	112:6f327212ef96	255	__IO uint32_t APB1FZ; /!< Debug MCU APB1 freeze register, Address offset: 0x08 /
Kojto	112:6f327212ef96	256	__IO uint32_t APB2FZ; /!< Debug MCU APB2 freeze register, Address offset: 0x0C /
Kojto	112:6f327212ef96	257	}DBGMCU_TypeDef;
Kojto	112:6f327212ef96	258
Kojto	112:6f327212ef96	259	/**
Kojto	112:6f327212ef96	260	* @brief DMA Controller
Kojto	112:6f327212ef96	261	*/
Kojto	112:6f327212ef96	262
Kojto	112:6f327212ef96	263	typedef struct
Kojto	112:6f327212ef96	264	{
Kojto	112:6f327212ef96	265	__IO uint32_t CCR; /!< DMA channel x configuration register /
Kojto	112:6f327212ef96	266	__IO uint32_t CNDTR; /!< DMA channel x number of data register /
Kojto	112:6f327212ef96	267	__IO uint32_t CPAR; /!< DMA channel x peripheral address register /
Kojto	112:6f327212ef96	268	__IO uint32_t CMAR; /!< DMA channel x memory address register /
Kojto	112:6f327212ef96	269	} DMA_Channel_TypeDef;
Kojto	112:6f327212ef96	270
Kojto	112:6f327212ef96	271	typedef struct
Kojto	112:6f327212ef96	272	{
Kojto	112:6f327212ef96	273	__IO uint32_t ISR; /!< DMA interrupt status register, Address offset: 0x00 /
Kojto	112:6f327212ef96	274	__IO uint32_t IFCR; /!< DMA interrupt flag clear register, Address offset: 0x04 /
Kojto	112:6f327212ef96	275	} DMA_TypeDef;
Kojto	112:6f327212ef96	276
Kojto	112:6f327212ef96	277	/**
Kojto	112:6f327212ef96	278	* @brief External Interrupt/Event Controller
Kojto	112:6f327212ef96	279	*/
Kojto	112:6f327212ef96	280
Kojto	112:6f327212ef96	281	typedef struct
Kojto	112:6f327212ef96	282	{
Kojto	112:6f327212ef96	283	__IO uint32_t IMR; /!<EXTI Interrupt mask register, Address offset: 0x00 /
Kojto	112:6f327212ef96	284	__IO uint32_t EMR; /!<EXTI Event mask register, Address offset: 0x04 /
Kojto	112:6f327212ef96	285	__IO uint32_t RTSR; /!<EXTI Rising trigger selection register , Address offset: 0x08 /
Kojto	112:6f327212ef96	286	__IO uint32_t FTSR; /!<EXTI Falling trigger selection register, Address offset: 0x0C /
Kojto	112:6f327212ef96	287	__IO uint32_t SWIER; /!<EXTI Software interrupt event register, Address offset: 0x10 /
Kojto	112:6f327212ef96	288	__IO uint32_t PR; /!<EXTI Pending register, Address offset: 0x14 /
Kojto	112:6f327212ef96	289	} EXTI_TypeDef;
Kojto	112:6f327212ef96	290
Kojto	112:6f327212ef96	291	/**
Kojto	112:6f327212ef96	292	* @brief FLASH Registers
Kojto	112:6f327212ef96	293	*/
Kojto	112:6f327212ef96	294	typedef struct
Kojto	112:6f327212ef96	295	{
Kojto	112:6f327212ef96	296	__IO uint32_t ACR; /!< Access control register, Address offset: 0x00 /
Kojto	112:6f327212ef96	297	__IO uint32_t PECR; /!< Program/erase control register, Address offset: 0x04 /
Kojto	112:6f327212ef96	298	__IO uint32_t PDKEYR; /!< Power down key register, Address offset: 0x08 /
Kojto	112:6f327212ef96	299	__IO uint32_t PEKEYR; /!< Program/erase key register, Address offset: 0x0c /
Kojto	112:6f327212ef96	300	__IO uint32_t PRGKEYR; /!< Program memory key register, Address offset: 0x10 /
Kojto	112:6f327212ef96	301	__IO uint32_t OPTKEYR; /!< Option byte key register, Address offset: 0x14 /
Kojto	112:6f327212ef96	302	__IO uint32_t SR; /!< Status register, Address offset: 0x18 /
Kojto	112:6f327212ef96	303	__IO uint32_t OBR; /!< Option byte register, Address offset: 0x1c /
Kojto	112:6f327212ef96	304	__IO uint32_t WRPR1; /!< Write protection register 1, Address offset: 0x20 /
Kojto	112:6f327212ef96	305	uint32_t RESERVED[23]; /!< Reserved, Address offset: 0x24 /
Kojto	112:6f327212ef96	306	__IO uint32_t WRPR2; /!< Write protection register 2, Address offset: 0x80 /
Kojto	112:6f327212ef96	307	} FLASH_TypeDef;
Kojto	112:6f327212ef96	308
Kojto	112:6f327212ef96	309	/**
Kojto	112:6f327212ef96	310	* @brief Option Bytes Registers
Kojto	112:6f327212ef96	311	*/
Kojto	112:6f327212ef96	312	typedef struct
Kojto	112:6f327212ef96	313	{
Kojto	112:6f327212ef96	314	__IO uint32_t RDP; /!< Read protection register, Address offset: 0x00 /
Kojto	112:6f327212ef96	315	__IO uint32_t USER; /!< user register, Address offset: 0x04 /
Kojto	112:6f327212ef96	316	__IO uint32_t WRP01; /!< write protection register 0 1, Address offset: 0x08 /
Kojto	112:6f327212ef96	317	__IO uint32_t WRP23; /!< write protection register 2 3, Address offset: 0x0C /
Kojto	112:6f327212ef96	318	__IO uint32_t WRP45; /!< write protection register 4 5, Address offset: 0x10 /
Kojto	112:6f327212ef96	319	__IO uint32_t WRP67; /!< write protection register 6 7, Address offset: 0x14 /
Kojto	112:6f327212ef96	320	} OB_TypeDef;
Kojto	112:6f327212ef96	321
Kojto	112:6f327212ef96	322	/**
Kojto	112:6f327212ef96	323	* @brief Operational Amplifier (OPAMP)
Kojto	112:6f327212ef96	324	*/
Kojto	112:6f327212ef96	325	typedef struct
Kojto	112:6f327212ef96	326	{
Kojto	112:6f327212ef96	327	__IO uint32_t CSR; /!< OPAMP control/status register, Address offset: 0x00 /
Kojto	112:6f327212ef96	328	__IO uint32_t OTR; /!< OPAMP offset trimming register for normal mode, Address offset: 0x04 /
Kojto	112:6f327212ef96	329	__IO uint32_t LPOTR; /!< OPAMP offset trimming register for low power mode, Address offset: 0x08 /
Kojto	112:6f327212ef96	330	} OPAMP_TypeDef;
Kojto	112:6f327212ef96	331
Kojto	112:6f327212ef96	332	/**
Kojto	112:6f327212ef96	333	* @brief General Purpose IO
Kojto	112:6f327212ef96	334	*/
Kojto	112:6f327212ef96	335
Kojto	112:6f327212ef96	336	typedef struct
Kojto	112:6f327212ef96	337	{
Kojto	112:6f327212ef96	338	__IO uint32_t MODER; /!< GPIO port mode register, Address offset: 0x00 /
Kojto	112:6f327212ef96	339	__IO uint32_t OTYPER; /!< GPIO port output type register, Address offset: 0x04 /
Kojto	112:6f327212ef96	340	__IO uint32_t OSPEEDR; /!< GPIO port output speed register, Address offset: 0x08 /
Kojto	112:6f327212ef96	341	__IO uint32_t PUPDR; /!< GPIO port pull-up/pull-down register, Address offset: 0x0C /
Kojto	112:6f327212ef96	342	__IO uint32_t IDR; /!< GPIO port input data register, Address offset: 0x10 /
Kojto	112:6f327212ef96	343	__IO uint32_t ODR; /!< GPIO port output data register, Address offset: 0x14 /
Kojto	112:6f327212ef96	344	__IO uint32_t BSRR; /!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 /
Kojto	112:6f327212ef96	345	__IO uint32_t LCKR; /!< GPIO port configuration lock register, Address offset: 0x1C /
Kojto	112:6f327212ef96	346	__IO uint32_t AFR[2]; /!< GPIO alternate function register, Address offset: 0x20-0x24 /
Kojto	112:6f327212ef96	347	__IO uint32_t BRR; /!< GPIO bit reset register, Address offset: 0x28 /
Kojto	112:6f327212ef96	348	} GPIO_TypeDef;
Kojto	112:6f327212ef96	349
Kojto	112:6f327212ef96	350	/**
Kojto	112:6f327212ef96	351	* @brief SysTem Configuration
Kojto	112:6f327212ef96	352	*/
Kojto	112:6f327212ef96	353
Kojto	112:6f327212ef96	354	typedef struct
Kojto	112:6f327212ef96	355	{
Kojto	112:6f327212ef96	356	__IO uint32_t MEMRMP; /!< SYSCFG memory remap register, Address offset: 0x00 /
Kojto	112:6f327212ef96	357	__IO uint32_t PMC; /!< SYSCFG peripheral mode configuration register, Address offset: 0x04 /
Kojto	112:6f327212ef96	358	__IO uint32_t EXTICR[4]; /!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 /
Kojto	112:6f327212ef96	359	} SYSCFG_TypeDef;
Kojto	112:6f327212ef96	360
Kojto	112:6f327212ef96	361	/**
Kojto	112:6f327212ef96	362	* @brief Inter-integrated Circuit Interface
Kojto	112:6f327212ef96	363	*/
Kojto	112:6f327212ef96	364
Kojto	112:6f327212ef96	365	typedef struct
Kojto	112:6f327212ef96	366	{
Kojto	112:6f327212ef96	367	__IO uint32_t CR1; /!< I2C Control register 1, Address offset: 0x00 /
Kojto	112:6f327212ef96	368	__IO uint32_t CR2; /!< I2C Control register 2, Address offset: 0x04 /
Kojto	112:6f327212ef96	369	__IO uint32_t OAR1; /!< I2C Own address register 1, Address offset: 0x08 /
Kojto	112:6f327212ef96	370	__IO uint32_t OAR2; /!< I2C Own address register 2, Address offset: 0x0C /
Kojto	112:6f327212ef96	371	__IO uint32_t DR; /!< I2C Data register, Address offset: 0x10 /
Kojto	112:6f327212ef96	372	__IO uint32_t SR1; /!< I2C Status register 1, Address offset: 0x14 /
Kojto	112:6f327212ef96	373	__IO uint32_t SR2; /!< I2C Status register 2, Address offset: 0x18 /
Kojto	112:6f327212ef96	374	__IO uint32_t CCR; /!< I2C Clock control register, Address offset: 0x1C /
Kojto	112:6f327212ef96	375	__IO uint32_t TRISE; /!< I2C TRISE register, Address offset: 0x20 /
Kojto	112:6f327212ef96	376	} I2C_TypeDef;
Kojto	112:6f327212ef96	377
Kojto	112:6f327212ef96	378	/**
Kojto	112:6f327212ef96	379	* @brief Independent WATCHDOG
Kojto	112:6f327212ef96	380	*/
Kojto	112:6f327212ef96	381
Kojto	112:6f327212ef96	382	typedef struct
Kojto	112:6f327212ef96	383	{
Kojto	112:6f327212ef96	384	__IO uint32_t KR; /!< Key register, Address offset: 0x00 /
Kojto	112:6f327212ef96	385	__IO uint32_t PR; /!< Prescaler register, Address offset: 0x04 /
Kojto	112:6f327212ef96	386	__IO uint32_t RLR; /!< Reload register, Address offset: 0x08 /
Kojto	112:6f327212ef96	387	__IO uint32_t SR; /!< Status register, Address offset: 0x0C /
Kojto	112:6f327212ef96	388	} IWDG_TypeDef;
Kojto	112:6f327212ef96	389
Kojto	112:6f327212ef96	390	/**
Kojto	112:6f327212ef96	391	* @brief LCD
Kojto	112:6f327212ef96	392	*/
Kojto	112:6f327212ef96	393
Kojto	112:6f327212ef96	394	typedef struct
Kojto	112:6f327212ef96	395	{
Kojto	112:6f327212ef96	396	__IO uint32_t CR; /!< LCD control register, Address offset: 0x00 /
Kojto	112:6f327212ef96	397	__IO uint32_t FCR; /!< LCD frame control register, Address offset: 0x04 /
Kojto	112:6f327212ef96	398	__IO uint32_t SR; /!< LCD status register, Address offset: 0x08 /
Kojto	112:6f327212ef96	399	__IO uint32_t CLR; /!< LCD clear register, Address offset: 0x0C /
Kojto	112:6f327212ef96	400	uint32_t RESERVED; /!< Reserved, Address offset: 0x10 /
Kojto	112:6f327212ef96	401	__IO uint32_t RAM[16]; /!< LCD display memory, Address offset: 0x14-0x50 /
Kojto	112:6f327212ef96	402	} LCD_TypeDef;
Kojto	112:6f327212ef96	403
Kojto	112:6f327212ef96	404	/**
Kojto	112:6f327212ef96	405	* @brief Power Control
Kojto	112:6f327212ef96	406	*/
Kojto	112:6f327212ef96	407
Kojto	112:6f327212ef96	408	typedef struct
Kojto	112:6f327212ef96	409	{
Kojto	112:6f327212ef96	410	__IO uint32_t CR; /!< PWR power control register, Address offset: 0x00 /
Kojto	112:6f327212ef96	411	__IO uint32_t CSR; /!< PWR power control/status register, Address offset: 0x04 /
Kojto	112:6f327212ef96	412	} PWR_TypeDef;
Kojto	112:6f327212ef96	413
Kojto	112:6f327212ef96	414	/**
Kojto	112:6f327212ef96	415	* @brief Reset and Clock Control
Kojto	112:6f327212ef96	416	*/
Kojto	112:6f327212ef96	417
Kojto	112:6f327212ef96	418	typedef struct
Kojto	112:6f327212ef96	419	{
Kojto	112:6f327212ef96	420	__IO uint32_t CR; /!< RCC clock control register, Address offset: 0x00 /
Kojto	112:6f327212ef96	421	__IO uint32_t ICSCR; /!< RCC Internal clock sources calibration register, Address offset: 0x04 /
Kojto	112:6f327212ef96	422	__IO uint32_t CFGR; /!< RCC Clock configuration register, Address offset: 0x08 /
Kojto	112:6f327212ef96	423	__IO uint32_t CIR; /!< RCC Clock interrupt register, Address offset: 0x0C /
Kojto	112:6f327212ef96	424	__IO uint32_t AHBRSTR; /!< RCC AHB peripheral reset register, Address offset: 0x10 /
Kojto	112:6f327212ef96	425	__IO uint32_t APB2RSTR; /!< RCC APB2 peripheral reset register, Address offset: 0x14 /
Kojto	112:6f327212ef96	426	__IO uint32_t APB1RSTR; /!< RCC APB1 peripheral reset register, Address offset: 0x18 /
Kojto	112:6f327212ef96	427	__IO uint32_t AHBENR; /!< RCC AHB peripheral clock enable register, Address offset: 0x1C /
Kojto	112:6f327212ef96	428	__IO uint32_t APB2ENR; /!< RCC APB2 peripheral clock enable register, Address offset: 0x20 /
Kojto	112:6f327212ef96	429	__IO uint32_t APB1ENR; /!< RCC APB1 peripheral clock enable register, Address offset: 0x24 /
Kojto	112:6f327212ef96	430	__IO uint32_t AHBLPENR; /!< RCC AHB peripheral clock enable in low power mode register, Address offset: 0x28 /
Kojto	112:6f327212ef96	431	__IO uint32_t APB2LPENR; /!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x2C /
Kojto	112:6f327212ef96	432	__IO uint32_t APB1LPENR; /!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x30 /
Kojto	112:6f327212ef96	433	__IO uint32_t CSR; /!< RCC Control/status register, Address offset: 0x34 /
Kojto	112:6f327212ef96	434	} RCC_TypeDef;
Kojto	112:6f327212ef96	435
Kojto	112:6f327212ef96	436	/**
Kojto	112:6f327212ef96	437	* @brief Routing Interface
Kojto	112:6f327212ef96	438	*/
Kojto	112:6f327212ef96	439
Kojto	112:6f327212ef96	440	typedef struct
Kojto	112:6f327212ef96	441	{
Kojto	112:6f327212ef96	442	__IO uint32_t ICR; /!< RI input capture register, Address offset: 0x00 /
Kojto	112:6f327212ef96	443	__IO uint32_t ASCR1; /!< RI analog switches control register, Address offset: 0x04 /
Kojto	112:6f327212ef96	444	__IO uint32_t ASCR2; /!< RI analog switch control register 2, Address offset: 0x08 /
Kojto	112:6f327212ef96	445	__IO uint32_t HYSCR1; /!< RI hysteresis control register, Address offset: 0x0C /
Kojto	112:6f327212ef96	446	__IO uint32_t HYSCR2; /!< RI Hysteresis control register, Address offset: 0x10 /
Kojto	112:6f327212ef96	447	__IO uint32_t HYSCR3; /!< RI Hysteresis control register, Address offset: 0x14 /
Kojto	112:6f327212ef96	448	uint32_t RESERVED1; /!< Reserved, 0x18 /
Kojto	112:6f327212ef96	449	__IO uint32_t ASMR1; /!< RI Analog switch mode register 1, Address offset: 0x1C /
Kojto	112:6f327212ef96	450	__IO uint32_t CMR1; /!< RI Channel mask register 1, Address offset: 0x20 /
Kojto	112:6f327212ef96	451	__IO uint32_t CICR1; /!< RI Channel Iden for capture register 1, Address offset: 0x24 /
Kojto	112:6f327212ef96	452	__IO uint32_t ASMR2; /!< RI Analog switch mode register 2, Address offset: 0x28 /
Kojto	112:6f327212ef96	453	__IO uint32_t CMR2; /!< RI Channel mask register 2, Address offset: 0x2C /
Kojto	112:6f327212ef96	454	__IO uint32_t CICR2; /!< RI Channel Iden for capture register 2, Address offset: 0x30 /
Kojto	112:6f327212ef96	455	__IO uint32_t ASMR3; /!< RI Analog switch mode register 3, Address offset: 0x34 /
Kojto	112:6f327212ef96	456	__IO uint32_t CMR3; /!< RI Channel mask register 3, Address offset: 0x38 /
Kojto	112:6f327212ef96	457	__IO uint32_t CICR3; /!< RI Channel Iden for capture register 3, Address offset: 0x3C /
Kojto	112:6f327212ef96	458	} RI_TypeDef;
Kojto	112:6f327212ef96	459
Kojto	112:6f327212ef96	460	/**
Kojto	112:6f327212ef96	461	* @brief Real-Time Clock
Kojto	112:6f327212ef96	462	*/
Kojto	112:6f327212ef96	463	typedef struct
Kojto	112:6f327212ef96	464	{
Kojto	112:6f327212ef96	465	__IO uint32_t TR; /!< RTC time register, Address offset: 0x00 /
Kojto	112:6f327212ef96	466	__IO uint32_t DR; /!< RTC date register, Address offset: 0x04 /
Kojto	112:6f327212ef96	467	__IO uint32_t CR; /!< RTC control register, Address offset: 0x08 /
Kojto	112:6f327212ef96	468	__IO uint32_t ISR; /!< RTC initialization and status register, Address offset: 0x0C /
Kojto	112:6f327212ef96	469	__IO uint32_t PRER; /!< RTC prescaler register, Address offset: 0x10 /
Kojto	112:6f327212ef96	470	__IO uint32_t WUTR; /!< RTC wakeup timer register, Address offset: 0x14 /
Kojto	112:6f327212ef96	471	__IO uint32_t CALIBR; /!< RTC calibration register, Address offset: 0x18 /
Kojto	112:6f327212ef96	472	__IO uint32_t ALRMAR; /!< RTC alarm A register, Address offset: 0x1C /
Kojto	112:6f327212ef96	473	__IO uint32_t ALRMBR; /!< RTC alarm B register, Address offset: 0x20 /
Kojto	112:6f327212ef96	474	__IO uint32_t WPR; /!< RTC write protection register, Address offset: 0x24 /
Kojto	112:6f327212ef96	475	__IO uint32_t SSR; /!< RTC sub second register, Address offset: 0x28 /
Kojto	112:6f327212ef96	476	__IO uint32_t SHIFTR; /!< RTC shift control register, Address offset: 0x2C /
Kojto	112:6f327212ef96	477	__IO uint32_t TSTR; /!< RTC time stamp time register, Address offset: 0x30 /
Kojto	112:6f327212ef96	478	__IO uint32_t TSDR; /!< RTC time stamp date register, Address offset: 0x34 /
Kojto	112:6f327212ef96	479	__IO uint32_t TSSSR; /!< RTC time-stamp sub second register, Address offset: 0x38 /
Kojto	112:6f327212ef96	480	__IO uint32_t CALR; /!< RRTC calibration register, Address offset: 0x3C /
Kojto	112:6f327212ef96	481	__IO uint32_t TAFCR; /!< RTC tamper and alternate function configuration register, Address offset: 0x40 /
Kojto	112:6f327212ef96	482	__IO uint32_t ALRMASSR; /!< RTC alarm A sub second register, Address offset: 0x44 /
Kojto	112:6f327212ef96	483	__IO uint32_t ALRMBSSR; /!< RTC alarm B sub second register, Address offset: 0x48 /
Kojto	112:6f327212ef96	484	uint32_t RESERVED7; /!< Reserved, 0x4C /
Kojto	112:6f327212ef96	485	__IO uint32_t BKP0R; /!< RTC backup register 0, Address offset: 0x50 /
Kojto	112:6f327212ef96	486	__IO uint32_t BKP1R; /!< RTC backup register 1, Address offset: 0x54 /
Kojto	112:6f327212ef96	487	__IO uint32_t BKP2R; /!< RTC backup register 2, Address offset: 0x58 /
Kojto	112:6f327212ef96	488	__IO uint32_t BKP3R; /!< RTC backup register 3, Address offset: 0x5C /
Kojto	112:6f327212ef96	489	__IO uint32_t BKP4R; /!< RTC backup register 4, Address offset: 0x60 /
Kojto	112:6f327212ef96	490	__IO uint32_t BKP5R; /!< RTC backup register 5, Address offset: 0x64 /
Kojto	112:6f327212ef96	491	__IO uint32_t BKP6R; /!< RTC backup register 6, Address offset: 0x68 /
Kojto	112:6f327212ef96	492	__IO uint32_t BKP7R; /!< RTC backup register 7, Address offset: 0x6C /
Kojto	112:6f327212ef96	493	__IO uint32_t BKP8R; /!< RTC backup register 8, Address offset: 0x70 /
Kojto	112:6f327212ef96	494	__IO uint32_t BKP9R; /!< RTC backup register 9, Address offset: 0x74 /
Kojto	112:6f327212ef96	495	__IO uint32_t BKP10R; /!< RTC backup register 10, Address offset: 0x78 /
Kojto	112:6f327212ef96	496	__IO uint32_t BKP11R; /!< RTC backup register 11, Address offset: 0x7C /
Kojto	112:6f327212ef96	497	__IO uint32_t BKP12R; /!< RTC backup register 12, Address offset: 0x80 /
Kojto	112:6f327212ef96	498	__IO uint32_t BKP13R; /!< RTC backup register 13, Address offset: 0x84 /
Kojto	112:6f327212ef96	499	__IO uint32_t BKP14R; /!< RTC backup register 14, Address offset: 0x88 /
Kojto	112:6f327212ef96	500	__IO uint32_t BKP15R; /!< RTC backup register 15, Address offset: 0x8C /
Kojto	112:6f327212ef96	501	__IO uint32_t BKP16R; /!< RTC backup register 16, Address offset: 0x90 /
Kojto	112:6f327212ef96	502	__IO uint32_t BKP17R; /!< RTC backup register 17, Address offset: 0x94 /
Kojto	112:6f327212ef96	503	__IO uint32_t BKP18R; /!< RTC backup register 18, Address offset: 0x98 /
Kojto	112:6f327212ef96	504	__IO uint32_t BKP19R; /!< RTC backup register 19, Address offset: 0x9C /
Kojto	112:6f327212ef96	505	__IO uint32_t BKP20R; /!< RTC backup register 20, Address offset: 0xA0 /
Kojto	112:6f327212ef96	506	__IO uint32_t BKP21R; /!< RTC backup register 21, Address offset: 0xA4 /
Kojto	112:6f327212ef96	507	__IO uint32_t BKP22R; /!< RTC backup register 22, Address offset: 0xA8 /
Kojto	112:6f327212ef96	508	__IO uint32_t BKP23R; /!< RTC backup register 23, Address offset: 0xAC /
Kojto	112:6f327212ef96	509	__IO uint32_t BKP24R; /!< RTC backup register 24, Address offset: 0xB0 /
Kojto	112:6f327212ef96	510	__IO uint32_t BKP25R; /!< RTC backup register 25, Address offset: 0xB4 /
Kojto	112:6f327212ef96	511	__IO uint32_t BKP26R; /!< RTC backup register 26, Address offset: 0xB8 /
Kojto	112:6f327212ef96	512	__IO uint32_t BKP27R; /!< RTC backup register 27, Address offset: 0xBC /
Kojto	112:6f327212ef96	513	__IO uint32_t BKP28R; /!< RTC backup register 28, Address offset: 0xC0 /
Kojto	112:6f327212ef96	514	__IO uint32_t BKP29R; /!< RTC backup register 29, Address offset: 0xC4 /
Kojto	112:6f327212ef96	515	__IO uint32_t BKP30R; /!< RTC backup register 30, Address offset: 0xC8 /
Kojto	112:6f327212ef96	516	__IO uint32_t BKP31R; /!< RTC backup register 31, Address offset: 0xCC /
Kojto	112:6f327212ef96	517	} RTC_TypeDef;
Kojto	112:6f327212ef96	518
Kojto	112:6f327212ef96	519	/**
Kojto	112:6f327212ef96	520	* @brief Serial Peripheral Interface
Kojto	112:6f327212ef96	521	*/
Kojto	112:6f327212ef96	522
Kojto	112:6f327212ef96	523	typedef struct
Kojto	112:6f327212ef96	524	{
Kojto	112:6f327212ef96	525	__IO uint32_t CR1; /!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 /
Kojto	112:6f327212ef96	526	__IO uint32_t CR2; /!< SPI Control register 2, Address offset: 0x04 /
Kojto	112:6f327212ef96	527	__IO uint32_t SR; /!< SPI Status register, Address offset: 0x08 /
Kojto	112:6f327212ef96	528	__IO uint32_t DR; /!< SPI data register, Address offset: 0x0C /
Kojto	112:6f327212ef96	529	__IO uint32_t CRCPR; /!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 /
Kojto	112:6f327212ef96	530	__IO uint32_t RXCRCR; /!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 /
Kojto	112:6f327212ef96	531	__IO uint32_t TXCRCR; /!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 /
Kojto	112:6f327212ef96	532	__IO uint32_t I2SCFGR; /!< SPI_I2S configuration register, Address offset: 0x1C /
Kojto	112:6f327212ef96	533	__IO uint32_t I2SPR; /!< SPI_I2S prescaler register, Address offset: 0x20 /
Kojto	112:6f327212ef96	534	} SPI_TypeDef;
Kojto	112:6f327212ef96	535
Kojto	112:6f327212ef96	536	/**
Kojto	112:6f327212ef96	537	* @brief TIM
Kojto	112:6f327212ef96	538	*/
Kojto	112:6f327212ef96	539	typedef struct
Kojto	112:6f327212ef96	540	{
Kojto	112:6f327212ef96	541	__IO uint32_t CR1; /!< TIM control register 1, Address offset: 0x00 /
Kojto	112:6f327212ef96	542	__IO uint32_t CR2; /!< TIM control register 2, Address offset: 0x04 /
Kojto	112:6f327212ef96	543	__IO uint32_t SMCR; /!< TIM slave Mode Control register, Address offset: 0x08 /
Kojto	112:6f327212ef96	544	__IO uint32_t DIER; /!< TIM DMA/interrupt enable register, Address offset: 0x0C /
Kojto	112:6f327212ef96	545	__IO uint32_t SR; /!< TIM status register, Address offset: 0x10 /
Kojto	112:6f327212ef96	546	__IO uint32_t EGR; /!< TIM event generation register, Address offset: 0x14 /
Kojto	112:6f327212ef96	547	__IO uint32_t CCMR1; /!< TIM capture/compare mode register 1, Address offset: 0x18 /
Kojto	112:6f327212ef96	548	__IO uint32_t CCMR2; /!< TIM capture/compare mode register 2, Address offset: 0x1C /
Kojto	112:6f327212ef96	549	__IO uint32_t CCER; /!< TIM capture/compare enable register, Address offset: 0x20 /
Kojto	112:6f327212ef96	550	__IO uint32_t CNT; /!< TIM counter register, Address offset: 0x24 /
Kojto	112:6f327212ef96	551	__IO uint32_t PSC; /!< TIM prescaler register, Address offset: 0x28 /
Kojto	112:6f327212ef96	552	__IO uint32_t ARR; /!< TIM auto-reload register, Address offset: 0x2C /
Kojto	112:6f327212ef96	553	uint32_t RESERVED12; /!< Reserved, 0x30 /
Kojto	112:6f327212ef96	554	__IO uint32_t CCR1; /!< TIM capture/compare register 1, Address offset: 0x34 /
Kojto	112:6f327212ef96	555	__IO uint32_t CCR2; /!< TIM capture/compare register 2, Address offset: 0x38 /
Kojto	112:6f327212ef96	556	__IO uint32_t CCR3; /!< TIM capture/compare register 3, Address offset: 0x3C /
Kojto	112:6f327212ef96	557	__IO uint32_t CCR4; /!< TIM capture/compare register 4, Address offset: 0x40 /
Kojto	112:6f327212ef96	558	uint32_t RESERVED17; /!< Reserved, 0x44 /
Kojto	112:6f327212ef96	559	__IO uint32_t DCR; /!< TIM DMA control register, Address offset: 0x48 /
Kojto	112:6f327212ef96	560	__IO uint32_t DMAR; /!< TIM DMA address for full transfer, Address offset: 0x4C /
Kojto	112:6f327212ef96	561	__IO uint32_t OR; /!< TIM option register, Address offset: 0x50 /
Kojto	112:6f327212ef96	562	} TIM_TypeDef;
Kojto	112:6f327212ef96	563	/**
Kojto	112:6f327212ef96	564	* @brief Universal Synchronous Asynchronous Receiver Transmitter
Kojto	112:6f327212ef96	565	*/
Kojto	112:6f327212ef96	566
Kojto	112:6f327212ef96	567	typedef struct
Kojto	112:6f327212ef96	568	{
Kojto	112:6f327212ef96	569	__IO uint32_t SR; /!< USART Status register, Address offset: 0x00 /
Kojto	112:6f327212ef96	570	__IO uint32_t DR; /!< USART Data register, Address offset: 0x04 /
Kojto	112:6f327212ef96	571	__IO uint32_t BRR; /!< USART Baud rate register, Address offset: 0x08 /
Kojto	112:6f327212ef96	572	__IO uint32_t CR1; /!< USART Control register 1, Address offset: 0x0C /
Kojto	112:6f327212ef96	573	__IO uint32_t CR2; /!< USART Control register 2, Address offset: 0x10 /
Kojto	112:6f327212ef96	574	__IO uint32_t CR3; /!< USART Control register 3, Address offset: 0x14 /
Kojto	112:6f327212ef96	575	__IO uint32_t GTPR; /!< USART Guard time and prescaler register, Address offset: 0x18 /
Kojto	112:6f327212ef96	576	} USART_TypeDef;
Kojto	112:6f327212ef96	577
Kojto	112:6f327212ef96	578	/**
Kojto	112:6f327212ef96	579	* @brief Universal Serial Bus Full Speed Device
Kojto	112:6f327212ef96	580	*/
Kojto	112:6f327212ef96	581
Kojto	112:6f327212ef96	582	typedef struct
Kojto	112:6f327212ef96	583	{
Kojto	112:6f327212ef96	584	__IO uint16_t EP0R; /!< USB Endpoint 0 register, Address offset: 0x00 /
Kojto	112:6f327212ef96	585	__IO uint16_t RESERVED0; /!< Reserved /
Kojto	112:6f327212ef96	586	__IO uint16_t EP1R; /!< USB Endpoint 1 register, Address offset: 0x04 /
Kojto	112:6f327212ef96	587	__IO uint16_t RESERVED1; /!< Reserved /
Kojto	112:6f327212ef96	588	__IO uint16_t EP2R; /!< USB Endpoint 2 register, Address offset: 0x08 /
Kojto	112:6f327212ef96	589	__IO uint16_t RESERVED2; /!< Reserved /
Kojto	112:6f327212ef96	590	__IO uint16_t EP3R; /!< USB Endpoint 3 register, Address offset: 0x0C /
Kojto	112:6f327212ef96	591	__IO uint16_t RESERVED3; /!< Reserved /
Kojto	112:6f327212ef96	592	__IO uint16_t EP4R; /!< USB Endpoint 4 register, Address offset: 0x10 /
Kojto	112:6f327212ef96	593	__IO uint16_t RESERVED4; /!< Reserved /
Kojto	112:6f327212ef96	594	__IO uint16_t EP5R; /!< USB Endpoint 5 register, Address offset: 0x14 /
Kojto	112:6f327212ef96	595	__IO uint16_t RESERVED5; /!< Reserved /
Kojto	112:6f327212ef96	596	__IO uint16_t EP6R; /!< USB Endpoint 6 register, Address offset: 0x18 /
Kojto	112:6f327212ef96	597	__IO uint16_t RESERVED6; /!< Reserved /
Kojto	112:6f327212ef96	598	__IO uint16_t EP7R; /!< USB Endpoint 7 register, Address offset: 0x1C /
Kojto	112:6f327212ef96	599	__IO uint16_t RESERVED7[17]; /!< Reserved /
Kojto	112:6f327212ef96	600	__IO uint16_t CNTR; /!< Control register, Address offset: 0x40 /
Kojto	112:6f327212ef96	601	__IO uint16_t RESERVED8; /!< Reserved /
Kojto	112:6f327212ef96	602	__IO uint16_t ISTR; /!< Interrupt status register, Address offset: 0x44 /
Kojto	112:6f327212ef96	603	__IO uint16_t RESERVED9; /!< Reserved /
Kojto	112:6f327212ef96	604	__IO uint16_t FNR; /!< Frame number register, Address offset: 0x48 /
Kojto	112:6f327212ef96	605	__IO uint16_t RESERVEDA; /!< Reserved /
Kojto	112:6f327212ef96	606	__IO uint16_t DADDR; /!< Device address register, Address offset: 0x4C /
Kojto	112:6f327212ef96	607	__IO uint16_t RESERVEDB; /!< Reserved /
Kojto	112:6f327212ef96	608	__IO uint16_t BTABLE; /!< Buffer Table address register, Address offset: 0x50 /
Kojto	112:6f327212ef96	609	__IO uint16_t RESERVEDC; /!< Reserved /
Kojto	112:6f327212ef96	610	} USB_TypeDef;
Kojto	112:6f327212ef96	611
Kojto	112:6f327212ef96	612	/**
Kojto	112:6f327212ef96	613	* @brief Window WATCHDOG
Kojto	112:6f327212ef96	614	*/
Kojto	112:6f327212ef96	615	typedef struct
Kojto	112:6f327212ef96	616	{
Kojto	112:6f327212ef96	617	__IO uint32_t CR; /!< WWDG Control register, Address offset: 0x00 /
Kojto	112:6f327212ef96	618	__IO uint32_t CFR; /!< WWDG Configuration register, Address offset: 0x04 /
Kojto	112:6f327212ef96	619	__IO uint32_t SR; /!< WWDG Status register, Address offset: 0x08 /
Kojto	112:6f327212ef96	620	} WWDG_TypeDef;
Kojto	112:6f327212ef96	621
Kojto	112:6f327212ef96	622	/**
Kojto	112:6f327212ef96	623	* @brief Universal Serial Bus Full Speed Device
Kojto	112:6f327212ef96	624	*/
Kojto	112:6f327212ef96	625	/**
Kojto	112:6f327212ef96	626	* @}
Kojto	112:6f327212ef96	627	*/
Kojto	112:6f327212ef96	628
Kojto	112:6f327212ef96	629	/** @addtogroup Peripheral_memory_map
Kojto	112:6f327212ef96	630	* @{
Kojto	112:6f327212ef96	631	*/
Kojto	112:6f327212ef96	632
Kojto	112:6f327212ef96	633	#define FLASH_BASE ((uint32_t)0x08000000) /!< FLASH base address in the alias region /
Kojto	112:6f327212ef96	634	#define FLASH_EEPROM_BASE ((uint32_t)(FLASH_BASE + 0x80000)) /!< FLASH EEPROM base address in the alias region /
Kojto	112:6f327212ef96	635	#define SRAM_BASE ((uint32_t)0x20000000) /!< SRAM base address in the alias region /
Kojto	112:6f327212ef96	636	#define PERIPH_BASE ((uint32_t)0x40000000) /!< Peripheral base address in the alias region /
Kojto	112:6f327212ef96	637	#define SRAM_BB_BASE ((uint32_t)0x22000000) /!< SRAM base address in the bit-band region /
Kojto	112:6f327212ef96	638	#define PERIPH_BB_BASE ((uint32_t)0x42000000) /!< Peripheral base address in the bit-band region /
Kojto	112:6f327212ef96	639	#define FLASH_END ((uint32_t)0x0803FFFF) /!< Program end FLASH address for Cat3 /
Kojto	112:6f327212ef96	640	#define FLASH_EEPROM_END ((uint32_t)0x08081FFF) /!< FLASH EEPROM end address (8KB) /
Kojto	112:6f327212ef96	641
Kojto	112:6f327212ef96	642	/!< Peripheral memory map /
Kojto	112:6f327212ef96	643	#define APB1PERIPH_BASE PERIPH_BASE
Kojto	112:6f327212ef96	644	#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
Kojto	112:6f327212ef96	645	#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000)
Kojto	112:6f327212ef96	646
Kojto	112:6f327212ef96	647	/!< APB1 peripherals /
Kojto	112:6f327212ef96	648	#define TIM2_BASE (APB1PERIPH_BASE + 0x00000000)
Kojto	112:6f327212ef96	649	#define TIM3_BASE (APB1PERIPH_BASE + 0x00000400)
Kojto	112:6f327212ef96	650	#define TIM4_BASE (APB1PERIPH_BASE + 0x00000800)
Kojto	112:6f327212ef96	651	#define TIM5_BASE (APB1PERIPH_BASE + 0x00000C00)
Kojto	112:6f327212ef96	652	#define TIM6_BASE (APB1PERIPH_BASE + 0x00001000)
Kojto	112:6f327212ef96	653	#define TIM7_BASE (APB1PERIPH_BASE + 0x00001400)
Kojto	112:6f327212ef96	654	#define LCD_BASE (APB1PERIPH_BASE + 0x00002400)
Kojto	112:6f327212ef96	655	#define RTC_BASE (APB1PERIPH_BASE + 0x00002800)
Kojto	112:6f327212ef96	656	#define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00)
Kojto	112:6f327212ef96	657	#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000)
Kojto	112:6f327212ef96	658	#define SPI2_BASE (APB1PERIPH_BASE + 0x00003800)
Kojto	112:6f327212ef96	659	#define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00)
Kojto	112:6f327212ef96	660	#define USART2_BASE (APB1PERIPH_BASE + 0x00004400)
Kojto	112:6f327212ef96	661	#define USART3_BASE (APB1PERIPH_BASE + 0x00004800)
Kojto	112:6f327212ef96	662	#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400)
Kojto	112:6f327212ef96	663	#define I2C2_BASE (APB1PERIPH_BASE + 0x00005800)
Kojto	112:6f327212ef96	664
Kojto	112:6f327212ef96	665	/* USB device FS */
Kojto	112:6f327212ef96	666	#define USB_BASE (APB1PERIPH_BASE + 0x00005C00) /!< USB_IP Peripheral Registers base address /
Kojto	112:6f327212ef96	667	#define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000) /!< USB_IP Packet Memory Area base address /
Kojto	112:6f327212ef96	668
Kojto	112:6f327212ef96	669	/* USB device FS SRAM */
Kojto	112:6f327212ef96	670	#define PWR_BASE (APB1PERIPH_BASE + 0x00007000)
Kojto	112:6f327212ef96	671	#define DAC_BASE (APB1PERIPH_BASE + 0x00007400)
Kojto	112:6f327212ef96	672	#define COMP_BASE (APB1PERIPH_BASE + 0x00007C00)
Kojto	112:6f327212ef96	673	#define RI_BASE (APB1PERIPH_BASE + 0x00007C04)
Kojto	112:6f327212ef96	674	#define OPAMP_BASE (APB1PERIPH_BASE + 0x00007C5C)
Kojto	112:6f327212ef96	675
Kojto	112:6f327212ef96	676	/!< APB2 peripherals /
Kojto	112:6f327212ef96	677	#define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000)
Kojto	112:6f327212ef96	678	#define EXTI_BASE (APB2PERIPH_BASE + 0x00000400)
Kojto	112:6f327212ef96	679	#define TIM9_BASE (APB2PERIPH_BASE + 0x00000800)
Kojto	112:6f327212ef96	680	#define TIM10_BASE (APB2PERIPH_BASE + 0x00000C00)
Kojto	112:6f327212ef96	681	#define TIM11_BASE (APB2PERIPH_BASE + 0x00001000)
Kojto	112:6f327212ef96	682	#define ADC1_BASE (APB2PERIPH_BASE + 0x00002400)
Kojto	112:6f327212ef96	683	#define ADC_BASE (APB2PERIPH_BASE + 0x00002700)
Kojto	112:6f327212ef96	684	#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000)
Kojto	112:6f327212ef96	685	#define USART1_BASE (APB2PERIPH_BASE + 0x00003800)
Kojto	112:6f327212ef96	686
Kojto	112:6f327212ef96	687	/!< AHB peripherals /
Kojto	112:6f327212ef96	688	#define GPIOA_BASE (AHBPERIPH_BASE + 0x00000000)
Kojto	112:6f327212ef96	689	#define GPIOB_BASE (AHBPERIPH_BASE + 0x00000400)
Kojto	112:6f327212ef96	690	#define GPIOC_BASE (AHBPERIPH_BASE + 0x00000800)
Kojto	112:6f327212ef96	691	#define GPIOD_BASE (AHBPERIPH_BASE + 0x00000C00)
Kojto	112:6f327212ef96	692	#define GPIOE_BASE (AHBPERIPH_BASE + 0x00001000)
Kojto	112:6f327212ef96	693	#define GPIOH_BASE (AHBPERIPH_BASE + 0x00001400)
Kojto	112:6f327212ef96	694	#define CRC_BASE (AHBPERIPH_BASE + 0x00003000)
Kojto	112:6f327212ef96	695	#define RCC_BASE (AHBPERIPH_BASE + 0x00003800)
Kojto	112:6f327212ef96	696	#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00003C00) /!< FLASH registers base address /
Kojto	112:6f327212ef96	697	#define OB_BASE ((uint32_t)0x1FF80000) /!< FLASH Option Bytes base address /
Kojto	112:6f327212ef96	698	#define DMA1_BASE (AHBPERIPH_BASE + 0x00006000)
Kojto	112:6f327212ef96	699	#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008)
Kojto	112:6f327212ef96	700	#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C)
Kojto	112:6f327212ef96	701	#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030)
Kojto	112:6f327212ef96	702	#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044)
Kojto	112:6f327212ef96	703	#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058)
Kojto	112:6f327212ef96	704	#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006C)
Kojto	112:6f327212ef96	705	#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080)
Kojto	112:6f327212ef96	706	#define DMA2_BASE (AHBPERIPH_BASE + 0x00006400)
Kojto	112:6f327212ef96	707	#define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008)
Kojto	112:6f327212ef96	708	#define DMA2_Channel2_BASE (DMA2_BASE + 0x0000001C)
Kojto	112:6f327212ef96	709	#define DMA2_Channel3_BASE (DMA2_BASE + 0x00000030)
Kojto	112:6f327212ef96	710	#define DMA2_Channel4_BASE (DMA2_BASE + 0x00000044)
Kojto	112:6f327212ef96	711	#define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058)
Kojto	112:6f327212ef96	712	#define DBGMCU_BASE ((uint32_t)0xE0042000) /!< Debug MCU registers base address /
Kojto	112:6f327212ef96	713
Kojto	112:6f327212ef96	714	/**
Kojto	112:6f327212ef96	715	* @}
Kojto	112:6f327212ef96	716	*/
Kojto	112:6f327212ef96	717
Kojto	112:6f327212ef96	718	/** @addtogroup Peripheral_declaration
Kojto	112:6f327212ef96	719	* @{
Kojto	112:6f327212ef96	720	*/
Kojto	112:6f327212ef96	721
Kojto	112:6f327212ef96	722	#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
Kojto	112:6f327212ef96	723	#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
Kojto	112:6f327212ef96	724	#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
Kojto	112:6f327212ef96	725	#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
Kojto	112:6f327212ef96	726	#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
Kojto	112:6f327212ef96	727	#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
Kojto	112:6f327212ef96	728	#define LCD ((LCD_TypeDef *) LCD_BASE)
Kojto	112:6f327212ef96	729	#define RTC ((RTC_TypeDef *) RTC_BASE)
Kojto	112:6f327212ef96	730	#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
Kojto	112:6f327212ef96	731	#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
Kojto	112:6f327212ef96	732	#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
Kojto	112:6f327212ef96	733	#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
Kojto	112:6f327212ef96	734	#define USART2 ((USART_TypeDef *) USART2_BASE)
Kojto	112:6f327212ef96	735	#define USART3 ((USART_TypeDef *) USART3_BASE)
Kojto	112:6f327212ef96	736	#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
Kojto	112:6f327212ef96	737	#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
Kojto	112:6f327212ef96	738	/* USB device FS */
Kojto	112:6f327212ef96	739	#define USB ((USB_TypeDef *) USB_BASE)
Kojto	112:6f327212ef96	740	/* USB device FS SRAM */
Kojto	112:6f327212ef96	741	#define PWR ((PWR_TypeDef *) PWR_BASE)
Kojto	112:6f327212ef96	742	#define DAC ((DAC_TypeDef *) DAC_BASE)
Kojto	112:6f327212ef96	743	#define COMP ((COMP_TypeDef *) COMP_BASE)
Kojto	112:6f327212ef96	744	#define COMP1 ((COMP_TypeDef *) COMP_BASE)
Kojto	112:6f327212ef96	745	#define COMP2 ((COMP_TypeDef *) (COMP_BASE + 0x00000001))
Kojto	112:6f327212ef96	746	#define RI ((RI_TypeDef *) RI_BASE)
Kojto	112:6f327212ef96	747	#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
Kojto	112:6f327212ef96	748	#define OPAMP1 ((OPAMP_TypeDef *) OPAMP_BASE)
Kojto	112:6f327212ef96	749	#define OPAMP2 ((OPAMP_TypeDef *) (OPAMP_BASE + 0x00000001))
Kojto	112:6f327212ef96	750	#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
Kojto	112:6f327212ef96	751	#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
Kojto	112:6f327212ef96	752	#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
Kojto	112:6f327212ef96	753	#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
Kojto	112:6f327212ef96	754	#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
Kojto	112:6f327212ef96	755	#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
Kojto	112:6f327212ef96	756	#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
Kojto	112:6f327212ef96	757	#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
Kojto	112:6f327212ef96	758	#define USART1 ((USART_TypeDef *) USART1_BASE)
Kojto	112:6f327212ef96	759	#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
Kojto	112:6f327212ef96	760	#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
Kojto	112:6f327212ef96	761	#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
Kojto	112:6f327212ef96	762	#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
Kojto	112:6f327212ef96	763	#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
Kojto	112:6f327212ef96	764	#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
Kojto	112:6f327212ef96	765	#define CRC ((CRC_TypeDef *) CRC_BASE)
Kojto	112:6f327212ef96	766	#define RCC ((RCC_TypeDef *) RCC_BASE)
Kojto	112:6f327212ef96	767	#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
Kojto	112:6f327212ef96	768	#define OB ((OB_TypeDef *) OB_BASE)
Kojto	112:6f327212ef96	769	#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
Kojto	112:6f327212ef96	770	#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
Kojto	112:6f327212ef96	771	#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
Kojto	112:6f327212ef96	772	#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
Kojto	112:6f327212ef96	773	#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
Kojto	112:6f327212ef96	774	#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
Kojto	112:6f327212ef96	775	#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
Kojto	112:6f327212ef96	776	#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
Kojto	112:6f327212ef96	777	#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
Kojto	112:6f327212ef96	778	#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
Kojto	112:6f327212ef96	779	#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
Kojto	112:6f327212ef96	780	#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
Kojto	112:6f327212ef96	781	#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
Kojto	112:6f327212ef96	782	#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
Kojto	112:6f327212ef96	783	#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
Kojto	112:6f327212ef96	784
Kojto	112:6f327212ef96	785	/**
Kojto	112:6f327212ef96	786	* @}
Kojto	112:6f327212ef96	787	*/
Kojto	112:6f327212ef96	788
Kojto	112:6f327212ef96	789	/** @addtogroup Exported_constants
Kojto	112:6f327212ef96	790	* @{
Kojto	112:6f327212ef96	791	*/
Kojto	112:6f327212ef96	792
Kojto	112:6f327212ef96	793	/** @addtogroup Peripheral_Registers_Bits_Definition
Kojto	112:6f327212ef96	794	* @{
Kojto	112:6f327212ef96	795	*/
Kojto	112:6f327212ef96	796
Kojto	112:6f327212ef96	797	/******************************************************************************/
Kojto	112:6f327212ef96	798	/* Peripheral Registers Bits Definition */
Kojto	112:6f327212ef96	799	/******************************************************************************/
Kojto	112:6f327212ef96	800	/******************************************************************************/
Kojto	112:6f327212ef96	801	/* */
Kojto	112:6f327212ef96	802	/* Analog to Digital Converter (ADC) */
Kojto	112:6f327212ef96	803	/* */
Kojto	112:6f327212ef96	804	/******************************************************************************/
Kojto	112:6f327212ef96	805
Kojto	112:6f327212ef96	806	/****************** Bit definition for ADC_SR register ******************/
Kojto	112:6f327212ef96	807	#define ADC_SR_AWD ((uint32_t)0x00000001) /!< Analog watchdog flag /
Kojto	112:6f327212ef96	808	#define ADC_SR_EOC ((uint32_t)0x00000002) /!< End of conversion /
Kojto	112:6f327212ef96	809	#define ADC_SR_JEOC ((uint32_t)0x00000004) /!< Injected channel end of conversion /
Kojto	112:6f327212ef96	810	#define ADC_SR_JSTRT ((uint32_t)0x00000008) /!< Injected channel Start flag /
Kojto	112:6f327212ef96	811	#define ADC_SR_STRT ((uint32_t)0x00000010) /!< Regular channel Start flag /
Kojto	112:6f327212ef96	812	#define ADC_SR_OVR ((uint32_t)0x00000020) /!< Overrun flag /
Kojto	112:6f327212ef96	813	#define ADC_SR_ADONS ((uint32_t)0x00000040) /!< ADC ON status /
Kojto	112:6f327212ef96	814	#define ADC_SR_RCNR ((uint32_t)0x00000100) /!< Regular channel not ready flag /
Kojto	112:6f327212ef96	815	#define ADC_SR_JCNR ((uint32_t)0x00000200) /!< Injected channel not ready flag /
Kojto	112:6f327212ef96	816
Kojto	112:6f327212ef96	817	/***************** Bit definition for ADC_CR1 register ******************/
Kojto	112:6f327212ef96	818	#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /!< AWDCH[4:0] bits (Analog watchdog channel select bits) /
Kojto	112:6f327212ef96	819	#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /!< Bit 0 /
Kojto	112:6f327212ef96	820	#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /!< Bit 1 /
Kojto	112:6f327212ef96	821	#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /!< Bit 2 /
Kojto	112:6f327212ef96	822	#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /!< Bit 3 /
Kojto	112:6f327212ef96	823	#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /!< Bit 4 /
Kojto	112:6f327212ef96	824
Kojto	112:6f327212ef96	825	#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /!< Interrupt enable for EOC /
Kojto	112:6f327212ef96	826	#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /!< Analog Watchdog interrupt enable /
Kojto	112:6f327212ef96	827	#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /!< Interrupt enable for injected channels /
Kojto	112:6f327212ef96	828	#define ADC_CR1_SCAN ((uint32_t)0x00000100) /!< Scan mode /
Kojto	112:6f327212ef96	829	#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /!< Enable the watchdog on a single channel in scan mode /
Kojto	112:6f327212ef96	830	#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /!< Automatic injected group conversion /
Kojto	112:6f327212ef96	831	#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /!< Discontinuous mode on regular channels /
Kojto	112:6f327212ef96	832	#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /!< Discontinuous mode on injected channels /
Kojto	112:6f327212ef96	833
Kojto	112:6f327212ef96	834	#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /!< DISCNUM[2:0] bits (Discontinuous mode channel count) /
Kojto	112:6f327212ef96	835	#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /!< Bit 0 /
Kojto	112:6f327212ef96	836	#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /!< Bit 1 /
Kojto	112:6f327212ef96	837	#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /!< Bit 2 /
Kojto	112:6f327212ef96	838
Kojto	112:6f327212ef96	839	#define ADC_CR1_PDD ((uint32_t)0x00010000) /!< Power Down during Delay phase /
Kojto	112:6f327212ef96	840	#define ADC_CR1_PDI ((uint32_t)0x00020000) /!< Power Down during Idle phase /
Kojto	112:6f327212ef96	841
Kojto	112:6f327212ef96	842	#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /!< Analog watchdog enable on injected channels /
Kojto	112:6f327212ef96	843	#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /!< Analog watchdog enable on regular channels /
Kojto	112:6f327212ef96	844
Kojto	112:6f327212ef96	845	#define ADC_CR1_RES ((uint32_t)0x03000000) /!< RES[1:0] bits (Resolution) /
Kojto	112:6f327212ef96	846	#define ADC_CR1_RES_0 ((uint32_t)0x01000000) /!< Bit 0 /
Kojto	112:6f327212ef96	847	#define ADC_CR1_RES_1 ((uint32_t)0x02000000) /!< Bit 1 /
Kojto	112:6f327212ef96	848
Kojto	112:6f327212ef96	849	#define ADC_CR1_OVRIE ((uint32_t)0x04000000) /!< Overrun interrupt enable /
Kojto	112:6f327212ef96	850
Kojto	112:6f327212ef96	851	/***************** Bit definition for ADC_CR2 register ******************/
Kojto	112:6f327212ef96	852	#define ADC_CR2_ADON ((uint32_t)0x00000001) /!< A/D Converter ON / OFF /
Kojto	112:6f327212ef96	853	#define ADC_CR2_CONT ((uint32_t)0x00000002) /!< Continuous Conversion /
Kojto	112:6f327212ef96	854	#define ADC_CR2_CFG ((uint32_t)0x00000004) /!< ADC Configuration /
Kojto	112:6f327212ef96	855
Kojto	112:6f327212ef96	856	#define ADC_CR2_DELS ((uint32_t)0x00000070) /!< DELS[2:0] bits (Delay selection) /
Kojto	112:6f327212ef96	857	#define ADC_CR2_DELS_0 ((uint32_t)0x00000010) /!< Bit 0 /
Kojto	112:6f327212ef96	858	#define ADC_CR2_DELS_1 ((uint32_t)0x00000020) /!< Bit 1 /
Kojto	112:6f327212ef96	859	#define ADC_CR2_DELS_2 ((uint32_t)0x00000040) /!< Bit 2 /
Kojto	112:6f327212ef96	860
Kojto	112:6f327212ef96	861	#define ADC_CR2_DMA ((uint32_t)0x00000100) /!< Direct Memory access mode /
Kojto	112:6f327212ef96	862	#define ADC_CR2_DDS ((uint32_t)0x00000200) /!< DMA disable selection (Single ADC) /
Kojto	112:6f327212ef96	863	#define ADC_CR2_EOCS ((uint32_t)0x00000400) /!< End of conversion selection /
Kojto	112:6f327212ef96	864	#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /!< Data Alignment /
Kojto	112:6f327212ef96	865
Kojto	112:6f327212ef96	866	#define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /!< JEXTSEL[3:0] bits (External event select for injected group) /
Kojto	112:6f327212ef96	867	#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /!< Bit 0 /
Kojto	112:6f327212ef96	868	#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /!< Bit 1 /
Kojto	112:6f327212ef96	869	#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /!< Bit 2 /
Kojto	112:6f327212ef96	870	#define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /!< Bit 3 /
Kojto	112:6f327212ef96	871
Kojto	112:6f327212ef96	872	#define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /!< JEXTEN[1:0] bits (External Trigger Conversion mode for injected channels) /
Kojto	112:6f327212ef96	873	#define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /!< Bit 0 /
Kojto	112:6f327212ef96	874	#define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /!< Bit 1 /
Kojto	112:6f327212ef96	875
Kojto	112:6f327212ef96	876	#define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /!< Start Conversion of injected channels /
Kojto	112:6f327212ef96	877
Kojto	112:6f327212ef96	878	#define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /!< EXTSEL[3:0] bits (External Event Select for regular group) /
Kojto	112:6f327212ef96	879	#define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /!< Bit 0 /
Kojto	112:6f327212ef96	880	#define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /!< Bit 1 /
Kojto	112:6f327212ef96	881	#define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /!< Bit 2 /
Kojto	112:6f327212ef96	882	#define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /!< Bit 3 /
Kojto	112:6f327212ef96	883
Kojto	112:6f327212ef96	884	#define ADC_CR2_EXTEN ((uint32_t)0x30000000) /!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) /
Kojto	112:6f327212ef96	885	#define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /!< Bit 0 /
Kojto	112:6f327212ef96	886	#define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /!< Bit 1 /
Kojto	112:6f327212ef96	887
Kojto	112:6f327212ef96	888	#define ADC_CR2_SWSTART ((uint32_t)0x40000000) /!< Start Conversion of regular channels /
Kojto	112:6f327212ef96	889
Kojto	112:6f327212ef96	890	/**************** Bit definition for ADC_SMPR1 register *****************/
Kojto	112:6f327212ef96	891	#define ADC_SMPR1_SMP20 ((uint32_t)0x00000007) /!< SMP20[2:0] bits (Channel 20 Sample time selection) /
Kojto	112:6f327212ef96	892	#define ADC_SMPR1_SMP20_0 ((uint32_t)0x00000001) /!< Bit 0 /
Kojto	112:6f327212ef96	893	#define ADC_SMPR1_SMP20_1 ((uint32_t)0x00000002) /!< Bit 1 /
Kojto	112:6f327212ef96	894	#define ADC_SMPR1_SMP20_2 ((uint32_t)0x00000004) /!< Bit 2 /
Kojto	112:6f327212ef96	895
Kojto	112:6f327212ef96	896	#define ADC_SMPR1_SMP21 ((uint32_t)0x00000038) /!< SMP21[2:0] bits (Channel 21 Sample time selection) /
Kojto	112:6f327212ef96	897	#define ADC_SMPR1_SMP21_0 ((uint32_t)0x00000008) /!< Bit 0 /
Kojto	112:6f327212ef96	898	#define ADC_SMPR1_SMP21_1 ((uint32_t)0x00000010) /!< Bit 1 /
Kojto	112:6f327212ef96	899	#define ADC_SMPR1_SMP21_2 ((uint32_t)0x00000020) /!< Bit 2 /
Kojto	112:6f327212ef96	900
Kojto	112:6f327212ef96	901	#define ADC_SMPR1_SMP22 ((uint32_t)0x000001C0) /!< SMP22[2:0] bits (Channel 22 Sample time selection) /
Kojto	112:6f327212ef96	902	#define ADC_SMPR1_SMP22_0 ((uint32_t)0x00000040) /!< Bit 0 /
Kojto	112:6f327212ef96	903	#define ADC_SMPR1_SMP22_1 ((uint32_t)0x00000080) /!< Bit 1 /
Kojto	112:6f327212ef96	904	#define ADC_SMPR1_SMP22_2 ((uint32_t)0x00000100) /!< Bit 2 /
Kojto	112:6f327212ef96	905
Kojto	112:6f327212ef96	906	#define ADC_SMPR1_SMP23 ((uint32_t)0x00000E00) /!< SMP23[2:0] bits (Channel 23 Sample time selection) /
Kojto	112:6f327212ef96	907	#define ADC_SMPR1_SMP23_0 ((uint32_t)0x00000200) /!< Bit 0 /
Kojto	112:6f327212ef96	908	#define ADC_SMPR1_SMP23_1 ((uint32_t)0x00000400) /!< Bit 1 /
Kojto	112:6f327212ef96	909	#define ADC_SMPR1_SMP23_2 ((uint32_t)0x00000800) /!< Bit 2 /
Kojto	112:6f327212ef96	910
Kojto	112:6f327212ef96	911	#define ADC_SMPR1_SMP24 ((uint32_t)0x00007000) /!< SMP24[2:0] bits (Channel 24 Sample time selection) /
Kojto	112:6f327212ef96	912	#define ADC_SMPR1_SMP24_0 ((uint32_t)0x00001000) /!< Bit 0 /
Kojto	112:6f327212ef96	913	#define ADC_SMPR1_SMP24_1 ((uint32_t)0x00002000) /!< Bit 1 /
Kojto	112:6f327212ef96	914	#define ADC_SMPR1_SMP24_2 ((uint32_t)0x00004000) /!< Bit 2 /
Kojto	112:6f327212ef96	915
Kojto	112:6f327212ef96	916	#define ADC_SMPR1_SMP25 ((uint32_t)0x00038000) /!< SMP25[2:0] bits (Channel 25 Sample time selection) /
Kojto	112:6f327212ef96	917	#define ADC_SMPR1_SMP25_0 ((uint32_t)0x00008000) /!< Bit 0 /
Kojto	112:6f327212ef96	918	#define ADC_SMPR1_SMP25_1 ((uint32_t)0x00010000) /!< Bit 1 /
Kojto	112:6f327212ef96	919	#define ADC_SMPR1_SMP25_2 ((uint32_t)0x00020000) /!< Bit 2 /
Kojto	112:6f327212ef96	920
Kojto	112:6f327212ef96	921	#define ADC_SMPR1_SMP26 ((uint32_t)0x001C0000) /!< SMP26[2:0] bits (Channel 26 Sample time selection) /
Kojto	112:6f327212ef96	922	#define ADC_SMPR1_SMP26_0 ((uint32_t)0x00040000) /!< Bit 0 /
Kojto	112:6f327212ef96	923	#define ADC_SMPR1_SMP26_1 ((uint32_t)0x00080000) /!< Bit 1 /
Kojto	112:6f327212ef96	924	#define ADC_SMPR1_SMP26_2 ((uint32_t)0x00100000) /!< Bit 2 /
Kojto	112:6f327212ef96	925
Kojto	112:6f327212ef96	926	#define ADC_SMPR1_SMP27 ((uint32_t)0x00E00000) /!< SMP27[2:0] bits (Channel 27 Sample time selection) /
Kojto	112:6f327212ef96	927	#define ADC_SMPR1_SMP27_0 ((uint32_t)0x00200000) /!< Bit 0 /
Kojto	112:6f327212ef96	928	#define ADC_SMPR1_SMP27_1 ((uint32_t)0x00400000) /!< Bit 1 /
Kojto	112:6f327212ef96	929	#define ADC_SMPR1_SMP27_2 ((uint32_t)0x00800000) /!< Bit 2 /
Kojto	112:6f327212ef96	930
Kojto	112:6f327212ef96	931	#define ADC_SMPR1_SMP28 ((uint32_t)0x07000000) /!< SMP28[2:0] bits (Channel 28 Sample time selection) /
Kojto	112:6f327212ef96	932	#define ADC_SMPR1_SMP28_0 ((uint32_t)0x01000000) /!< Bit 0 /
Kojto	112:6f327212ef96	933	#define ADC_SMPR1_SMP28_1 ((uint32_t)0x02000000) /!< Bit 1 /
Kojto	112:6f327212ef96	934	#define ADC_SMPR1_SMP28_2 ((uint32_t)0x04000000) /!< Bit 2 /
Kojto	112:6f327212ef96	935
Kojto	112:6f327212ef96	936	#define ADC_SMPR1_SMP29 ((uint32_t)0x38000000) /!< SMP29[2:0] bits (Channel 29 Sample time selection) /
Kojto	112:6f327212ef96	937	#define ADC_SMPR1_SMP29_0 ((uint32_t)0x08000000) /!< Bit 0 /
Kojto	112:6f327212ef96	938	#define ADC_SMPR1_SMP29_1 ((uint32_t)0x10000000) /!< Bit 1 /
Kojto	112:6f327212ef96	939	#define ADC_SMPR1_SMP29_2 ((uint32_t)0x20000000) /!< Bit 2 /
Kojto	112:6f327212ef96	940
Kojto	112:6f327212ef96	941	/**************** Bit definition for ADC_SMPR2 register *****************/
Kojto	112:6f327212ef96	942	#define ADC_SMPR2_SMP10 ((uint32_t)0x00000007) /!< SMP10[2:0] bits (Channel 10 Sample time selection) /
Kojto	112:6f327212ef96	943	#define ADC_SMPR2_SMP10_0 ((uint32_t)0x00000001) /!< Bit 0 /
Kojto	112:6f327212ef96	944	#define ADC_SMPR2_SMP10_1 ((uint32_t)0x00000002) /!< Bit 1 /
Kojto	112:6f327212ef96	945	#define ADC_SMPR2_SMP10_2 ((uint32_t)0x00000004) /!< Bit 2 /
Kojto	112:6f327212ef96	946
Kojto	112:6f327212ef96	947	#define ADC_SMPR2_SMP11 ((uint32_t)0x00000038) /!< SMP11[2:0] bits (Channel 11 Sample time selection) /
Kojto	112:6f327212ef96	948	#define ADC_SMPR2_SMP11_0 ((uint32_t)0x00000008) /!< Bit 0 /
Kojto	112:6f327212ef96	949	#define ADC_SMPR2_SMP11_1 ((uint32_t)0x00000010) /!< Bit 1 /
Kojto	112:6f327212ef96	950	#define ADC_SMPR2_SMP11_2 ((uint32_t)0x00000020) /!< Bit 2 /
Kojto	112:6f327212ef96	951
Kojto	112:6f327212ef96	952	#define ADC_SMPR2_SMP12 ((uint32_t)0x000001C0) /!< SMP12[2:0] bits (Channel 12 Sample time selection) /
Kojto	112:6f327212ef96	953	#define ADC_SMPR2_SMP12_0 ((uint32_t)0x00000040) /!< Bit 0 /
Kojto	112:6f327212ef96	954	#define ADC_SMPR2_SMP12_1 ((uint32_t)0x00000080) /!< Bit 1 /
Kojto	112:6f327212ef96	955	#define ADC_SMPR2_SMP12_2 ((uint32_t)0x00000100) /!< Bit 2 /
Kojto	112:6f327212ef96	956
Kojto	112:6f327212ef96	957	#define ADC_SMPR2_SMP13 ((uint32_t)0x00000E00) /!< SMP13[2:0] bits (Channel 13 Sample time selection) /
Kojto	112:6f327212ef96	958	#define ADC_SMPR2_SMP13_0 ((uint32_t)0x00000200) /!< Bit 0 /
Kojto	112:6f327212ef96	959	#define ADC_SMPR2_SMP13_1 ((uint32_t)0x00000400) /!< Bit 1 /
Kojto	112:6f327212ef96	960	#define ADC_SMPR2_SMP13_2 ((uint32_t)0x00000800) /!< Bit 2 /
Kojto	112:6f327212ef96	961
Kojto	112:6f327212ef96	962	#define ADC_SMPR2_SMP14 ((uint32_t)0x00007000) /!< SMP14[2:0] bits (Channel 14 Sample time selection) /
Kojto	112:6f327212ef96	963	#define ADC_SMPR2_SMP14_0 ((uint32_t)0x00001000) /!< Bit 0 /
Kojto	112:6f327212ef96	964	#define ADC_SMPR2_SMP14_1 ((uint32_t)0x00002000) /!< Bit 1 /
Kojto	112:6f327212ef96	965	#define ADC_SMPR2_SMP14_2 ((uint32_t)0x00004000) /!< Bit 2 /
Kojto	112:6f327212ef96	966
Kojto	112:6f327212ef96	967	#define ADC_SMPR2_SMP15 ((uint32_t)0x00038000) /!< SMP15[2:0] bits (Channel 5 Sample time selection) /
Kojto	112:6f327212ef96	968	#define ADC_SMPR2_SMP15_0 ((uint32_t)0x00008000) /!< Bit 0 /
Kojto	112:6f327212ef96	969	#define ADC_SMPR2_SMP15_1 ((uint32_t)0x00010000) /!< Bit 1 /
Kojto	112:6f327212ef96	970	#define ADC_SMPR2_SMP15_2 ((uint32_t)0x00020000) /!< Bit 2 /
Kojto	112:6f327212ef96	971
Kojto	112:6f327212ef96	972	#define ADC_SMPR2_SMP16 ((uint32_t)0x001C0000) /!< SMP16[2:0] bits (Channel 16 Sample time selection) /
Kojto	112:6f327212ef96	973	#define ADC_SMPR2_SMP16_0 ((uint32_t)0x00040000) /!< Bit 0 /
Kojto	112:6f327212ef96	974	#define ADC_SMPR2_SMP16_1 ((uint32_t)0x00080000) /!< Bit 1 /
Kojto	112:6f327212ef96	975	#define ADC_SMPR2_SMP16_2 ((uint32_t)0x00100000) /!< Bit 2 /
Kojto	112:6f327212ef96	976
Kojto	112:6f327212ef96	977	#define ADC_SMPR2_SMP17 ((uint32_t)0x00E00000) /!< SMP17[2:0] bits (Channel 17 Sample time selection) /
Kojto	112:6f327212ef96	978	#define ADC_SMPR2_SMP17_0 ((uint32_t)0x00200000) /!< Bit 0 /
Kojto	112:6f327212ef96	979	#define ADC_SMPR2_SMP17_1 ((uint32_t)0x00400000) /!< Bit 1 /
Kojto	112:6f327212ef96	980	#define ADC_SMPR2_SMP17_2 ((uint32_t)0x00800000) /!< Bit 2 /
Kojto	112:6f327212ef96	981
Kojto	112:6f327212ef96	982	#define ADC_SMPR2_SMP18 ((uint32_t)0x07000000) /!< SMP18[2:0] bits (Channel 18 Sample time selection) /
Kojto	112:6f327212ef96	983	#define ADC_SMPR2_SMP18_0 ((uint32_t)0x01000000) /!< Bit 0 /
Kojto	112:6f327212ef96	984	#define ADC_SMPR2_SMP18_1 ((uint32_t)0x02000000) /!< Bit 1 /
Kojto	112:6f327212ef96	985	#define ADC_SMPR2_SMP18_2 ((uint32_t)0x04000000) /!< Bit 2 /
Kojto	112:6f327212ef96	986
Kojto	112:6f327212ef96	987	#define ADC_SMPR2_SMP19 ((uint32_t)0x38000000) /!< SMP19[2:0] bits (Channel 19 Sample time selection) /
Kojto	112:6f327212ef96	988	#define ADC_SMPR2_SMP19_0 ((uint32_t)0x08000000) /!< Bit 0 /
Kojto	112:6f327212ef96	989	#define ADC_SMPR2_SMP19_1 ((uint32_t)0x10000000) /!< Bit 1 /
Kojto	112:6f327212ef96	990	#define ADC_SMPR2_SMP19_2 ((uint32_t)0x20000000) /!< Bit 2 /
Kojto	112:6f327212ef96	991
Kojto	112:6f327212ef96	992	/**************** Bit definition for ADC_SMPR3 register *****************/
Kojto	112:6f327212ef96	993	#define ADC_SMPR3_SMP0 ((uint32_t)0x00000007) /!< SMP0[2:0] bits (Channel 0 Sample time selection) /
Kojto	112:6f327212ef96	994	#define ADC_SMPR3_SMP0_0 ((uint32_t)0x00000001) /!< Bit 0 /
Kojto	112:6f327212ef96	995	#define ADC_SMPR3_SMP0_1 ((uint32_t)0x00000002) /!< Bit 1 /
Kojto	112:6f327212ef96	996	#define ADC_SMPR3_SMP0_2 ((uint32_t)0x00000004) /!< Bit 2 /
Kojto	112:6f327212ef96	997
Kojto	112:6f327212ef96	998	#define ADC_SMPR3_SMP1 ((uint32_t)0x00000038) /!< SMP1[2:0] bits (Channel 1 Sample time selection) /
Kojto	112:6f327212ef96	999	#define ADC_SMPR3_SMP1_0 ((uint32_t)0x00000008) /!< Bit 0 /
Kojto	112:6f327212ef96	1000	#define ADC_SMPR3_SMP1_1 ((uint32_t)0x00000010) /!< Bit 1 /
Kojto	112:6f327212ef96	1001	#define ADC_SMPR3_SMP1_2 ((uint32_t)0x00000020) /!< Bit 2 /
Kojto	112:6f327212ef96	1002
Kojto	112:6f327212ef96	1003	#define ADC_SMPR3_SMP2 ((uint32_t)0x000001C0) /!< SMP2[2:0] bits (Channel 2 Sample time selection) /
Kojto	112:6f327212ef96	1004	#define ADC_SMPR3_SMP2_0 ((uint32_t)0x00000040) /!< Bit 0 /
Kojto	112:6f327212ef96	1005	#define ADC_SMPR3_SMP2_1 ((uint32_t)0x00000080) /!< Bit 1 /
Kojto	112:6f327212ef96	1006	#define ADC_SMPR3_SMP2_2 ((uint32_t)0x00000100) /!< Bit 2 /
Kojto	112:6f327212ef96	1007
Kojto	112:6f327212ef96	1008	#define ADC_SMPR3_SMP3 ((uint32_t)0x00000E00) /!< SMP3[2:0] bits (Channel 3 Sample time selection) /
Kojto	112:6f327212ef96	1009	#define ADC_SMPR3_SMP3_0 ((uint32_t)0x00000200) /!< Bit 0 /
Kojto	112:6f327212ef96	1010	#define ADC_SMPR3_SMP3_1 ((uint32_t)0x00000400) /!< Bit 1 /
Kojto	112:6f327212ef96	1011	#define ADC_SMPR3_SMP3_2 ((uint32_t)0x00000800) /!< Bit 2 /
Kojto	112:6f327212ef96	1012
Kojto	112:6f327212ef96	1013	#define ADC_SMPR3_SMP4 ((uint32_t)0x00007000) /!< SMP4[2:0] bits (Channel 4 Sample time selection) /
Kojto	112:6f327212ef96	1014	#define ADC_SMPR3_SMP4_0 ((uint32_t)0x00001000) /!< Bit 0 /
Kojto	112:6f327212ef96	1015	#define ADC_SMPR3_SMP4_1 ((uint32_t)0x00002000) /!< Bit 1 /
Kojto	112:6f327212ef96	1016	#define ADC_SMPR3_SMP4_2 ((uint32_t)0x00004000) /!< Bit 2 /
Kojto	112:6f327212ef96	1017
Kojto	112:6f327212ef96	1018	#define ADC_SMPR3_SMP5 ((uint32_t)0x00038000) /!< SMP5[2:0] bits (Channel 5 Sample time selection) /
Kojto	112:6f327212ef96	1019	#define ADC_SMPR3_SMP5_0 ((uint32_t)0x00008000) /!< Bit 0 /
Kojto	112:6f327212ef96	1020	#define ADC_SMPR3_SMP5_1 ((uint32_t)0x00010000) /!< Bit 1 /
Kojto	112:6f327212ef96	1021	#define ADC_SMPR3_SMP5_2 ((uint32_t)0x00020000) /!< Bit 2 /
Kojto	112:6f327212ef96	1022
Kojto	112:6f327212ef96	1023	#define ADC_SMPR3_SMP6 ((uint32_t)0x001C0000) /!< SMP6[2:0] bits (Channel 6 Sample time selection) /
Kojto	112:6f327212ef96	1024	#define ADC_SMPR3_SMP6_0 ((uint32_t)0x00040000) /!< Bit 0 /
Kojto	112:6f327212ef96	1025	#define ADC_SMPR3_SMP6_1 ((uint32_t)0x00080000) /!< Bit 1 /
Kojto	112:6f327212ef96	1026	#define ADC_SMPR3_SMP6_2 ((uint32_t)0x00100000) /!< Bit 2 /
Kojto	112:6f327212ef96	1027
Kojto	112:6f327212ef96	1028	#define ADC_SMPR3_SMP7 ((uint32_t)0x00E00000) /!< SMP7[2:0] bits (Channel 7 Sample time selection) /
Kojto	112:6f327212ef96	1029	#define ADC_SMPR3_SMP7_0 ((uint32_t)0x00200000) /!< Bit 0 /
Kojto	112:6f327212ef96	1030	#define ADC_SMPR3_SMP7_1 ((uint32_t)0x00400000) /!< Bit 1 /
Kojto	112:6f327212ef96	1031	#define ADC_SMPR3_SMP7_2 ((uint32_t)0x00800000) /!< Bit 2 /
Kojto	112:6f327212ef96	1032
Kojto	112:6f327212ef96	1033	#define ADC_SMPR3_SMP8 ((uint32_t)0x07000000) /!< SMP8[2:0] bits (Channel 8 Sample time selection) /
Kojto	112:6f327212ef96	1034	#define ADC_SMPR3_SMP8_0 ((uint32_t)0x01000000) /!< Bit 0 /
Kojto	112:6f327212ef96	1035	#define ADC_SMPR3_SMP8_1 ((uint32_t)0x02000000) /!< Bit 1 /
Kojto	112:6f327212ef96	1036	#define ADC_SMPR3_SMP8_2 ((uint32_t)0x04000000) /!< Bit 2 /
Kojto	112:6f327212ef96	1037
Kojto	112:6f327212ef96	1038	#define ADC_SMPR3_SMP9 ((uint32_t)0x38000000) /!< SMP9[2:0] bits (Channel 9 Sample time selection) /
Kojto	112:6f327212ef96	1039	#define ADC_SMPR3_SMP9_0 ((uint32_t)0x08000000) /!< Bit 0 /
Kojto	112:6f327212ef96	1040	#define ADC_SMPR3_SMP9_1 ((uint32_t)0x10000000) /!< Bit 1 /
Kojto	112:6f327212ef96	1041	#define ADC_SMPR3_SMP9_2 ((uint32_t)0x20000000) /!< Bit 2 /
Kojto	112:6f327212ef96	1042
Kojto	112:6f327212ef96	1043	/**************** Bit definition for ADC_JOFR1 register *****************/
Kojto	112:6f327212ef96	1044	#define ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) /!< Data offset for injected channel 1 /
Kojto	112:6f327212ef96	1045
Kojto	112:6f327212ef96	1046	/**************** Bit definition for ADC_JOFR2 register *****************/
Kojto	112:6f327212ef96	1047	#define ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) /!< Data offset for injected channel 2 /
Kojto	112:6f327212ef96	1048
Kojto	112:6f327212ef96	1049	/**************** Bit definition for ADC_JOFR3 register *****************/
Kojto	112:6f327212ef96	1050	#define ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) /!< Data offset for injected channel 3 /
Kojto	112:6f327212ef96	1051
Kojto	112:6f327212ef96	1052	/**************** Bit definition for ADC_JOFR4 register *****************/
Kojto	112:6f327212ef96	1053	#define ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) /!< Data offset for injected channel 4 /
Kojto	112:6f327212ef96	1054
Kojto	112:6f327212ef96	1055	/***************** Bit definition for ADC_HTR register ******************/
Kojto	112:6f327212ef96	1056	#define ADC_HTR_HT ((uint32_t)0x00000FFF) /!< Analog watchdog high threshold /
Kojto	112:6f327212ef96	1057
Kojto	112:6f327212ef96	1058	/***************** Bit definition for ADC_LTR register ******************/
Kojto	112:6f327212ef96	1059	#define ADC_LTR_LT ((uint32_t)0x00000FFF) /!< Analog watchdog low threshold /
Kojto	112:6f327212ef96	1060
Kojto	112:6f327212ef96	1061	/***************** Bit definition for ADC_SQR1 register *****************/
Kojto	112:6f327212ef96	1062	#define ADC_SQR1_L ((uint32_t)0x01F00000) /!< L[4:0] bits (Regular channel sequence length) /
Kojto	112:6f327212ef96	1063	#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /!< Bit 0 /
Kojto	112:6f327212ef96	1064	#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /!< Bit 1 /
Kojto	112:6f327212ef96	1065	#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /!< Bit 2 /
Kojto	112:6f327212ef96	1066	#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /!< Bit 3 /
Kojto	112:6f327212ef96	1067	#define ADC_SQR1_L_4 ((uint32_t)0x01000000) /!< Bit 4 /
Kojto	112:6f327212ef96	1068
Kojto	112:6f327212ef96	1069	#define ADC_SQR1_SQ28 ((uint32_t)0x000F8000) /!< SQ28[4:0] bits (25th conversion in regular sequence) /
Kojto	112:6f327212ef96	1070	#define ADC_SQR1_SQ28_0 ((uint32_t)0x00008000) /!< Bit 0 /
Kojto	112:6f327212ef96	1071	#define ADC_SQR1_SQ28_1 ((uint32_t)0x00010000) /!< Bit 1 /
Kojto	112:6f327212ef96	1072	#define ADC_SQR1_SQ28_2 ((uint32_t)0x00020000) /!< Bit 2 /
Kojto	112:6f327212ef96	1073	#define ADC_SQR1_SQ28_3 ((uint32_t)0x00040000) /!< Bit 3 /
Kojto	112:6f327212ef96	1074	#define ADC_SQR1_SQ28_4 ((uint32_t)0x00080000) /!< Bit 4 /
Kojto	112:6f327212ef96	1075
Kojto	112:6f327212ef96	1076	#define ADC_SQR1_SQ27 ((uint32_t)0x00007C00) /!< SQ27[4:0] bits (27th conversion in regular sequence) /
Kojto	112:6f327212ef96	1077	#define ADC_SQR1_SQ27_0 ((uint32_t)0x00000400) /!< Bit 0 /
Kojto	112:6f327212ef96	1078	#define ADC_SQR1_SQ27_1 ((uint32_t)0x00000800) /!< Bit 1 /
Kojto	112:6f327212ef96	1079	#define ADC_SQR1_SQ27_2 ((uint32_t)0x00001000) /!< Bit 2 /
Kojto	112:6f327212ef96	1080	#define ADC_SQR1_SQ27_3 ((uint32_t)0x00002000) /!< Bit 3 /
Kojto	112:6f327212ef96	1081	#define ADC_SQR1_SQ27_4 ((uint32_t)0x00004000) /!< Bit 4 /
Kojto	112:6f327212ef96	1082
Kojto	112:6f327212ef96	1083	#define ADC_SQR1_SQ26 ((uint32_t)0x000003E0) /!< SQ26[4:0] bits (26th conversion in regular sequence) /
Kojto	112:6f327212ef96	1084	#define ADC_SQR1_SQ26_0 ((uint32_t)0x00000020) /!< Bit 0 /
Kojto	112:6f327212ef96	1085	#define ADC_SQR1_SQ26_1 ((uint32_t)0x00000040) /!< Bit 1 /
Kojto	112:6f327212ef96	1086	#define ADC_SQR1_SQ26_2 ((uint32_t)0x00000080) /!< Bit 2 /
Kojto	112:6f327212ef96	1087	#define ADC_SQR1_SQ26_3 ((uint32_t)0x00000100) /!< Bit 3 /
Kojto	112:6f327212ef96	1088	#define ADC_SQR1_SQ26_4 ((uint32_t)0x00000200) /!< Bit 4 /
Kojto	112:6f327212ef96	1089
Kojto	112:6f327212ef96	1090	#define ADC_SQR1_SQ25 ((uint32_t)0x0000001F) /!< SQ25[4:0] bits (25th conversion in regular sequence) /
Kojto	112:6f327212ef96	1091	#define ADC_SQR1_SQ25_0 ((uint32_t)0x00000001) /!< Bit 0 /
Kojto	112:6f327212ef96	1092	#define ADC_SQR1_SQ25_1 ((uint32_t)0x00000002) /!< Bit 1 /
Kojto	112:6f327212ef96	1093	#define ADC_SQR1_SQ25_2 ((uint32_t)0x00000004) /!< Bit 2 /
Kojto	112:6f327212ef96	1094	#define ADC_SQR1_SQ25_3 ((uint32_t)0x00000008) /!< Bit 3 /
Kojto	112:6f327212ef96	1095	#define ADC_SQR1_SQ25_4 ((uint32_t)0x00000010) /!< Bit 4 /
Kojto	112:6f327212ef96	1096
Kojto	112:6f327212ef96	1097	/***************** Bit definition for ADC_SQR2 register *****************/
Kojto	112:6f327212ef96	1098	#define ADC_SQR2_SQ19 ((uint32_t)0x0000001F) /!< SQ19[4:0] bits (19th conversion in regular sequence) /
Kojto	112:6f327212ef96	1099	#define ADC_SQR2_SQ19_0 ((uint32_t)0x00000001) /!< Bit 0 /
Kojto	112:6f327212ef96	1100	#define ADC_SQR2_SQ19_1 ((uint32_t)0x00000002) /!< Bit 1 /
Kojto	112:6f327212ef96	1101	#define ADC_SQR2_SQ19_2 ((uint32_t)0x00000004) /!< Bit 2 /
Kojto	112:6f327212ef96	1102	#define ADC_SQR2_SQ19_3 ((uint32_t)0x00000008) /!< Bit 3 /
Kojto	112:6f327212ef96	1103	#define ADC_SQR2_SQ19_4 ((uint32_t)0x00000010) /!< Bit 4 /
Kojto	112:6f327212ef96	1104
Kojto	112:6f327212ef96	1105	#define ADC_SQR2_SQ20 ((uint32_t)0x000003E0) /!< SQ20[4:0] bits (20th conversion in regular sequence) /
Kojto	112:6f327212ef96	1106	#define ADC_SQR2_SQ20_0 ((uint32_t)0x00000020) /!< Bit 0 /
Kojto	112:6f327212ef96	1107	#define ADC_SQR2_SQ20_1 ((uint32_t)0x00000040) /!< Bit 1 /
Kojto	112:6f327212ef96	1108	#define ADC_SQR2_SQ20_2 ((uint32_t)0x00000080) /!< Bit 2 /
Kojto	112:6f327212ef96	1109	#define ADC_SQR2_SQ20_3 ((uint32_t)0x00000100) /!< Bit 3 /
Kojto	112:6f327212ef96	1110	#define ADC_SQR2_SQ20_4 ((uint32_t)0x00000200) /!< Bit 4 /
Kojto	112:6f327212ef96	1111
Kojto	112:6f327212ef96	1112	#define ADC_SQR2_SQ21 ((uint32_t)0x00007C00) /!< SQ21[4:0] bits (21th conversion in regular sequence) /
Kojto	112:6f327212ef96	1113	#define ADC_SQR2_SQ21_0 ((uint32_t)0x00000400) /!< Bit 0 /
Kojto	112:6f327212ef96	1114	#define ADC_SQR2_SQ21_1 ((uint32_t)0x00000800) /!< Bit 1 /
Kojto	112:6f327212ef96	1115	#define ADC_SQR2_SQ21_2 ((uint32_t)0x00001000) /!< Bit 2 /
Kojto	112:6f327212ef96	1116	#define ADC_SQR2_SQ21_3 ((uint32_t)0x00002000) /!< Bit 3 /
Kojto	112:6f327212ef96	1117	#define ADC_SQR2_SQ21_4 ((uint32_t)0x00004000) /!< Bit 4 /
Kojto	112:6f327212ef96	1118
Kojto	112:6f327212ef96	1119	#define ADC_SQR2_SQ22 ((uint32_t)0x000F8000) /!< SQ22[4:0] bits (22th conversion in regular sequence) /
Kojto	112:6f327212ef96	1120	#define ADC_SQR2_SQ22_0 ((uint32_t)0x00008000) /!< Bit 0 /
Kojto	112:6f327212ef96	1121	#define ADC_SQR2_SQ22_1 ((uint32_t)0x00010000) /!< Bit 1 /
Kojto	112:6f327212ef96	1122	#define ADC_SQR2_SQ22_2 ((uint32_t)0x00020000) /!< Bit 2 /
Kojto	112:6f327212ef96	1123	#define ADC_SQR2_SQ22_3 ((uint32_t)0x00040000) /!< Bit 3 /
Kojto	112:6f327212ef96	1124	#define ADC_SQR2_SQ22_4 ((uint32_t)0x00080000) /!< Bit 4 /
Kojto	112:6f327212ef96	1125
Kojto	112:6f327212ef96	1126	#define ADC_SQR2_SQ23 ((uint32_t)0x01F00000) /!< SQ23[4:0] bits (23th conversion in regular sequence) /
Kojto	112:6f327212ef96	1127	#define ADC_SQR2_SQ23_0 ((uint32_t)0x00100000) /!< Bit 0 /
Kojto	112:6f327212ef96	1128	#define ADC_SQR2_SQ23_1 ((uint32_t)0x00200000) /!< Bit 1 /
Kojto	112:6f327212ef96	1129	#define ADC_SQR2_SQ23_2 ((uint32_t)0x00400000) /!< Bit 2 /
Kojto	112:6f327212ef96	1130	#define ADC_SQR2_SQ23_3 ((uint32_t)0x00800000) /!< Bit 3 /
Kojto	112:6f327212ef96	1131	#define ADC_SQR2_SQ23_4 ((uint32_t)0x01000000) /!< Bit 4 /
Kojto	112:6f327212ef96	1132
Kojto	112:6f327212ef96	1133	#define ADC_SQR2_SQ24 ((uint32_t)0x3E000000) /!< SQ24[4:0] bits (24th conversion in regular sequence) /
Kojto	112:6f327212ef96	1134	#define ADC_SQR2_SQ24_0 ((uint32_t)0x02000000) /!< Bit 0 /
Kojto	112:6f327212ef96	1135	#define ADC_SQR2_SQ24_1 ((uint32_t)0x04000000) /!< Bit 1 /
Kojto	112:6f327212ef96	1136	#define ADC_SQR2_SQ24_2 ((uint32_t)0x08000000) /!< Bit 2 /
Kojto	112:6f327212ef96	1137	#define ADC_SQR2_SQ24_3 ((uint32_t)0x10000000) /!< Bit 3 /
Kojto	112:6f327212ef96	1138	#define ADC_SQR2_SQ24_4 ((uint32_t)0x20000000) /!< Bit 4 /
Kojto	112:6f327212ef96	1139
Kojto	112:6f327212ef96	1140	/***************** Bit definition for ADC_SQR3 register *****************/
Kojto	112:6f327212ef96	1141	#define ADC_SQR3_SQ13 ((uint32_t)0x0000001F) /!< SQ13[4:0] bits (13th conversion in regular sequence) /
Kojto	112:6f327212ef96	1142	#define ADC_SQR3_SQ13_0 ((uint32_t)0x00000001) /!< Bit 0 /
Kojto	112:6f327212ef96	1143	#define ADC_SQR3_SQ13_1 ((uint32_t)0x00000002) /!< Bit 1 /
Kojto	112:6f327212ef96	1144	#define ADC_SQR3_SQ13_2 ((uint32_t)0x00000004) /!< Bit 2 /
Kojto	112:6f327212ef96	1145	#define ADC_SQR3_SQ13_3 ((uint32_t)0x00000008) /!< Bit 3 /
Kojto	112:6f327212ef96	1146	#define ADC_SQR3_SQ13_4 ((uint32_t)0x00000010) /!< Bit 4 /
Kojto	112:6f327212ef96	1147
Kojto	112:6f327212ef96	1148	#define ADC_SQR3_SQ14 ((uint32_t)0x000003E0) /!< SQ14[4:0] bits (14th conversion in regular sequence) /
Kojto	112:6f327212ef96	1149	#define ADC_SQR3_SQ14_0 ((uint32_t)0x00000020) /!< Bit 0 /
Kojto	112:6f327212ef96	1150	#define ADC_SQR3_SQ14_1 ((uint32_t)0x00000040) /!< Bit 1 /
Kojto	112:6f327212ef96	1151	#define ADC_SQR3_SQ14_2 ((uint32_t)0x00000080) /!< Bit 2 /
Kojto	112:6f327212ef96	1152	#define ADC_SQR3_SQ14_3 ((uint32_t)0x00000100) /!< Bit 3 /
Kojto	112:6f327212ef96	1153	#define ADC_SQR3_SQ14_4 ((uint32_t)0x00000200) /!< Bit 4 /
Kojto	112:6f327212ef96	1154
Kojto	112:6f327212ef96	1155	#define ADC_SQR3_SQ15 ((uint32_t)0x00007C00) /!< SQ15[4:0] bits (15th conversion in regular sequence) /
Kojto	112:6f327212ef96	1156	#define ADC_SQR3_SQ15_0 ((uint32_t)0x00000400) /!< Bit 0 /
Kojto	112:6f327212ef96	1157	#define ADC_SQR3_SQ15_1 ((uint32_t)0x00000800) /!< Bit 1 /
Kojto	112:6f327212ef96	1158	#define ADC_SQR3_SQ15_2 ((uint32_t)0x00001000) /!< Bit 2 /
Kojto	112:6f327212ef96	1159	#define ADC_SQR3_SQ15_3 ((uint32_t)0x00002000) /!< Bit 3 /
Kojto	112:6f327212ef96	1160	#define ADC_SQR3_SQ15_4 ((uint32_t)0x00004000) /!< Bit 4 /
Kojto	112:6f327212ef96	1161
Kojto	112:6f327212ef96	1162	#define ADC_SQR3_SQ16 ((uint32_t)0x000F8000) /!< SQ16[4:0] bits (16th conversion in regular sequence) /
Kojto	112:6f327212ef96	1163	#define ADC_SQR3_SQ16_0 ((uint32_t)0x00008000) /!< Bit 0 /
Kojto	112:6f327212ef96	1164	#define ADC_SQR3_SQ16_1 ((uint32_t)0x00010000) /!< Bit 1 /
Kojto	112:6f327212ef96	1165	#define ADC_SQR3_SQ16_2 ((uint32_t)0x00020000) /!< Bit 2 /
Kojto	112:6f327212ef96	1166	#define ADC_SQR3_SQ16_3 ((uint32_t)0x00040000) /!< Bit 3 /
Kojto	112:6f327212ef96	1167	#define ADC_SQR3_SQ16_4 ((uint32_t)0x00080000) /!< Bit 4 /
Kojto	112:6f327212ef96	1168
Kojto	112:6f327212ef96	1169	#define ADC_SQR3_SQ17 ((uint32_t)0x01F00000) /!< SQ17[4:0] bits (17th conversion in regular sequence) /
Kojto	112:6f327212ef96	1170	#define ADC_SQR3_SQ17_0 ((uint32_t)0x00100000) /!< Bit 0 /
Kojto	112:6f327212ef96	1171	#define ADC_SQR3_SQ17_1 ((uint32_t)0x00200000) /!< Bit 1 /
Kojto	112:6f327212ef96	1172	#define ADC_SQR3_SQ17_2 ((uint32_t)0x00400000) /!< Bit 2 /
Kojto	112:6f327212ef96	1173	#define ADC_SQR3_SQ17_3 ((uint32_t)0x00800000) /!< Bit 3 /
Kojto	112:6f327212ef96	1174	#define ADC_SQR3_SQ17_4 ((uint32_t)0x01000000) /!< Bit 4 /
Kojto	112:6f327212ef96	1175
Kojto	112:6f327212ef96	1176	#define ADC_SQR3_SQ18 ((uint32_t)0x3E000000) /!< SQ18[4:0] bits (18th conversion in regular sequence) /
Kojto	112:6f327212ef96	1177	#define ADC_SQR3_SQ18_0 ((uint32_t)0x02000000) /!< Bit 0 /
Kojto	112:6f327212ef96	1178	#define ADC_SQR3_SQ18_1 ((uint32_t)0x04000000) /!< Bit 1 /
Kojto	112:6f327212ef96	1179	#define ADC_SQR3_SQ18_2 ((uint32_t)0x08000000) /!< Bit 2 /
Kojto	112:6f327212ef96	1180	#define ADC_SQR3_SQ18_3 ((uint32_t)0x10000000) /!< Bit 3 /
Kojto	112:6f327212ef96	1181	#define ADC_SQR3_SQ18_4 ((uint32_t)0x20000000) /!< Bit 4 /
Kojto	112:6f327212ef96	1182
Kojto	112:6f327212ef96	1183	/***************** Bit definition for ADC_SQR4 register *****************/
Kojto	112:6f327212ef96	1184	#define ADC_SQR4_SQ7 ((uint32_t)0x0000001F) /!< SQ7[4:0] bits (7th conversion in regular sequence) /
Kojto	112:6f327212ef96	1185	#define ADC_SQR4_SQ7_0 ((uint32_t)0x00000001) /!< Bit 0 /
Kojto	112:6f327212ef96	1186	#define ADC_SQR4_SQ7_1 ((uint32_t)0x00000002) /!< Bit 1 /
Kojto	112:6f327212ef96	1187	#define ADC_SQR4_SQ7_2 ((uint32_t)0x00000004) /!< Bit 2 /
Kojto	112:6f327212ef96	1188	#define ADC_SQR4_SQ7_3 ((uint32_t)0x00000008) /!< Bit 3 /
Kojto	112:6f327212ef96	1189	#define ADC_SQR4_SQ7_4 ((uint32_t)0x00000010) /!< Bit 4 /
Kojto	112:6f327212ef96	1190
Kojto	112:6f327212ef96	1191	#define ADC_SQR4_SQ8 ((uint32_t)0x000003E0) /!< SQ8[4:0] bits (8th conversion in regular sequence) /
Kojto	112:6f327212ef96	1192	#define ADC_SQR4_SQ8_0 ((uint32_t)0x00000020) /!< Bit 0 /
Kojto	112:6f327212ef96	1193	#define ADC_SQR4_SQ8_1 ((uint32_t)0x00000040) /!< Bit 1 /
Kojto	112:6f327212ef96	1194	#define ADC_SQR4_SQ8_2 ((uint32_t)0x00000080) /!< Bit 2 /
Kojto	112:6f327212ef96	1195	#define ADC_SQR4_SQ8_3 ((uint32_t)0x00000100) /!< Bit 3 /
Kojto	112:6f327212ef96	1196	#define ADC_SQR4_SQ8_4 ((uint32_t)0x00000200) /!< Bit 4 /
Kojto	112:6f327212ef96	1197
Kojto	112:6f327212ef96	1198	#define ADC_SQR4_SQ9 ((uint32_t)0x00007C00) /!< SQ9[4:0] bits (9th conversion in regular sequence) /
Kojto	112:6f327212ef96	1199	#define ADC_SQR4_SQ9_0 ((uint32_t)0x00000400) /!< Bit 0 /
Kojto	112:6f327212ef96	1200	#define ADC_SQR4_SQ9_1 ((uint32_t)0x00000800) /!< Bit 1 /
Kojto	112:6f327212ef96	1201	#define ADC_SQR4_SQ9_2 ((uint32_t)0x00001000) /!< Bit 2 /
Kojto	112:6f327212ef96	1202	#define ADC_SQR4_SQ9_3 ((uint32_t)0x00002000) /!< Bit 3 /
Kojto	112:6f327212ef96	1203	#define ADC_SQR4_SQ9_4 ((uint32_t)0x00004000) /!< Bit 4 /
Kojto	112:6f327212ef96	1204
Kojto	112:6f327212ef96	1205	#define ADC_SQR4_SQ10 ((uint32_t)0x000F8000) /!< SQ10[4:0] bits (10th conversion in regular sequence) /
Kojto	112:6f327212ef96	1206	#define ADC_SQR4_SQ10_0 ((uint32_t)0x00008000) /!< Bit 0 /
Kojto	112:6f327212ef96	1207	#define ADC_SQR4_SQ10_1 ((uint32_t)0x00010000) /!< Bit 1 /
Kojto	112:6f327212ef96	1208	#define ADC_SQR4_SQ10_2 ((uint32_t)0x00020000) /!< Bit 2 /
Kojto	112:6f327212ef96	1209	#define ADC_SQR4_SQ10_3 ((uint32_t)0x00040000) /!< Bit 3 /
Kojto	112:6f327212ef96	1210	#define ADC_SQR4_SQ10_4 ((uint32_t)0x00080000) /!< Bit 4 /
Kojto	112:6f327212ef96	1211
Kojto	112:6f327212ef96	1212	#define ADC_SQR4_SQ11 ((uint32_t)0x01F00000) /!< SQ11[4:0] bits (11th conversion in regular sequence) /
Kojto	112:6f327212ef96	1213	#define ADC_SQR4_SQ11_0 ((uint32_t)0x00100000) /!< Bit 0 /
Kojto	112:6f327212ef96	1214	#define ADC_SQR4_SQ11_1 ((uint32_t)0x00200000) /!< Bit 1 /
Kojto	112:6f327212ef96	1215	#define ADC_SQR4_SQ11_2 ((uint32_t)0x00400000) /!< Bit 2 /
Kojto	112:6f327212ef96	1216	#define ADC_SQR4_SQ11_3 ((uint32_t)0x00800000) /!< Bit 3 /
Kojto	112:6f327212ef96	1217	#define ADC_SQR4_SQ11_4 ((uint32_t)0x01000000) /!< Bit 4 /
Kojto	112:6f327212ef96	1218
Kojto	112:6f327212ef96	1219	#define ADC_SQR4_SQ12 ((uint32_t)0x3E000000) /!< SQ12[4:0] bits (12th conversion in regular sequence) /
Kojto	112:6f327212ef96	1220	#define ADC_SQR4_SQ12_0 ((uint32_t)0x02000000) /!< Bit 0 /
Kojto	112:6f327212ef96	1221	#define ADC_SQR4_SQ12_1 ((uint32_t)0x04000000) /!< Bit 1 /
Kojto	112:6f327212ef96	1222	#define ADC_SQR4_SQ12_2 ((uint32_t)0x08000000) /!< Bit 2 /
Kojto	112:6f327212ef96	1223	#define ADC_SQR4_SQ12_3 ((uint32_t)0x10000000) /!< Bit 3 /
Kojto	112:6f327212ef96	1224	#define ADC_SQR4_SQ12_4 ((uint32_t)0x20000000) /!< Bit 4 /
Kojto	112:6f327212ef96	1225
Kojto	112:6f327212ef96	1226	/***************** Bit definition for ADC_SQR5 register *****************/
Kojto	112:6f327212ef96	1227	#define ADC_SQR5_SQ1 ((uint32_t)0x0000001F) /!< SQ1[4:0] bits (1st conversion in regular sequence) /
Kojto	112:6f327212ef96	1228	#define ADC_SQR5_SQ1_0 ((uint32_t)0x00000001) /!< Bit 0 /
Kojto	112:6f327212ef96	1229	#define ADC_SQR5_SQ1_1 ((uint32_t)0x00000002) /!< Bit 1 /
Kojto	112:6f327212ef96	1230	#define ADC_SQR5_SQ1_2 ((uint32_t)0x00000004) /!< Bit 2 /
Kojto	112:6f327212ef96	1231	#define ADC_SQR5_SQ1_3 ((uint32_t)0x00000008) /!< Bit 3 /
Kojto	112:6f327212ef96	1232	#define ADC_SQR5_SQ1_4 ((uint32_t)0x00000010) /!< Bit 4 /
Kojto	112:6f327212ef96	1233
Kojto	112:6f327212ef96	1234	#define ADC_SQR5_SQ2 ((uint32_t)0x000003E0) /!< SQ2[4:0] bits (2nd conversion in regular sequence) /
Kojto	112:6f327212ef96	1235	#define ADC_SQR5_SQ2_0 ((uint32_t)0x00000020) /!< Bit 0 /
Kojto	112:6f327212ef96	1236	#define ADC_SQR5_SQ2_1 ((uint32_t)0x00000040) /!< Bit 1 /
Kojto	112:6f327212ef96	1237	#define ADC_SQR5_SQ2_2 ((uint32_t)0x00000080) /!< Bit 2 /
Kojto	112:6f327212ef96	1238	#define ADC_SQR5_SQ2_3 ((uint32_t)0x00000100) /!< Bit 3 /
Kojto	112:6f327212ef96	1239	#define ADC_SQR5_SQ2_4 ((uint32_t)0x00000200) /!< Bit 4 /
Kojto	112:6f327212ef96	1240
Kojto	112:6f327212ef96	1241	#define ADC_SQR5_SQ3 ((uint32_t)0x00007C00) /!< SQ3[4:0] bits (3rd conversion in regular sequence) /
Kojto	112:6f327212ef96	1242	#define ADC_SQR5_SQ3_0 ((uint32_t)0x00000400) /!< Bit 0 /
Kojto	112:6f327212ef96	1243	#define ADC_SQR5_SQ3_1 ((uint32_t)0x00000800) /!< Bit 1 /
Kojto	112:6f327212ef96	1244	#define ADC_SQR5_SQ3_2 ((uint32_t)0x00001000) /!< Bit 2 /
Kojto	112:6f327212ef96	1245	#define ADC_SQR5_SQ3_3 ((uint32_t)0x00002000) /!< Bit 3 /
Kojto	112:6f327212ef96	1246	#define ADC_SQR5_SQ3_4 ((uint32_t)0x00004000) /!< Bit 4 /
Kojto	112:6f327212ef96	1247
Kojto	112:6f327212ef96	1248	#define ADC_SQR5_SQ4 ((uint32_t)0x000F8000) /!< SQ4[4:0] bits (4th conversion in regular sequence) /
Kojto	112:6f327212ef96	1249	#define ADC_SQR5_SQ4_0 ((uint32_t)0x00008000) /!< Bit 0 /
Kojto	112:6f327212ef96	1250	#define ADC_SQR5_SQ4_1 ((uint32_t)0x00010000) /!< Bit 1 /
Kojto	112:6f327212ef96	1251	#define ADC_SQR5_SQ4_2 ((uint32_t)0x00020000) /!< Bit 2 /
Kojto	112:6f327212ef96	1252	#define ADC_SQR5_SQ4_3 ((uint32_t)0x00040000) /!< Bit 3 /
Kojto	112:6f327212ef96	1253	#define ADC_SQR5_SQ4_4 ((uint32_t)0x00080000) /!< Bit 4 /
Kojto	112:6f327212ef96	1254
Kojto	112:6f327212ef96	1255	#define ADC_SQR5_SQ5 ((uint32_t)0x01F00000) /!< SQ5[4:0] bits (5th conversion in regular sequence) /
Kojto	112:6f327212ef96	1256	#define ADC_SQR5_SQ5_0 ((uint32_t)0x00100000) /!< Bit 0 /
Kojto	112:6f327212ef96	1257	#define ADC_SQR5_SQ5_1 ((uint32_t)0x00200000) /!< Bit 1 /
Kojto	112:6f327212ef96	1258	#define ADC_SQR5_SQ5_2 ((uint32_t)0x00400000) /!< Bit 2 /
Kojto	112:6f327212ef96	1259	#define ADC_SQR5_SQ5_3 ((uint32_t)0x00800000) /!< Bit 3 /
Kojto	112:6f327212ef96	1260	#define ADC_SQR5_SQ5_4 ((uint32_t)0x01000000) /!< Bit 4 /
Kojto	112:6f327212ef96	1261
Kojto	112:6f327212ef96	1262	#define ADC_SQR5_SQ6 ((uint32_t)0x3E000000) /!< SQ6[4:0] bits (6th conversion in regular sequence) /
Kojto	112:6f327212ef96	1263	#define ADC_SQR5_SQ6_0 ((uint32_t)0x02000000) /!< Bit 0 /
Kojto	112:6f327212ef96	1264	#define ADC_SQR5_SQ6_1 ((uint32_t)0x04000000) /!< Bit 1 /
Kojto	112:6f327212ef96	1265	#define ADC_SQR5_SQ6_2 ((uint32_t)0x08000000) /!< Bit 2 /
Kojto	112:6f327212ef96	1266	#define ADC_SQR5_SQ6_3 ((uint32_t)0x10000000) /!< Bit 3 /
Kojto	112:6f327212ef96	1267	#define ADC_SQR5_SQ6_4 ((uint32_t)0x20000000) /!< Bit 4 /
Kojto	112:6f327212ef96	1268
Kojto	112:6f327212ef96	1269
Kojto	112:6f327212ef96	1270	/***************** Bit definition for ADC_JSQR register *****************/
Kojto	112:6f327212ef96	1271	#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /!< JSQ1[4:0] bits (1st conversion in injected sequence) /
Kojto	112:6f327212ef96	1272	#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /!< Bit 0 /
Kojto	112:6f327212ef96	1273	#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /!< Bit 1 /
Kojto	112:6f327212ef96	1274	#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /!< Bit 2 /
Kojto	112:6f327212ef96	1275	#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /!< Bit 3 /
Kojto	112:6f327212ef96	1276	#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /!< Bit 4 /
Kojto	112:6f327212ef96	1277
Kojto	112:6f327212ef96	1278	#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /!< JSQ2[4:0] bits (2nd conversion in injected sequence) /
Kojto	112:6f327212ef96	1279	#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /!< Bit 0 /
Kojto	112:6f327212ef96	1280	#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /!< Bit 1 /
Kojto	112:6f327212ef96	1281	#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /!< Bit 2 /
Kojto	112:6f327212ef96	1282	#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /!< Bit 3 /
Kojto	112:6f327212ef96	1283	#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /!< Bit 4 /
Kojto	112:6f327212ef96	1284
Kojto	112:6f327212ef96	1285	#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /!< JSQ3[4:0] bits (3rd conversion in injected sequence) /
Kojto	112:6f327212ef96	1286	#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /!< Bit 0 /
Kojto	112:6f327212ef96	1287	#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /!< Bit 1 /
Kojto	112:6f327212ef96	1288	#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /!< Bit 2 /
Kojto	112:6f327212ef96	1289	#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /!< Bit 3 /
Kojto	112:6f327212ef96	1290	#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /!< Bit 4 /
Kojto	112:6f327212ef96	1291
Kojto	112:6f327212ef96	1292	#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /!< JSQ4[4:0] bits (4th conversion in injected sequence) /
Kojto	112:6f327212ef96	1293	#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /!< Bit 0 /
Kojto	112:6f327212ef96	1294	#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /!< Bit 1 /
Kojto	112:6f327212ef96	1295	#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /!< Bit 2 /
Kojto	112:6f327212ef96	1296	#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /!< Bit 3 /
Kojto	112:6f327212ef96	1297	#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /!< Bit 4 /
Kojto	112:6f327212ef96	1298
Kojto	112:6f327212ef96	1299	#define ADC_JSQR_JL ((uint32_t)0x00300000) /!< JL[1:0] bits (Injected Sequence length) /
Kojto	112:6f327212ef96	1300	#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /!< Bit 0 /
Kojto	112:6f327212ef96	1301	#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /!< Bit 1 /
Kojto	112:6f327212ef96	1302
Kojto	112:6f327212ef96	1303	/***************** Bit definition for ADC_JDR1 register *****************/
Kojto	112:6f327212ef96	1304	#define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) /!< Injected data /
Kojto	112:6f327212ef96	1305
Kojto	112:6f327212ef96	1306	/***************** Bit definition for ADC_JDR2 register *****************/
Kojto	112:6f327212ef96	1307	#define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) /!< Injected data /
Kojto	112:6f327212ef96	1308
Kojto	112:6f327212ef96	1309	/***************** Bit definition for ADC_JDR3 register *****************/
Kojto	112:6f327212ef96	1310	#define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) /!< Injected data /
Kojto	112:6f327212ef96	1311
Kojto	112:6f327212ef96	1312	/***************** Bit definition for ADC_JDR4 register *****************/
Kojto	112:6f327212ef96	1313	#define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) /!< Injected data /
Kojto	112:6f327212ef96	1314
Kojto	112:6f327212ef96	1315	/****************** Bit definition for ADC_DR register ******************/
Kojto	112:6f327212ef96	1316	#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /!< Regular data /
Kojto	112:6f327212ef96	1317
Kojto	112:6f327212ef96	1318	/***************** Bit definition for ADC_CSR register ******************/
Kojto	112:6f327212ef96	1319	#define ADC_CSR_AWD1 ((uint32_t)0x00000001) /!< ADC1 Analog watchdog flag /
Kojto	112:6f327212ef96	1320	#define ADC_CSR_EOC1 ((uint32_t)0x00000002) /!< ADC1 End of conversion /
Kojto	112:6f327212ef96	1321	#define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /!< ADC1 Injected channel end of conversion /
Kojto	112:6f327212ef96	1322	#define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /!< ADC1 Injected channel Start flag /
Kojto	112:6f327212ef96	1323	#define ADC_CSR_STRT1 ((uint32_t)0x00000010) /!< ADC1 Regular channel Start flag /
Kojto	112:6f327212ef96	1324	#define ADC_CSR_OVR1 ((uint32_t)0x00000020) /!< ADC1 overrun flag /
Kojto	112:6f327212ef96	1325	#define ADC_CSR_ADONS1 ((uint32_t)0x00000040) /!< ADON status of ADC1 /
Kojto	112:6f327212ef96	1326
Kojto	112:6f327212ef96	1327	/***************** Bit definition for ADC_CCR register ******************/
Kojto	112:6f327212ef96	1328	#define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /!< ADC prescaler/
Kojto	112:6f327212ef96	1329	#define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /!< Bit 0 /
Kojto	112:6f327212ef96	1330	#define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /!< Bit 1 /
Kojto	112:6f327212ef96	1331	#define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /!< Temperature Sensor and VREFINT Enable /
Kojto	112:6f327212ef96	1332
Kojto	112:6f327212ef96	1333	/******************************************************************************/
Kojto	112:6f327212ef96	1334	/* */
Kojto	112:6f327212ef96	1335	/* Analog Comparators (COMP) */
Kojto	112:6f327212ef96	1336	/* */
Kojto	112:6f327212ef96	1337	/******************************************************************************/
Kojto	112:6f327212ef96	1338
Kojto	112:6f327212ef96	1339	/**************** Bit definition for COMP_CSR register ******************/
Kojto	112:6f327212ef96	1340	#define COMP_CSR_10KPU ((uint32_t)0x00000001) /!< 10K pull-up resistor /
Kojto	112:6f327212ef96	1341	#define COMP_CSR_400KPU ((uint32_t)0x00000002) /!< 400K pull-up resistor /
Kojto	112:6f327212ef96	1342	#define COMP_CSR_10KPD ((uint32_t)0x00000004) /!< 10K pull-down resistor /
Kojto	112:6f327212ef96	1343	#define COMP_CSR_400KPD ((uint32_t)0x00000008) /!< 400K pull-down resistor /
Kojto	112:6f327212ef96	1344	#define COMP_CSR_CMP1EN ((uint32_t)0x00000010) /!< Comparator 1 enable /
Kojto	112:6f327212ef96	1345	#define COMP_CSR_CMP1OUT ((uint32_t)0x00000080) /!< Comparator 1 output /
Kojto	112:6f327212ef96	1346
Kojto	112:6f327212ef96	1347	#define COMP_CSR_SPEED ((uint32_t)0x00001000) /!< Comparator 2 speed /
Kojto	112:6f327212ef96	1348	#define COMP_CSR_CMP2OUT ((uint32_t)0x00002000) /!< Comparator 2 ouput /
Kojto	112:6f327212ef96	1349	#define COMP_CSR_VREFOUTEN ((uint32_t)0x00010000) /!< Comparator Vref Enable /
Kojto	112:6f327212ef96	1350	#define COMP_CSR_WNDWE ((uint32_t)0x00020000) /!< Window mode enable /
Kojto	112:6f327212ef96	1351	#define COMP_CSR_INSEL ((uint32_t)0x001C0000) /!< INSEL[2:0] Inversion input Selection /
Kojto	112:6f327212ef96	1352	#define COMP_CSR_INSEL_0 ((uint32_t)0x00040000) /!< Bit 0 /
Kojto	112:6f327212ef96	1353	#define COMP_CSR_INSEL_1 ((uint32_t)0x00080000) /!< Bit 1 /
Kojto	112:6f327212ef96	1354	#define COMP_CSR_INSEL_2 ((uint32_t)0x00100000) /!< Bit 2 /
Kojto	112:6f327212ef96	1355	#define COMP_CSR_OUTSEL ((uint32_t)0x00E00000) /!< OUTSEL[2:0] comparator 2 output redirection /
Kojto	112:6f327212ef96	1356	#define COMP_CSR_OUTSEL_0 ((uint32_t)0x00200000) /!< Bit 0 /
Kojto	112:6f327212ef96	1357	#define COMP_CSR_OUTSEL_1 ((uint32_t)0x00400000) /!< Bit 1 /
Kojto	112:6f327212ef96	1358	#define COMP_CSR_OUTSEL_2 ((uint32_t)0x00800000) /!< Bit 2 /
Kojto	112:6f327212ef96	1359
Kojto	112:6f327212ef96	1360	#define COMP_CSR_FCH3 ((uint32_t)0x04000000) /!< Bit 26 /
Kojto	112:6f327212ef96	1361	#define COMP_CSR_FCH8 ((uint32_t)0x08000000) /!< Bit 27 /
Kojto	112:6f327212ef96	1362	#define COMP_CSR_RCH13 ((uint32_t)0x10000000) /!< Bit 28 /
Kojto	112:6f327212ef96	1363
Kojto	112:6f327212ef96	1364	#define COMP_CSR_CAIE ((uint32_t)0x20000000) /!< Bit 29 /
Kojto	112:6f327212ef96	1365	#define COMP_CSR_CAIF ((uint32_t)0x40000000) /!< Bit 30 /
Kojto	112:6f327212ef96	1366	#define COMP_CSR_TSUSP ((uint32_t)0x80000000) /!< Bit 31 /
Kojto	112:6f327212ef96	1367
Kojto	112:6f327212ef96	1368	/******************************************************************************/
Kojto	112:6f327212ef96	1369	/* */
Kojto	112:6f327212ef96	1370	/* Operational Amplifier (OPAMP) */
Kojto	112:6f327212ef96	1371	/* */
Kojto	112:6f327212ef96	1372	/******************************************************************************/
Kojto	112:6f327212ef96	1373	/***************** Bit definition for OPAMP_CSR register ****************/
Kojto	112:6f327212ef96	1374	#define OPAMP_CSR_OPA1PD ((uint32_t)0x00000001) /!< OPAMP1 disable /
Kojto	112:6f327212ef96	1375	#define OPAMP_CSR_S3SEL1 ((uint32_t)0x00000002) /!< Switch 3 for OPAMP1 Enable /
Kojto	112:6f327212ef96	1376	#define OPAMP_CSR_S4SEL1 ((uint32_t)0x00000004) /!< Switch 4 for OPAMP1 Enable /
Kojto	112:6f327212ef96	1377	#define OPAMP_CSR_S5SEL1 ((uint32_t)0x00000008) /!< Switch 5 for OPAMP1 Enable /
Kojto	112:6f327212ef96	1378	#define OPAMP_CSR_S6SEL1 ((uint32_t)0x00000010) /!< Switch 6 for OPAMP1 Enable /
Kojto	112:6f327212ef96	1379	#define OPAMP_CSR_OPA1CAL_L ((uint32_t)0x00000020) /!< OPAMP1 Offset calibration for P differential pair /
Kojto	112:6f327212ef96	1380	#define OPAMP_CSR_OPA1CAL_H ((uint32_t)0x00000040) /!< OPAMP1 Offset calibration for N differential pair /
Kojto	112:6f327212ef96	1381	#define OPAMP_CSR_OPA1LPM ((uint32_t)0x00000080) /!< OPAMP1 Low power enable /
Kojto	112:6f327212ef96	1382	#define OPAMP_CSR_OPA2PD ((uint32_t)0x00000100) /!< OPAMP2 disable /
Kojto	112:6f327212ef96	1383	#define OPAMP_CSR_S3SEL2 ((uint32_t)0x00000200) /!< Switch 3 for OPAMP2 Enable /
Kojto	112:6f327212ef96	1384	#define OPAMP_CSR_S4SEL2 ((uint32_t)0x00000400) /!< Switch 4 for OPAMP2 Enable /
Kojto	112:6f327212ef96	1385	#define OPAMP_CSR_S5SEL2 ((uint32_t)0x00000800) /!< Switch 5 for OPAMP2 Enable /
Kojto	112:6f327212ef96	1386	#define OPAMP_CSR_S6SEL2 ((uint32_t)0x00001000) /!< Switch 6 for OPAMP2 Enable /
Kojto	112:6f327212ef96	1387	#define OPAMP_CSR_OPA2CAL_L ((uint32_t)0x00002000) /!< OPAMP2 Offset calibration for P differential pair /
Kojto	112:6f327212ef96	1388	#define OPAMP_CSR_OPA2CAL_H ((uint32_t)0x00004000) /!< OPAMP2 Offset calibration for N differential pair /
Kojto	112:6f327212ef96	1389	#define OPAMP_CSR_OPA2LPM ((uint32_t)0x00008000) /!< OPAMP2 Low power enable /
Kojto	112:6f327212ef96	1390	#define OPAMP_CSR_ANAWSEL1 ((uint32_t)0x01000000) /!< Switch ANA Enable for OPAMP1 /
Kojto	112:6f327212ef96	1391	#define OPAMP_CSR_ANAWSEL2 ((uint32_t)0x02000000) /!< Switch ANA Enable for OPAMP2 /
Kojto	112:6f327212ef96	1392	#define OPAMP_CSR_S7SEL2 ((uint32_t)0x08000000) /!< Switch 7 for OPAMP2 Enable /
Kojto	112:6f327212ef96	1393	#define OPAMP_CSR_AOP_RANGE ((uint32_t)0x10000000) /!< Power range selection /
Kojto	112:6f327212ef96	1394	#define OPAMP_CSR_OPA1CALOUT ((uint32_t)0x20000000) /!< OPAMP1 calibration output /
Kojto	112:6f327212ef96	1395	#define OPAMP_CSR_OPA2CALOUT ((uint32_t)0x40000000) /!< OPAMP2 calibration output /
Kojto	112:6f327212ef96	1396
Kojto	112:6f327212ef96	1397	/***************** Bit definition for OPAMP_OTR register ****************/
Kojto	112:6f327212ef96	1398	#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW ((uint32_t)0x0000001F) /!< Offset trim for transistors differential pair PMOS of OPAMP1 /
Kojto	112:6f327212ef96	1399	#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH ((uint32_t)0x000003E0) /!< Offset trim for transistors differential pair NMOS of OPAMP1 /
Kojto	112:6f327212ef96	1400	#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW ((uint32_t)0x00007C00) /!< Offset trim for transistors differential pair PMOS of OPAMP2 /
Kojto	112:6f327212ef96	1401	#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH ((uint32_t)0x000F8000) /!< Offset trim for transistors differential pair NMOS of OPAMP2 /
Kojto	112:6f327212ef96	1402	#define OPAMP_OTR_OT_USER ((uint32_t)0x80000000) /!< Switch to OPAMP offset user trimmed values /
Kojto	112:6f327212ef96	1403
Kojto	112:6f327212ef96	1404	/***************** Bit definition for OPAMP_LPOTR register **************/
Kojto	112:6f327212ef96	1405	#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW ((uint32_t)0x0000001F) /!< Offset trim for transistors differential pair PMOS of OPAMP1 /
Kojto	112:6f327212ef96	1406	#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH ((uint32_t)0x000003E0) /!< Offset trim for transistors differential pair NMOS of OPAMP1 /
Kojto	112:6f327212ef96	1407	#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW ((uint32_t)0x00007C00) /!< Offset trim for transistors differential pair PMOS of OPAMP2 /
Kojto	112:6f327212ef96	1408	#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH ((uint32_t)0x000F8000) /!< Offset trim for transistors differential pair NMOS of OPAMP2 /
Kojto	112:6f327212ef96	1409
Kojto	112:6f327212ef96	1410	/******************************************************************************/
Kojto	112:6f327212ef96	1411	/* */
Kojto	112:6f327212ef96	1412	/* CRC calculation unit (CRC) */
Kojto	112:6f327212ef96	1413	/* */
Kojto	112:6f327212ef96	1414	/******************************************************************************/
Kojto	112:6f327212ef96	1415
Kojto	112:6f327212ef96	1416	/***************** Bit definition for CRC_DR register *******************/
Kojto	112:6f327212ef96	1417	#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /!< Data register bits /
Kojto	112:6f327212ef96	1418
Kojto	112:6f327212ef96	1419	/***************** Bit definition for CRC_IDR register ******************/
Kojto	112:6f327212ef96	1420	#define CRC_IDR_IDR ((uint32_t)0x000000FF) /!< General-purpose 8-bit data register bits /
Kojto	112:6f327212ef96	1421
Kojto	112:6f327212ef96	1422	/****************** Bit definition for CRC_CR register ******************/
Kojto	112:6f327212ef96	1423	#define CRC_CR_RESET ((uint32_t)0x00000001) /!< RESET bit /
Kojto	112:6f327212ef96	1424
Kojto	112:6f327212ef96	1425	/******************************************************************************/
Kojto	112:6f327212ef96	1426	/* */
Kojto	112:6f327212ef96	1427	/* Digital to Analog Converter (DAC) */
Kojto	112:6f327212ef96	1428	/* */
Kojto	112:6f327212ef96	1429	/******************************************************************************/
Kojto	112:6f327212ef96	1430
Kojto	112:6f327212ef96	1431	/****************** Bit definition for DAC_CR register ******************/
Kojto	112:6f327212ef96	1432	#define DAC_CR_EN1 ((uint32_t)0x00000001) /!<DAC channel1 enable /
Kojto	112:6f327212ef96	1433	#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /!<DAC channel1 output buffer disable /
Kojto	112:6f327212ef96	1434	#define DAC_CR_TEN1 ((uint32_t)0x00000004) /!<DAC channel1 Trigger enable /
Kojto	112:6f327212ef96	1435
Kojto	112:6f327212ef96	1436	#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /!<TSEL1[2:0] (DAC channel1 Trigger selection) /
Kojto	112:6f327212ef96	1437	#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /!<Bit 0 /
Kojto	112:6f327212ef96	1438	#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /!<Bit 1 /
Kojto	112:6f327212ef96	1439	#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /!<Bit 2 /
Kojto	112:6f327212ef96	1440
Kojto	112:6f327212ef96	1441	#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) /
Kojto	112:6f327212ef96	1442	#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /!<Bit 0 /
Kojto	112:6f327212ef96	1443	#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /!<Bit 1 /
Kojto	112:6f327212ef96	1444
Kojto	112:6f327212ef96	1445	#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) /
Kojto	112:6f327212ef96	1446	#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /!<Bit 0 /
Kojto	112:6f327212ef96	1447	#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /!<Bit 1 /
Kojto	112:6f327212ef96	1448	#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /!<Bit 2 /
Kojto	112:6f327212ef96	1449	#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /!<Bit 3 /
Kojto	112:6f327212ef96	1450
Kojto	112:6f327212ef96	1451	#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /!<DAC channel1 DMA enable /
Kojto	112:6f327212ef96	1452	#define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /!<DAC channel1 DMA Interrupt enable /
Kojto	112:6f327212ef96	1453	#define DAC_CR_EN2 ((uint32_t)0x00010000) /!<DAC channel2 enable /
Kojto	112:6f327212ef96	1454	#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /!<DAC channel2 output buffer disable /
Kojto	112:6f327212ef96	1455	#define DAC_CR_TEN2 ((uint32_t)0x00040000) /!<DAC channel2 Trigger enable /
Kojto	112:6f327212ef96	1456
Kojto	112:6f327212ef96	1457	#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /!<TSEL2[2:0] (DAC channel2 Trigger selection) /
Kojto	112:6f327212ef96	1458	#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /!<Bit 0 /
Kojto	112:6f327212ef96	1459	#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /!<Bit 1 /
Kojto	112:6f327212ef96	1460	#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /!<Bit 2 /
Kojto	112:6f327212ef96	1461
Kojto	112:6f327212ef96	1462	#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) /
Kojto	112:6f327212ef96	1463	#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /!<Bit 0 /
Kojto	112:6f327212ef96	1464	#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /!<Bit 1 /
Kojto	112:6f327212ef96	1465
Kojto	112:6f327212ef96	1466	#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) /
Kojto	112:6f327212ef96	1467	#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /!<Bit 0 /
Kojto	112:6f327212ef96	1468	#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /!<Bit 1 /
Kojto	112:6f327212ef96	1469	#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /!<Bit 2 /
Kojto	112:6f327212ef96	1470	#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /!<Bit 3 /
Kojto	112:6f327212ef96	1471
Kojto	112:6f327212ef96	1472	#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /!<DAC channel2 DMA enabled /
Kojto	112:6f327212ef96	1473	#define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000) /!<DAC channel2 DMA underrun interrupt enable /
Kojto	112:6f327212ef96	1474	/*************** Bit definition for DAC_SWTRIGR register ****************/
Kojto	112:6f327212ef96	1475	#define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) /!<DAC channel1 software trigger /
Kojto	112:6f327212ef96	1476	#define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x00000002) /!<DAC channel2 software trigger /
Kojto	112:6f327212ef96	1477
Kojto	112:6f327212ef96	1478	/*************** Bit definition for DAC_DHR12R1 register ****************/
Kojto	112:6f327212ef96	1479	#define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFF) /!<DAC channel1 12-bit Right aligned data /
Kojto	112:6f327212ef96	1480
Kojto	112:6f327212ef96	1481	/*************** Bit definition for DAC_DHR12L1 register ****************/
Kojto	112:6f327212ef96	1482	#define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0) /!<DAC channel1 12-bit Left aligned data /
Kojto	112:6f327212ef96	1483
Kojto	112:6f327212ef96	1484	/**************** Bit definition for DAC_DHR8R1 register ****************/
Kojto	112:6f327212ef96	1485	#define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FF) /!<DAC channel1 8-bit Right aligned data /
Kojto	112:6f327212ef96	1486
Kojto	112:6f327212ef96	1487	/*************** Bit definition for DAC_DHR12R2 register ****************/
Kojto	112:6f327212ef96	1488	#define DAC_DHR12R2_DACC2DHR ((uint32_t)0x00000FFF) /!<DAC channel2 12-bit Right aligned data /
Kojto	112:6f327212ef96	1489
Kojto	112:6f327212ef96	1490	/*************** Bit definition for DAC_DHR12L2 register ****************/
Kojto	112:6f327212ef96	1491	#define DAC_DHR12L2_DACC2DHR ((uint32_t)0x0000FFF0) /!<DAC channel2 12-bit Left aligned data /
Kojto	112:6f327212ef96	1492
Kojto	112:6f327212ef96	1493	/**************** Bit definition for DAC_DHR8R2 register ****************/
Kojto	112:6f327212ef96	1494	#define DAC_DHR8R2_DACC2DHR ((uint32_t)0x000000FF) /!<DAC channel2 8-bit Right aligned data /
Kojto	112:6f327212ef96	1495
Kojto	112:6f327212ef96	1496	/*************** Bit definition for DAC_DHR12RD register ****************/
Kojto	112:6f327212ef96	1497	#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /!<DAC channel1 12-bit Right aligned data /
Kojto	112:6f327212ef96	1498	#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /!<DAC channel2 12-bit Right aligned data /
Kojto	112:6f327212ef96	1499
Kojto	112:6f327212ef96	1500	/*************** Bit definition for DAC_DHR12LD register ****************/
Kojto	112:6f327212ef96	1501	#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /!<DAC channel1 12-bit Left aligned data /
Kojto	112:6f327212ef96	1502	#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /!<DAC channel2 12-bit Left aligned data /
Kojto	112:6f327212ef96	1503
Kojto	112:6f327212ef96	1504	/**************** Bit definition for DAC_DHR8RD register ****************/
Kojto	112:6f327212ef96	1505	#define DAC_DHR8RD_DACC1DHR ((uint32_t)0x000000FF) /!<DAC channel1 8-bit Right aligned data /
Kojto	112:6f327212ef96	1506	#define DAC_DHR8RD_DACC2DHR ((uint32_t)0x0000FF00) /!<DAC channel2 8-bit Right aligned data /
Kojto	112:6f327212ef96	1507
Kojto	112:6f327212ef96	1508	/***************** Bit definition for DAC_DOR1 register *****************/
Kojto	112:6f327212ef96	1509	#define DAC_DOR1_DACC1DOR ((uint32_t)0x00000FFF) /!<DAC channel1 data output /
Kojto	112:6f327212ef96	1510
Kojto	112:6f327212ef96	1511	/***************** Bit definition for DAC_DOR2 register *****************/
Kojto	112:6f327212ef96	1512	#define DAC_DOR2_DACC2DOR ((uint_t)0x00000FFF) /!<DAC channel2 data output /
Kojto	112:6f327212ef96	1513
Kojto	112:6f327212ef96	1514	/****************** Bit definition for DAC_SR register ******************/
Kojto	112:6f327212ef96	1515	#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /!<DAC channel1 DMA underrun flag /
Kojto	112:6f327212ef96	1516	#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /!<DAC channel2 DMA underrun flag /
Kojto	112:6f327212ef96	1517
Kojto	112:6f327212ef96	1518	/******************************************************************************/
Kojto	112:6f327212ef96	1519	/* */
Kojto	112:6f327212ef96	1520	/* Debug MCU (DBGMCU) */
Kojto	112:6f327212ef96	1521	/* */
Kojto	112:6f327212ef96	1522	/******************************************************************************/
Kojto	112:6f327212ef96	1523
Kojto	112:6f327212ef96	1524	/************** Bit definition for DBGMCU_IDCODE register ***************/
Kojto	112:6f327212ef96	1525	#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /!< Device Identifier /
Kojto	112:6f327212ef96	1526
Kojto	112:6f327212ef96	1527	#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /!< REV_ID[15:0] bits (Revision Identifier) /
Kojto	112:6f327212ef96	1528	#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /!< Bit 0 /
Kojto	112:6f327212ef96	1529	#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /!< Bit 1 /
Kojto	112:6f327212ef96	1530	#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /!< Bit 2 /
Kojto	112:6f327212ef96	1531	#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /!< Bit 3 /
Kojto	112:6f327212ef96	1532	#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /!< Bit 4 /
Kojto	112:6f327212ef96	1533	#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /!< Bit 5 /
Kojto	112:6f327212ef96	1534	#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /!< Bit 6 /
Kojto	112:6f327212ef96	1535	#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /!< Bit 7 /
Kojto	112:6f327212ef96	1536	#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /!< Bit 8 /
Kojto	112:6f327212ef96	1537	#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /!< Bit 9 /
Kojto	112:6f327212ef96	1538	#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /!< Bit 10 /
Kojto	112:6f327212ef96	1539	#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /!< Bit 11 /
Kojto	112:6f327212ef96	1540	#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /!< Bit 12 /
Kojto	112:6f327212ef96	1541	#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /!< Bit 13 /
Kojto	112:6f327212ef96	1542	#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /!< Bit 14 /
Kojto	112:6f327212ef96	1543	#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /!< Bit 15 /
Kojto	112:6f327212ef96	1544
Kojto	112:6f327212ef96	1545	/**************** Bit definition for DBGMCU_CR register *****************/
Kojto	112:6f327212ef96	1546	#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) /!< Debug Sleep Mode /
Kojto	112:6f327212ef96	1547	#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /!< Debug Stop Mode /
Kojto	112:6f327212ef96	1548	#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /!< Debug Standby mode /
Kojto	112:6f327212ef96	1549	#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) /!< Trace Pin Assignment Control /
Kojto	112:6f327212ef96	1550
Kojto	112:6f327212ef96	1551	#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) /!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) /
Kojto	112:6f327212ef96	1552	#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) /!< Bit 0 /
Kojto	112:6f327212ef96	1553	#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) /!< Bit 1 /
Kojto	112:6f327212ef96	1554
Kojto	112:6f327212ef96	1555	/**************** Bit definition for DBGMCU_APB1_FZ register ************/
Kojto	112:6f327212ef96	1556
Kojto	112:6f327212ef96	1557	#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001) /!< TIM2 counter stopped when core is halted /
Kojto	112:6f327212ef96	1558	#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) /!< TIM3 counter stopped when core is halted /
Kojto	112:6f327212ef96	1559	#define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004) /!< TIM4 counter stopped when core is halted /
Kojto	112:6f327212ef96	1560	#define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008) /!< TIM5 counter stopped when core is halted /
Kojto	112:6f327212ef96	1561	#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010) /!< TIM6 counter stopped when core is halted /
Kojto	112:6f327212ef96	1562	#define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020) /!< TIM7 counter stopped when core is halted /
Kojto	112:6f327212ef96	1563	#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) /!< RTC Counter stopped when Core is halted /
Kojto	112:6f327212ef96	1564	#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) /!< Debug Window Watchdog stopped when Core is halted /
Kojto	112:6f327212ef96	1565	#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) /!< Debug Independent Watchdog stopped when Core is halted /
Kojto	112:6f327212ef96	1566	#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) /!< SMBUS timeout mode stopped when Core is halted /
Kojto	112:6f327212ef96	1567	#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000) /!< SMBUS timeout mode stopped when Core is halted /
Kojto	112:6f327212ef96	1568
Kojto	112:6f327212ef96	1569	/**************** Bit definition for DBGMCU_APB2_FZ register ************/
Kojto	112:6f327212ef96	1570
Kojto	112:6f327212ef96	1571	#define DBGMCU_APB2_FZ_DBG_TIM9_STOP ((uint32_t)0x00000004) /!< TIM9 counter stopped when core is halted /
Kojto	112:6f327212ef96	1572	#define DBGMCU_APB2_FZ_DBG_TIM10_STOP ((uint32_t)0x00000008) /!< TIM10 counter stopped when core is halted /
Kojto	112:6f327212ef96	1573	#define DBGMCU_APB2_FZ_DBG_TIM11_STOP ((uint32_t)0x00000010) /!< TIM11 counter stopped when core is halted /
Kojto	112:6f327212ef96	1574
Kojto	112:6f327212ef96	1575	/******************************************************************************/
Kojto	112:6f327212ef96	1576	/* */
Kojto	112:6f327212ef96	1577	/* DMA Controller (DMA) */
Kojto	112:6f327212ef96	1578	/* */
Kojto	112:6f327212ef96	1579	/******************************************************************************/
Kojto	112:6f327212ef96	1580
Kojto	112:6f327212ef96	1581	/***************** Bit definition for DMA_ISR register ******************/
Kojto	112:6f327212ef96	1582	#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /!< Channel 1 Global interrupt flag /
Kojto	112:6f327212ef96	1583	#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /!< Channel 1 Transfer Complete flag /
Kojto	112:6f327212ef96	1584	#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /!< Channel 1 Half Transfer flag /
Kojto	112:6f327212ef96	1585	#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /!< Channel 1 Transfer Error flag /
Kojto	112:6f327212ef96	1586	#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /!< Channel 2 Global interrupt flag /
Kojto	112:6f327212ef96	1587	#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /!< Channel 2 Transfer Complete flag /
Kojto	112:6f327212ef96	1588	#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /!< Channel 2 Half Transfer flag /
Kojto	112:6f327212ef96	1589	#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /!< Channel 2 Transfer Error flag /
Kojto	112:6f327212ef96	1590	#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /!< Channel 3 Global interrupt flag /
Kojto	112:6f327212ef96	1591	#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /!< Channel 3 Transfer Complete flag /
Kojto	112:6f327212ef96	1592	#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /!< Channel 3 Half Transfer flag /
Kojto	112:6f327212ef96	1593	#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /!< Channel 3 Transfer Error flag /
Kojto	112:6f327212ef96	1594	#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /!< Channel 4 Global interrupt flag /
Kojto	112:6f327212ef96	1595	#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /!< Channel 4 Transfer Complete flag /
Kojto	112:6f327212ef96	1596	#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /!< Channel 4 Half Transfer flag /
Kojto	112:6f327212ef96	1597	#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /!< Channel 4 Transfer Error flag /
Kojto	112:6f327212ef96	1598	#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /!< Channel 5 Global interrupt flag /
Kojto	112:6f327212ef96	1599	#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /!< Channel 5 Transfer Complete flag /
Kojto	112:6f327212ef96	1600	#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /!< Channel 5 Half Transfer flag /
Kojto	112:6f327212ef96	1601	#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /!< Channel 5 Transfer Error flag /
Kojto	112:6f327212ef96	1602	#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /!< Channel 6 Global interrupt flag /
Kojto	112:6f327212ef96	1603	#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /!< Channel 6 Transfer Complete flag /
Kojto	112:6f327212ef96	1604	#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /!< Channel 6 Half Transfer flag /
Kojto	112:6f327212ef96	1605	#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /!< Channel 6 Transfer Error flag /
Kojto	112:6f327212ef96	1606	#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /!< Channel 7 Global interrupt flag /
Kojto	112:6f327212ef96	1607	#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /!< Channel 7 Transfer Complete flag /
Kojto	112:6f327212ef96	1608	#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /!< Channel 7 Half Transfer flag /
Kojto	112:6f327212ef96	1609	#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /!< Channel 7 Transfer Error flag /
Kojto	112:6f327212ef96	1610
Kojto	112:6f327212ef96	1611	/***************** Bit definition for DMA_IFCR register *****************/
Kojto	112:6f327212ef96	1612	#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /!< Channel 1 Global interrupt clear /
Kojto	112:6f327212ef96	1613	#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /!< Channel 1 Transfer Complete clear /
Kojto	112:6f327212ef96	1614	#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /!< Channel 1 Half Transfer clear /
Kojto	112:6f327212ef96	1615	#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /!< Channel 1 Transfer Error clear /
Kojto	112:6f327212ef96	1616	#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /!< Channel 2 Global interrupt clear /
Kojto	112:6f327212ef96	1617	#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /!< Channel 2 Transfer Complete clear /
Kojto	112:6f327212ef96	1618	#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /!< Channel 2 Half Transfer clear /
Kojto	112:6f327212ef96	1619	#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /!< Channel 2 Transfer Error clear /
Kojto	112:6f327212ef96	1620	#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /!< Channel 3 Global interrupt clear /
Kojto	112:6f327212ef96	1621	#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /!< Channel 3 Transfer Complete clear /
Kojto	112:6f327212ef96	1622	#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /!< Channel 3 Half Transfer clear /
Kojto	112:6f327212ef96	1623	#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /!< Channel 3 Transfer Error clear /
Kojto	112:6f327212ef96	1624	#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /!< Channel 4 Global interrupt clear /
Kojto	112:6f327212ef96	1625	#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /!< Channel 4 Transfer Complete clear /
Kojto	112:6f327212ef96	1626	#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /!< Channel 4 Half Transfer clear /
Kojto	112:6f327212ef96	1627	#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /!< Channel 4 Transfer Error clear /
Kojto	112:6f327212ef96	1628	#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /!< Channel 5 Global interrupt clear /
Kojto	112:6f327212ef96	1629	#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /!< Channel 5 Transfer Complete clear /
Kojto	112:6f327212ef96	1630	#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /!< Channel 5 Half Transfer clear /
Kojto	112:6f327212ef96	1631	#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /!< Channel 5 Transfer Error clear /
Kojto	112:6f327212ef96	1632	#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /!< Channel 6 Global interrupt clear /
Kojto	112:6f327212ef96	1633	#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /!< Channel 6 Transfer Complete clear /
Kojto	112:6f327212ef96	1634	#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /!< Channel 6 Half Transfer clear /
Kojto	112:6f327212ef96	1635	#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /!< Channel 6 Transfer Error clear /
Kojto	112:6f327212ef96	1636	#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /!< Channel 7 Global interrupt clear /
Kojto	112:6f327212ef96	1637	#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /!< Channel 7 Transfer Complete clear /
Kojto	112:6f327212ef96	1638	#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /!< Channel 7 Half Transfer clear /
Kojto	112:6f327212ef96	1639	#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /!< Channel 7 Transfer Error clear /
Kojto	112:6f327212ef96	1640
Kojto	112:6f327212ef96	1641	/***************** Bit definition for DMA_CCR register *****************/
Kojto	112:6f327212ef96	1642	#define DMA_CCR_EN ((uint32_t)0x00000001) /!< Channel enable/
Kojto	112:6f327212ef96	1643	#define DMA_CCR_TCIE ((uint32_t)0x00000002) /!< Transfer complete interrupt enable /
Kojto	112:6f327212ef96	1644	#define DMA_CCR_HTIE ((uint32_t)0x00000004) /!< Half Transfer interrupt enable /
Kojto	112:6f327212ef96	1645	#define DMA_CCR_TEIE ((uint32_t)0x00000008) /!< Transfer error interrupt enable /
Kojto	112:6f327212ef96	1646	#define DMA_CCR_DIR ((uint32_t)0x00000010) /!< Data transfer direction /
Kojto	112:6f327212ef96	1647	#define DMA_CCR_CIRC ((uint32_t)0x00000020) /!< Circular mode /
Kojto	112:6f327212ef96	1648	#define DMA_CCR_PINC ((uint32_t)0x00000040) /!< Peripheral increment mode /
Kojto	112:6f327212ef96	1649	#define DMA_CCR_MINC ((uint32_t)0x00000080) /!< Memory increment mode /
Kojto	112:6f327212ef96	1650
Kojto	112:6f327212ef96	1651	#define DMA_CCR_PSIZE ((uint32_t)0x00000300) /!< PSIZE[1:0] bits (Peripheral size) /
Kojto	112:6f327212ef96	1652	#define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /!< Bit 0 /
Kojto	112:6f327212ef96	1653	#define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /!< Bit 1 /
Kojto	112:6f327212ef96	1654
Kojto	112:6f327212ef96	1655	#define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /!< MSIZE[1:0] bits (Memory size) /
Kojto	112:6f327212ef96	1656	#define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /!< Bit 0 /
Kojto	112:6f327212ef96	1657	#define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /!< Bit 1 /
Kojto	112:6f327212ef96	1658
Kojto	112:6f327212ef96	1659	#define DMA_CCR_PL ((uint32_t)0x00003000) /!< PL[1:0] bits(Channel Priority level) /
Kojto	112:6f327212ef96	1660	#define DMA_CCR_PL_0 ((uint32_t)0x00001000) /!< Bit 0 /
Kojto	112:6f327212ef96	1661	#define DMA_CCR_PL_1 ((uint32_t)0x00002000) /!< Bit 1 /
Kojto	112:6f327212ef96	1662
Kojto	112:6f327212ef96	1663	#define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /!< Memory to memory mode /
Kojto	112:6f327212ef96	1664
Kojto	112:6f327212ef96	1665	/**************** Bit definition for DMA_CNDTR1 register ****************/
Kojto	112:6f327212ef96	1666	#define DMA_CNDTR1_NDT ((uint32_t)0x0000FFFF) /!< Number of data to Transfer /
Kojto	112:6f327212ef96	1667
Kojto	112:6f327212ef96	1668	/**************** Bit definition for DMA_CNDTR2 register ****************/
Kojto	112:6f327212ef96	1669	#define DMA_CNDTR2_NDT ((uint32_t)0x0000FFFF) /!< Number of data to Transfer /
Kojto	112:6f327212ef96	1670
Kojto	112:6f327212ef96	1671	/**************** Bit definition for DMA_CNDTR3 register ****************/
Kojto	112:6f327212ef96	1672	#define DMA_CNDTR3_NDT ((uint32_t)0x0000FFFF) /!< Number of data to Transfer /
Kojto	112:6f327212ef96	1673
Kojto	112:6f327212ef96	1674	/**************** Bit definition for DMA_CNDTR4 register ****************/
Kojto	112:6f327212ef96	1675	#define DMA_CNDTR4_NDT ((uint32_t)0x0000FFFF) /!< Number of data to Transfer /
Kojto	112:6f327212ef96	1676
Kojto	112:6f327212ef96	1677	/**************** Bit definition for DMA_CNDTR5 register ****************/
Kojto	112:6f327212ef96	1678	#define DMA_CNDTR5_NDT ((uint32_t)0x0000FFFF) /!< Number of data to Transfer /
Kojto	112:6f327212ef96	1679
Kojto	112:6f327212ef96	1680	/**************** Bit definition for DMA_CNDTR6 register ****************/
Kojto	112:6f327212ef96	1681	#define DMA_CNDTR6_NDT ((uint32_t)0x0000FFFF) /!< Number of data to Transfer /
Kojto	112:6f327212ef96	1682
Kojto	112:6f327212ef96	1683	/**************** Bit definition for DMA_CNDTR7 register ****************/
Kojto	112:6f327212ef96	1684	#define DMA_CNDTR7_NDT ((uint32_t)0x0000FFFF) /!< Number of data to Transfer /
Kojto	112:6f327212ef96	1685
Kojto	112:6f327212ef96	1686	/**************** Bit definition for DMA_CPAR1 register *****************/
Kojto	112:6f327212ef96	1687	#define DMA_CPAR1_PA ((uint32_t)0xFFFFFFFF) /!< Peripheral Address /
Kojto	112:6f327212ef96	1688
Kojto	112:6f327212ef96	1689	/**************** Bit definition for DMA_CPAR2 register *****************/
Kojto	112:6f327212ef96	1690	#define DMA_CPAR2_PA ((uint32_t)0xFFFFFFFF) /!< Peripheral Address /
Kojto	112:6f327212ef96	1691
Kojto	112:6f327212ef96	1692	/**************** Bit definition for DMA_CPAR3 register *****************/
Kojto	112:6f327212ef96	1693	#define DMA_CPAR3_PA ((uint32_t)0xFFFFFFFF) /!< Peripheral Address /
Kojto	112:6f327212ef96	1694
Kojto	112:6f327212ef96	1695
Kojto	112:6f327212ef96	1696	/**************** Bit definition for DMA_CPAR4 register *****************/
Kojto	112:6f327212ef96	1697	#define DMA_CPAR4_PA ((uint32_t)0xFFFFFFFF) /!< Peripheral Address /
Kojto	112:6f327212ef96	1698
Kojto	112:6f327212ef96	1699	/**************** Bit definition for DMA_CPAR5 register *****************/
Kojto	112:6f327212ef96	1700	#define DMA_CPAR5_PA ((uint32_t)0xFFFFFFFF) /!< Peripheral Address /
Kojto	112:6f327212ef96	1701
Kojto	112:6f327212ef96	1702	/**************** Bit definition for DMA_CPAR6 register *****************/
Kojto	112:6f327212ef96	1703	#define DMA_CPAR6_PA ((uint32_t)0xFFFFFFFF) /!< Peripheral Address /
Kojto	112:6f327212ef96	1704
Kojto	112:6f327212ef96	1705
Kojto	112:6f327212ef96	1706	/**************** Bit definition for DMA_CPAR7 register *****************/
Kojto	112:6f327212ef96	1707	#define DMA_CPAR7_PA ((uint32_t)0xFFFFFFFF) /!< Peripheral Address /
Kojto	112:6f327212ef96	1708
Kojto	112:6f327212ef96	1709	/**************** Bit definition for DMA_CMAR1 register *****************/
Kojto	112:6f327212ef96	1710	#define DMA_CMAR1_MA ((uint32_t)0xFFFFFFFF) /!< Memory Address /
Kojto	112:6f327212ef96	1711
Kojto	112:6f327212ef96	1712	/**************** Bit definition for DMA_CMAR2 register *****************/
Kojto	112:6f327212ef96	1713	#define DMA_CMAR2_MA ((uint32_t)0xFFFFFFFF) /!< Memory Address /
Kojto	112:6f327212ef96	1714
Kojto	112:6f327212ef96	1715	/**************** Bit definition for DMA_CMAR3 register *****************/
Kojto	112:6f327212ef96	1716	#define DMA_CMAR3_MA ((uint32_t)0xFFFFFFFF) /!< Memory Address /
Kojto	112:6f327212ef96	1717
Kojto	112:6f327212ef96	1718
Kojto	112:6f327212ef96	1719	/**************** Bit definition for DMA_CMAR4 register *****************/
Kojto	112:6f327212ef96	1720	#define DMA_CMAR4_MA ((uint32_t)0xFFFFFFFF) /!< Memory Address /
Kojto	112:6f327212ef96	1721
Kojto	112:6f327212ef96	1722	/**************** Bit definition for DMA_CMAR5 register *****************/
Kojto	112:6f327212ef96	1723	#define DMA_CMAR5_MA ((uint32_t)0xFFFFFFFF) /!< Memory Address /
Kojto	112:6f327212ef96	1724
Kojto	112:6f327212ef96	1725	/**************** Bit definition for DMA_CMAR6 register *****************/
Kojto	112:6f327212ef96	1726	#define DMA_CMAR6_MA ((uint32_t)0xFFFFFFFF) /!< Memory Address /
Kojto	112:6f327212ef96	1727
Kojto	112:6f327212ef96	1728	/**************** Bit definition for DMA_CMAR7 register *****************/
Kojto	112:6f327212ef96	1729	#define DMA_CMAR7_MA ((uint32_t)0xFFFFFFFF) /!< Memory Address /
Kojto	112:6f327212ef96	1730
Kojto	112:6f327212ef96	1731	/******************************************************************************/
Kojto	112:6f327212ef96	1732	/* */
Kojto	112:6f327212ef96	1733	/* External Interrupt/Event Controller (EXTI) */
Kojto	112:6f327212ef96	1734	/* */
Kojto	112:6f327212ef96	1735	/******************************************************************************/
Kojto	112:6f327212ef96	1736
Kojto	112:6f327212ef96	1737	/***************** Bit definition for EXTI_IMR register *****************/
Kojto	112:6f327212ef96	1738	#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /!< Interrupt Mask on line 0 /
Kojto	112:6f327212ef96	1739	#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /!< Interrupt Mask on line 1 /
Kojto	112:6f327212ef96	1740	#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /!< Interrupt Mask on line 2 /
Kojto	112:6f327212ef96	1741	#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /!< Interrupt Mask on line 3 /
Kojto	112:6f327212ef96	1742	#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /!< Interrupt Mask on line 4 /
Kojto	112:6f327212ef96	1743	#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /!< Interrupt Mask on line 5 /
Kojto	112:6f327212ef96	1744	#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /!< Interrupt Mask on line 6 /
Kojto	112:6f327212ef96	1745	#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /!< Interrupt Mask on line 7 /
Kojto	112:6f327212ef96	1746	#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /!< Interrupt Mask on line 8 /
Kojto	112:6f327212ef96	1747	#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /!< Interrupt Mask on line 9 /
Kojto	112:6f327212ef96	1748	#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /!< Interrupt Mask on line 10 /
Kojto	112:6f327212ef96	1749	#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /!< Interrupt Mask on line 11 /
Kojto	112:6f327212ef96	1750	#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /!< Interrupt Mask on line 12 /
Kojto	112:6f327212ef96	1751	#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /!< Interrupt Mask on line 13 /
Kojto	112:6f327212ef96	1752	#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /!< Interrupt Mask on line 14 /
Kojto	112:6f327212ef96	1753	#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /!< Interrupt Mask on line 15 /
Kojto	112:6f327212ef96	1754	#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /!< Interrupt Mask on line 16 /
Kojto	112:6f327212ef96	1755	#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /!< Interrupt Mask on line 17 /
Kojto	112:6f327212ef96	1756	#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /!< Interrupt Mask on line 18 /
Kojto	112:6f327212ef96	1757	#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /!< Interrupt Mask on line 19 /
Kojto	112:6f327212ef96	1758	#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /!< Interrupt Mask on line 20 /
Kojto	112:6f327212ef96	1759	#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /!< Interrupt Mask on line 21 /
Kojto	112:6f327212ef96	1760	#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /!< Interrupt Mask on line 22 /
Kojto	112:6f327212ef96	1761	#define EXTI_IMR_MR23 ((uint32_t)0x00800000) /!< Interrupt Mask on line 23 /
Kojto	112:6f327212ef96	1762
Kojto	112:6f327212ef96	1763	/***************** Bit definition for EXTI_EMR register *****************/
Kojto	112:6f327212ef96	1764	#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /!< Event Mask on line 0 /
Kojto	112:6f327212ef96	1765	#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /!< Event Mask on line 1 /
Kojto	112:6f327212ef96	1766	#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /!< Event Mask on line 2 /
Kojto	112:6f327212ef96	1767	#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /!< Event Mask on line 3 /
Kojto	112:6f327212ef96	1768	#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /!< Event Mask on line 4 /
Kojto	112:6f327212ef96	1769	#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /!< Event Mask on line 5 /
Kojto	112:6f327212ef96	1770	#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /!< Event Mask on line 6 /
Kojto	112:6f327212ef96	1771	#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /!< Event Mask on line 7 /
Kojto	112:6f327212ef96	1772	#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /!< Event Mask on line 8 /
Kojto	112:6f327212ef96	1773	#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /!< Event Mask on line 9 /
Kojto	112:6f327212ef96	1774	#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /!< Event Mask on line 10 /
Kojto	112:6f327212ef96	1775	#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /!< Event Mask on line 11 /
Kojto	112:6f327212ef96	1776	#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /!< Event Mask on line 12 /
Kojto	112:6f327212ef96	1777	#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /!< Event Mask on line 13 /
Kojto	112:6f327212ef96	1778	#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /!< Event Mask on line 14 /
Kojto	112:6f327212ef96	1779	#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /!< Event Mask on line 15 /
Kojto	112:6f327212ef96	1780	#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /!< Event Mask on line 16 /
Kojto	112:6f327212ef96	1781	#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /!< Event Mask on line 17 /
Kojto	112:6f327212ef96	1782	#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /!< Event Mask on line 18 /
Kojto	112:6f327212ef96	1783	#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /!< Event Mask on line 19 /
Kojto	112:6f327212ef96	1784	#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /!< Event Mask on line 20 /
Kojto	112:6f327212ef96	1785	#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /!< Event Mask on line 21 /
Kojto	112:6f327212ef96	1786	#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /!< Event Mask on line 22 /
Kojto	112:6f327212ef96	1787	#define EXTI_EMR_MR23 ((uint32_t)0x00800000) /!< Event Mask on line 23 /
Kojto	112:6f327212ef96	1788
Kojto	112:6f327212ef96	1789	/**************** Bit definition for EXTI_RTSR register *****************/
Kojto	112:6f327212ef96	1790	#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /!< Rising trigger event configuration bit of line 0 /
Kojto	112:6f327212ef96	1791	#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /!< Rising trigger event configuration bit of line 1 /
Kojto	112:6f327212ef96	1792	#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /!< Rising trigger event configuration bit of line 2 /
Kojto	112:6f327212ef96	1793	#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /!< Rising trigger event configuration bit of line 3 /
Kojto	112:6f327212ef96	1794	#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /!< Rising trigger event configuration bit of line 4 /
Kojto	112:6f327212ef96	1795	#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /!< Rising trigger event configuration bit of line 5 /
Kojto	112:6f327212ef96	1796	#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /!< Rising trigger event configuration bit of line 6 /
Kojto	112:6f327212ef96	1797	#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /!< Rising trigger event configuration bit of line 7 /
Kojto	112:6f327212ef96	1798	#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /!< Rising trigger event configuration bit of line 8 /
Kojto	112:6f327212ef96	1799	#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /!< Rising trigger event configuration bit of line 9 /
Kojto	112:6f327212ef96	1800	#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /!< Rising trigger event configuration bit of line 10 /
Kojto	112:6f327212ef96	1801	#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /!< Rising trigger event configuration bit of line 11 /
Kojto	112:6f327212ef96	1802	#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /!< Rising trigger event configuration bit of line 12 /
Kojto	112:6f327212ef96	1803	#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /!< Rising trigger event configuration bit of line 13 /
Kojto	112:6f327212ef96	1804	#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /!< Rising trigger event configuration bit of line 14 /
Kojto	112:6f327212ef96	1805	#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /!< Rising trigger event configuration bit of line 15 /
Kojto	112:6f327212ef96	1806	#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /!< Rising trigger event configuration bit of line 16 /
Kojto	112:6f327212ef96	1807	#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /!< Rising trigger event configuration bit of line 17 /
Kojto	112:6f327212ef96	1808	#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /!< Rising trigger event configuration bit of line 18 /
Kojto	112:6f327212ef96	1809	#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /!< Rising trigger event configuration bit of line 19 /
Kojto	112:6f327212ef96	1810	#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /!< Rising trigger event configuration bit of line 20 /
Kojto	112:6f327212ef96	1811	#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /!< Rising trigger event configuration bit of line 21 /
Kojto	112:6f327212ef96	1812	#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /!< Rising trigger event configuration bit of line 22 /
Kojto	112:6f327212ef96	1813	#define EXTI_RTSR_TR23 ((uint32_t)0x00800000) /!< Rising trigger event configuration bit of line 23 /
Kojto	112:6f327212ef96	1814
Kojto	112:6f327212ef96	1815	/**************** Bit definition for EXTI_FTSR register *****************/
Kojto	112:6f327212ef96	1816	#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /!< Falling trigger event configuration bit of line 0 /
Kojto	112:6f327212ef96	1817	#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /!< Falling trigger event configuration bit of line 1 /
Kojto	112:6f327212ef96	1818	#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /!< Falling trigger event configuration bit of line 2 /
Kojto	112:6f327212ef96	1819	#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /!< Falling trigger event configuration bit of line 3 /
Kojto	112:6f327212ef96	1820	#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /!< Falling trigger event configuration bit of line 4 /
Kojto	112:6f327212ef96	1821	#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /!< Falling trigger event configuration bit of line 5 /
Kojto	112:6f327212ef96	1822	#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /!< Falling trigger event configuration bit of line 6 /
Kojto	112:6f327212ef96	1823	#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /!< Falling trigger event configuration bit of line 7 /
Kojto	112:6f327212ef96	1824	#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /!< Falling trigger event configuration bit of line 8 /
Kojto	112:6f327212ef96	1825	#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /!< Falling trigger event configuration bit of line 9 /
Kojto	112:6f327212ef96	1826	#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /!< Falling trigger event configuration bit of line 10 /
Kojto	112:6f327212ef96	1827	#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /!< Falling trigger event configuration bit of line 11 /
Kojto	112:6f327212ef96	1828	#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /!< Falling trigger event configuration bit of line 12 /
Kojto	112:6f327212ef96	1829	#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /!< Falling trigger event configuration bit of line 13 /
Kojto	112:6f327212ef96	1830	#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /!< Falling trigger event configuration bit of line 14 /
Kojto	112:6f327212ef96	1831	#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /!< Falling trigger event configuration bit of line 15 /
Kojto	112:6f327212ef96	1832	#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /!< Falling trigger event configuration bit of line 16 /
Kojto	112:6f327212ef96	1833	#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /!< Falling trigger event configuration bit of line 17 /
Kojto	112:6f327212ef96	1834	#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /!< Falling trigger event configuration bit of line 18 /
Kojto	112:6f327212ef96	1835	#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /!< Falling trigger event configuration bit of line 19 /
Kojto	112:6f327212ef96	1836	#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /!< Falling trigger event configuration bit of line 20 /
Kojto	112:6f327212ef96	1837	#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /!< Falling trigger event configuration bit of line 21 /
Kojto	112:6f327212ef96	1838	#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /!< Falling trigger event configuration bit of line 22 /
Kojto	112:6f327212ef96	1839	#define EXTI_FTSR_TR23 ((uint32_t)0x00800000) /!< Falling trigger event configuration bit of line 23 /
Kojto	112:6f327212ef96	1840
Kojto	112:6f327212ef96	1841	/**************** Bit definition for EXTI_SWIER register ****************/
Kojto	112:6f327212ef96	1842	#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /!< Software Interrupt on line 0 /
Kojto	112:6f327212ef96	1843	#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /!< Software Interrupt on line 1 /
Kojto	112:6f327212ef96	1844	#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /!< Software Interrupt on line 2 /
Kojto	112:6f327212ef96	1845	#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /!< Software Interrupt on line 3 /
Kojto	112:6f327212ef96	1846	#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /!< Software Interrupt on line 4 /
Kojto	112:6f327212ef96	1847	#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /!< Software Interrupt on line 5 /
Kojto	112:6f327212ef96	1848	#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /!< Software Interrupt on line 6 /
Kojto	112:6f327212ef96	1849	#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /!< Software Interrupt on line 7 /
Kojto	112:6f327212ef96	1850	#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /!< Software Interrupt on line 8 /
Kojto	112:6f327212ef96	1851	#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /!< Software Interrupt on line 9 /
Kojto	112:6f327212ef96	1852	#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /!< Software Interrupt on line 10 /
Kojto	112:6f327212ef96	1853	#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /!< Software Interrupt on line 11 /
Kojto	112:6f327212ef96	1854	#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /!< Software Interrupt on line 12 /
Kojto	112:6f327212ef96	1855	#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /!< Software Interrupt on line 13 /
Kojto	112:6f327212ef96	1856	#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /!< Software Interrupt on line 14 /
Kojto	112:6f327212ef96	1857	#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /!< Software Interrupt on line 15 /
Kojto	112:6f327212ef96	1858	#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /!< Software Interrupt on line 16 /
Kojto	112:6f327212ef96	1859	#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /!< Software Interrupt on line 17 /
Kojto	112:6f327212ef96	1860	#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /!< Software Interrupt on line 18 /
Kojto	112:6f327212ef96	1861	#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /!< Software Interrupt on line 19 /
Kojto	112:6f327212ef96	1862	#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /!< Software Interrupt on line 20 /
Kojto	112:6f327212ef96	1863	#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /!< Software Interrupt on line 21 /
Kojto	112:6f327212ef96	1864	#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /!< Software Interrupt on line 22 /
Kojto	112:6f327212ef96	1865	#define EXTI_SWIER_SWIER23 ((uint32_t)0x00800000) /!< Software Interrupt on line 23 /
Kojto	112:6f327212ef96	1866
Kojto	112:6f327212ef96	1867	/***************** Bit definition for EXTI_PR register ******************/
Kojto	112:6f327212ef96	1868	#define EXTI_PR_PR0 ((uint32_t)0x00000001) /!< Pending bit 0 /
Kojto	112:6f327212ef96	1869	#define EXTI_PR_PR1 ((uint32_t)0x00000002) /!< Pending bit 1 /
Kojto	112:6f327212ef96	1870	#define EXTI_PR_PR2 ((uint32_t)0x00000004) /!< Pending bit 2 /
Kojto	112:6f327212ef96	1871	#define EXTI_PR_PR3 ((uint32_t)0x00000008) /!< Pending bit 3 /
Kojto	112:6f327212ef96	1872	#define EXTI_PR_PR4 ((uint32_t)0x00000010) /!< Pending bit 4 /
Kojto	112:6f327212ef96	1873	#define EXTI_PR_PR5 ((uint32_t)0x00000020) /!< Pending bit 5 /
Kojto	112:6f327212ef96	1874	#define EXTI_PR_PR6 ((uint32_t)0x00000040) /!< Pending bit 6 /
Kojto	112:6f327212ef96	1875	#define EXTI_PR_PR7 ((uint32_t)0x00000080) /!< Pending bit 7 /
Kojto	112:6f327212ef96	1876	#define EXTI_PR_PR8 ((uint32_t)0x00000100) /!< Pending bit 8 /
Kojto	112:6f327212ef96	1877	#define EXTI_PR_PR9 ((uint32_t)0x00000200) /!< Pending bit 9 /
Kojto	112:6f327212ef96	1878	#define EXTI_PR_PR10 ((uint32_t)0x00000400) /!< Pending bit 10 /
Kojto	112:6f327212ef96	1879	#define EXTI_PR_PR11 ((uint32_t)0x00000800) /!< Pending bit 11 /
Kojto	112:6f327212ef96	1880	#define EXTI_PR_PR12 ((uint32_t)0x00001000) /!< Pending bit 12 /
Kojto	112:6f327212ef96	1881	#define EXTI_PR_PR13 ((uint32_t)0x00002000) /!< Pending bit 13 /
Kojto	112:6f327212ef96	1882	#define EXTI_PR_PR14 ((uint32_t)0x00004000) /!< Pending bit 14 /
Kojto	112:6f327212ef96	1883	#define EXTI_PR_PR15 ((uint32_t)0x00008000) /!< Pending bit 15 /
Kojto	112:6f327212ef96	1884	#define EXTI_PR_PR16 ((uint32_t)0x00010000) /!< Pending bit 16 /
Kojto	112:6f327212ef96	1885	#define EXTI_PR_PR17 ((uint32_t)0x00020000) /!< Pending bit 17 /
Kojto	112:6f327212ef96	1886	#define EXTI_PR_PR18 ((uint32_t)0x00040000) /!< Pending bit 18 /
Kojto	112:6f327212ef96	1887	#define EXTI_PR_PR19 ((uint32_t)0x00080000) /!< Pending bit 19 /
Kojto	112:6f327212ef96	1888	#define EXTI_PR_PR20 ((uint32_t)0x00100000) /!< Pending bit 20 /
Kojto	112:6f327212ef96	1889	#define EXTI_PR_PR21 ((uint32_t)0x00200000) /!< Pending bit 21 /
Kojto	112:6f327212ef96	1890	#define EXTI_PR_PR22 ((uint32_t)0x00400000) /!< Pending bit 22 /
Kojto	112:6f327212ef96	1891	#define EXTI_PR_PR23 ((uint32_t)0x00800000) /!< Pending bit 23 /
Kojto	112:6f327212ef96	1892
Kojto	112:6f327212ef96	1893	/******************************************************************************/
Kojto	112:6f327212ef96	1894	/* */
Kojto	112:6f327212ef96	1895	/* FLASH, DATA EEPROM and Option Bytes Registers */
Kojto	112:6f327212ef96	1896	/* (FLASH, DATA_EEPROM, OB) */
Kojto	112:6f327212ef96	1897	/* */
Kojto	112:6f327212ef96	1898	/******************************************************************************/
Kojto	112:6f327212ef96	1899
Kojto	112:6f327212ef96	1900	/***************** Bit definition for FLASH_ACR register ****************/
Kojto	112:6f327212ef96	1901	#define FLASH_ACR_LATENCY ((uint32_t)0x00000001) /!< Latency /
Kojto	112:6f327212ef96	1902	#define FLASH_ACR_PRFTEN ((uint32_t)0x00000002) /!< Prefetch Buffer Enable /
Kojto	112:6f327212ef96	1903	#define FLASH_ACR_ACC64 ((uint32_t)0x00000004) /!< Access 64 bits /
Kojto	112:6f327212ef96	1904	#define FLASH_ACR_SLEEP_PD ((uint32_t)0x00000008) /!< Flash mode during sleep mode /
Kojto	112:6f327212ef96	1905	#define FLASH_ACR_RUN_PD ((uint32_t)0x00000010) /!< Flash mode during RUN mode /
Kojto	112:6f327212ef96	1906
Kojto	112:6f327212ef96	1907	/***************** Bit definition for FLASH_PECR register ****************/
Kojto	112:6f327212ef96	1908	#define FLASH_PECR_PELOCK ((uint32_t)0x00000001) /!< FLASH_PECR and Flash data Lock /
Kojto	112:6f327212ef96	1909	#define FLASH_PECR_PRGLOCK ((uint32_t)0x00000002) /!< Program matrix Lock /
Kojto	112:6f327212ef96	1910	#define FLASH_PECR_OPTLOCK ((uint32_t)0x00000004) /!< Option byte matrix Lock /
Kojto	112:6f327212ef96	1911	#define FLASH_PECR_PROG ((uint32_t)0x00000008) /!< Program matrix selection /
Kojto	112:6f327212ef96	1912	#define FLASH_PECR_DATA ((uint32_t)0x00000010) /!< Data matrix selection /
Kojto	112:6f327212ef96	1913	#define FLASH_PECR_FTDW ((uint32_t)0x00000100) /!< Fixed Time Data write for Word/Half Word/Byte programming /
Kojto	112:6f327212ef96	1914	#define FLASH_PECR_ERASE ((uint32_t)0x00000200) /!< Page erasing mode /
Kojto	112:6f327212ef96	1915	#define FLASH_PECR_FPRG ((uint32_t)0x00000400) /!< Fast Page/Half Page programming mode /
Kojto	112:6f327212ef96	1916	#define FLASH_PECR_EOPIE ((uint32_t)0x00010000) /!< End of programming interrupt /
Kojto	112:6f327212ef96	1917	#define FLASH_PECR_ERRIE ((uint32_t)0x00020000) /!< Error interrupt /
Kojto	112:6f327212ef96	1918	#define FLASH_PECR_OBL_LAUNCH ((uint32_t)0x00040000) /!< Launch the option byte loading /
Kojto	112:6f327212ef96	1919
Kojto	112:6f327212ef96	1920	/**************** Bit definition for FLASH_PDKEYR register ****************/
Kojto	112:6f327212ef96	1921	#define FLASH_PDKEYR_PDKEYR ((uint32_t)0xFFFFFFFF) /!< FLASH_PEC and data matrix Key /
Kojto	112:6f327212ef96	1922
Kojto	112:6f327212ef96	1923	/**************** Bit definition for FLASH_PEKEYR register ****************/
Kojto	112:6f327212ef96	1924	#define FLASH_PEKEYR_PEKEYR ((uint32_t)0xFFFFFFFF) /!< FLASH_PEC and data matrix Key /
Kojto	112:6f327212ef96	1925
Kojto	112:6f327212ef96	1926	/**************** Bit definition for FLASH_PRGKEYR register ****************/
Kojto	112:6f327212ef96	1927	#define FLASH_PRGKEYR_PRGKEYR ((uint32_t)0xFFFFFFFF) /!< Program matrix Key /
Kojto	112:6f327212ef96	1928
Kojto	112:6f327212ef96	1929	/**************** Bit definition for FLASH_OPTKEYR register ****************/
Kojto	112:6f327212ef96	1930	#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /!< Option bytes matrix Key /
Kojto	112:6f327212ef96	1931
Kojto	112:6f327212ef96	1932	/**************** Bit definition for FLASH_SR register *****************/
Kojto	112:6f327212ef96	1933	#define FLASH_SR_BSY ((uint32_t)0x00000001) /!< Busy /
Kojto	112:6f327212ef96	1934	#define FLASH_SR_EOP ((uint32_t)0x00000002) /!< End Of Programming/
Kojto	112:6f327212ef96	1935	#define FLASH_SR_ENDHV ((uint32_t)0x00000004) /!< End of high voltage /
Kojto	112:6f327212ef96	1936	#define FLASH_SR_READY ((uint32_t)0x00000008) /!< Flash ready after low power mode /
Kojto	112:6f327212ef96	1937
Kojto	112:6f327212ef96	1938	#define FLASH_SR_WRPERR ((uint32_t)0x00000100) /!< Write protected error /
Kojto	112:6f327212ef96	1939	#define FLASH_SR_PGAERR ((uint32_t)0x00000200) /!< Programming Alignment Error /
Kojto	112:6f327212ef96	1940	#define FLASH_SR_SIZERR ((uint32_t)0x00000400) /!< Size error /
Kojto	112:6f327212ef96	1941	#define FLASH_SR_OPTVERR ((uint32_t)0x00000800) /!< Option validity error /
Kojto	112:6f327212ef96	1942	#define FLASH_SR_OPTVERRUSR ((uint32_t)0x00001000) /!< Option User validity error /
Kojto	112:6f327212ef96	1943	#define FLASH_SR_RDERR ((uint32_t)0x00002000) /!< Read protected error /
Kojto	112:6f327212ef96	1944
Kojto	112:6f327212ef96	1945	/**************** Bit definition for FLASH_OBR register *****************/
Kojto	112:6f327212ef96	1946	#define FLASH_OBR_RDPRT ((uint32_t)0x000000FF) /!< Read Protection /
Kojto	112:6f327212ef96	1947	#define FLASH_OBR_SPRMOD ((uint32_t)0x00000100) /!< Selection of protection mode of WPRi bits /
Kojto	112:6f327212ef96	1948	#define FLASH_OBR_BOR_LEV ((uint32_t)0x000F0000) /!< BOR_LEV[3:0] Brown Out Reset Threshold Level/
Kojto	112:6f327212ef96	1949	#define FLASH_OBR_USER ((uint32_t)0x00700000) /!< User Option Bytes /
Kojto	112:6f327212ef96	1950	#define FLASH_OBR_IWDG_SW ((uint32_t)0x00100000) /!< IWDG_SW /
Kojto	112:6f327212ef96	1951	#define FLASH_OBR_nRST_STOP ((uint32_t)0x00200000) /!< nRST_STOP /
Kojto	112:6f327212ef96	1952	#define FLASH_OBR_nRST_STDBY ((uint32_t)0x00400000) /!< nRST_STDBY /
Kojto	112:6f327212ef96	1953
Kojto	112:6f327212ef96	1954	/**************** Bit definition for FLASH_WRPR register ****************/
Kojto	112:6f327212ef96	1955	#define FLASH_WRPR1_WRP ((uint32_t)0xFFFFFFFF) /!< Write Protect /
Kojto	112:6f327212ef96	1956	#define FLASH_WRPR2_WRP ((uint32_t)0xFFFFFFFF) /!< Write Protect /
Kojto	112:6f327212ef96	1957
Kojto	112:6f327212ef96	1958	/******************************************************************************/
Kojto	112:6f327212ef96	1959	/* */
Kojto	112:6f327212ef96	1960	/* General Purpose I/O */
Kojto	112:6f327212ef96	1961	/* */
Kojto	112:6f327212ef96	1962	/******************************************************************************/
Kojto	112:6f327212ef96	1963	/**************** Bits definition for GPIO_MODER register ***************/
Kojto	112:6f327212ef96	1964	#define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
Kojto	112:6f327212ef96	1965	#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
Kojto	112:6f327212ef96	1966	#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
Kojto	112:6f327212ef96	1967
Kojto	112:6f327212ef96	1968	#define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
Kojto	112:6f327212ef96	1969	#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
Kojto	112:6f327212ef96	1970	#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
Kojto	112:6f327212ef96	1971
Kojto	112:6f327212ef96	1972	#define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
Kojto	112:6f327212ef96	1973	#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
Kojto	112:6f327212ef96	1974	#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
Kojto	112:6f327212ef96	1975
Kojto	112:6f327212ef96	1976	#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
Kojto	112:6f327212ef96	1977	#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
Kojto	112:6f327212ef96	1978	#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
Kojto	112:6f327212ef96	1979
Kojto	112:6f327212ef96	1980	#define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
Kojto	112:6f327212ef96	1981	#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
Kojto	112:6f327212ef96	1982	#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
Kojto	112:6f327212ef96	1983
Kojto	112:6f327212ef96	1984	#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
Kojto	112:6f327212ef96	1985	#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
Kojto	112:6f327212ef96	1986	#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
Kojto	112:6f327212ef96	1987
Kojto	112:6f327212ef96	1988	#define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
Kojto	112:6f327212ef96	1989	#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
Kojto	112:6f327212ef96	1990	#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
Kojto	112:6f327212ef96	1991
Kojto	112:6f327212ef96	1992	#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
Kojto	112:6f327212ef96	1993	#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
Kojto	112:6f327212ef96	1994	#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
Kojto	112:6f327212ef96	1995
Kojto	112:6f327212ef96	1996	#define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
Kojto	112:6f327212ef96	1997	#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
Kojto	112:6f327212ef96	1998	#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
Kojto	112:6f327212ef96	1999
Kojto	112:6f327212ef96	2000	#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
Kojto	112:6f327212ef96	2001	#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
Kojto	112:6f327212ef96	2002	#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
Kojto	112:6f327212ef96	2003
Kojto	112:6f327212ef96	2004	#define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
Kojto	112:6f327212ef96	2005	#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
Kojto	112:6f327212ef96	2006	#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
Kojto	112:6f327212ef96	2007
Kojto	112:6f327212ef96	2008	#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
Kojto	112:6f327212ef96	2009	#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
Kojto	112:6f327212ef96	2010	#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
Kojto	112:6f327212ef96	2011
Kojto	112:6f327212ef96	2012	#define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
Kojto	112:6f327212ef96	2013	#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
Kojto	112:6f327212ef96	2014	#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
Kojto	112:6f327212ef96	2015
Kojto	112:6f327212ef96	2016	#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
Kojto	112:6f327212ef96	2017	#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
Kojto	112:6f327212ef96	2018	#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
Kojto	112:6f327212ef96	2019
Kojto	112:6f327212ef96	2020	#define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
Kojto	112:6f327212ef96	2021	#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
Kojto	112:6f327212ef96	2022	#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
Kojto	112:6f327212ef96	2023
Kojto	112:6f327212ef96	2024	#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
Kojto	112:6f327212ef96	2025	#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
Kojto	112:6f327212ef96	2026	#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
Kojto	112:6f327212ef96	2027
Kojto	112:6f327212ef96	2028	/**************** Bits definition for GPIO_OTYPER register **************/
Kojto	112:6f327212ef96	2029	#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
Kojto	112:6f327212ef96	2030	#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
Kojto	112:6f327212ef96	2031	#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
Kojto	112:6f327212ef96	2032	#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
Kojto	112:6f327212ef96	2033	#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
Kojto	112:6f327212ef96	2034	#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
Kojto	112:6f327212ef96	2035	#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
Kojto	112:6f327212ef96	2036	#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
Kojto	112:6f327212ef96	2037	#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
Kojto	112:6f327212ef96	2038	#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
Kojto	112:6f327212ef96	2039	#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
Kojto	112:6f327212ef96	2040	#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
Kojto	112:6f327212ef96	2041	#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
Kojto	112:6f327212ef96	2042	#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
Kojto	112:6f327212ef96	2043	#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
Kojto	112:6f327212ef96	2044	#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
Kojto	112:6f327212ef96	2045
Kojto	112:6f327212ef96	2046	/**************** Bits definition for GPIO_OSPEEDR register *************/
Kojto	112:6f327212ef96	2047	#define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
Kojto	112:6f327212ef96	2048	#define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
Kojto	112:6f327212ef96	2049	#define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
Kojto	112:6f327212ef96	2050
Kojto	112:6f327212ef96	2051	#define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
Kojto	112:6f327212ef96	2052	#define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
Kojto	112:6f327212ef96	2053	#define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
Kojto	112:6f327212ef96	2054
Kojto	112:6f327212ef96	2055	#define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
Kojto	112:6f327212ef96	2056	#define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
Kojto	112:6f327212ef96	2057	#define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
Kojto	112:6f327212ef96	2058
Kojto	112:6f327212ef96	2059	#define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
Kojto	112:6f327212ef96	2060	#define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
Kojto	112:6f327212ef96	2061	#define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
Kojto	112:6f327212ef96	2062
Kojto	112:6f327212ef96	2063	#define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
Kojto	112:6f327212ef96	2064	#define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
Kojto	112:6f327212ef96	2065	#define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
Kojto	112:6f327212ef96	2066
Kojto	112:6f327212ef96	2067	#define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
Kojto	112:6f327212ef96	2068	#define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
Kojto	112:6f327212ef96	2069	#define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
Kojto	112:6f327212ef96	2070
Kojto	112:6f327212ef96	2071	#define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
Kojto	112:6f327212ef96	2072	#define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
Kojto	112:6f327212ef96	2073	#define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
Kojto	112:6f327212ef96	2074
Kojto	112:6f327212ef96	2075	#define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
Kojto	112:6f327212ef96	2076	#define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
Kojto	112:6f327212ef96	2077	#define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
Kojto	112:6f327212ef96	2078
Kojto	112:6f327212ef96	2079	#define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
Kojto	112:6f327212ef96	2080	#define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
Kojto	112:6f327212ef96	2081	#define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
Kojto	112:6f327212ef96	2082
Kojto	112:6f327212ef96	2083	#define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
Kojto	112:6f327212ef96	2084	#define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
Kojto	112:6f327212ef96	2085	#define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
Kojto	112:6f327212ef96	2086
Kojto	112:6f327212ef96	2087	#define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
Kojto	112:6f327212ef96	2088	#define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
Kojto	112:6f327212ef96	2089	#define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
Kojto	112:6f327212ef96	2090
Kojto	112:6f327212ef96	2091	#define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
Kojto	112:6f327212ef96	2092	#define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
Kojto	112:6f327212ef96	2093	#define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
Kojto	112:6f327212ef96	2094
Kojto	112:6f327212ef96	2095	#define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
Kojto	112:6f327212ef96	2096	#define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
Kojto	112:6f327212ef96	2097	#define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
Kojto	112:6f327212ef96	2098
Kojto	112:6f327212ef96	2099	#define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
Kojto	112:6f327212ef96	2100	#define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
Kojto	112:6f327212ef96	2101	#define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
Kojto	112:6f327212ef96	2102
Kojto	112:6f327212ef96	2103	#define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
Kojto	112:6f327212ef96	2104	#define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
Kojto	112:6f327212ef96	2105	#define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
Kojto	112:6f327212ef96	2106
Kojto	112:6f327212ef96	2107	#define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
Kojto	112:6f327212ef96	2108	#define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
Kojto	112:6f327212ef96	2109	#define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
Kojto	112:6f327212ef96	2110
Kojto	112:6f327212ef96	2111	/**************** Bits definition for GPIO_PUPDR register ***************/
Kojto	112:6f327212ef96	2112	#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
Kojto	112:6f327212ef96	2113	#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
Kojto	112:6f327212ef96	2114	#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
Kojto	112:6f327212ef96	2115
Kojto	112:6f327212ef96	2116	#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
Kojto	112:6f327212ef96	2117	#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
Kojto	112:6f327212ef96	2118	#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
Kojto	112:6f327212ef96	2119
Kojto	112:6f327212ef96	2120	#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
Kojto	112:6f327212ef96	2121	#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
Kojto	112:6f327212ef96	2122	#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
Kojto	112:6f327212ef96	2123
Kojto	112:6f327212ef96	2124	#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
Kojto	112:6f327212ef96	2125	#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
Kojto	112:6f327212ef96	2126	#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
Kojto	112:6f327212ef96	2127
Kojto	112:6f327212ef96	2128	#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
Kojto	112:6f327212ef96	2129	#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
Kojto	112:6f327212ef96	2130	#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
Kojto	112:6f327212ef96	2131
Kojto	112:6f327212ef96	2132	#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
Kojto	112:6f327212ef96	2133	#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
Kojto	112:6f327212ef96	2134	#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
Kojto	112:6f327212ef96	2135
Kojto	112:6f327212ef96	2136	#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
Kojto	112:6f327212ef96	2137	#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
Kojto	112:6f327212ef96	2138	#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
Kojto	112:6f327212ef96	2139
Kojto	112:6f327212ef96	2140	#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
Kojto	112:6f327212ef96	2141	#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
Kojto	112:6f327212ef96	2142	#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
Kojto	112:6f327212ef96	2143
Kojto	112:6f327212ef96	2144	#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
Kojto	112:6f327212ef96	2145	#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
Kojto	112:6f327212ef96	2146	#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
Kojto	112:6f327212ef96	2147
Kojto	112:6f327212ef96	2148	#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
Kojto	112:6f327212ef96	2149	#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
Kojto	112:6f327212ef96	2150	#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
Kojto	112:6f327212ef96	2151
Kojto	112:6f327212ef96	2152	#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
Kojto	112:6f327212ef96	2153	#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
Kojto	112:6f327212ef96	2154	#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
Kojto	112:6f327212ef96	2155
Kojto	112:6f327212ef96	2156	#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
Kojto	112:6f327212ef96	2157	#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
Kojto	112:6f327212ef96	2158	#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
Kojto	112:6f327212ef96	2159
Kojto	112:6f327212ef96	2160	#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
Kojto	112:6f327212ef96	2161	#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
Kojto	112:6f327212ef96	2162	#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
Kojto	112:6f327212ef96	2163
Kojto	112:6f327212ef96	2164	#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
Kojto	112:6f327212ef96	2165	#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
Kojto	112:6f327212ef96	2166	#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
Kojto	112:6f327212ef96	2167
Kojto	112:6f327212ef96	2168	#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
Kojto	112:6f327212ef96	2169	#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
Kojto	112:6f327212ef96	2170	#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
Kojto	112:6f327212ef96	2171	#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
Kojto	112:6f327212ef96	2172	#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
Kojto	112:6f327212ef96	2173	#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
Kojto	112:6f327212ef96	2174
Kojto	112:6f327212ef96	2175	/**************** Bits definition for GPIO_IDR register *****************/
Kojto	112:6f327212ef96	2176	#define GPIO_IDR_IDR_0 ((uint32_t)0x00000001)
Kojto	112:6f327212ef96	2177	#define GPIO_IDR_IDR_1 ((uint32_t)0x00000002)
Kojto	112:6f327212ef96	2178	#define GPIO_IDR_IDR_2 ((uint32_t)0x00000004)
Kojto	112:6f327212ef96	2179	#define GPIO_IDR_IDR_3 ((uint32_t)0x00000008)
Kojto	112:6f327212ef96	2180	#define GPIO_IDR_IDR_4 ((uint32_t)0x00000010)
Kojto	112:6f327212ef96	2181	#define GPIO_IDR_IDR_5 ((uint32_t)0x00000020)
Kojto	112:6f327212ef96	2182	#define GPIO_IDR_IDR_6 ((uint32_t)0x00000040)
Kojto	112:6f327212ef96	2183	#define GPIO_IDR_IDR_7 ((uint32_t)0x00000080)
Kojto	112:6f327212ef96	2184	#define GPIO_IDR_IDR_8 ((uint32_t)0x00000100)
Kojto	112:6f327212ef96	2185	#define GPIO_IDR_IDR_9 ((uint32_t)0x00000200)
Kojto	112:6f327212ef96	2186	#define GPIO_IDR_IDR_10 ((uint32_t)0x00000400)
Kojto	112:6f327212ef96	2187	#define GPIO_IDR_IDR_11 ((uint32_t)0x00000800)
Kojto	112:6f327212ef96	2188	#define GPIO_IDR_IDR_12 ((uint32_t)0x00001000)
Kojto	112:6f327212ef96	2189	#define GPIO_IDR_IDR_13 ((uint32_t)0x00002000)
Kojto	112:6f327212ef96	2190	#define GPIO_IDR_IDR_14 ((uint32_t)0x00004000)
Kojto	112:6f327212ef96	2191	#define GPIO_IDR_IDR_15 ((uint32_t)0x00008000)
Kojto	112:6f327212ef96	2192
Kojto	112:6f327212ef96	2193	/**************** Bits definition for GPIO_ODR register *****************/
Kojto	112:6f327212ef96	2194	#define GPIO_ODR_ODR_0 ((uint32_t)0x00000001)
Kojto	112:6f327212ef96	2195	#define GPIO_ODR_ODR_1 ((uint32_t)0x00000002)
Kojto	112:6f327212ef96	2196	#define GPIO_ODR_ODR_2 ((uint32_t)0x00000004)
Kojto	112:6f327212ef96	2197	#define GPIO_ODR_ODR_3 ((uint32_t)0x00000008)
Kojto	112:6f327212ef96	2198	#define GPIO_ODR_ODR_4 ((uint32_t)0x00000010)
Kojto	112:6f327212ef96	2199	#define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)
Kojto	112:6f327212ef96	2200	#define GPIO_ODR_ODR_6 ((uint32_t)0x00000040)
Kojto	112:6f327212ef96	2201	#define GPIO_ODR_ODR_7 ((uint32_t)0x00000080)
Kojto	112:6f327212ef96	2202	#define GPIO_ODR_ODR_8 ((uint32_t)0x00000100)
Kojto	112:6f327212ef96	2203	#define GPIO_ODR_ODR_9 ((uint32_t)0x00000200)
Kojto	112:6f327212ef96	2204	#define GPIO_ODR_ODR_10 ((uint32_t)0x00000400)
Kojto	112:6f327212ef96	2205	#define GPIO_ODR_ODR_11 ((uint32_t)0x00000800)
Kojto	112:6f327212ef96	2206	#define GPIO_ODR_ODR_12 ((uint32_t)0x00001000)
Kojto	112:6f327212ef96	2207	#define GPIO_ODR_ODR_13 ((uint32_t)0x00002000)
Kojto	112:6f327212ef96	2208	#define GPIO_ODR_ODR_14 ((uint32_t)0x00004000)
Kojto	112:6f327212ef96	2209	#define GPIO_ODR_ODR_15 ((uint32_t)0x00008000)
Kojto	112:6f327212ef96	2210
Kojto	112:6f327212ef96	2211	/**************** Bits definition for GPIO_BSRR register ****************/
Kojto	112:6f327212ef96	2212	#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
Kojto	112:6f327212ef96	2213	#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
Kojto	112:6f327212ef96	2214	#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
Kojto	112:6f327212ef96	2215	#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
Kojto	112:6f327212ef96	2216	#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
Kojto	112:6f327212ef96	2217	#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
Kojto	112:6f327212ef96	2218	#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
Kojto	112:6f327212ef96	2219	#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
Kojto	112:6f327212ef96	2220	#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
Kojto	112:6f327212ef96	2221	#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
Kojto	112:6f327212ef96	2222	#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
Kojto	112:6f327212ef96	2223	#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
Kojto	112:6f327212ef96	2224	#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
Kojto	112:6f327212ef96	2225	#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
Kojto	112:6f327212ef96	2226	#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
Kojto	112:6f327212ef96	2227	#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
Kojto	112:6f327212ef96	2228	#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
Kojto	112:6f327212ef96	2229	#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
Kojto	112:6f327212ef96	2230	#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
Kojto	112:6f327212ef96	2231	#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
Kojto	112:6f327212ef96	2232	#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
Kojto	112:6f327212ef96	2233	#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
Kojto	112:6f327212ef96	2234	#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
Kojto	112:6f327212ef96	2235	#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
Kojto	112:6f327212ef96	2236	#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
Kojto	112:6f327212ef96	2237	#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
Kojto	112:6f327212ef96	2238	#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
Kojto	112:6f327212ef96	2239	#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
Kojto	112:6f327212ef96	2240	#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
Kojto	112:6f327212ef96	2241	#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
Kojto	112:6f327212ef96	2242	#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
Kojto	112:6f327212ef96	2243	#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
Kojto	112:6f327212ef96	2244
Kojto	112:6f327212ef96	2245	/**************** Bit definition for GPIO_LCKR register ******************/
Kojto	112:6f327212ef96	2246	#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
Kojto	112:6f327212ef96	2247	#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
Kojto	112:6f327212ef96	2248	#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
Kojto	112:6f327212ef96	2249	#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
Kojto	112:6f327212ef96	2250	#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
Kojto	112:6f327212ef96	2251	#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
Kojto	112:6f327212ef96	2252	#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
Kojto	112:6f327212ef96	2253	#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
Kojto	112:6f327212ef96	2254	#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
Kojto	112:6f327212ef96	2255	#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
Kojto	112:6f327212ef96	2256	#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
Kojto	112:6f327212ef96	2257	#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
Kojto	112:6f327212ef96	2258	#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
Kojto	112:6f327212ef96	2259	#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
Kojto	112:6f327212ef96	2260	#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
Kojto	112:6f327212ef96	2261	#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
Kojto	112:6f327212ef96	2262	#define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
Kojto	112:6f327212ef96	2263
Kojto	112:6f327212ef96	2264	/**************** Bit definition for GPIO_AFRL register ******************/
Kojto	112:6f327212ef96	2265	#define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F)
Kojto	112:6f327212ef96	2266	#define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0)
Kojto	112:6f327212ef96	2267	#define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00)
Kojto	112:6f327212ef96	2268	#define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000)
Kojto	112:6f327212ef96	2269	#define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000)
Kojto	112:6f327212ef96	2270	#define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000)
Kojto	112:6f327212ef96	2271	#define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000)
Kojto	112:6f327212ef96	2272	#define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000)
Kojto	112:6f327212ef96	2273
Kojto	112:6f327212ef96	2274	/**************** Bit definition for GPIO_AFRH register ******************/
Kojto	112:6f327212ef96	2275	#define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000F)
Kojto	112:6f327212ef96	2276	#define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0)
Kojto	112:6f327212ef96	2277	#define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00)
Kojto	112:6f327212ef96	2278	#define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000)
Kojto	112:6f327212ef96	2279	#define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000)
Kojto	112:6f327212ef96	2280	#define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000)
Kojto	112:6f327212ef96	2281	#define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000)
Kojto	112:6f327212ef96	2282	#define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000)
Kojto	112:6f327212ef96	2283
Kojto	112:6f327212ef96	2284	/**************** Bit definition for GPIO_BRR register *******************/
Kojto	112:6f327212ef96	2285	#define GPIO_BRR_BR_0 ((uint32_t)0x00000001)
Kojto	112:6f327212ef96	2286	#define GPIO_BRR_BR_1 ((uint32_t)0x00000002)
Kojto	112:6f327212ef96	2287	#define GPIO_BRR_BR_2 ((uint32_t)0x00000004)
Kojto	112:6f327212ef96	2288	#define GPIO_BRR_BR_3 ((uint32_t)0x00000008)
Kojto	112:6f327212ef96	2289	#define GPIO_BRR_BR_4 ((uint32_t)0x00000010)
Kojto	112:6f327212ef96	2290	#define GPIO_BRR_BR_5 ((uint32_t)0x00000020)
Kojto	112:6f327212ef96	2291	#define GPIO_BRR_BR_6 ((uint32_t)0x00000040)
Kojto	112:6f327212ef96	2292	#define GPIO_BRR_BR_7 ((uint32_t)0x00000080)
Kojto	112:6f327212ef96	2293	#define GPIO_BRR_BR_8 ((uint32_t)0x00000100)
Kojto	112:6f327212ef96	2294	#define GPIO_BRR_BR_9 ((uint32_t)0x00000200)
Kojto	112:6f327212ef96	2295	#define GPIO_BRR_BR_10 ((uint32_t)0x00000400)
Kojto	112:6f327212ef96	2296	#define GPIO_BRR_BR_11 ((uint32_t)0x00000800)
Kojto	112:6f327212ef96	2297	#define GPIO_BRR_BR_12 ((uint32_t)0x00001000)
Kojto	112:6f327212ef96	2298	#define GPIO_BRR_BR_13 ((uint32_t)0x00002000)
Kojto	112:6f327212ef96	2299	#define GPIO_BRR_BR_14 ((uint32_t)0x00004000)
Kojto	112:6f327212ef96	2300	#define GPIO_BRR_BR_15 ((uint32_t)0x00008000)
Kojto	112:6f327212ef96	2301
Kojto	112:6f327212ef96	2302
Kojto	112:6f327212ef96	2303	/******************************************************************************/
Kojto	112:6f327212ef96	2304	/* */
Kojto	112:6f327212ef96	2305	/* Inter-integrated Circuit Interface (I2C) */
Kojto	112:6f327212ef96	2306	/* */
Kojto	112:6f327212ef96	2307	/******************************************************************************/
Kojto	112:6f327212ef96	2308
Kojto	112:6f327212ef96	2309	/***************** Bit definition for I2C_CR1 register ******************/
Kojto	112:6f327212ef96	2310	#define I2C_CR1_PE ((uint32_t)0x00000001) /!< Peripheral Enable /
Kojto	112:6f327212ef96	2311	#define I2C_CR1_SMBUS ((uint32_t)0x00000002) /!< SMBus Mode /
Kojto	112:6f327212ef96	2312	#define I2C_CR1_SMBTYPE ((uint32_t)0x00000008) /!< SMBus Type /
Kojto	112:6f327212ef96	2313	#define I2C_CR1_ENARP ((uint32_t)0x00000010) /!< ARP Enable /
Kojto	112:6f327212ef96	2314	#define I2C_CR1_ENPEC ((uint32_t)0x00000020) /!< PEC Enable /
Kojto	112:6f327212ef96	2315	#define I2C_CR1_ENGC ((uint32_t)0x00000040) /!< General Call Enable /
Kojto	112:6f327212ef96	2316	#define I2C_CR1_NOSTRETCH ((uint32_t)0x00000080) /!< Clock Stretching Disable (Slave mode) /
Kojto	112:6f327212ef96	2317	#define I2C_CR1_START ((uint32_t)0x00000100) /!< Start Generation /
Kojto	112:6f327212ef96	2318	#define I2C_CR1_STOP ((uint32_t)0x00000200) /!< Stop Generation /
Kojto	112:6f327212ef96	2319	#define I2C_CR1_ACK ((uint32_t)0x00000400) /!< Acknowledge Enable /
Kojto	112:6f327212ef96	2320	#define I2C_CR1_POS ((uint32_t)0x00000800) /!< Acknowledge/PEC Position (for data reception) /
Kojto	112:6f327212ef96	2321	#define I2C_CR1_PEC ((uint32_t)0x00001000) /!< Packet Error Checking /
Kojto	112:6f327212ef96	2322	#define I2C_CR1_ALERT ((uint32_t)0x00002000) /!< SMBus Alert /
Kojto	112:6f327212ef96	2323	#define I2C_CR1_SWRST ((uint32_t)0x00008000) /!< Software Reset /
Kojto	112:6f327212ef96	2324
Kojto	112:6f327212ef96	2325	/***************** Bit definition for I2C_CR2 register ******************/
Kojto	112:6f327212ef96	2326	#define I2C_CR2_FREQ ((uint32_t)0x0000003F) /!< FREQ[5:0] bits (Peripheral Clock Frequency) /
Kojto	112:6f327212ef96	2327	#define I2C_CR2_FREQ_0 ((uint32_t)0x00000001) /!< Bit 0 /
Kojto	112:6f327212ef96	2328	#define I2C_CR2_FREQ_1 ((uint32_t)0x00000002) /!< Bit 1 /
Kojto	112:6f327212ef96	2329	#define I2C_CR2_FREQ_2 ((uint32_t)0x00000004) /!< Bit 2 /
Kojto	112:6f327212ef96	2330	#define I2C_CR2_FREQ_3 ((uint32_t)0x00000008) /!< Bit 3 /
Kojto	112:6f327212ef96	2331	#define I2C_CR2_FREQ_4 ((uint32_t)0x00000010) /!< Bit 4 /
Kojto	112:6f327212ef96	2332	#define I2C_CR2_FREQ_5 ((uint32_t)0x00000020) /!< Bit 5 /
Kojto	112:6f327212ef96	2333
Kojto	112:6f327212ef96	2334	#define I2C_CR2_ITERREN ((uint32_t)0x00000100) /!< Error Interrupt Enable /
Kojto	112:6f327212ef96	2335	#define I2C_CR2_ITEVTEN ((uint32_t)0x00000200) /!< Event Interrupt Enable /
Kojto	112:6f327212ef96	2336	#define I2C_CR2_ITBUFEN ((uint32_t)0x00000400) /!< Buffer Interrupt Enable /
Kojto	112:6f327212ef96	2337	#define I2C_CR2_DMAEN ((uint32_t)0x00000800) /!< DMA Requests Enable /
Kojto	112:6f327212ef96	2338	#define I2C_CR2_LAST ((uint32_t)0x00001000) /!< DMA Last Transfer /
Kojto	112:6f327212ef96	2339
Kojto	112:6f327212ef96	2340	/***************** Bit definition for I2C_OAR1 register *****************/
Kojto	112:6f327212ef96	2341	#define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /!< Interface Address /
Kojto	112:6f327212ef96	2342	#define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /!< Interface Address /
Kojto	112:6f327212ef96	2343
Kojto	112:6f327212ef96	2344	#define I2C_OAR1_ADD0 ((uint32_t)0x00000001) /!< Bit 0 /
Kojto	112:6f327212ef96	2345	#define I2C_OAR1_ADD1 ((uint32_t)0x00000002) /!< Bit 1 /
Kojto	112:6f327212ef96	2346	#define I2C_OAR1_ADD2 ((uint32_t)0x00000004) /!< Bit 2 /
Kojto	112:6f327212ef96	2347	#define I2C_OAR1_ADD3 ((uint32_t)0x00000008) /!< Bit 3 /
Kojto	112:6f327212ef96	2348	#define I2C_OAR1_ADD4 ((uint32_t)0x00000010) /!< Bit 4 /
Kojto	112:6f327212ef96	2349	#define I2C_OAR1_ADD5 ((uint32_t)0x00000020) /!< Bit 5 /
Kojto	112:6f327212ef96	2350	#define I2C_OAR1_ADD6 ((uint32_t)0x00000040) /!< Bit 6 /
Kojto	112:6f327212ef96	2351	#define I2C_OAR1_ADD7 ((uint32_t)0x00000080) /!< Bit 7 /
Kojto	112:6f327212ef96	2352	#define I2C_OAR1_ADD8 ((uint32_t)0x00000100) /!< Bit 8 /
Kojto	112:6f327212ef96	2353	#define I2C_OAR1_ADD9 ((uint32_t)0x00000200) /!< Bit 9 /
Kojto	112:6f327212ef96	2354
Kojto	112:6f327212ef96	2355	#define I2C_OAR1_ADDMODE ((uint32_t)0x00008000) /!< Addressing Mode (Slave mode) /
Kojto	112:6f327212ef96	2356
Kojto	112:6f327212ef96	2357	/***************** Bit definition for I2C_OAR2 register *****************/
Kojto	112:6f327212ef96	2358	#define I2C_OAR2_ENDUAL ((uint32_t)0x00000001) /!< Dual addressing mode enable /
Kojto	112:6f327212ef96	2359	#define I2C_OAR2_ADD2 ((uint32_t)0x000000FE) /!< Interface address /
Kojto	112:6f327212ef96	2360
Kojto	112:6f327212ef96	2361	/****************** Bit definition for I2C_DR register ******************/
Kojto	112:6f327212ef96	2362	#define I2C_DR_DR ((uint32_t)0x000000FF) /!< 8-bit Data Register /
Kojto	112:6f327212ef96	2363
Kojto	112:6f327212ef96	2364	/***************** Bit definition for I2C_SR1 register ******************/
Kojto	112:6f327212ef96	2365	#define I2C_SR1_SB ((uint32_t)0x00000001) /!< Start Bit (Master mode) /
Kojto	112:6f327212ef96	2366	#define I2C_SR1_ADDR ((uint32_t)0x00000002) /!< Address sent (master mode)/matched (slave mode) /
Kojto	112:6f327212ef96	2367	#define I2C_SR1_BTF ((uint32_t)0x00000004) /!< Byte Transfer Finished /
Kojto	112:6f327212ef96	2368	#define I2C_SR1_ADD10 ((uint32_t)0x00000008) /!< 10-bit header sent (Master mode) /
Kojto	112:6f327212ef96	2369	#define I2C_SR1_STOPF ((uint32_t)0x00000010) /!< Stop detection (Slave mode) /
Kojto	112:6f327212ef96	2370	#define I2C_SR1_RXNE ((uint32_t)0x00000040) /!< Data Register not Empty (receivers) /
Kojto	112:6f327212ef96	2371	#define I2C_SR1_TXE ((uint32_t)0x00000080) /!< Data Register Empty (transmitters) /
Kojto	112:6f327212ef96	2372	#define I2C_SR1_BERR ((uint32_t)0x00000100) /!< Bus Error /
Kojto	112:6f327212ef96	2373	#define I2C_SR1_ARLO ((uint32_t)0x00000200) /!< Arbitration Lost (master mode) /
Kojto	112:6f327212ef96	2374	#define I2C_SR1_AF ((uint32_t)0x00000400) /!< Acknowledge Failure /
Kojto	112:6f327212ef96	2375	#define I2C_SR1_OVR ((uint32_t)0x00000800) /!< Overrun/Underrun /
Kojto	112:6f327212ef96	2376	#define I2C_SR1_PECERR ((uint32_t)0x00001000) /!< PEC Error in reception /
Kojto	112:6f327212ef96	2377	#define I2C_SR1_TIMEOUT ((uint32_t)0x00004000) /!< Timeout or Tlow Error /
Kojto	112:6f327212ef96	2378	#define I2C_SR1_SMBALERT ((uint32_t)0x00008000) /!< SMBus Alert /
Kojto	112:6f327212ef96	2379
Kojto	112:6f327212ef96	2380	/***************** Bit definition for I2C_SR2 register ******************/
Kojto	112:6f327212ef96	2381	#define I2C_SR2_MSL ((uint32_t)0x00000001) /!< Master/Slave /
Kojto	112:6f327212ef96	2382	#define I2C_SR2_BUSY ((uint32_t)0x00000002) /!< Bus Busy /
Kojto	112:6f327212ef96	2383	#define I2C_SR2_TRA ((uint32_t)0x00000004) /!< Transmitter/Receiver /
Kojto	112:6f327212ef96	2384	#define I2C_SR2_GENCALL ((uint32_t)0x00000010) /!< General Call Address (Slave mode) /
Kojto	112:6f327212ef96	2385	#define I2C_SR2_SMBDEFAULT ((uint32_t)0x00000020) /!< SMBus Device Default Address (Slave mode) /
Kojto	112:6f327212ef96	2386	#define I2C_SR2_SMBHOST ((uint32_t)0x00000040) /!< SMBus Host Header (Slave mode) /
Kojto	112:6f327212ef96	2387	#define I2C_SR2_DUALF ((uint32_t)0x00000080) /!< Dual Flag (Slave mode) /
Kojto	112:6f327212ef96	2388	#define I2C_SR2_PEC ((uint32_t)0x0000FF00) /!< Packet Error Checking Register /
Kojto	112:6f327212ef96	2389
Kojto	112:6f327212ef96	2390	/***************** Bit definition for I2C_CCR register ******************/
Kojto	112:6f327212ef96	2391	#define I2C_CCR_CCR ((uint32_t)0x00000FFF) /!< Clock Control Register in Fast/Standard mode (Master mode) /
Kojto	112:6f327212ef96	2392	#define I2C_CCR_DUTY ((uint32_t)0x00004000) /!< Fast Mode Duty Cycle /
Kojto	112:6f327212ef96	2393	#define I2C_CCR_FS ((uint32_t)0x00008000) /!< I2C Master Mode Selection /
Kojto	112:6f327212ef96	2394
Kojto	112:6f327212ef96	2395	/**************** Bit definition for I2C_TRISE register *****************/
Kojto	112:6f327212ef96	2396	#define I2C_TRISE_TRISE ((uint32_t)0x0000003F) /!< Maximum Rise Time in Fast/Standard mode (Master mode) /
Kojto	112:6f327212ef96	2397
Kojto	112:6f327212ef96	2398	/******************************************************************************/
Kojto	112:6f327212ef96	2399	/* */
Kojto	112:6f327212ef96	2400	/* Independent WATCHDOG (IWDG) */
Kojto	112:6f327212ef96	2401	/* */
Kojto	112:6f327212ef96	2402	/******************************************************************************/
Kojto	112:6f327212ef96	2403
Kojto	112:6f327212ef96	2404	/***************** Bit definition for IWDG_KR register ******************/
Kojto	112:6f327212ef96	2405	#define IWDG_KR_KEY ((uint32_t)0x0000FFFF) /!< Key value (write only, read 0000h) /
Kojto	112:6f327212ef96	2406
Kojto	112:6f327212ef96	2407	/***************** Bit definition for IWDG_PR register ******************/
Kojto	112:6f327212ef96	2408	#define IWDG_PR_PR ((uint32_t)0x00000007) /!< PR[2:0] (Prescaler divider) /
Kojto	112:6f327212ef96	2409	#define IWDG_PR_PR_0 ((uint32_t)0x00000001) /!< Bit 0 /
Kojto	112:6f327212ef96	2410	#define IWDG_PR_PR_1 ((uint32_t)0x00000002) /!< Bit 1 /
Kojto	112:6f327212ef96	2411	#define IWDG_PR_PR_2 ((uint32_t)0x00000004) /!< Bit 2 /
Kojto	112:6f327212ef96	2412
Kojto	112:6f327212ef96	2413	/***************** Bit definition for IWDG_RLR register *****************/
Kojto	112:6f327212ef96	2414	#define IWDG_RLR_RL ((uint32_t)0x00000FFF) /!< Watchdog counter reload value /
Kojto	112:6f327212ef96	2415
Kojto	112:6f327212ef96	2416	/***************** Bit definition for IWDG_SR register ******************/
Kojto	112:6f327212ef96	2417	#define IWDG_SR_PVU ((uint32_t)0x00000001) /!< Watchdog prescaler value update /
Kojto	112:6f327212ef96	2418	#define IWDG_SR_RVU ((uint32_t)0x00000002) /!< Watchdog counter reload value update /
Kojto	112:6f327212ef96	2419
Kojto	112:6f327212ef96	2420	/******************************************************************************/
Kojto	112:6f327212ef96	2421	/* */
Kojto	112:6f327212ef96	2422	/* LCD Controller (LCD) */
Kojto	112:6f327212ef96	2423	/* */
Kojto	112:6f327212ef96	2424	/******************************************************************************/
Kojto	112:6f327212ef96	2425
Kojto	112:6f327212ef96	2426	/***************** Bit definition for LCD_CR register *******************/
Kojto	112:6f327212ef96	2427	#define LCD_CR_LCDEN ((uint32_t)0x00000001) /!< LCD Enable Bit /
Kojto	112:6f327212ef96	2428	#define LCD_CR_VSEL ((uint32_t)0x00000002) /!< Voltage source selector Bit /
Kojto	112:6f327212ef96	2429
Kojto	112:6f327212ef96	2430	#define LCD_CR_DUTY ((uint32_t)0x0000001C) /!< DUTY[2:0] bits (Duty selector) /
Kojto	112:6f327212ef96	2431	#define LCD_CR_DUTY_0 ((uint32_t)0x00000004) /!< Duty selector Bit 0 /
Kojto	112:6f327212ef96	2432	#define LCD_CR_DUTY_1 ((uint32_t)0x00000008) /!< Duty selector Bit 1 /
Kojto	112:6f327212ef96	2433	#define LCD_CR_DUTY_2 ((uint32_t)0x00000010) /!< Duty selector Bit 2 /
Kojto	112:6f327212ef96	2434
Kojto	112:6f327212ef96	2435	#define LCD_CR_BIAS ((uint32_t)0x00000060) /!< BIAS[1:0] bits (Bias selector) /
Kojto	112:6f327212ef96	2436	#define LCD_CR_BIAS_0 ((uint32_t)0x00000020) /!< Bias selector Bit 0 /
Kojto	112:6f327212ef96	2437	#define LCD_CR_BIAS_1 ((uint32_t)0x00000040) /!< Bias selector Bit 1 /
Kojto	112:6f327212ef96	2438
Kojto	112:6f327212ef96	2439	#define LCD_CR_MUX_SEG ((uint32_t)0x00000080) /!< Mux Segment Enable Bit /
Kojto	112:6f327212ef96	2440
Kojto	112:6f327212ef96	2441	/***************** Bit definition for LCD_FCR register ******************/
Kojto	112:6f327212ef96	2442	#define LCD_FCR_HD ((uint32_t)0x00000001) /!< High Drive Enable Bit /
Kojto	112:6f327212ef96	2443	#define LCD_FCR_SOFIE ((uint32_t)0x00000002) /!< Start of Frame Interrupt Enable Bit /
Kojto	112:6f327212ef96	2444	#define LCD_FCR_UDDIE ((uint32_t)0x00000008) /!< Update Display Done Interrupt Enable Bit /
Kojto	112:6f327212ef96	2445
Kojto	112:6f327212ef96	2446	#define LCD_FCR_PON ((uint32_t)0x00000070) /!< PON[2:0] bits (Puls ON Duration) /
Kojto	112:6f327212ef96	2447	#define LCD_FCR_PON_0 ((uint32_t)0x00000010) /!< Bit 0 /
Kojto	112:6f327212ef96	2448	#define LCD_FCR_PON_1 ((uint32_t)0x00000020) /!< Bit 1 /
Kojto	112:6f327212ef96	2449	#define LCD_FCR_PON_2 ((uint32_t)0x00000040) /!< Bit 2 /
Kojto	112:6f327212ef96	2450
Kojto	112:6f327212ef96	2451	#define LCD_FCR_DEAD ((uint32_t)0x00000380) /!< DEAD[2:0] bits (DEAD Time) /
Kojto	112:6f327212ef96	2452	#define LCD_FCR_DEAD_0 ((uint32_t)0x00000080) /!< Bit 0 /
Kojto	112:6f327212ef96	2453	#define LCD_FCR_DEAD_1 ((uint32_t)0x00000100) /!< Bit 1 /
Kojto	112:6f327212ef96	2454	#define LCD_FCR_DEAD_2 ((uint32_t)0x00000200) /!< Bit 2 /
Kojto	112:6f327212ef96	2455
Kojto	112:6f327212ef96	2456	#define LCD_FCR_CC ((uint32_t)0x00001C00) /!< CC[2:0] bits (Contrast Control) /
Kojto	112:6f327212ef96	2457	#define LCD_FCR_CC_0 ((uint32_t)0x00000400) /!< Bit 0 /
Kojto	112:6f327212ef96	2458	#define LCD_FCR_CC_1 ((uint32_t)0x00000800) /!< Bit 1 /
Kojto	112:6f327212ef96	2459	#define LCD_FCR_CC_2 ((uint32_t)0x00001000) /!< Bit 2 /
Kojto	112:6f327212ef96	2460
Kojto	112:6f327212ef96	2461	#define LCD_FCR_BLINKF ((uint32_t)0x0000E000) /!< BLINKF[2:0] bits (Blink Frequency) /
Kojto	112:6f327212ef96	2462	#define LCD_FCR_BLINKF_0 ((uint32_t)0x00002000) /!< Bit 0 /
Kojto	112:6f327212ef96	2463	#define LCD_FCR_BLINKF_1 ((uint32_t)0x00004000) /!< Bit 1 /
Kojto	112:6f327212ef96	2464	#define LCD_FCR_BLINKF_2 ((uint32_t)0x00008000) /!< Bit 2 /
Kojto	112:6f327212ef96	2465
Kojto	112:6f327212ef96	2466	#define LCD_FCR_BLINK ((uint32_t)0x00030000) /!< BLINK[1:0] bits (Blink Enable) /
Kojto	112:6f327212ef96	2467	#define LCD_FCR_BLINK_0 ((uint32_t)0x00010000) /!< Bit 0 /
Kojto	112:6f327212ef96	2468	#define LCD_FCR_BLINK_1 ((uint32_t)0x00020000) /!< Bit 1 /
Kojto	112:6f327212ef96	2469
Kojto	112:6f327212ef96	2470	#define LCD_FCR_DIV ((uint32_t)0x003C0000) /!< DIV[3:0] bits (Divider) /
Kojto	112:6f327212ef96	2471	#define LCD_FCR_PS ((uint32_t)0x03C00000) /!< PS[3:0] bits (Prescaler) /
Kojto	112:6f327212ef96	2472
Kojto	112:6f327212ef96	2473	/***************** Bit definition for LCD_SR register *******************/
Kojto	112:6f327212ef96	2474	#define LCD_SR_ENS ((uint32_t)0x00000001) /!< LCD Enabled Bit /
Kojto	112:6f327212ef96	2475	#define LCD_SR_SOF ((uint32_t)0x00000002) /!< Start Of Frame Flag Bit /
Kojto	112:6f327212ef96	2476	#define LCD_SR_UDR ((uint32_t)0x00000004) /!< Update Display Request Bit /
Kojto	112:6f327212ef96	2477	#define LCD_SR_UDD ((uint32_t)0x00000008) /!< Update Display Done Flag Bit /
Kojto	112:6f327212ef96	2478	#define LCD_SR_RDY ((uint32_t)0x00000010) /!< Ready Flag Bit /
Kojto	112:6f327212ef96	2479	#define LCD_SR_FCRSR ((uint32_t)0x00000020) /!< LCD FCR Register Synchronization Flag Bit /
Kojto	112:6f327212ef96	2480
Kojto	112:6f327212ef96	2481	/***************** Bit definition for LCD_CLR register ******************/
Kojto	112:6f327212ef96	2482	#define LCD_CLR_SOFC ((uint32_t)0x00000002) /!< Start Of Frame Flag Clear Bit /
Kojto	112:6f327212ef96	2483	#define LCD_CLR_UDDC ((uint32_t)0x00000008) /!< Update Display Done Flag Clear Bit /
Kojto	112:6f327212ef96	2484
Kojto	112:6f327212ef96	2485	/***************** Bit definition for LCD_RAM register ******************/
Kojto	112:6f327212ef96	2486	#define LCD_RAM_SEGMENT_DATA ((uint32_t)0xFFFFFFFF) /!< Segment Data Bits /
Kojto	112:6f327212ef96	2487
Kojto	112:6f327212ef96	2488	/******************************************************************************/
Kojto	112:6f327212ef96	2489	/* */
Kojto	112:6f327212ef96	2490	/* Power Control (PWR) */
Kojto	112:6f327212ef96	2491	/* */
Kojto	112:6f327212ef96	2492	/******************************************************************************/
Kojto	112:6f327212ef96	2493
Kojto	112:6f327212ef96	2494	/****************** Bit definition for PWR_CR register ******************/
Kojto	112:6f327212ef96	2495	#define PWR_CR_LPSDSR ((uint32_t)0x00000001) /!< Low-power deepsleep/sleep/low power run /
Kojto	112:6f327212ef96	2496	#define PWR_CR_PDDS ((uint32_t)0x00000002) /!< Power Down Deepsleep /
Kojto	112:6f327212ef96	2497	#define PWR_CR_CWUF ((uint32_t)0x00000004) /!< Clear Wakeup Flag /
Kojto	112:6f327212ef96	2498	#define PWR_CR_CSBF ((uint32_t)0x00000008) /!< Clear Standby Flag /
Kojto	112:6f327212ef96	2499	#define PWR_CR_PVDE ((uint32_t)0x00000010) /!< Power Voltage Detector Enable /
Kojto	112:6f327212ef96	2500
Kojto	112:6f327212ef96	2501	#define PWR_CR_PLS ((uint32_t)0x000000E0) /!< PLS[2:0] bits (PVD Level Selection) /
Kojto	112:6f327212ef96	2502	#define PWR_CR_PLS_0 ((uint32_t)0x00000020) /!< Bit 0 /
Kojto	112:6f327212ef96	2503	#define PWR_CR_PLS_1 ((uint32_t)0x00000040) /!< Bit 1 /
Kojto	112:6f327212ef96	2504	#define PWR_CR_PLS_2 ((uint32_t)0x00000080) /!< Bit 2 /
Kojto	112:6f327212ef96	2505
Kojto	112:6f327212ef96	2506	/!< PVD level configuration /
Kojto	112:6f327212ef96	2507	#define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /!< PVD level 0 /
Kojto	112:6f327212ef96	2508	#define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /!< PVD level 1 /
Kojto	112:6f327212ef96	2509	#define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /!< PVD level 2 /
Kojto	112:6f327212ef96	2510	#define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /!< PVD level 3 /
Kojto	112:6f327212ef96	2511	#define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /!< PVD level 4 /
Kojto	112:6f327212ef96	2512	#define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /!< PVD level 5 /
Kojto	112:6f327212ef96	2513	#define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /!< PVD level 6 /
Kojto	112:6f327212ef96	2514	#define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /!< PVD level 7 /
Kojto	112:6f327212ef96	2515
Kojto	112:6f327212ef96	2516	#define PWR_CR_DBP ((uint32_t)0x00000100) /!< Disable Backup Domain write protection /
Kojto	112:6f327212ef96	2517	#define PWR_CR_ULP ((uint32_t)0x00000200) /!< Ultra Low Power mode /
Kojto	112:6f327212ef96	2518	#define PWR_CR_FWU ((uint32_t)0x00000400) /!< Fast wakeup /
Kojto	112:6f327212ef96	2519
Kojto	112:6f327212ef96	2520	#define PWR_CR_VOS ((uint32_t)0x00001800) /!< VOS[1:0] bits (Voltage scaling range selection) /
Kojto	112:6f327212ef96	2521	#define PWR_CR_VOS_0 ((uint32_t)0x00000800) /!< Bit 0 /
Kojto	112:6f327212ef96	2522	#define PWR_CR_VOS_1 ((uint32_t)0x00001000) /!< Bit 1 /
Kojto	112:6f327212ef96	2523	#define PWR_CR_LPRUN ((uint32_t)0x00004000) /!< Low power run mode /
Kojto	112:6f327212ef96	2524
Kojto	112:6f327212ef96	2525	/***************** Bit definition for PWR_CSR register ******************/
Kojto	112:6f327212ef96	2526	#define PWR_CSR_WUF ((uint32_t)0x00000001) /!< Wakeup Flag /
Kojto	112:6f327212ef96	2527	#define PWR_CSR_SBF ((uint32_t)0x00000002) /!< Standby Flag /
Kojto	112:6f327212ef96	2528	#define PWR_CSR_PVDO ((uint32_t)0x00000004) /!< PVD Output /
Kojto	112:6f327212ef96	2529	#define PWR_CSR_VREFINTRDYF ((uint32_t)0x00000008) /!< Internal voltage reference (VREFINT) ready flag /
Kojto	112:6f327212ef96	2530	#define PWR_CSR_VOSF ((uint32_t)0x00000010) /!< Voltage Scaling select flag /
Kojto	112:6f327212ef96	2531	#define PWR_CSR_REGLPF ((uint32_t)0x00000020) /!< Regulator LP flag /
Kojto	112:6f327212ef96	2532
Kojto	112:6f327212ef96	2533	#define PWR_CSR_EWUP1 ((uint32_t)0x00000100) /!< Enable WKUP pin 1 /
Kojto	112:6f327212ef96	2534	#define PWR_CSR_EWUP2 ((uint32_t)0x00000200) /!< Enable WKUP pin 2 /
Kojto	112:6f327212ef96	2535	#define PWR_CSR_EWUP3 ((uint32_t)0x00000400) /!< Enable WKUP pin 3 /
Kojto	112:6f327212ef96	2536
Kojto	112:6f327212ef96	2537	/******************************************************************************/
Kojto	112:6f327212ef96	2538	/* */
Kojto	112:6f327212ef96	2539	/* Reset and Clock Control (RCC) */
Kojto	112:6f327212ef96	2540	/* */
Kojto	112:6f327212ef96	2541	/******************************************************************************/
Kojto	112:6f327212ef96	2542	/****************** Bit definition for RCC_CR register ******************/
Kojto	112:6f327212ef96	2543	#define RCC_CR_HSION ((uint32_t)0x00000001) /!< Internal High Speed clock enable /
Kojto	112:6f327212ef96	2544	#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /!< Internal High Speed clock ready flag /
Kojto	112:6f327212ef96	2545
Kojto	112:6f327212ef96	2546	#define RCC_CR_MSION ((uint32_t)0x00000100) /!< Internal Multi Speed clock enable /
Kojto	112:6f327212ef96	2547	#define RCC_CR_MSIRDY ((uint32_t)0x00000200) /!< Internal Multi Speed clock ready flag /
Kojto	112:6f327212ef96	2548
Kojto	112:6f327212ef96	2549	#define RCC_CR_HSEON ((uint32_t)0x00010000) /!< External High Speed clock enable /
Kojto	112:6f327212ef96	2550	#define RCC_CR_HSERDY ((uint32_t)0x00020000) /!< External High Speed clock ready flag /
Kojto	112:6f327212ef96	2551	#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /!< External High Speed clock Bypass /
Kojto	112:6f327212ef96	2552
Kojto	112:6f327212ef96	2553	#define RCC_CR_PLLON ((uint32_t)0x01000000) /!< PLL enable /
Kojto	112:6f327212ef96	2554	#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /!< PLL clock ready flag /
Kojto	112:6f327212ef96	2555	#define RCC_CR_CSSON ((uint32_t)0x10000000) /!< Clock Security System enable /
Kojto	112:6f327212ef96	2556
Kojto	112:6f327212ef96	2557	#define RCC_CR_RTCPRE ((uint32_t)0x60000000) /!< RTC/LCD Prescaler /
Kojto	112:6f327212ef96	2558	#define RCC_CR_RTCPRE_0 ((uint32_t)0x20000000) /!< Bit0 /
Kojto	112:6f327212ef96	2559	#define RCC_CR_RTCPRE_1 ((uint32_t)0x40000000) /!< Bit1 /
Kojto	112:6f327212ef96	2560
Kojto	112:6f327212ef96	2561	/****************** Bit definition for RCC_ICSCR register ***************/
Kojto	112:6f327212ef96	2562	#define RCC_ICSCR_HSICAL ((uint32_t)0x000000FF) /!< Internal High Speed clock Calibration /
Kojto	112:6f327212ef96	2563	#define RCC_ICSCR_HSITRIM ((uint32_t)0x00001F00) /!< Internal High Speed clock trimming /
Kojto	112:6f327212ef96	2564
Kojto	112:6f327212ef96	2565	#define RCC_ICSCR_MSIRANGE ((uint32_t)0x0000E000) /!< Internal Multi Speed clock Range /
Kojto	112:6f327212ef96	2566	#define RCC_ICSCR_MSIRANGE_0 ((uint32_t)0x00000000) /!< Internal Multi Speed clock Range 65.536 KHz /
Kojto	112:6f327212ef96	2567	#define RCC_ICSCR_MSIRANGE_1 ((uint32_t)0x00002000) /!< Internal Multi Speed clock Range 131.072 KHz /
Kojto	112:6f327212ef96	2568	#define RCC_ICSCR_MSIRANGE_2 ((uint32_t)0x00004000) /!< Internal Multi Speed clock Range 262.144 KHz /
Kojto	112:6f327212ef96	2569	#define RCC_ICSCR_MSIRANGE_3 ((uint32_t)0x00006000) /!< Internal Multi Speed clock Range 524.288 KHz /
Kojto	112:6f327212ef96	2570	#define RCC_ICSCR_MSIRANGE_4 ((uint32_t)0x00008000) /!< Internal Multi Speed clock Range 1.048 MHz /
Kojto	112:6f327212ef96	2571	#define RCC_ICSCR_MSIRANGE_5 ((uint32_t)0x0000A000) /!< Internal Multi Speed clock Range 2.097 MHz /
Kojto	112:6f327212ef96	2572	#define RCC_ICSCR_MSIRANGE_6 ((uint32_t)0x0000C000) /!< Internal Multi Speed clock Range 4.194 MHz /
Kojto	112:6f327212ef96	2573	#define RCC_ICSCR_MSICAL ((uint32_t)0x00FF0000) /!< Internal Multi Speed clock Calibration /
Kojto	112:6f327212ef96	2574	#define RCC_ICSCR_MSITRIM ((uint32_t)0xFF000000) /!< Internal Multi Speed clock trimming /
Kojto	112:6f327212ef96	2575
Kojto	112:6f327212ef96	2576	/****************** Bit definition for RCC_CFGR register ****************/
Kojto	112:6f327212ef96	2577	#define RCC_CFGR_SW ((uint32_t)0x00000003) /!< SW[1:0] bits (System clock Switch) /
Kojto	112:6f327212ef96	2578	#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /!< Bit 0 /
Kojto	112:6f327212ef96	2579	#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /!< Bit 1 /
Kojto	112:6f327212ef96	2580
Kojto	112:6f327212ef96	2581	/!< SW configuration /
Kojto	112:6f327212ef96	2582	#define RCC_CFGR_SW_MSI ((uint32_t)0x00000000) /!< MSI selected as system clock /
Kojto	112:6f327212ef96	2583	#define RCC_CFGR_SW_HSI ((uint32_t)0x00000001) /!< HSI selected as system clock /
Kojto	112:6f327212ef96	2584	#define RCC_CFGR_SW_HSE ((uint32_t)0x00000002) /!< HSE selected as system clock /
Kojto	112:6f327212ef96	2585	#define RCC_CFGR_SW_PLL ((uint32_t)0x00000003) /!< PLL selected as system clock /
Kojto	112:6f327212ef96	2586
Kojto	112:6f327212ef96	2587	#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /!< SWS[1:0] bits (System Clock Switch Status) /
Kojto	112:6f327212ef96	2588	#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /!< Bit 0 /
Kojto	112:6f327212ef96	2589	#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /!< Bit 1 /
Kojto	112:6f327212ef96	2590
Kojto	112:6f327212ef96	2591	/!< SWS configuration /
Kojto	112:6f327212ef96	2592	#define RCC_CFGR_SWS_MSI ((uint32_t)0x00000000) /!< MSI oscillator used as system clock /
Kojto	112:6f327212ef96	2593	#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000004) /!< HSI oscillator used as system clock /
Kojto	112:6f327212ef96	2594	#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000008) /!< HSE oscillator used as system clock /
Kojto	112:6f327212ef96	2595	#define RCC_CFGR_SWS_PLL ((uint32_t)0x0000000C) /!< PLL used as system clock /
Kojto	112:6f327212ef96	2596
Kojto	112:6f327212ef96	2597	#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /!< HPRE[3:0] bits (AHB prescaler) /
Kojto	112:6f327212ef96	2598	#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /!< Bit 0 /
Kojto	112:6f327212ef96	2599	#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /!< Bit 1 /
Kojto	112:6f327212ef96	2600	#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /!< Bit 2 /
Kojto	112:6f327212ef96	2601	#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /!< Bit 3 /
Kojto	112:6f327212ef96	2602
Kojto	112:6f327212ef96	2603	/!< HPRE configuration /
Kojto	112:6f327212ef96	2604	#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /!< SYSCLK not divided /
Kojto	112:6f327212ef96	2605	#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /!< SYSCLK divided by 2 /
Kojto	112:6f327212ef96	2606	#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /!< SYSCLK divided by 4 /
Kojto	112:6f327212ef96	2607	#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /!< SYSCLK divided by 8 /
Kojto	112:6f327212ef96	2608	#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /!< SYSCLK divided by 16 /
Kojto	112:6f327212ef96	2609	#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /!< SYSCLK divided by 64 /
Kojto	112:6f327212ef96	2610	#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /!< SYSCLK divided by 128 /
Kojto	112:6f327212ef96	2611	#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /!< SYSCLK divided by 256 /
Kojto	112:6f327212ef96	2612	#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /!< SYSCLK divided by 512 /
Kojto	112:6f327212ef96	2613
Kojto	112:6f327212ef96	2614	#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /!< PRE1[2:0] bits (APB1 prescaler) /
Kojto	112:6f327212ef96	2615	#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /!< Bit 0 /
Kojto	112:6f327212ef96	2616	#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /!< Bit 1 /
Kojto	112:6f327212ef96	2617	#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /!< Bit 2 /
Kojto	112:6f327212ef96	2618
Kojto	112:6f327212ef96	2619	/!< PPRE1 configuration /
Kojto	112:6f327212ef96	2620	#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /!< HCLK not divided /
Kojto	112:6f327212ef96	2621	#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /!< HCLK divided by 2 /
Kojto	112:6f327212ef96	2622	#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /!< HCLK divided by 4 /
Kojto	112:6f327212ef96	2623	#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /!< HCLK divided by 8 /
Kojto	112:6f327212ef96	2624	#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /!< HCLK divided by 16 /
Kojto	112:6f327212ef96	2625
Kojto	112:6f327212ef96	2626	#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /!< PRE2[2:0] bits (APB2 prescaler) /
Kojto	112:6f327212ef96	2627	#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /!< Bit 0 /
Kojto	112:6f327212ef96	2628	#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /!< Bit 1 /
Kojto	112:6f327212ef96	2629	#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /!< Bit 2 /
Kojto	112:6f327212ef96	2630
Kojto	112:6f327212ef96	2631	/!< PPRE2 configuration /
Kojto	112:6f327212ef96	2632	#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /!< HCLK not divided /
Kojto	112:6f327212ef96	2633	#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /!< HCLK divided by 2 /
Kojto	112:6f327212ef96	2634	#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /!< HCLK divided by 4 /
Kojto	112:6f327212ef96	2635	#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /!< HCLK divided by 8 /
Kojto	112:6f327212ef96	2636	#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /!< HCLK divided by 16 /
Kojto	112:6f327212ef96	2637
Kojto	112:6f327212ef96	2638	/!< PLL entry clock source/
Kojto	112:6f327212ef96	2639	#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /!< PLL entry clock source /
Kojto	112:6f327212ef96	2640
Kojto	112:6f327212ef96	2641	#define RCC_CFGR_PLLSRC_HSI ((uint32_t)0x00000000) /!< HSI as PLL entry clock source /
Kojto	112:6f327212ef96	2642	#define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000) /!< HSE as PLL entry clock source /
Kojto	112:6f327212ef96	2643
Kojto	112:6f327212ef96	2644
Kojto	112:6f327212ef96	2645	/!< PLLMUL configuration /
Kojto	112:6f327212ef96	2646	#define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000) /!< PLLMUL[3:0] bits (PLL multiplication factor) /
Kojto	112:6f327212ef96	2647	#define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000) /!< Bit 0 /
Kojto	112:6f327212ef96	2648	#define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000) /!< Bit 1 /
Kojto	112:6f327212ef96	2649	#define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000) /!< Bit 2 /
Kojto	112:6f327212ef96	2650	#define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000) /!< Bit 3 /
Kojto	112:6f327212ef96	2651
Kojto	112:6f327212ef96	2652	/!< PLLMUL configuration /
Kojto	112:6f327212ef96	2653	#define RCC_CFGR_PLLMUL3 ((uint32_t)0x00000000) /!< PLL input clock 3 */
Kojto	112:6f327212ef96	2654	#define RCC_CFGR_PLLMUL4 ((uint32_t)0x00040000) /!< PLL input clock 4 */
Kojto	112:6f327212ef96	2655	#define RCC_CFGR_PLLMUL6 ((uint32_t)0x00080000) /!< PLL input clock 6 */
Kojto	112:6f327212ef96	2656	#define RCC_CFGR_PLLMUL8 ((uint32_t)0x000C0000) /!< PLL input clock 8 */
Kojto	112:6f327212ef96	2657	#define RCC_CFGR_PLLMUL12 ((uint32_t)0x00100000) /!< PLL input clock 12 */
Kojto	112:6f327212ef96	2658	#define RCC_CFGR_PLLMUL16 ((uint32_t)0x00140000) /!< PLL input clock 16 */
Kojto	112:6f327212ef96	2659	#define RCC_CFGR_PLLMUL24 ((uint32_t)0x00180000) /!< PLL input clock 24 */
Kojto	112:6f327212ef96	2660	#define RCC_CFGR_PLLMUL32 ((uint32_t)0x001C0000) /!< PLL input clock 32 */
Kojto	112:6f327212ef96	2661	#define RCC_CFGR_PLLMUL48 ((uint32_t)0x00200000) /!< PLL input clock 48 */
Kojto	112:6f327212ef96	2662
Kojto	112:6f327212ef96	2663	/!< PLLDIV configuration /
Kojto	112:6f327212ef96	2664	#define RCC_CFGR_PLLDIV ((uint32_t)0x00C00000) /!< PLLDIV[1:0] bits (PLL Output Division) /
Kojto	112:6f327212ef96	2665	#define RCC_CFGR_PLLDIV_0 ((uint32_t)0x00400000) /!< Bit0 /
Kojto	112:6f327212ef96	2666	#define RCC_CFGR_PLLDIV_1 ((uint32_t)0x00800000) /!< Bit1 /
Kojto	112:6f327212ef96	2667
Kojto	112:6f327212ef96	2668
Kojto	112:6f327212ef96	2669	/!< PLLDIV configuration /
Kojto	112:6f327212ef96	2670	#define RCC_CFGR_PLLDIV1 ((uint32_t)0x00000000) /!< PLL clock output = CKVCO / 1 /
Kojto	112:6f327212ef96	2671	#define RCC_CFGR_PLLDIV2 ((uint32_t)0x00400000) /!< PLL clock output = CKVCO / 2 /
Kojto	112:6f327212ef96	2672	#define RCC_CFGR_PLLDIV3 ((uint32_t)0x00800000) /!< PLL clock output = CKVCO / 3 /
Kojto	112:6f327212ef96	2673	#define RCC_CFGR_PLLDIV4 ((uint32_t)0x00C00000) /!< PLL clock output = CKVCO / 4 /
Kojto	112:6f327212ef96	2674
Kojto	112:6f327212ef96	2675
Kojto	112:6f327212ef96	2676	#define RCC_CFGR_MCOSEL ((uint32_t)0x07000000) /!< MCO[2:0] bits (Microcontroller Clock Output) /
Kojto	112:6f327212ef96	2677	#define RCC_CFGR_MCOSEL_0 ((uint32_t)0x01000000) /!< Bit 0 /
Kojto	112:6f327212ef96	2678	#define RCC_CFGR_MCOSEL_1 ((uint32_t)0x02000000) /!< Bit 1 /
Kojto	112:6f327212ef96	2679	#define RCC_CFGR_MCOSEL_2 ((uint32_t)0x04000000) /!< Bit 2 /
Kojto	112:6f327212ef96	2680
Kojto	112:6f327212ef96	2681	/!< MCO configuration /
Kojto	112:6f327212ef96	2682	#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /!< No clock /
Kojto	112:6f327212ef96	2683	#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x01000000) /!< System clock selected /
Kojto	112:6f327212ef96	2684	#define RCC_CFGR_MCO_HSI ((uint32_t)0x02000000) /!< Internal 16 MHz RC oscillator clock selected /
Kojto	112:6f327212ef96	2685	#define RCC_CFGR_MCO_MSI ((uint32_t)0x03000000) /!< Internal Medium Speed RC oscillator clock selected /
Kojto	112:6f327212ef96	2686	#define RCC_CFGR_MCO_HSE ((uint32_t)0x04000000) /!< External 1-25 MHz oscillator clock selected /
Kojto	112:6f327212ef96	2687	#define RCC_CFGR_MCO_PLL ((uint32_t)0x05000000) /!< PLL clock divided /
Kojto	112:6f327212ef96	2688	#define RCC_CFGR_MCO_LSI ((uint32_t)0x06000000) /!< LSI selected /
Kojto	112:6f327212ef96	2689	#define RCC_CFGR_MCO_LSE ((uint32_t)0x07000000) /!< LSE selected /
Kojto	112:6f327212ef96	2690
Kojto	112:6f327212ef96	2691	#define RCC_CFGR_MCOPRE ((uint32_t)0x70000000) /!< MCOPRE[2:0] bits (Microcontroller Clock Output Prescaler) /
Kojto	112:6f327212ef96	2692	#define RCC_CFGR_MCOPRE_0 ((uint32_t)0x10000000) /!< Bit 0 /
Kojto	112:6f327212ef96	2693	#define RCC_CFGR_MCOPRE_1 ((uint32_t)0x20000000) /!< Bit 1 /
Kojto	112:6f327212ef96	2694	#define RCC_CFGR_MCOPRE_2 ((uint32_t)0x40000000) /!< Bit 2 /
Kojto	112:6f327212ef96	2695
Kojto	112:6f327212ef96	2696	/!< MCO Prescaler configuration /
Kojto	112:6f327212ef96	2697	#define RCC_CFGR_MCO_DIV1 ((uint32_t)0x00000000) /!< MCO Clock divided by 1 /
Kojto	112:6f327212ef96	2698	#define RCC_CFGR_MCO_DIV2 ((uint32_t)0x10000000) /!< MCO Clock divided by 2 /
Kojto	112:6f327212ef96	2699	#define RCC_CFGR_MCO_DIV4 ((uint32_t)0x20000000) /!< MCO Clock divided by 4 /
Kojto	112:6f327212ef96	2700	#define RCC_CFGR_MCO_DIV8 ((uint32_t)0x30000000) /!< MCO Clock divided by 8 /
Kojto	112:6f327212ef96	2701	#define RCC_CFGR_MCO_DIV16 ((uint32_t)0x40000000) /!< MCO Clock divided by 16 /
Kojto	112:6f327212ef96	2702
Kojto	112:6f327212ef96	2703	/!<*************** Bit definition for RCC_CIR register ******************/
Kojto	112:6f327212ef96	2704	#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /!< LSI Ready Interrupt flag /
Kojto	112:6f327212ef96	2705	#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /!< LSE Ready Interrupt flag /
Kojto	112:6f327212ef96	2706	#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /!< HSI Ready Interrupt flag /
Kojto	112:6f327212ef96	2707	#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /!< HSE Ready Interrupt flag /
Kojto	112:6f327212ef96	2708	#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /!< PLL Ready Interrupt flag /
Kojto	112:6f327212ef96	2709	#define RCC_CIR_MSIRDYF ((uint32_t)0x00000020) /!< MSI Ready Interrupt flag /
Kojto	112:6f327212ef96	2710	#define RCC_CIR_LSECSS ((uint32_t)0x00000040) /!< LSE CSS Interrupt flag /
Kojto	112:6f327212ef96	2711	#define RCC_CIR_CSSF ((uint32_t)0x00000080) /!< Clock Security System Interrupt flag /
Kojto	112:6f327212ef96	2712
Kojto	112:6f327212ef96	2713	#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /!< LSI Ready Interrupt Enable /
Kojto	112:6f327212ef96	2714	#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /!< LSE Ready Interrupt Enable /
Kojto	112:6f327212ef96	2715	#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /!< HSI Ready Interrupt Enable /
Kojto	112:6f327212ef96	2716	#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /!< HSE Ready Interrupt Enable /
Kojto	112:6f327212ef96	2717	#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /!< PLL Ready Interrupt Enable /
Kojto	112:6f327212ef96	2718	#define RCC_CIR_MSIRDYIE ((uint32_t)0x00002000) /!< MSI Ready Interrupt Enable /
Kojto	112:6f327212ef96	2719	#define RCC_CIR_LSECSSIE ((uint32_t)0x00004000) /!< LSE CSS Interrupt Enable /
Kojto	112:6f327212ef96	2720
Kojto	112:6f327212ef96	2721	#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /!< LSI Ready Interrupt Clear /
Kojto	112:6f327212ef96	2722	#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /!< LSE Ready Interrupt Clear /
Kojto	112:6f327212ef96	2723	#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /!< HSI Ready Interrupt Clear /
Kojto	112:6f327212ef96	2724	#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /!< HSE Ready Interrupt Clear /
Kojto	112:6f327212ef96	2725	#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /!< PLL Ready Interrupt Clear /
Kojto	112:6f327212ef96	2726	#define RCC_CIR_MSIRDYC ((uint32_t)0x00200000) /!< MSI Ready Interrupt Clear /
Kojto	112:6f327212ef96	2727	#define RCC_CIR_LSECSSC ((uint32_t)0x00400000) /!< LSE CSS Interrupt Clear /
Kojto	112:6f327212ef96	2728	#define RCC_CIR_CSSC ((uint32_t)0x00800000) /!< Clock Security System Interrupt Clear /
Kojto	112:6f327212ef96	2729
Kojto	112:6f327212ef96	2730	/*************** Bit definition for RCC_AHBRSTR register ****************/
Kojto	112:6f327212ef96	2731	#define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00000001) /!< GPIO port A reset /
Kojto	112:6f327212ef96	2732	#define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00000002) /!< GPIO port B reset /
Kojto	112:6f327212ef96	2733	#define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00000004) /!< GPIO port C reset /
Kojto	112:6f327212ef96	2734	#define RCC_AHBRSTR_GPIODRST ((uint32_t)0x00000008) /!< GPIO port D reset /
Kojto	112:6f327212ef96	2735	#define RCC_AHBRSTR_GPIOERST ((uint32_t)0x00000010) /!< GPIO port E reset /
Kojto	112:6f327212ef96	2736	#define RCC_AHBRSTR_GPIOHRST ((uint32_t)0x00000020) /!< GPIO port H reset /
Kojto	112:6f327212ef96	2737	#define RCC_AHBRSTR_CRCRST ((uint32_t)0x00001000) /!< CRC reset /
Kojto	112:6f327212ef96	2738	#define RCC_AHBRSTR_FLITFRST ((uint32_t)0x00008000) /!< FLITF reset /
Kojto	112:6f327212ef96	2739	#define RCC_AHBRSTR_DMA1RST ((uint32_t)0x01000000) /!< DMA1 reset /
Kojto	112:6f327212ef96	2740	#define RCC_AHBRSTR_DMA2RST ((uint32_t)0x02000000) /!< DMA2 reset /
Kojto	112:6f327212ef96	2741
Kojto	112:6f327212ef96	2742	/*************** Bit definition for RCC_APB2RSTR register ***************/
Kojto	112:6f327212ef96	2743	#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /!< System Configuration SYSCFG reset /
Kojto	112:6f327212ef96	2744	#define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00000004) /!< TIM9 reset /
Kojto	112:6f327212ef96	2745	#define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00000008) /!< TIM10 reset /
Kojto	112:6f327212ef96	2746	#define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00000010) /!< TIM11 reset /
Kojto	112:6f327212ef96	2747	#define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) /!< ADC1 reset /
Kojto	112:6f327212ef96	2748	#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /!< SPI1 reset /
Kojto	112:6f327212ef96	2749	#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /!< USART1 reset /
Kojto	112:6f327212ef96	2750
Kojto	112:6f327212ef96	2751	/*************** Bit definition for RCC_APB1RSTR register ***************/
Kojto	112:6f327212ef96	2752	#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /!< Timer 2 reset /
Kojto	112:6f327212ef96	2753	#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /!< Timer 3 reset /
Kojto	112:6f327212ef96	2754	#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /!< Timer 4 reset /
Kojto	112:6f327212ef96	2755	#define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /!< Timer 5 reset /
Kojto	112:6f327212ef96	2756	#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /!< Timer 6 reset /
Kojto	112:6f327212ef96	2757	#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /!< Timer 7 reset /
Kojto	112:6f327212ef96	2758	#define RCC_APB1RSTR_LCDRST ((uint32_t)0x00000200) /!< LCD reset /
Kojto	112:6f327212ef96	2759	#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /!< Window Watchdog reset /
Kojto	112:6f327212ef96	2760	#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /!< SPI 2 reset /
Kojto	112:6f327212ef96	2761	#define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /!< SPI 3 reset /
Kojto	112:6f327212ef96	2762	#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /!< USART 2 reset /
Kojto	112:6f327212ef96	2763	#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /!< USART 3 reset /
Kojto	112:6f327212ef96	2764	#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /!< I2C 1 reset /
Kojto	112:6f327212ef96	2765	#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /!< I2C 2 reset /
Kojto	112:6f327212ef96	2766	#define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /!< USB reset /
Kojto	112:6f327212ef96	2767	#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /!< Power interface reset /
Kojto	112:6f327212ef96	2768	#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /!< DAC interface reset /
Kojto	112:6f327212ef96	2769	#define RCC_APB1RSTR_COMPRST ((uint32_t)0x80000000) /!< Comparator interface reset /
Kojto	112:6f327212ef96	2770
Kojto	112:6f327212ef96	2771	/**************** Bit definition for RCC_AHBENR register ****************/
Kojto	112:6f327212ef96	2772	#define RCC_AHBENR_GPIOAEN ((uint32_t)0x00000001) /!< GPIO port A clock enable /
Kojto	112:6f327212ef96	2773	#define RCC_AHBENR_GPIOBEN ((uint32_t)0x00000002) /!< GPIO port B clock enable /
Kojto	112:6f327212ef96	2774	#define RCC_AHBENR_GPIOCEN ((uint32_t)0x00000004) /!< GPIO port C clock enable /
Kojto	112:6f327212ef96	2775	#define RCC_AHBENR_GPIODEN ((uint32_t)0x00000008) /!< GPIO port D clock enable /
Kojto	112:6f327212ef96	2776	#define RCC_AHBENR_GPIOEEN ((uint32_t)0x00000010) /!< GPIO port E clock enable /
Kojto	112:6f327212ef96	2777	#define RCC_AHBENR_GPIOHEN ((uint32_t)0x00000020) /!< GPIO port H clock enable /
Kojto	112:6f327212ef96	2778	#define RCC_AHBENR_CRCEN ((uint32_t)0x00001000) /!< CRC clock enable /
Kojto	112:6f327212ef96	2779	#define RCC_AHBENR_FLITFEN ((uint32_t)0x00008000) /*!< FLITF clock enable (has effect only when
Kojto	112:6f327212ef96	2780	the Flash memory is in power down mode) */
Kojto	112:6f327212ef96	2781	#define RCC_AHBENR_DMA1EN ((uint32_t)0x01000000) /!< DMA1 clock enable /
Kojto	112:6f327212ef96	2782	#define RCC_AHBENR_DMA2EN ((uint32_t)0x02000000) /!< DMA2 clock enable /
Kojto	112:6f327212ef96	2783
Kojto	112:6f327212ef96	2784	/**************** Bit definition for RCC_APB2ENR register ***************/
Kojto	112:6f327212ef96	2785	#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001) /!< System Configuration SYSCFG clock enable /
Kojto	112:6f327212ef96	2786	#define RCC_APB2ENR_TIM9EN ((uint32_t)0x00000004) /!< TIM9 interface clock enable /
Kojto	112:6f327212ef96	2787	#define RCC_APB2ENR_TIM10EN ((uint32_t)0x00000008) /!< TIM10 interface clock enable /
Kojto	112:6f327212ef96	2788	#define RCC_APB2ENR_TIM11EN ((uint32_t)0x00000010) /!< TIM11 Timer clock enable /
Kojto	112:6f327212ef96	2789	#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) /!< ADC1 clock enable /
Kojto	112:6f327212ef96	2790	#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /!< SPI1 clock enable /
Kojto	112:6f327212ef96	2791	#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /!< USART1 clock enable /
Kojto	112:6f327212ef96	2792
Kojto	112:6f327212ef96	2793	/*************** Bit definition for RCC_APB1ENR register ****************/
Kojto	112:6f327212ef96	2794	#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /!< Timer 2 clock enabled/
Kojto	112:6f327212ef96	2795	#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /!< Timer 3 clock enable /
Kojto	112:6f327212ef96	2796	#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /!< Timer 4 clock enable /
Kojto	112:6f327212ef96	2797	#define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /!< Timer 5 clock enable /
Kojto	112:6f327212ef96	2798	#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /!< Timer 6 clock enable /
Kojto	112:6f327212ef96	2799	#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /!< Timer 7 clock enable /
Kojto	112:6f327212ef96	2800	#define RCC_APB1ENR_LCDEN ((uint32_t)0x00000200) /!< LCD clock enable /
Kojto	112:6f327212ef96	2801	#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /!< Window Watchdog clock enable /
Kojto	112:6f327212ef96	2802	#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /!< SPI 2 clock enable /
Kojto	112:6f327212ef96	2803	#define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /!< SPI 3 clock enable /
Kojto	112:6f327212ef96	2804	#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /!< USART 2 clock enable /
Kojto	112:6f327212ef96	2805	#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /!< USART 3 clock enable /
Kojto	112:6f327212ef96	2806	#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /!< I2C 1 clock enable /
Kojto	112:6f327212ef96	2807	#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /!< I2C 2 clock enable /
Kojto	112:6f327212ef96	2808	#define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /!< USB clock enable /
Kojto	112:6f327212ef96	2809	#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /!< Power interface clock enable /
Kojto	112:6f327212ef96	2810	#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /!< DAC interface clock enable /
Kojto	112:6f327212ef96	2811	#define RCC_APB1ENR_COMPEN ((uint32_t)0x80000000) /!< Comparator interface clock enable /
Kojto	112:6f327212ef96	2812
Kojto	112:6f327212ef96	2813	/**************** Bit definition for RCC_AHBLPENR register **************/
Kojto	112:6f327212ef96	2814	#define RCC_AHBLPENR_GPIOALPEN ((uint32_t)0x00000001) /!< GPIO port A clock enabled in sleep mode /
Kojto	112:6f327212ef96	2815	#define RCC_AHBLPENR_GPIOBLPEN ((uint32_t)0x00000002) /!< GPIO port B clock enabled in sleep mode /
Kojto	112:6f327212ef96	2816	#define RCC_AHBLPENR_GPIOCLPEN ((uint32_t)0x00000004) /!< GPIO port C clock enabled in sleep mode /
Kojto	112:6f327212ef96	2817	#define RCC_AHBLPENR_GPIODLPEN ((uint32_t)0x00000008) /!< GPIO port D clock enabled in sleep mode /
Kojto	112:6f327212ef96	2818	#define RCC_AHBLPENR_GPIOELPEN ((uint32_t)0x00000010) /!< GPIO port E clock enabled in sleep mode /
Kojto	112:6f327212ef96	2819	#define RCC_AHBLPENR_GPIOHLPEN ((uint32_t)0x00000020) /!< GPIO port H clock enabled in sleep mode /
Kojto	112:6f327212ef96	2820	#define RCC_AHBLPENR_CRCLPEN ((uint32_t)0x00001000) /!< CRC clock enabled in sleep mode /
Kojto	112:6f327212ef96	2821	#define RCC_AHBLPENR_FLITFLPEN ((uint32_t)0x00008000) /*!< Flash Interface clock enabled in sleep mode
Kojto	112:6f327212ef96	2822	(has effect only when the Flash memory is
Kojto	112:6f327212ef96	2823	in power down mode) */
Kojto	112:6f327212ef96	2824	#define RCC_AHBLPENR_SRAMLPEN ((uint32_t)0x00010000) /!< SRAM clock enabled in sleep mode /
Kojto	112:6f327212ef96	2825	#define RCC_AHBLPENR_DMA1LPEN ((uint32_t)0x01000000) /!< DMA1 clock enabled in sleep mode /
Kojto	112:6f327212ef96	2826	#define RCC_AHBLPENR_DMA2LPEN ((uint32_t)0x02000000) /!< DMA2 clock enabled in sleep mode /
Kojto	112:6f327212ef96	2827
Kojto	112:6f327212ef96	2828	/**************** Bit definition for RCC_APB2LPENR register *************/
Kojto	112:6f327212ef96	2829	#define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00000001) /!< System Configuration SYSCFG clock enabled in sleep mode /
Kojto	112:6f327212ef96	2830	#define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00000004) /!< TIM9 interface clock enabled in sleep mode /
Kojto	112:6f327212ef96	2831	#define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00000008) /!< TIM10 interface clock enabled in sleep mode /
Kojto	112:6f327212ef96	2832	#define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00000010) /!< TIM11 Timer clock enabled in sleep mode /
Kojto	112:6f327212ef96	2833	#define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000200) /!< ADC1 clock enabled in sleep mode /
Kojto	112:6f327212ef96	2834	#define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000) /!< SPI1 clock enabled in sleep mode /
Kojto	112:6f327212ef96	2835	#define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00004000) /!< USART1 clock enabled in sleep mode /
Kojto	112:6f327212ef96	2836
Kojto	112:6f327212ef96	2837	/*************** Bit definition for RCC_APB1LPENR register **************/
Kojto	112:6f327212ef96	2838	#define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001) /!< Timer 2 clock enabled in sleep mode /
Kojto	112:6f327212ef96	2839	#define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002) /!< Timer 3 clock enabled in sleep mode /
Kojto	112:6f327212ef96	2840	#define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004) /!< Timer 4 clock enabled in sleep mode /
Kojto	112:6f327212ef96	2841	#define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008) /!< Timer 5 clock enabled in sleep mode /
Kojto	112:6f327212ef96	2842	#define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010) /!< Timer 6 clock enabled in sleep mode /
Kojto	112:6f327212ef96	2843	#define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020) /!< Timer 7 clock enabled in sleep mode /
Kojto	112:6f327212ef96	2844	#define RCC_APB1LPENR_LCDLPEN ((uint32_t)0x00000200) /!< LCD clock enabled in sleep mode /
Kojto	112:6f327212ef96	2845	#define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800) /!< Window Watchdog clock enabled in sleep mode /
Kojto	112:6f327212ef96	2846	#define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000) /!< SPI 2 clock enabled in sleep mode /
Kojto	112:6f327212ef96	2847	#define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000) /!< SPI 3 clock enabled in sleep mode /
Kojto	112:6f327212ef96	2848	#define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000) /!< USART 2 clock enabled in sleep mode /
Kojto	112:6f327212ef96	2849	#define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000) /!< USART 3 clock enabled in sleep mode /
Kojto	112:6f327212ef96	2850	#define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000) /!< I2C 1 clock enabled in sleep mode /
Kojto	112:6f327212ef96	2851	#define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000) /!< I2C 2 clock enabled in sleep mode /
Kojto	112:6f327212ef96	2852	#define RCC_APB1LPENR_USBLPEN ((uint32_t)0x00800000) /!< USB clock enabled in sleep mode /
Kojto	112:6f327212ef96	2853	#define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000) /!< Power interface clock enabled in sleep mode /
Kojto	112:6f327212ef96	2854	#define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000) /!< DAC interface clock enabled in sleep mode /
Kojto	112:6f327212ef96	2855	#define RCC_APB1LPENR_COMPLPEN ((uint32_t)0x80000000) /!< Comparator interface clock enabled in sleep mode/
Kojto	112:6f327212ef96	2856
Kojto	112:6f327212ef96	2857	/***************** Bit definition for RCC_CSR register ******************/
Kojto	112:6f327212ef96	2858	#define RCC_CSR_LSION ((uint32_t)0x00000001) /!< Internal Low Speed oscillator enable /
Kojto	112:6f327212ef96	2859	#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /!< Internal Low Speed oscillator Ready /
Kojto	112:6f327212ef96	2860
Kojto	112:6f327212ef96	2861	#define RCC_CSR_LSEON ((uint32_t)0x00000100) /!< External Low Speed oscillator enable /
Kojto	112:6f327212ef96	2862	#define RCC_CSR_LSERDY ((uint32_t)0x00000200) /!< External Low Speed oscillator Ready /
Kojto	112:6f327212ef96	2863	#define RCC_CSR_LSEBYP ((uint32_t)0x00000400) /!< External Low Speed oscillator Bypass /
Kojto	112:6f327212ef96	2864
Kojto	112:6f327212ef96	2865	#define RCC_CSR_LSECSSON ((uint32_t)0x00000800) /!< External Low Speed oscillator CSS Enable /
Kojto	112:6f327212ef96	2866	#define RCC_CSR_LSECSSD ((uint32_t)0x00001000) /!< External Low Speed oscillator CSS Detected /
Kojto	112:6f327212ef96	2867
Kojto	112:6f327212ef96	2868	#define RCC_CSR_RTCSEL ((uint32_t)0x00030000) /!< RTCSEL[1:0] bits (RTC clock source selection) /
Kojto	112:6f327212ef96	2869	#define RCC_CSR_RTCSEL_0 ((uint32_t)0x00010000) /!< Bit 0 /
Kojto	112:6f327212ef96	2870	#define RCC_CSR_RTCSEL_1 ((uint32_t)0x00020000) /!< Bit 1 /
Kojto	112:6f327212ef96	2871
Kojto	112:6f327212ef96	2872	/!< RTC congiguration /
Kojto	112:6f327212ef96	2873	#define RCC_CSR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /!< No clock /
Kojto	112:6f327212ef96	2874	#define RCC_CSR_RTCSEL_LSE ((uint32_t)0x00010000) /!< LSE oscillator clock used as RTC clock /
Kojto	112:6f327212ef96	2875	#define RCC_CSR_RTCSEL_LSI ((uint32_t)0x00020000) /!< LSI oscillator clock used as RTC clock /
Kojto	112:6f327212ef96	2876	#define RCC_CSR_RTCSEL_HSE ((uint32_t)0x00030000) /!< HSE oscillator clock divided by 2, 4, 8 or 16 by RTCPRE used as RTC clock /
Kojto	112:6f327212ef96	2877
Kojto	112:6f327212ef96	2878	#define RCC_CSR_RTCEN ((uint32_t)0x00400000) /!< RTC clock enable /
Kojto	112:6f327212ef96	2879	#define RCC_CSR_RTCRST ((uint32_t)0x00800000) /!< RTC reset /
Kojto	112:6f327212ef96	2880
Kojto	112:6f327212ef96	2881	#define RCC_CSR_RMVF ((uint32_t)0x01000000) /!< Remove reset flag /
Kojto	112:6f327212ef96	2882	#define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /!< Option Bytes Loader reset flag /
Kojto	112:6f327212ef96	2883	#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /!< PIN reset flag /
Kojto	112:6f327212ef96	2884	#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /!< POR/PDR reset flag /
Kojto	112:6f327212ef96	2885	#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /!< Software Reset flag /
Kojto	112:6f327212ef96	2886	#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /!< Independent Watchdog reset flag /
Kojto	112:6f327212ef96	2887	#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /!< Window watchdog reset flag /
Kojto	112:6f327212ef96	2888	#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /!< Low-Power reset flag /
Kojto	112:6f327212ef96	2889
Kojto	112:6f327212ef96	2890	/******************************************************************************/
Kojto	112:6f327212ef96	2891	/* */
Kojto	112:6f327212ef96	2892	/* Real-Time Clock (RTC) */
Kojto	112:6f327212ef96	2893	/* */
Kojto	112:6f327212ef96	2894	/******************************************************************************/
Kojto	112:6f327212ef96	2895	/****************** Bits definition for RTC_TR register *****************/
Kojto	112:6f327212ef96	2896	#define RTC_TR_PM ((uint32_t)0x00400000)
Kojto	112:6f327212ef96	2897	#define RTC_TR_HT ((uint32_t)0x00300000)
Kojto	112:6f327212ef96	2898	#define RTC_TR_HT_0 ((uint32_t)0x00100000)
Kojto	112:6f327212ef96	2899	#define RTC_TR_HT_1 ((uint32_t)0x00200000)
Kojto	112:6f327212ef96	2900	#define RTC_TR_HU ((uint32_t)0x000F0000)
Kojto	112:6f327212ef96	2901	#define RTC_TR_HU_0 ((uint32_t)0x00010000)
Kojto	112:6f327212ef96	2902	#define RTC_TR_HU_1 ((uint32_t)0x00020000)
Kojto	112:6f327212ef96	2903	#define RTC_TR_HU_2 ((uint32_t)0x00040000)
Kojto	112:6f327212ef96	2904	#define RTC_TR_HU_3 ((uint32_t)0x00080000)
Kojto	112:6f327212ef96	2905	#define RTC_TR_MNT ((uint32_t)0x00007000)
Kojto	112:6f327212ef96	2906	#define RTC_TR_MNT_0 ((uint32_t)0x00001000)
Kojto	112:6f327212ef96	2907	#define RTC_TR_MNT_1 ((uint32_t)0x00002000)
Kojto	112:6f327212ef96	2908	#define RTC_TR_MNT_2 ((uint32_t)0x00004000)
Kojto	112:6f327212ef96	2909	#define RTC_TR_MNU ((uint32_t)0x00000F00)
Kojto	112:6f327212ef96	2910	#define RTC_TR_MNU_0 ((uint32_t)0x00000100)
Kojto	112:6f327212ef96	2911	#define RTC_TR_MNU_1 ((uint32_t)0x00000200)
Kojto	112:6f327212ef96	2912	#define RTC_TR_MNU_2 ((uint32_t)0x00000400)
Kojto	112:6f327212ef96	2913	#define RTC_TR_MNU_3 ((uint32_t)0x00000800)
Kojto	112:6f327212ef96	2914	#define RTC_TR_ST ((uint32_t)0x00000070)
Kojto	112:6f327212ef96	2915	#define RTC_TR_ST_0 ((uint32_t)0x00000010)
Kojto	112:6f327212ef96	2916	#define RTC_TR_ST_1 ((uint32_t)0x00000020)
Kojto	112:6f327212ef96	2917	#define RTC_TR_ST_2 ((uint32_t)0x00000040)
Kojto	112:6f327212ef96	2918	#define RTC_TR_SU ((uint32_t)0x0000000F)
Kojto	112:6f327212ef96	2919	#define RTC_TR_SU_0 ((uint32_t)0x00000001)
Kojto	112:6f327212ef96	2920	#define RTC_TR_SU_1 ((uint32_t)0x00000002)
Kojto	112:6f327212ef96	2921	#define RTC_TR_SU_2 ((uint32_t)0x00000004)
Kojto	112:6f327212ef96	2922	#define RTC_TR_SU_3 ((uint32_t)0x00000008)
Kojto	112:6f327212ef96	2923
Kojto	112:6f327212ef96	2924	/****************** Bits definition for RTC_DR register *****************/
Kojto	112:6f327212ef96	2925	#define RTC_DR_YT ((uint32_t)0x00F00000)
Kojto	112:6f327212ef96	2926	#define RTC_DR_YT_0 ((uint32_t)0x00100000)
Kojto	112:6f327212ef96	2927	#define RTC_DR_YT_1 ((uint32_t)0x00200000)
Kojto	112:6f327212ef96	2928	#define RTC_DR_YT_2 ((uint32_t)0x00400000)
Kojto	112:6f327212ef96	2929	#define RTC_DR_YT_3 ((uint32_t)0x00800000)
Kojto	112:6f327212ef96	2930	#define RTC_DR_YU ((uint32_t)0x000F0000)
Kojto	112:6f327212ef96	2931	#define RTC_DR_YU_0 ((uint32_t)0x00010000)
Kojto	112:6f327212ef96	2932	#define RTC_DR_YU_1 ((uint32_t)0x00020000)
Kojto	112:6f327212ef96	2933	#define RTC_DR_YU_2 ((uint32_t)0x00040000)
Kojto	112:6f327212ef96	2934	#define RTC_DR_YU_3 ((uint32_t)0x00080000)
Kojto	112:6f327212ef96	2935	#define RTC_DR_WDU ((uint32_t)0x0000E000)
Kojto	112:6f327212ef96	2936	#define RTC_DR_WDU_0 ((uint32_t)0x00002000)
Kojto	112:6f327212ef96	2937	#define RTC_DR_WDU_1 ((uint32_t)0x00004000)
Kojto	112:6f327212ef96	2938	#define RTC_DR_WDU_2 ((uint32_t)0x00008000)
Kojto	112:6f327212ef96	2939	#define RTC_DR_MT ((uint32_t)0x00001000)
Kojto	112:6f327212ef96	2940	#define RTC_DR_MU ((uint32_t)0x00000F00)
Kojto	112:6f327212ef96	2941	#define RTC_DR_MU_0 ((uint32_t)0x00000100)
Kojto	112:6f327212ef96	2942	#define RTC_DR_MU_1 ((uint32_t)0x00000200)
Kojto	112:6f327212ef96	2943	#define RTC_DR_MU_2 ((uint32_t)0x00000400)
Kojto	112:6f327212ef96	2944	#define RTC_DR_MU_3 ((uint32_t)0x00000800)
Kojto	112:6f327212ef96	2945	#define RTC_DR_DT ((uint32_t)0x00000030)
Kojto	112:6f327212ef96	2946	#define RTC_DR_DT_0 ((uint32_t)0x00000010)
Kojto	112:6f327212ef96	2947	#define RTC_DR_DT_1 ((uint32_t)0x00000020)
Kojto	112:6f327212ef96	2948	#define RTC_DR_DU ((uint32_t)0x0000000F)
Kojto	112:6f327212ef96	2949	#define RTC_DR_DU_0 ((uint32_t)0x00000001)
Kojto	112:6f327212ef96	2950	#define RTC_DR_DU_1 ((uint32_t)0x00000002)
Kojto	112:6f327212ef96	2951	#define RTC_DR_DU_2 ((uint32_t)0x00000004)
Kojto	112:6f327212ef96	2952	#define RTC_DR_DU_3 ((uint32_t)0x00000008)
Kojto	112:6f327212ef96	2953
Kojto	112:6f327212ef96	2954	/****************** Bits definition for RTC_CR register *****************/
Kojto	112:6f327212ef96	2955	#define RTC_CR_COE ((uint32_t)0x00800000)
Kojto	112:6f327212ef96	2956	#define RTC_CR_OSEL ((uint32_t)0x00600000)
Kojto	112:6f327212ef96	2957	#define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
Kojto	112:6f327212ef96	2958	#define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
Kojto	112:6f327212ef96	2959	#define RTC_CR_POL ((uint32_t)0x00100000)
Kojto	112:6f327212ef96	2960	#define RTC_CR_COSEL ((uint32_t)0x00080000)
Kojto	112:6f327212ef96	2961	#define RTC_CR_BCK ((uint32_t)0x00040000)
Kojto	112:6f327212ef96	2962	#define RTC_CR_SUB1H ((uint32_t)0x00020000)
Kojto	112:6f327212ef96	2963	#define RTC_CR_ADD1H ((uint32_t)0x00010000)
Kojto	112:6f327212ef96	2964	#define RTC_CR_TSIE ((uint32_t)0x00008000)
Kojto	112:6f327212ef96	2965	#define RTC_CR_WUTIE ((uint32_t)0x00004000)
Kojto	112:6f327212ef96	2966	#define RTC_CR_ALRBIE ((uint32_t)0x00002000)
Kojto	112:6f327212ef96	2967	#define RTC_CR_ALRAIE ((uint32_t)0x00001000)
Kojto	112:6f327212ef96	2968	#define RTC_CR_TSE ((uint32_t)0x00000800)
Kojto	112:6f327212ef96	2969	#define RTC_CR_WUTE ((uint32_t)0x00000400)
Kojto	112:6f327212ef96	2970	#define RTC_CR_ALRBE ((uint32_t)0x00000200)
Kojto	112:6f327212ef96	2971	#define RTC_CR_ALRAE ((uint32_t)0x00000100)
Kojto	112:6f327212ef96	2972	#define RTC_CR_DCE ((uint32_t)0x00000080)
Kojto	112:6f327212ef96	2973	#define RTC_CR_FMT ((uint32_t)0x00000040)
Kojto	112:6f327212ef96	2974	#define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
Kojto	112:6f327212ef96	2975	#define RTC_CR_REFCKON ((uint32_t)0x00000010)
Kojto	112:6f327212ef96	2976	#define RTC_CR_TSEDGE ((uint32_t)0x00000008)
Kojto	112:6f327212ef96	2977	#define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
Kojto	112:6f327212ef96	2978	#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
Kojto	112:6f327212ef96	2979	#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
Kojto	112:6f327212ef96	2980	#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
Kojto	112:6f327212ef96	2981
Kojto	112:6f327212ef96	2982	/****************** Bits definition for RTC_ISR register ****************/
Kojto	112:6f327212ef96	2983	#define RTC_ISR_RECALPF ((uint32_t)0x00010000)
Kojto	112:6f327212ef96	2984	#define RTC_ISR_TAMP3F ((uint32_t)0x00008000)
Kojto	112:6f327212ef96	2985	#define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
Kojto	112:6f327212ef96	2986	#define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
Kojto	112:6f327212ef96	2987	#define RTC_ISR_TSOVF ((uint32_t)0x00001000)
Kojto	112:6f327212ef96	2988	#define RTC_ISR_TSF ((uint32_t)0x00000800)
Kojto	112:6f327212ef96	2989	#define RTC_ISR_WUTF ((uint32_t)0x00000400)
Kojto	112:6f327212ef96	2990	#define RTC_ISR_ALRBF ((uint32_t)0x00000200)
Kojto	112:6f327212ef96	2991	#define RTC_ISR_ALRAF ((uint32_t)0x00000100)
Kojto	112:6f327212ef96	2992	#define RTC_ISR_INIT ((uint32_t)0x00000080)
Kojto	112:6f327212ef96	2993	#define RTC_ISR_INITF ((uint32_t)0x00000040)
Kojto	112:6f327212ef96	2994	#define RTC_ISR_RSF ((uint32_t)0x00000020)
Kojto	112:6f327212ef96	2995	#define RTC_ISR_INITS ((uint32_t)0x00000010)
Kojto	112:6f327212ef96	2996	#define RTC_ISR_SHPF ((uint32_t)0x00000008)
Kojto	112:6f327212ef96	2997	#define RTC_ISR_WUTWF ((uint32_t)0x00000004)
Kojto	112:6f327212ef96	2998	#define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
Kojto	112:6f327212ef96	2999	#define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
Kojto	112:6f327212ef96	3000
Kojto	112:6f327212ef96	3001	/****************** Bits definition for RTC_PRER register ***************/
Kojto	112:6f327212ef96	3002	#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
Kojto	112:6f327212ef96	3003	#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
Kojto	112:6f327212ef96	3004
Kojto	112:6f327212ef96	3005	/****************** Bits definition for RTC_WUTR register ***************/
Kojto	112:6f327212ef96	3006	#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
Kojto	112:6f327212ef96	3007
Kojto	112:6f327212ef96	3008	/****************** Bits definition for RTC_CALIBR register *************/
Kojto	112:6f327212ef96	3009	#define RTC_CALIBR_DCS ((uint32_t)0x00000080)
Kojto	112:6f327212ef96	3010	#define RTC_CALIBR_DC ((uint32_t)0x0000001F)
Kojto	112:6f327212ef96	3011
Kojto	112:6f327212ef96	3012	/****************** Bits definition for RTC_ALRMAR register *************/
Kojto	112:6f327212ef96	3013	#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
Kojto	112:6f327212ef96	3014	#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
Kojto	112:6f327212ef96	3015	#define RTC_ALRMAR_DT ((uint32_t)0x30000000)
Kojto	112:6f327212ef96	3016	#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
Kojto	112:6f327212ef96	3017	#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
Kojto	112:6f327212ef96	3018	#define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
Kojto	112:6f327212ef96	3019	#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
Kojto	112:6f327212ef96	3020	#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
Kojto	112:6f327212ef96	3021	#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
Kojto	112:6f327212ef96	3022	#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
Kojto	112:6f327212ef96	3023	#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
Kojto	112:6f327212ef96	3024	#define RTC_ALRMAR_PM ((uint32_t)0x00400000)
Kojto	112:6f327212ef96	3025	#define RTC_ALRMAR_HT ((uint32_t)0x00300000)
Kojto	112:6f327212ef96	3026	#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
Kojto	112:6f327212ef96	3027	#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
Kojto	112:6f327212ef96	3028	#define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
Kojto	112:6f327212ef96	3029	#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
Kojto	112:6f327212ef96	3030	#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
Kojto	112:6f327212ef96	3031	#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
Kojto	112:6f327212ef96	3032	#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
Kojto	112:6f327212ef96	3033	#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
Kojto	112:6f327212ef96	3034	#define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
Kojto	112:6f327212ef96	3035	#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
Kojto	112:6f327212ef96	3036	#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
Kojto	112:6f327212ef96	3037	#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
Kojto	112:6f327212ef96	3038	#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
Kojto	112:6f327212ef96	3039	#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
Kojto	112:6f327212ef96	3040	#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
Kojto	112:6f327212ef96	3041	#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
Kojto	112:6f327212ef96	3042	#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
Kojto	112:6f327212ef96	3043	#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
Kojto	112:6f327212ef96	3044	#define RTC_ALRMAR_ST ((uint32_t)0x00000070)
Kojto	112:6f327212ef96	3045	#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
Kojto	112:6f327212ef96	3046	#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
Kojto	112:6f327212ef96	3047	#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
Kojto	112:6f327212ef96	3048	#define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
Kojto	112:6f327212ef96	3049	#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
Kojto	112:6f327212ef96	3050	#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
Kojto	112:6f327212ef96	3051	#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
Kojto	112:6f327212ef96	3052	#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
Kojto	112:6f327212ef96	3053
Kojto	112:6f327212ef96	3054	/****************** Bits definition for RTC_ALRMBR register *************/
Kojto	112:6f327212ef96	3055	#define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
Kojto	112:6f327212ef96	3056	#define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
Kojto	112:6f327212ef96	3057	#define RTC_ALRMBR_DT ((uint32_t)0x30000000)
Kojto	112:6f327212ef96	3058	#define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
Kojto	112:6f327212ef96	3059	#define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
Kojto	112:6f327212ef96	3060	#define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
Kojto	112:6f327212ef96	3061	#define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
Kojto	112:6f327212ef96	3062	#define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
Kojto	112:6f327212ef96	3063	#define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
Kojto	112:6f327212ef96	3064	#define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
Kojto	112:6f327212ef96	3065	#define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
Kojto	112:6f327212ef96	3066	#define RTC_ALRMBR_PM ((uint32_t)0x00400000)
Kojto	112:6f327212ef96	3067	#define RTC_ALRMBR_HT ((uint32_t)0x00300000)
Kojto	112:6f327212ef96	3068	#define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
Kojto	112:6f327212ef96	3069	#define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
Kojto	112:6f327212ef96	3070	#define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
Kojto	112:6f327212ef96	3071	#define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
Kojto	112:6f327212ef96	3072	#define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
Kojto	112:6f327212ef96	3073	#define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
Kojto	112:6f327212ef96	3074	#define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
Kojto	112:6f327212ef96	3075	#define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
Kojto	112:6f327212ef96	3076	#define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
Kojto	112:6f327212ef96	3077	#define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
Kojto	112:6f327212ef96	3078	#define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
Kojto	112:6f327212ef96	3079	#define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
Kojto	112:6f327212ef96	3080	#define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
Kojto	112:6f327212ef96	3081	#define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
Kojto	112:6f327212ef96	3082	#define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
Kojto	112:6f327212ef96	3083	#define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
Kojto	112:6f327212ef96	3084	#define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
Kojto	112:6f327212ef96	3085	#define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
Kojto	112:6f327212ef96	3086	#define RTC_ALRMBR_ST ((uint32_t)0x00000070)
Kojto	112:6f327212ef96	3087	#define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
Kojto	112:6f327212ef96	3088	#define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
Kojto	112:6f327212ef96	3089	#define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
Kojto	112:6f327212ef96	3090	#define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
Kojto	112:6f327212ef96	3091	#define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
Kojto	112:6f327212ef96	3092	#define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
Kojto	112:6f327212ef96	3093	#define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
Kojto	112:6f327212ef96	3094	#define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
Kojto	112:6f327212ef96	3095
Kojto	112:6f327212ef96	3096	/****************** Bits definition for RTC_WPR register ****************/
Kojto	112:6f327212ef96	3097	#define RTC_WPR_KEY ((uint32_t)0x000000FF)
Kojto	112:6f327212ef96	3098
Kojto	112:6f327212ef96	3099	/****************** Bits definition for RTC_SSR register ****************/
Kojto	112:6f327212ef96	3100	#define RTC_SSR_SS ((uint32_t)0x0000FFFF)
Kojto	112:6f327212ef96	3101
Kojto	112:6f327212ef96	3102	/****************** Bits definition for RTC_SHIFTR register *************/
Kojto	112:6f327212ef96	3103	#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
Kojto	112:6f327212ef96	3104	#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
Kojto	112:6f327212ef96	3105
Kojto	112:6f327212ef96	3106	/****************** Bits definition for RTC_TSTR register ***************/
Kojto	112:6f327212ef96	3107	#define RTC_TSTR_PM ((uint32_t)0x00400000)
Kojto	112:6f327212ef96	3108	#define RTC_TSTR_HT ((uint32_t)0x00300000)
Kojto	112:6f327212ef96	3109	#define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
Kojto	112:6f327212ef96	3110	#define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
Kojto	112:6f327212ef96	3111	#define RTC_TSTR_HU ((uint32_t)0x000F0000)
Kojto	112:6f327212ef96	3112	#define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
Kojto	112:6f327212ef96	3113	#define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
Kojto	112:6f327212ef96	3114	#define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
Kojto	112:6f327212ef96	3115	#define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
Kojto	112:6f327212ef96	3116	#define RTC_TSTR_MNT ((uint32_t)0x00007000)
Kojto	112:6f327212ef96	3117	#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
Kojto	112:6f327212ef96	3118	#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
Kojto	112:6f327212ef96	3119	#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
Kojto	112:6f327212ef96	3120	#define RTC_TSTR_MNU ((uint32_t)0x00000F00)
Kojto	112:6f327212ef96	3121	#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
Kojto	112:6f327212ef96	3122	#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
Kojto	112:6f327212ef96	3123	#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
Kojto	112:6f327212ef96	3124	#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
Kojto	112:6f327212ef96	3125	#define RTC_TSTR_ST ((uint32_t)0x00000070)
Kojto	112:6f327212ef96	3126	#define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
Kojto	112:6f327212ef96	3127	#define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
Kojto	112:6f327212ef96	3128	#define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
Kojto	112:6f327212ef96	3129	#define RTC_TSTR_SU ((uint32_t)0x0000000F)
Kojto	112:6f327212ef96	3130	#define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
Kojto	112:6f327212ef96	3131	#define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
Kojto	112:6f327212ef96	3132	#define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
Kojto	112:6f327212ef96	3133	#define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
Kojto	112:6f327212ef96	3134
Kojto	112:6f327212ef96	3135	/****************** Bits definition for RTC_TSDR register ***************/
Kojto	112:6f327212ef96	3136	#define RTC_TSDR_WDU ((uint32_t)0x0000E000)
Kojto	112:6f327212ef96	3137	#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
Kojto	112:6f327212ef96	3138	#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
Kojto	112:6f327212ef96	3139	#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
Kojto	112:6f327212ef96	3140	#define RTC_TSDR_MT ((uint32_t)0x00001000)
Kojto	112:6f327212ef96	3141	#define RTC_TSDR_MU ((uint32_t)0x00000F00)
Kojto	112:6f327212ef96	3142	#define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
Kojto	112:6f327212ef96	3143	#define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
Kojto	112:6f327212ef96	3144	#define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
Kojto	112:6f327212ef96	3145	#define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
Kojto	112:6f327212ef96	3146	#define RTC_TSDR_DT ((uint32_t)0x00000030)
Kojto	112:6f327212ef96	3147	#define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
Kojto	112:6f327212ef96	3148	#define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
Kojto	112:6f327212ef96	3149	#define RTC_TSDR_DU ((uint32_t)0x0000000F)
Kojto	112:6f327212ef96	3150	#define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
Kojto	112:6f327212ef96	3151	#define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
Kojto	112:6f327212ef96	3152	#define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
Kojto	112:6f327212ef96	3153	#define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
Kojto	112:6f327212ef96	3154
Kojto	112:6f327212ef96	3155	/****************** Bits definition for RTC_TSSSR register **************/
Kojto	112:6f327212ef96	3156	#define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
Kojto	112:6f327212ef96	3157
Kojto	112:6f327212ef96	3158	/****************** Bits definition for RTC_CAL register ***************/
Kojto	112:6f327212ef96	3159	#define RTC_CALR_CALP ((uint32_t)0x00008000)
Kojto	112:6f327212ef96	3160	#define RTC_CALR_CALW8 ((uint32_t)0x00004000)
Kojto	112:6f327212ef96	3161	#define RTC_CALR_CALW16 ((uint32_t)0x00002000)
Kojto	112:6f327212ef96	3162	#define RTC_CALR_CALM ((uint32_t)0x000001FF)
Kojto	112:6f327212ef96	3163	#define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
Kojto	112:6f327212ef96	3164	#define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
Kojto	112:6f327212ef96	3165	#define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
Kojto	112:6f327212ef96	3166	#define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
Kojto	112:6f327212ef96	3167	#define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
Kojto	112:6f327212ef96	3168	#define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
Kojto	112:6f327212ef96	3169	#define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
Kojto	112:6f327212ef96	3170	#define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
Kojto	112:6f327212ef96	3171	#define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
Kojto	112:6f327212ef96	3172
Kojto	112:6f327212ef96	3173	/****************** Bits definition for RTC_TAFCR register **************/
Kojto	112:6f327212ef96	3174	#define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
Kojto	112:6f327212ef96	3175	#define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
Kojto	112:6f327212ef96	3176	#define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
Kojto	112:6f327212ef96	3177	#define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
Kojto	112:6f327212ef96	3178	#define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
Kojto	112:6f327212ef96	3179	#define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
Kojto	112:6f327212ef96	3180	#define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
Kojto	112:6f327212ef96	3181	#define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
Kojto	112:6f327212ef96	3182	#define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
Kojto	112:6f327212ef96	3183	#define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
Kojto	112:6f327212ef96	3184	#define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
Kojto	112:6f327212ef96	3185	#define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
Kojto	112:6f327212ef96	3186	#define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
Kojto	112:6f327212ef96	3187	#define RTC_TAFCR_TAMP3TRG ((uint32_t)0x00000040)
Kojto	112:6f327212ef96	3188	#define RTC_TAFCR_TAMP3E ((uint32_t)0x00000020)
Kojto	112:6f327212ef96	3189	#define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
Kojto	112:6f327212ef96	3190	#define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
Kojto	112:6f327212ef96	3191	#define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
Kojto	112:6f327212ef96	3192	#define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
Kojto	112:6f327212ef96	3193	#define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
Kojto	112:6f327212ef96	3194
Kojto	112:6f327212ef96	3195	/****************** Bits definition for RTC_ALRMASSR register ***********/
Kojto	112:6f327212ef96	3196	#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
Kojto	112:6f327212ef96	3197	#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
Kojto	112:6f327212ef96	3198	#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
Kojto	112:6f327212ef96	3199	#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
Kojto	112:6f327212ef96	3200	#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
Kojto	112:6f327212ef96	3201	#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
Kojto	112:6f327212ef96	3202
Kojto	112:6f327212ef96	3203	/****************** Bits definition for RTC_ALRMBSSR register ***********/
Kojto	112:6f327212ef96	3204	#define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
Kojto	112:6f327212ef96	3205	#define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
Kojto	112:6f327212ef96	3206	#define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
Kojto	112:6f327212ef96	3207	#define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
Kojto	112:6f327212ef96	3208	#define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
Kojto	112:6f327212ef96	3209	#define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
Kojto	112:6f327212ef96	3210
Kojto	112:6f327212ef96	3211	/****************** Bits definition for RTC_BKP0R register **************/
Kojto	112:6f327212ef96	3212	#define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
Kojto	112:6f327212ef96	3213
Kojto	112:6f327212ef96	3214	/****************** Bits definition for RTC_BKP1R register **************/
Kojto	112:6f327212ef96	3215	#define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
Kojto	112:6f327212ef96	3216
Kojto	112:6f327212ef96	3217	/****************** Bits definition for RTC_BKP2R register **************/
Kojto	112:6f327212ef96	3218	#define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
Kojto	112:6f327212ef96	3219
Kojto	112:6f327212ef96	3220	/****************** Bits definition for RTC_BKP3R register **************/
Kojto	112:6f327212ef96	3221	#define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
Kojto	112:6f327212ef96	3222
Kojto	112:6f327212ef96	3223	/****************** Bits definition for RTC_BKP4R register **************/
Kojto	112:6f327212ef96	3224	#define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
Kojto	112:6f327212ef96	3225
Kojto	112:6f327212ef96	3226	/****************** Bits definition for RTC_BKP5R register **************/
Kojto	112:6f327212ef96	3227	#define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
Kojto	112:6f327212ef96	3228
Kojto	112:6f327212ef96	3229	/****************** Bits definition for RTC_BKP6R register **************/
Kojto	112:6f327212ef96	3230	#define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
Kojto	112:6f327212ef96	3231
Kojto	112:6f327212ef96	3232	/****************** Bits definition for RTC_BKP7R register **************/
Kojto	112:6f327212ef96	3233	#define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
Kojto	112:6f327212ef96	3234
Kojto	112:6f327212ef96	3235	/****************** Bits definition for RTC_BKP8R register **************/
Kojto	112:6f327212ef96	3236	#define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
Kojto	112:6f327212ef96	3237
Kojto	112:6f327212ef96	3238	/****************** Bits definition for RTC_BKP9R register **************/
Kojto	112:6f327212ef96	3239	#define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
Kojto	112:6f327212ef96	3240
Kojto	112:6f327212ef96	3241	/****************** Bits definition for RTC_BKP10R register *************/
Kojto	112:6f327212ef96	3242	#define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
Kojto	112:6f327212ef96	3243
Kojto	112:6f327212ef96	3244	/****************** Bits definition for RTC_BKP11R register *************/
Kojto	112:6f327212ef96	3245	#define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
Kojto	112:6f327212ef96	3246
Kojto	112:6f327212ef96	3247	/****************** Bits definition for RTC_BKP12R register *************/
Kojto	112:6f327212ef96	3248	#define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
Kojto	112:6f327212ef96	3249
Kojto	112:6f327212ef96	3250	/****************** Bits definition for RTC_BKP13R register *************/
Kojto	112:6f327212ef96	3251	#define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
Kojto	112:6f327212ef96	3252
Kojto	112:6f327212ef96	3253	/****************** Bits definition for RTC_BKP14R register *************/
Kojto	112:6f327212ef96	3254	#define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
Kojto	112:6f327212ef96	3255
Kojto	112:6f327212ef96	3256	/****************** Bits definition for RTC_BKP15R register *************/
Kojto	112:6f327212ef96	3257	#define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
Kojto	112:6f327212ef96	3258
Kojto	112:6f327212ef96	3259	/****************** Bits definition for RTC_BKP16R register *************/
Kojto	112:6f327212ef96	3260	#define RTC_BKP16R ((uint32_t)0xFFFFFFFF)
Kojto	112:6f327212ef96	3261
Kojto	112:6f327212ef96	3262	/****************** Bits definition for RTC_BKP17R register *************/
Kojto	112:6f327212ef96	3263	#define RTC_BKP17R ((uint32_t)0xFFFFFFFF)
Kojto	112:6f327212ef96	3264
Kojto	112:6f327212ef96	3265	/****************** Bits definition for RTC_BKP18R register *************/
Kojto	112:6f327212ef96	3266	#define RTC_BKP18R ((uint32_t)0xFFFFFFFF)
Kojto	112:6f327212ef96	3267
Kojto	112:6f327212ef96	3268	/****************** Bits definition for RTC_BKP19R register *************/
Kojto	112:6f327212ef96	3269	#define RTC_BKP19R ((uint32_t)0xFFFFFFFF)
Kojto	112:6f327212ef96	3270
Kojto	112:6f327212ef96	3271	/****************** Bits definition for RTC_BKP20R register *************/
Kojto	112:6f327212ef96	3272	#define RTC_BKP20R ((uint32_t)0xFFFFFFFF)
Kojto	112:6f327212ef96	3273
Kojto	112:6f327212ef96	3274	/****************** Bits definition for RTC_BKP21R register *************/
Kojto	112:6f327212ef96	3275	#define RTC_BKP21R ((uint32_t)0xFFFFFFFF)
Kojto	112:6f327212ef96	3276
Kojto	112:6f327212ef96	3277	/****************** Bits definition for RTC_BKP22R register *************/
Kojto	112:6f327212ef96	3278	#define RTC_BKP22R ((uint32_t)0xFFFFFFFF)
Kojto	112:6f327212ef96	3279
Kojto	112:6f327212ef96	3280	/****************** Bits definition for RTC_BKP23R register *************/
Kojto	112:6f327212ef96	3281	#define RTC_BKP23R ((uint32_t)0xFFFFFFFF)
Kojto	112:6f327212ef96	3282
Kojto	112:6f327212ef96	3283	/****************** Bits definition for RTC_BKP24R register *************/
Kojto	112:6f327212ef96	3284	#define RTC_BKP24R ((uint32_t)0xFFFFFFFF)
Kojto	112:6f327212ef96	3285
Kojto	112:6f327212ef96	3286	/****************** Bits definition for RTC_BKP25R register *************/
Kojto	112:6f327212ef96	3287	#define RTC_BKP25R ((uint32_t)0xFFFFFFFF)
Kojto	112:6f327212ef96	3288
Kojto	112:6f327212ef96	3289	/****************** Bits definition for RTC_BKP26R register *************/
Kojto	112:6f327212ef96	3290	#define RTC_BKP26R ((uint32_t)0xFFFFFFFF)
Kojto	112:6f327212ef96	3291
Kojto	112:6f327212ef96	3292	/****************** Bits definition for RTC_BKP27R register *************/
Kojto	112:6f327212ef96	3293	#define RTC_BKP27R ((uint32_t)0xFFFFFFFF)
Kojto	112:6f327212ef96	3294
Kojto	112:6f327212ef96	3295	/****************** Bits definition for RTC_BKP28R register *************/
Kojto	112:6f327212ef96	3296	#define RTC_BKP28R ((uint32_t)0xFFFFFFFF)
Kojto	112:6f327212ef96	3297
Kojto	112:6f327212ef96	3298	/****************** Bits definition for RTC_BKP29R register *************/
Kojto	112:6f327212ef96	3299	#define RTC_BKP29R ((uint32_t)0xFFFFFFFF)
Kojto	112:6f327212ef96	3300
Kojto	112:6f327212ef96	3301	/****************** Bits definition for RTC_BKP30R register *************/
Kojto	112:6f327212ef96	3302	#define RTC_BKP30R ((uint32_t)0xFFFFFFFF)
Kojto	112:6f327212ef96	3303
Kojto	112:6f327212ef96	3304	/****************** Bits definition for RTC_BKP31R register *************/
Kojto	112:6f327212ef96	3305	#define RTC_BKP31R ((uint32_t)0xFFFFFFFF)
Kojto	112:6f327212ef96	3306
Kojto	112:6f327212ef96	3307	/****************** Number of backup registers ****************************/
Kojto	112:6f327212ef96	3308	#define RTC_BKP_NUMBER 32
Kojto	112:6f327212ef96	3309
Kojto	112:6f327212ef96	3310	/******************************************************************************/
Kojto	112:6f327212ef96	3311	/* */
Kojto	112:6f327212ef96	3312	/* Serial Peripheral Interface (SPI) */
Kojto	112:6f327212ef96	3313	/* */
Kojto	112:6f327212ef96	3314	/******************************************************************************/
Kojto	112:6f327212ef96	3315
Kojto	112:6f327212ef96	3316	/***************** Bit definition for SPI_CR1 register ******************/
Kojto	112:6f327212ef96	3317	#define SPI_CR1_CPHA ((uint32_t)0x00000001) /!< Clock Phase /
Kojto	112:6f327212ef96	3318	#define SPI_CR1_CPOL ((uint32_t)0x00000002) /!< Clock Polarity /
Kojto	112:6f327212ef96	3319	#define SPI_CR1_MSTR ((uint32_t)0x00000004) /!< Master Selection /
Kojto	112:6f327212ef96	3320
Kojto	112:6f327212ef96	3321	#define SPI_CR1_BR ((uint32_t)0x00000038) /!< BR[2:0] bits (Baud Rate Control) /
Kojto	112:6f327212ef96	3322	#define SPI_CR1_BR_0 ((uint32_t)0x00000008) /!< Bit 0 /
Kojto	112:6f327212ef96	3323	#define SPI_CR1_BR_1 ((uint32_t)0x00000010) /!< Bit 1 /
Kojto	112:6f327212ef96	3324	#define SPI_CR1_BR_2 ((uint32_t)0x00000020) /!< Bit 2 /
Kojto	112:6f327212ef96	3325
Kojto	112:6f327212ef96	3326	#define SPI_CR1_SPE ((uint32_t)0x00000040) /!< SPI Enable /
Kojto	112:6f327212ef96	3327	#define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /!< Frame Format /
Kojto	112:6f327212ef96	3328	#define SPI_CR1_SSI ((uint32_t)0x00000100) /!< Internal slave select /
Kojto	112:6f327212ef96	3329	#define SPI_CR1_SSM ((uint32_t)0x00000200) /!< Software slave management /
Kojto	112:6f327212ef96	3330	#define SPI_CR1_RXONLY ((uint32_t)0x00000400) /!< Receive only /
Kojto	112:6f327212ef96	3331	#define SPI_CR1_DFF ((uint32_t)0x00000800) /!< Data Frame Format /
Kojto	112:6f327212ef96	3332	#define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /!< Transmit CRC next /
Kojto	112:6f327212ef96	3333	#define SPI_CR1_CRCEN ((uint32_t)0x00002000) /!< Hardware CRC calculation enable /
Kojto	112:6f327212ef96	3334	#define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /!< Output enable in bidirectional mode /
Kojto	112:6f327212ef96	3335	#define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /!< Bidirectional data mode enable /
Kojto	112:6f327212ef96	3336
Kojto	112:6f327212ef96	3337	/***************** Bit definition for SPI_CR2 register ******************/
Kojto	112:6f327212ef96	3338	#define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /!< Rx Buffer DMA Enable /
Kojto	112:6f327212ef96	3339	#define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /!< Tx Buffer DMA Enable /
Kojto	112:6f327212ef96	3340	#define SPI_CR2_SSOE ((uint32_t)0x00000004) /!< SS Output Enable /
Kojto	112:6f327212ef96	3341	#define SPI_CR2_FRF ((uint32_t)0x00000010) /!< Frame format /
Kojto	112:6f327212ef96	3342	#define SPI_CR2_ERRIE ((uint32_t)0x00000020) /!< Error Interrupt Enable /
Kojto	112:6f327212ef96	3343	#define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /!< RX buffer Not Empty Interrupt Enable /
Kojto	112:6f327212ef96	3344	#define SPI_CR2_TXEIE ((uint32_t)0x00000080) /!< Tx buffer Empty Interrupt Enable /
Kojto	112:6f327212ef96	3345
Kojto	112:6f327212ef96	3346	/****************** Bit definition for SPI_SR register ******************/
Kojto	112:6f327212ef96	3347	#define SPI_SR_RXNE ((uint32_t)0x00000001) /!< Receive buffer Not Empty /
Kojto	112:6f327212ef96	3348	#define SPI_SR_TXE ((uint32_t)0x00000002) /!< Transmit buffer Empty /
Kojto	112:6f327212ef96	3349	#define SPI_SR_CHSIDE ((uint32_t)0x00000004) /!< Channel side /
Kojto	112:6f327212ef96	3350	#define SPI_SR_UDR ((uint32_t)0x00000008) /!< Underrun flag /
Kojto	112:6f327212ef96	3351	#define SPI_SR_CRCERR ((uint32_t)0x00000010) /!< CRC Error flag /
Kojto	112:6f327212ef96	3352	#define SPI_SR_MODF ((uint32_t)0x00000020) /!< Mode fault /
Kojto	112:6f327212ef96	3353	#define SPI_SR_OVR ((uint32_t)0x00000040) /!< Overrun flag /
Kojto	112:6f327212ef96	3354	#define SPI_SR_BSY ((uint32_t)0x00000080) /!< Busy flag /
Kojto	112:6f327212ef96	3355	#define SPI_SR_FRE ((uint32_t)0x00000100) /!<Frame format error flag /
Kojto	112:6f327212ef96	3356
Kojto	112:6f327212ef96	3357	/****************** Bit definition for SPI_DR register ******************/
Kojto	112:6f327212ef96	3358	#define SPI_DR_DR ((uint32_t)0x0000FFFF) /!< Data Register /
Kojto	112:6f327212ef96	3359
Kojto	112:6f327212ef96	3360	/***************** Bit definition for SPI_CRCPR register ****************/
Kojto	112:6f327212ef96	3361	#define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /!< CRC polynomial register /
Kojto	112:6f327212ef96	3362
Kojto	112:6f327212ef96	3363	/**************** Bit definition for SPI_RXCRCR register ****************/
Kojto	112:6f327212ef96	3364	#define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /!< Rx CRC Register /
Kojto	112:6f327212ef96	3365
Kojto	112:6f327212ef96	3366	/**************** Bit definition for SPI_TXCRCR register ****************/
Kojto	112:6f327212ef96	3367	#define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /!< Tx CRC Register /
Kojto	112:6f327212ef96	3368
Kojto	112:6f327212ef96	3369	/**************** Bit definition for SPI_I2SCFGR register ***************/
Kojto	112:6f327212ef96	3370	#define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /!<Channel length (number of bits per audio channel) /
Kojto	112:6f327212ef96	3371
Kojto	112:6f327212ef96	3372	#define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /!<DATLEN[1:0] bits (Data length to be transferred) /
Kojto	112:6f327212ef96	3373	#define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /!<Bit 0 /
Kojto	112:6f327212ef96	3374	#define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /!<Bit 1 /
Kojto	112:6f327212ef96	3375
Kojto	112:6f327212ef96	3376	#define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /!<steady state clock polarity /
Kojto	112:6f327212ef96	3377
Kojto	112:6f327212ef96	3378	#define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /!<I2SSTD[1:0] bits (I2S standard selection) /
Kojto	112:6f327212ef96	3379	#define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /!<Bit 0 /
Kojto	112:6f327212ef96	3380	#define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /!<Bit 1 /
Kojto	112:6f327212ef96	3381
Kojto	112:6f327212ef96	3382	#define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /!<PCM frame synchronization /
Kojto	112:6f327212ef96	3383
Kojto	112:6f327212ef96	3384	#define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /!<I2SCFG[1:0] bits (I2S configuration mode) /
Kojto	112:6f327212ef96	3385	#define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /!<Bit 0 /
Kojto	112:6f327212ef96	3386	#define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /!<Bit 1 /
Kojto	112:6f327212ef96	3387
Kojto	112:6f327212ef96	3388	#define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /!<I2S Enable /
Kojto	112:6f327212ef96	3389	#define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /!<I2S mode selection /
Kojto	112:6f327212ef96	3390
Kojto	112:6f327212ef96	3391	/**************** Bit definition for SPI_I2SPR register *****************/
Kojto	112:6f327212ef96	3392	#define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /!<I2S Linear prescaler /
Kojto	112:6f327212ef96	3393	#define SPI_I2SPR_ODD ((uint32_t)0x00000100) /!<Odd factor for the prescaler /
Kojto	112:6f327212ef96	3394	#define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /!<Master Clock Output Enable /
Kojto	112:6f327212ef96	3395
Kojto	112:6f327212ef96	3396	/******************************************************************************/
Kojto	112:6f327212ef96	3397	/* */
Kojto	112:6f327212ef96	3398	/* System Configuration (SYSCFG) */
Kojto	112:6f327212ef96	3399	/* */
Kojto	112:6f327212ef96	3400	/******************************************************************************/
Kojto	112:6f327212ef96	3401	/*************** Bit definition for SYSCFG_MEMRMP register **************/
Kojto	112:6f327212ef96	3402	#define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000003) /!< SYSCFG_Memory Remap Config /
Kojto	112:6f327212ef96	3403	#define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001) /!< Bit 0 /
Kojto	112:6f327212ef96	3404	#define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002) /!< Bit 1 /
Kojto	112:6f327212ef96	3405	#define SYSCFG_MEMRMP_BOOT_MODE ((uint32_t)0x00000300) /!< Boot mode Config /
Kojto	112:6f327212ef96	3406	#define SYSCFG_MEMRMP_BOOT_MODE_0 ((uint32_t)0x00000100) /!< Bit 0 /
Kojto	112:6f327212ef96	3407	#define SYSCFG_MEMRMP_BOOT_MODE_1 ((uint32_t)0x00000200) /!< Bit 1 /
Kojto	112:6f327212ef96	3408
Kojto	112:6f327212ef96	3409	/*************** Bit definition for SYSCFG_PMC register *****************/
Kojto	112:6f327212ef96	3410	#define SYSCFG_PMC_USB_PU ((uint32_t)0x00000001) /!< SYSCFG PMC /
Kojto	112:6f327212ef96	3411
Kojto	112:6f327212ef96	3412	/*************** Bit definition for SYSCFG_EXTICR1 register *************/
Kojto	112:6f327212ef96	3413	#define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x0000000F) /!< EXTI 0 configuration /
Kojto	112:6f327212ef96	3414	#define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x000000F0) /!< EXTI 1 configuration /
Kojto	112:6f327212ef96	3415	#define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x00000F00) /!< EXTI 2 configuration /
Kojto	112:6f327212ef96	3416	#define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0x0000F000) /!< EXTI 3 configuration /
Kojto	112:6f327212ef96	3417
Kojto	112:6f327212ef96	3418	/**
Kojto	112:6f327212ef96	3419	* @brief EXTI0 configuration
Kojto	112:6f327212ef96	3420	*/
Kojto	112:6f327212ef96	3421	#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /!< PA[0] pin /
Kojto	112:6f327212ef96	3422	#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /!< PB[0] pin /
Kojto	112:6f327212ef96	3423	#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /!< PC[0] pin /
Kojto	112:6f327212ef96	3424	#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /!< PD[0] pin /
Kojto	112:6f327212ef96	3425	#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /!< PE[0] pin /
Kojto	112:6f327212ef96	3426	#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000005) /!< PH[0] pin /
Kojto	112:6f327212ef96	3427	#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000006) /!< PF[0] pin /
Kojto	112:6f327212ef96	3428	#define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000007) /!< PG[0] pin /
Kojto	112:6f327212ef96	3429
Kojto	112:6f327212ef96	3430	/**
Kojto	112:6f327212ef96	3431	* @brief EXTI1 configuration
Kojto	112:6f327212ef96	3432	*/
Kojto	112:6f327212ef96	3433	#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /!< PA[1] pin /
Kojto	112:6f327212ef96	3434	#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /!< PB[1] pin /
Kojto	112:6f327212ef96	3435	#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /!< PC[1] pin /
Kojto	112:6f327212ef96	3436	#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /!< PD[1] pin /
Kojto	112:6f327212ef96	3437	#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /!< PE[1] pin /
Kojto	112:6f327212ef96	3438	#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000050) /!< PH[1] pin /
Kojto	112:6f327212ef96	3439	#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000060) /!< PF[1] pin /
Kojto	112:6f327212ef96	3440	#define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000070) /!< PG[1] pin /
Kojto	112:6f327212ef96	3441
Kojto	112:6f327212ef96	3442	/**
Kojto	112:6f327212ef96	3443	* @brief EXTI2 configuration
Kojto	112:6f327212ef96	3444	*/
Kojto	112:6f327212ef96	3445	#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /!< PA[2] pin /
Kojto	112:6f327212ef96	3446	#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /!< PB[2] pin /
Kojto	112:6f327212ef96	3447	#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /!< PC[2] pin /
Kojto	112:6f327212ef96	3448	#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /!< PD[2] pin /
Kojto	112:6f327212ef96	3449	#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /!< PE[2] pin /
Kojto	112:6f327212ef96	3450	#define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x00000500) /!< PH[2] pin /
Kojto	112:6f327212ef96	3451	#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000600) /!< PF[2] pin /
Kojto	112:6f327212ef96	3452	#define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000700) /!< PG[2] pin /
Kojto	112:6f327212ef96	3453
Kojto	112:6f327212ef96	3454	/**
Kojto	112:6f327212ef96	3455	* @brief EXTI3 configuration
Kojto	112:6f327212ef96	3456	*/
Kojto	112:6f327212ef96	3457	#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /!< PA[3] pin /
Kojto	112:6f327212ef96	3458	#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /!< PB[3] pin /
Kojto	112:6f327212ef96	3459	#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /!< PC[3] pin /
Kojto	112:6f327212ef96	3460	#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /!< PD[3] pin /
Kojto	112:6f327212ef96	3461	#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /!< PE[3] pin /
Kojto	112:6f327212ef96	3462	#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00003000) /!< PF[3] pin /
Kojto	112:6f327212ef96	3463	#define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00004000) /!< PG[3] pin /
Kojto	112:6f327212ef96	3464
Kojto	112:6f327212ef96	3465	/*************** Bit definition for SYSCFG_EXTICR2 register ***************/
Kojto	112:6f327212ef96	3466	#define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x0000000F) /!< EXTI 4 configuration /
Kojto	112:6f327212ef96	3467	#define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x000000F0) /!< EXTI 5 configuration /
Kojto	112:6f327212ef96	3468	#define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x00000F00) /!< EXTI 6 configuration /
Kojto	112:6f327212ef96	3469	#define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0x0000F000) /!< EXTI 7 configuration /
Kojto	112:6f327212ef96	3470
Kojto	112:6f327212ef96	3471	/**
Kojto	112:6f327212ef96	3472	* @brief EXTI4 configuration
Kojto	112:6f327212ef96	3473	*/
Kojto	112:6f327212ef96	3474	#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /!< PA[4] pin /
Kojto	112:6f327212ef96	3475	#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /!< PB[4] pin /
Kojto	112:6f327212ef96	3476	#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /!< PC[4] pin /
Kojto	112:6f327212ef96	3477	#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /!< PD[4] pin /
Kojto	112:6f327212ef96	3478	#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /!< PE[4] pin /
Kojto	112:6f327212ef96	3479	#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000006) /!< PF[4] pin /
Kojto	112:6f327212ef96	3480	#define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000007) /!< PG[4] pin /
Kojto	112:6f327212ef96	3481
Kojto	112:6f327212ef96	3482	/**
Kojto	112:6f327212ef96	3483	* @brief EXTI5 configuration
Kojto	112:6f327212ef96	3484	*/
Kojto	112:6f327212ef96	3485	#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /!< PA[5] pin /
Kojto	112:6f327212ef96	3486	#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /!< PB[5] pin /
Kojto	112:6f327212ef96	3487	#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /!< PC[5] pin /
Kojto	112:6f327212ef96	3488	#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /!< PD[5] pin /
Kojto	112:6f327212ef96	3489	#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /!< PE[5] pin /
Kojto	112:6f327212ef96	3490	#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000060) /!< PF[5] pin /
Kojto	112:6f327212ef96	3491	#define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000070) /!< PG[5] pin /
Kojto	112:6f327212ef96	3492
Kojto	112:6f327212ef96	3493	/**
Kojto	112:6f327212ef96	3494	* @brief EXTI6 configuration
Kojto	112:6f327212ef96	3495	*/
Kojto	112:6f327212ef96	3496	#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /!< PA[6] pin /
Kojto	112:6f327212ef96	3497	#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /!< PB[6] pin /
Kojto	112:6f327212ef96	3498	#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /!< PC[6] pin /
Kojto	112:6f327212ef96	3499	#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /!< PD[6] pin /
Kojto	112:6f327212ef96	3500	#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /!< PE[6] pin /
Kojto	112:6f327212ef96	3501	#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000600) /!< PF[6] pin /
Kojto	112:6f327212ef96	3502	#define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000700) /!< PG[6] pin /
Kojto	112:6f327212ef96	3503
Kojto	112:6f327212ef96	3504	/**
Kojto	112:6f327212ef96	3505	* @brief EXTI7 configuration
Kojto	112:6f327212ef96	3506	*/
Kojto	112:6f327212ef96	3507	#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /!< PA[7] pin /
Kojto	112:6f327212ef96	3508	#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /!< PB[7] pin /
Kojto	112:6f327212ef96	3509	#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /!< PC[7] pin /
Kojto	112:6f327212ef96	3510	#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /!< PD[7] pin /
Kojto	112:6f327212ef96	3511	#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /!< PE[7] pin /
Kojto	112:6f327212ef96	3512	#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00006000) /!< PF[7] pin /
Kojto	112:6f327212ef96	3513	#define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00007000) /!< PG[7] pin /
Kojto	112:6f327212ef96	3514
Kojto	112:6f327212ef96	3515	/*************** Bit definition for SYSCFG_EXTICR3 register ***************/
Kojto	112:6f327212ef96	3516	#define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x0000000F) /!< EXTI 8 configuration /
Kojto	112:6f327212ef96	3517	#define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x000000F0) /!< EXTI 9 configuration /
Kojto	112:6f327212ef96	3518	#define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x00000F00) /!< EXTI 10 configuration /
Kojto	112:6f327212ef96	3519	#define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0x0000F000) /!< EXTI 11 configuration /
Kojto	112:6f327212ef96	3520
Kojto	112:6f327212ef96	3521	/**
Kojto	112:6f327212ef96	3522	* @brief EXTI8 configuration
Kojto	112:6f327212ef96	3523	*/
Kojto	112:6f327212ef96	3524	#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /!< PA[8] pin /
Kojto	112:6f327212ef96	3525	#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /!< PB[8] pin /
Kojto	112:6f327212ef96	3526	#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /!< PC[8] pin /
Kojto	112:6f327212ef96	3527	#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /!< PD[8] pin /
Kojto	112:6f327212ef96	3528	#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /!< PE[8] pin /
Kojto	112:6f327212ef96	3529	#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000006) /!< PF[8] pin /
Kojto	112:6f327212ef96	3530	#define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000007) /!< PG[8] pin /
Kojto	112:6f327212ef96	3531
Kojto	112:6f327212ef96	3532	/**
Kojto	112:6f327212ef96	3533	* @brief EXTI9 configuration
Kojto	112:6f327212ef96	3534	*/
Kojto	112:6f327212ef96	3535	#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /!< PA[9] pin /
Kojto	112:6f327212ef96	3536	#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /!< PB[9] pin /
Kojto	112:6f327212ef96	3537	#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /!< PC[9] pin /
Kojto	112:6f327212ef96	3538	#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /!< PD[9] pin /
Kojto	112:6f327212ef96	3539	#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /!< PE[9] pin /
Kojto	112:6f327212ef96	3540	#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000060) /!< PF[9] pin /
Kojto	112:6f327212ef96	3541	#define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000070) /!< PG[9] pin /
Kojto	112:6f327212ef96	3542
Kojto	112:6f327212ef96	3543	/**
Kojto	112:6f327212ef96	3544	* @brief EXTI10 configuration
Kojto	112:6f327212ef96	3545	*/
Kojto	112:6f327212ef96	3546	#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /!< PA[10] pin /
Kojto	112:6f327212ef96	3547	#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /!< PB[10] pin /
Kojto	112:6f327212ef96	3548	#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /!< PC[10] pin /
Kojto	112:6f327212ef96	3549	#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /!< PD[10] pin /
Kojto	112:6f327212ef96	3550	#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /!< PE[10] pin /
Kojto	112:6f327212ef96	3551	#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000600) /!< PF[10] pin /
Kojto	112:6f327212ef96	3552	#define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000700) /!< PG[10] pin /
Kojto	112:6f327212ef96	3553
Kojto	112:6f327212ef96	3554	/**
Kojto	112:6f327212ef96	3555	* @brief EXTI11 configuration
Kojto	112:6f327212ef96	3556	*/
Kojto	112:6f327212ef96	3557	#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /!< PA[11] pin /
Kojto	112:6f327212ef96	3558	#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /!< PB[11] pin /
Kojto	112:6f327212ef96	3559	#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /!< PC[11] pin /
Kojto	112:6f327212ef96	3560	#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /!< PD[11] pin /
Kojto	112:6f327212ef96	3561	#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /!< PE[11] pin /
Kojto	112:6f327212ef96	3562	#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00006000) /!< PF[11] pin /
Kojto	112:6f327212ef96	3563	#define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00007000) /!< PG[11] pin /
Kojto	112:6f327212ef96	3564
Kojto	112:6f327212ef96	3565	/*************** Bit definition for SYSCFG_EXTICR4 register ***************/
Kojto	112:6f327212ef96	3566	#define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x0000000F) /!< EXTI 12 configuration /
Kojto	112:6f327212ef96	3567	#define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x000000F0) /!< EXTI 13 configuration /
Kojto	112:6f327212ef96	3568	#define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x00000F00) /!< EXTI 14 configuration /
Kojto	112:6f327212ef96	3569	#define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0x0000F000) /!< EXTI 15 configuration /
Kojto	112:6f327212ef96	3570
Kojto	112:6f327212ef96	3571	/**
Kojto	112:6f327212ef96	3572	* @brief EXTI12 configuration
Kojto	112:6f327212ef96	3573	*/
Kojto	112:6f327212ef96	3574	#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /!< PA[12] pin /
Kojto	112:6f327212ef96	3575	#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /!< PB[12] pin /
Kojto	112:6f327212ef96	3576	#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /!< PC[12] pin /
Kojto	112:6f327212ef96	3577	#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /!< PD[12] pin /
Kojto	112:6f327212ef96	3578	#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /!< PE[12] pin /
Kojto	112:6f327212ef96	3579	#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000006) /!< PF[12] pin /
Kojto	112:6f327212ef96	3580	#define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000007) /!< PG[12] pin /
Kojto	112:6f327212ef96	3581
Kojto	112:6f327212ef96	3582	/**
Kojto	112:6f327212ef96	3583	* @brief EXTI13 configuration
Kojto	112:6f327212ef96	3584	*/
Kojto	112:6f327212ef96	3585	#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /!< PA[13] pin /
Kojto	112:6f327212ef96	3586	#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /!< PB[13] pin /
Kojto	112:6f327212ef96	3587	#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /!< PC[13] pin /
Kojto	112:6f327212ef96	3588	#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /!< PD[13] pin /
Kojto	112:6f327212ef96	3589	#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /!< PE[13] pin /
Kojto	112:6f327212ef96	3590	#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000060) /!< PF[13] pin /
Kojto	112:6f327212ef96	3591	#define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000070) /!< PG[13] pin /
Kojto	112:6f327212ef96	3592
Kojto	112:6f327212ef96	3593	/**
Kojto	112:6f327212ef96	3594	* @brief EXTI14 configuration
Kojto	112:6f327212ef96	3595	*/
Kojto	112:6f327212ef96	3596	#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /!< PA[14] pin /
Kojto	112:6f327212ef96	3597	#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /!< PB[14] pin /
Kojto	112:6f327212ef96	3598	#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /!< PC[14] pin /
Kojto	112:6f327212ef96	3599	#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /!< PD[14] pin /
Kojto	112:6f327212ef96	3600	#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /!< PE[14] pin /
Kojto	112:6f327212ef96	3601	#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000600) /!< PF[14] pin /
Kojto	112:6f327212ef96	3602	#define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000700) /!< PG[14] pin /
Kojto	112:6f327212ef96	3603
Kojto	112:6f327212ef96	3604	/**
Kojto	112:6f327212ef96	3605	* @brief EXTI15 configuration
Kojto	112:6f327212ef96	3606	*/
Kojto	112:6f327212ef96	3607	#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /!< PA[15] pin /
Kojto	112:6f327212ef96	3608	#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /!< PB[15] pin /
Kojto	112:6f327212ef96	3609	#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /!< PC[15] pin /
Kojto	112:6f327212ef96	3610	#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /!< PD[15] pin /
Kojto	112:6f327212ef96	3611	#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /!< PE[15] pin /
Kojto	112:6f327212ef96	3612	#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00006000) /!< PF[15] pin /
Kojto	112:6f327212ef96	3613	#define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00007000) /!< PG[15] pin /
Kojto	112:6f327212ef96	3614
Kojto	112:6f327212ef96	3615	/******************************************************************************/
Kojto	112:6f327212ef96	3616	/* */
Kojto	112:6f327212ef96	3617	/* Routing Interface (RI) */
Kojto	112:6f327212ef96	3618	/* */
Kojto	112:6f327212ef96	3619	/******************************************************************************/
Kojto	112:6f327212ef96	3620
Kojto	112:6f327212ef96	3621	/****************** Bit definition for RI_ICR register ******************/
Kojto	112:6f327212ef96	3622	#define RI_ICR_IC1OS ((uint32_t)0x0000000F) /!< IC1OS[3:0] bits (Input Capture 1 select bits) /
Kojto	112:6f327212ef96	3623	#define RI_ICR_IC1OS_0 ((uint32_t)0x00000001) /!< Bit 0 /
Kojto	112:6f327212ef96	3624	#define RI_ICR_IC1OS_1 ((uint32_t)0x00000002) /!< Bit 1 /
Kojto	112:6f327212ef96	3625	#define RI_ICR_IC1OS_2 ((uint32_t)0x00000004) /!< Bit 2 /
Kojto	112:6f327212ef96	3626	#define RI_ICR_IC1OS_3 ((uint32_t)0x00000008) /!< Bit 3 /
Kojto	112:6f327212ef96	3627
Kojto	112:6f327212ef96	3628	#define RI_ICR_IC2OS ((uint32_t)0x000000F0) /!< IC2OS[3:0] bits (Input Capture 2 select bits) /
Kojto	112:6f327212ef96	3629	#define RI_ICR_IC2OS_0 ((uint32_t)0x00000010) /!< Bit 0 /
Kojto	112:6f327212ef96	3630	#define RI_ICR_IC2OS_1 ((uint32_t)0x00000020) /!< Bit 1 /
Kojto	112:6f327212ef96	3631	#define RI_ICR_IC2OS_2 ((uint32_t)0x00000040) /!< Bit 2 /
Kojto	112:6f327212ef96	3632	#define RI_ICR_IC2OS_3 ((uint32_t)0x00000080) /!< Bit 3 /
Kojto	112:6f327212ef96	3633
Kojto	112:6f327212ef96	3634	#define RI_ICR_IC3OS ((uint32_t)0x00000F00) /!< IC3OS[3:0] bits (Input Capture 3 select bits) /
Kojto	112:6f327212ef96	3635	#define RI_ICR_IC3OS_0 ((uint32_t)0x00000100) /!< Bit 0 /
Kojto	112:6f327212ef96	3636	#define RI_ICR_IC3OS_1 ((uint32_t)0x00000200) /!< Bit 1 /
Kojto	112:6f327212ef96	3637	#define RI_ICR_IC3OS_2 ((uint32_t)0x00000400) /!< Bit 2 /
Kojto	112:6f327212ef96	3638	#define RI_ICR_IC3OS_3 ((uint32_t)0x00000800) /!< Bit 3 /
Kojto	112:6f327212ef96	3639
Kojto	112:6f327212ef96	3640	#define RI_ICR_IC4OS ((uint32_t)0x0000F000) /!< IC4OS[3:0] bits (Input Capture 4 select bits) /
Kojto	112:6f327212ef96	3641	#define RI_ICR_IC4OS_0 ((uint32_t)0x00001000) /!< Bit 0 /
Kojto	112:6f327212ef96	3642	#define RI_ICR_IC4OS_1 ((uint32_t)0x00002000) /!< Bit 1 /
Kojto	112:6f327212ef96	3643	#define RI_ICR_IC4OS_2 ((uint32_t)0x00004000) /!< Bit 2 /
Kojto	112:6f327212ef96	3644	#define RI_ICR_IC4OS_3 ((uint32_t)0x00008000) /!< Bit 3 /
Kojto	112:6f327212ef96	3645
Kojto	112:6f327212ef96	3646	#define RI_ICR_TIM ((uint32_t)0x00030000) /!< TIM[3:0] bits (Timers select bits) /
Kojto	112:6f327212ef96	3647	#define RI_ICR_TIM_0 ((uint32_t)0x00010000) /!< Bit 0 /
Kojto	112:6f327212ef96	3648	#define RI_ICR_TIM_1 ((uint32_t)0x00020000) /!< Bit 1 /
Kojto	112:6f327212ef96	3649
Kojto	112:6f327212ef96	3650	#define RI_ICR_IC1 ((uint32_t)0x00040000) /!< Input capture 1 /
Kojto	112:6f327212ef96	3651	#define RI_ICR_IC2 ((uint32_t)0x00080000) /!< Input capture 2 /
Kojto	112:6f327212ef96	3652	#define RI_ICR_IC3 ((uint32_t)0x00100000) /!< Input capture 3 /
Kojto	112:6f327212ef96	3653	#define RI_ICR_IC4 ((uint32_t)0x00200000) /!< Input capture 4 /
Kojto	112:6f327212ef96	3654
Kojto	112:6f327212ef96	3655	/****************** Bit definition for RI_ASCR1 register ******************/
Kojto	112:6f327212ef96	3656	#define RI_ASCR1_CH ((uint32_t)0x7BFDFFFF) /!< AS_CH[25:18] & AS_CH[15:0] bits ( Analog switches selection bits) /
Kojto	112:6f327212ef96	3657	#define RI_ASCR1_CH_0 ((uint32_t)0x00000001) /!< Bit 0 /
Kojto	112:6f327212ef96	3658	#define RI_ASCR1_CH_1 ((uint32_t)0x00000002) /!< Bit 1 /
Kojto	112:6f327212ef96	3659	#define RI_ASCR1_CH_2 ((uint32_t)0x00000004) /!< Bit 2 /
Kojto	112:6f327212ef96	3660	#define RI_ASCR1_CH_3 ((uint32_t)0x00000008) /!< Bit 3 /
Kojto	112:6f327212ef96	3661	#define RI_ASCR1_CH_4 ((uint32_t)0x00000010) /!< Bit 4 /
Kojto	112:6f327212ef96	3662	#define RI_ASCR1_CH_5 ((uint32_t)0x00000020) /!< Bit 5 /
Kojto	112:6f327212ef96	3663	#define RI_ASCR1_CH_6 ((uint32_t)0x00000040) /!< Bit 6 /
Kojto	112:6f327212ef96	3664	#define RI_ASCR1_CH_7 ((uint32_t)0x00000080) /!< Bit 7 /
Kojto	112:6f327212ef96	3665	#define RI_ASCR1_CH_8 ((uint32_t)0x00000100) /!< Bit 8 /
Kojto	112:6f327212ef96	3666	#define RI_ASCR1_CH_9 ((uint32_t)0x00000200) /!< Bit 9 /
Kojto	112:6f327212ef96	3667	#define RI_ASCR1_CH_10 ((uint32_t)0x00000400) /!< Bit 10 /
Kojto	112:6f327212ef96	3668	#define RI_ASCR1_CH_11 ((uint32_t)0x00000800) /!< Bit 11 /
Kojto	112:6f327212ef96	3669	#define RI_ASCR1_CH_12 ((uint32_t)0x00001000) /!< Bit 12 /
Kojto	112:6f327212ef96	3670	#define RI_ASCR1_CH_13 ((uint32_t)0x00002000) /!< Bit 13 /
Kojto	112:6f327212ef96	3671	#define RI_ASCR1_CH_14 ((uint32_t)0x00004000) /!< Bit 14 /
Kojto	112:6f327212ef96	3672	#define RI_ASCR1_CH_15 ((uint32_t)0x00008000) /!< Bit 15 /
Kojto	112:6f327212ef96	3673	#define RI_ASCR1_CH_31 ((uint32_t)0x00010000) /!< Bit 16 /
Kojto	112:6f327212ef96	3674	#define RI_ASCR1_CH_18 ((uint32_t)0x00040000) /!< Bit 18 /
Kojto	112:6f327212ef96	3675	#define RI_ASCR1_CH_19 ((uint32_t)0x00080000) /!< Bit 19 /
Kojto	112:6f327212ef96	3676	#define RI_ASCR1_CH_20 ((uint32_t)0x00100000) /!< Bit 20 /
Kojto	112:6f327212ef96	3677	#define RI_ASCR1_CH_21 ((uint32_t)0x00200000) /!< Bit 21 /
Kojto	112:6f327212ef96	3678	#define RI_ASCR1_CH_22 ((uint32_t)0x00400000) /!< Bit 22 /
Kojto	112:6f327212ef96	3679	#define RI_ASCR1_CH_23 ((uint32_t)0x00800000) /!< Bit 23 /
Kojto	112:6f327212ef96	3680	#define RI_ASCR1_CH_24 ((uint32_t)0x01000000) /!< Bit 24 /
Kojto	112:6f327212ef96	3681	#define RI_ASCR1_CH_25 ((uint32_t)0x02000000) /!< Bit 25 /
Kojto	112:6f327212ef96	3682	#define RI_ASCR1_VCOMP ((uint32_t)0x04000000) /!< ADC analog switch selection for internal node to COMP1 /
Kojto	112:6f327212ef96	3683	#define RI_ASCR1_CH_27 ((uint32_t)0x00400000) /!< Bit 27 /
Kojto	112:6f327212ef96	3684	#define RI_ASCR1_CH_28 ((uint32_t)0x00800000) /!< Bit 28 /
Kojto	112:6f327212ef96	3685	#define RI_ASCR1_CH_29 ((uint32_t)0x01000000) /!< Bit 29 /
Kojto	112:6f327212ef96	3686	#define RI_ASCR1_CH_30 ((uint32_t)0x02000000) /!< Bit 30 /
Kojto	112:6f327212ef96	3687	#define RI_ASCR1_SCM ((uint32_t)0x80000000) /!< I/O Switch control mode /
Kojto	112:6f327212ef96	3688
Kojto	112:6f327212ef96	3689	/****************** Bit definition for RI_ASCR2 register ******************/
Kojto	112:6f327212ef96	3690	#define RI_ASCR2_GR10_1 ((uint32_t)0x00000001) /!< GR10-1 selection bit /
Kojto	112:6f327212ef96	3691	#define RI_ASCR2_GR10_2 ((uint32_t)0x00000002) /!< GR10-2 selection bit /
Kojto	112:6f327212ef96	3692	#define RI_ASCR2_GR10_3 ((uint32_t)0x00000004) /!< GR10-3 selection bit /
Kojto	112:6f327212ef96	3693	#define RI_ASCR2_GR10_4 ((uint32_t)0x00000008) /!< GR10-4 selection bit /
Kojto	112:6f327212ef96	3694	#define RI_ASCR2_GR6_1 ((uint32_t)0x00000010) /!< GR6-1 selection bit /
Kojto	112:6f327212ef96	3695	#define RI_ASCR2_GR6_2 ((uint32_t)0x00000020) /!< GR6-2 selection bit /
Kojto	112:6f327212ef96	3696	#define RI_ASCR2_GR5_1 ((uint32_t)0x00000040) /!< GR5-1 selection bit /
Kojto	112:6f327212ef96	3697	#define RI_ASCR2_GR5_2 ((uint32_t)0x00000080) /!< GR5-2 selection bit /
Kojto	112:6f327212ef96	3698	#define RI_ASCR2_GR5_3 ((uint32_t)0x00000100) /!< GR5-3 selection bit /
Kojto	112:6f327212ef96	3699	#define RI_ASCR2_GR4_1 ((uint32_t)0x00000200) /!< GR4-1 selection bit /
Kojto	112:6f327212ef96	3700	#define RI_ASCR2_GR4_2 ((uint32_t)0x00000400) /!< GR4-2 selection bit /
Kojto	112:6f327212ef96	3701	#define RI_ASCR2_GR4_3 ((uint32_t)0x00000800) /!< GR4-3 selection bit /
Kojto	112:6f327212ef96	3702	#define RI_ASCR2_GR4_4 ((uint32_t)0x00008000) /!< GR4-4 selection bit /
Kojto	112:6f327212ef96	3703	#define RI_ASCR2_CH0b ((uint32_t)0x00010000) /!< CH0b selection bit /
Kojto	112:6f327212ef96	3704	#define RI_ASCR2_GR6_3 ((uint32_t)0x08000000) /!< GR6-3 selection bit /
Kojto	112:6f327212ef96	3705	#define RI_ASCR2_GR6_4 ((uint32_t)0x10000000) /!< GR6-4 selection bit /
Kojto	112:6f327212ef96	3706
Kojto	112:6f327212ef96	3707	/****************** Bit definition for RI_HYSCR1 register ******************/
Kojto	112:6f327212ef96	3708	#define RI_HYSCR1_PA ((uint32_t)0x0000FFFF) /!< PA[15:0] Port A Hysteresis selection /
Kojto	112:6f327212ef96	3709	#define RI_HYSCR1_PA_0 ((uint32_t)0x00000001) /!< Bit 0 /
Kojto	112:6f327212ef96	3710	#define RI_HYSCR1_PA_1 ((uint32_t)0x00000002) /!< Bit 1 /
Kojto	112:6f327212ef96	3711	#define RI_HYSCR1_PA_2 ((uint32_t)0x00000004) /!< Bit 2 /
Kojto	112:6f327212ef96	3712	#define RI_HYSCR1_PA_3 ((uint32_t)0x00000008) /!< Bit 3 /
Kojto	112:6f327212ef96	3713	#define RI_HYSCR1_PA_4 ((uint32_t)0x00000010) /!< Bit 4 /
Kojto	112:6f327212ef96	3714	#define RI_HYSCR1_PA_5 ((uint32_t)0x00000020) /!< Bit 5 /
Kojto	112:6f327212ef96	3715	#define RI_HYSCR1_PA_6 ((uint32_t)0x00000040) /!< Bit 6 /
Kojto	112:6f327212ef96	3716	#define RI_HYSCR1_PA_7 ((uint32_t)0x00000080) /!< Bit 7 /
Kojto	112:6f327212ef96	3717	#define RI_HYSCR1_PA_8 ((uint32_t)0x00000100) /!< Bit 8 /
Kojto	112:6f327212ef96	3718	#define RI_HYSCR1_PA_9 ((uint32_t)0x00000200) /!< Bit 9 /
Kojto	112:6f327212ef96	3719	#define RI_HYSCR1_PA_10 ((uint32_t)0x00000400) /!< Bit 10 /
Kojto	112:6f327212ef96	3720	#define RI_HYSCR1_PA_11 ((uint32_t)0x00000800) /!< Bit 11 /
Kojto	112:6f327212ef96	3721	#define RI_HYSCR1_PA_12 ((uint32_t)0x00001000) /!< Bit 12 /
Kojto	112:6f327212ef96	3722	#define RI_HYSCR1_PA_13 ((uint32_t)0x00002000) /!< Bit 13 /
Kojto	112:6f327212ef96	3723	#define RI_HYSCR1_PA_14 ((uint32_t)0x00004000) /!< Bit 14 /
Kojto	112:6f327212ef96	3724	#define RI_HYSCR1_PA_15 ((uint32_t)0x00008000) /!< Bit 15 /
Kojto	112:6f327212ef96	3725
Kojto	112:6f327212ef96	3726	#define RI_HYSCR1_PB ((uint32_t)0xFFFF0000) /!< PB[15:0] Port B Hysteresis selection /
Kojto	112:6f327212ef96	3727	#define RI_HYSCR1_PB_0 ((uint32_t)0x00010000) /!< Bit 0 /
Kojto	112:6f327212ef96	3728	#define RI_HYSCR1_PB_1 ((uint32_t)0x00020000) /!< Bit 1 /
Kojto	112:6f327212ef96	3729	#define RI_HYSCR1_PB_2 ((uint32_t)0x00040000) /!< Bit 2 /
Kojto	112:6f327212ef96	3730	#define RI_HYSCR1_PB_3 ((uint32_t)0x00080000) /!< Bit 3 /
Kojto	112:6f327212ef96	3731	#define RI_HYSCR1_PB_4 ((uint32_t)0x00100000) /!< Bit 4 /
Kojto	112:6f327212ef96	3732	#define RI_HYSCR1_PB_5 ((uint32_t)0x00200000) /!< Bit 5 /
Kojto	112:6f327212ef96	3733	#define RI_HYSCR1_PB_6 ((uint32_t)0x00400000) /!< Bit 6 /
Kojto	112:6f327212ef96	3734	#define RI_HYSCR1_PB_7 ((uint32_t)0x00800000) /!< Bit 7 /
Kojto	112:6f327212ef96	3735	#define RI_HYSCR1_PB_8 ((uint32_t)0x01000000) /!< Bit 8 /
Kojto	112:6f327212ef96	3736	#define RI_HYSCR1_PB_9 ((uint32_t)0x02000000) /!< Bit 9 /
Kojto	112:6f327212ef96	3737	#define RI_HYSCR1_PB_10 ((uint32_t)0x04000000) /!< Bit 10 /
Kojto	112:6f327212ef96	3738	#define RI_HYSCR1_PB_11 ((uint32_t)0x08000000) /!< Bit 11 /
Kojto	112:6f327212ef96	3739	#define RI_HYSCR1_PB_12 ((uint32_t)0x10000000) /!< Bit 12 /
Kojto	112:6f327212ef96	3740	#define RI_HYSCR1_PB_13 ((uint32_t)0x20000000) /!< Bit 13 /
Kojto	112:6f327212ef96	3741	#define RI_HYSCR1_PB_14 ((uint32_t)0x40000000) /!< Bit 14 /
Kojto	112:6f327212ef96	3742	#define RI_HYSCR1_PB_15 ((uint32_t)0x80000000) /!< Bit 15 /
Kojto	112:6f327212ef96	3743
Kojto	112:6f327212ef96	3744	/****************** Bit definition for RI_HYSCR2 register ******************/
Kojto	112:6f327212ef96	3745	#define RI_HYSCR2_PC ((uint32_t)0x0000FFFF) /!< PC[15:0] Port C Hysteresis selection /
Kojto	112:6f327212ef96	3746	#define RI_HYSCR2_PC_0 ((uint32_t)0x00000001) /!< Bit 0 /
Kojto	112:6f327212ef96	3747	#define RI_HYSCR2_PC_1 ((uint32_t)0x00000002) /!< Bit 1 /
Kojto	112:6f327212ef96	3748	#define RI_HYSCR2_PC_2 ((uint32_t)0x00000004) /!< Bit 2 /
Kojto	112:6f327212ef96	3749	#define RI_HYSCR2_PC_3 ((uint32_t)0x00000008) /!< Bit 3 /
Kojto	112:6f327212ef96	3750	#define RI_HYSCR2_PC_4 ((uint32_t)0x00000010) /!< Bit 4 /
Kojto	112:6f327212ef96	3751	#define RI_HYSCR2_PC_5 ((uint32_t)0x00000020) /!< Bit 5 /
Kojto	112:6f327212ef96	3752	#define RI_HYSCR2_PC_6 ((uint32_t)0x00000040) /!< Bit 6 /
Kojto	112:6f327212ef96	3753	#define RI_HYSCR2_PC_7 ((uint32_t)0x00000080) /!< Bit 7 /
Kojto	112:6f327212ef96	3754	#define RI_HYSCR2_PC_8 ((uint32_t)0x00000100) /!< Bit 8 /
Kojto	112:6f327212ef96	3755	#define RI_HYSCR2_PC_9 ((uint32_t)0x00000200) /!< Bit 9 /
Kojto	112:6f327212ef96	3756	#define RI_HYSCR2_PC_10 ((uint32_t)0x00000400) /!< Bit 10 /
Kojto	112:6f327212ef96	3757	#define RI_HYSCR2_PC_11 ((uint32_t)0x00000800) /!< Bit 11 /
Kojto	112:6f327212ef96	3758	#define RI_HYSCR2_PC_12 ((uint32_t)0x00001000) /!< Bit 12 /
Kojto	112:6f327212ef96	3759	#define RI_HYSCR2_PC_13 ((uint32_t)0x00002000) /!< Bit 13 /
Kojto	112:6f327212ef96	3760	#define RI_HYSCR2_PC_14 ((uint32_t)0x00004000) /!< Bit 14 /
Kojto	112:6f327212ef96	3761	#define RI_HYSCR2_PC_15 ((uint32_t)0x00008000) /!< Bit 15 /
Kojto	112:6f327212ef96	3762
Kojto	112:6f327212ef96	3763	#define RI_HYSCR2_PD ((uint32_t)0xFFFF0000) /!< PD[15:0] Port D Hysteresis selection /
Kojto	112:6f327212ef96	3764	#define RI_HYSCR2_PD_0 ((uint32_t)0x00010000) /!< Bit 0 /
Kojto	112:6f327212ef96	3765	#define RI_HYSCR2_PD_1 ((uint32_t)0x00020000) /!< Bit 1 /
Kojto	112:6f327212ef96	3766	#define RI_HYSCR2_PD_2 ((uint32_t)0x00040000) /!< Bit 2 /
Kojto	112:6f327212ef96	3767	#define RI_HYSCR2_PD_3 ((uint32_t)0x00080000) /!< Bit 3 /
Kojto	112:6f327212ef96	3768	#define RI_HYSCR2_PD_4 ((uint32_t)0x00100000) /!< Bit 4 /
Kojto	112:6f327212ef96	3769	#define RI_HYSCR2_PD_5 ((uint32_t)0x00200000) /!< Bit 5 /
Kojto	112:6f327212ef96	3770	#define RI_HYSCR2_PD_6 ((uint32_t)0x00400000) /!< Bit 6 /
Kojto	112:6f327212ef96	3771	#define RI_HYSCR2_PD_7 ((uint32_t)0x00800000) /!< Bit 7 /
Kojto	112:6f327212ef96	3772	#define RI_HYSCR2_PD_8 ((uint32_t)0x01000000) /!< Bit 8 /
Kojto	112:6f327212ef96	3773	#define RI_HYSCR2_PD_9 ((uint32_t)0x02000000) /!< Bit 9 /
Kojto	112:6f327212ef96	3774	#define RI_HYSCR2_PD_10 ((uint32_t)0x04000000) /!< Bit 10 /
Kojto	112:6f327212ef96	3775	#define RI_HYSCR2_PD_11 ((uint32_t)0x08000000) /!< Bit 11 /
Kojto	112:6f327212ef96	3776	#define RI_HYSCR2_PD_12 ((uint32_t)0x10000000) /!< Bit 12 /
Kojto	112:6f327212ef96	3777	#define RI_HYSCR2_PD_13 ((uint32_t)0x20000000) /!< Bit 13 /
Kojto	112:6f327212ef96	3778	#define RI_HYSCR2_PD_14 ((uint32_t)0x40000000) /!< Bit 14 /
Kojto	112:6f327212ef96	3779	#define RI_HYSCR2_PD_15 ((uint32_t)0x80000000) /!< Bit 15 /
Kojto	112:6f327212ef96	3780
Kojto	112:6f327212ef96	3781	/****************** Bit definition for RI_HYSCR3 register ******************/
Kojto	112:6f327212ef96	3782	#define RI_HYSCR3_PE ((uint32_t)0x0000FFFF) /!< PE[15:0] Port E Hysteresis selection /
Kojto	112:6f327212ef96	3783	#define RI_HYSCR3_PE_0 ((uint32_t)0x00000001) /!< Bit 0 /
Kojto	112:6f327212ef96	3784	#define RI_HYSCR3_PE_1 ((uint32_t)0x00000002) /!< Bit 1 /
Kojto	112:6f327212ef96	3785	#define RI_HYSCR3_PE_2 ((uint32_t)0x00000004) /!< Bit 2 /
Kojto	112:6f327212ef96	3786	#define RI_HYSCR3_PE_3 ((uint32_t)0x00000008) /!< Bit 3 /
Kojto	112:6f327212ef96	3787	#define RI_HYSCR3_PE_4 ((uint32_t)0x00000010) /!< Bit 4 /
Kojto	112:6f327212ef96	3788	#define RI_HYSCR3_PE_5 ((uint32_t)0x00000020) /!< Bit 5 /
Kojto	112:6f327212ef96	3789	#define RI_HYSCR3_PE_6 ((uint32_t)0x00000040) /!< Bit 6 /
Kojto	112:6f327212ef96	3790	#define RI_HYSCR3_PE_7 ((uint32_t)0x00000080) /!< Bit 7 /
Kojto	112:6f327212ef96	3791	#define RI_HYSCR3_PE_8 ((uint32_t)0x00000100) /!< Bit 8 /
Kojto	112:6f327212ef96	3792	#define RI_HYSCR3_PE_9 ((uint32_t)0x00000200) /!< Bit 9 /
Kojto	112:6f327212ef96	3793	#define RI_HYSCR3_PE_10 ((uint32_t)0x00000400) /!< Bit 10 /
Kojto	112:6f327212ef96	3794	#define RI_HYSCR3_PE_11 ((uint32_t)0x00000800) /!< Bit 11 /
Kojto	112:6f327212ef96	3795	#define RI_HYSCR3_PE_12 ((uint32_t)0x00001000) /!< Bit 12 /
Kojto	112:6f327212ef96	3796	#define RI_HYSCR3_PE_13 ((uint32_t)0x00002000) /!< Bit 13 /
Kojto	112:6f327212ef96	3797	#define RI_HYSCR3_PE_14 ((uint32_t)0x00004000) /!< Bit 14 /
Kojto	112:6f327212ef96	3798	#define RI_HYSCR3_PE_15 ((uint32_t)0x00008000) /!< Bit 15 /
Kojto	112:6f327212ef96	3799
Kojto	112:6f327212ef96	3800	/****************** Bit definition for RI_ASMR1 register ******************/
Kojto	112:6f327212ef96	3801	#define RI_ASMR1_PA ((uint32_t)0x0000FFFF) /!< PA[15:0] Port A selection/
Kojto	112:6f327212ef96	3802	#define RI_ASMR1_PA_0 ((uint32_t)0x00000001) /!< Bit 0 /
Kojto	112:6f327212ef96	3803	#define RI_ASMR1_PA_1 ((uint32_t)0x00000002) /!< Bit 1 /
Kojto	112:6f327212ef96	3804	#define RI_ASMR1_PA_2 ((uint32_t)0x00000004) /!< Bit 2 /
Kojto	112:6f327212ef96	3805	#define RI_ASMR1_PA_3 ((uint32_t)0x00000008) /!< Bit 3 /
Kojto	112:6f327212ef96	3806	#define RI_ASMR1_PA_4 ((uint32_t)0x00000010) /!< Bit 4 /
Kojto	112:6f327212ef96	3807	#define RI_ASMR1_PA_5 ((uint32_t)0x00000020) /!< Bit 5 /
Kojto	112:6f327212ef96	3808	#define RI_ASMR1_PA_6 ((uint32_t)0x00000040) /!< Bit 6 /
Kojto	112:6f327212ef96	3809	#define RI_ASMR1_PA_7 ((uint32_t)0x00000080) /!< Bit 7 /
Kojto	112:6f327212ef96	3810	#define RI_ASMR1_PA_8 ((uint32_t)0x00000100) /!< Bit 8 /
Kojto	112:6f327212ef96	3811	#define RI_ASMR1_PA_9 ((uint32_t)0x00000200) /!< Bit 9 /
Kojto	112:6f327212ef96	3812	#define RI_ASMR1_PA_10 ((uint32_t)0x00000400) /!< Bit 10 /
Kojto	112:6f327212ef96	3813	#define RI_ASMR1_PA_11 ((uint32_t)0x00000800) /!< Bit 11 /
Kojto	112:6f327212ef96	3814	#define RI_ASMR1_PA_12 ((uint32_t)0x00001000) /!< Bit 12 /
Kojto	112:6f327212ef96	3815	#define RI_ASMR1_PA_13 ((uint32_t)0x00002000) /!< Bit 13 /
Kojto	112:6f327212ef96	3816	#define RI_ASMR1_PA_14 ((uint32_t)0x00004000) /!< Bit 14 /
Kojto	112:6f327212ef96	3817	#define RI_ASMR1_PA_15 ((uint32_t)0x00008000) /!< Bit 15 /
Kojto	112:6f327212ef96	3818
Kojto	112:6f327212ef96	3819	/****************** Bit definition for RI_CMR1 register ******************/
Kojto	112:6f327212ef96	3820	#define RI_CMR1_PA ((uint32_t)0x0000FFFF) /!< PA[15:0] Port A selection/
Kojto	112:6f327212ef96	3821	#define RI_CMR1_PA_0 ((uint32_t)0x00000001) /!< Bit 0 /
Kojto	112:6f327212ef96	3822	#define RI_CMR1_PA_1 ((uint32_t)0x00000002) /!< Bit 1 /
Kojto	112:6f327212ef96	3823	#define RI_CMR1_PA_2 ((uint32_t)0x00000004) /!< Bit 2 /
Kojto	112:6f327212ef96	3824	#define RI_CMR1_PA_3 ((uint32_t)0x00000008) /!< Bit 3 /
Kojto	112:6f327212ef96	3825	#define RI_CMR1_PA_4 ((uint32_t)0x00000010) /!< Bit 4 /
Kojto	112:6f327212ef96	3826	#define RI_CMR1_PA_5 ((uint32_t)0x00000020) /!< Bit 5 /
Kojto	112:6f327212ef96	3827	#define RI_CMR1_PA_6 ((uint32_t)0x00000040) /!< Bit 6 /
Kojto	112:6f327212ef96	3828	#define RI_CMR1_PA_7 ((uint32_t)0x00000080) /!< Bit 7 /
Kojto	112:6f327212ef96	3829	#define RI_CMR1_PA_8 ((uint32_t)0x00000100) /!< Bit 8 /
Kojto	112:6f327212ef96	3830	#define RI_CMR1_PA_9 ((uint32_t)0x00000200) /!< Bit 9 /
Kojto	112:6f327212ef96	3831	#define RI_CMR1_PA_10 ((uint32_t)0x00000400) /!< Bit 10 /
Kojto	112:6f327212ef96	3832	#define RI_CMR1_PA_11 ((uint32_t)0x00000800) /!< Bit 11 /
Kojto	112:6f327212ef96	3833	#define RI_CMR1_PA_12 ((uint32_t)0x00001000) /!< Bit 12 /
Kojto	112:6f327212ef96	3834	#define RI_CMR1_PA_13 ((uint32_t)0x00002000) /!< Bit 13 /
Kojto	112:6f327212ef96	3835	#define RI_CMR1_PA_14 ((uint32_t)0x00004000) /!< Bit 14 /
Kojto	112:6f327212ef96	3836	#define RI_CMR1_PA_15 ((uint32_t)0x00008000) /!< Bit 15 /
Kojto	112:6f327212ef96	3837
Kojto	112:6f327212ef96	3838	/****************** Bit definition for RI_CICR1 register ******************/
Kojto	112:6f327212ef96	3839	#define RI_CICR1_PA ((uint32_t)0x0000FFFF) /!< PA[15:0] Port A selection/
Kojto	112:6f327212ef96	3840	#define RI_CICR1_PA_0 ((uint32_t)0x00000001) /!< Bit 0 /
Kojto	112:6f327212ef96	3841	#define RI_CICR1_PA_1 ((uint32_t)0x00000002) /!< Bit 1 /
Kojto	112:6f327212ef96	3842	#define RI_CICR1_PA_2 ((uint32_t)0x00000004) /!< Bit 2 /
Kojto	112:6f327212ef96	3843	#define RI_CICR1_PA_3 ((uint32_t)0x00000008) /!< Bit 3 /
Kojto	112:6f327212ef96	3844	#define RI_CICR1_PA_4 ((uint32_t)0x00000010) /!< Bit 4 /
Kojto	112:6f327212ef96	3845	#define RI_CICR1_PA_5 ((uint32_t)0x00000020) /!< Bit 5 /
Kojto	112:6f327212ef96	3846	#define RI_CICR1_PA_6 ((uint32_t)0x00000040) /!< Bit 6 /
Kojto	112:6f327212ef96	3847	#define RI_CICR1_PA_7 ((uint32_t)0x00000080) /!< Bit 7 /
Kojto	112:6f327212ef96	3848	#define RI_CICR1_PA_8 ((uint32_t)0x00000100) /!< Bit 8 /
Kojto	112:6f327212ef96	3849	#define RI_CICR1_PA_9 ((uint32_t)0x00000200) /!< Bit 9 /
Kojto	112:6f327212ef96	3850	#define RI_CICR1_PA_10 ((uint32_t)0x00000400) /!< Bit 10 /
Kojto	112:6f327212ef96	3851	#define RI_CICR1_PA_11 ((uint32_t)0x00000800) /!< Bit 11 /
Kojto	112:6f327212ef96	3852	#define RI_CICR1_PA_12 ((uint32_t)0x00001000) /!< Bit 12 /
Kojto	112:6f327212ef96	3853	#define RI_CICR1_PA_13 ((uint32_t)0x00002000) /!< Bit 13 /
Kojto	112:6f327212ef96	3854	#define RI_CICR1_PA_14 ((uint32_t)0x00004000) /!< Bit 14 /
Kojto	112:6f327212ef96	3855	#define RI_CICR1_PA_15 ((uint32_t)0x00008000) /!< Bit 15 /
Kojto	112:6f327212ef96	3856
Kojto	112:6f327212ef96	3857	/****************** Bit definition for RI_ASMR2 register ******************/
Kojto	112:6f327212ef96	3858	#define RI_ASMR2_PB ((uint32_t)0x0000FFFF) /!< PB[15:0] Port B selection /
Kojto	112:6f327212ef96	3859	#define RI_ASMR2_PB_0 ((uint32_t)0x00000001) /!< Bit 0 /
Kojto	112:6f327212ef96	3860	#define RI_ASMR2_PB_1 ((uint32_t)0x00000002) /!< Bit 1 /
Kojto	112:6f327212ef96	3861	#define RI_ASMR2_PB_2 ((uint32_t)0x00000004) /!< Bit 2 /
Kojto	112:6f327212ef96	3862	#define RI_ASMR2_PB_3 ((uint32_t)0x00000008) /!< Bit 3 /
Kojto	112:6f327212ef96	3863	#define RI_ASMR2_PB_4 ((uint32_t)0x00000010) /!< Bit 4 /
Kojto	112:6f327212ef96	3864	#define RI_ASMR2_PB_5 ((uint32_t)0x00000020) /!< Bit 5 /
Kojto	112:6f327212ef96	3865	#define RI_ASMR2_PB_6 ((uint32_t)0x00000040) /!< Bit 6 /
Kojto	112:6f327212ef96	3866	#define RI_ASMR2_PB_7 ((uint32_t)0x00000080) /!< Bit 7 /
Kojto	112:6f327212ef96	3867	#define RI_ASMR2_PB_8 ((uint32_t)0x00000100) /!< Bit 8 /
Kojto	112:6f327212ef96	3868	#define RI_ASMR2_PB_9 ((uint32_t)0x00000200) /!< Bit 9 /
Kojto	112:6f327212ef96	3869	#define RI_ASMR2_PB_10 ((uint32_t)0x00000400) /!< Bit 10 /
Kojto	112:6f327212ef96	3870	#define RI_ASMR2_PB_11 ((uint32_t)0x00000800) /!< Bit 11 /
Kojto	112:6f327212ef96	3871	#define RI_ASMR2_PB_12 ((uint32_t)0x00001000) /!< Bit 12 /
Kojto	112:6f327212ef96	3872	#define RI_ASMR2_PB_13 ((uint32_t)0x00002000) /!< Bit 13 /
Kojto	112:6f327212ef96	3873	#define RI_ASMR2_PB_14 ((uint32_t)0x00004000) /!< Bit 14 /
Kojto	112:6f327212ef96	3874	#define RI_ASMR2_PB_15 ((uint32_t)0x00008000) /!< Bit 15 /
Kojto	112:6f327212ef96	3875
Kojto	112:6f327212ef96	3876	/****************** Bit definition for RI_CMR2 register ******************/
Kojto	112:6f327212ef96	3877	#define RI_CMR2_PB ((uint32_t)0x0000FFFF) /!< PB[15:0] Port B selection /
Kojto	112:6f327212ef96	3878	#define RI_CMR2_PB_0 ((uint32_t)0x00000001) /!< Bit 0 /
Kojto	112:6f327212ef96	3879	#define RI_CMR2_PB_1 ((uint32_t)0x00000002) /!< Bit 1 /
Kojto	112:6f327212ef96	3880	#define RI_CMR2_PB_2 ((uint32_t)0x00000004) /!< Bit 2 /
Kojto	112:6f327212ef96	3881	#define RI_CMR2_PB_3 ((uint32_t)0x00000008) /!< Bit 3 /
Kojto	112:6f327212ef96	3882	#define RI_CMR2_PB_4 ((uint32_t)0x00000010) /!< Bit 4 /
Kojto	112:6f327212ef96	3883	#define RI_CMR2_PB_5 ((uint32_t)0x00000020) /!< Bit 5 /
Kojto	112:6f327212ef96	3884	#define RI_CMR2_PB_6 ((uint32_t)0x00000040) /!< Bit 6 /
Kojto	112:6f327212ef96	3885	#define RI_CMR2_PB_7 ((uint32_t)0x00000080) /!< Bit 7 /
Kojto	112:6f327212ef96	3886	#define RI_CMR2_PB_8 ((uint32_t)0x00000100) /!< Bit 8 /
Kojto	112:6f327212ef96	3887	#define RI_CMR2_PB_9 ((uint32_t)0x00000200) /!< Bit 9 /
Kojto	112:6f327212ef96	3888	#define RI_CMR2_PB_10 ((uint32_t)0x00000400) /!< Bit 10 /
Kojto	112:6f327212ef96	3889	#define RI_CMR2_PB_11 ((uint32_t)0x00000800) /!< Bit 11 /
Kojto	112:6f327212ef96	3890	#define RI_CMR2_PB_12 ((uint32_t)0x00001000) /!< Bit 12 /
Kojto	112:6f327212ef96	3891	#define RI_CMR2_PB_13 ((uint32_t)0x00002000) /!< Bit 13 /
Kojto	112:6f327212ef96	3892	#define RI_CMR2_PB_14 ((uint32_t)0x00004000) /!< Bit 14 /
Kojto	112:6f327212ef96	3893	#define RI_CMR2_PB_15 ((uint32_t)0x00008000) /!< Bit 15 /
Kojto	112:6f327212ef96	3894
Kojto	112:6f327212ef96	3895	/****************** Bit definition for RI_CICR2 register ******************/
Kojto	112:6f327212ef96	3896	#define RI_CICR2_PB ((uint32_t)0x0000FFFF) /!< PB[15:0] Port B selection /
Kojto	112:6f327212ef96	3897	#define RI_CICR2_PB_0 ((uint32_t)0x00000001) /!< Bit 0 /
Kojto	112:6f327212ef96	3898	#define RI_CICR2_PB_1 ((uint32_t)0x00000002) /!< Bit 1 /
Kojto	112:6f327212ef96	3899	#define RI_CICR2_PB_2 ((uint32_t)0x00000004) /!< Bit 2 /
Kojto	112:6f327212ef96	3900	#define RI_CICR2_PB_3 ((uint32_t)0x00000008) /!< Bit 3 /
Kojto	112:6f327212ef96	3901	#define RI_CICR2_PB_4 ((uint32_t)0x00000010) /!< Bit 4 /
Kojto	112:6f327212ef96	3902	#define RI_CICR2_PB_5 ((uint32_t)0x00000020) /!< Bit 5 /
Kojto	112:6f327212ef96	3903	#define RI_CICR2_PB_6 ((uint32_t)0x00000040) /!< Bit 6 /
Kojto	112:6f327212ef96	3904	#define RI_CICR2_PB_7 ((uint32_t)0x00000080) /!< Bit 7 /
Kojto	112:6f327212ef96	3905	#define RI_CICR2_PB_8 ((uint32_t)0x00000100) /!< Bit 8 /
Kojto	112:6f327212ef96	3906	#define RI_CICR2_PB_9 ((uint32_t)0x00000200) /!< Bit 9 /
Kojto	112:6f327212ef96	3907	#define RI_CICR2_PB_10 ((uint32_t)0x00000400) /!< Bit 10 /
Kojto	112:6f327212ef96	3908	#define RI_CICR2_PB_11 ((uint32_t)0x00000800) /!< Bit 11 /
Kojto	112:6f327212ef96	3909	#define RI_CICR2_PB_12 ((uint32_t)0x00001000) /!< Bit 12 /
Kojto	112:6f327212ef96	3910	#define RI_CICR2_PB_13 ((uint32_t)0x00002000) /!< Bit 13 /
Kojto	112:6f327212ef96	3911	#define RI_CICR2_PB_14 ((uint32_t)0x00004000) /!< Bit 14 /
Kojto	112:6f327212ef96	3912	#define RI_CICR2_PB_15 ((uint32_t)0x00008000) /!< Bit 15 /
Kojto	112:6f327212ef96	3913
Kojto	112:6f327212ef96	3914	/****************** Bit definition for RI_ASMR3 register ******************/
Kojto	112:6f327212ef96	3915	#define RI_ASMR3_PC ((uint32_t)0x0000FFFF) /!< PC[15:0] Port C selection /
Kojto	112:6f327212ef96	3916	#define RI_ASMR3_PC_0 ((uint32_t)0x00000001) /!< Bit 0 /
Kojto	112:6f327212ef96	3917	#define RI_ASMR3_PC_1 ((uint32_t)0x00000002) /!< Bit 1 /
Kojto	112:6f327212ef96	3918	#define RI_ASMR3_PC_2 ((uint32_t)0x00000004) /!< Bit 2 /
Kojto	112:6f327212ef96	3919	#define RI_ASMR3_PC_3 ((uint32_t)0x00000008) /!< Bit 3 /
Kojto	112:6f327212ef96	3920	#define RI_ASMR3_PC_4 ((uint32_t)0x00000010) /!< Bit 4 /
Kojto	112:6f327212ef96	3921	#define RI_ASMR3_PC_5 ((uint32_t)0x00000020) /!< Bit 5 /
Kojto	112:6f327212ef96	3922	#define RI_ASMR3_PC_6 ((uint32_t)0x00000040) /!< Bit 6 /
Kojto	112:6f327212ef96	3923	#define RI_ASMR3_PC_7 ((uint32_t)0x00000080) /!< Bit 7 /
Kojto	112:6f327212ef96	3924	#define RI_ASMR3_PC_8 ((uint32_t)0x00000100) /!< Bit 8 /
Kojto	112:6f327212ef96	3925	#define RI_ASMR3_PC_9 ((uint32_t)0x00000200) /!< Bit 9 /
Kojto	112:6f327212ef96	3926	#define RI_ASMR3_PC_10 ((uint32_t)0x00000400) /!< Bit 10 /
Kojto	112:6f327212ef96	3927	#define RI_ASMR3_PC_11 ((uint32_t)0x00000800) /!< Bit 11 /
Kojto	112:6f327212ef96	3928	#define RI_ASMR3_PC_12 ((uint32_t)0x00001000) /!< Bit 12 /
Kojto	112:6f327212ef96	3929	#define RI_ASMR3_PC_13 ((uint32_t)0x00002000) /!< Bit 13 /
Kojto	112:6f327212ef96	3930	#define RI_ASMR3_PC_14 ((uint32_t)0x00004000) /!< Bit 14 /
Kojto	112:6f327212ef96	3931	#define RI_ASMR3_PC_15 ((uint32_t)0x00008000) /!< Bit 15 /
Kojto	112:6f327212ef96	3932
Kojto	112:6f327212ef96	3933	/****************** Bit definition for RI_CMR3 register ******************/
Kojto	112:6f327212ef96	3934	#define RI_CMR3_PC ((uint32_t)0x0000FFFF) /!< PC[15:0] Port C selection /
Kojto	112:6f327212ef96	3935	#define RI_CMR3_PC_0 ((uint32_t)0x00000001) /!< Bit 0 /
Kojto	112:6f327212ef96	3936	#define RI_CMR3_PC_1 ((uint32_t)0x00000002) /!< Bit 1 /
Kojto	112:6f327212ef96	3937	#define RI_CMR3_PC_2 ((uint32_t)0x00000004) /!< Bit 2 /
Kojto	112:6f327212ef96	3938	#define RI_CMR3_PC_3 ((uint32_t)0x00000008) /!< Bit 3 /
Kojto	112:6f327212ef96	3939	#define RI_CMR3_PC_4 ((uint32_t)0x00000010) /!< Bit 4 /
Kojto	112:6f327212ef96	3940	#define RI_CMR3_PC_5 ((uint32_t)0x00000020) /!< Bit 5 /
Kojto	112:6f327212ef96	3941	#define RI_CMR3_PC_6 ((uint32_t)0x00000040) /!< Bit 6 /
Kojto	112:6f327212ef96	3942	#define RI_CMR3_PC_7 ((uint32_t)0x00000080) /!< Bit 7 /
Kojto	112:6f327212ef96	3943	#define RI_CMR3_PC_8 ((uint32_t)0x00000100) /!< Bit 8 /
Kojto	112:6f327212ef96	3944	#define RI_CMR3_PC_9 ((uint32_t)0x00000200) /!< Bit 9 /
Kojto	112:6f327212ef96	3945	#define RI_CMR3_PC_10 ((uint32_t)0x00000400) /!< Bit 10 /
Kojto	112:6f327212ef96	3946	#define RI_CMR3_PC_11 ((uint32_t)0x00000800) /!< Bit 11 /
Kojto	112:6f327212ef96	3947	#define RI_CMR3_PC_12 ((uint32_t)0x00001000) /!< Bit 12 /
Kojto	112:6f327212ef96	3948	#define RI_CMR3_PC_13 ((uint32_t)0x00002000) /!< Bit 13 /
Kojto	112:6f327212ef96	3949	#define RI_CMR3_PC_14 ((uint32_t)0x00004000) /!< Bit 14 /
Kojto	112:6f327212ef96	3950	#define RI_CMR3_PC_15 ((uint32_t)0x00008000) /!< Bit 15 /
Kojto	112:6f327212ef96	3951
Kojto	112:6f327212ef96	3952	/****************** Bit definition for RI_CICR3 register ******************/
Kojto	112:6f327212ef96	3953	#define RI_CICR3_PC ((uint32_t)0x0000FFFF) /!< PC[15:0] Port C selection /
Kojto	112:6f327212ef96	3954	#define RI_CICR3_PC_0 ((uint32_t)0x00000001) /!< Bit 0 /
Kojto	112:6f327212ef96	3955	#define RI_CICR3_PC_1 ((uint32_t)0x00000002) /!< Bit 1 /
Kojto	112:6f327212ef96	3956	#define RI_CICR3_PC_2 ((uint32_t)0x00000004) /!< Bit 2 /
Kojto	112:6f327212ef96	3957	#define RI_CICR3_PC_3 ((uint32_t)0x00000008) /!< Bit 3 /
Kojto	112:6f327212ef96	3958	#define RI_CICR3_PC_4 ((uint32_t)0x00000010) /!< Bit 4 /
Kojto	112:6f327212ef96	3959	#define RI_CICR3_PC_5 ((uint32_t)0x00000020) /!< Bit 5 /
Kojto	112:6f327212ef96	3960	#define RI_CICR3_PC_6 ((uint32_t)0x00000040) /!< Bit 6 /
Kojto	112:6f327212ef96	3961	#define RI_CICR3_PC_7 ((uint32_t)0x00000080) /!< Bit 7 /
Kojto	112:6f327212ef96	3962	#define RI_CICR3_PC_8 ((uint32_t)0x00000100) /!< Bit 8 /
Kojto	112:6f327212ef96	3963	#define RI_CICR3_PC_9 ((uint32_t)0x00000200) /!< Bit 9 /
Kojto	112:6f327212ef96	3964	#define RI_CICR3_PC_10 ((uint32_t)0x00000400) /!< Bit 10 /
Kojto	112:6f327212ef96	3965	#define RI_CICR3_PC_11 ((uint32_t)0x00000800) /!< Bit 11 /
Kojto	112:6f327212ef96	3966	#define RI_CICR3_PC_12 ((uint32_t)0x00001000) /!< Bit 12 /
Kojto	112:6f327212ef96	3967	#define RI_CICR3_PC_13 ((uint32_t)0x00002000) /!< Bit 13 /
Kojto	112:6f327212ef96	3968	#define RI_CICR3_PC_14 ((uint32_t)0x00004000) /!< Bit 14 /
Kojto	112:6f327212ef96	3969	#define RI_CICR3_PC_15 ((uint32_t)0x00008000) /!< Bit 15 /
Kojto	112:6f327212ef96	3970
Kojto	112:6f327212ef96	3971	/******************************************************************************/
Kojto	112:6f327212ef96	3972	/* */
Kojto	112:6f327212ef96	3973	/* Timers (TIM) */
Kojto	112:6f327212ef96	3974	/* */
Kojto	112:6f327212ef96	3975	/******************************************************************************/
Kojto	112:6f327212ef96	3976
Kojto	112:6f327212ef96	3977	/***************** Bit definition for TIM_CR1 register ******************/
Kojto	112:6f327212ef96	3978	#define TIM_CR1_CEN ((uint32_t)0x00000001) /!<Counter enable /
Kojto	112:6f327212ef96	3979	#define TIM_CR1_UDIS ((uint32_t)0x00000002) /!<Update disable /
Kojto	112:6f327212ef96	3980	#define TIM_CR1_URS ((uint32_t)0x00000004) /!<Update request source /
Kojto	112:6f327212ef96	3981	#define TIM_CR1_OPM ((uint32_t)0x00000008) /!<One pulse mode /
Kojto	112:6f327212ef96	3982	#define TIM_CR1_DIR ((uint32_t)0x00000010) /!<Direction /
Kojto	112:6f327212ef96	3983
Kojto	112:6f327212ef96	3984	#define TIM_CR1_CMS ((uint32_t)0x00000060) /!<CMS[1:0] bits (Center-aligned mode selection) /
Kojto	112:6f327212ef96	3985	#define TIM_CR1_CMS_0 ((uint32_t)0x00000020) /!<Bit 0 /
Kojto	112:6f327212ef96	3986	#define TIM_CR1_CMS_1 ((uint32_t)0x00000040) /!<Bit 1 /
Kojto	112:6f327212ef96	3987
Kojto	112:6f327212ef96	3988	#define TIM_CR1_ARPE ((uint32_t)0x00000080) /!<Auto-reload preload enable /
Kojto	112:6f327212ef96	3989
Kojto	112:6f327212ef96	3990	#define TIM_CR1_CKD ((uint32_t)0x00000300) /!<CKD[1:0] bits (clock division) /
Kojto	112:6f327212ef96	3991	#define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /!<Bit 0 /
Kojto	112:6f327212ef96	3992	#define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /!<Bit 1 /
Kojto	112:6f327212ef96	3993
Kojto	112:6f327212ef96	3994	/***************** Bit definition for TIM_CR2 register ******************/
Kojto	112:6f327212ef96	3995	#define TIM_CR2_CCDS ((uint32_t)0x00000008) /!<Capture/Compare DMA Selection /
Kojto	112:6f327212ef96	3996
Kojto	112:6f327212ef96	3997	#define TIM_CR2_MMS ((uint32_t)0x00000070) /!<MMS[2:0] bits (Master Mode Selection) /
Kojto	112:6f327212ef96	3998	#define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /!<Bit 0 /
Kojto	112:6f327212ef96	3999	#define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /!<Bit 1 /
Kojto	112:6f327212ef96	4000	#define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /!<Bit 2 /
Kojto	112:6f327212ef96	4001
Kojto	112:6f327212ef96	4002	#define TIM_CR2_TI1S ((uint32_t)0x00000080) /!<TI1 Selection /
Kojto	112:6f327212ef96	4003
Kojto	112:6f327212ef96	4004	/***************** Bit definition for TIM_SMCR register *****************/
Kojto	112:6f327212ef96	4005	#define TIM_SMCR_SMS ((uint32_t)0x00000007) /!<SMS[2:0] bits (Slave mode selection) /
Kojto	112:6f327212ef96	4006	#define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /!<Bit 0 /
Kojto	112:6f327212ef96	4007	#define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /!<Bit 1 /
Kojto	112:6f327212ef96	4008	#define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /!<Bit 2 /
Kojto	112:6f327212ef96	4009
Kojto	112:6f327212ef96	4010	#define TIM_SMCR_OCCS ((uint32_t)0x00000008) /!< OCREF clear selection /
Kojto	112:6f327212ef96	4011
Kojto	112:6f327212ef96	4012	#define TIM_SMCR_TS ((uint32_t)0x00000070) /!<TS[2:0] bits (Trigger selection) /
Kojto	112:6f327212ef96	4013	#define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /!<Bit 0 /
Kojto	112:6f327212ef96	4014	#define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /!<Bit 1 /
Kojto	112:6f327212ef96	4015	#define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /!<Bit 2 /
Kojto	112:6f327212ef96	4016
Kojto	112:6f327212ef96	4017	#define TIM_SMCR_MSM ((uint32_t)0x00000080) /!<Master/slave mode /
Kojto	112:6f327212ef96	4018
Kojto	112:6f327212ef96	4019	#define TIM_SMCR_ETF ((uint32_t)0x00000F00) /!<ETF[3:0] bits (External trigger filter) /
Kojto	112:6f327212ef96	4020	#define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /!<Bit 0 /
Kojto	112:6f327212ef96	4021	#define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /!<Bit 1 /
Kojto	112:6f327212ef96	4022	#define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /!<Bit 2 /
Kojto	112:6f327212ef96	4023	#define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /!<Bit 3 /
Kojto	112:6f327212ef96	4024
Kojto	112:6f327212ef96	4025	#define TIM_SMCR_ETPS ((uint32_t)0x00003000) /!<ETPS[1:0] bits (External trigger prescaler) /
Kojto	112:6f327212ef96	4026	#define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /!<Bit 0 /
Kojto	112:6f327212ef96	4027	#define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /!<Bit 1 /
Kojto	112:6f327212ef96	4028
Kojto	112:6f327212ef96	4029	#define TIM_SMCR_ECE ((uint32_t)0x00004000) /!<External clock enable /
Kojto	112:6f327212ef96	4030	#define TIM_SMCR_ETP ((uint32_t)0x00008000) /!<External trigger polarity /
Kojto	112:6f327212ef96	4031
Kojto	112:6f327212ef96	4032	/***************** Bit definition for TIM_DIER register *****************/
Kojto	112:6f327212ef96	4033	#define TIM_DIER_UIE ((uint32_t)0x00000001) /!<Update interrupt enable /
Kojto	112:6f327212ef96	4034	#define TIM_DIER_CC1IE ((uint32_t)0x00000002) /!<Capture/Compare 1 interrupt enable /
Kojto	112:6f327212ef96	4035	#define TIM_DIER_CC2IE ((uint32_t)0x00000004) /!<Capture/Compare 2 interrupt enable /
Kojto	112:6f327212ef96	4036	#define TIM_DIER_CC3IE ((uint32_t)0x00000008) /!<Capture/Compare 3 interrupt enable /
Kojto	112:6f327212ef96	4037	#define TIM_DIER_CC4IE ((uint32_t)0x00000010) /!<Capture/Compare 4 interrupt enable /
Kojto	112:6f327212ef96	4038	#define TIM_DIER_TIE ((uint32_t)0x00000040) /!<Trigger interrupt enable /
Kojto	112:6f327212ef96	4039	#define TIM_DIER_UDE ((uint32_t)0x00000100) /!<Update DMA request enable /
Kojto	112:6f327212ef96	4040	#define TIM_DIER_CC1DE ((uint32_t)0x00000200) /!<Capture/Compare 1 DMA request enable /
Kojto	112:6f327212ef96	4041	#define TIM_DIER_CC2DE ((uint32_t)0x00000400) /!<Capture/Compare 2 DMA request enable /
Kojto	112:6f327212ef96	4042	#define TIM_DIER_CC3DE ((uint32_t)0x00000800) /!<Capture/Compare 3 DMA request enable /
Kojto	112:6f327212ef96	4043	#define TIM_DIER_CC4DE ((uint32_t)0x00001000) /!<Capture/Compare 4 DMA request enable /
Kojto	112:6f327212ef96	4044	#define TIM_DIER_COMDE ((uint16_t)0x2000) /!<COM DMA request enable /
Kojto	112:6f327212ef96	4045	#define TIM_DIER_TDE ((uint32_t)0x00004000) /!<Trigger DMA request enable /
Kojto	112:6f327212ef96	4046
Kojto	112:6f327212ef96	4047	/****************** Bit definition for TIM_SR register ******************/
Kojto	112:6f327212ef96	4048	#define TIM_SR_UIF ((uint32_t)0x00000001) /!<Update interrupt Flag /
Kojto	112:6f327212ef96	4049	#define TIM_SR_CC1IF ((uint32_t)0x00000002) /!<Capture/Compare 1 interrupt Flag /
Kojto	112:6f327212ef96	4050	#define TIM_SR_CC2IF ((uint32_t)0x00000004) /!<Capture/Compare 2 interrupt Flag /
Kojto	112:6f327212ef96	4051	#define TIM_SR_CC3IF ((uint32_t)0x00000008) /!<Capture/Compare 3 interrupt Flag /
Kojto	112:6f327212ef96	4052	#define TIM_SR_CC4IF ((uint32_t)0x00000010) /!<Capture/Compare 4 interrupt Flag /
Kojto	112:6f327212ef96	4053	#define TIM_SR_TIF ((uint32_t)0x00000040) /!<Trigger interrupt Flag /
Kojto	112:6f327212ef96	4054	#define TIM_SR_CC1OF ((uint32_t)0x00000200) /!<Capture/Compare 1 Overcapture Flag /
Kojto	112:6f327212ef96	4055	#define TIM_SR_CC2OF ((uint32_t)0x00000400) /!<Capture/Compare 2 Overcapture Flag /
Kojto	112:6f327212ef96	4056	#define TIM_SR_CC3OF ((uint32_t)0x00000800) /!<Capture/Compare 3 Overcapture Flag /
Kojto	112:6f327212ef96	4057	#define TIM_SR_CC4OF ((uint32_t)0x00001000) /!<Capture/Compare 4 Overcapture Flag /
Kojto	112:6f327212ef96	4058
Kojto	112:6f327212ef96	4059	/***************** Bit definition for TIM_EGR register ******************/
Kojto	112:6f327212ef96	4060	#define TIM_EGR_UG ((uint32_t)0x00000001) /!<Update Generation /
Kojto	112:6f327212ef96	4061	#define TIM_EGR_CC1G ((uint32_t)0x00000002) /!<Capture/Compare 1 Generation /
Kojto	112:6f327212ef96	4062	#define TIM_EGR_CC2G ((uint32_t)0x00000004) /!<Capture/Compare 2 Generation /
Kojto	112:6f327212ef96	4063	#define TIM_EGR_CC3G ((uint32_t)0x00000008) /!<Capture/Compare 3 Generation /
Kojto	112:6f327212ef96	4064	#define TIM_EGR_CC4G ((uint32_t)0x00000010) /!<Capture/Compare 4 Generation /
Kojto	112:6f327212ef96	4065	#define TIM_EGR_TG ((uint32_t)0x00000040) /!<Trigger Generation /
Kojto	112:6f327212ef96	4066
Kojto	112:6f327212ef96	4067	/**************** Bit definition for TIM_CCMR1 register *****************/
Kojto	112:6f327212ef96	4068	#define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /!<CC1S[1:0] bits (Capture/Compare 1 Selection) /
Kojto	112:6f327212ef96	4069	#define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /!<Bit 0 /
Kojto	112:6f327212ef96	4070	#define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /!<Bit 1 /
Kojto	112:6f327212ef96	4071
Kojto	112:6f327212ef96	4072	#define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /!<Output Compare 1 Fast enable /
Kojto	112:6f327212ef96	4073	#define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /!<Output Compare 1 Preload enable /
Kojto	112:6f327212ef96	4074
Kojto	112:6f327212ef96	4075	#define TIM_CCMR1_OC1M ((uint32_t)0x00000070) /!<OC1M[2:0] bits (Output Compare 1 Mode) /
Kojto	112:6f327212ef96	4076	#define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /!<Bit 0 /
Kojto	112:6f327212ef96	4077	#define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /!<Bit 1 /
Kojto	112:6f327212ef96	4078	#define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /!<Bit 2 /
Kojto	112:6f327212ef96	4079
Kojto	112:6f327212ef96	4080	#define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /!<Output Compare 1Clear Enable /
Kojto	112:6f327212ef96	4081
Kojto	112:6f327212ef96	4082	#define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /!<CC2S[1:0] bits (Capture/Compare 2 Selection) /
Kojto	112:6f327212ef96	4083	#define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /!<Bit 0 /
Kojto	112:6f327212ef96	4084	#define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /!<Bit 1 /
Kojto	112:6f327212ef96	4085
Kojto	112:6f327212ef96	4086	#define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /!<Output Compare 2 Fast enable /
Kojto	112:6f327212ef96	4087	#define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /!<Output Compare 2 Preload enable /
Kojto	112:6f327212ef96	4088
Kojto	112:6f327212ef96	4089	#define TIM_CCMR1_OC2M ((uint32_t)0x00007000) /!<OC2M[2:0] bits (Output Compare 2 Mode) /
Kojto	112:6f327212ef96	4090	#define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /!<Bit 0 /
Kojto	112:6f327212ef96	4091	#define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /!<Bit 1 /
Kojto	112:6f327212ef96	4092	#define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /!<Bit 2 /
Kojto	112:6f327212ef96	4093
Kojto	112:6f327212ef96	4094	#define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /!<Output Compare 2 Clear Enable /
Kojto	112:6f327212ef96	4095
Kojto	112:6f327212ef96	4096	/----------------------------------------------------------------------------/
Kojto	112:6f327212ef96	4097
Kojto	112:6f327212ef96	4098	#define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) /
Kojto	112:6f327212ef96	4099	#define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /!<Bit 0 /
Kojto	112:6f327212ef96	4100	#define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /!<Bit 1 /
Kojto	112:6f327212ef96	4101
Kojto	112:6f327212ef96	4102	#define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /!<IC1F[3:0] bits (Input Capture 1 Filter) /
Kojto	112:6f327212ef96	4103	#define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /!<Bit 0 /
Kojto	112:6f327212ef96	4104	#define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /!<Bit 1 /
Kojto	112:6f327212ef96	4105	#define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /!<Bit 2 /
Kojto	112:6f327212ef96	4106	#define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /!<Bit 3 /
Kojto	112:6f327212ef96	4107
Kojto	112:6f327212ef96	4108	#define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) /
Kojto	112:6f327212ef96	4109	#define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /!<Bit 0 /
Kojto	112:6f327212ef96	4110	#define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /!<Bit 1 /
Kojto	112:6f327212ef96	4111
Kojto	112:6f327212ef96	4112	#define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /!<IC2F[3:0] bits (Input Capture 2 Filter) /
Kojto	112:6f327212ef96	4113	#define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /!<Bit 0 /
Kojto	112:6f327212ef96	4114	#define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /!<Bit 1 /
Kojto	112:6f327212ef96	4115	#define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /!<Bit 2 /
Kojto	112:6f327212ef96	4116	#define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /!<Bit 3 /
Kojto	112:6f327212ef96	4117
Kojto	112:6f327212ef96	4118	/**************** Bit definition for TIM_CCMR2 register *****************/
Kojto	112:6f327212ef96	4119	#define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /!<CC3S[1:0] bits (Capture/Compare 3 Selection) /
Kojto	112:6f327212ef96	4120	#define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /!<Bit 0 /
Kojto	112:6f327212ef96	4121	#define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /!<Bit 1 /
Kojto	112:6f327212ef96	4122
Kojto	112:6f327212ef96	4123	#define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /!<Output Compare 3 Fast enable /
Kojto	112:6f327212ef96	4124	#define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /!<Output Compare 3 Preload enable /
Kojto	112:6f327212ef96	4125
Kojto	112:6f327212ef96	4126	#define TIM_CCMR2_OC3M ((uint32_t)0x00000070) /!<OC3M[2:0] bits (Output Compare 3 Mode) /
Kojto	112:6f327212ef96	4127	#define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /!<Bit 0 /
Kojto	112:6f327212ef96	4128	#define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /!<Bit 1 /
Kojto	112:6f327212ef96	4129	#define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /!<Bit 2 /
Kojto	112:6f327212ef96	4130
Kojto	112:6f327212ef96	4131	#define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /!<Output Compare 3 Clear Enable /
Kojto	112:6f327212ef96	4132
Kojto	112:6f327212ef96	4133	#define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /!<CC4S[1:0] bits (Capture/Compare 4 Selection) /
Kojto	112:6f327212ef96	4134	#define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /!<Bit 0 /
Kojto	112:6f327212ef96	4135	#define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /!<Bit 1 /
Kojto	112:6f327212ef96	4136
Kojto	112:6f327212ef96	4137	#define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /!<Output Compare 4 Fast enable /
Kojto	112:6f327212ef96	4138	#define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /!<Output Compare 4 Preload enable /
Kojto	112:6f327212ef96	4139
Kojto	112:6f327212ef96	4140	#define TIM_CCMR2_OC4M ((uint32_t)0x00007000) /!<OC4M[2:0] bits (Output Compare 4 Mode) /
Kojto	112:6f327212ef96	4141	#define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /!<Bit 0 /
Kojto	112:6f327212ef96	4142	#define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /!<Bit 1 /
Kojto	112:6f327212ef96	4143	#define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /!<Bit 2 /
Kojto	112:6f327212ef96	4144
Kojto	112:6f327212ef96	4145	#define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /!<Output Compare 4 Clear Enable /
Kojto	112:6f327212ef96	4146
Kojto	112:6f327212ef96	4147	/----------------------------------------------------------------------------/
Kojto	112:6f327212ef96	4148
Kojto	112:6f327212ef96	4149	#define TIM_CCMR2_IC3PSC ((uint32_t)0x0000000C) /!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) /
Kojto	112:6f327212ef96	4150	#define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004) /!<Bit 0 /
Kojto	112:6f327212ef96	4151	#define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008) /!<Bit 1 /
Kojto	112:6f327212ef96	4152
Kojto	112:6f327212ef96	4153	#define TIM_CCMR2_IC3F ((uint32_t)0x000000F0) /!<IC3F[3:0] bits (Input Capture 3 Filter) /
Kojto	112:6f327212ef96	4154	#define TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010) /!<Bit 0 /
Kojto	112:6f327212ef96	4155	#define TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020) /!<Bit 1 /
Kojto	112:6f327212ef96	4156	#define TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040) /!<Bit 2 /
Kojto	112:6f327212ef96	4157	#define TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080) /!<Bit 3 /
Kojto	112:6f327212ef96	4158
Kojto	112:6f327212ef96	4159	#define TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00) /!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) /
Kojto	112:6f327212ef96	4160	#define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400) /!<Bit 0 /
Kojto	112:6f327212ef96	4161	#define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800) /!<Bit 1 /
Kojto	112:6f327212ef96	4162
Kojto	112:6f327212ef96	4163	#define TIM_CCMR2_IC4F ((uint32_t)0x0000F000) /!<IC4F[3:0] bits (Input Capture 4 Filter) /
Kojto	112:6f327212ef96	4164	#define TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000) /!<Bit 0 /
Kojto	112:6f327212ef96	4165	#define TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000) /!<Bit 1 /
Kojto	112:6f327212ef96	4166	#define TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000) /!<Bit 2 /
Kojto	112:6f327212ef96	4167	#define TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000) /!<Bit 3 /
Kojto	112:6f327212ef96	4168
Kojto	112:6f327212ef96	4169	/***************** Bit definition for TIM_CCER register *****************/
Kojto	112:6f327212ef96	4170	#define TIM_CCER_CC1E ((uint32_t)0x00000001) /!<Capture/Compare 1 output enable /
Kojto	112:6f327212ef96	4171	#define TIM_CCER_CC1P ((uint32_t)0x00000002) /!<Capture/Compare 1 output Polarity /
Kojto	112:6f327212ef96	4172	#define TIM_CCER_CC1NP ((uint32_t)0x00000008) /!<Capture/Compare 1 Complementary output Polarity /
Kojto	112:6f327212ef96	4173	#define TIM_CCER_CC2E ((uint32_t)0x00000010) /!<Capture/Compare 2 output enable /
Kojto	112:6f327212ef96	4174	#define TIM_CCER_CC2P ((uint32_t)0x00000020) /!<Capture/Compare 2 output Polarity /
Kojto	112:6f327212ef96	4175	#define TIM_CCER_CC2NP ((uint32_t)0x00000080) /!<Capture/Compare 2 Complementary output Polarity /
Kojto	112:6f327212ef96	4176	#define TIM_CCER_CC3E ((uint32_t)0x00000100) /!<Capture/Compare 3 output enable /
Kojto	112:6f327212ef96	4177	#define TIM_CCER_CC3P ((uint32_t)0x00000200) /!<Capture/Compare 3 output Polarity /
Kojto	112:6f327212ef96	4178	#define TIM_CCER_CC3NP ((uint32_t)0x00000800) /!<Capture/Compare 3 Complementary output Polarity /
Kojto	112:6f327212ef96	4179	#define TIM_CCER_CC4E ((uint32_t)0x00001000) /!<Capture/Compare 4 output enable /
Kojto	112:6f327212ef96	4180	#define TIM_CCER_CC4P ((uint32_t)0x00002000) /!<Capture/Compare 4 output Polarity /
Kojto	112:6f327212ef96	4181	#define TIM_CCER_CC4NP ((uint32_t)0x00008000) /!<Capture/Compare 4 Complementary output Polarity /
Kojto	112:6f327212ef96	4182
Kojto	112:6f327212ef96	4183	/***************** Bit definition for TIM_CNT register ******************/
Kojto	112:6f327212ef96	4184	#define TIM_CNT_CNT ((uint32_t)0x0000FFFF) /!<Counter Value /
Kojto	112:6f327212ef96	4185
Kojto	112:6f327212ef96	4186	/***************** Bit definition for TIM_PSC register ******************/
Kojto	112:6f327212ef96	4187	#define TIM_PSC_PSC ((uint32_t)0x0000FFFF) /!<Prescaler Value /
Kojto	112:6f327212ef96	4188
Kojto	112:6f327212ef96	4189	/***************** Bit definition for TIM_ARR register ******************/
Kojto	112:6f327212ef96	4190	#define TIM_ARR_ARR ((uint32_t)0x0000FFFF) /!<actual auto-reload Value /
Kojto	112:6f327212ef96	4191
Kojto	112:6f327212ef96	4192	/***************** Bit definition for TIM_CCR1 register *****************/
Kojto	112:6f327212ef96	4193	#define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /!<Capture/Compare 1 Value /
Kojto	112:6f327212ef96	4194
Kojto	112:6f327212ef96	4195	/***************** Bit definition for TIM_CCR2 register *****************/
Kojto	112:6f327212ef96	4196	#define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) /!<Capture/Compare 2 Value /
Kojto	112:6f327212ef96	4197
Kojto	112:6f327212ef96	4198	/***************** Bit definition for TIM_CCR3 register *****************/
Kojto	112:6f327212ef96	4199	#define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) /!<Capture/Compare 3 Value /
Kojto	112:6f327212ef96	4200
Kojto	112:6f327212ef96	4201	/***************** Bit definition for TIM_CCR4 register *****************/
Kojto	112:6f327212ef96	4202	#define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) /!<Capture/Compare 4 Value /
Kojto	112:6f327212ef96	4203
Kojto	112:6f327212ef96	4204	/***************** Bit definition for TIM_DCR register ******************/
Kojto	112:6f327212ef96	4205	#define TIM_DCR_DBA ((uint32_t)0x0000001F) /!<DBA[4:0] bits (DMA Base Address) /
Kojto	112:6f327212ef96	4206	#define TIM_DCR_DBA_0 ((uint32_t)0x00000001) /!<Bit 0 /
Kojto	112:6f327212ef96	4207	#define TIM_DCR_DBA_1 ((uint32_t)0x00000002) /!<Bit 1 /
Kojto	112:6f327212ef96	4208	#define TIM_DCR_DBA_2 ((uint32_t)0x00000004) /!<Bit 2 /
Kojto	112:6f327212ef96	4209	#define TIM_DCR_DBA_3 ((uint32_t)0x00000008) /!<Bit 3 /
Kojto	112:6f327212ef96	4210	#define TIM_DCR_DBA_4 ((uint32_t)0x00000010) /!<Bit 4 /
Kojto	112:6f327212ef96	4211
Kojto	112:6f327212ef96	4212	#define TIM_DCR_DBL ((uint32_t)0x00001F00) /!<DBL[4:0] bits (DMA Burst Length) /
Kojto	112:6f327212ef96	4213	#define TIM_DCR_DBL_0 ((uint32_t)0x00000100) /!<Bit 0 /
Kojto	112:6f327212ef96	4214	#define TIM_DCR_DBL_1 ((uint32_t)0x00000200) /!<Bit 1 /
Kojto	112:6f327212ef96	4215	#define TIM_DCR_DBL_2 ((uint32_t)0x00000400) /!<Bit 2 /
Kojto	112:6f327212ef96	4216	#define TIM_DCR_DBL_3 ((uint32_t)0x00000800) /!<Bit 3 /
Kojto	112:6f327212ef96	4217	#define TIM_DCR_DBL_4 ((uint32_t)0x00001000) /!<Bit 4 /
Kojto	112:6f327212ef96	4218
Kojto	112:6f327212ef96	4219	/***************** Bit definition for TIM_DMAR register *****************/
Kojto	112:6f327212ef96	4220	#define TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) /!<DMA register for burst accesses /
Kojto	112:6f327212ef96	4221
Kojto	112:6f327212ef96	4222	/***************** Bit definition for TIM_OR register *******************/
Kojto	112:6f327212ef96	4223	#define TIM_OR_TI1RMP ((uint32_t)0x00000003) /!<TI1_RMP[1:0] bits (TIM Input 1 remap) /
Kojto	112:6f327212ef96	4224	#define TIM_OR_TI1RMP_0 ((uint32_t)0x00000001) /!<Bit 0 /
Kojto	112:6f327212ef96	4225	#define TIM_OR_TI1RMP_1 ((uint32_t)0x00000002) /!<Bit 1 /
Kojto	112:6f327212ef96	4226
Kojto	112:6f327212ef96	4227	#define TIM_OR_ETR_RMP ((uint32_t)0x00000004) /!<ETR_RMP bit (TIM10/11 ETR remap)/
Kojto	112:6f327212ef96	4228	#define TIM_OR_TI1_RMP_RI ((uint32_t)0x00000008) /!<TI1_RMP_RI bit (TIM10/11 Input 1 remap for Routing interface) /
Kojto	112:6f327212ef96	4229
Kojto	112:6f327212ef96	4230	/----------------------------------------------------------------------------/
Kojto	112:6f327212ef96	4231	#define TIM9_OR_ITR1_RMP ((uint32_t)0x00000004) /!<ITR1_RMP bit (TIM9 Internal trigger 1 remap) /
Kojto	112:6f327212ef96	4232
Kojto	112:6f327212ef96	4233	/----------------------------------------------------------------------------/
Kojto	112:6f327212ef96	4234	#define TIM2_OR_ITR1_RMP ((uint32_t)0x00000001) /!<ITR1_RMP bit (TIM2 Internal trigger 1 remap) /
Kojto	112:6f327212ef96	4235
Kojto	112:6f327212ef96	4236	/----------------------------------------------------------------------------/
Kojto	112:6f327212ef96	4237	#define TIM3_OR_ITR2_RMP ((uint32_t)0x00000001) /!<ITR2_RMP bit (TIM3 Internal trigger 2 remap) /
Kojto	112:6f327212ef96	4238
Kojto	112:6f327212ef96	4239	/----------------------------------------------------------------------------/
Kojto	112:6f327212ef96	4240
Kojto	112:6f327212ef96	4241
Kojto	112:6f327212ef96	4242	/******************************************************************************/
Kojto	112:6f327212ef96	4243	/* */
Kojto	112:6f327212ef96	4244	/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
Kojto	112:6f327212ef96	4245	/* */
Kojto	112:6f327212ef96	4246	/******************************************************************************/
Kojto	112:6f327212ef96	4247
Kojto	112:6f327212ef96	4248	/***************** Bit definition for USART_SR register *****************/
Kojto	112:6f327212ef96	4249	#define USART_SR_PE ((uint32_t)0x00000001) /!< Parity Error /
Kojto	112:6f327212ef96	4250	#define USART_SR_FE ((uint32_t)0x00000002) /!< Framing Error /
Kojto	112:6f327212ef96	4251	#define USART_SR_NE ((uint32_t)0x00000004) /!< Noise Error Flag /
Kojto	112:6f327212ef96	4252	#define USART_SR_ORE ((uint32_t)0x00000008) /!< OverRun Error /
Kojto	112:6f327212ef96	4253	#define USART_SR_IDLE ((uint32_t)0x00000010) /!< IDLE line detected /
Kojto	112:6f327212ef96	4254	#define USART_SR_RXNE ((uint32_t)0x00000020) /!< Read Data Register Not Empty /
Kojto	112:6f327212ef96	4255	#define USART_SR_TC ((uint32_t)0x00000040) /!< Transmission Complete /
Kojto	112:6f327212ef96	4256	#define USART_SR_TXE ((uint32_t)0x00000080) /!< Transmit Data Register Empty /
Kojto	112:6f327212ef96	4257	#define USART_SR_LBD ((uint32_t)0x00000100) /!< LIN Break Detection Flag /
Kojto	112:6f327212ef96	4258	#define USART_SR_CTS ((uint32_t)0x00000200) /!< CTS Flag /
Kojto	112:6f327212ef96	4259
Kojto	112:6f327212ef96	4260	/***************** Bit definition for USART_DR register *****************/
Kojto	112:6f327212ef96	4261	#define USART_DR_DR ((uint32_t)0x000001FF) /!< Data value /
Kojto	112:6f327212ef96	4262
Kojto	112:6f327212ef96	4263	/**************** Bit definition for USART_BRR register *****************/
Kojto	112:6f327212ef96	4264	#define USART_BRR_DIV_FRACTION ((uint32_t)0x0000000F) /!< Fraction of USARTDIV /
Kojto	112:6f327212ef96	4265	#define USART_BRR_DIV_MANTISSA ((uint32_t)0x0000FFF0) /!< Mantissa of USARTDIV /
Kojto	112:6f327212ef96	4266
Kojto	112:6f327212ef96	4267	/**************** Bit definition for USART_CR1 register *****************/
Kojto	112:6f327212ef96	4268	#define USART_CR1_SBK ((uint32_t)0x00000001) /!< Send Break /
Kojto	112:6f327212ef96	4269	#define USART_CR1_RWU ((uint32_t)0x00000002) /!< Receiver wakeup /
Kojto	112:6f327212ef96	4270	#define USART_CR1_RE ((uint32_t)0x00000004) /!< Receiver Enable /
Kojto	112:6f327212ef96	4271	#define USART_CR1_TE ((uint32_t)0x00000008) /!< Transmitter Enable /
Kojto	112:6f327212ef96	4272	#define USART_CR1_IDLEIE ((uint32_t)0x00000010) /!< IDLE Interrupt Enable /
Kojto	112:6f327212ef96	4273	#define USART_CR1_RXNEIE ((uint32_t)0x00000020) /!< RXNE Interrupt Enable /
Kojto	112:6f327212ef96	4274	#define USART_CR1_TCIE ((uint32_t)0x00000040) /!< Transmission Complete Interrupt Enable /
Kojto	112:6f327212ef96	4275	#define USART_CR1_TXEIE ((uint32_t)0x00000080) /!< PE Interrupt Enable /
Kojto	112:6f327212ef96	4276	#define USART_CR1_PEIE ((uint32_t)0x00000100) /!< PE Interrupt Enable /
Kojto	112:6f327212ef96	4277	#define USART_CR1_PS ((uint32_t)0x00000200) /!< Parity Selection /
Kojto	112:6f327212ef96	4278	#define USART_CR1_PCE ((uint32_t)0x00000400) /!< Parity Control Enable /
Kojto	112:6f327212ef96	4279	#define USART_CR1_WAKE ((uint32_t)0x00000800) /!< Wakeup method /
Kojto	112:6f327212ef96	4280	#define USART_CR1_M ((uint32_t)0x00001000) /!< Word length /
Kojto	112:6f327212ef96	4281	#define USART_CR1_UE ((uint32_t)0x00002000) /!< USART Enable /
Kojto	112:6f327212ef96	4282	#define USART_CR1_OVER8 ((uint32_t)0x00008000) /!< Oversampling by 8-bit mode /
Kojto	112:6f327212ef96	4283
Kojto	112:6f327212ef96	4284	/**************** Bit definition for USART_CR2 register *****************/
Kojto	112:6f327212ef96	4285	#define USART_CR2_ADD ((uint32_t)0x0000000F) /!< Address of the USART node /
Kojto	112:6f327212ef96	4286	#define USART_CR2_LBDL ((uint32_t)0x00000020) /!< LIN Break Detection Length /
Kojto	112:6f327212ef96	4287	#define USART_CR2_LBDIE ((uint32_t)0x00000040) /!< LIN Break Detection Interrupt Enable /
Kojto	112:6f327212ef96	4288	#define USART_CR2_LBCL ((uint32_t)0x00000100) /!< Last Bit Clock pulse /
Kojto	112:6f327212ef96	4289	#define USART_CR2_CPHA ((uint32_t)0x00000200) /!< Clock Phase /
Kojto	112:6f327212ef96	4290	#define USART_CR2_CPOL ((uint32_t)0x00000400) /!< Clock Polarity /
Kojto	112:6f327212ef96	4291	#define USART_CR2_CLKEN ((uint32_t)0x00000800) /!< Clock Enable /
Kojto	112:6f327212ef96	4292
Kojto	112:6f327212ef96	4293	#define USART_CR2_STOP ((uint32_t)0x00003000) /!< STOP[1:0] bits (STOP bits) /
Kojto	112:6f327212ef96	4294	#define USART_CR2_STOP_0 ((uint32_t)0x00001000) /!< Bit 0 /
Kojto	112:6f327212ef96	4295	#define USART_CR2_STOP_1 ((uint32_t)0x00002000) /!< Bit 1 /
Kojto	112:6f327212ef96	4296
Kojto	112:6f327212ef96	4297	#define USART_CR2_LINEN ((uint32_t)0x00004000) /!< LIN mode enable /
Kojto	112:6f327212ef96	4298
Kojto	112:6f327212ef96	4299	/**************** Bit definition for USART_CR3 register *****************/
Kojto	112:6f327212ef96	4300	#define USART_CR3_EIE ((uint32_t)0x00000001) /!< Error Interrupt Enable /
Kojto	112:6f327212ef96	4301	#define USART_CR3_IREN ((uint32_t)0x00000002) /!< IrDA mode Enable /
Kojto	112:6f327212ef96	4302	#define USART_CR3_IRLP ((uint32_t)0x00000004) /!< IrDA Low-Power /
Kojto	112:6f327212ef96	4303	#define USART_CR3_HDSEL ((uint32_t)0x00000008) /!< Half-Duplex Selection /
Kojto	112:6f327212ef96	4304	#define USART_CR3_NACK ((uint32_t)0x00000010) /!< Smartcard NACK enable /
Kojto	112:6f327212ef96	4305	#define USART_CR3_SCEN ((uint32_t)0x00000020) /!< Smartcard mode enable /
Kojto	112:6f327212ef96	4306	#define USART_CR3_DMAR ((uint32_t)0x00000040) /!< DMA Enable Receiver /
Kojto	112:6f327212ef96	4307	#define USART_CR3_DMAT ((uint32_t)0x00000080) /!< DMA Enable Transmitter /
Kojto	112:6f327212ef96	4308	#define USART_CR3_RTSE ((uint32_t)0x00000100) /!< RTS Enable /
Kojto	112:6f327212ef96	4309	#define USART_CR3_CTSE ((uint32_t)0x00000200) /!< CTS Enable /
Kojto	112:6f327212ef96	4310	#define USART_CR3_CTSIE ((uint32_t)0x00000400) /!< CTS Interrupt Enable /
Kojto	112:6f327212ef96	4311	#define USART_CR3_ONEBIT ((uint32_t)0x00000800) /!< One sample bit method enable /
Kojto	112:6f327212ef96	4312
Kojto	112:6f327212ef96	4313	/**************** Bit definition for USART_GTPR register ****************/
Kojto	112:6f327212ef96	4314	#define USART_GTPR_PSC ((uint32_t)0x000000FF) /!< PSC[7:0] bits (Prescaler value) /
Kojto	112:6f327212ef96	4315	#define USART_GTPR_PSC_0 ((uint32_t)0x00000001) /!< Bit 0 /
Kojto	112:6f327212ef96	4316	#define USART_GTPR_PSC_1 ((uint32_t)0x00000002) /!< Bit 1 /
Kojto	112:6f327212ef96	4317	#define USART_GTPR_PSC_2 ((uint32_t)0x00000004) /!< Bit 2 /
Kojto	112:6f327212ef96	4318	#define USART_GTPR_PSC_3 ((uint32_t)0x00000008) /!< Bit 3 /
Kojto	112:6f327212ef96	4319	#define USART_GTPR_PSC_4 ((uint32_t)0x00000010) /!< Bit 4 /
Kojto	112:6f327212ef96	4320	#define USART_GTPR_PSC_5 ((uint32_t)0x00000020) /!< Bit 5 /
Kojto	112:6f327212ef96	4321	#define USART_GTPR_PSC_6 ((uint32_t)0x00000040) /!< Bit 6 /
Kojto	112:6f327212ef96	4322	#define USART_GTPR_PSC_7 ((uint32_t)0x00000080) /!< Bit 7 /
Kojto	112:6f327212ef96	4323
Kojto	112:6f327212ef96	4324	#define USART_GTPR_GT ((uint32_t)0x0000FF00) /!< Guard time value /
Kojto	112:6f327212ef96	4325
Kojto	112:6f327212ef96	4326	/******************************************************************************/
Kojto	112:6f327212ef96	4327	/* */
Kojto	112:6f327212ef96	4328	/* Universal Serial Bus (USB) */
Kojto	112:6f327212ef96	4329	/* */
Kojto	112:6f327212ef96	4330	/******************************************************************************/
Kojto	112:6f327212ef96	4331
Kojto	112:6f327212ef96	4332	/!<Endpoint-specific registers /
Kojto	112:6f327212ef96	4333
Kojto	112:6f327212ef96	4334	#define USB_EP0R USB_BASE /!< endpoint 0 register address /
Kojto	112:6f327212ef96	4335	#define USB_EP1R (USB_BASE + 0x00000004) /!< endpoint 1 register address /
Kojto	112:6f327212ef96	4336	#define USB_EP2R (USB_BASE + 0x00000008) /!< endpoint 2 register address /
Kojto	112:6f327212ef96	4337	#define USB_EP3R (USB_BASE + 0x0000000C) /!< endpoint 3 register address /
Kojto	112:6f327212ef96	4338	#define USB_EP4R (USB_BASE + 0x00000010) /!< endpoint 4 register address /
Kojto	112:6f327212ef96	4339	#define USB_EP5R (USB_BASE + 0x00000014) /!< endpoint 5 register address /
Kojto	112:6f327212ef96	4340	#define USB_EP6R (USB_BASE + 0x00000018) /!< endpoint 6 register address /
Kojto	112:6f327212ef96	4341	#define USB_EP7R (USB_BASE + 0x0000001C) /!< endpoint 7 register address /
Kojto	112:6f327212ef96	4342
Kojto	112:6f327212ef96	4343	/* bit positions */
Kojto	112:6f327212ef96	4344	#define USB_EP_CTR_RX ((uint32_t)0x00008000) /!< EndPoint Correct TRansfer RX /
Kojto	112:6f327212ef96	4345	#define USB_EP_DTOG_RX ((uint32_t)0x00004000) /!< EndPoint Data TOGGLE RX /
Kojto	112:6f327212ef96	4346	#define USB_EPRX_STAT ((uint32_t)0x00003000) /!< EndPoint RX STATus bit field /
Kojto	112:6f327212ef96	4347	#define USB_EP_SETUP ((uint32_t)0x00000800) /!< EndPoint SETUP /
Kojto	112:6f327212ef96	4348	#define USB_EP_T_FIELD ((uint32_t)0x00000600) /!< EndPoint TYPE /
Kojto	112:6f327212ef96	4349	#define USB_EP_KIND ((uint32_t)0x00000100) /!< EndPoint KIND /
Kojto	112:6f327212ef96	4350	#define USB_EP_CTR_TX ((uint32_t)0x00000080) /!< EndPoint Correct TRansfer TX /
Kojto	112:6f327212ef96	4351	#define USB_EP_DTOG_TX ((uint32_t)0x00000040) /!< EndPoint Data TOGGLE TX /
Kojto	112:6f327212ef96	4352	#define USB_EPTX_STAT ((uint32_t)0x00000030) /!< EndPoint TX STATus bit field /
Kojto	112:6f327212ef96	4353	#define USB_EPADDR_FIELD ((uint32_t)0x0000000F) /!< EndPoint ADDRess FIELD /
Kojto	112:6f327212ef96	4354
Kojto	112:6f327212ef96	4355	/* EndPoint REGister MASK (no toggle fields) */
Kojto	112:6f327212ef96	4356	#define USB_EPREG_MASK (USB_EP_CTR_RX\|USB_EP_SETUP\|USB_EP_T_FIELD\|USB_EP_KIND\|USB_EP_CTR_TX\|USB_EPADDR_FIELD)
Kojto	112:6f327212ef96	4357	/!< EP_TYPE[1:0] EndPoint TYPE /
Kojto	112:6f327212ef96	4358	#define USB_EP_TYPE_MASK ((uint32_t)0x00000600) /!< EndPoint TYPE Mask /
Kojto	112:6f327212ef96	4359	#define USB_EP_BULK ((uint32_t)0x00000000) /!< EndPoint BULK /
Kojto	112:6f327212ef96	4360	#define USB_EP_CONTROL ((uint32_t)0x00000200) /!< EndPoint CONTROL /
Kojto	112:6f327212ef96	4361	#define USB_EP_ISOCHRONOUS ((uint32_t)0x00000400) /!< EndPoint ISOCHRONOUS /
Kojto	112:6f327212ef96	4362	#define USB_EP_INTERRUPT ((uint32_t)0x00000600) /!< EndPoint INTERRUPT /
Kojto	112:6f327212ef96	4363	#define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
Kojto	112:6f327212ef96	4364
Kojto	112:6f327212ef96	4365	#define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /!< EP_KIND EndPoint KIND /
Kojto	112:6f327212ef96	4366	/!< STAT_TX[1:0] STATus for TX transfer /
Kojto	112:6f327212ef96	4367	#define USB_EP_TX_DIS ((uint32_t)0x00000000) /!< EndPoint TX DISabled /
Kojto	112:6f327212ef96	4368	#define USB_EP_TX_STALL ((uint32_t)0x00000010) /!< EndPoint TX STALLed /
Kojto	112:6f327212ef96	4369	#define USB_EP_TX_NAK ((uint32_t)0x00000020) /!< EndPoint TX NAKed /
Kojto	112:6f327212ef96	4370	#define USB_EP_TX_VALID ((uint32_t)0x00000030) /!< EndPoint TX VALID /
Kojto	112:6f327212ef96	4371	#define USB_EPTX_DTOG1 ((uint32_t)0x00000010) /!< EndPoint TX Data TOGgle bit1 /
Kojto	112:6f327212ef96	4372	#define USB_EPTX_DTOG2 ((uint32_t)0x00000020) /!< EndPoint TX Data TOGgle bit2 /
Kojto	112:6f327212ef96	4373	#define USB_EPTX_DTOGMASK (USB_EPTX_STAT\|USB_EPREG_MASK)
Kojto	112:6f327212ef96	4374	/!< STAT_RX[1:0] STATus for RX transfer /
Kojto	112:6f327212ef96	4375	#define USB_EP_RX_DIS ((uint32_t)0x00000000) /!< EndPoint RX DISabled /
Kojto	112:6f327212ef96	4376	#define USB_EP_RX_STALL ((uint32_t)0x00001000) /!< EndPoint RX STALLed /
Kojto	112:6f327212ef96	4377	#define USB_EP_RX_NAK ((uint32_t)0x00002000) /!< EndPoint RX NAKed /
Kojto	112:6f327212ef96	4378	#define USB_EP_RX_VALID ((uint32_t)0x00003000) /!< EndPoint RX VALID /
Kojto	112:6f327212ef96	4379	#define USB_EPRX_DTOG1 ((uint32_t)0x00001000) /!< EndPoint RX Data TOGgle bit1 /
Kojto	112:6f327212ef96	4380	#define USB_EPRX_DTOG2 ((uint32_t)0x00002000) /!< EndPoint RX Data TOGgle bit1 /
Kojto	112:6f327212ef96	4381	#define USB_EPRX_DTOGMASK (USB_EPRX_STAT\|USB_EPREG_MASK)
Kojto	112:6f327212ef96	4382
Kojto	112:6f327212ef96	4383	/***************** Bit definition for USB_EP0R register *****************/
Kojto	112:6f327212ef96	4384	#define USB_EP0R_EA ((uint32_t)0x0000000F) /!<Endpoint Address /
Kojto	112:6f327212ef96	4385
Kojto	112:6f327212ef96	4386	#define USB_EP0R_STAT_TX ((uint32_t)0x00000030) /!<STAT_TX[1:0] bits (Status bits, for transmission transfers) /
Kojto	112:6f327212ef96	4387	#define USB_EP0R_STAT_TX_0 ((uint32_t)0x00000010) /!<Bit 0 /
Kojto	112:6f327212ef96	4388	#define USB_EP0R_STAT_TX_1 ((uint32_t)0x00000020) /!<Bit 1 /
Kojto	112:6f327212ef96	4389
Kojto	112:6f327212ef96	4390	#define USB_EP0R_DTOG_TX ((uint32_t)0x00000040) /!<Data Toggle, for transmission transfers /
Kojto	112:6f327212ef96	4391	#define USB_EP0R_CTR_TX ((uint32_t)0x00000080) /!<Correct Transfer for transmission /
Kojto	112:6f327212ef96	4392	#define USB_EP0R_EP_KIND ((uint32_t)0x00000100) /!<Endpoint Kind /
Kojto	112:6f327212ef96	4393
Kojto	112:6f327212ef96	4394	#define USB_EP0R_EP_TYPE ((uint32_t)0x00000600) /!<EP_TYPE[1:0] bits (Endpoint type) /
Kojto	112:6f327212ef96	4395	#define USB_EP0R_EP_TYPE_0 ((uint32_t)0x00000200) /!<Bit 0 /
Kojto	112:6f327212ef96	4396	#define USB_EP0R_EP_TYPE_1 ((uint32_t)0x00000400) /!<Bit 1 /
Kojto	112:6f327212ef96	4397
Kojto	112:6f327212ef96	4398	#define USB_EP0R_SETUP ((uint32_t)0x00000800) /!<Setup transaction completed /
Kojto	112:6f327212ef96	4399
Kojto	112:6f327212ef96	4400	#define USB_EP0R_STAT_RX ((uint32_t)0x00003000) /!<STAT_RX[1:0] bits (Status bits, for reception transfers) /
Kojto	112:6f327212ef96	4401	#define USB_EP0R_STAT_RX_0 ((uint32_t)0x00001000) /!<Bit 0 /
Kojto	112:6f327212ef96	4402	#define USB_EP0R_STAT_RX_1 ((uint32_t)0x00002000) /!<Bit 1 /
Kojto	112:6f327212ef96	4403
Kojto	112:6f327212ef96	4404	#define USB_EP0R_DTOG_RX ((uint32_t)0x00004000) /!<Data Toggle, for reception transfers /
Kojto	112:6f327212ef96	4405	#define USB_EP0R_CTR_RX ((uint32_t)0x00008000) /!<Correct Transfer for reception /
Kojto	112:6f327212ef96	4406
Kojto	112:6f327212ef96	4407	/***************** Bit definition for USB_EP1R register *****************/
Kojto	112:6f327212ef96	4408	#define USB_EP1R_EA ((uint32_t)0x0000000F) /!<Endpoint Address /
Kojto	112:6f327212ef96	4409
Kojto	112:6f327212ef96	4410	#define USB_EP1R_STAT_TX ((uint32_t)0x00000030) /!<STAT_TX[1:0] bits (Status bits, for transmission transfers) /
Kojto	112:6f327212ef96	4411	#define USB_EP1R_STAT_TX_0 ((uint32_t)0x00000010) /!<Bit 0 /
Kojto	112:6f327212ef96	4412	#define USB_EP1R_STAT_TX_1 ((uint32_t)0x00000020) /!<Bit 1 /
Kojto	112:6f327212ef96	4413
Kojto	112:6f327212ef96	4414	#define USB_EP1R_DTOG_TX ((uint32_t)0x00000040) /!<Data Toggle, for transmission transfers /
Kojto	112:6f327212ef96	4415	#define USB_EP1R_CTR_TX ((uint32_t)0x00000080) /!<Correct Transfer for transmission /
Kojto	112:6f327212ef96	4416	#define USB_EP1R_EP_KIND ((uint32_t)0x00000100) /!<Endpoint Kind /
Kojto	112:6f327212ef96	4417
Kojto	112:6f327212ef96	4418	#define USB_EP1R_EP_TYPE ((uint32_t)0x00000600) /!<EP_TYPE[1:0] bits (Endpoint type) /
Kojto	112:6f327212ef96	4419	#define USB_EP1R_EP_TYPE_0 ((uint32_t)0x00000200) /!<Bit 0 /
Kojto	112:6f327212ef96	4420	#define USB_EP1R_EP_TYPE_1 ((uint32_t)0x00000400) /!<Bit 1 /
Kojto	112:6f327212ef96	4421
Kojto	112:6f327212ef96	4422	#define USB_EP1R_SETUP ((uint32_t)0x00000800) /!<Setup transaction completed /
Kojto	112:6f327212ef96	4423
Kojto	112:6f327212ef96	4424	#define USB_EP1R_STAT_RX ((uint32_t)0x00003000) /!<STAT_RX[1:0] bits (Status bits, for reception transfers) /
Kojto	112:6f327212ef96	4425	#define USB_EP1R_STAT_RX_0 ((uint32_t)0x00001000) /!<Bit 0 /
Kojto	112:6f327212ef96	4426	#define USB_EP1R_STAT_RX_1 ((uint32_t)0x00002000) /!<Bit 1 /
Kojto	112:6f327212ef96	4427
Kojto	112:6f327212ef96	4428	#define USB_EP1R_DTOG_RX ((uint32_t)0x00004000) /!<Data Toggle, for reception transfers /
Kojto	112:6f327212ef96	4429	#define USB_EP1R_CTR_RX ((uint32_t)0x00008000) /!<Correct Transfer for reception /
Kojto	112:6f327212ef96	4430
Kojto	112:6f327212ef96	4431	/***************** Bit definition for USB_EP2R register *****************/
Kojto	112:6f327212ef96	4432	#define USB_EP2R_EA ((uint32_t)0x0000000F) /!<Endpoint Address /
Kojto	112:6f327212ef96	4433
Kojto	112:6f327212ef96	4434	#define USB_EP2R_STAT_TX ((uint32_t)0x00000030) /!<STAT_TX[1:0] bits (Status bits, for transmission transfers) /
Kojto	112:6f327212ef96	4435	#define USB_EP2R_STAT_TX_0 ((uint32_t)0x00000010) /!<Bit 0 /
Kojto	112:6f327212ef96	4436	#define USB_EP2R_STAT_TX_1 ((uint32_t)0x00000020) /!<Bit 1 /
Kojto	112:6f327212ef96	4437
Kojto	112:6f327212ef96	4438	#define USB_EP2R_DTOG_TX ((uint32_t)0x00000040) /!<Data Toggle, for transmission transfers /
Kojto	112:6f327212ef96	4439	#define USB_EP2R_CTR_TX ((uint32_t)0x00000080) /!<Correct Transfer for transmission /
Kojto	112:6f327212ef96	4440	#define USB_EP2R_EP_KIND ((uint32_t)0x00000100) /!<Endpoint Kind /
Kojto	112:6f327212ef96	4441
Kojto	112:6f327212ef96	4442	#define USB_EP2R_EP_TYPE ((uint32_t)0x00000600) /!<EP_TYPE[1:0] bits (Endpoint type) /
Kojto	112:6f327212ef96	4443	#define USB_EP2R_EP_TYPE_0 ((uint32_t)0x00000200) /!<Bit 0 /
Kojto	112:6f327212ef96	4444	#define USB_EP2R_EP_TYPE_1 ((uint32_t)0x00000400) /!<Bit 1 /
Kojto	112:6f327212ef96	4445
Kojto	112:6f327212ef96	4446	#define USB_EP2R_SETUP ((uint32_t)0x00000800) /!<Setup transaction completed /
Kojto	112:6f327212ef96	4447
Kojto	112:6f327212ef96	4448	#define USB_EP2R_STAT_RX ((uint32_t)0x00003000) /!<STAT_RX[1:0] bits (Status bits, for reception transfers) /
Kojto	112:6f327212ef96	4449	#define USB_EP2R_STAT_RX_0 ((uint32_t)0x00001000) /!<Bit 0 /
Kojto	112:6f327212ef96	4450	#define USB_EP2R_STAT_RX_1 ((uint32_t)0x00002000) /!<Bit 1 /
Kojto	112:6f327212ef96	4451
Kojto	112:6f327212ef96	4452	#define USB_EP2R_DTOG_RX ((uint32_t)0x00004000) /!<Data Toggle, for reception transfers /
Kojto	112:6f327212ef96	4453	#define USB_EP2R_CTR_RX ((uint32_t)0x00008000) /!<Correct Transfer for reception /
Kojto	112:6f327212ef96	4454
Kojto	112:6f327212ef96	4455	/***************** Bit definition for USB_EP3R register *****************/
Kojto	112:6f327212ef96	4456	#define USB_EP3R_EA ((uint32_t)0x0000000F) /!<Endpoint Address /
Kojto	112:6f327212ef96	4457
Kojto	112:6f327212ef96	4458	#define USB_EP3R_STAT_TX ((uint32_t)0x00000030) /!<STAT_TX[1:0] bits (Status bits, for transmission transfers) /
Kojto	112:6f327212ef96	4459	#define USB_EP3R_STAT_TX_0 ((uint32_t)0x00000010) /!<Bit 0 /
Kojto	112:6f327212ef96	4460	#define USB_EP3R_STAT_TX_1 ((uint32_t)0x00000020) /!<Bit 1 /
Kojto	112:6f327212ef96	4461
Kojto	112:6f327212ef96	4462	#define USB_EP3R_DTOG_TX ((uint32_t)0x00000040) /!<Data Toggle, for transmission transfers /
Kojto	112:6f327212ef96	4463	#define USB_EP3R_CTR_TX ((uint32_t)0x00000080) /!<Correct Transfer for transmission /
Kojto	112:6f327212ef96	4464	#define USB_EP3R_EP_KIND ((uint32_t)0x00000100) /!<Endpoint Kind /
Kojto	112:6f327212ef96	4465
Kojto	112:6f327212ef96	4466	#define USB_EP3R_EP_TYPE ((uint32_t)0x00000600) /!<EP_TYPE[1:0] bits (Endpoint type) /
Kojto	112:6f327212ef96	4467	#define USB_EP3R_EP_TYPE_0 ((uint32_t)0x00000200) /!<Bit 0 /
Kojto	112:6f327212ef96	4468	#define USB_EP3R_EP_TYPE_1 ((uint32_t)0x00000400) /!<Bit 1 /
Kojto	112:6f327212ef96	4469
Kojto	112:6f327212ef96	4470	#define USB_EP3R_SETUP ((uint32_t)0x00000800) /!<Setup transaction completed /
Kojto	112:6f327212ef96	4471
Kojto	112:6f327212ef96	4472	#define USB_EP3R_STAT_RX ((uint32_t)0x00003000) /!<STAT_RX[1:0] bits (Status bits, for reception transfers) /
Kojto	112:6f327212ef96	4473	#define USB_EP3R_STAT_RX_0 ((uint32_t)0x00001000) /!<Bit 0 /
Kojto	112:6f327212ef96	4474	#define USB_EP3R_STAT_RX_1 ((uint32_t)0x00002000) /!<Bit 1 /
Kojto	112:6f327212ef96	4475
Kojto	112:6f327212ef96	4476	#define USB_EP3R_DTOG_RX ((uint32_t)0x00004000) /!<Data Toggle, for reception transfers /
Kojto	112:6f327212ef96	4477	#define USB_EP3R_CTR_RX ((uint32_t)0x00008000) /!<Correct Transfer for reception /
Kojto	112:6f327212ef96	4478
Kojto	112:6f327212ef96	4479	/***************** Bit definition for USB_EP4R register *****************/
Kojto	112:6f327212ef96	4480	#define USB_EP4R_EA ((uint32_t)0x0000000F) /!<Endpoint Address /
Kojto	112:6f327212ef96	4481
Kojto	112:6f327212ef96	4482	#define USB_EP4R_STAT_TX ((uint32_t)0x00000030) /!<STAT_TX[1:0] bits (Status bits, for transmission transfers) /
Kojto	112:6f327212ef96	4483	#define USB_EP4R_STAT_TX_0 ((uint32_t)0x00000010) /!<Bit 0 /
Kojto	112:6f327212ef96	4484	#define USB_EP4R_STAT_TX_1 ((uint32_t)0x00000020) /!<Bit 1 /
Kojto	112:6f327212ef96	4485
Kojto	112:6f327212ef96	4486	#define USB_EP4R_DTOG_TX ((uint32_t)0x00000040) /!<Data Toggle, for transmission transfers /
Kojto	112:6f327212ef96	4487	#define USB_EP4R_CTR_TX ((uint32_t)0x00000080) /!<Correct Transfer for transmission /
Kojto	112:6f327212ef96	4488	#define USB_EP4R_EP_KIND ((uint32_t)0x00000100) /!<Endpoint Kind /
Kojto	112:6f327212ef96	4489
Kojto	112:6f327212ef96	4490	#define USB_EP4R_EP_TYPE ((uint32_t)0x00000600) /!<EP_TYPE[1:0] bits (Endpoint type) /
Kojto	112:6f327212ef96	4491	#define USB_EP4R_EP_TYPE_0 ((uint32_t)0x00000200) /!<Bit 0 /
Kojto	112:6f327212ef96	4492	#define USB_EP4R_EP_TYPE_1 ((uint32_t)0x00000400) /!<Bit 1 /
Kojto	112:6f327212ef96	4493
Kojto	112:6f327212ef96	4494	#define USB_EP4R_SETUP ((uint32_t)0x00000800) /!<Setup transaction completed /
Kojto	112:6f327212ef96	4495
Kojto	112:6f327212ef96	4496	#define USB_EP4R_STAT_RX ((uint32_t)0x00003000) /!<STAT_RX[1:0] bits (Status bits, for reception transfers) /
Kojto	112:6f327212ef96	4497	#define USB_EP4R_STAT_RX_0 ((uint32_t)0x00001000) /!<Bit 0 /
Kojto	112:6f327212ef96	4498	#define USB_EP4R_STAT_RX_1 ((uint32_t)0x00002000) /!<Bit 1 /
Kojto	112:6f327212ef96	4499
Kojto	112:6f327212ef96	4500	#define USB_EP4R_DTOG_RX ((uint32_t)0x00004000) /!<Data Toggle, for reception transfers /
Kojto	112:6f327212ef96	4501	#define USB_EP4R_CTR_RX ((uint32_t)0x00008000) /!<Correct Transfer for reception /
Kojto	112:6f327212ef96	4502
Kojto	112:6f327212ef96	4503	/***************** Bit definition for USB_EP5R register *****************/
Kojto	112:6f327212ef96	4504	#define USB_EP5R_EA ((uint32_t)0x0000000F) /!<Endpoint Address /
Kojto	112:6f327212ef96	4505
Kojto	112:6f327212ef96	4506	#define USB_EP5R_STAT_TX ((uint32_t)0x00000030) /!<STAT_TX[1:0] bits (Status bits, for transmission transfers) /
Kojto	112:6f327212ef96	4507	#define USB_EP5R_STAT_TX_0 ((uint32_t)0x00000010) /!<Bit 0 /
Kojto	112:6f327212ef96	4508	#define USB_EP5R_STAT_TX_1 ((uint32_t)0x00000020) /!<Bit 1 /
Kojto	112:6f327212ef96	4509
Kojto	112:6f327212ef96	4510	#define USB_EP5R_DTOG_TX ((uint32_t)0x00000040) /!<Data Toggle, for transmission transfers /
Kojto	112:6f327212ef96	4511	#define USB_EP5R_CTR_TX ((uint32_t)0x00000080) /!<Correct Transfer for transmission /
Kojto	112:6f327212ef96	4512	#define USB_EP5R_EP_KIND ((uint32_t)0x00000100) /!<Endpoint Kind /
Kojto	112:6f327212ef96	4513
Kojto	112:6f327212ef96	4514	#define USB_EP5R_EP_TYPE ((uint32_t)0x00000600) /!<EP_TYPE[1:0] bits (Endpoint type) /
Kojto	112:6f327212ef96	4515	#define USB_EP5R_EP_TYPE_0 ((uint32_t)0x00000200) /!<Bit 0 /
Kojto	112:6f327212ef96	4516	#define USB_EP5R_EP_TYPE_1 ((uint32_t)0x00000400) /!<Bit 1 /
Kojto	112:6f327212ef96	4517
Kojto	112:6f327212ef96	4518	#define USB_EP5R_SETUP ((uint32_t)0x00000800) /!<Setup transaction completed /
Kojto	112:6f327212ef96	4519
Kojto	112:6f327212ef96	4520	#define USB_EP5R_STAT_RX ((uint32_t)0x00003000) /!<STAT_RX[1:0] bits (Status bits, for reception transfers) /
Kojto	112:6f327212ef96	4521	#define USB_EP5R_STAT_RX_0 ((uint32_t)0x00001000) /!<Bit 0 /
Kojto	112:6f327212ef96	4522	#define USB_EP5R_STAT_RX_1 ((uint32_t)0x00002000) /!<Bit 1 /
Kojto	112:6f327212ef96	4523
Kojto	112:6f327212ef96	4524	#define USB_EP5R_DTOG_RX ((uint32_t)0x00004000) /!<Data Toggle, for reception transfers /
Kojto	112:6f327212ef96	4525	#define USB_EP5R_CTR_RX ((uint32_t)0x00008000) /!<Correct Transfer for reception /
Kojto	112:6f327212ef96	4526
Kojto	112:6f327212ef96	4527	/***************** Bit definition for USB_EP6R register *****************/
Kojto	112:6f327212ef96	4528	#define USB_EP6R_EA ((uint32_t)0x0000000F) /!<Endpoint Address /
Kojto	112:6f327212ef96	4529
Kojto	112:6f327212ef96	4530	#define USB_EP6R_STAT_TX ((uint32_t)0x00000030) /!<STAT_TX[1:0] bits (Status bits, for transmission transfers) /
Kojto	112:6f327212ef96	4531	#define USB_EP6R_STAT_TX_0 ((uint32_t)0x00000010) /!<Bit 0 /
Kojto	112:6f327212ef96	4532	#define USB_EP6R_STAT_TX_1 ((uint32_t)0x00000020) /!<Bit 1 /
Kojto	112:6f327212ef96	4533
Kojto	112:6f327212ef96	4534	#define USB_EP6R_DTOG_TX ((uint32_t)0x00000040) /!<Data Toggle, for transmission transfers /
Kojto	112:6f327212ef96	4535	#define USB_EP6R_CTR_TX ((uint32_t)0x00000080) /!<Correct Transfer for transmission /
Kojto	112:6f327212ef96	4536	#define USB_EP6R_EP_KIND ((uint32_t)0x00000100) /!<Endpoint Kind /
Kojto	112:6f327212ef96	4537
Kojto	112:6f327212ef96	4538	#define USB_EP6R_EP_TYPE ((uint32_t)0x00000600) /!<EP_TYPE[1:0] bits (Endpoint type) /
Kojto	112:6f327212ef96	4539	#define USB_EP6R_EP_TYPE_0 ((uint32_t)0x00000200) /!<Bit 0 /
Kojto	112:6f327212ef96	4540	#define USB_EP6R_EP_TYPE_1 ((uint32_t)0x00000400) /!<Bit 1 /
Kojto	112:6f327212ef96	4541
Kojto	112:6f327212ef96	4542	#define USB_EP6R_SETUP ((uint32_t)0x00000800) /!<Setup transaction completed /
Kojto	112:6f327212ef96	4543
Kojto	112:6f327212ef96	4544	#define USB_EP6R_STAT_RX ((uint32_t)0x00003000) /!<STAT_RX[1:0] bits (Status bits, for reception transfers) /
Kojto	112:6f327212ef96	4545	#define USB_EP6R_STAT_RX_0 ((uint32_t)0x00001000) /!<Bit 0 /
Kojto	112:6f327212ef96	4546	#define USB_EP6R_STAT_RX_1 ((uint32_t)0x00002000) /!<Bit 1 /
Kojto	112:6f327212ef96	4547
Kojto	112:6f327212ef96	4548	#define USB_EP6R_DTOG_RX ((uint32_t)0x00004000) /!<Data Toggle, for reception transfers /
Kojto	112:6f327212ef96	4549	#define USB_EP6R_CTR_RX ((uint32_t)0x00008000) /!<Correct Transfer for reception /
Kojto	112:6f327212ef96	4550
Kojto	112:6f327212ef96	4551	/***************** Bit definition for USB_EP7R register *****************/
Kojto	112:6f327212ef96	4552	#define USB_EP7R_EA ((uint32_t)0x0000000F) /!<Endpoint Address /
Kojto	112:6f327212ef96	4553
Kojto	112:6f327212ef96	4554	#define USB_EP7R_STAT_TX ((uint32_t)0x00000030) /!<STAT_TX[1:0] bits (Status bits, for transmission transfers) /
Kojto	112:6f327212ef96	4555	#define USB_EP7R_STAT_TX_0 ((uint32_t)0x00000010) /!<Bit 0 /
Kojto	112:6f327212ef96	4556	#define USB_EP7R_STAT_TX_1 ((uint32_t)0x00000020) /!<Bit 1 /
Kojto	112:6f327212ef96	4557
Kojto	112:6f327212ef96	4558	#define USB_EP7R_DTOG_TX ((uint32_t)0x00000040) /!<Data Toggle, for transmission transfers /
Kojto	112:6f327212ef96	4559	#define USB_EP7R_CTR_TX ((uint32_t)0x00000080) /!<Correct Transfer for transmission /
Kojto	112:6f327212ef96	4560	#define USB_EP7R_EP_KIND ((uint32_t)0x00000100) /!<Endpoint Kind /
Kojto	112:6f327212ef96	4561
Kojto	112:6f327212ef96	4562	#define USB_EP7R_EP_TYPE ((uint32_t)0x00000600) /!<EP_TYPE[1:0] bits (Endpoint type) /
Kojto	112:6f327212ef96	4563	#define USB_EP7R_EP_TYPE_0 ((uint32_t)0x00000200) /!<Bit 0 /
Kojto	112:6f327212ef96	4564	#define USB_EP7R_EP_TYPE_1 ((uint32_t)0x00000400) /!<Bit 1 /
Kojto	112:6f327212ef96	4565
Kojto	112:6f327212ef96	4566	#define USB_EP7R_SETUP ((uint32_t)0x00000800) /!<Setup transaction completed /
Kojto	112:6f327212ef96	4567
Kojto	112:6f327212ef96	4568	#define USB_EP7R_STAT_RX ((uint32_t)0x00003000) /!<STAT_RX[1:0] bits (Status bits, for reception transfers) /
Kojto	112:6f327212ef96	4569	#define USB_EP7R_STAT_RX_0 ((uint32_t)0x00001000) /!<Bit 0 /
Kojto	112:6f327212ef96	4570	#define USB_EP7R_STAT_RX_1 ((uint32_t)0x00002000) /!<Bit 1 /
Kojto	112:6f327212ef96	4571
Kojto	112:6f327212ef96	4572	#define USB_EP7R_DTOG_RX ((uint32_t)0x00004000) /!<Data Toggle, for reception transfers /
Kojto	112:6f327212ef96	4573	#define USB_EP7R_CTR_RX ((uint32_t)0x00008000) /!<Correct Transfer for reception /
Kojto	112:6f327212ef96	4574
Kojto	112:6f327212ef96	4575	/!<Common registers /
Kojto	112:6f327212ef96	4576
Kojto	112:6f327212ef96	4577	#define USB_CNTR (USB_BASE + 0x00000040) /!< Control register /
Kojto	112:6f327212ef96	4578	#define USB_ISTR (USB_BASE + 0x00000044) /!< Interrupt status register /
Kojto	112:6f327212ef96	4579	#define USB_FNR (USB_BASE + 0x00000048) /!< Frame number register /
Kojto	112:6f327212ef96	4580	#define USB_DADDR (USB_BASE + 0x0000004C) /!< Device address register /
Kojto	112:6f327212ef96	4581	#define USB_BTABLE (USB_BASE + 0x00000050) /!< Buffer Table address register /
Kojto	112:6f327212ef96	4582
Kojto	112:6f327212ef96	4583
Kojto	112:6f327212ef96	4584
Kojto	112:6f327212ef96	4585	/***************** Bit definition for USB_CNTR register *****************/
Kojto	112:6f327212ef96	4586	#define USB_CNTR_FRES ((uint32_t)0x00000001) /!<Force USB Reset /
Kojto	112:6f327212ef96	4587	#define USB_CNTR_PDWN ((uint32_t)0x00000002) /!<Power down /
Kojto	112:6f327212ef96	4588	#define USB_CNTR_LP_MODE ((uint32_t)0x00000004) /!<Low-power mode /
Kojto	112:6f327212ef96	4589	#define USB_CNTR_FSUSP ((uint32_t)0x00000008) /!<Force suspend /
Kojto	112:6f327212ef96	4590	#define USB_CNTR_RESUME ((uint32_t)0x00000010) /!<Resume request /
Kojto	112:6f327212ef96	4591	#define USB_CNTR_ESOFM ((uint32_t)0x00000100) /!<Expected Start Of Frame Interrupt Mask /
Kojto	112:6f327212ef96	4592	#define USB_CNTR_SOFM ((uint32_t)0x00000200) /!<Start Of Frame Interrupt Mask /
Kojto	112:6f327212ef96	4593	#define USB_CNTR_RESETM ((uint32_t)0x00000400) /!<RESET Interrupt Mask /
Kojto	112:6f327212ef96	4594	#define USB_CNTR_SUSPM ((uint32_t)0x00000800) /!<Suspend mode Interrupt Mask /
Kojto	112:6f327212ef96	4595	#define USB_CNTR_WKUPM ((uint32_t)0x00001000) /!<Wakeup Interrupt Mask /
Kojto	112:6f327212ef96	4596	#define USB_CNTR_ERRM ((uint32_t)0x00002000) /!<Error Interrupt Mask /
Kojto	112:6f327212ef96	4597	#define USB_CNTR_PMAOVRM ((uint32_t)0x00004000) /!<Packet Memory Area Over / Underrun Interrupt Mask /
Kojto	112:6f327212ef96	4598	#define USB_CNTR_CTRM ((uint32_t)0x00008000) /!<Correct Transfer Interrupt Mask /
Kojto	112:6f327212ef96	4599
Kojto	112:6f327212ef96	4600	/***************** Bit definition for USB_ISTR register *****************/
Kojto	112:6f327212ef96	4601	#define USB_ISTR_EP_ID ((uint32_t)0x0000000F) /!<Endpoint Identifier /
Kojto	112:6f327212ef96	4602	#define USB_ISTR_DIR ((uint32_t)0x00000010) /!<Direction of transaction /
Kojto	112:6f327212ef96	4603	#define USB_ISTR_ESOF ((uint32_t)0x00000100) /!<Expected Start Of Frame /
Kojto	112:6f327212ef96	4604	#define USB_ISTR_SOF ((uint32_t)0x00000200) /!<Start Of Frame /
Kojto	112:6f327212ef96	4605	#define USB_ISTR_RESET ((uint32_t)0x00000400) /!<USB RESET request /
Kojto	112:6f327212ef96	4606	#define USB_ISTR_SUSP ((uint32_t)0x00000800) /!<Suspend mode request /
Kojto	112:6f327212ef96	4607	#define USB_ISTR_WKUP ((uint32_t)0x00001000) /!<Wake up /
Kojto	112:6f327212ef96	4608	#define USB_ISTR_ERR ((uint32_t)0x00002000) /!<Error /
Kojto	112:6f327212ef96	4609	#define USB_ISTR_PMAOVRM ((uint32_t)0x00004000) /!<Packet Memory Area Over / Underrun /
Kojto	112:6f327212ef96	4610	#define USB_ISTR_CTR ((uint32_t)0x00008000) /!<Correct Transfer /
Kojto	112:6f327212ef96	4611
Kojto	112:6f327212ef96	4612	#define USB_CLR_CTR (~USB_ISTR_CTR) /!< clear Correct TRansfer bit /
Kojto	112:6f327212ef96	4613	#define USB_CLR_PMAOVRM (~USB_ISTR_PMAOVR) /!< clear DMA OVeR/underrun bit/
Kojto	112:6f327212ef96	4614	#define USB_CLR_ERR (~USB_ISTR_ERR) /!< clear ERRor bit /
Kojto	112:6f327212ef96	4615	#define USB_CLR_WKUP (~USB_ISTR_WKUP) /!< clear WaKe UP bit /
Kojto	112:6f327212ef96	4616	#define USB_CLR_SUSP (~USB_ISTR_SUSP) /!< clear SUSPend bit /
Kojto	112:6f327212ef96	4617	#define USB_CLR_RESET (~USB_ISTR_RESET) /!< clear RESET bit /
Kojto	112:6f327212ef96	4618	#define USB_CLR_SOF (~USB_ISTR_SOF) /!< clear Start Of Frame bit /
Kojto	112:6f327212ef96	4619	#define USB_CLR_ESOF (~USB_ISTR_ESOF) /!< clear Expected Start Of Frame bit /
Kojto	112:6f327212ef96	4620
Kojto	112:6f327212ef96	4621
Kojto	112:6f327212ef96	4622	/***************** Bit definition for USB_FNR register ******************/
Kojto	112:6f327212ef96	4623	#define USB_FNR_FN ((uint32_t)0x000007FF) /!<Frame Number /
Kojto	112:6f327212ef96	4624	#define USB_FNR_LSOF ((uint32_t)0x00001800) /!<Lost SOF /
Kojto	112:6f327212ef96	4625	#define USB_FNR_LCK ((uint32_t)0x00002000) /!<Locked /
Kojto	112:6f327212ef96	4626	#define USB_FNR_RXDM ((uint32_t)0x00004000) /!<Receive Data - Line Status /
Kojto	112:6f327212ef96	4627	#define USB_FNR_RXDP ((uint32_t)0x00008000) /!<Receive Data + Line Status /
Kojto	112:6f327212ef96	4628
Kojto	112:6f327212ef96	4629	/**************** Bit definition for USB_DADDR register *****************/
Kojto	112:6f327212ef96	4630	#define USB_DADDR_ADD ((uint32_t)0x0000007F) /!<ADD[6:0] bits (Device Address) /
Kojto	112:6f327212ef96	4631	#define USB_DADDR_ADD0 ((uint32_t)0x00000001) /!<Bit 0 /
Kojto	112:6f327212ef96	4632	#define USB_DADDR_ADD1 ((uint32_t)0x00000002) /!<Bit 1 /
Kojto	112:6f327212ef96	4633	#define USB_DADDR_ADD2 ((uint32_t)0x00000004) /!<Bit 2 /
Kojto	112:6f327212ef96	4634	#define USB_DADDR_ADD3 ((uint32_t)0x00000008) /!<Bit 3 /
Kojto	112:6f327212ef96	4635	#define USB_DADDR_ADD4 ((uint32_t)0x00000010) /!<Bit 4 /
Kojto	112:6f327212ef96	4636	#define USB_DADDR_ADD5 ((uint32_t)0x00000020) /!<Bit 5 /
Kojto	112:6f327212ef96	4637	#define USB_DADDR_ADD6 ((uint32_t)0x00000040) /!<Bit 6 /
Kojto	112:6f327212ef96	4638
Kojto	112:6f327212ef96	4639	#define USB_DADDR_EF ((uint32_t)0x00000080) /!<Enable Function /
Kojto	112:6f327212ef96	4640
Kojto	112:6f327212ef96	4641	/**************** Bit definition for USB_BTABLE register ****************/
Kojto	112:6f327212ef96	4642	#define USB_BTABLE_BTABLE ((uint32_t)0x0000FFF8) /!<Buffer Table /
Kojto	112:6f327212ef96	4643
Kojto	112:6f327212ef96	4644	/!< Buffer descriptor table /
Kojto	112:6f327212ef96	4645	/*************** Bit definition for USB_ADDR0_TX register ***************/
Kojto	112:6f327212ef96	4646	#define USB_ADDR0_TX_ADDR0_TX ((uint32_t)0x0000FFFE) /!< Transmission Buffer Address 0 /
Kojto	112:6f327212ef96	4647
Kojto	112:6f327212ef96	4648	/*************** Bit definition for USB_ADDR1_TX register ***************/
Kojto	112:6f327212ef96	4649	#define USB_ADDR1_TX_ADDR1_TX ((uint32_t)0x0000FFFE) /!< Transmission Buffer Address 1 /
Kojto	112:6f327212ef96	4650
Kojto	112:6f327212ef96	4651	/*************** Bit definition for USB_ADDR2_TX register ***************/
Kojto	112:6f327212ef96	4652	#define USB_ADDR2_TX_ADDR2_TX ((uint32_t)0x0000FFFE) /!< Transmission Buffer Address 2 /
Kojto	112:6f327212ef96	4653
Kojto	112:6f327212ef96	4654	/*************** Bit definition for USB_ADDR3_TX register ***************/
Kojto	112:6f327212ef96	4655	#define USB_ADDR3_TX_ADDR3_TX ((uint32_t)0x0000FFFE) /!< Transmission Buffer Address 3 /
Kojto	112:6f327212ef96	4656
Kojto	112:6f327212ef96	4657	/*************** Bit definition for USB_ADDR4_TX register ***************/
Kojto	112:6f327212ef96	4658	#define USB_ADDR4_TX_ADDR4_TX ((uint32_t)0x0000FFFE) /!< Transmission Buffer Address 4 /
Kojto	112:6f327212ef96	4659
Kojto	112:6f327212ef96	4660	/*************** Bit definition for USB_ADDR5_TX register ***************/
Kojto	112:6f327212ef96	4661	#define USB_ADDR5_TX_ADDR5_TX ((uint32_t)0x0000FFFE) /!< Transmission Buffer Address 5 /
Kojto	112:6f327212ef96	4662
Kojto	112:6f327212ef96	4663	/*************** Bit definition for USB_ADDR6_TX register ***************/
Kojto	112:6f327212ef96	4664	#define USB_ADDR6_TX_ADDR6_TX ((uint32_t)0x0000FFFE) /!< Transmission Buffer Address 6 /
Kojto	112:6f327212ef96	4665
Kojto	112:6f327212ef96	4666	/*************** Bit definition for USB_ADDR7_TX register ***************/
Kojto	112:6f327212ef96	4667	#define USB_ADDR7_TX_ADDR7_TX ((uint32_t)0x0000FFFE) /!< Transmission Buffer Address 7 /
Kojto	112:6f327212ef96	4668
Kojto	112:6f327212ef96	4669	/----------------------------------------------------------------------------/
Kojto	112:6f327212ef96	4670
Kojto	112:6f327212ef96	4671	/*************** Bit definition for USB_COUNT0_TX register **************/
Kojto	112:6f327212ef96	4672	#define USB_COUNT0_TX_COUNT0_TX ((uint32_t)0x000003FF) /!< Transmission Byte Count 0 /
Kojto	112:6f327212ef96	4673
Kojto	112:6f327212ef96	4674	/*************** Bit definition for USB_COUNT1_TX register **************/
Kojto	112:6f327212ef96	4675	#define USB_COUNT1_TX_COUNT1_TX ((uint32_t)0x000003FF) /!< Transmission Byte Count 1 /
Kojto	112:6f327212ef96	4676
Kojto	112:6f327212ef96	4677	/*************** Bit definition for USB_COUNT2_TX register **************/
Kojto	112:6f327212ef96	4678	#define USB_COUNT2_TX_COUNT2_TX ((uint32_t)0x000003FF) /!< Transmission Byte Count 2 /
Kojto	112:6f327212ef96	4679
Kojto	112:6f327212ef96	4680	/*************** Bit definition for USB_COUNT3_TX register **************/
Kojto	112:6f327212ef96	4681	#define USB_COUNT3_TX_COUNT3_TX ((uint32_t)0x000003FF) /!< Transmission Byte Count 3 /
Kojto	112:6f327212ef96	4682
Kojto	112:6f327212ef96	4683	/*************** Bit definition for USB_COUNT4_TX register **************/
Kojto	112:6f327212ef96	4684	#define USB_COUNT4_TX_COUNT4_TX ((uint32_t)0x000003FF) /!< Transmission Byte Count 4 /
Kojto	112:6f327212ef96	4685
Kojto	112:6f327212ef96	4686	/*************** Bit definition for USB_COUNT5_TX register **************/
Kojto	112:6f327212ef96	4687	#define USB_COUNT5_TX_COUNT5_TX ((uint32_t)0x000003FF) /!< Transmission Byte Count 5 /
Kojto	112:6f327212ef96	4688
Kojto	112:6f327212ef96	4689	/*************** Bit definition for USB_COUNT6_TX register **************/
Kojto	112:6f327212ef96	4690	#define USB_COUNT6_TX_COUNT6_TX ((uint32_t)0x000003FF) /!< Transmission Byte Count 6 /
Kojto	112:6f327212ef96	4691
Kojto	112:6f327212ef96	4692	/*************** Bit definition for USB_COUNT7_TX register **************/
Kojto	112:6f327212ef96	4693	#define USB_COUNT7_TX_COUNT7_TX ((uint32_t)0x000003FF) /!< Transmission Byte Count 7 /
Kojto	112:6f327212ef96	4694
Kojto	112:6f327212ef96	4695	/----------------------------------------------------------------------------/
Kojto	112:6f327212ef96	4696
Kojto	112:6f327212ef96	4697	/************** Bit definition for USB_COUNT0_TX_0 register *************/
Kojto	112:6f327212ef96	4698	#define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) /!< Transmission Byte Count 0 (low) /
Kojto	112:6f327212ef96	4699
Kojto	112:6f327212ef96	4700	/************** Bit definition for USB_COUNT0_TX_1 register *************/
Kojto	112:6f327212ef96	4701	#define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) /!< Transmission Byte Count 0 (high) /
Kojto	112:6f327212ef96	4702
Kojto	112:6f327212ef96	4703	/************** Bit definition for USB_COUNT1_TX_0 register *************/
Kojto	112:6f327212ef96	4704	#define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) /!< Transmission Byte Count 1 (low) /
Kojto	112:6f327212ef96	4705
Kojto	112:6f327212ef96	4706	/************** Bit definition for USB_COUNT1_TX_1 register *************/
Kojto	112:6f327212ef96	4707	#define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) /!< Transmission Byte Count 1 (high) /
Kojto	112:6f327212ef96	4708
Kojto	112:6f327212ef96	4709	/************** Bit definition for USB_COUNT2_TX_0 register *************/
Kojto	112:6f327212ef96	4710	#define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) /!< Transmission Byte Count 2 (low) /
Kojto	112:6f327212ef96	4711
Kojto	112:6f327212ef96	4712	/************** Bit definition for USB_COUNT2_TX_1 register *************/
Kojto	112:6f327212ef96	4713	#define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) /!< Transmission Byte Count 2 (high) /
Kojto	112:6f327212ef96	4714
Kojto	112:6f327212ef96	4715	/************** Bit definition for USB_COUNT3_TX_0 register *************/
Kojto	112:6f327212ef96	4716	#define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint32_t)0x0000000003FF) /!< Transmission Byte Count 3 (low) /
Kojto	112:6f327212ef96	4717
Kojto	112:6f327212ef96	4718	/************** Bit definition for USB_COUNT3_TX_1 register *************/
Kojto	112:6f327212ef96	4719	#define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint32_t)0x000003FF0000) /!< Transmission Byte Count 3 (high) /
Kojto	112:6f327212ef96	4720
Kojto	112:6f327212ef96	4721	/************** Bit definition for USB_COUNT4_TX_0 register *************/
Kojto	112:6f327212ef96	4722	#define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) /!< Transmission Byte Count 4 (low) /
Kojto	112:6f327212ef96	4723
Kojto	112:6f327212ef96	4724	/************** Bit definition for USB_COUNT4_TX_1 register *************/
Kojto	112:6f327212ef96	4725	#define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) /!< Transmission Byte Count 4 (high) /
Kojto	112:6f327212ef96	4726
Kojto	112:6f327212ef96	4727	/************** Bit definition for USB_COUNT5_TX_0 register *************/
Kojto	112:6f327212ef96	4728	#define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) /!< Transmission Byte Count 5 (low) /
Kojto	112:6f327212ef96	4729
Kojto	112:6f327212ef96	4730	/************** Bit definition for USB_COUNT5_TX_1 register *************/
Kojto	112:6f327212ef96	4731	#define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) /!< Transmission Byte Count 5 (high) /
Kojto	112:6f327212ef96	4732
Kojto	112:6f327212ef96	4733	/************** Bit definition for USB_COUNT6_TX_0 register *************/
Kojto	112:6f327212ef96	4734	#define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) /!< Transmission Byte Count 6 (low) /
Kojto	112:6f327212ef96	4735
Kojto	112:6f327212ef96	4736	/************** Bit definition for USB_COUNT6_TX_1 register *************/
Kojto	112:6f327212ef96	4737	#define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) /!< Transmission Byte Count 6 (high) /
Kojto	112:6f327212ef96	4738
Kojto	112:6f327212ef96	4739	/************** Bit definition for USB_COUNT7_TX_0 register *************/
Kojto	112:6f327212ef96	4740	#define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) /!< Transmission Byte Count 7 (low) /
Kojto	112:6f327212ef96	4741
Kojto	112:6f327212ef96	4742	/************** Bit definition for USB_COUNT7_TX_1 register *************/
Kojto	112:6f327212ef96	4743	#define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) /!< Transmission Byte Count 7 (high) /
Kojto	112:6f327212ef96	4744
Kojto	112:6f327212ef96	4745	/----------------------------------------------------------------------------/
Kojto	112:6f327212ef96	4746
Kojto	112:6f327212ef96	4747	/*************** Bit definition for USB_ADDR0_RX register ***************/
Kojto	112:6f327212ef96	4748	#define USB_ADDR0_RX_ADDR0_RX ((uint32_t)0x0000FFFE) /!< Reception Buffer Address 0 /
Kojto	112:6f327212ef96	4749
Kojto	112:6f327212ef96	4750	/*************** Bit definition for USB_ADDR1_RX register ***************/
Kojto	112:6f327212ef96	4751	#define USB_ADDR1_RX_ADDR1_RX ((uint32_t)0x0000FFFE) /!< Reception Buffer Address 1 /
Kojto	112:6f327212ef96	4752
Kojto	112:6f327212ef96	4753	/*************** Bit definition for USB_ADDR2_RX register ***************/
Kojto	112:6f327212ef96	4754	#define USB_ADDR2_RX_ADDR2_RX ((uint32_t)0x0000FFFE) /!< Reception Buffer Address 2 /
Kojto	112:6f327212ef96	4755
Kojto	112:6f327212ef96	4756	/*************** Bit definition for USB_ADDR3_RX register ***************/
Kojto	112:6f327212ef96	4757	#define USB_ADDR3_RX_ADDR3_RX ((uint32_t)0x0000FFFE) /!< Reception Buffer Address 3 /
Kojto	112:6f327212ef96	4758
Kojto	112:6f327212ef96	4759	/*************** Bit definition for USB_ADDR4_RX register ***************/
Kojto	112:6f327212ef96	4760	#define USB_ADDR4_RX_ADDR4_RX ((uint32_t)0x0000FFFE) /!< Reception Buffer Address 4 /
Kojto	112:6f327212ef96	4761
Kojto	112:6f327212ef96	4762	/*************** Bit definition for USB_ADDR5_RX register ***************/
Kojto	112:6f327212ef96	4763	#define USB_ADDR5_RX_ADDR5_RX ((uint32_t)0x0000FFFE) /!< Reception Buffer Address 5 /
Kojto	112:6f327212ef96	4764
Kojto	112:6f327212ef96	4765	/*************** Bit definition for USB_ADDR6_RX register ***************/
Kojto	112:6f327212ef96	4766	#define USB_ADDR6_RX_ADDR6_RX ((uint32_t)0x0000FFFE) /!< Reception Buffer Address 6 /
Kojto	112:6f327212ef96	4767
Kojto	112:6f327212ef96	4768	/*************** Bit definition for USB_ADDR7_RX register ***************/
Kojto	112:6f327212ef96	4769	#define USB_ADDR7_RX_ADDR7_RX ((uint32_t)0x0000FFFE) /!< Reception Buffer Address 7 /
Kojto	112:6f327212ef96	4770
Kojto	112:6f327212ef96	4771	/----------------------------------------------------------------------------/
Kojto	112:6f327212ef96	4772
Kojto	112:6f327212ef96	4773	/*************** Bit definition for USB_COUNT0_RX register **************/
Kojto	112:6f327212ef96	4774	#define USB_COUNT0_RX_COUNT0_RX ((uint32_t)0x000003FF) /!< Reception Byte Count /
Kojto	112:6f327212ef96	4775
Kojto	112:6f327212ef96	4776	#define USB_COUNT0_RX_NUM_BLOCK ((uint32_t)0x00007C00) /!< NUM_BLOCK[4:0] bits (Number of blocks) /
Kojto	112:6f327212ef96	4777	#define USB_COUNT0_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /!< Bit 0 /
Kojto	112:6f327212ef96	4778	#define USB_COUNT0_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /!< Bit 1 /
Kojto	112:6f327212ef96	4779	#define USB_COUNT0_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /!< Bit 2 /
Kojto	112:6f327212ef96	4780	#define USB_COUNT0_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /!< Bit 3 /
Kojto	112:6f327212ef96	4781	#define USB_COUNT0_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /!< Bit 4 /
Kojto	112:6f327212ef96	4782
Kojto	112:6f327212ef96	4783	#define USB_COUNT0_RX_BLSIZE ((uint32_t)0x00008000) /!< BLock SIZE /
Kojto	112:6f327212ef96	4784
Kojto	112:6f327212ef96	4785	/*************** Bit definition for USB_COUNT1_RX register **************/
Kojto	112:6f327212ef96	4786	#define USB_COUNT1_RX_COUNT1_RX ((uint32_t)0x000003FF) /!< Reception Byte Count /
Kojto	112:6f327212ef96	4787
Kojto	112:6f327212ef96	4788	#define USB_COUNT1_RX_NUM_BLOCK ((uint32_t)0x00007C00) /!< NUM_BLOCK[4:0] bits (Number of blocks) /
Kojto	112:6f327212ef96	4789	#define USB_COUNT1_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /!< Bit 0 /
Kojto	112:6f327212ef96	4790	#define USB_COUNT1_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /!< Bit 1 /
Kojto	112:6f327212ef96	4791	#define USB_COUNT1_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /!< Bit 2 /
Kojto	112:6f327212ef96	4792	#define USB_COUNT1_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /!< Bit 3 /
Kojto	112:6f327212ef96	4793	#define USB_COUNT1_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /!< Bit 4 /
Kojto	112:6f327212ef96	4794
Kojto	112:6f327212ef96	4795	#define USB_COUNT1_RX_BLSIZE ((uint32_t)0x00008000) /!< BLock SIZE /
Kojto	112:6f327212ef96	4796
Kojto	112:6f327212ef96	4797	/*************** Bit definition for USB_COUNT2_RX register **************/
Kojto	112:6f327212ef96	4798	#define USB_COUNT2_RX_COUNT2_RX ((uint32_t)0x000003FF) /!< Reception Byte Count /
Kojto	112:6f327212ef96	4799
Kojto	112:6f327212ef96	4800	#define USB_COUNT2_RX_NUM_BLOCK ((uint32_t)0x00007C00) /!< NUM_BLOCK[4:0] bits (Number of blocks) /
Kojto	112:6f327212ef96	4801	#define USB_COUNT2_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /!< Bit 0 /
Kojto	112:6f327212ef96	4802	#define USB_COUNT2_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /!< Bit 1 /
Kojto	112:6f327212ef96	4803	#define USB_COUNT2_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /!< Bit 2 /
Kojto	112:6f327212ef96	4804	#define USB_COUNT2_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /!< Bit 3 /
Kojto	112:6f327212ef96	4805	#define USB_COUNT2_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /!< Bit 4 /
Kojto	112:6f327212ef96	4806
Kojto	112:6f327212ef96	4807	#define USB_COUNT2_RX_BLSIZE ((uint32_t)0x00008000) /!< BLock SIZE /
Kojto	112:6f327212ef96	4808
Kojto	112:6f327212ef96	4809	/*************** Bit definition for USB_COUNT3_RX register **************/
Kojto	112:6f327212ef96	4810	#define USB_COUNT3_RX_COUNT3_RX ((uint32_t)0x000003FF) /!< Reception Byte Count /
Kojto	112:6f327212ef96	4811
Kojto	112:6f327212ef96	4812	#define USB_COUNT3_RX_NUM_BLOCK ((uint32_t)0x00007C00) /!< NUM_BLOCK[4:0] bits (Number of blocks) /
Kojto	112:6f327212ef96	4813	#define USB_COUNT3_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /!< Bit 0 /
Kojto	112:6f327212ef96	4814	#define USB_COUNT3_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /!< Bit 1 /
Kojto	112:6f327212ef96	4815	#define USB_COUNT3_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /!< Bit 2 /
Kojto	112:6f327212ef96	4816	#define USB_COUNT3_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /!< Bit 3 /
Kojto	112:6f327212ef96	4817	#define USB_COUNT3_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /!< Bit 4 /
Kojto	112:6f327212ef96	4818
Kojto	112:6f327212ef96	4819	#define USB_COUNT3_RX_BLSIZE ((uint32_t)0x00008000) /!< BLock SIZE /
Kojto	112:6f327212ef96	4820
Kojto	112:6f327212ef96	4821	/*************** Bit definition for USB_COUNT4_RX register **************/
Kojto	112:6f327212ef96	4822	#define USB_COUNT4_RX_COUNT4_RX ((uint32_t)0x000003FF) /!< Reception Byte Count /
Kojto	112:6f327212ef96	4823
Kojto	112:6f327212ef96	4824	#define USB_COUNT4_RX_NUM_BLOCK ((uint32_t)0x00007C00) /!< NUM_BLOCK[4:0] bits (Number of blocks) /
Kojto	112:6f327212ef96	4825	#define USB_COUNT4_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /!< Bit 0 /
Kojto	112:6f327212ef96	4826	#define USB_COUNT4_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /!< Bit 1 /
Kojto	112:6f327212ef96	4827	#define USB_COUNT4_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /!< Bit 2 /
Kojto	112:6f327212ef96	4828	#define USB_COUNT4_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /!< Bit 3 /
Kojto	112:6f327212ef96	4829	#define USB_COUNT4_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /!< Bit 4 /
Kojto	112:6f327212ef96	4830
Kojto	112:6f327212ef96	4831	#define USB_COUNT4_RX_BLSIZE ((uint32_t)0x00008000) /!< BLock SIZE /
Kojto	112:6f327212ef96	4832
Kojto	112:6f327212ef96	4833	/*************** Bit definition for USB_COUNT5_RX register **************/
Kojto	112:6f327212ef96	4834	#define USB_COUNT5_RX_COUNT5_RX ((uint32_t)0x000003FF) /!< Reception Byte Count /
Kojto	112:6f327212ef96	4835
Kojto	112:6f327212ef96	4836	#define USB_COUNT5_RX_NUM_BLOCK ((uint32_t)0x00007C00) /!< NUM_BLOCK[4:0] bits (Number of blocks) /
Kojto	112:6f327212ef96	4837	#define USB_COUNT5_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /!< Bit 0 /
Kojto	112:6f327212ef96	4838	#define USB_COUNT5_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /!< Bit 1 /
Kojto	112:6f327212ef96	4839	#define USB_COUNT5_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /!< Bit 2 /
Kojto	112:6f327212ef96	4840	#define USB_COUNT5_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /!< Bit 3 /
Kojto	112:6f327212ef96	4841	#define USB_COUNT5_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /!< Bit 4 /
Kojto	112:6f327212ef96	4842
Kojto	112:6f327212ef96	4843	#define USB_COUNT5_RX_BLSIZE ((uint32_t)0x00008000) /!< BLock SIZE /
Kojto	112:6f327212ef96	4844
Kojto	112:6f327212ef96	4845	/*************** Bit definition for USB_COUNT6_RX register **************/
Kojto	112:6f327212ef96	4846	#define USB_COUNT6_RX_COUNT6_RX ((uint32_t)0x000003FF) /!< Reception Byte Count /
Kojto	112:6f327212ef96	4847
Kojto	112:6f327212ef96	4848	#define USB_COUNT6_RX_NUM_BLOCK ((uint32_t)0x00007C00) /!< NUM_BLOCK[4:0] bits (Number of blocks) /
Kojto	112:6f327212ef96	4849	#define USB_COUNT6_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /!< Bit 0 /
Kojto	112:6f327212ef96	4850	#define USB_COUNT6_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /!< Bit 1 /
Kojto	112:6f327212ef96	4851	#define USB_COUNT6_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /!< Bit 2 /
Kojto	112:6f327212ef96	4852	#define USB_COUNT6_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /!< Bit 3 /
Kojto	112:6f327212ef96	4853	#define USB_COUNT6_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /!< Bit 4 /
Kojto	112:6f327212ef96	4854
Kojto	112:6f327212ef96	4855	#define USB_COUNT6_RX_BLSIZE ((uint32_t)0x00008000) /!< BLock SIZE /
Kojto	112:6f327212ef96	4856
Kojto	112:6f327212ef96	4857	/*************** Bit definition for USB_COUNT7_RX register **************/
Kojto	112:6f327212ef96	4858	#define USB_COUNT7_RX_COUNT7_RX ((uint32_t)0x000003FF) /!< Reception Byte Count /
Kojto	112:6f327212ef96	4859
Kojto	112:6f327212ef96	4860	#define USB_COUNT7_RX_NUM_BLOCK ((uint32_t)0x00007C00) /!< NUM_BLOCK[4:0] bits (Number of blocks) /
Kojto	112:6f327212ef96	4861	#define USB_COUNT7_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /!< Bit 0 /
Kojto	112:6f327212ef96	4862	#define USB_COUNT7_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /!< Bit 1 /
Kojto	112:6f327212ef96	4863	#define USB_COUNT7_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /!< Bit 2 /
Kojto	112:6f327212ef96	4864	#define USB_COUNT7_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /!< Bit 3 /
Kojto	112:6f327212ef96	4865	#define USB_COUNT7_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /!< Bit 4 /
Kojto	112:6f327212ef96	4866
Kojto	112:6f327212ef96	4867	#define USB_COUNT7_RX_BLSIZE ((uint32_t)0x00008000) /!< BLock SIZE /
Kojto	112:6f327212ef96	4868
Kojto	112:6f327212ef96	4869	/----------------------------------------------------------------------------/
Kojto	112:6f327212ef96	4870
Kojto	112:6f327212ef96	4871	/************** Bit definition for USB_COUNT0_RX_0 register *************/
Kojto	112:6f327212ef96	4872	#define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) /!< Reception Byte Count (low) /
Kojto	112:6f327212ef96	4873
Kojto	112:6f327212ef96	4874	#define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
Kojto	112:6f327212ef96	4875	#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /!< Bit 0 /
Kojto	112:6f327212ef96	4876	#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /!< Bit 1 /
Kojto	112:6f327212ef96	4877	#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /!< Bit 2 /
Kojto	112:6f327212ef96	4878	#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /!< Bit 3 /
Kojto	112:6f327212ef96	4879	#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /!< Bit 4 /
Kojto	112:6f327212ef96	4880
Kojto	112:6f327212ef96	4881	#define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /!< BLock SIZE (low) /
Kojto	112:6f327212ef96	4882
Kojto	112:6f327212ef96	4883	/************** Bit definition for USB_COUNT0_RX_1 register *************/
Kojto	112:6f327212ef96	4884	#define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) /!< Reception Byte Count (high) /
Kojto	112:6f327212ef96	4885
Kojto	112:6f327212ef96	4886	#define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
Kojto	112:6f327212ef96	4887	#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /!< Bit 1 /
Kojto	112:6f327212ef96	4888	#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /!< Bit 1 /
Kojto	112:6f327212ef96	4889	#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /!< Bit 2 /
Kojto	112:6f327212ef96	4890	#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /!< Bit 3 /
Kojto	112:6f327212ef96	4891	#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /!< Bit 4 /
Kojto	112:6f327212ef96	4892
Kojto	112:6f327212ef96	4893	#define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /!< BLock SIZE (high) /
Kojto	112:6f327212ef96	4894
Kojto	112:6f327212ef96	4895	/************** Bit definition for USB_COUNT1_RX_0 register *************/
Kojto	112:6f327212ef96	4896	#define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) /!< Reception Byte Count (low) /
Kojto	112:6f327212ef96	4897
Kojto	112:6f327212ef96	4898	#define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
Kojto	112:6f327212ef96	4899	#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /!< Bit 0 /
Kojto	112:6f327212ef96	4900	#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /!< Bit 1 /
Kojto	112:6f327212ef96	4901	#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /!< Bit 2 /
Kojto	112:6f327212ef96	4902	#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /!< Bit 3 /
Kojto	112:6f327212ef96	4903	#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /!< Bit 4 /
Kojto	112:6f327212ef96	4904
Kojto	112:6f327212ef96	4905	#define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /!< BLock SIZE (low) /
Kojto	112:6f327212ef96	4906
Kojto	112:6f327212ef96	4907	/************** Bit definition for USB_COUNT1_RX_1 register *************/
Kojto	112:6f327212ef96	4908	#define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) /!< Reception Byte Count (high) /
Kojto	112:6f327212ef96	4909
Kojto	112:6f327212ef96	4910	#define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
Kojto	112:6f327212ef96	4911	#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /!< Bit 0 /
Kojto	112:6f327212ef96	4912	#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /!< Bit 1 /
Kojto	112:6f327212ef96	4913	#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /!< Bit 2 /
Kojto	112:6f327212ef96	4914	#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /!< Bit 3 /
Kojto	112:6f327212ef96	4915	#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /!< Bit 4 /
Kojto	112:6f327212ef96	4916
Kojto	112:6f327212ef96	4917	#define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /!< BLock SIZE (high) /
Kojto	112:6f327212ef96	4918
Kojto	112:6f327212ef96	4919	/************** Bit definition for USB_COUNT2_RX_0 register *************/
Kojto	112:6f327212ef96	4920	#define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) /!< Reception Byte Count (low) /
Kojto	112:6f327212ef96	4921
Kojto	112:6f327212ef96	4922	#define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
Kojto	112:6f327212ef96	4923	#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /!< Bit 0 /
Kojto	112:6f327212ef96	4924	#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /!< Bit 1 /
Kojto	112:6f327212ef96	4925	#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /!< Bit 2 /
Kojto	112:6f327212ef96	4926	#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /!< Bit 3 /
Kojto	112:6f327212ef96	4927	#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /!< Bit 4 /
Kojto	112:6f327212ef96	4928
Kojto	112:6f327212ef96	4929	#define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /!< BLock SIZE (low) /
Kojto	112:6f327212ef96	4930
Kojto	112:6f327212ef96	4931	/************** Bit definition for USB_COUNT2_RX_1 register *************/
Kojto	112:6f327212ef96	4932	#define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) /!< Reception Byte Count (high) /
Kojto	112:6f327212ef96	4933
Kojto	112:6f327212ef96	4934	#define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
Kojto	112:6f327212ef96	4935	#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /!< Bit 0 /
Kojto	112:6f327212ef96	4936	#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /!< Bit 1 /
Kojto	112:6f327212ef96	4937	#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /!< Bit 2 /
Kojto	112:6f327212ef96	4938	#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /!< Bit 3 /
Kojto	112:6f327212ef96	4939	#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /!< Bit 4 /
Kojto	112:6f327212ef96	4940
Kojto	112:6f327212ef96	4941	#define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /!< BLock SIZE (high) /
Kojto	112:6f327212ef96	4942
Kojto	112:6f327212ef96	4943	/************** Bit definition for USB_COUNT3_RX_0 register *************/
Kojto	112:6f327212ef96	4944	#define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) /!< Reception Byte Count (low) /
Kojto	112:6f327212ef96	4945
Kojto	112:6f327212ef96	4946	#define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
Kojto	112:6f327212ef96	4947	#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /!< Bit 0 /
Kojto	112:6f327212ef96	4948	#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /!< Bit 1 /
Kojto	112:6f327212ef96	4949	#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /!< Bit 2 /
Kojto	112:6f327212ef96	4950	#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /!< Bit 3 /
Kojto	112:6f327212ef96	4951	#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /!< Bit 4 /
Kojto	112:6f327212ef96	4952
Kojto	112:6f327212ef96	4953	#define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /!< BLock SIZE (low) /
Kojto	112:6f327212ef96	4954
Kojto	112:6f327212ef96	4955	/************** Bit definition for USB_COUNT3_RX_1 register *************/
Kojto	112:6f327212ef96	4956	#define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) /!< Reception Byte Count (high) /
Kojto	112:6f327212ef96	4957
Kojto	112:6f327212ef96	4958	#define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
Kojto	112:6f327212ef96	4959	#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /!< Bit 0 /
Kojto	112:6f327212ef96	4960	#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /!< Bit 1 /
Kojto	112:6f327212ef96	4961	#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /!< Bit 2 /
Kojto	112:6f327212ef96	4962	#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /!< Bit 3 /
Kojto	112:6f327212ef96	4963	#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /!< Bit 4 /
Kojto	112:6f327212ef96	4964
Kojto	112:6f327212ef96	4965	#define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /!< BLock SIZE (high) /
Kojto	112:6f327212ef96	4966
Kojto	112:6f327212ef96	4967	/************** Bit definition for USB_COUNT4_RX_0 register *************/
Kojto	112:6f327212ef96	4968	#define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) /!< Reception Byte Count (low) /
Kojto	112:6f327212ef96	4969
Kojto	112:6f327212ef96	4970	#define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
Kojto	112:6f327212ef96	4971	#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /!< Bit 0 /
Kojto	112:6f327212ef96	4972	#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /!< Bit 1 /
Kojto	112:6f327212ef96	4973	#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /!< Bit 2 /
Kojto	112:6f327212ef96	4974	#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /!< Bit 3 /
Kojto	112:6f327212ef96	4975	#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /!< Bit 4 /
Kojto	112:6f327212ef96	4976
Kojto	112:6f327212ef96	4977	#define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /!< BLock SIZE (low) /
Kojto	112:6f327212ef96	4978
Kojto	112:6f327212ef96	4979	/************** Bit definition for USB_COUNT4_RX_1 register *************/
Kojto	112:6f327212ef96	4980	#define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) /!< Reception Byte Count (high) /
Kojto	112:6f327212ef96	4981
Kojto	112:6f327212ef96	4982	#define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
Kojto	112:6f327212ef96	4983	#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /!< Bit 0 /
Kojto	112:6f327212ef96	4984	#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /!< Bit 1 /
Kojto	112:6f327212ef96	4985	#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /!< Bit 2 /
Kojto	112:6f327212ef96	4986	#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /!< Bit 3 /
Kojto	112:6f327212ef96	4987	#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /!< Bit 4 /
Kojto	112:6f327212ef96	4988
Kojto	112:6f327212ef96	4989	#define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /!< BLock SIZE (high) /
Kojto	112:6f327212ef96	4990
Kojto	112:6f327212ef96	4991	/************** Bit definition for USB_COUNT5_RX_0 register *************/
Kojto	112:6f327212ef96	4992	#define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) /!< Reception Byte Count (low) /
Kojto	112:6f327212ef96	4993
Kojto	112:6f327212ef96	4994	#define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
Kojto	112:6f327212ef96	4995	#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /!< Bit 0 /
Kojto	112:6f327212ef96	4996	#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /!< Bit 1 /
Kojto	112:6f327212ef96	4997	#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /!< Bit 2 /
Kojto	112:6f327212ef96	4998	#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /!< Bit 3 /
Kojto	112:6f327212ef96	4999	#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /!< Bit 4 /
Kojto	112:6f327212ef96	5000
Kojto	112:6f327212ef96	5001	#define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /!< BLock SIZE (low) /
Kojto	112:6f327212ef96	5002
Kojto	112:6f327212ef96	5003	/************** Bit definition for USB_COUNT5_RX_1 register *************/
Kojto	112:6f327212ef96	5004	#define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) /!< Reception Byte Count (high) /
Kojto	112:6f327212ef96	5005
Kojto	112:6f327212ef96	5006	#define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
Kojto	112:6f327212ef96	5007	#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /!< Bit 0 /
Kojto	112:6f327212ef96	5008	#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /!< Bit 1 /
Kojto	112:6f327212ef96	5009	#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /!< Bit 2 /
Kojto	112:6f327212ef96	5010	#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /!< Bit 3 /
Kojto	112:6f327212ef96	5011	#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /!< Bit 4 /
Kojto	112:6f327212ef96	5012
Kojto	112:6f327212ef96	5013	#define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /!< BLock SIZE (high) /
Kojto	112:6f327212ef96	5014
Kojto	112:6f327212ef96	5015	/************* Bit definition for USB_COUNT6_RX_0 register *************/
Kojto	112:6f327212ef96	5016	#define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) /!< Reception Byte Count (low) /
Kojto	112:6f327212ef96	5017
Kojto	112:6f327212ef96	5018	#define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
Kojto	112:6f327212ef96	5019	#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /!< Bit 0 /
Kojto	112:6f327212ef96	5020	#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /!< Bit 1 /
Kojto	112:6f327212ef96	5021	#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /!< Bit 2 /
Kojto	112:6f327212ef96	5022	#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /!< Bit 3 /
Kojto	112:6f327212ef96	5023	#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /!< Bit 4 /
Kojto	112:6f327212ef96	5024
Kojto	112:6f327212ef96	5025	#define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /!< BLock SIZE (low) /
Kojto	112:6f327212ef96	5026
Kojto	112:6f327212ef96	5027	/************** Bit definition for USB_COUNT6_RX_1 register *************/
Kojto	112:6f327212ef96	5028	#define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) /!< Reception Byte Count (high) /
Kojto	112:6f327212ef96	5029
Kojto	112:6f327212ef96	5030	#define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
Kojto	112:6f327212ef96	5031	#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /!< Bit 0 /
Kojto	112:6f327212ef96	5032	#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /!< Bit 1 /
Kojto	112:6f327212ef96	5033	#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /!< Bit 2 /
Kojto	112:6f327212ef96	5034	#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /!< Bit 3 /
Kojto	112:6f327212ef96	5035	#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /!< Bit 4 /
Kojto	112:6f327212ef96	5036
Kojto	112:6f327212ef96	5037	#define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /!< BLock SIZE (high) /
Kojto	112:6f327212ef96	5038
Kojto	112:6f327212ef96	5039	/************* Bit definition for USB_COUNT7_RX_0 register **************/
Kojto	112:6f327212ef96	5040	#define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) /!< Reception Byte Count (low) /
Kojto	112:6f327212ef96	5041
Kojto	112:6f327212ef96	5042	#define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
Kojto	112:6f327212ef96	5043	#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /!< Bit 0 /
Kojto	112:6f327212ef96	5044	#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /!< Bit 1 /
Kojto	112:6f327212ef96	5045	#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /!< Bit 2 /
Kojto	112:6f327212ef96	5046	#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /!< Bit 3 /
Kojto	112:6f327212ef96	5047	#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /!< Bit 4 /
Kojto	112:6f327212ef96	5048
Kojto	112:6f327212ef96	5049	#define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /!< BLock SIZE (low) /
Kojto	112:6f327212ef96	5050
Kojto	112:6f327212ef96	5051	/************* Bit definition for USB_COUNT7_RX_1 register **************/
Kojto	112:6f327212ef96	5052	#define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) /!< Reception Byte Count (high) /
Kojto	112:6f327212ef96	5053
Kojto	112:6f327212ef96	5054	#define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
Kojto	112:6f327212ef96	5055	#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /!< Bit 0 /
Kojto	112:6f327212ef96	5056	#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /!< Bit 1 /
Kojto	112:6f327212ef96	5057	#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /!< Bit 2 /
Kojto	112:6f327212ef96	5058	#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /!< Bit 3 /
Kojto	112:6f327212ef96	5059	#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /!< Bit 4 /
Kojto	112:6f327212ef96	5060
Kojto	112:6f327212ef96	5061	#define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /!< BLock SIZE (high) /
Kojto	112:6f327212ef96	5062
Kojto	112:6f327212ef96	5063	/******************************************************************************/
Kojto	112:6f327212ef96	5064	/* */
Kojto	112:6f327212ef96	5065	/* Window WATCHDOG (WWDG) */
Kojto	112:6f327212ef96	5066	/* */
Kojto	112:6f327212ef96	5067	/******************************************************************************/
Kojto	112:6f327212ef96	5068
Kojto	112:6f327212ef96	5069	/***************** Bit definition for WWDG_CR register ******************/
Kojto	112:6f327212ef96	5070	#define WWDG_CR_T ((uint32_t)0x0000007F) /!< T[6:0] bits (7-Bit counter (MSB to LSB)) /
Kojto	112:6f327212ef96	5071	#define WWDG_CR_T0 ((uint32_t)0x00000001) /!< Bit 0 /
Kojto	112:6f327212ef96	5072	#define WWDG_CR_T1 ((uint32_t)0x00000002) /!< Bit 1 /
Kojto	112:6f327212ef96	5073	#define WWDG_CR_T2 ((uint32_t)0x00000004) /!< Bit 2 /
Kojto	112:6f327212ef96	5074	#define WWDG_CR_T3 ((uint32_t)0x00000008) /!< Bit 3 /
Kojto	112:6f327212ef96	5075	#define WWDG_CR_T4 ((uint32_t)0x00000010) /!< Bit 4 /
Kojto	112:6f327212ef96	5076	#define WWDG_CR_T5 ((uint32_t)0x00000020) /!< Bit 5 /
Kojto	112:6f327212ef96	5077	#define WWDG_CR_T6 ((uint32_t)0x00000040) /!< Bit 6 /
Kojto	112:6f327212ef96	5078
Kojto	112:6f327212ef96	5079	#define WWDG_CR_WDGA ((uint32_t)0x00000080) /!< Activation bit /
Kojto	112:6f327212ef96	5080
Kojto	112:6f327212ef96	5081	/***************** Bit definition for WWDG_CFR register *****************/
Kojto	112:6f327212ef96	5082	#define WWDG_CFR_W ((uint32_t)0x0000007F) /!< W[6:0] bits (7-bit window value) /
Kojto	112:6f327212ef96	5083	#define WWDG_CFR_W0 ((uint32_t)0x00000001) /!< Bit 0 /
Kojto	112:6f327212ef96	5084	#define WWDG_CFR_W1 ((uint32_t)0x00000002) /!< Bit 1 /
Kojto	112:6f327212ef96	5085	#define WWDG_CFR_W2 ((uint32_t)0x00000004) /!< Bit 2 /
Kojto	112:6f327212ef96	5086	#define WWDG_CFR_W3 ((uint32_t)0x00000008) /!< Bit 3 /
Kojto	112:6f327212ef96	5087	#define WWDG_CFR_W4 ((uint32_t)0x00000010) /!< Bit 4 /
Kojto	112:6f327212ef96	5088	#define WWDG_CFR_W5 ((uint32_t)0x00000020) /!< Bit 5 /
Kojto	112:6f327212ef96	5089	#define WWDG_CFR_W6 ((uint32_t)0x00000040) /!< Bit 6 /
Kojto	112:6f327212ef96	5090
Kojto	112:6f327212ef96	5091	#define WWDG_CFR_WDGTB ((uint32_t)0x00000180) /!< WDGTB[1:0] bits (Timer Base) /
Kojto	112:6f327212ef96	5092	#define WWDG_CFR_WDGTB0 ((uint32_t)0x00000080) /!< Bit 0 /
Kojto	112:6f327212ef96	5093	#define WWDG_CFR_WDGTB1 ((uint32_t)0x00000100) /!< Bit 1 /
Kojto	112:6f327212ef96	5094
Kojto	112:6f327212ef96	5095	#define WWDG_CFR_EWI ((uint32_t)0x00000200) /!< Early Wakeup Interrupt /
Kojto	112:6f327212ef96	5096
Kojto	112:6f327212ef96	5097	/***************** Bit definition for WWDG_SR register ******************/
Kojto	112:6f327212ef96	5098	#define WWDG_SR_EWIF ((uint32_t)0x00000001) /!< Early Wakeup Interrupt Flag /
Kojto	112:6f327212ef96	5099
Kojto	112:6f327212ef96	5100	/******************************************************************************/
Kojto	112:6f327212ef96	5101	/* */
Kojto	112:6f327212ef96	5102	/* SystemTick (SysTick) */
Kojto	112:6f327212ef96	5103	/* */
Kojto	112:6f327212ef96	5104	/******************************************************************************/
Kojto	112:6f327212ef96	5105
Kojto	112:6f327212ef96	5106	/*************** Bit definition for SysTick_CTRL register ***************/
Kojto	112:6f327212ef96	5107	#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /!< Counter enable /
Kojto	112:6f327212ef96	5108	#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /!< Counting down to 0 pends the SysTick handler /
Kojto	112:6f327212ef96	5109	#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /!< Clock source /
Kojto	112:6f327212ef96	5110	#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /!< Count Flag /
Kojto	112:6f327212ef96	5111
Kojto	112:6f327212ef96	5112	/*************** Bit definition for SysTick_LOAD register ***************/
Kojto	112:6f327212ef96	5113	#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /!< Value to load into the SysTick Current Value Register when the counter reaches 0 /
Kojto	112:6f327212ef96	5114
Kojto	112:6f327212ef96	5115	/*************** Bit definition for SysTick_VAL register ****************/
Kojto	112:6f327212ef96	5116	#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /!< Current value at the time the register is accessed /
Kojto	112:6f327212ef96	5117
Kojto	112:6f327212ef96	5118	/*************** Bit definition for SysTick_CALIB register **************/
Kojto	112:6f327212ef96	5119	#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /!< Reload value to use for 10ms timing /
Kojto	112:6f327212ef96	5120	#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /!< Calibration value is not exactly 10 ms /
Kojto	112:6f327212ef96	5121	#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /!< The reference clock is not provided /
Kojto	112:6f327212ef96	5122
Kojto	112:6f327212ef96	5123	/******************************************************************************/
Kojto	112:6f327212ef96	5124	/* */
Kojto	112:6f327212ef96	5125	/* Nested Vectored Interrupt Controller (NVIC) */
Kojto	112:6f327212ef96	5126	/* */
Kojto	112:6f327212ef96	5127	/******************************************************************************/
Kojto	112:6f327212ef96	5128
Kojto	112:6f327212ef96	5129	/**************** Bit definition for NVIC_ISER register *****************/
Kojto	112:6f327212ef96	5130	#define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /!< Interrupt set enable bits /
Kojto	112:6f327212ef96	5131	#define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /!< bit 0 /
Kojto	112:6f327212ef96	5132	#define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /!< bit 1 /
Kojto	112:6f327212ef96	5133	#define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /!< bit 2 /
Kojto	112:6f327212ef96	5134	#define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /!< bit 3 /
Kojto	112:6f327212ef96	5135	#define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /!< bit 4 /
Kojto	112:6f327212ef96	5136	#define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /!< bit 5 /
Kojto	112:6f327212ef96	5137	#define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /!< bit 6 /
Kojto	112:6f327212ef96	5138	#define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /!< bit 7 /
Kojto	112:6f327212ef96	5139	#define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /!< bit 8 /
Kojto	112:6f327212ef96	5140	#define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /!< bit 9 /
Kojto	112:6f327212ef96	5141	#define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /!< bit 10 /
Kojto	112:6f327212ef96	5142	#define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /!< bit 11 /
Kojto	112:6f327212ef96	5143	#define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /!< bit 12 /
Kojto	112:6f327212ef96	5144	#define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /!< bit 13 /
Kojto	112:6f327212ef96	5145	#define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /!< bit 14 /
Kojto	112:6f327212ef96	5146	#define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /!< bit 15 /
Kojto	112:6f327212ef96	5147	#define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /!< bit 16 /
Kojto	112:6f327212ef96	5148	#define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /!< bit 17 /
Kojto	112:6f327212ef96	5149	#define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /!< bit 18 /
Kojto	112:6f327212ef96	5150	#define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /!< bit 19 /
Kojto	112:6f327212ef96	5151	#define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /!< bit 20 /
Kojto	112:6f327212ef96	5152	#define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /!< bit 21 /
Kojto	112:6f327212ef96	5153	#define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /!< bit 22 /
Kojto	112:6f327212ef96	5154	#define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /!< bit 23 /
Kojto	112:6f327212ef96	5155	#define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /!< bit 24 /
Kojto	112:6f327212ef96	5156	#define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /!< bit 25 /
Kojto	112:6f327212ef96	5157	#define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /!< bit 26 /
Kojto	112:6f327212ef96	5158	#define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /!< bit 27 /
Kojto	112:6f327212ef96	5159	#define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /!< bit 28 /
Kojto	112:6f327212ef96	5160	#define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /!< bit 29 /
Kojto	112:6f327212ef96	5161	#define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /!< bit 30 /
Kojto	112:6f327212ef96	5162	#define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /!< bit 31 /
Kojto	112:6f327212ef96	5163
Kojto	112:6f327212ef96	5164	/**************** Bit definition for NVIC_ICER register *****************/
Kojto	112:6f327212ef96	5165	#define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /!< Interrupt clear-enable bits /
Kojto	112:6f327212ef96	5166	#define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /!< bit 0 /
Kojto	112:6f327212ef96	5167	#define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /!< bit 1 /
Kojto	112:6f327212ef96	5168	#define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /!< bit 2 /
Kojto	112:6f327212ef96	5169	#define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /!< bit 3 /
Kojto	112:6f327212ef96	5170	#define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /!< bit 4 /
Kojto	112:6f327212ef96	5171	#define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /!< bit 5 /
Kojto	112:6f327212ef96	5172	#define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /!< bit 6 /
Kojto	112:6f327212ef96	5173	#define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /!< bit 7 /
Kojto	112:6f327212ef96	5174	#define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /!< bit 8 /
Kojto	112:6f327212ef96	5175	#define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /!< bit 9 /
Kojto	112:6f327212ef96	5176	#define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /!< bit 10 /
Kojto	112:6f327212ef96	5177	#define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /!< bit 11 /
Kojto	112:6f327212ef96	5178	#define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /!< bit 12 /
Kojto	112:6f327212ef96	5179	#define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /!< bit 13 /
Kojto	112:6f327212ef96	5180	#define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /!< bit 14 /
Kojto	112:6f327212ef96	5181	#define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /!< bit 15 /
Kojto	112:6f327212ef96	5182	#define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /!< bit 16 /
Kojto	112:6f327212ef96	5183	#define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /!< bit 17 /
Kojto	112:6f327212ef96	5184	#define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /!< bit 18 /
Kojto	112:6f327212ef96	5185	#define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /!< bit 19 /
Kojto	112:6f327212ef96	5186	#define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /!< bit 20 /
Kojto	112:6f327212ef96	5187	#define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /!< bit 21 /
Kojto	112:6f327212ef96	5188	#define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /!< bit 22 /
Kojto	112:6f327212ef96	5189	#define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /!< bit 23 /
Kojto	112:6f327212ef96	5190	#define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /!< bit 24 /
Kojto	112:6f327212ef96	5191	#define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /!< bit 25 /
Kojto	112:6f327212ef96	5192	#define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /!< bit 26 /
Kojto	112:6f327212ef96	5193	#define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /!< bit 27 /
Kojto	112:6f327212ef96	5194	#define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /!< bit 28 /
Kojto	112:6f327212ef96	5195	#define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /!< bit 29 /
Kojto	112:6f327212ef96	5196	#define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /!< bit 30 /
Kojto	112:6f327212ef96	5197	#define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /!< bit 31 /
Kojto	112:6f327212ef96	5198
Kojto	112:6f327212ef96	5199	/**************** Bit definition for NVIC_ISPR register *****************/
Kojto	112:6f327212ef96	5200	#define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /!< Interrupt set-pending bits /
Kojto	112:6f327212ef96	5201	#define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /!< bit 0 /
Kojto	112:6f327212ef96	5202	#define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /!< bit 1 /
Kojto	112:6f327212ef96	5203	#define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /!< bit 2 /
Kojto	112:6f327212ef96	5204	#define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /!< bit 3 /
Kojto	112:6f327212ef96	5205	#define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /!< bit 4 /
Kojto	112:6f327212ef96	5206	#define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /!< bit 5 /
Kojto	112:6f327212ef96	5207	#define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /!< bit 6 /
Kojto	112:6f327212ef96	5208	#define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /!< bit 7 /
Kojto	112:6f327212ef96	5209	#define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /!< bit 8 /
Kojto	112:6f327212ef96	5210	#define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /!< bit 9 /
Kojto	112:6f327212ef96	5211	#define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /!< bit 10 /
Kojto	112:6f327212ef96	5212	#define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /!< bit 11 /
Kojto	112:6f327212ef96	5213	#define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /!< bit 12 /
Kojto	112:6f327212ef96	5214	#define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /!< bit 13 /
Kojto	112:6f327212ef96	5215	#define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /!< bit 14 /
Kojto	112:6f327212ef96	5216	#define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /!< bit 15 /
Kojto	112:6f327212ef96	5217	#define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /!< bit 16 /
Kojto	112:6f327212ef96	5218	#define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /!< bit 17 /
Kojto	112:6f327212ef96	5219	#define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /!< bit 18 /
Kojto	112:6f327212ef96	5220	#define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /!< bit 19 /
Kojto	112:6f327212ef96	5221	#define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /!< bit 20 /
Kojto	112:6f327212ef96	5222	#define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /!< bit 21 /
Kojto	112:6f327212ef96	5223	#define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /!< bit 22 /
Kojto	112:6f327212ef96	5224	#define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /!< bit 23 /
Kojto	112:6f327212ef96	5225	#define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /!< bit 24 /
Kojto	112:6f327212ef96	5226	#define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /!< bit 25 /
Kojto	112:6f327212ef96	5227	#define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /!< bit 26 /
Kojto	112:6f327212ef96	5228	#define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /!< bit 27 /
Kojto	112:6f327212ef96	5229	#define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /!< bit 28 /
Kojto	112:6f327212ef96	5230	#define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /!< bit 29 /
Kojto	112:6f327212ef96	5231	#define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /!< bit 30 /
Kojto	112:6f327212ef96	5232	#define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /!< bit 31 /
Kojto	112:6f327212ef96	5233
Kojto	112:6f327212ef96	5234	/**************** Bit definition for NVIC_ICPR register *****************/
Kojto	112:6f327212ef96	5235	#define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /!< Interrupt clear-pending bits /
Kojto	112:6f327212ef96	5236	#define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /!< bit 0 /
Kojto	112:6f327212ef96	5237	#define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /!< bit 1 /
Kojto	112:6f327212ef96	5238	#define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /!< bit 2 /
Kojto	112:6f327212ef96	5239	#define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /!< bit 3 /
Kojto	112:6f327212ef96	5240	#define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /!< bit 4 /
Kojto	112:6f327212ef96	5241	#define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /!< bit 5 /
Kojto	112:6f327212ef96	5242	#define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /!< bit 6 /
Kojto	112:6f327212ef96	5243	#define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /!< bit 7 /
Kojto	112:6f327212ef96	5244	#define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /!< bit 8 /
Kojto	112:6f327212ef96	5245	#define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /!< bit 9 /
Kojto	112:6f327212ef96	5246	#define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /!< bit 10 /
Kojto	112:6f327212ef96	5247	#define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /!< bit 11 /
Kojto	112:6f327212ef96	5248	#define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /!< bit 12 /
Kojto	112:6f327212ef96	5249	#define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /!< bit 13 /
Kojto	112:6f327212ef96	5250	#define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /!< bit 14 /
Kojto	112:6f327212ef96	5251	#define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /!< bit 15 /
Kojto	112:6f327212ef96	5252	#define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /!< bit 16 /
Kojto	112:6f327212ef96	5253	#define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /!< bit 17 /
Kojto	112:6f327212ef96	5254	#define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /!< bit 18 /
Kojto	112:6f327212ef96	5255	#define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /!< bit 19 /
Kojto	112:6f327212ef96	5256	#define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /!< bit 20 /
Kojto	112:6f327212ef96	5257	#define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /!< bit 21 /
Kojto	112:6f327212ef96	5258	#define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /!< bit 22 /
Kojto	112:6f327212ef96	5259	#define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /!< bit 23 /
Kojto	112:6f327212ef96	5260	#define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /!< bit 24 /
Kojto	112:6f327212ef96	5261	#define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /!< bit 25 /
Kojto	112:6f327212ef96	5262	#define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /!< bit 26 /
Kojto	112:6f327212ef96	5263	#define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /!< bit 27 /
Kojto	112:6f327212ef96	5264	#define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /!< bit 28 /
Kojto	112:6f327212ef96	5265	#define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /!< bit 29 /
Kojto	112:6f327212ef96	5266	#define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /!< bit 30 /
Kojto	112:6f327212ef96	5267	#define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /!< bit 31 /
Kojto	112:6f327212ef96	5268
Kojto	112:6f327212ef96	5269	/**************** Bit definition for NVIC_IABR register *****************/
Kojto	112:6f327212ef96	5270	#define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /!< Interrupt active flags /
Kojto	112:6f327212ef96	5271	#define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /!< bit 0 /
Kojto	112:6f327212ef96	5272	#define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /!< bit 1 /
Kojto	112:6f327212ef96	5273	#define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /!< bit 2 /
Kojto	112:6f327212ef96	5274	#define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /!< bit 3 /
Kojto	112:6f327212ef96	5275	#define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /!< bit 4 /
Kojto	112:6f327212ef96	5276	#define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /!< bit 5 /
Kojto	112:6f327212ef96	5277	#define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /!< bit 6 /
Kojto	112:6f327212ef96	5278	#define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /!< bit 7 /
Kojto	112:6f327212ef96	5279	#define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /!< bit 8 /
Kojto	112:6f327212ef96	5280	#define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /!< bit 9 /
Kojto	112:6f327212ef96	5281	#define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /!< bit 10 /
Kojto	112:6f327212ef96	5282	#define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /!< bit 11 /
Kojto	112:6f327212ef96	5283	#define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /!< bit 12 /
Kojto	112:6f327212ef96	5284	#define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /!< bit 13 /
Kojto	112:6f327212ef96	5285	#define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /!< bit 14 /
Kojto	112:6f327212ef96	5286	#define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /!< bit 15 /
Kojto	112:6f327212ef96	5287	#define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /!< bit 16 /
Kojto	112:6f327212ef96	5288	#define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /!< bit 17 /
Kojto	112:6f327212ef96	5289	#define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /!< bit 18 /
Kojto	112:6f327212ef96	5290	#define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /!< bit 19 /
Kojto	112:6f327212ef96	5291	#define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /!< bit 20 /
Kojto	112:6f327212ef96	5292	#define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /!< bit 21 /
Kojto	112:6f327212ef96	5293	#define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /!< bit 22 /
Kojto	112:6f327212ef96	5294	#define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /!< bit 23 /
Kojto	112:6f327212ef96	5295	#define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /!< bit 24 /
Kojto	112:6f327212ef96	5296	#define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /!< bit 25 /
Kojto	112:6f327212ef96	5297	#define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /!< bit 26 /
Kojto	112:6f327212ef96	5298	#define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /!< bit 27 /
Kojto	112:6f327212ef96	5299	#define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /!< bit 28 /
Kojto	112:6f327212ef96	5300	#define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /!< bit 29 /
Kojto	112:6f327212ef96	5301	#define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /!< bit 30 /
Kojto	112:6f327212ef96	5302	#define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /!< bit 31 /
Kojto	112:6f327212ef96	5303
Kojto	112:6f327212ef96	5304	/**************** Bit definition for NVIC_PRI0 register *****************/
Kojto	112:6f327212ef96	5305	#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /!< Priority of interrupt 0 /
Kojto	112:6f327212ef96	5306	#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /!< Priority of interrupt 1 /
Kojto	112:6f327212ef96	5307	#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /!< Priority of interrupt 2 /
Kojto	112:6f327212ef96	5308	#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /!< Priority of interrupt 3 /
Kojto	112:6f327212ef96	5309
Kojto	112:6f327212ef96	5310	/**************** Bit definition for NVIC_PRI1 register *****************/
Kojto	112:6f327212ef96	5311	#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /!< Priority of interrupt 4 /
Kojto	112:6f327212ef96	5312	#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /!< Priority of interrupt 5 /
Kojto	112:6f327212ef96	5313	#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /!< Priority of interrupt 6 /
Kojto	112:6f327212ef96	5314	#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /!< Priority of interrupt 7 /
Kojto	112:6f327212ef96	5315
Kojto	112:6f327212ef96	5316	/**************** Bit definition for NVIC_PRI2 register *****************/
Kojto	112:6f327212ef96	5317	#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /!< Priority of interrupt 8 /
Kojto	112:6f327212ef96	5318	#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /!< Priority of interrupt 9 /
Kojto	112:6f327212ef96	5319	#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /!< Priority of interrupt 10 /
Kojto	112:6f327212ef96	5320	#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /!< Priority of interrupt 11 /
Kojto	112:6f327212ef96	5321
Kojto	112:6f327212ef96	5322	/**************** Bit definition for NVIC_PRI3 register *****************/
Kojto	112:6f327212ef96	5323	#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /!< Priority of interrupt 12 /
Kojto	112:6f327212ef96	5324	#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /!< Priority of interrupt 13 /
Kojto	112:6f327212ef96	5325	#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /!< Priority of interrupt 14 /
Kojto	112:6f327212ef96	5326	#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /!< Priority of interrupt 15 /
Kojto	112:6f327212ef96	5327
Kojto	112:6f327212ef96	5328	/**************** Bit definition for NVIC_PRI4 register *****************/
Kojto	112:6f327212ef96	5329	#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /!< Priority of interrupt 16 /
Kojto	112:6f327212ef96	5330	#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /!< Priority of interrupt 17 /
Kojto	112:6f327212ef96	5331	#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /!< Priority of interrupt 18 /
Kojto	112:6f327212ef96	5332	#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /!< Priority of interrupt 19 /
Kojto	112:6f327212ef96	5333
Kojto	112:6f327212ef96	5334	/**************** Bit definition for NVIC_PRI5 register *****************/
Kojto	112:6f327212ef96	5335	#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /!< Priority of interrupt 20 /
Kojto	112:6f327212ef96	5336	#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /!< Priority of interrupt 21 /
Kojto	112:6f327212ef96	5337	#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /!< Priority of interrupt 22 /
Kojto	112:6f327212ef96	5338	#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /!< Priority of interrupt 23 /
Kojto	112:6f327212ef96	5339
Kojto	112:6f327212ef96	5340	/**************** Bit definition for NVIC_PRI6 register *****************/
Kojto	112:6f327212ef96	5341	#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /!< Priority of interrupt 24 /
Kojto	112:6f327212ef96	5342	#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /!< Priority of interrupt 25 /
Kojto	112:6f327212ef96	5343	#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /!< Priority of interrupt 26 /
Kojto	112:6f327212ef96	5344	#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /!< Priority of interrupt 27 /
Kojto	112:6f327212ef96	5345
Kojto	112:6f327212ef96	5346	/**************** Bit definition for NVIC_PRI7 register *****************/
Kojto	112:6f327212ef96	5347	#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /!< Priority of interrupt 28 /
Kojto	112:6f327212ef96	5348	#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /!< Priority of interrupt 29 /
Kojto	112:6f327212ef96	5349	#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /!< Priority of interrupt 30 /
Kojto	112:6f327212ef96	5350	#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /!< Priority of interrupt 31 /
Kojto	112:6f327212ef96	5351
Kojto	112:6f327212ef96	5352	/**************** Bit definition for SCB_CPUID register *****************/
Kojto	112:6f327212ef96	5353	#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /!< Implementation defined revision number /
Kojto	112:6f327212ef96	5354	#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /!< Number of processor within family /
Kojto	112:6f327212ef96	5355	#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /!< Reads as 0x0F /
Kojto	112:6f327212ef96	5356	#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /!< Implementation defined variant number /
Kojto	112:6f327212ef96	5357	#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /!< Implementer code. ARM is 0x41 /
Kojto	112:6f327212ef96	5358
Kojto	112:6f327212ef96	5359	/***************** Bit definition for SCB_ICSR register *****************/
Kojto	112:6f327212ef96	5360	#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /!< Active ISR number field /
Kojto	112:6f327212ef96	5361	#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /!< All active exceptions minus the IPSR_current_exception yields the empty set /
Kojto	112:6f327212ef96	5362	#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /!< Pending ISR number field /
Kojto	112:6f327212ef96	5363	#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /!< Interrupt pending flag /
Kojto	112:6f327212ef96	5364	#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /!< It indicates that a pending interrupt becomes active in the next running cycle /
Kojto	112:6f327212ef96	5365	#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /!< Clear pending SysTick bit /
Kojto	112:6f327212ef96	5366	#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /!< Set pending SysTick bit /
Kojto	112:6f327212ef96	5367	#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /!< Clear pending pendSV bit /
Kojto	112:6f327212ef96	5368	#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /!< Set pending pendSV bit /
Kojto	112:6f327212ef96	5369	#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /!< Set pending NMI bit /
Kojto	112:6f327212ef96	5370
Kojto	112:6f327212ef96	5371	/***************** Bit definition for SCB_VTOR register *****************/
Kojto	112:6f327212ef96	5372	#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /!< Vector table base offset field /
Kojto	112:6f327212ef96	5373	#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /!< Table base in code(0) or RAM(1) /
Kojto	112:6f327212ef96	5374
Kojto	112:6f327212ef96	5375	/!<************** Bit definition for SCB_AIRCR register *****************/
Kojto	112:6f327212ef96	5376	#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /!< System Reset bit /
Kojto	112:6f327212ef96	5377	#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /!< Clear active vector bit /
Kojto	112:6f327212ef96	5378	#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /!< Requests chip control logic to generate a reset /
Kojto	112:6f327212ef96	5379
Kojto	112:6f327212ef96	5380	#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /!< PRIGROUP[2:0] bits (Priority group) /
Kojto	112:6f327212ef96	5381	#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /!< Bit 0 /
Kojto	112:6f327212ef96	5382	#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /!< Bit 1 /
Kojto	112:6f327212ef96	5383	#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /!< Bit 2 /
Kojto	112:6f327212ef96	5384
Kojto	112:6f327212ef96	5385	/* prority group configuration */
Kojto	112:6f327212ef96	5386	#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) /
Kojto	112:6f327212ef96	5387	#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) /
Kojto	112:6f327212ef96	5388	#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) /
Kojto	112:6f327212ef96	5389	#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) /
Kojto	112:6f327212ef96	5390	#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) /
Kojto	112:6f327212ef96	5391	#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) /
Kojto	112:6f327212ef96	5392	#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) /
Kojto	112:6f327212ef96	5393	#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) /
Kojto	112:6f327212ef96	5394
Kojto	112:6f327212ef96	5395	#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /!< Data endianness bit /
Kojto	112:6f327212ef96	5396	#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) /
Kojto	112:6f327212ef96	5397
Kojto	112:6f327212ef96	5398	/***************** Bit definition for SCB_SCR register ******************/
Kojto	112:6f327212ef96	5399	#define SCB_SCR_SLEEPONEXIT ((uint32_t)0x00000002) /!< Sleep on exit bit /
Kojto	112:6f327212ef96	5400	#define SCB_SCR_SLEEPDEEP ((uint32_t)0x00000004) /!< Sleep deep bit /
Kojto	112:6f327212ef96	5401	#define SCB_SCR_SEVONPEND ((uint32_t)0x00000010) /!< Wake up from WFE /
Kojto	112:6f327212ef96	5402
Kojto	112:6f327212ef96	5403	/****************** Bit definition for SCB_CCR register *****************/
Kojto	112:6f327212ef96	5404	#define SCB_CCR_NONBASETHRDENA ((uint32_t)0x00000001) /!< Thread mode can be entered from any level in Handler mode by controlled return value /
Kojto	112:6f327212ef96	5405	#define SCB_CCR_USERSETMPEND ((uint32_t)0x00000002) /!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception /
Kojto	112:6f327212ef96	5406	#define SCB_CCR_UNALIGN_TRP ((uint32_t)0x00000008) /!< Trap for unaligned access /
Kojto	112:6f327212ef96	5407	#define SCB_CCR_DIV_0_TRP ((uint32_t)0x00000010) /!< Trap on Divide by 0 /
Kojto	112:6f327212ef96	5408	#define SCB_CCR_BFHFNMIGN ((uint32_t)0x00000100) /!< Handlers running at priority -1 and -2 /
Kojto	112:6f327212ef96	5409	#define SCB_CCR_STKALIGN ((uint32_t)0x00000200) /!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned /
Kojto	112:6f327212ef96	5410
Kojto	112:6f327212ef96	5411	/***************** Bit definition for SCB_SHPR register ******************/
Kojto	112:6f327212ef96	5412	#define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) /!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor /
Kojto	112:6f327212ef96	5413	#define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) /!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved /
Kojto	112:6f327212ef96	5414	#define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) /!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV /
Kojto	112:6f327212ef96	5415	#define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) /!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick /
Kojto	112:6f327212ef96	5416
Kojto	112:6f327212ef96	5417	/**************** Bit definition for SCB_SHCSR register *****************/
Kojto	112:6f327212ef96	5418	#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /!< MemManage is active /
Kojto	112:6f327212ef96	5419	#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /!< BusFault is active /
Kojto	112:6f327212ef96	5420	#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /!< UsageFault is active /
Kojto	112:6f327212ef96	5421	#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /!< SVCall is active /
Kojto	112:6f327212ef96	5422	#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /!< Monitor is active /
Kojto	112:6f327212ef96	5423	#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /!< PendSV is active /
Kojto	112:6f327212ef96	5424	#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /!< SysTick is active /
Kojto	112:6f327212ef96	5425	#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /!< Usage Fault is pended /
Kojto	112:6f327212ef96	5426	#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /!< MemManage is pended /
Kojto	112:6f327212ef96	5427	#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /!< Bus Fault is pended /
Kojto	112:6f327212ef96	5428	#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /!< SVCall is pended /
Kojto	112:6f327212ef96	5429	#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /!< MemManage enable /
Kojto	112:6f327212ef96	5430	#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /!< Bus Fault enable /
Kojto	112:6f327212ef96	5431	#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /!< UsageFault enable /
Kojto	112:6f327212ef96	5432
Kojto	112:6f327212ef96	5433	/***************** Bit definition for SCB_CFSR register *****************/
Kojto	112:6f327212ef96	5434	/!< MFSR /
Kojto	112:6f327212ef96	5435	#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /!< Instruction access violation /
Kojto	112:6f327212ef96	5436	#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /!< Data access violation /
Kojto	112:6f327212ef96	5437	#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /!< Unstacking error /
Kojto	112:6f327212ef96	5438	#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /!< Stacking error /
Kojto	112:6f327212ef96	5439	#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /!< Memory Manage Address Register address valid flag /
Kojto	112:6f327212ef96	5440	/!< BFSR /
Kojto	112:6f327212ef96	5441	#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /!< Instruction bus error flag /
Kojto	112:6f327212ef96	5442	#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /!< Precise data bus error /
Kojto	112:6f327212ef96	5443	#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /!< Imprecise data bus error /
Kojto	112:6f327212ef96	5444	#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /!< Unstacking error /
Kojto	112:6f327212ef96	5445	#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /!< Stacking error /
Kojto	112:6f327212ef96	5446	#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /!< Bus Fault Address Register address valid flag /
Kojto	112:6f327212ef96	5447	/!< UFSR /
Kojto	112:6f327212ef96	5448	#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /!< The processor attempt to excecute an undefined instruction /
Kojto	112:6f327212ef96	5449	#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /!< Invalid combination of EPSR and instruction /
Kojto	112:6f327212ef96	5450	#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /!< Attempt to load EXC_RETURN into pc illegally /
Kojto	112:6f327212ef96	5451	#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /!< Attempt to use a coprocessor instruction /
Kojto	112:6f327212ef96	5452	#define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /!< Fault occurs when there is an attempt to make an unaligned memory access /
Kojto	112:6f327212ef96	5453	#define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 /
Kojto	112:6f327212ef96	5454
Kojto	112:6f327212ef96	5455	/***************** Bit definition for SCB_HFSR register *****************/
Kojto	112:6f327212ef96	5456	#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /!< Fault occures because of vector table read on exception processing /
Kojto	112:6f327212ef96	5457	#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /!< Hard Fault activated when a configurable Fault was received and cannot activate /
Kojto	112:6f327212ef96	5458	#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /!< Fault related to debug /
Kojto	112:6f327212ef96	5459
Kojto	112:6f327212ef96	5460	/***************** Bit definition for SCB_DFSR register *****************/
Kojto	112:6f327212ef96	5461	#define SCB_DFSR_HALTED ((uint32_t)0x00000001) /!< Halt request flag /
Kojto	112:6f327212ef96	5462	#define SCB_DFSR_BKPT ((uint32_t)0x00000002) /!< BKPT flag /
Kojto	112:6f327212ef96	5463	#define SCB_DFSR_DWTTRAP ((uint32_t)0x00000004) /!< Data Watchpoint and Trace (DWT) flag /
Kojto	112:6f327212ef96	5464	#define SCB_DFSR_VCATCH ((uint32_t)0x00000008) /!< Vector catch flag /
Kojto	112:6f327212ef96	5465	#define SCB_DFSR_EXTERNAL ((uint32_t)0x00000010) /!< External debug request flag /
Kojto	112:6f327212ef96	5466
Kojto	112:6f327212ef96	5467	/***************** Bit definition for SCB_MMFAR register ****************/
Kojto	112:6f327212ef96	5468	#define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /!< Mem Manage fault address field /
Kojto	112:6f327212ef96	5469
Kojto	112:6f327212ef96	5470	/***************** Bit definition for SCB_BFAR register *****************/
Kojto	112:6f327212ef96	5471	#define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /!< Bus fault address field /
Kojto	112:6f327212ef96	5472
Kojto	112:6f327212ef96	5473	/***************** Bit definition for SCB_afsr register *****************/
Kojto	112:6f327212ef96	5474	#define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /!< Implementation defined /
Kojto	112:6f327212ef96	5475	/**
Kojto	112:6f327212ef96	5476	* @}
Kojto	112:6f327212ef96	5477	*/
Kojto	112:6f327212ef96	5478
Kojto	112:6f327212ef96	5479	/**
Kojto	112:6f327212ef96	5480	* @}
Kojto	112:6f327212ef96	5481	*/
Kojto	112:6f327212ef96	5482	/** @addtogroup Exported_macro
Kojto	112:6f327212ef96	5483	* @{
Kojto	112:6f327212ef96	5484	*/
Kojto	112:6f327212ef96	5485
Kojto	112:6f327212ef96	5486	/**************************** ADC Instances *******************************/
Kojto	112:6f327212ef96	5487	#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
Kojto	112:6f327212ef96	5488
Kojto	112:6f327212ef96	5489	/****************************** COMP Instances ****************************/
Kojto	112:6f327212ef96	5490	#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) \|\| \
Kojto	112:6f327212ef96	5491	((INSTANCE) == COMP2))
Kojto	112:6f327212ef96	5492
Kojto	112:6f327212ef96	5493	/**************************** CRC Instances *******************************/
Kojto	112:6f327212ef96	5494	#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
Kojto	112:6f327212ef96	5495
Kojto	112:6f327212ef96	5496	/**************************** DAC Instances *******************************/
Kojto	112:6f327212ef96	5497	#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
Kojto	112:6f327212ef96	5498
Kojto	112:6f327212ef96	5499	/**************************** DMA Instances *******************************/
Kojto	112:6f327212ef96	5500	#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) \|\| \
Kojto	112:6f327212ef96	5501	((INSTANCE) == DMA1_Channel2) \|\| \
Kojto	112:6f327212ef96	5502	((INSTANCE) == DMA1_Channel3) \|\| \
Kojto	112:6f327212ef96	5503	((INSTANCE) == DMA1_Channel4) \|\| \
Kojto	112:6f327212ef96	5504	((INSTANCE) == DMA1_Channel5) \|\| \
Kojto	112:6f327212ef96	5505	((INSTANCE) == DMA1_Channel6) \|\| \
Kojto	112:6f327212ef96	5506	((INSTANCE) == DMA1_Channel7) \|\| \
Kojto	112:6f327212ef96	5507	((INSTANCE) == DMA2_Channel1) \|\| \
Kojto	112:6f327212ef96	5508	((INSTANCE) == DMA2_Channel2) \|\| \
Kojto	112:6f327212ef96	5509	((INSTANCE) == DMA2_Channel3) \|\| \
Kojto	112:6f327212ef96	5510	((INSTANCE) == DMA2_Channel4) \|\| \
Kojto	112:6f327212ef96	5511	((INSTANCE) == DMA2_Channel5))
Kojto	112:6f327212ef96	5512
Kojto	112:6f327212ef96	5513	/***************************** GPIO Instances *****************************/
Kojto	112:6f327212ef96	5514	#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) \|\| \
Kojto	112:6f327212ef96	5515	((INSTANCE) == GPIOB) \|\| \
Kojto	112:6f327212ef96	5516	((INSTANCE) == GPIOC) \|\| \
Kojto	112:6f327212ef96	5517	((INSTANCE) == GPIOD) \|\| \
Kojto	112:6f327212ef96	5518	((INSTANCE) == GPIOE) \|\| \
Kojto	112:6f327212ef96	5519	((INSTANCE) == GPIOH))
Kojto	112:6f327212ef96	5520
Kojto	112:6f327212ef96	5521	/************************** GPIO Lock Instances ***************************/
Kojto	112:6f327212ef96	5522	/* On L1, all GPIO Bank support the Lock mechanism */
Kojto	112:6f327212ef96	5523	#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
Kojto	112:6f327212ef96	5524
Kojto	112:6f327212ef96	5525	/****************************** I2C Instances *****************************/
Kojto	112:6f327212ef96	5526	#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) \|\| \
Kojto	112:6f327212ef96	5527	((INSTANCE) == I2C2))
Kojto	112:6f327212ef96	5528
Kojto	112:6f327212ef96	5529	#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) \|\| \
Kojto	112:6f327212ef96	5530	((INSTANCE) == SPI2) \|\| \
Kojto	112:6f327212ef96	5531	((INSTANCE) == SPI3))
Kojto	112:6f327212ef96	5532	/**************************** IWDG Instances ******************************/
Kojto	112:6f327212ef96	5533	#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
Kojto	112:6f327212ef96	5534
Kojto	112:6f327212ef96	5535	/**************************** OPAMP Instances *****************************/
Kojto	112:6f327212ef96	5536	#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) \|\| \
Kojto	112:6f327212ef96	5537	((INSTANCE) == OPAMP2))
Kojto	112:6f327212ef96	5538
Kojto	112:6f327212ef96	5539	/**************************** RTC Instances *******************************/
Kojto	112:6f327212ef96	5540	#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
Kojto	112:6f327212ef96	5541
Kojto	112:6f327212ef96	5542	/****************************** SPI Instances *****************************/
Kojto	112:6f327212ef96	5543	#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) \|\| \
Kojto	112:6f327212ef96	5544	((INSTANCE) == SPI2) \|\| \
Kojto	112:6f327212ef96	5545	((INSTANCE) == SPI3))
Kojto	112:6f327212ef96	5546
Kojto	112:6f327212ef96	5547	/**************************** TIM Instances *******************************/
Kojto	112:6f327212ef96	5548	#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
Kojto	112:6f327212ef96	5549	((INSTANCE) == TIM3) \|\| \
Kojto	112:6f327212ef96	5550	((INSTANCE) == TIM4) \|\| \
Kojto	112:6f327212ef96	5551	((INSTANCE) == TIM5) \|\| \
Kojto	112:6f327212ef96	5552	((INSTANCE) == TIM6) \|\| \
Kojto	112:6f327212ef96	5553	((INSTANCE) == TIM7) \|\| \
Kojto	112:6f327212ef96	5554	((INSTANCE) == TIM9) \|\| \
Kojto	112:6f327212ef96	5555	((INSTANCE) == TIM10) \|\| \
Kojto	112:6f327212ef96	5556	((INSTANCE) == TIM11))
Kojto	112:6f327212ef96	5557
Kojto	112:6f327212ef96	5558	#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
Kojto	112:6f327212ef96	5559	((INSTANCE) == TIM3) \|\| \
Kojto	112:6f327212ef96	5560	((INSTANCE) == TIM4) \|\| \
Kojto	112:6f327212ef96	5561	((INSTANCE) == TIM5) \|\| \
Kojto	112:6f327212ef96	5562	((INSTANCE) == TIM9) \|\| \
Kojto	112:6f327212ef96	5563	((INSTANCE) == TIM10) \|\| \
Kojto	112:6f327212ef96	5564	((INSTANCE) == TIM11))
Kojto	112:6f327212ef96	5565
Kojto	112:6f327212ef96	5566	#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
Kojto	112:6f327212ef96	5567	((INSTANCE) == TIM3) \|\| \
Kojto	112:6f327212ef96	5568	((INSTANCE) == TIM4) \|\| \
Kojto	112:6f327212ef96	5569	((INSTANCE) == TIM5) \|\| \
Kojto	112:6f327212ef96	5570	((INSTANCE) == TIM9))
Kojto	112:6f327212ef96	5571
Kojto	112:6f327212ef96	5572	#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
Kojto	112:6f327212ef96	5573	((INSTANCE) == TIM3) \|\| \
Kojto	112:6f327212ef96	5574	((INSTANCE) == TIM4) \|\| \
Kojto	112:6f327212ef96	5575	((INSTANCE) == TIM5))
Kojto	112:6f327212ef96	5576
Kojto	112:6f327212ef96	5577	#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
Kojto	112:6f327212ef96	5578	((INSTANCE) == TIM3) \|\| \
Kojto	112:6f327212ef96	5579	((INSTANCE) == TIM4) \|\| \
Kojto	112:6f327212ef96	5580	((INSTANCE) == TIM5))
Kojto	112:6f327212ef96	5581
Kojto	112:6f327212ef96	5582	#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
Kojto	112:6f327212ef96	5583	((INSTANCE) == TIM3) \|\| \
Kojto	112:6f327212ef96	5584	((INSTANCE) == TIM4) \|\| \
Kojto	112:6f327212ef96	5585	((INSTANCE) == TIM5) \|\| \
Kojto	112:6f327212ef96	5586	((INSTANCE) == TIM9))
Kojto	112:6f327212ef96	5587
Kojto	112:6f327212ef96	5588	#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
Kojto	112:6f327212ef96	5589	((INSTANCE) == TIM3) \|\| \
Kojto	112:6f327212ef96	5590	((INSTANCE) == TIM4) \|\| \
Kojto	112:6f327212ef96	5591	((INSTANCE) == TIM5) \|\| \
Kojto	112:6f327212ef96	5592	((INSTANCE) == TIM9) \|\| \
Kojto	112:6f327212ef96	5593	((INSTANCE) == TIM10) \|\| \
Kojto	112:6f327212ef96	5594	((INSTANCE) == TIM11))
Kojto	112:6f327212ef96	5595
Kojto	112:6f327212ef96	5596	#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
Kojto	112:6f327212ef96	5597	((INSTANCE) == TIM3) \|\| \
Kojto	112:6f327212ef96	5598	((INSTANCE) == TIM4) \|\| \
Kojto	112:6f327212ef96	5599	((INSTANCE) == TIM5) \|\| \
Kojto	112:6f327212ef96	5600	((INSTANCE) == TIM9))
Kojto	112:6f327212ef96	5601
Kojto	112:6f327212ef96	5602	#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
Kojto	112:6f327212ef96	5603	((INSTANCE) == TIM3) \|\| \
Kojto	112:6f327212ef96	5604	((INSTANCE) == TIM4) \|\| \
Kojto	112:6f327212ef96	5605	((INSTANCE) == TIM5) \|\| \
Kojto	112:6f327212ef96	5606	((INSTANCE) == TIM9))
Kojto	112:6f327212ef96	5607
Kojto	112:6f327212ef96	5608	#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
Kojto	112:6f327212ef96	5609	((INSTANCE) == TIM3) \|\| \
Kojto	112:6f327212ef96	5610	((INSTANCE) == TIM4))
Kojto	112:6f327212ef96	5611
Kojto	112:6f327212ef96	5612	#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
Kojto	112:6f327212ef96	5613	((INSTANCE) == TIM3) \|\| \
Kojto	112:6f327212ef96	5614	((INSTANCE) == TIM4) \|\| \
Kojto	112:6f327212ef96	5615	((INSTANCE) == TIM5))
Kojto	112:6f327212ef96	5616
Kojto	112:6f327212ef96	5617	#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
Kojto	112:6f327212ef96	5618	((INSTANCE) == TIM3) \|\| \
Kojto	112:6f327212ef96	5619	((INSTANCE) == TIM4) \|\| \
Kojto	112:6f327212ef96	5620	((INSTANCE) == TIM5) \|\| \
Kojto	112:6f327212ef96	5621	((INSTANCE) == TIM6) \|\| \
Kojto	112:6f327212ef96	5622	((INSTANCE) == TIM7) \|\| \
Kojto	112:6f327212ef96	5623	((INSTANCE) == TIM9))
Kojto	112:6f327212ef96	5624
Kojto	112:6f327212ef96	5625	#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
Kojto	112:6f327212ef96	5626	((INSTANCE) == TIM3) \|\| \
Kojto	112:6f327212ef96	5627	((INSTANCE) == TIM4) \|\| \
Kojto	112:6f327212ef96	5628	((INSTANCE) == TIM5) \|\| \
Kojto	112:6f327212ef96	5629	((INSTANCE) == TIM9))
Kojto	112:6f327212ef96	5630
Kojto	112:6f327212ef96	5631	#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM5)
Kojto	112:6f327212ef96	5632
Kojto	112:6f327212ef96	5633	#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
Kojto	112:6f327212ef96	5634	((INSTANCE) == TIM3) \|\| \
Kojto	112:6f327212ef96	5635	((INSTANCE) == TIM4) \|\| \
Kojto	112:6f327212ef96	5636	((INSTANCE) == TIM5))
Kojto	112:6f327212ef96	5637
Kojto	112:6f327212ef96	5638	#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
Kojto	112:6f327212ef96	5639	((((INSTANCE) == TIM2) && \
Kojto	112:6f327212ef96	5640	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
Kojto	112:6f327212ef96	5641	((CHANNEL) == TIM_CHANNEL_2) \|\| \
Kojto	112:6f327212ef96	5642	((CHANNEL) == TIM_CHANNEL_3) \|\| \
Kojto	112:6f327212ef96	5643	((CHANNEL) == TIM_CHANNEL_4))) \
Kojto	112:6f327212ef96	5644	\|\| \
Kojto	112:6f327212ef96	5645	(((INSTANCE) == TIM3) && \
Kojto	112:6f327212ef96	5646	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
Kojto	112:6f327212ef96	5647	((CHANNEL) == TIM_CHANNEL_2) \|\| \
Kojto	112:6f327212ef96	5648	((CHANNEL) == TIM_CHANNEL_3) \|\| \
Kojto	112:6f327212ef96	5649	((CHANNEL) == TIM_CHANNEL_4))) \
Kojto	112:6f327212ef96	5650	\|\| \
Kojto	112:6f327212ef96	5651	(((INSTANCE) == TIM4) && \
Kojto	112:6f327212ef96	5652	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
Kojto	112:6f327212ef96	5653	((CHANNEL) == TIM_CHANNEL_2) \|\| \
Kojto	112:6f327212ef96	5654	((CHANNEL) == TIM_CHANNEL_3) \|\| \
Kojto	112:6f327212ef96	5655	((CHANNEL) == TIM_CHANNEL_4))) \
Kojto	112:6f327212ef96	5656	\|\| \
Kojto	112:6f327212ef96	5657	(((INSTANCE) == TIM5) && \
Kojto	112:6f327212ef96	5658	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
Kojto	112:6f327212ef96	5659	((CHANNEL) == TIM_CHANNEL_2) \|\| \
Kojto	112:6f327212ef96	5660	((CHANNEL) == TIM_CHANNEL_3) \|\| \
Kojto	112:6f327212ef96	5661	((CHANNEL) == TIM_CHANNEL_4))) \
Kojto	112:6f327212ef96	5662	\|\| \
Kojto	112:6f327212ef96	5663	(((INSTANCE) == TIM9) && \
Kojto	112:6f327212ef96	5664	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
Kojto	112:6f327212ef96	5665	((CHANNEL) == TIM_CHANNEL_2))) \
Kojto	112:6f327212ef96	5666	\|\| \
Kojto	112:6f327212ef96	5667	(((INSTANCE) == TIM10) && \
Kojto	112:6f327212ef96	5668	(((CHANNEL) == TIM_CHANNEL_1))) \
Kojto	112:6f327212ef96	5669	\|\| \
Kojto	112:6f327212ef96	5670	(((INSTANCE) == TIM11) && \
Kojto	112:6f327212ef96	5671	(((CHANNEL) == TIM_CHANNEL_1))))
Kojto	112:6f327212ef96	5672
Kojto	112:6f327212ef96	5673	#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
Kojto	112:6f327212ef96	5674	((INSTANCE) == TIM3) \|\| \
Kojto	112:6f327212ef96	5675	((INSTANCE) == TIM4) \|\| \
Kojto	112:6f327212ef96	5676	((INSTANCE) == TIM5) \|\| \
Kojto	112:6f327212ef96	5677	((INSTANCE) == TIM9) \|\| \
Kojto	112:6f327212ef96	5678	((INSTANCE) == TIM10) \|\| \
Kojto	112:6f327212ef96	5679	((INSTANCE) == TIM11))
Kojto	112:6f327212ef96	5680
Kojto	112:6f327212ef96	5681	#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
Kojto	112:6f327212ef96	5682	((INSTANCE) == TIM3) \|\| \
Kojto	112:6f327212ef96	5683	((INSTANCE) == TIM4) \|\| \
Kojto	112:6f327212ef96	5684	((INSTANCE) == TIM5) \|\| \
Kojto	112:6f327212ef96	5685	((INSTANCE) == TIM6) \|\| \
Kojto	112:6f327212ef96	5686	((INSTANCE) == TIM7))
Kojto	112:6f327212ef96	5687
Kojto	112:6f327212ef96	5688	#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
Kojto	112:6f327212ef96	5689	((INSTANCE) == TIM3) \|\| \
Kojto	112:6f327212ef96	5690	((INSTANCE) == TIM4) \|\| \
Kojto	112:6f327212ef96	5691	((INSTANCE) == TIM5))
Kojto	112:6f327212ef96	5692
Kojto	112:6f327212ef96	5693	#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
Kojto	112:6f327212ef96	5694	((INSTANCE) == TIM3) \|\| \
Kojto	112:6f327212ef96	5695	((INSTANCE) == TIM4) \|\| \
Kojto	112:6f327212ef96	5696	((INSTANCE) == TIM5) \|\| \
Kojto	112:6f327212ef96	5697	((INSTANCE) == TIM9))
Kojto	112:6f327212ef96	5698
Kojto	112:6f327212ef96	5699	#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
Kojto	112:6f327212ef96	5700	((INSTANCE) == TIM3) \|\| \
Kojto	112:6f327212ef96	5701	((INSTANCE) == TIM4) \|\| \
Kojto	112:6f327212ef96	5702	((INSTANCE) == TIM5) \|\| \
Kojto	112:6f327212ef96	5703	((INSTANCE) == TIM9))
Kojto	112:6f327212ef96	5704
Kojto	112:6f327212ef96	5705	#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
Kojto	112:6f327212ef96	5706	((INSTANCE) == TIM3) \|\| \
Kojto	112:6f327212ef96	5707	((INSTANCE) == TIM9) \|\| \
Kojto	112:6f327212ef96	5708	((INSTANCE) == TIM10) \|\| \
Kojto	112:6f327212ef96	5709	((INSTANCE) == TIM11))
Kojto	112:6f327212ef96	5710
Kojto	112:6f327212ef96	5711	/****************** USART Instances : Synchronous mode ********************/
Kojto	112:6f327212ef96	5712	#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
Kojto	112:6f327212ef96	5713	((INSTANCE) == USART2) \|\| \
Kojto	112:6f327212ef96	5714	((INSTANCE) == USART3))
Kojto	112:6f327212ef96	5715
Kojto	112:6f327212ef96	5716	/****************** UART Instances : Asynchronous mode ********************/
Kojto	112:6f327212ef96	5717	#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
Kojto	112:6f327212ef96	5718	((INSTANCE) == USART2) \|\| \
Kojto	112:6f327212ef96	5719	((INSTANCE) == USART3))
Kojto	112:6f327212ef96	5720
Kojto	112:6f327212ef96	5721	/****************** UART Instances : Half-Duplex mode ********************/
Kojto	112:6f327212ef96	5722	#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
Kojto	112:6f327212ef96	5723	((INSTANCE) == USART2) \|\| \
Kojto	112:6f327212ef96	5724	((INSTANCE) == USART3))
Kojto	112:6f327212ef96	5725
Kojto	112:6f327212ef96	5726	/****************** UART Instances : LIN mode ********************/
Kojto	112:6f327212ef96	5727	#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
Kojto	112:6f327212ef96	5728	((INSTANCE) == USART2) \|\| \
Kojto	112:6f327212ef96	5729	((INSTANCE) == USART3))
Kojto	112:6f327212ef96	5730
Kojto	112:6f327212ef96	5731	/**************** UART Instances : Hardware Flow control ******************/
Kojto	112:6f327212ef96	5732	#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
Kojto	112:6f327212ef96	5733	((INSTANCE) == USART2) \|\| \
Kojto	112:6f327212ef96	5734	((INSTANCE) == USART3))
Kojto	112:6f327212ef96	5735
Kojto	112:6f327212ef96	5736	/******************* UART Instances : Smard card mode *********************/
Kojto	112:6f327212ef96	5737	#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
Kojto	112:6f327212ef96	5738	((INSTANCE) == USART2) \|\| \
Kojto	112:6f327212ef96	5739	((INSTANCE) == USART3))
Kojto	112:6f327212ef96	5740
Kojto	112:6f327212ef96	5741	/********************* UART Instances : IRDA mode *************************/
Kojto	112:6f327212ef96	5742	#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
Kojto	112:6f327212ef96	5743	((INSTANCE) == USART2) \|\| \
Kojto	112:6f327212ef96	5744	((INSTANCE) == USART3))
Kojto	112:6f327212ef96	5745
Kojto	112:6f327212ef96	5746	/*************** UART Instances : Multi-Processor mode ********************/
Kojto	112:6f327212ef96	5747	#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
Kojto	112:6f327212ef96	5748	((INSTANCE) == USART2) \|\| \
Kojto	112:6f327212ef96	5749	((INSTANCE) == USART3))
Kojto	112:6f327212ef96	5750
Kojto	112:6f327212ef96	5751	/**************************** WWDG Instances ******************************/
Kojto	112:6f327212ef96	5752	#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
Kojto	112:6f327212ef96	5753
Kojto	112:6f327212ef96	5754
Kojto	112:6f327212ef96	5755	/**************************** LCD Instances ******************************/
Kojto	112:6f327212ef96	5756	#define IS_LCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LCD)
Kojto	112:6f327212ef96	5757
Kojto	112:6f327212ef96	5758	/**************************** USB Instances ******************************/
Kojto	112:6f327212ef96	5759	#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
Kojto	112:6f327212ef96	5760
Kojto	112:6f327212ef96	5761	/**
Kojto	112:6f327212ef96	5762	* @}
Kojto	112:6f327212ef96	5763	*/
Kojto	112:6f327212ef96	5764
Kojto	112:6f327212ef96	5765	/******************************************************************************/
Kojto	112:6f327212ef96	5766	/* For a painless codes migration between the STM32L1xx device product */
Kojto	112:6f327212ef96	5767	/* lines, the aliases defined below are put in place to overcome the */
Kojto	112:6f327212ef96	5768	/* differences in the interrupt handlers and IRQn definitions. */
Kojto	112:6f327212ef96	5769	/* No need to update developed interrupt code when moving across */
Kojto	112:6f327212ef96	5770	/* product lines within the same STM32L1 Family */
Kojto	112:6f327212ef96	5771	/******************************************************************************/
Kojto	112:6f327212ef96	5772
Kojto	112:6f327212ef96	5773	/* Aliases for __IRQn */
Kojto	112:6f327212ef96	5774
Kojto	112:6f327212ef96	5775	/* Aliases for __IRQHandler */
Kojto	112:6f327212ef96	5776
Kojto	112:6f327212ef96	5777	/**
Kojto	112:6f327212ef96	5778	* @}
Kojto	112:6f327212ef96	5779	*/
Kojto	112:6f327212ef96	5780
Kojto	112:6f327212ef96	5781	/**
Kojto	112:6f327212ef96	5782	* @}
Kojto	112:6f327212ef96	5783	*/
Kojto	112:6f327212ef96	5784
Kojto	112:6f327212ef96	5785	#ifdef __cplusplus
Kojto	112:6f327212ef96	5786	}
Kojto	112:6f327212ef96	5787	#endif /* __cplusplus */
Kojto	112:6f327212ef96	5788
Kojto	112:6f327212ef96	5789	#endif /* __STM32L152xC_H */
Kojto	112:6f327212ef96	5790
Kojto	112:6f327212ef96	5791
Kojto	112:6f327212ef96	5792
Kojto	112:6f327212ef96	5793	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	04 Apr 2016
Imports:	4
Forks:	0
Commits:	122
Dependents:	4
Dependencies:	0
Followers:	1

The code in this repository is Apache licensed.

TARGET_MOTE_L152RC/stm32l152xc.h@112:6f327212ef96, 2016-01-13 (annotated)

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