Elijah Orr / mbed-renbed

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TARGET_SAMR21G18A/comp_evsys.h@121:672067c3ada4, 2016-04-14 (annotated)

Committer:
elijahorr
Date:
Thu Apr 14 07:28:54 2016 +0000
Revision:
121:672067c3ada4
Parent:
111:4336505e4b1c 
.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 111:4336505e4b1c 1 /**
Kojto 111:4336505e4b1c 2 * \file
Kojto 111:4336505e4b1c 3 *
Kojto 111:4336505e4b1c 4 * \brief Component description for EVSYS
Kojto 111:4336505e4b1c 5 *
Kojto 111:4336505e4b1c 6 * Copyright (c) 2015 Atmel Corporation. All rights reserved.
Kojto 111:4336505e4b1c 7 *
Kojto 111:4336505e4b1c 8 * \asf_license_start
Kojto 111:4336505e4b1c 9 *
Kojto 111:4336505e4b1c 10 * \page License
Kojto 111:4336505e4b1c 11 *
Kojto 111:4336505e4b1c 12 * Redistribution and use in source and binary forms, with or without
Kojto 111:4336505e4b1c 13 * modification, are permitted provided that the following conditions are met:
Kojto 111:4336505e4b1c 14 *
Kojto 111:4336505e4b1c 15 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 111:4336505e4b1c 16 * this list of conditions and the following disclaimer.
Kojto 111:4336505e4b1c 17 *
Kojto 111:4336505e4b1c 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 111:4336505e4b1c 19 * this list of conditions and the following disclaimer in the documentation
Kojto 111:4336505e4b1c 20 * and/or other materials provided with the distribution.
Kojto 111:4336505e4b1c 21 *
Kojto 111:4336505e4b1c 22 * 3. The name of Atmel may not be used to endorse or promote products derived
Kojto 111:4336505e4b1c 23 * from this software without specific prior written permission.
Kojto 111:4336505e4b1c 24 *
Kojto 111:4336505e4b1c 25 * 4. This software may only be redistributed and used in connection with an
Kojto 111:4336505e4b1c 26 * Atmel microcontroller product.
Kojto 111:4336505e4b1c 27 *
Kojto 111:4336505e4b1c 28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
Kojto 111:4336505e4b1c 29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
Kojto 111:4336505e4b1c 30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
Kojto 111:4336505e4b1c 31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
Kojto 111:4336505e4b1c 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 111:4336505e4b1c 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
Kojto 111:4336505e4b1c 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
Kojto 111:4336505e4b1c 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
Kojto 111:4336505e4b1c 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
Kojto 111:4336505e4b1c 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto 111:4336505e4b1c 38 * POSSIBILITY OF SUCH DAMAGE.
Kojto 111:4336505e4b1c 39 *
Kojto 111:4336505e4b1c 40 * \asf_license_stop
Kojto 111:4336505e4b1c 41 *
Kojto 111:4336505e4b1c 42 */
Kojto 111:4336505e4b1c 43
Kojto 111:4336505e4b1c 44 #ifndef _SAMR21_EVSYS_COMPONENT_
Kojto 111:4336505e4b1c 45 #define _SAMR21_EVSYS_COMPONENT_
Kojto 111:4336505e4b1c 46
Kojto 111:4336505e4b1c 47 /* ========================================================================== */
Kojto 111:4336505e4b1c 48 /** SOFTWARE API DEFINITION FOR EVSYS */
Kojto 111:4336505e4b1c 49 /* ========================================================================== */
Kojto 111:4336505e4b1c 50 /** \addtogroup SAMR21_EVSYS Event System Interface */
Kojto 111:4336505e4b1c 51 /*@{*/
Kojto 111:4336505e4b1c 52
Kojto 111:4336505e4b1c 53 #define EVSYS_U2208
Kojto 111:4336505e4b1c 54 #define REV_EVSYS 0x101
Kojto 111:4336505e4b1c 55
Kojto 111:4336505e4b1c 56 /* -------- EVSYS_CTRL : (EVSYS Offset: 0x00) ( /W 8) Control -------- */
Kojto 111:4336505e4b1c 57 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 58 typedef union {
Kojto 111:4336505e4b1c 59 struct {
Kojto 111:4336505e4b1c 60 uint8_t SWRST:1; /*!< bit: 0 Software Reset */
Kojto 111:4336505e4b1c 61 uint8_t :3; /*!< bit: 1.. 3 Reserved */
Kojto 111:4336505e4b1c 62 uint8_t GCLKREQ:1; /*!< bit: 4 Generic Clock Requests */
Kojto 111:4336505e4b1c 63 uint8_t :3; /*!< bit: 5.. 7 Reserved */
Kojto 111:4336505e4b1c 64 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 65 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 66 } EVSYS_CTRL_Type;
Kojto 111:4336505e4b1c 67 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 68
Kojto 111:4336505e4b1c 69 #define EVSYS_CTRL_OFFSET 0x00 /**< \brief (EVSYS_CTRL offset) Control */
Kojto 111:4336505e4b1c 70 #define EVSYS_CTRL_RESETVALUE 0x00ul /**< \brief (EVSYS_CTRL reset_value) Control */
Kojto 111:4336505e4b1c 71
Kojto 111:4336505e4b1c 72 #define EVSYS_CTRL_SWRST_Pos 0 /**< \brief (EVSYS_CTRL) Software Reset */
Kojto 111:4336505e4b1c 73 #define EVSYS_CTRL_SWRST (0x1ul << EVSYS_CTRL_SWRST_Pos)
Kojto 111:4336505e4b1c 74 #define EVSYS_CTRL_GCLKREQ_Pos 4 /**< \brief (EVSYS_CTRL) Generic Clock Requests */
Kojto 111:4336505e4b1c 75 #define EVSYS_CTRL_GCLKREQ (0x1ul << EVSYS_CTRL_GCLKREQ_Pos)
Kojto 111:4336505e4b1c 76 #define EVSYS_CTRL_MASK 0x11ul /**< \brief (EVSYS_CTRL) MASK Register */
Kojto 111:4336505e4b1c 77
Kojto 111:4336505e4b1c 78 /* -------- EVSYS_CHANNEL : (EVSYS Offset: 0x04) (R/W 32) Channel -------- */
Kojto 111:4336505e4b1c 79 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 80 typedef union {
Kojto 111:4336505e4b1c 81 struct {
Kojto 111:4336505e4b1c 82 uint32_t CHANNEL:4; /*!< bit: 0.. 3 Channel Selection */
Kojto 111:4336505e4b1c 83 uint32_t :4; /*!< bit: 4.. 7 Reserved */
Kojto 111:4336505e4b1c 84 uint32_t SWEVT:1; /*!< bit: 8 Software Event */
Kojto 111:4336505e4b1c 85 uint32_t :7; /*!< bit: 9..15 Reserved */
Kojto 111:4336505e4b1c 86 uint32_t EVGEN:7; /*!< bit: 16..22 Event Generator Selection */
Kojto 111:4336505e4b1c 87 uint32_t :1; /*!< bit: 23 Reserved */
Kojto 111:4336505e4b1c 88 uint32_t PATH:2; /*!< bit: 24..25 Path Selection */
Kojto 111:4336505e4b1c 89 uint32_t EDGSEL:2; /*!< bit: 26..27 Edge Detection Selection */
Kojto 111:4336505e4b1c 90 uint32_t :4; /*!< bit: 28..31 Reserved */
Kojto 111:4336505e4b1c 91 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 92 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 93 } EVSYS_CHANNEL_Type;
Kojto 111:4336505e4b1c 94 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 95
Kojto 111:4336505e4b1c 96 #define EVSYS_CHANNEL_OFFSET 0x04 /**< \brief (EVSYS_CHANNEL offset) Channel */
Kojto 111:4336505e4b1c 97 #define EVSYS_CHANNEL_RESETVALUE 0x00000000ul /**< \brief (EVSYS_CHANNEL reset_value) Channel */
Kojto 111:4336505e4b1c 98
Kojto 111:4336505e4b1c 99 #define EVSYS_CHANNEL_CHANNEL_Pos 0 /**< \brief (EVSYS_CHANNEL) Channel Selection */
Kojto 111:4336505e4b1c 100 #define EVSYS_CHANNEL_CHANNEL_Msk (0xFul << EVSYS_CHANNEL_CHANNEL_Pos)
Kojto 111:4336505e4b1c 101 #define EVSYS_CHANNEL_CHANNEL(value) (EVSYS_CHANNEL_CHANNEL_Msk & ((value) << EVSYS_CHANNEL_CHANNEL_Pos))
Kojto 111:4336505e4b1c 102 #define EVSYS_CHANNEL_SWEVT_Pos 8 /**< \brief (EVSYS_CHANNEL) Software Event */
Kojto 111:4336505e4b1c 103 #define EVSYS_CHANNEL_SWEVT (0x1ul << EVSYS_CHANNEL_SWEVT_Pos)
Kojto 111:4336505e4b1c 104 #define EVSYS_CHANNEL_EVGEN_Pos 16 /**< \brief (EVSYS_CHANNEL) Event Generator Selection */
Kojto 111:4336505e4b1c 105 #define EVSYS_CHANNEL_EVGEN_Msk (0x7Ful << EVSYS_CHANNEL_EVGEN_Pos)
Kojto 111:4336505e4b1c 106 #define EVSYS_CHANNEL_EVGEN(value) (EVSYS_CHANNEL_EVGEN_Msk & ((value) << EVSYS_CHANNEL_EVGEN_Pos))
Kojto 111:4336505e4b1c 107 #define EVSYS_CHANNEL_PATH_Pos 24 /**< \brief (EVSYS_CHANNEL) Path Selection */
Kojto 111:4336505e4b1c 108 #define EVSYS_CHANNEL_PATH_Msk (0x3ul << EVSYS_CHANNEL_PATH_Pos)
Kojto 111:4336505e4b1c 109 #define EVSYS_CHANNEL_PATH(value) (EVSYS_CHANNEL_PATH_Msk & ((value) << EVSYS_CHANNEL_PATH_Pos))
Kojto 111:4336505e4b1c 110 #define EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val 0x0ul /**< \brief (EVSYS_CHANNEL) Synchronous path */
Kojto 111:4336505e4b1c 111 #define EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val 0x1ul /**< \brief (EVSYS_CHANNEL) Resynchronized path */
Kojto 111:4336505e4b1c 112 #define EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val 0x2ul /**< \brief (EVSYS_CHANNEL) Asynchronous path */
Kojto 111:4336505e4b1c 113 #define EVSYS_CHANNEL_PATH_SYNCHRONOUS (EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos)
Kojto 111:4336505e4b1c 114 #define EVSYS_CHANNEL_PATH_RESYNCHRONIZED (EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val << EVSYS_CHANNEL_PATH_Pos)
Kojto 111:4336505e4b1c 115 #define EVSYS_CHANNEL_PATH_ASYNCHRONOUS (EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos)
Kojto 111:4336505e4b1c 116 #define EVSYS_CHANNEL_EDGSEL_Pos 26 /**< \brief (EVSYS_CHANNEL) Edge Detection Selection */
Kojto 111:4336505e4b1c 117 #define EVSYS_CHANNEL_EDGSEL_Msk (0x3ul << EVSYS_CHANNEL_EDGSEL_Pos)
Kojto 111:4336505e4b1c 118 #define EVSYS_CHANNEL_EDGSEL(value) (EVSYS_CHANNEL_EDGSEL_Msk & ((value) << EVSYS_CHANNEL_EDGSEL_Pos))
Kojto 111:4336505e4b1c 119 #define EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val 0x0ul /**< \brief (EVSYS_CHANNEL) No event output when using the resynchronized or synchronous path */
Kojto 111:4336505e4b1c 120 #define EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val 0x1ul /**< \brief (EVSYS_CHANNEL) Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path */
Kojto 111:4336505e4b1c 121 #define EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val 0x2ul /**< \brief (EVSYS_CHANNEL) Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path */
Kojto 111:4336505e4b1c 122 #define EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val 0x3ul /**< \brief (EVSYS_CHANNEL) Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path */
Kojto 111:4336505e4b1c 123 #define EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT (EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val << EVSYS_CHANNEL_EDGSEL_Pos)
Kojto 111:4336505e4b1c 124 #define EVSYS_CHANNEL_EDGSEL_RISING_EDGE (EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos)
Kojto 111:4336505e4b1c 125 #define EVSYS_CHANNEL_EDGSEL_FALLING_EDGE (EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos)
Kojto 111:4336505e4b1c 126 #define EVSYS_CHANNEL_EDGSEL_BOTH_EDGES (EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val << EVSYS_CHANNEL_EDGSEL_Pos)
Kojto 111:4336505e4b1c 127 #define EVSYS_CHANNEL_MASK 0x0F7F010Ful /**< \brief (EVSYS_CHANNEL) MASK Register */
Kojto 111:4336505e4b1c 128
Kojto 111:4336505e4b1c 129 /* -------- EVSYS_USER : (EVSYS Offset: 0x08) (R/W 16) User Multiplexer -------- */
Kojto 111:4336505e4b1c 130 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 131 typedef union {
Kojto 111:4336505e4b1c 132 struct {
Kojto 111:4336505e4b1c 133 uint16_t USER:5; /*!< bit: 0.. 4 User Multiplexer Selection */
Kojto 111:4336505e4b1c 134 uint16_t :3; /*!< bit: 5.. 7 Reserved */
Kojto 111:4336505e4b1c 135 uint16_t CHANNEL:5; /*!< bit: 8..12 Channel Event Selection */
Kojto 111:4336505e4b1c 136 uint16_t :3; /*!< bit: 13..15 Reserved */
Kojto 111:4336505e4b1c 137 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 138 uint16_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 139 } EVSYS_USER_Type;
Kojto 111:4336505e4b1c 140 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 141
Kojto 111:4336505e4b1c 142 #define EVSYS_USER_OFFSET 0x08 /**< \brief (EVSYS_USER offset) User Multiplexer */
Kojto 111:4336505e4b1c 143 #define EVSYS_USER_RESETVALUE 0x0000ul /**< \brief (EVSYS_USER reset_value) User Multiplexer */
Kojto 111:4336505e4b1c 144
Kojto 111:4336505e4b1c 145 #define EVSYS_USER_USER_Pos 0 /**< \brief (EVSYS_USER) User Multiplexer Selection */
Kojto 111:4336505e4b1c 146 #define EVSYS_USER_USER_Msk (0x1Ful << EVSYS_USER_USER_Pos)
Kojto 111:4336505e4b1c 147 #define EVSYS_USER_USER(value) (EVSYS_USER_USER_Msk & ((value) << EVSYS_USER_USER_Pos))
Kojto 111:4336505e4b1c 148 #define EVSYS_USER_CHANNEL_Pos 8 /**< \brief (EVSYS_USER) Channel Event Selection */
Kojto 111:4336505e4b1c 149 #define EVSYS_USER_CHANNEL_Msk (0x1Ful << EVSYS_USER_CHANNEL_Pos)
Kojto 111:4336505e4b1c 150 #define EVSYS_USER_CHANNEL(value) (EVSYS_USER_CHANNEL_Msk & ((value) << EVSYS_USER_CHANNEL_Pos))
Kojto 111:4336505e4b1c 151 #define EVSYS_USER_CHANNEL_0_Val 0x0ul /**< \brief (EVSYS_USER) No Channel Output Selected */
Kojto 111:4336505e4b1c 152 #define EVSYS_USER_CHANNEL_0 (EVSYS_USER_CHANNEL_0_Val << EVSYS_USER_CHANNEL_Pos)
Kojto 111:4336505e4b1c 153 #define EVSYS_USER_MASK 0x1F1Ful /**< \brief (EVSYS_USER) MASK Register */
Kojto 111:4336505e4b1c 154
Kojto 111:4336505e4b1c 155 /* -------- EVSYS_CHSTATUS : (EVSYS Offset: 0x0C) (R/ 32) Channel Status -------- */
Kojto 111:4336505e4b1c 156 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 157 typedef union {
Kojto 111:4336505e4b1c 158 struct {
Kojto 111:4336505e4b1c 159 uint32_t USRRDY0:1; /*!< bit: 0 Channel 0 User Ready */
Kojto 111:4336505e4b1c 160 uint32_t USRRDY1:1; /*!< bit: 1 Channel 1 User Ready */
Kojto 111:4336505e4b1c 161 uint32_t USRRDY2:1; /*!< bit: 2 Channel 2 User Ready */
Kojto 111:4336505e4b1c 162 uint32_t USRRDY3:1; /*!< bit: 3 Channel 3 User Ready */
Kojto 111:4336505e4b1c 163 uint32_t USRRDY4:1; /*!< bit: 4 Channel 4 User Ready */
Kojto 111:4336505e4b1c 164 uint32_t USRRDY5:1; /*!< bit: 5 Channel 5 User Ready */
Kojto 111:4336505e4b1c 165 uint32_t USRRDY6:1; /*!< bit: 6 Channel 6 User Ready */
Kojto 111:4336505e4b1c 166 uint32_t USRRDY7:1; /*!< bit: 7 Channel 7 User Ready */
Kojto 111:4336505e4b1c 167 uint32_t CHBUSY0:1; /*!< bit: 8 Channel 0 Busy */
Kojto 111:4336505e4b1c 168 uint32_t CHBUSY1:1; /*!< bit: 9 Channel 1 Busy */
Kojto 111:4336505e4b1c 169 uint32_t CHBUSY2:1; /*!< bit: 10 Channel 2 Busy */
Kojto 111:4336505e4b1c 170 uint32_t CHBUSY3:1; /*!< bit: 11 Channel 3 Busy */
Kojto 111:4336505e4b1c 171 uint32_t CHBUSY4:1; /*!< bit: 12 Channel 4 Busy */
Kojto 111:4336505e4b1c 172 uint32_t CHBUSY5:1; /*!< bit: 13 Channel 5 Busy */
Kojto 111:4336505e4b1c 173 uint32_t CHBUSY6:1; /*!< bit: 14 Channel 6 Busy */
Kojto 111:4336505e4b1c 174 uint32_t CHBUSY7:1; /*!< bit: 15 Channel 7 Busy */
Kojto 111:4336505e4b1c 175 uint32_t USRRDY8:1; /*!< bit: 16 Channel 8 User Ready */
Kojto 111:4336505e4b1c 176 uint32_t USRRDY9:1; /*!< bit: 17 Channel 9 User Ready */
Kojto 111:4336505e4b1c 177 uint32_t USRRDY10:1; /*!< bit: 18 Channel 10 User Ready */
Kojto 111:4336505e4b1c 178 uint32_t USRRDY11:1; /*!< bit: 19 Channel 11 User Ready */
Kojto 111:4336505e4b1c 179 uint32_t :4; /*!< bit: 20..23 Reserved */
Kojto 111:4336505e4b1c 180 uint32_t CHBUSY8:1; /*!< bit: 24 Channel 8 Busy */
Kojto 111:4336505e4b1c 181 uint32_t CHBUSY9:1; /*!< bit: 25 Channel 9 Busy */
Kojto 111:4336505e4b1c 182 uint32_t CHBUSY10:1; /*!< bit: 26 Channel 10 Busy */
Kojto 111:4336505e4b1c 183 uint32_t CHBUSY11:1; /*!< bit: 27 Channel 11 Busy */
Kojto 111:4336505e4b1c 184 uint32_t :4; /*!< bit: 28..31 Reserved */
Kojto 111:4336505e4b1c 185 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 186 struct {
Kojto 111:4336505e4b1c 187 uint32_t USRRDY:8; /*!< bit: 0.. 7 Channel x User Ready */
Kojto 111:4336505e4b1c 188 uint32_t CHBUSY:8; /*!< bit: 8..15 Channel x Busy */
Kojto 111:4336505e4b1c 189 uint32_t USRRDYp8:4; /*!< bit: 16..19 Channel x+8 User Ready */
Kojto 111:4336505e4b1c 190 uint32_t :4; /*!< bit: 20..23 Reserved */
Kojto 111:4336505e4b1c 191 uint32_t CHBUSYp8:4; /*!< bit: 24..27 Channel x+8 Busy */
Kojto 111:4336505e4b1c 192 uint32_t :4; /*!< bit: 28..31 Reserved */
Kojto 111:4336505e4b1c 193 } vec; /*!< Structure used for vec access */
Kojto 111:4336505e4b1c 194 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 195 } EVSYS_CHSTATUS_Type;
Kojto 111:4336505e4b1c 196 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 197
Kojto 111:4336505e4b1c 198 #define EVSYS_CHSTATUS_OFFSET 0x0C /**< \brief (EVSYS_CHSTATUS offset) Channel Status */
Kojto 111:4336505e4b1c 199 #define EVSYS_CHSTATUS_RESETVALUE 0x000F00FFul /**< \brief (EVSYS_CHSTATUS reset_value) Channel Status */
Kojto 111:4336505e4b1c 200
Kojto 111:4336505e4b1c 201 #define EVSYS_CHSTATUS_USRRDY0_Pos 0 /**< \brief (EVSYS_CHSTATUS) Channel 0 User Ready */
Kojto 111:4336505e4b1c 202 #define EVSYS_CHSTATUS_USRRDY0 (1 << EVSYS_CHSTATUS_USRRDY0_Pos)
Kojto 111:4336505e4b1c 203 #define EVSYS_CHSTATUS_USRRDY1_Pos 1 /**< \brief (EVSYS_CHSTATUS) Channel 1 User Ready */
Kojto 111:4336505e4b1c 204 #define EVSYS_CHSTATUS_USRRDY1 (1 << EVSYS_CHSTATUS_USRRDY1_Pos)
Kojto 111:4336505e4b1c 205 #define EVSYS_CHSTATUS_USRRDY2_Pos 2 /**< \brief (EVSYS_CHSTATUS) Channel 2 User Ready */
Kojto 111:4336505e4b1c 206 #define EVSYS_CHSTATUS_USRRDY2 (1 << EVSYS_CHSTATUS_USRRDY2_Pos)
Kojto 111:4336505e4b1c 207 #define EVSYS_CHSTATUS_USRRDY3_Pos 3 /**< \brief (EVSYS_CHSTATUS) Channel 3 User Ready */
Kojto 111:4336505e4b1c 208 #define EVSYS_CHSTATUS_USRRDY3 (1 << EVSYS_CHSTATUS_USRRDY3_Pos)
Kojto 111:4336505e4b1c 209 #define EVSYS_CHSTATUS_USRRDY4_Pos 4 /**< \brief (EVSYS_CHSTATUS) Channel 4 User Ready */
Kojto 111:4336505e4b1c 210 #define EVSYS_CHSTATUS_USRRDY4 (1 << EVSYS_CHSTATUS_USRRDY4_Pos)
Kojto 111:4336505e4b1c 211 #define EVSYS_CHSTATUS_USRRDY5_Pos 5 /**< \brief (EVSYS_CHSTATUS) Channel 5 User Ready */
Kojto 111:4336505e4b1c 212 #define EVSYS_CHSTATUS_USRRDY5 (1 << EVSYS_CHSTATUS_USRRDY5_Pos)
Kojto 111:4336505e4b1c 213 #define EVSYS_CHSTATUS_USRRDY6_Pos 6 /**< \brief (EVSYS_CHSTATUS) Channel 6 User Ready */
Kojto 111:4336505e4b1c 214 #define EVSYS_CHSTATUS_USRRDY6 (1 << EVSYS_CHSTATUS_USRRDY6_Pos)
Kojto 111:4336505e4b1c 215 #define EVSYS_CHSTATUS_USRRDY7_Pos 7 /**< \brief (EVSYS_CHSTATUS) Channel 7 User Ready */
Kojto 111:4336505e4b1c 216 #define EVSYS_CHSTATUS_USRRDY7 (1 << EVSYS_CHSTATUS_USRRDY7_Pos)
Kojto 111:4336505e4b1c 217 #define EVSYS_CHSTATUS_USRRDY_Pos 0 /**< \brief (EVSYS_CHSTATUS) Channel x User Ready */
Kojto 111:4336505e4b1c 218 #define EVSYS_CHSTATUS_USRRDY_Msk (0xFFul << EVSYS_CHSTATUS_USRRDY_Pos)
Kojto 111:4336505e4b1c 219 #define EVSYS_CHSTATUS_USRRDY(value) (EVSYS_CHSTATUS_USRRDY_Msk & ((value) << EVSYS_CHSTATUS_USRRDY_Pos))
Kojto 111:4336505e4b1c 220 #define EVSYS_CHSTATUS_CHBUSY0_Pos 8 /**< \brief (EVSYS_CHSTATUS) Channel 0 Busy */
Kojto 111:4336505e4b1c 221 #define EVSYS_CHSTATUS_CHBUSY0 (1 << EVSYS_CHSTATUS_CHBUSY0_Pos)
Kojto 111:4336505e4b1c 222 #define EVSYS_CHSTATUS_CHBUSY1_Pos 9 /**< \brief (EVSYS_CHSTATUS) Channel 1 Busy */
Kojto 111:4336505e4b1c 223 #define EVSYS_CHSTATUS_CHBUSY1 (1 << EVSYS_CHSTATUS_CHBUSY1_Pos)
Kojto 111:4336505e4b1c 224 #define EVSYS_CHSTATUS_CHBUSY2_Pos 10 /**< \brief (EVSYS_CHSTATUS) Channel 2 Busy */
Kojto 111:4336505e4b1c 225 #define EVSYS_CHSTATUS_CHBUSY2 (1 << EVSYS_CHSTATUS_CHBUSY2_Pos)
Kojto 111:4336505e4b1c 226 #define EVSYS_CHSTATUS_CHBUSY3_Pos 11 /**< \brief (EVSYS_CHSTATUS) Channel 3 Busy */
Kojto 111:4336505e4b1c 227 #define EVSYS_CHSTATUS_CHBUSY3 (1 << EVSYS_CHSTATUS_CHBUSY3_Pos)
Kojto 111:4336505e4b1c 228 #define EVSYS_CHSTATUS_CHBUSY4_Pos 12 /**< \brief (EVSYS_CHSTATUS) Channel 4 Busy */
Kojto 111:4336505e4b1c 229 #define EVSYS_CHSTATUS_CHBUSY4 (1 << EVSYS_CHSTATUS_CHBUSY4_Pos)
Kojto 111:4336505e4b1c 230 #define EVSYS_CHSTATUS_CHBUSY5_Pos 13 /**< \brief (EVSYS_CHSTATUS) Channel 5 Busy */
Kojto 111:4336505e4b1c 231 #define EVSYS_CHSTATUS_CHBUSY5 (1 << EVSYS_CHSTATUS_CHBUSY5_Pos)
Kojto 111:4336505e4b1c 232 #define EVSYS_CHSTATUS_CHBUSY6_Pos 14 /**< \brief (EVSYS_CHSTATUS) Channel 6 Busy */
Kojto 111:4336505e4b1c 233 #define EVSYS_CHSTATUS_CHBUSY6 (1 << EVSYS_CHSTATUS_CHBUSY6_Pos)
Kojto 111:4336505e4b1c 234 #define EVSYS_CHSTATUS_CHBUSY7_Pos 15 /**< \brief (EVSYS_CHSTATUS) Channel 7 Busy */
Kojto 111:4336505e4b1c 235 #define EVSYS_CHSTATUS_CHBUSY7 (1 << EVSYS_CHSTATUS_CHBUSY7_Pos)
Kojto 111:4336505e4b1c 236 #define EVSYS_CHSTATUS_CHBUSY_Pos 8 /**< \brief (EVSYS_CHSTATUS) Channel x Busy */
Kojto 111:4336505e4b1c 237 #define EVSYS_CHSTATUS_CHBUSY_Msk (0xFFul << EVSYS_CHSTATUS_CHBUSY_Pos)
Kojto 111:4336505e4b1c 238 #define EVSYS_CHSTATUS_CHBUSY(value) (EVSYS_CHSTATUS_CHBUSY_Msk & ((value) << EVSYS_CHSTATUS_CHBUSY_Pos))
Kojto 111:4336505e4b1c 239 #define EVSYS_CHSTATUS_USRRDY8_Pos 16 /**< \brief (EVSYS_CHSTATUS) Channel 8 User Ready */
Kojto 111:4336505e4b1c 240 #define EVSYS_CHSTATUS_USRRDY8 (1 << EVSYS_CHSTATUS_USRRDY8_Pos)
Kojto 111:4336505e4b1c 241 #define EVSYS_CHSTATUS_USRRDY9_Pos 17 /**< \brief (EVSYS_CHSTATUS) Channel 9 User Ready */
Kojto 111:4336505e4b1c 242 #define EVSYS_CHSTATUS_USRRDY9 (1 << EVSYS_CHSTATUS_USRRDY9_Pos)
Kojto 111:4336505e4b1c 243 #define EVSYS_CHSTATUS_USRRDY10_Pos 18 /**< \brief (EVSYS_CHSTATUS) Channel 10 User Ready */
Kojto 111:4336505e4b1c 244 #define EVSYS_CHSTATUS_USRRDY10 (1 << EVSYS_CHSTATUS_USRRDY10_Pos)
Kojto 111:4336505e4b1c 245 #define EVSYS_CHSTATUS_USRRDY11_Pos 19 /**< \brief (EVSYS_CHSTATUS) Channel 11 User Ready */
Kojto 111:4336505e4b1c 246 #define EVSYS_CHSTATUS_USRRDY11 (1 << EVSYS_CHSTATUS_USRRDY11_Pos)
Kojto 111:4336505e4b1c 247 #define EVSYS_CHSTATUS_USRRDYp8_Pos 16 /**< \brief (EVSYS_CHSTATUS) Channel x+8 User Ready */
Kojto 111:4336505e4b1c 248 #define EVSYS_CHSTATUS_USRRDYp8_Msk (0xFul << EVSYS_CHSTATUS_USRRDYp8_Pos)
Kojto 111:4336505e4b1c 249 #define EVSYS_CHSTATUS_USRRDYp8(value) (EVSYS_CHSTATUS_USRRDYp8_Msk & ((value) << EVSYS_CHSTATUS_USRRDYp8_Pos))
Kojto 111:4336505e4b1c 250 #define EVSYS_CHSTATUS_CHBUSY8_Pos 24 /**< \brief (EVSYS_CHSTATUS) Channel 8 Busy */
Kojto 111:4336505e4b1c 251 #define EVSYS_CHSTATUS_CHBUSY8 (1 << EVSYS_CHSTATUS_CHBUSY8_Pos)
Kojto 111:4336505e4b1c 252 #define EVSYS_CHSTATUS_CHBUSY9_Pos 25 /**< \brief (EVSYS_CHSTATUS) Channel 9 Busy */
Kojto 111:4336505e4b1c 253 #define EVSYS_CHSTATUS_CHBUSY9 (1 << EVSYS_CHSTATUS_CHBUSY9_Pos)
Kojto 111:4336505e4b1c 254 #define EVSYS_CHSTATUS_CHBUSY10_Pos 26 /**< \brief (EVSYS_CHSTATUS) Channel 10 Busy */
Kojto 111:4336505e4b1c 255 #define EVSYS_CHSTATUS_CHBUSY10 (1 << EVSYS_CHSTATUS_CHBUSY10_Pos)
Kojto 111:4336505e4b1c 256 #define EVSYS_CHSTATUS_CHBUSY11_Pos 27 /**< \brief (EVSYS_CHSTATUS) Channel 11 Busy */
Kojto 111:4336505e4b1c 257 #define EVSYS_CHSTATUS_CHBUSY11 (1 << EVSYS_CHSTATUS_CHBUSY11_Pos)
Kojto 111:4336505e4b1c 258 #define EVSYS_CHSTATUS_CHBUSYp8_Pos 24 /**< \brief (EVSYS_CHSTATUS) Channel x+8 Busy */
Kojto 111:4336505e4b1c 259 #define EVSYS_CHSTATUS_CHBUSYp8_Msk (0xFul << EVSYS_CHSTATUS_CHBUSYp8_Pos)
Kojto 111:4336505e4b1c 260 #define EVSYS_CHSTATUS_CHBUSYp8(value) (EVSYS_CHSTATUS_CHBUSYp8_Msk & ((value) << EVSYS_CHSTATUS_CHBUSYp8_Pos))
Kojto 111:4336505e4b1c 261 #define EVSYS_CHSTATUS_MASK 0x0F0FFFFFul /**< \brief (EVSYS_CHSTATUS) MASK Register */
Kojto 111:4336505e4b1c 262
Kojto 111:4336505e4b1c 263 /* -------- EVSYS_INTENCLR : (EVSYS Offset: 0x10) (R/W 32) Interrupt Enable Clear -------- */
Kojto 111:4336505e4b1c 264 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 265 typedef union {
Kojto 111:4336505e4b1c 266 struct {
Kojto 111:4336505e4b1c 267 uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun Interrupt Enable */
Kojto 111:4336505e4b1c 268 uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun Interrupt Enable */
Kojto 111:4336505e4b1c 269 uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun Interrupt Enable */
Kojto 111:4336505e4b1c 270 uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */
Kojto 111:4336505e4b1c 271 uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */
Kojto 111:4336505e4b1c 272 uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */
Kojto 111:4336505e4b1c 273 uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */
Kojto 111:4336505e4b1c 274 uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */
Kojto 111:4336505e4b1c 275 uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection Interrupt Enable */
Kojto 111:4336505e4b1c 276 uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection Interrupt Enable */
Kojto 111:4336505e4b1c 277 uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection Interrupt Enable */
Kojto 111:4336505e4b1c 278 uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection Interrupt Enable */
Kojto 111:4336505e4b1c 279 uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection Interrupt Enable */
Kojto 111:4336505e4b1c 280 uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection Interrupt Enable */
Kojto 111:4336505e4b1c 281 uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection Interrupt Enable */
Kojto 111:4336505e4b1c 282 uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection Interrupt Enable */
Kojto 111:4336505e4b1c 283 uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun Interrupt Enable */
Kojto 111:4336505e4b1c 284 uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun Interrupt Enable */
Kojto 111:4336505e4b1c 285 uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun Interrupt Enable */
Kojto 111:4336505e4b1c 286 uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun Interrupt Enable */
Kojto 111:4336505e4b1c 287 uint32_t :4; /*!< bit: 20..23 Reserved */
Kojto 111:4336505e4b1c 288 uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection Interrupt Enable */
Kojto 111:4336505e4b1c 289 uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection Interrupt Enable */
Kojto 111:4336505e4b1c 290 uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection Interrupt Enable */
Kojto 111:4336505e4b1c 291 uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection Interrupt Enable */
Kojto 111:4336505e4b1c 292 uint32_t :4; /*!< bit: 28..31 Reserved */
Kojto 111:4336505e4b1c 293 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 294 struct {
Kojto 111:4336505e4b1c 295 uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun Interrupt Enable */
Kojto 111:4336505e4b1c 296 uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection Interrupt Enable */
Kojto 111:4336505e4b1c 297 uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun Interrupt Enable */
Kojto 111:4336505e4b1c 298 uint32_t :4; /*!< bit: 20..23 Reserved */
Kojto 111:4336505e4b1c 299 uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection Interrupt Enable */
Kojto 111:4336505e4b1c 300 uint32_t :4; /*!< bit: 28..31 Reserved */
Kojto 111:4336505e4b1c 301 } vec; /*!< Structure used for vec access */
Kojto 111:4336505e4b1c 302 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 303 } EVSYS_INTENCLR_Type;
Kojto 111:4336505e4b1c 304 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 305
Kojto 111:4336505e4b1c 306 #define EVSYS_INTENCLR_OFFSET 0x10 /**< \brief (EVSYS_INTENCLR offset) Interrupt Enable Clear */
Kojto 111:4336505e4b1c 307 #define EVSYS_INTENCLR_RESETVALUE 0x00000000ul /**< \brief (EVSYS_INTENCLR reset_value) Interrupt Enable Clear */
Kojto 111:4336505e4b1c 308
Kojto 111:4336505e4b1c 309 #define EVSYS_INTENCLR_OVR0_Pos 0 /**< \brief (EVSYS_INTENCLR) Channel 0 Overrun Interrupt Enable */
Kojto 111:4336505e4b1c 310 #define EVSYS_INTENCLR_OVR0 (1 << EVSYS_INTENCLR_OVR0_Pos)
Kojto 111:4336505e4b1c 311 #define EVSYS_INTENCLR_OVR1_Pos 1 /**< \brief (EVSYS_INTENCLR) Channel 1 Overrun Interrupt Enable */
Kojto 111:4336505e4b1c 312 #define EVSYS_INTENCLR_OVR1 (1 << EVSYS_INTENCLR_OVR1_Pos)
Kojto 111:4336505e4b1c 313 #define EVSYS_INTENCLR_OVR2_Pos 2 /**< \brief (EVSYS_INTENCLR) Channel 2 Overrun Interrupt Enable */
Kojto 111:4336505e4b1c 314 #define EVSYS_INTENCLR_OVR2 (1 << EVSYS_INTENCLR_OVR2_Pos)
Kojto 111:4336505e4b1c 315 #define EVSYS_INTENCLR_OVR3_Pos 3 /**< \brief (EVSYS_INTENCLR) Channel 3 Overrun Interrupt Enable */
Kojto 111:4336505e4b1c 316 #define EVSYS_INTENCLR_OVR3 (1 << EVSYS_INTENCLR_OVR3_Pos)
Kojto 111:4336505e4b1c 317 #define EVSYS_INTENCLR_OVR4_Pos 4 /**< \brief (EVSYS_INTENCLR) Channel 4 Overrun Interrupt Enable */
Kojto 111:4336505e4b1c 318 #define EVSYS_INTENCLR_OVR4 (1 << EVSYS_INTENCLR_OVR4_Pos)
Kojto 111:4336505e4b1c 319 #define EVSYS_INTENCLR_OVR5_Pos 5 /**< \brief (EVSYS_INTENCLR) Channel 5 Overrun Interrupt Enable */
Kojto 111:4336505e4b1c 320 #define EVSYS_INTENCLR_OVR5 (1 << EVSYS_INTENCLR_OVR5_Pos)
Kojto 111:4336505e4b1c 321 #define EVSYS_INTENCLR_OVR6_Pos 6 /**< \brief (EVSYS_INTENCLR) Channel 6 Overrun Interrupt Enable */
Kojto 111:4336505e4b1c 322 #define EVSYS_INTENCLR_OVR6 (1 << EVSYS_INTENCLR_OVR6_Pos)
Kojto 111:4336505e4b1c 323 #define EVSYS_INTENCLR_OVR7_Pos 7 /**< \brief (EVSYS_INTENCLR) Channel 7 Overrun Interrupt Enable */
Kojto 111:4336505e4b1c 324 #define EVSYS_INTENCLR_OVR7 (1 << EVSYS_INTENCLR_OVR7_Pos)
Kojto 111:4336505e4b1c 325 #define EVSYS_INTENCLR_OVR_Pos 0 /**< \brief (EVSYS_INTENCLR) Channel x Overrun Interrupt Enable */
Kojto 111:4336505e4b1c 326 #define EVSYS_INTENCLR_OVR_Msk (0xFFul << EVSYS_INTENCLR_OVR_Pos)
Kojto 111:4336505e4b1c 327 #define EVSYS_INTENCLR_OVR(value) (EVSYS_INTENCLR_OVR_Msk & ((value) << EVSYS_INTENCLR_OVR_Pos))
Kojto 111:4336505e4b1c 328 #define EVSYS_INTENCLR_EVD0_Pos 8 /**< \brief (EVSYS_INTENCLR) Channel 0 Event Detection Interrupt Enable */
Kojto 111:4336505e4b1c 329 #define EVSYS_INTENCLR_EVD0 (1 << EVSYS_INTENCLR_EVD0_Pos)
Kojto 111:4336505e4b1c 330 #define EVSYS_INTENCLR_EVD1_Pos 9 /**< \brief (EVSYS_INTENCLR) Channel 1 Event Detection Interrupt Enable */
Kojto 111:4336505e4b1c 331 #define EVSYS_INTENCLR_EVD1 (1 << EVSYS_INTENCLR_EVD1_Pos)
Kojto 111:4336505e4b1c 332 #define EVSYS_INTENCLR_EVD2_Pos 10 /**< \brief (EVSYS_INTENCLR) Channel 2 Event Detection Interrupt Enable */
Kojto 111:4336505e4b1c 333 #define EVSYS_INTENCLR_EVD2 (1 << EVSYS_INTENCLR_EVD2_Pos)
Kojto 111:4336505e4b1c 334 #define EVSYS_INTENCLR_EVD3_Pos 11 /**< \brief (EVSYS_INTENCLR) Channel 3 Event Detection Interrupt Enable */
Kojto 111:4336505e4b1c 335 #define EVSYS_INTENCLR_EVD3 (1 << EVSYS_INTENCLR_EVD3_Pos)
Kojto 111:4336505e4b1c 336 #define EVSYS_INTENCLR_EVD4_Pos 12 /**< \brief (EVSYS_INTENCLR) Channel 4 Event Detection Interrupt Enable */
Kojto 111:4336505e4b1c 337 #define EVSYS_INTENCLR_EVD4 (1 << EVSYS_INTENCLR_EVD4_Pos)
Kojto 111:4336505e4b1c 338 #define EVSYS_INTENCLR_EVD5_Pos 13 /**< \brief (EVSYS_INTENCLR) Channel 5 Event Detection Interrupt Enable */
Kojto 111:4336505e4b1c 339 #define EVSYS_INTENCLR_EVD5 (1 << EVSYS_INTENCLR_EVD5_Pos)
Kojto 111:4336505e4b1c 340 #define EVSYS_INTENCLR_EVD6_Pos 14 /**< \brief (EVSYS_INTENCLR) Channel 6 Event Detection Interrupt Enable */
Kojto 111:4336505e4b1c 341 #define EVSYS_INTENCLR_EVD6 (1 << EVSYS_INTENCLR_EVD6_Pos)
Kojto 111:4336505e4b1c 342 #define EVSYS_INTENCLR_EVD7_Pos 15 /**< \brief (EVSYS_INTENCLR) Channel 7 Event Detection Interrupt Enable */
Kojto 111:4336505e4b1c 343 #define EVSYS_INTENCLR_EVD7 (1 << EVSYS_INTENCLR_EVD7_Pos)
Kojto 111:4336505e4b1c 344 #define EVSYS_INTENCLR_EVD_Pos 8 /**< \brief (EVSYS_INTENCLR) Channel x Event Detection Interrupt Enable */
Kojto 111:4336505e4b1c 345 #define EVSYS_INTENCLR_EVD_Msk (0xFFul << EVSYS_INTENCLR_EVD_Pos)
Kojto 111:4336505e4b1c 346 #define EVSYS_INTENCLR_EVD(value) (EVSYS_INTENCLR_EVD_Msk & ((value) << EVSYS_INTENCLR_EVD_Pos))
Kojto 111:4336505e4b1c 347 #define EVSYS_INTENCLR_OVR8_Pos 16 /**< \brief (EVSYS_INTENCLR) Channel 8 Overrun Interrupt Enable */
Kojto 111:4336505e4b1c 348 #define EVSYS_INTENCLR_OVR8 (1 << EVSYS_INTENCLR_OVR8_Pos)
Kojto 111:4336505e4b1c 349 #define EVSYS_INTENCLR_OVR9_Pos 17 /**< \brief (EVSYS_INTENCLR) Channel 9 Overrun Interrupt Enable */
Kojto 111:4336505e4b1c 350 #define EVSYS_INTENCLR_OVR9 (1 << EVSYS_INTENCLR_OVR9_Pos)
Kojto 111:4336505e4b1c 351 #define EVSYS_INTENCLR_OVR10_Pos 18 /**< \brief (EVSYS_INTENCLR) Channel 10 Overrun Interrupt Enable */
Kojto 111:4336505e4b1c 352 #define EVSYS_INTENCLR_OVR10 (1 << EVSYS_INTENCLR_OVR10_Pos)
Kojto 111:4336505e4b1c 353 #define EVSYS_INTENCLR_OVR11_Pos 19 /**< \brief (EVSYS_INTENCLR) Channel 11 Overrun Interrupt Enable */
Kojto 111:4336505e4b1c 354 #define EVSYS_INTENCLR_OVR11 (1 << EVSYS_INTENCLR_OVR11_Pos)
Kojto 111:4336505e4b1c 355 #define EVSYS_INTENCLR_OVRp8_Pos 16 /**< \brief (EVSYS_INTENCLR) Channel x+8 Overrun Interrupt Enable */
Kojto 111:4336505e4b1c 356 #define EVSYS_INTENCLR_OVRp8_Msk (0xFul << EVSYS_INTENCLR_OVRp8_Pos)
Kojto 111:4336505e4b1c 357 #define EVSYS_INTENCLR_OVRp8(value) (EVSYS_INTENCLR_OVRp8_Msk & ((value) << EVSYS_INTENCLR_OVRp8_Pos))
Kojto 111:4336505e4b1c 358 #define EVSYS_INTENCLR_EVD8_Pos 24 /**< \brief (EVSYS_INTENCLR) Channel 8 Event Detection Interrupt Enable */
Kojto 111:4336505e4b1c 359 #define EVSYS_INTENCLR_EVD8 (1 << EVSYS_INTENCLR_EVD8_Pos)
Kojto 111:4336505e4b1c 360 #define EVSYS_INTENCLR_EVD9_Pos 25 /**< \brief (EVSYS_INTENCLR) Channel 9 Event Detection Interrupt Enable */
Kojto 111:4336505e4b1c 361 #define EVSYS_INTENCLR_EVD9 (1 << EVSYS_INTENCLR_EVD9_Pos)
Kojto 111:4336505e4b1c 362 #define EVSYS_INTENCLR_EVD10_Pos 26 /**< \brief (EVSYS_INTENCLR) Channel 10 Event Detection Interrupt Enable */
Kojto 111:4336505e4b1c 363 #define EVSYS_INTENCLR_EVD10 (1 << EVSYS_INTENCLR_EVD10_Pos)
Kojto 111:4336505e4b1c 364 #define EVSYS_INTENCLR_EVD11_Pos 27 /**< \brief (EVSYS_INTENCLR) Channel 11 Event Detection Interrupt Enable */
Kojto 111:4336505e4b1c 365 #define EVSYS_INTENCLR_EVD11 (1 << EVSYS_INTENCLR_EVD11_Pos)
Kojto 111:4336505e4b1c 366 #define EVSYS_INTENCLR_EVDp8_Pos 24 /**< \brief (EVSYS_INTENCLR) Channel x+8 Event Detection Interrupt Enable */
Kojto 111:4336505e4b1c 367 #define EVSYS_INTENCLR_EVDp8_Msk (0xFul << EVSYS_INTENCLR_EVDp8_Pos)
Kojto 111:4336505e4b1c 368 #define EVSYS_INTENCLR_EVDp8(value) (EVSYS_INTENCLR_EVDp8_Msk & ((value) << EVSYS_INTENCLR_EVDp8_Pos))
Kojto 111:4336505e4b1c 369 #define EVSYS_INTENCLR_MASK 0x0F0FFFFFul /**< \brief (EVSYS_INTENCLR) MASK Register */
Kojto 111:4336505e4b1c 370
Kojto 111:4336505e4b1c 371 /* -------- EVSYS_INTENSET : (EVSYS Offset: 0x14) (R/W 32) Interrupt Enable Set -------- */
Kojto 111:4336505e4b1c 372 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 373 typedef union {
Kojto 111:4336505e4b1c 374 struct {
Kojto 111:4336505e4b1c 375 uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun Interrupt Enable */
Kojto 111:4336505e4b1c 376 uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun Interrupt Enable */
Kojto 111:4336505e4b1c 377 uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun Interrupt Enable */
Kojto 111:4336505e4b1c 378 uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */
Kojto 111:4336505e4b1c 379 uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */
Kojto 111:4336505e4b1c 380 uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */
Kojto 111:4336505e4b1c 381 uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */
Kojto 111:4336505e4b1c 382 uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */
Kojto 111:4336505e4b1c 383 uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection Interrupt Enable */
Kojto 111:4336505e4b1c 384 uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection Interrupt Enable */
Kojto 111:4336505e4b1c 385 uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection Interrupt Enable */
Kojto 111:4336505e4b1c 386 uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection Interrupt Enable */
Kojto 111:4336505e4b1c 387 uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection Interrupt Enable */
Kojto 111:4336505e4b1c 388 uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection Interrupt Enable */
Kojto 111:4336505e4b1c 389 uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection Interrupt Enable */
Kojto 111:4336505e4b1c 390 uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection Interrupt Enable */
Kojto 111:4336505e4b1c 391 uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun Interrupt Enable */
Kojto 111:4336505e4b1c 392 uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun Interrupt Enable */
Kojto 111:4336505e4b1c 393 uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun Interrupt Enable */
Kojto 111:4336505e4b1c 394 uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun Interrupt Enable */
Kojto 111:4336505e4b1c 395 uint32_t :4; /*!< bit: 20..23 Reserved */
Kojto 111:4336505e4b1c 396 uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection Interrupt Enable */
Kojto 111:4336505e4b1c 397 uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection Interrupt Enable */
Kojto 111:4336505e4b1c 398 uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection Interrupt Enable */
Kojto 111:4336505e4b1c 399 uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection Interrupt Enable */
Kojto 111:4336505e4b1c 400 uint32_t :4; /*!< bit: 28..31 Reserved */
Kojto 111:4336505e4b1c 401 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 402 struct {
Kojto 111:4336505e4b1c 403 uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun Interrupt Enable */
Kojto 111:4336505e4b1c 404 uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection Interrupt Enable */
Kojto 111:4336505e4b1c 405 uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun Interrupt Enable */
Kojto 111:4336505e4b1c 406 uint32_t :4; /*!< bit: 20..23 Reserved */
Kojto 111:4336505e4b1c 407 uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection Interrupt Enable */
Kojto 111:4336505e4b1c 408 uint32_t :4; /*!< bit: 28..31 Reserved */
Kojto 111:4336505e4b1c 409 } vec; /*!< Structure used for vec access */
Kojto 111:4336505e4b1c 410 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 411 } EVSYS_INTENSET_Type;
Kojto 111:4336505e4b1c 412 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 413
Kojto 111:4336505e4b1c 414 #define EVSYS_INTENSET_OFFSET 0x14 /**< \brief (EVSYS_INTENSET offset) Interrupt Enable Set */
Kojto 111:4336505e4b1c 415 #define EVSYS_INTENSET_RESETVALUE 0x00000000ul /**< \brief (EVSYS_INTENSET reset_value) Interrupt Enable Set */
Kojto 111:4336505e4b1c 416
Kojto 111:4336505e4b1c 417 #define EVSYS_INTENSET_OVR0_Pos 0 /**< \brief (EVSYS_INTENSET) Channel 0 Overrun Interrupt Enable */
Kojto 111:4336505e4b1c 418 #define EVSYS_INTENSET_OVR0 (1 << EVSYS_INTENSET_OVR0_Pos)
Kojto 111:4336505e4b1c 419 #define EVSYS_INTENSET_OVR1_Pos 1 /**< \brief (EVSYS_INTENSET) Channel 1 Overrun Interrupt Enable */
Kojto 111:4336505e4b1c 420 #define EVSYS_INTENSET_OVR1 (1 << EVSYS_INTENSET_OVR1_Pos)
Kojto 111:4336505e4b1c 421 #define EVSYS_INTENSET_OVR2_Pos 2 /**< \brief (EVSYS_INTENSET) Channel 2 Overrun Interrupt Enable */
Kojto 111:4336505e4b1c 422 #define EVSYS_INTENSET_OVR2 (1 << EVSYS_INTENSET_OVR2_Pos)
Kojto 111:4336505e4b1c 423 #define EVSYS_INTENSET_OVR3_Pos 3 /**< \brief (EVSYS_INTENSET) Channel 3 Overrun Interrupt Enable */
Kojto 111:4336505e4b1c 424 #define EVSYS_INTENSET_OVR3 (1 << EVSYS_INTENSET_OVR3_Pos)
Kojto 111:4336505e4b1c 425 #define EVSYS_INTENSET_OVR4_Pos 4 /**< \brief (EVSYS_INTENSET) Channel 4 Overrun Interrupt Enable */
Kojto 111:4336505e4b1c 426 #define EVSYS_INTENSET_OVR4 (1 << EVSYS_INTENSET_OVR4_Pos)
Kojto 111:4336505e4b1c 427 #define EVSYS_INTENSET_OVR5_Pos 5 /**< \brief (EVSYS_INTENSET) Channel 5 Overrun Interrupt Enable */
Kojto 111:4336505e4b1c 428 #define EVSYS_INTENSET_OVR5 (1 << EVSYS_INTENSET_OVR5_Pos)
Kojto 111:4336505e4b1c 429 #define EVSYS_INTENSET_OVR6_Pos 6 /**< \brief (EVSYS_INTENSET) Channel 6 Overrun Interrupt Enable */
Kojto 111:4336505e4b1c 430 #define EVSYS_INTENSET_OVR6 (1 << EVSYS_INTENSET_OVR6_Pos)
Kojto 111:4336505e4b1c 431 #define EVSYS_INTENSET_OVR7_Pos 7 /**< \brief (EVSYS_INTENSET) Channel 7 Overrun Interrupt Enable */
Kojto 111:4336505e4b1c 432 #define EVSYS_INTENSET_OVR7 (1 << EVSYS_INTENSET_OVR7_Pos)
Kojto 111:4336505e4b1c 433 #define EVSYS_INTENSET_OVR_Pos 0 /**< \brief (EVSYS_INTENSET) Channel x Overrun Interrupt Enable */
Kojto 111:4336505e4b1c 434 #define EVSYS_INTENSET_OVR_Msk (0xFFul << EVSYS_INTENSET_OVR_Pos)
Kojto 111:4336505e4b1c 435 #define EVSYS_INTENSET_OVR(value) (EVSYS_INTENSET_OVR_Msk & ((value) << EVSYS_INTENSET_OVR_Pos))
Kojto 111:4336505e4b1c 436 #define EVSYS_INTENSET_EVD0_Pos 8 /**< \brief (EVSYS_INTENSET) Channel 0 Event Detection Interrupt Enable */
Kojto 111:4336505e4b1c 437 #define EVSYS_INTENSET_EVD0 (1 << EVSYS_INTENSET_EVD0_Pos)
Kojto 111:4336505e4b1c 438 #define EVSYS_INTENSET_EVD1_Pos 9 /**< \brief (EVSYS_INTENSET) Channel 1 Event Detection Interrupt Enable */
Kojto 111:4336505e4b1c 439 #define EVSYS_INTENSET_EVD1 (1 << EVSYS_INTENSET_EVD1_Pos)
Kojto 111:4336505e4b1c 440 #define EVSYS_INTENSET_EVD2_Pos 10 /**< \brief (EVSYS_INTENSET) Channel 2 Event Detection Interrupt Enable */
Kojto 111:4336505e4b1c 441 #define EVSYS_INTENSET_EVD2 (1 << EVSYS_INTENSET_EVD2_Pos)
Kojto 111:4336505e4b1c 442 #define EVSYS_INTENSET_EVD3_Pos 11 /**< \brief (EVSYS_INTENSET) Channel 3 Event Detection Interrupt Enable */
Kojto 111:4336505e4b1c 443 #define EVSYS_INTENSET_EVD3 (1 << EVSYS_INTENSET_EVD3_Pos)
Kojto 111:4336505e4b1c 444 #define EVSYS_INTENSET_EVD4_Pos 12 /**< \brief (EVSYS_INTENSET) Channel 4 Event Detection Interrupt Enable */
Kojto 111:4336505e4b1c 445 #define EVSYS_INTENSET_EVD4 (1 << EVSYS_INTENSET_EVD4_Pos)
Kojto 111:4336505e4b1c 446 #define EVSYS_INTENSET_EVD5_Pos 13 /**< \brief (EVSYS_INTENSET) Channel 5 Event Detection Interrupt Enable */
Kojto 111:4336505e4b1c 447 #define EVSYS_INTENSET_EVD5 (1 << EVSYS_INTENSET_EVD5_Pos)
Kojto 111:4336505e4b1c 448 #define EVSYS_INTENSET_EVD6_Pos 14 /**< \brief (EVSYS_INTENSET) Channel 6 Event Detection Interrupt Enable */
Kojto 111:4336505e4b1c 449 #define EVSYS_INTENSET_EVD6 (1 << EVSYS_INTENSET_EVD6_Pos)
Kojto 111:4336505e4b1c 450 #define EVSYS_INTENSET_EVD7_Pos 15 /**< \brief (EVSYS_INTENSET) Channel 7 Event Detection Interrupt Enable */
Kojto 111:4336505e4b1c 451 #define EVSYS_INTENSET_EVD7 (1 << EVSYS_INTENSET_EVD7_Pos)
Kojto 111:4336505e4b1c 452 #define EVSYS_INTENSET_EVD_Pos 8 /**< \brief (EVSYS_INTENSET) Channel x Event Detection Interrupt Enable */
Kojto 111:4336505e4b1c 453 #define EVSYS_INTENSET_EVD_Msk (0xFFul << EVSYS_INTENSET_EVD_Pos)
Kojto 111:4336505e4b1c 454 #define EVSYS_INTENSET_EVD(value) (EVSYS_INTENSET_EVD_Msk & ((value) << EVSYS_INTENSET_EVD_Pos))
Kojto 111:4336505e4b1c 455 #define EVSYS_INTENSET_OVR8_Pos 16 /**< \brief (EVSYS_INTENSET) Channel 8 Overrun Interrupt Enable */
Kojto 111:4336505e4b1c 456 #define EVSYS_INTENSET_OVR8 (1 << EVSYS_INTENSET_OVR8_Pos)
Kojto 111:4336505e4b1c 457 #define EVSYS_INTENSET_OVR9_Pos 17 /**< \brief (EVSYS_INTENSET) Channel 9 Overrun Interrupt Enable */
Kojto 111:4336505e4b1c 458 #define EVSYS_INTENSET_OVR9 (1 << EVSYS_INTENSET_OVR9_Pos)
Kojto 111:4336505e4b1c 459 #define EVSYS_INTENSET_OVR10_Pos 18 /**< \brief (EVSYS_INTENSET) Channel 10 Overrun Interrupt Enable */
Kojto 111:4336505e4b1c 460 #define EVSYS_INTENSET_OVR10 (1 << EVSYS_INTENSET_OVR10_Pos)
Kojto 111:4336505e4b1c 461 #define EVSYS_INTENSET_OVR11_Pos 19 /**< \brief (EVSYS_INTENSET) Channel 11 Overrun Interrupt Enable */
Kojto 111:4336505e4b1c 462 #define EVSYS_INTENSET_OVR11 (1 << EVSYS_INTENSET_OVR11_Pos)
Kojto 111:4336505e4b1c 463 #define EVSYS_INTENSET_OVRp8_Pos 16 /**< \brief (EVSYS_INTENSET) Channel x+8 Overrun Interrupt Enable */
Kojto 111:4336505e4b1c 464 #define EVSYS_INTENSET_OVRp8_Msk (0xFul << EVSYS_INTENSET_OVRp8_Pos)
Kojto 111:4336505e4b1c 465 #define EVSYS_INTENSET_OVRp8(value) (EVSYS_INTENSET_OVRp8_Msk & ((value) << EVSYS_INTENSET_OVRp8_Pos))
Kojto 111:4336505e4b1c 466 #define EVSYS_INTENSET_EVD8_Pos 24 /**< \brief (EVSYS_INTENSET) Channel 8 Event Detection Interrupt Enable */
Kojto 111:4336505e4b1c 467 #define EVSYS_INTENSET_EVD8 (1 << EVSYS_INTENSET_EVD8_Pos)
Kojto 111:4336505e4b1c 468 #define EVSYS_INTENSET_EVD9_Pos 25 /**< \brief (EVSYS_INTENSET) Channel 9 Event Detection Interrupt Enable */
Kojto 111:4336505e4b1c 469 #define EVSYS_INTENSET_EVD9 (1 << EVSYS_INTENSET_EVD9_Pos)
Kojto 111:4336505e4b1c 470 #define EVSYS_INTENSET_EVD10_Pos 26 /**< \brief (EVSYS_INTENSET) Channel 10 Event Detection Interrupt Enable */
Kojto 111:4336505e4b1c 471 #define EVSYS_INTENSET_EVD10 (1 << EVSYS_INTENSET_EVD10_Pos)
Kojto 111:4336505e4b1c 472 #define EVSYS_INTENSET_EVD11_Pos 27 /**< \brief (EVSYS_INTENSET) Channel 11 Event Detection Interrupt Enable */
Kojto 111:4336505e4b1c 473 #define EVSYS_INTENSET_EVD11 (1 << EVSYS_INTENSET_EVD11_Pos)
Kojto 111:4336505e4b1c 474 #define EVSYS_INTENSET_EVDp8_Pos 24 /**< \brief (EVSYS_INTENSET) Channel x+8 Event Detection Interrupt Enable */
Kojto 111:4336505e4b1c 475 #define EVSYS_INTENSET_EVDp8_Msk (0xFul << EVSYS_INTENSET_EVDp8_Pos)
Kojto 111:4336505e4b1c 476 #define EVSYS_INTENSET_EVDp8(value) (EVSYS_INTENSET_EVDp8_Msk & ((value) << EVSYS_INTENSET_EVDp8_Pos))
Kojto 111:4336505e4b1c 477 #define EVSYS_INTENSET_MASK 0x0F0FFFFFul /**< \brief (EVSYS_INTENSET) MASK Register */
Kojto 111:4336505e4b1c 478
Kojto 111:4336505e4b1c 479 /* -------- EVSYS_INTFLAG : (EVSYS Offset: 0x18) (R/W 32) Interrupt Flag Status and Clear -------- */
Kojto 111:4336505e4b1c 480 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 481 typedef union { // __I to avoid read-modify-write on write-to-clear register
Kojto 111:4336505e4b1c 482 struct {
Kojto 111:4336505e4b1c 483 __I uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun */
Kojto 111:4336505e4b1c 484 __I uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun */
Kojto 111:4336505e4b1c 485 __I uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun */
Kojto 111:4336505e4b1c 486 __I uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun */
Kojto 111:4336505e4b1c 487 __I uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun */
Kojto 111:4336505e4b1c 488 __I uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun */
Kojto 111:4336505e4b1c 489 __I uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun */
Kojto 111:4336505e4b1c 490 __I uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun */
Kojto 111:4336505e4b1c 491 __I uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection */
Kojto 111:4336505e4b1c 492 __I uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection */
Kojto 111:4336505e4b1c 493 __I uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection */
Kojto 111:4336505e4b1c 494 __I uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection */
Kojto 111:4336505e4b1c 495 __I uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection */
Kojto 111:4336505e4b1c 496 __I uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection */
Kojto 111:4336505e4b1c 497 __I uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection */
Kojto 111:4336505e4b1c 498 __I uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection */
Kojto 111:4336505e4b1c 499 __I uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun */
Kojto 111:4336505e4b1c 500 __I uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun */
Kojto 111:4336505e4b1c 501 __I uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun */
Kojto 111:4336505e4b1c 502 __I uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun */
Kojto 111:4336505e4b1c 503 __I uint32_t :4; /*!< bit: 20..23 Reserved */
Kojto 111:4336505e4b1c 504 __I uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection */
Kojto 111:4336505e4b1c 505 __I uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection */
Kojto 111:4336505e4b1c 506 __I uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection */
Kojto 111:4336505e4b1c 507 __I uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection */
Kojto 111:4336505e4b1c 508 __I uint32_t :4; /*!< bit: 28..31 Reserved */
Kojto 111:4336505e4b1c 509 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 510 struct {
Kojto 111:4336505e4b1c 511 __I uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun */
Kojto 111:4336505e4b1c 512 __I uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection */
Kojto 111:4336505e4b1c 513 __I uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun */
Kojto 111:4336505e4b1c 514 __I uint32_t :4; /*!< bit: 20..23 Reserved */
Kojto 111:4336505e4b1c 515 __I uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection */
Kojto 111:4336505e4b1c 516 __I uint32_t :4; /*!< bit: 28..31 Reserved */
Kojto 111:4336505e4b1c 517 } vec; /*!< Structure used for vec access */
Kojto 111:4336505e4b1c 518 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 519 } EVSYS_INTFLAG_Type;
Kojto 111:4336505e4b1c 520 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 521
Kojto 111:4336505e4b1c 522 #define EVSYS_INTFLAG_OFFSET 0x18 /**< \brief (EVSYS_INTFLAG offset) Interrupt Flag Status and Clear */
Kojto 111:4336505e4b1c 523 #define EVSYS_INTFLAG_RESETVALUE 0x00000000ul /**< \brief (EVSYS_INTFLAG reset_value) Interrupt Flag Status and Clear */
Kojto 111:4336505e4b1c 524
Kojto 111:4336505e4b1c 525 #define EVSYS_INTFLAG_OVR0_Pos 0 /**< \brief (EVSYS_INTFLAG) Channel 0 Overrun */
Kojto 111:4336505e4b1c 526 #define EVSYS_INTFLAG_OVR0 (1 << EVSYS_INTFLAG_OVR0_Pos)
Kojto 111:4336505e4b1c 527 #define EVSYS_INTFLAG_OVR1_Pos 1 /**< \brief (EVSYS_INTFLAG) Channel 1 Overrun */
Kojto 111:4336505e4b1c 528 #define EVSYS_INTFLAG_OVR1 (1 << EVSYS_INTFLAG_OVR1_Pos)
Kojto 111:4336505e4b1c 529 #define EVSYS_INTFLAG_OVR2_Pos 2 /**< \brief (EVSYS_INTFLAG) Channel 2 Overrun */
Kojto 111:4336505e4b1c 530 #define EVSYS_INTFLAG_OVR2 (1 << EVSYS_INTFLAG_OVR2_Pos)
Kojto 111:4336505e4b1c 531 #define EVSYS_INTFLAG_OVR3_Pos 3 /**< \brief (EVSYS_INTFLAG) Channel 3 Overrun */
Kojto 111:4336505e4b1c 532 #define EVSYS_INTFLAG_OVR3 (1 << EVSYS_INTFLAG_OVR3_Pos)
Kojto 111:4336505e4b1c 533 #define EVSYS_INTFLAG_OVR4_Pos 4 /**< \brief (EVSYS_INTFLAG) Channel 4 Overrun */
Kojto 111:4336505e4b1c 534 #define EVSYS_INTFLAG_OVR4 (1 << EVSYS_INTFLAG_OVR4_Pos)
Kojto 111:4336505e4b1c 535 #define EVSYS_INTFLAG_OVR5_Pos 5 /**< \brief (EVSYS_INTFLAG) Channel 5 Overrun */
Kojto 111:4336505e4b1c 536 #define EVSYS_INTFLAG_OVR5 (1 << EVSYS_INTFLAG_OVR5_Pos)
Kojto 111:4336505e4b1c 537 #define EVSYS_INTFLAG_OVR6_Pos 6 /**< \brief (EVSYS_INTFLAG) Channel 6 Overrun */
Kojto 111:4336505e4b1c 538 #define EVSYS_INTFLAG_OVR6 (1 << EVSYS_INTFLAG_OVR6_Pos)
Kojto 111:4336505e4b1c 539 #define EVSYS_INTFLAG_OVR7_Pos 7 /**< \brief (EVSYS_INTFLAG) Channel 7 Overrun */
Kojto 111:4336505e4b1c 540 #define EVSYS_INTFLAG_OVR7 (1 << EVSYS_INTFLAG_OVR7_Pos)
Kojto 111:4336505e4b1c 541 #define EVSYS_INTFLAG_OVR_Pos 0 /**< \brief (EVSYS_INTFLAG) Channel x Overrun */
Kojto 111:4336505e4b1c 542 #define EVSYS_INTFLAG_OVR_Msk (0xFFul << EVSYS_INTFLAG_OVR_Pos)
Kojto 111:4336505e4b1c 543 #define EVSYS_INTFLAG_OVR(value) (EVSYS_INTFLAG_OVR_Msk & ((value) << EVSYS_INTFLAG_OVR_Pos))
Kojto 111:4336505e4b1c 544 #define EVSYS_INTFLAG_EVD0_Pos 8 /**< \brief (EVSYS_INTFLAG) Channel 0 Event Detection */
Kojto 111:4336505e4b1c 545 #define EVSYS_INTFLAG_EVD0 (1 << EVSYS_INTFLAG_EVD0_Pos)
Kojto 111:4336505e4b1c 546 #define EVSYS_INTFLAG_EVD1_Pos 9 /**< \brief (EVSYS_INTFLAG) Channel 1 Event Detection */
Kojto 111:4336505e4b1c 547 #define EVSYS_INTFLAG_EVD1 (1 << EVSYS_INTFLAG_EVD1_Pos)
Kojto 111:4336505e4b1c 548 #define EVSYS_INTFLAG_EVD2_Pos 10 /**< \brief (EVSYS_INTFLAG) Channel 2 Event Detection */
Kojto 111:4336505e4b1c 549 #define EVSYS_INTFLAG_EVD2 (1 << EVSYS_INTFLAG_EVD2_Pos)
Kojto 111:4336505e4b1c 550 #define EVSYS_INTFLAG_EVD3_Pos 11 /**< \brief (EVSYS_INTFLAG) Channel 3 Event Detection */
Kojto 111:4336505e4b1c 551 #define EVSYS_INTFLAG_EVD3 (1 << EVSYS_INTFLAG_EVD3_Pos)
Kojto 111:4336505e4b1c 552 #define EVSYS_INTFLAG_EVD4_Pos 12 /**< \brief (EVSYS_INTFLAG) Channel 4 Event Detection */
Kojto 111:4336505e4b1c 553 #define EVSYS_INTFLAG_EVD4 (1 << EVSYS_INTFLAG_EVD4_Pos)
Kojto 111:4336505e4b1c 554 #define EVSYS_INTFLAG_EVD5_Pos 13 /**< \brief (EVSYS_INTFLAG) Channel 5 Event Detection */
Kojto 111:4336505e4b1c 555 #define EVSYS_INTFLAG_EVD5 (1 << EVSYS_INTFLAG_EVD5_Pos)
Kojto 111:4336505e4b1c 556 #define EVSYS_INTFLAG_EVD6_Pos 14 /**< \brief (EVSYS_INTFLAG) Channel 6 Event Detection */
Kojto 111:4336505e4b1c 557 #define EVSYS_INTFLAG_EVD6 (1 << EVSYS_INTFLAG_EVD6_Pos)
Kojto 111:4336505e4b1c 558 #define EVSYS_INTFLAG_EVD7_Pos 15 /**< \brief (EVSYS_INTFLAG) Channel 7 Event Detection */
Kojto 111:4336505e4b1c 559 #define EVSYS_INTFLAG_EVD7 (1 << EVSYS_INTFLAG_EVD7_Pos)
Kojto 111:4336505e4b1c 560 #define EVSYS_INTFLAG_EVD_Pos 8 /**< \brief (EVSYS_INTFLAG) Channel x Event Detection */
Kojto 111:4336505e4b1c 561 #define EVSYS_INTFLAG_EVD_Msk (0xFFul << EVSYS_INTFLAG_EVD_Pos)
Kojto 111:4336505e4b1c 562 #define EVSYS_INTFLAG_EVD(value) (EVSYS_INTFLAG_EVD_Msk & ((value) << EVSYS_INTFLAG_EVD_Pos))
Kojto 111:4336505e4b1c 563 #define EVSYS_INTFLAG_OVR8_Pos 16 /**< \brief (EVSYS_INTFLAG) Channel 8 Overrun */
Kojto 111:4336505e4b1c 564 #define EVSYS_INTFLAG_OVR8 (1 << EVSYS_INTFLAG_OVR8_Pos)
Kojto 111:4336505e4b1c 565 #define EVSYS_INTFLAG_OVR9_Pos 17 /**< \brief (EVSYS_INTFLAG) Channel 9 Overrun */
Kojto 111:4336505e4b1c 566 #define EVSYS_INTFLAG_OVR9 (1 << EVSYS_INTFLAG_OVR9_Pos)
Kojto 111:4336505e4b1c 567 #define EVSYS_INTFLAG_OVR10_Pos 18 /**< \brief (EVSYS_INTFLAG) Channel 10 Overrun */
Kojto 111:4336505e4b1c 568 #define EVSYS_INTFLAG_OVR10 (1 << EVSYS_INTFLAG_OVR10_Pos)
Kojto 111:4336505e4b1c 569 #define EVSYS_INTFLAG_OVR11_Pos 19 /**< \brief (EVSYS_INTFLAG) Channel 11 Overrun */
Kojto 111:4336505e4b1c 570 #define EVSYS_INTFLAG_OVR11 (1 << EVSYS_INTFLAG_OVR11_Pos)
Kojto 111:4336505e4b1c 571 #define EVSYS_INTFLAG_OVRp8_Pos 16 /**< \brief (EVSYS_INTFLAG) Channel x+8 Overrun */
Kojto 111:4336505e4b1c 572 #define EVSYS_INTFLAG_OVRp8_Msk (0xFul << EVSYS_INTFLAG_OVRp8_Pos)
Kojto 111:4336505e4b1c 573 #define EVSYS_INTFLAG_OVRp8(value) (EVSYS_INTFLAG_OVRp8_Msk & ((value) << EVSYS_INTFLAG_OVRp8_Pos))
Kojto 111:4336505e4b1c 574 #define EVSYS_INTFLAG_EVD8_Pos 24 /**< \brief (EVSYS_INTFLAG) Channel 8 Event Detection */
Kojto 111:4336505e4b1c 575 #define EVSYS_INTFLAG_EVD8 (1 << EVSYS_INTFLAG_EVD8_Pos)
Kojto 111:4336505e4b1c 576 #define EVSYS_INTFLAG_EVD9_Pos 25 /**< \brief (EVSYS_INTFLAG) Channel 9 Event Detection */
Kojto 111:4336505e4b1c 577 #define EVSYS_INTFLAG_EVD9 (1 << EVSYS_INTFLAG_EVD9_Pos)
Kojto 111:4336505e4b1c 578 #define EVSYS_INTFLAG_EVD10_Pos 26 /**< \brief (EVSYS_INTFLAG) Channel 10 Event Detection */
Kojto 111:4336505e4b1c 579 #define EVSYS_INTFLAG_EVD10 (1 << EVSYS_INTFLAG_EVD10_Pos)
Kojto 111:4336505e4b1c 580 #define EVSYS_INTFLAG_EVD11_Pos 27 /**< \brief (EVSYS_INTFLAG) Channel 11 Event Detection */
Kojto 111:4336505e4b1c 581 #define EVSYS_INTFLAG_EVD11 (1 << EVSYS_INTFLAG_EVD11_Pos)
Kojto 111:4336505e4b1c 582 #define EVSYS_INTFLAG_EVDp8_Pos 24 /**< \brief (EVSYS_INTFLAG) Channel x+8 Event Detection */
Kojto 111:4336505e4b1c 583 #define EVSYS_INTFLAG_EVDp8_Msk (0xFul << EVSYS_INTFLAG_EVDp8_Pos)
Kojto 111:4336505e4b1c 584 #define EVSYS_INTFLAG_EVDp8(value) (EVSYS_INTFLAG_EVDp8_Msk & ((value) << EVSYS_INTFLAG_EVDp8_Pos))
Kojto 111:4336505e4b1c 585 #define EVSYS_INTFLAG_MASK 0x0F0FFFFFul /**< \brief (EVSYS_INTFLAG) MASK Register */
Kojto 111:4336505e4b1c 586
Kojto 111:4336505e4b1c 587 /** \brief EVSYS hardware registers */
Kojto 111:4336505e4b1c 588 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 589 typedef struct {
Kojto 111:4336505e4b1c 590 __O EVSYS_CTRL_Type CTRL; /**< \brief Offset: 0x00 ( /W 8) Control */
Kojto 111:4336505e4b1c 591 RoReg8 Reserved1[0x3];
Kojto 111:4336505e4b1c 592 __IO EVSYS_CHANNEL_Type CHANNEL; /**< \brief Offset: 0x04 (R/W 32) Channel */
Kojto 111:4336505e4b1c 593 __IO EVSYS_USER_Type USER; /**< \brief Offset: 0x08 (R/W 16) User Multiplexer */
Kojto 111:4336505e4b1c 594 RoReg8 Reserved2[0x2];
Kojto 111:4336505e4b1c 595 __I EVSYS_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x0C (R/ 32) Channel Status */
Kojto 111:4336505e4b1c 596 __IO EVSYS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x10 (R/W 32) Interrupt Enable Clear */
Kojto 111:4336505e4b1c 597 __IO EVSYS_INTENSET_Type INTENSET; /**< \brief Offset: 0x14 (R/W 32) Interrupt Enable Set */
Kojto 111:4336505e4b1c 598 __IO EVSYS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 32) Interrupt Flag Status and Clear */
Kojto 111:4336505e4b1c 599 } Evsys;
Kojto 111:4336505e4b1c 600 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 601
Kojto 111:4336505e4b1c 602 /*@}*/
Kojto 111:4336505e4b1c 603
Kojto 111:4336505e4b1c 604 #endif /* _SAMR21_EVSYS_COMPONENT_ */