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TARGET_SAMD21G18A/comp_sercom.h@121:672067c3ada4, 2016-04-14 (annotated)

Committer:
elijahorr
Date:
Thu Apr 14 07:28:54 2016 +0000
Revision:
121:672067c3ada4
Parent:
111:4336505e4b1c 
.

Who changed what in which revision?

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Kojto 111:4336505e4b1c 1 /**
Kojto 111:4336505e4b1c 2 * \file
Kojto 111:4336505e4b1c 3 *
Kojto 111:4336505e4b1c 4 * \brief Component description for SERCOM
Kojto 111:4336505e4b1c 5 *
Kojto 111:4336505e4b1c 6 * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
Kojto 111:4336505e4b1c 7 *
Kojto 111:4336505e4b1c 8 * \asf_license_start
Kojto 111:4336505e4b1c 9 *
Kojto 111:4336505e4b1c 10 * \page License
Kojto 111:4336505e4b1c 11 *
Kojto 111:4336505e4b1c 12 * Redistribution and use in source and binary forms, with or without
Kojto 111:4336505e4b1c 13 * modification, are permitted provided that the following conditions are met:
Kojto 111:4336505e4b1c 14 *
Kojto 111:4336505e4b1c 15 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 111:4336505e4b1c 16 * this list of conditions and the following disclaimer.
Kojto 111:4336505e4b1c 17 *
Kojto 111:4336505e4b1c 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 111:4336505e4b1c 19 * this list of conditions and the following disclaimer in the documentation
Kojto 111:4336505e4b1c 20 * and/or other materials provided with the distribution.
Kojto 111:4336505e4b1c 21 *
Kojto 111:4336505e4b1c 22 * 3. The name of Atmel may not be used to endorse or promote products derived
Kojto 111:4336505e4b1c 23 * from this software without specific prior written permission.
Kojto 111:4336505e4b1c 24 *
Kojto 111:4336505e4b1c 25 * 4. This software may only be redistributed and used in connection with an
Kojto 111:4336505e4b1c 26 * Atmel microcontroller product.
Kojto 111:4336505e4b1c 27 *
Kojto 111:4336505e4b1c 28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
Kojto 111:4336505e4b1c 29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
Kojto 111:4336505e4b1c 30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
Kojto 111:4336505e4b1c 31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
Kojto 111:4336505e4b1c 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 111:4336505e4b1c 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
Kojto 111:4336505e4b1c 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
Kojto 111:4336505e4b1c 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
Kojto 111:4336505e4b1c 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
Kojto 111:4336505e4b1c 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto 111:4336505e4b1c 38 * POSSIBILITY OF SUCH DAMAGE.
Kojto 111:4336505e4b1c 39 *
Kojto 111:4336505e4b1c 40 * \asf_license_stop
Kojto 111:4336505e4b1c 41 *
Kojto 111:4336505e4b1c 42 */
Kojto 111:4336505e4b1c 43 /*
Kojto 111:4336505e4b1c 44 * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
Kojto 111:4336505e4b1c 45 */
Kojto 111:4336505e4b1c 46
Kojto 111:4336505e4b1c 47 #ifndef _SAMD21_SERCOM_COMPONENT_
Kojto 111:4336505e4b1c 48 #define _SAMD21_SERCOM_COMPONENT_
Kojto 111:4336505e4b1c 49
Kojto 111:4336505e4b1c 50 /* ========================================================================== */
Kojto 111:4336505e4b1c 51 /** SOFTWARE API DEFINITION FOR SERCOM */
Kojto 111:4336505e4b1c 52 /* ========================================================================== */
Kojto 111:4336505e4b1c 53 /** \addtogroup SAMD21_SERCOM Serial Communication Interface */
Kojto 111:4336505e4b1c 54 /*@{*/
Kojto 111:4336505e4b1c 55
Kojto 111:4336505e4b1c 56 #define SERCOM_U2201
Kojto 111:4336505e4b1c 57 #define REV_SERCOM 0x201
Kojto 111:4336505e4b1c 58
Kojto 111:4336505e4b1c 59 /* -------- SERCOM_I2CM_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CM I2CM Control A -------- */
Kojto 111:4336505e4b1c 60 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 61 typedef union {
Kojto 111:4336505e4b1c 62 struct {
Kojto 111:4336505e4b1c 63 uint32_t SWRST:1; /*!< bit: 0 Software Reset */
Kojto 111:4336505e4b1c 64 uint32_t ENABLE:1; /*!< bit: 1 Enable */
Kojto 111:4336505e4b1c 65 uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
Kojto 111:4336505e4b1c 66 uint32_t :2; /*!< bit: 5.. 6 Reserved */
Kojto 111:4336505e4b1c 67 uint32_t RUNSTDBY:1; /*!< bit: 7 Run in Standby */
Kojto 111:4336505e4b1c 68 uint32_t :8; /*!< bit: 8..15 Reserved */
Kojto 111:4336505e4b1c 69 uint32_t PINOUT:1; /*!< bit: 16 Pin Usage */
Kojto 111:4336505e4b1c 70 uint32_t :3; /*!< bit: 17..19 Reserved */
Kojto 111:4336505e4b1c 71 uint32_t SDAHOLD:2; /*!< bit: 20..21 SDA Hold Time */
Kojto 111:4336505e4b1c 72 uint32_t MEXTTOEN:1; /*!< bit: 22 Master SCL Low Extend Timeout */
Kojto 111:4336505e4b1c 73 uint32_t SEXTTOEN:1; /*!< bit: 23 Slave SCL Low Extend Timeout */
Kojto 111:4336505e4b1c 74 uint32_t SPEED:2; /*!< bit: 24..25 Transfer Speed */
Kojto 111:4336505e4b1c 75 uint32_t :1; /*!< bit: 26 Reserved */
Kojto 111:4336505e4b1c 76 uint32_t SCLSM:1; /*!< bit: 27 SCL Clock Stretch Mode */
Kojto 111:4336505e4b1c 77 uint32_t INACTOUT:2; /*!< bit: 28..29 Inactive Time-Out */
Kojto 111:4336505e4b1c 78 uint32_t LOWTOUTEN:1; /*!< bit: 30 SCL Low Timeout Enable */
Kojto 111:4336505e4b1c 79 uint32_t :1; /*!< bit: 31 Reserved */
Kojto 111:4336505e4b1c 80 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 81 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 82 } SERCOM_I2CM_CTRLA_Type;
Kojto 111:4336505e4b1c 83 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 84
Kojto 111:4336505e4b1c 85 #define SERCOM_I2CM_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_I2CM_CTRLA offset) I2CM Control A */
Kojto 111:4336505e4b1c 86 #define SERCOM_I2CM_CTRLA_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CM_CTRLA reset_value) I2CM Control A */
Kojto 111:4336505e4b1c 87
Kojto 111:4336505e4b1c 88 #define SERCOM_I2CM_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_I2CM_CTRLA) Software Reset */
Kojto 111:4336505e4b1c 89 #define SERCOM_I2CM_CTRLA_SWRST (0x1ul << SERCOM_I2CM_CTRLA_SWRST_Pos)
Kojto 111:4336505e4b1c 90 #define SERCOM_I2CM_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_I2CM_CTRLA) Enable */
Kojto 111:4336505e4b1c 91 #define SERCOM_I2CM_CTRLA_ENABLE (0x1ul << SERCOM_I2CM_CTRLA_ENABLE_Pos)
Kojto 111:4336505e4b1c 92 #define SERCOM_I2CM_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_I2CM_CTRLA) Operating Mode */
Kojto 111:4336505e4b1c 93 #define SERCOM_I2CM_CTRLA_MODE_Msk (0x7ul << SERCOM_I2CM_CTRLA_MODE_Pos)
Kojto 111:4336505e4b1c 94 #define SERCOM_I2CM_CTRLA_MODE(value) ((SERCOM_I2CM_CTRLA_MODE_Msk & ((value) << SERCOM_I2CM_CTRLA_MODE_Pos)))
Kojto 111:4336505e4b1c 95 #define SERCOM_I2CM_CTRLA_MODE_USART_EXT_CLK_Val 0x0ul /**< \brief (SERCOM_I2CM_CTRLA) USART mode with external clock */
Kojto 111:4336505e4b1c 96 #define SERCOM_I2CM_CTRLA_MODE_USART_INT_CLK_Val 0x1ul /**< \brief (SERCOM_I2CM_CTRLA) USART mode with internal clock */
Kojto 111:4336505e4b1c 97 #define SERCOM_I2CM_CTRLA_MODE_SPI_SLAVE_Val 0x2ul /**< \brief (SERCOM_I2CM_CTRLA) SPI mode with external clock */
Kojto 111:4336505e4b1c 98 #define SERCOM_I2CM_CTRLA_MODE_SPI_MASTER_Val 0x3ul /**< \brief (SERCOM_I2CM_CTRLA) SPI mode with internal clock */
Kojto 111:4336505e4b1c 99 #define SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE_Val 0x4ul /**< \brief (SERCOM_I2CM_CTRLA) I2C mode with external clock */
Kojto 111:4336505e4b1c 100 #define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER_Val 0x5ul /**< \brief (SERCOM_I2CM_CTRLA) I2C mode with internal clock */
Kojto 111:4336505e4b1c 101 #define SERCOM_I2CM_CTRLA_MODE_USART_EXT_CLK (SERCOM_I2CM_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_I2CM_CTRLA_MODE_Pos)
Kojto 111:4336505e4b1c 102 #define SERCOM_I2CM_CTRLA_MODE_USART_INT_CLK (SERCOM_I2CM_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_I2CM_CTRLA_MODE_Pos)
Kojto 111:4336505e4b1c 103 #define SERCOM_I2CM_CTRLA_MODE_SPI_SLAVE (SERCOM_I2CM_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_I2CM_CTRLA_MODE_Pos)
Kojto 111:4336505e4b1c 104 #define SERCOM_I2CM_CTRLA_MODE_SPI_MASTER (SERCOM_I2CM_CTRLA_MODE_SPI_MASTER_Val << SERCOM_I2CM_CTRLA_MODE_Pos)
Kojto 111:4336505e4b1c 105 #define SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE (SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_I2CM_CTRLA_MODE_Pos)
Kojto 111:4336505e4b1c 106 #define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (SERCOM_I2CM_CTRLA_MODE_I2C_MASTER_Val << SERCOM_I2CM_CTRLA_MODE_Pos)
Kojto 111:4336505e4b1c 107 #define SERCOM_I2CM_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_I2CM_CTRLA) Run in Standby */
Kojto 111:4336505e4b1c 108 #define SERCOM_I2CM_CTRLA_RUNSTDBY (0x1ul << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos)
Kojto 111:4336505e4b1c 109 #define SERCOM_I2CM_CTRLA_PINOUT_Pos 16 /**< \brief (SERCOM_I2CM_CTRLA) Pin Usage */
Kojto 111:4336505e4b1c 110 #define SERCOM_I2CM_CTRLA_PINOUT (0x1ul << SERCOM_I2CM_CTRLA_PINOUT_Pos)
Kojto 111:4336505e4b1c 111 #define SERCOM_I2CM_CTRLA_SDAHOLD_Pos 20 /**< \brief (SERCOM_I2CM_CTRLA) SDA Hold Time */
Kojto 111:4336505e4b1c 112 #define SERCOM_I2CM_CTRLA_SDAHOLD_Msk (0x3ul << SERCOM_I2CM_CTRLA_SDAHOLD_Pos)
Kojto 111:4336505e4b1c 113 #define SERCOM_I2CM_CTRLA_SDAHOLD(value) ((SERCOM_I2CM_CTRLA_SDAHOLD_Msk & ((value) << SERCOM_I2CM_CTRLA_SDAHOLD_Pos)))
Kojto 111:4336505e4b1c 114 #define SERCOM_I2CM_CTRLA_MEXTTOEN_Pos 22 /**< \brief (SERCOM_I2CM_CTRLA) Master SCL Low Extend Timeout */
Kojto 111:4336505e4b1c 115 #define SERCOM_I2CM_CTRLA_MEXTTOEN (0x1ul << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos)
Kojto 111:4336505e4b1c 116 #define SERCOM_I2CM_CTRLA_SEXTTOEN_Pos 23 /**< \brief (SERCOM_I2CM_CTRLA) Slave SCL Low Extend Timeout */
Kojto 111:4336505e4b1c 117 #define SERCOM_I2CM_CTRLA_SEXTTOEN (0x1ul << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos)
Kojto 111:4336505e4b1c 118 #define SERCOM_I2CM_CTRLA_SPEED_Pos 24 /**< \brief (SERCOM_I2CM_CTRLA) Transfer Speed */
Kojto 111:4336505e4b1c 119 #define SERCOM_I2CM_CTRLA_SPEED_Msk (0x3ul << SERCOM_I2CM_CTRLA_SPEED_Pos)
Kojto 111:4336505e4b1c 120 #define SERCOM_I2CM_CTRLA_SPEED(value) ((SERCOM_I2CM_CTRLA_SPEED_Msk & ((value) << SERCOM_I2CM_CTRLA_SPEED_Pos)))
Kojto 111:4336505e4b1c 121 #define SERCOM_I2CM_CTRLA_SCLSM_Pos 27 /**< \brief (SERCOM_I2CM_CTRLA) SCL Clock Stretch Mode */
Kojto 111:4336505e4b1c 122 #define SERCOM_I2CM_CTRLA_SCLSM (0x1ul << SERCOM_I2CM_CTRLA_SCLSM_Pos)
Kojto 111:4336505e4b1c 123 #define SERCOM_I2CM_CTRLA_INACTOUT_Pos 28 /**< \brief (SERCOM_I2CM_CTRLA) Inactive Time-Out */
Kojto 111:4336505e4b1c 124 #define SERCOM_I2CM_CTRLA_INACTOUT_Msk (0x3ul << SERCOM_I2CM_CTRLA_INACTOUT_Pos)
Kojto 111:4336505e4b1c 125 #define SERCOM_I2CM_CTRLA_INACTOUT(value) ((SERCOM_I2CM_CTRLA_INACTOUT_Msk & ((value) << SERCOM_I2CM_CTRLA_INACTOUT_Pos)))
Kojto 111:4336505e4b1c 126 #define SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos 30 /**< \brief (SERCOM_I2CM_CTRLA) SCL Low Timeout Enable */
Kojto 111:4336505e4b1c 127 #define SERCOM_I2CM_CTRLA_LOWTOUTEN (0x1ul << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos)
Kojto 111:4336505e4b1c 128 #define SERCOM_I2CM_CTRLA_MASK 0x7BF1009Ful /**< \brief (SERCOM_I2CM_CTRLA) MASK Register */
Kojto 111:4336505e4b1c 129
Kojto 111:4336505e4b1c 130 /* -------- SERCOM_I2CS_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CS I2CS Control A -------- */
Kojto 111:4336505e4b1c 131 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 132 typedef union {
Kojto 111:4336505e4b1c 133 struct {
Kojto 111:4336505e4b1c 134 uint32_t SWRST:1; /*!< bit: 0 Software Reset */
Kojto 111:4336505e4b1c 135 uint32_t ENABLE:1; /*!< bit: 1 Enable */
Kojto 111:4336505e4b1c 136 uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
Kojto 111:4336505e4b1c 137 uint32_t :2; /*!< bit: 5.. 6 Reserved */
Kojto 111:4336505e4b1c 138 uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */
Kojto 111:4336505e4b1c 139 uint32_t :8; /*!< bit: 8..15 Reserved */
Kojto 111:4336505e4b1c 140 uint32_t PINOUT:1; /*!< bit: 16 Pin Usage */
Kojto 111:4336505e4b1c 141 uint32_t :3; /*!< bit: 17..19 Reserved */
Kojto 111:4336505e4b1c 142 uint32_t SDAHOLD:2; /*!< bit: 20..21 SDA Hold Time */
Kojto 111:4336505e4b1c 143 uint32_t :1; /*!< bit: 22 Reserved */
Kojto 111:4336505e4b1c 144 uint32_t SEXTTOEN:1; /*!< bit: 23 Slave SCL Low Extend Timeout */
Kojto 111:4336505e4b1c 145 uint32_t SPEED:2; /*!< bit: 24..25 Transfer Speed */
Kojto 111:4336505e4b1c 146 uint32_t :1; /*!< bit: 26 Reserved */
Kojto 111:4336505e4b1c 147 uint32_t SCLSM:1; /*!< bit: 27 SCL Clock Stretch Mode */
Kojto 111:4336505e4b1c 148 uint32_t :2; /*!< bit: 28..29 Reserved */
Kojto 111:4336505e4b1c 149 uint32_t LOWTOUTEN:1; /*!< bit: 30 SCL Low Timeout Enable */
Kojto 111:4336505e4b1c 150 uint32_t :1; /*!< bit: 31 Reserved */
Kojto 111:4336505e4b1c 151 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 152 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 153 } SERCOM_I2CS_CTRLA_Type;
Kojto 111:4336505e4b1c 154 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 155
Kojto 111:4336505e4b1c 156 #define SERCOM_I2CS_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_I2CS_CTRLA offset) I2CS Control A */
Kojto 111:4336505e4b1c 157 #define SERCOM_I2CS_CTRLA_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CS_CTRLA reset_value) I2CS Control A */
Kojto 111:4336505e4b1c 158
Kojto 111:4336505e4b1c 159 #define SERCOM_I2CS_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_I2CS_CTRLA) Software Reset */
Kojto 111:4336505e4b1c 160 #define SERCOM_I2CS_CTRLA_SWRST (0x1ul << SERCOM_I2CS_CTRLA_SWRST_Pos)
Kojto 111:4336505e4b1c 161 #define SERCOM_I2CS_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_I2CS_CTRLA) Enable */
Kojto 111:4336505e4b1c 162 #define SERCOM_I2CS_CTRLA_ENABLE (0x1ul << SERCOM_I2CS_CTRLA_ENABLE_Pos)
Kojto 111:4336505e4b1c 163 #define SERCOM_I2CS_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_I2CS_CTRLA) Operating Mode */
Kojto 111:4336505e4b1c 164 #define SERCOM_I2CS_CTRLA_MODE_Msk (0x7ul << SERCOM_I2CS_CTRLA_MODE_Pos)
Kojto 111:4336505e4b1c 165 #define SERCOM_I2CS_CTRLA_MODE(value) ((SERCOM_I2CS_CTRLA_MODE_Msk & ((value) << SERCOM_I2CS_CTRLA_MODE_Pos)))
Kojto 111:4336505e4b1c 166 #define SERCOM_I2CS_CTRLA_MODE_USART_EXT_CLK_Val 0x0ul /**< \brief (SERCOM_I2CS_CTRLA) USART mode with external clock */
Kojto 111:4336505e4b1c 167 #define SERCOM_I2CS_CTRLA_MODE_USART_INT_CLK_Val 0x1ul /**< \brief (SERCOM_I2CS_CTRLA) USART mode with internal clock */
Kojto 111:4336505e4b1c 168 #define SERCOM_I2CS_CTRLA_MODE_SPI_SLAVE_Val 0x2ul /**< \brief (SERCOM_I2CS_CTRLA) SPI mode with external clock */
Kojto 111:4336505e4b1c 169 #define SERCOM_I2CS_CTRLA_MODE_SPI_MASTER_Val 0x3ul /**< \brief (SERCOM_I2CS_CTRLA) SPI mode with internal clock */
Kojto 111:4336505e4b1c 170 #define SERCOM_I2CS_CTRLA_MODE_I2C_SLAVE_Val 0x4ul /**< \brief (SERCOM_I2CS_CTRLA) I2C mode with external clock */
Kojto 111:4336505e4b1c 171 #define SERCOM_I2CS_CTRLA_MODE_I2C_MASTER_Val 0x5ul /**< \brief (SERCOM_I2CS_CTRLA) I2C mode with internal clock */
Kojto 111:4336505e4b1c 172 #define SERCOM_I2CS_CTRLA_MODE_USART_EXT_CLK (SERCOM_I2CS_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_I2CS_CTRLA_MODE_Pos)
Kojto 111:4336505e4b1c 173 #define SERCOM_I2CS_CTRLA_MODE_USART_INT_CLK (SERCOM_I2CS_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_I2CS_CTRLA_MODE_Pos)
Kojto 111:4336505e4b1c 174 #define SERCOM_I2CS_CTRLA_MODE_SPI_SLAVE (SERCOM_I2CS_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_I2CS_CTRLA_MODE_Pos)
Kojto 111:4336505e4b1c 175 #define SERCOM_I2CS_CTRLA_MODE_SPI_MASTER (SERCOM_I2CS_CTRLA_MODE_SPI_MASTER_Val << SERCOM_I2CS_CTRLA_MODE_Pos)
Kojto 111:4336505e4b1c 176 #define SERCOM_I2CS_CTRLA_MODE_I2C_SLAVE (SERCOM_I2CS_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_I2CS_CTRLA_MODE_Pos)
Kojto 111:4336505e4b1c 177 #define SERCOM_I2CS_CTRLA_MODE_I2C_MASTER (SERCOM_I2CS_CTRLA_MODE_I2C_MASTER_Val << SERCOM_I2CS_CTRLA_MODE_Pos)
Kojto 111:4336505e4b1c 178 #define SERCOM_I2CS_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_I2CS_CTRLA) Run during Standby */
Kojto 111:4336505e4b1c 179 #define SERCOM_I2CS_CTRLA_RUNSTDBY (0x1ul << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos)
Kojto 111:4336505e4b1c 180 #define SERCOM_I2CS_CTRLA_PINOUT_Pos 16 /**< \brief (SERCOM_I2CS_CTRLA) Pin Usage */
Kojto 111:4336505e4b1c 181 #define SERCOM_I2CS_CTRLA_PINOUT (0x1ul << SERCOM_I2CS_CTRLA_PINOUT_Pos)
Kojto 111:4336505e4b1c 182 #define SERCOM_I2CS_CTRLA_SDAHOLD_Pos 20 /**< \brief (SERCOM_I2CS_CTRLA) SDA Hold Time */
Kojto 111:4336505e4b1c 183 #define SERCOM_I2CS_CTRLA_SDAHOLD_Msk (0x3ul << SERCOM_I2CS_CTRLA_SDAHOLD_Pos)
Kojto 111:4336505e4b1c 184 #define SERCOM_I2CS_CTRLA_SDAHOLD(value) ((SERCOM_I2CS_CTRLA_SDAHOLD_Msk & ((value) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos)))
Kojto 111:4336505e4b1c 185 #define SERCOM_I2CS_CTRLA_SEXTTOEN_Pos 23 /**< \brief (SERCOM_I2CS_CTRLA) Slave SCL Low Extend Timeout */
Kojto 111:4336505e4b1c 186 #define SERCOM_I2CS_CTRLA_SEXTTOEN (0x1ul << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos)
Kojto 111:4336505e4b1c 187 #define SERCOM_I2CS_CTRLA_SPEED_Pos 24 /**< \brief (SERCOM_I2CS_CTRLA) Transfer Speed */
Kojto 111:4336505e4b1c 188 #define SERCOM_I2CS_CTRLA_SPEED_Msk (0x3ul << SERCOM_I2CS_CTRLA_SPEED_Pos)
Kojto 111:4336505e4b1c 189 #define SERCOM_I2CS_CTRLA_SPEED(value) ((SERCOM_I2CS_CTRLA_SPEED_Msk & ((value) << SERCOM_I2CS_CTRLA_SPEED_Pos)))
Kojto 111:4336505e4b1c 190 #define SERCOM_I2CS_CTRLA_SCLSM_Pos 27 /**< \brief (SERCOM_I2CS_CTRLA) SCL Clock Stretch Mode */
Kojto 111:4336505e4b1c 191 #define SERCOM_I2CS_CTRLA_SCLSM (0x1ul << SERCOM_I2CS_CTRLA_SCLSM_Pos)
Kojto 111:4336505e4b1c 192 #define SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos 30 /**< \brief (SERCOM_I2CS_CTRLA) SCL Low Timeout Enable */
Kojto 111:4336505e4b1c 193 #define SERCOM_I2CS_CTRLA_LOWTOUTEN (0x1ul << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos)
Kojto 111:4336505e4b1c 194 #define SERCOM_I2CS_CTRLA_MASK 0x4BB1009Ful /**< \brief (SERCOM_I2CS_CTRLA) MASK Register */
Kojto 111:4336505e4b1c 195
Kojto 111:4336505e4b1c 196 /* -------- SERCOM_SPI_CTRLA : (SERCOM Offset: 0x00) (R/W 32) SPI SPI Control A -------- */
Kojto 111:4336505e4b1c 197 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 198 typedef union {
Kojto 111:4336505e4b1c 199 struct {
Kojto 111:4336505e4b1c 200 uint32_t SWRST:1; /*!< bit: 0 Software Reset */
Kojto 111:4336505e4b1c 201 uint32_t ENABLE:1; /*!< bit: 1 Enable */
Kojto 111:4336505e4b1c 202 uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
Kojto 111:4336505e4b1c 203 uint32_t :2; /*!< bit: 5.. 6 Reserved */
Kojto 111:4336505e4b1c 204 uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */
Kojto 111:4336505e4b1c 205 uint32_t IBON:1; /*!< bit: 8 Immediate Buffer Overflow Notification */
Kojto 111:4336505e4b1c 206 uint32_t :7; /*!< bit: 9..15 Reserved */
Kojto 111:4336505e4b1c 207 uint32_t DOPO:2; /*!< bit: 16..17 Data Out Pinout */
Kojto 111:4336505e4b1c 208 uint32_t :2; /*!< bit: 18..19 Reserved */
Kojto 111:4336505e4b1c 209 uint32_t DIPO:2; /*!< bit: 20..21 Data In Pinout */
Kojto 111:4336505e4b1c 210 uint32_t :2; /*!< bit: 22..23 Reserved */
Kojto 111:4336505e4b1c 211 uint32_t FORM:4; /*!< bit: 24..27 Frame Format */
Kojto 111:4336505e4b1c 212 uint32_t CPHA:1; /*!< bit: 28 Clock Phase */
Kojto 111:4336505e4b1c 213 uint32_t CPOL:1; /*!< bit: 29 Clock Polarity */
Kojto 111:4336505e4b1c 214 uint32_t DORD:1; /*!< bit: 30 Data Order */
Kojto 111:4336505e4b1c 215 uint32_t :1; /*!< bit: 31 Reserved */
Kojto 111:4336505e4b1c 216 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 217 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 218 } SERCOM_SPI_CTRLA_Type;
Kojto 111:4336505e4b1c 219 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 220
Kojto 111:4336505e4b1c 221 #define SERCOM_SPI_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_SPI_CTRLA offset) SPI Control A */
Kojto 111:4336505e4b1c 222 #define SERCOM_SPI_CTRLA_RESETVALUE 0x00000000ul /**< \brief (SERCOM_SPI_CTRLA reset_value) SPI Control A */
Kojto 111:4336505e4b1c 223
Kojto 111:4336505e4b1c 224 #define SERCOM_SPI_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_SPI_CTRLA) Software Reset */
Kojto 111:4336505e4b1c 225 #define SERCOM_SPI_CTRLA_SWRST (0x1ul << SERCOM_SPI_CTRLA_SWRST_Pos)
Kojto 111:4336505e4b1c 226 #define SERCOM_SPI_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_SPI_CTRLA) Enable */
Kojto 111:4336505e4b1c 227 #define SERCOM_SPI_CTRLA_ENABLE (0x1ul << SERCOM_SPI_CTRLA_ENABLE_Pos)
Kojto 111:4336505e4b1c 228 #define SERCOM_SPI_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_SPI_CTRLA) Operating Mode */
Kojto 111:4336505e4b1c 229 #define SERCOM_SPI_CTRLA_MODE_Msk (0x7ul << SERCOM_SPI_CTRLA_MODE_Pos)
Kojto 111:4336505e4b1c 230 #define SERCOM_SPI_CTRLA_MODE(value) ((SERCOM_SPI_CTRLA_MODE_Msk & ((value) << SERCOM_SPI_CTRLA_MODE_Pos)))
Kojto 111:4336505e4b1c 231 #define SERCOM_SPI_CTRLA_MODE_USART_EXT_CLK_Val 0x0ul /**< \brief (SERCOM_SPI_CTRLA) USART mode with external clock */
Kojto 111:4336505e4b1c 232 #define SERCOM_SPI_CTRLA_MODE_USART_INT_CLK_Val 0x1ul /**< \brief (SERCOM_SPI_CTRLA) USART mode with internal clock */
Kojto 111:4336505e4b1c 233 #define SERCOM_SPI_CTRLA_MODE_SPI_SLAVE_Val 0x2ul /**< \brief (SERCOM_SPI_CTRLA) SPI mode with external clock */
Kojto 111:4336505e4b1c 234 #define SERCOM_SPI_CTRLA_MODE_SPI_MASTER_Val 0x3ul /**< \brief (SERCOM_SPI_CTRLA) SPI mode with internal clock */
Kojto 111:4336505e4b1c 235 #define SERCOM_SPI_CTRLA_MODE_I2C_SLAVE_Val 0x4ul /**< \brief (SERCOM_SPI_CTRLA) I2C mode with external clock */
Kojto 111:4336505e4b1c 236 #define SERCOM_SPI_CTRLA_MODE_I2C_MASTER_Val 0x5ul /**< \brief (SERCOM_SPI_CTRLA) I2C mode with internal clock */
Kojto 111:4336505e4b1c 237 #define SERCOM_SPI_CTRLA_MODE_USART_EXT_CLK (SERCOM_SPI_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_SPI_CTRLA_MODE_Pos)
Kojto 111:4336505e4b1c 238 #define SERCOM_SPI_CTRLA_MODE_USART_INT_CLK (SERCOM_SPI_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_SPI_CTRLA_MODE_Pos)
Kojto 111:4336505e4b1c 239 #define SERCOM_SPI_CTRLA_MODE_SPI_SLAVE (SERCOM_SPI_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_SPI_CTRLA_MODE_Pos)
Kojto 111:4336505e4b1c 240 #define SERCOM_SPI_CTRLA_MODE_SPI_MASTER (SERCOM_SPI_CTRLA_MODE_SPI_MASTER_Val << SERCOM_SPI_CTRLA_MODE_Pos)
Kojto 111:4336505e4b1c 241 #define SERCOM_SPI_CTRLA_MODE_I2C_SLAVE (SERCOM_SPI_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_SPI_CTRLA_MODE_Pos)
Kojto 111:4336505e4b1c 242 #define SERCOM_SPI_CTRLA_MODE_I2C_MASTER (SERCOM_SPI_CTRLA_MODE_I2C_MASTER_Val << SERCOM_SPI_CTRLA_MODE_Pos)
Kojto 111:4336505e4b1c 243 #define SERCOM_SPI_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_SPI_CTRLA) Run during Standby */
Kojto 111:4336505e4b1c 244 #define SERCOM_SPI_CTRLA_RUNSTDBY (0x1ul << SERCOM_SPI_CTRLA_RUNSTDBY_Pos)
Kojto 111:4336505e4b1c 245 #define SERCOM_SPI_CTRLA_IBON_Pos 8 /**< \brief (SERCOM_SPI_CTRLA) Immediate Buffer Overflow Notification */
Kojto 111:4336505e4b1c 246 #define SERCOM_SPI_CTRLA_IBON (0x1ul << SERCOM_SPI_CTRLA_IBON_Pos)
Kojto 111:4336505e4b1c 247 #define SERCOM_SPI_CTRLA_DOPO_Pos 16 /**< \brief (SERCOM_SPI_CTRLA) Data Out Pinout */
Kojto 111:4336505e4b1c 248 #define SERCOM_SPI_CTRLA_DOPO_Msk (0x3ul << SERCOM_SPI_CTRLA_DOPO_Pos)
Kojto 111:4336505e4b1c 249 #define SERCOM_SPI_CTRLA_DOPO(value) ((SERCOM_SPI_CTRLA_DOPO_Msk & ((value) << SERCOM_SPI_CTRLA_DOPO_Pos)))
Kojto 111:4336505e4b1c 250 #define SERCOM_SPI_CTRLA_DIPO_Pos 20 /**< \brief (SERCOM_SPI_CTRLA) Data In Pinout */
Kojto 111:4336505e4b1c 251 #define SERCOM_SPI_CTRLA_DIPO_Msk (0x3ul << SERCOM_SPI_CTRLA_DIPO_Pos)
Kojto 111:4336505e4b1c 252 #define SERCOM_SPI_CTRLA_DIPO(value) ((SERCOM_SPI_CTRLA_DIPO_Msk & ((value) << SERCOM_SPI_CTRLA_DIPO_Pos)))
Kojto 111:4336505e4b1c 253 #define SERCOM_SPI_CTRLA_FORM_Pos 24 /**< \brief (SERCOM_SPI_CTRLA) Frame Format */
Kojto 111:4336505e4b1c 254 #define SERCOM_SPI_CTRLA_FORM_Msk (0xFul << SERCOM_SPI_CTRLA_FORM_Pos)
Kojto 111:4336505e4b1c 255 #define SERCOM_SPI_CTRLA_FORM(value) ((SERCOM_SPI_CTRLA_FORM_Msk & ((value) << SERCOM_SPI_CTRLA_FORM_Pos)))
Kojto 111:4336505e4b1c 256 #define SERCOM_SPI_CTRLA_CPHA_Pos 28 /**< \brief (SERCOM_SPI_CTRLA) Clock Phase */
Kojto 111:4336505e4b1c 257 #define SERCOM_SPI_CTRLA_CPHA (0x1ul << SERCOM_SPI_CTRLA_CPHA_Pos)
Kojto 111:4336505e4b1c 258 #define SERCOM_SPI_CTRLA_CPOL_Pos 29 /**< \brief (SERCOM_SPI_CTRLA) Clock Polarity */
Kojto 111:4336505e4b1c 259 #define SERCOM_SPI_CTRLA_CPOL (0x1ul << SERCOM_SPI_CTRLA_CPOL_Pos)
Kojto 111:4336505e4b1c 260 #define SERCOM_SPI_CTRLA_DORD_Pos 30 /**< \brief (SERCOM_SPI_CTRLA) Data Order */
Kojto 111:4336505e4b1c 261 #define SERCOM_SPI_CTRLA_DORD (0x1ul << SERCOM_SPI_CTRLA_DORD_Pos)
Kojto 111:4336505e4b1c 262 #define SERCOM_SPI_CTRLA_MASK 0x7F33019Ful /**< \brief (SERCOM_SPI_CTRLA) MASK Register */
Kojto 111:4336505e4b1c 263
Kojto 111:4336505e4b1c 264 /* -------- SERCOM_USART_CTRLA : (SERCOM Offset: 0x00) (R/W 32) USART USART Control A -------- */
Kojto 111:4336505e4b1c 265 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 266 typedef union {
Kojto 111:4336505e4b1c 267 struct {
Kojto 111:4336505e4b1c 268 uint32_t SWRST:1; /*!< bit: 0 Software Reset */
Kojto 111:4336505e4b1c 269 uint32_t ENABLE:1; /*!< bit: 1 Enable */
Kojto 111:4336505e4b1c 270 uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
Kojto 111:4336505e4b1c 271 uint32_t :2; /*!< bit: 5.. 6 Reserved */
Kojto 111:4336505e4b1c 272 uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */
Kojto 111:4336505e4b1c 273 uint32_t IBON:1; /*!< bit: 8 Immediate Buffer Overflow Notification */
Kojto 111:4336505e4b1c 274 uint32_t :4; /*!< bit: 9..12 Reserved */
Kojto 111:4336505e4b1c 275 uint32_t SAMPR:3; /*!< bit: 13..15 Sample */
Kojto 111:4336505e4b1c 276 uint32_t TXPO:2; /*!< bit: 16..17 Transmit Data Pinout */
Kojto 111:4336505e4b1c 277 uint32_t :2; /*!< bit: 18..19 Reserved */
Kojto 111:4336505e4b1c 278 uint32_t RXPO:2; /*!< bit: 20..21 Receive Data Pinout */
Kojto 111:4336505e4b1c 279 uint32_t SAMPA:2; /*!< bit: 22..23 Sample Adjustment */
Kojto 111:4336505e4b1c 280 uint32_t FORM:4; /*!< bit: 24..27 Frame Format */
Kojto 111:4336505e4b1c 281 uint32_t CMODE:1; /*!< bit: 28 Communication Mode */
Kojto 111:4336505e4b1c 282 uint32_t CPOL:1; /*!< bit: 29 Clock Polarity */
Kojto 111:4336505e4b1c 283 uint32_t DORD:1; /*!< bit: 30 Data Order */
Kojto 111:4336505e4b1c 284 uint32_t :1; /*!< bit: 31 Reserved */
Kojto 111:4336505e4b1c 285 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 286 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 287 } SERCOM_USART_CTRLA_Type;
Kojto 111:4336505e4b1c 288 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 289
Kojto 111:4336505e4b1c 290 #define SERCOM_USART_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_USART_CTRLA offset) USART Control A */
Kojto 111:4336505e4b1c 291 #define SERCOM_USART_CTRLA_RESETVALUE 0x00000000ul /**< \brief (SERCOM_USART_CTRLA reset_value) USART Control A */
Kojto 111:4336505e4b1c 292
Kojto 111:4336505e4b1c 293 #define SERCOM_USART_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_USART_CTRLA) Software Reset */
Kojto 111:4336505e4b1c 294 #define SERCOM_USART_CTRLA_SWRST (0x1ul << SERCOM_USART_CTRLA_SWRST_Pos)
Kojto 111:4336505e4b1c 295 #define SERCOM_USART_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_USART_CTRLA) Enable */
Kojto 111:4336505e4b1c 296 #define SERCOM_USART_CTRLA_ENABLE (0x1ul << SERCOM_USART_CTRLA_ENABLE_Pos)
Kojto 111:4336505e4b1c 297 #define SERCOM_USART_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_USART_CTRLA) Operating Mode */
Kojto 111:4336505e4b1c 298 #define SERCOM_USART_CTRLA_MODE_Msk (0x7ul << SERCOM_USART_CTRLA_MODE_Pos)
Kojto 111:4336505e4b1c 299 #define SERCOM_USART_CTRLA_MODE(value) ((SERCOM_USART_CTRLA_MODE_Msk & ((value) << SERCOM_USART_CTRLA_MODE_Pos)))
Kojto 111:4336505e4b1c 300 #define SERCOM_USART_CTRLA_MODE_USART_EXT_CLK_Val 0x0ul /**< \brief (SERCOM_USART_CTRLA) USART mode with external clock */
Kojto 111:4336505e4b1c 301 #define SERCOM_USART_CTRLA_MODE_USART_INT_CLK_Val 0x1ul /**< \brief (SERCOM_USART_CTRLA) USART mode with internal clock */
Kojto 111:4336505e4b1c 302 #define SERCOM_USART_CTRLA_MODE_SPI_SLAVE_Val 0x2ul /**< \brief (SERCOM_USART_CTRLA) SPI mode with external clock */
Kojto 111:4336505e4b1c 303 #define SERCOM_USART_CTRLA_MODE_SPI_MASTER_Val 0x3ul /**< \brief (SERCOM_USART_CTRLA) SPI mode with internal clock */
Kojto 111:4336505e4b1c 304 #define SERCOM_USART_CTRLA_MODE_I2C_SLAVE_Val 0x4ul /**< \brief (SERCOM_USART_CTRLA) I2C mode with external clock */
Kojto 111:4336505e4b1c 305 #define SERCOM_USART_CTRLA_MODE_I2C_MASTER_Val 0x5ul /**< \brief (SERCOM_USART_CTRLA) I2C mode with internal clock */
Kojto 111:4336505e4b1c 306 #define SERCOM_USART_CTRLA_MODE_USART_EXT_CLK (SERCOM_USART_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_USART_CTRLA_MODE_Pos)
Kojto 111:4336505e4b1c 307 #define SERCOM_USART_CTRLA_MODE_USART_INT_CLK (SERCOM_USART_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_USART_CTRLA_MODE_Pos)
Kojto 111:4336505e4b1c 308 #define SERCOM_USART_CTRLA_MODE_SPI_SLAVE (SERCOM_USART_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_USART_CTRLA_MODE_Pos)
Kojto 111:4336505e4b1c 309 #define SERCOM_USART_CTRLA_MODE_SPI_MASTER (SERCOM_USART_CTRLA_MODE_SPI_MASTER_Val << SERCOM_USART_CTRLA_MODE_Pos)
Kojto 111:4336505e4b1c 310 #define SERCOM_USART_CTRLA_MODE_I2C_SLAVE (SERCOM_USART_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_USART_CTRLA_MODE_Pos)
Kojto 111:4336505e4b1c 311 #define SERCOM_USART_CTRLA_MODE_I2C_MASTER (SERCOM_USART_CTRLA_MODE_I2C_MASTER_Val << SERCOM_USART_CTRLA_MODE_Pos)
Kojto 111:4336505e4b1c 312 #define SERCOM_USART_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_USART_CTRLA) Run during Standby */
Kojto 111:4336505e4b1c 313 #define SERCOM_USART_CTRLA_RUNSTDBY (0x1ul << SERCOM_USART_CTRLA_RUNSTDBY_Pos)
Kojto 111:4336505e4b1c 314 #define SERCOM_USART_CTRLA_IBON_Pos 8 /**< \brief (SERCOM_USART_CTRLA) Immediate Buffer Overflow Notification */
Kojto 111:4336505e4b1c 315 #define SERCOM_USART_CTRLA_IBON (0x1ul << SERCOM_USART_CTRLA_IBON_Pos)
Kojto 111:4336505e4b1c 316 #define SERCOM_USART_CTRLA_SAMPR_Pos 13 /**< \brief (SERCOM_USART_CTRLA) Sample */
Kojto 111:4336505e4b1c 317 #define SERCOM_USART_CTRLA_SAMPR_Msk (0x7ul << SERCOM_USART_CTRLA_SAMPR_Pos)
Kojto 111:4336505e4b1c 318 #define SERCOM_USART_CTRLA_SAMPR(value) ((SERCOM_USART_CTRLA_SAMPR_Msk & ((value) << SERCOM_USART_CTRLA_SAMPR_Pos)))
Kojto 111:4336505e4b1c 319 #define SERCOM_USART_CTRLA_TXPO_Pos 16 /**< \brief (SERCOM_USART_CTRLA) Transmit Data Pinout */
Kojto 111:4336505e4b1c 320 #define SERCOM_USART_CTRLA_TXPO_Msk (0x3ul << SERCOM_USART_CTRLA_TXPO_Pos)
Kojto 111:4336505e4b1c 321 #define SERCOM_USART_CTRLA_TXPO(value) ((SERCOM_USART_CTRLA_TXPO_Msk & ((value) << SERCOM_USART_CTRLA_TXPO_Pos)))
Kojto 111:4336505e4b1c 322 #define SERCOM_USART_CTRLA_RXPO_Pos 20 /**< \brief (SERCOM_USART_CTRLA) Receive Data Pinout */
Kojto 111:4336505e4b1c 323 #define SERCOM_USART_CTRLA_RXPO_Msk (0x3ul << SERCOM_USART_CTRLA_RXPO_Pos)
Kojto 111:4336505e4b1c 324 #define SERCOM_USART_CTRLA_RXPO(value) ((SERCOM_USART_CTRLA_RXPO_Msk & ((value) << SERCOM_USART_CTRLA_RXPO_Pos)))
Kojto 111:4336505e4b1c 325 #define SERCOM_USART_CTRLA_SAMPA_Pos 22 /**< \brief (SERCOM_USART_CTRLA) Sample Adjustment */
Kojto 111:4336505e4b1c 326 #define SERCOM_USART_CTRLA_SAMPA_Msk (0x3ul << SERCOM_USART_CTRLA_SAMPA_Pos)
Kojto 111:4336505e4b1c 327 #define SERCOM_USART_CTRLA_SAMPA(value) ((SERCOM_USART_CTRLA_SAMPA_Msk & ((value) << SERCOM_USART_CTRLA_SAMPA_Pos)))
Kojto 111:4336505e4b1c 328 #define SERCOM_USART_CTRLA_FORM_Pos 24 /**< \brief (SERCOM_USART_CTRLA) Frame Format */
Kojto 111:4336505e4b1c 329 #define SERCOM_USART_CTRLA_FORM_Msk (0xFul << SERCOM_USART_CTRLA_FORM_Pos)
Kojto 111:4336505e4b1c 330 #define SERCOM_USART_CTRLA_FORM(value) ((SERCOM_USART_CTRLA_FORM_Msk & ((value) << SERCOM_USART_CTRLA_FORM_Pos)))
Kojto 111:4336505e4b1c 331 #define SERCOM_USART_CTRLA_CMODE_Pos 28 /**< \brief (SERCOM_USART_CTRLA) Communication Mode */
Kojto 111:4336505e4b1c 332 #define SERCOM_USART_CTRLA_CMODE (0x1ul << SERCOM_USART_CTRLA_CMODE_Pos)
Kojto 111:4336505e4b1c 333 #define SERCOM_USART_CTRLA_CPOL_Pos 29 /**< \brief (SERCOM_USART_CTRLA) Clock Polarity */
Kojto 111:4336505e4b1c 334 #define SERCOM_USART_CTRLA_CPOL (0x1ul << SERCOM_USART_CTRLA_CPOL_Pos)
Kojto 111:4336505e4b1c 335 #define SERCOM_USART_CTRLA_DORD_Pos 30 /**< \brief (SERCOM_USART_CTRLA) Data Order */
Kojto 111:4336505e4b1c 336 #define SERCOM_USART_CTRLA_DORD (0x1ul << SERCOM_USART_CTRLA_DORD_Pos)
Kojto 111:4336505e4b1c 337 #define SERCOM_USART_CTRLA_MASK 0x7FF3E19Ful /**< \brief (SERCOM_USART_CTRLA) MASK Register */
Kojto 111:4336505e4b1c 338
Kojto 111:4336505e4b1c 339 /* -------- SERCOM_I2CM_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CM I2CM Control B -------- */
Kojto 111:4336505e4b1c 340 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 341 typedef union {
Kojto 111:4336505e4b1c 342 struct {
Kojto 111:4336505e4b1c 343 uint32_t :8; /*!< bit: 0.. 7 Reserved */
Kojto 111:4336505e4b1c 344 uint32_t SMEN:1; /*!< bit: 8 Smart Mode Enable */
Kojto 111:4336505e4b1c 345 uint32_t QCEN:1; /*!< bit: 9 Quick Command Enable */
Kojto 111:4336505e4b1c 346 uint32_t :6; /*!< bit: 10..15 Reserved */
Kojto 111:4336505e4b1c 347 uint32_t CMD:2; /*!< bit: 16..17 Command */
Kojto 111:4336505e4b1c 348 uint32_t ACKACT:1; /*!< bit: 18 Acknowledge Action */
Kojto 111:4336505e4b1c 349 uint32_t :13; /*!< bit: 19..31 Reserved */
Kojto 111:4336505e4b1c 350 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 351 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 352 } SERCOM_I2CM_CTRLB_Type;
Kojto 111:4336505e4b1c 353 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 354
Kojto 111:4336505e4b1c 355 #define SERCOM_I2CM_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_I2CM_CTRLB offset) I2CM Control B */
Kojto 111:4336505e4b1c 356 #define SERCOM_I2CM_CTRLB_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CM_CTRLB reset_value) I2CM Control B */
Kojto 111:4336505e4b1c 357
Kojto 111:4336505e4b1c 358 #define SERCOM_I2CM_CTRLB_SMEN_Pos 8 /**< \brief (SERCOM_I2CM_CTRLB) Smart Mode Enable */
Kojto 111:4336505e4b1c 359 #define SERCOM_I2CM_CTRLB_SMEN (0x1ul << SERCOM_I2CM_CTRLB_SMEN_Pos)
Kojto 111:4336505e4b1c 360 #define SERCOM_I2CM_CTRLB_QCEN_Pos 9 /**< \brief (SERCOM_I2CM_CTRLB) Quick Command Enable */
Kojto 111:4336505e4b1c 361 #define SERCOM_I2CM_CTRLB_QCEN (0x1ul << SERCOM_I2CM_CTRLB_QCEN_Pos)
Kojto 111:4336505e4b1c 362 #define SERCOM_I2CM_CTRLB_CMD_Pos 16 /**< \brief (SERCOM_I2CM_CTRLB) Command */
Kojto 111:4336505e4b1c 363 #define SERCOM_I2CM_CTRLB_CMD_Msk (0x3ul << SERCOM_I2CM_CTRLB_CMD_Pos)
Kojto 111:4336505e4b1c 364 #define SERCOM_I2CM_CTRLB_CMD(value) ((SERCOM_I2CM_CTRLB_CMD_Msk & ((value) << SERCOM_I2CM_CTRLB_CMD_Pos)))
Kojto 111:4336505e4b1c 365 #define SERCOM_I2CM_CTRLB_ACKACT_Pos 18 /**< \brief (SERCOM_I2CM_CTRLB) Acknowledge Action */
Kojto 111:4336505e4b1c 366 #define SERCOM_I2CM_CTRLB_ACKACT (0x1ul << SERCOM_I2CM_CTRLB_ACKACT_Pos)
Kojto 111:4336505e4b1c 367 #define SERCOM_I2CM_CTRLB_MASK 0x00070300ul /**< \brief (SERCOM_I2CM_CTRLB) MASK Register */
Kojto 111:4336505e4b1c 368
Kojto 111:4336505e4b1c 369 /* -------- SERCOM_I2CS_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CS I2CS Control B -------- */
Kojto 111:4336505e4b1c 370 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 371 typedef union {
Kojto 111:4336505e4b1c 372 struct {
Kojto 111:4336505e4b1c 373 uint32_t :8; /*!< bit: 0.. 7 Reserved */
Kojto 111:4336505e4b1c 374 uint32_t SMEN:1; /*!< bit: 8 Smart Mode Enable */
Kojto 111:4336505e4b1c 375 uint32_t GCMD:1; /*!< bit: 9 PMBus Group Command */
Kojto 111:4336505e4b1c 376 uint32_t AACKEN:1; /*!< bit: 10 Automatic Address Acknowledge */
Kojto 111:4336505e4b1c 377 uint32_t :3; /*!< bit: 11..13 Reserved */
Kojto 111:4336505e4b1c 378 uint32_t AMODE:2; /*!< bit: 14..15 Address Mode */
Kojto 111:4336505e4b1c 379 uint32_t CMD:2; /*!< bit: 16..17 Command */
Kojto 111:4336505e4b1c 380 uint32_t ACKACT:1; /*!< bit: 18 Acknowledge Action */
Kojto 111:4336505e4b1c 381 uint32_t :13; /*!< bit: 19..31 Reserved */
Kojto 111:4336505e4b1c 382 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 383 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 384 } SERCOM_I2CS_CTRLB_Type;
Kojto 111:4336505e4b1c 385 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 386
Kojto 111:4336505e4b1c 387 #define SERCOM_I2CS_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_I2CS_CTRLB offset) I2CS Control B */
Kojto 111:4336505e4b1c 388 #define SERCOM_I2CS_CTRLB_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CS_CTRLB reset_value) I2CS Control B */
Kojto 111:4336505e4b1c 389
Kojto 111:4336505e4b1c 390 #define SERCOM_I2CS_CTRLB_SMEN_Pos 8 /**< \brief (SERCOM_I2CS_CTRLB) Smart Mode Enable */
Kojto 111:4336505e4b1c 391 #define SERCOM_I2CS_CTRLB_SMEN (0x1ul << SERCOM_I2CS_CTRLB_SMEN_Pos)
Kojto 111:4336505e4b1c 392 #define SERCOM_I2CS_CTRLB_GCMD_Pos 9 /**< \brief (SERCOM_I2CS_CTRLB) PMBus Group Command */
Kojto 111:4336505e4b1c 393 #define SERCOM_I2CS_CTRLB_GCMD (0x1ul << SERCOM_I2CS_CTRLB_GCMD_Pos)
Kojto 111:4336505e4b1c 394 #define SERCOM_I2CS_CTRLB_AACKEN_Pos 10 /**< \brief (SERCOM_I2CS_CTRLB) Automatic Address Acknowledge */
Kojto 111:4336505e4b1c 395 #define SERCOM_I2CS_CTRLB_AACKEN (0x1ul << SERCOM_I2CS_CTRLB_AACKEN_Pos)
Kojto 111:4336505e4b1c 396 #define SERCOM_I2CS_CTRLB_AMODE_Pos 14 /**< \brief (SERCOM_I2CS_CTRLB) Address Mode */
Kojto 111:4336505e4b1c 397 #define SERCOM_I2CS_CTRLB_AMODE_Msk (0x3ul << SERCOM_I2CS_CTRLB_AMODE_Pos)
Kojto 111:4336505e4b1c 398 #define SERCOM_I2CS_CTRLB_AMODE(value) ((SERCOM_I2CS_CTRLB_AMODE_Msk & ((value) << SERCOM_I2CS_CTRLB_AMODE_Pos)))
Kojto 111:4336505e4b1c 399 #define SERCOM_I2CS_CTRLB_CMD_Pos 16 /**< \brief (SERCOM_I2CS_CTRLB) Command */
Kojto 111:4336505e4b1c 400 #define SERCOM_I2CS_CTRLB_CMD_Msk (0x3ul << SERCOM_I2CS_CTRLB_CMD_Pos)
Kojto 111:4336505e4b1c 401 #define SERCOM_I2CS_CTRLB_CMD(value) ((SERCOM_I2CS_CTRLB_CMD_Msk & ((value) << SERCOM_I2CS_CTRLB_CMD_Pos)))
Kojto 111:4336505e4b1c 402 #define SERCOM_I2CS_CTRLB_ACKACT_Pos 18 /**< \brief (SERCOM_I2CS_CTRLB) Acknowledge Action */
Kojto 111:4336505e4b1c 403 #define SERCOM_I2CS_CTRLB_ACKACT (0x1ul << SERCOM_I2CS_CTRLB_ACKACT_Pos)
Kojto 111:4336505e4b1c 404 #define SERCOM_I2CS_CTRLB_MASK 0x0007C700ul /**< \brief (SERCOM_I2CS_CTRLB) MASK Register */
Kojto 111:4336505e4b1c 405
Kojto 111:4336505e4b1c 406 /* -------- SERCOM_SPI_CTRLB : (SERCOM Offset: 0x04) (R/W 32) SPI SPI Control B -------- */
Kojto 111:4336505e4b1c 407 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 408 typedef union {
Kojto 111:4336505e4b1c 409 struct {
Kojto 111:4336505e4b1c 410 uint32_t CHSIZE:3; /*!< bit: 0.. 2 Character Size */
Kojto 111:4336505e4b1c 411 uint32_t :3; /*!< bit: 3.. 5 Reserved */
Kojto 111:4336505e4b1c 412 uint32_t PLOADEN:1; /*!< bit: 6 Data Preload Enable */
Kojto 111:4336505e4b1c 413 uint32_t :2; /*!< bit: 7.. 8 Reserved */
Kojto 111:4336505e4b1c 414 uint32_t SSDE:1; /*!< bit: 9 Slave Select Low Detect Enable */
Kojto 111:4336505e4b1c 415 uint32_t :3; /*!< bit: 10..12 Reserved */
Kojto 111:4336505e4b1c 416 uint32_t MSSEN:1; /*!< bit: 13 Master Slave Select Enable */
Kojto 111:4336505e4b1c 417 uint32_t AMODE:2; /*!< bit: 14..15 Address Mode */
Kojto 111:4336505e4b1c 418 uint32_t :1; /*!< bit: 16 Reserved */
Kojto 111:4336505e4b1c 419 uint32_t RXEN:1; /*!< bit: 17 Receiver Enable */
Kojto 111:4336505e4b1c 420 uint32_t :14; /*!< bit: 18..31 Reserved */
Kojto 111:4336505e4b1c 421 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 422 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 423 } SERCOM_SPI_CTRLB_Type;
Kojto 111:4336505e4b1c 424 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 425
Kojto 111:4336505e4b1c 426 #define SERCOM_SPI_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_SPI_CTRLB offset) SPI Control B */
Kojto 111:4336505e4b1c 427 #define SERCOM_SPI_CTRLB_RESETVALUE 0x00000000ul /**< \brief (SERCOM_SPI_CTRLB reset_value) SPI Control B */
Kojto 111:4336505e4b1c 428
Kojto 111:4336505e4b1c 429 #define SERCOM_SPI_CTRLB_CHSIZE_Pos 0 /**< \brief (SERCOM_SPI_CTRLB) Character Size */
Kojto 111:4336505e4b1c 430 #define SERCOM_SPI_CTRLB_CHSIZE_Msk (0x7ul << SERCOM_SPI_CTRLB_CHSIZE_Pos)
Kojto 111:4336505e4b1c 431 #define SERCOM_SPI_CTRLB_CHSIZE(value) ((SERCOM_SPI_CTRLB_CHSIZE_Msk & ((value) << SERCOM_SPI_CTRLB_CHSIZE_Pos)))
Kojto 111:4336505e4b1c 432 #define SERCOM_SPI_CTRLB_PLOADEN_Pos 6 /**< \brief (SERCOM_SPI_CTRLB) Data Preload Enable */
Kojto 111:4336505e4b1c 433 #define SERCOM_SPI_CTRLB_PLOADEN (0x1ul << SERCOM_SPI_CTRLB_PLOADEN_Pos)
Kojto 111:4336505e4b1c 434 #define SERCOM_SPI_CTRLB_SSDE_Pos 9 /**< \brief (SERCOM_SPI_CTRLB) Slave Select Low Detect Enable */
Kojto 111:4336505e4b1c 435 #define SERCOM_SPI_CTRLB_SSDE (0x1ul << SERCOM_SPI_CTRLB_SSDE_Pos)
Kojto 111:4336505e4b1c 436 #define SERCOM_SPI_CTRLB_MSSEN_Pos 13 /**< \brief (SERCOM_SPI_CTRLB) Master Slave Select Enable */
Kojto 111:4336505e4b1c 437 #define SERCOM_SPI_CTRLB_MSSEN (0x1ul << SERCOM_SPI_CTRLB_MSSEN_Pos)
Kojto 111:4336505e4b1c 438 #define SERCOM_SPI_CTRLB_AMODE_Pos 14 /**< \brief (SERCOM_SPI_CTRLB) Address Mode */
Kojto 111:4336505e4b1c 439 #define SERCOM_SPI_CTRLB_AMODE_Msk (0x3ul << SERCOM_SPI_CTRLB_AMODE_Pos)
Kojto 111:4336505e4b1c 440 #define SERCOM_SPI_CTRLB_AMODE(value) ((SERCOM_SPI_CTRLB_AMODE_Msk & ((value) << SERCOM_SPI_CTRLB_AMODE_Pos)))
Kojto 111:4336505e4b1c 441 #define SERCOM_SPI_CTRLB_RXEN_Pos 17 /**< \brief (SERCOM_SPI_CTRLB) Receiver Enable */
Kojto 111:4336505e4b1c 442 #define SERCOM_SPI_CTRLB_RXEN (0x1ul << SERCOM_SPI_CTRLB_RXEN_Pos)
Kojto 111:4336505e4b1c 443 #define SERCOM_SPI_CTRLB_MASK 0x0002E247ul /**< \brief (SERCOM_SPI_CTRLB) MASK Register */
Kojto 111:4336505e4b1c 444
Kojto 111:4336505e4b1c 445 /* -------- SERCOM_USART_CTRLB : (SERCOM Offset: 0x04) (R/W 32) USART USART Control B -------- */
Kojto 111:4336505e4b1c 446 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 447 typedef union {
Kojto 111:4336505e4b1c 448 struct {
Kojto 111:4336505e4b1c 449 uint32_t CHSIZE:3; /*!< bit: 0.. 2 Character Size */
Kojto 111:4336505e4b1c 450 uint32_t :3; /*!< bit: 3.. 5 Reserved */
Kojto 111:4336505e4b1c 451 uint32_t SBMODE:1; /*!< bit: 6 Stop Bit Mode */
Kojto 111:4336505e4b1c 452 uint32_t :1; /*!< bit: 7 Reserved */
Kojto 111:4336505e4b1c 453 uint32_t COLDEN:1; /*!< bit: 8 Collision Detection Enable */
Kojto 111:4336505e4b1c 454 uint32_t SFDE:1; /*!< bit: 9 Start of Frame Detection Enable */
Kojto 111:4336505e4b1c 455 uint32_t ENC:1; /*!< bit: 10 Encoding Format */
Kojto 111:4336505e4b1c 456 uint32_t :2; /*!< bit: 11..12 Reserved */
Kojto 111:4336505e4b1c 457 uint32_t PMODE:1; /*!< bit: 13 Parity Mode */
Kojto 111:4336505e4b1c 458 uint32_t :2; /*!< bit: 14..15 Reserved */
Kojto 111:4336505e4b1c 459 uint32_t TXEN:1; /*!< bit: 16 Transmitter Enable */
Kojto 111:4336505e4b1c 460 uint32_t RXEN:1; /*!< bit: 17 Receiver Enable */
Kojto 111:4336505e4b1c 461 uint32_t :14; /*!< bit: 18..31 Reserved */
Kojto 111:4336505e4b1c 462 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 463 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 464 } SERCOM_USART_CTRLB_Type;
Kojto 111:4336505e4b1c 465 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 466
Kojto 111:4336505e4b1c 467 #define SERCOM_USART_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_USART_CTRLB offset) USART Control B */
Kojto 111:4336505e4b1c 468 #define SERCOM_USART_CTRLB_RESETVALUE 0x00000000ul /**< \brief (SERCOM_USART_CTRLB reset_value) USART Control B */
Kojto 111:4336505e4b1c 469
Kojto 111:4336505e4b1c 470 #define SERCOM_USART_CTRLB_CHSIZE_Pos 0 /**< \brief (SERCOM_USART_CTRLB) Character Size */
Kojto 111:4336505e4b1c 471 #define SERCOM_USART_CTRLB_CHSIZE_Msk (0x7ul << SERCOM_USART_CTRLB_CHSIZE_Pos)
Kojto 111:4336505e4b1c 472 #define SERCOM_USART_CTRLB_CHSIZE(value) ((SERCOM_USART_CTRLB_CHSIZE_Msk & ((value) << SERCOM_USART_CTRLB_CHSIZE_Pos)))
Kojto 111:4336505e4b1c 473 #define SERCOM_USART_CTRLB_SBMODE_Pos 6 /**< \brief (SERCOM_USART_CTRLB) Stop Bit Mode */
Kojto 111:4336505e4b1c 474 #define SERCOM_USART_CTRLB_SBMODE (0x1ul << SERCOM_USART_CTRLB_SBMODE_Pos)
Kojto 111:4336505e4b1c 475 #define SERCOM_USART_CTRLB_COLDEN_Pos 8 /**< \brief (SERCOM_USART_CTRLB) Collision Detection Enable */
Kojto 111:4336505e4b1c 476 #define SERCOM_USART_CTRLB_COLDEN (0x1ul << SERCOM_USART_CTRLB_COLDEN_Pos)
Kojto 111:4336505e4b1c 477 #define SERCOM_USART_CTRLB_SFDE_Pos 9 /**< \brief (SERCOM_USART_CTRLB) Start of Frame Detection Enable */
Kojto 111:4336505e4b1c 478 #define SERCOM_USART_CTRLB_SFDE (0x1ul << SERCOM_USART_CTRLB_SFDE_Pos)
Kojto 111:4336505e4b1c 479 #define SERCOM_USART_CTRLB_ENC_Pos 10 /**< \brief (SERCOM_USART_CTRLB) Encoding Format */
Kojto 111:4336505e4b1c 480 #define SERCOM_USART_CTRLB_ENC (0x1ul << SERCOM_USART_CTRLB_ENC_Pos)
Kojto 111:4336505e4b1c 481 #define SERCOM_USART_CTRLB_PMODE_Pos 13 /**< \brief (SERCOM_USART_CTRLB) Parity Mode */
Kojto 111:4336505e4b1c 482 #define SERCOM_USART_CTRLB_PMODE (0x1ul << SERCOM_USART_CTRLB_PMODE_Pos)
Kojto 111:4336505e4b1c 483 #define SERCOM_USART_CTRLB_TXEN_Pos 16 /**< \brief (SERCOM_USART_CTRLB) Transmitter Enable */
Kojto 111:4336505e4b1c 484 #define SERCOM_USART_CTRLB_TXEN (0x1ul << SERCOM_USART_CTRLB_TXEN_Pos)
Kojto 111:4336505e4b1c 485 #define SERCOM_USART_CTRLB_RXEN_Pos 17 /**< \brief (SERCOM_USART_CTRLB) Receiver Enable */
Kojto 111:4336505e4b1c 486 #define SERCOM_USART_CTRLB_RXEN (0x1ul << SERCOM_USART_CTRLB_RXEN_Pos)
Kojto 111:4336505e4b1c 487 #define SERCOM_USART_CTRLB_MASK 0x00032747ul /**< \brief (SERCOM_USART_CTRLB) MASK Register */
Kojto 111:4336505e4b1c 488
Kojto 111:4336505e4b1c 489 /* -------- SERCOM_I2CM_BAUD : (SERCOM Offset: 0x0C) (R/W 32) I2CM I2CM Baud Rate -------- */
Kojto 111:4336505e4b1c 490 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 491 typedef union {
Kojto 111:4336505e4b1c 492 struct {
Kojto 111:4336505e4b1c 493 uint32_t BAUD:8; /*!< bit: 0.. 7 Baud Rate Value */
Kojto 111:4336505e4b1c 494 uint32_t BAUDLOW:8; /*!< bit: 8..15 Baud Rate Value Low */
Kojto 111:4336505e4b1c 495 uint32_t HSBAUD:8; /*!< bit: 16..23 High Speed Baud Rate Value */
Kojto 111:4336505e4b1c 496 uint32_t HSBAUDLOW:8; /*!< bit: 24..31 High Speed Baud Rate Value Low */
Kojto 111:4336505e4b1c 497 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 498 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 499 } SERCOM_I2CM_BAUD_Type;
Kojto 111:4336505e4b1c 500 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 501
Kojto 111:4336505e4b1c 502 #define SERCOM_I2CM_BAUD_OFFSET 0x0C /**< \brief (SERCOM_I2CM_BAUD offset) I2CM Baud Rate */
Kojto 111:4336505e4b1c 503 #define SERCOM_I2CM_BAUD_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CM_BAUD reset_value) I2CM Baud Rate */
Kojto 111:4336505e4b1c 504
Kojto 111:4336505e4b1c 505 #define SERCOM_I2CM_BAUD_BAUD_Pos 0 /**< \brief (SERCOM_I2CM_BAUD) Baud Rate Value */
Kojto 111:4336505e4b1c 506 #define SERCOM_I2CM_BAUD_BAUD_Msk (0xFFul << SERCOM_I2CM_BAUD_BAUD_Pos)
Kojto 111:4336505e4b1c 507 #define SERCOM_I2CM_BAUD_BAUD(value) ((SERCOM_I2CM_BAUD_BAUD_Msk & ((value) << SERCOM_I2CM_BAUD_BAUD_Pos)))
Kojto 111:4336505e4b1c 508 #define SERCOM_I2CM_BAUD_BAUDLOW_Pos 8 /**< \brief (SERCOM_I2CM_BAUD) Baud Rate Value Low */
Kojto 111:4336505e4b1c 509 #define SERCOM_I2CM_BAUD_BAUDLOW_Msk (0xFFul << SERCOM_I2CM_BAUD_BAUDLOW_Pos)
Kojto 111:4336505e4b1c 510 #define SERCOM_I2CM_BAUD_BAUDLOW(value) ((SERCOM_I2CM_BAUD_BAUDLOW_Msk & ((value) << SERCOM_I2CM_BAUD_BAUDLOW_Pos)))
Kojto 111:4336505e4b1c 511 #define SERCOM_I2CM_BAUD_HSBAUD_Pos 16 /**< \brief (SERCOM_I2CM_BAUD) High Speed Baud Rate Value */
Kojto 111:4336505e4b1c 512 #define SERCOM_I2CM_BAUD_HSBAUD_Msk (0xFFul << SERCOM_I2CM_BAUD_HSBAUD_Pos)
Kojto 111:4336505e4b1c 513 #define SERCOM_I2CM_BAUD_HSBAUD(value) ((SERCOM_I2CM_BAUD_HSBAUD_Msk & ((value) << SERCOM_I2CM_BAUD_HSBAUD_Pos)))
Kojto 111:4336505e4b1c 514 #define SERCOM_I2CM_BAUD_HSBAUDLOW_Pos 24 /**< \brief (SERCOM_I2CM_BAUD) High Speed Baud Rate Value Low */
Kojto 111:4336505e4b1c 515 #define SERCOM_I2CM_BAUD_HSBAUDLOW_Msk (0xFFul << SERCOM_I2CM_BAUD_HSBAUDLOW_Pos)
Kojto 111:4336505e4b1c 516 #define SERCOM_I2CM_BAUD_HSBAUDLOW(value) ((SERCOM_I2CM_BAUD_HSBAUDLOW_Msk & ((value) << SERCOM_I2CM_BAUD_HSBAUDLOW_Pos)))
Kojto 111:4336505e4b1c 517 #define SERCOM_I2CM_BAUD_MASK 0xFFFFFFFFul /**< \brief (SERCOM_I2CM_BAUD) MASK Register */
Kojto 111:4336505e4b1c 518
Kojto 111:4336505e4b1c 519 /* -------- SERCOM_SPI_BAUD : (SERCOM Offset: 0x0C) (R/W 8) SPI SPI Baud Rate -------- */
Kojto 111:4336505e4b1c 520 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 521 typedef union {
Kojto 111:4336505e4b1c 522 struct {
Kojto 111:4336505e4b1c 523 uint8_t BAUD:8; /*!< bit: 0.. 7 Baud Rate Value */
Kojto 111:4336505e4b1c 524 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 525 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 526 } SERCOM_SPI_BAUD_Type;
Kojto 111:4336505e4b1c 527 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 528
Kojto 111:4336505e4b1c 529 #define SERCOM_SPI_BAUD_OFFSET 0x0C /**< \brief (SERCOM_SPI_BAUD offset) SPI Baud Rate */
Kojto 111:4336505e4b1c 530 #define SERCOM_SPI_BAUD_RESETVALUE 0x00ul /**< \brief (SERCOM_SPI_BAUD reset_value) SPI Baud Rate */
Kojto 111:4336505e4b1c 531
Kojto 111:4336505e4b1c 532 #define SERCOM_SPI_BAUD_BAUD_Pos 0 /**< \brief (SERCOM_SPI_BAUD) Baud Rate Value */
Kojto 111:4336505e4b1c 533 #define SERCOM_SPI_BAUD_BAUD_Msk (0xFFul << SERCOM_SPI_BAUD_BAUD_Pos)
Kojto 111:4336505e4b1c 534 #define SERCOM_SPI_BAUD_BAUD(value) ((SERCOM_SPI_BAUD_BAUD_Msk & ((value) << SERCOM_SPI_BAUD_BAUD_Pos)))
Kojto 111:4336505e4b1c 535 #define SERCOM_SPI_BAUD_MASK 0xFFul /**< \brief (SERCOM_SPI_BAUD) MASK Register */
Kojto 111:4336505e4b1c 536
Kojto 111:4336505e4b1c 537 /* -------- SERCOM_USART_BAUD : (SERCOM Offset: 0x0C) (R/W 16) USART USART Baud Rate -------- */
Kojto 111:4336505e4b1c 538 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 539 typedef union {
Kojto 111:4336505e4b1c 540 struct {
Kojto 111:4336505e4b1c 541 uint16_t BAUD:16; /*!< bit: 0..15 Baud Rate Value */
Kojto 111:4336505e4b1c 542 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 543 struct { // FRAC mode
Kojto 111:4336505e4b1c 544 uint16_t BAUD:13; /*!< bit: 0..12 Baud Rate Value */
Kojto 111:4336505e4b1c 545 uint16_t FP:3; /*!< bit: 13..15 Fractional Part */
Kojto 111:4336505e4b1c 546 } FRAC; /*!< Structure used for FRAC */
Kojto 111:4336505e4b1c 547 struct { // FRACFP mode
Kojto 111:4336505e4b1c 548 uint16_t BAUD:13; /*!< bit: 0..12 Baud Rate Value */
Kojto 111:4336505e4b1c 549 uint16_t FP:3; /*!< bit: 13..15 Fractional Part */
Kojto 111:4336505e4b1c 550 } FRACFP; /*!< Structure used for FRACFP */
Kojto 111:4336505e4b1c 551 struct { // USARTFP mode
Kojto 111:4336505e4b1c 552 uint16_t BAUD:16; /*!< bit: 0..15 Baud Rate Value */
Kojto 111:4336505e4b1c 553 } USARTFP; /*!< Structure used for USARTFP */
Kojto 111:4336505e4b1c 554 uint16_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 555 } SERCOM_USART_BAUD_Type;
Kojto 111:4336505e4b1c 556 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 557
Kojto 111:4336505e4b1c 558 #define SERCOM_USART_BAUD_OFFSET 0x0C /**< \brief (SERCOM_USART_BAUD offset) USART Baud Rate */
Kojto 111:4336505e4b1c 559 #define SERCOM_USART_BAUD_RESETVALUE 0x0000ul /**< \brief (SERCOM_USART_BAUD reset_value) USART Baud Rate */
Kojto 111:4336505e4b1c 560
Kojto 111:4336505e4b1c 561 #define SERCOM_USART_BAUD_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD) Baud Rate Value */
Kojto 111:4336505e4b1c 562 #define SERCOM_USART_BAUD_BAUD_Msk (0xFFFFul << SERCOM_USART_BAUD_BAUD_Pos)
Kojto 111:4336505e4b1c 563 #define SERCOM_USART_BAUD_BAUD(value) ((SERCOM_USART_BAUD_BAUD_Msk & ((value) << SERCOM_USART_BAUD_BAUD_Pos)))
Kojto 111:4336505e4b1c 564 #define SERCOM_USART_BAUD_MASK 0xFFFFul /**< \brief (SERCOM_USART_BAUD) MASK Register */
Kojto 111:4336505e4b1c 565
Kojto 111:4336505e4b1c 566 // FRAC mode
Kojto 111:4336505e4b1c 567 #define SERCOM_USART_BAUD_FRAC_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD_FRAC) Baud Rate Value */
Kojto 111:4336505e4b1c 568 #define SERCOM_USART_BAUD_FRAC_BAUD_Msk (0x1FFFul << SERCOM_USART_BAUD_FRAC_BAUD_Pos)
Kojto 111:4336505e4b1c 569 #define SERCOM_USART_BAUD_FRAC_BAUD(value) ((SERCOM_USART_BAUD_FRAC_BAUD_Msk & ((value) << SERCOM_USART_BAUD_FRAC_BAUD_Pos)))
Kojto 111:4336505e4b1c 570 #define SERCOM_USART_BAUD_FRAC_FP_Pos 13 /**< \brief (SERCOM_USART_BAUD_FRAC) Fractional Part */
Kojto 111:4336505e4b1c 571 #define SERCOM_USART_BAUD_FRAC_FP_Msk (0x7ul << SERCOM_USART_BAUD_FRAC_FP_Pos)
Kojto 111:4336505e4b1c 572 #define SERCOM_USART_BAUD_FRAC_FP(value) ((SERCOM_USART_BAUD_FRAC_FP_Msk & ((value) << SERCOM_USART_BAUD_FRAC_FP_Pos)))
Kojto 111:4336505e4b1c 573 #define SERCOM_USART_BAUD_FRAC_MASK 0xFFFFul /**< \brief (SERCOM_USART_BAUD_FRAC) MASK Register */
Kojto 111:4336505e4b1c 574
Kojto 111:4336505e4b1c 575 // FRACFP mode
Kojto 111:4336505e4b1c 576 #define SERCOM_USART_BAUD_FRACFP_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD_FRACFP) Baud Rate Value */
Kojto 111:4336505e4b1c 577 #define SERCOM_USART_BAUD_FRACFP_BAUD_Msk (0x1FFFul << SERCOM_USART_BAUD_FRACFP_BAUD_Pos)
Kojto 111:4336505e4b1c 578 #define SERCOM_USART_BAUD_FRACFP_BAUD(value) ((SERCOM_USART_BAUD_FRACFP_BAUD_Msk & ((value) << SERCOM_USART_BAUD_FRACFP_BAUD_Pos)))
Kojto 111:4336505e4b1c 579 #define SERCOM_USART_BAUD_FRACFP_FP_Pos 13 /**< \brief (SERCOM_USART_BAUD_FRACFP) Fractional Part */
Kojto 111:4336505e4b1c 580 #define SERCOM_USART_BAUD_FRACFP_FP_Msk (0x7ul << SERCOM_USART_BAUD_FRACFP_FP_Pos)
Kojto 111:4336505e4b1c 581 #define SERCOM_USART_BAUD_FRACFP_FP(value) ((SERCOM_USART_BAUD_FRACFP_FP_Msk & ((value) << SERCOM_USART_BAUD_FRACFP_FP_Pos)))
Kojto 111:4336505e4b1c 582 #define SERCOM_USART_BAUD_FRACFP_MASK 0xFFFFul /**< \brief (SERCOM_USART_BAUD_FRACFP) MASK Register */
Kojto 111:4336505e4b1c 583
Kojto 111:4336505e4b1c 584 // USARTFP mode
Kojto 111:4336505e4b1c 585 #define SERCOM_USART_BAUD_USARTFP_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD_USARTFP) Baud Rate Value */
Kojto 111:4336505e4b1c 586 #define SERCOM_USART_BAUD_USARTFP_BAUD_Msk (0xFFFFul << SERCOM_USART_BAUD_USARTFP_BAUD_Pos)
Kojto 111:4336505e4b1c 587 #define SERCOM_USART_BAUD_USARTFP_BAUD(value) ((SERCOM_USART_BAUD_USARTFP_BAUD_Msk & ((value) << SERCOM_USART_BAUD_USARTFP_BAUD_Pos)))
Kojto 111:4336505e4b1c 588 #define SERCOM_USART_BAUD_USARTFP_MASK 0xFFFFul /**< \brief (SERCOM_USART_BAUD_USARTFP) MASK Register */
Kojto 111:4336505e4b1c 589
Kojto 111:4336505e4b1c 590 /* -------- SERCOM_USART_RXPL : (SERCOM Offset: 0x0E) (R/W 8) USART USART Receive Pulse Length -------- */
Kojto 111:4336505e4b1c 591 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 592 typedef union {
Kojto 111:4336505e4b1c 593 struct {
Kojto 111:4336505e4b1c 594 uint8_t RXPL:8; /*!< bit: 0.. 7 Receive Pulse Length */
Kojto 111:4336505e4b1c 595 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 596 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 597 } SERCOM_USART_RXPL_Type;
Kojto 111:4336505e4b1c 598 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 599
Kojto 111:4336505e4b1c 600 #define SERCOM_USART_RXPL_OFFSET 0x0E /**< \brief (SERCOM_USART_RXPL offset) USART Receive Pulse Length */
Kojto 111:4336505e4b1c 601 #define SERCOM_USART_RXPL_RESETVALUE 0x00ul /**< \brief (SERCOM_USART_RXPL reset_value) USART Receive Pulse Length */
Kojto 111:4336505e4b1c 602
Kojto 111:4336505e4b1c 603 #define SERCOM_USART_RXPL_RXPL_Pos 0 /**< \brief (SERCOM_USART_RXPL) Receive Pulse Length */
Kojto 111:4336505e4b1c 604 #define SERCOM_USART_RXPL_RXPL_Msk (0xFFul << SERCOM_USART_RXPL_RXPL_Pos)
Kojto 111:4336505e4b1c 605 #define SERCOM_USART_RXPL_RXPL(value) ((SERCOM_USART_RXPL_RXPL_Msk & ((value) << SERCOM_USART_RXPL_RXPL_Pos)))
Kojto 111:4336505e4b1c 606 #define SERCOM_USART_RXPL_MASK 0xFFul /**< \brief (SERCOM_USART_RXPL) MASK Register */
Kojto 111:4336505e4b1c 607
Kojto 111:4336505e4b1c 608 /* -------- SERCOM_I2CM_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) I2CM I2CM Interrupt Enable Clear -------- */
Kojto 111:4336505e4b1c 609 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 610 typedef union {
Kojto 111:4336505e4b1c 611 struct {
Kojto 111:4336505e4b1c 612 uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt Disable */
Kojto 111:4336505e4b1c 613 uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt Disable */
Kojto 111:4336505e4b1c 614 uint8_t :5; /*!< bit: 2.. 6 Reserved */
Kojto 111:4336505e4b1c 615 uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */
Kojto 111:4336505e4b1c 616 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 617 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 618 } SERCOM_I2CM_INTENCLR_Type;
Kojto 111:4336505e4b1c 619 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 620
Kojto 111:4336505e4b1c 621 #define SERCOM_I2CM_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_I2CM_INTENCLR offset) I2CM Interrupt Enable Clear */
Kojto 111:4336505e4b1c 622 #define SERCOM_I2CM_INTENCLR_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CM_INTENCLR reset_value) I2CM Interrupt Enable Clear */
Kojto 111:4336505e4b1c 623
Kojto 111:4336505e4b1c 624 #define SERCOM_I2CM_INTENCLR_MB_Pos 0 /**< \brief (SERCOM_I2CM_INTENCLR) Master On Bus Interrupt Disable */
Kojto 111:4336505e4b1c 625 #define SERCOM_I2CM_INTENCLR_MB (0x1ul << SERCOM_I2CM_INTENCLR_MB_Pos)
Kojto 111:4336505e4b1c 626 #define SERCOM_I2CM_INTENCLR_SB_Pos 1 /**< \brief (SERCOM_I2CM_INTENCLR) Slave On Bus Interrupt Disable */
Kojto 111:4336505e4b1c 627 #define SERCOM_I2CM_INTENCLR_SB (0x1ul << SERCOM_I2CM_INTENCLR_SB_Pos)
Kojto 111:4336505e4b1c 628 #define SERCOM_I2CM_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_I2CM_INTENCLR) Combined Error Interrupt Disable */
Kojto 111:4336505e4b1c 629 #define SERCOM_I2CM_INTENCLR_ERROR (0x1ul << SERCOM_I2CM_INTENCLR_ERROR_Pos)
Kojto 111:4336505e4b1c 630 #define SERCOM_I2CM_INTENCLR_MASK 0x83ul /**< \brief (SERCOM_I2CM_INTENCLR) MASK Register */
Kojto 111:4336505e4b1c 631
Kojto 111:4336505e4b1c 632 /* -------- SERCOM_I2CS_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) I2CS I2CS Interrupt Enable Clear -------- */
Kojto 111:4336505e4b1c 633 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 634 typedef union {
Kojto 111:4336505e4b1c 635 struct {
Kojto 111:4336505e4b1c 636 uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt Disable */
Kojto 111:4336505e4b1c 637 uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt Disable */
Kojto 111:4336505e4b1c 638 uint8_t DRDY:1; /*!< bit: 2 Data Interrupt Disable */
Kojto 111:4336505e4b1c 639 uint8_t :4; /*!< bit: 3.. 6 Reserved */
Kojto 111:4336505e4b1c 640 uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */
Kojto 111:4336505e4b1c 641 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 642 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 643 } SERCOM_I2CS_INTENCLR_Type;
Kojto 111:4336505e4b1c 644 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 645
Kojto 111:4336505e4b1c 646 #define SERCOM_I2CS_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_I2CS_INTENCLR offset) I2CS Interrupt Enable Clear */
Kojto 111:4336505e4b1c 647 #define SERCOM_I2CS_INTENCLR_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CS_INTENCLR reset_value) I2CS Interrupt Enable Clear */
Kojto 111:4336505e4b1c 648
Kojto 111:4336505e4b1c 649 #define SERCOM_I2CS_INTENCLR_PREC_Pos 0 /**< \brief (SERCOM_I2CS_INTENCLR) Stop Received Interrupt Disable */
Kojto 111:4336505e4b1c 650 #define SERCOM_I2CS_INTENCLR_PREC (0x1ul << SERCOM_I2CS_INTENCLR_PREC_Pos)
Kojto 111:4336505e4b1c 651 #define SERCOM_I2CS_INTENCLR_AMATCH_Pos 1 /**< \brief (SERCOM_I2CS_INTENCLR) Address Match Interrupt Disable */
Kojto 111:4336505e4b1c 652 #define SERCOM_I2CS_INTENCLR_AMATCH (0x1ul << SERCOM_I2CS_INTENCLR_AMATCH_Pos)
Kojto 111:4336505e4b1c 653 #define SERCOM_I2CS_INTENCLR_DRDY_Pos 2 /**< \brief (SERCOM_I2CS_INTENCLR) Data Interrupt Disable */
Kojto 111:4336505e4b1c 654 #define SERCOM_I2CS_INTENCLR_DRDY (0x1ul << SERCOM_I2CS_INTENCLR_DRDY_Pos)
Kojto 111:4336505e4b1c 655 #define SERCOM_I2CS_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_I2CS_INTENCLR) Combined Error Interrupt Disable */
Kojto 111:4336505e4b1c 656 #define SERCOM_I2CS_INTENCLR_ERROR (0x1ul << SERCOM_I2CS_INTENCLR_ERROR_Pos)
Kojto 111:4336505e4b1c 657 #define SERCOM_I2CS_INTENCLR_MASK 0x87ul /**< \brief (SERCOM_I2CS_INTENCLR) MASK Register */
Kojto 111:4336505e4b1c 658
Kojto 111:4336505e4b1c 659 /* -------- SERCOM_SPI_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) SPI SPI Interrupt Enable Clear -------- */
Kojto 111:4336505e4b1c 660 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 661 typedef union {
Kojto 111:4336505e4b1c 662 struct {
Kojto 111:4336505e4b1c 663 uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Disable */
Kojto 111:4336505e4b1c 664 uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Disable */
Kojto 111:4336505e4b1c 665 uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Disable */
Kojto 111:4336505e4b1c 666 uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Disable */
Kojto 111:4336505e4b1c 667 uint8_t :3; /*!< bit: 4.. 6 Reserved */
Kojto 111:4336505e4b1c 668 uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */
Kojto 111:4336505e4b1c 669 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 670 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 671 } SERCOM_SPI_INTENCLR_Type;
Kojto 111:4336505e4b1c 672 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 673
Kojto 111:4336505e4b1c 674 #define SERCOM_SPI_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_SPI_INTENCLR offset) SPI Interrupt Enable Clear */
Kojto 111:4336505e4b1c 675 #define SERCOM_SPI_INTENCLR_RESETVALUE 0x00ul /**< \brief (SERCOM_SPI_INTENCLR reset_value) SPI Interrupt Enable Clear */
Kojto 111:4336505e4b1c 676
Kojto 111:4336505e4b1c 677 #define SERCOM_SPI_INTENCLR_DRE_Pos 0 /**< \brief (SERCOM_SPI_INTENCLR) Data Register Empty Interrupt Disable */
Kojto 111:4336505e4b1c 678 #define SERCOM_SPI_INTENCLR_DRE (0x1ul << SERCOM_SPI_INTENCLR_DRE_Pos)
Kojto 111:4336505e4b1c 679 #define SERCOM_SPI_INTENCLR_TXC_Pos 1 /**< \brief (SERCOM_SPI_INTENCLR) Transmit Complete Interrupt Disable */
Kojto 111:4336505e4b1c 680 #define SERCOM_SPI_INTENCLR_TXC (0x1ul << SERCOM_SPI_INTENCLR_TXC_Pos)
Kojto 111:4336505e4b1c 681 #define SERCOM_SPI_INTENCLR_RXC_Pos 2 /**< \brief (SERCOM_SPI_INTENCLR) Receive Complete Interrupt Disable */
Kojto 111:4336505e4b1c 682 #define SERCOM_SPI_INTENCLR_RXC (0x1ul << SERCOM_SPI_INTENCLR_RXC_Pos)
Kojto 111:4336505e4b1c 683 #define SERCOM_SPI_INTENCLR_SSL_Pos 3 /**< \brief (SERCOM_SPI_INTENCLR) Slave Select Low Interrupt Disable */
Kojto 111:4336505e4b1c 684 #define SERCOM_SPI_INTENCLR_SSL (0x1ul << SERCOM_SPI_INTENCLR_SSL_Pos)
Kojto 111:4336505e4b1c 685 #define SERCOM_SPI_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_SPI_INTENCLR) Combined Error Interrupt Disable */
Kojto 111:4336505e4b1c 686 #define SERCOM_SPI_INTENCLR_ERROR (0x1ul << SERCOM_SPI_INTENCLR_ERROR_Pos)
Kojto 111:4336505e4b1c 687 #define SERCOM_SPI_INTENCLR_MASK 0x8Ful /**< \brief (SERCOM_SPI_INTENCLR) MASK Register */
Kojto 111:4336505e4b1c 688
Kojto 111:4336505e4b1c 689 /* -------- SERCOM_USART_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) USART USART Interrupt Enable Clear -------- */
Kojto 111:4336505e4b1c 690 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 691 typedef union {
Kojto 111:4336505e4b1c 692 struct {
Kojto 111:4336505e4b1c 693 uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Disable */
Kojto 111:4336505e4b1c 694 uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Disable */
Kojto 111:4336505e4b1c 695 uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Disable */
Kojto 111:4336505e4b1c 696 uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt Disable */
Kojto 111:4336505e4b1c 697 uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt Disable */
Kojto 111:4336505e4b1c 698 uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt Disable */
Kojto 111:4336505e4b1c 699 uint8_t :1; /*!< bit: 6 Reserved */
Kojto 111:4336505e4b1c 700 uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */
Kojto 111:4336505e4b1c 701 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 702 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 703 } SERCOM_USART_INTENCLR_Type;
Kojto 111:4336505e4b1c 704 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 705
Kojto 111:4336505e4b1c 706 #define SERCOM_USART_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_USART_INTENCLR offset) USART Interrupt Enable Clear */
Kojto 111:4336505e4b1c 707 #define SERCOM_USART_INTENCLR_RESETVALUE 0x00ul /**< \brief (SERCOM_USART_INTENCLR reset_value) USART Interrupt Enable Clear */
Kojto 111:4336505e4b1c 708
Kojto 111:4336505e4b1c 709 #define SERCOM_USART_INTENCLR_DRE_Pos 0 /**< \brief (SERCOM_USART_INTENCLR) Data Register Empty Interrupt Disable */
Kojto 111:4336505e4b1c 710 #define SERCOM_USART_INTENCLR_DRE (0x1ul << SERCOM_USART_INTENCLR_DRE_Pos)
Kojto 111:4336505e4b1c 711 #define SERCOM_USART_INTENCLR_TXC_Pos 1 /**< \brief (SERCOM_USART_INTENCLR) Transmit Complete Interrupt Disable */
Kojto 111:4336505e4b1c 712 #define SERCOM_USART_INTENCLR_TXC (0x1ul << SERCOM_USART_INTENCLR_TXC_Pos)
Kojto 111:4336505e4b1c 713 #define SERCOM_USART_INTENCLR_RXC_Pos 2 /**< \brief (SERCOM_USART_INTENCLR) Receive Complete Interrupt Disable */
Kojto 111:4336505e4b1c 714 #define SERCOM_USART_INTENCLR_RXC (0x1ul << SERCOM_USART_INTENCLR_RXC_Pos)
Kojto 111:4336505e4b1c 715 #define SERCOM_USART_INTENCLR_RXS_Pos 3 /**< \brief (SERCOM_USART_INTENCLR) Receive Start Interrupt Disable */
Kojto 111:4336505e4b1c 716 #define SERCOM_USART_INTENCLR_RXS (0x1ul << SERCOM_USART_INTENCLR_RXS_Pos)
Kojto 111:4336505e4b1c 717 #define SERCOM_USART_INTENCLR_CTSIC_Pos 4 /**< \brief (SERCOM_USART_INTENCLR) Clear To Send Input Change Interrupt Disable */
Kojto 111:4336505e4b1c 718 #define SERCOM_USART_INTENCLR_CTSIC (0x1ul << SERCOM_USART_INTENCLR_CTSIC_Pos)
Kojto 111:4336505e4b1c 719 #define SERCOM_USART_INTENCLR_RXBRK_Pos 5 /**< \brief (SERCOM_USART_INTENCLR) Break Received Interrupt Disable */
Kojto 111:4336505e4b1c 720 #define SERCOM_USART_INTENCLR_RXBRK (0x1ul << SERCOM_USART_INTENCLR_RXBRK_Pos)
Kojto 111:4336505e4b1c 721 #define SERCOM_USART_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_USART_INTENCLR) Combined Error Interrupt Disable */
Kojto 111:4336505e4b1c 722 #define SERCOM_USART_INTENCLR_ERROR (0x1ul << SERCOM_USART_INTENCLR_ERROR_Pos)
Kojto 111:4336505e4b1c 723 #define SERCOM_USART_INTENCLR_MASK 0xBFul /**< \brief (SERCOM_USART_INTENCLR) MASK Register */
Kojto 111:4336505e4b1c 724
Kojto 111:4336505e4b1c 725 /* -------- SERCOM_I2CM_INTENSET : (SERCOM Offset: 0x16) (R/W 8) I2CM I2CM Interrupt Enable Set -------- */
Kojto 111:4336505e4b1c 726 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 727 typedef union {
Kojto 111:4336505e4b1c 728 struct {
Kojto 111:4336505e4b1c 729 uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt Enable */
Kojto 111:4336505e4b1c 730 uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt Enable */
Kojto 111:4336505e4b1c 731 uint8_t :5; /*!< bit: 2.. 6 Reserved */
Kojto 111:4336505e4b1c 732 uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */
Kojto 111:4336505e4b1c 733 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 734 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 735 } SERCOM_I2CM_INTENSET_Type;
Kojto 111:4336505e4b1c 736 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 737
Kojto 111:4336505e4b1c 738 #define SERCOM_I2CM_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_I2CM_INTENSET offset) I2CM Interrupt Enable Set */
Kojto 111:4336505e4b1c 739 #define SERCOM_I2CM_INTENSET_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CM_INTENSET reset_value) I2CM Interrupt Enable Set */
Kojto 111:4336505e4b1c 740
Kojto 111:4336505e4b1c 741 #define SERCOM_I2CM_INTENSET_MB_Pos 0 /**< \brief (SERCOM_I2CM_INTENSET) Master On Bus Interrupt Enable */
Kojto 111:4336505e4b1c 742 #define SERCOM_I2CM_INTENSET_MB (0x1ul << SERCOM_I2CM_INTENSET_MB_Pos)
Kojto 111:4336505e4b1c 743 #define SERCOM_I2CM_INTENSET_SB_Pos 1 /**< \brief (SERCOM_I2CM_INTENSET) Slave On Bus Interrupt Enable */
Kojto 111:4336505e4b1c 744 #define SERCOM_I2CM_INTENSET_SB (0x1ul << SERCOM_I2CM_INTENSET_SB_Pos)
Kojto 111:4336505e4b1c 745 #define SERCOM_I2CM_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_I2CM_INTENSET) Combined Error Interrupt Enable */
Kojto 111:4336505e4b1c 746 #define SERCOM_I2CM_INTENSET_ERROR (0x1ul << SERCOM_I2CM_INTENSET_ERROR_Pos)
Kojto 111:4336505e4b1c 747 #define SERCOM_I2CM_INTENSET_MASK 0x83ul /**< \brief (SERCOM_I2CM_INTENSET) MASK Register */
Kojto 111:4336505e4b1c 748
Kojto 111:4336505e4b1c 749 /* -------- SERCOM_I2CS_INTENSET : (SERCOM Offset: 0x16) (R/W 8) I2CS I2CS Interrupt Enable Set -------- */
Kojto 111:4336505e4b1c 750 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 751 typedef union {
Kojto 111:4336505e4b1c 752 struct {
Kojto 111:4336505e4b1c 753 uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt Enable */
Kojto 111:4336505e4b1c 754 uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt Enable */
Kojto 111:4336505e4b1c 755 uint8_t DRDY:1; /*!< bit: 2 Data Interrupt Enable */
Kojto 111:4336505e4b1c 756 uint8_t :4; /*!< bit: 3.. 6 Reserved */
Kojto 111:4336505e4b1c 757 uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */
Kojto 111:4336505e4b1c 758 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 759 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 760 } SERCOM_I2CS_INTENSET_Type;
Kojto 111:4336505e4b1c 761 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 762
Kojto 111:4336505e4b1c 763 #define SERCOM_I2CS_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_I2CS_INTENSET offset) I2CS Interrupt Enable Set */
Kojto 111:4336505e4b1c 764 #define SERCOM_I2CS_INTENSET_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CS_INTENSET reset_value) I2CS Interrupt Enable Set */
Kojto 111:4336505e4b1c 765
Kojto 111:4336505e4b1c 766 #define SERCOM_I2CS_INTENSET_PREC_Pos 0 /**< \brief (SERCOM_I2CS_INTENSET) Stop Received Interrupt Enable */
Kojto 111:4336505e4b1c 767 #define SERCOM_I2CS_INTENSET_PREC (0x1ul << SERCOM_I2CS_INTENSET_PREC_Pos)
Kojto 111:4336505e4b1c 768 #define SERCOM_I2CS_INTENSET_AMATCH_Pos 1 /**< \brief (SERCOM_I2CS_INTENSET) Address Match Interrupt Enable */
Kojto 111:4336505e4b1c 769 #define SERCOM_I2CS_INTENSET_AMATCH (0x1ul << SERCOM_I2CS_INTENSET_AMATCH_Pos)
Kojto 111:4336505e4b1c 770 #define SERCOM_I2CS_INTENSET_DRDY_Pos 2 /**< \brief (SERCOM_I2CS_INTENSET) Data Interrupt Enable */
Kojto 111:4336505e4b1c 771 #define SERCOM_I2CS_INTENSET_DRDY (0x1ul << SERCOM_I2CS_INTENSET_DRDY_Pos)
Kojto 111:4336505e4b1c 772 #define SERCOM_I2CS_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_I2CS_INTENSET) Combined Error Interrupt Enable */
Kojto 111:4336505e4b1c 773 #define SERCOM_I2CS_INTENSET_ERROR (0x1ul << SERCOM_I2CS_INTENSET_ERROR_Pos)
Kojto 111:4336505e4b1c 774 #define SERCOM_I2CS_INTENSET_MASK 0x87ul /**< \brief (SERCOM_I2CS_INTENSET) MASK Register */
Kojto 111:4336505e4b1c 775
Kojto 111:4336505e4b1c 776 /* -------- SERCOM_SPI_INTENSET : (SERCOM Offset: 0x16) (R/W 8) SPI SPI Interrupt Enable Set -------- */
Kojto 111:4336505e4b1c 777 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 778 typedef union {
Kojto 111:4336505e4b1c 779 struct {
Kojto 111:4336505e4b1c 780 uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */
Kojto 111:4336505e4b1c 781 uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */
Kojto 111:4336505e4b1c 782 uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */
Kojto 111:4336505e4b1c 783 uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Enable */
Kojto 111:4336505e4b1c 784 uint8_t :3; /*!< bit: 4.. 6 Reserved */
Kojto 111:4336505e4b1c 785 uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */
Kojto 111:4336505e4b1c 786 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 787 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 788 } SERCOM_SPI_INTENSET_Type;
Kojto 111:4336505e4b1c 789 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 790
Kojto 111:4336505e4b1c 791 #define SERCOM_SPI_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_SPI_INTENSET offset) SPI Interrupt Enable Set */
Kojto 111:4336505e4b1c 792 #define SERCOM_SPI_INTENSET_RESETVALUE 0x00ul /**< \brief (SERCOM_SPI_INTENSET reset_value) SPI Interrupt Enable Set */
Kojto 111:4336505e4b1c 793
Kojto 111:4336505e4b1c 794 #define SERCOM_SPI_INTENSET_DRE_Pos 0 /**< \brief (SERCOM_SPI_INTENSET) Data Register Empty Interrupt Enable */
Kojto 111:4336505e4b1c 795 #define SERCOM_SPI_INTENSET_DRE (0x1ul << SERCOM_SPI_INTENSET_DRE_Pos)
Kojto 111:4336505e4b1c 796 #define SERCOM_SPI_INTENSET_TXC_Pos 1 /**< \brief (SERCOM_SPI_INTENSET) Transmit Complete Interrupt Enable */
Kojto 111:4336505e4b1c 797 #define SERCOM_SPI_INTENSET_TXC (0x1ul << SERCOM_SPI_INTENSET_TXC_Pos)
Kojto 111:4336505e4b1c 798 #define SERCOM_SPI_INTENSET_RXC_Pos 2 /**< \brief (SERCOM_SPI_INTENSET) Receive Complete Interrupt Enable */
Kojto 111:4336505e4b1c 799 #define SERCOM_SPI_INTENSET_RXC (0x1ul << SERCOM_SPI_INTENSET_RXC_Pos)
Kojto 111:4336505e4b1c 800 #define SERCOM_SPI_INTENSET_SSL_Pos 3 /**< \brief (SERCOM_SPI_INTENSET) Slave Select Low Interrupt Enable */
Kojto 111:4336505e4b1c 801 #define SERCOM_SPI_INTENSET_SSL (0x1ul << SERCOM_SPI_INTENSET_SSL_Pos)
Kojto 111:4336505e4b1c 802 #define SERCOM_SPI_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_SPI_INTENSET) Combined Error Interrupt Enable */
Kojto 111:4336505e4b1c 803 #define SERCOM_SPI_INTENSET_ERROR (0x1ul << SERCOM_SPI_INTENSET_ERROR_Pos)
Kojto 111:4336505e4b1c 804 #define SERCOM_SPI_INTENSET_MASK 0x8Ful /**< \brief (SERCOM_SPI_INTENSET) MASK Register */
Kojto 111:4336505e4b1c 805
Kojto 111:4336505e4b1c 806 /* -------- SERCOM_USART_INTENSET : (SERCOM Offset: 0x16) (R/W 8) USART USART Interrupt Enable Set -------- */
Kojto 111:4336505e4b1c 807 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 808 typedef union {
Kojto 111:4336505e4b1c 809 struct {
Kojto 111:4336505e4b1c 810 uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */
Kojto 111:4336505e4b1c 811 uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */
Kojto 111:4336505e4b1c 812 uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */
Kojto 111:4336505e4b1c 813 uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt Enable */
Kojto 111:4336505e4b1c 814 uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt Enable */
Kojto 111:4336505e4b1c 815 uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt Enable */
Kojto 111:4336505e4b1c 816 uint8_t :1; /*!< bit: 6 Reserved */
Kojto 111:4336505e4b1c 817 uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */
Kojto 111:4336505e4b1c 818 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 819 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 820 } SERCOM_USART_INTENSET_Type;
Kojto 111:4336505e4b1c 821 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 822
Kojto 111:4336505e4b1c 823 #define SERCOM_USART_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_USART_INTENSET offset) USART Interrupt Enable Set */
Kojto 111:4336505e4b1c 824 #define SERCOM_USART_INTENSET_RESETVALUE 0x00ul /**< \brief (SERCOM_USART_INTENSET reset_value) USART Interrupt Enable Set */
Kojto 111:4336505e4b1c 825
Kojto 111:4336505e4b1c 826 #define SERCOM_USART_INTENSET_DRE_Pos 0 /**< \brief (SERCOM_USART_INTENSET) Data Register Empty Interrupt Enable */
Kojto 111:4336505e4b1c 827 #define SERCOM_USART_INTENSET_DRE (0x1ul << SERCOM_USART_INTENSET_DRE_Pos)
Kojto 111:4336505e4b1c 828 #define SERCOM_USART_INTENSET_TXC_Pos 1 /**< \brief (SERCOM_USART_INTENSET) Transmit Complete Interrupt Enable */
Kojto 111:4336505e4b1c 829 #define SERCOM_USART_INTENSET_TXC (0x1ul << SERCOM_USART_INTENSET_TXC_Pos)
Kojto 111:4336505e4b1c 830 #define SERCOM_USART_INTENSET_RXC_Pos 2 /**< \brief (SERCOM_USART_INTENSET) Receive Complete Interrupt Enable */
Kojto 111:4336505e4b1c 831 #define SERCOM_USART_INTENSET_RXC (0x1ul << SERCOM_USART_INTENSET_RXC_Pos)
Kojto 111:4336505e4b1c 832 #define SERCOM_USART_INTENSET_RXS_Pos 3 /**< \brief (SERCOM_USART_INTENSET) Receive Start Interrupt Enable */
Kojto 111:4336505e4b1c 833 #define SERCOM_USART_INTENSET_RXS (0x1ul << SERCOM_USART_INTENSET_RXS_Pos)
Kojto 111:4336505e4b1c 834 #define SERCOM_USART_INTENSET_CTSIC_Pos 4 /**< \brief (SERCOM_USART_INTENSET) Clear To Send Input Change Interrupt Enable */
Kojto 111:4336505e4b1c 835 #define SERCOM_USART_INTENSET_CTSIC (0x1ul << SERCOM_USART_INTENSET_CTSIC_Pos)
Kojto 111:4336505e4b1c 836 #define SERCOM_USART_INTENSET_RXBRK_Pos 5 /**< \brief (SERCOM_USART_INTENSET) Break Received Interrupt Enable */
Kojto 111:4336505e4b1c 837 #define SERCOM_USART_INTENSET_RXBRK (0x1ul << SERCOM_USART_INTENSET_RXBRK_Pos)
Kojto 111:4336505e4b1c 838 #define SERCOM_USART_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_USART_INTENSET) Combined Error Interrupt Enable */
Kojto 111:4336505e4b1c 839 #define SERCOM_USART_INTENSET_ERROR (0x1ul << SERCOM_USART_INTENSET_ERROR_Pos)
Kojto 111:4336505e4b1c 840 #define SERCOM_USART_INTENSET_MASK 0xBFul /**< \brief (SERCOM_USART_INTENSET) MASK Register */
Kojto 111:4336505e4b1c 841
Kojto 111:4336505e4b1c 842 /* -------- SERCOM_I2CM_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) I2CM I2CM Interrupt Flag Status and Clear -------- */
Kojto 111:4336505e4b1c 843 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 844 typedef union {
Kojto 111:4336505e4b1c 845 struct {
Kojto 111:4336505e4b1c 846 uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt */
Kojto 111:4336505e4b1c 847 uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt */
Kojto 111:4336505e4b1c 848 uint8_t :5; /*!< bit: 2.. 6 Reserved */
Kojto 111:4336505e4b1c 849 uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
Kojto 111:4336505e4b1c 850 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 851 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 852 } SERCOM_I2CM_INTFLAG_Type;
Kojto 111:4336505e4b1c 853 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 854
Kojto 111:4336505e4b1c 855 #define SERCOM_I2CM_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_I2CM_INTFLAG offset) I2CM Interrupt Flag Status and Clear */
Kojto 111:4336505e4b1c 856 #define SERCOM_I2CM_INTFLAG_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CM_INTFLAG reset_value) I2CM Interrupt Flag Status and Clear */
Kojto 111:4336505e4b1c 857
Kojto 111:4336505e4b1c 858 #define SERCOM_I2CM_INTFLAG_MB_Pos 0 /**< \brief (SERCOM_I2CM_INTFLAG) Master On Bus Interrupt */
Kojto 111:4336505e4b1c 859 #define SERCOM_I2CM_INTFLAG_MB (0x1ul << SERCOM_I2CM_INTFLAG_MB_Pos)
Kojto 111:4336505e4b1c 860 #define SERCOM_I2CM_INTFLAG_SB_Pos 1 /**< \brief (SERCOM_I2CM_INTFLAG) Slave On Bus Interrupt */
Kojto 111:4336505e4b1c 861 #define SERCOM_I2CM_INTFLAG_SB (0x1ul << SERCOM_I2CM_INTFLAG_SB_Pos)
Kojto 111:4336505e4b1c 862 #define SERCOM_I2CM_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_I2CM_INTFLAG) Combined Error Interrupt */
Kojto 111:4336505e4b1c 863 #define SERCOM_I2CM_INTFLAG_ERROR (0x1ul << SERCOM_I2CM_INTFLAG_ERROR_Pos)
Kojto 111:4336505e4b1c 864 #define SERCOM_I2CM_INTFLAG_MASK 0x83ul /**< \brief (SERCOM_I2CM_INTFLAG) MASK Register */
Kojto 111:4336505e4b1c 865
Kojto 111:4336505e4b1c 866 /* -------- SERCOM_I2CS_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) I2CS I2CS Interrupt Flag Status and Clear -------- */
Kojto 111:4336505e4b1c 867 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 868 typedef union {
Kojto 111:4336505e4b1c 869 struct {
Kojto 111:4336505e4b1c 870 uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt */
Kojto 111:4336505e4b1c 871 uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt */
Kojto 111:4336505e4b1c 872 uint8_t DRDY:1; /*!< bit: 2 Data Interrupt */
Kojto 111:4336505e4b1c 873 uint8_t :4; /*!< bit: 3.. 6 Reserved */
Kojto 111:4336505e4b1c 874 uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
Kojto 111:4336505e4b1c 875 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 876 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 877 } SERCOM_I2CS_INTFLAG_Type;
Kojto 111:4336505e4b1c 878 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 879
Kojto 111:4336505e4b1c 880 #define SERCOM_I2CS_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_I2CS_INTFLAG offset) I2CS Interrupt Flag Status and Clear */
Kojto 111:4336505e4b1c 881 #define SERCOM_I2CS_INTFLAG_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CS_INTFLAG reset_value) I2CS Interrupt Flag Status and Clear */
Kojto 111:4336505e4b1c 882
Kojto 111:4336505e4b1c 883 #define SERCOM_I2CS_INTFLAG_PREC_Pos 0 /**< \brief (SERCOM_I2CS_INTFLAG) Stop Received Interrupt */
Kojto 111:4336505e4b1c 884 #define SERCOM_I2CS_INTFLAG_PREC (0x1ul << SERCOM_I2CS_INTFLAG_PREC_Pos)
Kojto 111:4336505e4b1c 885 #define SERCOM_I2CS_INTFLAG_AMATCH_Pos 1 /**< \brief (SERCOM_I2CS_INTFLAG) Address Match Interrupt */
Kojto 111:4336505e4b1c 886 #define SERCOM_I2CS_INTFLAG_AMATCH (0x1ul << SERCOM_I2CS_INTFLAG_AMATCH_Pos)
Kojto 111:4336505e4b1c 887 #define SERCOM_I2CS_INTFLAG_DRDY_Pos 2 /**< \brief (SERCOM_I2CS_INTFLAG) Data Interrupt */
Kojto 111:4336505e4b1c 888 #define SERCOM_I2CS_INTFLAG_DRDY (0x1ul << SERCOM_I2CS_INTFLAG_DRDY_Pos)
Kojto 111:4336505e4b1c 889 #define SERCOM_I2CS_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_I2CS_INTFLAG) Combined Error Interrupt */
Kojto 111:4336505e4b1c 890 #define SERCOM_I2CS_INTFLAG_ERROR (0x1ul << SERCOM_I2CS_INTFLAG_ERROR_Pos)
Kojto 111:4336505e4b1c 891 #define SERCOM_I2CS_INTFLAG_MASK 0x87ul /**< \brief (SERCOM_I2CS_INTFLAG) MASK Register */
Kojto 111:4336505e4b1c 892
Kojto 111:4336505e4b1c 893 /* -------- SERCOM_SPI_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) SPI SPI Interrupt Flag Status and Clear -------- */
Kojto 111:4336505e4b1c 894 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 895 typedef union {
Kojto 111:4336505e4b1c 896 struct {
Kojto 111:4336505e4b1c 897 uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */
Kojto 111:4336505e4b1c 898 uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */
Kojto 111:4336505e4b1c 899 uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */
Kojto 111:4336505e4b1c 900 uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Flag */
Kojto 111:4336505e4b1c 901 uint8_t :3; /*!< bit: 4.. 6 Reserved */
Kojto 111:4336505e4b1c 902 uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
Kojto 111:4336505e4b1c 903 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 904 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 905 } SERCOM_SPI_INTFLAG_Type;
Kojto 111:4336505e4b1c 906 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 907
Kojto 111:4336505e4b1c 908 #define SERCOM_SPI_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_SPI_INTFLAG offset) SPI Interrupt Flag Status and Clear */
Kojto 111:4336505e4b1c 909 #define SERCOM_SPI_INTFLAG_RESETVALUE 0x00ul /**< \brief (SERCOM_SPI_INTFLAG reset_value) SPI Interrupt Flag Status and Clear */
Kojto 111:4336505e4b1c 910
Kojto 111:4336505e4b1c 911 #define SERCOM_SPI_INTFLAG_DRE_Pos 0 /**< \brief (SERCOM_SPI_INTFLAG) Data Register Empty Interrupt */
Kojto 111:4336505e4b1c 912 #define SERCOM_SPI_INTFLAG_DRE (0x1ul << SERCOM_SPI_INTFLAG_DRE_Pos)
Kojto 111:4336505e4b1c 913 #define SERCOM_SPI_INTFLAG_TXC_Pos 1 /**< \brief (SERCOM_SPI_INTFLAG) Transmit Complete Interrupt */
Kojto 111:4336505e4b1c 914 #define SERCOM_SPI_INTFLAG_TXC (0x1ul << SERCOM_SPI_INTFLAG_TXC_Pos)
Kojto 111:4336505e4b1c 915 #define SERCOM_SPI_INTFLAG_RXC_Pos 2 /**< \brief (SERCOM_SPI_INTFLAG) Receive Complete Interrupt */
Kojto 111:4336505e4b1c 916 #define SERCOM_SPI_INTFLAG_RXC (0x1ul << SERCOM_SPI_INTFLAG_RXC_Pos)
Kojto 111:4336505e4b1c 917 #define SERCOM_SPI_INTFLAG_SSL_Pos 3 /**< \brief (SERCOM_SPI_INTFLAG) Slave Select Low Interrupt Flag */
Kojto 111:4336505e4b1c 918 #define SERCOM_SPI_INTFLAG_SSL (0x1ul << SERCOM_SPI_INTFLAG_SSL_Pos)
Kojto 111:4336505e4b1c 919 #define SERCOM_SPI_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_SPI_INTFLAG) Combined Error Interrupt */
Kojto 111:4336505e4b1c 920 #define SERCOM_SPI_INTFLAG_ERROR (0x1ul << SERCOM_SPI_INTFLAG_ERROR_Pos)
Kojto 111:4336505e4b1c 921 #define SERCOM_SPI_INTFLAG_MASK 0x8Ful /**< \brief (SERCOM_SPI_INTFLAG) MASK Register */
Kojto 111:4336505e4b1c 922
Kojto 111:4336505e4b1c 923 /* -------- SERCOM_USART_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) USART USART Interrupt Flag Status and Clear -------- */
Kojto 111:4336505e4b1c 924 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 925 typedef union {
Kojto 111:4336505e4b1c 926 struct {
Kojto 111:4336505e4b1c 927 uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */
Kojto 111:4336505e4b1c 928 uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */
Kojto 111:4336505e4b1c 929 uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */
Kojto 111:4336505e4b1c 930 uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt */
Kojto 111:4336505e4b1c 931 uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt */
Kojto 111:4336505e4b1c 932 uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt */
Kojto 111:4336505e4b1c 933 uint8_t :1; /*!< bit: 6 Reserved */
Kojto 111:4336505e4b1c 934 uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
Kojto 111:4336505e4b1c 935 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 936 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 937 } SERCOM_USART_INTFLAG_Type;
Kojto 111:4336505e4b1c 938 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 939
Kojto 111:4336505e4b1c 940 #define SERCOM_USART_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_USART_INTFLAG offset) USART Interrupt Flag Status and Clear */
Kojto 111:4336505e4b1c 941 #define SERCOM_USART_INTFLAG_RESETVALUE 0x00ul /**< \brief (SERCOM_USART_INTFLAG reset_value) USART Interrupt Flag Status and Clear */
Kojto 111:4336505e4b1c 942
Kojto 111:4336505e4b1c 943 #define SERCOM_USART_INTFLAG_DRE_Pos 0 /**< \brief (SERCOM_USART_INTFLAG) Data Register Empty Interrupt */
Kojto 111:4336505e4b1c 944 #define SERCOM_USART_INTFLAG_DRE (0x1ul << SERCOM_USART_INTFLAG_DRE_Pos)
Kojto 111:4336505e4b1c 945 #define SERCOM_USART_INTFLAG_TXC_Pos 1 /**< \brief (SERCOM_USART_INTFLAG) Transmit Complete Interrupt */
Kojto 111:4336505e4b1c 946 #define SERCOM_USART_INTFLAG_TXC (0x1ul << SERCOM_USART_INTFLAG_TXC_Pos)
Kojto 111:4336505e4b1c 947 #define SERCOM_USART_INTFLAG_RXC_Pos 2 /**< \brief (SERCOM_USART_INTFLAG) Receive Complete Interrupt */
Kojto 111:4336505e4b1c 948 #define SERCOM_USART_INTFLAG_RXC (0x1ul << SERCOM_USART_INTFLAG_RXC_Pos)
Kojto 111:4336505e4b1c 949 #define SERCOM_USART_INTFLAG_RXS_Pos 3 /**< \brief (SERCOM_USART_INTFLAG) Receive Start Interrupt */
Kojto 111:4336505e4b1c 950 #define SERCOM_USART_INTFLAG_RXS (0x1ul << SERCOM_USART_INTFLAG_RXS_Pos)
Kojto 111:4336505e4b1c 951 #define SERCOM_USART_INTFLAG_CTSIC_Pos 4 /**< \brief (SERCOM_USART_INTFLAG) Clear To Send Input Change Interrupt */
Kojto 111:4336505e4b1c 952 #define SERCOM_USART_INTFLAG_CTSIC (0x1ul << SERCOM_USART_INTFLAG_CTSIC_Pos)
Kojto 111:4336505e4b1c 953 #define SERCOM_USART_INTFLAG_RXBRK_Pos 5 /**< \brief (SERCOM_USART_INTFLAG) Break Received Interrupt */
Kojto 111:4336505e4b1c 954 #define SERCOM_USART_INTFLAG_RXBRK (0x1ul << SERCOM_USART_INTFLAG_RXBRK_Pos)
Kojto 111:4336505e4b1c 955 #define SERCOM_USART_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_USART_INTFLAG) Combined Error Interrupt */
Kojto 111:4336505e4b1c 956 #define SERCOM_USART_INTFLAG_ERROR (0x1ul << SERCOM_USART_INTFLAG_ERROR_Pos)
Kojto 111:4336505e4b1c 957 #define SERCOM_USART_INTFLAG_MASK 0xBFul /**< \brief (SERCOM_USART_INTFLAG) MASK Register */
Kojto 111:4336505e4b1c 958
Kojto 111:4336505e4b1c 959 /* -------- SERCOM_I2CM_STATUS : (SERCOM Offset: 0x1A) (R/W 16) I2CM I2CM Status -------- */
Kojto 111:4336505e4b1c 960 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 961 typedef union {
Kojto 111:4336505e4b1c 962 struct {
Kojto 111:4336505e4b1c 963 uint16_t BUSERR:1; /*!< bit: 0 Bus Error */
Kojto 111:4336505e4b1c 964 uint16_t ARBLOST:1; /*!< bit: 1 Arbitration Lost */
Kojto 111:4336505e4b1c 965 uint16_t RXNACK:1; /*!< bit: 2 Received Not Acknowledge */
Kojto 111:4336505e4b1c 966 uint16_t :1; /*!< bit: 3 Reserved */
Kojto 111:4336505e4b1c 967 uint16_t BUSSTATE:2; /*!< bit: 4.. 5 Bus State */
Kojto 111:4336505e4b1c 968 uint16_t LOWTOUT:1; /*!< bit: 6 SCL Low Timeout */
Kojto 111:4336505e4b1c 969 uint16_t CLKHOLD:1; /*!< bit: 7 Clock Hold */
Kojto 111:4336505e4b1c 970 uint16_t MEXTTOUT:1; /*!< bit: 8 Master SCL Low Extend Timeout */
Kojto 111:4336505e4b1c 971 uint16_t SEXTTOUT:1; /*!< bit: 9 Slave SCL Low Extend Timeout */
Kojto 111:4336505e4b1c 972 uint16_t LENERR:1; /*!< bit: 10 Length Error */
Kojto 111:4336505e4b1c 973 uint16_t :5; /*!< bit: 11..15 Reserved */
Kojto 111:4336505e4b1c 974 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 975 uint16_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 976 } SERCOM_I2CM_STATUS_Type;
Kojto 111:4336505e4b1c 977 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 978
Kojto 111:4336505e4b1c 979 #define SERCOM_I2CM_STATUS_OFFSET 0x1A /**< \brief (SERCOM_I2CM_STATUS offset) I2CM Status */
Kojto 111:4336505e4b1c 980 #define SERCOM_I2CM_STATUS_RESETVALUE 0x0000ul /**< \brief (SERCOM_I2CM_STATUS reset_value) I2CM Status */
Kojto 111:4336505e4b1c 981
Kojto 111:4336505e4b1c 982 #define SERCOM_I2CM_STATUS_BUSERR_Pos 0 /**< \brief (SERCOM_I2CM_STATUS) Bus Error */
Kojto 111:4336505e4b1c 983 #define SERCOM_I2CM_STATUS_BUSERR (0x1ul << SERCOM_I2CM_STATUS_BUSERR_Pos)
Kojto 111:4336505e4b1c 984 #define SERCOM_I2CM_STATUS_ARBLOST_Pos 1 /**< \brief (SERCOM_I2CM_STATUS) Arbitration Lost */
Kojto 111:4336505e4b1c 985 #define SERCOM_I2CM_STATUS_ARBLOST (0x1ul << SERCOM_I2CM_STATUS_ARBLOST_Pos)
Kojto 111:4336505e4b1c 986 #define SERCOM_I2CM_STATUS_RXNACK_Pos 2 /**< \brief (SERCOM_I2CM_STATUS) Received Not Acknowledge */
Kojto 111:4336505e4b1c 987 #define SERCOM_I2CM_STATUS_RXNACK (0x1ul << SERCOM_I2CM_STATUS_RXNACK_Pos)
Kojto 111:4336505e4b1c 988 #define SERCOM_I2CM_STATUS_BUSSTATE_Pos 4 /**< \brief (SERCOM_I2CM_STATUS) Bus State */
Kojto 111:4336505e4b1c 989 #define SERCOM_I2CM_STATUS_BUSSTATE_Msk (0x3ul << SERCOM_I2CM_STATUS_BUSSTATE_Pos)
Kojto 111:4336505e4b1c 990 #define SERCOM_I2CM_STATUS_BUSSTATE(value) ((SERCOM_I2CM_STATUS_BUSSTATE_Msk & ((value) << SERCOM_I2CM_STATUS_BUSSTATE_Pos)))
Kojto 111:4336505e4b1c 991 #define SERCOM_I2CM_STATUS_LOWTOUT_Pos 6 /**< \brief (SERCOM_I2CM_STATUS) SCL Low Timeout */
Kojto 111:4336505e4b1c 992 #define SERCOM_I2CM_STATUS_LOWTOUT (0x1ul << SERCOM_I2CM_STATUS_LOWTOUT_Pos)
Kojto 111:4336505e4b1c 993 #define SERCOM_I2CM_STATUS_CLKHOLD_Pos 7 /**< \brief (SERCOM_I2CM_STATUS) Clock Hold */
Kojto 111:4336505e4b1c 994 #define SERCOM_I2CM_STATUS_CLKHOLD (0x1ul << SERCOM_I2CM_STATUS_CLKHOLD_Pos)
Kojto 111:4336505e4b1c 995 #define SERCOM_I2CM_STATUS_MEXTTOUT_Pos 8 /**< \brief (SERCOM_I2CM_STATUS) Master SCL Low Extend Timeout */
Kojto 111:4336505e4b1c 996 #define SERCOM_I2CM_STATUS_MEXTTOUT (0x1ul << SERCOM_I2CM_STATUS_MEXTTOUT_Pos)
Kojto 111:4336505e4b1c 997 #define SERCOM_I2CM_STATUS_SEXTTOUT_Pos 9 /**< \brief (SERCOM_I2CM_STATUS) Slave SCL Low Extend Timeout */
Kojto 111:4336505e4b1c 998 #define SERCOM_I2CM_STATUS_SEXTTOUT (0x1ul << SERCOM_I2CM_STATUS_SEXTTOUT_Pos)
Kojto 111:4336505e4b1c 999 #define SERCOM_I2CM_STATUS_LENERR_Pos 10 /**< \brief (SERCOM_I2CM_STATUS) Length Error */
Kojto 111:4336505e4b1c 1000 #define SERCOM_I2CM_STATUS_LENERR (0x1ul << SERCOM_I2CM_STATUS_LENERR_Pos)
Kojto 111:4336505e4b1c 1001 #define SERCOM_I2CM_STATUS_MASK 0x07F7ul /**< \brief (SERCOM_I2CM_STATUS) MASK Register */
Kojto 111:4336505e4b1c 1002
Kojto 111:4336505e4b1c 1003 /* -------- SERCOM_I2CS_STATUS : (SERCOM Offset: 0x1A) (R/W 16) I2CS I2CS Status -------- */
Kojto 111:4336505e4b1c 1004 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 1005 typedef union {
Kojto 111:4336505e4b1c 1006 struct {
Kojto 111:4336505e4b1c 1007 uint16_t BUSERR:1; /*!< bit: 0 Bus Error */
Kojto 111:4336505e4b1c 1008 uint16_t COLL:1; /*!< bit: 1 Transmit Collision */
Kojto 111:4336505e4b1c 1009 uint16_t RXNACK:1; /*!< bit: 2 Received Not Acknowledge */
Kojto 111:4336505e4b1c 1010 uint16_t DIR:1; /*!< bit: 3 Read/Write Direction */
Kojto 111:4336505e4b1c 1011 uint16_t SR:1; /*!< bit: 4 Repeated Start */
Kojto 111:4336505e4b1c 1012 uint16_t :1; /*!< bit: 5 Reserved */
Kojto 111:4336505e4b1c 1013 uint16_t LOWTOUT:1; /*!< bit: 6 SCL Low Timeout */
Kojto 111:4336505e4b1c 1014 uint16_t CLKHOLD:1; /*!< bit: 7 Clock Hold */
Kojto 111:4336505e4b1c 1015 uint16_t :1; /*!< bit: 8 Reserved */
Kojto 111:4336505e4b1c 1016 uint16_t SEXTTOUT:1; /*!< bit: 9 Slave SCL Low Extend Timeout */
Kojto 111:4336505e4b1c 1017 uint16_t HS:1; /*!< bit: 10 High Speed */
Kojto 111:4336505e4b1c 1018 uint16_t :5; /*!< bit: 11..15 Reserved */
Kojto 111:4336505e4b1c 1019 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 1020 uint16_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 1021 } SERCOM_I2CS_STATUS_Type;
Kojto 111:4336505e4b1c 1022 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 1023
Kojto 111:4336505e4b1c 1024 #define SERCOM_I2CS_STATUS_OFFSET 0x1A /**< \brief (SERCOM_I2CS_STATUS offset) I2CS Status */
Kojto 111:4336505e4b1c 1025 #define SERCOM_I2CS_STATUS_RESETVALUE 0x0000ul /**< \brief (SERCOM_I2CS_STATUS reset_value) I2CS Status */
Kojto 111:4336505e4b1c 1026
Kojto 111:4336505e4b1c 1027 #define SERCOM_I2CS_STATUS_BUSERR_Pos 0 /**< \brief (SERCOM_I2CS_STATUS) Bus Error */
Kojto 111:4336505e4b1c 1028 #define SERCOM_I2CS_STATUS_BUSERR (0x1ul << SERCOM_I2CS_STATUS_BUSERR_Pos)
Kojto 111:4336505e4b1c 1029 #define SERCOM_I2CS_STATUS_COLL_Pos 1 /**< \brief (SERCOM_I2CS_STATUS) Transmit Collision */
Kojto 111:4336505e4b1c 1030 #define SERCOM_I2CS_STATUS_COLL (0x1ul << SERCOM_I2CS_STATUS_COLL_Pos)
Kojto 111:4336505e4b1c 1031 #define SERCOM_I2CS_STATUS_RXNACK_Pos 2 /**< \brief (SERCOM_I2CS_STATUS) Received Not Acknowledge */
Kojto 111:4336505e4b1c 1032 #define SERCOM_I2CS_STATUS_RXNACK (0x1ul << SERCOM_I2CS_STATUS_RXNACK_Pos)
Kojto 111:4336505e4b1c 1033 #define SERCOM_I2CS_STATUS_DIR_Pos 3 /**< \brief (SERCOM_I2CS_STATUS) Read/Write Direction */
Kojto 111:4336505e4b1c 1034 #define SERCOM_I2CS_STATUS_DIR (0x1ul << SERCOM_I2CS_STATUS_DIR_Pos)
Kojto 111:4336505e4b1c 1035 #define SERCOM_I2CS_STATUS_SR_Pos 4 /**< \brief (SERCOM_I2CS_STATUS) Repeated Start */
Kojto 111:4336505e4b1c 1036 #define SERCOM_I2CS_STATUS_SR (0x1ul << SERCOM_I2CS_STATUS_SR_Pos)
Kojto 111:4336505e4b1c 1037 #define SERCOM_I2CS_STATUS_LOWTOUT_Pos 6 /**< \brief (SERCOM_I2CS_STATUS) SCL Low Timeout */
Kojto 111:4336505e4b1c 1038 #define SERCOM_I2CS_STATUS_LOWTOUT (0x1ul << SERCOM_I2CS_STATUS_LOWTOUT_Pos)
Kojto 111:4336505e4b1c 1039 #define SERCOM_I2CS_STATUS_CLKHOLD_Pos 7 /**< \brief (SERCOM_I2CS_STATUS) Clock Hold */
Kojto 111:4336505e4b1c 1040 #define SERCOM_I2CS_STATUS_CLKHOLD (0x1ul << SERCOM_I2CS_STATUS_CLKHOLD_Pos)
Kojto 111:4336505e4b1c 1041 #define SERCOM_I2CS_STATUS_SEXTTOUT_Pos 9 /**< \brief (SERCOM_I2CS_STATUS) Slave SCL Low Extend Timeout */
Kojto 111:4336505e4b1c 1042 #define SERCOM_I2CS_STATUS_SEXTTOUT (0x1ul << SERCOM_I2CS_STATUS_SEXTTOUT_Pos)
Kojto 111:4336505e4b1c 1043 #define SERCOM_I2CS_STATUS_HS_Pos 10 /**< \brief (SERCOM_I2CS_STATUS) High Speed */
Kojto 111:4336505e4b1c 1044 #define SERCOM_I2CS_STATUS_HS (0x1ul << SERCOM_I2CS_STATUS_HS_Pos)
Kojto 111:4336505e4b1c 1045 #define SERCOM_I2CS_STATUS_MASK 0x06DFul /**< \brief (SERCOM_I2CS_STATUS) MASK Register */
Kojto 111:4336505e4b1c 1046
Kojto 111:4336505e4b1c 1047 /* -------- SERCOM_SPI_STATUS : (SERCOM Offset: 0x1A) (R/W 16) SPI SPI Status -------- */
Kojto 111:4336505e4b1c 1048 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 1049 typedef union {
Kojto 111:4336505e4b1c 1050 struct {
Kojto 111:4336505e4b1c 1051 uint16_t :2; /*!< bit: 0.. 1 Reserved */
Kojto 111:4336505e4b1c 1052 uint16_t BUFOVF:1; /*!< bit: 2 Buffer Overflow */
Kojto 111:4336505e4b1c 1053 uint16_t :13; /*!< bit: 3..15 Reserved */
Kojto 111:4336505e4b1c 1054 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 1055 uint16_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 1056 } SERCOM_SPI_STATUS_Type;
Kojto 111:4336505e4b1c 1057 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 1058
Kojto 111:4336505e4b1c 1059 #define SERCOM_SPI_STATUS_OFFSET 0x1A /**< \brief (SERCOM_SPI_STATUS offset) SPI Status */
Kojto 111:4336505e4b1c 1060 #define SERCOM_SPI_STATUS_RESETVALUE 0x0000ul /**< \brief (SERCOM_SPI_STATUS reset_value) SPI Status */
Kojto 111:4336505e4b1c 1061
Kojto 111:4336505e4b1c 1062 #define SERCOM_SPI_STATUS_BUFOVF_Pos 2 /**< \brief (SERCOM_SPI_STATUS) Buffer Overflow */
Kojto 111:4336505e4b1c 1063 #define SERCOM_SPI_STATUS_BUFOVF (0x1ul << SERCOM_SPI_STATUS_BUFOVF_Pos)
Kojto 111:4336505e4b1c 1064 #define SERCOM_SPI_STATUS_MASK 0x0004ul /**< \brief (SERCOM_SPI_STATUS) MASK Register */
Kojto 111:4336505e4b1c 1065
Kojto 111:4336505e4b1c 1066 /* -------- SERCOM_USART_STATUS : (SERCOM Offset: 0x1A) (R/W 16) USART USART Status -------- */
Kojto 111:4336505e4b1c 1067 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 1068 typedef union {
Kojto 111:4336505e4b1c 1069 struct {
Kojto 111:4336505e4b1c 1070 uint16_t PERR:1; /*!< bit: 0 Parity Error */
Kojto 111:4336505e4b1c 1071 uint16_t FERR:1; /*!< bit: 1 Frame Error */
Kojto 111:4336505e4b1c 1072 uint16_t BUFOVF:1; /*!< bit: 2 Buffer Overflow */
Kojto 111:4336505e4b1c 1073 uint16_t CTS:1; /*!< bit: 3 Clear To Send */
Kojto 111:4336505e4b1c 1074 uint16_t ISF:1; /*!< bit: 4 Inconsistent Sync Field */
Kojto 111:4336505e4b1c 1075 uint16_t COLL:1; /*!< bit: 5 Collision Detected */
Kojto 111:4336505e4b1c 1076 uint16_t :10; /*!< bit: 6..15 Reserved */
Kojto 111:4336505e4b1c 1077 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 1078 uint16_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 1079 } SERCOM_USART_STATUS_Type;
Kojto 111:4336505e4b1c 1080 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 1081
Kojto 111:4336505e4b1c 1082 #define SERCOM_USART_STATUS_OFFSET 0x1A /**< \brief (SERCOM_USART_STATUS offset) USART Status */
Kojto 111:4336505e4b1c 1083 #define SERCOM_USART_STATUS_RESETVALUE 0x0000ul /**< \brief (SERCOM_USART_STATUS reset_value) USART Status */
Kojto 111:4336505e4b1c 1084
Kojto 111:4336505e4b1c 1085 #define SERCOM_USART_STATUS_PERR_Pos 0 /**< \brief (SERCOM_USART_STATUS) Parity Error */
Kojto 111:4336505e4b1c 1086 #define SERCOM_USART_STATUS_PERR (0x1ul << SERCOM_USART_STATUS_PERR_Pos)
Kojto 111:4336505e4b1c 1087 #define SERCOM_USART_STATUS_FERR_Pos 1 /**< \brief (SERCOM_USART_STATUS) Frame Error */
Kojto 111:4336505e4b1c 1088 #define SERCOM_USART_STATUS_FERR (0x1ul << SERCOM_USART_STATUS_FERR_Pos)
Kojto 111:4336505e4b1c 1089 #define SERCOM_USART_STATUS_BUFOVF_Pos 2 /**< \brief (SERCOM_USART_STATUS) Buffer Overflow */
Kojto 111:4336505e4b1c 1090 #define SERCOM_USART_STATUS_BUFOVF (0x1ul << SERCOM_USART_STATUS_BUFOVF_Pos)
Kojto 111:4336505e4b1c 1091 #define SERCOM_USART_STATUS_CTS_Pos 3 /**< \brief (SERCOM_USART_STATUS) Clear To Send */
Kojto 111:4336505e4b1c 1092 #define SERCOM_USART_STATUS_CTS (0x1ul << SERCOM_USART_STATUS_CTS_Pos)
Kojto 111:4336505e4b1c 1093 #define SERCOM_USART_STATUS_ISF_Pos 4 /**< \brief (SERCOM_USART_STATUS) Inconsistent Sync Field */
Kojto 111:4336505e4b1c 1094 #define SERCOM_USART_STATUS_ISF (0x1ul << SERCOM_USART_STATUS_ISF_Pos)
Kojto 111:4336505e4b1c 1095 #define SERCOM_USART_STATUS_COLL_Pos 5 /**< \brief (SERCOM_USART_STATUS) Collision Detected */
Kojto 111:4336505e4b1c 1096 #define SERCOM_USART_STATUS_COLL (0x1ul << SERCOM_USART_STATUS_COLL_Pos)
Kojto 111:4336505e4b1c 1097 #define SERCOM_USART_STATUS_MASK 0x003Ful /**< \brief (SERCOM_USART_STATUS) MASK Register */
Kojto 111:4336505e4b1c 1098
Kojto 111:4336505e4b1c 1099 /* -------- SERCOM_I2CM_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) I2CM I2CM Syncbusy -------- */
Kojto 111:4336505e4b1c 1100 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 1101 typedef union {
Kojto 111:4336505e4b1c 1102 struct {
Kojto 111:4336505e4b1c 1103 uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
Kojto 111:4336505e4b1c 1104 uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */
Kojto 111:4336505e4b1c 1105 uint32_t SYSOP:1; /*!< bit: 2 System Operation Synchronization Busy */
Kojto 111:4336505e4b1c 1106 uint32_t :29; /*!< bit: 3..31 Reserved */
Kojto 111:4336505e4b1c 1107 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 1108 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 1109 } SERCOM_I2CM_SYNCBUSY_Type;
Kojto 111:4336505e4b1c 1110 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 1111
Kojto 111:4336505e4b1c 1112 #define SERCOM_I2CM_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_I2CM_SYNCBUSY offset) I2CM Syncbusy */
Kojto 111:4336505e4b1c 1113 #define SERCOM_I2CM_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CM_SYNCBUSY reset_value) I2CM Syncbusy */
Kojto 111:4336505e4b1c 1114
Kojto 111:4336505e4b1c 1115 #define SERCOM_I2CM_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_I2CM_SYNCBUSY) Software Reset Synchronization Busy */
Kojto 111:4336505e4b1c 1116 #define SERCOM_I2CM_SYNCBUSY_SWRST (0x1ul << SERCOM_I2CM_SYNCBUSY_SWRST_Pos)
Kojto 111:4336505e4b1c 1117 #define SERCOM_I2CM_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_I2CM_SYNCBUSY) SERCOM Enable Synchronization Busy */
Kojto 111:4336505e4b1c 1118 #define SERCOM_I2CM_SYNCBUSY_ENABLE (0x1ul << SERCOM_I2CM_SYNCBUSY_ENABLE_Pos)
Kojto 111:4336505e4b1c 1119 #define SERCOM_I2CM_SYNCBUSY_SYSOP_Pos 2 /**< \brief (SERCOM_I2CM_SYNCBUSY) System Operation Synchronization Busy */
Kojto 111:4336505e4b1c 1120 #define SERCOM_I2CM_SYNCBUSY_SYSOP (0x1ul << SERCOM_I2CM_SYNCBUSY_SYSOP_Pos)
Kojto 111:4336505e4b1c 1121 #define SERCOM_I2CM_SYNCBUSY_MASK 0x00000007ul /**< \brief (SERCOM_I2CM_SYNCBUSY) MASK Register */
Kojto 111:4336505e4b1c 1122
Kojto 111:4336505e4b1c 1123 /* -------- SERCOM_I2CS_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) I2CS I2CS Syncbusy -------- */
Kojto 111:4336505e4b1c 1124 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 1125 typedef union {
Kojto 111:4336505e4b1c 1126 struct {
Kojto 111:4336505e4b1c 1127 uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
Kojto 111:4336505e4b1c 1128 uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */
Kojto 111:4336505e4b1c 1129 uint32_t :30; /*!< bit: 2..31 Reserved */
Kojto 111:4336505e4b1c 1130 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 1131 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 1132 } SERCOM_I2CS_SYNCBUSY_Type;
Kojto 111:4336505e4b1c 1133 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 1134
Kojto 111:4336505e4b1c 1135 #define SERCOM_I2CS_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_I2CS_SYNCBUSY offset) I2CS Syncbusy */
Kojto 111:4336505e4b1c 1136 #define SERCOM_I2CS_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CS_SYNCBUSY reset_value) I2CS Syncbusy */
Kojto 111:4336505e4b1c 1137
Kojto 111:4336505e4b1c 1138 #define SERCOM_I2CS_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_I2CS_SYNCBUSY) Software Reset Synchronization Busy */
Kojto 111:4336505e4b1c 1139 #define SERCOM_I2CS_SYNCBUSY_SWRST (0x1ul << SERCOM_I2CS_SYNCBUSY_SWRST_Pos)
Kojto 111:4336505e4b1c 1140 #define SERCOM_I2CS_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_I2CS_SYNCBUSY) SERCOM Enable Synchronization Busy */
Kojto 111:4336505e4b1c 1141 #define SERCOM_I2CS_SYNCBUSY_ENABLE (0x1ul << SERCOM_I2CS_SYNCBUSY_ENABLE_Pos)
Kojto 111:4336505e4b1c 1142 #define SERCOM_I2CS_SYNCBUSY_MASK 0x00000003ul /**< \brief (SERCOM_I2CS_SYNCBUSY) MASK Register */
Kojto 111:4336505e4b1c 1143
Kojto 111:4336505e4b1c 1144 /* -------- SERCOM_SPI_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) SPI SPI Syncbusy -------- */
Kojto 111:4336505e4b1c 1145 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 1146 typedef union {
Kojto 111:4336505e4b1c 1147 struct {
Kojto 111:4336505e4b1c 1148 uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
Kojto 111:4336505e4b1c 1149 uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */
Kojto 111:4336505e4b1c 1150 uint32_t CTRLB:1; /*!< bit: 2 CTRLB Synchronization Busy */
Kojto 111:4336505e4b1c 1151 uint32_t :29; /*!< bit: 3..31 Reserved */
Kojto 111:4336505e4b1c 1152 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 1153 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 1154 } SERCOM_SPI_SYNCBUSY_Type;
Kojto 111:4336505e4b1c 1155 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 1156
Kojto 111:4336505e4b1c 1157 #define SERCOM_SPI_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_SPI_SYNCBUSY offset) SPI Syncbusy */
Kojto 111:4336505e4b1c 1158 #define SERCOM_SPI_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (SERCOM_SPI_SYNCBUSY reset_value) SPI Syncbusy */
Kojto 111:4336505e4b1c 1159
Kojto 111:4336505e4b1c 1160 #define SERCOM_SPI_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_SPI_SYNCBUSY) Software Reset Synchronization Busy */
Kojto 111:4336505e4b1c 1161 #define SERCOM_SPI_SYNCBUSY_SWRST (0x1ul << SERCOM_SPI_SYNCBUSY_SWRST_Pos)
Kojto 111:4336505e4b1c 1162 #define SERCOM_SPI_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_SPI_SYNCBUSY) SERCOM Enable Synchronization Busy */
Kojto 111:4336505e4b1c 1163 #define SERCOM_SPI_SYNCBUSY_ENABLE (0x1ul << SERCOM_SPI_SYNCBUSY_ENABLE_Pos)
Kojto 111:4336505e4b1c 1164 #define SERCOM_SPI_SYNCBUSY_CTRLB_Pos 2 /**< \brief (SERCOM_SPI_SYNCBUSY) CTRLB Synchronization Busy */
Kojto 111:4336505e4b1c 1165 #define SERCOM_SPI_SYNCBUSY_CTRLB (0x1ul << SERCOM_SPI_SYNCBUSY_CTRLB_Pos)
Kojto 111:4336505e4b1c 1166 #define SERCOM_SPI_SYNCBUSY_MASK 0x00000007ul /**< \brief (SERCOM_SPI_SYNCBUSY) MASK Register */
Kojto 111:4336505e4b1c 1167
Kojto 111:4336505e4b1c 1168 /* -------- SERCOM_USART_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) USART USART Syncbusy -------- */
Kojto 111:4336505e4b1c 1169 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 1170 typedef union {
Kojto 111:4336505e4b1c 1171 struct {
Kojto 111:4336505e4b1c 1172 uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
Kojto 111:4336505e4b1c 1173 uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */
Kojto 111:4336505e4b1c 1174 uint32_t CTRLB:1; /*!< bit: 2 CTRLB Synchronization Busy */
Kojto 111:4336505e4b1c 1175 uint32_t :29; /*!< bit: 3..31 Reserved */
Kojto 111:4336505e4b1c 1176 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 1177 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 1178 } SERCOM_USART_SYNCBUSY_Type;
Kojto 111:4336505e4b1c 1179 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 1180
Kojto 111:4336505e4b1c 1181 #define SERCOM_USART_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_USART_SYNCBUSY offset) USART Syncbusy */
Kojto 111:4336505e4b1c 1182 #define SERCOM_USART_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (SERCOM_USART_SYNCBUSY reset_value) USART Syncbusy */
Kojto 111:4336505e4b1c 1183
Kojto 111:4336505e4b1c 1184 #define SERCOM_USART_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_USART_SYNCBUSY) Software Reset Synchronization Busy */
Kojto 111:4336505e4b1c 1185 #define SERCOM_USART_SYNCBUSY_SWRST (0x1ul << SERCOM_USART_SYNCBUSY_SWRST_Pos)
Kojto 111:4336505e4b1c 1186 #define SERCOM_USART_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_USART_SYNCBUSY) SERCOM Enable Synchronization Busy */
Kojto 111:4336505e4b1c 1187 #define SERCOM_USART_SYNCBUSY_ENABLE (0x1ul << SERCOM_USART_SYNCBUSY_ENABLE_Pos)
Kojto 111:4336505e4b1c 1188 #define SERCOM_USART_SYNCBUSY_CTRLB_Pos 2 /**< \brief (SERCOM_USART_SYNCBUSY) CTRLB Synchronization Busy */
Kojto 111:4336505e4b1c 1189 #define SERCOM_USART_SYNCBUSY_CTRLB (0x1ul << SERCOM_USART_SYNCBUSY_CTRLB_Pos)
Kojto 111:4336505e4b1c 1190 #define SERCOM_USART_SYNCBUSY_MASK 0x00000007ul /**< \brief (SERCOM_USART_SYNCBUSY) MASK Register */
Kojto 111:4336505e4b1c 1191
Kojto 111:4336505e4b1c 1192 /* -------- SERCOM_I2CM_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CM I2CM Address -------- */
Kojto 111:4336505e4b1c 1193 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 1194 typedef union {
Kojto 111:4336505e4b1c 1195 struct {
Kojto 111:4336505e4b1c 1196 uint32_t ADDR:11; /*!< bit: 0..10 Address Value */
Kojto 111:4336505e4b1c 1197 uint32_t :2; /*!< bit: 11..12 Reserved */
Kojto 111:4336505e4b1c 1198 uint32_t LENEN:1; /*!< bit: 13 Length Enable */
Kojto 111:4336505e4b1c 1199 uint32_t HS:1; /*!< bit: 14 High Speed Mode */
Kojto 111:4336505e4b1c 1200 uint32_t TENBITEN:1; /*!< bit: 15 Ten Bit Addressing Enable */
Kojto 111:4336505e4b1c 1201 uint32_t LEN:8; /*!< bit: 16..23 Length */
Kojto 111:4336505e4b1c 1202 uint32_t :8; /*!< bit: 24..31 Reserved */
Kojto 111:4336505e4b1c 1203 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 1204 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 1205 } SERCOM_I2CM_ADDR_Type;
Kojto 111:4336505e4b1c 1206 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 1207
Kojto 111:4336505e4b1c 1208 #define SERCOM_I2CM_ADDR_OFFSET 0x24 /**< \brief (SERCOM_I2CM_ADDR offset) I2CM Address */
Kojto 111:4336505e4b1c 1209 #define SERCOM_I2CM_ADDR_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CM_ADDR reset_value) I2CM Address */
Kojto 111:4336505e4b1c 1210
Kojto 111:4336505e4b1c 1211 #define SERCOM_I2CM_ADDR_ADDR_Pos 0 /**< \brief (SERCOM_I2CM_ADDR) Address Value */
Kojto 111:4336505e4b1c 1212 #define SERCOM_I2CM_ADDR_ADDR_Msk (0x7FFul << SERCOM_I2CM_ADDR_ADDR_Pos)
Kojto 111:4336505e4b1c 1213 #define SERCOM_I2CM_ADDR_ADDR(value) ((SERCOM_I2CM_ADDR_ADDR_Msk & ((value) << SERCOM_I2CM_ADDR_ADDR_Pos)))
Kojto 111:4336505e4b1c 1214 #define SERCOM_I2CM_ADDR_LENEN_Pos 13 /**< \brief (SERCOM_I2CM_ADDR) Length Enable */
Kojto 111:4336505e4b1c 1215 #define SERCOM_I2CM_ADDR_LENEN (0x1ul << SERCOM_I2CM_ADDR_LENEN_Pos)
Kojto 111:4336505e4b1c 1216 #define SERCOM_I2CM_ADDR_HS_Pos 14 /**< \brief (SERCOM_I2CM_ADDR) High Speed Mode */
Kojto 111:4336505e4b1c 1217 #define SERCOM_I2CM_ADDR_HS (0x1ul << SERCOM_I2CM_ADDR_HS_Pos)
Kojto 111:4336505e4b1c 1218 #define SERCOM_I2CM_ADDR_TENBITEN_Pos 15 /**< \brief (SERCOM_I2CM_ADDR) Ten Bit Addressing Enable */
Kojto 111:4336505e4b1c 1219 #define SERCOM_I2CM_ADDR_TENBITEN (0x1ul << SERCOM_I2CM_ADDR_TENBITEN_Pos)
Kojto 111:4336505e4b1c 1220 #define SERCOM_I2CM_ADDR_LEN_Pos 16 /**< \brief (SERCOM_I2CM_ADDR) Length */
Kojto 111:4336505e4b1c 1221 #define SERCOM_I2CM_ADDR_LEN_Msk (0xFFul << SERCOM_I2CM_ADDR_LEN_Pos)
Kojto 111:4336505e4b1c 1222 #define SERCOM_I2CM_ADDR_LEN(value) ((SERCOM_I2CM_ADDR_LEN_Msk & ((value) << SERCOM_I2CM_ADDR_LEN_Pos)))
Kojto 111:4336505e4b1c 1223 #define SERCOM_I2CM_ADDR_MASK 0x00FFE7FFul /**< \brief (SERCOM_I2CM_ADDR) MASK Register */
Kojto 111:4336505e4b1c 1224
Kojto 111:4336505e4b1c 1225 /* -------- SERCOM_I2CS_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CS I2CS Address -------- */
Kojto 111:4336505e4b1c 1226 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 1227 typedef union {
Kojto 111:4336505e4b1c 1228 struct {
Kojto 111:4336505e4b1c 1229 uint32_t GENCEN:1; /*!< bit: 0 General Call Address Enable */
Kojto 111:4336505e4b1c 1230 uint32_t ADDR:10; /*!< bit: 1..10 Address Value */
Kojto 111:4336505e4b1c 1231 uint32_t :4; /*!< bit: 11..14 Reserved */
Kojto 111:4336505e4b1c 1232 uint32_t TENBITEN:1; /*!< bit: 15 Ten Bit Addressing Enable */
Kojto 111:4336505e4b1c 1233 uint32_t :1; /*!< bit: 16 Reserved */
Kojto 111:4336505e4b1c 1234 uint32_t ADDRMASK:10; /*!< bit: 17..26 Address Mask */
Kojto 111:4336505e4b1c 1235 uint32_t :5; /*!< bit: 27..31 Reserved */
Kojto 111:4336505e4b1c 1236 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 1237 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 1238 } SERCOM_I2CS_ADDR_Type;
Kojto 111:4336505e4b1c 1239 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 1240
Kojto 111:4336505e4b1c 1241 #define SERCOM_I2CS_ADDR_OFFSET 0x24 /**< \brief (SERCOM_I2CS_ADDR offset) I2CS Address */
Kojto 111:4336505e4b1c 1242 #define SERCOM_I2CS_ADDR_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CS_ADDR reset_value) I2CS Address */
Kojto 111:4336505e4b1c 1243
Kojto 111:4336505e4b1c 1244 #define SERCOM_I2CS_ADDR_GENCEN_Pos 0 /**< \brief (SERCOM_I2CS_ADDR) General Call Address Enable */
Kojto 111:4336505e4b1c 1245 #define SERCOM_I2CS_ADDR_GENCEN (0x1ul << SERCOM_I2CS_ADDR_GENCEN_Pos)
Kojto 111:4336505e4b1c 1246 #define SERCOM_I2CS_ADDR_ADDR_Pos 1 /**< \brief (SERCOM_I2CS_ADDR) Address Value */
Kojto 111:4336505e4b1c 1247 #define SERCOM_I2CS_ADDR_ADDR_Msk (0x3FFul << SERCOM_I2CS_ADDR_ADDR_Pos)
Kojto 111:4336505e4b1c 1248 #define SERCOM_I2CS_ADDR_ADDR(value) ((SERCOM_I2CS_ADDR_ADDR_Msk & ((value) << SERCOM_I2CS_ADDR_ADDR_Pos)))
Kojto 111:4336505e4b1c 1249 #define SERCOM_I2CS_ADDR_TENBITEN_Pos 15 /**< \brief (SERCOM_I2CS_ADDR) Ten Bit Addressing Enable */
Kojto 111:4336505e4b1c 1250 #define SERCOM_I2CS_ADDR_TENBITEN (0x1ul << SERCOM_I2CS_ADDR_TENBITEN_Pos)
Kojto 111:4336505e4b1c 1251 #define SERCOM_I2CS_ADDR_ADDRMASK_Pos 17 /**< \brief (SERCOM_I2CS_ADDR) Address Mask */
Kojto 111:4336505e4b1c 1252 #define SERCOM_I2CS_ADDR_ADDRMASK_Msk (0x3FFul << SERCOM_I2CS_ADDR_ADDRMASK_Pos)
Kojto 111:4336505e4b1c 1253 #define SERCOM_I2CS_ADDR_ADDRMASK(value) ((SERCOM_I2CS_ADDR_ADDRMASK_Msk & ((value) << SERCOM_I2CS_ADDR_ADDRMASK_Pos)))
Kojto 111:4336505e4b1c 1254 #define SERCOM_I2CS_ADDR_MASK 0x07FE87FFul /**< \brief (SERCOM_I2CS_ADDR) MASK Register */
Kojto 111:4336505e4b1c 1255
Kojto 111:4336505e4b1c 1256 /* -------- SERCOM_SPI_ADDR : (SERCOM Offset: 0x24) (R/W 32) SPI SPI Address -------- */
Kojto 111:4336505e4b1c 1257 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 1258 typedef union {
Kojto 111:4336505e4b1c 1259 struct {
Kojto 111:4336505e4b1c 1260 uint32_t ADDR:8; /*!< bit: 0.. 7 Address Value */
Kojto 111:4336505e4b1c 1261 uint32_t :8; /*!< bit: 8..15 Reserved */
Kojto 111:4336505e4b1c 1262 uint32_t ADDRMASK:8; /*!< bit: 16..23 Address Mask */
Kojto 111:4336505e4b1c 1263 uint32_t :8; /*!< bit: 24..31 Reserved */
Kojto 111:4336505e4b1c 1264 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 1265 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 1266 } SERCOM_SPI_ADDR_Type;
Kojto 111:4336505e4b1c 1267 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 1268
Kojto 111:4336505e4b1c 1269 #define SERCOM_SPI_ADDR_OFFSET 0x24 /**< \brief (SERCOM_SPI_ADDR offset) SPI Address */
Kojto 111:4336505e4b1c 1270 #define SERCOM_SPI_ADDR_RESETVALUE 0x00000000ul /**< \brief (SERCOM_SPI_ADDR reset_value) SPI Address */
Kojto 111:4336505e4b1c 1271
Kojto 111:4336505e4b1c 1272 #define SERCOM_SPI_ADDR_ADDR_Pos 0 /**< \brief (SERCOM_SPI_ADDR) Address Value */
Kojto 111:4336505e4b1c 1273 #define SERCOM_SPI_ADDR_ADDR_Msk (0xFFul << SERCOM_SPI_ADDR_ADDR_Pos)
Kojto 111:4336505e4b1c 1274 #define SERCOM_SPI_ADDR_ADDR(value) ((SERCOM_SPI_ADDR_ADDR_Msk & ((value) << SERCOM_SPI_ADDR_ADDR_Pos)))
Kojto 111:4336505e4b1c 1275 #define SERCOM_SPI_ADDR_ADDRMASK_Pos 16 /**< \brief (SERCOM_SPI_ADDR) Address Mask */
Kojto 111:4336505e4b1c 1276 #define SERCOM_SPI_ADDR_ADDRMASK_Msk (0xFFul << SERCOM_SPI_ADDR_ADDRMASK_Pos)
Kojto 111:4336505e4b1c 1277 #define SERCOM_SPI_ADDR_ADDRMASK(value) ((SERCOM_SPI_ADDR_ADDRMASK_Msk & ((value) << SERCOM_SPI_ADDR_ADDRMASK_Pos)))
Kojto 111:4336505e4b1c 1278 #define SERCOM_SPI_ADDR_MASK 0x00FF00FFul /**< \brief (SERCOM_SPI_ADDR) MASK Register */
Kojto 111:4336505e4b1c 1279
Kojto 111:4336505e4b1c 1280 /* -------- SERCOM_I2CM_DATA : (SERCOM Offset: 0x28) (R/W 8) I2CM I2CM Data -------- */
Kojto 111:4336505e4b1c 1281 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 1282 typedef union {
Kojto 111:4336505e4b1c 1283 struct {
Kojto 111:4336505e4b1c 1284 uint8_t DATA:8; /*!< bit: 0.. 7 Data Value */
Kojto 111:4336505e4b1c 1285 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 1286 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 1287 } SERCOM_I2CM_DATA_Type;
Kojto 111:4336505e4b1c 1288 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 1289
Kojto 111:4336505e4b1c 1290 #define SERCOM_I2CM_DATA_OFFSET 0x28 /**< \brief (SERCOM_I2CM_DATA offset) I2CM Data */
Kojto 111:4336505e4b1c 1291 #define SERCOM_I2CM_DATA_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CM_DATA reset_value) I2CM Data */
Kojto 111:4336505e4b1c 1292
Kojto 111:4336505e4b1c 1293 #define SERCOM_I2CM_DATA_DATA_Pos 0 /**< \brief (SERCOM_I2CM_DATA) Data Value */
Kojto 111:4336505e4b1c 1294 #define SERCOM_I2CM_DATA_DATA_Msk (0xFFul << SERCOM_I2CM_DATA_DATA_Pos)
Kojto 111:4336505e4b1c 1295 #define SERCOM_I2CM_DATA_DATA(value) ((SERCOM_I2CM_DATA_DATA_Msk & ((value) << SERCOM_I2CM_DATA_DATA_Pos)))
Kojto 111:4336505e4b1c 1296 #define SERCOM_I2CM_DATA_MASK 0xFFul /**< \brief (SERCOM_I2CM_DATA) MASK Register */
Kojto 111:4336505e4b1c 1297
Kojto 111:4336505e4b1c 1298 /* -------- SERCOM_I2CS_DATA : (SERCOM Offset: 0x28) (R/W 8) I2CS I2CS Data -------- */
Kojto 111:4336505e4b1c 1299 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 1300 typedef union {
Kojto 111:4336505e4b1c 1301 struct {
Kojto 111:4336505e4b1c 1302 uint8_t DATA:8; /*!< bit: 0.. 7 Data Value */
Kojto 111:4336505e4b1c 1303 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 1304 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 1305 } SERCOM_I2CS_DATA_Type;
Kojto 111:4336505e4b1c 1306 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 1307
Kojto 111:4336505e4b1c 1308 #define SERCOM_I2CS_DATA_OFFSET 0x28 /**< \brief (SERCOM_I2CS_DATA offset) I2CS Data */
Kojto 111:4336505e4b1c 1309 #define SERCOM_I2CS_DATA_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CS_DATA reset_value) I2CS Data */
Kojto 111:4336505e4b1c 1310
Kojto 111:4336505e4b1c 1311 #define SERCOM_I2CS_DATA_DATA_Pos 0 /**< \brief (SERCOM_I2CS_DATA) Data Value */
Kojto 111:4336505e4b1c 1312 #define SERCOM_I2CS_DATA_DATA_Msk (0xFFul << SERCOM_I2CS_DATA_DATA_Pos)
Kojto 111:4336505e4b1c 1313 #define SERCOM_I2CS_DATA_DATA(value) ((SERCOM_I2CS_DATA_DATA_Msk & ((value) << SERCOM_I2CS_DATA_DATA_Pos)))
Kojto 111:4336505e4b1c 1314 #define SERCOM_I2CS_DATA_MASK 0xFFul /**< \brief (SERCOM_I2CS_DATA) MASK Register */
Kojto 111:4336505e4b1c 1315
Kojto 111:4336505e4b1c 1316 /* -------- SERCOM_SPI_DATA : (SERCOM Offset: 0x28) (R/W 32) SPI SPI Data -------- */
Kojto 111:4336505e4b1c 1317 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 1318 typedef union {
Kojto 111:4336505e4b1c 1319 struct {
Kojto 111:4336505e4b1c 1320 uint32_t DATA:9; /*!< bit: 0.. 8 Data Value */
Kojto 111:4336505e4b1c 1321 uint32_t :23; /*!< bit: 9..31 Reserved */
Kojto 111:4336505e4b1c 1322 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 1323 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 1324 } SERCOM_SPI_DATA_Type;
Kojto 111:4336505e4b1c 1325 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 1326
Kojto 111:4336505e4b1c 1327 #define SERCOM_SPI_DATA_OFFSET 0x28 /**< \brief (SERCOM_SPI_DATA offset) SPI Data */
Kojto 111:4336505e4b1c 1328 #define SERCOM_SPI_DATA_RESETVALUE 0x00000000ul /**< \brief (SERCOM_SPI_DATA reset_value) SPI Data */
Kojto 111:4336505e4b1c 1329
Kojto 111:4336505e4b1c 1330 #define SERCOM_SPI_DATA_DATA_Pos 0 /**< \brief (SERCOM_SPI_DATA) Data Value */
Kojto 111:4336505e4b1c 1331 #define SERCOM_SPI_DATA_DATA_Msk (0x1FFul << SERCOM_SPI_DATA_DATA_Pos)
Kojto 111:4336505e4b1c 1332 #define SERCOM_SPI_DATA_DATA(value) ((SERCOM_SPI_DATA_DATA_Msk & ((value) << SERCOM_SPI_DATA_DATA_Pos)))
Kojto 111:4336505e4b1c 1333 #define SERCOM_SPI_DATA_MASK 0x000001FFul /**< \brief (SERCOM_SPI_DATA) MASK Register */
Kojto 111:4336505e4b1c 1334
Kojto 111:4336505e4b1c 1335 /* -------- SERCOM_USART_DATA : (SERCOM Offset: 0x28) (R/W 16) USART USART Data -------- */
Kojto 111:4336505e4b1c 1336 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 1337 typedef union {
Kojto 111:4336505e4b1c 1338 struct {
Kojto 111:4336505e4b1c 1339 uint16_t DATA:9; /*!< bit: 0.. 8 Data Value */
Kojto 111:4336505e4b1c 1340 uint16_t :7; /*!< bit: 9..15 Reserved */
Kojto 111:4336505e4b1c 1341 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 1342 uint16_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 1343 } SERCOM_USART_DATA_Type;
Kojto 111:4336505e4b1c 1344 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 1345
Kojto 111:4336505e4b1c 1346 #define SERCOM_USART_DATA_OFFSET 0x28 /**< \brief (SERCOM_USART_DATA offset) USART Data */
Kojto 111:4336505e4b1c 1347 #define SERCOM_USART_DATA_RESETVALUE 0x0000ul /**< \brief (SERCOM_USART_DATA reset_value) USART Data */
Kojto 111:4336505e4b1c 1348
Kojto 111:4336505e4b1c 1349 #define SERCOM_USART_DATA_DATA_Pos 0 /**< \brief (SERCOM_USART_DATA) Data Value */
Kojto 111:4336505e4b1c 1350 #define SERCOM_USART_DATA_DATA_Msk (0x1FFul << SERCOM_USART_DATA_DATA_Pos)
Kojto 111:4336505e4b1c 1351 #define SERCOM_USART_DATA_DATA(value) ((SERCOM_USART_DATA_DATA_Msk & ((value) << SERCOM_USART_DATA_DATA_Pos)))
Kojto 111:4336505e4b1c 1352 #define SERCOM_USART_DATA_MASK 0x01FFul /**< \brief (SERCOM_USART_DATA) MASK Register */
Kojto 111:4336505e4b1c 1353
Kojto 111:4336505e4b1c 1354 /* -------- SERCOM_I2CM_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) I2CM I2CM Debug Control -------- */
Kojto 111:4336505e4b1c 1355 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 1356 typedef union {
Kojto 111:4336505e4b1c 1357 struct {
Kojto 111:4336505e4b1c 1358 uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */
Kojto 111:4336505e4b1c 1359 uint8_t :7; /*!< bit: 1.. 7 Reserved */
Kojto 111:4336505e4b1c 1360 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 1361 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 1362 } SERCOM_I2CM_DBGCTRL_Type;
Kojto 111:4336505e4b1c 1363 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 1364
Kojto 111:4336505e4b1c 1365 #define SERCOM_I2CM_DBGCTRL_OFFSET 0x30 /**< \brief (SERCOM_I2CM_DBGCTRL offset) I2CM Debug Control */
Kojto 111:4336505e4b1c 1366 #define SERCOM_I2CM_DBGCTRL_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CM_DBGCTRL reset_value) I2CM Debug Control */
Kojto 111:4336505e4b1c 1367
Kojto 111:4336505e4b1c 1368 #define SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos 0 /**< \brief (SERCOM_I2CM_DBGCTRL) Debug Mode */
Kojto 111:4336505e4b1c 1369 #define SERCOM_I2CM_DBGCTRL_DBGSTOP (0x1ul << SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos)
Kojto 111:4336505e4b1c 1370 #define SERCOM_I2CM_DBGCTRL_MASK 0x01ul /**< \brief (SERCOM_I2CM_DBGCTRL) MASK Register */
Kojto 111:4336505e4b1c 1371
Kojto 111:4336505e4b1c 1372 /* -------- SERCOM_SPI_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) SPI SPI Debug Control -------- */
Kojto 111:4336505e4b1c 1373 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 1374 typedef union {
Kojto 111:4336505e4b1c 1375 struct {
Kojto 111:4336505e4b1c 1376 uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */
Kojto 111:4336505e4b1c 1377 uint8_t :7; /*!< bit: 1.. 7 Reserved */
Kojto 111:4336505e4b1c 1378 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 1379 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 1380 } SERCOM_SPI_DBGCTRL_Type;
Kojto 111:4336505e4b1c 1381 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 1382
Kojto 111:4336505e4b1c 1383 #define SERCOM_SPI_DBGCTRL_OFFSET 0x30 /**< \brief (SERCOM_SPI_DBGCTRL offset) SPI Debug Control */
Kojto 111:4336505e4b1c 1384 #define SERCOM_SPI_DBGCTRL_RESETVALUE 0x00ul /**< \brief (SERCOM_SPI_DBGCTRL reset_value) SPI Debug Control */
Kojto 111:4336505e4b1c 1385
Kojto 111:4336505e4b1c 1386 #define SERCOM_SPI_DBGCTRL_DBGSTOP_Pos 0 /**< \brief (SERCOM_SPI_DBGCTRL) Debug Mode */
Kojto 111:4336505e4b1c 1387 #define SERCOM_SPI_DBGCTRL_DBGSTOP (0x1ul << SERCOM_SPI_DBGCTRL_DBGSTOP_Pos)
Kojto 111:4336505e4b1c 1388 #define SERCOM_SPI_DBGCTRL_MASK 0x01ul /**< \brief (SERCOM_SPI_DBGCTRL) MASK Register */
Kojto 111:4336505e4b1c 1389
Kojto 111:4336505e4b1c 1390 /* -------- SERCOM_USART_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) USART USART Debug Control -------- */
Kojto 111:4336505e4b1c 1391 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 1392 typedef union {
Kojto 111:4336505e4b1c 1393 struct {
Kojto 111:4336505e4b1c 1394 uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */
Kojto 111:4336505e4b1c 1395 uint8_t :7; /*!< bit: 1.. 7 Reserved */
Kojto 111:4336505e4b1c 1396 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 1397 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 1398 } SERCOM_USART_DBGCTRL_Type;
Kojto 111:4336505e4b1c 1399 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 1400
Kojto 111:4336505e4b1c 1401 #define SERCOM_USART_DBGCTRL_OFFSET 0x30 /**< \brief (SERCOM_USART_DBGCTRL offset) USART Debug Control */
Kojto 111:4336505e4b1c 1402 #define SERCOM_USART_DBGCTRL_RESETVALUE 0x00ul /**< \brief (SERCOM_USART_DBGCTRL reset_value) USART Debug Control */
Kojto 111:4336505e4b1c 1403
Kojto 111:4336505e4b1c 1404 #define SERCOM_USART_DBGCTRL_DBGSTOP_Pos 0 /**< \brief (SERCOM_USART_DBGCTRL) Debug Mode */
Kojto 111:4336505e4b1c 1405 #define SERCOM_USART_DBGCTRL_DBGSTOP (0x1ul << SERCOM_USART_DBGCTRL_DBGSTOP_Pos)
Kojto 111:4336505e4b1c 1406 #define SERCOM_USART_DBGCTRL_MASK 0x01ul /**< \brief (SERCOM_USART_DBGCTRL) MASK Register */
Kojto 111:4336505e4b1c 1407
Kojto 111:4336505e4b1c 1408 /** \brief SERCOM_I2CM hardware registers */
Kojto 111:4336505e4b1c 1409 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 1410 typedef struct { /* I2C Master Mode */
Kojto 111:4336505e4b1c 1411 __IO SERCOM_I2CM_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CM Control A */
Kojto 111:4336505e4b1c 1412 __IO SERCOM_I2CM_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CM Control B */
Kojto 111:4336505e4b1c 1413 RoReg8 Reserved1[0x4];
Kojto 111:4336505e4b1c 1414 __IO SERCOM_I2CM_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 32) I2CM Baud Rate */
Kojto 111:4336505e4b1c 1415 RoReg8 Reserved2[0x4];
Kojto 111:4336505e4b1c 1416 __IO SERCOM_I2CM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) I2CM Interrupt Enable Clear */
Kojto 111:4336505e4b1c 1417 RoReg8 Reserved3[0x1];
Kojto 111:4336505e4b1c 1418 __IO SERCOM_I2CM_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) I2CM Interrupt Enable Set */
Kojto 111:4336505e4b1c 1419 RoReg8 Reserved4[0x1];
Kojto 111:4336505e4b1c 1420 __IO SERCOM_I2CM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) I2CM Interrupt Flag Status and Clear */
Kojto 111:4336505e4b1c 1421 RoReg8 Reserved5[0x1];
Kojto 111:4336505e4b1c 1422 __IO SERCOM_I2CM_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) I2CM Status */
Kojto 111:4336505e4b1c 1423 __I SERCOM_I2CM_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) I2CM Syncbusy */
Kojto 111:4336505e4b1c 1424 RoReg8 Reserved6[0x4];
Kojto 111:4336505e4b1c 1425 __IO SERCOM_I2CM_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) I2CM Address */
Kojto 111:4336505e4b1c 1426 __IO SERCOM_I2CM_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 8) I2CM Data */
Kojto 111:4336505e4b1c 1427 RoReg8 Reserved7[0x7];
Kojto 111:4336505e4b1c 1428 __IO SERCOM_I2CM_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) I2CM Debug Control */
Kojto 111:4336505e4b1c 1429 } SercomI2cm;
Kojto 111:4336505e4b1c 1430 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 1431
Kojto 111:4336505e4b1c 1432 /** \brief SERCOM_I2CS hardware registers */
Kojto 111:4336505e4b1c 1433 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 1434 typedef struct { /* I2C Slave Mode */
Kojto 111:4336505e4b1c 1435 __IO SERCOM_I2CS_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CS Control A */
Kojto 111:4336505e4b1c 1436 __IO SERCOM_I2CS_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CS Control B */
Kojto 111:4336505e4b1c 1437 RoReg8 Reserved1[0xC];
Kojto 111:4336505e4b1c 1438 __IO SERCOM_I2CS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) I2CS Interrupt Enable Clear */
Kojto 111:4336505e4b1c 1439 RoReg8 Reserved2[0x1];
Kojto 111:4336505e4b1c 1440 __IO SERCOM_I2CS_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) I2CS Interrupt Enable Set */
Kojto 111:4336505e4b1c 1441 RoReg8 Reserved3[0x1];
Kojto 111:4336505e4b1c 1442 __IO SERCOM_I2CS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) I2CS Interrupt Flag Status and Clear */
Kojto 111:4336505e4b1c 1443 RoReg8 Reserved4[0x1];
Kojto 111:4336505e4b1c 1444 __IO SERCOM_I2CS_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) I2CS Status */
Kojto 111:4336505e4b1c 1445 __I SERCOM_I2CS_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) I2CS Syncbusy */
Kojto 111:4336505e4b1c 1446 RoReg8 Reserved5[0x4];
Kojto 111:4336505e4b1c 1447 __IO SERCOM_I2CS_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) I2CS Address */
Kojto 111:4336505e4b1c 1448 __IO SERCOM_I2CS_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 8) I2CS Data */
Kojto 111:4336505e4b1c 1449 } SercomI2cs;
Kojto 111:4336505e4b1c 1450 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 1451
Kojto 111:4336505e4b1c 1452 /** \brief SERCOM_SPI hardware registers */
Kojto 111:4336505e4b1c 1453 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 1454 typedef struct { /* SPI Mode */
Kojto 111:4336505e4b1c 1455 __IO SERCOM_SPI_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) SPI Control A */
Kojto 111:4336505e4b1c 1456 __IO SERCOM_SPI_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) SPI Control B */
Kojto 111:4336505e4b1c 1457 RoReg8 Reserved1[0x4];
Kojto 111:4336505e4b1c 1458 __IO SERCOM_SPI_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 8) SPI Baud Rate */
Kojto 111:4336505e4b1c 1459 RoReg8 Reserved2[0x7];
Kojto 111:4336505e4b1c 1460 __IO SERCOM_SPI_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) SPI Interrupt Enable Clear */
Kojto 111:4336505e4b1c 1461 RoReg8 Reserved3[0x1];
Kojto 111:4336505e4b1c 1462 __IO SERCOM_SPI_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) SPI Interrupt Enable Set */
Kojto 111:4336505e4b1c 1463 RoReg8 Reserved4[0x1];
Kojto 111:4336505e4b1c 1464 __IO SERCOM_SPI_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) SPI Interrupt Flag Status and Clear */
Kojto 111:4336505e4b1c 1465 RoReg8 Reserved5[0x1];
Kojto 111:4336505e4b1c 1466 __IO SERCOM_SPI_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) SPI Status */
Kojto 111:4336505e4b1c 1467 __I SERCOM_SPI_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) SPI Syncbusy */
Kojto 111:4336505e4b1c 1468 RoReg8 Reserved6[0x4];
Kojto 111:4336505e4b1c 1469 __IO SERCOM_SPI_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) SPI Address */
Kojto 111:4336505e4b1c 1470 __IO SERCOM_SPI_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 32) SPI Data */
Kojto 111:4336505e4b1c 1471 RoReg8 Reserved7[0x4];
Kojto 111:4336505e4b1c 1472 __IO SERCOM_SPI_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) SPI Debug Control */
Kojto 111:4336505e4b1c 1473 } SercomSpi;
Kojto 111:4336505e4b1c 1474 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 1475
Kojto 111:4336505e4b1c 1476 /** \brief SERCOM_USART hardware registers */
Kojto 111:4336505e4b1c 1477 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 1478 typedef struct { /* USART Mode */
Kojto 111:4336505e4b1c 1479 __IO SERCOM_USART_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) USART Control A */
Kojto 111:4336505e4b1c 1480 __IO SERCOM_USART_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) USART Control B */
Kojto 111:4336505e4b1c 1481 RoReg8 Reserved1[0x4];
Kojto 111:4336505e4b1c 1482 __IO SERCOM_USART_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 16) USART Baud Rate */
Kojto 111:4336505e4b1c 1483 __IO SERCOM_USART_RXPL_Type RXPL; /**< \brief Offset: 0x0E (R/W 8) USART Receive Pulse Length */
Kojto 111:4336505e4b1c 1484 RoReg8 Reserved2[0x5];
Kojto 111:4336505e4b1c 1485 __IO SERCOM_USART_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) USART Interrupt Enable Clear */
Kojto 111:4336505e4b1c 1486 RoReg8 Reserved3[0x1];
Kojto 111:4336505e4b1c 1487 __IO SERCOM_USART_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) USART Interrupt Enable Set */
Kojto 111:4336505e4b1c 1488 RoReg8 Reserved4[0x1];
Kojto 111:4336505e4b1c 1489 __IO SERCOM_USART_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) USART Interrupt Flag Status and Clear */
Kojto 111:4336505e4b1c 1490 RoReg8 Reserved5[0x1];
Kojto 111:4336505e4b1c 1491 __IO SERCOM_USART_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) USART Status */
Kojto 111:4336505e4b1c 1492 __I SERCOM_USART_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) USART Syncbusy */
Kojto 111:4336505e4b1c 1493 RoReg8 Reserved6[0x8];
Kojto 111:4336505e4b1c 1494 __IO SERCOM_USART_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 16) USART Data */
Kojto 111:4336505e4b1c 1495 RoReg8 Reserved7[0x6];
Kojto 111:4336505e4b1c 1496 __IO SERCOM_USART_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) USART Debug Control */
Kojto 111:4336505e4b1c 1497 } SercomUsart;
Kojto 111:4336505e4b1c 1498 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 1499
Kojto 111:4336505e4b1c 1500 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 1501 typedef union {
Kojto 111:4336505e4b1c 1502 SercomI2cm I2CM; /**< \brief Offset: 0x00 I2C Master Mode */
Kojto 111:4336505e4b1c 1503 SercomI2cs I2CS; /**< \brief Offset: 0x00 I2C Slave Mode */
Kojto 111:4336505e4b1c 1504 SercomSpi SPI; /**< \brief Offset: 0x00 SPI Mode */
Kojto 111:4336505e4b1c 1505 SercomUsart USART; /**< \brief Offset: 0x00 USART Mode */
Kojto 111:4336505e4b1c 1506 } Sercom;
Kojto 111:4336505e4b1c 1507 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 1508
Kojto 111:4336505e4b1c 1509 /*@}*/
Kojto 111:4336505e4b1c 1510
Kojto 111:4336505e4b1c 1511 #endif /* _SAMD21_SERCOM_COMPONENT_ */