Elijah Orr / mbed-renbed

Fork of the official mbed C/C SDK provides the software platform and libraries to build your applications for RenBED.

Dependents:   1-RenBuggyTimed RenBED_RGB RenBED_RGB_PWM RenBED_RGB

Fork of mbed by mbed official

TARGET_SAMD21G18A/comp_dsu.h@121:672067c3ada4, 2016-04-14 (annotated)

Committer:
elijahorr
Date:
Thu Apr 14 07:28:54 2016 +0000
Revision:
121:672067c3ada4
Parent:
111:4336505e4b1c 
.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 111:4336505e4b1c 1 /**
Kojto 111:4336505e4b1c 2 * \file
Kojto 111:4336505e4b1c 3 *
Kojto 111:4336505e4b1c 4 * \brief Component description for DSU
Kojto 111:4336505e4b1c 5 *
Kojto 111:4336505e4b1c 6 * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
Kojto 111:4336505e4b1c 7 *
Kojto 111:4336505e4b1c 8 * \asf_license_start
Kojto 111:4336505e4b1c 9 *
Kojto 111:4336505e4b1c 10 * \page License
Kojto 111:4336505e4b1c 11 *
Kojto 111:4336505e4b1c 12 * Redistribution and use in source and binary forms, with or without
Kojto 111:4336505e4b1c 13 * modification, are permitted provided that the following conditions are met:
Kojto 111:4336505e4b1c 14 *
Kojto 111:4336505e4b1c 15 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 111:4336505e4b1c 16 * this list of conditions and the following disclaimer.
Kojto 111:4336505e4b1c 17 *
Kojto 111:4336505e4b1c 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 111:4336505e4b1c 19 * this list of conditions and the following disclaimer in the documentation
Kojto 111:4336505e4b1c 20 * and/or other materials provided with the distribution.
Kojto 111:4336505e4b1c 21 *
Kojto 111:4336505e4b1c 22 * 3. The name of Atmel may not be used to endorse or promote products derived
Kojto 111:4336505e4b1c 23 * from this software without specific prior written permission.
Kojto 111:4336505e4b1c 24 *
Kojto 111:4336505e4b1c 25 * 4. This software may only be redistributed and used in connection with an
Kojto 111:4336505e4b1c 26 * Atmel microcontroller product.
Kojto 111:4336505e4b1c 27 *
Kojto 111:4336505e4b1c 28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
Kojto 111:4336505e4b1c 29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
Kojto 111:4336505e4b1c 30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
Kojto 111:4336505e4b1c 31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
Kojto 111:4336505e4b1c 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 111:4336505e4b1c 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
Kojto 111:4336505e4b1c 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
Kojto 111:4336505e4b1c 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
Kojto 111:4336505e4b1c 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
Kojto 111:4336505e4b1c 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto 111:4336505e4b1c 38 * POSSIBILITY OF SUCH DAMAGE.
Kojto 111:4336505e4b1c 39 *
Kojto 111:4336505e4b1c 40 * \asf_license_stop
Kojto 111:4336505e4b1c 41 *
Kojto 111:4336505e4b1c 42 */
Kojto 111:4336505e4b1c 43 /*
Kojto 111:4336505e4b1c 44 * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
Kojto 111:4336505e4b1c 45 */
Kojto 111:4336505e4b1c 46
Kojto 111:4336505e4b1c 47 #ifndef _SAMD21_DSU_COMPONENT_
Kojto 111:4336505e4b1c 48 #define _SAMD21_DSU_COMPONENT_
Kojto 111:4336505e4b1c 49
Kojto 111:4336505e4b1c 50 /* ========================================================================== */
Kojto 111:4336505e4b1c 51 /** SOFTWARE API DEFINITION FOR DSU */
Kojto 111:4336505e4b1c 52 /* ========================================================================== */
Kojto 111:4336505e4b1c 53 /** \addtogroup SAMD21_DSU Device Service Unit */
Kojto 111:4336505e4b1c 54 /*@{*/
Kojto 111:4336505e4b1c 55
Kojto 111:4336505e4b1c 56 #define DSU_U2209
Kojto 111:4336505e4b1c 57 #define REV_DSU 0x202
Kojto 111:4336505e4b1c 58
Kojto 111:4336505e4b1c 59 /* -------- DSU_CTRL : (DSU Offset: 0x0000) ( /W 8) Control -------- */
Kojto 111:4336505e4b1c 60 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 61 typedef union {
Kojto 111:4336505e4b1c 62 struct {
Kojto 111:4336505e4b1c 63 uint8_t SWRST:1; /*!< bit: 0 Software Reset */
Kojto 111:4336505e4b1c 64 uint8_t :1; /*!< bit: 1 Reserved */
Kojto 111:4336505e4b1c 65 uint8_t CRC:1; /*!< bit: 2 32-bit Cyclic Redundancy Check */
Kojto 111:4336505e4b1c 66 uint8_t MBIST:1; /*!< bit: 3 Memory Built-In Self-Test */
Kojto 111:4336505e4b1c 67 uint8_t CE:1; /*!< bit: 4 Chip Erase */
Kojto 111:4336505e4b1c 68 uint8_t :3; /*!< bit: 5.. 7 Reserved */
Kojto 111:4336505e4b1c 69 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 70 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 71 } DSU_CTRL_Type;
Kojto 111:4336505e4b1c 72 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 73
Kojto 111:4336505e4b1c 74 #define DSU_CTRL_OFFSET 0x0000 /**< \brief (DSU_CTRL offset) Control */
Kojto 111:4336505e4b1c 75 #define DSU_CTRL_RESETVALUE 0x00ul /**< \brief (DSU_CTRL reset_value) Control */
Kojto 111:4336505e4b1c 76
Kojto 111:4336505e4b1c 77 #define DSU_CTRL_SWRST_Pos 0 /**< \brief (DSU_CTRL) Software Reset */
Kojto 111:4336505e4b1c 78 #define DSU_CTRL_SWRST (0x1ul << DSU_CTRL_SWRST_Pos)
Kojto 111:4336505e4b1c 79 #define DSU_CTRL_CRC_Pos 2 /**< \brief (DSU_CTRL) 32-bit Cyclic Redundancy Check */
Kojto 111:4336505e4b1c 80 #define DSU_CTRL_CRC (0x1ul << DSU_CTRL_CRC_Pos)
Kojto 111:4336505e4b1c 81 #define DSU_CTRL_MBIST_Pos 3 /**< \brief (DSU_CTRL) Memory Built-In Self-Test */
Kojto 111:4336505e4b1c 82 #define DSU_CTRL_MBIST (0x1ul << DSU_CTRL_MBIST_Pos)
Kojto 111:4336505e4b1c 83 #define DSU_CTRL_CE_Pos 4 /**< \brief (DSU_CTRL) Chip Erase */
Kojto 111:4336505e4b1c 84 #define DSU_CTRL_CE (0x1ul << DSU_CTRL_CE_Pos)
Kojto 111:4336505e4b1c 85 #define DSU_CTRL_MASK 0x1Dul /**< \brief (DSU_CTRL) MASK Register */
Kojto 111:4336505e4b1c 86
Kojto 111:4336505e4b1c 87 /* -------- DSU_STATUSA : (DSU Offset: 0x0001) (R/W 8) Status A -------- */
Kojto 111:4336505e4b1c 88 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 89 typedef union {
Kojto 111:4336505e4b1c 90 struct {
Kojto 111:4336505e4b1c 91 uint8_t DONE:1; /*!< bit: 0 Done */
Kojto 111:4336505e4b1c 92 uint8_t CRSTEXT:1; /*!< bit: 1 CPU Reset Phase Extension */
Kojto 111:4336505e4b1c 93 uint8_t BERR:1; /*!< bit: 2 Bus Error */
Kojto 111:4336505e4b1c 94 uint8_t FAIL:1; /*!< bit: 3 Failure */
Kojto 111:4336505e4b1c 95 uint8_t PERR:1; /*!< bit: 4 Protection Error */
Kojto 111:4336505e4b1c 96 uint8_t :3; /*!< bit: 5.. 7 Reserved */
Kojto 111:4336505e4b1c 97 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 98 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 99 } DSU_STATUSA_Type;
Kojto 111:4336505e4b1c 100 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 101
Kojto 111:4336505e4b1c 102 #define DSU_STATUSA_OFFSET 0x0001 /**< \brief (DSU_STATUSA offset) Status A */
Kojto 111:4336505e4b1c 103 #define DSU_STATUSA_RESETVALUE 0x00ul /**< \brief (DSU_STATUSA reset_value) Status A */
Kojto 111:4336505e4b1c 104
Kojto 111:4336505e4b1c 105 #define DSU_STATUSA_DONE_Pos 0 /**< \brief (DSU_STATUSA) Done */
Kojto 111:4336505e4b1c 106 #define DSU_STATUSA_DONE (0x1ul << DSU_STATUSA_DONE_Pos)
Kojto 111:4336505e4b1c 107 #define DSU_STATUSA_CRSTEXT_Pos 1 /**< \brief (DSU_STATUSA) CPU Reset Phase Extension */
Kojto 111:4336505e4b1c 108 #define DSU_STATUSA_CRSTEXT (0x1ul << DSU_STATUSA_CRSTEXT_Pos)
Kojto 111:4336505e4b1c 109 #define DSU_STATUSA_BERR_Pos 2 /**< \brief (DSU_STATUSA) Bus Error */
Kojto 111:4336505e4b1c 110 #define DSU_STATUSA_BERR (0x1ul << DSU_STATUSA_BERR_Pos)
Kojto 111:4336505e4b1c 111 #define DSU_STATUSA_FAIL_Pos 3 /**< \brief (DSU_STATUSA) Failure */
Kojto 111:4336505e4b1c 112 #define DSU_STATUSA_FAIL (0x1ul << DSU_STATUSA_FAIL_Pos)
Kojto 111:4336505e4b1c 113 #define DSU_STATUSA_PERR_Pos 4 /**< \brief (DSU_STATUSA) Protection Error */
Kojto 111:4336505e4b1c 114 #define DSU_STATUSA_PERR (0x1ul << DSU_STATUSA_PERR_Pos)
Kojto 111:4336505e4b1c 115 #define DSU_STATUSA_MASK 0x1Ful /**< \brief (DSU_STATUSA) MASK Register */
Kojto 111:4336505e4b1c 116
Kojto 111:4336505e4b1c 117 /* -------- DSU_STATUSB : (DSU Offset: 0x0002) (R/ 8) Status B -------- */
Kojto 111:4336505e4b1c 118 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 119 typedef union {
Kojto 111:4336505e4b1c 120 struct {
Kojto 111:4336505e4b1c 121 uint8_t PROT:1; /*!< bit: 0 Protected */
Kojto 111:4336505e4b1c 122 uint8_t DBGPRES:1; /*!< bit: 1 Debugger Present */
Kojto 111:4336505e4b1c 123 uint8_t DCCD0:1; /*!< bit: 2 Debug Communication Channel 0 Dirty */
Kojto 111:4336505e4b1c 124 uint8_t DCCD1:1; /*!< bit: 3 Debug Communication Channel 1 Dirty */
Kojto 111:4336505e4b1c 125 uint8_t HPE:1; /*!< bit: 4 Hot-Plugging Enable */
Kojto 111:4336505e4b1c 126 uint8_t :3; /*!< bit: 5.. 7 Reserved */
Kojto 111:4336505e4b1c 127 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 128 struct {
Kojto 111:4336505e4b1c 129 uint8_t :2; /*!< bit: 0.. 1 Reserved */
Kojto 111:4336505e4b1c 130 uint8_t DCCD:2; /*!< bit: 2.. 3 Debug Communication Channel x Dirty */
Kojto 111:4336505e4b1c 131 uint8_t :4; /*!< bit: 4.. 7 Reserved */
Kojto 111:4336505e4b1c 132 } vec; /*!< Structure used for vec access */
Kojto 111:4336505e4b1c 133 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 134 } DSU_STATUSB_Type;
Kojto 111:4336505e4b1c 135 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 136
Kojto 111:4336505e4b1c 137 #define DSU_STATUSB_OFFSET 0x0002 /**< \brief (DSU_STATUSB offset) Status B */
Kojto 111:4336505e4b1c 138 #define DSU_STATUSB_RESETVALUE 0x10ul /**< \brief (DSU_STATUSB reset_value) Status B */
Kojto 111:4336505e4b1c 139
Kojto 111:4336505e4b1c 140 #define DSU_STATUSB_PROT_Pos 0 /**< \brief (DSU_STATUSB) Protected */
Kojto 111:4336505e4b1c 141 #define DSU_STATUSB_PROT (0x1ul << DSU_STATUSB_PROT_Pos)
Kojto 111:4336505e4b1c 142 #define DSU_STATUSB_DBGPRES_Pos 1 /**< \brief (DSU_STATUSB) Debugger Present */
Kojto 111:4336505e4b1c 143 #define DSU_STATUSB_DBGPRES (0x1ul << DSU_STATUSB_DBGPRES_Pos)
Kojto 111:4336505e4b1c 144 #define DSU_STATUSB_DCCD0_Pos 2 /**< \brief (DSU_STATUSB) Debug Communication Channel 0 Dirty */
Kojto 111:4336505e4b1c 145 #define DSU_STATUSB_DCCD0 (1 << DSU_STATUSB_DCCD0_Pos)
Kojto 111:4336505e4b1c 146 #define DSU_STATUSB_DCCD1_Pos 3 /**< \brief (DSU_STATUSB) Debug Communication Channel 1 Dirty */
Kojto 111:4336505e4b1c 147 #define DSU_STATUSB_DCCD1 (1 << DSU_STATUSB_DCCD1_Pos)
Kojto 111:4336505e4b1c 148 #define DSU_STATUSB_DCCD_Pos 2 /**< \brief (DSU_STATUSB) Debug Communication Channel x Dirty */
Kojto 111:4336505e4b1c 149 #define DSU_STATUSB_DCCD_Msk (0x3ul << DSU_STATUSB_DCCD_Pos)
Kojto 111:4336505e4b1c 150 #define DSU_STATUSB_DCCD(value) ((DSU_STATUSB_DCCD_Msk & ((value) << DSU_STATUSB_DCCD_Pos)))
Kojto 111:4336505e4b1c 151 #define DSU_STATUSB_HPE_Pos 4 /**< \brief (DSU_STATUSB) Hot-Plugging Enable */
Kojto 111:4336505e4b1c 152 #define DSU_STATUSB_HPE (0x1ul << DSU_STATUSB_HPE_Pos)
Kojto 111:4336505e4b1c 153 #define DSU_STATUSB_MASK 0x1Ful /**< \brief (DSU_STATUSB) MASK Register */
Kojto 111:4336505e4b1c 154
Kojto 111:4336505e4b1c 155 /* -------- DSU_ADDR : (DSU Offset: 0x0004) (R/W 32) Address -------- */
Kojto 111:4336505e4b1c 156 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 157 typedef union {
Kojto 111:4336505e4b1c 158 struct {
Kojto 111:4336505e4b1c 159 uint32_t :2; /*!< bit: 0.. 1 Reserved */
Kojto 111:4336505e4b1c 160 uint32_t ADDR:30; /*!< bit: 2..31 Address */
Kojto 111:4336505e4b1c 161 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 162 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 163 } DSU_ADDR_Type;
Kojto 111:4336505e4b1c 164 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 165
Kojto 111:4336505e4b1c 166 #define DSU_ADDR_OFFSET 0x0004 /**< \brief (DSU_ADDR offset) Address */
Kojto 111:4336505e4b1c 167 #define DSU_ADDR_RESETVALUE 0x00000000ul /**< \brief (DSU_ADDR reset_value) Address */
Kojto 111:4336505e4b1c 168
Kojto 111:4336505e4b1c 169 #define DSU_ADDR_ADDR_Pos 2 /**< \brief (DSU_ADDR) Address */
Kojto 111:4336505e4b1c 170 #define DSU_ADDR_ADDR_Msk (0x3FFFFFFFul << DSU_ADDR_ADDR_Pos)
Kojto 111:4336505e4b1c 171 #define DSU_ADDR_ADDR(value) ((DSU_ADDR_ADDR_Msk & ((value) << DSU_ADDR_ADDR_Pos)))
Kojto 111:4336505e4b1c 172 #define DSU_ADDR_MASK 0xFFFFFFFCul /**< \brief (DSU_ADDR) MASK Register */
Kojto 111:4336505e4b1c 173
Kojto 111:4336505e4b1c 174 /* -------- DSU_LENGTH : (DSU Offset: 0x0008) (R/W 32) Length -------- */
Kojto 111:4336505e4b1c 175 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 176 typedef union {
Kojto 111:4336505e4b1c 177 struct {
Kojto 111:4336505e4b1c 178 uint32_t :2; /*!< bit: 0.. 1 Reserved */
Kojto 111:4336505e4b1c 179 uint32_t LENGTH:30; /*!< bit: 2..31 Length */
Kojto 111:4336505e4b1c 180 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 181 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 182 } DSU_LENGTH_Type;
Kojto 111:4336505e4b1c 183 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 184
Kojto 111:4336505e4b1c 185 #define DSU_LENGTH_OFFSET 0x0008 /**< \brief (DSU_LENGTH offset) Length */
Kojto 111:4336505e4b1c 186 #define DSU_LENGTH_RESETVALUE 0x00000000ul /**< \brief (DSU_LENGTH reset_value) Length */
Kojto 111:4336505e4b1c 187
Kojto 111:4336505e4b1c 188 #define DSU_LENGTH_LENGTH_Pos 2 /**< \brief (DSU_LENGTH) Length */
Kojto 111:4336505e4b1c 189 #define DSU_LENGTH_LENGTH_Msk (0x3FFFFFFFul << DSU_LENGTH_LENGTH_Pos)
Kojto 111:4336505e4b1c 190 #define DSU_LENGTH_LENGTH(value) ((DSU_LENGTH_LENGTH_Msk & ((value) << DSU_LENGTH_LENGTH_Pos)))
Kojto 111:4336505e4b1c 191 #define DSU_LENGTH_MASK 0xFFFFFFFCul /**< \brief (DSU_LENGTH) MASK Register */
Kojto 111:4336505e4b1c 192
Kojto 111:4336505e4b1c 193 /* -------- DSU_DATA : (DSU Offset: 0x000C) (R/W 32) Data -------- */
Kojto 111:4336505e4b1c 194 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 195 typedef union {
Kojto 111:4336505e4b1c 196 struct {
Kojto 111:4336505e4b1c 197 uint32_t DATA:32; /*!< bit: 0..31 Data */
Kojto 111:4336505e4b1c 198 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 199 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 200 } DSU_DATA_Type;
Kojto 111:4336505e4b1c 201 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 202
Kojto 111:4336505e4b1c 203 #define DSU_DATA_OFFSET 0x000C /**< \brief (DSU_DATA offset) Data */
Kojto 111:4336505e4b1c 204 #define DSU_DATA_RESETVALUE 0x00000000ul /**< \brief (DSU_DATA reset_value) Data */
Kojto 111:4336505e4b1c 205
Kojto 111:4336505e4b1c 206 #define DSU_DATA_DATA_Pos 0 /**< \brief (DSU_DATA) Data */
Kojto 111:4336505e4b1c 207 #define DSU_DATA_DATA_Msk (0xFFFFFFFFul << DSU_DATA_DATA_Pos)
Kojto 111:4336505e4b1c 208 #define DSU_DATA_DATA(value) ((DSU_DATA_DATA_Msk & ((value) << DSU_DATA_DATA_Pos)))
Kojto 111:4336505e4b1c 209 #define DSU_DATA_MASK 0xFFFFFFFFul /**< \brief (DSU_DATA) MASK Register */
Kojto 111:4336505e4b1c 210
Kojto 111:4336505e4b1c 211 /* -------- DSU_DCC : (DSU Offset: 0x0010) (R/W 32) Debug Communication Channel n -------- */
Kojto 111:4336505e4b1c 212 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 213 typedef union {
Kojto 111:4336505e4b1c 214 struct {
Kojto 111:4336505e4b1c 215 uint32_t DATA:32; /*!< bit: 0..31 Data */
Kojto 111:4336505e4b1c 216 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 217 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 218 } DSU_DCC_Type;
Kojto 111:4336505e4b1c 219 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 220
Kojto 111:4336505e4b1c 221 #define DSU_DCC_OFFSET 0x0010 /**< \brief (DSU_DCC offset) Debug Communication Channel n */
Kojto 111:4336505e4b1c 222 #define DSU_DCC_RESETVALUE 0x00000000ul /**< \brief (DSU_DCC reset_value) Debug Communication Channel n */
Kojto 111:4336505e4b1c 223
Kojto 111:4336505e4b1c 224 #define DSU_DCC_DATA_Pos 0 /**< \brief (DSU_DCC) Data */
Kojto 111:4336505e4b1c 225 #define DSU_DCC_DATA_Msk (0xFFFFFFFFul << DSU_DCC_DATA_Pos)
Kojto 111:4336505e4b1c 226 #define DSU_DCC_DATA(value) ((DSU_DCC_DATA_Msk & ((value) << DSU_DCC_DATA_Pos)))
Kojto 111:4336505e4b1c 227 #define DSU_DCC_MASK 0xFFFFFFFFul /**< \brief (DSU_DCC) MASK Register */
Kojto 111:4336505e4b1c 228
Kojto 111:4336505e4b1c 229 /* -------- DSU_DID : (DSU Offset: 0x0018) (R/ 32) Device Identification -------- */
Kojto 111:4336505e4b1c 230 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 231 typedef union {
Kojto 111:4336505e4b1c 232 struct {
Kojto 111:4336505e4b1c 233 uint32_t DEVSEL:8; /*!< bit: 0.. 7 Device Select */
Kojto 111:4336505e4b1c 234 uint32_t REVISION:4; /*!< bit: 8..11 Revision */
Kojto 111:4336505e4b1c 235 uint32_t DIE:4; /*!< bit: 12..15 Die Identification */
Kojto 111:4336505e4b1c 236 uint32_t SERIES:6; /*!< bit: 16..21 Product Series */
Kojto 111:4336505e4b1c 237 uint32_t :1; /*!< bit: 22 Reserved */
Kojto 111:4336505e4b1c 238 uint32_t FAMILY:5; /*!< bit: 23..27 Product Family */
Kojto 111:4336505e4b1c 239 uint32_t PROCESSOR:4; /*!< bit: 28..31 Processor */
Kojto 111:4336505e4b1c 240 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 241 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 242 } DSU_DID_Type;
Kojto 111:4336505e4b1c 243 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 244
Kojto 111:4336505e4b1c 245 #define DSU_DID_OFFSET 0x0018 /**< \brief (DSU_DID offset) Device Identification */
Kojto 111:4336505e4b1c 246
Kojto 111:4336505e4b1c 247 #define DSU_DID_DEVSEL_Pos 0 /**< \brief (DSU_DID) Device Select */
Kojto 111:4336505e4b1c 248 #define DSU_DID_DEVSEL_Msk (0xFFul << DSU_DID_DEVSEL_Pos)
Kojto 111:4336505e4b1c 249 #define DSU_DID_DEVSEL(value) ((DSU_DID_DEVSEL_Msk & ((value) << DSU_DID_DEVSEL_Pos)))
Kojto 111:4336505e4b1c 250 #define DSU_DID_REVISION_Pos 8 /**< \brief (DSU_DID) Revision */
Kojto 111:4336505e4b1c 251 #define DSU_DID_REVISION_Msk (0xFul << DSU_DID_REVISION_Pos)
Kojto 111:4336505e4b1c 252 #define DSU_DID_REVISION(value) ((DSU_DID_REVISION_Msk & ((value) << DSU_DID_REVISION_Pos)))
Kojto 111:4336505e4b1c 253 #define DSU_DID_DIE_Pos 12 /**< \brief (DSU_DID) Die Identification */
Kojto 111:4336505e4b1c 254 #define DSU_DID_DIE_Msk (0xFul << DSU_DID_DIE_Pos)
Kojto 111:4336505e4b1c 255 #define DSU_DID_DIE(value) ((DSU_DID_DIE_Msk & ((value) << DSU_DID_DIE_Pos)))
Kojto 111:4336505e4b1c 256 #define DSU_DID_SERIES_Pos 16 /**< \brief (DSU_DID) Product Series */
Kojto 111:4336505e4b1c 257 #define DSU_DID_SERIES_Msk (0x3Ful << DSU_DID_SERIES_Pos)
Kojto 111:4336505e4b1c 258 #define DSU_DID_SERIES(value) ((DSU_DID_SERIES_Msk & ((value) << DSU_DID_SERIES_Pos)))
Kojto 111:4336505e4b1c 259 #define DSU_DID_FAMILY_Pos 23 /**< \brief (DSU_DID) Product Family */
Kojto 111:4336505e4b1c 260 #define DSU_DID_FAMILY_Msk (0x1Ful << DSU_DID_FAMILY_Pos)
Kojto 111:4336505e4b1c 261 #define DSU_DID_FAMILY(value) ((DSU_DID_FAMILY_Msk & ((value) << DSU_DID_FAMILY_Pos)))
Kojto 111:4336505e4b1c 262 #define DSU_DID_PROCESSOR_Pos 28 /**< \brief (DSU_DID) Processor */
Kojto 111:4336505e4b1c 263 #define DSU_DID_PROCESSOR_Msk (0xFul << DSU_DID_PROCESSOR_Pos)
Kojto 111:4336505e4b1c 264 #define DSU_DID_PROCESSOR(value) ((DSU_DID_PROCESSOR_Msk & ((value) << DSU_DID_PROCESSOR_Pos)))
Kojto 111:4336505e4b1c 265 #define DSU_DID_MASK 0xFFBFFFFFul /**< \brief (DSU_DID) MASK Register */
Kojto 111:4336505e4b1c 266
Kojto 111:4336505e4b1c 267 /* -------- DSU_ENTRY : (DSU Offset: 0x1000) (R/ 32) Coresight ROM Table Entry n -------- */
Kojto 111:4336505e4b1c 268 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 269 typedef union {
Kojto 111:4336505e4b1c 270 struct {
Kojto 111:4336505e4b1c 271 uint32_t EPRES:1; /*!< bit: 0 Entry Present */
Kojto 111:4336505e4b1c 272 uint32_t FMT:1; /*!< bit: 1 Format */
Kojto 111:4336505e4b1c 273 uint32_t :10; /*!< bit: 2..11 Reserved */
Kojto 111:4336505e4b1c 274 uint32_t ADDOFF:20; /*!< bit: 12..31 Address Offset */
Kojto 111:4336505e4b1c 275 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 276 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 277 } DSU_ENTRY_Type;
Kojto 111:4336505e4b1c 278 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 279
Kojto 111:4336505e4b1c 280 #define DSU_ENTRY_OFFSET 0x1000 /**< \brief (DSU_ENTRY offset) Coresight ROM Table Entry n */
Kojto 111:4336505e4b1c 281 #define DSU_ENTRY_RESETVALUE 0x00000002ul /**< \brief (DSU_ENTRY reset_value) Coresight ROM Table Entry n */
Kojto 111:4336505e4b1c 282
Kojto 111:4336505e4b1c 283 #define DSU_ENTRY_EPRES_Pos 0 /**< \brief (DSU_ENTRY) Entry Present */
Kojto 111:4336505e4b1c 284 #define DSU_ENTRY_EPRES (0x1ul << DSU_ENTRY_EPRES_Pos)
Kojto 111:4336505e4b1c 285 #define DSU_ENTRY_FMT_Pos 1 /**< \brief (DSU_ENTRY) Format */
Kojto 111:4336505e4b1c 286 #define DSU_ENTRY_FMT (0x1ul << DSU_ENTRY_FMT_Pos)
Kojto 111:4336505e4b1c 287 #define DSU_ENTRY_ADDOFF_Pos 12 /**< \brief (DSU_ENTRY) Address Offset */
Kojto 111:4336505e4b1c 288 #define DSU_ENTRY_ADDOFF_Msk (0xFFFFFul << DSU_ENTRY_ADDOFF_Pos)
Kojto 111:4336505e4b1c 289 #define DSU_ENTRY_ADDOFF(value) ((DSU_ENTRY_ADDOFF_Msk & ((value) << DSU_ENTRY_ADDOFF_Pos)))
Kojto 111:4336505e4b1c 290 #define DSU_ENTRY_MASK 0xFFFFF003ul /**< \brief (DSU_ENTRY) MASK Register */
Kojto 111:4336505e4b1c 291
Kojto 111:4336505e4b1c 292 /* -------- DSU_END : (DSU Offset: 0x1008) (R/ 32) Coresight ROM Table End -------- */
Kojto 111:4336505e4b1c 293 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 294 typedef union {
Kojto 111:4336505e4b1c 295 struct {
Kojto 111:4336505e4b1c 296 uint32_t END:32; /*!< bit: 0..31 End Marker */
Kojto 111:4336505e4b1c 297 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 298 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 299 } DSU_END_Type;
Kojto 111:4336505e4b1c 300 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 301
Kojto 111:4336505e4b1c 302 #define DSU_END_OFFSET 0x1008 /**< \brief (DSU_END offset) Coresight ROM Table End */
Kojto 111:4336505e4b1c 303 #define DSU_END_RESETVALUE 0x00000000ul /**< \brief (DSU_END reset_value) Coresight ROM Table End */
Kojto 111:4336505e4b1c 304
Kojto 111:4336505e4b1c 305 #define DSU_END_END_Pos 0 /**< \brief (DSU_END) End Marker */
Kojto 111:4336505e4b1c 306 #define DSU_END_END_Msk (0xFFFFFFFFul << DSU_END_END_Pos)
Kojto 111:4336505e4b1c 307 #define DSU_END_END(value) ((DSU_END_END_Msk & ((value) << DSU_END_END_Pos)))
Kojto 111:4336505e4b1c 308 #define DSU_END_MASK 0xFFFFFFFFul /**< \brief (DSU_END) MASK Register */
Kojto 111:4336505e4b1c 309
Kojto 111:4336505e4b1c 310 /* -------- DSU_MEMTYPE : (DSU Offset: 0x1FCC) (R/ 32) Coresight ROM Table Memory Type -------- */
Kojto 111:4336505e4b1c 311 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 312 typedef union {
Kojto 111:4336505e4b1c 313 struct {
Kojto 111:4336505e4b1c 314 uint32_t SMEMP:1; /*!< bit: 0 System Memory Present */
Kojto 111:4336505e4b1c 315 uint32_t :31; /*!< bit: 1..31 Reserved */
Kojto 111:4336505e4b1c 316 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 317 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 318 } DSU_MEMTYPE_Type;
Kojto 111:4336505e4b1c 319 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 320
Kojto 111:4336505e4b1c 321 #define DSU_MEMTYPE_OFFSET 0x1FCC /**< \brief (DSU_MEMTYPE offset) Coresight ROM Table Memory Type */
Kojto 111:4336505e4b1c 322 #define DSU_MEMTYPE_RESETVALUE 0x00000000ul /**< \brief (DSU_MEMTYPE reset_value) Coresight ROM Table Memory Type */
Kojto 111:4336505e4b1c 323
Kojto 111:4336505e4b1c 324 #define DSU_MEMTYPE_SMEMP_Pos 0 /**< \brief (DSU_MEMTYPE) System Memory Present */
Kojto 111:4336505e4b1c 325 #define DSU_MEMTYPE_SMEMP (0x1ul << DSU_MEMTYPE_SMEMP_Pos)
Kojto 111:4336505e4b1c 326 #define DSU_MEMTYPE_MASK 0x00000001ul /**< \brief (DSU_MEMTYPE) MASK Register */
Kojto 111:4336505e4b1c 327
Kojto 111:4336505e4b1c 328 /* -------- DSU_PID4 : (DSU Offset: 0x1FD0) (R/ 32) Peripheral Identification 4 -------- */
Kojto 111:4336505e4b1c 329 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 330 typedef union {
Kojto 111:4336505e4b1c 331 struct {
Kojto 111:4336505e4b1c 332 uint32_t JEPCC:4; /*!< bit: 0.. 3 JEP-106 Continuation Code */
Kojto 111:4336505e4b1c 333 uint32_t FKBC:4; /*!< bit: 4.. 7 4KB Count */
Kojto 111:4336505e4b1c 334 uint32_t :24; /*!< bit: 8..31 Reserved */
Kojto 111:4336505e4b1c 335 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 336 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 337 } DSU_PID4_Type;
Kojto 111:4336505e4b1c 338 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 339
Kojto 111:4336505e4b1c 340 #define DSU_PID4_OFFSET 0x1FD0 /**< \brief (DSU_PID4 offset) Peripheral Identification 4 */
Kojto 111:4336505e4b1c 341 #define DSU_PID4_RESETVALUE 0x00000000ul /**< \brief (DSU_PID4 reset_value) Peripheral Identification 4 */
Kojto 111:4336505e4b1c 342
Kojto 111:4336505e4b1c 343 #define DSU_PID4_JEPCC_Pos 0 /**< \brief (DSU_PID4) JEP-106 Continuation Code */
Kojto 111:4336505e4b1c 344 #define DSU_PID4_JEPCC_Msk (0xFul << DSU_PID4_JEPCC_Pos)
Kojto 111:4336505e4b1c 345 #define DSU_PID4_JEPCC(value) ((DSU_PID4_JEPCC_Msk & ((value) << DSU_PID4_JEPCC_Pos)))
Kojto 111:4336505e4b1c 346 #define DSU_PID4_FKBC_Pos 4 /**< \brief (DSU_PID4) 4KB Count */
Kojto 111:4336505e4b1c 347 #define DSU_PID4_FKBC_Msk (0xFul << DSU_PID4_FKBC_Pos)
Kojto 111:4336505e4b1c 348 #define DSU_PID4_FKBC(value) ((DSU_PID4_FKBC_Msk & ((value) << DSU_PID4_FKBC_Pos)))
Kojto 111:4336505e4b1c 349 #define DSU_PID4_MASK 0x000000FFul /**< \brief (DSU_PID4) MASK Register */
Kojto 111:4336505e4b1c 350
Kojto 111:4336505e4b1c 351 /* -------- DSU_PID0 : (DSU Offset: 0x1FE0) (R/ 32) Peripheral Identification 0 -------- */
Kojto 111:4336505e4b1c 352 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 353 typedef union {
Kojto 111:4336505e4b1c 354 struct {
Kojto 111:4336505e4b1c 355 uint32_t PARTNBL:8; /*!< bit: 0.. 7 Part Number Low */
Kojto 111:4336505e4b1c 356 uint32_t :24; /*!< bit: 8..31 Reserved */
Kojto 111:4336505e4b1c 357 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 358 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 359 } DSU_PID0_Type;
Kojto 111:4336505e4b1c 360 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 361
Kojto 111:4336505e4b1c 362 #define DSU_PID0_OFFSET 0x1FE0 /**< \brief (DSU_PID0 offset) Peripheral Identification 0 */
Kojto 111:4336505e4b1c 363 #define DSU_PID0_RESETVALUE 0x000000D0ul /**< \brief (DSU_PID0 reset_value) Peripheral Identification 0 */
Kojto 111:4336505e4b1c 364
Kojto 111:4336505e4b1c 365 #define DSU_PID0_PARTNBL_Pos 0 /**< \brief (DSU_PID0) Part Number Low */
Kojto 111:4336505e4b1c 366 #define DSU_PID0_PARTNBL_Msk (0xFFul << DSU_PID0_PARTNBL_Pos)
Kojto 111:4336505e4b1c 367 #define DSU_PID0_PARTNBL(value) ((DSU_PID0_PARTNBL_Msk & ((value) << DSU_PID0_PARTNBL_Pos)))
Kojto 111:4336505e4b1c 368 #define DSU_PID0_MASK 0x000000FFul /**< \brief (DSU_PID0) MASK Register */
Kojto 111:4336505e4b1c 369
Kojto 111:4336505e4b1c 370 /* -------- DSU_PID1 : (DSU Offset: 0x1FE4) (R/ 32) Peripheral Identification 1 -------- */
Kojto 111:4336505e4b1c 371 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 372 typedef union {
Kojto 111:4336505e4b1c 373 struct {
Kojto 111:4336505e4b1c 374 uint32_t PARTNBH:4; /*!< bit: 0.. 3 Part Number High */
Kojto 111:4336505e4b1c 375 uint32_t JEPIDCL:4; /*!< bit: 4.. 7 Low part of the JEP-106 Identity Code */
Kojto 111:4336505e4b1c 376 uint32_t :24; /*!< bit: 8..31 Reserved */
Kojto 111:4336505e4b1c 377 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 378 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 379 } DSU_PID1_Type;
Kojto 111:4336505e4b1c 380 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 381
Kojto 111:4336505e4b1c 382 #define DSU_PID1_OFFSET 0x1FE4 /**< \brief (DSU_PID1 offset) Peripheral Identification 1 */
Kojto 111:4336505e4b1c 383 #define DSU_PID1_RESETVALUE 0x000000FCul /**< \brief (DSU_PID1 reset_value) Peripheral Identification 1 */
Kojto 111:4336505e4b1c 384
Kojto 111:4336505e4b1c 385 #define DSU_PID1_PARTNBH_Pos 0 /**< \brief (DSU_PID1) Part Number High */
Kojto 111:4336505e4b1c 386 #define DSU_PID1_PARTNBH_Msk (0xFul << DSU_PID1_PARTNBH_Pos)
Kojto 111:4336505e4b1c 387 #define DSU_PID1_PARTNBH(value) ((DSU_PID1_PARTNBH_Msk & ((value) << DSU_PID1_PARTNBH_Pos)))
Kojto 111:4336505e4b1c 388 #define DSU_PID1_JEPIDCL_Pos 4 /**< \brief (DSU_PID1) Low part of the JEP-106 Identity Code */
Kojto 111:4336505e4b1c 389 #define DSU_PID1_JEPIDCL_Msk (0xFul << DSU_PID1_JEPIDCL_Pos)
Kojto 111:4336505e4b1c 390 #define DSU_PID1_JEPIDCL(value) ((DSU_PID1_JEPIDCL_Msk & ((value) << DSU_PID1_JEPIDCL_Pos)))
Kojto 111:4336505e4b1c 391 #define DSU_PID1_MASK 0x000000FFul /**< \brief (DSU_PID1) MASK Register */
Kojto 111:4336505e4b1c 392
Kojto 111:4336505e4b1c 393 /* -------- DSU_PID2 : (DSU Offset: 0x1FE8) (R/ 32) Peripheral Identification 2 -------- */
Kojto 111:4336505e4b1c 394 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 395 typedef union {
Kojto 111:4336505e4b1c 396 struct {
Kojto 111:4336505e4b1c 397 uint32_t JEPIDCH:3; /*!< bit: 0.. 2 JEP-106 Identity Code High */
Kojto 111:4336505e4b1c 398 uint32_t JEPU:1; /*!< bit: 3 JEP-106 Identity Code is used */
Kojto 111:4336505e4b1c 399 uint32_t REVISION:4; /*!< bit: 4.. 7 Revision Number */
Kojto 111:4336505e4b1c 400 uint32_t :24; /*!< bit: 8..31 Reserved */
Kojto 111:4336505e4b1c 401 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 402 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 403 } DSU_PID2_Type;
Kojto 111:4336505e4b1c 404 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 405
Kojto 111:4336505e4b1c 406 #define DSU_PID2_OFFSET 0x1FE8 /**< \brief (DSU_PID2 offset) Peripheral Identification 2 */
Kojto 111:4336505e4b1c 407 #define DSU_PID2_RESETVALUE 0x00000009ul /**< \brief (DSU_PID2 reset_value) Peripheral Identification 2 */
Kojto 111:4336505e4b1c 408
Kojto 111:4336505e4b1c 409 #define DSU_PID2_JEPIDCH_Pos 0 /**< \brief (DSU_PID2) JEP-106 Identity Code High */
Kojto 111:4336505e4b1c 410 #define DSU_PID2_JEPIDCH_Msk (0x7ul << DSU_PID2_JEPIDCH_Pos)
Kojto 111:4336505e4b1c 411 #define DSU_PID2_JEPIDCH(value) ((DSU_PID2_JEPIDCH_Msk & ((value) << DSU_PID2_JEPIDCH_Pos)))
Kojto 111:4336505e4b1c 412 #define DSU_PID2_JEPU_Pos 3 /**< \brief (DSU_PID2) JEP-106 Identity Code is used */
Kojto 111:4336505e4b1c 413 #define DSU_PID2_JEPU (0x1ul << DSU_PID2_JEPU_Pos)
Kojto 111:4336505e4b1c 414 #define DSU_PID2_REVISION_Pos 4 /**< \brief (DSU_PID2) Revision Number */
Kojto 111:4336505e4b1c 415 #define DSU_PID2_REVISION_Msk (0xFul << DSU_PID2_REVISION_Pos)
Kojto 111:4336505e4b1c 416 #define DSU_PID2_REVISION(value) ((DSU_PID2_REVISION_Msk & ((value) << DSU_PID2_REVISION_Pos)))
Kojto 111:4336505e4b1c 417 #define DSU_PID2_MASK 0x000000FFul /**< \brief (DSU_PID2) MASK Register */
Kojto 111:4336505e4b1c 418
Kojto 111:4336505e4b1c 419 /* -------- DSU_PID3 : (DSU Offset: 0x1FEC) (R/ 32) Peripheral Identification 3 -------- */
Kojto 111:4336505e4b1c 420 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 421 typedef union {
Kojto 111:4336505e4b1c 422 struct {
Kojto 111:4336505e4b1c 423 uint32_t CUSMOD:4; /*!< bit: 0.. 3 ARM CUSMOD */
Kojto 111:4336505e4b1c 424 uint32_t REVAND:4; /*!< bit: 4.. 7 Revision Number */
Kojto 111:4336505e4b1c 425 uint32_t :24; /*!< bit: 8..31 Reserved */
Kojto 111:4336505e4b1c 426 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 427 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 428 } DSU_PID3_Type;
Kojto 111:4336505e4b1c 429 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 430
Kojto 111:4336505e4b1c 431 #define DSU_PID3_OFFSET 0x1FEC /**< \brief (DSU_PID3 offset) Peripheral Identification 3 */
Kojto 111:4336505e4b1c 432 #define DSU_PID3_RESETVALUE 0x00000000ul /**< \brief (DSU_PID3 reset_value) Peripheral Identification 3 */
Kojto 111:4336505e4b1c 433
Kojto 111:4336505e4b1c 434 #define DSU_PID3_CUSMOD_Pos 0 /**< \brief (DSU_PID3) ARM CUSMOD */
Kojto 111:4336505e4b1c 435 #define DSU_PID3_CUSMOD_Msk (0xFul << DSU_PID3_CUSMOD_Pos)
Kojto 111:4336505e4b1c 436 #define DSU_PID3_CUSMOD(value) ((DSU_PID3_CUSMOD_Msk & ((value) << DSU_PID3_CUSMOD_Pos)))
Kojto 111:4336505e4b1c 437 #define DSU_PID3_REVAND_Pos 4 /**< \brief (DSU_PID3) Revision Number */
Kojto 111:4336505e4b1c 438 #define DSU_PID3_REVAND_Msk (0xFul << DSU_PID3_REVAND_Pos)
Kojto 111:4336505e4b1c 439 #define DSU_PID3_REVAND(value) ((DSU_PID3_REVAND_Msk & ((value) << DSU_PID3_REVAND_Pos)))
Kojto 111:4336505e4b1c 440 #define DSU_PID3_MASK 0x000000FFul /**< \brief (DSU_PID3) MASK Register */
Kojto 111:4336505e4b1c 441
Kojto 111:4336505e4b1c 442 /* -------- DSU_CID0 : (DSU Offset: 0x1FF0) (R/ 32) Component Identification 0 -------- */
Kojto 111:4336505e4b1c 443 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 444 typedef union {
Kojto 111:4336505e4b1c 445 struct {
Kojto 111:4336505e4b1c 446 uint32_t PREAMBLEB0:8; /*!< bit: 0.. 7 Preamble Byte 0 */
Kojto 111:4336505e4b1c 447 uint32_t :24; /*!< bit: 8..31 Reserved */
Kojto 111:4336505e4b1c 448 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 449 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 450 } DSU_CID0_Type;
Kojto 111:4336505e4b1c 451 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 452
Kojto 111:4336505e4b1c 453 #define DSU_CID0_OFFSET 0x1FF0 /**< \brief (DSU_CID0 offset) Component Identification 0 */
Kojto 111:4336505e4b1c 454 #define DSU_CID0_RESETVALUE 0x0000000Dul /**< \brief (DSU_CID0 reset_value) Component Identification 0 */
Kojto 111:4336505e4b1c 455
Kojto 111:4336505e4b1c 456 #define DSU_CID0_PREAMBLEB0_Pos 0 /**< \brief (DSU_CID0) Preamble Byte 0 */
Kojto 111:4336505e4b1c 457 #define DSU_CID0_PREAMBLEB0_Msk (0xFFul << DSU_CID0_PREAMBLEB0_Pos)
Kojto 111:4336505e4b1c 458 #define DSU_CID0_PREAMBLEB0(value) ((DSU_CID0_PREAMBLEB0_Msk & ((value) << DSU_CID0_PREAMBLEB0_Pos)))
Kojto 111:4336505e4b1c 459 #define DSU_CID0_MASK 0x000000FFul /**< \brief (DSU_CID0) MASK Register */
Kojto 111:4336505e4b1c 460
Kojto 111:4336505e4b1c 461 /* -------- DSU_CID1 : (DSU Offset: 0x1FF4) (R/ 32) Component Identification 1 -------- */
Kojto 111:4336505e4b1c 462 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 463 typedef union {
Kojto 111:4336505e4b1c 464 struct {
Kojto 111:4336505e4b1c 465 uint32_t PREAMBLE:4; /*!< bit: 0.. 3 Preamble */
Kojto 111:4336505e4b1c 466 uint32_t CCLASS:4; /*!< bit: 4.. 7 Component Class */
Kojto 111:4336505e4b1c 467 uint32_t :24; /*!< bit: 8..31 Reserved */
Kojto 111:4336505e4b1c 468 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 469 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 470 } DSU_CID1_Type;
Kojto 111:4336505e4b1c 471 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 472
Kojto 111:4336505e4b1c 473 #define DSU_CID1_OFFSET 0x1FF4 /**< \brief (DSU_CID1 offset) Component Identification 1 */
Kojto 111:4336505e4b1c 474 #define DSU_CID1_RESETVALUE 0x00000010ul /**< \brief (DSU_CID1 reset_value) Component Identification 1 */
Kojto 111:4336505e4b1c 475
Kojto 111:4336505e4b1c 476 #define DSU_CID1_PREAMBLE_Pos 0 /**< \brief (DSU_CID1) Preamble */
Kojto 111:4336505e4b1c 477 #define DSU_CID1_PREAMBLE_Msk (0xFul << DSU_CID1_PREAMBLE_Pos)
Kojto 111:4336505e4b1c 478 #define DSU_CID1_PREAMBLE(value) ((DSU_CID1_PREAMBLE_Msk & ((value) << DSU_CID1_PREAMBLE_Pos)))
Kojto 111:4336505e4b1c 479 #define DSU_CID1_CCLASS_Pos 4 /**< \brief (DSU_CID1) Component Class */
Kojto 111:4336505e4b1c 480 #define DSU_CID1_CCLASS_Msk (0xFul << DSU_CID1_CCLASS_Pos)
Kojto 111:4336505e4b1c 481 #define DSU_CID1_CCLASS(value) ((DSU_CID1_CCLASS_Msk & ((value) << DSU_CID1_CCLASS_Pos)))
Kojto 111:4336505e4b1c 482 #define DSU_CID1_MASK 0x000000FFul /**< \brief (DSU_CID1) MASK Register */
Kojto 111:4336505e4b1c 483
Kojto 111:4336505e4b1c 484 /* -------- DSU_CID2 : (DSU Offset: 0x1FF8) (R/ 32) Component Identification 2 -------- */
Kojto 111:4336505e4b1c 485 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 486 typedef union {
Kojto 111:4336505e4b1c 487 struct {
Kojto 111:4336505e4b1c 488 uint32_t PREAMBLEB2:8; /*!< bit: 0.. 7 Preamble Byte 2 */
Kojto 111:4336505e4b1c 489 uint32_t :24; /*!< bit: 8..31 Reserved */
Kojto 111:4336505e4b1c 490 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 491 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 492 } DSU_CID2_Type;
Kojto 111:4336505e4b1c 493 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 494
Kojto 111:4336505e4b1c 495 #define DSU_CID2_OFFSET 0x1FF8 /**< \brief (DSU_CID2 offset) Component Identification 2 */
Kojto 111:4336505e4b1c 496 #define DSU_CID2_RESETVALUE 0x00000005ul /**< \brief (DSU_CID2 reset_value) Component Identification 2 */
Kojto 111:4336505e4b1c 497
Kojto 111:4336505e4b1c 498 #define DSU_CID2_PREAMBLEB2_Pos 0 /**< \brief (DSU_CID2) Preamble Byte 2 */
Kojto 111:4336505e4b1c 499 #define DSU_CID2_PREAMBLEB2_Msk (0xFFul << DSU_CID2_PREAMBLEB2_Pos)
Kojto 111:4336505e4b1c 500 #define DSU_CID2_PREAMBLEB2(value) ((DSU_CID2_PREAMBLEB2_Msk & ((value) << DSU_CID2_PREAMBLEB2_Pos)))
Kojto 111:4336505e4b1c 501 #define DSU_CID2_MASK 0x000000FFul /**< \brief (DSU_CID2) MASK Register */
Kojto 111:4336505e4b1c 502
Kojto 111:4336505e4b1c 503 /* -------- DSU_CID3 : (DSU Offset: 0x1FFC) (R/ 32) Component Identification 3 -------- */
Kojto 111:4336505e4b1c 504 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 505 typedef union {
Kojto 111:4336505e4b1c 506 struct {
Kojto 111:4336505e4b1c 507 uint32_t PREAMBLEB3:8; /*!< bit: 0.. 7 Preamble Byte 3 */
Kojto 111:4336505e4b1c 508 uint32_t :24; /*!< bit: 8..31 Reserved */
Kojto 111:4336505e4b1c 509 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 510 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 511 } DSU_CID3_Type;
Kojto 111:4336505e4b1c 512 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 513
Kojto 111:4336505e4b1c 514 #define DSU_CID3_OFFSET 0x1FFC /**< \brief (DSU_CID3 offset) Component Identification 3 */
Kojto 111:4336505e4b1c 515 #define DSU_CID3_RESETVALUE 0x000000B1ul /**< \brief (DSU_CID3 reset_value) Component Identification 3 */
Kojto 111:4336505e4b1c 516
Kojto 111:4336505e4b1c 517 #define DSU_CID3_PREAMBLEB3_Pos 0 /**< \brief (DSU_CID3) Preamble Byte 3 */
Kojto 111:4336505e4b1c 518 #define DSU_CID3_PREAMBLEB3_Msk (0xFFul << DSU_CID3_PREAMBLEB3_Pos)
Kojto 111:4336505e4b1c 519 #define DSU_CID3_PREAMBLEB3(value) ((DSU_CID3_PREAMBLEB3_Msk & ((value) << DSU_CID3_PREAMBLEB3_Pos)))
Kojto 111:4336505e4b1c 520 #define DSU_CID3_MASK 0x000000FFul /**< \brief (DSU_CID3) MASK Register */
Kojto 111:4336505e4b1c 521
Kojto 111:4336505e4b1c 522 /** \brief DSU hardware registers */
Kojto 111:4336505e4b1c 523 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 524 typedef struct {
Kojto 111:4336505e4b1c 525 __O DSU_CTRL_Type CTRL; /**< \brief Offset: 0x0000 ( /W 8) Control */
Kojto 111:4336505e4b1c 526 __IO DSU_STATUSA_Type STATUSA; /**< \brief Offset: 0x0001 (R/W 8) Status A */
Kojto 111:4336505e4b1c 527 __I DSU_STATUSB_Type STATUSB; /**< \brief Offset: 0x0002 (R/ 8) Status B */
Kojto 111:4336505e4b1c 528 RoReg8 Reserved1[0x1];
Kojto 111:4336505e4b1c 529 __IO DSU_ADDR_Type ADDR; /**< \brief Offset: 0x0004 (R/W 32) Address */
Kojto 111:4336505e4b1c 530 __IO DSU_LENGTH_Type LENGTH; /**< \brief Offset: 0x0008 (R/W 32) Length */
Kojto 111:4336505e4b1c 531 __IO DSU_DATA_Type DATA; /**< \brief Offset: 0x000C (R/W 32) Data */
Kojto 111:4336505e4b1c 532 __IO DSU_DCC_Type DCC[2]; /**< \brief Offset: 0x0010 (R/W 32) Debug Communication Channel n */
Kojto 111:4336505e4b1c 533 __I DSU_DID_Type DID; /**< \brief Offset: 0x0018 (R/ 32) Device Identification */
Kojto 111:4336505e4b1c 534 RoReg8 Reserved2[0xFE4];
Kojto 111:4336505e4b1c 535 __I DSU_ENTRY_Type ENTRY[2]; /**< \brief Offset: 0x1000 (R/ 32) Coresight ROM Table Entry n */
Kojto 111:4336505e4b1c 536 __I DSU_END_Type END; /**< \brief Offset: 0x1008 (R/ 32) Coresight ROM Table End */
Kojto 111:4336505e4b1c 537 RoReg8 Reserved3[0xFC0];
Kojto 111:4336505e4b1c 538 __I DSU_MEMTYPE_Type MEMTYPE; /**< \brief Offset: 0x1FCC (R/ 32) Coresight ROM Table Memory Type */
Kojto 111:4336505e4b1c 539 __I DSU_PID4_Type PID4; /**< \brief Offset: 0x1FD0 (R/ 32) Peripheral Identification 4 */
Kojto 111:4336505e4b1c 540 RoReg8 Reserved4[0xC];
Kojto 111:4336505e4b1c 541 __I DSU_PID0_Type PID0; /**< \brief Offset: 0x1FE0 (R/ 32) Peripheral Identification 0 */
Kojto 111:4336505e4b1c 542 __I DSU_PID1_Type PID1; /**< \brief Offset: 0x1FE4 (R/ 32) Peripheral Identification 1 */
Kojto 111:4336505e4b1c 543 __I DSU_PID2_Type PID2; /**< \brief Offset: 0x1FE8 (R/ 32) Peripheral Identification 2 */
Kojto 111:4336505e4b1c 544 __I DSU_PID3_Type PID3; /**< \brief Offset: 0x1FEC (R/ 32) Peripheral Identification 3 */
Kojto 111:4336505e4b1c 545 __I DSU_CID0_Type CID0; /**< \brief Offset: 0x1FF0 (R/ 32) Component Identification 0 */
Kojto 111:4336505e4b1c 546 __I DSU_CID1_Type CID1; /**< \brief Offset: 0x1FF4 (R/ 32) Component Identification 1 */
Kojto 111:4336505e4b1c 547 __I DSU_CID2_Type CID2; /**< \brief Offset: 0x1FF8 (R/ 32) Component Identification 2 */
Kojto 111:4336505e4b1c 548 __I DSU_CID3_Type CID3; /**< \brief Offset: 0x1FFC (R/ 32) Component Identification 3 */
Kojto 111:4336505e4b1c 549 } Dsu;
Kojto 111:4336505e4b1c 550 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 551
Kojto 111:4336505e4b1c 552 /*@}*/
Kojto 111:4336505e4b1c 553
Kojto 111:4336505e4b1c 554 #endif /* _SAMD21_DSU_COMPONENT_ */