Elijah Orr
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TARGET_NUCLEO_F401RE/stm32f4xx_ll_fsmc.h@121:672067c3ada4, 2016-04-14 (annotated)
- Committer:
- elijahorr
- Date:
- Thu Apr 14 07:28:54 2016 +0000
- Revision:
- 121:672067c3ada4
- Parent:
- 110:165afa46840b
.
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| emilmont | 77:869cf507173a | 1 | /** |
| emilmont | 77:869cf507173a | 2 | ****************************************************************************** |
| emilmont | 77:869cf507173a | 3 | * @file stm32f4xx_ll_fsmc.h |
| emilmont | 77:869cf507173a | 4 | * @author MCD Application Team |
| Kojto | 110:165afa46840b | 5 | * @version V1.4.1 |
| Kojto | 110:165afa46840b | 6 | * @date 09-October-2015 |
| emilmont | 77:869cf507173a | 7 | * @brief Header file of FSMC HAL module. |
| emilmont | 77:869cf507173a | 8 | ****************************************************************************** |
| emilmont | 77:869cf507173a | 9 | * @attention |
| emilmont | 77:869cf507173a | 10 | * |
| Kojto | 99:dbbf35b96557 | 11 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> |
| emilmont | 77:869cf507173a | 12 | * |
| emilmont | 77:869cf507173a | 13 | * Redistribution and use in source and binary forms, with or without modification, |
| emilmont | 77:869cf507173a | 14 | * are permitted provided that the following conditions are met: |
| emilmont | 77:869cf507173a | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| emilmont | 77:869cf507173a | 16 | * this list of conditions and the following disclaimer. |
| emilmont | 77:869cf507173a | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| emilmont | 77:869cf507173a | 18 | * this list of conditions and the following disclaimer in the documentation |
| emilmont | 77:869cf507173a | 19 | * and/or other materials provided with the distribution. |
| emilmont | 77:869cf507173a | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| emilmont | 77:869cf507173a | 21 | * may be used to endorse or promote products derived from this software |
| emilmont | 77:869cf507173a | 22 | * without specific prior written permission. |
| emilmont | 77:869cf507173a | 23 | * |
| emilmont | 77:869cf507173a | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| emilmont | 77:869cf507173a | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| emilmont | 77:869cf507173a | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| emilmont | 77:869cf507173a | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| emilmont | 77:869cf507173a | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| emilmont | 77:869cf507173a | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| emilmont | 77:869cf507173a | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| emilmont | 77:869cf507173a | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| emilmont | 77:869cf507173a | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| emilmont | 77:869cf507173a | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| emilmont | 77:869cf507173a | 34 | * |
| emilmont | 77:869cf507173a | 35 | ****************************************************************************** |
| emilmont | 77:869cf507173a | 36 | */ |
| emilmont | 77:869cf507173a | 37 | |
| emilmont | 77:869cf507173a | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| emilmont | 77:869cf507173a | 39 | #ifndef __STM32F4xx_LL_FSMC_H |
| emilmont | 77:869cf507173a | 40 | #define __STM32F4xx_LL_FSMC_H |
| emilmont | 77:869cf507173a | 41 | |
| emilmont | 77:869cf507173a | 42 | #ifdef __cplusplus |
| emilmont | 77:869cf507173a | 43 | extern "C" { |
| emilmont | 77:869cf507173a | 44 | #endif |
| emilmont | 77:869cf507173a | 45 | |
| emilmont | 77:869cf507173a | 46 | /* Includes ------------------------------------------------------------------*/ |
| emilmont | 77:869cf507173a | 47 | #include "stm32f4xx_hal_def.h" |
| emilmont | 77:869cf507173a | 48 | |
| emilmont | 77:869cf507173a | 49 | /** @addtogroup STM32F4xx_HAL_Driver |
| emilmont | 77:869cf507173a | 50 | * @{ |
| emilmont | 77:869cf507173a | 51 | */ |
| Kojto | 99:dbbf35b96557 | 52 | |
| Kojto | 99:dbbf35b96557 | 53 | /** @addtogroup FSMC_LL |
| emilmont | 77:869cf507173a | 54 | * @{ |
| Kojto | 99:dbbf35b96557 | 55 | */ |
| emilmont | 77:869cf507173a | 56 | |
| Kojto | 110:165afa46840b | 57 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) |
| Kojto | 99:dbbf35b96557 | 58 | /* Private types -------------------------------------------------------------*/ |
| Kojto | 99:dbbf35b96557 | 59 | /** @defgroup FSMC_LL_Private_Types FSMC Private Types |
| Kojto | 99:dbbf35b96557 | 60 | * @{ |
| Kojto | 99:dbbf35b96557 | 61 | */ |
| emilmont | 77:869cf507173a | 62 | |
| emilmont | 77:869cf507173a | 63 | /** |
| Kojto | 99:dbbf35b96557 | 64 | * @brief FSMC NORSRAM Configuration Structure definition |
| emilmont | 77:869cf507173a | 65 | */ |
| emilmont | 77:869cf507173a | 66 | typedef struct |
| emilmont | 77:869cf507173a | 67 | { |
| emilmont | 77:869cf507173a | 68 | uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used. |
| bogdanm | 85:024bf7f99721 | 69 | This parameter can be a value of @ref FSMC_NORSRAM_Bank */ |
| bogdanm | 85:024bf7f99721 | 70 | |
| emilmont | 77:869cf507173a | 71 | uint32_t DataAddressMux; /*!< Specifies whether the address and data values are |
| emilmont | 77:869cf507173a | 72 | multiplexed on the data bus or not. |
| emilmont | 77:869cf507173a | 73 | This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */ |
| bogdanm | 85:024bf7f99721 | 74 | |
| emilmont | 77:869cf507173a | 75 | uint32_t MemoryType; /*!< Specifies the type of external memory attached to |
| emilmont | 77:869cf507173a | 76 | the corresponding memory device. |
| emilmont | 77:869cf507173a | 77 | This parameter can be a value of @ref FSMC_Memory_Type */ |
| bogdanm | 85:024bf7f99721 | 78 | |
| emilmont | 77:869cf507173a | 79 | uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. |
| emilmont | 77:869cf507173a | 80 | This parameter can be a value of @ref FSMC_NORSRAM_Data_Width */ |
| bogdanm | 85:024bf7f99721 | 81 | |
| emilmont | 77:869cf507173a | 82 | uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, |
| emilmont | 77:869cf507173a | 83 | valid only with synchronous burst Flash memories. |
| emilmont | 77:869cf507173a | 84 | This parameter can be a value of @ref FSMC_Burst_Access_Mode */ |
| bogdanm | 85:024bf7f99721 | 85 | |
| emilmont | 77:869cf507173a | 86 | uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing |
| emilmont | 77:869cf507173a | 87 | the Flash memory in burst mode. |
| emilmont | 77:869cf507173a | 88 | This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */ |
| bogdanm | 85:024bf7f99721 | 89 | |
| emilmont | 77:869cf507173a | 90 | uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash |
| emilmont | 77:869cf507173a | 91 | memory, valid only when accessing Flash memories in burst mode. |
| emilmont | 77:869cf507173a | 92 | This parameter can be a value of @ref FSMC_Wrap_Mode */ |
| bogdanm | 85:024bf7f99721 | 93 | |
| emilmont | 77:869cf507173a | 94 | uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one |
| emilmont | 77:869cf507173a | 95 | clock cycle before the wait state or during the wait state, |
| emilmont | 77:869cf507173a | 96 | valid only when accessing memories in burst mode. |
| emilmont | 77:869cf507173a | 97 | This parameter can be a value of @ref FSMC_Wait_Timing */ |
| bogdanm | 85:024bf7f99721 | 98 | |
| emilmont | 77:869cf507173a | 99 | uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FSMC. |
| emilmont | 77:869cf507173a | 100 | This parameter can be a value of @ref FSMC_Write_Operation */ |
| bogdanm | 85:024bf7f99721 | 101 | |
| emilmont | 77:869cf507173a | 102 | uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait |
| emilmont | 77:869cf507173a | 103 | signal, valid for Flash memory access in burst mode. |
| emilmont | 77:869cf507173a | 104 | This parameter can be a value of @ref FSMC_Wait_Signal */ |
| bogdanm | 85:024bf7f99721 | 105 | |
| emilmont | 77:869cf507173a | 106 | uint32_t ExtendedMode; /*!< Enables or disables the extended mode. |
| emilmont | 77:869cf507173a | 107 | This parameter can be a value of @ref FSMC_Extended_Mode */ |
| bogdanm | 85:024bf7f99721 | 108 | |
| emilmont | 77:869cf507173a | 109 | uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, |
| emilmont | 77:869cf507173a | 110 | valid only with asynchronous Flash memories. |
| emilmont | 77:869cf507173a | 111 | This parameter can be a value of @ref FSMC_AsynchronousWait */ |
| bogdanm | 85:024bf7f99721 | 112 | |
| emilmont | 77:869cf507173a | 113 | uint32_t WriteBurst; /*!< Enables or disables the write burst operation. |
| bogdanm | 85:024bf7f99721 | 114 | This parameter can be a value of @ref FSMC_Write_Burst */ |
| emilmont | 77:869cf507173a | 115 | |
| emilmont | 77:869cf507173a | 116 | }FSMC_NORSRAM_InitTypeDef; |
| emilmont | 77:869cf507173a | 117 | |
| emilmont | 77:869cf507173a | 118 | /** |
| Kojto | 99:dbbf35b96557 | 119 | * @brief FSMC NORSRAM Timing parameters structure definition |
| emilmont | 77:869cf507173a | 120 | */ |
| emilmont | 77:869cf507173a | 121 | typedef struct |
| emilmont | 77:869cf507173a | 122 | { |
| emilmont | 77:869cf507173a | 123 | uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure |
| emilmont | 77:869cf507173a | 124 | the duration of the address setup time. |
| emilmont | 77:869cf507173a | 125 | This parameter can be a value between Min_Data = 0 and Max_Data = 15. |
| emilmont | 77:869cf507173a | 126 | @note This parameter is not used with synchronous NOR Flash memories. */ |
| bogdanm | 85:024bf7f99721 | 127 | |
| emilmont | 77:869cf507173a | 128 | uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure |
| emilmont | 77:869cf507173a | 129 | the duration of the address hold time. |
| emilmont | 77:869cf507173a | 130 | This parameter can be a value between Min_Data = 1 and Max_Data = 15. |
| emilmont | 77:869cf507173a | 131 | @note This parameter is not used with synchronous NOR Flash memories. */ |
| bogdanm | 85:024bf7f99721 | 132 | |
| emilmont | 77:869cf507173a | 133 | uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure |
| emilmont | 77:869cf507173a | 134 | the duration of the data setup time. |
| emilmont | 77:869cf507173a | 135 | This parameter can be a value between Min_Data = 1 and Max_Data = 255. |
| emilmont | 77:869cf507173a | 136 | @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed |
| emilmont | 77:869cf507173a | 137 | NOR Flash memories. */ |
| bogdanm | 85:024bf7f99721 | 138 | |
| emilmont | 77:869cf507173a | 139 | uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure |
| emilmont | 77:869cf507173a | 140 | the duration of the bus turnaround. |
| emilmont | 77:869cf507173a | 141 | This parameter can be a value between Min_Data = 0 and Max_Data = 15. |
| emilmont | 77:869cf507173a | 142 | @note This parameter is only used for multiplexed NOR Flash memories. */ |
| bogdanm | 85:024bf7f99721 | 143 | |
| emilmont | 77:869cf507173a | 144 | uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of |
| emilmont | 77:869cf507173a | 145 | HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16. |
| emilmont | 77:869cf507173a | 146 | @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM |
| emilmont | 77:869cf507173a | 147 | accesses. */ |
| bogdanm | 85:024bf7f99721 | 148 | |
| emilmont | 77:869cf507173a | 149 | uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue |
| emilmont | 77:869cf507173a | 150 | to the memory before getting the first data. |
| emilmont | 77:869cf507173a | 151 | The parameter value depends on the memory type as shown below: |
| emilmont | 77:869cf507173a | 152 | - It must be set to 0 in case of a CRAM |
| emilmont | 77:869cf507173a | 153 | - It is don't care in asynchronous NOR, SRAM or ROM accesses |
| emilmont | 77:869cf507173a | 154 | - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories |
| emilmont | 77:869cf507173a | 155 | with synchronous burst mode enable */ |
| bogdanm | 85:024bf7f99721 | 156 | |
| emilmont | 77:869cf507173a | 157 | uint32_t AccessMode; /*!< Specifies the asynchronous access mode. |
| emilmont | 77:869cf507173a | 158 | This parameter can be a value of @ref FSMC_Access_Mode */ |
| bogdanm | 85:024bf7f99721 | 159 | |
| emilmont | 77:869cf507173a | 160 | }FSMC_NORSRAM_TimingTypeDef; |
| emilmont | 77:869cf507173a | 161 | |
| Kojto | 110:165afa46840b | 162 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) |
| emilmont | 77:869cf507173a | 163 | /** |
| Kojto | 99:dbbf35b96557 | 164 | * @brief FSMC NAND Configuration Structure definition |
| emilmont | 77:869cf507173a | 165 | */ |
| emilmont | 77:869cf507173a | 166 | typedef struct |
| emilmont | 77:869cf507173a | 167 | { |
| emilmont | 77:869cf507173a | 168 | uint32_t NandBank; /*!< Specifies the NAND memory device that will be used. |
| bogdanm | 85:024bf7f99721 | 169 | This parameter can be a value of @ref FSMC_NAND_Bank */ |
| bogdanm | 85:024bf7f99721 | 170 | |
| emilmont | 77:869cf507173a | 171 | uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device. |
| emilmont | 77:869cf507173a | 172 | This parameter can be any value of @ref FSMC_Wait_feature */ |
| bogdanm | 85:024bf7f99721 | 173 | |
| emilmont | 77:869cf507173a | 174 | uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. |
| emilmont | 77:869cf507173a | 175 | This parameter can be any value of @ref FSMC_NAND_Data_Width */ |
| bogdanm | 85:024bf7f99721 | 176 | |
| emilmont | 77:869cf507173a | 177 | uint32_t EccComputation; /*!< Enables or disables the ECC computation. |
| emilmont | 77:869cf507173a | 178 | This parameter can be any value of @ref FSMC_ECC */ |
| bogdanm | 85:024bf7f99721 | 179 | |
| emilmont | 77:869cf507173a | 180 | uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC. |
| emilmont | 77:869cf507173a | 181 | This parameter can be any value of @ref FSMC_ECC_Page_Size */ |
| bogdanm | 85:024bf7f99721 | 182 | |
| emilmont | 77:869cf507173a | 183 | uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the |
| emilmont | 77:869cf507173a | 184 | delay between CLE low and RE low. |
| emilmont | 77:869cf507173a | 185 | This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ |
| bogdanm | 85:024bf7f99721 | 186 | |
| emilmont | 77:869cf507173a | 187 | uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the |
| emilmont | 77:869cf507173a | 188 | delay between ALE low and RE low. |
| emilmont | 77:869cf507173a | 189 | This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ |
| bogdanm | 85:024bf7f99721 | 190 | |
| emilmont | 77:869cf507173a | 191 | }FSMC_NAND_InitTypeDef; |
| emilmont | 77:869cf507173a | 192 | |
| emilmont | 77:869cf507173a | 193 | /** |
| Kojto | 99:dbbf35b96557 | 194 | * @brief FSMC NAND/PCCARD Timing parameters structure definition |
| emilmont | 77:869cf507173a | 195 | */ |
| emilmont | 77:869cf507173a | 196 | typedef struct |
| emilmont | 77:869cf507173a | 197 | { |
| emilmont | 77:869cf507173a | 198 | uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before |
| emilmont | 77:869cf507173a | 199 | the command assertion for NAND-Flash read or write access |
| emilmont | 77:869cf507173a | 200 | to common/Attribute or I/O memory space (depending on |
| emilmont | 77:869cf507173a | 201 | the memory space timing to be configured). |
| emilmont | 77:869cf507173a | 202 | This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ |
| bogdanm | 85:024bf7f99721 | 203 | |
| emilmont | 77:869cf507173a | 204 | uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the |
| emilmont | 77:869cf507173a | 205 | command for NAND-Flash read or write access to |
| emilmont | 77:869cf507173a | 206 | common/Attribute or I/O memory space (depending on the |
| emilmont | 77:869cf507173a | 207 | memory space timing to be configured). |
| emilmont | 77:869cf507173a | 208 | This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ |
| bogdanm | 85:024bf7f99721 | 209 | |
| emilmont | 77:869cf507173a | 210 | uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address |
| emilmont | 77:869cf507173a | 211 | (and data for write access) after the command de-assertion |
| emilmont | 77:869cf507173a | 212 | for NAND-Flash read or write access to common/Attribute |
| emilmont | 77:869cf507173a | 213 | or I/O memory space (depending on the memory space timing |
| emilmont | 77:869cf507173a | 214 | to be configured). |
| emilmont | 77:869cf507173a | 215 | This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ |
| bogdanm | 85:024bf7f99721 | 216 | |
| emilmont | 77:869cf507173a | 217 | uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the |
| emilmont | 77:869cf507173a | 218 | data bus is kept in HiZ after the start of a NAND-Flash |
| emilmont | 77:869cf507173a | 219 | write access to common/Attribute or I/O memory space (depending |
| emilmont | 77:869cf507173a | 220 | on the memory space timing to be configured). |
| emilmont | 77:869cf507173a | 221 | This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ |
| bogdanm | 85:024bf7f99721 | 222 | |
| emilmont | 77:869cf507173a | 223 | }FSMC_NAND_PCC_TimingTypeDef; |
| emilmont | 77:869cf507173a | 224 | |
| emilmont | 77:869cf507173a | 225 | /** |
| Kojto | 99:dbbf35b96557 | 226 | * @brief FSMC NAND Configuration Structure definition |
| bogdanm | 85:024bf7f99721 | 227 | */ |
| emilmont | 77:869cf507173a | 228 | typedef struct |
| emilmont | 77:869cf507173a | 229 | { |
| emilmont | 77:869cf507173a | 230 | uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device. |
| emilmont | 77:869cf507173a | 231 | This parameter can be any value of @ref FSMC_Wait_feature */ |
| bogdanm | 85:024bf7f99721 | 232 | |
| emilmont | 77:869cf507173a | 233 | uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the |
| emilmont | 77:869cf507173a | 234 | delay between CLE low and RE low. |
| emilmont | 77:869cf507173a | 235 | This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ |
| bogdanm | 85:024bf7f99721 | 236 | |
| emilmont | 77:869cf507173a | 237 | uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the |
| emilmont | 77:869cf507173a | 238 | delay between ALE low and RE low. |
| emilmont | 77:869cf507173a | 239 | This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ |
| bogdanm | 85:024bf7f99721 | 240 | |
| bogdanm | 85:024bf7f99721 | 241 | }FSMC_PCCARD_InitTypeDef; |
| Kojto | 99:dbbf35b96557 | 242 | /** |
| Kojto | 99:dbbf35b96557 | 243 | * @} |
| Kojto | 99:dbbf35b96557 | 244 | */ |
| Kojto | 110:165afa46840b | 245 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ |
| emilmont | 77:869cf507173a | 246 | |
| Kojto | 99:dbbf35b96557 | 247 | /* Private constants ---------------------------------------------------------*/ |
| Kojto | 99:dbbf35b96557 | 248 | /** @defgroup FSMC_LL_Private_Constants FSMC Private Constants |
| Kojto | 99:dbbf35b96557 | 249 | * @{ |
| Kojto | 99:dbbf35b96557 | 250 | */ |
| emilmont | 77:869cf507173a | 251 | |
| Kojto | 99:dbbf35b96557 | 252 | /** @defgroup FSMC_LL_NOR_SRAM_Controller FSMC NOR/SRAM Controller |
| emilmont | 77:869cf507173a | 253 | * @{ |
| emilmont | 77:869cf507173a | 254 | */ |
| Kojto | 99:dbbf35b96557 | 255 | /** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank |
| emilmont | 77:869cf507173a | 256 | * @{ |
| emilmont | 77:869cf507173a | 257 | */ |
| emilmont | 77:869cf507173a | 258 | #define FSMC_NORSRAM_BANK1 ((uint32_t)0x00000000) |
| emilmont | 77:869cf507173a | 259 | #define FSMC_NORSRAM_BANK2 ((uint32_t)0x00000002) |
| emilmont | 77:869cf507173a | 260 | #define FSMC_NORSRAM_BANK3 ((uint32_t)0x00000004) |
| emilmont | 77:869cf507173a | 261 | #define FSMC_NORSRAM_BANK4 ((uint32_t)0x00000006) |
| emilmont | 77:869cf507173a | 262 | /** |
| emilmont | 77:869cf507173a | 263 | * @} |
| emilmont | 77:869cf507173a | 264 | */ |
| emilmont | 77:869cf507173a | 265 | |
| Kojto | 99:dbbf35b96557 | 266 | /** @defgroup FSMC_Data_Address_Bus_Multiplexing FSMC Data Address Bus Multiplexing |
| emilmont | 77:869cf507173a | 267 | * @{ |
| emilmont | 77:869cf507173a | 268 | */ |
| emilmont | 77:869cf507173a | 269 | #define FSMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000) |
| emilmont | 77:869cf507173a | 270 | #define FSMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002) |
| emilmont | 77:869cf507173a | 271 | /** |
| emilmont | 77:869cf507173a | 272 | * @} |
| emilmont | 77:869cf507173a | 273 | */ |
| emilmont | 77:869cf507173a | 274 | |
| Kojto | 99:dbbf35b96557 | 275 | /** @defgroup FSMC_Memory_Type FSMC Memory Type |
| emilmont | 77:869cf507173a | 276 | * @{ |
| emilmont | 77:869cf507173a | 277 | */ |
| emilmont | 77:869cf507173a | 278 | #define FSMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000) |
| emilmont | 77:869cf507173a | 279 | #define FSMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004) |
| emilmont | 77:869cf507173a | 280 | #define FSMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008) |
| emilmont | 77:869cf507173a | 281 | /** |
| emilmont | 77:869cf507173a | 282 | * @} |
| emilmont | 77:869cf507173a | 283 | */ |
| emilmont | 77:869cf507173a | 284 | |
| Kojto | 99:dbbf35b96557 | 285 | /** @defgroup FSMC_NORSRAM_Data_Width FSMC NOR/SRAM Data Width |
| emilmont | 77:869cf507173a | 286 | * @{ |
| emilmont | 77:869cf507173a | 287 | */ |
| emilmont | 77:869cf507173a | 288 | #define FSMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000) |
| emilmont | 77:869cf507173a | 289 | #define FSMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010) |
| emilmont | 77:869cf507173a | 290 | #define FSMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020) |
| emilmont | 77:869cf507173a | 291 | /** |
| emilmont | 77:869cf507173a | 292 | * @} |
| emilmont | 77:869cf507173a | 293 | */ |
| emilmont | 77:869cf507173a | 294 | |
| Kojto | 99:dbbf35b96557 | 295 | /** @defgroup FSMC_NORSRAM_Flash_Access FSMC NOR/SRAM Flash Access |
| emilmont | 77:869cf507173a | 296 | * @{ |
| emilmont | 77:869cf507173a | 297 | */ |
| emilmont | 77:869cf507173a | 298 | #define FSMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040) |
| emilmont | 77:869cf507173a | 299 | #define FSMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000) |
| emilmont | 77:869cf507173a | 300 | /** |
| emilmont | 77:869cf507173a | 301 | * @} |
| emilmont | 77:869cf507173a | 302 | */ |
| emilmont | 77:869cf507173a | 303 | |
| Kojto | 99:dbbf35b96557 | 304 | /** @defgroup FSMC_Burst_Access_Mode FSMC Burst Access Mode |
| emilmont | 77:869cf507173a | 305 | * @{ |
| emilmont | 77:869cf507173a | 306 | */ |
| emilmont | 77:869cf507173a | 307 | #define FSMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000) |
| emilmont | 77:869cf507173a | 308 | #define FSMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100) |
| emilmont | 77:869cf507173a | 309 | /** |
| emilmont | 77:869cf507173a | 310 | * @} |
| emilmont | 77:869cf507173a | 311 | */ |
| emilmont | 77:869cf507173a | 312 | |
| Kojto | 99:dbbf35b96557 | 313 | /** @defgroup FSMC_Wait_Signal_Polarity FSMC Wait Signal Polarity |
| emilmont | 77:869cf507173a | 314 | * @{ |
| emilmont | 77:869cf507173a | 315 | */ |
| emilmont | 77:869cf507173a | 316 | #define FSMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000) |
| emilmont | 77:869cf507173a | 317 | #define FSMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200) |
| emilmont | 77:869cf507173a | 318 | /** |
| emilmont | 77:869cf507173a | 319 | * @} |
| emilmont | 77:869cf507173a | 320 | */ |
| emilmont | 77:869cf507173a | 321 | |
| Kojto | 99:dbbf35b96557 | 322 | /** @defgroup FSMC_Wrap_Mode FSMC Wrap Mode |
| Kojto | 99:dbbf35b96557 | 323 | * @{ |
| Kojto | 99:dbbf35b96557 | 324 | */ |
| Kojto | 99:dbbf35b96557 | 325 | #define FSMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000) |
| Kojto | 99:dbbf35b96557 | 326 | #define FSMC_WRAP_MODE_ENABLE ((uint32_t)0x00000400) |
| Kojto | 99:dbbf35b96557 | 327 | /** |
| Kojto | 99:dbbf35b96557 | 328 | * @} |
| Kojto | 99:dbbf35b96557 | 329 | */ |
| Kojto | 99:dbbf35b96557 | 330 | |
| Kojto | 99:dbbf35b96557 | 331 | /** @defgroup FSMC_Wait_Timing FSMC Wait Timing |
| emilmont | 77:869cf507173a | 332 | * @{ |
| emilmont | 77:869cf507173a | 333 | */ |
| emilmont | 77:869cf507173a | 334 | #define FSMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000) |
| emilmont | 77:869cf507173a | 335 | #define FSMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800) |
| emilmont | 77:869cf507173a | 336 | /** |
| emilmont | 77:869cf507173a | 337 | * @} |
| emilmont | 77:869cf507173a | 338 | */ |
| emilmont | 77:869cf507173a | 339 | |
| Kojto | 99:dbbf35b96557 | 340 | /** @defgroup FSMC_Write_Operation FSMC Write Operation |
| emilmont | 77:869cf507173a | 341 | * @{ |
| emilmont | 77:869cf507173a | 342 | */ |
| emilmont | 77:869cf507173a | 343 | #define FSMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000) |
| emilmont | 77:869cf507173a | 344 | #define FSMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000) |
| emilmont | 77:869cf507173a | 345 | /** |
| emilmont | 77:869cf507173a | 346 | * @} |
| emilmont | 77:869cf507173a | 347 | */ |
| emilmont | 77:869cf507173a | 348 | |
| Kojto | 99:dbbf35b96557 | 349 | /** @defgroup FSMC_Wait_Signal FSMC Wait Signal |
| Kojto | 99:dbbf35b96557 | 350 | * @{ |
| Kojto | 99:dbbf35b96557 | 351 | */ |
| Kojto | 99:dbbf35b96557 | 352 | #define FSMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000) |
| Kojto | 99:dbbf35b96557 | 353 | #define FSMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000) |
| Kojto | 99:dbbf35b96557 | 354 | /** |
| Kojto | 99:dbbf35b96557 | 355 | * @} |
| Kojto | 99:dbbf35b96557 | 356 | */ |
| Kojto | 99:dbbf35b96557 | 357 | |
| Kojto | 99:dbbf35b96557 | 358 | /** @defgroup FSMC_Extended_Mode FSMC Extended Mode |
| Kojto | 99:dbbf35b96557 | 359 | * @{ |
| Kojto | 99:dbbf35b96557 | 360 | */ |
| Kojto | 99:dbbf35b96557 | 361 | #define FSMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000) |
| Kojto | 99:dbbf35b96557 | 362 | #define FSMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000) |
| Kojto | 99:dbbf35b96557 | 363 | /** |
| Kojto | 99:dbbf35b96557 | 364 | * @} |
| Kojto | 99:dbbf35b96557 | 365 | */ |
| Kojto | 99:dbbf35b96557 | 366 | |
| Kojto | 99:dbbf35b96557 | 367 | /** @defgroup FSMC_AsynchronousWait FSMC Asynchronous Wait |
| emilmont | 77:869cf507173a | 368 | * @{ |
| emilmont | 77:869cf507173a | 369 | */ |
| emilmont | 77:869cf507173a | 370 | #define FSMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000) |
| emilmont | 77:869cf507173a | 371 | #define FSMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000) |
| emilmont | 77:869cf507173a | 372 | /** |
| emilmont | 77:869cf507173a | 373 | * @} |
| emilmont | 77:869cf507173a | 374 | */ |
| emilmont | 77:869cf507173a | 375 | |
| Kojto | 99:dbbf35b96557 | 376 | /** @defgroup FSMC_Write_Burst FSMC Write Burst |
| emilmont | 77:869cf507173a | 377 | * @{ |
| emilmont | 77:869cf507173a | 378 | */ |
| emilmont | 77:869cf507173a | 379 | #define FSMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000) |
| emilmont | 77:869cf507173a | 380 | #define FSMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000) |
| emilmont | 77:869cf507173a | 381 | /** |
| emilmont | 77:869cf507173a | 382 | * @} |
| emilmont | 77:869cf507173a | 383 | */ |
| emilmont | 77:869cf507173a | 384 | |
| Kojto | 99:dbbf35b96557 | 385 | /** @defgroup FSMC_Continous_Clock FSMC Continous Clock |
| emilmont | 77:869cf507173a | 386 | * @{ |
| emilmont | 77:869cf507173a | 387 | */ |
| Kojto | 99:dbbf35b96557 | 388 | #define FSMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000) |
| Kojto | 99:dbbf35b96557 | 389 | #define FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000) |
| emilmont | 77:869cf507173a | 390 | /** |
| emilmont | 77:869cf507173a | 391 | * @} |
| emilmont | 77:869cf507173a | 392 | */ |
| emilmont | 77:869cf507173a | 393 | |
| Kojto | 99:dbbf35b96557 | 394 | /** @defgroup FSMC_Access_Mode FSMC Access Mode |
| emilmont | 77:869cf507173a | 395 | * @{ |
| emilmont | 77:869cf507173a | 396 | */ |
| emilmont | 77:869cf507173a | 397 | #define FSMC_ACCESS_MODE_A ((uint32_t)0x00000000) |
| emilmont | 77:869cf507173a | 398 | #define FSMC_ACCESS_MODE_B ((uint32_t)0x10000000) |
| emilmont | 77:869cf507173a | 399 | #define FSMC_ACCESS_MODE_C ((uint32_t)0x20000000) |
| emilmont | 77:869cf507173a | 400 | #define FSMC_ACCESS_MODE_D ((uint32_t)0x30000000) |
| emilmont | 77:869cf507173a | 401 | /** |
| emilmont | 77:869cf507173a | 402 | * @} |
| emilmont | 77:869cf507173a | 403 | */ |
| emilmont | 77:869cf507173a | 404 | /** |
| emilmont | 77:869cf507173a | 405 | * @} |
| emilmont | 77:869cf507173a | 406 | */ |
| emilmont | 77:869cf507173a | 407 | |
| Kojto | 110:165afa46840b | 408 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) |
| Kojto | 99:dbbf35b96557 | 409 | /** @defgroup FSMC_LL_NAND_Controller FSMC NAND and PCCARD Controller |
| Kojto | 99:dbbf35b96557 | 410 | * @{ |
| Kojto | 99:dbbf35b96557 | 411 | */ |
| Kojto | 99:dbbf35b96557 | 412 | /** @defgroup FSMC_NAND_Bank FSMC NAND Bank |
| Kojto | 99:dbbf35b96557 | 413 | * @{ |
| Kojto | 99:dbbf35b96557 | 414 | */ |
| Kojto | 99:dbbf35b96557 | 415 | #define FSMC_NAND_BANK2 ((uint32_t)0x00000010) |
| Kojto | 99:dbbf35b96557 | 416 | #define FSMC_NAND_BANK3 ((uint32_t)0x00000100) |
| Kojto | 99:dbbf35b96557 | 417 | /** |
| Kojto | 99:dbbf35b96557 | 418 | * @} |
| Kojto | 99:dbbf35b96557 | 419 | */ |
| Kojto | 99:dbbf35b96557 | 420 | |
| Kojto | 99:dbbf35b96557 | 421 | /** @defgroup FSMC_Wait_feature FSMC Wait feature |
| emilmont | 77:869cf507173a | 422 | * @{ |
| emilmont | 77:869cf507173a | 423 | */ |
| emilmont | 77:869cf507173a | 424 | #define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000) |
| emilmont | 77:869cf507173a | 425 | #define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002) |
| emilmont | 77:869cf507173a | 426 | /** |
| emilmont | 77:869cf507173a | 427 | * @} |
| emilmont | 77:869cf507173a | 428 | */ |
| emilmont | 77:869cf507173a | 429 | |
| Kojto | 99:dbbf35b96557 | 430 | /** @defgroup FSMC_PCR_Memory_Type FSMC PCR Memory Type |
| emilmont | 77:869cf507173a | 431 | * @{ |
| emilmont | 77:869cf507173a | 432 | */ |
| emilmont | 77:869cf507173a | 433 | #define FSMC_PCR_MEMORY_TYPE_PCCARD ((uint32_t)0x00000000) |
| emilmont | 77:869cf507173a | 434 | #define FSMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008) |
| emilmont | 77:869cf507173a | 435 | /** |
| emilmont | 77:869cf507173a | 436 | * @} |
| emilmont | 77:869cf507173a | 437 | */ |
| emilmont | 77:869cf507173a | 438 | |
| Kojto | 99:dbbf35b96557 | 439 | /** @defgroup FSMC_NAND_Data_Width FSMC NAND Data Width |
| emilmont | 77:869cf507173a | 440 | * @{ |
| emilmont | 77:869cf507173a | 441 | */ |
| emilmont | 77:869cf507173a | 442 | #define FSMC_NAND_PCC_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000) |
| emilmont | 77:869cf507173a | 443 | #define FSMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010) |
| emilmont | 77:869cf507173a | 444 | /** |
| emilmont | 77:869cf507173a | 445 | * @} |
| emilmont | 77:869cf507173a | 446 | */ |
| emilmont | 77:869cf507173a | 447 | |
| Kojto | 99:dbbf35b96557 | 448 | /** @defgroup FSMC_ECC FSMC ECC |
| emilmont | 77:869cf507173a | 449 | * @{ |
| emilmont | 77:869cf507173a | 450 | */ |
| emilmont | 77:869cf507173a | 451 | #define FSMC_NAND_ECC_DISABLE ((uint32_t)0x00000000) |
| emilmont | 77:869cf507173a | 452 | #define FSMC_NAND_ECC_ENABLE ((uint32_t)0x00000040) |
| emilmont | 77:869cf507173a | 453 | /** |
| emilmont | 77:869cf507173a | 454 | * @} |
| emilmont | 77:869cf507173a | 455 | */ |
| emilmont | 77:869cf507173a | 456 | |
| Kojto | 99:dbbf35b96557 | 457 | /** @defgroup FSMC_ECC_Page_Size FSMC ECC Page Size |
| emilmont | 77:869cf507173a | 458 | * @{ |
| emilmont | 77:869cf507173a | 459 | */ |
| emilmont | 77:869cf507173a | 460 | #define FSMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000) |
| emilmont | 77:869cf507173a | 461 | #define FSMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000) |
| emilmont | 77:869cf507173a | 462 | #define FSMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000) |
| emilmont | 77:869cf507173a | 463 | #define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000) |
| emilmont | 77:869cf507173a | 464 | #define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000) |
| emilmont | 77:869cf507173a | 465 | #define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000) |
| emilmont | 77:869cf507173a | 466 | /** |
| emilmont | 77:869cf507173a | 467 | * @} |
| emilmont | 77:869cf507173a | 468 | */ |
| emilmont | 77:869cf507173a | 469 | /** |
| emilmont | 77:869cf507173a | 470 | * @} |
| emilmont | 77:869cf507173a | 471 | */ |
| Kojto | 110:165afa46840b | 472 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ |
| Kojto | 110:165afa46840b | 473 | |
| Kojto | 99:dbbf35b96557 | 474 | /** @defgroup FSMC_LL_Interrupt_definition FSMC Interrupt definition |
| emilmont | 77:869cf507173a | 475 | * @{ |
| emilmont | 77:869cf507173a | 476 | */ |
| emilmont | 77:869cf507173a | 477 | #define FSMC_IT_RISING_EDGE ((uint32_t)0x00000008) |
| emilmont | 77:869cf507173a | 478 | #define FSMC_IT_LEVEL ((uint32_t)0x00000010) |
| emilmont | 77:869cf507173a | 479 | #define FSMC_IT_FALLING_EDGE ((uint32_t)0x00000020) |
| emilmont | 77:869cf507173a | 480 | #define FSMC_IT_REFRESH_ERROR ((uint32_t)0x00004000) |
| emilmont | 77:869cf507173a | 481 | /** |
| emilmont | 77:869cf507173a | 482 | * @} |
| emilmont | 77:869cf507173a | 483 | */ |
| emilmont | 77:869cf507173a | 484 | |
| Kojto | 99:dbbf35b96557 | 485 | /** @defgroup FSMC_LL_Flag_definition FSMC Flag definition |
| emilmont | 77:869cf507173a | 486 | * @{ |
| emilmont | 77:869cf507173a | 487 | */ |
| emilmont | 77:869cf507173a | 488 | #define FSMC_FLAG_RISING_EDGE ((uint32_t)0x00000001) |
| emilmont | 77:869cf507173a | 489 | #define FSMC_FLAG_LEVEL ((uint32_t)0x00000002) |
| emilmont | 77:869cf507173a | 490 | #define FSMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004) |
| emilmont | 77:869cf507173a | 491 | #define FSMC_FLAG_FEMPT ((uint32_t)0x00000040) |
| emilmont | 77:869cf507173a | 492 | /** |
| emilmont | 77:869cf507173a | 493 | * @} |
| emilmont | 77:869cf507173a | 494 | */ |
| emilmont | 77:869cf507173a | 495 | |
| Kojto | 99:dbbf35b96557 | 496 | /** @defgroup FSMC_LL_Alias_definition FSMC Alias definition |
| Kojto | 99:dbbf35b96557 | 497 | * @{ |
| emilmont | 77:869cf507173a | 498 | */ |
| Kojto | 99:dbbf35b96557 | 499 | #define FSMC_NORSRAM_TypeDef FSMC_Bank1_TypeDef |
| Kojto | 99:dbbf35b96557 | 500 | #define FSMC_NORSRAM_EXTENDED_TypeDef FSMC_Bank1E_TypeDef |
| Kojto | 110:165afa46840b | 501 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) |
| Kojto | 99:dbbf35b96557 | 502 | #define FSMC_NAND_TypeDef FSMC_Bank2_3_TypeDef |
| Kojto | 99:dbbf35b96557 | 503 | #define FSMC_PCCARD_TypeDef FSMC_Bank4_TypeDef |
| Kojto | 110:165afa46840b | 504 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ |
| emilmont | 77:869cf507173a | 505 | |
| Kojto | 99:dbbf35b96557 | 506 | #define FSMC_NORSRAM_DEVICE FSMC_Bank1 |
| Kojto | 99:dbbf35b96557 | 507 | #define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E |
| Kojto | 110:165afa46840b | 508 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) |
| Kojto | 99:dbbf35b96557 | 509 | #define FSMC_NAND_DEVICE FSMC_Bank2_3 |
| Kojto | 99:dbbf35b96557 | 510 | #define FSMC_PCCARD_DEVICE FSMC_Bank4 |
| Kojto | 110:165afa46840b | 511 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ |
| emilmont | 77:869cf507173a | 512 | |
| emilmont | 77:869cf507173a | 513 | #define FMC_NORSRAM_TypeDef FSMC_NORSRAM_TypeDef |
| emilmont | 77:869cf507173a | 514 | #define FMC_NORSRAM_EXTENDED_TypeDef FSMC_NORSRAM_EXTENDED_TypeDef |
| emilmont | 77:869cf507173a | 515 | #define FMC_NORSRAM_InitTypeDef FSMC_NORSRAM_InitTypeDef |
| emilmont | 77:869cf507173a | 516 | #define FMC_NORSRAM_TimingTypeDef FSMC_NORSRAM_TimingTypeDef |
| emilmont | 77:869cf507173a | 517 | |
| emilmont | 77:869cf507173a | 518 | #define FMC_NORSRAM_Init FSMC_NORSRAM_Init |
| emilmont | 77:869cf507173a | 519 | #define FMC_NORSRAM_Timing_Init FSMC_NORSRAM_Timing_Init |
| emilmont | 77:869cf507173a | 520 | #define FMC_NORSRAM_Extended_Timing_Init FSMC_NORSRAM_Extended_Timing_Init |
| emilmont | 77:869cf507173a | 521 | #define FMC_NORSRAM_DeInit FSMC_NORSRAM_DeInit |
| emilmont | 77:869cf507173a | 522 | #define FMC_NORSRAM_WriteOperation_Enable FSMC_NORSRAM_WriteOperation_Enable |
| emilmont | 77:869cf507173a | 523 | #define FMC_NORSRAM_WriteOperation_Disable FSMC_NORSRAM_WriteOperation_Disable |
| emilmont | 77:869cf507173a | 524 | |
| emilmont | 77:869cf507173a | 525 | #define __FMC_NORSRAM_ENABLE __FSMC_NORSRAM_ENABLE |
| emilmont | 77:869cf507173a | 526 | #define __FMC_NORSRAM_DISABLE __FSMC_NORSRAM_DISABLE |
| emilmont | 77:869cf507173a | 527 | |
| Kojto | 110:165afa46840b | 528 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) |
| emilmont | 77:869cf507173a | 529 | #define FMC_NAND_InitTypeDef FSMC_NAND_InitTypeDef |
| emilmont | 77:869cf507173a | 530 | #define FMC_PCCARD_InitTypeDef FSMC_PCCARD_InitTypeDef |
| emilmont | 77:869cf507173a | 531 | #define FMC_NAND_PCC_TimingTypeDef FSMC_NAND_PCC_TimingTypeDef |
| emilmont | 77:869cf507173a | 532 | |
| emilmont | 77:869cf507173a | 533 | #define FMC_NAND_Init FSMC_NAND_Init |
| emilmont | 77:869cf507173a | 534 | #define FMC_NAND_CommonSpace_Timing_Init FSMC_NAND_CommonSpace_Timing_Init |
| emilmont | 77:869cf507173a | 535 | #define FMC_NAND_AttributeSpace_Timing_Init FSMC_NAND_AttributeSpace_Timing_Init |
| emilmont | 77:869cf507173a | 536 | #define FMC_NAND_DeInit FSMC_NAND_DeInit |
| emilmont | 77:869cf507173a | 537 | #define FMC_NAND_ECC_Enable FSMC_NAND_ECC_Enable |
| emilmont | 77:869cf507173a | 538 | #define FMC_NAND_ECC_Disable FSMC_NAND_ECC_Disable |
| emilmont | 77:869cf507173a | 539 | #define FMC_NAND_GetECC FSMC_NAND_GetECC |
| emilmont | 77:869cf507173a | 540 | #define FMC_PCCARD_Init FSMC_PCCARD_Init |
| emilmont | 77:869cf507173a | 541 | #define FMC_PCCARD_CommonSpace_Timing_Init FSMC_PCCARD_CommonSpace_Timing_Init |
| emilmont | 77:869cf507173a | 542 | #define FMC_PCCARD_AttributeSpace_Timing_Init FSMC_PCCARD_AttributeSpace_Timing_Init |
| emilmont | 77:869cf507173a | 543 | #define FMC_PCCARD_IOSpace_Timing_Init FSMC_PCCARD_IOSpace_Timing_Init |
| emilmont | 77:869cf507173a | 544 | #define FMC_PCCARD_DeInit FSMC_PCCARD_DeInit |
| emilmont | 77:869cf507173a | 545 | |
| emilmont | 77:869cf507173a | 546 | #define __FMC_NAND_ENABLE __FSMC_NAND_ENABLE |
| emilmont | 77:869cf507173a | 547 | #define __FMC_NAND_DISABLE __FSMC_NAND_DISABLE |
| emilmont | 77:869cf507173a | 548 | #define __FMC_PCCARD_ENABLE __FSMC_PCCARD_ENABLE |
| emilmont | 77:869cf507173a | 549 | #define __FMC_PCCARD_DISABLE __FSMC_PCCARD_DISABLE |
| emilmont | 77:869cf507173a | 550 | #define __FMC_NAND_ENABLE_IT __FSMC_NAND_ENABLE_IT |
| emilmont | 77:869cf507173a | 551 | #define __FMC_NAND_DISABLE_IT __FSMC_NAND_DISABLE_IT |
| emilmont | 77:869cf507173a | 552 | #define __FMC_NAND_GET_FLAG __FSMC_NAND_GET_FLAG |
| emilmont | 77:869cf507173a | 553 | #define __FMC_NAND_CLEAR_FLAG __FSMC_NAND_CLEAR_FLAG |
| emilmont | 77:869cf507173a | 554 | #define __FMC_PCCARD_ENABLE_IT __FSMC_PCCARD_ENABLE_IT |
| emilmont | 77:869cf507173a | 555 | #define __FMC_PCCARD_DISABLE_IT __FSMC_PCCARD_DISABLE_IT |
| emilmont | 77:869cf507173a | 556 | #define __FMC_PCCARD_GET_FLAG __FSMC_PCCARD_GET_FLAG |
| emilmont | 77:869cf507173a | 557 | #define __FMC_PCCARD_CLEAR_FLAG __FSMC_PCCARD_CLEAR_FLAG |
| Kojto | 110:165afa46840b | 558 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ |
| emilmont | 77:869cf507173a | 559 | |
| emilmont | 77:869cf507173a | 560 | #define FMC_NORSRAM_TypeDef FSMC_NORSRAM_TypeDef |
| emilmont | 77:869cf507173a | 561 | #define FMC_NORSRAM_EXTENDED_TypeDef FSMC_NORSRAM_EXTENDED_TypeDef |
| Kojto | 110:165afa46840b | 562 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) |
| emilmont | 77:869cf507173a | 563 | #define FMC_NAND_TypeDef FSMC_NAND_TypeDef |
| emilmont | 77:869cf507173a | 564 | #define FMC_PCCARD_TypeDef FSMC_PCCARD_TypeDef |
| Kojto | 110:165afa46840b | 565 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ |
| emilmont | 77:869cf507173a | 566 | |
| emilmont | 77:869cf507173a | 567 | #define FMC_NORSRAM_DEVICE FSMC_NORSRAM_DEVICE |
| Kojto | 110:165afa46840b | 568 | #define FMC_NORSRAM_EXTENDED_DEVICE FSMC_NORSRAM_EXTENDED_DEVICE |
| Kojto | 110:165afa46840b | 569 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) |
| emilmont | 77:869cf507173a | 570 | #define FMC_NAND_DEVICE FSMC_NAND_DEVICE |
| emilmont | 77:869cf507173a | 571 | #define FMC_PCCARD_DEVICE FSMC_PCCARD_DEVICE |
| emilmont | 77:869cf507173a | 572 | |
| emilmont | 77:869cf507173a | 573 | #define FMC_NAND_BANK2 FSMC_NAND_BANK2 |
| Kojto | 110:165afa46840b | 574 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ |
| emilmont | 77:869cf507173a | 575 | |
| Kojto | 90:cb3d968589d8 | 576 | #define FMC_NORSRAM_BANK1 FSMC_NORSRAM_BANK1 |
| Kojto | 90:cb3d968589d8 | 577 | #define FMC_NORSRAM_BANK2 FSMC_NORSRAM_BANK2 |
| Kojto | 90:cb3d968589d8 | 578 | #define FMC_NORSRAM_BANK3 FSMC_NORSRAM_BANK3 |
| Kojto | 90:cb3d968589d8 | 579 | |
| emilmont | 77:869cf507173a | 580 | #define FMC_IT_RISING_EDGE FSMC_IT_RISING_EDGE |
| emilmont | 77:869cf507173a | 581 | #define FMC_IT_LEVEL FSMC_IT_LEVEL |
| emilmont | 77:869cf507173a | 582 | #define FMC_IT_FALLING_EDGE FSMC_IT_FALLING_EDGE |
| emilmont | 77:869cf507173a | 583 | #define FMC_IT_REFRESH_ERROR FSMC_IT_REFRESH_ERROR |
| emilmont | 77:869cf507173a | 584 | |
| emilmont | 77:869cf507173a | 585 | #define FMC_FLAG_RISING_EDGE FSMC_FLAG_RISING_EDGE |
| emilmont | 77:869cf507173a | 586 | #define FMC_FLAG_LEVEL FSMC_FLAG_LEVEL |
| emilmont | 77:869cf507173a | 587 | #define FMC_FLAG_FALLING_EDGE FSMC_FLAG_FALLING_EDGE |
| emilmont | 77:869cf507173a | 588 | #define FMC_FLAG_FEMPT FSMC_FLAG_FEMPT |
| Kojto | 99:dbbf35b96557 | 589 | /** |
| Kojto | 99:dbbf35b96557 | 590 | * @} |
| Kojto | 99:dbbf35b96557 | 591 | */ |
| emilmont | 77:869cf507173a | 592 | |
| Kojto | 99:dbbf35b96557 | 593 | /** |
| Kojto | 99:dbbf35b96557 | 594 | * @} |
| Kojto | 99:dbbf35b96557 | 595 | */ |
| Kojto | 99:dbbf35b96557 | 596 | |
| Kojto | 99:dbbf35b96557 | 597 | /* Private macro -------------------------------------------------------------*/ |
| Kojto | 99:dbbf35b96557 | 598 | /** @defgroup FSMC_LL_Private_Macros FSMC Private Macros |
| Kojto | 99:dbbf35b96557 | 599 | * @{ |
| Kojto | 99:dbbf35b96557 | 600 | */ |
| Kojto | 99:dbbf35b96557 | 601 | |
| Kojto | 99:dbbf35b96557 | 602 | /** @defgroup FSMC_LL_NOR_Macros FSMC NOR/SRAM Exported Macros |
| Kojto | 99:dbbf35b96557 | 603 | * @brief macros to handle NOR device enable/disable and read/write operations |
| Kojto | 99:dbbf35b96557 | 604 | * @{ |
| Kojto | 99:dbbf35b96557 | 605 | */ |
| Kojto | 99:dbbf35b96557 | 606 | /** |
| Kojto | 99:dbbf35b96557 | 607 | * @brief Enable the NORSRAM device access. |
| Kojto | 99:dbbf35b96557 | 608 | * @param __INSTANCE__: FSMC_NORSRAM Instance |
| Kojto | 99:dbbf35b96557 | 609 | * @param __BANK__: FSMC_NORSRAM Bank |
| Kojto | 99:dbbf35b96557 | 610 | * @retval none |
| Kojto | 99:dbbf35b96557 | 611 | */ |
| Kojto | 99:dbbf35b96557 | 612 | #define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FSMC_BCR1_MBKEN) |
| Kojto | 99:dbbf35b96557 | 613 | |
| Kojto | 99:dbbf35b96557 | 614 | /** |
| Kojto | 99:dbbf35b96557 | 615 | * @brief Disable the NORSRAM device access. |
| Kojto | 99:dbbf35b96557 | 616 | * @param __INSTANCE__: FSMC_NORSRAM Instance |
| Kojto | 99:dbbf35b96557 | 617 | * @param __BANK__: FSMC_NORSRAM Bank |
| Kojto | 99:dbbf35b96557 | 618 | * @retval none |
| Kojto | 99:dbbf35b96557 | 619 | */ |
| Kojto | 99:dbbf35b96557 | 620 | #define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FSMC_BCR1_MBKEN) |
| Kojto | 99:dbbf35b96557 | 621 | /** |
| Kojto | 99:dbbf35b96557 | 622 | * @} |
| Kojto | 99:dbbf35b96557 | 623 | */ |
| Kojto | 99:dbbf35b96557 | 624 | |
| Kojto | 99:dbbf35b96557 | 625 | /** @defgroup FSMC_LL_NAND_Macros FSMC NAND Macros |
| Kojto | 99:dbbf35b96557 | 626 | * @brief macros to handle NAND device enable/disable |
| Kojto | 99:dbbf35b96557 | 627 | * @{ |
| Kojto | 99:dbbf35b96557 | 628 | */ |
| Kojto | 110:165afa46840b | 629 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) |
| Kojto | 99:dbbf35b96557 | 630 | /** |
| Kojto | 99:dbbf35b96557 | 631 | * @brief Enable the NAND device access. |
| Kojto | 99:dbbf35b96557 | 632 | * @param __INSTANCE__: FSMC_NAND Instance |
| Kojto | 99:dbbf35b96557 | 633 | * @param __BANK__: FSMC_NAND Bank |
| Kojto | 99:dbbf35b96557 | 634 | * @retval none |
| Kojto | 99:dbbf35b96557 | 635 | */ |
| Kojto | 99:dbbf35b96557 | 636 | #define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FSMC_PCR2_PBKEN): \ |
| Kojto | 99:dbbf35b96557 | 637 | ((__INSTANCE__)->PCR3 |= FSMC_PCR3_PBKEN)) |
| Kojto | 99:dbbf35b96557 | 638 | |
| Kojto | 99:dbbf35b96557 | 639 | /** |
| Kojto | 99:dbbf35b96557 | 640 | * @brief Disable the NAND device access. |
| Kojto | 99:dbbf35b96557 | 641 | * @param __INSTANCE__: FSMC_NAND Instance |
| Kojto | 99:dbbf35b96557 | 642 | * @param __BANK__: FSMC_NAND Bank |
| Kojto | 99:dbbf35b96557 | 643 | * @retval none |
| Kojto | 99:dbbf35b96557 | 644 | */ |
| Kojto | 99:dbbf35b96557 | 645 | #define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FSMC_PCR2_PBKEN): \ |
| Kojto | 99:dbbf35b96557 | 646 | ((__INSTANCE__)->PCR3 &= ~FSMC_PCR3_PBKEN)) |
| Kojto | 99:dbbf35b96557 | 647 | /** |
| Kojto | 99:dbbf35b96557 | 648 | * @} |
| Kojto | 99:dbbf35b96557 | 649 | */ |
| Kojto | 99:dbbf35b96557 | 650 | |
| Kojto | 99:dbbf35b96557 | 651 | /** @defgroup FSMC_LL_PCCARD_Macros FSMC PCCARD Macros |
| Kojto | 99:dbbf35b96557 | 652 | * @brief macros to handle SRAM read/write operations |
| Kojto | 99:dbbf35b96557 | 653 | * @{ |
| Kojto | 99:dbbf35b96557 | 654 | */ |
| Kojto | 99:dbbf35b96557 | 655 | /** |
| Kojto | 99:dbbf35b96557 | 656 | * @brief Enable the PCCARD device access. |
| Kojto | 99:dbbf35b96557 | 657 | * @param __INSTANCE__: FSMC_PCCARD Instance |
| Kojto | 99:dbbf35b96557 | 658 | * @retval none |
| Kojto | 99:dbbf35b96557 | 659 | */ |
| Kojto | 99:dbbf35b96557 | 660 | #define __FSMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 |= FSMC_PCR4_PBKEN) |
| Kojto | 99:dbbf35b96557 | 661 | |
| Kojto | 99:dbbf35b96557 | 662 | /** |
| Kojto | 99:dbbf35b96557 | 663 | * @brief Disable the PCCARD device access. |
| Kojto | 99:dbbf35b96557 | 664 | * @param __INSTANCE__: FSMC_PCCARD Instance |
| Kojto | 99:dbbf35b96557 | 665 | * @retval none |
| Kojto | 99:dbbf35b96557 | 666 | */ |
| Kojto | 99:dbbf35b96557 | 667 | #define __FSMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FSMC_PCR4_PBKEN) |
| Kojto | 99:dbbf35b96557 | 668 | /** |
| Kojto | 99:dbbf35b96557 | 669 | * @} |
| Kojto | 99:dbbf35b96557 | 670 | */ |
| Kojto | 99:dbbf35b96557 | 671 | |
| Kojto | 99:dbbf35b96557 | 672 | /** @defgroup FSMC_LL_Flag_Interrupt_Macros FSMC Flag&Interrupt Macros |
| Kojto | 99:dbbf35b96557 | 673 | * @brief macros to handle FSMC flags and interrupts |
| Kojto | 99:dbbf35b96557 | 674 | * @{ |
| Kojto | 99:dbbf35b96557 | 675 | */ |
| Kojto | 99:dbbf35b96557 | 676 | /** |
| Kojto | 99:dbbf35b96557 | 677 | * @brief Enable the NAND device interrupt. |
| Kojto | 99:dbbf35b96557 | 678 | * @param __INSTANCE__: FSMC_NAND Instance |
| Kojto | 99:dbbf35b96557 | 679 | * @param __BANK__: FSMC_NAND Bank |
| Kojto | 99:dbbf35b96557 | 680 | * @param __INTERRUPT__: FSMC_NAND interrupt |
| Kojto | 99:dbbf35b96557 | 681 | * This parameter can be any combination of the following values: |
| Kojto | 99:dbbf35b96557 | 682 | * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. |
| Kojto | 99:dbbf35b96557 | 683 | * @arg FSMC_IT_LEVEL: Interrupt level. |
| Kojto | 99:dbbf35b96557 | 684 | * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge. |
| Kojto | 99:dbbf35b96557 | 685 | * @retval None |
| Kojto | 99:dbbf35b96557 | 686 | */ |
| Kojto | 99:dbbf35b96557 | 687 | #define __FSMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 |= (__INTERRUPT__)): \ |
| Kojto | 99:dbbf35b96557 | 688 | ((__INSTANCE__)->SR3 |= (__INTERRUPT__))) |
| Kojto | 99:dbbf35b96557 | 689 | |
| Kojto | 99:dbbf35b96557 | 690 | /** |
| Kojto | 99:dbbf35b96557 | 691 | * @brief Disable the NAND device interrupt. |
| Kojto | 99:dbbf35b96557 | 692 | * @param __INSTANCE__: FSMC_NAND Instance |
| Kojto | 99:dbbf35b96557 | 693 | * @param __BANK__: FSMC_NAND Bank |
| Kojto | 99:dbbf35b96557 | 694 | * @param __INTERRUPT__: FSMC_NAND interrupt |
| Kojto | 99:dbbf35b96557 | 695 | * This parameter can be any combination of the following values: |
| Kojto | 99:dbbf35b96557 | 696 | * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. |
| Kojto | 99:dbbf35b96557 | 697 | * @arg FSMC_IT_LEVEL: Interrupt level. |
| Kojto | 99:dbbf35b96557 | 698 | * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge. |
| Kojto | 99:dbbf35b96557 | 699 | * @retval None |
| Kojto | 99:dbbf35b96557 | 700 | */ |
| Kojto | 99:dbbf35b96557 | 701 | #define __FSMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \ |
| Kojto | 99:dbbf35b96557 | 702 | ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__))) |
| Kojto | 99:dbbf35b96557 | 703 | |
| Kojto | 99:dbbf35b96557 | 704 | /** |
| Kojto | 99:dbbf35b96557 | 705 | * @brief Get flag status of the NAND device. |
| Kojto | 99:dbbf35b96557 | 706 | * @param __INSTANCE__: FSMC_NAND Instance |
| Kojto | 99:dbbf35b96557 | 707 | * @param __BANK__ : FSMC_NAND Bank |
| Kojto | 99:dbbf35b96557 | 708 | * @param __FLAG__ : FSMC_NAND flag |
| Kojto | 99:dbbf35b96557 | 709 | * This parameter can be any combination of the following values: |
| Kojto | 99:dbbf35b96557 | 710 | * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. |
| Kojto | 99:dbbf35b96557 | 711 | * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. |
| Kojto | 99:dbbf35b96557 | 712 | * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. |
| Kojto | 99:dbbf35b96557 | 713 | * @arg FSMC_FLAG_FEMPT: FIFO empty flag. |
| Kojto | 99:dbbf35b96557 | 714 | * @retval The state of FLAG (SET or RESET). |
| Kojto | 99:dbbf35b96557 | 715 | */ |
| Kojto | 99:dbbf35b96557 | 716 | #define __FSMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \ |
| Kojto | 99:dbbf35b96557 | 717 | (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__))) |
| Kojto | 99:dbbf35b96557 | 718 | /** |
| Kojto | 99:dbbf35b96557 | 719 | * @brief Clear flag status of the NAND device. |
| Kojto | 99:dbbf35b96557 | 720 | * @param __INSTANCE__: FSMC_NAND Instance |
| Kojto | 99:dbbf35b96557 | 721 | * @param __BANK__: FSMC_NAND Bank |
| Kojto | 99:dbbf35b96557 | 722 | * @param __FLAG__: FSMC_NAND flag |
| Kojto | 99:dbbf35b96557 | 723 | * This parameter can be any combination of the following values: |
| Kojto | 99:dbbf35b96557 | 724 | * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. |
| Kojto | 99:dbbf35b96557 | 725 | * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. |
| Kojto | 99:dbbf35b96557 | 726 | * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. |
| Kojto | 99:dbbf35b96557 | 727 | * @arg FSMC_FLAG_FEMPT: FIFO empty flag. |
| Kojto | 99:dbbf35b96557 | 728 | * @retval None |
| Kojto | 99:dbbf35b96557 | 729 | */ |
| Kojto | 99:dbbf35b96557 | 730 | #define __FSMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \ |
| Kojto | 99:dbbf35b96557 | 731 | ((__INSTANCE__)->SR3 &= ~(__FLAG__))) |
| Kojto | 99:dbbf35b96557 | 732 | /** |
| Kojto | 99:dbbf35b96557 | 733 | * @brief Enable the PCCARD device interrupt. |
| Kojto | 99:dbbf35b96557 | 734 | * @param __INSTANCE__: FSMC_PCCARD Instance |
| Kojto | 99:dbbf35b96557 | 735 | * @param __INTERRUPT__: FSMC_PCCARD interrupt |
| Kojto | 99:dbbf35b96557 | 736 | * This parameter can be any combination of the following values: |
| Kojto | 99:dbbf35b96557 | 737 | * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. |
| Kojto | 99:dbbf35b96557 | 738 | * @arg FSMC_IT_LEVEL: Interrupt level. |
| Kojto | 99:dbbf35b96557 | 739 | * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge. |
| Kojto | 99:dbbf35b96557 | 740 | * @retval None |
| Kojto | 99:dbbf35b96557 | 741 | */ |
| Kojto | 99:dbbf35b96557 | 742 | #define __FSMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 |= (__INTERRUPT__)) |
| Kojto | 99:dbbf35b96557 | 743 | |
| Kojto | 99:dbbf35b96557 | 744 | /** |
| Kojto | 99:dbbf35b96557 | 745 | * @brief Disable the PCCARD device interrupt. |
| Kojto | 99:dbbf35b96557 | 746 | * @param __INSTANCE__: FSMC_PCCARD Instance |
| Kojto | 99:dbbf35b96557 | 747 | * @param __INTERRUPT__: FSMC_PCCARD interrupt |
| Kojto | 99:dbbf35b96557 | 748 | * This parameter can be any combination of the following values: |
| Kojto | 99:dbbf35b96557 | 749 | * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. |
| Kojto | 99:dbbf35b96557 | 750 | * @arg FSMC_IT_LEVEL: Interrupt level. |
| Kojto | 99:dbbf35b96557 | 751 | * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge. |
| Kojto | 99:dbbf35b96557 | 752 | * @retval None |
| Kojto | 99:dbbf35b96557 | 753 | */ |
| Kojto | 99:dbbf35b96557 | 754 | #define __FSMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__)) |
| Kojto | 99:dbbf35b96557 | 755 | |
| Kojto | 99:dbbf35b96557 | 756 | /** |
| Kojto | 99:dbbf35b96557 | 757 | * @brief Get flag status of the PCCARD device. |
| Kojto | 99:dbbf35b96557 | 758 | * @param __INSTANCE__: FSMC_PCCARD Instance |
| Kojto | 99:dbbf35b96557 | 759 | * @param __FLAG__: FSMC_PCCARD flag |
| Kojto | 99:dbbf35b96557 | 760 | * This parameter can be any combination of the following values: |
| Kojto | 99:dbbf35b96557 | 761 | * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. |
| Kojto | 99:dbbf35b96557 | 762 | * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. |
| Kojto | 99:dbbf35b96557 | 763 | * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. |
| Kojto | 99:dbbf35b96557 | 764 | * @arg FSMC_FLAG_FEMPT: FIFO empty flag. |
| Kojto | 99:dbbf35b96557 | 765 | * @retval The state of FLAG (SET or RESET). |
| Kojto | 99:dbbf35b96557 | 766 | */ |
| Kojto | 99:dbbf35b96557 | 767 | #define __FSMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__)) |
| Kojto | 99:dbbf35b96557 | 768 | |
| Kojto | 99:dbbf35b96557 | 769 | /** |
| Kojto | 99:dbbf35b96557 | 770 | * @brief Clear flag status of the PCCARD device. |
| Kojto | 99:dbbf35b96557 | 771 | * @param __INSTANCE__: FSMC_PCCARD Instance |
| Kojto | 99:dbbf35b96557 | 772 | * @param __FLAG__: FSMC_PCCARD flag |
| Kojto | 99:dbbf35b96557 | 773 | * This parameter can be any combination of the following values: |
| Kojto | 99:dbbf35b96557 | 774 | * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. |
| Kojto | 99:dbbf35b96557 | 775 | * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. |
| Kojto | 99:dbbf35b96557 | 776 | * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. |
| Kojto | 99:dbbf35b96557 | 777 | * @arg FSMC_FLAG_FEMPT: FIFO empty flag. |
| Kojto | 99:dbbf35b96557 | 778 | * @retval None |
| Kojto | 99:dbbf35b96557 | 779 | */ |
| Kojto | 99:dbbf35b96557 | 780 | #define __FSMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__)) |
| Kojto | 99:dbbf35b96557 | 781 | /** |
| Kojto | 99:dbbf35b96557 | 782 | * @} |
| Kojto | 99:dbbf35b96557 | 783 | */ |
| Kojto | 110:165afa46840b | 784 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ |
| Kojto | 99:dbbf35b96557 | 785 | |
| Kojto | 99:dbbf35b96557 | 786 | /** @defgroup FSMC_LL_Assert_Macros FSMC Assert Macros |
| Kojto | 99:dbbf35b96557 | 787 | * @{ |
| Kojto | 99:dbbf35b96557 | 788 | */ |
| Kojto | 99:dbbf35b96557 | 789 | #define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) || \ |
| Kojto | 99:dbbf35b96557 | 790 | ((__BANK__) == FSMC_NORSRAM_BANK2) || \ |
| Kojto | 99:dbbf35b96557 | 791 | ((__BANK__) == FSMC_NORSRAM_BANK3) || \ |
| Kojto | 99:dbbf35b96557 | 792 | ((__BANK__) == FSMC_NORSRAM_BANK4)) |
| Kojto | 99:dbbf35b96557 | 793 | |
| Kojto | 99:dbbf35b96557 | 794 | #define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \ |
| Kojto | 99:dbbf35b96557 | 795 | ((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE)) |
| Kojto | 99:dbbf35b96557 | 796 | |
| Kojto | 99:dbbf35b96557 | 797 | #define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) || \ |
| Kojto | 99:dbbf35b96557 | 798 | ((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \ |
| Kojto | 99:dbbf35b96557 | 799 | ((__MEMORY__) == FSMC_MEMORY_TYPE_NOR)) |
| Kojto | 99:dbbf35b96557 | 800 | |
| Kojto | 99:dbbf35b96557 | 801 | #define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) || \ |
| Kojto | 99:dbbf35b96557 | 802 | ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \ |
| Kojto | 99:dbbf35b96557 | 803 | ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32)) |
| Kojto | 99:dbbf35b96557 | 804 | |
| Kojto | 99:dbbf35b96557 | 805 | #define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \ |
| Kojto | 99:dbbf35b96557 | 806 | ((__MODE__) == FSMC_ACCESS_MODE_B) || \ |
| Kojto | 99:dbbf35b96557 | 807 | ((__MODE__) == FSMC_ACCESS_MODE_C) || \ |
| Kojto | 99:dbbf35b96557 | 808 | ((__MODE__) == FSMC_ACCESS_MODE_D)) |
| Kojto | 99:dbbf35b96557 | 809 | |
| Kojto | 99:dbbf35b96557 | 810 | #define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_NAND_BANK2) || \ |
| Kojto | 99:dbbf35b96557 | 811 | ((BANK) == FSMC_NAND_BANK3)) |
| Kojto | 99:dbbf35b96557 | 812 | |
| Kojto | 99:dbbf35b96557 | 813 | #define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \ |
| Kojto | 99:dbbf35b96557 | 814 | ((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE)) |
| Kojto | 99:dbbf35b96557 | 815 | |
| Kojto | 99:dbbf35b96557 | 816 | #define IS_FSMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) || \ |
| Kojto | 99:dbbf35b96557 | 817 | ((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16)) |
| Kojto | 99:dbbf35b96557 | 818 | |
| Kojto | 99:dbbf35b96557 | 819 | #define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_NAND_ECC_DISABLE) || \ |
| Kojto | 99:dbbf35b96557 | 820 | ((STATE) == FSMC_NAND_ECC_ENABLE)) |
| Kojto | 99:dbbf35b96557 | 821 | |
| Kojto | 99:dbbf35b96557 | 822 | #define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE) || \ |
| Kojto | 99:dbbf35b96557 | 823 | ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE) || \ |
| Kojto | 99:dbbf35b96557 | 824 | ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \ |
| Kojto | 99:dbbf35b96557 | 825 | ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \ |
| Kojto | 99:dbbf35b96557 | 826 | ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \ |
| Kojto | 99:dbbf35b96557 | 827 | ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE)) |
| Kojto | 99:dbbf35b96557 | 828 | |
| Kojto | 99:dbbf35b96557 | 829 | #define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 255) |
| Kojto | 99:dbbf35b96557 | 830 | |
| Kojto | 99:dbbf35b96557 | 831 | #define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 255) |
| Kojto | 99:dbbf35b96557 | 832 | |
| Kojto | 99:dbbf35b96557 | 833 | #define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 255) |
| Kojto | 99:dbbf35b96557 | 834 | |
| Kojto | 99:dbbf35b96557 | 835 | #define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 255) |
| Kojto | 99:dbbf35b96557 | 836 | |
| Kojto | 99:dbbf35b96557 | 837 | #define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 255) |
| Kojto | 99:dbbf35b96557 | 838 | |
| Kojto | 99:dbbf35b96557 | 839 | #define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 255) |
| Kojto | 99:dbbf35b96557 | 840 | |
| Kojto | 99:dbbf35b96557 | 841 | #define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE) |
| Kojto | 99:dbbf35b96557 | 842 | |
| Kojto | 99:dbbf35b96557 | 843 | #define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE) |
| Kojto | 99:dbbf35b96557 | 844 | |
| Kojto | 99:dbbf35b96557 | 845 | #define IS_FSMC_NAND_DEVICE(INSTANCE) ((INSTANCE) == FSMC_NAND_DEVICE) |
| Kojto | 99:dbbf35b96557 | 846 | |
| Kojto | 99:dbbf35b96557 | 847 | #define IS_FSMC_PCCARD_DEVICE(INSTANCE) ((INSTANCE) == FSMC_PCCARD_DEVICE) |
| Kojto | 99:dbbf35b96557 | 848 | |
| Kojto | 99:dbbf35b96557 | 849 | #define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \ |
| Kojto | 99:dbbf35b96557 | 850 | ((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE)) |
| Kojto | 99:dbbf35b96557 | 851 | |
| Kojto | 99:dbbf35b96557 | 852 | #define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \ |
| Kojto | 99:dbbf35b96557 | 853 | ((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH)) |
| Kojto | 99:dbbf35b96557 | 854 | |
| Kojto | 99:dbbf35b96557 | 855 | #define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \ |
| Kojto | 99:dbbf35b96557 | 856 | ((__MODE__) == FSMC_WRAP_MODE_ENABLE)) |
| Kojto | 99:dbbf35b96557 | 857 | |
| Kojto | 99:dbbf35b96557 | 858 | #define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \ |
| Kojto | 99:dbbf35b96557 | 859 | ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS)) |
| Kojto | 99:dbbf35b96557 | 860 | |
| Kojto | 99:dbbf35b96557 | 861 | #define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \ |
| Kojto | 99:dbbf35b96557 | 862 | ((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE)) |
| Kojto | 99:dbbf35b96557 | 863 | |
| Kojto | 99:dbbf35b96557 | 864 | #define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \ |
| Kojto | 99:dbbf35b96557 | 865 | ((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE)) |
| Kojto | 99:dbbf35b96557 | 866 | |
| Kojto | 99:dbbf35b96557 | 867 | #define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \ |
| Kojto | 99:dbbf35b96557 | 868 | ((__MODE__) == FSMC_EXTENDED_MODE_ENABLE)) |
| Kojto | 99:dbbf35b96557 | 869 | |
| Kojto | 99:dbbf35b96557 | 870 | #define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \ |
| Kojto | 99:dbbf35b96557 | 871 | ((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE)) |
| Kojto | 99:dbbf35b96557 | 872 | |
| Kojto | 99:dbbf35b96557 | 873 | #define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17)) |
| Kojto | 99:dbbf35b96557 | 874 | |
| Kojto | 99:dbbf35b96557 | 875 | #define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \ |
| Kojto | 99:dbbf35b96557 | 876 | ((__BURST__) == FSMC_WRITE_BURST_ENABLE)) |
| Kojto | 99:dbbf35b96557 | 877 | |
| Kojto | 99:dbbf35b96557 | 878 | #define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15) |
| Kojto | 99:dbbf35b96557 | 879 | |
| Kojto | 99:dbbf35b96557 | 880 | #define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15)) |
| Kojto | 99:dbbf35b96557 | 881 | |
| Kojto | 99:dbbf35b96557 | 882 | #define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255)) |
| Kojto | 99:dbbf35b96557 | 883 | |
| Kojto | 99:dbbf35b96557 | 884 | #define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15) |
| Kojto | 99:dbbf35b96557 | 885 | |
| Kojto | 99:dbbf35b96557 | 886 | #define IS_FSMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \ |
| Kojto | 99:dbbf35b96557 | 887 | ((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC)) |
| Kojto | 99:dbbf35b96557 | 888 | |
| Kojto | 99:dbbf35b96557 | 889 | #define IS_FSMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16)) |
| Kojto | 99:dbbf35b96557 | 890 | |
| Kojto | 99:dbbf35b96557 | 891 | /** |
| Kojto | 99:dbbf35b96557 | 892 | * @} |
| Kojto | 99:dbbf35b96557 | 893 | */ |
| Kojto | 99:dbbf35b96557 | 894 | /** |
| Kojto | 99:dbbf35b96557 | 895 | * @} |
| Kojto | 99:dbbf35b96557 | 896 | */ |
| Kojto | 99:dbbf35b96557 | 897 | |
| Kojto | 99:dbbf35b96557 | 898 | /* Private functions ---------------------------------------------------------*/ |
| Kojto | 99:dbbf35b96557 | 899 | /** @defgroup FSMC_LL_Private_Functions FSMC LL Private Functions |
| Kojto | 99:dbbf35b96557 | 900 | * @{ |
| Kojto | 99:dbbf35b96557 | 901 | */ |
| Kojto | 99:dbbf35b96557 | 902 | |
| Kojto | 99:dbbf35b96557 | 903 | /** @defgroup FSMC_LL_NORSRAM NOR SRAM |
| Kojto | 99:dbbf35b96557 | 904 | * @{ |
| Kojto | 99:dbbf35b96557 | 905 | */ |
| Kojto | 99:dbbf35b96557 | 906 | |
| Kojto | 99:dbbf35b96557 | 907 | /** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions |
| Kojto | 99:dbbf35b96557 | 908 | * @{ |
| Kojto | 99:dbbf35b96557 | 909 | */ |
| Kojto | 99:dbbf35b96557 | 910 | HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef *Init); |
| Kojto | 99:dbbf35b96557 | 911 | HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); |
| Kojto | 99:dbbf35b96557 | 912 | HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode); |
| Kojto | 99:dbbf35b96557 | 913 | HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); |
| Kojto | 99:dbbf35b96557 | 914 | /** |
| Kojto | 99:dbbf35b96557 | 915 | * @} |
| Kojto | 99:dbbf35b96557 | 916 | */ |
| Kojto | 99:dbbf35b96557 | 917 | |
| Kojto | 99:dbbf35b96557 | 918 | /** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions |
| Kojto | 99:dbbf35b96557 | 919 | * @{ |
| Kojto | 99:dbbf35b96557 | 920 | */ |
| Kojto | 99:dbbf35b96557 | 921 | HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank); |
| Kojto | 99:dbbf35b96557 | 922 | HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank); |
| Kojto | 99:dbbf35b96557 | 923 | /** |
| Kojto | 99:dbbf35b96557 | 924 | * @} |
| Kojto | 99:dbbf35b96557 | 925 | */ |
| Kojto | 99:dbbf35b96557 | 926 | /** |
| Kojto | 99:dbbf35b96557 | 927 | * @} |
| Kojto | 99:dbbf35b96557 | 928 | */ |
| Kojto | 99:dbbf35b96557 | 929 | |
| Kojto | 110:165afa46840b | 930 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) |
| Kojto | 99:dbbf35b96557 | 931 | /** @defgroup FSMC_LL_NAND NAND |
| Kojto | 99:dbbf35b96557 | 932 | * @{ |
| Kojto | 99:dbbf35b96557 | 933 | */ |
| Kojto | 99:dbbf35b96557 | 934 | /** @defgroup FSMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions |
| Kojto | 99:dbbf35b96557 | 935 | * @{ |
| Kojto | 99:dbbf35b96557 | 936 | */ |
| Kojto | 99:dbbf35b96557 | 937 | HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init); |
| Kojto | 99:dbbf35b96557 | 938 | HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); |
| Kojto | 99:dbbf35b96557 | 939 | HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); |
| Kojto | 99:dbbf35b96557 | 940 | HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank); |
| Kojto | 99:dbbf35b96557 | 941 | /** |
| Kojto | 99:dbbf35b96557 | 942 | * @} |
| Kojto | 99:dbbf35b96557 | 943 | */ |
| Kojto | 99:dbbf35b96557 | 944 | |
| Kojto | 99:dbbf35b96557 | 945 | /** @defgroup FSMC_LL_NAND_Private_Functions_Group2 NAND Control functions |
| Kojto | 99:dbbf35b96557 | 946 | * @{ |
| Kojto | 99:dbbf35b96557 | 947 | */ |
| Kojto | 99:dbbf35b96557 | 948 | HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank); |
| Kojto | 99:dbbf35b96557 | 949 | HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank); |
| Kojto | 99:dbbf35b96557 | 950 | HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout); |
| Kojto | 99:dbbf35b96557 | 951 | /** |
| Kojto | 99:dbbf35b96557 | 952 | * @} |
| Kojto | 99:dbbf35b96557 | 953 | */ |
| Kojto | 99:dbbf35b96557 | 954 | /** |
| Kojto | 99:dbbf35b96557 | 955 | * @} |
| Kojto | 99:dbbf35b96557 | 956 | */ |
| Kojto | 99:dbbf35b96557 | 957 | |
| Kojto | 99:dbbf35b96557 | 958 | /** @defgroup FSMC_LL_PCCARD PCCARD |
| Kojto | 99:dbbf35b96557 | 959 | * @{ |
| Kojto | 99:dbbf35b96557 | 960 | */ |
| Kojto | 99:dbbf35b96557 | 961 | /** @defgroup FSMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions |
| Kojto | 99:dbbf35b96557 | 962 | * @{ |
| Kojto | 99:dbbf35b96557 | 963 | */ |
| Kojto | 99:dbbf35b96557 | 964 | HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init); |
| Kojto | 99:dbbf35b96557 | 965 | HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing); |
| Kojto | 99:dbbf35b96557 | 966 | HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing); |
| Kojto | 99:dbbf35b96557 | 967 | HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing); |
| Kojto | 99:dbbf35b96557 | 968 | HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device); |
| Kojto | 99:dbbf35b96557 | 969 | /** |
| Kojto | 99:dbbf35b96557 | 970 | * @} |
| Kojto | 99:dbbf35b96557 | 971 | */ |
| Kojto | 99:dbbf35b96557 | 972 | /** |
| Kojto | 99:dbbf35b96557 | 973 | * @} |
| Kojto | 99:dbbf35b96557 | 974 | */ |
| Kojto | 110:165afa46840b | 975 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ |
| Kojto | 99:dbbf35b96557 | 976 | |
| Kojto | 99:dbbf35b96557 | 977 | /** |
| Kojto | 99:dbbf35b96557 | 978 | * @} |
| Kojto | 99:dbbf35b96557 | 979 | */ |
| Kojto | 110:165afa46840b | 980 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ |
| emilmont | 77:869cf507173a | 981 | |
| emilmont | 77:869cf507173a | 982 | /** |
| emilmont | 77:869cf507173a | 983 | * @} |
| emilmont | 77:869cf507173a | 984 | */ |
| emilmont | 77:869cf507173a | 985 | |
| emilmont | 77:869cf507173a | 986 | /** |
| emilmont | 77:869cf507173a | 987 | * @} |
| emilmont | 77:869cf507173a | 988 | */ |
| emilmont | 77:869cf507173a | 989 | |
| emilmont | 77:869cf507173a | 990 | #ifdef __cplusplus |
| emilmont | 77:869cf507173a | 991 | } |
| emilmont | 77:869cf507173a | 992 | #endif |
| emilmont | 77:869cf507173a | 993 | |
| emilmont | 77:869cf507173a | 994 | #endif /* __STM32F4xx_LL_FSMC_H */ |
| emilmont | 77:869cf507173a | 995 | |
| emilmont | 77:869cf507173a | 996 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |